1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* True if -mnan=2008, false if -mnan=legacy. */
263 static bfd_boolean mips_flag_nan2008
= FALSE
;
265 /* This is the struct we use to hold the module level set of options.
266 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp32 and
267 fp fields to -1 to indicate that they have not been initialized. */
269 static struct mips_set_options file_mips_opts
=
271 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
272 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
273 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
274 /* gp32 */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
275 /* soft_float */ FALSE
, /* single_float */ FALSE
278 /* This is similar to file_mips_opts, but for the current set of options. */
280 static struct mips_set_options mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp32 */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
289 /* The set of ASEs that were selected on the command line, either
290 explicitly via ASE options or implicitly through things like -march. */
291 static unsigned int file_ase
;
293 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
294 static unsigned int file_ase_explicit
;
296 /* These variables are filled in with the masks of registers used.
297 The object format code reads them and puts them in the appropriate
299 unsigned long mips_gprmask
;
300 unsigned long mips_cprmask
[4];
302 /* True if any MIPS16 code was produced. */
303 static int file_ase_mips16
;
305 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2 \
307 || mips_opts.isa == ISA_MIPS32R3 \
308 || mips_opts.isa == ISA_MIPS32R5 \
309 || mips_opts.isa == ISA_MIPS64 \
310 || mips_opts.isa == ISA_MIPS64R2 \
311 || mips_opts.isa == ISA_MIPS64R3 \
312 || mips_opts.isa == ISA_MIPS64R5)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static const char *mips_arch_string
;
332 /* The argument of the -mtune= flag. The architecture for which we
334 static int mips_tune
= CPU_UNKNOWN
;
335 static const char *mips_tune_string
;
337 /* True when generating 32-bit code for a 64-bit processor. */
338 static int mips_32bitmode
= 0;
340 /* True if the given ABI requires 32-bit registers. */
341 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
343 /* Likewise 64-bit registers. */
344 #define ABI_NEEDS_64BIT_REGS(ABI) \
346 || (ABI) == N64_ABI \
349 /* Return true if ISA supports 64 bit wide gp registers. */
350 #define ISA_HAS_64BIT_REGS(ISA) \
351 ((ISA) == ISA_MIPS3 \
352 || (ISA) == ISA_MIPS4 \
353 || (ISA) == ISA_MIPS5 \
354 || (ISA) == ISA_MIPS64 \
355 || (ISA) == ISA_MIPS64R2 \
356 || (ISA) == ISA_MIPS64R3 \
357 || (ISA) == ISA_MIPS64R5)
359 /* Return true if ISA supports 64 bit wide float registers. */
360 #define ISA_HAS_64BIT_FPRS(ISA) \
361 ((ISA) == ISA_MIPS3 \
362 || (ISA) == ISA_MIPS4 \
363 || (ISA) == ISA_MIPS5 \
364 || (ISA) == ISA_MIPS32R2 \
365 || (ISA) == ISA_MIPS32R3 \
366 || (ISA) == ISA_MIPS32R5 \
367 || (ISA) == ISA_MIPS64 \
368 || (ISA) == ISA_MIPS64R2 \
369 || (ISA) == ISA_MIPS64R3 \
370 || (ISA) == ISA_MIPS64R5 )
372 /* Return true if ISA supports 64-bit right rotate (dror et al.)
374 #define ISA_HAS_DROR(ISA) \
375 ((ISA) == ISA_MIPS64R2 \
376 || (ISA) == ISA_MIPS64R3 \
377 || (ISA) == ISA_MIPS64R5 \
378 || (mips_opts.micromips \
379 && ISA_HAS_64BIT_REGS (ISA)) \
382 /* Return true if ISA supports 32-bit right rotate (ror et al.)
384 #define ISA_HAS_ROR(ISA) \
385 ((ISA) == ISA_MIPS32R2 \
386 || (ISA) == ISA_MIPS32R3 \
387 || (ISA) == ISA_MIPS32R5 \
388 || (ISA) == ISA_MIPS64R2 \
389 || (ISA) == ISA_MIPS64R3 \
390 || (ISA) == ISA_MIPS64R5 \
391 || (mips_opts.ase & ASE_SMARTMIPS) \
392 || mips_opts.micromips \
395 /* Return true if ISA supports single-precision floats in odd registers. */
396 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
397 ((ISA) == ISA_MIPS32 \
398 || (ISA) == ISA_MIPS32R2 \
399 || (ISA) == ISA_MIPS32R3 \
400 || (ISA) == ISA_MIPS32R5 \
401 || (ISA) == ISA_MIPS64 \
402 || (ISA) == ISA_MIPS64R2 \
403 || (ISA) == ISA_MIPS64R3 \
404 || (ISA) == ISA_MIPS64R5)
406 /* Return true if ISA supports move to/from high part of a 64-bit
407 floating-point register. */
408 #define ISA_HAS_MXHC1(ISA) \
409 ((ISA) == ISA_MIPS32R2 \
410 || (ISA) == ISA_MIPS32R3 \
411 || (ISA) == ISA_MIPS32R5 \
412 || (ISA) == ISA_MIPS64R2 \
413 || (ISA) == ISA_MIPS64R3 \
414 || (ISA) == ISA_MIPS64R5)
416 #define HAVE_32BIT_GPRS \
417 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
419 #define HAVE_32BIT_FPRS \
420 (mips_opts.fp != 64 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
422 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
423 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
425 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
427 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
429 /* True if relocations are stored in-place. */
430 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
432 /* The ABI-derived address size. */
433 #define HAVE_64BIT_ADDRESSES \
434 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
435 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
437 /* The size of symbolic constants (i.e., expressions of the form
438 "SYMBOL" or "SYMBOL + OFFSET"). */
439 #define HAVE_32BIT_SYMBOLS \
440 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
441 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
443 /* Addresses are loaded in different ways, depending on the address size
444 in use. The n32 ABI Documentation also mandates the use of additions
445 with overflow checking, but existing implementations don't follow it. */
446 #define ADDRESS_ADD_INSN \
447 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
449 #define ADDRESS_ADDI_INSN \
450 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
452 #define ADDRESS_LOAD_INSN \
453 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
455 #define ADDRESS_STORE_INSN \
456 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
458 /* Return true if the given CPU supports the MIPS16 ASE. */
459 #define CPU_HAS_MIPS16(cpu) \
460 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
461 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
463 /* Return true if the given CPU supports the microMIPS ASE. */
464 #define CPU_HAS_MICROMIPS(cpu) 0
466 /* True if CPU has a dror instruction. */
467 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
469 /* True if CPU has a ror instruction. */
470 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
472 /* True if CPU is in the Octeon family */
473 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
475 /* True if CPU has seq/sne and seqi/snei instructions. */
476 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
478 /* True, if CPU has support for ldc1 and sdc1. */
479 #define CPU_HAS_LDC1_SDC1(CPU) \
480 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
482 /* True if mflo and mfhi can be immediately followed by instructions
483 which write to the HI and LO registers.
485 According to MIPS specifications, MIPS ISAs I, II, and III need
486 (at least) two instructions between the reads of HI/LO and
487 instructions which write them, and later ISAs do not. Contradicting
488 the MIPS specifications, some MIPS IV processor user manuals (e.g.
489 the UM for the NEC Vr5000) document needing the instructions between
490 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
491 MIPS64 and later ISAs to have the interlocks, plus any specific
492 earlier-ISA CPUs for which CPU documentation declares that the
493 instructions are really interlocked. */
494 #define hilo_interlocks \
495 (mips_opts.isa == ISA_MIPS32 \
496 || mips_opts.isa == ISA_MIPS32R2 \
497 || mips_opts.isa == ISA_MIPS32R3 \
498 || mips_opts.isa == ISA_MIPS32R5 \
499 || mips_opts.isa == ISA_MIPS64 \
500 || mips_opts.isa == ISA_MIPS64R2 \
501 || mips_opts.isa == ISA_MIPS64R3 \
502 || mips_opts.isa == ISA_MIPS64R5 \
503 || mips_opts.arch == CPU_R4010 \
504 || mips_opts.arch == CPU_R5900 \
505 || mips_opts.arch == CPU_R10000 \
506 || mips_opts.arch == CPU_R12000 \
507 || mips_opts.arch == CPU_R14000 \
508 || mips_opts.arch == CPU_R16000 \
509 || mips_opts.arch == CPU_RM7000 \
510 || mips_opts.arch == CPU_VR5500 \
511 || mips_opts.micromips \
514 /* Whether the processor uses hardware interlocks to protect reads
515 from the GPRs after they are loaded from memory, and thus does not
516 require nops to be inserted. This applies to instructions marked
517 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
518 level I and microMIPS mode instructions are always interlocked. */
519 #define gpr_interlocks \
520 (mips_opts.isa != ISA_MIPS1 \
521 || mips_opts.arch == CPU_R3900 \
522 || mips_opts.arch == CPU_R5900 \
523 || mips_opts.micromips \
526 /* Whether the processor uses hardware interlocks to avoid delays
527 required by coprocessor instructions, and thus does not require
528 nops to be inserted. This applies to instructions marked
529 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
530 between instructions marked INSN_WRITE_COND_CODE and ones marked
531 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
532 levels I, II, and III and microMIPS mode instructions are always
534 /* Itbl support may require additional care here. */
535 #define cop_interlocks \
536 ((mips_opts.isa != ISA_MIPS1 \
537 && mips_opts.isa != ISA_MIPS2 \
538 && mips_opts.isa != ISA_MIPS3) \
539 || mips_opts.arch == CPU_R4300 \
540 || mips_opts.micromips \
543 /* Whether the processor uses hardware interlocks to protect reads
544 from coprocessor registers after they are loaded from memory, and
545 thus does not require nops to be inserted. This applies to
546 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
547 requires at MIPS ISA level I and microMIPS mode instructions are
548 always interlocked. */
549 #define cop_mem_interlocks \
550 (mips_opts.isa != ISA_MIPS1 \
551 || mips_opts.micromips \
554 /* Is this a mfhi or mflo instruction? */
555 #define MF_HILO_INSN(PINFO) \
556 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
558 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
559 has been selected. This implies, in particular, that addresses of text
560 labels have their LSB set. */
561 #define HAVE_CODE_COMPRESSION \
562 ((mips_opts.mips16 | mips_opts.micromips) != 0)
564 /* The minimum and maximum signed values that can be stored in a GPR. */
565 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
566 #define GPR_SMIN (-GPR_SMAX - 1)
568 /* MIPS PIC level. */
570 enum mips_pic_level mips_pic
;
572 /* 1 if we should generate 32 bit offsets from the $gp register in
573 SVR4_PIC mode. Currently has no meaning in other modes. */
574 static int mips_big_got
= 0;
576 /* 1 if trap instructions should used for overflow rather than break
578 static int mips_trap
= 0;
580 /* 1 if double width floating point constants should not be constructed
581 by assembling two single width halves into two single width floating
582 point registers which just happen to alias the double width destination
583 register. On some architectures this aliasing can be disabled by a bit
584 in the status register, and the setting of this bit cannot be determined
585 automatically at assemble time. */
586 static int mips_disable_float_construction
;
588 /* Non-zero if any .set noreorder directives were used. */
590 static int mips_any_noreorder
;
592 /* Non-zero if nops should be inserted when the register referenced in
593 an mfhi/mflo instruction is read in the next two instructions. */
594 static int mips_7000_hilo_fix
;
596 /* The size of objects in the small data section. */
597 static unsigned int g_switch_value
= 8;
598 /* Whether the -G option was used. */
599 static int g_switch_seen
= 0;
604 /* If we can determine in advance that GP optimization won't be
605 possible, we can skip the relaxation stuff that tries to produce
606 GP-relative references. This makes delay slot optimization work
609 This function can only provide a guess, but it seems to work for
610 gcc output. It needs to guess right for gcc, otherwise gcc
611 will put what it thinks is a GP-relative instruction in a branch
614 I don't know if a fix is needed for the SVR4_PIC mode. I've only
615 fixed it for the non-PIC mode. KR 95/04/07 */
616 static int nopic_need_relax (symbolS
*, int);
618 /* handle of the OPCODE hash table */
619 static struct hash_control
*op_hash
= NULL
;
621 /* The opcode hash table we use for the mips16. */
622 static struct hash_control
*mips16_op_hash
= NULL
;
624 /* The opcode hash table we use for the microMIPS ASE. */
625 static struct hash_control
*micromips_op_hash
= NULL
;
627 /* This array holds the chars that always start a comment. If the
628 pre-processor is disabled, these aren't very useful */
629 const char comment_chars
[] = "#";
631 /* This array holds the chars that only start a comment at the beginning of
632 a line. If the line seems to have the form '# 123 filename'
633 .line and .file directives will appear in the pre-processed output */
634 /* Note that input_file.c hand checks for '#' at the beginning of the
635 first line of the input file. This is because the compiler outputs
636 #NO_APP at the beginning of its output. */
637 /* Also note that C style comments are always supported. */
638 const char line_comment_chars
[] = "#";
640 /* This array holds machine specific line separator characters. */
641 const char line_separator_chars
[] = ";";
643 /* Chars that can be used to separate mant from exp in floating point nums */
644 const char EXP_CHARS
[] = "eE";
646 /* Chars that mean this number is a floating point constant */
649 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
651 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
652 changed in read.c . Ideally it shouldn't have to know about it at all,
653 but nothing is ideal around here.
656 /* Types of printf format used for instruction-related error messages.
657 "I" means int ("%d") and "S" means string ("%s"). */
658 enum mips_insn_error_format
{
664 /* Information about an error that was found while assembling the current
666 struct mips_insn_error
{
667 /* We sometimes need to match an instruction against more than one
668 opcode table entry. Errors found during this matching are reported
669 against a particular syntactic argument rather than against the
670 instruction as a whole. We grade these messages so that errors
671 against argument N have a greater priority than an error against
672 any argument < N, since the former implies that arguments up to N
673 were acceptable and that the opcode entry was therefore a closer match.
674 If several matches report an error against the same argument,
675 we only use that error if it is the same in all cases.
677 min_argnum is the minimum argument number for which an error message
678 should be accepted. It is 0 if MSG is against the instruction as
682 /* The printf()-style message, including its format and arguments. */
683 enum mips_insn_error_format format
;
691 /* The error that should be reported for the current instruction. */
692 static struct mips_insn_error insn_error
;
694 static int auto_align
= 1;
696 /* When outputting SVR4 PIC code, the assembler needs to know the
697 offset in the stack frame from which to restore the $gp register.
698 This is set by the .cprestore pseudo-op, and saved in this
700 static offsetT mips_cprestore_offset
= -1;
702 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
703 more optimizations, it can use a register value instead of a memory-saved
704 offset and even an other register than $gp as global pointer. */
705 static offsetT mips_cpreturn_offset
= -1;
706 static int mips_cpreturn_register
= -1;
707 static int mips_gp_register
= GP
;
708 static int mips_gprel_offset
= 0;
710 /* Whether mips_cprestore_offset has been set in the current function
711 (or whether it has already been warned about, if not). */
712 static int mips_cprestore_valid
= 0;
714 /* This is the register which holds the stack frame, as set by the
715 .frame pseudo-op. This is needed to implement .cprestore. */
716 static int mips_frame_reg
= SP
;
718 /* Whether mips_frame_reg has been set in the current function
719 (or whether it has already been warned about, if not). */
720 static int mips_frame_reg_valid
= 0;
722 /* To output NOP instructions correctly, we need to keep information
723 about the previous two instructions. */
725 /* Whether we are optimizing. The default value of 2 means to remove
726 unneeded NOPs and swap branch instructions when possible. A value
727 of 1 means to not swap branches. A value of 0 means to always
729 static int mips_optimize
= 2;
731 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
732 equivalent to seeing no -g option at all. */
733 static int mips_debug
= 0;
735 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
736 #define MAX_VR4130_NOPS 4
738 /* The maximum number of NOPs needed to fill delay slots. */
739 #define MAX_DELAY_NOPS 2
741 /* The maximum number of NOPs needed for any purpose. */
744 /* A list of previous instructions, with index 0 being the most recent.
745 We need to look back MAX_NOPS instructions when filling delay slots
746 or working around processor errata. We need to look back one
747 instruction further if we're thinking about using history[0] to
748 fill a branch delay slot. */
749 static struct mips_cl_insn history
[1 + MAX_NOPS
];
751 /* Arrays of operands for each instruction. */
752 #define MAX_OPERANDS 6
753 struct mips_operand_array
{
754 const struct mips_operand
*operand
[MAX_OPERANDS
];
756 static struct mips_operand_array
*mips_operands
;
757 static struct mips_operand_array
*mips16_operands
;
758 static struct mips_operand_array
*micromips_operands
;
760 /* Nop instructions used by emit_nop. */
761 static struct mips_cl_insn nop_insn
;
762 static struct mips_cl_insn mips16_nop_insn
;
763 static struct mips_cl_insn micromips_nop16_insn
;
764 static struct mips_cl_insn micromips_nop32_insn
;
766 /* The appropriate nop for the current mode. */
767 #define NOP_INSN (mips_opts.mips16 \
769 : (mips_opts.micromips \
770 ? (mips_opts.insn32 \
771 ? µmips_nop32_insn \
772 : µmips_nop16_insn) \
775 /* The size of NOP_INSN in bytes. */
776 #define NOP_INSN_SIZE ((mips_opts.mips16 \
777 || (mips_opts.micromips && !mips_opts.insn32)) \
780 /* If this is set, it points to a frag holding nop instructions which
781 were inserted before the start of a noreorder section. If those
782 nops turn out to be unnecessary, the size of the frag can be
784 static fragS
*prev_nop_frag
;
786 /* The number of nop instructions we created in prev_nop_frag. */
787 static int prev_nop_frag_holds
;
789 /* The number of nop instructions that we know we need in
791 static int prev_nop_frag_required
;
793 /* The number of instructions we've seen since prev_nop_frag. */
794 static int prev_nop_frag_since
;
796 /* Relocations against symbols are sometimes done in two parts, with a HI
797 relocation and a LO relocation. Each relocation has only 16 bits of
798 space to store an addend. This means that in order for the linker to
799 handle carries correctly, it must be able to locate both the HI and
800 the LO relocation. This means that the relocations must appear in
801 order in the relocation table.
803 In order to implement this, we keep track of each unmatched HI
804 relocation. We then sort them so that they immediately precede the
805 corresponding LO relocation. */
810 struct mips_hi_fixup
*next
;
813 /* The section this fixup is in. */
817 /* The list of unmatched HI relocs. */
819 static struct mips_hi_fixup
*mips_hi_fixup_list
;
821 /* The frag containing the last explicit relocation operator.
822 Null if explicit relocations have not been used. */
824 static fragS
*prev_reloc_op_frag
;
826 /* Map mips16 register numbers to normal MIPS register numbers. */
828 static const unsigned int mips16_to_32_reg_map
[] =
830 16, 17, 2, 3, 4, 5, 6, 7
833 /* Map microMIPS register numbers to normal MIPS register numbers. */
835 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
837 /* The microMIPS registers with type h. */
838 static const unsigned int micromips_to_32_reg_h_map1
[] =
840 5, 5, 6, 4, 4, 4, 4, 4
842 static const unsigned int micromips_to_32_reg_h_map2
[] =
844 6, 7, 7, 21, 22, 5, 6, 7
847 /* The microMIPS registers with type m. */
848 static const unsigned int micromips_to_32_reg_m_map
[] =
850 0, 17, 2, 3, 16, 18, 19, 20
853 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
855 /* Classifies the kind of instructions we're interested in when
856 implementing -mfix-vr4120. */
857 enum fix_vr4120_class
865 NUM_FIX_VR4120_CLASSES
868 /* ...likewise -mfix-loongson2f-jump. */
869 static bfd_boolean mips_fix_loongson2f_jump
;
871 /* ...likewise -mfix-loongson2f-nop. */
872 static bfd_boolean mips_fix_loongson2f_nop
;
874 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
875 static bfd_boolean mips_fix_loongson2f
;
877 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
878 there must be at least one other instruction between an instruction
879 of type X and an instruction of type Y. */
880 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
882 /* True if -mfix-vr4120 is in force. */
883 static int mips_fix_vr4120
;
885 /* ...likewise -mfix-vr4130. */
886 static int mips_fix_vr4130
;
888 /* ...likewise -mfix-24k. */
889 static int mips_fix_24k
;
891 /* ...likewise -mfix-rm7000 */
892 static int mips_fix_rm7000
;
894 /* ...likewise -mfix-cn63xxp1 */
895 static bfd_boolean mips_fix_cn63xxp1
;
897 /* We don't relax branches by default, since this causes us to expand
898 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
899 fail to compute the offset before expanding the macro to the most
900 efficient expansion. */
902 static int mips_relax_branch
;
904 /* The expansion of many macros depends on the type of symbol that
905 they refer to. For example, when generating position-dependent code,
906 a macro that refers to a symbol may have two different expansions,
907 one which uses GP-relative addresses and one which uses absolute
908 addresses. When generating SVR4-style PIC, a macro may have
909 different expansions for local and global symbols.
911 We handle these situations by generating both sequences and putting
912 them in variant frags. In position-dependent code, the first sequence
913 will be the GP-relative one and the second sequence will be the
914 absolute one. In SVR4 PIC, the first sequence will be for global
915 symbols and the second will be for local symbols.
917 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
918 SECOND are the lengths of the two sequences in bytes. These fields
919 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
920 the subtype has the following flags:
923 Set if it has been decided that we should use the second
924 sequence instead of the first.
927 Set in the first variant frag if the macro's second implementation
928 is longer than its first. This refers to the macro as a whole,
929 not an individual relaxation.
932 Set in the first variant frag if the macro appeared in a .set nomacro
933 block and if one alternative requires a warning but the other does not.
936 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
939 RELAX_DELAY_SLOT_16BIT
940 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
943 RELAX_DELAY_SLOT_SIZE_FIRST
944 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
945 the macro is of the wrong size for the branch delay slot.
947 RELAX_DELAY_SLOT_SIZE_SECOND
948 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
949 the macro is of the wrong size for the branch delay slot.
951 The frag's "opcode" points to the first fixup for relaxable code.
953 Relaxable macros are generated using a sequence such as:
955 relax_start (SYMBOL);
956 ... generate first expansion ...
958 ... generate second expansion ...
961 The code and fixups for the unwanted alternative are discarded
962 by md_convert_frag. */
963 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
965 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
966 #define RELAX_SECOND(X) ((X) & 0xff)
967 #define RELAX_USE_SECOND 0x10000
968 #define RELAX_SECOND_LONGER 0x20000
969 #define RELAX_NOMACRO 0x40000
970 #define RELAX_DELAY_SLOT 0x80000
971 #define RELAX_DELAY_SLOT_16BIT 0x100000
972 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
973 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
975 /* Branch without likely bit. If label is out of range, we turn:
977 beq reg1, reg2, label
987 with the following opcode replacements:
994 bltzal <-> bgezal (with jal label instead of j label)
996 Even though keeping the delay slot instruction in the delay slot of
997 the branch would be more efficient, it would be very tricky to do
998 correctly, because we'd have to introduce a variable frag *after*
999 the delay slot instruction, and expand that instead. Let's do it
1000 the easy way for now, even if the branch-not-taken case now costs
1001 one additional instruction. Out-of-range branches are not supposed
1002 to be common, anyway.
1004 Branch likely. If label is out of range, we turn:
1006 beql reg1, reg2, label
1007 delay slot (annulled if branch not taken)
1016 delay slot (executed only if branch taken)
1019 It would be possible to generate a shorter sequence by losing the
1020 likely bit, generating something like:
1025 delay slot (executed only if branch taken)
1037 bltzall -> bgezal (with jal label instead of j label)
1038 bgezall -> bltzal (ditto)
1041 but it's not clear that it would actually improve performance. */
1042 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1043 ((relax_substateT) \
1046 | ((toofar) ? 0x20 : 0) \
1047 | ((link) ? 0x40 : 0) \
1048 | ((likely) ? 0x80 : 0) \
1049 | ((uncond) ? 0x100 : 0)))
1050 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1051 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1052 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1053 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1054 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1055 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1057 /* For mips16 code, we use an entirely different form of relaxation.
1058 mips16 supports two versions of most instructions which take
1059 immediate values: a small one which takes some small value, and a
1060 larger one which takes a 16 bit value. Since branches also follow
1061 this pattern, relaxing these values is required.
1063 We can assemble both mips16 and normal MIPS code in a single
1064 object. Therefore, we need to support this type of relaxation at
1065 the same time that we support the relaxation described above. We
1066 use the high bit of the subtype field to distinguish these cases.
1068 The information we store for this type of relaxation is the
1069 argument code found in the opcode file for this relocation, whether
1070 the user explicitly requested a small or extended form, and whether
1071 the relocation is in a jump or jal delay slot. That tells us the
1072 size of the value, and how it should be stored. We also store
1073 whether the fragment is considered to be extended or not. We also
1074 store whether this is known to be a branch to a different section,
1075 whether we have tried to relax this frag yet, and whether we have
1076 ever extended a PC relative fragment because of a shift count. */
1077 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1080 | ((small) ? 0x100 : 0) \
1081 | ((ext) ? 0x200 : 0) \
1082 | ((dslot) ? 0x400 : 0) \
1083 | ((jal_dslot) ? 0x800 : 0))
1084 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1085 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1086 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1087 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1088 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1089 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1090 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1091 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1092 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1093 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1094 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1095 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1097 /* For microMIPS code, we use relaxation similar to one we use for
1098 MIPS16 code. Some instructions that take immediate values support
1099 two encodings: a small one which takes some small value, and a
1100 larger one which takes a 16 bit value. As some branches also follow
1101 this pattern, relaxing these values is required.
1103 We can assemble both microMIPS and normal MIPS code in a single
1104 object. Therefore, we need to support this type of relaxation at
1105 the same time that we support the relaxation described above. We
1106 use one of the high bits of the subtype field to distinguish these
1109 The information we store for this type of relaxation is the argument
1110 code found in the opcode file for this relocation, the register
1111 selected as the assembler temporary, whether the branch is
1112 unconditional, whether it is compact, whether it stores the link
1113 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1114 branches to a sequence of instructions is enabled, and whether the
1115 displacement of a branch is too large to fit as an immediate argument
1116 of a 16-bit and a 32-bit branch, respectively. */
1117 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1118 relax32, toofar16, toofar32) \
1121 | (((at) & 0x1f) << 8) \
1122 | ((uncond) ? 0x2000 : 0) \
1123 | ((compact) ? 0x4000 : 0) \
1124 | ((link) ? 0x8000 : 0) \
1125 | ((relax32) ? 0x10000 : 0) \
1126 | ((toofar16) ? 0x20000 : 0) \
1127 | ((toofar32) ? 0x40000 : 0))
1128 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1129 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1130 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1131 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1132 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1133 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1134 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1136 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1137 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1138 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1139 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1140 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1141 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1143 /* Sign-extend 16-bit value X. */
1144 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1146 /* Is the given value a sign-extended 32-bit value? */
1147 #define IS_SEXT_32BIT_NUM(x) \
1148 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1149 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1151 /* Is the given value a sign-extended 16-bit value? */
1152 #define IS_SEXT_16BIT_NUM(x) \
1153 (((x) &~ (offsetT) 0x7fff) == 0 \
1154 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1156 /* Is the given value a sign-extended 12-bit value? */
1157 #define IS_SEXT_12BIT_NUM(x) \
1158 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1160 /* Is the given value a sign-extended 9-bit value? */
1161 #define IS_SEXT_9BIT_NUM(x) \
1162 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1164 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1165 #define IS_ZEXT_32BIT_NUM(x) \
1166 (((x) &~ (offsetT) 0xffffffff) == 0 \
1167 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1169 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1171 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1172 (((STRUCT) >> (SHIFT)) & (MASK))
1174 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1175 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1177 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1178 : EXTRACT_BITS ((INSN).insn_opcode, \
1179 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1180 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1181 EXTRACT_BITS ((INSN).insn_opcode, \
1182 MIPS16OP_MASK_##FIELD, \
1183 MIPS16OP_SH_##FIELD)
1185 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1186 #define MIPS16_EXTEND (0xf000U << 16)
1188 /* Whether or not we are emitting a branch-likely macro. */
1189 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1191 /* Global variables used when generating relaxable macros. See the
1192 comment above RELAX_ENCODE for more details about how relaxation
1195 /* 0 if we're not emitting a relaxable macro.
1196 1 if we're emitting the first of the two relaxation alternatives.
1197 2 if we're emitting the second alternative. */
1200 /* The first relaxable fixup in the current frag. (In other words,
1201 the first fixup that refers to relaxable code.) */
1204 /* sizes[0] says how many bytes of the first alternative are stored in
1205 the current frag. Likewise sizes[1] for the second alternative. */
1206 unsigned int sizes
[2];
1208 /* The symbol on which the choice of sequence depends. */
1212 /* Global variables used to decide whether a macro needs a warning. */
1214 /* True if the macro is in a branch delay slot. */
1215 bfd_boolean delay_slot_p
;
1217 /* Set to the length in bytes required if the macro is in a delay slot
1218 that requires a specific length of instruction, otherwise zero. */
1219 unsigned int delay_slot_length
;
1221 /* For relaxable macros, sizes[0] is the length of the first alternative
1222 in bytes and sizes[1] is the length of the second alternative.
1223 For non-relaxable macros, both elements give the length of the
1225 unsigned int sizes
[2];
1227 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1228 instruction of the first alternative in bytes and first_insn_sizes[1]
1229 is the length of the first instruction of the second alternative.
1230 For non-relaxable macros, both elements give the length of the first
1231 instruction in bytes.
1233 Set to zero if we haven't yet seen the first instruction. */
1234 unsigned int first_insn_sizes
[2];
1236 /* For relaxable macros, insns[0] is the number of instructions for the
1237 first alternative and insns[1] is the number of instructions for the
1240 For non-relaxable macros, both elements give the number of
1241 instructions for the macro. */
1242 unsigned int insns
[2];
1244 /* The first variant frag for this macro. */
1246 } mips_macro_warning
;
1248 /* Prototypes for static functions. */
1250 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1252 static void append_insn
1253 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1254 bfd_boolean expansionp
);
1255 static void mips_no_prev_insn (void);
1256 static void macro_build (expressionS
*, const char *, const char *, ...);
1257 static void mips16_macro_build
1258 (expressionS
*, const char *, const char *, va_list *);
1259 static void load_register (int, expressionS
*, int);
1260 static void macro_start (void);
1261 static void macro_end (void);
1262 static void macro (struct mips_cl_insn
*ip
, char *str
);
1263 static void mips16_macro (struct mips_cl_insn
* ip
);
1264 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1265 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1266 static void mips16_immed
1267 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1268 unsigned int, unsigned long *);
1269 static size_t my_getSmallExpression
1270 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1271 static void my_getExpression (expressionS
*, char *);
1272 static void s_align (int);
1273 static void s_change_sec (int);
1274 static void s_change_section (int);
1275 static void s_cons (int);
1276 static void s_float_cons (int);
1277 static void s_mips_globl (int);
1278 static void s_option (int);
1279 static void s_mipsset (int);
1280 static void s_abicalls (int);
1281 static void s_cpload (int);
1282 static void s_cpsetup (int);
1283 static void s_cplocal (int);
1284 static void s_cprestore (int);
1285 static void s_cpreturn (int);
1286 static void s_dtprelword (int);
1287 static void s_dtpreldword (int);
1288 static void s_tprelword (int);
1289 static void s_tpreldword (int);
1290 static void s_gpvalue (int);
1291 static void s_gpword (int);
1292 static void s_gpdword (int);
1293 static void s_ehword (int);
1294 static void s_cpadd (int);
1295 static void s_insn (int);
1296 static void s_nan (int);
1297 static void md_obj_begin (void);
1298 static void md_obj_end (void);
1299 static void s_mips_ent (int);
1300 static void s_mips_end (int);
1301 static void s_mips_frame (int);
1302 static void s_mips_mask (int reg_type
);
1303 static void s_mips_stab (int);
1304 static void s_mips_weakext (int);
1305 static void s_mips_file (int);
1306 static void s_mips_loc (int);
1307 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1308 static int relaxed_branch_length (fragS
*, asection
*, int);
1309 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1310 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1312 /* Table and functions used to map between CPU/ISA names, and
1313 ISA levels, and CPU numbers. */
1315 struct mips_cpu_info
1317 const char *name
; /* CPU or ISA name. */
1318 int flags
; /* MIPS_CPU_* flags. */
1319 int ase
; /* Set of ASEs implemented by the CPU. */
1320 int isa
; /* ISA level. */
1321 int cpu
; /* CPU number (default CPU if ISA). */
1324 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1326 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1327 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1328 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1330 /* Command-line options. */
1331 const char *md_shortopts
= "O::g::G:";
1335 OPTION_MARCH
= OPTION_MD_BASE
,
1365 OPTION_NO_SMARTMIPS
,
1373 OPTION_NO_MICROMIPS
,
1376 OPTION_COMPAT_ARCH_BASE
,
1385 OPTION_M7000_HILO_FIX
,
1386 OPTION_MNO_7000_HILO_FIX
,
1390 OPTION_NO_FIX_RM7000
,
1391 OPTION_FIX_LOONGSON2F_JUMP
,
1392 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1393 OPTION_FIX_LOONGSON2F_NOP
,
1394 OPTION_NO_FIX_LOONGSON2F_NOP
,
1396 OPTION_NO_FIX_VR4120
,
1398 OPTION_NO_FIX_VR4130
,
1399 OPTION_FIX_CN63XXP1
,
1400 OPTION_NO_FIX_CN63XXP1
,
1407 OPTION_CONSTRUCT_FLOATS
,
1408 OPTION_NO_CONSTRUCT_FLOATS
,
1411 OPTION_RELAX_BRANCH
,
1412 OPTION_NO_RELAX_BRANCH
,
1421 OPTION_SINGLE_FLOAT
,
1422 OPTION_DOUBLE_FLOAT
,
1435 OPTION_MVXWORKS_PIC
,
1440 struct option md_longopts
[] =
1442 /* Options which specify architecture. */
1443 {"march", required_argument
, NULL
, OPTION_MARCH
},
1444 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1445 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1446 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1447 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1448 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1449 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1450 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1451 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1452 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1453 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1454 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1455 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1456 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1457 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1458 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1460 /* Options which specify Application Specific Extensions (ASEs). */
1461 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1462 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1463 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1464 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1465 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1466 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1467 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1468 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1469 {"mmt", no_argument
, NULL
, OPTION_MT
},
1470 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1471 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1472 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1473 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1474 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1475 {"meva", no_argument
, NULL
, OPTION_EVA
},
1476 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1477 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1478 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1479 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1480 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1481 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1482 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1483 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1484 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1485 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1486 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1488 /* Old-style architecture options. Don't add more of these. */
1489 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1490 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1491 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1492 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1493 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1494 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1495 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1496 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1498 /* Options which enable bug fixes. */
1499 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1500 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1501 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1502 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1503 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1504 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1505 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1506 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1507 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1508 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1509 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1510 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1511 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1512 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1513 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1514 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1515 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1517 /* Miscellaneous options. */
1518 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1519 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1520 {"break", no_argument
, NULL
, OPTION_BREAK
},
1521 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1522 {"EB", no_argument
, NULL
, OPTION_EB
},
1523 {"EL", no_argument
, NULL
, OPTION_EL
},
1524 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1525 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1526 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1527 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1528 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1529 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1530 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1531 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1532 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1533 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1534 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1535 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1536 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1537 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1538 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1539 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1540 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1541 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1543 /* Strictly speaking this next option is ELF specific,
1544 but we allow it for other ports as well in order to
1545 make testing easier. */
1546 {"32", no_argument
, NULL
, OPTION_32
},
1548 /* ELF-specific options. */
1549 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1550 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1551 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1552 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1553 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1554 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1555 {"n32", no_argument
, NULL
, OPTION_N32
},
1556 {"64", no_argument
, NULL
, OPTION_64
},
1557 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1558 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1559 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1560 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1561 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1562 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1564 {NULL
, no_argument
, NULL
, 0}
1566 size_t md_longopts_size
= sizeof (md_longopts
);
1568 /* Information about either an Application Specific Extension or an
1569 optional architecture feature that, for simplicity, we treat in the
1570 same way as an ASE. */
1573 /* The name of the ASE, used in both the command-line and .set options. */
1576 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1577 and 64-bit architectures, the flags here refer to the subset that
1578 is available on both. */
1581 /* The ASE_* flag used for instructions that are available on 64-bit
1582 architectures but that are not included in FLAGS. */
1583 unsigned int flags64
;
1585 /* The command-line options that turn the ASE on and off. */
1589 /* The minimum required architecture revisions for MIPS32, MIPS64,
1590 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1593 int micromips32_rev
;
1594 int micromips64_rev
;
1597 /* A table of all supported ASEs. */
1598 static const struct mips_ase mips_ases
[] = {
1599 { "dsp", ASE_DSP
, ASE_DSP64
,
1600 OPTION_DSP
, OPTION_NO_DSP
,
1603 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1604 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1607 { "eva", ASE_EVA
, 0,
1608 OPTION_EVA
, OPTION_NO_EVA
,
1611 { "mcu", ASE_MCU
, 0,
1612 OPTION_MCU
, OPTION_NO_MCU
,
1615 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1616 { "mdmx", ASE_MDMX
, 0,
1617 OPTION_MDMX
, OPTION_NO_MDMX
,
1620 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1621 { "mips3d", ASE_MIPS3D
, 0,
1622 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1626 OPTION_MT
, OPTION_NO_MT
,
1629 { "smartmips", ASE_SMARTMIPS
, 0,
1630 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1633 { "virt", ASE_VIRT
, ASE_VIRT64
,
1634 OPTION_VIRT
, OPTION_NO_VIRT
,
1637 { "msa", ASE_MSA
, ASE_MSA64
,
1638 OPTION_MSA
, OPTION_NO_MSA
,
1641 { "xpa", ASE_XPA
, 0,
1642 OPTION_XPA
, OPTION_NO_XPA
,
1646 /* The set of ASEs that require -mfp64. */
1647 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1649 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1650 static const unsigned int mips_ase_groups
[] = {
1656 The following pseudo-ops from the Kane and Heinrich MIPS book
1657 should be defined here, but are currently unsupported: .alias,
1658 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1660 The following pseudo-ops from the Kane and Heinrich MIPS book are
1661 specific to the type of debugging information being generated, and
1662 should be defined by the object format: .aent, .begin, .bend,
1663 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1666 The following pseudo-ops from the Kane and Heinrich MIPS book are
1667 not MIPS CPU specific, but are also not specific to the object file
1668 format. This file is probably the best place to define them, but
1669 they are not currently supported: .asm0, .endr, .lab, .struct. */
1671 static const pseudo_typeS mips_pseudo_table
[] =
1673 /* MIPS specific pseudo-ops. */
1674 {"option", s_option
, 0},
1675 {"set", s_mipsset
, 0},
1676 {"rdata", s_change_sec
, 'r'},
1677 {"sdata", s_change_sec
, 's'},
1678 {"livereg", s_ignore
, 0},
1679 {"abicalls", s_abicalls
, 0},
1680 {"cpload", s_cpload
, 0},
1681 {"cpsetup", s_cpsetup
, 0},
1682 {"cplocal", s_cplocal
, 0},
1683 {"cprestore", s_cprestore
, 0},
1684 {"cpreturn", s_cpreturn
, 0},
1685 {"dtprelword", s_dtprelword
, 0},
1686 {"dtpreldword", s_dtpreldword
, 0},
1687 {"tprelword", s_tprelword
, 0},
1688 {"tpreldword", s_tpreldword
, 0},
1689 {"gpvalue", s_gpvalue
, 0},
1690 {"gpword", s_gpword
, 0},
1691 {"gpdword", s_gpdword
, 0},
1692 {"ehword", s_ehword
, 0},
1693 {"cpadd", s_cpadd
, 0},
1694 {"insn", s_insn
, 0},
1697 /* Relatively generic pseudo-ops that happen to be used on MIPS
1699 {"asciiz", stringer
, 8 + 1},
1700 {"bss", s_change_sec
, 'b'},
1702 {"half", s_cons
, 1},
1703 {"dword", s_cons
, 3},
1704 {"weakext", s_mips_weakext
, 0},
1705 {"origin", s_org
, 0},
1706 {"repeat", s_rept
, 0},
1708 /* For MIPS this is non-standard, but we define it for consistency. */
1709 {"sbss", s_change_sec
, 'B'},
1711 /* These pseudo-ops are defined in read.c, but must be overridden
1712 here for one reason or another. */
1713 {"align", s_align
, 0},
1714 {"byte", s_cons
, 0},
1715 {"data", s_change_sec
, 'd'},
1716 {"double", s_float_cons
, 'd'},
1717 {"float", s_float_cons
, 'f'},
1718 {"globl", s_mips_globl
, 0},
1719 {"global", s_mips_globl
, 0},
1720 {"hword", s_cons
, 1},
1722 {"long", s_cons
, 2},
1723 {"octa", s_cons
, 4},
1724 {"quad", s_cons
, 3},
1725 {"section", s_change_section
, 0},
1726 {"short", s_cons
, 1},
1727 {"single", s_float_cons
, 'f'},
1728 {"stabd", s_mips_stab
, 'd'},
1729 {"stabn", s_mips_stab
, 'n'},
1730 {"stabs", s_mips_stab
, 's'},
1731 {"text", s_change_sec
, 't'},
1732 {"word", s_cons
, 2},
1734 { "extern", ecoff_directive_extern
, 0},
1739 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1741 /* These pseudo-ops should be defined by the object file format.
1742 However, a.out doesn't support them, so we have versions here. */
1743 {"aent", s_mips_ent
, 1},
1744 {"bgnb", s_ignore
, 0},
1745 {"end", s_mips_end
, 0},
1746 {"endb", s_ignore
, 0},
1747 {"ent", s_mips_ent
, 0},
1748 {"file", s_mips_file
, 0},
1749 {"fmask", s_mips_mask
, 'F'},
1750 {"frame", s_mips_frame
, 0},
1751 {"loc", s_mips_loc
, 0},
1752 {"mask", s_mips_mask
, 'R'},
1753 {"verstamp", s_ignore
, 0},
1757 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1758 purpose of the `.dc.a' internal pseudo-op. */
1761 mips_address_bytes (void)
1763 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1766 extern void pop_insert (const pseudo_typeS
*);
1769 mips_pop_insert (void)
1771 pop_insert (mips_pseudo_table
);
1772 if (! ECOFF_DEBUGGING
)
1773 pop_insert (mips_nonecoff_pseudo_table
);
1776 /* Symbols labelling the current insn. */
1778 struct insn_label_list
1780 struct insn_label_list
*next
;
1784 static struct insn_label_list
*free_insn_labels
;
1785 #define label_list tc_segment_info_data.labels
1787 static void mips_clear_insn_labels (void);
1788 static void mips_mark_labels (void);
1789 static void mips_compressed_mark_labels (void);
1792 mips_clear_insn_labels (void)
1794 register struct insn_label_list
**pl
;
1795 segment_info_type
*si
;
1799 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1802 si
= seg_info (now_seg
);
1803 *pl
= si
->label_list
;
1804 si
->label_list
= NULL
;
1808 /* Mark instruction labels in MIPS16/microMIPS mode. */
1811 mips_mark_labels (void)
1813 if (HAVE_CODE_COMPRESSION
)
1814 mips_compressed_mark_labels ();
1817 static char *expr_end
;
1819 /* An expression in a macro instruction. This is set by mips_ip and
1820 mips16_ip and when populated is always an O_constant. */
1822 static expressionS imm_expr
;
1824 /* The relocatable field in an instruction and the relocs associated
1825 with it. These variables are used for instructions like LUI and
1826 JAL as well as true offsets. They are also used for address
1827 operands in macros. */
1829 static expressionS offset_expr
;
1830 static bfd_reloc_code_real_type offset_reloc
[3]
1831 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1833 /* This is set to the resulting size of the instruction to be produced
1834 by mips16_ip if an explicit extension is used or by mips_ip if an
1835 explicit size is supplied. */
1837 static unsigned int forced_insn_length
;
1839 /* True if we are assembling an instruction. All dot symbols defined during
1840 this time should be treated as code labels. */
1842 static bfd_boolean mips_assembling_insn
;
1844 /* The pdr segment for per procedure frame/regmask info. Not used for
1847 static segT pdr_seg
;
1849 /* The default target format to use. */
1851 #if defined (TE_FreeBSD)
1852 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1853 #elif defined (TE_TMIPS)
1854 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1856 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1860 mips_target_format (void)
1862 switch (OUTPUT_FLAVOR
)
1864 case bfd_target_elf_flavour
:
1866 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1867 return (target_big_endian
1868 ? "elf32-bigmips-vxworks"
1869 : "elf32-littlemips-vxworks");
1871 return (target_big_endian
1872 ? (HAVE_64BIT_OBJECTS
1873 ? ELF_TARGET ("elf64-", "big")
1875 ? ELF_TARGET ("elf32-n", "big")
1876 : ELF_TARGET ("elf32-", "big")))
1877 : (HAVE_64BIT_OBJECTS
1878 ? ELF_TARGET ("elf64-", "little")
1880 ? ELF_TARGET ("elf32-n", "little")
1881 : ELF_TARGET ("elf32-", "little"))));
1888 /* Return the ISA revision that is currently in use, or 0 if we are
1889 generating code for MIPS V or below. */
1894 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1897 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
1900 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
1903 /* microMIPS implies revision 2 or above. */
1904 if (mips_opts
.micromips
)
1907 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1913 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1916 mips_ase_mask (unsigned int flags
)
1920 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1921 if (flags
& mips_ase_groups
[i
])
1922 flags
|= mips_ase_groups
[i
];
1926 /* Check whether the current ISA supports ASE. Issue a warning if
1930 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1934 static unsigned int warned_isa
;
1935 static unsigned int warned_fp32
;
1937 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1938 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1940 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1941 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1942 && (warned_isa
& ase
->flags
) != ase
->flags
)
1944 warned_isa
|= ase
->flags
;
1945 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1946 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1948 as_warn (_("the %d-bit %s architecture does not support the"
1949 " `%s' extension"), size
, base
, ase
->name
);
1951 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
1952 ase
->name
, base
, size
, min_rev
);
1954 if ((ase
->flags
& FP64_ASES
)
1955 && mips_opts
.fp
!= 64
1956 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1958 warned_fp32
|= ase
->flags
;
1959 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
1963 /* Check all enabled ASEs to see whether they are supported by the
1964 chosen architecture. */
1967 mips_check_isa_supports_ases (void)
1969 unsigned int i
, mask
;
1971 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1973 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1974 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1975 mips_check_isa_supports_ase (&mips_ases
[i
]);
1979 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1980 that were affected. */
1983 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1987 mask
= mips_ase_mask (ase
->flags
);
1988 mips_opts
.ase
&= ~mask
;
1990 mips_opts
.ase
|= ase
->flags
;
1994 /* Return the ASE called NAME, or null if none. */
1996 static const struct mips_ase
*
1997 mips_lookup_ase (const char *name
)
2001 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2002 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2003 return &mips_ases
[i
];
2007 /* Return the length of a microMIPS instruction in bytes. If bits of
2008 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
2009 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
2010 major opcode) will require further modifications to the opcode
2013 static inline unsigned int
2014 micromips_insn_length (const struct mips_opcode
*mo
)
2016 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2019 /* Return the length of MIPS16 instruction OPCODE. */
2021 static inline unsigned int
2022 mips16_opcode_length (unsigned long opcode
)
2024 return (opcode
>> 16) == 0 ? 2 : 4;
2027 /* Return the length of instruction INSN. */
2029 static inline unsigned int
2030 insn_length (const struct mips_cl_insn
*insn
)
2032 if (mips_opts
.micromips
)
2033 return micromips_insn_length (insn
->insn_mo
);
2034 else if (mips_opts
.mips16
)
2035 return mips16_opcode_length (insn
->insn_opcode
);
2040 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2043 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2048 insn
->insn_opcode
= mo
->match
;
2051 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2052 insn
->fixp
[i
] = NULL
;
2053 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2054 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2055 insn
->mips16_absolute_jump_p
= 0;
2056 insn
->complete_p
= 0;
2057 insn
->cleared_p
= 0;
2060 /* Get a list of all the operands in INSN. */
2062 static const struct mips_operand_array
*
2063 insn_operands (const struct mips_cl_insn
*insn
)
2065 if (insn
->insn_mo
>= &mips_opcodes
[0]
2066 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2067 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2069 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2070 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2071 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2073 if (insn
->insn_mo
>= µmips_opcodes
[0]
2074 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2075 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2080 /* Get a description of operand OPNO of INSN. */
2082 static const struct mips_operand
*
2083 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2085 const struct mips_operand_array
*operands
;
2087 operands
= insn_operands (insn
);
2088 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2090 return operands
->operand
[opno
];
2093 /* Install UVAL as the value of OPERAND in INSN. */
2096 insn_insert_operand (struct mips_cl_insn
*insn
,
2097 const struct mips_operand
*operand
, unsigned int uval
)
2099 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2102 /* Extract the value of OPERAND from INSN. */
2104 static inline unsigned
2105 insn_extract_operand (const struct mips_cl_insn
*insn
,
2106 const struct mips_operand
*operand
)
2108 return mips_extract_operand (operand
, insn
->insn_opcode
);
2111 /* Record the current MIPS16/microMIPS mode in now_seg. */
2114 mips_record_compressed_mode (void)
2116 segment_info_type
*si
;
2118 si
= seg_info (now_seg
);
2119 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2120 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2121 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2122 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2125 /* Read a standard MIPS instruction from BUF. */
2127 static unsigned long
2128 read_insn (char *buf
)
2130 if (target_big_endian
)
2131 return bfd_getb32 ((bfd_byte
*) buf
);
2133 return bfd_getl32 ((bfd_byte
*) buf
);
2136 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2140 write_insn (char *buf
, unsigned int insn
)
2142 md_number_to_chars (buf
, insn
, 4);
2146 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2147 has length LENGTH. */
2149 static unsigned long
2150 read_compressed_insn (char *buf
, unsigned int length
)
2156 for (i
= 0; i
< length
; i
+= 2)
2159 if (target_big_endian
)
2160 insn
|= bfd_getb16 ((char *) buf
);
2162 insn
|= bfd_getl16 ((char *) buf
);
2168 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2169 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2172 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2176 for (i
= 0; i
< length
; i
+= 2)
2177 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2178 return buf
+ length
;
2181 /* Install INSN at the location specified by its "frag" and "where" fields. */
2184 install_insn (const struct mips_cl_insn
*insn
)
2186 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2187 if (HAVE_CODE_COMPRESSION
)
2188 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2190 write_insn (f
, insn
->insn_opcode
);
2191 mips_record_compressed_mode ();
2194 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2195 and install the opcode in the new location. */
2198 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2203 insn
->where
= where
;
2204 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2205 if (insn
->fixp
[i
] != NULL
)
2207 insn
->fixp
[i
]->fx_frag
= frag
;
2208 insn
->fixp
[i
]->fx_where
= where
;
2210 install_insn (insn
);
2213 /* Add INSN to the end of the output. */
2216 add_fixed_insn (struct mips_cl_insn
*insn
)
2218 char *f
= frag_more (insn_length (insn
));
2219 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2222 /* Start a variant frag and move INSN to the start of the variant part,
2223 marking it as fixed. The other arguments are as for frag_var. */
2226 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2227 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2229 frag_grow (max_chars
);
2230 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2232 frag_var (rs_machine_dependent
, max_chars
, var
,
2233 subtype
, symbol
, offset
, NULL
);
2236 /* Insert N copies of INSN into the history buffer, starting at
2237 position FIRST. Neither FIRST nor N need to be clipped. */
2240 insert_into_history (unsigned int first
, unsigned int n
,
2241 const struct mips_cl_insn
*insn
)
2243 if (mips_relax
.sequence
!= 2)
2247 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2249 history
[i
] = history
[i
- n
];
2255 /* Clear the error in insn_error. */
2258 clear_insn_error (void)
2260 memset (&insn_error
, 0, sizeof (insn_error
));
2263 /* Possibly record error message MSG for the current instruction.
2264 If the error is about a particular argument, ARGNUM is the 1-based
2265 number of that argument, otherwise it is 0. FORMAT is the format
2266 of MSG. Return true if MSG was used, false if the current message
2270 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2275 /* Give priority to errors against specific arguments, and to
2276 the first whole-instruction message. */
2282 /* Keep insn_error if it is against a later argument. */
2283 if (argnum
< insn_error
.min_argnum
)
2286 /* If both errors are against the same argument but are different,
2287 give up on reporting a specific error for this argument.
2288 See the comment about mips_insn_error for details. */
2289 if (argnum
== insn_error
.min_argnum
2291 && strcmp (insn_error
.msg
, msg
) != 0)
2294 insn_error
.min_argnum
+= 1;
2298 insn_error
.min_argnum
= argnum
;
2299 insn_error
.format
= format
;
2300 insn_error
.msg
= msg
;
2304 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2305 as for set_insn_error_format. */
2308 set_insn_error (int argnum
, const char *msg
)
2310 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2313 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2314 as for set_insn_error_format. */
2317 set_insn_error_i (int argnum
, const char *msg
, int i
)
2319 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2323 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2324 are as for set_insn_error_format. */
2327 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2329 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2331 insn_error
.u
.ss
[0] = s1
;
2332 insn_error
.u
.ss
[1] = s2
;
2336 /* Report the error in insn_error, which is against assembly code STR. */
2339 report_insn_error (const char *str
)
2343 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2344 switch (insn_error
.format
)
2351 as_bad (msg
, insn_error
.u
.i
, str
);
2355 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2360 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2361 the idea is to make it obvious at a glance that each errata is
2365 init_vr4120_conflicts (void)
2367 #define CONFLICT(FIRST, SECOND) \
2368 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2370 /* Errata 21 - [D]DIV[U] after [D]MACC */
2371 CONFLICT (MACC
, DIV
);
2372 CONFLICT (DMACC
, DIV
);
2374 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2375 CONFLICT (DMULT
, DMULT
);
2376 CONFLICT (DMULT
, DMACC
);
2377 CONFLICT (DMACC
, DMULT
);
2378 CONFLICT (DMACC
, DMACC
);
2380 /* Errata 24 - MT{LO,HI} after [D]MACC */
2381 CONFLICT (MACC
, MTHILO
);
2382 CONFLICT (DMACC
, MTHILO
);
2384 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2385 instruction is executed immediately after a MACC or DMACC
2386 instruction, the result of [either instruction] is incorrect." */
2387 CONFLICT (MACC
, MULT
);
2388 CONFLICT (MACC
, DMULT
);
2389 CONFLICT (DMACC
, MULT
);
2390 CONFLICT (DMACC
, DMULT
);
2392 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2393 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2394 DDIV or DDIVU instruction, the result of the MACC or
2395 DMACC instruction is incorrect.". */
2396 CONFLICT (DMULT
, MACC
);
2397 CONFLICT (DMULT
, DMACC
);
2398 CONFLICT (DIV
, MACC
);
2399 CONFLICT (DIV
, DMACC
);
2409 #define RNUM_MASK 0x00000ff
2410 #define RTYPE_MASK 0x0ffff00
2411 #define RTYPE_NUM 0x0000100
2412 #define RTYPE_FPU 0x0000200
2413 #define RTYPE_FCC 0x0000400
2414 #define RTYPE_VEC 0x0000800
2415 #define RTYPE_GP 0x0001000
2416 #define RTYPE_CP0 0x0002000
2417 #define RTYPE_PC 0x0004000
2418 #define RTYPE_ACC 0x0008000
2419 #define RTYPE_CCC 0x0010000
2420 #define RTYPE_VI 0x0020000
2421 #define RTYPE_VF 0x0040000
2422 #define RTYPE_R5900_I 0x0080000
2423 #define RTYPE_R5900_Q 0x0100000
2424 #define RTYPE_R5900_R 0x0200000
2425 #define RTYPE_R5900_ACC 0x0400000
2426 #define RTYPE_MSA 0x0800000
2427 #define RWARN 0x8000000
2429 #define GENERIC_REGISTER_NUMBERS \
2430 {"$0", RTYPE_NUM | 0}, \
2431 {"$1", RTYPE_NUM | 1}, \
2432 {"$2", RTYPE_NUM | 2}, \
2433 {"$3", RTYPE_NUM | 3}, \
2434 {"$4", RTYPE_NUM | 4}, \
2435 {"$5", RTYPE_NUM | 5}, \
2436 {"$6", RTYPE_NUM | 6}, \
2437 {"$7", RTYPE_NUM | 7}, \
2438 {"$8", RTYPE_NUM | 8}, \
2439 {"$9", RTYPE_NUM | 9}, \
2440 {"$10", RTYPE_NUM | 10}, \
2441 {"$11", RTYPE_NUM | 11}, \
2442 {"$12", RTYPE_NUM | 12}, \
2443 {"$13", RTYPE_NUM | 13}, \
2444 {"$14", RTYPE_NUM | 14}, \
2445 {"$15", RTYPE_NUM | 15}, \
2446 {"$16", RTYPE_NUM | 16}, \
2447 {"$17", RTYPE_NUM | 17}, \
2448 {"$18", RTYPE_NUM | 18}, \
2449 {"$19", RTYPE_NUM | 19}, \
2450 {"$20", RTYPE_NUM | 20}, \
2451 {"$21", RTYPE_NUM | 21}, \
2452 {"$22", RTYPE_NUM | 22}, \
2453 {"$23", RTYPE_NUM | 23}, \
2454 {"$24", RTYPE_NUM | 24}, \
2455 {"$25", RTYPE_NUM | 25}, \
2456 {"$26", RTYPE_NUM | 26}, \
2457 {"$27", RTYPE_NUM | 27}, \
2458 {"$28", RTYPE_NUM | 28}, \
2459 {"$29", RTYPE_NUM | 29}, \
2460 {"$30", RTYPE_NUM | 30}, \
2461 {"$31", RTYPE_NUM | 31}
2463 #define FPU_REGISTER_NAMES \
2464 {"$f0", RTYPE_FPU | 0}, \
2465 {"$f1", RTYPE_FPU | 1}, \
2466 {"$f2", RTYPE_FPU | 2}, \
2467 {"$f3", RTYPE_FPU | 3}, \
2468 {"$f4", RTYPE_FPU | 4}, \
2469 {"$f5", RTYPE_FPU | 5}, \
2470 {"$f6", RTYPE_FPU | 6}, \
2471 {"$f7", RTYPE_FPU | 7}, \
2472 {"$f8", RTYPE_FPU | 8}, \
2473 {"$f9", RTYPE_FPU | 9}, \
2474 {"$f10", RTYPE_FPU | 10}, \
2475 {"$f11", RTYPE_FPU | 11}, \
2476 {"$f12", RTYPE_FPU | 12}, \
2477 {"$f13", RTYPE_FPU | 13}, \
2478 {"$f14", RTYPE_FPU | 14}, \
2479 {"$f15", RTYPE_FPU | 15}, \
2480 {"$f16", RTYPE_FPU | 16}, \
2481 {"$f17", RTYPE_FPU | 17}, \
2482 {"$f18", RTYPE_FPU | 18}, \
2483 {"$f19", RTYPE_FPU | 19}, \
2484 {"$f20", RTYPE_FPU | 20}, \
2485 {"$f21", RTYPE_FPU | 21}, \
2486 {"$f22", RTYPE_FPU | 22}, \
2487 {"$f23", RTYPE_FPU | 23}, \
2488 {"$f24", RTYPE_FPU | 24}, \
2489 {"$f25", RTYPE_FPU | 25}, \
2490 {"$f26", RTYPE_FPU | 26}, \
2491 {"$f27", RTYPE_FPU | 27}, \
2492 {"$f28", RTYPE_FPU | 28}, \
2493 {"$f29", RTYPE_FPU | 29}, \
2494 {"$f30", RTYPE_FPU | 30}, \
2495 {"$f31", RTYPE_FPU | 31}
2497 #define FPU_CONDITION_CODE_NAMES \
2498 {"$fcc0", RTYPE_FCC | 0}, \
2499 {"$fcc1", RTYPE_FCC | 1}, \
2500 {"$fcc2", RTYPE_FCC | 2}, \
2501 {"$fcc3", RTYPE_FCC | 3}, \
2502 {"$fcc4", RTYPE_FCC | 4}, \
2503 {"$fcc5", RTYPE_FCC | 5}, \
2504 {"$fcc6", RTYPE_FCC | 6}, \
2505 {"$fcc7", RTYPE_FCC | 7}
2507 #define COPROC_CONDITION_CODE_NAMES \
2508 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2509 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2510 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2511 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2512 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2513 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2514 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2515 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2517 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2518 {"$a4", RTYPE_GP | 8}, \
2519 {"$a5", RTYPE_GP | 9}, \
2520 {"$a6", RTYPE_GP | 10}, \
2521 {"$a7", RTYPE_GP | 11}, \
2522 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2523 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2524 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2525 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2526 {"$t0", RTYPE_GP | 12}, \
2527 {"$t1", RTYPE_GP | 13}, \
2528 {"$t2", RTYPE_GP | 14}, \
2529 {"$t3", RTYPE_GP | 15}
2531 #define O32_SYMBOLIC_REGISTER_NAMES \
2532 {"$t0", RTYPE_GP | 8}, \
2533 {"$t1", RTYPE_GP | 9}, \
2534 {"$t2", RTYPE_GP | 10}, \
2535 {"$t3", RTYPE_GP | 11}, \
2536 {"$t4", RTYPE_GP | 12}, \
2537 {"$t5", RTYPE_GP | 13}, \
2538 {"$t6", RTYPE_GP | 14}, \
2539 {"$t7", RTYPE_GP | 15}, \
2540 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2541 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2542 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2543 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2545 /* Remaining symbolic register names */
2546 #define SYMBOLIC_REGISTER_NAMES \
2547 {"$zero", RTYPE_GP | 0}, \
2548 {"$at", RTYPE_GP | 1}, \
2549 {"$AT", RTYPE_GP | 1}, \
2550 {"$v0", RTYPE_GP | 2}, \
2551 {"$v1", RTYPE_GP | 3}, \
2552 {"$a0", RTYPE_GP | 4}, \
2553 {"$a1", RTYPE_GP | 5}, \
2554 {"$a2", RTYPE_GP | 6}, \
2555 {"$a3", RTYPE_GP | 7}, \
2556 {"$s0", RTYPE_GP | 16}, \
2557 {"$s1", RTYPE_GP | 17}, \
2558 {"$s2", RTYPE_GP | 18}, \
2559 {"$s3", RTYPE_GP | 19}, \
2560 {"$s4", RTYPE_GP | 20}, \
2561 {"$s5", RTYPE_GP | 21}, \
2562 {"$s6", RTYPE_GP | 22}, \
2563 {"$s7", RTYPE_GP | 23}, \
2564 {"$t8", RTYPE_GP | 24}, \
2565 {"$t9", RTYPE_GP | 25}, \
2566 {"$k0", RTYPE_GP | 26}, \
2567 {"$kt0", RTYPE_GP | 26}, \
2568 {"$k1", RTYPE_GP | 27}, \
2569 {"$kt1", RTYPE_GP | 27}, \
2570 {"$gp", RTYPE_GP | 28}, \
2571 {"$sp", RTYPE_GP | 29}, \
2572 {"$s8", RTYPE_GP | 30}, \
2573 {"$fp", RTYPE_GP | 30}, \
2574 {"$ra", RTYPE_GP | 31}
2576 #define MIPS16_SPECIAL_REGISTER_NAMES \
2577 {"$pc", RTYPE_PC | 0}
2579 #define MDMX_VECTOR_REGISTER_NAMES \
2580 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2581 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2582 {"$v2", RTYPE_VEC | 2}, \
2583 {"$v3", RTYPE_VEC | 3}, \
2584 {"$v4", RTYPE_VEC | 4}, \
2585 {"$v5", RTYPE_VEC | 5}, \
2586 {"$v6", RTYPE_VEC | 6}, \
2587 {"$v7", RTYPE_VEC | 7}, \
2588 {"$v8", RTYPE_VEC | 8}, \
2589 {"$v9", RTYPE_VEC | 9}, \
2590 {"$v10", RTYPE_VEC | 10}, \
2591 {"$v11", RTYPE_VEC | 11}, \
2592 {"$v12", RTYPE_VEC | 12}, \
2593 {"$v13", RTYPE_VEC | 13}, \
2594 {"$v14", RTYPE_VEC | 14}, \
2595 {"$v15", RTYPE_VEC | 15}, \
2596 {"$v16", RTYPE_VEC | 16}, \
2597 {"$v17", RTYPE_VEC | 17}, \
2598 {"$v18", RTYPE_VEC | 18}, \
2599 {"$v19", RTYPE_VEC | 19}, \
2600 {"$v20", RTYPE_VEC | 20}, \
2601 {"$v21", RTYPE_VEC | 21}, \
2602 {"$v22", RTYPE_VEC | 22}, \
2603 {"$v23", RTYPE_VEC | 23}, \
2604 {"$v24", RTYPE_VEC | 24}, \
2605 {"$v25", RTYPE_VEC | 25}, \
2606 {"$v26", RTYPE_VEC | 26}, \
2607 {"$v27", RTYPE_VEC | 27}, \
2608 {"$v28", RTYPE_VEC | 28}, \
2609 {"$v29", RTYPE_VEC | 29}, \
2610 {"$v30", RTYPE_VEC | 30}, \
2611 {"$v31", RTYPE_VEC | 31}
2613 #define R5900_I_NAMES \
2614 {"$I", RTYPE_R5900_I | 0}
2616 #define R5900_Q_NAMES \
2617 {"$Q", RTYPE_R5900_Q | 0}
2619 #define R5900_R_NAMES \
2620 {"$R", RTYPE_R5900_R | 0}
2622 #define R5900_ACC_NAMES \
2623 {"$ACC", RTYPE_R5900_ACC | 0 }
2625 #define MIPS_DSP_ACCUMULATOR_NAMES \
2626 {"$ac0", RTYPE_ACC | 0}, \
2627 {"$ac1", RTYPE_ACC | 1}, \
2628 {"$ac2", RTYPE_ACC | 2}, \
2629 {"$ac3", RTYPE_ACC | 3}
2631 static const struct regname reg_names
[] = {
2632 GENERIC_REGISTER_NUMBERS
,
2634 FPU_CONDITION_CODE_NAMES
,
2635 COPROC_CONDITION_CODE_NAMES
,
2637 /* The $txx registers depends on the abi,
2638 these will be added later into the symbol table from
2639 one of the tables below once mips_abi is set after
2640 parsing of arguments from the command line. */
2641 SYMBOLIC_REGISTER_NAMES
,
2643 MIPS16_SPECIAL_REGISTER_NAMES
,
2644 MDMX_VECTOR_REGISTER_NAMES
,
2649 MIPS_DSP_ACCUMULATOR_NAMES
,
2653 static const struct regname reg_names_o32
[] = {
2654 O32_SYMBOLIC_REGISTER_NAMES
,
2658 static const struct regname reg_names_n32n64
[] = {
2659 N32N64_SYMBOLIC_REGISTER_NAMES
,
2663 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2664 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2665 of these register symbols, return the associated vector register,
2666 otherwise return SYMVAL itself. */
2669 mips_prefer_vec_regno (unsigned int symval
)
2671 if ((symval
& -2) == (RTYPE_GP
| 2))
2672 return RTYPE_VEC
| (symval
& 1);
2676 /* Return true if string [S, E) is a valid register name, storing its
2677 symbol value in *SYMVAL_PTR if so. */
2680 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2685 /* Terminate name. */
2689 /* Look up the name. */
2690 symbol
= symbol_find (s
);
2693 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2696 *symval_ptr
= S_GET_VALUE (symbol
);
2700 /* Return true if the string at *SPTR is a valid register name. Allow it
2701 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2704 When returning true, move *SPTR past the register, store the
2705 register's symbol value in *SYMVAL_PTR and the channel mask in
2706 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2707 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2708 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2711 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2712 unsigned int *channels_ptr
)
2716 unsigned int channels
, symval
, bit
;
2718 /* Find end of name. */
2720 if (is_name_beginner (*e
))
2722 while (is_part_of_name (*e
))
2726 if (!mips_parse_register_1 (s
, e
, &symval
))
2731 /* Eat characters from the end of the string that are valid
2732 channel suffixes. The preceding register must be $ACC or
2733 end with a digit, so there is no ambiguity. */
2736 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2737 if (m
> s
&& m
[-1] == *q
)
2744 || !mips_parse_register_1 (s
, m
, &symval
)
2745 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2750 *symval_ptr
= symval
;
2752 *channels_ptr
= channels
;
2756 /* Check if SPTR points at a valid register specifier according to TYPES.
2757 If so, then return 1, advance S to consume the specifier and store
2758 the register's number in REGNOP, otherwise return 0. */
2761 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2765 if (mips_parse_register (s
, ®no
, NULL
))
2767 if (types
& RTYPE_VEC
)
2768 regno
= mips_prefer_vec_regno (regno
);
2777 as_warn (_("unrecognized register name `%s'"), *s
);
2782 return regno
<= RNUM_MASK
;
2785 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2786 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2789 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2794 for (i
= 0; i
< 4; i
++)
2795 if (*s
== "xyzw"[i
])
2797 *channels
|= 1 << (3 - i
);
2803 /* Token types for parsed operand lists. */
2804 enum mips_operand_token_type
{
2805 /* A plain register, e.g. $f2. */
2808 /* A 4-bit XYZW channel mask. */
2811 /* A constant vector index, e.g. [1]. */
2814 /* A register vector index, e.g. [$2]. */
2817 /* A continuous range of registers, e.g. $s0-$s4. */
2820 /* A (possibly relocated) expression. */
2823 /* A floating-point value. */
2826 /* A single character. This can be '(', ')' or ',', but '(' only appears
2830 /* A doubled character, either "--" or "++". */
2833 /* The end of the operand list. */
2837 /* A parsed operand token. */
2838 struct mips_operand_token
2840 /* The type of token. */
2841 enum mips_operand_token_type type
;
2844 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2847 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2848 unsigned int channels
;
2850 /* The integer value of an OT_INTEGER_INDEX. */
2853 /* The two register symbol values involved in an OT_REG_RANGE. */
2855 unsigned int regno1
;
2856 unsigned int regno2
;
2859 /* The value of an OT_INTEGER. The value is represented as an
2860 expression and the relocation operators that were applied to
2861 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2862 relocation operators were used. */
2865 bfd_reloc_code_real_type relocs
[3];
2868 /* The binary data for an OT_FLOAT constant, and the number of bytes
2871 unsigned char data
[8];
2875 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2880 /* An obstack used to construct lists of mips_operand_tokens. */
2881 static struct obstack mips_operand_tokens
;
2883 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2886 mips_add_token (struct mips_operand_token
*token
,
2887 enum mips_operand_token_type type
)
2890 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2893 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2894 and OT_REG tokens for them if so, and return a pointer to the first
2895 unconsumed character. Return null otherwise. */
2898 mips_parse_base_start (char *s
)
2900 struct mips_operand_token token
;
2901 unsigned int regno
, channels
;
2902 bfd_boolean decrement_p
;
2908 SKIP_SPACE_TABS (s
);
2910 /* Only match "--" as part of a base expression. In other contexts "--X"
2911 is a double negative. */
2912 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2916 SKIP_SPACE_TABS (s
);
2919 /* Allow a channel specifier because that leads to better error messages
2920 than treating something like "$vf0x++" as an expression. */
2921 if (!mips_parse_register (&s
, ®no
, &channels
))
2925 mips_add_token (&token
, OT_CHAR
);
2930 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2933 token
.u
.regno
= regno
;
2934 mips_add_token (&token
, OT_REG
);
2938 token
.u
.channels
= channels
;
2939 mips_add_token (&token
, OT_CHANNELS
);
2942 /* For consistency, only match "++" as part of base expressions too. */
2943 SKIP_SPACE_TABS (s
);
2944 if (s
[0] == '+' && s
[1] == '+')
2948 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2954 /* Parse one or more tokens from S. Return a pointer to the first
2955 unconsumed character on success. Return null if an error was found
2956 and store the error text in insn_error. FLOAT_FORMAT is as for
2957 mips_parse_arguments. */
2960 mips_parse_argument_token (char *s
, char float_format
)
2962 char *end
, *save_in
, *err
;
2963 unsigned int regno1
, regno2
, channels
;
2964 struct mips_operand_token token
;
2966 /* First look for "($reg", since we want to treat that as an
2967 OT_CHAR and OT_REG rather than an expression. */
2968 end
= mips_parse_base_start (s
);
2972 /* Handle other characters that end up as OT_CHARs. */
2973 if (*s
== ')' || *s
== ',')
2976 mips_add_token (&token
, OT_CHAR
);
2981 /* Handle tokens that start with a register. */
2982 if (mips_parse_register (&s
, ®no1
, &channels
))
2986 /* A register and a VU0 channel suffix. */
2987 token
.u
.regno
= regno1
;
2988 mips_add_token (&token
, OT_REG
);
2990 token
.u
.channels
= channels
;
2991 mips_add_token (&token
, OT_CHANNELS
);
2995 SKIP_SPACE_TABS (s
);
2998 /* A register range. */
3000 SKIP_SPACE_TABS (s
);
3001 if (!mips_parse_register (&s
, ®no2
, NULL
))
3003 set_insn_error (0, _("invalid register range"));
3007 token
.u
.reg_range
.regno1
= regno1
;
3008 token
.u
.reg_range
.regno2
= regno2
;
3009 mips_add_token (&token
, OT_REG_RANGE
);
3013 /* Add the register itself. */
3014 token
.u
.regno
= regno1
;
3015 mips_add_token (&token
, OT_REG
);
3017 /* Check for a vector index. */
3021 SKIP_SPACE_TABS (s
);
3022 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3023 mips_add_token (&token
, OT_REG_INDEX
);
3026 expressionS element
;
3028 my_getExpression (&element
, s
);
3029 if (element
.X_op
!= O_constant
)
3031 set_insn_error (0, _("vector element must be constant"));
3035 token
.u
.index
= element
.X_add_number
;
3036 mips_add_token (&token
, OT_INTEGER_INDEX
);
3038 SKIP_SPACE_TABS (s
);
3041 set_insn_error (0, _("missing `]'"));
3051 /* First try to treat expressions as floats. */
3052 save_in
= input_line_pointer
;
3053 input_line_pointer
= s
;
3054 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3055 &token
.u
.flt
.length
);
3056 end
= input_line_pointer
;
3057 input_line_pointer
= save_in
;
3060 set_insn_error (0, err
);
3065 mips_add_token (&token
, OT_FLOAT
);
3070 /* Treat everything else as an integer expression. */
3071 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3072 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3073 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3074 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3076 mips_add_token (&token
, OT_INTEGER
);
3080 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3081 if expressions should be treated as 32-bit floating-point constants,
3082 'd' if they should be treated as 64-bit floating-point constants,
3083 or 0 if they should be treated as integer expressions (the usual case).
3085 Return a list of tokens on success, otherwise return 0. The caller
3086 must obstack_free the list after use. */
3088 static struct mips_operand_token
*
3089 mips_parse_arguments (char *s
, char float_format
)
3091 struct mips_operand_token token
;
3093 SKIP_SPACE_TABS (s
);
3096 s
= mips_parse_argument_token (s
, float_format
);
3099 obstack_free (&mips_operand_tokens
,
3100 obstack_finish (&mips_operand_tokens
));
3103 SKIP_SPACE_TABS (s
);
3105 mips_add_token (&token
, OT_END
);
3106 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3109 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3110 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3113 is_opcode_valid (const struct mips_opcode
*mo
)
3115 int isa
= mips_opts
.isa
;
3116 int ase
= mips_opts
.ase
;
3120 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3121 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3122 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3123 ase
|= mips_ases
[i
].flags64
;
3125 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3128 /* Check whether the instruction or macro requires single-precision or
3129 double-precision floating-point support. Note that this information is
3130 stored differently in the opcode table for insns and macros. */
3131 if (mo
->pinfo
== INSN_MACRO
)
3133 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3134 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3138 fp_s
= mo
->pinfo
& FP_S
;
3139 fp_d
= mo
->pinfo
& FP_D
;
3142 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3145 if (fp_s
&& mips_opts
.soft_float
)
3151 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3152 selected ISA and architecture. */
3155 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3157 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3160 /* Return TRUE if the size of the microMIPS opcode MO matches one
3161 explicitly requested. Always TRUE in the standard MIPS mode. */
3164 is_size_valid (const struct mips_opcode
*mo
)
3166 if (!mips_opts
.micromips
)
3169 if (mips_opts
.insn32
)
3171 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3173 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3176 if (!forced_insn_length
)
3178 if (mo
->pinfo
== INSN_MACRO
)
3180 return forced_insn_length
== micromips_insn_length (mo
);
3183 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3184 of the preceding instruction. Always TRUE in the standard MIPS mode.
3186 We don't accept macros in 16-bit delay slots to avoid a case where
3187 a macro expansion fails because it relies on a preceding 32-bit real
3188 instruction to have matched and does not handle the operands correctly.
3189 The only macros that may expand to 16-bit instructions are JAL that
3190 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3191 and BGT (that likewise cannot be placed in a delay slot) that decay to
3192 a NOP. In all these cases the macros precede any corresponding real
3193 instruction definitions in the opcode table, so they will match in the
3194 second pass where the size of the delay slot is ignored and therefore
3195 produce correct code. */
3198 is_delay_slot_valid (const struct mips_opcode
*mo
)
3200 if (!mips_opts
.micromips
)
3203 if (mo
->pinfo
== INSN_MACRO
)
3204 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3205 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3206 && micromips_insn_length (mo
) != 4)
3208 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3209 && micromips_insn_length (mo
) != 2)
3215 /* For consistency checking, verify that all bits of OPCODE are specified
3216 either by the match/mask part of the instruction definition, or by the
3217 operand list. Also build up a list of operands in OPERANDS.
3219 INSN_BITS says which bits of the instruction are significant.
3220 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3221 provides the mips_operand description of each operand. DECODE_OPERAND
3222 is null for MIPS16 instructions. */
3225 validate_mips_insn (const struct mips_opcode
*opcode
,
3226 unsigned long insn_bits
,
3227 const struct mips_operand
*(*decode_operand
) (const char *),
3228 struct mips_operand_array
*operands
)
3231 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3232 const struct mips_operand
*operand
;
3234 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3235 if ((mask
& opcode
->match
) != opcode
->match
)
3237 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3238 opcode
->name
, opcode
->args
);
3243 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3244 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3245 for (s
= opcode
->args
; *s
; ++s
)
3258 if (!decode_operand
)
3259 operand
= decode_mips16_operand (*s
, FALSE
);
3261 operand
= decode_operand (s
);
3262 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3264 as_bad (_("internal: unknown operand type: %s %s"),
3265 opcode
->name
, opcode
->args
);
3268 gas_assert (opno
< MAX_OPERANDS
);
3269 operands
->operand
[opno
] = operand
;
3270 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3272 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3273 if (operand
->type
== OP_MDMX_IMM_REG
)
3274 /* Bit 5 is the format selector (OB vs QH). The opcode table
3275 has separate entries for each format. */
3276 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3277 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3278 used_bits
&= ~(mask
& 0x700);
3280 /* Skip prefix characters. */
3281 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3286 doubled
= used_bits
& mask
& insn_bits
;
3289 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3290 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3294 undefined
= ~used_bits
& insn_bits
;
3295 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3297 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3298 undefined
, opcode
->name
, opcode
->args
);
3301 used_bits
&= ~insn_bits
;
3304 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3305 used_bits
, opcode
->name
, opcode
->args
);
3311 /* The MIPS16 version of validate_mips_insn. */
3314 validate_mips16_insn (const struct mips_opcode
*opcode
,
3315 struct mips_operand_array
*operands
)
3317 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3319 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3320 instruction. Use TMP to describe the full instruction. */
3321 struct mips_opcode tmp
;
3326 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3328 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3331 /* The microMIPS version of validate_mips_insn. */
3334 validate_micromips_insn (const struct mips_opcode
*opc
,
3335 struct mips_operand_array
*operands
)
3337 unsigned long insn_bits
;
3338 unsigned long major
;
3339 unsigned int length
;
3341 if (opc
->pinfo
== INSN_MACRO
)
3342 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3345 length
= micromips_insn_length (opc
);
3346 if (length
!= 2 && length
!= 4)
3348 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3349 "%s %s"), length
, opc
->name
, opc
->args
);
3352 major
= opc
->match
>> (10 + 8 * (length
- 2));
3353 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3354 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3356 as_bad (_("internal error: bad microMIPS opcode "
3357 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3361 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3362 insn_bits
= 1 << 4 * length
;
3363 insn_bits
<<= 4 * length
;
3365 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3369 /* This function is called once, at assembler startup time. It should set up
3370 all the tables, etc. that the MD part of the assembler will need. */
3375 const char *retval
= NULL
;
3379 if (mips_pic
!= NO_PIC
)
3381 if (g_switch_seen
&& g_switch_value
!= 0)
3382 as_bad (_("-G may not be used in position-independent code"));
3386 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3387 as_warn (_("could not set architecture and machine"));
3389 op_hash
= hash_new ();
3391 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3392 for (i
= 0; i
< NUMOPCODES
;)
3394 const char *name
= mips_opcodes
[i
].name
;
3396 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3399 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3400 mips_opcodes
[i
].name
, retval
);
3401 /* Probably a memory allocation problem? Give up now. */
3402 as_fatal (_("broken assembler, no assembly attempted"));
3406 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3407 decode_mips_operand
, &mips_operands
[i
]))
3409 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3411 create_insn (&nop_insn
, mips_opcodes
+ i
);
3412 if (mips_fix_loongson2f_nop
)
3413 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3414 nop_insn
.fixed_p
= 1;
3418 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3421 mips16_op_hash
= hash_new ();
3422 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3423 bfd_mips16_num_opcodes
);
3426 while (i
< bfd_mips16_num_opcodes
)
3428 const char *name
= mips16_opcodes
[i
].name
;
3430 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3432 as_fatal (_("internal: can't hash `%s': %s"),
3433 mips16_opcodes
[i
].name
, retval
);
3436 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3438 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3440 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3441 mips16_nop_insn
.fixed_p
= 1;
3445 while (i
< bfd_mips16_num_opcodes
3446 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3449 micromips_op_hash
= hash_new ();
3450 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3451 bfd_micromips_num_opcodes
);
3454 while (i
< bfd_micromips_num_opcodes
)
3456 const char *name
= micromips_opcodes
[i
].name
;
3458 retval
= hash_insert (micromips_op_hash
, name
,
3459 (void *) µmips_opcodes
[i
]);
3461 as_fatal (_("internal: can't hash `%s': %s"),
3462 micromips_opcodes
[i
].name
, retval
);
3465 struct mips_cl_insn
*micromips_nop_insn
;
3467 if (!validate_micromips_insn (µmips_opcodes
[i
],
3468 µmips_operands
[i
]))
3471 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3473 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3474 micromips_nop_insn
= µmips_nop16_insn
;
3475 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3476 micromips_nop_insn
= µmips_nop32_insn
;
3480 if (micromips_nop_insn
->insn_mo
== NULL
3481 && strcmp (name
, "nop") == 0)
3483 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3484 micromips_nop_insn
->fixed_p
= 1;
3488 while (++i
< bfd_micromips_num_opcodes
3489 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3493 as_fatal (_("broken assembler, no assembly attempted"));
3495 /* We add all the general register names to the symbol table. This
3496 helps us detect invalid uses of them. */
3497 for (i
= 0; reg_names
[i
].name
; i
++)
3498 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3499 reg_names
[i
].num
, /* & RNUM_MASK, */
3500 &zero_address_frag
));
3502 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3503 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3504 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3505 &zero_address_frag
));
3507 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3508 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3509 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3510 &zero_address_frag
));
3512 for (i
= 0; i
< 32; i
++)
3516 /* R5900 VU0 floating-point register. */
3517 regname
[sizeof (rename
) - 1] = 0;
3518 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3519 symbol_table_insert (symbol_new (regname
, reg_section
,
3520 RTYPE_VF
| i
, &zero_address_frag
));
3522 /* R5900 VU0 integer register. */
3523 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3524 symbol_table_insert (symbol_new (regname
, reg_section
,
3525 RTYPE_VI
| i
, &zero_address_frag
));
3528 snprintf (regname
, sizeof (regname
) - 1, "$w%d", i
);
3529 symbol_table_insert (symbol_new (regname
, reg_section
,
3530 RTYPE_MSA
| i
, &zero_address_frag
));
3533 obstack_init (&mips_operand_tokens
);
3535 mips_no_prev_insn ();
3538 mips_cprmask
[0] = 0;
3539 mips_cprmask
[1] = 0;
3540 mips_cprmask
[2] = 0;
3541 mips_cprmask
[3] = 0;
3543 /* set the default alignment for the text section (2**2) */
3544 record_alignment (text_section
, 2);
3546 bfd_set_gp_size (stdoutput
, g_switch_value
);
3548 /* On a native system other than VxWorks, sections must be aligned
3549 to 16 byte boundaries. When configured for an embedded ELF
3550 target, we don't bother. */
3551 if (strncmp (TARGET_OS
, "elf", 3) != 0
3552 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3554 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3555 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3556 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3559 /* Create a .reginfo section for register masks and a .mdebug
3560 section for debugging information. */
3568 subseg
= now_subseg
;
3570 /* The ABI says this section should be loaded so that the
3571 running program can access it. However, we don't load it
3572 if we are configured for an embedded target */
3573 flags
= SEC_READONLY
| SEC_DATA
;
3574 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3575 flags
|= SEC_ALLOC
| SEC_LOAD
;
3577 if (mips_abi
!= N64_ABI
)
3579 sec
= subseg_new (".reginfo", (subsegT
) 0);
3581 bfd_set_section_flags (stdoutput
, sec
, flags
);
3582 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3584 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3588 /* The 64-bit ABI uses a .MIPS.options section rather than
3589 .reginfo section. */
3590 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3591 bfd_set_section_flags (stdoutput
, sec
, flags
);
3592 bfd_set_section_alignment (stdoutput
, sec
, 3);
3594 /* Set up the option header. */
3596 Elf_Internal_Options opthdr
;
3599 opthdr
.kind
= ODK_REGINFO
;
3600 opthdr
.size
= (sizeof (Elf_External_Options
)
3601 + sizeof (Elf64_External_RegInfo
));
3604 f
= frag_more (sizeof (Elf_External_Options
));
3605 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3606 (Elf_External_Options
*) f
);
3608 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3612 if (ECOFF_DEBUGGING
)
3614 sec
= subseg_new (".mdebug", (subsegT
) 0);
3615 (void) bfd_set_section_flags (stdoutput
, sec
,
3616 SEC_HAS_CONTENTS
| SEC_READONLY
);
3617 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3619 else if (mips_flag_pdr
)
3621 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3622 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3623 SEC_READONLY
| SEC_RELOC
3625 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3628 subseg_set (seg
, subseg
);
3631 if (! ECOFF_DEBUGGING
)
3634 if (mips_fix_vr4120
)
3635 init_vr4120_conflicts ();
3641 mips_emit_delays ();
3642 if (! ECOFF_DEBUGGING
)
3647 md_assemble (char *str
)
3649 struct mips_cl_insn insn
;
3650 bfd_reloc_code_real_type unused_reloc
[3]
3651 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3653 imm_expr
.X_op
= O_absent
;
3654 offset_expr
.X_op
= O_absent
;
3655 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3656 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3657 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3659 mips_mark_labels ();
3660 mips_assembling_insn
= TRUE
;
3661 clear_insn_error ();
3663 if (mips_opts
.mips16
)
3664 mips16_ip (str
, &insn
);
3667 mips_ip (str
, &insn
);
3668 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3669 str
, insn
.insn_opcode
));
3673 report_insn_error (str
);
3674 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3677 if (mips_opts
.mips16
)
3678 mips16_macro (&insn
);
3685 if (offset_expr
.X_op
!= O_absent
)
3686 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3688 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3691 mips_assembling_insn
= FALSE
;
3694 /* Convenience functions for abstracting away the differences between
3695 MIPS16 and non-MIPS16 relocations. */
3697 static inline bfd_boolean
3698 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3702 case BFD_RELOC_MIPS16_JMP
:
3703 case BFD_RELOC_MIPS16_GPREL
:
3704 case BFD_RELOC_MIPS16_GOT16
:
3705 case BFD_RELOC_MIPS16_CALL16
:
3706 case BFD_RELOC_MIPS16_HI16_S
:
3707 case BFD_RELOC_MIPS16_HI16
:
3708 case BFD_RELOC_MIPS16_LO16
:
3716 static inline bfd_boolean
3717 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3721 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3722 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3723 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3724 case BFD_RELOC_MICROMIPS_GPREL16
:
3725 case BFD_RELOC_MICROMIPS_JMP
:
3726 case BFD_RELOC_MICROMIPS_HI16
:
3727 case BFD_RELOC_MICROMIPS_HI16_S
:
3728 case BFD_RELOC_MICROMIPS_LO16
:
3729 case BFD_RELOC_MICROMIPS_LITERAL
:
3730 case BFD_RELOC_MICROMIPS_GOT16
:
3731 case BFD_RELOC_MICROMIPS_CALL16
:
3732 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3733 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3734 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3735 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3736 case BFD_RELOC_MICROMIPS_SUB
:
3737 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3738 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3739 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3740 case BFD_RELOC_MICROMIPS_HIGHEST
:
3741 case BFD_RELOC_MICROMIPS_HIGHER
:
3742 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3743 case BFD_RELOC_MICROMIPS_JALR
:
3751 static inline bfd_boolean
3752 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3754 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3757 static inline bfd_boolean
3758 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3760 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3761 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3764 static inline bfd_boolean
3765 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3767 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3768 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3771 static inline bfd_boolean
3772 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3774 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3775 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3778 static inline bfd_boolean
3779 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3781 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3784 static inline bfd_boolean
3785 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3787 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3788 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3791 /* Return true if RELOC is a PC-relative relocation that does not have
3792 full address range. */
3794 static inline bfd_boolean
3795 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3799 case BFD_RELOC_16_PCREL_S2
:
3800 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3801 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3802 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3805 case BFD_RELOC_32_PCREL
:
3806 return HAVE_64BIT_ADDRESSES
;
3813 /* Return true if the given relocation might need a matching %lo().
3814 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3815 need a matching %lo() when applied to local symbols. */
3817 static inline bfd_boolean
3818 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3820 return (HAVE_IN_PLACE_ADDENDS
3821 && (hi16_reloc_p (reloc
)
3822 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3823 all GOT16 relocations evaluate to "G". */
3824 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3827 /* Return the type of %lo() reloc needed by RELOC, given that
3828 reloc_needs_lo_p. */
3830 static inline bfd_reloc_code_real_type
3831 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3833 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3834 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3838 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3841 static inline bfd_boolean
3842 fixup_has_matching_lo_p (fixS
*fixp
)
3844 return (fixp
->fx_next
!= NULL
3845 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3846 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3847 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3850 /* Move all labels in LABELS to the current insertion point. TEXT_P
3851 says whether the labels refer to text or data. */
3854 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3856 struct insn_label_list
*l
;
3859 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3861 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3862 symbol_set_frag (l
->label
, frag_now
);
3863 val
= (valueT
) frag_now_fix ();
3864 /* MIPS16/microMIPS text labels are stored as odd. */
3865 if (text_p
&& HAVE_CODE_COMPRESSION
)
3867 S_SET_VALUE (l
->label
, val
);
3871 /* Move all labels in insn_labels to the current insertion point
3872 and treat them as text labels. */
3875 mips_move_text_labels (void)
3877 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3881 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3883 bfd_boolean linkonce
= FALSE
;
3884 segT symseg
= S_GET_SEGMENT (sym
);
3886 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3888 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3890 /* The GNU toolchain uses an extension for ELF: a section
3891 beginning with the magic string .gnu.linkonce is a
3892 linkonce section. */
3893 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3894 sizeof ".gnu.linkonce" - 1) == 0)
3900 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3901 linker to handle them specially, such as generating jalx instructions
3902 when needed. We also make them odd for the duration of the assembly,
3903 in order to generate the right sort of code. We will make them even
3904 in the adjust_symtab routine, while leaving them marked. This is
3905 convenient for the debugger and the disassembler. The linker knows
3906 to make them odd again. */
3909 mips_compressed_mark_label (symbolS
*label
)
3911 gas_assert (HAVE_CODE_COMPRESSION
);
3913 if (mips_opts
.mips16
)
3914 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3916 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3917 if ((S_GET_VALUE (label
) & 1) == 0
3918 /* Don't adjust the address if the label is global or weak, or
3919 in a link-once section, since we'll be emitting symbol reloc
3920 references to it which will be patched up by the linker, and
3921 the final value of the symbol may or may not be MIPS16/microMIPS. */
3922 && !S_IS_WEAK (label
)
3923 && !S_IS_EXTERNAL (label
)
3924 && !s_is_linkonce (label
, now_seg
))
3925 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3928 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3931 mips_compressed_mark_labels (void)
3933 struct insn_label_list
*l
;
3935 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3936 mips_compressed_mark_label (l
->label
);
3939 /* End the current frag. Make it a variant frag and record the
3943 relax_close_frag (void)
3945 mips_macro_warning
.first_frag
= frag_now
;
3946 frag_var (rs_machine_dependent
, 0, 0,
3947 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3948 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3950 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3951 mips_relax
.first_fixup
= 0;
3954 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3955 See the comment above RELAX_ENCODE for more details. */
3958 relax_start (symbolS
*symbol
)
3960 gas_assert (mips_relax
.sequence
== 0);
3961 mips_relax
.sequence
= 1;
3962 mips_relax
.symbol
= symbol
;
3965 /* Start generating the second version of a relaxable sequence.
3966 See the comment above RELAX_ENCODE for more details. */
3971 gas_assert (mips_relax
.sequence
== 1);
3972 mips_relax
.sequence
= 2;
3975 /* End the current relaxable sequence. */
3980 gas_assert (mips_relax
.sequence
== 2);
3981 relax_close_frag ();
3982 mips_relax
.sequence
= 0;
3985 /* Return true if IP is a delayed branch or jump. */
3987 static inline bfd_boolean
3988 delayed_branch_p (const struct mips_cl_insn
*ip
)
3990 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3991 | INSN_COND_BRANCH_DELAY
3992 | INSN_COND_BRANCH_LIKELY
)) != 0;
3995 /* Return true if IP is a compact branch or jump. */
3997 static inline bfd_boolean
3998 compact_branch_p (const struct mips_cl_insn
*ip
)
4000 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4001 | INSN2_COND_BRANCH
)) != 0;
4004 /* Return true if IP is an unconditional branch or jump. */
4006 static inline bfd_boolean
4007 uncond_branch_p (const struct mips_cl_insn
*ip
)
4009 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4010 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4013 /* Return true if IP is a branch-likely instruction. */
4015 static inline bfd_boolean
4016 branch_likely_p (const struct mips_cl_insn
*ip
)
4018 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4021 /* Return the type of nop that should be used to fill the delay slot
4022 of delayed branch IP. */
4024 static struct mips_cl_insn
*
4025 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4027 if (mips_opts
.micromips
4028 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4029 return µmips_nop32_insn
;
4033 /* Return a mask that has bit N set if OPCODE reads the register(s)
4037 insn_read_mask (const struct mips_opcode
*opcode
)
4039 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4042 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4046 insn_write_mask (const struct mips_opcode
*opcode
)
4048 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4051 /* Return a mask of the registers specified by operand OPERAND of INSN.
4052 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4056 operand_reg_mask (const struct mips_cl_insn
*insn
,
4057 const struct mips_operand
*operand
,
4058 unsigned int type_mask
)
4060 unsigned int uval
, vsel
;
4062 switch (operand
->type
)
4069 case OP_ADDIUSP_INT
:
4070 case OP_ENTRY_EXIT_LIST
:
4071 case OP_REPEAT_DEST_REG
:
4072 case OP_REPEAT_PREV_REG
:
4075 case OP_VU0_MATCH_SUFFIX
:
4080 case OP_OPTIONAL_REG
:
4082 const struct mips_reg_operand
*reg_op
;
4084 reg_op
= (const struct mips_reg_operand
*) operand
;
4085 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4087 uval
= insn_extract_operand (insn
, operand
);
4088 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4093 const struct mips_reg_pair_operand
*pair_op
;
4095 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4096 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4098 uval
= insn_extract_operand (insn
, operand
);
4099 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4102 case OP_CLO_CLZ_DEST
:
4103 if (!(type_mask
& (1 << OP_REG_GP
)))
4105 uval
= insn_extract_operand (insn
, operand
);
4106 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4108 case OP_LWM_SWM_LIST
:
4111 case OP_SAVE_RESTORE_LIST
:
4114 case OP_MDMX_IMM_REG
:
4115 if (!(type_mask
& (1 << OP_REG_VEC
)))
4117 uval
= insn_extract_operand (insn
, operand
);
4119 if ((vsel
& 0x18) == 0x18)
4121 return 1 << (uval
& 31);
4124 if (!(type_mask
& (1 << OP_REG_GP
)))
4126 return 1 << insn_extract_operand (insn
, operand
);
4131 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4132 where bit N of OPNO_MASK is set if operand N should be included.
4133 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4137 insn_reg_mask (const struct mips_cl_insn
*insn
,
4138 unsigned int type_mask
, unsigned int opno_mask
)
4140 unsigned int opno
, reg_mask
;
4144 while (opno_mask
!= 0)
4147 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4154 /* Return the mask of core registers that IP reads. */
4157 gpr_read_mask (const struct mips_cl_insn
*ip
)
4159 unsigned long pinfo
, pinfo2
;
4162 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4163 pinfo
= ip
->insn_mo
->pinfo
;
4164 pinfo2
= ip
->insn_mo
->pinfo2
;
4165 if (pinfo
& INSN_UDI
)
4167 /* UDI instructions have traditionally been assumed to read RS
4169 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4170 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4172 if (pinfo
& INSN_READ_GPR_24
)
4174 if (pinfo2
& INSN2_READ_GPR_16
)
4176 if (pinfo2
& INSN2_READ_SP
)
4178 if (pinfo2
& INSN2_READ_GPR_31
)
4180 /* Don't include register 0. */
4184 /* Return the mask of core registers that IP writes. */
4187 gpr_write_mask (const struct mips_cl_insn
*ip
)
4189 unsigned long pinfo
, pinfo2
;
4192 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4193 pinfo
= ip
->insn_mo
->pinfo
;
4194 pinfo2
= ip
->insn_mo
->pinfo2
;
4195 if (pinfo
& INSN_WRITE_GPR_24
)
4197 if (pinfo
& INSN_WRITE_GPR_31
)
4199 if (pinfo
& INSN_UDI
)
4200 /* UDI instructions have traditionally been assumed to write to RD. */
4201 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4202 if (pinfo2
& INSN2_WRITE_SP
)
4204 /* Don't include register 0. */
4208 /* Return the mask of floating-point registers that IP reads. */
4211 fpr_read_mask (const struct mips_cl_insn
*ip
)
4213 unsigned long pinfo
;
4216 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4217 | (1 << OP_REG_MSA
)),
4218 insn_read_mask (ip
->insn_mo
));
4219 pinfo
= ip
->insn_mo
->pinfo
;
4220 /* Conservatively treat all operands to an FP_D instruction are doubles.
4221 (This is overly pessimistic for things like cvt.d.s.) */
4222 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4227 /* Return the mask of floating-point registers that IP writes. */
4230 fpr_write_mask (const struct mips_cl_insn
*ip
)
4232 unsigned long pinfo
;
4235 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4236 | (1 << OP_REG_MSA
)),
4237 insn_write_mask (ip
->insn_mo
));
4238 pinfo
= ip
->insn_mo
->pinfo
;
4239 /* Conservatively treat all operands to an FP_D instruction are doubles.
4240 (This is overly pessimistic for things like cvt.s.d.) */
4241 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4246 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4247 Check whether that is allowed. */
4250 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4252 const char *s
= insn
->name
;
4254 if (insn
->pinfo
== INSN_MACRO
)
4255 /* Let a macro pass, we'll catch it later when it is expanded. */
4258 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4260 /* Allow odd registers for single-precision ops. */
4261 switch (insn
->pinfo
& (FP_S
| FP_D
))
4272 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4273 s
= strchr (insn
->name
, '.');
4274 if (s
!= NULL
&& opnum
== 2)
4275 s
= strchr (s
+ 1, '.');
4276 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4279 /* Single-precision coprocessor loads and moves are OK too. */
4280 if ((insn
->pinfo
& FP_S
)
4281 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4282 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4288 /* Information about an instruction argument that we're trying to match. */
4289 struct mips_arg_info
4291 /* The instruction so far. */
4292 struct mips_cl_insn
*insn
;
4294 /* The first unconsumed operand token. */
4295 struct mips_operand_token
*token
;
4297 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4300 /* The 1-based argument number, for error reporting. This does not
4301 count elided optional registers, etc.. */
4304 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4305 unsigned int last_regno
;
4307 /* If the first operand was an OP_REG, this is the register that it
4308 specified, otherwise it is ILLEGAL_REG. */
4309 unsigned int dest_regno
;
4311 /* The value of the last OP_INT operand. Only used for OP_MSB,
4312 where it gives the lsb position. */
4313 unsigned int last_op_int
;
4315 /* If true, match routines should assume that no later instruction
4316 alternative matches and should therefore be as accomodating as
4317 possible. Match routines should not report errors if something
4318 is only invalid for !LAX_MATCH. */
4319 bfd_boolean lax_match
;
4321 /* True if a reference to the current AT register was seen. */
4322 bfd_boolean seen_at
;
4325 /* Record that the argument is out of range. */
4328 match_out_of_range (struct mips_arg_info
*arg
)
4330 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4333 /* Record that the argument isn't constant but needs to be. */
4336 match_not_constant (struct mips_arg_info
*arg
)
4338 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4342 /* Try to match an OT_CHAR token for character CH. Consume the token
4343 and return true on success, otherwise return false. */
4346 match_char (struct mips_arg_info
*arg
, char ch
)
4348 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4358 /* Try to get an expression from the next tokens in ARG. Consume the
4359 tokens and return true on success, storing the expression value in
4360 VALUE and relocation types in R. */
4363 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4364 bfd_reloc_code_real_type
*r
)
4366 /* If the next token is a '(' that was parsed as being part of a base
4367 expression, assume we have an elided offset. The later match will fail
4368 if this turns out to be wrong. */
4369 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4371 value
->X_op
= O_constant
;
4372 value
->X_add_number
= 0;
4373 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4377 /* Reject register-based expressions such as "0+$2" and "(($2))".
4378 For plain registers the default error seems more appropriate. */
4379 if (arg
->token
->type
== OT_INTEGER
4380 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4382 set_insn_error (arg
->argnum
, _("register value used as expression"));
4386 if (arg
->token
->type
== OT_INTEGER
)
4388 *value
= arg
->token
->u
.integer
.value
;
4389 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4395 (arg
->argnum
, _("operand %d must be an immediate expression"),
4400 /* Try to get a constant expression from the next tokens in ARG. Consume
4401 the tokens and return return true on success, storing the constant value
4402 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4406 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4409 bfd_reloc_code_real_type r
[3];
4411 if (!match_expression (arg
, &ex
, r
))
4414 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4415 *value
= ex
.X_add_number
;
4418 match_not_constant (arg
);
4424 /* Return the RTYPE_* flags for a register operand of type TYPE that
4425 appears in instruction OPCODE. */
4428 convert_reg_type (const struct mips_opcode
*opcode
,
4429 enum mips_reg_operand_type type
)
4434 return RTYPE_NUM
| RTYPE_GP
;
4437 /* Allow vector register names for MDMX if the instruction is a 64-bit
4438 FPR load, store or move (including moves to and from GPRs). */
4439 if ((mips_opts
.ase
& ASE_MDMX
)
4440 && (opcode
->pinfo
& FP_D
)
4441 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4442 | INSN_COPROC_MEMORY_DELAY
4443 | INSN_LOAD_COPROC_DELAY
4445 | INSN_STORE_MEMORY
)))
4446 return RTYPE_FPU
| RTYPE_VEC
;
4450 if (opcode
->pinfo
& (FP_D
| FP_S
))
4451 return RTYPE_CCC
| RTYPE_FCC
;
4455 if (opcode
->membership
& INSN_5400
)
4457 return RTYPE_FPU
| RTYPE_VEC
;
4463 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4464 return RTYPE_NUM
| RTYPE_CP0
;
4471 return RTYPE_NUM
| RTYPE_VI
;
4474 return RTYPE_NUM
| RTYPE_VF
;
4476 case OP_REG_R5900_I
:
4477 return RTYPE_R5900_I
;
4479 case OP_REG_R5900_Q
:
4480 return RTYPE_R5900_Q
;
4482 case OP_REG_R5900_R
:
4483 return RTYPE_R5900_R
;
4485 case OP_REG_R5900_ACC
:
4486 return RTYPE_R5900_ACC
;
4491 case OP_REG_MSA_CTRL
:
4497 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4500 check_regno (struct mips_arg_info
*arg
,
4501 enum mips_reg_operand_type type
, unsigned int regno
)
4503 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4504 arg
->seen_at
= TRUE
;
4506 if (type
== OP_REG_FP
4509 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4510 as_warn (_("float register should be even, was %d"), regno
);
4512 if (type
== OP_REG_CCC
)
4517 name
= arg
->insn
->insn_mo
->name
;
4518 length
= strlen (name
);
4519 if ((regno
& 1) != 0
4520 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4521 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4522 as_warn (_("condition code register should be even for %s, was %d"),
4525 if ((regno
& 3) != 0
4526 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4527 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4532 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4533 a register of type TYPE. Return true on success, storing the register
4534 number in *REGNO and warning about any dubious uses. */
4537 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4538 unsigned int symval
, unsigned int *regno
)
4540 if (type
== OP_REG_VEC
)
4541 symval
= mips_prefer_vec_regno (symval
);
4542 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4545 *regno
= symval
& RNUM_MASK
;
4546 check_regno (arg
, type
, *regno
);
4550 /* Try to interpret the next token in ARG as a register of type TYPE.
4551 Consume the token and return true on success, storing the register
4552 number in *REGNO. Return false on failure. */
4555 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4556 unsigned int *regno
)
4558 if (arg
->token
->type
== OT_REG
4559 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4567 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4568 Consume the token and return true on success, storing the register numbers
4569 in *REGNO1 and *REGNO2. Return false on failure. */
4572 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4573 unsigned int *regno1
, unsigned int *regno2
)
4575 if (match_reg (arg
, type
, regno1
))
4580 if (arg
->token
->type
== OT_REG_RANGE
4581 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4582 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4583 && *regno1
<= *regno2
)
4591 /* OP_INT matcher. */
4594 match_int_operand (struct mips_arg_info
*arg
,
4595 const struct mips_operand
*operand_base
)
4597 const struct mips_int_operand
*operand
;
4599 int min_val
, max_val
, factor
;
4602 operand
= (const struct mips_int_operand
*) operand_base
;
4603 factor
= 1 << operand
->shift
;
4604 min_val
= mips_int_operand_min (operand
);
4605 max_val
= mips_int_operand_max (operand
);
4607 if (operand_base
->lsb
== 0
4608 && operand_base
->size
== 16
4609 && operand
->shift
== 0
4610 && operand
->bias
== 0
4611 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4613 /* The operand can be relocated. */
4614 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4617 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4618 /* Relocation operators were used. Accept the arguent and
4619 leave the relocation value in offset_expr and offset_relocs
4620 for the caller to process. */
4623 if (offset_expr
.X_op
!= O_constant
)
4625 /* Accept non-constant operands if no later alternative matches,
4626 leaving it for the caller to process. */
4627 if (!arg
->lax_match
)
4629 offset_reloc
[0] = BFD_RELOC_LO16
;
4633 /* Clear the global state; we're going to install the operand
4635 sval
= offset_expr
.X_add_number
;
4636 offset_expr
.X_op
= O_absent
;
4638 /* For compatibility with older assemblers, we accept
4639 0x8000-0xffff as signed 16-bit numbers when only
4640 signed numbers are allowed. */
4643 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4644 if (!arg
->lax_match
&& sval
<= max_val
)
4650 if (!match_const_int (arg
, &sval
))
4654 arg
->last_op_int
= sval
;
4656 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
4658 match_out_of_range (arg
);
4662 uval
= (unsigned int) sval
>> operand
->shift
;
4663 uval
-= operand
->bias
;
4665 /* Handle -mfix-cn63xxp1. */
4667 && mips_fix_cn63xxp1
4668 && !mips_opts
.micromips
4669 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4684 /* The rest must be changed to 28. */
4689 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4693 /* OP_MAPPED_INT matcher. */
4696 match_mapped_int_operand (struct mips_arg_info
*arg
,
4697 const struct mips_operand
*operand_base
)
4699 const struct mips_mapped_int_operand
*operand
;
4700 unsigned int uval
, num_vals
;
4703 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4704 if (!match_const_int (arg
, &sval
))
4707 num_vals
= 1 << operand_base
->size
;
4708 for (uval
= 0; uval
< num_vals
; uval
++)
4709 if (operand
->int_map
[uval
] == sval
)
4711 if (uval
== num_vals
)
4713 match_out_of_range (arg
);
4717 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4721 /* OP_MSB matcher. */
4724 match_msb_operand (struct mips_arg_info
*arg
,
4725 const struct mips_operand
*operand_base
)
4727 const struct mips_msb_operand
*operand
;
4728 int min_val
, max_val
, max_high
;
4729 offsetT size
, sval
, high
;
4731 operand
= (const struct mips_msb_operand
*) operand_base
;
4732 min_val
= operand
->bias
;
4733 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4734 max_high
= operand
->opsize
;
4736 if (!match_const_int (arg
, &size
))
4739 high
= size
+ arg
->last_op_int
;
4740 sval
= operand
->add_lsb
? high
: size
;
4742 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4744 match_out_of_range (arg
);
4747 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4751 /* OP_REG matcher. */
4754 match_reg_operand (struct mips_arg_info
*arg
,
4755 const struct mips_operand
*operand_base
)
4757 const struct mips_reg_operand
*operand
;
4758 unsigned int regno
, uval
, num_vals
;
4760 operand
= (const struct mips_reg_operand
*) operand_base
;
4761 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4764 if (operand
->reg_map
)
4766 num_vals
= 1 << operand
->root
.size
;
4767 for (uval
= 0; uval
< num_vals
; uval
++)
4768 if (operand
->reg_map
[uval
] == regno
)
4770 if (num_vals
== uval
)
4776 arg
->last_regno
= regno
;
4777 if (arg
->opnum
== 1)
4778 arg
->dest_regno
= regno
;
4779 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4783 /* OP_REG_PAIR matcher. */
4786 match_reg_pair_operand (struct mips_arg_info
*arg
,
4787 const struct mips_operand
*operand_base
)
4789 const struct mips_reg_pair_operand
*operand
;
4790 unsigned int regno1
, regno2
, uval
, num_vals
;
4792 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4793 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4794 || !match_char (arg
, ',')
4795 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4798 num_vals
= 1 << operand_base
->size
;
4799 for (uval
= 0; uval
< num_vals
; uval
++)
4800 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4802 if (uval
== num_vals
)
4805 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4809 /* OP_PCREL matcher. The caller chooses the relocation type. */
4812 match_pcrel_operand (struct mips_arg_info
*arg
)
4814 bfd_reloc_code_real_type r
[3];
4816 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4819 /* OP_PERF_REG matcher. */
4822 match_perf_reg_operand (struct mips_arg_info
*arg
,
4823 const struct mips_operand
*operand
)
4827 if (!match_const_int (arg
, &sval
))
4832 || (mips_opts
.arch
== CPU_R5900
4833 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4834 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4836 set_insn_error (arg
->argnum
, _("invalid performance register"));
4840 insn_insert_operand (arg
->insn
, operand
, sval
);
4844 /* OP_ADDIUSP matcher. */
4847 match_addiusp_operand (struct mips_arg_info
*arg
,
4848 const struct mips_operand
*operand
)
4853 if (!match_const_int (arg
, &sval
))
4858 match_out_of_range (arg
);
4863 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4865 match_out_of_range (arg
);
4869 uval
= (unsigned int) sval
;
4870 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4871 insn_insert_operand (arg
->insn
, operand
, uval
);
4875 /* OP_CLO_CLZ_DEST matcher. */
4878 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4879 const struct mips_operand
*operand
)
4883 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4886 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4890 /* OP_LWM_SWM_LIST matcher. */
4893 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4894 const struct mips_operand
*operand
)
4896 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4897 struct mips_arg_info reset
;
4900 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4904 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4909 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4912 while (match_char (arg
, ',')
4913 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4916 if (operand
->size
== 2)
4918 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4924 and any permutations of these. */
4925 if ((reglist
& 0xfff1ffff) != 0x80010000)
4928 sregs
= (reglist
>> 17) & 7;
4933 /* The list must include at least one of ra and s0-sN,
4934 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4935 which are $23 and $30 respectively.) E.g.:
4943 and any permutations of these. */
4944 if ((reglist
& 0x3f00ffff) != 0)
4947 ra
= (reglist
>> 27) & 0x10;
4948 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4951 if ((sregs
& -sregs
) != sregs
)
4954 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4958 /* OP_ENTRY_EXIT_LIST matcher. */
4961 match_entry_exit_operand (struct mips_arg_info
*arg
,
4962 const struct mips_operand
*operand
)
4965 bfd_boolean is_exit
;
4967 /* The format is the same for both ENTRY and EXIT, but the constraints
4969 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4970 mask
= (is_exit
? 7 << 3 : 0);
4973 unsigned int regno1
, regno2
;
4974 bfd_boolean is_freg
;
4976 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4978 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4983 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4986 mask
|= (5 + regno2
) << 3;
4988 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4989 mask
|= (regno2
- 3) << 3;
4990 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4991 mask
|= (regno2
- 15) << 1;
4992 else if (regno1
== RA
&& regno2
== RA
)
4997 while (match_char (arg
, ','));
4999 insn_insert_operand (arg
->insn
, operand
, mask
);
5003 /* OP_SAVE_RESTORE_LIST matcher. */
5006 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5008 unsigned int opcode
, args
, statics
, sregs
;
5009 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5012 opcode
= arg
->insn
->insn_opcode
;
5014 num_frame_sizes
= 0;
5020 unsigned int regno1
, regno2
;
5022 if (arg
->token
->type
== OT_INTEGER
)
5024 /* Handle the frame size. */
5025 if (!match_const_int (arg
, &frame_size
))
5027 num_frame_sizes
+= 1;
5031 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5034 while (regno1
<= regno2
)
5036 if (regno1
>= 4 && regno1
<= 7)
5038 if (num_frame_sizes
== 0)
5040 args
|= 1 << (regno1
- 4);
5042 /* statics $a0-$a3 */
5043 statics
|= 1 << (regno1
- 4);
5045 else if (regno1
>= 16 && regno1
<= 23)
5047 sregs
|= 1 << (regno1
- 16);
5048 else if (regno1
== 30)
5051 else if (regno1
== 31)
5052 /* Add $ra to insn. */
5062 while (match_char (arg
, ','));
5064 /* Encode args/statics combination. */
5067 else if (args
== 0xf)
5068 /* All $a0-$a3 are args. */
5069 opcode
|= MIPS16_ALL_ARGS
<< 16;
5070 else if (statics
== 0xf)
5071 /* All $a0-$a3 are statics. */
5072 opcode
|= MIPS16_ALL_STATICS
<< 16;
5075 /* Count arg registers. */
5085 /* Count static registers. */
5087 while (statics
& 0x8)
5089 statics
= (statics
<< 1) & 0xf;
5095 /* Encode args/statics. */
5096 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5099 /* Encode $s0/$s1. */
5100 if (sregs
& (1 << 0)) /* $s0 */
5102 if (sregs
& (1 << 1)) /* $s1 */
5106 /* Encode $s2-$s8. */
5115 opcode
|= num_sregs
<< 24;
5117 /* Encode frame size. */
5118 if (num_frame_sizes
== 0)
5120 set_insn_error (arg
->argnum
, _("missing frame size"));
5123 if (num_frame_sizes
> 1)
5125 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5128 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5130 set_insn_error (arg
->argnum
, _("invalid frame size"));
5133 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5136 opcode
|= (((frame_size
& 0xf0) << 16)
5137 | (frame_size
& 0x0f));
5140 /* Finally build the instruction. */
5141 if ((opcode
>> 16) != 0 || frame_size
== 0)
5142 opcode
|= MIPS16_EXTEND
;
5143 arg
->insn
->insn_opcode
= opcode
;
5147 /* OP_MDMX_IMM_REG matcher. */
5150 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5151 const struct mips_operand
*operand
)
5153 unsigned int regno
, uval
;
5155 const struct mips_opcode
*opcode
;
5157 /* The mips_opcode records whether this is an octobyte or quadhalf
5158 instruction. Start out with that bit in place. */
5159 opcode
= arg
->insn
->insn_mo
;
5160 uval
= mips_extract_operand (operand
, opcode
->match
);
5161 is_qh
= (uval
!= 0);
5163 if (arg
->token
->type
== OT_REG
)
5165 if ((opcode
->membership
& INSN_5400
)
5166 && strcmp (opcode
->name
, "rzu.ob") == 0)
5168 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5173 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5177 /* Check whether this is a vector register or a broadcast of
5178 a single element. */
5179 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5181 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5183 set_insn_error (arg
->argnum
, _("invalid element selector"));
5186 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5191 /* A full vector. */
5192 if ((opcode
->membership
& INSN_5400
)
5193 && (strcmp (opcode
->name
, "sll.ob") == 0
5194 || strcmp (opcode
->name
, "srl.ob") == 0))
5196 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5202 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5204 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5212 if (!match_const_int (arg
, &sval
))
5214 if (sval
< 0 || sval
> 31)
5216 match_out_of_range (arg
);
5219 uval
|= (sval
& 31);
5221 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5223 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5225 insn_insert_operand (arg
->insn
, operand
, uval
);
5229 /* OP_IMM_INDEX matcher. */
5232 match_imm_index_operand (struct mips_arg_info
*arg
,
5233 const struct mips_operand
*operand
)
5235 unsigned int max_val
;
5237 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5240 max_val
= (1 << operand
->size
) - 1;
5241 if (arg
->token
->u
.index
> max_val
)
5243 match_out_of_range (arg
);
5246 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5251 /* OP_REG_INDEX matcher. */
5254 match_reg_index_operand (struct mips_arg_info
*arg
,
5255 const struct mips_operand
*operand
)
5259 if (arg
->token
->type
!= OT_REG_INDEX
)
5262 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5265 insn_insert_operand (arg
->insn
, operand
, regno
);
5270 /* OP_PC matcher. */
5273 match_pc_operand (struct mips_arg_info
*arg
)
5275 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5283 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5284 register that we need to match. */
5287 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5291 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5294 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5295 the length of the value in bytes (4 for float, 8 for double) and
5296 USING_GPRS says whether the destination is a GPR rather than an FPR.
5298 Return the constant in IMM and OFFSET as follows:
5300 - If the constant should be loaded via memory, set IMM to O_absent and
5301 OFFSET to the memory address.
5303 - Otherwise, if the constant should be loaded into two 32-bit registers,
5304 set IMM to the O_constant to load into the high register and OFFSET
5305 to the corresponding value for the low register.
5307 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5309 These constants only appear as the last operand in an instruction,
5310 and every instruction that accepts them in any variant accepts them
5311 in all variants. This means we don't have to worry about backing out
5312 any changes if the instruction does not match. We just match
5313 unconditionally and report an error if the constant is invalid. */
5316 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5317 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5322 const char *newname
;
5323 unsigned char *data
;
5325 /* Where the constant is placed is based on how the MIPS assembler
5328 length == 4 && using_gprs -- immediate value only
5329 length == 8 && using_gprs -- .rdata or immediate value
5330 length == 4 && !using_gprs -- .lit4 or immediate value
5331 length == 8 && !using_gprs -- .lit8 or immediate value
5333 The .lit4 and .lit8 sections are only used if permitted by the
5335 if (arg
->token
->type
!= OT_FLOAT
)
5337 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5341 gas_assert (arg
->token
->u
.flt
.length
== length
);
5342 data
= arg
->token
->u
.flt
.data
;
5345 /* Handle 32-bit constants for which an immediate value is best. */
5348 || g_switch_value
< 4
5349 || (data
[0] == 0 && data
[1] == 0)
5350 || (data
[2] == 0 && data
[3] == 0)))
5352 imm
->X_op
= O_constant
;
5353 if (!target_big_endian
)
5354 imm
->X_add_number
= bfd_getl32 (data
);
5356 imm
->X_add_number
= bfd_getb32 (data
);
5357 offset
->X_op
= O_absent
;
5361 /* Handle 64-bit constants for which an immediate value is best. */
5363 && !mips_disable_float_construction
5364 /* Constants can only be constructed in GPRs and copied
5365 to FPRs if the GPRs are at least as wide as the FPRs.
5366 Force the constant into memory if we are using 64-bit FPRs
5367 but the GPRs are only 32 bits wide. */
5368 /* ??? No longer true with the addition of MTHC1, but this
5369 is legacy code... */
5370 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5371 && ((data
[0] == 0 && data
[1] == 0)
5372 || (data
[2] == 0 && data
[3] == 0))
5373 && ((data
[4] == 0 && data
[5] == 0)
5374 || (data
[6] == 0 && data
[7] == 0)))
5376 /* The value is simple enough to load with a couple of instructions.
5377 If using 32-bit registers, set IMM to the high order 32 bits and
5378 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5380 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5382 imm
->X_op
= O_constant
;
5383 offset
->X_op
= O_constant
;
5384 if (!target_big_endian
)
5386 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5387 offset
->X_add_number
= bfd_getl32 (data
);
5391 imm
->X_add_number
= bfd_getb32 (data
);
5392 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5394 if (offset
->X_add_number
== 0)
5395 offset
->X_op
= O_absent
;
5399 imm
->X_op
= O_constant
;
5400 if (!target_big_endian
)
5401 imm
->X_add_number
= bfd_getl64 (data
);
5403 imm
->X_add_number
= bfd_getb64 (data
);
5404 offset
->X_op
= O_absent
;
5409 /* Switch to the right section. */
5411 subseg
= now_subseg
;
5414 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5419 if (using_gprs
|| g_switch_value
< 8)
5420 newname
= RDATA_SECTION_NAME
;
5425 new_seg
= subseg_new (newname
, (subsegT
) 0);
5426 bfd_set_section_flags (stdoutput
, new_seg
,
5427 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5428 frag_align (length
== 4 ? 2 : 3, 0, 0);
5429 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5430 record_alignment (new_seg
, 4);
5432 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5434 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5436 /* Set the argument to the current address in the section. */
5437 imm
->X_op
= O_absent
;
5438 offset
->X_op
= O_symbol
;
5439 offset
->X_add_symbol
= symbol_temp_new_now ();
5440 offset
->X_add_number
= 0;
5442 /* Put the floating point number into the section. */
5443 p
= frag_more (length
);
5444 memcpy (p
, data
, length
);
5446 /* Switch back to the original section. */
5447 subseg_set (seg
, subseg
);
5451 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5455 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5456 const struct mips_operand
*operand
,
5457 bfd_boolean match_p
)
5461 /* The operand can be an XYZW mask or a single 2-bit channel index
5462 (with X being 0). */
5463 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5465 /* The suffix can be omitted when it is already part of the opcode. */
5466 if (arg
->token
->type
!= OT_CHANNELS
)
5469 uval
= arg
->token
->u
.channels
;
5470 if (operand
->size
== 2)
5472 /* Check that a single bit is set and convert it into a 2-bit index. */
5473 if ((uval
& -uval
) != uval
)
5475 uval
= 4 - ffs (uval
);
5478 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5483 insn_insert_operand (arg
->insn
, operand
, uval
);
5487 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5488 of the argument text if the match is successful, otherwise return null. */
5491 match_operand (struct mips_arg_info
*arg
,
5492 const struct mips_operand
*operand
)
5494 switch (operand
->type
)
5497 return match_int_operand (arg
, operand
);
5500 return match_mapped_int_operand (arg
, operand
);
5503 return match_msb_operand (arg
, operand
);
5506 case OP_OPTIONAL_REG
:
5507 return match_reg_operand (arg
, operand
);
5510 return match_reg_pair_operand (arg
, operand
);
5513 return match_pcrel_operand (arg
);
5516 return match_perf_reg_operand (arg
, operand
);
5518 case OP_ADDIUSP_INT
:
5519 return match_addiusp_operand (arg
, operand
);
5521 case OP_CLO_CLZ_DEST
:
5522 return match_clo_clz_dest_operand (arg
, operand
);
5524 case OP_LWM_SWM_LIST
:
5525 return match_lwm_swm_list_operand (arg
, operand
);
5527 case OP_ENTRY_EXIT_LIST
:
5528 return match_entry_exit_operand (arg
, operand
);
5530 case OP_SAVE_RESTORE_LIST
:
5531 return match_save_restore_list_operand (arg
);
5533 case OP_MDMX_IMM_REG
:
5534 return match_mdmx_imm_reg_operand (arg
, operand
);
5536 case OP_REPEAT_DEST_REG
:
5537 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5539 case OP_REPEAT_PREV_REG
:
5540 return match_tied_reg_operand (arg
, arg
->last_regno
);
5543 return match_pc_operand (arg
);
5546 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5548 case OP_VU0_MATCH_SUFFIX
:
5549 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5552 return match_imm_index_operand (arg
, operand
);
5555 return match_reg_index_operand (arg
, operand
);
5560 /* ARG is the state after successfully matching an instruction.
5561 Issue any queued-up warnings. */
5564 check_completed_insn (struct mips_arg_info
*arg
)
5569 as_warn (_("used $at without \".set noat\""));
5571 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
5575 /* Return true if modifying general-purpose register REG needs a delay. */
5578 reg_needs_delay (unsigned int reg
)
5580 unsigned long prev_pinfo
;
5582 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5583 if (!mips_opts
.noreorder
5584 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
5585 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5586 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5592 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5593 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5594 by VR4120 errata. */
5597 classify_vr4120_insn (const char *name
)
5599 if (strncmp (name
, "macc", 4) == 0)
5600 return FIX_VR4120_MACC
;
5601 if (strncmp (name
, "dmacc", 5) == 0)
5602 return FIX_VR4120_DMACC
;
5603 if (strncmp (name
, "mult", 4) == 0)
5604 return FIX_VR4120_MULT
;
5605 if (strncmp (name
, "dmult", 5) == 0)
5606 return FIX_VR4120_DMULT
;
5607 if (strstr (name
, "div"))
5608 return FIX_VR4120_DIV
;
5609 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5610 return FIX_VR4120_MTHILO
;
5611 return NUM_FIX_VR4120_CLASSES
;
5614 #define INSN_ERET 0x42000018
5615 #define INSN_DERET 0x4200001f
5616 #define INSN_DMULT 0x1c
5617 #define INSN_DMULTU 0x1d
5619 /* Return the number of instructions that must separate INSN1 and INSN2,
5620 where INSN1 is the earlier instruction. Return the worst-case value
5621 for any INSN2 if INSN2 is null. */
5624 insns_between (const struct mips_cl_insn
*insn1
,
5625 const struct mips_cl_insn
*insn2
)
5627 unsigned long pinfo1
, pinfo2
;
5630 /* If INFO2 is null, pessimistically assume that all flags are set for
5631 the second instruction. */
5632 pinfo1
= insn1
->insn_mo
->pinfo
;
5633 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5635 /* For most targets, write-after-read dependencies on the HI and LO
5636 registers must be separated by at least two instructions. */
5637 if (!hilo_interlocks
)
5639 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5641 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5645 /* If we're working around r7000 errata, there must be two instructions
5646 between an mfhi or mflo and any instruction that uses the result. */
5647 if (mips_7000_hilo_fix
5648 && !mips_opts
.micromips
5649 && MF_HILO_INSN (pinfo1
)
5650 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5653 /* If we're working around 24K errata, one instruction is required
5654 if an ERET or DERET is followed by a branch instruction. */
5655 if (mips_fix_24k
&& !mips_opts
.micromips
)
5657 if (insn1
->insn_opcode
== INSN_ERET
5658 || insn1
->insn_opcode
== INSN_DERET
)
5661 || insn2
->insn_opcode
== INSN_ERET
5662 || insn2
->insn_opcode
== INSN_DERET
5663 || delayed_branch_p (insn2
))
5668 /* If we're working around PMC RM7000 errata, there must be three
5669 nops between a dmult and a load instruction. */
5670 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
5672 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
5673 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
5675 if (pinfo2
& INSN_LOAD_MEMORY
)
5680 /* If working around VR4120 errata, check for combinations that need
5681 a single intervening instruction. */
5682 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5684 unsigned int class1
, class2
;
5686 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5687 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5691 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5692 if (vr4120_conflicts
[class1
] & (1 << class2
))
5697 if (!HAVE_CODE_COMPRESSION
)
5699 /* Check for GPR or coprocessor load delays. All such delays
5700 are on the RT register. */
5701 /* Itbl support may require additional care here. */
5702 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
5703 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5705 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5709 /* Check for generic coprocessor hazards.
5711 This case is not handled very well. There is no special
5712 knowledge of CP0 handling, and the coprocessors other than
5713 the floating point unit are not distinguished at all. */
5714 /* Itbl support may require additional care here. FIXME!
5715 Need to modify this to include knowledge about
5716 user specified delays! */
5717 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5718 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5720 /* Handle cases where INSN1 writes to a known general coprocessor
5721 register. There must be a one instruction delay before INSN2
5722 if INSN2 reads that register, otherwise no delay is needed. */
5723 mask
= fpr_write_mask (insn1
);
5726 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5731 /* Read-after-write dependencies on the control registers
5732 require a two-instruction gap. */
5733 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5734 && (pinfo2
& INSN_READ_COND_CODE
))
5737 /* We don't know exactly what INSN1 does. If INSN2 is
5738 also a coprocessor instruction, assume there must be
5739 a one instruction gap. */
5740 if (pinfo2
& INSN_COP
)
5745 /* Check for read-after-write dependencies on the coprocessor
5746 control registers in cases where INSN1 does not need a general
5747 coprocessor delay. This means that INSN1 is a floating point
5748 comparison instruction. */
5749 /* Itbl support may require additional care here. */
5750 else if (!cop_interlocks
5751 && (pinfo1
& INSN_WRITE_COND_CODE
)
5752 && (pinfo2
& INSN_READ_COND_CODE
))
5759 /* Return the number of nops that would be needed to work around the
5760 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5761 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5762 that are contained within the first IGNORE instructions of HIST. */
5765 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5766 const struct mips_cl_insn
*insn
)
5771 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5772 are not affected by the errata. */
5774 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5775 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5776 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5779 /* Search for the first MFLO or MFHI. */
5780 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5781 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5783 /* Extract the destination register. */
5784 mask
= gpr_write_mask (&hist
[i
]);
5786 /* No nops are needed if INSN reads that register. */
5787 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5790 /* ...or if any of the intervening instructions do. */
5791 for (j
= 0; j
< i
; j
++)
5792 if (gpr_read_mask (&hist
[j
]) & mask
)
5796 return MAX_VR4130_NOPS
- i
;
5801 #define BASE_REG_EQ(INSN1, INSN2) \
5802 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5803 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5805 /* Return the minimum alignment for this store instruction. */
5808 fix_24k_align_to (const struct mips_opcode
*mo
)
5810 if (strcmp (mo
->name
, "sh") == 0)
5813 if (strcmp (mo
->name
, "swc1") == 0
5814 || strcmp (mo
->name
, "swc2") == 0
5815 || strcmp (mo
->name
, "sw") == 0
5816 || strcmp (mo
->name
, "sc") == 0
5817 || strcmp (mo
->name
, "s.s") == 0)
5820 if (strcmp (mo
->name
, "sdc1") == 0
5821 || strcmp (mo
->name
, "sdc2") == 0
5822 || strcmp (mo
->name
, "s.d") == 0)
5829 struct fix_24k_store_info
5831 /* Immediate offset, if any, for this store instruction. */
5833 /* Alignment required by this store instruction. */
5835 /* True for register offsets. */
5836 int register_offset
;
5839 /* Comparison function used by qsort. */
5842 fix_24k_sort (const void *a
, const void *b
)
5844 const struct fix_24k_store_info
*pos1
= a
;
5845 const struct fix_24k_store_info
*pos2
= b
;
5847 return (pos1
->off
- pos2
->off
);
5850 /* INSN is a store instruction. Try to record the store information
5851 in STINFO. Return false if the information isn't known. */
5854 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5855 const struct mips_cl_insn
*insn
)
5857 /* The instruction must have a known offset. */
5858 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5861 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5862 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5866 /* Return the number of nops that would be needed to work around the 24k
5867 "lost data on stores during refill" errata if instruction INSN
5868 immediately followed the 2 instructions described by HIST.
5869 Ignore hazards that are contained within the first IGNORE
5870 instructions of HIST.
5872 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5873 for the data cache refills and store data. The following describes
5874 the scenario where the store data could be lost.
5876 * A data cache miss, due to either a load or a store, causing fill
5877 data to be supplied by the memory subsystem
5878 * The first three doublewords of fill data are returned and written
5880 * A sequence of four stores occurs in consecutive cycles around the
5881 final doubleword of the fill:
5885 * Zero, One or more instructions
5888 The four stores A-D must be to different doublewords of the line that
5889 is being filled. The fourth instruction in the sequence above permits
5890 the fill of the final doubleword to be transferred from the FSB into
5891 the cache. In the sequence above, the stores may be either integer
5892 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5893 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5894 different doublewords on the line. If the floating point unit is
5895 running in 1:2 mode, it is not possible to create the sequence above
5896 using only floating point store instructions.
5898 In this case, the cache line being filled is incorrectly marked
5899 invalid, thereby losing the data from any store to the line that
5900 occurs between the original miss and the completion of the five
5901 cycle sequence shown above.
5903 The workarounds are:
5905 * Run the data cache in write-through mode.
5906 * Insert a non-store instruction between
5907 Store A and Store B or Store B and Store C. */
5910 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5911 const struct mips_cl_insn
*insn
)
5913 struct fix_24k_store_info pos
[3];
5914 int align
, i
, base_offset
;
5919 /* If the previous instruction wasn't a store, there's nothing to
5921 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5924 /* If the instructions after the previous one are unknown, we have
5925 to assume the worst. */
5929 /* Check whether we are dealing with three consecutive stores. */
5930 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5931 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5934 /* If we don't know the relationship between the store addresses,
5935 assume the worst. */
5936 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5937 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5940 if (!fix_24k_record_store_info (&pos
[0], insn
)
5941 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5942 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5945 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5947 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5948 X bytes and such that the base register + X is known to be aligned
5951 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5955 align
= pos
[0].align_to
;
5956 base_offset
= pos
[0].off
;
5957 for (i
= 1; i
< 3; i
++)
5958 if (align
< pos
[i
].align_to
)
5960 align
= pos
[i
].align_to
;
5961 base_offset
= pos
[i
].off
;
5963 for (i
= 0; i
< 3; i
++)
5964 pos
[i
].off
-= base_offset
;
5967 pos
[0].off
&= ~align
+ 1;
5968 pos
[1].off
&= ~align
+ 1;
5969 pos
[2].off
&= ~align
+ 1;
5971 /* If any two stores write to the same chunk, they also write to the
5972 same doubleword. The offsets are still sorted at this point. */
5973 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5976 /* A range of at least 9 bytes is needed for the stores to be in
5977 non-overlapping doublewords. */
5978 if (pos
[2].off
- pos
[0].off
<= 8)
5981 if (pos
[2].off
- pos
[1].off
>= 24
5982 || pos
[1].off
- pos
[0].off
>= 24
5983 || pos
[2].off
- pos
[0].off
>= 32)
5989 /* Return the number of nops that would be needed if instruction INSN
5990 immediately followed the MAX_NOPS instructions given by HIST,
5991 where HIST[0] is the most recent instruction. Ignore hazards
5992 between INSN and the first IGNORE instructions in HIST.
5994 If INSN is null, return the worse-case number of nops for any
5998 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5999 const struct mips_cl_insn
*insn
)
6001 int i
, nops
, tmp_nops
;
6004 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6006 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6007 if (tmp_nops
> nops
)
6011 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6013 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6014 if (tmp_nops
> nops
)
6018 if (mips_fix_24k
&& !mips_opts
.micromips
)
6020 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6021 if (tmp_nops
> nops
)
6028 /* The variable arguments provide NUM_INSNS extra instructions that
6029 might be added to HIST. Return the largest number of nops that
6030 would be needed after the extended sequence, ignoring hazards
6031 in the first IGNORE instructions. */
6034 nops_for_sequence (int num_insns
, int ignore
,
6035 const struct mips_cl_insn
*hist
, ...)
6038 struct mips_cl_insn buffer
[MAX_NOPS
];
6039 struct mips_cl_insn
*cursor
;
6042 va_start (args
, hist
);
6043 cursor
= buffer
+ num_insns
;
6044 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6045 while (cursor
> buffer
)
6046 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6048 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6053 /* Like nops_for_insn, but if INSN is a branch, take into account the
6054 worst-case delay for the branch target. */
6057 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6058 const struct mips_cl_insn
*insn
)
6062 nops
= nops_for_insn (ignore
, hist
, insn
);
6063 if (delayed_branch_p (insn
))
6065 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6066 hist
, insn
, get_delay_slot_nop (insn
));
6067 if (tmp_nops
> nops
)
6070 else if (compact_branch_p (insn
))
6072 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6073 if (tmp_nops
> nops
)
6079 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6082 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6084 gas_assert (!HAVE_CODE_COMPRESSION
);
6085 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6086 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6089 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6090 jr target pc &= 'hffff_ffff_cfff_ffff. */
6093 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6095 gas_assert (!HAVE_CODE_COMPRESSION
);
6096 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6097 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6098 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6106 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6107 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6110 ep
.X_op
= O_constant
;
6111 ep
.X_add_number
= 0xcfff0000;
6112 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6113 ep
.X_add_number
= 0xffff;
6114 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6115 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6120 fix_loongson2f (struct mips_cl_insn
* ip
)
6122 if (mips_fix_loongson2f_nop
)
6123 fix_loongson2f_nop (ip
);
6125 if (mips_fix_loongson2f_jump
)
6126 fix_loongson2f_jump (ip
);
6129 /* IP is a branch that has a delay slot, and we need to fill it
6130 automatically. Return true if we can do that by swapping IP
6131 with the previous instruction.
6132 ADDRESS_EXPR is an operand of the instruction to be used with
6136 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6137 bfd_reloc_code_real_type
*reloc_type
)
6139 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6140 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6141 unsigned int fpr_read
, prev_fpr_write
;
6143 /* -O2 and above is required for this optimization. */
6144 if (mips_optimize
< 2)
6147 /* If we have seen .set volatile or .set nomove, don't optimize. */
6148 if (mips_opts
.nomove
)
6151 /* We can't swap if the previous instruction's position is fixed. */
6152 if (history
[0].fixed_p
)
6155 /* If the previous previous insn was in a .set noreorder, we can't
6156 swap. Actually, the MIPS assembler will swap in this situation.
6157 However, gcc configured -with-gnu-as will generate code like
6165 in which we can not swap the bne and INSN. If gcc is not configured
6166 -with-gnu-as, it does not output the .set pseudo-ops. */
6167 if (history
[1].noreorder_p
)
6170 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6171 This means that the previous instruction was a 4-byte one anyhow. */
6172 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6175 /* If the branch is itself the target of a branch, we can not swap.
6176 We cheat on this; all we check for is whether there is a label on
6177 this instruction. If there are any branches to anything other than
6178 a label, users must use .set noreorder. */
6179 if (seg_info (now_seg
)->label_list
)
6182 /* If the previous instruction is in a variant frag other than this
6183 branch's one, we cannot do the swap. This does not apply to
6184 MIPS16 code, which uses variant frags for different purposes. */
6185 if (!mips_opts
.mips16
6187 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6190 /* We do not swap with instructions that cannot architecturally
6191 be placed in a branch delay slot, such as SYNC or ERET. We
6192 also refrain from swapping with a trap instruction, since it
6193 complicates trap handlers to have the trap instruction be in
6195 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6196 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6199 /* Check for conflicts between the branch and the instructions
6200 before the candidate delay slot. */
6201 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6204 /* Check for conflicts between the swapped sequence and the
6205 target of the branch. */
6206 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6209 /* If the branch reads a register that the previous
6210 instruction sets, we can not swap. */
6211 gpr_read
= gpr_read_mask (ip
);
6212 prev_gpr_write
= gpr_write_mask (&history
[0]);
6213 if (gpr_read
& prev_gpr_write
)
6216 fpr_read
= fpr_read_mask (ip
);
6217 prev_fpr_write
= fpr_write_mask (&history
[0]);
6218 if (fpr_read
& prev_fpr_write
)
6221 /* If the branch writes a register that the previous
6222 instruction sets, we can not swap. */
6223 gpr_write
= gpr_write_mask (ip
);
6224 if (gpr_write
& prev_gpr_write
)
6227 /* If the branch writes a register that the previous
6228 instruction reads, we can not swap. */
6229 prev_gpr_read
= gpr_read_mask (&history
[0]);
6230 if (gpr_write
& prev_gpr_read
)
6233 /* If one instruction sets a condition code and the
6234 other one uses a condition code, we can not swap. */
6235 pinfo
= ip
->insn_mo
->pinfo
;
6236 if ((pinfo
& INSN_READ_COND_CODE
)
6237 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6239 if ((pinfo
& INSN_WRITE_COND_CODE
)
6240 && (prev_pinfo
& INSN_READ_COND_CODE
))
6243 /* If the previous instruction uses the PC, we can not swap. */
6244 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6245 if (prev_pinfo2
& INSN2_READ_PC
)
6248 /* If the previous instruction has an incorrect size for a fixed
6249 branch delay slot in microMIPS mode, we cannot swap. */
6250 pinfo2
= ip
->insn_mo
->pinfo2
;
6251 if (mips_opts
.micromips
6252 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6253 && insn_length (history
) != 2)
6255 if (mips_opts
.micromips
6256 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6257 && insn_length (history
) != 4)
6260 /* On R5900 short loops need to be fixed by inserting a nop in
6261 the branch delay slots.
6262 A short loop can be terminated too early. */
6263 if (mips_opts
.arch
== CPU_R5900
6264 /* Check if instruction has a parameter, ignore "j $31". */
6265 && (address_expr
!= NULL
)
6266 /* Parameter must be 16 bit. */
6267 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6268 /* Branch to same segment. */
6269 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6270 /* Branch to same code fragment. */
6271 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6272 /* Can only calculate branch offset if value is known. */
6273 && symbol_constant_p(address_expr
->X_add_symbol
)
6274 /* Check if branch is really conditional. */
6275 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6276 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6277 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6280 /* Check if loop is shorter than 6 instructions including
6281 branch and delay slot. */
6282 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6289 /* When the loop includes branches or jumps,
6290 it is not a short loop. */
6291 for (i
= 0; i
< (distance
/ 4); i
++)
6293 if ((history
[i
].cleared_p
)
6294 || delayed_branch_p(&history
[i
]))
6302 /* Insert nop after branch to fix short loop. */
6311 /* Decide how we should add IP to the instruction stream.
6312 ADDRESS_EXPR is an operand of the instruction to be used with
6315 static enum append_method
6316 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6317 bfd_reloc_code_real_type
*reloc_type
)
6319 /* The relaxed version of a macro sequence must be inherently
6321 if (mips_relax
.sequence
== 2)
6324 /* We must not dabble with instructions in a ".set norerorder" block. */
6325 if (mips_opts
.noreorder
)
6328 /* Otherwise, it's our responsibility to fill branch delay slots. */
6329 if (delayed_branch_p (ip
))
6331 if (!branch_likely_p (ip
)
6332 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6335 if (mips_opts
.mips16
6336 && ISA_SUPPORTS_MIPS16E
6337 && gpr_read_mask (ip
) != 0)
6338 return APPEND_ADD_COMPACT
;
6340 return APPEND_ADD_WITH_NOP
;
6346 /* IP is a MIPS16 instruction whose opcode we have just changed.
6347 Point IP->insn_mo to the new opcode's definition. */
6350 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6352 const struct mips_opcode
*mo
, *end
;
6354 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6355 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6356 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6364 /* For microMIPS macros, we need to generate a local number label
6365 as the target of branches. */
6366 #define MICROMIPS_LABEL_CHAR '\037'
6367 static unsigned long micromips_target_label
;
6368 static char micromips_target_name
[32];
6371 micromips_label_name (void)
6373 char *p
= micromips_target_name
;
6374 char symbol_name_temporary
[24];
6382 l
= micromips_target_label
;
6383 #ifdef LOCAL_LABEL_PREFIX
6384 *p
++ = LOCAL_LABEL_PREFIX
;
6387 *p
++ = MICROMIPS_LABEL_CHAR
;
6390 symbol_name_temporary
[i
++] = l
% 10 + '0';
6395 *p
++ = symbol_name_temporary
[--i
];
6398 return micromips_target_name
;
6402 micromips_label_expr (expressionS
*label_expr
)
6404 label_expr
->X_op
= O_symbol
;
6405 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6406 label_expr
->X_add_number
= 0;
6410 micromips_label_inc (void)
6412 micromips_target_label
++;
6413 *micromips_target_name
= '\0';
6417 micromips_add_label (void)
6421 s
= colon (micromips_label_name ());
6422 micromips_label_inc ();
6423 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6426 /* If assembling microMIPS code, then return the microMIPS reloc
6427 corresponding to the requested one if any. Otherwise return
6428 the reloc unchanged. */
6430 static bfd_reloc_code_real_type
6431 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6433 static const bfd_reloc_code_real_type relocs
[][2] =
6435 /* Keep sorted incrementally by the left-hand key. */
6436 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6437 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6438 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6439 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6440 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6441 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6442 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6443 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6444 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6445 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6446 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6447 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6448 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6449 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6450 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6451 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6452 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6453 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6454 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6455 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6456 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6457 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6458 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6459 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6460 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6461 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6462 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6464 bfd_reloc_code_real_type r
;
6467 if (!mips_opts
.micromips
)
6469 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6475 return relocs
[i
][1];
6480 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6481 Return true on success, storing the resolved value in RESULT. */
6484 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6489 case BFD_RELOC_MIPS_HIGHEST
:
6490 case BFD_RELOC_MICROMIPS_HIGHEST
:
6491 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6494 case BFD_RELOC_MIPS_HIGHER
:
6495 case BFD_RELOC_MICROMIPS_HIGHER
:
6496 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6499 case BFD_RELOC_HI16_S
:
6500 case BFD_RELOC_MICROMIPS_HI16_S
:
6501 case BFD_RELOC_MIPS16_HI16_S
:
6502 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6505 case BFD_RELOC_HI16
:
6506 case BFD_RELOC_MICROMIPS_HI16
:
6507 case BFD_RELOC_MIPS16_HI16
:
6508 *result
= (operand
>> 16) & 0xffff;
6511 case BFD_RELOC_LO16
:
6512 case BFD_RELOC_MICROMIPS_LO16
:
6513 case BFD_RELOC_MIPS16_LO16
:
6514 *result
= operand
& 0xffff;
6517 case BFD_RELOC_UNUSED
:
6526 /* Output an instruction. IP is the instruction information.
6527 ADDRESS_EXPR is an operand of the instruction to be used with
6528 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6529 a macro expansion. */
6532 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6533 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6535 unsigned long prev_pinfo2
, pinfo
;
6536 bfd_boolean relaxed_branch
= FALSE
;
6537 enum append_method method
;
6538 bfd_boolean relax32
;
6541 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6542 fix_loongson2f (ip
);
6544 file_ase_mips16
|= mips_opts
.mips16
;
6545 file_ase_micromips
|= mips_opts
.micromips
;
6547 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6548 pinfo
= ip
->insn_mo
->pinfo
;
6550 if (mips_opts
.micromips
6552 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6553 && micromips_insn_length (ip
->insn_mo
) != 2)
6554 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6555 && micromips_insn_length (ip
->insn_mo
) != 4)))
6556 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
6557 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6559 if (address_expr
== NULL
)
6561 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6562 && reloc_type
[1] == BFD_RELOC_UNUSED
6563 && reloc_type
[2] == BFD_RELOC_UNUSED
6564 && address_expr
->X_op
== O_constant
)
6566 switch (*reloc_type
)
6568 case BFD_RELOC_MIPS_JMP
:
6572 shift
= mips_opts
.micromips
? 1 : 2;
6573 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6574 as_bad (_("jump to misaligned address (0x%lx)"),
6575 (unsigned long) address_expr
->X_add_number
);
6576 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6582 case BFD_RELOC_MIPS16_JMP
:
6583 if ((address_expr
->X_add_number
& 3) != 0)
6584 as_bad (_("jump to misaligned address (0x%lx)"),
6585 (unsigned long) address_expr
->X_add_number
);
6587 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6588 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6589 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6593 case BFD_RELOC_16_PCREL_S2
:
6597 shift
= mips_opts
.micromips
? 1 : 2;
6598 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6599 as_bad (_("branch to misaligned address (0x%lx)"),
6600 (unsigned long) address_expr
->X_add_number
);
6601 if (!mips_relax_branch
)
6603 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6604 & ~((1 << (shift
+ 16)) - 1))
6605 as_bad (_("branch address range overflow (0x%lx)"),
6606 (unsigned long) address_expr
->X_add_number
);
6607 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6617 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6620 ip
->insn_opcode
|= value
& 0xffff;
6628 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6630 /* There are a lot of optimizations we could do that we don't.
6631 In particular, we do not, in general, reorder instructions.
6632 If you use gcc with optimization, it will reorder
6633 instructions and generally do much more optimization then we
6634 do here; repeating all that work in the assembler would only
6635 benefit hand written assembly code, and does not seem worth
6637 int nops
= (mips_optimize
== 0
6638 ? nops_for_insn (0, history
, NULL
)
6639 : nops_for_insn_or_target (0, history
, ip
));
6643 unsigned long old_frag_offset
;
6646 old_frag
= frag_now
;
6647 old_frag_offset
= frag_now_fix ();
6649 for (i
= 0; i
< nops
; i
++)
6650 add_fixed_insn (NOP_INSN
);
6651 insert_into_history (0, nops
, NOP_INSN
);
6655 listing_prev_line ();
6656 /* We may be at the start of a variant frag. In case we
6657 are, make sure there is enough space for the frag
6658 after the frags created by listing_prev_line. The
6659 argument to frag_grow here must be at least as large
6660 as the argument to all other calls to frag_grow in
6661 this file. We don't have to worry about being in the
6662 middle of a variant frag, because the variants insert
6663 all needed nop instructions themselves. */
6667 mips_move_text_labels ();
6669 #ifndef NO_ECOFF_DEBUGGING
6670 if (ECOFF_DEBUGGING
)
6671 ecoff_fix_loc (old_frag
, old_frag_offset
);
6675 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6679 /* Work out how many nops in prev_nop_frag are needed by IP,
6680 ignoring hazards generated by the first prev_nop_frag_since
6682 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6683 gas_assert (nops
<= prev_nop_frag_holds
);
6685 /* Enforce NOPS as a minimum. */
6686 if (nops
> prev_nop_frag_required
)
6687 prev_nop_frag_required
= nops
;
6689 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6691 /* Settle for the current number of nops. Update the history
6692 accordingly (for the benefit of any future .set reorder code). */
6693 prev_nop_frag
= NULL
;
6694 insert_into_history (prev_nop_frag_since
,
6695 prev_nop_frag_holds
, NOP_INSN
);
6699 /* Allow this instruction to replace one of the nops that was
6700 tentatively added to prev_nop_frag. */
6701 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6702 prev_nop_frag_holds
--;
6703 prev_nop_frag_since
++;
6707 method
= get_append_method (ip
, address_expr
, reloc_type
);
6708 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6710 dwarf2_emit_insn (0);
6711 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6712 so "move" the instruction address accordingly.
6714 Also, it doesn't seem appropriate for the assembler to reorder .loc
6715 entries. If this instruction is a branch that we are going to swap
6716 with the previous instruction, the two instructions should be
6717 treated as a unit, and the debug information for both instructions
6718 should refer to the start of the branch sequence. Using the
6719 current position is certainly wrong when swapping a 32-bit branch
6720 and a 16-bit delay slot, since the current position would then be
6721 in the middle of a branch. */
6722 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6724 relax32
= (mips_relax_branch
6725 /* Don't try branch relaxation within .set nomacro, or within
6726 .set noat if we use $at for PIC computations. If it turns
6727 out that the branch was out-of-range, we'll get an error. */
6728 && !mips_opts
.warn_about_macros
6729 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6730 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6731 as they have no complementing branches. */
6732 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6734 if (!HAVE_CODE_COMPRESSION
6737 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6738 && delayed_branch_p (ip
))
6740 relaxed_branch
= TRUE
;
6741 add_relaxed_insn (ip
, (relaxed_branch_length
6743 uncond_branch_p (ip
) ? -1
6744 : branch_likely_p (ip
) ? 1
6748 uncond_branch_p (ip
),
6749 branch_likely_p (ip
),
6750 pinfo
& INSN_WRITE_GPR_31
,
6752 address_expr
->X_add_symbol
,
6753 address_expr
->X_add_number
);
6754 *reloc_type
= BFD_RELOC_UNUSED
;
6756 else if (mips_opts
.micromips
6758 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6759 || *reloc_type
> BFD_RELOC_UNUSED
)
6760 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6761 /* Don't try branch relaxation when users specify
6762 16-bit/32-bit instructions. */
6763 && !forced_insn_length
)
6765 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6766 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6767 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6768 int compact
= compact_branch_p (ip
);
6769 int al
= pinfo
& INSN_WRITE_GPR_31
;
6772 gas_assert (address_expr
!= NULL
);
6773 gas_assert (!mips_relax
.sequence
);
6775 relaxed_branch
= TRUE
;
6776 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6777 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6778 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6780 address_expr
->X_add_symbol
,
6781 address_expr
->X_add_number
);
6782 *reloc_type
= BFD_RELOC_UNUSED
;
6784 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6786 /* We need to set up a variant frag. */
6787 gas_assert (address_expr
!= NULL
);
6788 add_relaxed_insn (ip
, 4, 0,
6790 (*reloc_type
- BFD_RELOC_UNUSED
,
6791 forced_insn_length
== 2, forced_insn_length
== 4,
6792 delayed_branch_p (&history
[0]),
6793 history
[0].mips16_absolute_jump_p
),
6794 make_expr_symbol (address_expr
), 0);
6796 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6798 if (!delayed_branch_p (ip
))
6799 /* Make sure there is enough room to swap this instruction with
6800 a following jump instruction. */
6802 add_fixed_insn (ip
);
6806 if (mips_opts
.mips16
6807 && mips_opts
.noreorder
6808 && delayed_branch_p (&history
[0]))
6809 as_warn (_("extended instruction in delay slot"));
6811 if (mips_relax
.sequence
)
6813 /* If we've reached the end of this frag, turn it into a variant
6814 frag and record the information for the instructions we've
6816 if (frag_room () < 4)
6817 relax_close_frag ();
6818 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6821 if (mips_relax
.sequence
!= 2)
6823 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6824 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6825 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6826 mips_macro_warning
.insns
[0]++;
6828 if (mips_relax
.sequence
!= 1)
6830 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6831 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6832 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6833 mips_macro_warning
.insns
[1]++;
6836 if (mips_opts
.mips16
)
6839 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6841 add_fixed_insn (ip
);
6844 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6846 bfd_reloc_code_real_type final_type
[3];
6847 reloc_howto_type
*howto0
;
6848 reloc_howto_type
*howto
;
6851 /* Perform any necessary conversion to microMIPS relocations
6852 and find out how many relocations there actually are. */
6853 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6854 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6856 /* In a compound relocation, it is the final (outermost)
6857 operator that determines the relocated field. */
6858 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6863 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6864 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6865 bfd_get_reloc_size (howto
),
6867 howto0
&& howto0
->pc_relative
,
6870 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6871 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6872 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6874 /* These relocations can have an addend that won't fit in
6875 4 octets for 64bit assembly. */
6877 && ! howto
->partial_inplace
6878 && (reloc_type
[0] == BFD_RELOC_16
6879 || reloc_type
[0] == BFD_RELOC_32
6880 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6881 || reloc_type
[0] == BFD_RELOC_GPREL16
6882 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6883 || reloc_type
[0] == BFD_RELOC_GPREL32
6884 || reloc_type
[0] == BFD_RELOC_64
6885 || reloc_type
[0] == BFD_RELOC_CTOR
6886 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6887 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6888 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6889 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6890 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6891 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6892 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6893 || hi16_reloc_p (reloc_type
[0])
6894 || lo16_reloc_p (reloc_type
[0])))
6895 ip
->fixp
[0]->fx_no_overflow
= 1;
6897 /* These relocations can have an addend that won't fit in 2 octets. */
6898 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6899 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6900 ip
->fixp
[0]->fx_no_overflow
= 1;
6902 if (mips_relax
.sequence
)
6904 if (mips_relax
.first_fixup
== 0)
6905 mips_relax
.first_fixup
= ip
->fixp
[0];
6907 else if (reloc_needs_lo_p (*reloc_type
))
6909 struct mips_hi_fixup
*hi_fixup
;
6911 /* Reuse the last entry if it already has a matching %lo. */
6912 hi_fixup
= mips_hi_fixup_list
;
6914 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6916 hi_fixup
= ((struct mips_hi_fixup
*)
6917 xmalloc (sizeof (struct mips_hi_fixup
)));
6918 hi_fixup
->next
= mips_hi_fixup_list
;
6919 mips_hi_fixup_list
= hi_fixup
;
6921 hi_fixup
->fixp
= ip
->fixp
[0];
6922 hi_fixup
->seg
= now_seg
;
6925 /* Add fixups for the second and third relocations, if given.
6926 Note that the ABI allows the second relocation to be
6927 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6928 moment we only use RSS_UNDEF, but we could add support
6929 for the others if it ever becomes necessary. */
6930 for (i
= 1; i
< 3; i
++)
6931 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6933 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6934 ip
->fixp
[0]->fx_size
, NULL
, 0,
6935 FALSE
, final_type
[i
]);
6937 /* Use fx_tcbit to mark compound relocs. */
6938 ip
->fixp
[0]->fx_tcbit
= 1;
6939 ip
->fixp
[i
]->fx_tcbit
= 1;
6944 /* Update the register mask information. */
6945 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6946 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6951 insert_into_history (0, 1, ip
);
6954 case APPEND_ADD_WITH_NOP
:
6956 struct mips_cl_insn
*nop
;
6958 insert_into_history (0, 1, ip
);
6959 nop
= get_delay_slot_nop (ip
);
6960 add_fixed_insn (nop
);
6961 insert_into_history (0, 1, nop
);
6962 if (mips_relax
.sequence
)
6963 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6967 case APPEND_ADD_COMPACT
:
6968 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6969 gas_assert (mips_opts
.mips16
);
6970 ip
->insn_opcode
|= 0x0080;
6971 find_altered_mips16_opcode (ip
);
6973 insert_into_history (0, 1, ip
);
6978 struct mips_cl_insn delay
= history
[0];
6979 if (mips_opts
.mips16
)
6981 know (delay
.frag
== ip
->frag
);
6982 move_insn (ip
, delay
.frag
, delay
.where
);
6983 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6985 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6987 /* Add the delay slot instruction to the end of the
6988 current frag and shrink the fixed part of the
6989 original frag. If the branch occupies the tail of
6990 the latter, move it backwards to cover the gap. */
6991 delay
.frag
->fr_fix
-= branch_disp
;
6992 if (delay
.frag
== ip
->frag
)
6993 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6994 add_fixed_insn (&delay
);
6998 move_insn (&delay
, ip
->frag
,
6999 ip
->where
- branch_disp
+ insn_length (ip
));
7000 move_insn (ip
, history
[0].frag
, history
[0].where
);
7004 insert_into_history (0, 1, &delay
);
7009 /* If we have just completed an unconditional branch, clear the history. */
7010 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7011 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7015 mips_no_prev_insn ();
7017 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7018 history
[i
].cleared_p
= 1;
7021 /* We need to emit a label at the end of branch-likely macros. */
7022 if (emit_branch_likely_macro
)
7024 emit_branch_likely_macro
= FALSE
;
7025 micromips_add_label ();
7028 /* We just output an insn, so the next one doesn't have a label. */
7029 mips_clear_insn_labels ();
7032 /* Forget that there was any previous instruction or label.
7033 When BRANCH is true, the branch history is also flushed. */
7036 mips_no_prev_insn (void)
7038 prev_nop_frag
= NULL
;
7039 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7040 mips_clear_insn_labels ();
7043 /* This function must be called before we emit something other than
7044 instructions. It is like mips_no_prev_insn except that it inserts
7045 any NOPS that might be needed by previous instructions. */
7048 mips_emit_delays (void)
7050 if (! mips_opts
.noreorder
)
7052 int nops
= nops_for_insn (0, history
, NULL
);
7056 add_fixed_insn (NOP_INSN
);
7057 mips_move_text_labels ();
7060 mips_no_prev_insn ();
7063 /* Start a (possibly nested) noreorder block. */
7066 start_noreorder (void)
7068 if (mips_opts
.noreorder
== 0)
7073 /* None of the instructions before the .set noreorder can be moved. */
7074 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7075 history
[i
].fixed_p
= 1;
7077 /* Insert any nops that might be needed between the .set noreorder
7078 block and the previous instructions. We will later remove any
7079 nops that turn out not to be needed. */
7080 nops
= nops_for_insn (0, history
, NULL
);
7083 if (mips_optimize
!= 0)
7085 /* Record the frag which holds the nop instructions, so
7086 that we can remove them if we don't need them. */
7087 frag_grow (nops
* NOP_INSN_SIZE
);
7088 prev_nop_frag
= frag_now
;
7089 prev_nop_frag_holds
= nops
;
7090 prev_nop_frag_required
= 0;
7091 prev_nop_frag_since
= 0;
7094 for (; nops
> 0; --nops
)
7095 add_fixed_insn (NOP_INSN
);
7097 /* Move on to a new frag, so that it is safe to simply
7098 decrease the size of prev_nop_frag. */
7099 frag_wane (frag_now
);
7101 mips_move_text_labels ();
7103 mips_mark_labels ();
7104 mips_clear_insn_labels ();
7106 mips_opts
.noreorder
++;
7107 mips_any_noreorder
= 1;
7110 /* End a nested noreorder block. */
7113 end_noreorder (void)
7115 mips_opts
.noreorder
--;
7116 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7118 /* Commit to inserting prev_nop_frag_required nops and go back to
7119 handling nop insertion the .set reorder way. */
7120 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7122 insert_into_history (prev_nop_frag_since
,
7123 prev_nop_frag_required
, NOP_INSN
);
7124 prev_nop_frag
= NULL
;
7128 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7129 higher bits unset. */
7132 normalize_constant_expr (expressionS
*ex
)
7134 if (ex
->X_op
== O_constant
7135 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7136 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7140 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7141 all higher bits unset. */
7144 normalize_address_expr (expressionS
*ex
)
7146 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7147 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7148 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7149 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7153 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7154 Return true if the match was successful.
7156 OPCODE_EXTRA is a value that should be ORed into the opcode
7157 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7158 there are more alternatives after OPCODE and SOFT_MATCH is
7159 as for mips_arg_info. */
7162 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7163 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7164 bfd_boolean lax_match
, bfd_boolean complete_p
)
7167 struct mips_arg_info arg
;
7168 const struct mips_operand
*operand
;
7171 imm_expr
.X_op
= O_absent
;
7172 offset_expr
.X_op
= O_absent
;
7173 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7174 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7175 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7177 create_insn (insn
, opcode
);
7178 /* When no opcode suffix is specified, assume ".xyzw". */
7179 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7180 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7182 insn
->insn_opcode
|= opcode_extra
;
7183 memset (&arg
, 0, sizeof (arg
));
7187 arg
.last_regno
= ILLEGAL_REG
;
7188 arg
.dest_regno
= ILLEGAL_REG
;
7189 arg
.lax_match
= lax_match
;
7190 for (args
= opcode
->args
;; ++args
)
7192 if (arg
.token
->type
== OT_END
)
7194 /* Handle unary instructions in which only one operand is given.
7195 The source is then the same as the destination. */
7196 if (arg
.opnum
== 1 && *args
== ',')
7198 operand
= (mips_opts
.micromips
7199 ? decode_micromips_operand (args
+ 1)
7200 : decode_mips_operand (args
+ 1));
7201 if (operand
&& mips_optional_operand_p (operand
))
7209 /* Treat elided base registers as $0. */
7210 if (strcmp (args
, "(b)") == 0)
7218 /* The register suffix is optional. */
7223 /* Fail the match if there were too few operands. */
7227 /* Successful match. */
7230 clear_insn_error ();
7231 if (arg
.dest_regno
== arg
.last_regno
7232 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7236 (0, _("source and destination must be different"));
7237 else if (arg
.last_regno
== 31)
7239 (0, _("a destination register must be supplied"));
7241 else if (arg
.last_regno
== 31
7242 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7243 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7244 set_insn_error (0, _("the source register must not be $31"));
7245 check_completed_insn (&arg
);
7249 /* Fail the match if the line has too many operands. */
7253 /* Handle characters that need to match exactly. */
7254 if (*args
== '(' || *args
== ')' || *args
== ',')
7256 if (match_char (&arg
, *args
))
7263 if (arg
.token
->type
== OT_DOUBLE_CHAR
7264 && arg
.token
->u
.ch
== *args
)
7272 /* Handle special macro operands. Work out the properties of
7281 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7287 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7289 imm_expr
.X_op
= O_constant
;
7290 if (HAVE_32BIT_GPRS
)
7291 normalize_constant_expr (&imm_expr
);
7295 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7297 /* Assume that the offset has been elided and that what
7298 we saw was a base register. The match will fail later
7299 if that assumption turns out to be wrong. */
7300 offset_expr
.X_op
= O_constant
;
7301 offset_expr
.X_add_number
= 0;
7305 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7307 normalize_address_expr (&offset_expr
);
7312 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7318 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7324 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7330 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7336 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7340 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7344 gas_assert (mips_opts
.micromips
);
7350 if (!forced_insn_length
)
7351 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7353 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7355 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7361 operand
= (mips_opts
.micromips
7362 ? decode_micromips_operand (args
)
7363 : decode_mips_operand (args
));
7367 /* Skip prefixes. */
7368 if (*args
== '+' || *args
== 'm')
7371 if (mips_optional_operand_p (operand
)
7373 && (arg
.token
[0].type
!= OT_REG
7374 || arg
.token
[1].type
== OT_END
))
7376 /* Assume that the register has been elided and is the
7377 same as the first operand. */
7382 if (!match_operand (&arg
, operand
))
7387 /* Like match_insn, but for MIPS16. */
7390 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7391 struct mips_operand_token
*tokens
)
7394 const struct mips_operand
*operand
;
7395 const struct mips_operand
*ext_operand
;
7396 struct mips_arg_info arg
;
7399 create_insn (insn
, opcode
);
7400 imm_expr
.X_op
= O_absent
;
7401 offset_expr
.X_op
= O_absent
;
7402 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7403 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7404 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7407 memset (&arg
, 0, sizeof (arg
));
7411 arg
.last_regno
= ILLEGAL_REG
;
7412 arg
.dest_regno
= ILLEGAL_REG
;
7414 for (args
= opcode
->args
;; ++args
)
7418 if (arg
.token
->type
== OT_END
)
7422 /* Handle unary instructions in which only one operand is given.
7423 The source is then the same as the destination. */
7424 if (arg
.opnum
== 1 && *args
== ',')
7426 operand
= decode_mips16_operand (args
[1], FALSE
);
7427 if (operand
&& mips_optional_operand_p (operand
))
7435 /* Fail the match if there were too few operands. */
7439 /* Successful match. Stuff the immediate value in now, if
7441 clear_insn_error ();
7442 if (opcode
->pinfo
== INSN_MACRO
)
7444 gas_assert (relax_char
== 0 || relax_char
== 'p');
7445 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7448 && offset_expr
.X_op
== O_constant
7449 && calculate_reloc (*offset_reloc
,
7450 offset_expr
.X_add_number
,
7453 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7454 forced_insn_length
, &insn
->insn_opcode
);
7455 offset_expr
.X_op
= O_absent
;
7456 *offset_reloc
= BFD_RELOC_UNUSED
;
7458 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7460 if (forced_insn_length
== 2)
7461 set_insn_error (0, _("invalid unextended operand value"));
7462 forced_insn_length
= 4;
7463 insn
->insn_opcode
|= MIPS16_EXTEND
;
7465 else if (relax_char
)
7466 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7468 check_completed_insn (&arg
);
7472 /* Fail the match if the line has too many operands. */
7476 /* Handle characters that need to match exactly. */
7477 if (*args
== '(' || *args
== ')' || *args
== ',')
7479 if (match_char (&arg
, *args
))
7497 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7499 imm_expr
.X_op
= O_constant
;
7500 if (HAVE_32BIT_GPRS
)
7501 normalize_constant_expr (&imm_expr
);
7506 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7507 insn
->insn_opcode
<<= 16;
7511 operand
= decode_mips16_operand (c
, FALSE
);
7515 /* '6' is a special case. It is used for BREAK and SDBBP,
7516 whose operands are only meaningful to the software that decodes
7517 them. This means that there is no architectural reason why
7518 they cannot be prefixed by EXTEND, but in practice,
7519 exception handlers will only look at the instruction
7520 itself. We therefore allow '6' to be extended when
7521 disassembling but not when assembling. */
7522 if (operand
->type
!= OP_PCREL
&& c
!= '6')
7524 ext_operand
= decode_mips16_operand (c
, TRUE
);
7525 if (operand
!= ext_operand
)
7527 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7529 offset_expr
.X_op
= O_constant
;
7530 offset_expr
.X_add_number
= 0;
7535 /* We need the OT_INTEGER check because some MIPS16
7536 immediate variants are listed before the register ones. */
7537 if (arg
.token
->type
!= OT_INTEGER
7538 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
7541 /* '8' is used for SLTI(U) and has traditionally not
7542 been allowed to take relocation operators. */
7543 if (offset_reloc
[0] != BFD_RELOC_UNUSED
7544 && (ext_operand
->size
!= 16 || c
== '8'))
7552 if (mips_optional_operand_p (operand
)
7554 && (arg
.token
[0].type
!= OT_REG
7555 || arg
.token
[1].type
== OT_END
))
7557 /* Assume that the register has been elided and is the
7558 same as the first operand. */
7563 if (!match_operand (&arg
, operand
))
7568 /* Record that the current instruction is invalid for the current ISA. */
7571 match_invalid_for_isa (void)
7574 (0, _("opcode not supported on this processor: %s (%s)"),
7575 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7576 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7579 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
7580 Return true if a definite match or failure was found, storing any match
7581 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
7582 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
7583 tried and failed to match under normal conditions and now want to try a
7584 more relaxed match. */
7587 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7588 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
7589 int opcode_extra
, bfd_boolean lax_match
)
7591 const struct mips_opcode
*opcode
;
7592 const struct mips_opcode
*invalid_delay_slot
;
7593 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
7595 /* Search for a match, ignoring alternatives that don't satisfy the
7596 current ISA or forced_length. */
7597 invalid_delay_slot
= 0;
7598 seen_valid_for_isa
= FALSE
;
7599 seen_valid_for_size
= FALSE
;
7603 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7604 if (is_opcode_valid (opcode
))
7606 seen_valid_for_isa
= TRUE
;
7607 if (is_size_valid (opcode
))
7609 bfd_boolean delay_slot_ok
;
7611 seen_valid_for_size
= TRUE
;
7612 delay_slot_ok
= is_delay_slot_valid (opcode
);
7613 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
7614 lax_match
, delay_slot_ok
))
7618 if (!invalid_delay_slot
)
7619 invalid_delay_slot
= opcode
;
7628 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
7630 /* If the only matches we found had the wrong length for the delay slot,
7631 pick the first such match. We'll issue an appropriate warning later. */
7632 if (invalid_delay_slot
)
7634 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
7640 /* Handle the case where we didn't try to match an instruction because
7641 all the alternatives were incompatible with the current ISA. */
7642 if (!seen_valid_for_isa
)
7644 match_invalid_for_isa ();
7648 /* Handle the case where we didn't try to match an instruction because
7649 all the alternatives were of the wrong size. */
7650 if (!seen_valid_for_size
)
7652 if (mips_opts
.insn32
)
7653 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
7656 (0, _("unrecognized %d-bit version of microMIPS opcode"),
7657 8 * forced_insn_length
);
7664 /* Like match_insns, but for MIPS16. */
7667 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7668 struct mips_operand_token
*tokens
)
7670 const struct mips_opcode
*opcode
;
7671 bfd_boolean seen_valid_for_isa
;
7673 /* Search for a match, ignoring alternatives that don't satisfy the
7674 current ISA. There are no separate entries for extended forms so
7675 we deal with forced_length later. */
7676 seen_valid_for_isa
= FALSE
;
7680 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7681 if (is_opcode_valid_16 (opcode
))
7683 seen_valid_for_isa
= TRUE
;
7684 if (match_mips16_insn (insn
, opcode
, tokens
))
7689 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
7690 && strcmp (opcode
->name
, first
->name
) == 0);
7692 /* Handle the case where we didn't try to match an instruction because
7693 all the alternatives were incompatible with the current ISA. */
7694 if (!seen_valid_for_isa
)
7696 match_invalid_for_isa ();
7703 /* Set up global variables for the start of a new macro. */
7708 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
7709 memset (&mips_macro_warning
.first_insn_sizes
, 0,
7710 sizeof (mips_macro_warning
.first_insn_sizes
));
7711 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
7712 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
7713 && delayed_branch_p (&history
[0]));
7714 switch (history
[0].insn_mo
->pinfo2
7715 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
7717 case INSN2_BRANCH_DELAY_32BIT
:
7718 mips_macro_warning
.delay_slot_length
= 4;
7720 case INSN2_BRANCH_DELAY_16BIT
:
7721 mips_macro_warning
.delay_slot_length
= 2;
7724 mips_macro_warning
.delay_slot_length
= 0;
7727 mips_macro_warning
.first_frag
= NULL
;
7730 /* Given that a macro is longer than one instruction or of the wrong size,
7731 return the appropriate warning for it. Return null if no warning is
7732 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7733 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7734 and RELAX_NOMACRO. */
7737 macro_warning (relax_substateT subtype
)
7739 if (subtype
& RELAX_DELAY_SLOT
)
7740 return _("macro instruction expanded into multiple instructions"
7741 " in a branch delay slot");
7742 else if (subtype
& RELAX_NOMACRO
)
7743 return _("macro instruction expanded into multiple instructions");
7744 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
7745 | RELAX_DELAY_SLOT_SIZE_SECOND
))
7746 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
7747 ? _("macro instruction expanded into a wrong size instruction"
7748 " in a 16-bit branch delay slot")
7749 : _("macro instruction expanded into a wrong size instruction"
7750 " in a 32-bit branch delay slot"));
7755 /* Finish up a macro. Emit warnings as appropriate. */
7760 /* Relaxation warning flags. */
7761 relax_substateT subtype
= 0;
7763 /* Check delay slot size requirements. */
7764 if (mips_macro_warning
.delay_slot_length
== 2)
7765 subtype
|= RELAX_DELAY_SLOT_16BIT
;
7766 if (mips_macro_warning
.delay_slot_length
!= 0)
7768 if (mips_macro_warning
.delay_slot_length
7769 != mips_macro_warning
.first_insn_sizes
[0])
7770 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
7771 if (mips_macro_warning
.delay_slot_length
7772 != mips_macro_warning
.first_insn_sizes
[1])
7773 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
7776 /* Check instruction count requirements. */
7777 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
7779 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
7780 subtype
|= RELAX_SECOND_LONGER
;
7781 if (mips_opts
.warn_about_macros
)
7782 subtype
|= RELAX_NOMACRO
;
7783 if (mips_macro_warning
.delay_slot_p
)
7784 subtype
|= RELAX_DELAY_SLOT
;
7787 /* If both alternatives fail to fill a delay slot correctly,
7788 emit the warning now. */
7789 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
7790 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
7795 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
7796 | RELAX_DELAY_SLOT_SIZE_FIRST
7797 | RELAX_DELAY_SLOT_SIZE_SECOND
);
7798 msg
= macro_warning (s
);
7800 as_warn ("%s", msg
);
7804 /* If both implementations are longer than 1 instruction, then emit the
7806 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
7811 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
7812 msg
= macro_warning (s
);
7814 as_warn ("%s", msg
);
7818 /* If any flags still set, then one implementation might need a warning
7819 and the other either will need one of a different kind or none at all.
7820 Pass any remaining flags over to relaxation. */
7821 if (mips_macro_warning
.first_frag
!= NULL
)
7822 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7825 /* Instruction operand formats used in macros that vary between
7826 standard MIPS and microMIPS code. */
7828 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7829 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7830 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7831 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7832 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7833 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7834 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7835 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7837 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7838 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7839 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7840 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7841 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7842 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7843 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7844 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7846 /* Read a macro's relocation codes from *ARGS and store them in *R.
7847 The first argument in *ARGS will be either the code for a single
7848 relocation or -1 followed by the three codes that make up a
7849 composite relocation. */
7852 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7856 next
= va_arg (*args
, int);
7858 r
[0] = (bfd_reloc_code_real_type
) next
;
7861 for (i
= 0; i
< 3; i
++)
7862 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7863 /* This function is only used for 16-bit relocation fields.
7864 To make the macro code simpler, treat an unrelocated value
7865 in the same way as BFD_RELOC_LO16. */
7866 if (r
[0] == BFD_RELOC_UNUSED
)
7867 r
[0] = BFD_RELOC_LO16
;
7871 /* Build an instruction created by a macro expansion. This is passed
7872 a pointer to the count of instructions created so far, an
7873 expression, the name of the instruction to build, an operand format
7874 string, and corresponding arguments. */
7877 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7879 const struct mips_opcode
*mo
= NULL
;
7880 bfd_reloc_code_real_type r
[3];
7881 const struct mips_opcode
*amo
;
7882 const struct mips_operand
*operand
;
7883 struct hash_control
*hash
;
7884 struct mips_cl_insn insn
;
7888 va_start (args
, fmt
);
7890 if (mips_opts
.mips16
)
7892 mips16_macro_build (ep
, name
, fmt
, &args
);
7897 r
[0] = BFD_RELOC_UNUSED
;
7898 r
[1] = BFD_RELOC_UNUSED
;
7899 r
[2] = BFD_RELOC_UNUSED
;
7900 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7901 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7903 gas_assert (strcmp (name
, amo
->name
) == 0);
7907 /* Search until we get a match for NAME. It is assumed here that
7908 macros will never generate MDMX, MIPS-3D, or MT instructions.
7909 We try to match an instruction that fulfils the branch delay
7910 slot instruction length requirement (if any) of the previous
7911 instruction. While doing this we record the first instruction
7912 seen that matches all the other conditions and use it anyway
7913 if the requirement cannot be met; we will issue an appropriate
7914 warning later on. */
7915 if (strcmp (fmt
, amo
->args
) == 0
7916 && amo
->pinfo
!= INSN_MACRO
7917 && is_opcode_valid (amo
)
7918 && is_size_valid (amo
))
7920 if (is_delay_slot_valid (amo
))
7930 gas_assert (amo
->name
);
7932 while (strcmp (name
, amo
->name
) == 0);
7935 create_insn (&insn
, mo
);
7948 macro_read_relocs (&args
, r
);
7949 gas_assert (*r
== BFD_RELOC_GPREL16
7950 || *r
== BFD_RELOC_MIPS_HIGHER
7951 || *r
== BFD_RELOC_HI16_S
7952 || *r
== BFD_RELOC_LO16
7953 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7957 macro_read_relocs (&args
, r
);
7961 macro_read_relocs (&args
, r
);
7962 gas_assert (ep
!= NULL
7963 && (ep
->X_op
== O_constant
7964 || (ep
->X_op
== O_symbol
7965 && (*r
== BFD_RELOC_MIPS_HIGHEST
7966 || *r
== BFD_RELOC_HI16_S
7967 || *r
== BFD_RELOC_HI16
7968 || *r
== BFD_RELOC_GPREL16
7969 || *r
== BFD_RELOC_MIPS_GOT_HI16
7970 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7974 gas_assert (ep
!= NULL
);
7977 * This allows macro() to pass an immediate expression for
7978 * creating short branches without creating a symbol.
7980 * We don't allow branch relaxation for these branches, as
7981 * they should only appear in ".set nomacro" anyway.
7983 if (ep
->X_op
== O_constant
)
7985 /* For microMIPS we always use relocations for branches.
7986 So we should not resolve immediate values. */
7987 gas_assert (!mips_opts
.micromips
);
7989 if ((ep
->X_add_number
& 3) != 0)
7990 as_bad (_("branch to misaligned address (0x%lx)"),
7991 (unsigned long) ep
->X_add_number
);
7992 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7993 as_bad (_("branch address range overflow (0x%lx)"),
7994 (unsigned long) ep
->X_add_number
);
7995 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
7999 *r
= BFD_RELOC_16_PCREL_S2
;
8003 gas_assert (ep
!= NULL
);
8004 *r
= BFD_RELOC_MIPS_JMP
;
8008 operand
= (mips_opts
.micromips
8009 ? decode_micromips_operand (fmt
)
8010 : decode_mips_operand (fmt
));
8014 uval
= va_arg (args
, int);
8015 if (operand
->type
== OP_CLO_CLZ_DEST
)
8016 uval
|= (uval
<< 5);
8017 insn_insert_operand (&insn
, operand
, uval
);
8019 if (*fmt
== '+' || *fmt
== 'm')
8025 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8027 append_insn (&insn
, ep
, r
, TRUE
);
8031 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8034 struct mips_opcode
*mo
;
8035 struct mips_cl_insn insn
;
8036 const struct mips_operand
*operand
;
8037 bfd_reloc_code_real_type r
[3]
8038 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8040 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8042 gas_assert (strcmp (name
, mo
->name
) == 0);
8044 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8047 gas_assert (mo
->name
);
8048 gas_assert (strcmp (name
, mo
->name
) == 0);
8051 create_insn (&insn
, mo
);
8089 gas_assert (ep
!= NULL
);
8091 if (ep
->X_op
!= O_constant
)
8092 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8093 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8095 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8097 *r
= BFD_RELOC_UNUSED
;
8103 operand
= decode_mips16_operand (c
, FALSE
);
8107 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8112 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8114 append_insn (&insn
, ep
, r
, TRUE
);
8118 * Generate a "jalr" instruction with a relocation hint to the called
8119 * function. This occurs in NewABI PIC code.
8122 macro_build_jalr (expressionS
*ep
, int cprestore
)
8124 static const bfd_reloc_code_real_type jalr_relocs
[2]
8125 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8126 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8130 if (MIPS_JALR_HINT_P (ep
))
8135 if (mips_opts
.micromips
)
8137 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8138 ? "jalr" : "jalrs");
8139 if (MIPS_JALR_HINT_P (ep
)
8141 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8142 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8144 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8147 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8148 if (MIPS_JALR_HINT_P (ep
))
8149 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8153 * Generate a "lui" instruction.
8156 macro_build_lui (expressionS
*ep
, int regnum
)
8158 gas_assert (! mips_opts
.mips16
);
8160 if (ep
->X_op
!= O_constant
)
8162 gas_assert (ep
->X_op
== O_symbol
);
8163 /* _gp_disp is a special case, used from s_cpload.
8164 __gnu_local_gp is used if mips_no_shared. */
8165 gas_assert (mips_pic
== NO_PIC
8167 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8168 || (! mips_in_shared
8169 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8170 "__gnu_local_gp") == 0));
8173 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8176 /* Generate a sequence of instructions to do a load or store from a constant
8177 offset off of a base register (breg) into/from a target register (treg),
8178 using AT if necessary. */
8180 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8181 int treg
, int breg
, int dbl
)
8183 gas_assert (ep
->X_op
== O_constant
);
8185 /* Sign-extending 32-bit constants makes their handling easier. */
8187 normalize_constant_expr (ep
);
8189 /* Right now, this routine can only handle signed 32-bit constants. */
8190 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8191 as_warn (_("operand overflow"));
8193 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8195 /* Signed 16-bit offset will fit in the op. Easy! */
8196 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8200 /* 32-bit offset, need multiple instructions and AT, like:
8201 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8202 addu $tempreg,$tempreg,$breg
8203 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8204 to handle the complete offset. */
8205 macro_build_lui (ep
, AT
);
8206 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8207 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8210 as_bad (_("macro used $at after \".set noat\""));
8215 * Generates code to set the $at register to true (one)
8216 * if reg is less than the immediate expression.
8219 set_at (int reg
, int unsignedp
)
8221 if (imm_expr
.X_add_number
>= -0x8000
8222 && imm_expr
.X_add_number
< 0x8000)
8223 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8224 AT
, reg
, BFD_RELOC_LO16
);
8227 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8228 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8232 /* Count the leading zeroes by performing a binary chop. This is a
8233 bulky bit of source, but performance is a LOT better for the
8234 majority of values than a simple loop to count the bits:
8235 for (lcnt = 0; (lcnt < 32); lcnt++)
8236 if ((v) & (1 << (31 - lcnt)))
8238 However it is not code size friendly, and the gain will drop a bit
8239 on certain cached systems.
8241 #define COUNT_TOP_ZEROES(v) \
8242 (((v) & ~0xffff) == 0 \
8243 ? ((v) & ~0xff) == 0 \
8244 ? ((v) & ~0xf) == 0 \
8245 ? ((v) & ~0x3) == 0 \
8246 ? ((v) & ~0x1) == 0 \
8251 : ((v) & ~0x7) == 0 \
8254 : ((v) & ~0x3f) == 0 \
8255 ? ((v) & ~0x1f) == 0 \
8258 : ((v) & ~0x7f) == 0 \
8261 : ((v) & ~0xfff) == 0 \
8262 ? ((v) & ~0x3ff) == 0 \
8263 ? ((v) & ~0x1ff) == 0 \
8266 : ((v) & ~0x7ff) == 0 \
8269 : ((v) & ~0x3fff) == 0 \
8270 ? ((v) & ~0x1fff) == 0 \
8273 : ((v) & ~0x7fff) == 0 \
8276 : ((v) & ~0xffffff) == 0 \
8277 ? ((v) & ~0xfffff) == 0 \
8278 ? ((v) & ~0x3ffff) == 0 \
8279 ? ((v) & ~0x1ffff) == 0 \
8282 : ((v) & ~0x7ffff) == 0 \
8285 : ((v) & ~0x3fffff) == 0 \
8286 ? ((v) & ~0x1fffff) == 0 \
8289 : ((v) & ~0x7fffff) == 0 \
8292 : ((v) & ~0xfffffff) == 0 \
8293 ? ((v) & ~0x3ffffff) == 0 \
8294 ? ((v) & ~0x1ffffff) == 0 \
8297 : ((v) & ~0x7ffffff) == 0 \
8300 : ((v) & ~0x3fffffff) == 0 \
8301 ? ((v) & ~0x1fffffff) == 0 \
8304 : ((v) & ~0x7fffffff) == 0 \
8309 * This routine generates the least number of instructions necessary to load
8310 * an absolute expression value into a register.
8313 load_register (int reg
, expressionS
*ep
, int dbl
)
8316 expressionS hi32
, lo32
;
8318 if (ep
->X_op
!= O_big
)
8320 gas_assert (ep
->X_op
== O_constant
);
8322 /* Sign-extending 32-bit constants makes their handling easier. */
8324 normalize_constant_expr (ep
);
8326 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8328 /* We can handle 16 bit signed values with an addiu to
8329 $zero. No need to ever use daddiu here, since $zero and
8330 the result are always correct in 32 bit mode. */
8331 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8334 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8336 /* We can handle 16 bit unsigned values with an ori to
8338 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8341 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8343 /* 32 bit values require an lui. */
8344 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8345 if ((ep
->X_add_number
& 0xffff) != 0)
8346 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8351 /* The value is larger than 32 bits. */
8353 if (!dbl
|| HAVE_32BIT_GPRS
)
8357 sprintf_vma (value
, ep
->X_add_number
);
8358 as_bad (_("number (0x%s) larger than 32 bits"), value
);
8359 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8363 if (ep
->X_op
!= O_big
)
8366 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8367 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8368 hi32
.X_add_number
&= 0xffffffff;
8370 lo32
.X_add_number
&= 0xffffffff;
8374 gas_assert (ep
->X_add_number
> 2);
8375 if (ep
->X_add_number
== 3)
8376 generic_bignum
[3] = 0;
8377 else if (ep
->X_add_number
> 4)
8378 as_bad (_("number larger than 64 bits"));
8379 lo32
.X_op
= O_constant
;
8380 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8381 hi32
.X_op
= O_constant
;
8382 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8385 if (hi32
.X_add_number
== 0)
8390 unsigned long hi
, lo
;
8392 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8394 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8396 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8399 if (lo32
.X_add_number
& 0x80000000)
8401 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8402 if (lo32
.X_add_number
& 0xffff)
8403 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8408 /* Check for 16bit shifted constant. We know that hi32 is
8409 non-zero, so start the mask on the first bit of the hi32
8414 unsigned long himask
, lomask
;
8418 himask
= 0xffff >> (32 - shift
);
8419 lomask
= (0xffff << shift
) & 0xffffffff;
8423 himask
= 0xffff << (shift
- 32);
8426 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8427 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8431 tmp
.X_op
= O_constant
;
8433 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8434 | (lo32
.X_add_number
>> shift
));
8436 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8437 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8438 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8439 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8444 while (shift
<= (64 - 16));
8446 /* Find the bit number of the lowest one bit, and store the
8447 shifted value in hi/lo. */
8448 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8449 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8453 while ((lo
& 1) == 0)
8458 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8464 while ((hi
& 1) == 0)
8473 /* Optimize if the shifted value is a (power of 2) - 1. */
8474 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8475 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8477 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8482 /* This instruction will set the register to be all
8484 tmp
.X_op
= O_constant
;
8485 tmp
.X_add_number
= (offsetT
) -1;
8486 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8490 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8491 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
8493 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
8494 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8499 /* Sign extend hi32 before calling load_register, because we can
8500 generally get better code when we load a sign extended value. */
8501 if ((hi32
.X_add_number
& 0x80000000) != 0)
8502 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
8503 load_register (reg
, &hi32
, 0);
8506 if ((lo32
.X_add_number
& 0xffff0000) == 0)
8510 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
8518 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
8520 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8521 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
8527 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
8531 mid16
.X_add_number
>>= 16;
8532 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8533 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8536 if ((lo32
.X_add_number
& 0xffff) != 0)
8537 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8541 load_delay_nop (void)
8543 if (!gpr_interlocks
)
8544 macro_build (NULL
, "nop", "");
8547 /* Load an address into a register. */
8550 load_address (int reg
, expressionS
*ep
, int *used_at
)
8552 if (ep
->X_op
!= O_constant
8553 && ep
->X_op
!= O_symbol
)
8555 as_bad (_("expression too complex"));
8556 ep
->X_op
= O_constant
;
8559 if (ep
->X_op
== O_constant
)
8561 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
8565 if (mips_pic
== NO_PIC
)
8567 /* If this is a reference to a GP relative symbol, we want
8568 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8570 lui $reg,<sym> (BFD_RELOC_HI16_S)
8571 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8572 If we have an addend, we always use the latter form.
8574 With 64bit address space and a usable $at we want
8575 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8576 lui $at,<sym> (BFD_RELOC_HI16_S)
8577 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8578 daddiu $at,<sym> (BFD_RELOC_LO16)
8582 If $at is already in use, we use a path which is suboptimal
8583 on superscalar processors.
8584 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8585 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8587 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8589 daddiu $reg,<sym> (BFD_RELOC_LO16)
8591 For GP relative symbols in 64bit address space we can use
8592 the same sequence as in 32bit address space. */
8593 if (HAVE_64BIT_SYMBOLS
)
8595 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8596 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8598 relax_start (ep
->X_add_symbol
);
8599 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8600 mips_gp_register
, BFD_RELOC_GPREL16
);
8604 if (*used_at
== 0 && mips_opts
.at
)
8606 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8607 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
8608 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8609 BFD_RELOC_MIPS_HIGHER
);
8610 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
8611 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
8612 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
8617 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8618 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8619 BFD_RELOC_MIPS_HIGHER
);
8620 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8621 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
8622 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8623 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
8626 if (mips_relax
.sequence
)
8631 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8632 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8634 relax_start (ep
->X_add_symbol
);
8635 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8636 mips_gp_register
, BFD_RELOC_GPREL16
);
8639 macro_build_lui (ep
, reg
);
8640 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
8641 reg
, reg
, BFD_RELOC_LO16
);
8642 if (mips_relax
.sequence
)
8646 else if (!mips_big_got
)
8650 /* If this is a reference to an external symbol, we want
8651 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8653 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8655 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8656 If there is a constant, it must be added in after.
8658 If we have NewABI, we want
8659 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8660 unless we're referencing a global symbol with a non-zero
8661 offset, in which case cst must be added separately. */
8664 if (ep
->X_add_number
)
8666 ex
.X_add_number
= ep
->X_add_number
;
8667 ep
->X_add_number
= 0;
8668 relax_start (ep
->X_add_symbol
);
8669 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8670 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8671 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8672 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8673 ex
.X_op
= O_constant
;
8674 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8675 reg
, reg
, BFD_RELOC_LO16
);
8676 ep
->X_add_number
= ex
.X_add_number
;
8679 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8680 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8681 if (mips_relax
.sequence
)
8686 ex
.X_add_number
= ep
->X_add_number
;
8687 ep
->X_add_number
= 0;
8688 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8689 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8691 relax_start (ep
->X_add_symbol
);
8693 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8697 if (ex
.X_add_number
!= 0)
8699 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8700 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8701 ex
.X_op
= O_constant
;
8702 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8703 reg
, reg
, BFD_RELOC_LO16
);
8707 else if (mips_big_got
)
8711 /* This is the large GOT case. If this is a reference to an
8712 external symbol, we want
8713 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8715 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8717 Otherwise, for a reference to a local symbol in old ABI, we want
8718 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8720 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8721 If there is a constant, it must be added in after.
8723 In the NewABI, for local symbols, with or without offsets, we want:
8724 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8725 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8729 ex
.X_add_number
= ep
->X_add_number
;
8730 ep
->X_add_number
= 0;
8731 relax_start (ep
->X_add_symbol
);
8732 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8733 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8734 reg
, reg
, mips_gp_register
);
8735 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8736 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8737 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8738 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8739 else if (ex
.X_add_number
)
8741 ex
.X_op
= O_constant
;
8742 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8746 ep
->X_add_number
= ex
.X_add_number
;
8748 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8749 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8750 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8751 BFD_RELOC_MIPS_GOT_OFST
);
8756 ex
.X_add_number
= ep
->X_add_number
;
8757 ep
->X_add_number
= 0;
8758 relax_start (ep
->X_add_symbol
);
8759 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8760 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8761 reg
, reg
, mips_gp_register
);
8762 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8763 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8765 if (reg_needs_delay (mips_gp_register
))
8767 /* We need a nop before loading from $gp. This special
8768 check is required because the lui which starts the main
8769 instruction stream does not refer to $gp, and so will not
8770 insert the nop which may be required. */
8771 macro_build (NULL
, "nop", "");
8773 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8774 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8776 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8780 if (ex
.X_add_number
!= 0)
8782 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8783 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8784 ex
.X_op
= O_constant
;
8785 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8793 if (!mips_opts
.at
&& *used_at
== 1)
8794 as_bad (_("macro used $at after \".set noat\""));
8797 /* Move the contents of register SOURCE into register DEST. */
8800 move_register (int dest
, int source
)
8802 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8803 instruction specifically requires a 32-bit one. */
8804 if (mips_opts
.micromips
8805 && !mips_opts
.insn32
8806 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8807 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8809 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8813 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8814 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8815 The two alternatives are:
8817 Global symbol Local sybmol
8818 ------------- ------------
8819 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8821 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8823 load_got_offset emits the first instruction and add_got_offset
8824 emits the second for a 16-bit offset or add_got_offset_hilo emits
8825 a sequence to add a 32-bit offset using a scratch register. */
8828 load_got_offset (int dest
, expressionS
*local
)
8833 global
.X_add_number
= 0;
8835 relax_start (local
->X_add_symbol
);
8836 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8837 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8839 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8840 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8845 add_got_offset (int dest
, expressionS
*local
)
8849 global
.X_op
= O_constant
;
8850 global
.X_op_symbol
= NULL
;
8851 global
.X_add_symbol
= NULL
;
8852 global
.X_add_number
= local
->X_add_number
;
8854 relax_start (local
->X_add_symbol
);
8855 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8856 dest
, dest
, BFD_RELOC_LO16
);
8858 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8863 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8866 int hold_mips_optimize
;
8868 global
.X_op
= O_constant
;
8869 global
.X_op_symbol
= NULL
;
8870 global
.X_add_symbol
= NULL
;
8871 global
.X_add_number
= local
->X_add_number
;
8873 relax_start (local
->X_add_symbol
);
8874 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8876 /* Set mips_optimize around the lui instruction to avoid
8877 inserting an unnecessary nop after the lw. */
8878 hold_mips_optimize
= mips_optimize
;
8880 macro_build_lui (&global
, tmp
);
8881 mips_optimize
= hold_mips_optimize
;
8882 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8885 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8888 /* Emit a sequence of instructions to emulate a branch likely operation.
8889 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8890 is its complementing branch with the original condition negated.
8891 CALL is set if the original branch specified the link operation.
8892 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8894 Code like this is produced in the noreorder mode:
8899 delay slot (executed only if branch taken)
8907 delay slot (executed only if branch taken)
8910 In the reorder mode the delay slot would be filled with a nop anyway,
8911 so code produced is simply:
8916 This function is used when producing code for the microMIPS ASE that
8917 does not implement branch likely instructions in hardware. */
8920 macro_build_branch_likely (const char *br
, const char *brneg
,
8921 int call
, expressionS
*ep
, const char *fmt
,
8922 unsigned int sreg
, unsigned int treg
)
8924 int noreorder
= mips_opts
.noreorder
;
8927 gas_assert (mips_opts
.micromips
);
8931 micromips_label_expr (&expr1
);
8932 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8933 macro_build (NULL
, "nop", "");
8934 macro_build (ep
, call
? "bal" : "b", "p");
8936 /* Set to true so that append_insn adds a label. */
8937 emit_branch_likely_macro
= TRUE
;
8941 macro_build (ep
, br
, fmt
, sreg
, treg
);
8942 macro_build (NULL
, "nop", "");
8947 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8948 the condition code tested. EP specifies the branch target. */
8951 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8978 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8981 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8982 the register tested. EP specifies the branch target. */
8985 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8987 const char *brneg
= NULL
;
8997 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9001 gas_assert (mips_opts
.micromips
);
9002 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9010 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9017 br
= mips_opts
.micromips
? "blez" : "blezl";
9024 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9028 gas_assert (mips_opts
.micromips
);
9029 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9036 if (mips_opts
.micromips
&& brneg
)
9037 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9039 macro_build (ep
, br
, "s,p", sreg
);
9042 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9043 TREG as the registers tested. EP specifies the branch target. */
9046 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9047 unsigned int sreg
, unsigned int treg
)
9049 const char *brneg
= NULL
;
9061 br
= mips_opts
.micromips
? "beq" : "beql";
9070 br
= mips_opts
.micromips
? "bne" : "bnel";
9076 if (mips_opts
.micromips
&& brneg
)
9077 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9079 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9082 /* Return the high part that should be loaded in order to make the low
9083 part of VALUE accessible using an offset of OFFBITS bits. */
9086 offset_high_part (offsetT value
, unsigned int offbits
)
9093 bias
= 1 << (offbits
- 1);
9094 low_mask
= bias
* 2 - 1;
9095 return (value
+ bias
) & ~low_mask
;
9098 /* Return true if the value stored in offset_expr and offset_reloc
9099 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9100 amount that the caller wants to add without inducing overflow
9101 and ALIGN is the known alignment of the value in bytes. */
9104 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9108 /* Accept any relocation operator if overflow isn't a concern. */
9109 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9112 /* These relocations are guaranteed not to overflow in correct links. */
9113 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9114 || gprel16_reloc_p (*offset_reloc
))
9117 if (offset_expr
.X_op
== O_constant
9118 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9119 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9126 * This routine implements the seemingly endless macro or synthesized
9127 * instructions and addressing modes in the mips assembly language. Many
9128 * of these macros are simple and are similar to each other. These could
9129 * probably be handled by some kind of table or grammar approach instead of
9130 * this verbose method. Others are not simple macros but are more like
9131 * optimizing code generation.
9132 * One interesting optimization is when several store macros appear
9133 * consecutively that would load AT with the upper half of the same address.
9134 * The ensuing load upper instructions are ommited. This implies some kind
9135 * of global optimization. We currently only optimize within a single macro.
9136 * For many of the load and store macros if the address is specified as a
9137 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9138 * first load register 'at' with zero and use it as the base register. The
9139 * mips assembler simply uses register $zero. Just one tiny optimization
9143 macro (struct mips_cl_insn
*ip
, char *str
)
9145 const struct mips_operand_array
*operands
;
9146 unsigned int breg
, i
;
9147 unsigned int tempreg
;
9150 expressionS label_expr
;
9165 bfd_boolean large_offset
;
9167 int hold_mips_optimize
;
9169 unsigned int op
[MAX_OPERANDS
];
9171 gas_assert (! mips_opts
.mips16
);
9173 operands
= insn_operands (ip
);
9174 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9175 if (operands
->operand
[i
])
9176 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9180 mask
= ip
->insn_mo
->mask
;
9182 label_expr
.X_op
= O_constant
;
9183 label_expr
.X_op_symbol
= NULL
;
9184 label_expr
.X_add_symbol
= NULL
;
9185 label_expr
.X_add_number
= 0;
9187 expr1
.X_op
= O_constant
;
9188 expr1
.X_op_symbol
= NULL
;
9189 expr1
.X_add_symbol
= NULL
;
9190 expr1
.X_add_number
= 1;
9206 if (mips_opts
.micromips
)
9207 micromips_label_expr (&label_expr
);
9209 label_expr
.X_add_number
= 8;
9210 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9212 macro_build (NULL
, "nop", "");
9214 move_register (op
[0], op
[1]);
9215 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9216 if (mips_opts
.micromips
)
9217 micromips_add_label ();
9234 if (!mips_opts
.micromips
)
9236 if (imm_expr
.X_add_number
>= -0x200
9237 && imm_expr
.X_add_number
< 0x200)
9239 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9240 (int) imm_expr
.X_add_number
);
9249 if (imm_expr
.X_add_number
>= -0x8000
9250 && imm_expr
.X_add_number
< 0x8000)
9252 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9257 load_register (AT
, &imm_expr
, dbl
);
9258 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9277 if (imm_expr
.X_add_number
>= 0
9278 && imm_expr
.X_add_number
< 0x10000)
9280 if (mask
!= M_NOR_I
)
9281 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9284 macro_build (&imm_expr
, "ori", "t,r,i",
9285 op
[0], op
[1], BFD_RELOC_LO16
);
9286 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9292 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9293 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9297 switch (imm_expr
.X_add_number
)
9300 macro_build (NULL
, "nop", "");
9303 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9307 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9308 (int) imm_expr
.X_add_number
);
9311 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9312 (unsigned long) imm_expr
.X_add_number
);
9321 gas_assert (mips_opts
.micromips
);
9322 macro_build_branch_ccl (mask
, &offset_expr
,
9323 EXTRACT_OPERAND (1, BCC
, *ip
));
9330 if (imm_expr
.X_add_number
== 0)
9336 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
9341 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9348 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9349 else if (op
[0] == 0)
9350 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9354 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9355 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9356 &offset_expr
, AT
, ZERO
);
9366 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9372 /* Check for > max integer. */
9373 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9376 /* Result is always false. */
9378 macro_build (NULL
, "nop", "");
9380 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9383 ++imm_expr
.X_add_number
;
9387 if (mask
== M_BGEL_I
)
9389 if (imm_expr
.X_add_number
== 0)
9391 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9392 &offset_expr
, op
[0]);
9395 if (imm_expr
.X_add_number
== 1)
9397 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9398 &offset_expr
, op
[0]);
9401 if (imm_expr
.X_add_number
<= GPR_SMIN
)
9404 /* result is always true */
9405 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
9406 macro_build (&offset_expr
, "b", "p");
9411 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9412 &offset_expr
, AT
, ZERO
);
9420 else if (op
[0] == 0)
9421 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9422 &offset_expr
, ZERO
, op
[1]);
9426 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9427 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9428 &offset_expr
, AT
, ZERO
);
9437 && imm_expr
.X_add_number
== -1))
9439 ++imm_expr
.X_add_number
;
9443 if (mask
== M_BGEUL_I
)
9445 if (imm_expr
.X_add_number
== 0)
9447 else if (imm_expr
.X_add_number
== 1)
9448 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9449 &offset_expr
, op
[0], ZERO
);
9454 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9455 &offset_expr
, AT
, ZERO
);
9463 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9464 else if (op
[0] == 0)
9465 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9469 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9470 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9471 &offset_expr
, AT
, ZERO
);
9479 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9480 &offset_expr
, op
[0], ZERO
);
9481 else if (op
[0] == 0)
9486 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9487 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9488 &offset_expr
, AT
, ZERO
);
9496 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9497 else if (op
[0] == 0)
9498 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
9502 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9503 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9504 &offset_expr
, AT
, ZERO
);
9511 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9513 ++imm_expr
.X_add_number
;
9517 if (mask
== M_BLTL_I
)
9519 if (imm_expr
.X_add_number
== 0)
9520 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9521 else if (imm_expr
.X_add_number
== 1)
9522 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9527 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9528 &offset_expr
, AT
, ZERO
);
9536 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9537 &offset_expr
, op
[0], ZERO
);
9538 else if (op
[0] == 0)
9543 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9544 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9545 &offset_expr
, AT
, ZERO
);
9554 && imm_expr
.X_add_number
== -1))
9556 ++imm_expr
.X_add_number
;
9560 if (mask
== M_BLTUL_I
)
9562 if (imm_expr
.X_add_number
== 0)
9564 else if (imm_expr
.X_add_number
== 1)
9565 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9566 &offset_expr
, op
[0], ZERO
);
9571 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9572 &offset_expr
, AT
, ZERO
);
9580 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9581 else if (op
[0] == 0)
9582 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
9586 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9587 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9588 &offset_expr
, AT
, ZERO
);
9597 else if (op
[0] == 0)
9598 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9599 &offset_expr
, ZERO
, op
[1]);
9603 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9604 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9605 &offset_expr
, AT
, ZERO
);
9621 as_warn (_("divide by zero"));
9623 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9625 macro_build (NULL
, "break", BRK_FMT
, 7);
9632 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9633 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9637 if (mips_opts
.micromips
)
9638 micromips_label_expr (&label_expr
);
9640 label_expr
.X_add_number
= 8;
9641 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9642 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9643 macro_build (NULL
, "break", BRK_FMT
, 7);
9644 if (mips_opts
.micromips
)
9645 micromips_add_label ();
9647 expr1
.X_add_number
= -1;
9649 load_register (AT
, &expr1
, dbl
);
9650 if (mips_opts
.micromips
)
9651 micromips_label_expr (&label_expr
);
9653 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
9654 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
9657 expr1
.X_add_number
= 1;
9658 load_register (AT
, &expr1
, dbl
);
9659 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
9663 expr1
.X_add_number
= 0x80000000;
9664 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
9668 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
9669 /* We want to close the noreorder block as soon as possible, so
9670 that later insns are available for delay slot filling. */
9675 if (mips_opts
.micromips
)
9676 micromips_label_expr (&label_expr
);
9678 label_expr
.X_add_number
= 8;
9679 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
9680 macro_build (NULL
, "nop", "");
9682 /* We want to close the noreorder block as soon as possible, so
9683 that later insns are available for delay slot filling. */
9686 macro_build (NULL
, "break", BRK_FMT
, 6);
9688 if (mips_opts
.micromips
)
9689 micromips_add_label ();
9690 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9729 if (imm_expr
.X_add_number
== 0)
9731 as_warn (_("divide by zero"));
9733 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9735 macro_build (NULL
, "break", BRK_FMT
, 7);
9738 if (imm_expr
.X_add_number
== 1)
9740 if (strcmp (s2
, "mflo") == 0)
9741 move_register (op
[0], op
[1]);
9743 move_register (op
[0], ZERO
);
9746 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
9748 if (strcmp (s2
, "mflo") == 0)
9749 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9751 move_register (op
[0], ZERO
);
9756 load_register (AT
, &imm_expr
, dbl
);
9757 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9758 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9780 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9781 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9782 /* We want to close the noreorder block as soon as possible, so
9783 that later insns are available for delay slot filling. */
9788 if (mips_opts
.micromips
)
9789 micromips_label_expr (&label_expr
);
9791 label_expr
.X_add_number
= 8;
9792 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9793 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9795 /* We want to close the noreorder block as soon as possible, so
9796 that later insns are available for delay slot filling. */
9798 macro_build (NULL
, "break", BRK_FMT
, 7);
9799 if (mips_opts
.micromips
)
9800 micromips_add_label ();
9802 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9814 /* Load the address of a symbol into a register. If breg is not
9815 zero, we then add a base register to it. */
9818 if (dbl
&& HAVE_32BIT_GPRS
)
9819 as_warn (_("dla used to load 32-bit register"));
9821 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9822 as_warn (_("la used to load 64-bit address"));
9824 if (small_offset_p (0, align
, 16))
9826 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9827 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9831 if (mips_opts
.at
&& (op
[0] == breg
))
9839 if (offset_expr
.X_op
!= O_symbol
9840 && offset_expr
.X_op
!= O_constant
)
9842 as_bad (_("expression too complex"));
9843 offset_expr
.X_op
= O_constant
;
9846 if (offset_expr
.X_op
== O_constant
)
9847 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9848 else if (mips_pic
== NO_PIC
)
9850 /* If this is a reference to a GP relative symbol, we want
9851 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9853 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9854 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9855 If we have a constant, we need two instructions anyhow,
9856 so we may as well always use the latter form.
9858 With 64bit address space and a usable $at we want
9859 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9860 lui $at,<sym> (BFD_RELOC_HI16_S)
9861 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9862 daddiu $at,<sym> (BFD_RELOC_LO16)
9864 daddu $tempreg,$tempreg,$at
9866 If $at is already in use, we use a path which is suboptimal
9867 on superscalar processors.
9868 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9869 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9871 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9873 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9875 For GP relative symbols in 64bit address space we can use
9876 the same sequence as in 32bit address space. */
9877 if (HAVE_64BIT_SYMBOLS
)
9879 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9880 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9882 relax_start (offset_expr
.X_add_symbol
);
9883 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9884 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9888 if (used_at
== 0 && mips_opts
.at
)
9890 macro_build (&offset_expr
, "lui", LUI_FMT
,
9891 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9892 macro_build (&offset_expr
, "lui", LUI_FMT
,
9893 AT
, BFD_RELOC_HI16_S
);
9894 macro_build (&offset_expr
, "daddiu", "t,r,j",
9895 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9896 macro_build (&offset_expr
, "daddiu", "t,r,j",
9897 AT
, AT
, BFD_RELOC_LO16
);
9898 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9899 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9904 macro_build (&offset_expr
, "lui", LUI_FMT
,
9905 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9906 macro_build (&offset_expr
, "daddiu", "t,r,j",
9907 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9908 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9909 macro_build (&offset_expr
, "daddiu", "t,r,j",
9910 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9911 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9912 macro_build (&offset_expr
, "daddiu", "t,r,j",
9913 tempreg
, tempreg
, BFD_RELOC_LO16
);
9916 if (mips_relax
.sequence
)
9921 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9922 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9924 relax_start (offset_expr
.X_add_symbol
);
9925 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9926 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9929 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9930 as_bad (_("offset too large"));
9931 macro_build_lui (&offset_expr
, tempreg
);
9932 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9933 tempreg
, tempreg
, BFD_RELOC_LO16
);
9934 if (mips_relax
.sequence
)
9938 else if (!mips_big_got
&& !HAVE_NEWABI
)
9940 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9942 /* If this is a reference to an external symbol, and there
9943 is no constant, we want
9944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9945 or for lca or if tempreg is PIC_CALL_REG
9946 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9947 For a local symbol, we want
9948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9950 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9952 If we have a small constant, and this is a reference to
9953 an external symbol, we want
9954 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9956 addiu $tempreg,$tempreg,<constant>
9957 For a local symbol, we want the same instruction
9958 sequence, but we output a BFD_RELOC_LO16 reloc on the
9961 If we have a large constant, and this is a reference to
9962 an external symbol, we want
9963 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9964 lui $at,<hiconstant>
9965 addiu $at,$at,<loconstant>
9966 addu $tempreg,$tempreg,$at
9967 For a local symbol, we want the same instruction
9968 sequence, but we output a BFD_RELOC_LO16 reloc on the
9972 if (offset_expr
.X_add_number
== 0)
9974 if (mips_pic
== SVR4_PIC
9976 && (call
|| tempreg
== PIC_CALL_REG
))
9977 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9979 relax_start (offset_expr
.X_add_symbol
);
9980 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9981 lw_reloc_type
, mips_gp_register
);
9984 /* We're going to put in an addu instruction using
9985 tempreg, so we may as well insert the nop right
9990 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9991 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9993 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9994 tempreg
, tempreg
, BFD_RELOC_LO16
);
9996 /* FIXME: If breg == 0, and the next instruction uses
9997 $tempreg, then if this variant case is used an extra
9998 nop will be generated. */
10000 else if (offset_expr
.X_add_number
>= -0x8000
10001 && offset_expr
.X_add_number
< 0x8000)
10003 load_got_offset (tempreg
, &offset_expr
);
10005 add_got_offset (tempreg
, &offset_expr
);
10009 expr1
.X_add_number
= offset_expr
.X_add_number
;
10010 offset_expr
.X_add_number
=
10011 SEXT_16BIT (offset_expr
.X_add_number
);
10012 load_got_offset (tempreg
, &offset_expr
);
10013 offset_expr
.X_add_number
= expr1
.X_add_number
;
10014 /* If we are going to add in a base register, and the
10015 target register and the base register are the same,
10016 then we are using AT as a temporary register. Since
10017 we want to load the constant into AT, we add our
10018 current AT (from the global offset table) and the
10019 register into the register now, and pretend we were
10020 not using a base register. */
10024 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10029 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10033 else if (!mips_big_got
&& HAVE_NEWABI
)
10035 int add_breg_early
= 0;
10037 /* If this is a reference to an external, and there is no
10038 constant, or local symbol (*), with or without a
10040 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10041 or for lca or if tempreg is PIC_CALL_REG
10042 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10044 If we have a small constant, and this is a reference to
10045 an external symbol, we want
10046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10047 addiu $tempreg,$tempreg,<constant>
10049 If we have a large constant, and this is a reference to
10050 an external symbol, we want
10051 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10052 lui $at,<hiconstant>
10053 addiu $at,$at,<loconstant>
10054 addu $tempreg,$tempreg,$at
10056 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10057 local symbols, even though it introduces an additional
10060 if (offset_expr
.X_add_number
)
10062 expr1
.X_add_number
= offset_expr
.X_add_number
;
10063 offset_expr
.X_add_number
= 0;
10065 relax_start (offset_expr
.X_add_symbol
);
10066 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10067 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10069 if (expr1
.X_add_number
>= -0x8000
10070 && expr1
.X_add_number
< 0x8000)
10072 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10073 tempreg
, tempreg
, BFD_RELOC_LO16
);
10075 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10079 /* If we are going to add in a base register, and the
10080 target register and the base register are the same,
10081 then we are using AT as a temporary register. Since
10082 we want to load the constant into AT, we add our
10083 current AT (from the global offset table) and the
10084 register into the register now, and pretend we were
10085 not using a base register. */
10090 gas_assert (tempreg
== AT
);
10091 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10094 add_breg_early
= 1;
10097 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10098 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10104 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10107 offset_expr
.X_add_number
= expr1
.X_add_number
;
10109 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10110 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10111 if (add_breg_early
)
10113 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10114 op
[0], tempreg
, breg
);
10120 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10122 relax_start (offset_expr
.X_add_symbol
);
10123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10124 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10126 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10127 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10132 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10133 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10136 else if (mips_big_got
&& !HAVE_NEWABI
)
10139 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10140 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10141 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10143 /* This is the large GOT case. If this is a reference to an
10144 external symbol, and there is no constant, we want
10145 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10146 addu $tempreg,$tempreg,$gp
10147 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10148 or for lca or if tempreg is PIC_CALL_REG
10149 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10150 addu $tempreg,$tempreg,$gp
10151 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10152 For a local symbol, we want
10153 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10155 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10157 If we have a small constant, and this is a reference to
10158 an external symbol, we want
10159 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10160 addu $tempreg,$tempreg,$gp
10161 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10163 addiu $tempreg,$tempreg,<constant>
10164 For a local symbol, we want
10165 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10167 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10169 If we have a large constant, and this is a reference to
10170 an external symbol, we want
10171 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10172 addu $tempreg,$tempreg,$gp
10173 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10174 lui $at,<hiconstant>
10175 addiu $at,$at,<loconstant>
10176 addu $tempreg,$tempreg,$at
10177 For a local symbol, we want
10178 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10179 lui $at,<hiconstant>
10180 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10181 addu $tempreg,$tempreg,$at
10184 expr1
.X_add_number
= offset_expr
.X_add_number
;
10185 offset_expr
.X_add_number
= 0;
10186 relax_start (offset_expr
.X_add_symbol
);
10187 gpdelay
= reg_needs_delay (mips_gp_register
);
10188 if (expr1
.X_add_number
== 0 && breg
== 0
10189 && (call
|| tempreg
== PIC_CALL_REG
))
10191 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10192 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10194 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10195 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10196 tempreg
, tempreg
, mips_gp_register
);
10197 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10198 tempreg
, lw_reloc_type
, tempreg
);
10199 if (expr1
.X_add_number
== 0)
10203 /* We're going to put in an addu instruction using
10204 tempreg, so we may as well insert the nop right
10209 else if (expr1
.X_add_number
>= -0x8000
10210 && expr1
.X_add_number
< 0x8000)
10213 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10214 tempreg
, tempreg
, BFD_RELOC_LO16
);
10220 /* If we are going to add in a base register, and the
10221 target register and the base register are the same,
10222 then we are using AT as a temporary register. Since
10223 we want to load the constant into AT, we add our
10224 current AT (from the global offset table) and the
10225 register into the register now, and pretend we were
10226 not using a base register. */
10231 gas_assert (tempreg
== AT
);
10233 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10238 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10239 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10243 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10248 /* This is needed because this instruction uses $gp, but
10249 the first instruction on the main stream does not. */
10250 macro_build (NULL
, "nop", "");
10253 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10254 local_reloc_type
, mips_gp_register
);
10255 if (expr1
.X_add_number
>= -0x8000
10256 && expr1
.X_add_number
< 0x8000)
10259 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10260 tempreg
, tempreg
, BFD_RELOC_LO16
);
10261 /* FIXME: If add_number is 0, and there was no base
10262 register, the external symbol case ended with a load,
10263 so if the symbol turns out to not be external, and
10264 the next instruction uses tempreg, an unnecessary nop
10265 will be inserted. */
10271 /* We must add in the base register now, as in the
10272 external symbol case. */
10273 gas_assert (tempreg
== AT
);
10275 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10278 /* We set breg to 0 because we have arranged to add
10279 it in in both cases. */
10283 macro_build_lui (&expr1
, AT
);
10284 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10285 AT
, AT
, BFD_RELOC_LO16
);
10286 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10287 tempreg
, tempreg
, AT
);
10292 else if (mips_big_got
&& HAVE_NEWABI
)
10294 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10295 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10296 int add_breg_early
= 0;
10298 /* This is the large GOT case. If this is a reference to an
10299 external symbol, and there is no constant, we want
10300 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10301 add $tempreg,$tempreg,$gp
10302 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10303 or for lca or if tempreg is PIC_CALL_REG
10304 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10305 add $tempreg,$tempreg,$gp
10306 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10308 If we have a small constant, and this is a reference to
10309 an external symbol, we want
10310 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10311 add $tempreg,$tempreg,$gp
10312 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10313 addi $tempreg,$tempreg,<constant>
10315 If we have a large constant, and this is a reference to
10316 an external symbol, we want
10317 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10318 addu $tempreg,$tempreg,$gp
10319 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10320 lui $at,<hiconstant>
10321 addi $at,$at,<loconstant>
10322 add $tempreg,$tempreg,$at
10324 If we have NewABI, and we know it's a local symbol, we want
10325 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10326 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10327 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10329 relax_start (offset_expr
.X_add_symbol
);
10331 expr1
.X_add_number
= offset_expr
.X_add_number
;
10332 offset_expr
.X_add_number
= 0;
10334 if (expr1
.X_add_number
== 0 && breg
== 0
10335 && (call
|| tempreg
== PIC_CALL_REG
))
10337 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10338 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10340 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10341 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10342 tempreg
, tempreg
, mips_gp_register
);
10343 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10344 tempreg
, lw_reloc_type
, tempreg
);
10346 if (expr1
.X_add_number
== 0)
10348 else if (expr1
.X_add_number
>= -0x8000
10349 && expr1
.X_add_number
< 0x8000)
10351 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10352 tempreg
, tempreg
, BFD_RELOC_LO16
);
10354 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10358 /* If we are going to add in a base register, and the
10359 target register and the base register are the same,
10360 then we are using AT as a temporary register. Since
10361 we want to load the constant into AT, we add our
10362 current AT (from the global offset table) and the
10363 register into the register now, and pretend we were
10364 not using a base register. */
10369 gas_assert (tempreg
== AT
);
10370 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10373 add_breg_early
= 1;
10376 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10377 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10382 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10385 offset_expr
.X_add_number
= expr1
.X_add_number
;
10386 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10387 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10388 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10389 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10390 if (add_breg_early
)
10392 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10393 op
[0], tempreg
, breg
);
10403 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10407 gas_assert (!mips_opts
.micromips
);
10408 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10412 gas_assert (!mips_opts
.micromips
);
10413 macro_build (NULL
, "c2", "C", 0x02);
10417 gas_assert (!mips_opts
.micromips
);
10418 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10422 gas_assert (!mips_opts
.micromips
);
10423 macro_build (NULL
, "c2", "C", 3);
10427 gas_assert (!mips_opts
.micromips
);
10428 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10432 /* The j instruction may not be used in PIC code, since it
10433 requires an absolute address. We convert it to a b
10435 if (mips_pic
== NO_PIC
)
10436 macro_build (&offset_expr
, "j", "a");
10438 macro_build (&offset_expr
, "b", "p");
10441 /* The jal instructions must be handled as macros because when
10442 generating PIC code they expand to multi-instruction
10443 sequences. Normally they are simple instructions. */
10447 /* Fall through. */
10449 gas_assert (mips_opts
.micromips
);
10450 if (mips_opts
.insn32
)
10452 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10460 /* Fall through. */
10463 if (mips_pic
== NO_PIC
)
10465 s
= jals
? "jalrs" : "jalr";
10466 if (mips_opts
.micromips
10467 && !mips_opts
.insn32
10469 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10470 macro_build (NULL
, s
, "mj", op
[1]);
10472 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10476 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10477 && mips_cprestore_offset
>= 0);
10479 if (op
[1] != PIC_CALL_REG
)
10480 as_warn (_("MIPS PIC call to register other than $25"));
10482 s
= ((mips_opts
.micromips
10483 && !mips_opts
.insn32
10484 && (!mips_opts
.noreorder
|| cprestore
))
10485 ? "jalrs" : "jalr");
10486 if (mips_opts
.micromips
10487 && !mips_opts
.insn32
10489 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10490 macro_build (NULL
, s
, "mj", op
[1]);
10492 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10493 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
10495 if (mips_cprestore_offset
< 0)
10496 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10499 if (!mips_frame_reg_valid
)
10501 as_warn (_("no .frame pseudo-op used in PIC code"));
10502 /* Quiet this warning. */
10503 mips_frame_reg_valid
= 1;
10505 if (!mips_cprestore_valid
)
10507 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10508 /* Quiet this warning. */
10509 mips_cprestore_valid
= 1;
10511 if (mips_opts
.noreorder
)
10512 macro_build (NULL
, "nop", "");
10513 expr1
.X_add_number
= mips_cprestore_offset
;
10514 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10517 HAVE_64BIT_ADDRESSES
);
10525 gas_assert (mips_opts
.micromips
);
10526 if (mips_opts
.insn32
)
10528 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10532 /* Fall through. */
10534 if (mips_pic
== NO_PIC
)
10535 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
10536 else if (mips_pic
== SVR4_PIC
)
10538 /* If this is a reference to an external symbol, and we are
10539 using a small GOT, we want
10540 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10544 lw $gp,cprestore($sp)
10545 The cprestore value is set using the .cprestore
10546 pseudo-op. If we are using a big GOT, we want
10547 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10549 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10553 lw $gp,cprestore($sp)
10554 If the symbol is not external, we want
10555 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10557 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10560 lw $gp,cprestore($sp)
10562 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10563 sequences above, minus nops, unless the symbol is local,
10564 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10570 relax_start (offset_expr
.X_add_symbol
);
10571 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10572 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10575 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10576 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
10582 relax_start (offset_expr
.X_add_symbol
);
10583 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10584 BFD_RELOC_MIPS_CALL_HI16
);
10585 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10586 PIC_CALL_REG
, mips_gp_register
);
10587 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10588 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10591 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10592 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
10594 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10595 PIC_CALL_REG
, PIC_CALL_REG
,
10596 BFD_RELOC_MIPS_GOT_OFST
);
10600 macro_build_jalr (&offset_expr
, 0);
10604 relax_start (offset_expr
.X_add_symbol
);
10607 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10608 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10617 gpdelay
= reg_needs_delay (mips_gp_register
);
10618 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10619 BFD_RELOC_MIPS_CALL_HI16
);
10620 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10621 PIC_CALL_REG
, mips_gp_register
);
10622 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10623 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10628 macro_build (NULL
, "nop", "");
10630 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10631 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
10634 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10635 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
10637 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
10639 if (mips_cprestore_offset
< 0)
10640 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10643 if (!mips_frame_reg_valid
)
10645 as_warn (_("no .frame pseudo-op used in PIC code"));
10646 /* Quiet this warning. */
10647 mips_frame_reg_valid
= 1;
10649 if (!mips_cprestore_valid
)
10651 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10652 /* Quiet this warning. */
10653 mips_cprestore_valid
= 1;
10655 if (mips_opts
.noreorder
)
10656 macro_build (NULL
, "nop", "");
10657 expr1
.X_add_number
= mips_cprestore_offset
;
10658 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10661 HAVE_64BIT_ADDRESSES
);
10665 else if (mips_pic
== VXWORKS_PIC
)
10666 as_bad (_("non-PIC jump used in PIC library"));
10773 gas_assert (!mips_opts
.micromips
);
10776 /* Itbl support may require additional care here. */
10782 /* Itbl support may require additional care here. */
10788 offbits
= (mips_opts
.micromips
? 12 : 16);
10789 /* Itbl support may require additional care here. */
10793 gas_assert (!mips_opts
.micromips
);
10796 /* Itbl support may require additional care here. */
10802 offbits
= (mips_opts
.micromips
? 12 : 16);
10807 offbits
= (mips_opts
.micromips
? 12 : 16);
10812 /* Itbl support may require additional care here. */
10818 offbits
= (mips_opts
.micromips
? 12 : 16);
10819 /* Itbl support may require additional care here. */
10825 /* Itbl support may require additional care here. */
10831 /* Itbl support may require additional care here. */
10837 offbits
= (mips_opts
.micromips
? 12 : 16);
10842 offbits
= (mips_opts
.micromips
? 12 : 16);
10847 offbits
= (mips_opts
.micromips
? 12 : 16);
10852 offbits
= (mips_opts
.micromips
? 12 : 16);
10857 offbits
= (mips_opts
.micromips
? 12 : 16);
10860 gas_assert (mips_opts
.micromips
);
10867 gas_assert (mips_opts
.micromips
);
10874 gas_assert (mips_opts
.micromips
);
10880 gas_assert (mips_opts
.micromips
);
10887 /* We don't want to use $0 as tempreg. */
10888 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10891 tempreg
= op
[0] + lp
;
10907 gas_assert (!mips_opts
.micromips
);
10910 /* Itbl support may require additional care here. */
10916 /* Itbl support may require additional care here. */
10922 offbits
= (mips_opts
.micromips
? 12 : 16);
10923 /* Itbl support may require additional care here. */
10927 gas_assert (!mips_opts
.micromips
);
10930 /* Itbl support may require additional care here. */
10936 offbits
= (mips_opts
.micromips
? 12 : 16);
10941 offbits
= (mips_opts
.micromips
? 12 : 16);
10946 offbits
= (mips_opts
.micromips
? 12 : 16);
10951 offbits
= (mips_opts
.micromips
? 12 : 16);
10955 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10956 offbits
= (mips_opts
.micromips
? 12 : 16);
10965 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10966 offbits
= (mips_opts
.micromips
? 12 : 16);
10977 /* Itbl support may require additional care here. */
10982 offbits
= (mips_opts
.micromips
? 12 : 16);
10983 /* Itbl support may require additional care here. */
10989 /* Itbl support may require additional care here. */
10993 gas_assert (!mips_opts
.micromips
);
10996 /* Itbl support may require additional care here. */
11002 offbits
= (mips_opts
.micromips
? 12 : 16);
11007 offbits
= (mips_opts
.micromips
? 12 : 16);
11010 gas_assert (mips_opts
.micromips
);
11016 gas_assert (mips_opts
.micromips
);
11022 gas_assert (mips_opts
.micromips
);
11028 gas_assert (mips_opts
.micromips
);
11037 if (small_offset_p (0, align
, 16))
11039 /* The first case exists for M_LD_AB and M_SD_AB, which are
11040 macros for o32 but which should act like normal instructions
11043 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11044 offset_reloc
[1], offset_reloc
[2], breg
);
11045 else if (small_offset_p (0, align
, offbits
))
11048 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11050 macro_build (NULL
, s
, fmt
, op
[0],
11051 (int) offset_expr
.X_add_number
, breg
);
11057 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11058 tempreg
, breg
, -1, offset_reloc
[0],
11059 offset_reloc
[1], offset_reloc
[2]);
11061 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11063 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11071 if (offset_expr
.X_op
!= O_constant
11072 && offset_expr
.X_op
!= O_symbol
)
11074 as_bad (_("expression too complex"));
11075 offset_expr
.X_op
= O_constant
;
11078 if (HAVE_32BIT_ADDRESSES
11079 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11083 sprintf_vma (value
, offset_expr
.X_add_number
);
11084 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11087 /* A constant expression in PIC code can be handled just as it
11088 is in non PIC code. */
11089 if (offset_expr
.X_op
== O_constant
)
11091 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11092 offbits
== 0 ? 16 : offbits
);
11093 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11095 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11097 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11098 tempreg
, tempreg
, breg
);
11101 if (offset_expr
.X_add_number
!= 0)
11102 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11103 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11104 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11106 else if (offbits
== 16)
11107 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11109 macro_build (NULL
, s
, fmt
, op
[0],
11110 (int) offset_expr
.X_add_number
, tempreg
);
11112 else if (offbits
!= 16)
11114 /* The offset field is too narrow to be used for a low-part
11115 relocation, so load the whole address into the auxillary
11117 load_address (tempreg
, &offset_expr
, &used_at
);
11119 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11120 tempreg
, tempreg
, breg
);
11122 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11124 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11126 else if (mips_pic
== NO_PIC
)
11128 /* If this is a reference to a GP relative symbol, and there
11129 is no base register, we want
11130 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11131 Otherwise, if there is no base register, we want
11132 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11133 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11134 If we have a constant, we need two instructions anyhow,
11135 so we always use the latter form.
11137 If we have a base register, and this is a reference to a
11138 GP relative symbol, we want
11139 addu $tempreg,$breg,$gp
11140 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11142 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11143 addu $tempreg,$tempreg,$breg
11144 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11145 With a constant we always use the latter case.
11147 With 64bit address space and no base register and $at usable,
11149 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11150 lui $at,<sym> (BFD_RELOC_HI16_S)
11151 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11154 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11155 If we have a base register, we want
11156 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11157 lui $at,<sym> (BFD_RELOC_HI16_S)
11158 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11162 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11164 Without $at we can't generate the optimal path for superscalar
11165 processors here since this would require two temporary registers.
11166 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11167 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11169 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11171 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11172 If we have a base register, we want
11173 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11174 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11176 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11178 daddu $tempreg,$tempreg,$breg
11179 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11181 For GP relative symbols in 64bit address space we can use
11182 the same sequence as in 32bit address space. */
11183 if (HAVE_64BIT_SYMBOLS
)
11185 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11186 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11188 relax_start (offset_expr
.X_add_symbol
);
11191 macro_build (&offset_expr
, s
, fmt
, op
[0],
11192 BFD_RELOC_GPREL16
, mips_gp_register
);
11196 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11197 tempreg
, breg
, mips_gp_register
);
11198 macro_build (&offset_expr
, s
, fmt
, op
[0],
11199 BFD_RELOC_GPREL16
, tempreg
);
11204 if (used_at
== 0 && mips_opts
.at
)
11206 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11207 BFD_RELOC_MIPS_HIGHEST
);
11208 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11210 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11211 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11213 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11214 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11215 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11216 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11222 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11223 BFD_RELOC_MIPS_HIGHEST
);
11224 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11225 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11226 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11227 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11228 tempreg
, BFD_RELOC_HI16_S
);
11229 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11231 macro_build (NULL
, "daddu", "d,v,t",
11232 tempreg
, tempreg
, breg
);
11233 macro_build (&offset_expr
, s
, fmt
, op
[0],
11234 BFD_RELOC_LO16
, tempreg
);
11237 if (mips_relax
.sequence
)
11244 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11245 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11247 relax_start (offset_expr
.X_add_symbol
);
11248 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11252 macro_build_lui (&offset_expr
, tempreg
);
11253 macro_build (&offset_expr
, s
, fmt
, op
[0],
11254 BFD_RELOC_LO16
, tempreg
);
11255 if (mips_relax
.sequence
)
11260 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11261 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11263 relax_start (offset_expr
.X_add_symbol
);
11264 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11265 tempreg
, breg
, mips_gp_register
);
11266 macro_build (&offset_expr
, s
, fmt
, op
[0],
11267 BFD_RELOC_GPREL16
, tempreg
);
11270 macro_build_lui (&offset_expr
, tempreg
);
11271 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11272 tempreg
, tempreg
, breg
);
11273 macro_build (&offset_expr
, s
, fmt
, op
[0],
11274 BFD_RELOC_LO16
, tempreg
);
11275 if (mips_relax
.sequence
)
11279 else if (!mips_big_got
)
11281 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11283 /* If this is a reference to an external symbol, we want
11284 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11286 <op> op[0],0($tempreg)
11288 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11290 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11291 <op> op[0],0($tempreg)
11293 For NewABI, we want
11294 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11295 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11297 If there is a base register, we add it to $tempreg before
11298 the <op>. If there is a constant, we stick it in the
11299 <op> instruction. We don't handle constants larger than
11300 16 bits, because we have no way to load the upper 16 bits
11301 (actually, we could handle them for the subset of cases
11302 in which we are not using $at). */
11303 gas_assert (offset_expr
.X_op
== O_symbol
);
11306 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11307 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11309 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11310 tempreg
, tempreg
, breg
);
11311 macro_build (&offset_expr
, s
, fmt
, op
[0],
11312 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11315 expr1
.X_add_number
= offset_expr
.X_add_number
;
11316 offset_expr
.X_add_number
= 0;
11317 if (expr1
.X_add_number
< -0x8000
11318 || expr1
.X_add_number
>= 0x8000)
11319 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11320 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11321 lw_reloc_type
, mips_gp_register
);
11323 relax_start (offset_expr
.X_add_symbol
);
11325 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11326 tempreg
, BFD_RELOC_LO16
);
11329 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11330 tempreg
, tempreg
, breg
);
11331 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11333 else if (mips_big_got
&& !HAVE_NEWABI
)
11337 /* If this is a reference to an external symbol, we want
11338 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11339 addu $tempreg,$tempreg,$gp
11340 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11341 <op> op[0],0($tempreg)
11343 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11345 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11346 <op> op[0],0($tempreg)
11347 If there is a base register, we add it to $tempreg before
11348 the <op>. If there is a constant, we stick it in the
11349 <op> instruction. We don't handle constants larger than
11350 16 bits, because we have no way to load the upper 16 bits
11351 (actually, we could handle them for the subset of cases
11352 in which we are not using $at). */
11353 gas_assert (offset_expr
.X_op
== O_symbol
);
11354 expr1
.X_add_number
= offset_expr
.X_add_number
;
11355 offset_expr
.X_add_number
= 0;
11356 if (expr1
.X_add_number
< -0x8000
11357 || expr1
.X_add_number
>= 0x8000)
11358 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11359 gpdelay
= reg_needs_delay (mips_gp_register
);
11360 relax_start (offset_expr
.X_add_symbol
);
11361 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11362 BFD_RELOC_MIPS_GOT_HI16
);
11363 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11365 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11366 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11369 macro_build (NULL
, "nop", "");
11370 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11371 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11373 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11374 tempreg
, BFD_RELOC_LO16
);
11378 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11379 tempreg
, tempreg
, breg
);
11380 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11382 else if (mips_big_got
&& HAVE_NEWABI
)
11384 /* If this is a reference to an external symbol, we want
11385 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11386 add $tempreg,$tempreg,$gp
11387 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11388 <op> op[0],<ofst>($tempreg)
11389 Otherwise, for local symbols, we want:
11390 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11391 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11392 gas_assert (offset_expr
.X_op
== O_symbol
);
11393 expr1
.X_add_number
= offset_expr
.X_add_number
;
11394 offset_expr
.X_add_number
= 0;
11395 if (expr1
.X_add_number
< -0x8000
11396 || expr1
.X_add_number
>= 0x8000)
11397 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11398 relax_start (offset_expr
.X_add_symbol
);
11399 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11400 BFD_RELOC_MIPS_GOT_HI16
);
11401 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11403 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11404 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11406 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11407 tempreg
, tempreg
, breg
);
11408 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11411 offset_expr
.X_add_number
= expr1
.X_add_number
;
11412 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11413 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11415 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11416 tempreg
, tempreg
, breg
);
11417 macro_build (&offset_expr
, s
, fmt
, op
[0],
11418 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11427 gas_assert (mips_opts
.micromips
);
11428 gas_assert (mips_opts
.insn32
);
11429 start_noreorder ();
11430 macro_build (NULL
, "jr", "s", RA
);
11431 expr1
.X_add_number
= op
[0] << 2;
11432 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11437 gas_assert (mips_opts
.micromips
);
11438 gas_assert (mips_opts
.insn32
);
11439 macro_build (NULL
, "jr", "s", op
[0]);
11440 if (mips_opts
.noreorder
)
11441 macro_build (NULL
, "nop", "");
11446 load_register (op
[0], &imm_expr
, 0);
11450 load_register (op
[0], &imm_expr
, 1);
11454 if (imm_expr
.X_op
== O_constant
)
11457 load_register (AT
, &imm_expr
, 0);
11458 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11463 gas_assert (imm_expr
.X_op
== O_absent
11464 && offset_expr
.X_op
== O_symbol
11465 && strcmp (segment_name (S_GET_SEGMENT
11466 (offset_expr
.X_add_symbol
)),
11468 && offset_expr
.X_add_number
== 0);
11469 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
11470 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
11475 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11476 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11477 order 32 bits of the value and the low order 32 bits are either
11478 zero or in OFFSET_EXPR. */
11479 if (imm_expr
.X_op
== O_constant
)
11481 if (HAVE_64BIT_GPRS
)
11482 load_register (op
[0], &imm_expr
, 1);
11487 if (target_big_endian
)
11499 load_register (hreg
, &imm_expr
, 0);
11502 if (offset_expr
.X_op
== O_absent
)
11503 move_register (lreg
, 0);
11506 gas_assert (offset_expr
.X_op
== O_constant
);
11507 load_register (lreg
, &offset_expr
, 0);
11513 gas_assert (imm_expr
.X_op
== O_absent
);
11515 /* We know that sym is in the .rdata section. First we get the
11516 upper 16 bits of the address. */
11517 if (mips_pic
== NO_PIC
)
11519 macro_build_lui (&offset_expr
, AT
);
11524 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11525 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11529 /* Now we load the register(s). */
11530 if (HAVE_64BIT_GPRS
)
11533 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
11534 BFD_RELOC_LO16
, AT
);
11539 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
11540 BFD_RELOC_LO16
, AT
);
11543 /* FIXME: How in the world do we deal with the possible
11545 offset_expr
.X_add_number
+= 4;
11546 macro_build (&offset_expr
, "lw", "t,o(b)",
11547 op
[0] + 1, BFD_RELOC_LO16
, AT
);
11553 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11554 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11555 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11556 the value and the low order 32 bits are either zero or in
11558 if (imm_expr
.X_op
== O_constant
)
11561 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
11562 if (HAVE_64BIT_FPRS
)
11564 gas_assert (HAVE_64BIT_GPRS
);
11565 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
11569 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
11570 if (offset_expr
.X_op
== O_absent
)
11571 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
11574 gas_assert (offset_expr
.X_op
== O_constant
);
11575 load_register (AT
, &offset_expr
, 0);
11576 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11582 gas_assert (imm_expr
.X_op
== O_absent
11583 && offset_expr
.X_op
== O_symbol
11584 && offset_expr
.X_add_number
== 0);
11585 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
11586 if (strcmp (s
, ".lit8") == 0)
11588 op
[2] = mips_gp_register
;
11589 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
11590 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11591 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11595 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
11597 if (mips_pic
!= NO_PIC
)
11598 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11599 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11602 /* FIXME: This won't work for a 64 bit address. */
11603 macro_build_lui (&offset_expr
, AT
);
11607 offset_reloc
[0] = BFD_RELOC_LO16
;
11608 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11609 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11616 * The MIPS assembler seems to check for X_add_number not
11617 * being double aligned and generating:
11618 * lui at,%hi(foo+1)
11620 * addiu at,at,%lo(foo+1)
11623 * But, the resulting address is the same after relocation so why
11624 * generate the extra instruction?
11626 /* Itbl support may require additional care here. */
11629 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11638 gas_assert (!mips_opts
.micromips
);
11639 /* Itbl support may require additional care here. */
11642 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11662 if (HAVE_64BIT_GPRS
)
11672 if (HAVE_64BIT_GPRS
)
11680 /* Even on a big endian machine $fn comes before $fn+1. We have
11681 to adjust when loading from memory. We set coproc if we must
11682 load $fn+1 first. */
11683 /* Itbl support may require additional care here. */
11684 if (!target_big_endian
)
11688 if (small_offset_p (0, align
, 16))
11691 if (!small_offset_p (4, align
, 16))
11693 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11694 -1, offset_reloc
[0], offset_reloc
[1],
11696 expr1
.X_add_number
= 0;
11700 offset_reloc
[0] = BFD_RELOC_LO16
;
11701 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11702 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11704 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11706 ep
->X_add_number
+= 4;
11707 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11708 offset_reloc
[1], offset_reloc
[2], breg
);
11709 ep
->X_add_number
-= 4;
11710 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11711 offset_reloc
[1], offset_reloc
[2], breg
);
11715 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11716 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11718 ep
->X_add_number
+= 4;
11719 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11720 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11726 if (offset_expr
.X_op
!= O_symbol
11727 && offset_expr
.X_op
!= O_constant
)
11729 as_bad (_("expression too complex"));
11730 offset_expr
.X_op
= O_constant
;
11733 if (HAVE_32BIT_ADDRESSES
11734 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11738 sprintf_vma (value
, offset_expr
.X_add_number
);
11739 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11742 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11744 /* If this is a reference to a GP relative symbol, we want
11745 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11746 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11747 If we have a base register, we use this
11749 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11750 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11751 If this is not a GP relative symbol, we want
11752 lui $at,<sym> (BFD_RELOC_HI16_S)
11753 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11754 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11755 If there is a base register, we add it to $at after the
11756 lui instruction. If there is a constant, we always use
11758 if (offset_expr
.X_op
== O_symbol
11759 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11760 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11762 relax_start (offset_expr
.X_add_symbol
);
11765 tempreg
= mips_gp_register
;
11769 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11770 AT
, breg
, mips_gp_register
);
11775 /* Itbl support may require additional care here. */
11776 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11777 BFD_RELOC_GPREL16
, tempreg
);
11778 offset_expr
.X_add_number
+= 4;
11780 /* Set mips_optimize to 2 to avoid inserting an
11782 hold_mips_optimize
= mips_optimize
;
11784 /* Itbl support may require additional care here. */
11785 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11786 BFD_RELOC_GPREL16
, tempreg
);
11787 mips_optimize
= hold_mips_optimize
;
11791 offset_expr
.X_add_number
-= 4;
11794 if (offset_high_part (offset_expr
.X_add_number
, 16)
11795 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11797 load_address (AT
, &offset_expr
, &used_at
);
11798 offset_expr
.X_op
= O_constant
;
11799 offset_expr
.X_add_number
= 0;
11802 macro_build_lui (&offset_expr
, AT
);
11804 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11805 /* Itbl support may require additional care here. */
11806 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11807 BFD_RELOC_LO16
, AT
);
11808 /* FIXME: How do we handle overflow here? */
11809 offset_expr
.X_add_number
+= 4;
11810 /* Itbl support may require additional care here. */
11811 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11812 BFD_RELOC_LO16
, AT
);
11813 if (mips_relax
.sequence
)
11816 else if (!mips_big_got
)
11818 /* If this is a reference to an external symbol, we want
11819 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11822 <op> op[0]+1,4($at)
11824 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11826 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11827 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11828 If there is a base register we add it to $at before the
11829 lwc1 instructions. If there is a constant we include it
11830 in the lwc1 instructions. */
11832 expr1
.X_add_number
= offset_expr
.X_add_number
;
11833 if (expr1
.X_add_number
< -0x8000
11834 || expr1
.X_add_number
>= 0x8000 - 4)
11835 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11836 load_got_offset (AT
, &offset_expr
);
11839 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11841 /* Set mips_optimize to 2 to avoid inserting an undesired
11843 hold_mips_optimize
= mips_optimize
;
11846 /* Itbl support may require additional care here. */
11847 relax_start (offset_expr
.X_add_symbol
);
11848 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11849 BFD_RELOC_LO16
, AT
);
11850 expr1
.X_add_number
+= 4;
11851 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11852 BFD_RELOC_LO16
, AT
);
11854 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11855 BFD_RELOC_LO16
, AT
);
11856 offset_expr
.X_add_number
+= 4;
11857 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11858 BFD_RELOC_LO16
, AT
);
11861 mips_optimize
= hold_mips_optimize
;
11863 else if (mips_big_got
)
11867 /* If this is a reference to an external symbol, we want
11868 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11870 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11873 <op> op[0]+1,4($at)
11875 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11877 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11878 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11879 If there is a base register we add it to $at before the
11880 lwc1 instructions. If there is a constant we include it
11881 in the lwc1 instructions. */
11883 expr1
.X_add_number
= offset_expr
.X_add_number
;
11884 offset_expr
.X_add_number
= 0;
11885 if (expr1
.X_add_number
< -0x8000
11886 || expr1
.X_add_number
>= 0x8000 - 4)
11887 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11888 gpdelay
= reg_needs_delay (mips_gp_register
);
11889 relax_start (offset_expr
.X_add_symbol
);
11890 macro_build (&offset_expr
, "lui", LUI_FMT
,
11891 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11892 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11893 AT
, AT
, mips_gp_register
);
11894 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11895 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11898 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11899 /* Itbl support may require additional care here. */
11900 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11901 BFD_RELOC_LO16
, AT
);
11902 expr1
.X_add_number
+= 4;
11904 /* Set mips_optimize to 2 to avoid inserting an undesired
11906 hold_mips_optimize
= mips_optimize
;
11908 /* Itbl support may require additional care here. */
11909 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11910 BFD_RELOC_LO16
, AT
);
11911 mips_optimize
= hold_mips_optimize
;
11912 expr1
.X_add_number
-= 4;
11915 offset_expr
.X_add_number
= expr1
.X_add_number
;
11917 macro_build (NULL
, "nop", "");
11918 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11919 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11922 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11923 /* Itbl support may require additional care here. */
11924 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11925 BFD_RELOC_LO16
, AT
);
11926 offset_expr
.X_add_number
+= 4;
11928 /* Set mips_optimize to 2 to avoid inserting an undesired
11930 hold_mips_optimize
= mips_optimize
;
11932 /* Itbl support may require additional care here. */
11933 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11934 BFD_RELOC_LO16
, AT
);
11935 mips_optimize
= hold_mips_optimize
;
11954 /* New code added to support COPZ instructions.
11955 This code builds table entries out of the macros in mip_opcodes.
11956 R4000 uses interlocks to handle coproc delays.
11957 Other chips (like the R3000) require nops to be inserted for delays.
11959 FIXME: Currently, we require that the user handle delays.
11960 In order to fill delay slots for non-interlocked chips,
11961 we must have a way to specify delays based on the coprocessor.
11962 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11963 What are the side-effects of the cop instruction?
11964 What cache support might we have and what are its effects?
11965 Both coprocessor & memory require delays. how long???
11966 What registers are read/set/modified?
11968 If an itbl is provided to interpret cop instructions,
11969 this knowledge can be encoded in the itbl spec. */
11983 gas_assert (!mips_opts
.micromips
);
11984 /* For now we just do C (same as Cz). The parameter will be
11985 stored in insn_opcode by mips_ip. */
11986 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11990 move_register (op
[0], op
[1]);
11994 gas_assert (mips_opts
.micromips
);
11995 gas_assert (mips_opts
.insn32
);
11996 move_register (micromips_to_32_reg_h_map1
[op
[0]],
11997 micromips_to_32_reg_m_map
[op
[1]]);
11998 move_register (micromips_to_32_reg_h_map2
[op
[0]],
11999 micromips_to_32_reg_n_map
[op
[2]]);
12005 if (mips_opts
.arch
== CPU_R5900
)
12006 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12010 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12011 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12018 /* The MIPS assembler some times generates shifts and adds. I'm
12019 not trying to be that fancy. GCC should do this for us
12022 load_register (AT
, &imm_expr
, dbl
);
12023 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12024 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12037 start_noreorder ();
12040 load_register (AT
, &imm_expr
, dbl
);
12041 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12042 op
[1], imm
? AT
: op
[2]);
12043 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12044 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12045 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12047 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12050 if (mips_opts
.micromips
)
12051 micromips_label_expr (&label_expr
);
12053 label_expr
.X_add_number
= 8;
12054 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12055 macro_build (NULL
, "nop", "");
12056 macro_build (NULL
, "break", BRK_FMT
, 6);
12057 if (mips_opts
.micromips
)
12058 micromips_add_label ();
12061 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12074 start_noreorder ();
12077 load_register (AT
, &imm_expr
, dbl
);
12078 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12079 op
[1], imm
? AT
: op
[2]);
12080 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12081 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12083 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12086 if (mips_opts
.micromips
)
12087 micromips_label_expr (&label_expr
);
12089 label_expr
.X_add_number
= 8;
12090 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12091 macro_build (NULL
, "nop", "");
12092 macro_build (NULL
, "break", BRK_FMT
, 6);
12093 if (mips_opts
.micromips
)
12094 micromips_add_label ();
12100 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12102 if (op
[0] == op
[1])
12109 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12110 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12114 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12115 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12116 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12117 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12121 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12123 if (op
[0] == op
[1])
12130 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12131 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12135 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12136 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12137 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12138 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12147 rot
= imm_expr
.X_add_number
& 0x3f;
12148 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12150 rot
= (64 - rot
) & 0x3f;
12152 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12154 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12159 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12162 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12163 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12166 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12167 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12168 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12176 rot
= imm_expr
.X_add_number
& 0x1f;
12177 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12179 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12180 (32 - rot
) & 0x1f);
12185 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12189 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12190 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12191 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12196 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12198 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12202 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12203 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12204 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12205 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12209 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12211 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12215 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12216 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12217 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12218 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12227 rot
= imm_expr
.X_add_number
& 0x3f;
12228 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12231 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12233 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12238 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12241 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12242 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12245 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12246 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12247 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12255 rot
= imm_expr
.X_add_number
& 0x1f;
12256 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12258 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12263 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12267 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12268 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12269 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12275 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12276 else if (op
[2] == 0)
12277 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12280 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12281 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12286 if (imm_expr
.X_add_number
== 0)
12288 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12293 as_warn (_("instruction %s: result is always false"),
12294 ip
->insn_mo
->name
);
12295 move_register (op
[0], 0);
12298 if (CPU_HAS_SEQ (mips_opts
.arch
)
12299 && -512 <= imm_expr
.X_add_number
12300 && imm_expr
.X_add_number
< 512)
12302 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12303 (int) imm_expr
.X_add_number
);
12306 if (imm_expr
.X_add_number
>= 0
12307 && imm_expr
.X_add_number
< 0x10000)
12308 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12309 else if (imm_expr
.X_add_number
> -0x8000
12310 && imm_expr
.X_add_number
< 0)
12312 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12313 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12314 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12316 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12319 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12320 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12325 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12326 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12329 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12332 case M_SGE
: /* X >= Y <==> not (X < Y) */
12338 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12339 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12342 case M_SGE_I
: /* X >= I <==> not (X < I) */
12344 if (imm_expr
.X_add_number
>= -0x8000
12345 && imm_expr
.X_add_number
< 0x8000)
12346 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12347 op
[0], op
[1], BFD_RELOC_LO16
);
12350 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12351 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12355 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12358 case M_SGT
: /* X > Y <==> Y < X */
12364 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12367 case M_SGT_I
: /* X > I <==> I < X */
12374 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12375 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12378 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12384 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12385 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12388 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12395 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12396 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12397 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12401 if (imm_expr
.X_add_number
>= -0x8000
12402 && imm_expr
.X_add_number
< 0x8000)
12404 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12409 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12410 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12414 if (imm_expr
.X_add_number
>= -0x8000
12415 && imm_expr
.X_add_number
< 0x8000)
12417 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12422 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12423 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12428 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12429 else if (op
[2] == 0)
12430 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12433 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12434 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12439 if (imm_expr
.X_add_number
== 0)
12441 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12446 as_warn (_("instruction %s: result is always true"),
12447 ip
->insn_mo
->name
);
12448 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
12449 op
[0], 0, BFD_RELOC_LO16
);
12452 if (CPU_HAS_SEQ (mips_opts
.arch
)
12453 && -512 <= imm_expr
.X_add_number
12454 && imm_expr
.X_add_number
< 512)
12456 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
12457 (int) imm_expr
.X_add_number
);
12460 if (imm_expr
.X_add_number
>= 0
12461 && imm_expr
.X_add_number
< 0x10000)
12463 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
12466 else if (imm_expr
.X_add_number
> -0x8000
12467 && imm_expr
.X_add_number
< 0)
12469 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12470 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12471 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12473 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12476 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12477 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
12482 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12483 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12486 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12501 if (!mips_opts
.micromips
)
12503 if (imm_expr
.X_add_number
> -0x200
12504 && imm_expr
.X_add_number
<= 0x200)
12506 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
12507 (int) -imm_expr
.X_add_number
);
12516 if (imm_expr
.X_add_number
> -0x8000
12517 && imm_expr
.X_add_number
<= 0x8000)
12519 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12520 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12525 load_register (AT
, &imm_expr
, dbl
);
12526 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
12548 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12549 macro_build (NULL
, s
, "s,t", op
[0], AT
);
12554 gas_assert (!mips_opts
.micromips
);
12555 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
12559 * Is the double cfc1 instruction a bug in the mips assembler;
12560 * or is there a reason for it?
12562 start_noreorder ();
12563 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12564 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12565 macro_build (NULL
, "nop", "");
12566 expr1
.X_add_number
= 3;
12567 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
12568 expr1
.X_add_number
= 2;
12569 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
12570 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
12571 macro_build (NULL
, "nop", "");
12572 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
12574 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
12575 macro_build (NULL
, "nop", "");
12592 offbits
= (mips_opts
.micromips
? 12 : 16);
12598 offbits
= (mips_opts
.micromips
? 12 : 16);
12610 offbits
= (mips_opts
.micromips
? 12 : 16);
12617 offbits
= (mips_opts
.micromips
? 12 : 16);
12623 large_offset
= !small_offset_p (off
, align
, offbits
);
12625 expr1
.X_add_number
= 0;
12630 if (small_offset_p (0, align
, 16))
12631 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
12632 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
12635 load_address (tempreg
, ep
, &used_at
);
12637 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12638 tempreg
, tempreg
, breg
);
12640 offset_reloc
[0] = BFD_RELOC_LO16
;
12641 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12642 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12647 else if (!ust
&& op
[0] == breg
)
12658 if (!target_big_endian
)
12659 ep
->X_add_number
+= off
;
12661 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
12663 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12664 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12666 if (!target_big_endian
)
12667 ep
->X_add_number
-= off
;
12669 ep
->X_add_number
+= off
;
12671 macro_build (NULL
, s2
, "t,~(b)",
12672 tempreg
, (int) ep
->X_add_number
, breg
);
12674 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12675 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12677 /* If necessary, move the result in tempreg to the final destination. */
12678 if (!ust
&& op
[0] != tempreg
)
12680 /* Protect second load's delay slot. */
12682 move_register (op
[0], tempreg
);
12688 if (target_big_endian
== ust
)
12689 ep
->X_add_number
+= off
;
12690 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12691 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12692 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12694 /* For halfword transfers we need a temporary register to shuffle
12695 bytes. Unfortunately for M_USH_A we have none available before
12696 the next store as AT holds the base address. We deal with this
12697 case by clobbering TREG and then restoring it as with ULH. */
12698 tempreg
= ust
== large_offset
? op
[0] : AT
;
12700 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12702 if (target_big_endian
== ust
)
12703 ep
->X_add_number
-= off
;
12705 ep
->X_add_number
+= off
;
12706 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12707 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12709 /* For M_USH_A re-retrieve the LSB. */
12710 if (ust
&& large_offset
)
12712 if (target_big_endian
)
12713 ep
->X_add_number
+= off
;
12715 ep
->X_add_number
-= off
;
12716 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12717 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12719 /* For ULH and M_USH_A OR the LSB in. */
12720 if (!ust
|| large_offset
)
12722 tempreg
= !large_offset
? AT
: op
[0];
12723 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12724 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12729 /* FIXME: Check if this is one of the itbl macros, since they
12730 are added dynamically. */
12731 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
12734 if (!mips_opts
.at
&& used_at
)
12735 as_bad (_("macro used $at after \".set noat\""));
12738 /* Implement macros in mips16 mode. */
12741 mips16_macro (struct mips_cl_insn
*ip
)
12743 const struct mips_operand_array
*operands
;
12748 const char *s
, *s2
, *s3
;
12749 unsigned int op
[MAX_OPERANDS
];
12752 mask
= ip
->insn_mo
->mask
;
12754 operands
= insn_operands (ip
);
12755 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12756 if (operands
->operand
[i
])
12757 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12761 expr1
.X_op
= O_constant
;
12762 expr1
.X_op_symbol
= NULL
;
12763 expr1
.X_add_symbol
= NULL
;
12764 expr1
.X_add_number
= 1;
12783 start_noreorder ();
12784 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12785 expr1
.X_add_number
= 2;
12786 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12787 macro_build (NULL
, "break", "6", 7);
12789 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12790 since that causes an overflow. We should do that as well,
12791 but I don't see how to do the comparisons without a temporary
12794 macro_build (NULL
, s
, "x", op
[0]);
12813 start_noreorder ();
12814 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12815 expr1
.X_add_number
= 2;
12816 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12817 macro_build (NULL
, "break", "6", 7);
12819 macro_build (NULL
, s2
, "x", op
[0]);
12825 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12826 macro_build (NULL
, "mflo", "x", op
[0]);
12834 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12835 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12839 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12840 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12844 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12845 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12867 goto do_reverse_branch
;
12871 goto do_reverse_branch
;
12883 goto do_reverse_branch
;
12894 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12895 macro_build (&offset_expr
, s2
, "p");
12922 goto do_addone_branch_i
;
12927 goto do_addone_branch_i
;
12942 goto do_addone_branch_i
;
12948 do_addone_branch_i
:
12949 ++imm_expr
.X_add_number
;
12952 macro_build (&imm_expr
, s
, s3
, op
[0]);
12953 macro_build (&offset_expr
, s2
, "p");
12957 expr1
.X_add_number
= 0;
12958 macro_build (&expr1
, "slti", "x,8", op
[1]);
12959 if (op
[0] != op
[1])
12960 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12961 expr1
.X_add_number
= 2;
12962 macro_build (&expr1
, "bteqz", "p");
12963 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12968 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12969 opcode bits in *OPCODE_EXTRA. */
12971 static struct mips_opcode
*
12972 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
12973 ssize_t length
, unsigned int *opcode_extra
)
12975 char *name
, *dot
, *p
;
12976 unsigned int mask
, suffix
;
12978 struct mips_opcode
*insn
;
12980 /* Make a copy of the instruction so that we can fiddle with it. */
12981 name
= alloca (length
+ 1);
12982 memcpy (name
, start
, length
);
12983 name
[length
] = '\0';
12985 /* Look up the instruction as-is. */
12986 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12990 dot
= strchr (name
, '.');
12993 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12994 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
12995 if (*p
== 0 && mask
!= 0)
12998 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13000 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13002 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13008 if (mips_opts
.micromips
)
13010 /* See if there's an instruction size override suffix,
13011 either `16' or `32', at the end of the mnemonic proper,
13012 that defines the operation, i.e. before the first `.'
13013 character if any. Strip it and retry. */
13014 opend
= dot
!= NULL
? dot
- name
: length
;
13015 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13017 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13023 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13024 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13027 forced_insn_length
= suffix
;
13036 /* Assemble an instruction into its binary format. If the instruction
13037 is a macro, set imm_expr and offset_expr to the values associated
13038 with "I" and "A" operands respectively. Otherwise store the value
13039 of the relocatable field (if any) in offset_expr. In both cases
13040 set offset_reloc to the relocation operators applied to offset_expr. */
13043 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13045 const struct mips_opcode
*first
, *past
;
13046 struct hash_control
*hash
;
13049 struct mips_operand_token
*tokens
;
13050 unsigned int opcode_extra
;
13052 if (mips_opts
.micromips
)
13054 hash
= micromips_op_hash
;
13055 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13060 past
= &mips_opcodes
[NUMOPCODES
];
13062 forced_insn_length
= 0;
13065 /* We first try to match an instruction up to a space or to the end. */
13066 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13069 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13072 set_insn_error (0, _("unrecognized opcode"));
13076 if (strcmp (first
->name
, "li.s") == 0)
13078 else if (strcmp (first
->name
, "li.d") == 0)
13082 tokens
= mips_parse_arguments (str
+ end
, format
);
13086 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13087 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13088 set_insn_error (0, _("invalid operands"));
13090 obstack_free (&mips_operand_tokens
, tokens
);
13093 /* As for mips_ip, but used when assembling MIPS16 code.
13094 Also set forced_insn_length to the resulting instruction size in
13095 bytes if the user explicitly requested a small or extended instruction. */
13098 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13101 struct mips_opcode
*first
;
13102 struct mips_operand_token
*tokens
;
13104 forced_insn_length
= 0;
13106 for (s
= str
; ISLOWER (*s
); ++s
)
13120 if (s
[1] == 't' && s
[2] == ' ')
13122 forced_insn_length
= 2;
13126 else if (s
[1] == 'e' && s
[2] == ' ')
13128 forced_insn_length
= 4;
13132 /* Fall through. */
13134 set_insn_error (0, _("unrecognized opcode"));
13138 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13139 forced_insn_length
= 2;
13142 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13147 set_insn_error (0, _("unrecognized opcode"));
13151 tokens
= mips_parse_arguments (s
, 0);
13155 if (!match_mips16_insns (insn
, first
, tokens
))
13156 set_insn_error (0, _("invalid operands"));
13158 obstack_free (&mips_operand_tokens
, tokens
);
13161 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13162 NBITS is the number of significant bits in VAL. */
13164 static unsigned long
13165 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13170 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13173 else if (nbits
== 15)
13175 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13180 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13183 return (extval
<< 16) | val
;
13186 /* Like decode_mips16_operand, but require the operand to be defined and
13187 require it to be an integer. */
13189 static const struct mips_int_operand
*
13190 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13192 const struct mips_operand
*operand
;
13194 operand
= decode_mips16_operand (type
, extended_p
);
13195 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13197 return (const struct mips_int_operand
*) operand
;
13200 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13203 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13204 bfd_reloc_code_real_type reloc
, offsetT sval
)
13206 int min_val
, max_val
;
13208 min_val
= mips_int_operand_min (operand
);
13209 max_val
= mips_int_operand_max (operand
);
13210 if (reloc
!= BFD_RELOC_UNUSED
)
13213 sval
= SEXT_16BIT (sval
);
13218 return (sval
>= min_val
13220 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13223 /* Install immediate value VAL into MIPS16 instruction *INSN,
13224 extending it if necessary. The instruction in *INSN may
13225 already be extended.
13227 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13228 if none. In the former case, VAL is a 16-bit number with no
13229 defined signedness.
13231 TYPE is the type of the immediate field. USER_INSN_LENGTH
13232 is the length that the user requested, or 0 if none. */
13235 mips16_immed (char *file
, unsigned int line
, int type
,
13236 bfd_reloc_code_real_type reloc
, offsetT val
,
13237 unsigned int user_insn_length
, unsigned long *insn
)
13239 const struct mips_int_operand
*operand
;
13240 unsigned int uval
, length
;
13242 operand
= mips16_immed_operand (type
, FALSE
);
13243 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13245 /* We need an extended instruction. */
13246 if (user_insn_length
== 2)
13247 as_bad_where (file
, line
, _("invalid unextended operand value"));
13249 *insn
|= MIPS16_EXTEND
;
13251 else if (user_insn_length
== 4)
13253 /* The operand doesn't force an unextended instruction to be extended.
13254 Warn if the user wanted an extended instruction anyway. */
13255 *insn
|= MIPS16_EXTEND
;
13256 as_warn_where (file
, line
,
13257 _("extended operand requested but not required"));
13260 length
= mips16_opcode_length (*insn
);
13263 operand
= mips16_immed_operand (type
, TRUE
);
13264 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13265 as_bad_where (file
, line
,
13266 _("operand value out of range for instruction"));
13268 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13270 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13272 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13275 struct percent_op_match
13278 bfd_reloc_code_real_type reloc
;
13281 static const struct percent_op_match mips_percent_op
[] =
13283 {"%lo", BFD_RELOC_LO16
},
13284 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13285 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13286 {"%call16", BFD_RELOC_MIPS_CALL16
},
13287 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13288 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13289 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13290 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13291 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13292 {"%got", BFD_RELOC_MIPS_GOT16
},
13293 {"%gp_rel", BFD_RELOC_GPREL16
},
13294 {"%half", BFD_RELOC_16
},
13295 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13296 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13297 {"%neg", BFD_RELOC_MIPS_SUB
},
13298 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13299 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13300 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13301 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13302 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13303 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13304 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13305 {"%hi", BFD_RELOC_HI16_S
}
13308 static const struct percent_op_match mips16_percent_op
[] =
13310 {"%lo", BFD_RELOC_MIPS16_LO16
},
13311 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13312 {"%got", BFD_RELOC_MIPS16_GOT16
},
13313 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13314 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13315 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13316 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13317 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13318 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13319 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13320 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13321 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13325 /* Return true if *STR points to a relocation operator. When returning true,
13326 move *STR over the operator and store its relocation code in *RELOC.
13327 Leave both *STR and *RELOC alone when returning false. */
13330 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13332 const struct percent_op_match
*percent_op
;
13335 if (mips_opts
.mips16
)
13337 percent_op
= mips16_percent_op
;
13338 limit
= ARRAY_SIZE (mips16_percent_op
);
13342 percent_op
= mips_percent_op
;
13343 limit
= ARRAY_SIZE (mips_percent_op
);
13346 for (i
= 0; i
< limit
; i
++)
13347 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13349 int len
= strlen (percent_op
[i
].str
);
13351 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13354 *str
+= strlen (percent_op
[i
].str
);
13355 *reloc
= percent_op
[i
].reloc
;
13357 /* Check whether the output BFD supports this relocation.
13358 If not, issue an error and fall back on something safe. */
13359 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13361 as_bad (_("relocation %s isn't supported by the current ABI"),
13362 percent_op
[i
].str
);
13363 *reloc
= BFD_RELOC_UNUSED
;
13371 /* Parse string STR as a 16-bit relocatable operand. Store the
13372 expression in *EP and the relocations in the array starting
13373 at RELOC. Return the number of relocation operators used.
13375 On exit, EXPR_END points to the first character after the expression. */
13378 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13381 bfd_reloc_code_real_type reversed_reloc
[3];
13382 size_t reloc_index
, i
;
13383 int crux_depth
, str_depth
;
13386 /* Search for the start of the main expression, recoding relocations
13387 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13388 of the main expression and with CRUX_DEPTH containing the number
13389 of open brackets at that point. */
13396 crux_depth
= str_depth
;
13398 /* Skip over whitespace and brackets, keeping count of the number
13400 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13405 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13406 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13408 my_getExpression (ep
, crux
);
13411 /* Match every open bracket. */
13412 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13416 if (crux_depth
> 0)
13417 as_bad (_("unclosed '('"));
13421 if (reloc_index
!= 0)
13423 prev_reloc_op_frag
= frag_now
;
13424 for (i
= 0; i
< reloc_index
; i
++)
13425 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13428 return reloc_index
;
13432 my_getExpression (expressionS
*ep
, char *str
)
13436 save_in
= input_line_pointer
;
13437 input_line_pointer
= str
;
13439 expr_end
= input_line_pointer
;
13440 input_line_pointer
= save_in
;
13444 md_atof (int type
, char *litP
, int *sizeP
)
13446 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13450 md_number_to_chars (char *buf
, valueT val
, int n
)
13452 if (target_big_endian
)
13453 number_to_chars_bigendian (buf
, val
, n
);
13455 number_to_chars_littleendian (buf
, val
, n
);
13458 static int support_64bit_objects(void)
13460 const char **list
, **l
;
13463 list
= bfd_target_list ();
13464 for (l
= list
; *l
!= NULL
; l
++)
13465 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13466 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13468 yes
= (*l
!= NULL
);
13473 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13474 NEW_VALUE. Warn if another value was already specified. Note:
13475 we have to defer parsing the -march and -mtune arguments in order
13476 to handle 'from-abi' correctly, since the ABI might be specified
13477 in a later argument. */
13480 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13482 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13483 as_warn (_("a different %s was already specified, is now %s"),
13484 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13487 *string_ptr
= new_value
;
13491 md_parse_option (int c
, char *arg
)
13495 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13496 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13498 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13499 c
== mips_ases
[i
].option_on
);
13505 case OPTION_CONSTRUCT_FLOATS
:
13506 mips_disable_float_construction
= 0;
13509 case OPTION_NO_CONSTRUCT_FLOATS
:
13510 mips_disable_float_construction
= 1;
13522 target_big_endian
= 1;
13526 target_big_endian
= 0;
13532 else if (arg
[0] == '0')
13534 else if (arg
[0] == '1')
13544 mips_debug
= atoi (arg
);
13548 file_mips_opts
.isa
= ISA_MIPS1
;
13552 file_mips_opts
.isa
= ISA_MIPS2
;
13556 file_mips_opts
.isa
= ISA_MIPS3
;
13560 file_mips_opts
.isa
= ISA_MIPS4
;
13564 file_mips_opts
.isa
= ISA_MIPS5
;
13567 case OPTION_MIPS32
:
13568 file_mips_opts
.isa
= ISA_MIPS32
;
13571 case OPTION_MIPS32R2
:
13572 file_mips_opts
.isa
= ISA_MIPS32R2
;
13575 case OPTION_MIPS32R3
:
13576 file_mips_opts
.isa
= ISA_MIPS32R3
;
13579 case OPTION_MIPS32R5
:
13580 file_mips_opts
.isa
= ISA_MIPS32R5
;
13583 case OPTION_MIPS64R2
:
13584 file_mips_opts
.isa
= ISA_MIPS64R2
;
13587 case OPTION_MIPS64R3
:
13588 file_mips_opts
.isa
= ISA_MIPS64R3
;
13591 case OPTION_MIPS64R5
:
13592 file_mips_opts
.isa
= ISA_MIPS64R5
;
13595 case OPTION_MIPS64
:
13596 file_mips_opts
.isa
= ISA_MIPS64
;
13600 mips_set_option_string (&mips_tune_string
, arg
);
13604 mips_set_option_string (&mips_arch_string
, arg
);
13608 mips_set_option_string (&mips_arch_string
, "4650");
13609 mips_set_option_string (&mips_tune_string
, "4650");
13612 case OPTION_NO_M4650
:
13616 mips_set_option_string (&mips_arch_string
, "4010");
13617 mips_set_option_string (&mips_tune_string
, "4010");
13620 case OPTION_NO_M4010
:
13624 mips_set_option_string (&mips_arch_string
, "4100");
13625 mips_set_option_string (&mips_tune_string
, "4100");
13628 case OPTION_NO_M4100
:
13632 mips_set_option_string (&mips_arch_string
, "3900");
13633 mips_set_option_string (&mips_tune_string
, "3900");
13636 case OPTION_NO_M3900
:
13639 case OPTION_MICROMIPS
:
13640 if (mips_opts
.mips16
== 1)
13642 as_bad (_("-mmicromips cannot be used with -mips16"));
13645 mips_opts
.micromips
= 1;
13646 mips_no_prev_insn ();
13649 case OPTION_NO_MICROMIPS
:
13650 mips_opts
.micromips
= 0;
13651 mips_no_prev_insn ();
13654 case OPTION_MIPS16
:
13655 if (mips_opts
.micromips
== 1)
13657 as_bad (_("-mips16 cannot be used with -micromips"));
13660 mips_opts
.mips16
= 1;
13661 mips_no_prev_insn ();
13664 case OPTION_NO_MIPS16
:
13665 mips_opts
.mips16
= 0;
13666 mips_no_prev_insn ();
13669 case OPTION_FIX_24K
:
13673 case OPTION_NO_FIX_24K
:
13677 case OPTION_FIX_RM7000
:
13678 mips_fix_rm7000
= 1;
13681 case OPTION_NO_FIX_RM7000
:
13682 mips_fix_rm7000
= 0;
13685 case OPTION_FIX_LOONGSON2F_JUMP
:
13686 mips_fix_loongson2f_jump
= TRUE
;
13689 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13690 mips_fix_loongson2f_jump
= FALSE
;
13693 case OPTION_FIX_LOONGSON2F_NOP
:
13694 mips_fix_loongson2f_nop
= TRUE
;
13697 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13698 mips_fix_loongson2f_nop
= FALSE
;
13701 case OPTION_FIX_VR4120
:
13702 mips_fix_vr4120
= 1;
13705 case OPTION_NO_FIX_VR4120
:
13706 mips_fix_vr4120
= 0;
13709 case OPTION_FIX_VR4130
:
13710 mips_fix_vr4130
= 1;
13713 case OPTION_NO_FIX_VR4130
:
13714 mips_fix_vr4130
= 0;
13717 case OPTION_FIX_CN63XXP1
:
13718 mips_fix_cn63xxp1
= TRUE
;
13721 case OPTION_NO_FIX_CN63XXP1
:
13722 mips_fix_cn63xxp1
= FALSE
;
13725 case OPTION_RELAX_BRANCH
:
13726 mips_relax_branch
= 1;
13729 case OPTION_NO_RELAX_BRANCH
:
13730 mips_relax_branch
= 0;
13733 case OPTION_INSN32
:
13734 mips_opts
.insn32
= TRUE
;
13737 case OPTION_NO_INSN32
:
13738 mips_opts
.insn32
= FALSE
;
13741 case OPTION_MSHARED
:
13742 mips_in_shared
= TRUE
;
13745 case OPTION_MNO_SHARED
:
13746 mips_in_shared
= FALSE
;
13749 case OPTION_MSYM32
:
13750 mips_opts
.sym32
= TRUE
;
13753 case OPTION_MNO_SYM32
:
13754 mips_opts
.sym32
= FALSE
;
13757 /* When generating ELF code, we permit -KPIC and -call_shared to
13758 select SVR4_PIC, and -non_shared to select no PIC. This is
13759 intended to be compatible with Irix 5. */
13760 case OPTION_CALL_SHARED
:
13761 mips_pic
= SVR4_PIC
;
13762 mips_abicalls
= TRUE
;
13765 case OPTION_CALL_NONPIC
:
13767 mips_abicalls
= TRUE
;
13770 case OPTION_NON_SHARED
:
13772 mips_abicalls
= FALSE
;
13775 /* The -xgot option tells the assembler to use 32 bit offsets
13776 when accessing the got in SVR4_PIC mode. It is for Irix
13783 g_switch_value
= atoi (arg
);
13787 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13790 mips_abi
= O32_ABI
;
13794 mips_abi
= N32_ABI
;
13798 mips_abi
= N64_ABI
;
13799 if (!support_64bit_objects())
13800 as_fatal (_("no compiled in support for 64 bit object file format"));
13804 file_mips_opts
.gp32
= 1;
13808 file_mips_opts
.gp32
= 0;
13812 file_mips_opts
.fp
= 32;
13816 file_mips_opts
.fp
= 64;
13819 case OPTION_SINGLE_FLOAT
:
13820 file_mips_opts
.single_float
= 1;
13823 case OPTION_DOUBLE_FLOAT
:
13824 file_mips_opts
.single_float
= 0;
13827 case OPTION_SOFT_FLOAT
:
13828 file_mips_opts
.soft_float
= 1;
13831 case OPTION_HARD_FLOAT
:
13832 file_mips_opts
.soft_float
= 0;
13836 if (strcmp (arg
, "32") == 0)
13837 mips_abi
= O32_ABI
;
13838 else if (strcmp (arg
, "o64") == 0)
13839 mips_abi
= O64_ABI
;
13840 else if (strcmp (arg
, "n32") == 0)
13841 mips_abi
= N32_ABI
;
13842 else if (strcmp (arg
, "64") == 0)
13844 mips_abi
= N64_ABI
;
13845 if (! support_64bit_objects())
13846 as_fatal (_("no compiled in support for 64 bit object file "
13849 else if (strcmp (arg
, "eabi") == 0)
13850 mips_abi
= EABI_ABI
;
13853 as_fatal (_("invalid abi -mabi=%s"), arg
);
13858 case OPTION_M7000_HILO_FIX
:
13859 mips_7000_hilo_fix
= TRUE
;
13862 case OPTION_MNO_7000_HILO_FIX
:
13863 mips_7000_hilo_fix
= FALSE
;
13866 case OPTION_MDEBUG
:
13867 mips_flag_mdebug
= TRUE
;
13870 case OPTION_NO_MDEBUG
:
13871 mips_flag_mdebug
= FALSE
;
13875 mips_flag_pdr
= TRUE
;
13878 case OPTION_NO_PDR
:
13879 mips_flag_pdr
= FALSE
;
13882 case OPTION_MVXWORKS_PIC
:
13883 mips_pic
= VXWORKS_PIC
;
13887 if (strcmp (arg
, "2008") == 0)
13888 mips_flag_nan2008
= TRUE
;
13889 else if (strcmp (arg
, "legacy") == 0)
13890 mips_flag_nan2008
= FALSE
;
13893 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
13902 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13907 /* Set up globals to generate code for the ISA or processor
13908 described by INFO. */
13911 mips_set_architecture (const struct mips_cpu_info
*info
)
13915 file_mips_opts
.arch
= info
->cpu
;
13916 mips_opts
.arch
= info
->cpu
;
13917 mips_opts
.isa
= info
->isa
;
13922 /* Likewise for tuning. */
13925 mips_set_tune (const struct mips_cpu_info
*info
)
13928 mips_tune
= info
->cpu
;
13933 mips_after_parse_args (void)
13935 const struct mips_cpu_info
*arch_info
= 0;
13936 const struct mips_cpu_info
*tune_info
= 0;
13938 /* GP relative stuff not working for PE */
13939 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13941 if (g_switch_seen
&& g_switch_value
!= 0)
13942 as_bad (_("-G not supported in this configuration"));
13943 g_switch_value
= 0;
13946 if (mips_abi
== NO_ABI
)
13947 mips_abi
= MIPS_DEFAULT_ABI
;
13949 /* The following code determines the architecture and register size.
13950 Similar code was added to GCC 3.3 (see override_options() in
13951 config/mips/mips.c). The GAS and GCC code should be kept in sync
13952 as much as possible. */
13954 if (mips_arch_string
!= 0)
13955 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13957 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
13959 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
13960 ISA level specified by -mipsN, while arch_info->isa contains
13961 the -march selection (if any). */
13962 if (arch_info
!= 0)
13964 /* -march takes precedence over -mipsN, since it is more descriptive.
13965 There's no harm in specifying both as long as the ISA levels
13967 if (file_mips_opts
.isa
!= arch_info
->isa
)
13968 as_bad (_("-%s conflicts with the other architecture options,"
13969 " which imply -%s"),
13970 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
13971 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13974 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
13977 if (arch_info
== 0)
13979 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13980 gas_assert (arch_info
);
13983 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13984 as_bad (_("-march=%s is not compatible with the selected ABI"),
13987 mips_set_architecture (arch_info
);
13989 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
13991 if (mips_tune_string
!= 0)
13992 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13994 if (tune_info
== 0)
13995 mips_set_tune (arch_info
);
13997 mips_set_tune (tune_info
);
13999 if (file_mips_opts
.gp32
>= 0)
14001 /* The user specified the size of the integer registers. Make sure
14002 it agrees with the ABI and ISA. */
14003 if (file_mips_opts
.gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14004 as_bad (_("-mgp64 used with a 32-bit processor"));
14005 else if (file_mips_opts
.gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
14006 as_bad (_("-mgp32 used with a 64-bit ABI"));
14007 else if (file_mips_opts
.gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
14008 as_bad (_("-mgp64 used with a 32-bit ABI"));
14012 /* Infer the integer register size from the ABI and processor.
14013 Restrict ourselves to 32-bit registers if that's all the
14014 processor has, or if the ABI cannot handle 64-bit registers. */
14015 file_mips_opts
.gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
14016 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
14019 switch (file_mips_opts
.fp
)
14023 /* No user specified float register size.
14024 ??? GAS treats single-float processors as though they had 64-bit
14025 float registers (although it complains when double-precision
14026 instructions are used). As things stand, saying they have 32-bit
14027 registers would lead to spurious "register must be even" messages.
14028 So here we assume float registers are never smaller than the
14030 if (file_mips_opts
.gp32
== 0)
14031 /* 64-bit integer registers implies 64-bit float registers. */
14032 file_mips_opts
.fp
= 64;
14033 else if ((mips_opts
.ase
& FP64_ASES
)
14034 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14035 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14036 file_mips_opts
.fp
= 64;
14038 /* 32-bit float registers. */
14039 file_mips_opts
.fp
= 32;
14042 /* The user specified the size of the float registers. Check if it
14043 agrees with the ABI and ISA. */
14045 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14046 as_bad (_("-mfp64 used with a 32-bit fpu"));
14047 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
14048 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
14049 as_warn (_("-mfp64 used with a 32-bit ABI"));
14052 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14053 as_warn (_("-mfp32 used with a 64-bit ABI"));
14057 /* End of GCC-shared inference code. */
14059 /* This flag is set when we have a 64-bit capable CPU but use only
14060 32-bit wide registers. Note that EABI does not use it. */
14061 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
14062 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp32
== 1)
14063 || mips_abi
== O32_ABI
))
14064 mips_32bitmode
= 1;
14066 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
14067 as_bad (_("trap exception not supported at ISA 1"));
14069 /* If the selected architecture includes support for ASEs, enable
14070 generation of code for them. */
14071 if (mips_opts
.mips16
== -1)
14072 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
14073 if (mips_opts
.micromips
== -1)
14074 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
14077 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14078 ASEs from being selected implicitly. */
14079 if (file_mips_opts
.fp
!= 64)
14080 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
14082 /* If the user didn't explicitly select or deselect a particular ASE,
14083 use the default setting for the CPU. */
14084 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
14086 file_mips_opts
.isa
= mips_opts
.isa
;
14087 file_mips_opts
.ase
= mips_opts
.ase
;
14088 mips_opts
.gp32
= file_mips_opts
.gp32
;
14089 mips_opts
.fp
= file_mips_opts
.fp
;
14090 mips_opts
.soft_float
= file_mips_opts
.soft_float
;
14091 mips_opts
.single_float
= file_mips_opts
.single_float
;
14093 mips_check_isa_supports_ases ();
14095 if (mips_flag_mdebug
< 0)
14096 mips_flag_mdebug
= 0;
14100 mips_init_after_args (void)
14102 /* initialize opcodes */
14103 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14104 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14108 md_pcrel_from (fixS
*fixP
)
14110 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14111 switch (fixP
->fx_r_type
)
14113 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14114 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14115 /* Return the address of the delay slot. */
14118 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14119 case BFD_RELOC_MICROMIPS_JMP
:
14120 case BFD_RELOC_16_PCREL_S2
:
14121 case BFD_RELOC_MIPS_JMP
:
14122 /* Return the address of the delay slot. */
14130 /* This is called before the symbol table is processed. In order to
14131 work with gcc when using mips-tfile, we must keep all local labels.
14132 However, in other cases, we want to discard them. If we were
14133 called with -g, but we didn't see any debugging information, it may
14134 mean that gcc is smuggling debugging information through to
14135 mips-tfile, in which case we must generate all local labels. */
14138 mips_frob_file_before_adjust (void)
14140 #ifndef NO_ECOFF_DEBUGGING
14141 if (ECOFF_DEBUGGING
14143 && ! ecoff_debugging_seen
)
14144 flag_keep_locals
= 1;
14148 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14149 the corresponding LO16 reloc. This is called before md_apply_fix and
14150 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14151 relocation operators.
14153 For our purposes, a %lo() expression matches a %got() or %hi()
14156 (a) it refers to the same symbol; and
14157 (b) the offset applied in the %lo() expression is no lower than
14158 the offset applied in the %got() or %hi().
14160 (b) allows us to cope with code like:
14163 lh $4,%lo(foo+2)($4)
14165 ...which is legal on RELA targets, and has a well-defined behaviour
14166 if the user knows that adding 2 to "foo" will not induce a carry to
14169 When several %lo()s match a particular %got() or %hi(), we use the
14170 following rules to distinguish them:
14172 (1) %lo()s with smaller offsets are a better match than %lo()s with
14175 (2) %lo()s with no matching %got() or %hi() are better than those
14176 that already have a matching %got() or %hi().
14178 (3) later %lo()s are better than earlier %lo()s.
14180 These rules are applied in order.
14182 (1) means, among other things, that %lo()s with identical offsets are
14183 chosen if they exist.
14185 (2) means that we won't associate several high-part relocations with
14186 the same low-part relocation unless there's no alternative. Having
14187 several high parts for the same low part is a GNU extension; this rule
14188 allows careful users to avoid it.
14190 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14191 with the last high-part relocation being at the front of the list.
14192 It therefore makes sense to choose the last matching low-part
14193 relocation, all other things being equal. It's also easier
14194 to code that way. */
14197 mips_frob_file (void)
14199 struct mips_hi_fixup
*l
;
14200 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14202 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14204 segment_info_type
*seginfo
;
14205 bfd_boolean matched_lo_p
;
14206 fixS
**hi_pos
, **lo_pos
, **pos
;
14208 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14210 /* If a GOT16 relocation turns out to be against a global symbol,
14211 there isn't supposed to be a matching LO. Ignore %gots against
14212 constants; we'll report an error for those later. */
14213 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14214 && !(l
->fixp
->fx_addsy
14215 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14218 /* Check quickly whether the next fixup happens to be a matching %lo. */
14219 if (fixup_has_matching_lo_p (l
->fixp
))
14222 seginfo
= seg_info (l
->seg
);
14224 /* Set HI_POS to the position of this relocation in the chain.
14225 Set LO_POS to the position of the chosen low-part relocation.
14226 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14227 relocation that matches an immediately-preceding high-part
14231 matched_lo_p
= FALSE
;
14232 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14234 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14236 if (*pos
== l
->fixp
)
14239 if ((*pos
)->fx_r_type
== looking_for_rtype
14240 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14241 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14243 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14245 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14248 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14249 && fixup_has_matching_lo_p (*pos
));
14252 /* If we found a match, remove the high-part relocation from its
14253 current position and insert it before the low-part relocation.
14254 Make the offsets match so that fixup_has_matching_lo_p()
14257 We don't warn about unmatched high-part relocations since some
14258 versions of gcc have been known to emit dead "lui ...%hi(...)"
14260 if (lo_pos
!= NULL
)
14262 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14263 if (l
->fixp
->fx_next
!= *lo_pos
)
14265 *hi_pos
= l
->fixp
->fx_next
;
14266 l
->fixp
->fx_next
= *lo_pos
;
14274 mips_force_relocation (fixS
*fixp
)
14276 if (generic_force_reloc (fixp
))
14279 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14280 so that the linker relaxation can update targets. */
14281 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14282 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14283 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14289 /* Read the instruction associated with RELOC from BUF. */
14291 static unsigned int
14292 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14294 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14295 return read_compressed_insn (buf
, 4);
14297 return read_insn (buf
);
14300 /* Write instruction INSN to BUF, given that it has been relocated
14304 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14305 unsigned long insn
)
14307 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14308 write_compressed_insn (buf
, insn
, 4);
14310 write_insn (buf
, insn
);
14313 /* Apply a fixup to the object file. */
14316 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14319 unsigned long insn
;
14320 reloc_howto_type
*howto
;
14322 if (fixP
->fx_pcrel
)
14323 switch (fixP
->fx_r_type
)
14325 case BFD_RELOC_16_PCREL_S2
:
14326 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14327 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14328 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14329 case BFD_RELOC_32_PCREL
:
14333 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
14337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14338 _("PC-relative reference to a different section"));
14342 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14343 that have no MIPS ELF equivalent. */
14344 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
14346 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14351 gas_assert (fixP
->fx_size
== 2
14352 || fixP
->fx_size
== 4
14353 || fixP
->fx_r_type
== BFD_RELOC_8
14354 || fixP
->fx_r_type
== BFD_RELOC_16
14355 || fixP
->fx_r_type
== BFD_RELOC_64
14356 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14357 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14358 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14359 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14360 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14361 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14363 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14365 /* Don't treat parts of a composite relocation as done. There are two
14368 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14369 should nevertheless be emitted if the first part is.
14371 (2) In normal usage, composite relocations are never assembly-time
14372 constants. The easiest way of dealing with the pathological
14373 exceptions is to generate a relocation against STN_UNDEF and
14374 leave everything up to the linker. */
14375 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14378 switch (fixP
->fx_r_type
)
14380 case BFD_RELOC_MIPS_TLS_GD
:
14381 case BFD_RELOC_MIPS_TLS_LDM
:
14382 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14383 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14384 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14385 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14386 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14387 case BFD_RELOC_MIPS_TLS_TPREL32
:
14388 case BFD_RELOC_MIPS_TLS_TPREL64
:
14389 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14390 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14391 case BFD_RELOC_MICROMIPS_TLS_GD
:
14392 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14393 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14394 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14395 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14396 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14397 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14398 case BFD_RELOC_MIPS16_TLS_GD
:
14399 case BFD_RELOC_MIPS16_TLS_LDM
:
14400 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14401 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14402 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14403 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14404 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14405 if (!fixP
->fx_addsy
)
14407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14408 _("TLS relocation against a constant"));
14411 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14414 case BFD_RELOC_MIPS_JMP
:
14415 case BFD_RELOC_MIPS_SHIFT5
:
14416 case BFD_RELOC_MIPS_SHIFT6
:
14417 case BFD_RELOC_MIPS_GOT_DISP
:
14418 case BFD_RELOC_MIPS_GOT_PAGE
:
14419 case BFD_RELOC_MIPS_GOT_OFST
:
14420 case BFD_RELOC_MIPS_SUB
:
14421 case BFD_RELOC_MIPS_INSERT_A
:
14422 case BFD_RELOC_MIPS_INSERT_B
:
14423 case BFD_RELOC_MIPS_DELETE
:
14424 case BFD_RELOC_MIPS_HIGHEST
:
14425 case BFD_RELOC_MIPS_HIGHER
:
14426 case BFD_RELOC_MIPS_SCN_DISP
:
14427 case BFD_RELOC_MIPS_REL16
:
14428 case BFD_RELOC_MIPS_RELGOT
:
14429 case BFD_RELOC_MIPS_JALR
:
14430 case BFD_RELOC_HI16
:
14431 case BFD_RELOC_HI16_S
:
14432 case BFD_RELOC_LO16
:
14433 case BFD_RELOC_GPREL16
:
14434 case BFD_RELOC_MIPS_LITERAL
:
14435 case BFD_RELOC_MIPS_CALL16
:
14436 case BFD_RELOC_MIPS_GOT16
:
14437 case BFD_RELOC_GPREL32
:
14438 case BFD_RELOC_MIPS_GOT_HI16
:
14439 case BFD_RELOC_MIPS_GOT_LO16
:
14440 case BFD_RELOC_MIPS_CALL_HI16
:
14441 case BFD_RELOC_MIPS_CALL_LO16
:
14442 case BFD_RELOC_MIPS16_GPREL
:
14443 case BFD_RELOC_MIPS16_GOT16
:
14444 case BFD_RELOC_MIPS16_CALL16
:
14445 case BFD_RELOC_MIPS16_HI16
:
14446 case BFD_RELOC_MIPS16_HI16_S
:
14447 case BFD_RELOC_MIPS16_LO16
:
14448 case BFD_RELOC_MIPS16_JMP
:
14449 case BFD_RELOC_MICROMIPS_JMP
:
14450 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14451 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14452 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14453 case BFD_RELOC_MICROMIPS_SUB
:
14454 case BFD_RELOC_MICROMIPS_HIGHEST
:
14455 case BFD_RELOC_MICROMIPS_HIGHER
:
14456 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14457 case BFD_RELOC_MICROMIPS_JALR
:
14458 case BFD_RELOC_MICROMIPS_HI16
:
14459 case BFD_RELOC_MICROMIPS_HI16_S
:
14460 case BFD_RELOC_MICROMIPS_LO16
:
14461 case BFD_RELOC_MICROMIPS_GPREL16
:
14462 case BFD_RELOC_MICROMIPS_LITERAL
:
14463 case BFD_RELOC_MICROMIPS_CALL16
:
14464 case BFD_RELOC_MICROMIPS_GOT16
:
14465 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14466 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14467 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14468 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14469 case BFD_RELOC_MIPS_EH
:
14474 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14476 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14477 if (mips16_reloc_p (fixP
->fx_r_type
))
14478 insn
|= mips16_immed_extend (value
, 16);
14480 insn
|= (value
& 0xffff);
14481 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14484 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14485 _("unsupported constant in relocation"));
14490 /* This is handled like BFD_RELOC_32, but we output a sign
14491 extended value if we are only 32 bits. */
14494 if (8 <= sizeof (valueT
))
14495 md_number_to_chars (buf
, *valP
, 8);
14500 if ((*valP
& 0x80000000) != 0)
14504 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14505 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14510 case BFD_RELOC_RVA
:
14512 case BFD_RELOC_32_PCREL
:
14515 /* If we are deleting this reloc entry, we must fill in the
14516 value now. This can happen if we have a .word which is not
14517 resolved when it appears but is later defined. */
14519 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14522 case BFD_RELOC_16_PCREL_S2
:
14523 if ((*valP
& 0x3) != 0)
14524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14525 _("branch to misaligned address (%lx)"), (long) *valP
);
14527 /* We need to save the bits in the instruction since fixup_segment()
14528 might be deleting the relocation entry (i.e., a branch within
14529 the current segment). */
14530 if (! fixP
->fx_done
)
14533 /* Update old instruction data. */
14534 insn
= read_insn (buf
);
14536 if (*valP
+ 0x20000 <= 0x3ffff)
14538 insn
|= (*valP
>> 2) & 0xffff;
14539 write_insn (buf
, insn
);
14541 else if (mips_pic
== NO_PIC
14543 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14544 && (fixP
->fx_frag
->fr_address
14545 < text_section
->vma
+ bfd_get_section_size (text_section
))
14546 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14547 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14548 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14550 /* The branch offset is too large. If this is an
14551 unconditional branch, and we are not generating PIC code,
14552 we can convert it to an absolute jump instruction. */
14553 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14554 insn
= 0x0c000000; /* jal */
14556 insn
= 0x08000000; /* j */
14557 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14559 fixP
->fx_addsy
= section_symbol (text_section
);
14560 *valP
+= md_pcrel_from (fixP
);
14561 write_insn (buf
, insn
);
14565 /* If we got here, we have branch-relaxation disabled,
14566 and there's nothing we can do to fix this instruction
14567 without turning it into a longer sequence. */
14568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14569 _("branch out of range"));
14573 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14574 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14575 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14576 /* We adjust the offset back to even. */
14577 if ((*valP
& 0x1) != 0)
14580 if (! fixP
->fx_done
)
14583 /* Should never visit here, because we keep the relocation. */
14587 case BFD_RELOC_VTABLE_INHERIT
:
14590 && !S_IS_DEFINED (fixP
->fx_addsy
)
14591 && !S_IS_WEAK (fixP
->fx_addsy
))
14592 S_SET_WEAK (fixP
->fx_addsy
);
14595 case BFD_RELOC_VTABLE_ENTRY
:
14603 /* Remember value for tc_gen_reloc. */
14604 fixP
->fx_addnumber
= *valP
;
14614 name
= input_line_pointer
;
14615 c
= get_symbol_end ();
14616 p
= (symbolS
*) symbol_find_or_make (name
);
14617 *input_line_pointer
= c
;
14621 /* Align the current frag to a given power of two. If a particular
14622 fill byte should be used, FILL points to an integer that contains
14623 that byte, otherwise FILL is null.
14625 This function used to have the comment:
14627 The MIPS assembler also automatically adjusts any preceding label.
14629 The implementation therefore applied the adjustment to a maximum of
14630 one label. However, other label adjustments are applied to batches
14631 of labels, and adjusting just one caused problems when new labels
14632 were added for the sake of debugging or unwind information.
14633 We therefore adjust all preceding labels (given as LABELS) instead. */
14636 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14638 mips_emit_delays ();
14639 mips_record_compressed_mode ();
14640 if (fill
== NULL
&& subseg_text_p (now_seg
))
14641 frag_align_code (to
, 0);
14643 frag_align (to
, fill
? *fill
: 0, 0);
14644 record_alignment (now_seg
, to
);
14645 mips_move_labels (labels
, FALSE
);
14648 /* Align to a given power of two. .align 0 turns off the automatic
14649 alignment used by the data creating pseudo-ops. */
14652 s_align (int x ATTRIBUTE_UNUSED
)
14654 int temp
, fill_value
, *fill_ptr
;
14655 long max_alignment
= 28;
14657 /* o Note that the assembler pulls down any immediately preceding label
14658 to the aligned address.
14659 o It's not documented but auto alignment is reinstated by
14660 a .align pseudo instruction.
14661 o Note also that after auto alignment is turned off the mips assembler
14662 issues an error on attempt to assemble an improperly aligned data item.
14665 temp
= get_absolute_expression ();
14666 if (temp
> max_alignment
)
14667 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
14670 as_warn (_("alignment negative, 0 assumed"));
14673 if (*input_line_pointer
== ',')
14675 ++input_line_pointer
;
14676 fill_value
= get_absolute_expression ();
14677 fill_ptr
= &fill_value
;
14683 segment_info_type
*si
= seg_info (now_seg
);
14684 struct insn_label_list
*l
= si
->label_list
;
14685 /* Auto alignment should be switched on by next section change. */
14687 mips_align (temp
, fill_ptr
, l
);
14694 demand_empty_rest_of_line ();
14698 s_change_sec (int sec
)
14702 /* The ELF backend needs to know that we are changing sections, so
14703 that .previous works correctly. We could do something like check
14704 for an obj_section_change_hook macro, but that might be confusing
14705 as it would not be appropriate to use it in the section changing
14706 functions in read.c, since obj-elf.c intercepts those. FIXME:
14707 This should be cleaner, somehow. */
14708 obj_elf_section_change_hook ();
14710 mips_emit_delays ();
14721 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14722 demand_empty_rest_of_line ();
14726 seg
= subseg_new (RDATA_SECTION_NAME
,
14727 (subsegT
) get_absolute_expression ());
14728 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14729 | SEC_READONLY
| SEC_RELOC
14731 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14732 record_alignment (seg
, 4);
14733 demand_empty_rest_of_line ();
14737 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14738 bfd_set_section_flags (stdoutput
, seg
,
14739 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14740 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14741 record_alignment (seg
, 4);
14742 demand_empty_rest_of_line ();
14746 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14747 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14748 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14749 record_alignment (seg
, 4);
14750 demand_empty_rest_of_line ();
14758 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14760 char *section_name
;
14765 int section_entry_size
;
14766 int section_alignment
;
14768 section_name
= input_line_pointer
;
14769 c
= get_symbol_end ();
14771 next_c
= *(input_line_pointer
+ 1);
14773 /* Do we have .section Name<,"flags">? */
14774 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14776 /* just after name is now '\0'. */
14777 *input_line_pointer
= c
;
14778 input_line_pointer
= section_name
;
14779 obj_elf_section (ignore
);
14782 input_line_pointer
++;
14784 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14786 section_type
= get_absolute_expression ();
14789 if (*input_line_pointer
++ == ',')
14790 section_flag
= get_absolute_expression ();
14793 if (*input_line_pointer
++ == ',')
14794 section_entry_size
= get_absolute_expression ();
14796 section_entry_size
= 0;
14797 if (*input_line_pointer
++ == ',')
14798 section_alignment
= get_absolute_expression ();
14800 section_alignment
= 0;
14801 /* FIXME: really ignore? */
14802 (void) section_alignment
;
14804 section_name
= xstrdup (section_name
);
14806 /* When using the generic form of .section (as implemented by obj-elf.c),
14807 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14808 traditionally had to fall back on the more common @progbits instead.
14810 There's nothing really harmful in this, since bfd will correct
14811 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14812 means that, for backwards compatibility, the special_section entries
14813 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14815 Even so, we shouldn't force users of the MIPS .section syntax to
14816 incorrectly label the sections as SHT_PROGBITS. The best compromise
14817 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14818 generic type-checking code. */
14819 if (section_type
== SHT_MIPS_DWARF
)
14820 section_type
= SHT_PROGBITS
;
14822 obj_elf_change_section (section_name
, section_type
, section_flag
,
14823 section_entry_size
, 0, 0, 0);
14825 if (now_seg
->name
!= section_name
)
14826 free (section_name
);
14830 mips_enable_auto_align (void)
14836 s_cons (int log_size
)
14838 segment_info_type
*si
= seg_info (now_seg
);
14839 struct insn_label_list
*l
= si
->label_list
;
14841 mips_emit_delays ();
14842 if (log_size
> 0 && auto_align
)
14843 mips_align (log_size
, 0, l
);
14844 cons (1 << log_size
);
14845 mips_clear_insn_labels ();
14849 s_float_cons (int type
)
14851 segment_info_type
*si
= seg_info (now_seg
);
14852 struct insn_label_list
*l
= si
->label_list
;
14854 mips_emit_delays ();
14859 mips_align (3, 0, l
);
14861 mips_align (2, 0, l
);
14865 mips_clear_insn_labels ();
14868 /* Handle .globl. We need to override it because on Irix 5 you are
14871 where foo is an undefined symbol, to mean that foo should be
14872 considered to be the address of a function. */
14875 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14884 name
= input_line_pointer
;
14885 c
= get_symbol_end ();
14886 symbolP
= symbol_find_or_make (name
);
14887 S_SET_EXTERNAL (symbolP
);
14889 *input_line_pointer
= c
;
14890 SKIP_WHITESPACE ();
14892 /* On Irix 5, every global symbol that is not explicitly labelled as
14893 being a function is apparently labelled as being an object. */
14896 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14897 && (*input_line_pointer
!= ','))
14902 secname
= input_line_pointer
;
14903 c
= get_symbol_end ();
14904 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14906 as_bad (_("%s: no such section"), secname
);
14907 *input_line_pointer
= c
;
14909 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14910 flag
= BSF_FUNCTION
;
14913 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14915 c
= *input_line_pointer
;
14918 input_line_pointer
++;
14919 SKIP_WHITESPACE ();
14920 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14926 demand_empty_rest_of_line ();
14930 s_option (int x ATTRIBUTE_UNUSED
)
14935 opt
= input_line_pointer
;
14936 c
= get_symbol_end ();
14940 /* FIXME: What does this mean? */
14942 else if (strncmp (opt
, "pic", 3) == 0)
14946 i
= atoi (opt
+ 3);
14951 mips_pic
= SVR4_PIC
;
14952 mips_abicalls
= TRUE
;
14955 as_bad (_(".option pic%d not supported"), i
);
14957 if (mips_pic
== SVR4_PIC
)
14959 if (g_switch_seen
&& g_switch_value
!= 0)
14960 as_warn (_("-G may not be used with SVR4 PIC code"));
14961 g_switch_value
= 0;
14962 bfd_set_gp_size (stdoutput
, 0);
14966 as_warn (_("unrecognized option \"%s\""), opt
);
14968 *input_line_pointer
= c
;
14969 demand_empty_rest_of_line ();
14972 /* This structure is used to hold a stack of .set values. */
14974 struct mips_option_stack
14976 struct mips_option_stack
*next
;
14977 struct mips_set_options options
;
14980 static struct mips_option_stack
*mips_opts_stack
;
14982 /* Handle the .set pseudo-op. */
14985 s_mipsset (int x ATTRIBUTE_UNUSED
)
14987 char *name
= input_line_pointer
, ch
;
14988 const struct mips_ase
*ase
;
14990 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14991 ++input_line_pointer
;
14992 ch
= *input_line_pointer
;
14993 *input_line_pointer
= '\0';
14995 if (strcmp (name
, "reorder") == 0)
14997 if (mips_opts
.noreorder
)
15000 else if (strcmp (name
, "noreorder") == 0)
15002 if (!mips_opts
.noreorder
)
15003 start_noreorder ();
15005 else if (strncmp (name
, "at=", 3) == 0)
15007 char *s
= name
+ 3;
15009 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15010 as_bad (_("unrecognized register name `%s'"), s
);
15012 else if (strcmp (name
, "at") == 0)
15014 mips_opts
.at
= ATREG
;
15016 else if (strcmp (name
, "noat") == 0)
15018 mips_opts
.at
= ZERO
;
15020 else if (strcmp (name
, "macro") == 0)
15022 mips_opts
.warn_about_macros
= 0;
15024 else if (strcmp (name
, "nomacro") == 0)
15026 if (mips_opts
.noreorder
== 0)
15027 as_bad (_("`noreorder' must be set before `nomacro'"));
15028 mips_opts
.warn_about_macros
= 1;
15030 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15032 mips_opts
.nomove
= 0;
15034 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15036 mips_opts
.nomove
= 1;
15038 else if (strcmp (name
, "bopt") == 0)
15040 mips_opts
.nobopt
= 0;
15042 else if (strcmp (name
, "nobopt") == 0)
15044 mips_opts
.nobopt
= 1;
15046 else if (strcmp (name
, "gp=default") == 0)
15047 mips_opts
.gp32
= file_mips_opts
.gp32
;
15048 else if (strcmp (name
, "gp=32") == 0)
15049 mips_opts
.gp32
= 1;
15050 else if (strcmp (name
, "gp=64") == 0)
15052 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15053 as_warn (_("%s isa does not support 64-bit registers"),
15054 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15055 mips_opts
.gp32
= 0;
15057 else if (strcmp (name
, "fp=default") == 0)
15058 mips_opts
.fp
= file_mips_opts
.fp
;
15059 else if (strcmp (name
, "fp=32") == 0)
15061 else if (strcmp (name
, "fp=64") == 0)
15063 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15064 as_warn (_("%s isa does not support 64-bit floating point registers"),
15065 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15068 else if (strcmp (name
, "softfloat") == 0)
15069 mips_opts
.soft_float
= 1;
15070 else if (strcmp (name
, "hardfloat") == 0)
15071 mips_opts
.soft_float
= 0;
15072 else if (strcmp (name
, "singlefloat") == 0)
15073 mips_opts
.single_float
= 1;
15074 else if (strcmp (name
, "doublefloat") == 0)
15075 mips_opts
.single_float
= 0;
15076 else if (strcmp (name
, "mips16") == 0
15077 || strcmp (name
, "MIPS-16") == 0)
15079 if (mips_opts
.micromips
== 1)
15080 as_fatal (_("`mips16' cannot be used with `micromips'"));
15081 mips_opts
.mips16
= 1;
15083 else if (strcmp (name
, "nomips16") == 0
15084 || strcmp (name
, "noMIPS-16") == 0)
15085 mips_opts
.mips16
= 0;
15086 else if (strcmp (name
, "micromips") == 0)
15088 if (mips_opts
.mips16
== 1)
15089 as_fatal (_("`micromips' cannot be used with `mips16'"));
15090 mips_opts
.micromips
= 1;
15092 else if (strcmp (name
, "nomicromips") == 0)
15093 mips_opts
.micromips
= 0;
15094 else if (name
[0] == 'n'
15096 && (ase
= mips_lookup_ase (name
+ 2)))
15097 mips_set_ase (ase
, FALSE
);
15098 else if ((ase
= mips_lookup_ase (name
)))
15099 mips_set_ase (ase
, TRUE
);
15100 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15104 /* Permit the user to change the ISA and architecture on the fly.
15105 Needless to say, misuse can cause serious problems. */
15106 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15109 mips_opts
.isa
= file_mips_opts
.isa
;
15110 mips_opts
.arch
= file_mips_opts
.arch
;
15112 else if (strncmp (name
, "arch=", 5) == 0)
15114 const struct mips_cpu_info
*p
;
15116 p
= mips_parse_cpu("internal use", name
+ 5);
15118 as_bad (_("unknown architecture %s"), name
+ 5);
15121 mips_opts
.arch
= p
->cpu
;
15122 mips_opts
.isa
= p
->isa
;
15125 else if (strncmp (name
, "mips", 4) == 0)
15127 const struct mips_cpu_info
*p
;
15129 p
= mips_parse_cpu("internal use", name
);
15131 as_bad (_("unknown ISA level %s"), name
+ 4);
15134 mips_opts
.arch
= p
->cpu
;
15135 mips_opts
.isa
= p
->isa
;
15139 as_bad (_("unknown ISA or architecture %s"), name
);
15141 switch (mips_opts
.isa
)
15151 mips_opts
.gp32
= 1;
15161 mips_opts
.gp32
= 0;
15162 if (mips_opts
.arch
== CPU_R5900
)
15172 as_bad (_("unknown ISA level %s"), name
+ 4);
15177 mips_opts
.gp32
= file_mips_opts
.gp32
;
15178 mips_opts
.fp
= file_mips_opts
.fp
;
15181 else if (strcmp (name
, "autoextend") == 0)
15182 mips_opts
.noautoextend
= 0;
15183 else if (strcmp (name
, "noautoextend") == 0)
15184 mips_opts
.noautoextend
= 1;
15185 else if (strcmp (name
, "insn32") == 0)
15186 mips_opts
.insn32
= TRUE
;
15187 else if (strcmp (name
, "noinsn32") == 0)
15188 mips_opts
.insn32
= FALSE
;
15189 else if (strcmp (name
, "push") == 0)
15191 struct mips_option_stack
*s
;
15193 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15194 s
->next
= mips_opts_stack
;
15195 s
->options
= mips_opts
;
15196 mips_opts_stack
= s
;
15198 else if (strcmp (name
, "pop") == 0)
15200 struct mips_option_stack
*s
;
15202 s
= mips_opts_stack
;
15204 as_bad (_(".set pop with no .set push"));
15207 /* If we're changing the reorder mode we need to handle
15208 delay slots correctly. */
15209 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15210 start_noreorder ();
15211 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15214 mips_opts
= s
->options
;
15215 mips_opts_stack
= s
->next
;
15219 else if (strcmp (name
, "sym32") == 0)
15220 mips_opts
.sym32
= TRUE
;
15221 else if (strcmp (name
, "nosym32") == 0)
15222 mips_opts
.sym32
= FALSE
;
15223 else if (strchr (name
, ','))
15225 /* Generic ".set" directive; use the generic handler. */
15226 *input_line_pointer
= ch
;
15227 input_line_pointer
= name
;
15233 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
15235 mips_check_isa_supports_ases ();
15236 *input_line_pointer
= ch
;
15237 demand_empty_rest_of_line ();
15240 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15241 .option pic2. It means to generate SVR4 PIC calls. */
15244 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15246 mips_pic
= SVR4_PIC
;
15247 mips_abicalls
= TRUE
;
15249 if (g_switch_seen
&& g_switch_value
!= 0)
15250 as_warn (_("-G may not be used with SVR4 PIC code"));
15251 g_switch_value
= 0;
15253 bfd_set_gp_size (stdoutput
, 0);
15254 demand_empty_rest_of_line ();
15257 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15258 PIC code. It sets the $gp register for the function based on the
15259 function address, which is in the register named in the argument.
15260 This uses a relocation against _gp_disp, which is handled specially
15261 by the linker. The result is:
15262 lui $gp,%hi(_gp_disp)
15263 addiu $gp,$gp,%lo(_gp_disp)
15264 addu $gp,$gp,.cpload argument
15265 The .cpload argument is normally $25 == $t9.
15267 The -mno-shared option changes this to:
15268 lui $gp,%hi(__gnu_local_gp)
15269 addiu $gp,$gp,%lo(__gnu_local_gp)
15270 and the argument is ignored. This saves an instruction, but the
15271 resulting code is not position independent; it uses an absolute
15272 address for __gnu_local_gp. Thus code assembled with -mno-shared
15273 can go into an ordinary executable, but not into a shared library. */
15276 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15282 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15283 .cpload is ignored. */
15284 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15290 if (mips_opts
.mips16
)
15292 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15293 ignore_rest_of_line ();
15297 /* .cpload should be in a .set noreorder section. */
15298 if (mips_opts
.noreorder
== 0)
15299 as_warn (_(".cpload not in noreorder section"));
15301 reg
= tc_get_register (0);
15303 /* If we need to produce a 64-bit address, we are better off using
15304 the default instruction sequence. */
15305 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15307 ex
.X_op
= O_symbol
;
15308 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15310 ex
.X_op_symbol
= NULL
;
15311 ex
.X_add_number
= 0;
15313 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15314 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15316 mips_mark_labels ();
15317 mips_assembling_insn
= TRUE
;
15320 macro_build_lui (&ex
, mips_gp_register
);
15321 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15322 mips_gp_register
, BFD_RELOC_LO16
);
15324 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15325 mips_gp_register
, reg
);
15328 mips_assembling_insn
= FALSE
;
15329 demand_empty_rest_of_line ();
15332 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15333 .cpsetup $reg1, offset|$reg2, label
15335 If offset is given, this results in:
15336 sd $gp, offset($sp)
15337 lui $gp, %hi(%neg(%gp_rel(label)))
15338 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15339 daddu $gp, $gp, $reg1
15341 If $reg2 is given, this results in:
15342 daddu $reg2, $gp, $0
15343 lui $gp, %hi(%neg(%gp_rel(label)))
15344 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15345 daddu $gp, $gp, $reg1
15346 $reg1 is normally $25 == $t9.
15348 The -mno-shared option replaces the last three instructions with
15350 addiu $gp,$gp,%lo(_gp) */
15353 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15355 expressionS ex_off
;
15356 expressionS ex_sym
;
15359 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15360 We also need NewABI support. */
15361 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15367 if (mips_opts
.mips16
)
15369 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15370 ignore_rest_of_line ();
15374 reg1
= tc_get_register (0);
15375 SKIP_WHITESPACE ();
15376 if (*input_line_pointer
!= ',')
15378 as_bad (_("missing argument separator ',' for .cpsetup"));
15382 ++input_line_pointer
;
15383 SKIP_WHITESPACE ();
15384 if (*input_line_pointer
== '$')
15386 mips_cpreturn_register
= tc_get_register (0);
15387 mips_cpreturn_offset
= -1;
15391 mips_cpreturn_offset
= get_absolute_expression ();
15392 mips_cpreturn_register
= -1;
15394 SKIP_WHITESPACE ();
15395 if (*input_line_pointer
!= ',')
15397 as_bad (_("missing argument separator ',' for .cpsetup"));
15401 ++input_line_pointer
;
15402 SKIP_WHITESPACE ();
15403 expression (&ex_sym
);
15405 mips_mark_labels ();
15406 mips_assembling_insn
= TRUE
;
15409 if (mips_cpreturn_register
== -1)
15411 ex_off
.X_op
= O_constant
;
15412 ex_off
.X_add_symbol
= NULL
;
15413 ex_off
.X_op_symbol
= NULL
;
15414 ex_off
.X_add_number
= mips_cpreturn_offset
;
15416 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15417 BFD_RELOC_LO16
, SP
);
15420 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15421 mips_gp_register
, 0);
15423 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15425 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15426 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15429 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15430 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15431 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15433 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15434 mips_gp_register
, reg1
);
15440 ex
.X_op
= O_symbol
;
15441 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15442 ex
.X_op_symbol
= NULL
;
15443 ex
.X_add_number
= 0;
15445 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15446 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15448 macro_build_lui (&ex
, mips_gp_register
);
15449 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15450 mips_gp_register
, BFD_RELOC_LO16
);
15455 mips_assembling_insn
= FALSE
;
15456 demand_empty_rest_of_line ();
15460 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15462 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15463 .cplocal is ignored. */
15464 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15470 if (mips_opts
.mips16
)
15472 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15473 ignore_rest_of_line ();
15477 mips_gp_register
= tc_get_register (0);
15478 demand_empty_rest_of_line ();
15481 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15482 offset from $sp. The offset is remembered, and after making a PIC
15483 call $gp is restored from that location. */
15486 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15490 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15491 .cprestore is ignored. */
15492 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15498 if (mips_opts
.mips16
)
15500 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15501 ignore_rest_of_line ();
15505 mips_cprestore_offset
= get_absolute_expression ();
15506 mips_cprestore_valid
= 1;
15508 ex
.X_op
= O_constant
;
15509 ex
.X_add_symbol
= NULL
;
15510 ex
.X_op_symbol
= NULL
;
15511 ex
.X_add_number
= mips_cprestore_offset
;
15513 mips_mark_labels ();
15514 mips_assembling_insn
= TRUE
;
15517 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15518 SP
, HAVE_64BIT_ADDRESSES
);
15521 mips_assembling_insn
= FALSE
;
15522 demand_empty_rest_of_line ();
15525 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15526 was given in the preceding .cpsetup, it results in:
15527 ld $gp, offset($sp)
15529 If a register $reg2 was given there, it results in:
15530 daddu $gp, $reg2, $0 */
15533 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15537 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15538 We also need NewABI support. */
15539 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15545 if (mips_opts
.mips16
)
15547 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15548 ignore_rest_of_line ();
15552 mips_mark_labels ();
15553 mips_assembling_insn
= TRUE
;
15556 if (mips_cpreturn_register
== -1)
15558 ex
.X_op
= O_constant
;
15559 ex
.X_add_symbol
= NULL
;
15560 ex
.X_op_symbol
= NULL
;
15561 ex
.X_add_number
= mips_cpreturn_offset
;
15563 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15566 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15567 mips_cpreturn_register
, 0);
15570 mips_assembling_insn
= FALSE
;
15571 demand_empty_rest_of_line ();
15574 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15575 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15576 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15577 debug information or MIPS16 TLS. */
15580 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15581 bfd_reloc_code_real_type rtype
)
15588 if (ex
.X_op
!= O_symbol
)
15590 as_bad (_("unsupported use of %s"), dirstr
);
15591 ignore_rest_of_line ();
15594 p
= frag_more (bytes
);
15595 md_number_to_chars (p
, 0, bytes
);
15596 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15597 demand_empty_rest_of_line ();
15598 mips_clear_insn_labels ();
15601 /* Handle .dtprelword. */
15604 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15606 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15609 /* Handle .dtpreldword. */
15612 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15614 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15617 /* Handle .tprelword. */
15620 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15622 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15625 /* Handle .tpreldword. */
15628 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15630 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15633 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15634 code. It sets the offset to use in gp_rel relocations. */
15637 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15639 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15640 We also need NewABI support. */
15641 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15647 mips_gprel_offset
= get_absolute_expression ();
15649 demand_empty_rest_of_line ();
15652 /* Handle the .gpword pseudo-op. This is used when generating PIC
15653 code. It generates a 32 bit GP relative reloc. */
15656 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15658 segment_info_type
*si
;
15659 struct insn_label_list
*l
;
15663 /* When not generating PIC code, this is treated as .word. */
15664 if (mips_pic
!= SVR4_PIC
)
15670 si
= seg_info (now_seg
);
15671 l
= si
->label_list
;
15672 mips_emit_delays ();
15674 mips_align (2, 0, l
);
15677 mips_clear_insn_labels ();
15679 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15681 as_bad (_("unsupported use of .gpword"));
15682 ignore_rest_of_line ();
15686 md_number_to_chars (p
, 0, 4);
15687 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15688 BFD_RELOC_GPREL32
);
15690 demand_empty_rest_of_line ();
15694 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15696 segment_info_type
*si
;
15697 struct insn_label_list
*l
;
15701 /* When not generating PIC code, this is treated as .dword. */
15702 if (mips_pic
!= SVR4_PIC
)
15708 si
= seg_info (now_seg
);
15709 l
= si
->label_list
;
15710 mips_emit_delays ();
15712 mips_align (3, 0, l
);
15715 mips_clear_insn_labels ();
15717 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15719 as_bad (_("unsupported use of .gpdword"));
15720 ignore_rest_of_line ();
15724 md_number_to_chars (p
, 0, 8);
15725 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15726 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15728 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15729 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15730 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15732 demand_empty_rest_of_line ();
15735 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15736 tables. It generates a R_MIPS_EH reloc. */
15739 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15744 mips_emit_delays ();
15747 mips_clear_insn_labels ();
15749 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15751 as_bad (_("unsupported use of .ehword"));
15752 ignore_rest_of_line ();
15756 md_number_to_chars (p
, 0, 4);
15757 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15758 BFD_RELOC_MIPS_EH
);
15760 demand_empty_rest_of_line ();
15763 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15764 tables in SVR4 PIC code. */
15767 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15771 /* This is ignored when not generating SVR4 PIC code. */
15772 if (mips_pic
!= SVR4_PIC
)
15778 mips_mark_labels ();
15779 mips_assembling_insn
= TRUE
;
15781 /* Add $gp to the register named as an argument. */
15783 reg
= tc_get_register (0);
15784 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15787 mips_assembling_insn
= FALSE
;
15788 demand_empty_rest_of_line ();
15791 /* Handle the .insn pseudo-op. This marks instruction labels in
15792 mips16/micromips mode. This permits the linker to handle them specially,
15793 such as generating jalx instructions when needed. We also make
15794 them odd for the duration of the assembly, in order to generate the
15795 right sort of code. We will make them even in the adjust_symtab
15796 routine, while leaving them marked. This is convenient for the
15797 debugger and the disassembler. The linker knows to make them odd
15801 s_insn (int ignore ATTRIBUTE_UNUSED
)
15803 mips_mark_labels ();
15805 demand_empty_rest_of_line ();
15808 /* Handle the .nan pseudo-op. */
15811 s_nan (int ignore ATTRIBUTE_UNUSED
)
15813 static const char str_legacy
[] = "legacy";
15814 static const char str_2008
[] = "2008";
15817 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15819 if (i
== sizeof (str_2008
) - 1
15820 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15821 mips_flag_nan2008
= TRUE
;
15822 else if (i
== sizeof (str_legacy
) - 1
15823 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15824 mips_flag_nan2008
= FALSE
;
15826 as_bad (_("bad .nan directive"));
15828 input_line_pointer
+= i
;
15829 demand_empty_rest_of_line ();
15832 /* Handle a .stab[snd] directive. Ideally these directives would be
15833 implemented in a transparent way, so that removing them would not
15834 have any effect on the generated instructions. However, s_stab
15835 internally changes the section, so in practice we need to decide
15836 now whether the preceding label marks compressed code. We do not
15837 support changing the compression mode of a label after a .stab*
15838 directive, such as in:
15844 so the current mode wins. */
15847 s_mips_stab (int type
)
15849 mips_mark_labels ();
15853 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15856 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15863 name
= input_line_pointer
;
15864 c
= get_symbol_end ();
15865 symbolP
= symbol_find_or_make (name
);
15866 S_SET_WEAK (symbolP
);
15867 *input_line_pointer
= c
;
15869 SKIP_WHITESPACE ();
15871 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15873 if (S_IS_DEFINED (symbolP
))
15875 as_bad (_("ignoring attempt to redefine symbol %s"),
15876 S_GET_NAME (symbolP
));
15877 ignore_rest_of_line ();
15881 if (*input_line_pointer
== ',')
15883 ++input_line_pointer
;
15884 SKIP_WHITESPACE ();
15888 if (exp
.X_op
!= O_symbol
)
15890 as_bad (_("bad .weakext directive"));
15891 ignore_rest_of_line ();
15894 symbol_set_value_expression (symbolP
, &exp
);
15897 demand_empty_rest_of_line ();
15900 /* Parse a register string into a number. Called from the ECOFF code
15901 to parse .frame. The argument is non-zero if this is the frame
15902 register, so that we can record it in mips_frame_reg. */
15905 tc_get_register (int frame
)
15909 SKIP_WHITESPACE ();
15910 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15914 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15915 mips_frame_reg_valid
= 1;
15916 mips_cprestore_valid
= 0;
15922 md_section_align (asection
*seg
, valueT addr
)
15924 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15926 /* We don't need to align ELF sections to the full alignment.
15927 However, Irix 5 may prefer that we align them at least to a 16
15928 byte boundary. We don't bother to align the sections if we
15929 are targeted for an embedded system. */
15930 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15935 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15938 /* Utility routine, called from above as well. If called while the
15939 input file is still being read, it's only an approximation. (For
15940 example, a symbol may later become defined which appeared to be
15941 undefined earlier.) */
15944 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15949 if (g_switch_value
> 0)
15951 const char *symname
;
15954 /* Find out whether this symbol can be referenced off the $gp
15955 register. It can be if it is smaller than the -G size or if
15956 it is in the .sdata or .sbss section. Certain symbols can
15957 not be referenced off the $gp, although it appears as though
15959 symname
= S_GET_NAME (sym
);
15960 if (symname
!= (const char *) NULL
15961 && (strcmp (symname
, "eprol") == 0
15962 || strcmp (symname
, "etext") == 0
15963 || strcmp (symname
, "_gp") == 0
15964 || strcmp (symname
, "edata") == 0
15965 || strcmp (symname
, "_fbss") == 0
15966 || strcmp (symname
, "_fdata") == 0
15967 || strcmp (symname
, "_ftext") == 0
15968 || strcmp (symname
, "end") == 0
15969 || strcmp (symname
, "_gp_disp") == 0))
15971 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15973 #ifndef NO_ECOFF_DEBUGGING
15974 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15975 && (symbol_get_obj (sym
)->ecoff_extern_size
15976 <= g_switch_value
))
15978 /* We must defer this decision until after the whole
15979 file has been read, since there might be a .extern
15980 after the first use of this symbol. */
15981 || (before_relaxing
15982 #ifndef NO_ECOFF_DEBUGGING
15983 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15985 && S_GET_VALUE (sym
) == 0)
15986 || (S_GET_VALUE (sym
) != 0
15987 && S_GET_VALUE (sym
) <= g_switch_value
)))
15991 const char *segname
;
15993 segname
= segment_name (S_GET_SEGMENT (sym
));
15994 gas_assert (strcmp (segname
, ".lit8") != 0
15995 && strcmp (segname
, ".lit4") != 0);
15996 change
= (strcmp (segname
, ".sdata") != 0
15997 && strcmp (segname
, ".sbss") != 0
15998 && strncmp (segname
, ".sdata.", 7) != 0
15999 && strncmp (segname
, ".sbss.", 6) != 0
16000 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16001 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16006 /* We are not optimizing for the $gp register. */
16011 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16014 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16018 /* Handle the case of a symbol equated to another symbol. */
16019 while (symbol_equated_reloc_p (sym
))
16023 /* It's possible to get a loop here in a badly written program. */
16024 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16030 if (symbol_section_p (sym
))
16033 symsec
= S_GET_SEGMENT (sym
);
16035 /* This must duplicate the test in adjust_reloc_syms. */
16036 return (!bfd_is_und_section (symsec
)
16037 && !bfd_is_abs_section (symsec
)
16038 && !bfd_is_com_section (symsec
)
16039 && !s_is_linkonce (sym
, segtype
)
16040 /* A global or weak symbol is treated as external. */
16041 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16045 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16046 extended opcode. SEC is the section the frag is in. */
16049 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16052 const struct mips_int_operand
*operand
;
16057 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16059 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16062 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16063 operand
= mips16_immed_operand (type
, FALSE
);
16065 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16066 val
= S_GET_VALUE (fragp
->fr_symbol
);
16067 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16069 if (operand
->root
.type
== OP_PCREL
)
16071 const struct mips_pcrel_operand
*pcrel_op
;
16075 /* We won't have the section when we are called from
16076 mips_relax_frag. However, we will always have been called
16077 from md_estimate_size_before_relax first. If this is a
16078 branch to a different section, we mark it as such. If SEC is
16079 NULL, and the frag is not marked, then it must be a branch to
16080 the same section. */
16081 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16084 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16089 /* Must have been called from md_estimate_size_before_relax. */
16092 fragp
->fr_subtype
=
16093 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16095 /* FIXME: We should support this, and let the linker
16096 catch branches and loads that are out of range. */
16097 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16098 _("unsupported PC relative reference to different section"));
16102 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16103 /* Assume non-extended on the first relaxation pass.
16104 The address we have calculated will be bogus if this is
16105 a forward branch to another frag, as the forward frag
16106 will have fr_address == 0. */
16110 /* In this case, we know for sure that the symbol fragment is in
16111 the same section. If the relax_marker of the symbol fragment
16112 differs from the relax_marker of this fragment, we have not
16113 yet adjusted the symbol fragment fr_address. We want to add
16114 in STRETCH in order to get a better estimate of the address.
16115 This particularly matters because of the shift bits. */
16117 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16121 /* Adjust stretch for any alignment frag. Note that if have
16122 been expanding the earlier code, the symbol may be
16123 defined in what appears to be an earlier frag. FIXME:
16124 This doesn't handle the fr_subtype field, which specifies
16125 a maximum number of bytes to skip when doing an
16127 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16129 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16132 stretch
= - ((- stretch
)
16133 & ~ ((1 << (int) f
->fr_offset
) - 1));
16135 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16144 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16146 /* The base address rules are complicated. The base address of
16147 a branch is the following instruction. The base address of a
16148 PC relative load or add is the instruction itself, but if it
16149 is in a delay slot (in which case it can not be extended) use
16150 the address of the instruction whose delay slot it is in. */
16151 if (pcrel_op
->include_isa_bit
)
16155 /* If we are currently assuming that this frag should be
16156 extended, then, the current address is two bytes
16158 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16161 /* Ignore the low bit in the target, since it will be set
16162 for a text label. */
16165 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16167 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16170 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16172 /* If any of the shifted bits are set, we must use an extended
16173 opcode. If the address depends on the size of this
16174 instruction, this can lead to a loop, so we arrange to always
16175 use an extended opcode. We only check this when we are in
16176 the main relaxation loop, when SEC is NULL. */
16177 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16179 fragp
->fr_subtype
=
16180 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16184 /* If we are about to mark a frag as extended because the value
16185 is precisely the next value above maxtiny, then there is a
16186 chance of an infinite loop as in the following code:
16191 In this case when the la is extended, foo is 0x3fc bytes
16192 away, so the la can be shrunk, but then foo is 0x400 away, so
16193 the la must be extended. To avoid this loop, we mark the
16194 frag as extended if it was small, and is about to become
16195 extended with the next value above maxtiny. */
16196 maxtiny
= mips_int_operand_max (operand
);
16197 if (val
== maxtiny
+ (1 << operand
->shift
)
16198 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16201 fragp
->fr_subtype
=
16202 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16206 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16207 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16209 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16212 /* Compute the length of a branch sequence, and adjust the
16213 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16214 worst-case length is computed, with UPDATE being used to indicate
16215 whether an unconditional (-1), branch-likely (+1) or regular (0)
16216 branch is to be computed. */
16218 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16220 bfd_boolean toofar
;
16224 && S_IS_DEFINED (fragp
->fr_symbol
)
16225 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16230 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16232 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16236 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16239 /* If the symbol is not defined or it's in a different segment,
16240 assume the user knows what's going on and emit a short
16246 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16248 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16249 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16250 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16251 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16257 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16260 if (mips_pic
!= NO_PIC
)
16262 /* Additional space for PIC loading of target address. */
16264 if (mips_opts
.isa
== ISA_MIPS1
)
16265 /* Additional space for $at-stabilizing nop. */
16269 /* If branch is conditional. */
16270 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16277 /* Compute the length of a branch sequence, and adjust the
16278 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16279 worst-case length is computed, with UPDATE being used to indicate
16280 whether an unconditional (-1), or regular (0) branch is to be
16284 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16286 bfd_boolean toofar
;
16290 && S_IS_DEFINED (fragp
->fr_symbol
)
16291 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16296 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16297 /* Ignore the low bit in the target, since it will be set
16298 for a text label. */
16299 if ((val
& 1) != 0)
16302 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16306 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16309 /* If the symbol is not defined or it's in a different segment,
16310 assume the user knows what's going on and emit a short
16316 if (fragp
&& update
16317 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16318 fragp
->fr_subtype
= (toofar
16319 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16320 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16325 bfd_boolean compact_known
= fragp
!= NULL
;
16326 bfd_boolean compact
= FALSE
;
16327 bfd_boolean uncond
;
16330 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16332 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16334 uncond
= update
< 0;
16336 /* If label is out of range, we turn branch <br>:
16338 <br> label # 4 bytes
16344 nop # 2 bytes if compact && !PIC
16347 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16350 /* If assembling PIC code, we further turn:
16356 lw/ld at, %got(label)(gp) # 4 bytes
16357 d/addiu at, %lo(label) # 4 bytes
16360 if (mips_pic
!= NO_PIC
)
16363 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16365 <brneg> 0f # 4 bytes
16366 nop # 2 bytes if !compact
16369 length
+= (compact_known
&& compact
) ? 4 : 6;
16375 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16376 bit accordingly. */
16379 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16381 bfd_boolean toofar
;
16384 && S_IS_DEFINED (fragp
->fr_symbol
)
16385 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16391 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16392 /* Ignore the low bit in the target, since it will be set
16393 for a text label. */
16394 if ((val
& 1) != 0)
16397 /* Assume this is a 2-byte branch. */
16398 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16400 /* We try to avoid the infinite loop by not adding 2 more bytes for
16405 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16407 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16408 else if (type
== 'E')
16409 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16414 /* If the symbol is not defined or it's in a different segment,
16415 we emit a normal 32-bit branch. */
16418 if (fragp
&& update
16419 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16421 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16422 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16430 /* Estimate the size of a frag before relaxing. Unless this is the
16431 mips16, we are not really relaxing here, and the final size is
16432 encoded in the subtype information. For the mips16, we have to
16433 decide whether we are using an extended opcode or not. */
16436 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16440 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16443 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16445 return fragp
->fr_var
;
16448 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16449 /* We don't want to modify the EXTENDED bit here; it might get us
16450 into infinite loops. We change it only in mips_relax_frag(). */
16451 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16453 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16457 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16458 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16459 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16460 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16461 fragp
->fr_var
= length
;
16466 if (mips_pic
== NO_PIC
)
16467 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16468 else if (mips_pic
== SVR4_PIC
)
16469 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16470 else if (mips_pic
== VXWORKS_PIC
)
16471 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16478 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16479 return -RELAX_FIRST (fragp
->fr_subtype
);
16482 return -RELAX_SECOND (fragp
->fr_subtype
);
16485 /* This is called to see whether a reloc against a defined symbol
16486 should be converted into a reloc against a section. */
16489 mips_fix_adjustable (fixS
*fixp
)
16491 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16492 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16495 if (fixp
->fx_addsy
== NULL
)
16498 /* If symbol SYM is in a mergeable section, relocations of the form
16499 SYM + 0 can usually be made section-relative. The mergeable data
16500 is then identified by the section offset rather than by the symbol.
16502 However, if we're generating REL LO16 relocations, the offset is split
16503 between the LO16 and parterning high part relocation. The linker will
16504 need to recalculate the complete offset in order to correctly identify
16507 The linker has traditionally not looked for the parterning high part
16508 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16509 placed anywhere. Rather than break backwards compatibility by changing
16510 this, it seems better not to force the issue, and instead keep the
16511 original symbol. This will work with either linker behavior. */
16512 if ((lo16_reloc_p (fixp
->fx_r_type
)
16513 || reloc_needs_lo_p (fixp
->fx_r_type
))
16514 && HAVE_IN_PLACE_ADDENDS
16515 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16518 /* There is no place to store an in-place offset for JALR relocations.
16519 Likewise an in-range offset of limited PC-relative relocations may
16520 overflow the in-place relocatable field if recalculated against the
16521 start address of the symbol's containing section. */
16522 if (HAVE_IN_PLACE_ADDENDS
16523 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16524 || jalr_reloc_p (fixp
->fx_r_type
)))
16527 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16528 to a floating-point stub. The same is true for non-R_MIPS16_26
16529 relocations against MIPS16 functions; in this case, the stub becomes
16530 the function's canonical address.
16532 Floating-point stubs are stored in unique .mips16.call.* or
16533 .mips16.fn.* sections. If a stub T for function F is in section S,
16534 the first relocation in section S must be against F; this is how the
16535 linker determines the target function. All relocations that might
16536 resolve to T must also be against F. We therefore have the following
16537 restrictions, which are given in an intentionally-redundant way:
16539 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16542 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16543 if that stub might be used.
16545 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16548 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16549 that stub might be used.
16551 There is a further restriction:
16553 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16554 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16555 targets with in-place addends; the relocation field cannot
16556 encode the low bit.
16558 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16559 against a MIPS16 symbol. We deal with (5) by by not reducing any
16560 such relocations on REL targets.
16562 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16563 relocation against some symbol R, no relocation against R may be
16564 reduced. (Note that this deals with (2) as well as (1) because
16565 relocations against global symbols will never be reduced on ELF
16566 targets.) This approach is a little simpler than trying to detect
16567 stub sections, and gives the "all or nothing" per-symbol consistency
16568 that we have for MIPS16 symbols. */
16569 if (fixp
->fx_subsy
== NULL
16570 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16571 || *symbol_get_tc (fixp
->fx_addsy
)
16572 || (HAVE_IN_PLACE_ADDENDS
16573 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16574 && jmp_reloc_p (fixp
->fx_r_type
))))
16580 /* Translate internal representation of relocation info to BFD target
16584 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16586 static arelent
*retval
[4];
16588 bfd_reloc_code_real_type code
;
16590 memset (retval
, 0, sizeof(retval
));
16591 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16592 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16593 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16594 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16596 if (fixp
->fx_pcrel
)
16598 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16599 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16600 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16601 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16602 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16604 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16605 Relocations want only the symbol offset. */
16606 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16609 reloc
->addend
= fixp
->fx_addnumber
;
16611 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16612 entry to be used in the relocation's section offset. */
16613 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16615 reloc
->address
= reloc
->addend
;
16619 code
= fixp
->fx_r_type
;
16621 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16622 if (reloc
->howto
== NULL
)
16624 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16625 _("cannot represent %s relocation in this object file"
16627 bfd_get_reloc_code_name (code
));
16634 /* Relax a machine dependent frag. This returns the amount by which
16635 the current size of the frag should change. */
16638 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16640 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16642 offsetT old_var
= fragp
->fr_var
;
16644 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16646 return fragp
->fr_var
- old_var
;
16649 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16651 offsetT old_var
= fragp
->fr_var
;
16652 offsetT new_var
= 4;
16654 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16655 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16656 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16657 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16658 fragp
->fr_var
= new_var
;
16660 return new_var
- old_var
;
16663 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16666 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16668 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16670 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16675 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16677 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16684 /* Convert a machine dependent frag. */
16687 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16689 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16692 unsigned long insn
;
16696 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16697 insn
= read_insn (buf
);
16699 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16701 /* We generate a fixup instead of applying it right now
16702 because, if there are linker relaxations, we're going to
16703 need the relocations. */
16704 exp
.X_op
= O_symbol
;
16705 exp
.X_add_symbol
= fragp
->fr_symbol
;
16706 exp
.X_add_number
= fragp
->fr_offset
;
16708 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16709 BFD_RELOC_16_PCREL_S2
);
16710 fixp
->fx_file
= fragp
->fr_file
;
16711 fixp
->fx_line
= fragp
->fr_line
;
16713 buf
= write_insn (buf
, insn
);
16719 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16720 _("relaxed out-of-range branch into a jump"));
16722 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16725 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16727 /* Reverse the branch. */
16728 switch ((insn
>> 28) & 0xf)
16731 if ((insn
& 0xff000000) == 0x47000000
16732 || (insn
& 0xff600000) == 0x45600000)
16734 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
16735 reversed by tweaking bit 23. */
16736 insn
^= 0x00800000;
16740 /* bc[0-3][tf]l? instructions can have the condition
16741 reversed by tweaking a single TF bit, and their
16742 opcodes all have 0x4???????. */
16743 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16744 insn
^= 0x00010000;
16749 /* bltz 0x04000000 bgez 0x04010000
16750 bltzal 0x04100000 bgezal 0x04110000 */
16751 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16752 insn
^= 0x00010000;
16756 /* beq 0x10000000 bne 0x14000000
16757 blez 0x18000000 bgtz 0x1c000000 */
16758 insn
^= 0x04000000;
16766 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16768 /* Clear the and-link bit. */
16769 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16771 /* bltzal 0x04100000 bgezal 0x04110000
16772 bltzall 0x04120000 bgezall 0x04130000 */
16773 insn
&= ~0x00100000;
16776 /* Branch over the branch (if the branch was likely) or the
16777 full jump (not likely case). Compute the offset from the
16778 current instruction to branch to. */
16779 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16783 /* How many bytes in instructions we've already emitted? */
16784 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16785 /* How many bytes in instructions from here to the end? */
16786 i
= fragp
->fr_var
- i
;
16788 /* Convert to instruction count. */
16790 /* Branch counts from the next instruction. */
16793 /* Branch over the jump. */
16794 buf
= write_insn (buf
, insn
);
16797 buf
= write_insn (buf
, 0);
16799 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16801 /* beql $0, $0, 2f */
16803 /* Compute the PC offset from the current instruction to
16804 the end of the variable frag. */
16805 /* How many bytes in instructions we've already emitted? */
16806 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16807 /* How many bytes in instructions from here to the end? */
16808 i
= fragp
->fr_var
- i
;
16809 /* Convert to instruction count. */
16811 /* Don't decrement i, because we want to branch over the
16815 buf
= write_insn (buf
, insn
);
16816 buf
= write_insn (buf
, 0);
16820 if (mips_pic
== NO_PIC
)
16823 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16824 ? 0x0c000000 : 0x08000000);
16825 exp
.X_op
= O_symbol
;
16826 exp
.X_add_symbol
= fragp
->fr_symbol
;
16827 exp
.X_add_number
= fragp
->fr_offset
;
16829 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16830 FALSE
, BFD_RELOC_MIPS_JMP
);
16831 fixp
->fx_file
= fragp
->fr_file
;
16832 fixp
->fx_line
= fragp
->fr_line
;
16834 buf
= write_insn (buf
, insn
);
16838 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16840 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16841 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16842 insn
|= at
<< OP_SH_RT
;
16843 exp
.X_op
= O_symbol
;
16844 exp
.X_add_symbol
= fragp
->fr_symbol
;
16845 exp
.X_add_number
= fragp
->fr_offset
;
16847 if (fragp
->fr_offset
)
16849 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16850 exp
.X_add_number
= 0;
16853 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16854 FALSE
, BFD_RELOC_MIPS_GOT16
);
16855 fixp
->fx_file
= fragp
->fr_file
;
16856 fixp
->fx_line
= fragp
->fr_line
;
16858 buf
= write_insn (buf
, insn
);
16860 if (mips_opts
.isa
== ISA_MIPS1
)
16862 buf
= write_insn (buf
, 0);
16864 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16865 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16866 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16868 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16869 FALSE
, BFD_RELOC_LO16
);
16870 fixp
->fx_file
= fragp
->fr_file
;
16871 fixp
->fx_line
= fragp
->fr_line
;
16873 buf
= write_insn (buf
, insn
);
16876 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16880 insn
|= at
<< OP_SH_RS
;
16882 buf
= write_insn (buf
, insn
);
16886 fragp
->fr_fix
+= fragp
->fr_var
;
16887 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16891 /* Relax microMIPS branches. */
16892 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16894 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16895 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16896 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16897 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16898 bfd_boolean short_ds
;
16899 unsigned long insn
;
16903 exp
.X_op
= O_symbol
;
16904 exp
.X_add_symbol
= fragp
->fr_symbol
;
16905 exp
.X_add_number
= fragp
->fr_offset
;
16907 fragp
->fr_fix
+= fragp
->fr_var
;
16909 /* Handle 16-bit branches that fit or are forced to fit. */
16910 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16912 /* We generate a fixup instead of applying it right now,
16913 because if there is linker relaxation, we're going to
16914 need the relocations. */
16916 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16917 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16918 else if (type
== 'E')
16919 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16920 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16924 fixp
->fx_file
= fragp
->fr_file
;
16925 fixp
->fx_line
= fragp
->fr_line
;
16927 /* These relocations can have an addend that won't fit in
16929 fixp
->fx_no_overflow
= 1;
16934 /* Handle 32-bit branches that fit or are forced to fit. */
16935 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16936 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16938 /* We generate a fixup instead of applying it right now,
16939 because if there is linker relaxation, we're going to
16940 need the relocations. */
16941 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16942 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16943 fixp
->fx_file
= fragp
->fr_file
;
16944 fixp
->fx_line
= fragp
->fr_line
;
16950 /* Relax 16-bit branches to 32-bit branches. */
16953 insn
= read_compressed_insn (buf
, 2);
16955 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16956 insn
= 0x94000000; /* beq */
16957 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16959 unsigned long regno
;
16961 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16962 regno
= micromips_to_32_reg_d_map
[regno
];
16963 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16964 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16969 /* Nothing else to do, just write it out. */
16970 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16971 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16973 buf
= write_compressed_insn (buf
, insn
, 4);
16974 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16979 insn
= read_compressed_insn (buf
, 4);
16981 /* Relax 32-bit branches to a sequence of instructions. */
16982 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16983 _("relaxed out-of-range branch into a jump"));
16985 /* Set the short-delay-slot bit. */
16986 short_ds
= al
&& (insn
& 0x02000000) != 0;
16988 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16992 /* Reverse the branch. */
16993 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16994 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16995 insn
^= 0x20000000;
16996 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16997 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16998 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16999 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17000 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17001 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17002 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17003 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17004 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17005 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17006 insn
^= 0x00400000;
17007 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17008 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17009 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17010 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17011 insn
^= 0x00200000;
17012 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
17014 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
17016 insn
^= 0x00800000;
17022 /* Clear the and-link and short-delay-slot bits. */
17023 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17025 /* bltzal 0x40200000 bgezal 0x40600000 */
17026 /* bltzals 0x42200000 bgezals 0x42600000 */
17027 insn
&= ~0x02200000;
17030 /* Make a label at the end for use with the branch. */
17031 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17032 micromips_label_inc ();
17033 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17036 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17037 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17038 fixp
->fx_file
= fragp
->fr_file
;
17039 fixp
->fx_line
= fragp
->fr_line
;
17041 /* Branch over the jump. */
17042 buf
= write_compressed_insn (buf
, insn
, 4);
17045 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17048 if (mips_pic
== NO_PIC
)
17050 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17052 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17053 insn
= al
? jal
: 0xd4000000;
17055 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17056 BFD_RELOC_MICROMIPS_JMP
);
17057 fixp
->fx_file
= fragp
->fr_file
;
17058 fixp
->fx_line
= fragp
->fr_line
;
17060 buf
= write_compressed_insn (buf
, insn
, 4);
17063 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17067 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17068 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17069 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17071 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17072 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17073 insn
|= at
<< MICROMIPSOP_SH_RT
;
17075 if (exp
.X_add_number
)
17077 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17078 exp
.X_add_number
= 0;
17081 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17082 BFD_RELOC_MICROMIPS_GOT16
);
17083 fixp
->fx_file
= fragp
->fr_file
;
17084 fixp
->fx_line
= fragp
->fr_line
;
17086 buf
= write_compressed_insn (buf
, insn
, 4);
17088 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17089 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17090 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17092 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17093 BFD_RELOC_MICROMIPS_LO16
);
17094 fixp
->fx_file
= fragp
->fr_file
;
17095 fixp
->fx_line
= fragp
->fr_line
;
17097 buf
= write_compressed_insn (buf
, insn
, 4);
17099 /* jr/jrc/jalr/jalrs $at */
17100 insn
= al
? jalr
: jr
;
17101 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17103 buf
= write_compressed_insn (buf
, insn
, 2);
17106 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17110 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17113 const struct mips_int_operand
*operand
;
17116 unsigned int user_length
, length
;
17117 unsigned long insn
;
17120 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17121 operand
= mips16_immed_operand (type
, FALSE
);
17123 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17124 val
= resolve_symbol_value (fragp
->fr_symbol
);
17125 if (operand
->root
.type
== OP_PCREL
)
17127 const struct mips_pcrel_operand
*pcrel_op
;
17130 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17131 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17133 /* The rules for the base address of a PC relative reloc are
17134 complicated; see mips16_extended_frag. */
17135 if (pcrel_op
->include_isa_bit
)
17140 /* Ignore the low bit in the target, since it will be
17141 set for a text label. */
17144 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17146 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17149 addr
&= -(1 << pcrel_op
->align_log2
);
17152 /* Make sure the section winds up with the alignment we have
17154 if (operand
->shift
> 0)
17155 record_alignment (asec
, operand
->shift
);
17159 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17160 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17161 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17162 _("extended instruction in delay slot"));
17164 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17166 insn
= read_compressed_insn (buf
, 2);
17168 insn
|= MIPS16_EXTEND
;
17170 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17172 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17177 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17178 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17180 length
= (ext
? 4 : 2);
17181 gas_assert (mips16_opcode_length (insn
) == length
);
17182 write_compressed_insn (buf
, insn
, length
);
17183 fragp
->fr_fix
+= length
;
17187 relax_substateT subtype
= fragp
->fr_subtype
;
17188 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17189 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17193 first
= RELAX_FIRST (subtype
);
17194 second
= RELAX_SECOND (subtype
);
17195 fixp
= (fixS
*) fragp
->fr_opcode
;
17197 /* If the delay slot chosen does not match the size of the instruction,
17198 then emit a warning. */
17199 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17200 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17205 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17206 | RELAX_DELAY_SLOT_SIZE_FIRST
17207 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17208 msg
= macro_warning (s
);
17210 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17214 /* Possibly emit a warning if we've chosen the longer option. */
17215 if (use_second
== second_longer
)
17221 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17222 msg
= macro_warning (s
);
17224 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17228 /* Go through all the fixups for the first sequence. Disable them
17229 (by marking them as done) if we're going to use the second
17230 sequence instead. */
17232 && fixp
->fx_frag
== fragp
17233 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17235 if (subtype
& RELAX_USE_SECOND
)
17237 fixp
= fixp
->fx_next
;
17240 /* Go through the fixups for the second sequence. Disable them if
17241 we're going to use the first sequence, otherwise adjust their
17242 addresses to account for the relaxation. */
17243 while (fixp
&& fixp
->fx_frag
== fragp
)
17245 if (subtype
& RELAX_USE_SECOND
)
17246 fixp
->fx_where
-= first
;
17249 fixp
= fixp
->fx_next
;
17252 /* Now modify the frag contents. */
17253 if (subtype
& RELAX_USE_SECOND
)
17257 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17258 memmove (start
, start
+ first
, second
);
17259 fragp
->fr_fix
-= first
;
17262 fragp
->fr_fix
-= second
;
17266 /* This function is called after the relocs have been generated.
17267 We've been storing mips16 text labels as odd. Here we convert them
17268 back to even for the convenience of the debugger. */
17271 mips_frob_file_after_relocs (void)
17274 unsigned int count
, i
;
17276 syms
= bfd_get_outsymbols (stdoutput
);
17277 count
= bfd_get_symcount (stdoutput
);
17278 for (i
= 0; i
< count
; i
++, syms
++)
17279 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17280 && ((*syms
)->value
& 1) != 0)
17282 (*syms
)->value
&= ~1;
17283 /* If the symbol has an odd size, it was probably computed
17284 incorrectly, so adjust that as well. */
17285 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17286 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17290 /* This function is called whenever a label is defined, including fake
17291 labels instantiated off the dot special symbol. It is used when
17292 handling branch delays; if a branch has a label, we assume we cannot
17293 move it. This also bumps the value of the symbol by 1 in compressed
17297 mips_record_label (symbolS
*sym
)
17299 segment_info_type
*si
= seg_info (now_seg
);
17300 struct insn_label_list
*l
;
17302 if (free_insn_labels
== NULL
)
17303 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17306 l
= free_insn_labels
;
17307 free_insn_labels
= l
->next
;
17311 l
->next
= si
->label_list
;
17312 si
->label_list
= l
;
17315 /* This function is called as tc_frob_label() whenever a label is defined
17316 and adds a DWARF-2 record we only want for true labels. */
17319 mips_define_label (symbolS
*sym
)
17321 mips_record_label (sym
);
17322 dwarf2_emit_label (sym
);
17325 /* This function is called by tc_new_dot_label whenever a new dot symbol
17329 mips_add_dot_label (symbolS
*sym
)
17331 mips_record_label (sym
);
17332 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17333 mips_compressed_mark_label (sym
);
17336 /* Some special processing for a MIPS ELF file. */
17339 mips_elf_final_processing (void)
17341 /* Write out the register information. */
17342 if (mips_abi
!= N64_ABI
)
17346 s
.ri_gprmask
= mips_gprmask
;
17347 s
.ri_cprmask
[0] = mips_cprmask
[0];
17348 s
.ri_cprmask
[1] = mips_cprmask
[1];
17349 s
.ri_cprmask
[2] = mips_cprmask
[2];
17350 s
.ri_cprmask
[3] = mips_cprmask
[3];
17351 /* The gp_value field is set by the MIPS ELF backend. */
17353 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17354 ((Elf32_External_RegInfo
*)
17355 mips_regmask_frag
));
17359 Elf64_Internal_RegInfo s
;
17361 s
.ri_gprmask
= mips_gprmask
;
17363 s
.ri_cprmask
[0] = mips_cprmask
[0];
17364 s
.ri_cprmask
[1] = mips_cprmask
[1];
17365 s
.ri_cprmask
[2] = mips_cprmask
[2];
17366 s
.ri_cprmask
[3] = mips_cprmask
[3];
17367 /* The gp_value field is set by the MIPS ELF backend. */
17369 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17370 ((Elf64_External_RegInfo
*)
17371 mips_regmask_frag
));
17374 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17375 sort of BFD interface for this. */
17376 if (mips_any_noreorder
)
17377 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17378 if (mips_pic
!= NO_PIC
)
17380 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17381 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17384 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17386 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17387 defined at present; this might need to change in future. */
17388 if (file_ase_mips16
)
17389 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17390 if (file_ase_micromips
)
17391 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17392 if (file_ase
& ASE_MDMX
)
17393 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17395 /* Set the MIPS ELF ABI flags. */
17396 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17397 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17398 else if (mips_abi
== O64_ABI
)
17399 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17400 else if (mips_abi
== EABI_ABI
)
17402 if (!file_mips_opts
.gp32
)
17403 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17405 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17407 else if (mips_abi
== N32_ABI
)
17408 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17410 /* Nothing to do for N64_ABI. */
17412 if (mips_32bitmode
)
17413 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17415 if (mips_flag_nan2008
)
17416 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17418 /* 32 bit code with 64 bit FP registers. */
17419 if (file_mips_opts
.fp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
17420 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
17423 typedef struct proc
{
17425 symbolS
*func_end_sym
;
17426 unsigned long reg_mask
;
17427 unsigned long reg_offset
;
17428 unsigned long fpreg_mask
;
17429 unsigned long fpreg_offset
;
17430 unsigned long frame_offset
;
17431 unsigned long frame_reg
;
17432 unsigned long pc_reg
;
17435 static procS cur_proc
;
17436 static procS
*cur_proc_ptr
;
17437 static int numprocs
;
17439 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17440 as "2", and a normal nop as "0". */
17442 #define NOP_OPCODE_MIPS 0
17443 #define NOP_OPCODE_MIPS16 1
17444 #define NOP_OPCODE_MICROMIPS 2
17447 mips_nop_opcode (void)
17449 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17450 return NOP_OPCODE_MICROMIPS
;
17451 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17452 return NOP_OPCODE_MIPS16
;
17454 return NOP_OPCODE_MIPS
;
17457 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17458 32-bit microMIPS NOPs here (if applicable). */
17461 mips_handle_align (fragS
*fragp
)
17465 int bytes
, size
, excess
;
17468 if (fragp
->fr_type
!= rs_align_code
)
17471 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17473 switch (nop_opcode
)
17475 case NOP_OPCODE_MICROMIPS
:
17476 opcode
= micromips_nop32_insn
.insn_opcode
;
17479 case NOP_OPCODE_MIPS16
:
17480 opcode
= mips16_nop_insn
.insn_opcode
;
17483 case NOP_OPCODE_MIPS
:
17485 opcode
= nop_insn
.insn_opcode
;
17490 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17491 excess
= bytes
% size
;
17493 /* Handle the leading part if we're not inserting a whole number of
17494 instructions, and make it the end of the fixed part of the frag.
17495 Try to fit in a short microMIPS NOP if applicable and possible,
17496 and use zeroes otherwise. */
17497 gas_assert (excess
< 4);
17498 fragp
->fr_fix
+= excess
;
17503 /* Fall through. */
17505 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17507 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17511 /* Fall through. */
17514 /* Fall through. */
17519 md_number_to_chars (p
, opcode
, size
);
17520 fragp
->fr_var
= size
;
17524 md_obj_begin (void)
17531 /* Check for premature end, nesting errors, etc. */
17533 as_warn (_("missing .end at end of assembly"));
17542 if (*input_line_pointer
== '-')
17544 ++input_line_pointer
;
17547 if (!ISDIGIT (*input_line_pointer
))
17548 as_bad (_("expected simple number"));
17549 if (input_line_pointer
[0] == '0')
17551 if (input_line_pointer
[1] == 'x')
17553 input_line_pointer
+= 2;
17554 while (ISXDIGIT (*input_line_pointer
))
17557 val
|= hex_value (*input_line_pointer
++);
17559 return negative
? -val
: val
;
17563 ++input_line_pointer
;
17564 while (ISDIGIT (*input_line_pointer
))
17567 val
|= *input_line_pointer
++ - '0';
17569 return negative
? -val
: val
;
17572 if (!ISDIGIT (*input_line_pointer
))
17574 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17575 *input_line_pointer
, *input_line_pointer
);
17576 as_warn (_("invalid number"));
17579 while (ISDIGIT (*input_line_pointer
))
17582 val
+= *input_line_pointer
++ - '0';
17584 return negative
? -val
: val
;
17587 /* The .file directive; just like the usual .file directive, but there
17588 is an initial number which is the ECOFF file index. In the non-ECOFF
17589 case .file implies DWARF-2. */
17592 s_mips_file (int x ATTRIBUTE_UNUSED
)
17594 static int first_file_directive
= 0;
17596 if (ECOFF_DEBUGGING
)
17605 filename
= dwarf2_directive_file (0);
17607 /* Versions of GCC up to 3.1 start files with a ".file"
17608 directive even for stabs output. Make sure that this
17609 ".file" is handled. Note that you need a version of GCC
17610 after 3.1 in order to support DWARF-2 on MIPS. */
17611 if (filename
!= NULL
&& ! first_file_directive
)
17613 (void) new_logical_line (filename
, -1);
17614 s_app_file_string (filename
, 0);
17616 first_file_directive
= 1;
17620 /* The .loc directive, implying DWARF-2. */
17623 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17625 if (!ECOFF_DEBUGGING
)
17626 dwarf2_directive_loc (0);
17629 /* The .end directive. */
17632 s_mips_end (int x ATTRIBUTE_UNUSED
)
17636 /* Following functions need their own .frame and .cprestore directives. */
17637 mips_frame_reg_valid
= 0;
17638 mips_cprestore_valid
= 0;
17640 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17643 demand_empty_rest_of_line ();
17648 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17649 as_warn (_(".end not in text section"));
17653 as_warn (_(".end directive without a preceding .ent directive"));
17654 demand_empty_rest_of_line ();
17660 gas_assert (S_GET_NAME (p
));
17661 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17662 as_warn (_(".end symbol does not match .ent symbol"));
17664 if (debug_type
== DEBUG_STABS
)
17665 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17669 as_warn (_(".end directive missing or unknown symbol"));
17671 /* Create an expression to calculate the size of the function. */
17672 if (p
&& cur_proc_ptr
)
17674 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17675 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17678 exp
->X_op
= O_subtract
;
17679 exp
->X_add_symbol
= symbol_temp_new_now ();
17680 exp
->X_op_symbol
= p
;
17681 exp
->X_add_number
= 0;
17683 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17686 /* Generate a .pdr section. */
17687 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17689 segT saved_seg
= now_seg
;
17690 subsegT saved_subseg
= now_subseg
;
17694 #ifdef md_flush_pending_output
17695 md_flush_pending_output ();
17698 gas_assert (pdr_seg
);
17699 subseg_set (pdr_seg
, 0);
17701 /* Write the symbol. */
17702 exp
.X_op
= O_symbol
;
17703 exp
.X_add_symbol
= p
;
17704 exp
.X_add_number
= 0;
17705 emit_expr (&exp
, 4);
17707 fragp
= frag_more (7 * 4);
17709 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17710 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17711 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17712 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17713 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17714 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17715 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17717 subseg_set (saved_seg
, saved_subseg
);
17720 cur_proc_ptr
= NULL
;
17723 /* The .aent and .ent directives. */
17726 s_mips_ent (int aent
)
17730 symbolP
= get_symbol ();
17731 if (*input_line_pointer
== ',')
17732 ++input_line_pointer
;
17733 SKIP_WHITESPACE ();
17734 if (ISDIGIT (*input_line_pointer
)
17735 || *input_line_pointer
== '-')
17738 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17739 as_warn (_(".ent or .aent not in text section"));
17741 if (!aent
&& cur_proc_ptr
)
17742 as_warn (_("missing .end"));
17746 /* This function needs its own .frame and .cprestore directives. */
17747 mips_frame_reg_valid
= 0;
17748 mips_cprestore_valid
= 0;
17750 cur_proc_ptr
= &cur_proc
;
17751 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17753 cur_proc_ptr
->func_sym
= symbolP
;
17757 if (debug_type
== DEBUG_STABS
)
17758 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17759 S_GET_NAME (symbolP
));
17762 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17764 demand_empty_rest_of_line ();
17767 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17768 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17769 s_mips_frame is used so that we can set the PDR information correctly.
17770 We can't use the ecoff routines because they make reference to the ecoff
17771 symbol table (in the mdebug section). */
17774 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17776 if (ECOFF_DEBUGGING
)
17782 if (cur_proc_ptr
== (procS
*) NULL
)
17784 as_warn (_(".frame outside of .ent"));
17785 demand_empty_rest_of_line ();
17789 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17791 SKIP_WHITESPACE ();
17792 if (*input_line_pointer
++ != ','
17793 || get_absolute_expression_and_terminator (&val
) != ',')
17795 as_warn (_("bad .frame directive"));
17796 --input_line_pointer
;
17797 demand_empty_rest_of_line ();
17801 cur_proc_ptr
->frame_offset
= val
;
17802 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17804 demand_empty_rest_of_line ();
17808 /* The .fmask and .mask directives. If the mdebug section is present
17809 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17810 embedded targets, s_mips_mask is used so that we can set the PDR
17811 information correctly. We can't use the ecoff routines because they
17812 make reference to the ecoff symbol table (in the mdebug section). */
17815 s_mips_mask (int reg_type
)
17817 if (ECOFF_DEBUGGING
)
17818 s_ignore (reg_type
);
17823 if (cur_proc_ptr
== (procS
*) NULL
)
17825 as_warn (_(".mask/.fmask outside of .ent"));
17826 demand_empty_rest_of_line ();
17830 if (get_absolute_expression_and_terminator (&mask
) != ',')
17832 as_warn (_("bad .mask/.fmask directive"));
17833 --input_line_pointer
;
17834 demand_empty_rest_of_line ();
17838 off
= get_absolute_expression ();
17840 if (reg_type
== 'F')
17842 cur_proc_ptr
->fpreg_mask
= mask
;
17843 cur_proc_ptr
->fpreg_offset
= off
;
17847 cur_proc_ptr
->reg_mask
= mask
;
17848 cur_proc_ptr
->reg_offset
= off
;
17851 demand_empty_rest_of_line ();
17855 /* A table describing all the processors gas knows about. Names are
17856 matched in the order listed.
17858 To ease comparison, please keep this table in the same order as
17859 gcc's mips_cpu_info_table[]. */
17860 static const struct mips_cpu_info mips_cpu_info_table
[] =
17862 /* Entries for generic ISAs */
17863 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17864 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17865 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17866 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17867 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17868 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17869 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17870 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
17871 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
17872 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17873 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17874 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
17875 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
17878 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17879 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17880 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17883 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17886 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17887 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17888 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17889 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17890 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17891 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17892 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17893 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17894 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17895 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17896 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17897 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17898 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17899 /* ST Microelectronics Loongson 2E and 2F cores */
17900 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17901 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17904 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17905 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17906 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17907 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17908 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17909 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17910 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17911 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17912 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17913 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17914 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17915 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17916 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17917 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17918 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17921 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17922 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17923 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17924 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17926 /* MIPS 32 Release 2 */
17927 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17928 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17929 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17930 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17931 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17932 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17933 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17934 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17935 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17936 ISA_MIPS32R2
, CPU_MIPS32R2
},
17937 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17938 ISA_MIPS32R2
, CPU_MIPS32R2
},
17939 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17940 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17941 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17942 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17943 /* Deprecated forms of the above. */
17944 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17945 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17946 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17947 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17948 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17949 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17950 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17951 /* Deprecated forms of the above. */
17952 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17953 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17954 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17955 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17956 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17957 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17958 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17959 /* Deprecated forms of the above. */
17960 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17961 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17962 /* 34Kn is a 34kc without DSP. */
17963 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17964 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17965 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17966 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17967 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17968 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17969 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17970 /* Deprecated forms of the above. */
17971 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17972 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17973 /* 1004K cores are multiprocessor versions of the 34K. */
17974 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17975 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17976 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17977 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17978 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
17979 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
17982 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17983 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17984 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17985 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17987 /* Broadcom SB-1 CPU core */
17988 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17989 /* Broadcom SB-1A CPU core */
17990 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17992 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
17994 /* MIPS 64 Release 2 */
17996 /* Cavium Networks Octeon CPU core */
17997 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17998 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17999 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
18002 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
18005 XLP is mostly like XLR, with the prominent exception that it is
18006 MIPS64R2 rather than MIPS64. */
18007 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
18010 { NULL
, 0, 0, 0, 0 }
18014 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18015 with a final "000" replaced by "k". Ignore case.
18017 Note: this function is shared between GCC and GAS. */
18020 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18022 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18023 given
++, canonical
++;
18025 return ((*given
== 0 && *canonical
== 0)
18026 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18030 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18031 CPU name. We've traditionally allowed a lot of variation here.
18033 Note: this function is shared between GCC and GAS. */
18036 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18038 /* First see if the name matches exactly, or with a final "000"
18039 turned into "k". */
18040 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18043 /* If not, try comparing based on numerical designation alone.
18044 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18045 if (TOLOWER (*given
) == 'r')
18047 if (!ISDIGIT (*given
))
18050 /* Skip over some well-known prefixes in the canonical name,
18051 hoping to find a number there too. */
18052 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18054 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18056 else if (TOLOWER (canonical
[0]) == 'r')
18059 return mips_strict_matching_cpu_name_p (canonical
, given
);
18063 /* Parse an option that takes the name of a processor as its argument.
18064 OPTION is the name of the option and CPU_STRING is the argument.
18065 Return the corresponding processor enumeration if the CPU_STRING is
18066 recognized, otherwise report an error and return null.
18068 A similar function exists in GCC. */
18070 static const struct mips_cpu_info
*
18071 mips_parse_cpu (const char *option
, const char *cpu_string
)
18073 const struct mips_cpu_info
*p
;
18075 /* 'from-abi' selects the most compatible architecture for the given
18076 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18077 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18078 version. Look first at the -mgp options, if given, otherwise base
18079 the choice on MIPS_DEFAULT_64BIT.
18081 Treat NO_ABI like the EABIs. One reason to do this is that the
18082 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18083 architecture. This code picks MIPS I for 'mips' and MIPS III for
18084 'mips64', just as we did in the days before 'from-abi'. */
18085 if (strcasecmp (cpu_string
, "from-abi") == 0)
18087 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18088 return mips_cpu_info_from_isa (ISA_MIPS1
);
18090 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18091 return mips_cpu_info_from_isa (ISA_MIPS3
);
18093 if (file_mips_opts
.gp32
>= 0)
18094 return mips_cpu_info_from_isa (file_mips_opts
.gp32
18095 ? ISA_MIPS1
: ISA_MIPS3
);
18097 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18102 /* 'default' has traditionally been a no-op. Probably not very useful. */
18103 if (strcasecmp (cpu_string
, "default") == 0)
18106 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18107 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18110 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
18114 /* Return the canonical processor information for ISA (a member of the
18115 ISA_MIPS* enumeration). */
18117 static const struct mips_cpu_info
*
18118 mips_cpu_info_from_isa (int isa
)
18122 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18123 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18124 && isa
== mips_cpu_info_table
[i
].isa
)
18125 return (&mips_cpu_info_table
[i
]);
18130 static const struct mips_cpu_info
*
18131 mips_cpu_info_from_arch (int arch
)
18135 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18136 if (arch
== mips_cpu_info_table
[i
].cpu
)
18137 return (&mips_cpu_info_table
[i
]);
18143 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18147 fprintf (stream
, "%24s", "");
18152 fprintf (stream
, ", ");
18156 if (*col_p
+ strlen (string
) > 72)
18158 fprintf (stream
, "\n%24s", "");
18162 fprintf (stream
, "%s", string
);
18163 *col_p
+= strlen (string
);
18169 md_show_usage (FILE *stream
)
18174 fprintf (stream
, _("\
18176 -EB generate big endian output\n\
18177 -EL generate little endian output\n\
18178 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18179 -G NUM allow referencing objects up to NUM bytes\n\
18180 implicitly with the gp register [default 8]\n"));
18181 fprintf (stream
, _("\
18182 -mips1 generate MIPS ISA I instructions\n\
18183 -mips2 generate MIPS ISA II instructions\n\
18184 -mips3 generate MIPS ISA III instructions\n\
18185 -mips4 generate MIPS ISA IV instructions\n\
18186 -mips5 generate MIPS ISA V instructions\n\
18187 -mips32 generate MIPS32 ISA instructions\n\
18188 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18189 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18190 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18191 -mips64 generate MIPS64 ISA instructions\n\
18192 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18193 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18194 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18195 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18199 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18200 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18201 show (stream
, "from-abi", &column
, &first
);
18202 fputc ('\n', stream
);
18204 fprintf (stream
, _("\
18205 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18206 -no-mCPU don't generate code specific to CPU.\n\
18207 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18211 show (stream
, "3900", &column
, &first
);
18212 show (stream
, "4010", &column
, &first
);
18213 show (stream
, "4100", &column
, &first
);
18214 show (stream
, "4650", &column
, &first
);
18215 fputc ('\n', stream
);
18217 fprintf (stream
, _("\
18218 -mips16 generate mips16 instructions\n\
18219 -no-mips16 do not generate mips16 instructions\n"));
18220 fprintf (stream
, _("\
18221 -mmicromips generate microMIPS instructions\n\
18222 -mno-micromips do not generate microMIPS instructions\n"));
18223 fprintf (stream
, _("\
18224 -msmartmips generate smartmips instructions\n\
18225 -mno-smartmips do not generate smartmips instructions\n"));
18226 fprintf (stream
, _("\
18227 -mdsp generate DSP instructions\n\
18228 -mno-dsp do not generate DSP instructions\n"));
18229 fprintf (stream
, _("\
18230 -mdspr2 generate DSP R2 instructions\n\
18231 -mno-dspr2 do not generate DSP R2 instructions\n"));
18232 fprintf (stream
, _("\
18233 -mmt generate MT instructions\n\
18234 -mno-mt do not generate MT instructions\n"));
18235 fprintf (stream
, _("\
18236 -mmcu generate MCU instructions\n\
18237 -mno-mcu do not generate MCU instructions\n"));
18238 fprintf (stream
, _("\
18239 -mmsa generate MSA instructions\n\
18240 -mno-msa do not generate MSA instructions\n"));
18241 fprintf (stream
, _("\
18242 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18243 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18244 fprintf (stream
, _("\
18245 -mvirt generate Virtualization instructions\n\
18246 -mno-virt do not generate Virtualization instructions\n"));
18247 fprintf (stream
, _("\
18248 -minsn32 only generate 32-bit microMIPS instructions\n\
18249 -mno-insn32 generate all microMIPS instructions\n"));
18250 fprintf (stream
, _("\
18251 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18252 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18253 -mfix-vr4120 work around certain VR4120 errata\n\
18254 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18255 -mfix-24k insert a nop after ERET and DERET instructions\n\
18256 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18257 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18258 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18259 -msym32 assume all symbols have 32-bit values\n\
18260 -O0 remove unneeded NOPs, do not swap branches\n\
18261 -O remove unneeded NOPs and swap branches\n\
18262 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18263 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18264 fprintf (stream
, _("\
18265 -mhard-float allow floating-point instructions\n\
18266 -msoft-float do not allow floating-point instructions\n\
18267 -msingle-float only allow 32-bit floating-point operations\n\
18268 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18269 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18270 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18271 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18275 show (stream
, "legacy", &column
, &first
);
18276 show (stream
, "2008", &column
, &first
);
18278 fputc ('\n', stream
);
18280 fprintf (stream
, _("\
18281 -KPIC, -call_shared generate SVR4 position independent code\n\
18282 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18283 -mvxworks-pic generate VxWorks position independent code\n\
18284 -non_shared do not generate code that can operate with DSOs\n\
18285 -xgot assume a 32 bit GOT\n\
18286 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18287 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18288 position dependent (non shared) code\n\
18289 -mabi=ABI create ABI conformant object file for:\n"));
18293 show (stream
, "32", &column
, &first
);
18294 show (stream
, "o64", &column
, &first
);
18295 show (stream
, "n32", &column
, &first
);
18296 show (stream
, "64", &column
, &first
);
18297 show (stream
, "eabi", &column
, &first
);
18299 fputc ('\n', stream
);
18301 fprintf (stream
, _("\
18302 -32 create o32 ABI object file (default)\n\
18303 -n32 create n32 ABI object file\n\
18304 -64 create 64 ABI object file\n"));
18309 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18311 if (HAVE_64BIT_SYMBOLS
)
18312 return dwarf2_format_64bit_irix
;
18314 return dwarf2_format_32bit
;
18319 mips_dwarf2_addr_size (void)
18321 if (HAVE_64BIT_OBJECTS
)
18327 /* Standard calling conventions leave the CFA at SP on entry. */
18329 mips_cfi_frame_initial_instructions (void)
18331 cfi_add_CFA_def_cfa_register (SP
);
18335 tc_mips_regname_to_dw2regnum (char *regname
)
18337 unsigned int regnum
= -1;
18340 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
18346 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
18347 Given a symbolic attribute NAME, return the proper integer value.
18348 Returns -1 if the attribute is not known. */
18351 mips_convert_symbolic_attribute (const char *name
)
18353 static const struct
18358 attribute_table
[] =
18360 #define T(tag) {#tag, tag}
18361 T (Tag_GNU_MIPS_ABI_FP
),
18362 T (Tag_GNU_MIPS_ABI_MSA
),
18370 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
18371 if (streq (name
, attribute_table
[i
].name
))
18372 return attribute_table
[i
].tag
;