1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* These variables are filled in with the masks of registers used.
69 The object format code reads them and puts them in the appropriate
71 unsigned long mips_gprmask
;
72 unsigned long mips_cprmask
[4];
74 /* MIPS ISA (Instruction Set Architecture) level. */
75 static int mips_isa
= -1;
77 /* MIPS PIC level. 0 is normal, non-PIC code. 2 means to generate
78 SVR4 ABI PIC calls. 1 doesn't mean anything. */
81 static int mips_warn_about_macros
;
82 static int mips_noreorder
;
83 static int mips_any_noreorder
;
84 static int mips_nomove
;
86 static int mips_nobopt
;
89 /* The size of the small data section. */
90 static int g_switch_value
= 8;
96 /* handle of the OPCODE hash table */
97 static struct hash_control
*op_hash
= NULL
;
99 /* This array holds the chars that always start a comment. If the
100 pre-processor is disabled, these aren't very useful */
101 const char comment_chars
[] = "#";
103 /* This array holds the chars that only start a comment at the beginning of
104 a line. If the line seems to have the form '# 123 filename'
105 .line and .file directives will appear in the pre-processed output */
106 /* Note that input_file.c hand checks for '#' at the beginning of the
107 first line of the input file. This is because the compiler outputs
108 #NO_APP at the beginning of its output. */
109 /* Also note that C style comments are always supported. */
110 const char line_comment_chars
[] = "#";
112 /* This array holds machine specific line separator characters. */
113 const char line_separator_chars
[] = "";
115 /* Chars that can be used to separate mant from exp in floating point nums */
116 const char EXP_CHARS
[] = "eE";
118 /* Chars that mean this number is a floating point constant */
121 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
123 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
124 changed in read.c . Ideally it shouldn't have to know about it at all,
125 but nothing is ideal around here.
128 static char *insn_error
;
130 static int byte_order
= BYTE_ORDER
;
132 static int auto_align
= 1;
134 /* Symbol labelling the current insn. */
135 static symbolS
*insn_label
;
137 /* When outputting SVR4 PIC code, the assembler needs to know the
138 offset in the stack frame from which to restore the $gp register.
139 This is set by the .cprestore pseudo-op, and saved in this
141 static offsetT mips_cprestore_offset
= -1;
143 /* This is the register which holds the stack frame, as set by the
144 .frame pseudo-op. This is needed to implement .cprestore. */
145 static int mips_frame_reg
= SP
;
147 /* To output NOP instructions correctly, we need to keep information
148 about the previous two instructions. */
150 /* Whether we are optimizing. The default value of 2 means to remove
151 unneeded NOPs and swap branch instructions when possible. A value
152 of 1 means to not swap branches. A value of 0 means to always
154 static int mips_optimize
= 2;
156 /* The previous instruction. */
157 static struct mips_cl_insn prev_insn
;
159 /* The instruction before prev_insn. */
160 static struct mips_cl_insn prev_prev_insn
;
162 /* If we don't want information for prev_insn or prev_prev_insn, we
163 point the insn_mo field at this dummy integer. */
164 static const struct mips_opcode dummy_opcode
= { 0 };
166 /* Non-zero if prev_insn is valid. */
167 static int prev_insn_valid
;
169 /* The frag for the previous instruction. */
170 static struct frag
*prev_insn_frag
;
172 /* The offset into prev_insn_frag for the previous instruction. */
173 static long prev_insn_where
;
175 /* The reloc for the previous instruction, if any. */
176 static fixS
*prev_insn_fixp
;
178 /* Non-zero if the previous instruction was in a delay slot. */
179 static int prev_insn_is_delay_slot
;
181 /* Non-zero if the previous instruction was in a .set noreorder. */
182 static int prev_insn_unreordered
;
184 /* Non-zero if the previous previous instruction was in a .set
186 static int prev_prev_insn_unreordered
;
188 /* Since the MIPS does not have multiple forms of PC relative
189 instructions, we do not have to do relaxing as is done on other
190 platforms. However, we do have to handle GP relative addressing
191 correctly, which turns out to be a similar problem.
193 Every macro that refers to a symbol can occur in (at least) two
194 forms, one with GP relative addressing and one without. For
195 example, loading a global variable into a register generally uses
196 an macroinstruction like this:
198 If i can be addressed off the GP register (this is true if it is in
199 the .sbss or .sdata section, or if it is known to be smaller than
200 the -G argument) this will generate the following instruction:
202 This instruction will use a GPREL reloc. If i can not be addressed
203 off the GP register, the following instruction sequence will be used:
206 In this case the first instruction will have a HI16 reloc, and the
207 second reloc will have a LO16 reloc. Both relocs will be against
210 The issue here is that we may not know whether i is GP addressable
211 until after we see the instruction that uses it. Therefore, we
212 want to be able to choose the final instruction sequence only at
213 the end of the assembly. This is similar to the way other
214 platforms choose the form of a PC relative instruction only at the
217 When generating position independent code we do not use GP
218 addressing in the same way, but the issue still arises as external
219 symbols and local symbols must be handled differently.
221 We handle these issues by actually generating both possible
222 instruction sequences. The longer one is put in a frag_var with
223 type rs_machine_dependent. We encode what to do with the frag in
224 the subtype field. We encode (1) the number of existing bytes to
225 replace, (2) the number of new bytes to use, (3) the offset from
226 the start of the existing bytes to the first reloc we must generate
227 (that is, the offset is applied from the start of the existing
228 bytes after they are replaced by the new bytes, if any), (4) the
229 offset from the start of the existing bytes to the second reloc,
230 (5) whether a third reloc is needed (the third reloc is always four
231 bytes after the second reloc), and (6) whether to warn if this
232 variant is used (this is sometimes needed if .set nomacro or .set
233 noat is in effect). All these numbers are reasonably small.
235 Generating two instruction sequences must be handled carefully to
236 ensure that delay slots are handled correctly. Fortunately, the
237 issue only arises in a restricted number of cases. When the second
238 instruction sequence is generated, append_insn is directed to
239 maintain the existing delay slot information, so it continues to
240 apply to any code after the second instruction sequence. This
241 means that the second instruction sequence must not impose any
242 requirements not required by the first instruction sequence.
244 These variant frags are then handled in functions called by the
245 machine independent code. md_estimate_size_before_relax returns
246 the final size of the frag. md_convert_frag sets up the final form
247 of the frag. tc_gen_reloc adjust the first reloc and adds a second
249 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
253 | (((reloc1) + 64) << 9) \
254 | (((reloc2) + 64) << 2) \
255 | ((reloc3) ? (1 << 1) : 0) \
257 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
258 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
259 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
260 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
261 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
262 #define RELAX_WARN(i) ((i) & 1)
264 /* Prototypes for static functions. */
267 #define internalError() \
268 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
270 #define internalError() as_fatal ("MIPS internal Error");
273 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
274 unsigned int reg
, int fpr
));
275 static void append_insn
PARAMS ((char *place
,
276 struct mips_cl_insn
* ip
,
278 bfd_reloc_code_real_type r
));
279 static void mips_no_prev_insn
PARAMS ((void));
280 static void mips_emit_delays
PARAMS ((void));
281 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
282 const char *name
, const char *fmt
,
284 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
285 expressionS
* ep
, int regnum
));
286 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
287 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
289 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
290 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
291 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
292 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
293 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
294 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
295 static symbolS
*get_symbol
PARAMS ((void));
296 static void mips_align
PARAMS ((int to
, int fill
));
297 static void s_align
PARAMS ((int));
298 static void s_stringer
PARAMS ((int));
299 static void s_change_sec
PARAMS ((int));
300 static void s_cons
PARAMS ((int));
301 static void s_err
PARAMS ((int));
302 static void s_extern
PARAMS ((int));
303 static void s_float_cons
PARAMS ((int));
304 static void s_option
PARAMS ((int));
305 static void s_mipsset
PARAMS ((int));
306 static void s_mips_space
PARAMS ((int));
307 static void s_abicalls
PARAMS ((int));
308 static void s_cpload
PARAMS ((int));
309 static void s_cprestore
PARAMS ((int));
310 static void s_gpword
PARAMS ((int));
311 static void s_cpadd
PARAMS ((int));
312 #ifndef ECOFF_DEBUGGING
313 static void md_obj_begin
PARAMS ((void));
314 static void md_obj_end
PARAMS ((void));
315 static long get_number
PARAMS ((void));
316 static void s_ent
PARAMS ((int));
317 static void s_mipsend
PARAMS ((int));
318 static void s_file
PARAMS ((int));
320 static void s_frame
PARAMS ((int));
321 static void s_loc
PARAMS ((int));
322 static void s_mask
PARAMS ((char));
328 The following pseudo-ops from the Kane and Heinrich MIPS book
329 should be defined here, but are currently unsupported: .alias,
330 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
332 The following pseudo-ops from the Kane and Heinrich MIPS book are
333 specific to the type of debugging information being generated, and
334 should be defined by the object format: .aent, .begin, .bend,
335 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
338 The following pseudo-ops from the Kane and Heinrich MIPS book are
339 not MIPS CPU specific, but are also not specific to the object file
340 format. This file is probably the best place to define them, but
341 they are not currently supported: .asm0, .endr, .lab, .repeat,
342 .struct, .weakext. */
344 const pseudo_typeS md_pseudo_table
[] =
346 /* MIPS specific pseudo-ops. */
347 {"option", s_option
, 0},
348 {"set", s_mipsset
, 0},
349 {"rdata", s_change_sec
, 'r'},
350 {"sdata", s_change_sec
, 's'},
351 {"livereg", s_ignore
, 0},
352 { "abicalls", s_abicalls
, 0},
353 { "cpload", s_cpload
, 0},
354 { "cprestore", s_cprestore
, 0},
355 { "gpword", s_gpword
, 0},
356 { "cpadd", s_cpadd
, 0},
358 /* Relatively generic pseudo-ops that happen to be used on MIPS
360 {"asciiz", s_stringer
, 1},
361 {"bss", s_change_sec
, 'b'},
364 {"dword", s_cons
, 3},
366 /* These pseudo-ops are defined in read.c, but must be overridden
367 here for one reason or another. */
368 {"align", s_align
, 0},
369 {"ascii", s_stringer
, 0},
370 {"asciz", s_stringer
, 1},
372 {"data", s_change_sec
, 'd'},
373 {"double", s_float_cons
, 'd'},
374 {"extern", s_extern
, 0},
375 {"float", s_float_cons
, 'f'},
376 {"space", s_mips_space
, 0},
377 {"text", s_change_sec
, 't'},
380 #ifndef ECOFF_DEBUGGING
381 /* These pseudo-ops should be defined by the object file format.
382 However, a.out doesn't support them, so we have versions here. */
384 {"bgnb", s_ignore
, 0},
385 {"end", s_mipsend
, 0},
386 {"endb", s_ignore
, 0},
389 {"fmask", s_ignore
, 'F'},
390 {"frame", s_ignore
, 0},
391 {"loc", s_ignore
, 0},
392 {"mask", s_ignore
, 'R'},
393 {"verstamp", s_ignore
, 0},
400 const relax_typeS md_relax_table
[] =
406 static char *expr_end
;
408 static expressionS imm_expr
;
409 static expressionS offset_expr
;
410 static bfd_reloc_code_real_type imm_reloc
;
411 static bfd_reloc_code_real_type offset_reloc
;
413 /* FIXME: This should be handled in a different way. */
414 extern int target_big_endian
;
417 * This function is called once, at assembler startup time. It should
418 * set up all the tables, etc. that the MD part of the assembler will need.
424 register const char *retval
= NULL
;
425 register unsigned int i
= 0;
429 if (strcmp (TARGET_CPU
, "mips") == 0)
431 else if (strcmp (TARGET_CPU
, "r6000") == 0
432 || strcmp (TARGET_CPU
, "mips2") == 0)
434 else if (strcmp (TARGET_CPU
, "mips64") == 0
435 || strcmp (TARGET_CPU
, "r4000") == 0
436 || strcmp (TARGET_CPU
, "mips3") == 0)
445 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
448 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
451 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
455 as_warn ("Could not set architecture and machine");
457 op_hash
= hash_new ();
459 for (i
= 0; i
< NUMOPCODES
;)
461 const char *name
= mips_opcodes
[i
].name
;
463 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
466 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
467 mips_opcodes
[i
].name
, retval
);
468 as_fatal ("Broken assembler. No assembly attempted.");
472 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
473 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
474 != mips_opcodes
[i
].match
))
476 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
477 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
478 as_fatal ("Broken assembler. No assembly attempted.");
482 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
485 mips_no_prev_insn ();
493 /* set the default alignment for the text section (2**2) */
494 record_alignment (text_section
, 2);
496 /* FIXME: This should be handled in a different way. */
497 target_big_endian
= byte_order
== BIG_ENDIAN
;
500 bfd_set_gp_size (stdoutput
, g_switch_value
);
504 /* Sections must be aligned to 16 byte boundaries. */
505 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
506 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
507 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
509 /* Create a .reginfo section for register masks and a .mdebug
510 section for debugging information. */
518 sec
= subseg_new (".reginfo", (subsegT
) 0);
520 /* I don't know why this section should be loaded, but the ABI
521 says that SHF_ALLOC should be set. */
522 (void) bfd_set_section_flags (stdoutput
, sec
,
523 (SEC_ALLOC
| SEC_LOAD
524 | SEC_READONLY
| SEC_DATA
));
525 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
527 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
529 #ifdef ECOFF_DEBUGGING
530 sec
= subseg_new (".mdebug", (subsegT
) 0);
531 (void) bfd_set_section_flags (stdoutput
, sec
,
532 SEC_HAS_CONTENTS
| SEC_READONLY
);
533 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
536 subseg_set (seg
, subseg
);
540 #ifndef ECOFF_DEBUGGING
548 #ifndef ECOFF_DEBUGGING
557 struct mips_cl_insn insn
;
559 imm_expr
.X_op
= O_absent
;
560 offset_expr
.X_op
= O_absent
;
562 mips_ip (str
, &insn
);
565 as_bad ("%s `%s'", insn_error
, str
);
568 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
574 if (imm_expr
.X_op
!= O_absent
)
575 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
576 else if (offset_expr
.X_op
!= O_absent
)
577 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
579 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
583 /* See whether instruction IP reads register REG. If FPR is non-zero,
584 REG is a floating point register. */
587 insn_uses_reg (ip
, reg
, fpr
)
588 struct mips_cl_insn
*ip
;
592 /* Don't report on general register 0, since it never changes. */
593 if (! fpr
&& reg
== 0)
598 /* If we are called with either $f0 or $f1, we must check $f0.
599 This is not optimal, because it will introduce an unnecessary
600 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
601 need to distinguish reading both $f0 and $f1 or just one of
602 them. Note that we don't have to check the other way,
603 because there is no instruction that sets both $f0 and $f1
604 and requires a delay. */
605 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
606 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
607 == (reg
&~ (unsigned) 1)))
609 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
610 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
611 == (reg
&~ (unsigned) 1)))
616 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
617 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
619 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
620 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
627 /* Output an instruction. PLACE is where to put the instruction; if
628 it is NULL, this uses frag_more to get room. IP is the instruction
629 information. ADDRESS_EXPR is an operand of the instruction to be
630 used with RELOC_TYPE. */
633 append_insn (place
, ip
, address_expr
, reloc_type
)
635 struct mips_cl_insn
*ip
;
636 expressionS
*address_expr
;
637 bfd_reloc_code_real_type reloc_type
;
639 register unsigned long prev_pinfo
, pinfo
;
644 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
645 pinfo
= ip
->insn_mo
->pinfo
;
647 if (place
== NULL
&& ! mips_noreorder
)
649 /* If the previous insn required any delay slots, see if we need
650 to insert a NOP or two. There are eight kinds of possible
651 hazards, of which an instruction can have at most one type.
652 (1) a load from memory delay
653 (2) a load from a coprocessor delay
654 (3) an unconditional branch delay
655 (4) a conditional branch delay
656 (5) a move to coprocessor register delay
657 (6) a load coprocessor register from memory delay
658 (7) a coprocessor condition code delay
659 (8) a HI/LO special register delay
661 There are a lot of optimizations we could do that we don't.
662 In particular, we do not, in general, reorder instructions.
663 If you use gcc with optimization, it will reorder
664 instructions and generally do much more optimization then we
665 do here; repeating all that work in the assembler would only
666 benefit hand written assembly code, and does not seem worth
669 /* This is how a NOP is emitted. */
670 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
672 /* The previous insn might require a delay slot, depending upon
673 the contents of the current insn. */
674 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
676 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
678 /* A load from a coprocessor or from memory. All load
679 delays delay the use of general register rt for one
680 instruction on the r3000. The r6000 and r4000 use
682 know (prev_pinfo
& INSN_WRITE_GPR_T
);
683 if (mips_optimize
== 0
684 || insn_uses_reg (ip
,
685 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
690 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
692 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
694 /* A generic coprocessor delay. The previous instruction
695 modified a coprocessor general or control register. If
696 it modified a control register, we need to avoid any
697 coprocessor instruction (this is probably not always
698 required, but it sometimes is). If it modified a general
699 register, we avoid using that register.
701 On the r6000 and r4000 loading a coprocessor register
702 from memory is interlocked, and does not require a delay.
704 This case is not handled very well. There is no special
705 knowledge of CP0 handling, and the coprocessors other
706 than the floating point unit are not distinguished at
708 if (prev_pinfo
& INSN_WRITE_FPR_T
)
710 if (mips_optimize
== 0
711 || insn_uses_reg (ip
,
712 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
717 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
719 if (mips_optimize
== 0
720 || insn_uses_reg (ip
,
721 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
728 /* We don't know exactly what the previous instruction
729 does. If the current instruction uses a coprocessor
730 register, we must insert a NOP. If previous
731 instruction may set the condition codes, and the
732 current instruction uses them, we must insert two
734 if (mips_optimize
== 0
735 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
736 && (pinfo
& INSN_READ_COND_CODE
)))
738 else if (pinfo
& INSN_COP
)
742 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
744 /* The previous instruction sets the coprocessor condition
745 codes, but does not require a general coprocessor delay
746 (this means it is a floating point comparison
747 instruction). If this instruction uses the condition
748 codes, we need to insert a single NOP. */
749 if (mips_optimize
== 0
750 || (pinfo
& INSN_READ_COND_CODE
))
753 else if (prev_pinfo
& INSN_READ_LO
)
755 /* The previous instruction reads the LO register; if the
756 current instruction writes to the LO register, we must
758 if (mips_optimize
== 0
759 || (pinfo
& INSN_WRITE_LO
))
762 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
764 /* The previous instruction reads the HI register; if the
765 current instruction writes to the HI register, we must
767 if (mips_optimize
== 0
768 || (pinfo
& INSN_WRITE_HI
))
772 /* There are two cases which require two intervening
773 instructions: 1) setting the condition codes using a move to
774 coprocessor instruction which requires a general coprocessor
775 delay and then reading the condition codes 2) reading the HI
776 or LO register and then writing to it. If we are not already
777 emitting a NOP instruction, we must check for these cases
778 compared to the instruction previous to the previous
781 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
782 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
783 && (pinfo
& INSN_READ_COND_CODE
))
784 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
785 && (pinfo
& INSN_WRITE_LO
))
786 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
787 && (pinfo
& INSN_WRITE_HI
))))
790 /* If we are being given a nop instruction, don't bother with
791 one of the nops we would otherwise output. This will only
792 happen when a nop instruction is used with mips_optimize set
794 if (nops
> 0 && ip
->insn_opcode
== 0)
797 /* Now emit the right number of NOP instructions. */
803 if (insn_label
!= NULL
)
805 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
806 insn_label
->sy_frag
= frag_now
;
807 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
817 if (address_expr
!= NULL
)
819 if (address_expr
->X_op
== O_constant
)
824 ip
->insn_opcode
|= address_expr
->X_add_number
;
828 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
831 case BFD_RELOC_MIPS_JMP
:
832 case BFD_RELOC_16_PCREL_S2
:
841 assert (reloc_type
!= BFD_RELOC_UNUSED
);
843 /* Don't generate a reloc if we are writing into a variant
846 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
848 reloc_type
== BFD_RELOC_16_PCREL_S2
,
853 md_number_to_chars (f
, ip
->insn_opcode
, 4);
855 /* Update the register mask information. */
856 if (pinfo
& INSN_WRITE_GPR_D
)
857 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
858 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
859 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
860 if (pinfo
& INSN_READ_GPR_S
)
861 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
862 if (pinfo
& INSN_WRITE_GPR_31
)
863 mips_gprmask
|= 1 << 31;
864 if (pinfo
& INSN_WRITE_FPR_D
)
865 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
866 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
867 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
868 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
869 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
870 if (pinfo
& INSN_COP
)
872 /* We don't keep enough information to sort these cases out. */
874 /* Never set the bit for $0, which is always zero. */
875 mips_gprmask
&=~ 1 << 0;
877 if (place
== NULL
&& ! mips_noreorder
)
879 /* Filling the branch delay slot is more complex. We try to
880 switch the branch with the previous instruction, which we can
881 do if the previous instruction does not set up a condition
882 that the branch tests and if the branch is not itself the
883 target of any branch. */
884 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
885 || (pinfo
& INSN_COND_BRANCH_DELAY
))
887 if (mips_optimize
< 2
888 /* If we have seen .set nobopt, don't optimize. */
890 /* If we have seen .set volatile or .set nomove, don't
893 /* If we had to emit any NOP instructions, then we
894 already know we can not swap. */
896 /* If we don't even know the previous insn, we can not
899 /* If the previous insn is already in a branch delay
900 slot, then we can not swap. */
901 || prev_insn_is_delay_slot
902 /* If the previous previous insn was in a .set
903 noreorder, we can't swap. Actually, the MIPS
904 assembler will swap in this situation. However, gcc
905 configured -with-gnu-as will generate code like
911 in which we can not swap the bne and INSN. If gcc is
912 not configured -with-gnu-as, it does not output the
913 .set pseudo-ops. We don't have to check
914 prev_insn_unreordered, because prev_insn_valid will
915 be 0 in that case. We don't want to use
916 prev_prev_insn_valid, because we do want to be able
917 to swap at the start of a function. */
918 || prev_prev_insn_unreordered
919 /* If the branch is itself the target of a branch, we
920 can not swap. We cheat on this; all we check for is
921 whether there is a label on this instruction. If
922 there are any branches to anything other than a
923 label, users must use .set noreorder. */
924 || insn_label
!= NULL
925 /* If the previous instruction is in a variant frag, we
926 can not do the swap. */
927 || prev_insn_frag
->fr_type
== rs_machine_dependent
928 /* If the branch reads the condition codes, we don't
929 even try to swap, because in the sequence
934 we can not swap, and I don't feel like handling that
936 || (pinfo
& INSN_READ_COND_CODE
)
937 /* We can not swap with an instruction that requires a
938 delay slot, becase the target of the branch might
939 interfere with that instruction. */
941 & (INSN_LOAD_COPROC_DELAY
942 | INSN_COPROC_MOVE_DELAY
943 | INSN_WRITE_COND_CODE
948 & (INSN_LOAD_MEMORY_DELAY
949 | INSN_COPROC_MEMORY_DELAY
)))
950 /* We can not swap with a branch instruction. */
952 & (INSN_UNCOND_BRANCH_DELAY
953 | INSN_COND_BRANCH_DELAY
954 | INSN_COND_BRANCH_LIKELY
))
955 /* We do not swap with a trap instruction, since it
956 complicates trap handlers to have the trap
957 instruction be in a delay slot. */
958 || (prev_pinfo
& INSN_TRAP
)
959 /* If the branch reads a register that the previous
960 instruction sets, we can not swap. */
961 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
962 && insn_uses_reg (ip
,
963 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
966 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
967 && insn_uses_reg (ip
,
968 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
971 /* If the branch writes a register that the previous
972 instruction sets, we can not swap (we know that
973 branches write only to RD or to $31). */
974 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
975 && (((pinfo
& INSN_WRITE_GPR_D
)
976 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
977 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
978 || ((pinfo
& INSN_WRITE_GPR_31
)
979 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
982 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
983 && (((pinfo
& INSN_WRITE_GPR_D
)
984 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
985 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
986 || ((pinfo
& INSN_WRITE_GPR_31
)
987 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
990 /* If the branch writes a register that the previous
991 instruction reads, we can not swap (we know that
992 branches only write to RD or to $31). */
993 || ((pinfo
& INSN_WRITE_GPR_D
)
994 && insn_uses_reg (&prev_insn
,
995 ((ip
->insn_opcode
>> OP_SH_RD
)
998 || ((pinfo
& INSN_WRITE_GPR_31
)
999 && insn_uses_reg (&prev_insn
, 31, 0))
1000 /* If the previous previous instruction has a load
1001 delay, and sets a register that the branch reads, we
1003 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1005 && (prev_prev_insn
.insn_mo
->pinfo
1006 & INSN_LOAD_MEMORY_DELAY
)))
1007 && insn_uses_reg (ip
,
1008 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1012 /* We could do even better for unconditional branches to
1013 portions of this object file; we could pick up the
1014 instruction at the destination, put it in the delay
1015 slot, and bump the destination address. */
1017 /* Update the previous insn information. */
1018 prev_prev_insn
= *ip
;
1019 prev_insn
.insn_mo
= &dummy_opcode
;
1026 /* It looks like we can actually do the swap. */
1027 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1028 memcpy (temp
, prev_f
, 4);
1029 memcpy (prev_f
, f
, 4);
1030 memcpy (f
, temp
, 4);
1033 prev_insn_fixp
->fx_frag
= frag_now
;
1034 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1038 fixp
->fx_frag
= prev_insn_frag
;
1039 fixp
->fx_where
= prev_insn_where
;
1041 /* Update the previous insn information; leave prev_insn
1043 prev_prev_insn
= *ip
;
1045 prev_insn_is_delay_slot
= 1;
1047 /* If that was an unconditional branch, forget the previous
1048 insn information. */
1049 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1051 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1052 prev_insn
.insn_mo
= &dummy_opcode
;
1055 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1057 /* We don't yet optimize a branch likely. What we should do
1058 is look at the target, copy the instruction found there
1059 into the delay slot, and increment the branch to jump to
1060 the next instruction. */
1062 /* Update the previous insn information. */
1063 prev_prev_insn
= *ip
;
1064 prev_insn
.insn_mo
= &dummy_opcode
;
1068 /* Update the previous insn information. */
1070 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1072 prev_prev_insn
= prev_insn
;
1075 /* Any time we see a branch, we always fill the delay slot
1076 immediately; since this insn is not a branch, we know it
1077 is not in a delay slot. */
1078 prev_insn_is_delay_slot
= 0;
1081 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1082 prev_insn_unreordered
= 0;
1083 prev_insn_frag
= frag_now
;
1084 prev_insn_where
= f
- frag_now
->fr_literal
;
1085 prev_insn_fixp
= fixp
;
1086 prev_insn_valid
= 1;
1089 /* We just output an insn, so the next one doesn't have a label. */
1093 /* This function forgets that there was any previous instruction or
1097 mips_no_prev_insn ()
1099 prev_insn
.insn_mo
= &dummy_opcode
;
1100 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1101 prev_insn_valid
= 0;
1102 prev_insn_is_delay_slot
= 0;
1103 prev_insn_unreordered
= 0;
1104 prev_prev_insn_unreordered
= 0;
1108 /* This function must be called whenever we turn on noreorder or emit
1109 something other than instructions. It inserts any NOPS which might
1110 be needed by the previous instruction, and clears the information
1111 kept for the previous instructions. */
1116 if (! mips_noreorder
)
1121 if ((prev_insn
.insn_mo
->pinfo
1122 & (INSN_LOAD_COPROC_DELAY
1123 | INSN_COPROC_MOVE_DELAY
1124 | INSN_WRITE_COND_CODE
1128 && (prev_insn
.insn_mo
->pinfo
1129 & (INSN_LOAD_MEMORY_DELAY
1130 | INSN_COPROC_MEMORY_DELAY
))))
1133 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1134 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1135 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1138 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1139 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1140 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1145 if (insn_label
!= NULL
)
1147 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1148 insn_label
->sy_frag
= frag_now
;
1149 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1152 mips_no_prev_insn ();
1156 /* Build an instruction created by a macro expansion. This is passed
1157 a pointer to the count of instructions created so far, an
1158 expression, the name of the instruction to build, an operand format
1159 string, and corresponding arguments. */
1163 macro_build (char *place
,
1169 #else /* ! defined (NO_STDARG) */
1171 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1178 #endif /* ! defined (NO_STDARG) */
1180 struct mips_cl_insn insn
;
1181 bfd_reloc_code_real_type r
;
1185 va_start (args
, fmt
);
1191 * If the macro is about to expand into a second instruction,
1192 * print a warning if needed. We need to pass ip as a parameter
1193 * to generate a better warning message here...
1195 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1196 as_warn ("Macro instruction expanded into multiple instructions");
1199 *counter
+= 1; /* bump instruction counter */
1201 r
= BFD_RELOC_UNUSED
;
1202 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1203 assert (insn
.insn_mo
);
1204 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1206 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1207 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1210 assert (insn
.insn_mo
->name
);
1211 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1213 insn
.insn_opcode
= insn
.insn_mo
->match
;
1229 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1235 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1240 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1245 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1252 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1256 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1260 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1267 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1273 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1274 assert (r
== BFD_RELOC_MIPS_GPREL
1275 || r
== BFD_RELOC_MIPS_LITERAL
1276 || r
== BFD_RELOC_LO16
1277 || r
== BFD_RELOC_MIPS_GOT16
1278 || r
== BFD_RELOC_MIPS_CALL16
);
1282 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1283 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1288 assert (ep
!= NULL
);
1290 * This allows macro() to pass an immediate expression for
1291 * creating short branches without creating a symbol.
1292 * Note that the expression still might come from the assembly
1293 * input, in which case the value is not checked for range nor
1294 * is a relocation entry generated (yuck).
1296 if (ep
->X_op
== O_constant
)
1298 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1302 r
= BFD_RELOC_16_PCREL_S2
;
1306 assert (ep
!= NULL
);
1307 r
= BFD_RELOC_MIPS_JMP
;
1316 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1318 append_insn (place
, &insn
, ep
, r
);
1322 * Generate a "lui" instruction.
1325 macro_build_lui (place
, counter
, ep
, regnum
)
1331 expressionS high_expr
;
1332 struct mips_cl_insn insn
;
1333 bfd_reloc_code_real_type r
;
1334 CONST
char *name
= "lui";
1335 CONST
char *fmt
= "t,u";
1341 high_expr
.X_op
= O_constant
;
1342 high_expr
.X_add_number
= 0;
1345 if (high_expr
.X_op
== O_constant
)
1347 /* we can compute the instruction now without a relocation entry */
1348 if (high_expr
.X_add_number
& 0x8000)
1349 high_expr
.X_add_number
+= 0x10000;
1350 high_expr
.X_add_number
=
1351 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1352 r
= BFD_RELOC_UNUSED
;
1356 assert (ep
->X_op
== O_symbol
);
1357 /* _gp_disp is a special case, used from s_cpload. */
1358 assert (mips_pic
== 0
1359 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1360 r
= BFD_RELOC_HI16_S
;
1364 * If the macro is about to expand into a second instruction,
1365 * print a warning if needed. We need to pass ip as a parameter
1366 * to generate a better warning message here...
1368 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1369 as_warn ("Macro instruction expanded into multiple instructions");
1372 *counter
+= 1; /* bump instruction counter */
1374 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1375 assert (insn
.insn_mo
);
1376 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1377 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1379 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1380 if (r
== BFD_RELOC_UNUSED
)
1382 insn
.insn_opcode
|= high_expr
.X_add_number
;
1383 append_insn (place
, &insn
, NULL
, r
);
1386 append_insn (place
, &insn
, &high_expr
, r
);
1390 * Generates code to set the $at register to true (one)
1391 * if reg is less than the immediate expression.
1394 set_at (counter
, reg
, unsignedp
)
1399 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1400 macro_build ((char *) NULL
, counter
, &imm_expr
,
1401 unsignedp
? "sltiu" : "slti",
1402 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1405 load_register (counter
, AT
, &imm_expr
);
1406 macro_build ((char *) NULL
, counter
, NULL
,
1407 unsignedp
? "sltu" : "slt",
1408 "d,v,t", AT
, reg
, AT
);
1412 /* Warn if an expression is not a constant. */
1415 check_absolute_expr (ip
, ex
)
1416 struct mips_cl_insn
*ip
;
1419 if (ex
->X_op
!= O_constant
)
1420 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1424 * This routine generates the least number of instructions neccessary to load
1425 * an absolute expression value into a register.
1428 load_register (counter
, reg
, ep
)
1433 assert (ep
->X_op
== O_constant
);
1434 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1435 macro_build ((char *) NULL
, counter
, ep
,
1436 mips_isa
< 3 ? "addiu" : "daddiu",
1437 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1438 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1439 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1440 (int) BFD_RELOC_LO16
);
1441 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1442 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1443 == ~ (offsetT
) 0x7fffffff))
1445 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
);
1446 if ((ep
->X_add_number
& 0xffff) != 0)
1447 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1448 (int) BFD_RELOC_LO16
);
1450 else if (mips_isa
< 3)
1452 as_bad ("Number larger than 32 bits");
1453 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1454 (int) BFD_RELOC_LO16
);
1459 expressionS hi32
, lo32
;
1463 hi32
.X_add_number
>>= shift
;
1464 hi32
.X_add_number
&= 0xffffffff;
1465 if ((hi32
.X_add_number
& 0x80000000) != 0)
1466 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1467 load_register (counter
, reg
, &hi32
);
1469 lo32
.X_add_number
&= 0xffffffff;
1470 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1471 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1477 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1480 mid16
.X_add_number
>>= 16;
1481 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1482 reg
, (int) BFD_RELOC_LO16
);
1483 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1486 if ((lo32
.X_add_number
& 0xffff) != 0)
1487 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1488 (int) BFD_RELOC_LO16
);
1492 /* Load an address into a register. */
1495 load_address (counter
, reg
, ep
)
1502 if (ep
->X_op
!= O_constant
1503 && ep
->X_op
!= O_symbol
)
1505 as_bad ("expression too complex");
1506 ep
->X_op
= O_constant
;
1509 if (ep
->X_op
== O_constant
)
1510 load_register (counter
, reg
, ep
);
1511 else if (mips_pic
== 0)
1513 /* If this is a reference to a GP relative symbol, we want
1514 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1516 lui $reg,$gp,<sym> (BFD_RELOC_HI16_S)
1517 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1518 If we have an addend, we always use the latter form. */
1519 if (ep
->X_add_number
!= 0)
1524 macro_build ((char *) NULL
, counter
, ep
,
1525 mips_isa
< 3 ? "addiu" : "daddiu",
1526 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1527 p
= frag_var (rs_machine_dependent
, 8, 0,
1528 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1529 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1531 macro_build_lui (p
, counter
, ep
, reg
);
1534 macro_build (p
, counter
, ep
,
1535 mips_isa
< 3 ? "addiu" : "daddiu",
1536 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1542 /* If this is a reference to an external symbol, we want
1543 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1545 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1547 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1548 If there is a constant, it must be added in afterward. */
1549 ex
.X_add_number
= ep
->X_add_number
;
1550 ep
->X_add_number
= 0;
1552 macro_build ((char *) NULL
, counter
, ep
,
1553 mips_isa
< 3 ? "lw" : "ld",
1554 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1555 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1556 p
= frag_var (rs_machine_dependent
, 4, 0,
1557 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1558 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1559 macro_build (p
, counter
, ep
,
1560 mips_isa
< 3 ? "addiu" : "daddiu",
1561 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1562 if (ex
.X_add_number
!= 0)
1564 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1565 as_bad ("PIC code offset overflow (max 16 signed bits)");
1566 ex
.X_op
= O_constant
;
1567 macro_build (p
, counter
, &ex
,
1568 mips_isa
< 3 ? "addiu" : "daddiu",
1569 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1576 * This routine implements the seemingly endless macro or synthesized
1577 * instructions and addressing modes in the mips assembly language. Many
1578 * of these macros are simple and are similar to each other. These could
1579 * probably be handled by some kind of table or grammer aproach instead of
1580 * this verbose method. Others are not simple macros but are more like
1581 * optimizing code generation.
1582 * One interesting optimization is when several store macros appear
1583 * consecutivly that would load AT with the upper half of the same address.
1584 * The ensuing load upper instructions are ommited. This implies some kind
1585 * of global optimization. We currently only optimize within a single macro.
1586 * For many of the load and store macros if the address is specified as a
1587 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1588 * first load register 'at' with zero and use it as the base register. The
1589 * mips assembler simply uses register $zero. Just one tiny optimization
1594 struct mips_cl_insn
*ip
;
1596 register int treg
, sreg
, dreg
, breg
;
1609 bfd_reloc_code_real_type r
;
1612 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1613 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1614 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1615 mask
= ip
->insn_mo
->mask
;
1617 expr1
.X_op
= O_constant
;
1618 expr1
.X_op_symbol
= NULL
;
1619 expr1
.X_add_symbol
= NULL
;
1620 expr1
.X_add_number
= 1;
1632 mips_emit_delays ();
1634 mips_any_noreorder
= 1;
1636 expr1
.X_add_number
= 8;
1637 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1639 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1641 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1642 macro_build ((char *) NULL
, &icnt
, NULL
,
1643 dbl
? "dsub" : "sub",
1644 "d,v,t", dreg
, 0, sreg
);
1667 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1669 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1670 (int) BFD_RELOC_LO16
);
1673 load_register (&icnt
, AT
, &imm_expr
);
1674 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1693 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1695 if (mask
!= M_NOR_I
)
1696 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1697 sreg
, (int) BFD_RELOC_LO16
);
1700 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1701 treg
, sreg
, (int) BFD_RELOC_LO16
);
1702 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "nor", "d,v,t",
1708 load_register (&icnt
, AT
, &imm_expr
);
1709 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1726 if (imm_expr
.X_add_number
== 0)
1728 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1732 load_register (&icnt
, AT
, &imm_expr
);
1733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1741 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1742 likely
? "bgezl" : "bgez",
1748 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1749 likely
? "blezl" : "blez",
1753 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1754 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1755 likely
? "beql" : "beq",
1762 /* check for > max integer */
1763 maxnum
= 0x7fffffff;
1771 if (imm_expr
.X_add_number
>= maxnum
)
1774 /* result is always false */
1777 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1778 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1782 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1783 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1788 imm_expr
.X_add_number
++;
1792 if (mask
== M_BGEL_I
)
1794 if (imm_expr
.X_add_number
== 0)
1796 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1797 likely
? "bgezl" : "bgez",
1801 if (imm_expr
.X_add_number
== 1)
1803 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1804 likely
? "bgtzl" : "bgtz",
1808 maxnum
= 0x7fffffff;
1816 maxnum
= - maxnum
- 1;
1817 if (imm_expr
.X_add_number
<= maxnum
)
1820 /* result is always true */
1821 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1822 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1825 set_at (&icnt
, sreg
, 0);
1826 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1827 likely
? "beql" : "beq",
1838 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1839 likely
? "beql" : "beq",
1843 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1846 likely
? "beql" : "beq",
1853 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1855 imm_expr
.X_add_number
++;
1859 if (mask
== M_BGEUL_I
)
1861 if (imm_expr
.X_add_number
== 0)
1863 if (imm_expr
.X_add_number
== 1)
1865 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1866 likely
? "bnel" : "bne",
1870 set_at (&icnt
, sreg
, 1);
1871 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1872 likely
? "beql" : "beq",
1881 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1882 likely
? "bgtzl" : "bgtz",
1888 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1889 likely
? "bltzl" : "bltz",
1893 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1894 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1895 likely
? "bnel" : "bne",
1904 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1905 likely
? "bnel" : "bne",
1911 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1913 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1914 likely
? "bnel" : "bne",
1923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1924 likely
? "blezl" : "blez",
1930 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1931 likely
? "bgezl" : "bgez",
1935 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1936 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1937 likely
? "beql" : "beq",
1944 maxnum
= 0x7fffffff;
1952 if (imm_expr
.X_add_number
>= maxnum
)
1954 imm_expr
.X_add_number
++;
1958 if (mask
== M_BLTL_I
)
1960 if (imm_expr
.X_add_number
== 0)
1962 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1963 likely
? "bltzl" : "bltz",
1967 if (imm_expr
.X_add_number
== 1)
1969 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1970 likely
? "blezl" : "blez",
1974 set_at (&icnt
, sreg
, 0);
1975 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1976 likely
? "bnel" : "bne",
1985 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1986 likely
? "beql" : "beq",
1992 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1994 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1995 likely
? "beql" : "beq",
2002 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2004 imm_expr
.X_add_number
++;
2008 if (mask
== M_BLTUL_I
)
2010 if (imm_expr
.X_add_number
== 0)
2012 if (imm_expr
.X_add_number
== 1)
2014 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2015 likely
? "beql" : "beq",
2019 set_at (&icnt
, sreg
, 1);
2020 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2021 likely
? "bnel" : "bne",
2030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2031 likely
? "bltzl" : "bltz",
2037 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2038 likely
? "bgtzl" : "bgtz",
2042 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2043 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2044 likely
? "bnel" : "bne",
2055 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2056 likely
? "bnel" : "bne",
2060 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2062 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2063 likely
? "bnel" : "bne",
2079 as_warn ("Divide by zero.");
2080 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2084 mips_emit_delays ();
2086 mips_any_noreorder
= 1;
2087 macro_build ((char *) NULL
, &icnt
, NULL
,
2088 dbl
? "ddiv" : "div",
2089 "z,s,t", sreg
, treg
);
2090 expr1
.X_add_number
= 8;
2091 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2092 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2093 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2094 expr1
.X_add_number
= -1;
2095 macro_build ((char *) NULL
, &icnt
, &expr1
,
2096 dbl
? "daddiu" : "addiu",
2097 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2098 expr1
.X_add_number
= dbl
? 20 : 16;
2099 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2102 expr1
.X_add_number
= 1;
2103 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2104 (int) BFD_RELOC_LO16
);
2105 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2110 expr1
.X_add_number
= 0x80000000;
2111 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
);
2113 expr1
.X_add_number
= 8;
2114 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2115 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2116 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2118 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2157 if (imm_expr
.X_add_number
== 0)
2159 as_warn ("Divide by zero.");
2160 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2163 if (imm_expr
.X_add_number
== 1)
2165 if (strcmp (s2
, "mflo") == 0)
2166 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2169 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2172 if (imm_expr
.X_add_number
== -1
2173 && s
[strlen (s
) - 1] != 'u')
2175 if (strcmp (s2
, "mflo") == 0)
2178 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2181 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2185 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2189 load_register (&icnt
, AT
, &imm_expr
);
2190 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2191 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2210 mips_emit_delays ();
2212 mips_any_noreorder
= 1;
2213 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2214 expr1
.X_add_number
= 8;
2215 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2216 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2217 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2219 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2223 /* Load the address of a symbol into a register. If M_LA_AB, we
2224 then add a base register to it. */
2225 if (offset_expr
.X_op
!= O_symbol
2226 && offset_expr
.X_op
!= O_constant
)
2228 as_bad ("expression too complex");
2229 offset_expr
.X_op
= O_constant
;
2243 if (offset_expr
.X_op
== O_constant
)
2244 load_register (&icnt
, tempreg
, &offset_expr
);
2245 else if (mips_pic
== 0)
2247 /* If this is a reference to an GP relative symbol, we want
2248 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2250 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2251 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2252 If we have a constant, we need two instructions anyhow,
2253 so we may as well always use the latter form. */
2254 if (offset_expr
.X_add_number
!= 0)
2259 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2260 mips_isa
< 3 ? "addiu" : "daddiu",
2261 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2262 p
= frag_var (rs_machine_dependent
, 8, 0,
2263 RELAX_ENCODE (4, 8, 0, 4, 0,
2264 mips_warn_about_macros
),
2265 offset_expr
.X_add_symbol
, (long) 0,
2268 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2271 macro_build (p
, &icnt
, &offset_expr
,
2272 mips_isa
< 3 ? "addiu" : "daddiu",
2273 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2277 /* If this is a reference to an external symbol, and there
2278 is no constant, we want
2279 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2280 For a local symbol, we want
2281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2283 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2285 If we have a small constant, and this is a reference to
2286 an external symbol, we want
2287 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2289 addiu $tempreg,$tempreg,<constant>
2290 For a local symbol, we want the same instruction
2291 sequence, but we output a BFD_RELOC_LO16 reloc on the
2294 If we have a large constant, and this is a reference to
2295 an external symbol, we want
2296 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2297 lui $at,<hiconstant>
2298 addiu $at,$at,<loconstant>
2299 addu $tempreg,$tempreg,$at
2300 For a local symbol, we want the same instruction
2301 sequence, but we output a BFD_RELOC_LO16 reloc on the
2302 addiu instruction. */
2303 expr1
.X_add_number
= offset_expr
.X_add_number
;
2304 offset_expr
.X_add_number
= 0;
2306 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2307 mips_isa
< 3 ? "lw" : "ld",
2308 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2309 if (expr1
.X_add_number
== 0)
2317 /* We're going to put in an addu instruction using
2318 tempreg, so we may as well insert the nop right
2320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2324 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2325 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2327 ? mips_warn_about_macros
2329 offset_expr
.X_add_symbol
, (long) 0,
2333 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2336 macro_build (p
, &icnt
, &expr1
,
2337 mips_isa
< 3 ? "addiu" : "daddiu",
2338 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2339 /* FIXME: If breg == 0, and the next instruction uses
2340 $tempreg, then if this variant case is used an extra
2341 nop will be generated. */
2343 else if (expr1
.X_add_number
>= -0x8000
2344 && expr1
.X_add_number
< 0x8000)
2346 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2348 macro_build ((char *) NULL
, &icnt
, &expr1
,
2349 mips_isa
< 3 ? "addiu" : "daddiu",
2350 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2351 (void) frag_var (rs_machine_dependent
, 0, 0,
2352 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2353 offset_expr
.X_add_symbol
, (long) 0,
2360 /* If we are going to add in a base register, and the
2361 target register and the base register are the same,
2362 then we are using AT as a temporary register. Since
2363 we want to load the constant into AT, we add our
2364 current AT (from the global offset table) and the
2365 register into the register now, and pretend we were
2366 not using a base register. */
2371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2374 mips_isa
< 3 ? "addu" : "daddu",
2375 "d,v,t", treg
, AT
, breg
);
2381 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2382 macro_build ((char *) NULL
, &icnt
, &expr1
,
2383 mips_isa
< 3 ? "addiu" : "daddiu",
2384 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2386 mips_isa
< 3 ? "addu" : "daddu",
2387 "d,v,t", tempreg
, tempreg
, AT
);
2388 (void) frag_var (rs_machine_dependent
, 0, 0,
2389 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2390 offset_expr
.X_add_symbol
, (long) 0,
2397 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2398 mips_isa
< 3 ? "addu" : "daddu",
2399 "d,v,t", treg
, tempreg
, breg
);
2407 /* The j instruction may not be used in PIC code, since it
2408 requires an absolute address. We convert it to a b
2411 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2413 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2416 /* The jal instructions must be handled as macros because when
2417 generating PIC code they expand to multi-instruction
2418 sequences. Normally they are simple instructions. */
2425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2430 /* I only know how to handle pic2. */
2431 assert (mips_pic
== 2);
2433 if (sreg
!= PIC_CALL_REG
)
2434 as_warn ("MIPS PIC call to register other than $25");
2436 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
2438 if (mips_cprestore_offset
< 0)
2439 as_warn ("No .cprestore pseudo-op used in PIC code");
2442 expr1
.X_add_number
= mips_cprestore_offset
;
2443 macro_build ((char *) NULL
, &icnt
, &expr1
,
2444 mips_isa
< 3 ? "lw" : "ld",
2445 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2452 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2456 /* I only know how to handle pic2. */
2457 assert (mips_pic
== 2);
2459 /* If this is a reference to an external symbol, we want
2460 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2464 lw $gp,cprestore($sp)
2465 The cprestore value is set using the .cprestore pseudo-op.
2466 If the symbol is not external, we want
2467 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2469 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2472 lw $gp,cprestore($sp)
2475 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2476 mips_isa
< 3 ? "lw" : "ld",
2477 "t,o(b)", PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL16
, GP
);
2478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2479 p
= frag_var (rs_machine_dependent
, 4, 0,
2480 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2481 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2482 macro_build (p
, &icnt
, &offset_expr
,
2483 mips_isa
< 3 ? "addiu" : "daddiu",
2484 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2485 (int) BFD_RELOC_LO16
);
2486 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "s",
2488 if (mips_cprestore_offset
< 0)
2489 as_warn ("No .cprestore pseudo-op used in PIC code");
2493 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2495 expr1
.X_add_number
= mips_cprestore_offset
;
2496 macro_build ((char *) NULL
, &icnt
, &expr1
,
2497 mips_isa
< 3 ? "lw" : "ld",
2498 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2566 if (breg
== treg
|| coproc
)
2635 if (mask
== M_LWC1_AB
2636 || mask
== M_SWC1_AB
2637 || mask
== M_LDC1_AB
2638 || mask
== M_SDC1_AB
2647 if (offset_expr
.X_op
!= O_constant
2648 && offset_expr
.X_op
!= O_symbol
)
2650 as_bad ("expression too complex");
2651 offset_expr
.X_op
= O_constant
;
2654 /* A constant expression in PIC code can be handled just as it
2655 is in non PIC code. */
2657 || offset_expr
.X_op
== O_constant
)
2659 /* If this is a reference to a GP relative symbol, and there
2660 is no base register, we want
2661 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2663 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2664 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2665 If we have a constant, we need two instructions anyhow,
2666 so we always use the latter form.
2668 If we have a base register, and this is a reference to a
2669 GP relative symbol, we want
2670 addu $tempreg,$breg,$gp
2671 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2673 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2674 addu $tempreg,$tempreg,$breg
2675 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2676 With a constant we always use the latter case. */
2679 if (offset_expr
.X_add_number
!= 0)
2684 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2685 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2686 p
= frag_var (rs_machine_dependent
, 8, 0,
2687 RELAX_ENCODE (4, 8, 0, 4, 0,
2688 mips_warn_about_macros
),
2689 offset_expr
.X_add_symbol
, (long) 0,
2692 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2695 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2696 (int) BFD_RELOC_LO16
, tempreg
);
2700 if (offset_expr
.X_add_number
!= 0)
2705 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2706 mips_isa
< 3 ? "addu" : "daddu",
2707 "d,v,t", tempreg
, breg
, GP
);
2708 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2709 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2710 p
= frag_var (rs_machine_dependent
, 12, 0,
2711 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2712 offset_expr
.X_add_symbol
, (long) 0,
2715 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2718 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2719 mips_isa
< 3 ? "addu" : "daddu",
2720 "d,v,t", tempreg
, tempreg
, breg
);
2723 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2724 (int) BFD_RELOC_LO16
, tempreg
);
2729 /* If this is a reference to an external symbol, we want
2730 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2732 <op> $treg,0($tempreg)
2734 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2736 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2737 <op> $treg,0($tempreg)
2738 If there is a base register, we add it to $tempreg before
2739 the <op>. If there is a constant, we stick it in the
2740 <op> instruction. We don't handle constants larger than
2741 16 bits, because we have no way to load the upper 16 bits
2742 (actually, we could handle them for the subset of cases
2743 in which we are not using $at). */
2744 assert (offset_expr
.X_op
== O_symbol
);
2745 expr1
.X_add_number
= offset_expr
.X_add_number
;
2746 offset_expr
.X_add_number
= 0;
2747 if (expr1
.X_add_number
< -0x8000
2748 || expr1
.X_add_number
>= 0x8000)
2749 as_bad ("PIC code offset overflow (max 16 signed bits)");
2751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2752 mips_isa
< 3 ? "lw" : "ld",
2753 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2754 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2755 p
= frag_var (rs_machine_dependent
, 4, 0,
2756 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2757 offset_expr
.X_add_symbol
, (long) 0,
2759 macro_build (p
, &icnt
, &offset_expr
,
2760 mips_isa
< 3 ? "addiu" : "daddiu",
2761 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2764 mips_isa
< 3 ? "addu" : "daddu",
2765 "d,v,t", tempreg
, tempreg
, breg
);
2766 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2767 (int) BFD_RELOC_LO16
, tempreg
);
2777 load_register (&icnt
, treg
, &imm_expr
);
2783 assert (offset_expr
.X_op
== O_symbol
2784 && strcmp (segment_name (S_GET_SEGMENT
2785 (offset_expr
.X_add_symbol
)),
2787 && offset_expr
.X_add_number
== 0);
2788 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2789 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2793 assert (imm_expr
.X_op
== O_constant
);
2794 load_register (&icnt
, treg
, &imm_expr
);
2799 /* We know that sym is in the .rdata instruction. First we get
2800 the upper 16 bits of the address. */
2803 /* FIXME: This won't work for a 64 bit address. */
2804 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
2808 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2809 mips_isa
< 3 ? "lw" : "ld",
2810 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2812 /* Now we load the register(s). */
2814 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
2815 treg
, (int) BFD_RELOC_LO16
, AT
);
2818 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2819 treg
, (int) BFD_RELOC_LO16
, AT
);
2822 /* FIXME: How in the world do we deal with the possible
2824 offset_expr
.X_add_number
+= 4;
2825 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2826 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
2835 /* Load a floating point number from the .lit8 section. */
2836 assert (offset_expr
.X_op
== O_symbol
2837 && strcmp (segment_name (S_GET_SEGMENT
2838 (offset_expr
.X_add_symbol
)),
2840 && offset_expr
.X_add_number
== 0);
2843 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2844 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2848 r
= BFD_RELOC_MIPS_LITERAL
;
2853 /* Load the double from the .rdata section. */
2854 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2855 mips_isa
< 3 ? "lw" : "ld",
2856 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2859 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2860 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
2869 /* Even on a big endian machine $fn comes before $fn+1. We have
2870 to adjust when loading from memory. */
2873 assert (mips_isa
< 2);
2874 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2875 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2877 /* FIXME: A possible overflow which I don't know how to deal
2879 offset_expr
.X_add_number
+= 4;
2880 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2881 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2889 * The MIPS assembler seems to check for X_add_number not
2890 * being double aligned and generating:
2893 * addiu at,at,%lo(foo+1)
2896 * But, the resulting address is the same after relocation so why
2897 * generate the extra instruction?
2944 if (offset_expr
.X_op
!= O_symbol
2945 && offset_expr
.X_op
!= O_constant
)
2947 as_bad ("expression too complex");
2948 offset_expr
.X_op
= O_constant
;
2951 /* Even on a big endian machine $fn comes before $fn+1. We have
2952 to adjust when loading from memory. We set coproc if we must
2953 load $fn+1 first. */
2954 if (byte_order
== LITTLE_ENDIAN
)
2958 || offset_expr
.X_op
== O_constant
)
2960 /* If this is a reference to a GP relative symbol, we want
2961 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2962 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
2963 If we have a base register, we use this
2965 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
2966 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
2967 If this is not a GP relative symbol, we want
2968 lui $at,<sym> (BFD_RELOC_HI16_S)
2969 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
2970 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
2971 If there is a base register, we add it to $at after the
2972 lui instruction. If there is a constant, we always use
2974 if (offset_expr
.X_add_number
!= 0)
2993 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2994 mips_isa
< 3 ? "addu" : "daddu",
2995 "d,v,t", AT
, breg
, GP
);
3001 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3002 coproc
? treg
+ 1 : treg
,
3003 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3004 offset_expr
.X_add_number
+= 4;
3005 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3006 coproc
? treg
: treg
+ 1,
3007 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3008 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3009 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3010 ! used_at
&& mips_noat
),
3011 offset_expr
.X_add_symbol
, (long) 0,
3014 /* We just generated two relocs. When tc_gen_reloc
3015 handles this case, it will skip the first reloc and
3016 handle the second. The second reloc already has an
3017 extra addend of 4, which we added above. We must
3018 subtract it out, and then subtract another 4 to make
3019 the first reloc come out right. The second reloc
3020 will come out right because we are going to add 4 to
3021 offset_expr when we build its instruction below. */
3022 offset_expr
.X_add_number
-= 8;
3023 offset_expr
.X_op
= O_constant
;
3025 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3030 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3031 mips_isa
< 3 ? "addu" : "daddu",
3032 "d,v,t", AT
, breg
, AT
);
3036 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3037 coproc
? treg
+ 1 : treg
,
3038 (int) BFD_RELOC_LO16
, AT
);
3041 /* FIXME: How do we handle overflow here? */
3042 offset_expr
.X_add_number
+= 4;
3043 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3044 coproc
? treg
: treg
+ 1,
3045 (int) BFD_RELOC_LO16
, AT
);
3051 /* If this is a reference to an external symbol, we want
3052 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3057 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3059 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3060 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3061 If there is a base register we add it to $at before the
3062 lwc1 instructions. If there is a constant we include it
3063 in the lwc1 instructions. */
3065 expr1
.X_add_number
= offset_expr
.X_add_number
;
3066 offset_expr
.X_add_number
= 0;
3067 if (expr1
.X_add_number
< -0x8000
3068 || expr1
.X_add_number
>= 0x8000 - 4)
3069 as_bad ("PIC code offset overflow (max 16 signed bits)");
3074 frag_grow (16 + off
);
3075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3076 mips_isa
< 3 ? "lw" : "ld",
3077 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3081 mips_isa
< 3 ? "addu" : "daddu",
3082 "d,v,t", AT
, breg
, AT
);
3083 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3084 coproc
? treg
+ 1 : treg
,
3085 (int) BFD_RELOC_LO16
, AT
);
3086 expr1
.X_add_number
+= 4;
3087 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3088 coproc
? treg
: treg
+ 1,
3089 (int) BFD_RELOC_LO16
, AT
);
3090 (void) frag_var (rs_machine_dependent
, 0, 0,
3091 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3092 offset_expr
.X_add_symbol
, (long) 0,
3107 assert (mips_isa
< 3);
3108 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3109 (int) BFD_RELOC_LO16
, breg
);
3110 offset_expr
.X_add_number
+= 4;
3111 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3112 (int) BFD_RELOC_LO16
, breg
);
3118 macro_build ((char *) NULL
, &icnt
, NULL
,
3119 dbl
? "dmultu" : "multu",
3121 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3127 /* The MIPS assembler some times generates shifts and adds. I'm
3128 not trying to be that fancy. GCC should do this for us
3130 load_register (&icnt
, AT
, &imm_expr
);
3131 macro_build ((char *) NULL
, &icnt
, NULL
,
3132 dbl
? "dmult" : "mult",
3134 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3140 mips_emit_delays ();
3142 mips_any_noreorder
= 1;
3143 macro_build ((char *) NULL
, &icnt
, NULL
,
3144 dbl
? "dmult" : "mult",
3146 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3147 macro_build ((char *) NULL
, &icnt
, NULL
,
3148 dbl
? "dsra32" : "sra",
3149 "d,w,<", dreg
, dreg
, 31);
3150 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3151 expr1
.X_add_number
= 8;
3152 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3153 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3154 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3156 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3162 mips_emit_delays ();
3164 mips_any_noreorder
= 1;
3165 macro_build ((char *) NULL
, &icnt
, NULL
,
3166 dbl
? "dmultu" : "multu",
3168 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3169 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3170 expr1
.X_add_number
= 8;
3171 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3172 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3173 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3178 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3179 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3180 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3182 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3186 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3187 imm_expr
.X_add_number
& 0x1f);
3188 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3189 (0 - imm_expr
.X_add_number
) & 0x1f);
3190 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3194 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3195 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3196 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3198 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3202 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3203 imm_expr
.X_add_number
& 0x1f);
3204 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3205 (0 - imm_expr
.X_add_number
) & 0x1f);
3206 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3210 assert (mips_isa
< 2);
3211 /* Even on a big endian machine $fn comes before $fn+1. We have
3212 to adjust when storing to memory. */
3213 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3214 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3215 (int) BFD_RELOC_LO16
, breg
);
3216 offset_expr
.X_add_number
+= 4;
3217 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3218 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3219 (int) BFD_RELOC_LO16
, breg
);
3224 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3225 treg
, (int) BFD_RELOC_LO16
);
3227 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3228 sreg
, (int) BFD_RELOC_LO16
);
3231 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3233 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3234 dreg
, (int) BFD_RELOC_LO16
);
3239 if (imm_expr
.X_add_number
== 0)
3241 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3242 sreg
, (int) BFD_RELOC_LO16
);
3247 as_warn ("Instruction %s: result is always false",
3249 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3252 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3254 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3255 sreg
, (int) BFD_RELOC_LO16
);
3258 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3260 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3261 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3262 mips_isa
< 3 ? "addiu" : "daddiu",
3263 "t,r,j", dreg
, sreg
,
3264 (int) BFD_RELOC_LO16
);
3269 load_register (&icnt
, AT
, &imm_expr
);
3270 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3274 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3275 (int) BFD_RELOC_LO16
);
3280 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3286 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3287 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3288 (int) BFD_RELOC_LO16
);
3291 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3293 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3295 macro_build ((char *) NULL
, &icnt
, &expr1
,
3296 mask
== M_SGE_I
? "slti" : "sltiu",
3297 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3302 load_register (&icnt
, AT
, &imm_expr
);
3303 macro_build ((char *) NULL
, &icnt
, NULL
,
3304 mask
== M_SGE_I
? "slt" : "sltu",
3305 "d,v,t", dreg
, sreg
, AT
);
3308 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3309 (int) BFD_RELOC_LO16
);
3314 case M_SGT
: /* sreg > treg <==> treg < sreg */
3320 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3323 case M_SGT_I
: /* sreg > I <==> I < sreg */
3329 load_register (&icnt
, AT
, &imm_expr
);
3330 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3333 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3339 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3340 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3341 (int) BFD_RELOC_LO16
);
3344 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3350 load_register (&icnt
, AT
, &imm_expr
);
3351 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3352 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3353 (int) BFD_RELOC_LO16
);
3357 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3359 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3360 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3363 load_register (&icnt
, AT
, &imm_expr
);
3364 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3368 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3370 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3371 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3374 load_register (&icnt
, AT
, &imm_expr
);
3375 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3381 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3384 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3388 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3390 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3396 if (imm_expr
.X_add_number
== 0)
3398 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3404 as_warn ("Instruction %s: result is always true",
3406 macro_build ((char *) NULL
, &icnt
, &expr1
,
3407 mips_isa
< 3 ? "addiu" : "daddiu",
3408 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3411 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3413 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3414 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3417 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3419 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3420 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3421 mips_isa
< 3 ? "addiu" : "daddiu",
3422 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3427 load_register (&icnt
, AT
, &imm_expr
);
3428 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3432 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3440 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3442 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3443 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3444 dbl
? "daddi" : "addi",
3445 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3448 load_register (&icnt
, AT
, &imm_expr
);
3449 macro_build ((char *) NULL
, &icnt
, NULL
,
3450 dbl
? "dsub" : "sub",
3451 "d,v,t", dreg
, sreg
, AT
);
3457 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3459 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3460 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3461 dbl
? "daddiu" : "addiu",
3462 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3465 load_register (&icnt
, AT
, &imm_expr
);
3466 macro_build ((char *) NULL
, &icnt
, NULL
,
3467 dbl
? "dsubu" : "subu",
3468 "d,v,t", dreg
, sreg
, AT
);
3489 load_register (&icnt
, AT
, &imm_expr
);
3490 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3495 assert (mips_isa
< 2);
3496 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3497 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3500 * Is the double cfc1 instruction a bug in the mips assembler;
3501 * or is there a reason for it?
3503 mips_emit_delays ();
3505 mips_any_noreorder
= 1;
3506 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3507 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3508 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3509 expr1
.X_add_number
= 3;
3510 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3511 (int) BFD_RELOC_LO16
);
3512 expr1
.X_add_number
= 2;
3513 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3514 (int) BFD_RELOC_LO16
);
3515 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3516 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3517 macro_build ((char *) NULL
, &icnt
, NULL
,
3518 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3519 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3520 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3530 /* avoid load delay */
3531 offset_expr
.X_add_number
+= 1;
3532 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3533 (int) BFD_RELOC_LO16
, breg
);
3534 offset_expr
.X_add_number
-= 1;
3535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3536 (int) BFD_RELOC_LO16
, breg
);
3537 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3538 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3542 /* does this work on a big endian machine? */
3543 offset_expr
.X_add_number
+= 3;
3544 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3545 (int) BFD_RELOC_LO16
, breg
);
3546 offset_expr
.X_add_number
-= 3;
3547 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3548 (int) BFD_RELOC_LO16
, breg
);
3554 load_address (&icnt
, AT
, &offset_expr
);
3555 if (mask
== M_ULW_A
)
3557 expr1
.X_add_number
= 3;
3558 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3559 (int) BFD_RELOC_LO16
, AT
);
3560 expr1
.X_add_number
= 0;
3561 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3562 (int) BFD_RELOC_LO16
, AT
);
3566 macro_build ((char *) NULL
, &icnt
, &expr1
,
3567 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3568 (int) BFD_RELOC_LO16
, AT
);
3569 expr1
.X_add_number
= 0;
3570 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3571 (int) BFD_RELOC_LO16
, AT
);
3572 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3574 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3580 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3581 (int) BFD_RELOC_LO16
, breg
);
3582 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3583 offset_expr
.X_add_number
+= 1;
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3585 (int) BFD_RELOC_LO16
, breg
);
3589 offset_expr
.X_add_number
+= 3;
3590 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3591 (int) BFD_RELOC_LO16
, breg
);
3592 offset_expr
.X_add_number
-= 3;
3593 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3594 (int) BFD_RELOC_LO16
, breg
);
3599 load_address (&icnt
, AT
, &offset_expr
);
3600 if (mask
== M_USW_A
)
3602 expr1
.X_add_number
= 3;
3603 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3604 (int) BFD_RELOC_LO16
, AT
);
3605 expr1
.X_add_number
= 0;
3606 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3607 (int) BFD_RELOC_LO16
, AT
);
3611 expr1
.X_add_number
= 0;
3612 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3613 (int) BFD_RELOC_LO16
, AT
);
3614 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3616 expr1
.X_add_number
= 1;
3617 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3618 (int) BFD_RELOC_LO16
, AT
);
3619 expr1
.X_add_number
= 0;
3620 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3621 (int) BFD_RELOC_LO16
, AT
);
3622 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3624 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3630 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3634 as_warn ("Macro used $at after \".set noat\"");
3639 This routine assembles an instruction into its binary format. As a side
3640 effect it sets one of the global variables imm_reloc or offset_reloc to the
3641 type of relocation to do if one of the operands is an address expression.
3646 struct mips_cl_insn
*ip
;
3651 struct mips_opcode
*insn
;
3654 unsigned int lastregno
= 0;
3659 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
3671 as_warn ("Unknown opcode: `%s'", str
);
3674 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
3676 as_warn ("`%s' not in hash table.", str
);
3677 insn_error
= "ERROR: Unrecognized opcode";
3685 assert (strcmp (insn
->name
, str
) == 0);
3687 if (insn
->pinfo
== INSN_MACRO
)
3688 insn_isa
= insn
->match
;
3689 else if (insn
->pinfo
& INSN_ISA2
)
3691 else if (insn
->pinfo
& INSN_ISA3
)
3696 if (insn_isa
> mips_isa
)
3698 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
3699 && strcmp (insn
->name
, insn
[1].name
) == 0)
3704 insn_error
= "ERROR: instruction not supported on this processor";
3709 ip
->insn_opcode
= insn
->match
;
3710 for (args
= insn
->args
;; ++args
)
3716 case '\0': /* end of args */
3729 ip
->insn_opcode
|= lastregno
<< 21;
3734 ip
->insn_opcode
|= lastregno
<< 16;
3738 ip
->insn_opcode
|= lastregno
<< 11;
3744 /* handle optional base register.
3745 Either the base register is omitted or
3746 we must have a left paren. */
3747 /* this is dependent on the next operand specifier
3748 is a 'b' for base register */
3749 assert (args
[1] == 'b');
3753 case ')': /* these must match exactly */
3758 case '<': /* must be at least one digit */
3760 * According to the manual, if the shift amount is greater
3761 * than 31 or less than 0 the the shift amount should be
3762 * mod 32. In reality the mips assembler issues an error.
3763 * We issue a warning and mask out all but the low 5 bits.
3765 my_getExpression (&imm_expr
, s
);
3766 check_absolute_expr (ip
, &imm_expr
);
3767 if ((unsigned long) imm_expr
.X_add_number
> 31)
3769 as_warn ("Improper shift amount (%ld)",
3770 (long) imm_expr
.X_add_number
);
3771 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
3773 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3774 imm_expr
.X_op
= O_absent
;
3778 case '>': /* shift amount minus 32 */
3779 my_getExpression (&imm_expr
, s
);
3780 check_absolute_expr (ip
, &imm_expr
);
3781 if ((unsigned long) imm_expr
.X_add_number
< 32
3782 || (unsigned long) imm_expr
.X_add_number
> 63)
3784 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
3785 imm_expr
.X_op
= O_absent
;
3789 case 'k': /* cache code */
3790 my_getExpression (&imm_expr
, s
);
3791 check_absolute_expr (ip
, &imm_expr
);
3792 if ((unsigned long) imm_expr
.X_add_number
> 31)
3794 as_warn ("Invalid cahce opcode (%lu)",
3795 (unsigned long) imm_expr
.X_add_number
);
3796 imm_expr
.X_add_number
&= 0x1f;
3798 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
3799 imm_expr
.X_op
= O_absent
;
3803 case 'c': /* break code */
3804 my_getExpression (&imm_expr
, s
);
3805 check_absolute_expr (ip
, &imm_expr
);
3806 if ((unsigned) imm_expr
.X_add_number
> 1023)
3807 as_warn ("Illegal break code (%ld)",
3808 (long) imm_expr
.X_add_number
);
3809 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3810 imm_expr
.X_op
= O_absent
;
3814 case 'B': /* syscall code */
3815 my_getExpression (&imm_expr
, s
);
3816 check_absolute_expr (ip
, &imm_expr
);
3817 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3818 as_warn ("Illegal syscall code (%ld)",
3819 (long) imm_expr
.X_add_number
);
3820 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3821 imm_expr
.X_op
= O_absent
;
3825 case 'C': /* Coprocessor code */
3826 my_getExpression (&imm_expr
, s
);
3827 check_absolute_expr (ip
, &imm_expr
);
3828 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3830 as_warn ("Coproccesor code > 25 bits (%ld)",
3831 (long) imm_expr
.X_add_number
);
3832 imm_expr
.X_add_number
&= ((1<<25) - 1);
3834 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3835 imm_expr
.X_op
= O_absent
;
3839 case 'b': /* base register */
3840 case 'd': /* destination register */
3841 case 's': /* source register */
3842 case 't': /* target register */
3843 case 'r': /* both target and source */
3844 case 'v': /* both dest and source */
3845 case 'w': /* both dest and target */
3846 case 'E': /* coprocessor target register */
3847 case 'G': /* coprocessor destination register */
3848 case 'x': /* ignore register name */
3849 case 'z': /* must be zero register */
3863 while (isdigit (*s
));
3865 as_bad ("Invalid register number (%d)", regno
);
3867 else if (*args
== 'E' || *args
== 'G')
3871 if (s
[1] == 'f' && s
[2] == 'p')
3876 else if (s
[1] == 's' && s
[2] == 'p')
3881 else if (s
[1] == 'g' && s
[2] == 'p')
3886 else if (s
[1] == 'a' && s
[2] == 't')
3894 if (regno
== AT
&& ! mips_noat
)
3895 as_warn ("Used $at without \".set noat\"");
3901 if (c
== 'r' || c
== 'v' || c
== 'w')
3908 /* 'z' only matches $0. */
3909 if (c
== 'z' && regno
!= 0)
3917 ip
->insn_opcode
|= regno
<< 21;
3921 ip
->insn_opcode
|= regno
<< 11;
3926 ip
->insn_opcode
|= regno
<< 16;
3929 /* This case exists because on the r3000 trunc
3930 expands into a macro which requires a gp
3931 register. On the r6000 or r4000 it is
3932 assembled into a single instruction which
3933 ignores the register. Thus the insn version
3934 is MIPS_ISA2 and uses 'x', and the macro
3935 version is MIPS_ISA1 and uses 't'. */
3938 /* This case is for the div instruction, which
3939 acts differently if the destination argument
3940 is $0. This only matches $0, and is checked
3941 outside the switch. */
3952 ip
->insn_opcode
|= lastregno
<< 21;
3955 ip
->insn_opcode
|= lastregno
<< 16;
3960 case 'D': /* floating point destination register */
3961 case 'S': /* floating point source register */
3962 case 'T': /* floating point target register */
3966 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3976 while (isdigit (*s
));
3979 as_bad ("Invalid float register number (%d)", regno
);
3981 if ((regno
& 1) != 0
3983 && ! (strcmp (str
, "mtc1") == 0 ||
3984 strcmp (str
, "mfc1") == 0 ||
3985 strcmp (str
, "lwc1") == 0 ||
3986 strcmp (str
, "swc1") == 0))
3987 as_warn ("Float register should be even, was %d",
3995 if (c
== 'V' || c
== 'W')
4005 ip
->insn_opcode
|= regno
<< 6;
4009 ip
->insn_opcode
|= regno
<< 11;
4013 ip
->insn_opcode
|= regno
<< 16;
4021 ip
->insn_opcode
|= lastregno
<< 11;
4024 ip
->insn_opcode
|= lastregno
<< 16;
4030 my_getExpression (&imm_expr
, s
);
4031 check_absolute_expr (ip
, &imm_expr
);
4036 my_getExpression (&offset_expr
, s
);
4037 imm_reloc
= BFD_RELOC_32
;
4049 unsigned char temp
[8];
4051 unsigned int length
;
4056 /* These only appear as the last operand in an
4057 instruction, and every instruction that accepts
4058 them in any variant accepts them in all variants.
4059 This means we don't have to worry about backing out
4060 any changes if the instruction does not match.
4062 The difference between them is the size of the
4063 floating point constant and where it goes. For 'F'
4064 and 'L' the constant is 64 bits; for 'f' and 'l' it
4065 is 32 bits. Where the constant is placed is based
4066 on how the MIPS assembler does things:
4069 f -- immediate value
4072 When generating PIC code, we do not use the .lit8
4073 or .lit4 sections at all, in order to reserve the
4074 entire global offset table. */
4076 f64
= *args
== 'F' || *args
== 'L';
4078 save_in
= input_line_pointer
;
4079 input_line_pointer
= s
;
4080 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4082 s
= input_line_pointer
;
4083 input_line_pointer
= save_in
;
4084 if (err
!= NULL
&& *err
!= '\0')
4086 as_bad ("Bad floating point constant: %s", err
);
4087 memset (temp
, '\0', sizeof temp
);
4088 length
= f64
? 8 : 4;
4091 assert (length
== (f64
? 8 : 4));
4094 || (mips_pic
!= 0 && *args
== 'l'))
4096 imm_expr
.X_op
= O_constant
;
4097 if (byte_order
== LITTLE_ENDIAN
)
4098 imm_expr
.X_add_number
=
4099 (((((((int) temp
[3] << 8)
4104 imm_expr
.X_add_number
=
4105 (((((((int) temp
[0] << 8)
4112 const char *newname
;
4115 /* Switch to the right section. */
4117 subseg
= now_subseg
;
4120 default: /* unused default case avoids warnings. */
4122 newname
= (mips_pic
== 0 ? ".lit8" : ".rdata");
4128 assert (mips_pic
== 0);
4132 new_seg
= subseg_new (newname
, (subsegT
) 0);
4134 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4137 as_bad ("Can't use floating point insn in this section");
4139 /* Set the argument to the current address in the
4141 offset_expr
.X_op
= O_symbol
;
4142 offset_expr
.X_add_symbol
=
4143 symbol_new ("L0\001", now_seg
,
4144 (valueT
) frag_now_fix (), frag_now
);
4145 offset_expr
.X_add_number
= 0;
4147 /* Put the floating point number into the section. */
4148 p
= frag_more ((int) length
);
4149 memcpy (p
, temp
, length
);
4151 /* Switch back to the original section. */
4152 subseg_set (seg
, subseg
);
4157 case 'i': /* 16 bit unsigned immediate */
4158 case 'j': /* 16 bit signed immediate */
4159 imm_reloc
= BFD_RELOC_LO16
;
4160 c
= my_getSmallExpression (&imm_expr
, s
);
4165 if (imm_expr
.X_op
== O_constant
)
4166 imm_expr
.X_add_number
=
4167 (imm_expr
.X_add_number
>> 16) & 0xffff;
4169 imm_reloc
= BFD_RELOC_HI16_S
;
4171 imm_reloc
= BFD_RELOC_HI16
;
4175 check_absolute_expr (ip
, &imm_expr
);
4178 if (imm_expr
.X_add_number
< 0
4179 || imm_expr
.X_add_number
>= 0x10000)
4181 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4182 !strcmp (insn
->name
, insn
[1].name
))
4184 as_bad ("16 bit expression not in range 0..65535");
4189 if (imm_expr
.X_add_number
< -0x8000 ||
4190 imm_expr
.X_add_number
>= 0x8000)
4192 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4193 !strcmp (insn
->name
, insn
[1].name
))
4195 as_bad ("16 bit expression not in range -32768..32767");
4201 case 'o': /* 16 bit offset */
4202 c
= my_getSmallExpression (&offset_expr
, s
);
4204 * If this value won't fit into a 16 bit offset, then
4205 * go find a macro that will generate the 32 bit offset
4208 if (offset_expr
.X_op
!= O_constant
4209 || offset_expr
.X_add_number
>= 0x8000
4210 || offset_expr
.X_add_number
< -0x8000)
4213 offset_reloc
= BFD_RELOC_LO16
;
4214 if (c
== 'h' || c
== 'H')
4216 assert (offset_expr
.X_op
== O_constant
);
4217 offset_expr
.X_add_number
=
4218 (offset_expr
.X_add_number
>> 16) & 0xffff;
4223 case 'p': /* pc relative offset */
4224 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4225 my_getExpression (&offset_expr
, s
);
4229 case 'u': /* upper 16 bits */
4230 c
= my_getSmallExpression (&imm_expr
, s
);
4231 if (imm_expr
.X_op
!= O_constant
4232 || imm_expr
.X_add_number
< 0
4233 || imm_expr
.X_add_number
>= 0x10000)
4234 as_bad ("lui expression not in range 0..65535");
4235 imm_reloc
= BFD_RELOC_LO16
;
4240 if (imm_expr
.X_op
== O_constant
)
4241 imm_expr
.X_add_number
=
4242 (imm_expr
.X_add_number
>> 16) & 0xffff;
4244 imm_reloc
= BFD_RELOC_HI16_S
;
4246 imm_reloc
= BFD_RELOC_HI16
;
4252 case 'a': /* 26 bit address */
4253 my_getExpression (&offset_expr
, s
);
4255 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4259 fprintf (stderr
, "bad char = '%c'\n", *args
);
4264 /* Args don't match. */
4265 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4266 !strcmp (insn
->name
, insn
[1].name
))
4272 insn_error
= "ERROR: Illegal operands";
4281 my_getSmallExpression (ep
, str
)
4292 ((str
[1] == 'h' && str
[2] == 'i')
4293 || (str
[1] == 'H' && str
[2] == 'I')
4294 || (str
[1] == 'l' && str
[2] == 'o'))
4306 * A small expression may be followed by a base register.
4307 * Scan to the end of this operand, and then back over a possible
4308 * base register. Then scan the small expression up to that
4309 * point. (Based on code in sparc.c...)
4311 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4313 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4315 if (isdigit (sp
[-2]))
4317 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4319 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4325 else if (sp
- 5 >= str
4328 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4329 || (sp
[-3] == 's' && sp
[-2] == 'p')
4330 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4331 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4337 /* no expression means zero offset */
4340 /* %xx(reg) is an error */
4341 ep
->X_op
= O_absent
;
4346 ep
->X_op
= O_constant
;
4349 ep
->X_add_symbol
= NULL
;
4350 ep
->X_op_symbol
= NULL
;
4351 ep
->X_add_number
= 0;
4356 my_getExpression (ep
, str
);
4363 my_getExpression (ep
, str
);
4364 return c
; /* => %hi or %lo encountered */
4368 my_getExpression (ep
, str
)
4374 save_in
= input_line_pointer
;
4375 input_line_pointer
= str
;
4377 expr_end
= input_line_pointer
;
4378 input_line_pointer
= save_in
;
4381 /* Turn a string in input_line_pointer into a floating point constant
4382 of type type, and store the appropriate bytes in *litP. The number
4383 of LITTLENUMS emitted is stored in *sizeP . An error message is
4384 returned, or NULL on OK. */
4387 md_atof (type
, litP
, sizeP
)
4393 LITTLENUM_TYPE words
[4];
4409 return "bad call to md_atof";
4412 t
= atof_ieee (input_line_pointer
, type
, words
);
4414 input_line_pointer
= t
;
4418 if (byte_order
== LITTLE_ENDIAN
)
4420 for (i
= prec
- 1; i
>= 0; i
--)
4422 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4428 for (i
= 0; i
< prec
; i
++)
4430 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4439 md_number_to_chars (buf
, val
, n
)
4447 number_to_chars_littleendian (buf
, val
, n
);
4451 number_to_chars_bigendian (buf
, val
, n
);
4460 md_parse_option (argP
, cntP
, vecP
)
4465 /* Accept -nocpp but ignore it. */
4466 if (strcmp (*argP
, "nocpp") == 0)
4472 if (strcmp (*argP
, "EL") == 0
4473 || strcmp (*argP
, "EB") == 0)
4475 /* FIXME: This breaks -L -EL. */
4483 if ((*argP
)[1] == '0')
4492 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4497 if (strncmp (*argP
, "mips", 4) == 0)
4499 mips_isa
= atol (*argP
+ 4);
4502 else if (mips_isa
< 1 || mips_isa
> 3)
4504 as_bad ("-mips%d not supported", mips_isa
);
4511 if (strncmp (*argP
, "mcpu=", 5) == 0)
4515 /* Identify the processor type */
4517 if (strcmp (p
, "default") == 0
4518 || strcmp (p
, "DEFAULT") == 0)
4522 if (*p
== 'r' || *p
== 'R')
4529 if (strcmp (p
, "2000") == 0
4530 || strcmp (p
, "2k") == 0
4531 || strcmp (p
, "2K") == 0)
4536 if (strcmp (p
, "3000") == 0
4537 || strcmp (p
, "3k") == 0
4538 || strcmp (p
, "3K") == 0)
4543 if (strcmp (p
, "4000") == 0
4544 || strcmp (p
, "4k") == 0
4545 || strcmp (p
, "4K") == 0)
4550 if (strcmp (p
, "6000") == 0
4551 || strcmp (p
, "6k") == 0
4552 || strcmp (p
, "6K") == 0)
4559 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4572 if ((*argP
)[1] != '\0')
4573 g_switch_value
= atoi (*argP
+ 1);
4576 **vecP
= (char *) NULL
;
4579 g_switch_value
= atoi (**vecP
);
4582 as_warn ("Number expected after -G");
4588 return 1; /* pretend you parsed the character */
4592 md_pcrel_from (fixP
)
4595 /* return the address of the delay slot */
4596 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4599 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4600 reloc for a cons. We could use the definition there, except that
4601 we want to handle 64 bit relocs specially. */
4604 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
4607 unsigned int nbytes
;
4610 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
4612 FIXME: There is no way to select anything but 32 bit mode right
4616 if (byte_order
== BIG_ENDIAN
)
4621 if (nbytes
!= 2 && nbytes
!= 4)
4622 as_bad ("Unsupported reloc size %d", nbytes
);
4624 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
4625 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
4629 md_apply_fix (fixP
, valueP
)
4636 assert (fixP
->fx_size
== 4);
4639 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
4641 switch (fixP
->fx_r_type
)
4644 case BFD_RELOC_MIPS_JMP
:
4645 case BFD_RELOC_HI16
:
4646 case BFD_RELOC_HI16_S
:
4647 case BFD_RELOC_LO16
:
4648 case BFD_RELOC_MIPS_GPREL
:
4649 case BFD_RELOC_MIPS_LITERAL
:
4650 case BFD_RELOC_MIPS_CALL16
:
4651 case BFD_RELOC_MIPS_GOT16
:
4652 case BFD_RELOC_MIPS_GPREL32
:
4653 /* Nothing needed to do. The value comes from the reloc entry */
4656 case BFD_RELOC_16_PCREL_S2
:
4658 * We need to save the bits in the instruction since fixup_segment()
4659 * might be deleting the relocation entry (i.e., a branch within
4660 * the current segment).
4663 as_warn ("Branch to odd address (%lx)", value
);
4665 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
4666 as_bad ("Relocation overflow");
4668 /* update old instruction data */
4669 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
4673 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
4677 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
4684 insn
|= value
& 0xFFFF;
4685 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
4699 const struct mips_opcode
*p
;
4700 int treg
, sreg
, dreg
, shamt
;
4705 for (i
= 0; i
< NUMOPCODES
; ++i
)
4707 p
= &mips_opcodes
[i
];
4708 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
4710 printf ("%08lx %s\t", oc
, p
->name
);
4711 treg
= (oc
>> 16) & 0x1f;
4712 sreg
= (oc
>> 21) & 0x1f;
4713 dreg
= (oc
>> 11) & 0x1f;
4714 shamt
= (oc
>> 6) & 0x1f;
4716 for (args
= p
->args
;; ++args
)
4727 printf ("%c", *args
);
4731 assert (treg
== sreg
);
4732 printf ("$%d,$%d", treg
, sreg
);
4737 printf ("$%d", dreg
);
4742 printf ("$%d", treg
);
4746 printf ("0x%x", treg
);
4751 printf ("$%d", sreg
);
4755 printf ("0x%08lx", oc
& 0x1ffffff);
4767 printf ("$%d", shamt
);
4778 printf ("%08lx UNDEFINED\n", oc
);
4789 name
= input_line_pointer
;
4790 c
= get_symbol_end ();
4791 p
= (symbolS
*) symbol_find_or_make (name
);
4792 *input_line_pointer
= c
;
4796 /* Align the current frag to a given power of two. The MIPS assembler
4797 also automatically adjusts any preceding label. */
4800 mips_align (to
, fill
)
4804 mips_emit_delays ();
4805 frag_align (to
, fill
);
4806 record_alignment (now_seg
, to
);
4807 if (insn_label
!= NULL
)
4809 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4810 insn_label
->sy_frag
= frag_now
;
4811 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4816 /* Align to a given power of two. .align 0 turns off the automatic
4817 alignment used by the data creating pseudo-ops. */
4824 register long temp_fill
;
4825 long max_alignment
= 15;
4829 o Note that the assembler pulls down any immediately preceeding label
4830 to the aligned address.
4831 o It's not documented but auto alignment is reinstated by
4832 a .align pseudo instruction.
4833 o Note also that after auto alignment is turned off the mips assembler
4834 issues an error on attempt to assemble an improperly aligned data item.
4839 temp
= get_absolute_expression ();
4840 if (temp
> max_alignment
)
4841 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4844 as_warn ("Alignment negative: 0 assumed.");
4847 if (*input_line_pointer
== ',')
4849 input_line_pointer
++;
4850 temp_fill
= get_absolute_expression ();
4857 mips_align (temp
, (int) temp_fill
);
4864 demand_empty_rest_of_line ();
4867 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4868 that there was a previous instruction. */
4871 s_stringer (append_zero
)
4874 mips_emit_delays ();
4876 stringer (append_zero
);
4887 mips_emit_delays ();
4897 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4898 demand_empty_rest_of_line ();
4903 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4904 demand_empty_rest_of_line ();
4906 #else /* ! defined (OBJ_ECOFF) */
4908 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
4909 bfd_set_section_flags (stdoutput
, seg
,
4915 bfd_set_section_alignment (stdoutput
, seg
, 4);
4916 demand_empty_rest_of_line ();
4918 #else /* ! defined (OBJ_ELF) */
4921 #endif /* ! defined (OBJ_ELF) */
4922 #endif /* ! defined (OBJ_ECOFF) */
4926 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4928 bfd_set_section_flags (stdoutput
, seg
,
4929 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
4930 bfd_set_section_alignment (stdoutput
, seg
, 4);
4932 demand_empty_rest_of_line ();
4934 #else /* ! defined (GPOPT) */
4935 as_bad ("Global pointers not supported; recompile -G 0");
4936 demand_empty_rest_of_line ();
4938 #endif /* ! defined (GPOPT) */
4948 mips_emit_delays ();
4949 if (log_size
> 0 && auto_align
)
4950 mips_align (log_size
, 0);
4952 cons (1 << log_size
);
4959 as_fatal ("Encountered `.err', aborting assembly");
4969 symbolP
= get_symbol ();
4970 if (*input_line_pointer
== ',')
4971 input_line_pointer
++;
4972 size
= get_absolute_expression ();
4973 S_SET_VALUE (symbolP
, size
);
4974 S_SET_EXTERNAL (symbolP
);
4976 #ifdef ECOFF_DEBUGGING
4977 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4978 so we use an additional ECOFF specific field. */
4979 symbolP
->ecoff_undefined
= 1;
4987 mips_emit_delays ();
5007 opt
= input_line_pointer
;
5008 c
= get_symbol_end ();
5012 /* FIXME: What does this mean? */
5014 else if (strncmp (opt
, "pic", 3) == 0)
5016 mips_pic
= atoi (opt
+ 3);
5017 /* Supposedly no other values are used. */
5018 assert (mips_pic
== 0 || mips_pic
== 2);
5021 as_warn ("Unrecognized option \"%s\"", opt
);
5023 *input_line_pointer
= c
;
5024 demand_empty_rest_of_line ();
5031 char *name
= input_line_pointer
, ch
;
5033 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5034 input_line_pointer
++;
5035 ch
= *input_line_pointer
;
5036 *input_line_pointer
= '\0';
5038 if (strcmp (name
, "reorder") == 0)
5042 prev_insn_unreordered
= 1;
5043 prev_prev_insn_unreordered
= 1;
5047 else if (strcmp (name
, "noreorder") == 0)
5049 mips_emit_delays ();
5051 mips_any_noreorder
= 1;
5053 else if (strcmp (name
, "at") == 0)
5057 else if (strcmp (name
, "noat") == 0)
5061 else if (strcmp (name
, "macro") == 0)
5063 mips_warn_about_macros
= 0;
5065 else if (strcmp (name
, "nomacro") == 0)
5067 if (mips_noreorder
== 0)
5068 as_bad ("`noreorder' must be set before `nomacro'");
5069 mips_warn_about_macros
= 1;
5071 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5075 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5079 else if (strcmp (name
, "bopt") == 0)
5083 else if (strcmp (name
, "nobopt") == 0)
5089 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5091 *input_line_pointer
= ch
;
5092 demand_empty_rest_of_line ();
5095 /* The same as the usual .space directive, except that we have to
5096 forget about any previous instruction. */
5099 s_mips_space (param
)
5102 mips_emit_delays ();
5107 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5108 .option pic2. It means to generate SVR4 PIC calls. */
5115 demand_empty_rest_of_line ();
5118 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5119 PIC code. It sets the $gp register for the function based on the
5120 function address, which is in the register named in the argument.
5121 This uses a relocation against _gp_disp, which is handled specially
5122 by the linker. The result is:
5123 lui $gp,%hi(_gp_disp)
5124 addiu $gp,$gp,%lo(_gp_disp)
5125 addu $gp,$gp,.cpload argument
5126 The .cpload argument is normally $25 == $t9. */
5135 /* If we are not generating PIC code, .cpload is ignored. */
5142 /* .cpload should be a in .set noreorder section. */
5143 if (mips_noreorder
== 0)
5144 as_warn (".cpload not in noreorder section");
5147 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5148 ex
.X_op_symbol
= NULL
;
5149 ex
.X_add_number
= 0;
5151 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5152 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5153 (int) BFD_RELOC_LO16
);
5155 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5156 GP
, GP
, tc_get_register (0));
5158 demand_empty_rest_of_line ();
5161 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5162 offset from $sp. The offset is remembered, and after making a PIC
5163 call $gp is restored from that location. */
5166 s_cprestore (ignore
)
5172 /* If we are not generating PIC code, .cprestore is ignored. */
5179 mips_cprestore_offset
= get_absolute_expression ();
5181 ex
.X_op
= O_constant
;
5182 ex
.X_add_symbol
= NULL
;
5183 ex
.X_op_symbol
= NULL
;
5184 ex
.X_add_number
= mips_cprestore_offset
;
5186 macro_build ((char *) NULL
, &icnt
, &ex
,
5187 mips_isa
< 3 ? "sw" : "sd",
5188 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5190 demand_empty_rest_of_line ();
5193 /* Handle the .gpword pseudo-op. This is used when generating PIC
5194 code. It generates a 32 bit GP relative reloc. */
5203 /* When not generating PIC code, this is treated as .word. */
5210 mips_emit_delays ();
5217 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5219 as_bad ("Unsupported use of .gpword");
5220 ignore_rest_of_line ();
5224 md_number_to_chars (p
, (valueT
) 0, 4);
5225 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5226 BFD_RELOC_MIPS_GPREL32
);
5228 demand_empty_rest_of_line ();
5231 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5232 tables in SVR4 PIC code. */
5241 /* This is ignored when not generating SVR4 PIC code. */
5248 /* Add $gp to the register named as an argument. */
5249 reg
= tc_get_register (0);
5250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5251 mips_isa
< 3 ? "addu" : "daddu",
5252 "d,v,t", reg
, reg
, GP
);
5254 demand_empty_rest_of_line ();
5257 /* Parse a register string into a number. Called from the ECOFF code
5258 to parse .frame. The argument is non-zero if this is the frame
5259 register, so that we can record it in mips_frame_reg. */
5262 tc_get_register (frame
)
5268 if (*input_line_pointer
++ != '$')
5270 as_warn ("expected `$'");
5273 else if (isdigit ((unsigned char) *input_line_pointer
))
5275 reg
= get_absolute_expression ();
5276 if (reg
< 0 || reg
>= 32)
5278 as_warn ("Bad register number");
5284 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5286 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5288 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5290 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5294 as_warn ("Unrecognized register name");
5297 input_line_pointer
+= 2;
5300 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5305 md_section_align (seg
, addr
)
5309 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5311 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5314 /* Estimate the size of a frag before relaxing. We are not really
5315 relaxing here, and the final size is encoded in the subtype
5320 md_estimate_size_before_relax (fragp
, segtype
)
5329 const char *symname
;
5331 /* Find out whether this symbol can be referenced off the GP
5332 register. It can be if it is smaller than the -G size or if
5333 it is in the .sdata or .sbss section. Certain symbols can
5334 not be referenced off the GP, although it appears as though
5336 symname
= S_GET_NAME (fragp
->fr_symbol
);
5337 if (symname
!= (const char *) NULL
5338 && (strcmp (symname
, "eprol") == 0
5339 || strcmp (symname
, "etext") == 0
5340 || strcmp (symname
, "_gp") == 0
5341 || strcmp (symname
, "edata") == 0
5342 || strcmp (symname
, "_fbss") == 0
5343 || strcmp (symname
, "_fdata") == 0
5344 || strcmp (symname
, "_ftext") == 0
5345 || strcmp (symname
, "end") == 0
5346 || strcmp (symname
, "_gp_disp") == 0))
5348 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5349 && S_GET_VALUE (fragp
->fr_symbol
) != 0
5350 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)
5354 const char *segname
;
5356 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5357 assert (strcmp (segname
, ".lit8") != 0
5358 && strcmp (segname
, ".lit4") != 0);
5359 change
= (strcmp (segname
, ".sdata") != 0
5360 && strcmp (segname
, ".sbss") != 0);
5362 #else /* ! defined (GPOPT) */
5363 /* We are not optimizing for the GP register. */
5365 #endif /* ! defined (GPOPT) */
5369 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5371 /* This must duplicate the test in adjust_reloc_syms. */
5372 change
= (symsec
!= &bfd_und_section
5373 && symsec
!= &bfd_abs_section
5374 && ! bfd_is_com_section (symsec
));
5379 /* Record the offset to the first reloc in the fr_opcode field.
5380 This lets md_convert_frag and tc_gen_reloc know that the code
5381 must be expanded. */
5382 fragp
->fr_opcode
= (fragp
->fr_literal
5384 - RELAX_OLD (fragp
->fr_subtype
)
5385 + RELAX_RELOC1 (fragp
->fr_subtype
));
5386 /* FIXME: This really needs as_warn_where. */
5387 if (RELAX_WARN (fragp
->fr_subtype
))
5388 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
5394 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
5397 /* Translate internal representation of relocation info to BFD target
5401 tc_gen_reloc (section
, fixp
)
5405 static arelent
*retval
[4];
5408 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
5411 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5412 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5413 if (fixp
->fx_pcrel
== 0)
5414 reloc
->addend
= fixp
->fx_addnumber
;
5419 reloc
->addend
= -reloc
->address
;
5422 /* If this is a variant frag, we may need to adjust the existing
5423 reloc and generate a new one. */
5424 if (fixp
->fx_frag
->fr_opcode
!= NULL
5425 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5426 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
5427 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
5431 /* If this is not the last reloc in this frag, then we have two
5432 GPREL relocs, both of which are being replaced. Let the
5433 second one handle all of them. */
5434 if (fixp
->fx_next
!= NULL
5435 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
5437 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5438 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5443 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
5444 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5445 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
5447 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5448 reloc2
->address
= (reloc
->address
5449 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
5450 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
5451 reloc2
->addend
= fixp
->fx_addnumber
;
5452 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
5453 assert (reloc2
->howto
!= NULL
);
5455 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
5459 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
5462 reloc3
->address
+= 4;
5467 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5468 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
5472 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
5474 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
5475 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
5480 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5482 if (reloc
->howto
== NULL
)
5484 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5485 "Can not represent relocation in this object file format");
5492 /* Convert a machine dependent frag. */
5495 md_convert_frag (abfd
, asec
, fragp
)
5503 if (fragp
->fr_opcode
== NULL
)
5506 old
= RELAX_OLD (fragp
->fr_subtype
);
5507 new = RELAX_NEW (fragp
->fr_subtype
);
5508 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
5511 memcpy (fixptr
- old
, fixptr
, new);
5513 fragp
->fr_fix
+= new - old
;
5516 /* This function is called whenever a label is defined. It is used
5517 when handling branch delays; if a branch has a label, we assume we
5521 mips_define_label (sym
)
5529 /* Some special processing for a MIPS ELF file. */
5532 mips_elf_final_processing ()
5536 /* Write out the .reginfo section. */
5537 s
.ri_gprmask
= mips_gprmask
;
5538 s
.ri_cprmask
[0] = mips_cprmask
[0];
5539 s
.ri_cprmask
[1] = mips_cprmask
[1];
5540 s
.ri_cprmask
[2] = mips_cprmask
[2];
5541 s
.ri_cprmask
[3] = mips_cprmask
[3];
5542 /* The gp_value field is set by the MIPS ELF backend. */
5544 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
5545 ((Elf32_External_RegInfo
*)
5546 mips_regmask_frag
));
5548 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
5549 sort of BFD interface for this. */
5550 if (mips_any_noreorder
)
5551 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
5553 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
5556 #endif /* OBJ_ELF */
5558 #ifndef ECOFF_DEBUGGING
5560 /* These functions should really be defined by the object file format,
5561 since they are related to debugging information. However, this
5562 code has to work for the a.out format, which does not define them,
5563 so we provide simple versions here. These don't actually generate
5564 any debugging information, but they do simple checking and someday
5565 somebody may make them useful. */
5569 struct loc
*loc_next
;
5570 unsigned long loc_fileno
;
5571 unsigned long loc_lineno
;
5572 unsigned long loc_offset
;
5573 unsigned short loc_delta
;
5574 unsigned short loc_count
;
5583 struct proc
*proc_next
;
5584 struct symbol
*proc_isym
;
5585 struct symbol
*proc_end
;
5586 unsigned long proc_reg_mask
;
5587 unsigned long proc_reg_offset
;
5588 unsigned long proc_fpreg_mask
;
5589 unsigned long proc_fpreg_offset
;
5590 unsigned long proc_frameoffset
;
5591 unsigned long proc_framereg
;
5592 unsigned long proc_pcreg
;
5594 struct file
*proc_file
;
5601 struct file
*file_next
;
5602 unsigned long file_fileno
;
5603 struct symbol
*file_symbol
;
5604 struct symbol
*file_end
;
5605 struct proc
*file_proc
;
5610 static struct obstack proc_frags
;
5611 static procS
*proc_lastP
;
5612 static procS
*proc_rootP
;
5613 static int numprocs
;
5618 obstack_begin (&proc_frags
, 0x2000);
5624 /* check for premature end, nesting errors, etc */
5625 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5626 as_warn ("missing `.end' at end of assembly");
5629 extern char hex_value
[];
5637 if (*input_line_pointer
== '-')
5639 ++input_line_pointer
;
5642 if (!isdigit (*input_line_pointer
))
5643 as_bad ("Expected simple number.");
5644 if (input_line_pointer
[0] == '0')
5646 if (input_line_pointer
[1] == 'x')
5648 input_line_pointer
+= 2;
5649 while (isxdigit (*input_line_pointer
))
5652 val
|= hex_value
[(int) *input_line_pointer
++];
5654 return negative
? -val
: val
;
5658 ++input_line_pointer
;
5659 while (isdigit (*input_line_pointer
))
5662 val
|= *input_line_pointer
++ - '0';
5664 return negative
? -val
: val
;
5667 if (!isdigit (*input_line_pointer
))
5669 printf (" *input_line_pointer == '%c' 0x%02x\n",
5670 *input_line_pointer
, *input_line_pointer
);
5671 as_warn ("Invalid number");
5674 while (isdigit (*input_line_pointer
))
5677 val
+= *input_line_pointer
++ - '0';
5679 return negative
? -val
: val
;
5682 /* The .file directive; just like the usual .file directive, but there
5683 is an initial number which is the ECOFF file index. */
5691 line
= get_number ();
5696 /* The .end directive. */
5704 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5707 demand_empty_rest_of_line ();
5711 if (now_seg
!= text_section
)
5712 as_warn (".end not in text section");
5715 as_warn (".end and no .ent seen yet.");
5721 assert (S_GET_NAME (p
));
5722 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
5723 as_warn (".end symbol does not match .ent symbol.");
5726 proc_lastP
->proc_end
= (symbolS
*) 1;
5729 /* The .aent and .ent directives. */
5739 symbolP
= get_symbol ();
5740 if (*input_line_pointer
== ',')
5741 input_line_pointer
++;
5743 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
5744 number
= get_number ();
5745 if (now_seg
!= text_section
)
5746 as_warn (".ent or .aent not in text section.");
5748 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5749 as_warn ("missing `.end'");
5753 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
5754 procP
->proc_isym
= symbolP
;
5755 procP
->proc_reg_mask
= 0;
5756 procP
->proc_reg_offset
= 0;
5757 procP
->proc_fpreg_mask
= 0;
5758 procP
->proc_fpreg_offset
= 0;
5759 procP
->proc_frameoffset
= 0;
5760 procP
->proc_framereg
= 0;
5761 procP
->proc_pcreg
= 0;
5762 procP
->proc_end
= NULL
;
5763 procP
->proc_next
= NULL
;
5765 proc_lastP
->proc_next
= procP
;
5771 demand_empty_rest_of_line ();
5774 /* The .frame directive. */
5787 frame_reg
= tc_get_register (1);
5788 if (*input_line_pointer
== ',')
5789 input_line_pointer
++;
5790 frame_off
= get_absolute_expression ();
5791 if (*input_line_pointer
== ',')
5792 input_line_pointer
++;
5793 pcreg
= tc_get_register (0);
5796 assert (proc_rootP
);
5797 proc_rootP
->proc_framereg
= frame_reg
;
5798 proc_rootP
->proc_frameoffset
= frame_off
;
5799 proc_rootP
->proc_pcreg
= pcreg
;
5800 /* bob macho .frame */
5802 /* We don't have to write out a frame stab for unoptimized code. */
5803 if (!(frame_reg
== FP
&& frame_off
== 0))
5806 as_warn ("No .ent for .frame to use.");
5807 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
5808 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
5809 S_SET_TYPE (symP
, N_RMASK
);
5810 S_SET_OTHER (symP
, 0);
5811 S_SET_DESC (symP
, 0);
5812 symP
->sy_forward
= proc_lastP
->proc_isym
;
5813 /* bob perhaps I should have used pseudo set */
5815 demand_empty_rest_of_line ();
5819 /* The .fmask and .mask directives. */
5826 char str
[100], *strP
;
5832 mask
= get_number ();
5833 if (*input_line_pointer
== ',')
5834 input_line_pointer
++;
5835 off
= get_absolute_expression ();
5837 /* bob only for coff */
5838 assert (proc_rootP
);
5839 if (reg_type
== 'F')
5841 proc_rootP
->proc_fpreg_mask
= mask
;
5842 proc_rootP
->proc_fpreg_offset
= off
;
5846 proc_rootP
->proc_reg_mask
= mask
;
5847 proc_rootP
->proc_reg_offset
= off
;
5850 /* bob macho .mask + .fmask */
5852 /* We don't have to write out a mask stab if no saved regs. */
5856 as_warn ("No .ent for .mask to use.");
5858 for (i
= 0; i
< 32; i
++)
5862 sprintf (strP
, "%c%d,", reg_type
, i
);
5863 strP
+= strlen (strP
);
5867 sprintf (strP
, ";%d,", off
);
5868 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
5869 S_SET_TYPE (symP
, N_RMASK
);
5870 S_SET_OTHER (symP
, 0);
5871 S_SET_DESC (symP
, 0);
5872 symP
->sy_forward
= proc_lastP
->proc_isym
;
5873 /* bob perhaps I should have used pseudo set */
5878 /* The .loc directive. */
5889 assert (now_seg
== text_section
);
5891 lineno
= get_number ();
5892 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
5894 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
5895 S_SET_TYPE (symbolP
, N_SLINE
);
5896 S_SET_OTHER (symbolP
, 0);
5897 S_SET_DESC (symbolP
, lineno
);
5898 symbolP
->sy_segment
= now_seg
;
5902 #endif /* ! defined (ECOFF_DEBUGGING) */