1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* Whether or not we have code that can call pic code. */
135 int mips_abicalls
= FALSE
;
137 /* This is the set of options which may be modified by the .set
138 pseudo-op. We use a struct so that .set push and .set pop are more
141 struct mips_set_options
143 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
144 if it has not been initialized. Changed by `.set mipsN', and the
145 -mipsN command line option, and the default CPU. */
147 /* Enabled Application Specific Extensions (ASEs). These are set to -1
148 if they have not been initialized. Changed by `.set <asename>', by
149 command line options, and based on the default architecture. */
152 /* Whether we are assembling for the mips16 processor. 0 if we are
153 not, 1 if we are, and -1 if the value has not been initialized.
154 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
155 -nomips16 command line options, and the default CPU. */
157 /* Non-zero if we should not reorder instructions. Changed by `.set
158 reorder' and `.set noreorder'. */
160 /* Non-zero if we should not permit the $at ($1) register to be used
161 in instructions. Changed by `.set at' and `.set noat'. */
163 /* Non-zero if we should warn when a macro instruction expands into
164 more than one machine instruction. Changed by `.set nomacro' and
166 int warn_about_macros
;
167 /* Non-zero if we should not move instructions. Changed by `.set
168 move', `.set volatile', `.set nomove', and `.set novolatile'. */
170 /* Non-zero if we should not optimize branches by moving the target
171 of the branch into the delay slot. Actually, we don't perform
172 this optimization anyhow. Changed by `.set bopt' and `.set
175 /* Non-zero if we should not autoextend mips16 instructions.
176 Changed by `.set autoextend' and `.set noautoextend'. */
178 /* Restrict general purpose registers and floating point registers
179 to 32 bit. This is initially determined when -mgp32 or -mfp32
180 is passed but can changed if the assembler code uses .set mipsN. */
185 /* True if -mgp32 was passed. */
186 static int file_mips_gp32
= -1;
188 /* True if -mfp32 was passed. */
189 static int file_mips_fp32
= -1;
191 /* This is the struct we use to hold the current set of options. Note
192 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
193 -1 to indicate that they have not been initialized. */
195 static struct mips_set_options mips_opts
=
197 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
200 /* These variables are filled in with the masks of registers used.
201 The object format code reads them and puts them in the appropriate
203 unsigned long mips_gprmask
;
204 unsigned long mips_cprmask
[4];
206 /* MIPS ISA we are using for this output file. */
207 static int file_mips_isa
= ISA_UNKNOWN
;
209 /* True if -mips16 was passed or implied by arguments passed on the
210 command line (e.g., by -march). */
211 static int file_ase_mips16
;
213 /* True if -mips3d was passed or implied by arguments passed on the
214 command line (e.g., by -march). */
215 static int file_ase_mips3d
;
217 /* True if -mdmx was passed or implied by arguments passed on the
218 command line (e.g., by -march). */
219 static int file_ase_mdmx
;
221 /* The argument of the -march= flag. The architecture we are assembling. */
222 static int mips_arch
= CPU_UNKNOWN
;
223 static const char *mips_arch_string
;
224 static const struct mips_cpu_info
*mips_arch_info
;
226 /* The argument of the -mtune= flag. The architecture for which we
228 static int mips_tune
= CPU_UNKNOWN
;
229 static const char *mips_tune_string
;
230 static const struct mips_cpu_info
*mips_tune_info
;
232 /* True when generating 32-bit code for a 64-bit processor. */
233 static int mips_32bitmode
= 0;
235 /* Some ISA's have delay slots for instructions which read or write
236 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
237 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
238 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
239 delay slot in this ISA. The uses of this macro assume that any
240 ISA that has delay slots for one of these, has them for all. They
241 also assume that ISAs which don't have delays for these insns, don't
242 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
243 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
245 || (ISA) == ISA_MIPS2 \
246 || (ISA) == ISA_MIPS3 \
249 /* True if the given ABI requires 32-bit registers. */
250 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
252 /* Likewise 64-bit registers. */
253 #define ABI_NEEDS_64BIT_REGS(ABI) \
255 || (ABI) == N64_ABI \
258 /* Return true if ISA supports 64 bit gp register instructions. */
259 #define ISA_HAS_64BIT_REGS(ISA) ( \
261 || (ISA) == ISA_MIPS4 \
262 || (ISA) == ISA_MIPS5 \
263 || (ISA) == ISA_MIPS64 \
266 /* Return true if ISA supports 64-bit right rotate (dror et al.)
268 #define ISA_HAS_DROR(ISA) ( \
272 /* Return true if ISA supports 32-bit right rotate (ror et al.)
274 #define ISA_HAS_ROR(ISA) ( \
275 (ISA) == ISA_MIPS32R2 \
278 #define HAVE_32BIT_GPRS \
279 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
281 #define HAVE_32BIT_FPRS \
282 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
284 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
285 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
287 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
289 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
291 /* We can only have 64bit addresses if the object file format
293 #define HAVE_32BIT_ADDRESSES \
295 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
296 || ! HAVE_64BIT_OBJECTS) \
297 && mips_pic != EMBEDDED_PIC))
299 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
300 #define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \
303 /* Return true if the given CPU supports the MIPS16 ASE. */
304 #define CPU_HAS_MIPS16(cpu) \
305 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
306 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
308 /* Return true if the given CPU supports the MIPS3D ASE. */
309 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
312 /* Return true if the given CPU supports the MDMX ASE. */
313 #define CPU_HAS_MDMX(cpu) (FALSE \
316 /* True if CPU has a dror instruction. */
317 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
319 /* True if CPU has a ror instruction. */
320 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
322 /* Whether the processor uses hardware interlocks to protect
323 reads from the HI and LO registers, and thus does not
324 require nops to be inserted. */
326 #define hilo_interlocks (mips_arch == CPU_R4010 \
327 || mips_arch == CPU_VR5500 \
328 || mips_arch == CPU_SB1 \
331 /* Whether the processor uses hardware interlocks to protect reads
332 from the GPRs, and thus does not require nops to be inserted. */
333 #define gpr_interlocks \
334 (mips_opts.isa != ISA_MIPS1 \
335 || mips_arch == CPU_VR5400 \
336 || mips_arch == CPU_VR5500 \
337 || mips_arch == CPU_R3900)
339 /* As with other "interlocks" this is used by hardware that has FP
340 (co-processor) interlocks. */
341 /* Itbl support may require additional care here. */
342 #define cop_interlocks (mips_arch == CPU_R4300 \
343 || mips_arch == CPU_VR5400 \
344 || mips_arch == CPU_VR5500 \
345 || mips_arch == CPU_SB1 \
348 /* Is this a mfhi or mflo instruction? */
349 #define MF_HILO_INSN(PINFO) \
350 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
352 /* MIPS PIC level. */
354 enum mips_pic_level mips_pic
;
356 /* Warn about all NOPS that the assembler generates. */
357 static int warn_nops
= 0;
359 /* 1 if we should generate 32 bit offsets from the $gp register in
360 SVR4_PIC mode. Currently has no meaning in other modes. */
361 static int mips_big_got
= 0;
363 /* 1 if trap instructions should used for overflow rather than break
365 static int mips_trap
= 0;
367 /* 1 if double width floating point constants should not be constructed
368 by assembling two single width halves into two single width floating
369 point registers which just happen to alias the double width destination
370 register. On some architectures this aliasing can be disabled by a bit
371 in the status register, and the setting of this bit cannot be determined
372 automatically at assemble time. */
373 static int mips_disable_float_construction
;
375 /* Non-zero if any .set noreorder directives were used. */
377 static int mips_any_noreorder
;
379 /* Non-zero if nops should be inserted when the register referenced in
380 an mfhi/mflo instruction is read in the next two instructions. */
381 static int mips_7000_hilo_fix
;
383 /* The size of the small data section. */
384 static unsigned int g_switch_value
= 8;
385 /* Whether the -G option was used. */
386 static int g_switch_seen
= 0;
391 /* If we can determine in advance that GP optimization won't be
392 possible, we can skip the relaxation stuff that tries to produce
393 GP-relative references. This makes delay slot optimization work
396 This function can only provide a guess, but it seems to work for
397 gcc output. It needs to guess right for gcc, otherwise gcc
398 will put what it thinks is a GP-relative instruction in a branch
401 I don't know if a fix is needed for the SVR4_PIC mode. I've only
402 fixed it for the non-PIC mode. KR 95/04/07 */
403 static int nopic_need_relax
PARAMS ((symbolS
*, int));
405 /* handle of the OPCODE hash table */
406 static struct hash_control
*op_hash
= NULL
;
408 /* The opcode hash table we use for the mips16. */
409 static struct hash_control
*mips16_op_hash
= NULL
;
411 /* This array holds the chars that always start a comment. If the
412 pre-processor is disabled, these aren't very useful */
413 const char comment_chars
[] = "#";
415 /* This array holds the chars that only start a comment at the beginning of
416 a line. If the line seems to have the form '# 123 filename'
417 .line and .file directives will appear in the pre-processed output */
418 /* Note that input_file.c hand checks for '#' at the beginning of the
419 first line of the input file. This is because the compiler outputs
420 #NO_APP at the beginning of its output. */
421 /* Also note that C style comments are always supported. */
422 const char line_comment_chars
[] = "#";
424 /* This array holds machine specific line separator characters. */
425 const char line_separator_chars
[] = ";";
427 /* Chars that can be used to separate mant from exp in floating point nums */
428 const char EXP_CHARS
[] = "eE";
430 /* Chars that mean this number is a floating point constant */
433 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
435 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
436 changed in read.c . Ideally it shouldn't have to know about it at all,
437 but nothing is ideal around here.
440 static char *insn_error
;
442 static int auto_align
= 1;
444 /* When outputting SVR4 PIC code, the assembler needs to know the
445 offset in the stack frame from which to restore the $gp register.
446 This is set by the .cprestore pseudo-op, and saved in this
448 static offsetT mips_cprestore_offset
= -1;
450 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
451 more optimizations, it can use a register value instead of a memory-saved
452 offset and even an other register than $gp as global pointer. */
453 static offsetT mips_cpreturn_offset
= -1;
454 static int mips_cpreturn_register
= -1;
455 static int mips_gp_register
= GP
;
456 static int mips_gprel_offset
= 0;
458 /* Whether mips_cprestore_offset has been set in the current function
459 (or whether it has already been warned about, if not). */
460 static int mips_cprestore_valid
= 0;
462 /* This is the register which holds the stack frame, as set by the
463 .frame pseudo-op. This is needed to implement .cprestore. */
464 static int mips_frame_reg
= SP
;
466 /* Whether mips_frame_reg has been set in the current function
467 (or whether it has already been warned about, if not). */
468 static int mips_frame_reg_valid
= 0;
470 /* To output NOP instructions correctly, we need to keep information
471 about the previous two instructions. */
473 /* Whether we are optimizing. The default value of 2 means to remove
474 unneeded NOPs and swap branch instructions when possible. A value
475 of 1 means to not swap branches. A value of 0 means to always
477 static int mips_optimize
= 2;
479 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
480 equivalent to seeing no -g option at all. */
481 static int mips_debug
= 0;
483 /* The previous instruction. */
484 static struct mips_cl_insn prev_insn
;
486 /* The instruction before prev_insn. */
487 static struct mips_cl_insn prev_prev_insn
;
489 /* If we don't want information for prev_insn or prev_prev_insn, we
490 point the insn_mo field at this dummy integer. */
491 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
493 /* Non-zero if prev_insn is valid. */
494 static int prev_insn_valid
;
496 /* The frag for the previous instruction. */
497 static struct frag
*prev_insn_frag
;
499 /* The offset into prev_insn_frag for the previous instruction. */
500 static long prev_insn_where
;
502 /* The reloc type for the previous instruction, if any. */
503 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
505 /* The reloc for the previous instruction, if any. */
506 static fixS
*prev_insn_fixp
[3];
508 /* Non-zero if the previous instruction was in a delay slot. */
509 static int prev_insn_is_delay_slot
;
511 /* Non-zero if the previous instruction was in a .set noreorder. */
512 static int prev_insn_unreordered
;
514 /* Non-zero if the previous instruction uses an extend opcode (if
516 static int prev_insn_extended
;
518 /* Non-zero if the previous previous instruction was in a .set
520 static int prev_prev_insn_unreordered
;
522 /* If this is set, it points to a frag holding nop instructions which
523 were inserted before the start of a noreorder section. If those
524 nops turn out to be unnecessary, the size of the frag can be
526 static fragS
*prev_nop_frag
;
528 /* The number of nop instructions we created in prev_nop_frag. */
529 static int prev_nop_frag_holds
;
531 /* The number of nop instructions that we know we need in
533 static int prev_nop_frag_required
;
535 /* The number of instructions we've seen since prev_nop_frag. */
536 static int prev_nop_frag_since
;
538 /* For ECOFF and ELF, relocations against symbols are done in two
539 parts, with a HI relocation and a LO relocation. Each relocation
540 has only 16 bits of space to store an addend. This means that in
541 order for the linker to handle carries correctly, it must be able
542 to locate both the HI and the LO relocation. This means that the
543 relocations must appear in order in the relocation table.
545 In order to implement this, we keep track of each unmatched HI
546 relocation. We then sort them so that they immediately precede the
547 corresponding LO relocation. */
552 struct mips_hi_fixup
*next
;
555 /* The section this fixup is in. */
559 /* The list of unmatched HI relocs. */
561 static struct mips_hi_fixup
*mips_hi_fixup_list
;
563 /* The frag containing the last explicit relocation operator.
564 Null if explicit relocations have not been used. */
566 static fragS
*prev_reloc_op_frag
;
568 /* Map normal MIPS register numbers to mips16 register numbers. */
570 #define X ILLEGAL_REG
571 static const int mips32_to_16_reg_map
[] =
573 X
, X
, 2, 3, 4, 5, 6, 7,
574 X
, X
, X
, X
, X
, X
, X
, X
,
575 0, 1, X
, X
, X
, X
, X
, X
,
576 X
, X
, X
, X
, X
, X
, X
, X
580 /* Map mips16 register numbers to normal MIPS register numbers. */
582 static const unsigned int mips16_to_32_reg_map
[] =
584 16, 17, 2, 3, 4, 5, 6, 7
587 static int mips_fix_4122_bugs
;
589 /* We don't relax branches by default, since this causes us to expand
590 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
591 fail to compute the offset before expanding the macro to the most
592 efficient expansion. */
594 static int mips_relax_branch
;
596 /* Since the MIPS does not have multiple forms of PC relative
597 instructions, we do not have to do relaxing as is done on other
598 platforms. However, we do have to handle GP relative addressing
599 correctly, which turns out to be a similar problem.
601 Every macro that refers to a symbol can occur in (at least) two
602 forms, one with GP relative addressing and one without. For
603 example, loading a global variable into a register generally uses
604 a macro instruction like this:
606 If i can be addressed off the GP register (this is true if it is in
607 the .sbss or .sdata section, or if it is known to be smaller than
608 the -G argument) this will generate the following instruction:
610 This instruction will use a GPREL reloc. If i can not be addressed
611 off the GP register, the following instruction sequence will be used:
614 In this case the first instruction will have a HI16 reloc, and the
615 second reloc will have a LO16 reloc. Both relocs will be against
618 The issue here is that we may not know whether i is GP addressable
619 until after we see the instruction that uses it. Therefore, we
620 want to be able to choose the final instruction sequence only at
621 the end of the assembly. This is similar to the way other
622 platforms choose the size of a PC relative instruction only at the
625 When generating position independent code we do not use GP
626 addressing in quite the same way, but the issue still arises as
627 external symbols and local symbols must be handled differently.
629 We handle these issues by actually generating both possible
630 instruction sequences. The longer one is put in a frag_var with
631 type rs_machine_dependent. We encode what to do with the frag in
632 the subtype field. We encode (1) the number of existing bytes to
633 replace, (2) the number of new bytes to use, (3) the offset from
634 the start of the existing bytes to the first reloc we must generate
635 (that is, the offset is applied from the start of the existing
636 bytes after they are replaced by the new bytes, if any), (4) the
637 offset from the start of the existing bytes to the second reloc,
638 (5) whether a third reloc is needed (the third reloc is always four
639 bytes after the second reloc), and (6) whether to warn if this
640 variant is used (this is sometimes needed if .set nomacro or .set
641 noat is in effect). All these numbers are reasonably small.
643 Generating two instruction sequences must be handled carefully to
644 ensure that delay slots are handled correctly. Fortunately, there
645 are a limited number of cases. When the second instruction
646 sequence is generated, append_insn is directed to maintain the
647 existing delay slot information, so it continues to apply to any
648 code after the second instruction sequence. This means that the
649 second instruction sequence must not impose any requirements not
650 required by the first instruction sequence.
652 These variant frags are then handled in functions called by the
653 machine independent code. md_estimate_size_before_relax returns
654 the final size of the frag. md_convert_frag sets up the final form
655 of the frag. tc_gen_reloc adjust the first reloc and adds a second
657 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
661 | (((reloc1) + 64) << 9) \
662 | (((reloc2) + 64) << 2) \
663 | ((reloc3) ? (1 << 1) : 0) \
665 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
666 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
667 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
668 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
669 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
670 #define RELAX_WARN(i) ((i) & 1)
672 /* Branch without likely bit. If label is out of range, we turn:
674 beq reg1, reg2, label
684 with the following opcode replacements:
691 bltzal <-> bgezal (with jal label instead of j label)
693 Even though keeping the delay slot instruction in the delay slot of
694 the branch would be more efficient, it would be very tricky to do
695 correctly, because we'd have to introduce a variable frag *after*
696 the delay slot instruction, and expand that instead. Let's do it
697 the easy way for now, even if the branch-not-taken case now costs
698 one additional instruction. Out-of-range branches are not supposed
699 to be common, anyway.
701 Branch likely. If label is out of range, we turn:
703 beql reg1, reg2, label
704 delay slot (annulled if branch not taken)
713 delay slot (executed only if branch taken)
716 It would be possible to generate a shorter sequence by losing the
717 likely bit, generating something like:
722 delay slot (executed only if branch taken)
734 bltzall -> bgezal (with jal label instead of j label)
735 bgezall -> bltzal (ditto)
738 but it's not clear that it would actually improve performance. */
739 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
742 | ((toofar) ? 1 : 0) \
744 | ((likely) ? 4 : 0) \
745 | ((uncond) ? 8 : 0)))
746 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
747 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
748 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
749 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
750 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
752 /* For mips16 code, we use an entirely different form of relaxation.
753 mips16 supports two versions of most instructions which take
754 immediate values: a small one which takes some small value, and a
755 larger one which takes a 16 bit value. Since branches also follow
756 this pattern, relaxing these values is required.
758 We can assemble both mips16 and normal MIPS code in a single
759 object. Therefore, we need to support this type of relaxation at
760 the same time that we support the relaxation described above. We
761 use the high bit of the subtype field to distinguish these cases.
763 The information we store for this type of relaxation is the
764 argument code found in the opcode file for this relocation, whether
765 the user explicitly requested a small or extended form, and whether
766 the relocation is in a jump or jal delay slot. That tells us the
767 size of the value, and how it should be stored. We also store
768 whether the fragment is considered to be extended or not. We also
769 store whether this is known to be a branch to a different section,
770 whether we have tried to relax this frag yet, and whether we have
771 ever extended a PC relative fragment because of a shift count. */
772 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
775 | ((small) ? 0x100 : 0) \
776 | ((ext) ? 0x200 : 0) \
777 | ((dslot) ? 0x400 : 0) \
778 | ((jal_dslot) ? 0x800 : 0))
779 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
780 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
781 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
782 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
783 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
784 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
785 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
786 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
787 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
788 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
789 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
790 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
792 /* Is the given value a sign-extended 32-bit value? */
793 #define IS_SEXT_32BIT_NUM(x) \
794 (((x) &~ (offsetT) 0x7fffffff) == 0 \
795 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
797 /* Is the given value a sign-extended 16-bit value? */
798 #define IS_SEXT_16BIT_NUM(x) \
799 (((x) &~ (offsetT) 0x7fff) == 0 \
800 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
803 /* Prototypes for static functions. */
806 #define internalError() \
807 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
809 #define internalError() as_fatal (_("MIPS internal Error"));
812 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
814 static inline bfd_boolean reloc_needs_lo_p
815 PARAMS ((bfd_reloc_code_real_type
));
816 static inline bfd_boolean fixup_has_matching_lo_p
818 static int insn_uses_reg
819 PARAMS ((struct mips_cl_insn
*ip
, unsigned int reg
,
820 enum mips_regclass
class));
821 static int reg_needs_delay
822 PARAMS ((unsigned int));
823 static void mips16_mark_labels
825 static void append_insn
826 PARAMS ((char *place
, struct mips_cl_insn
* ip
, expressionS
* p
,
827 bfd_reloc_code_real_type
*r
));
828 static void mips_no_prev_insn
830 static void mips_emit_delays
831 PARAMS ((bfd_boolean
));
833 static void macro_build
834 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *name
,
835 const char *fmt
, ...));
837 static void macro_build ();
839 static void mips16_macro_build
840 PARAMS ((char *, int *, expressionS
*, const char *, const char *, va_list));
841 static void macro_build_jalr
842 PARAMS ((int, expressionS
*));
843 static void macro_build_lui
844 PARAMS ((char *place
, int *counter
, expressionS
* ep
, int regnum
));
845 static void macro_build_ldst_constoffset
846 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *op
,
847 int valreg
, int breg
));
849 PARAMS ((int *counter
, int reg
, int unsignedp
));
850 static void check_absolute_expr
851 PARAMS ((struct mips_cl_insn
* ip
, expressionS
*));
852 static void load_register
853 PARAMS ((int *, int, expressionS
*, int));
854 static void load_address
855 PARAMS ((int *, int, expressionS
*, int *));
856 static void move_register
857 PARAMS ((int *, int, int));
859 PARAMS ((struct mips_cl_insn
* ip
));
860 static void mips16_macro
861 PARAMS ((struct mips_cl_insn
* ip
));
862 #ifdef LOSING_COMPILER
864 PARAMS ((struct mips_cl_insn
* ip
));
867 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
868 static void mips16_ip
869 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
870 static void mips16_immed
871 PARAMS ((char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
,
872 bfd_boolean
, unsigned long *, bfd_boolean
*, unsigned short *));
873 static bfd_boolean parse_relocation
874 PARAMS ((char **, bfd_reloc_code_real_type
*));
875 static size_t my_getSmallExpression
876 PARAMS ((expressionS
*, bfd_reloc_code_real_type
*, char *));
877 static void my_getExpression
878 PARAMS ((expressionS
*, char *));
880 static int support_64bit_objects
883 static void mips_set_option_string
884 PARAMS ((const char **, const char *));
885 static symbolS
*get_symbol
887 static void mips_align
888 PARAMS ((int to
, int fill
, symbolS
*label
));
891 static void s_change_sec
893 static void s_change_section
897 static void s_float_cons
899 static void s_mips_globl
903 static void s_mipsset
905 static void s_abicalls
909 static void s_cpsetup
911 static void s_cplocal
913 static void s_cprestore
915 static void s_cpreturn
917 static void s_gpvalue
921 static void s_gpdword
927 static void md_obj_begin
929 static void md_obj_end
931 static long get_number
933 static void s_mips_ent
935 static void s_mips_end
937 static void s_mips_frame
939 static void s_mips_mask
941 static void s_mips_stab
943 static void s_mips_weakext
945 static void s_mips_file
947 static void s_mips_loc
949 static bfd_boolean pic_need_relax
950 PARAMS ((symbolS
*, asection
*));
951 static int mips16_extended_frag
952 PARAMS ((fragS
*, asection
*, long));
953 static int relaxed_branch_length (fragS
*, asection
*, int);
954 static int validate_mips_insn
955 PARAMS ((const struct mips_opcode
*));
957 PARAMS ((FILE *, const char *, int *, int *));
959 static int mips_need_elf_addend_fixup
963 /* Table and functions used to map between CPU/ISA names, and
964 ISA levels, and CPU numbers. */
968 const char *name
; /* CPU or ISA name. */
969 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
970 int isa
; /* ISA level. */
971 int cpu
; /* CPU number (default CPU if ISA). */
974 static void mips_set_architecture
975 PARAMS ((const struct mips_cpu_info
*));
976 static void mips_set_tune
977 PARAMS ((const struct mips_cpu_info
*));
978 static bfd_boolean mips_strict_matching_cpu_name_p
979 PARAMS ((const char *, const char *));
980 static bfd_boolean mips_matching_cpu_name_p
981 PARAMS ((const char *, const char *));
982 static const struct mips_cpu_info
*mips_parse_cpu
983 PARAMS ((const char *, const char *));
984 static const struct mips_cpu_info
*mips_cpu_info_from_isa
989 The following pseudo-ops from the Kane and Heinrich MIPS book
990 should be defined here, but are currently unsupported: .alias,
991 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
993 The following pseudo-ops from the Kane and Heinrich MIPS book are
994 specific to the type of debugging information being generated, and
995 should be defined by the object format: .aent, .begin, .bend,
996 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
999 The following pseudo-ops from the Kane and Heinrich MIPS book are
1000 not MIPS CPU specific, but are also not specific to the object file
1001 format. This file is probably the best place to define them, but
1002 they are not currently supported: .asm0, .endr, .lab, .repeat,
1005 static const pseudo_typeS mips_pseudo_table
[] =
1007 /* MIPS specific pseudo-ops. */
1008 {"option", s_option
, 0},
1009 {"set", s_mipsset
, 0},
1010 {"rdata", s_change_sec
, 'r'},
1011 {"sdata", s_change_sec
, 's'},
1012 {"livereg", s_ignore
, 0},
1013 {"abicalls", s_abicalls
, 0},
1014 {"cpload", s_cpload
, 0},
1015 {"cpsetup", s_cpsetup
, 0},
1016 {"cplocal", s_cplocal
, 0},
1017 {"cprestore", s_cprestore
, 0},
1018 {"cpreturn", s_cpreturn
, 0},
1019 {"gpvalue", s_gpvalue
, 0},
1020 {"gpword", s_gpword
, 0},
1021 {"gpdword", s_gpdword
, 0},
1022 {"cpadd", s_cpadd
, 0},
1023 {"insn", s_insn
, 0},
1025 /* Relatively generic pseudo-ops that happen to be used on MIPS
1027 {"asciiz", stringer
, 1},
1028 {"bss", s_change_sec
, 'b'},
1030 {"half", s_cons
, 1},
1031 {"dword", s_cons
, 3},
1032 {"weakext", s_mips_weakext
, 0},
1034 /* These pseudo-ops are defined in read.c, but must be overridden
1035 here for one reason or another. */
1036 {"align", s_align
, 0},
1037 {"byte", s_cons
, 0},
1038 {"data", s_change_sec
, 'd'},
1039 {"double", s_float_cons
, 'd'},
1040 {"float", s_float_cons
, 'f'},
1041 {"globl", s_mips_globl
, 0},
1042 {"global", s_mips_globl
, 0},
1043 {"hword", s_cons
, 1},
1045 {"long", s_cons
, 2},
1046 {"octa", s_cons
, 4},
1047 {"quad", s_cons
, 3},
1048 {"section", s_change_section
, 0},
1049 {"short", s_cons
, 1},
1050 {"single", s_float_cons
, 'f'},
1051 {"stabn", s_mips_stab
, 'n'},
1052 {"text", s_change_sec
, 't'},
1053 {"word", s_cons
, 2},
1055 { "extern", ecoff_directive_extern
, 0},
1060 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1062 /* These pseudo-ops should be defined by the object file format.
1063 However, a.out doesn't support them, so we have versions here. */
1064 {"aent", s_mips_ent
, 1},
1065 {"bgnb", s_ignore
, 0},
1066 {"end", s_mips_end
, 0},
1067 {"endb", s_ignore
, 0},
1068 {"ent", s_mips_ent
, 0},
1069 {"file", s_mips_file
, 0},
1070 {"fmask", s_mips_mask
, 'F'},
1071 {"frame", s_mips_frame
, 0},
1072 {"loc", s_mips_loc
, 0},
1073 {"mask", s_mips_mask
, 'R'},
1074 {"verstamp", s_ignore
, 0},
1078 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
1083 pop_insert (mips_pseudo_table
);
1084 if (! ECOFF_DEBUGGING
)
1085 pop_insert (mips_nonecoff_pseudo_table
);
1088 /* Symbols labelling the current insn. */
1090 struct insn_label_list
1092 struct insn_label_list
*next
;
1096 static struct insn_label_list
*insn_labels
;
1097 static struct insn_label_list
*free_insn_labels
;
1099 static void mips_clear_insn_labels
PARAMS ((void));
1102 mips_clear_insn_labels ()
1104 register struct insn_label_list
**pl
;
1106 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1112 static char *expr_end
;
1114 /* Expressions which appear in instructions. These are set by
1117 static expressionS imm_expr
;
1118 static expressionS offset_expr
;
1120 /* Relocs associated with imm_expr and offset_expr. */
1122 static bfd_reloc_code_real_type imm_reloc
[3]
1123 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1124 static bfd_reloc_code_real_type offset_reloc
[3]
1125 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1127 /* These are set by mips16_ip if an explicit extension is used. */
1129 static bfd_boolean mips16_small
, mips16_ext
;
1132 /* The pdr segment for per procedure frame/regmask info. Not used for
1135 static segT pdr_seg
;
1138 /* The default target format to use. */
1141 mips_target_format ()
1143 switch (OUTPUT_FLAVOR
)
1145 case bfd_target_aout_flavour
:
1146 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1147 case bfd_target_ecoff_flavour
:
1148 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1149 case bfd_target_coff_flavour
:
1151 case bfd_target_elf_flavour
:
1153 /* This is traditional mips. */
1154 return (target_big_endian
1155 ? (HAVE_64BIT_OBJECTS
1156 ? "elf64-tradbigmips"
1158 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1159 : (HAVE_64BIT_OBJECTS
1160 ? "elf64-tradlittlemips"
1162 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1164 return (target_big_endian
1165 ? (HAVE_64BIT_OBJECTS
1168 ? "elf32-nbigmips" : "elf32-bigmips"))
1169 : (HAVE_64BIT_OBJECTS
1170 ? "elf64-littlemips"
1172 ? "elf32-nlittlemips" : "elf32-littlemips")));
1180 /* This function is called once, at assembler startup time. It should
1181 set up all the tables, etc. that the MD part of the assembler will need. */
1186 register const char *retval
= NULL
;
1190 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1191 as_warn (_("Could not set architecture and machine"));
1193 op_hash
= hash_new ();
1195 for (i
= 0; i
< NUMOPCODES
;)
1197 const char *name
= mips_opcodes
[i
].name
;
1199 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1202 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1203 mips_opcodes
[i
].name
, retval
);
1204 /* Probably a memory allocation problem? Give up now. */
1205 as_fatal (_("Broken assembler. No assembly attempted."));
1209 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1211 if (!validate_mips_insn (&mips_opcodes
[i
]))
1216 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1219 mips16_op_hash
= hash_new ();
1222 while (i
< bfd_mips16_num_opcodes
)
1224 const char *name
= mips16_opcodes
[i
].name
;
1226 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1228 as_fatal (_("internal: can't hash `%s': %s"),
1229 mips16_opcodes
[i
].name
, retval
);
1232 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1233 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1234 != mips16_opcodes
[i
].match
))
1236 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1237 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1242 while (i
< bfd_mips16_num_opcodes
1243 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1247 as_fatal (_("Broken assembler. No assembly attempted."));
1249 /* We add all the general register names to the symbol table. This
1250 helps us detect invalid uses of them. */
1251 for (i
= 0; i
< 32; i
++)
1255 sprintf (buf
, "$%d", i
);
1256 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1257 &zero_address_frag
));
1259 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1260 &zero_address_frag
));
1261 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1262 &zero_address_frag
));
1263 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1264 &zero_address_frag
));
1265 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1266 &zero_address_frag
));
1267 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1268 &zero_address_frag
));
1269 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1270 &zero_address_frag
));
1271 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1272 &zero_address_frag
));
1273 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1274 &zero_address_frag
));
1275 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1276 &zero_address_frag
));
1278 /* If we don't add these register names to the symbol table, they
1279 may end up being added as regular symbols by operand(), and then
1280 make it to the object file as undefined in case they're not
1281 regarded as local symbols. They're local in o32, since `$' is a
1282 local symbol prefix, but not in n32 or n64. */
1283 for (i
= 0; i
< 8; i
++)
1287 sprintf (buf
, "$fcc%i", i
);
1288 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1289 &zero_address_frag
));
1292 mips_no_prev_insn (FALSE
);
1295 mips_cprmask
[0] = 0;
1296 mips_cprmask
[1] = 0;
1297 mips_cprmask
[2] = 0;
1298 mips_cprmask
[3] = 0;
1300 /* set the default alignment for the text section (2**2) */
1301 record_alignment (text_section
, 2);
1303 if (USE_GLOBAL_POINTER_OPT
)
1304 bfd_set_gp_size (stdoutput
, g_switch_value
);
1306 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1308 /* On a native system, sections must be aligned to 16 byte
1309 boundaries. When configured for an embedded ELF target, we
1311 if (strcmp (TARGET_OS
, "elf") != 0)
1313 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1314 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1315 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1318 /* Create a .reginfo section for register masks and a .mdebug
1319 section for debugging information. */
1327 subseg
= now_subseg
;
1329 /* The ABI says this section should be loaded so that the
1330 running program can access it. However, we don't load it
1331 if we are configured for an embedded target */
1332 flags
= SEC_READONLY
| SEC_DATA
;
1333 if (strcmp (TARGET_OS
, "elf") != 0)
1334 flags
|= SEC_ALLOC
| SEC_LOAD
;
1336 if (mips_abi
!= N64_ABI
)
1338 sec
= subseg_new (".reginfo", (subsegT
) 0);
1340 bfd_set_section_flags (stdoutput
, sec
, flags
);
1341 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1344 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1349 /* The 64-bit ABI uses a .MIPS.options section rather than
1350 .reginfo section. */
1351 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1352 bfd_set_section_flags (stdoutput
, sec
, flags
);
1353 bfd_set_section_alignment (stdoutput
, sec
, 3);
1356 /* Set up the option header. */
1358 Elf_Internal_Options opthdr
;
1361 opthdr
.kind
= ODK_REGINFO
;
1362 opthdr
.size
= (sizeof (Elf_External_Options
)
1363 + sizeof (Elf64_External_RegInfo
));
1366 f
= frag_more (sizeof (Elf_External_Options
));
1367 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1368 (Elf_External_Options
*) f
);
1370 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1375 if (ECOFF_DEBUGGING
)
1377 sec
= subseg_new (".mdebug", (subsegT
) 0);
1378 (void) bfd_set_section_flags (stdoutput
, sec
,
1379 SEC_HAS_CONTENTS
| SEC_READONLY
);
1380 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1383 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1385 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1386 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1387 SEC_READONLY
| SEC_RELOC
1389 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1393 subseg_set (seg
, subseg
);
1397 if (! ECOFF_DEBUGGING
)
1404 if (! ECOFF_DEBUGGING
)
1412 struct mips_cl_insn insn
;
1413 bfd_reloc_code_real_type unused_reloc
[3]
1414 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1416 imm_expr
.X_op
= O_absent
;
1417 offset_expr
.X_op
= O_absent
;
1418 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1419 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1420 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1421 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1422 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1423 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1425 if (mips_opts
.mips16
)
1426 mips16_ip (str
, &insn
);
1429 mips_ip (str
, &insn
);
1430 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1431 str
, insn
.insn_opcode
));
1436 as_bad ("%s `%s'", insn_error
, str
);
1440 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1442 if (mips_opts
.mips16
)
1443 mips16_macro (&insn
);
1449 if (imm_expr
.X_op
!= O_absent
)
1450 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
);
1451 else if (offset_expr
.X_op
!= O_absent
)
1452 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
);
1454 append_insn (NULL
, &insn
, NULL
, unused_reloc
);
1458 /* Return true if the given relocation might need a matching %lo().
1459 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1460 applied to local symbols. */
1462 static inline bfd_boolean
1463 reloc_needs_lo_p (reloc
)
1464 bfd_reloc_code_real_type reloc
;
1466 return (reloc
== BFD_RELOC_HI16_S
1467 || reloc
== BFD_RELOC_MIPS_GOT16
);
1470 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1473 static inline bfd_boolean
1474 fixup_has_matching_lo_p (fixp
)
1477 return (fixp
->fx_next
!= NULL
1478 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1479 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1480 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1483 /* See whether instruction IP reads register REG. CLASS is the type
1487 insn_uses_reg (ip
, reg
, class)
1488 struct mips_cl_insn
*ip
;
1490 enum mips_regclass
class;
1492 if (class == MIPS16_REG
)
1494 assert (mips_opts
.mips16
);
1495 reg
= mips16_to_32_reg_map
[reg
];
1496 class = MIPS_GR_REG
;
1499 /* Don't report on general register ZERO, since it never changes. */
1500 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1503 if (class == MIPS_FP_REG
)
1505 assert (! mips_opts
.mips16
);
1506 /* If we are called with either $f0 or $f1, we must check $f0.
1507 This is not optimal, because it will introduce an unnecessary
1508 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1509 need to distinguish reading both $f0 and $f1 or just one of
1510 them. Note that we don't have to check the other way,
1511 because there is no instruction that sets both $f0 and $f1
1512 and requires a delay. */
1513 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1514 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1515 == (reg
&~ (unsigned) 1)))
1517 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1518 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1519 == (reg
&~ (unsigned) 1)))
1522 else if (! mips_opts
.mips16
)
1524 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1525 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1527 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1528 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1533 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1534 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1535 & MIPS16OP_MASK_RX
)]
1538 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1539 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1540 & MIPS16OP_MASK_RY
)]
1543 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1544 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1545 & MIPS16OP_MASK_MOVE32Z
)]
1548 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1550 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1552 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1554 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1555 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1556 & MIPS16OP_MASK_REGR32
) == reg
)
1563 /* This function returns true if modifying a register requires a
1567 reg_needs_delay (reg
)
1570 unsigned long prev_pinfo
;
1572 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1573 if (! mips_opts
.noreorder
1574 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1575 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1576 || (! gpr_interlocks
1577 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1579 /* A load from a coprocessor or from memory. All load
1580 delays delay the use of general register rt for one
1581 instruction on the r3000. The r6000 and r4000 use
1583 /* Itbl support may require additional care here. */
1584 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1585 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1592 /* Mark instruction labels in mips16 mode. This permits the linker to
1593 handle them specially, such as generating jalx instructions when
1594 needed. We also make them odd for the duration of the assembly, in
1595 order to generate the right sort of code. We will make them even
1596 in the adjust_symtab routine, while leaving them marked. This is
1597 convenient for the debugger and the disassembler. The linker knows
1598 to make them odd again. */
1601 mips16_mark_labels ()
1603 if (mips_opts
.mips16
)
1605 struct insn_label_list
*l
;
1608 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1611 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1612 S_SET_OTHER (l
->label
, STO_MIPS16
);
1614 val
= S_GET_VALUE (l
->label
);
1616 S_SET_VALUE (l
->label
, val
+ 1);
1621 /* Output an instruction. PLACE is where to put the instruction; if
1622 it is NULL, this uses frag_more to get room. IP is the instruction
1623 information. ADDRESS_EXPR is an operand of the instruction to be
1624 used with RELOC_TYPE. */
1627 append_insn (place
, ip
, address_expr
, reloc_type
)
1629 struct mips_cl_insn
*ip
;
1630 expressionS
*address_expr
;
1631 bfd_reloc_code_real_type
*reloc_type
;
1633 register unsigned long prev_pinfo
, pinfo
;
1637 bfd_boolean force_new_frag
= FALSE
;
1639 /* Mark instruction labels in mips16 mode. */
1640 mips16_mark_labels ();
1642 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1643 pinfo
= ip
->insn_mo
->pinfo
;
1645 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1649 /* If the previous insn required any delay slots, see if we need
1650 to insert a NOP or two. There are eight kinds of possible
1651 hazards, of which an instruction can have at most one type.
1652 (1) a load from memory delay
1653 (2) a load from a coprocessor delay
1654 (3) an unconditional branch delay
1655 (4) a conditional branch delay
1656 (5) a move to coprocessor register delay
1657 (6) a load coprocessor register from memory delay
1658 (7) a coprocessor condition code delay
1659 (8) a HI/LO special register delay
1661 There are a lot of optimizations we could do that we don't.
1662 In particular, we do not, in general, reorder instructions.
1663 If you use gcc with optimization, it will reorder
1664 instructions and generally do much more optimization then we
1665 do here; repeating all that work in the assembler would only
1666 benefit hand written assembly code, and does not seem worth
1669 /* This is how a NOP is emitted. */
1670 #define emit_nop() \
1672 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1673 : md_number_to_chars (frag_more (4), 0, 4))
1675 /* The previous insn might require a delay slot, depending upon
1676 the contents of the current insn. */
1677 if (! mips_opts
.mips16
1678 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1679 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1680 && ! cop_interlocks
)
1681 || (! gpr_interlocks
1682 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1684 /* A load from a coprocessor or from memory. All load
1685 delays delay the use of general register rt for one
1686 instruction on the r3000. The r6000 and r4000 use
1688 /* Itbl support may require additional care here. */
1689 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1690 if (mips_optimize
== 0
1691 || insn_uses_reg (ip
,
1692 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1697 else if (! mips_opts
.mips16
1698 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1699 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1700 && ! cop_interlocks
)
1701 || (mips_opts
.isa
== ISA_MIPS1
1702 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1704 /* A generic coprocessor delay. The previous instruction
1705 modified a coprocessor general or control register. If
1706 it modified a control register, we need to avoid any
1707 coprocessor instruction (this is probably not always
1708 required, but it sometimes is). If it modified a general
1709 register, we avoid using that register.
1711 On the r6000 and r4000 loading a coprocessor register
1712 from memory is interlocked, and does not require a delay.
1714 This case is not handled very well. There is no special
1715 knowledge of CP0 handling, and the coprocessors other
1716 than the floating point unit are not distinguished at
1718 /* Itbl support may require additional care here. FIXME!
1719 Need to modify this to include knowledge about
1720 user specified delays! */
1721 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1723 if (mips_optimize
== 0
1724 || insn_uses_reg (ip
,
1725 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1730 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1732 if (mips_optimize
== 0
1733 || insn_uses_reg (ip
,
1734 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1741 /* We don't know exactly what the previous instruction
1742 does. If the current instruction uses a coprocessor
1743 register, we must insert a NOP. If previous
1744 instruction may set the condition codes, and the
1745 current instruction uses them, we must insert two
1747 /* Itbl support may require additional care here. */
1748 if (mips_optimize
== 0
1749 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1750 && (pinfo
& INSN_READ_COND_CODE
)))
1752 else if (pinfo
& INSN_COP
)
1756 else if (! mips_opts
.mips16
1757 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1758 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1759 && ! cop_interlocks
)
1761 /* The previous instruction sets the coprocessor condition
1762 codes, but does not require a general coprocessor delay
1763 (this means it is a floating point comparison
1764 instruction). If this instruction uses the condition
1765 codes, we need to insert a single NOP. */
1766 /* Itbl support may require additional care here. */
1767 if (mips_optimize
== 0
1768 || (pinfo
& INSN_READ_COND_CODE
))
1772 /* If we're fixing up mfhi/mflo for the r7000 and the
1773 previous insn was an mfhi/mflo and the current insn
1774 reads the register that the mfhi/mflo wrote to, then
1777 else if (mips_7000_hilo_fix
1778 && MF_HILO_INSN (prev_pinfo
)
1779 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1786 /* If we're fixing up mfhi/mflo for the r7000 and the
1787 2nd previous insn was an mfhi/mflo and the current insn
1788 reads the register that the mfhi/mflo wrote to, then
1791 else if (mips_7000_hilo_fix
1792 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1793 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1801 else if (prev_pinfo
& INSN_READ_LO
)
1803 /* The previous instruction reads the LO register; if the
1804 current instruction writes to the LO register, we must
1805 insert two NOPS. Some newer processors have interlocks.
1806 Also the tx39's multiply instructions can be exectuted
1807 immediatly after a read from HI/LO (without the delay),
1808 though the tx39's divide insns still do require the
1810 if (! (hilo_interlocks
1811 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1812 && (mips_optimize
== 0
1813 || (pinfo
& INSN_WRITE_LO
)))
1815 /* Most mips16 branch insns don't have a delay slot.
1816 If a read from LO is immediately followed by a branch
1817 to a write to LO we have a read followed by a write
1818 less than 2 insns away. We assume the target of
1819 a branch might be a write to LO, and insert a nop
1820 between a read and an immediately following branch. */
1821 else if (mips_opts
.mips16
1822 && (mips_optimize
== 0
1823 || (pinfo
& MIPS16_INSN_BRANCH
)))
1826 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1828 /* The previous instruction reads the HI register; if the
1829 current instruction writes to the HI register, we must
1830 insert a NOP. Some newer processors have interlocks.
1831 Also the note tx39's multiply above. */
1832 if (! (hilo_interlocks
1833 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1834 && (mips_optimize
== 0
1835 || (pinfo
& INSN_WRITE_HI
)))
1837 /* Most mips16 branch insns don't have a delay slot.
1838 If a read from HI is immediately followed by a branch
1839 to a write to HI we have a read followed by a write
1840 less than 2 insns away. We assume the target of
1841 a branch might be a write to HI, and insert a nop
1842 between a read and an immediately following branch. */
1843 else if (mips_opts
.mips16
1844 && (mips_optimize
== 0
1845 || (pinfo
& MIPS16_INSN_BRANCH
)))
1849 /* If the previous instruction was in a noreorder section, then
1850 we don't want to insert the nop after all. */
1851 /* Itbl support may require additional care here. */
1852 if (prev_insn_unreordered
)
1855 /* There are two cases which require two intervening
1856 instructions: 1) setting the condition codes using a move to
1857 coprocessor instruction which requires a general coprocessor
1858 delay and then reading the condition codes 2) reading the HI
1859 or LO register and then writing to it (except on processors
1860 which have interlocks). If we are not already emitting a NOP
1861 instruction, we must check for these cases compared to the
1862 instruction previous to the previous instruction. */
1863 if ((! mips_opts
.mips16
1864 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1865 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1866 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1867 && (pinfo
& INSN_READ_COND_CODE
)
1868 && ! cop_interlocks
)
1869 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1870 && (pinfo
& INSN_WRITE_LO
)
1871 && ! (hilo_interlocks
1872 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1873 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1874 && (pinfo
& INSN_WRITE_HI
)
1875 && ! (hilo_interlocks
1876 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1881 if (prev_prev_insn_unreordered
)
1884 if (prev_prev_nop
&& nops
== 0)
1887 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1889 /* We're out of bits in pinfo, so we must resort to string
1890 ops here. Shortcuts are selected based on opcodes being
1891 limited to the VR4122 instruction set. */
1893 const char *pn
= prev_insn
.insn_mo
->name
;
1894 const char *tn
= ip
->insn_mo
->name
;
1895 if (strncmp(pn
, "macc", 4) == 0
1896 || strncmp(pn
, "dmacc", 5) == 0)
1898 /* Errata 21 - [D]DIV[U] after [D]MACC */
1899 if (strstr (tn
, "div"))
1904 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1905 if (pn
[0] == 'd' /* dmacc */
1906 && (strncmp(tn
, "dmult", 5) == 0
1907 || strncmp(tn
, "dmacc", 5) == 0))
1912 /* Errata 24 - MT{LO,HI} after [D]MACC */
1913 if (strcmp (tn
, "mtlo") == 0
1914 || strcmp (tn
, "mthi") == 0)
1920 else if (strncmp(pn
, "dmult", 5) == 0
1921 && (strncmp(tn
, "dmult", 5) == 0
1922 || strncmp(tn
, "dmacc", 5) == 0))
1924 /* Here is the rest of errata 23. */
1927 if (nops
< min_nops
)
1931 /* If we are being given a nop instruction, don't bother with
1932 one of the nops we would otherwise output. This will only
1933 happen when a nop instruction is used with mips_optimize set
1936 && ! mips_opts
.noreorder
1937 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1940 /* Now emit the right number of NOP instructions. */
1941 if (nops
> 0 && ! mips_opts
.noreorder
)
1944 unsigned long old_frag_offset
;
1946 struct insn_label_list
*l
;
1948 old_frag
= frag_now
;
1949 old_frag_offset
= frag_now_fix ();
1951 for (i
= 0; i
< nops
; i
++)
1956 listing_prev_line ();
1957 /* We may be at the start of a variant frag. In case we
1958 are, make sure there is enough space for the frag
1959 after the frags created by listing_prev_line. The
1960 argument to frag_grow here must be at least as large
1961 as the argument to all other calls to frag_grow in
1962 this file. We don't have to worry about being in the
1963 middle of a variant frag, because the variants insert
1964 all needed nop instructions themselves. */
1968 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1972 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1973 symbol_set_frag (l
->label
, frag_now
);
1974 val
= (valueT
) frag_now_fix ();
1975 /* mips16 text labels are stored as odd. */
1976 if (mips_opts
.mips16
)
1978 S_SET_VALUE (l
->label
, val
);
1981 #ifndef NO_ECOFF_DEBUGGING
1982 if (ECOFF_DEBUGGING
)
1983 ecoff_fix_loc (old_frag
, old_frag_offset
);
1986 else if (prev_nop_frag
!= NULL
)
1988 /* We have a frag holding nops we may be able to remove. If
1989 we don't need any nops, we can decrease the size of
1990 prev_nop_frag by the size of one instruction. If we do
1991 need some nops, we count them in prev_nops_required. */
1992 if (prev_nop_frag_since
== 0)
1996 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1997 --prev_nop_frag_holds
;
2000 prev_nop_frag_required
+= nops
;
2004 if (prev_prev_nop
== 0)
2006 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2007 --prev_nop_frag_holds
;
2010 ++prev_nop_frag_required
;
2013 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2014 prev_nop_frag
= NULL
;
2016 ++prev_nop_frag_since
;
2018 /* Sanity check: by the time we reach the second instruction
2019 after prev_nop_frag, we should have used up all the nops
2020 one way or another. */
2021 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2027 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2028 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2029 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2030 && mips_relax_branch
2031 /* Don't try branch relaxation within .set nomacro, or within
2032 .set noat if we use $at for PIC computations. If it turns
2033 out that the branch was out-of-range, we'll get an error. */
2034 && !mips_opts
.warn_about_macros
2035 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2036 && !mips_opts
.mips16
)
2038 f
= frag_var (rs_machine_dependent
,
2039 relaxed_branch_length
2041 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2042 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2044 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2045 pinfo
& INSN_COND_BRANCH_LIKELY
,
2046 pinfo
& INSN_WRITE_GPR_31
,
2048 address_expr
->X_add_symbol
,
2049 address_expr
->X_add_number
,
2051 *reloc_type
= BFD_RELOC_UNUSED
;
2053 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2055 /* We need to set up a variant frag. */
2056 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2057 f
= frag_var (rs_machine_dependent
, 4, 0,
2058 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2059 mips16_small
, mips16_ext
,
2061 & INSN_UNCOND_BRANCH_DELAY
),
2062 (*prev_insn_reloc_type
2063 == BFD_RELOC_MIPS16_JMP
)),
2064 make_expr_symbol (address_expr
), 0, NULL
);
2066 else if (place
!= NULL
)
2068 else if (mips_opts
.mips16
2070 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2072 /* Make sure there is enough room to swap this instruction with
2073 a following jump instruction. */
2079 if (mips_opts
.mips16
2080 && mips_opts
.noreorder
2081 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2082 as_warn (_("extended instruction in delay slot"));
2087 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2088 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2090 if (address_expr
->X_op
== O_constant
)
2094 switch (*reloc_type
)
2097 ip
->insn_opcode
|= address_expr
->X_add_number
;
2100 case BFD_RELOC_MIPS_HIGHEST
:
2101 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2103 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2106 case BFD_RELOC_MIPS_HIGHER
:
2107 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2108 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2111 case BFD_RELOC_HI16_S
:
2112 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2116 case BFD_RELOC_HI16
:
2117 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2120 case BFD_RELOC_LO16
:
2121 case BFD_RELOC_MIPS_GOT_DISP
:
2122 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2125 case BFD_RELOC_MIPS_JMP
:
2126 if ((address_expr
->X_add_number
& 3) != 0)
2127 as_bad (_("jump to misaligned address (0x%lx)"),
2128 (unsigned long) address_expr
->X_add_number
);
2129 if (address_expr
->X_add_number
& ~0xfffffff)
2130 as_bad (_("jump address range overflow (0x%lx)"),
2131 (unsigned long) address_expr
->X_add_number
);
2132 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2135 case BFD_RELOC_MIPS16_JMP
:
2136 if ((address_expr
->X_add_number
& 3) != 0)
2137 as_bad (_("jump to misaligned address (0x%lx)"),
2138 (unsigned long) address_expr
->X_add_number
);
2139 if (address_expr
->X_add_number
& ~0xfffffff)
2140 as_bad (_("jump address range overflow (0x%lx)"),
2141 (unsigned long) address_expr
->X_add_number
);
2143 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2144 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2145 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2148 case BFD_RELOC_16_PCREL_S2
:
2158 /* Don't generate a reloc if we are writing into a variant frag. */
2161 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2163 *reloc_type
== BFD_RELOC_16_PCREL_S2
,
2166 /* These relocations can have an addend that won't fit in
2167 4 octets for 64bit assembly. */
2168 if (HAVE_64BIT_GPRS
&&
2169 (*reloc_type
== BFD_RELOC_16
2170 || *reloc_type
== BFD_RELOC_32
2171 || *reloc_type
== BFD_RELOC_MIPS_JMP
2172 || *reloc_type
== BFD_RELOC_HI16_S
2173 || *reloc_type
== BFD_RELOC_LO16
2174 || *reloc_type
== BFD_RELOC_GPREL16
2175 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2176 || *reloc_type
== BFD_RELOC_GPREL32
2177 || *reloc_type
== BFD_RELOC_64
2178 || *reloc_type
== BFD_RELOC_CTOR
2179 || *reloc_type
== BFD_RELOC_MIPS_SUB
2180 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2181 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2182 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2183 || *reloc_type
== BFD_RELOC_MIPS_REL16
2184 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2185 fixp
[0]->fx_no_overflow
= 1;
2187 if (reloc_needs_lo_p (*reloc_type
))
2189 struct mips_hi_fixup
*hi_fixup
;
2191 /* Reuse the last entry if it already has a matching %lo. */
2192 hi_fixup
= mips_hi_fixup_list
;
2194 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2196 hi_fixup
= ((struct mips_hi_fixup
*)
2197 xmalloc (sizeof (struct mips_hi_fixup
)));
2198 hi_fixup
->next
= mips_hi_fixup_list
;
2199 mips_hi_fixup_list
= hi_fixup
;
2201 hi_fixup
->fixp
= fixp
[0];
2202 hi_fixup
->seg
= now_seg
;
2205 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2207 /* FIXME: This symbol can be one of
2208 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2209 address_expr
->X_op
= O_absent
;
2210 address_expr
->X_add_symbol
= 0;
2211 address_expr
->X_add_number
= 0;
2213 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2214 4, address_expr
, FALSE
,
2217 /* These relocations can have an addend that won't fit in
2218 4 octets for 64bit assembly. */
2219 if (HAVE_64BIT_GPRS
&&
2220 (*reloc_type
== BFD_RELOC_16
2221 || *reloc_type
== BFD_RELOC_32
2222 || *reloc_type
== BFD_RELOC_MIPS_JMP
2223 || *reloc_type
== BFD_RELOC_HI16_S
2224 || *reloc_type
== BFD_RELOC_LO16
2225 || *reloc_type
== BFD_RELOC_GPREL16
2226 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2227 || *reloc_type
== BFD_RELOC_GPREL32
2228 || *reloc_type
== BFD_RELOC_64
2229 || *reloc_type
== BFD_RELOC_CTOR
2230 || *reloc_type
== BFD_RELOC_MIPS_SUB
2231 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2232 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2233 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2234 || *reloc_type
== BFD_RELOC_MIPS_REL16
2235 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2236 fixp
[1]->fx_no_overflow
= 1;
2238 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2240 address_expr
->X_op
= O_absent
;
2241 address_expr
->X_add_symbol
= 0;
2242 address_expr
->X_add_number
= 0;
2244 fixp
[2] = fix_new_exp (frag_now
,
2245 f
- frag_now
->fr_literal
, 4,
2246 address_expr
, FALSE
,
2249 /* These relocations can have an addend that won't fit in
2250 4 octets for 64bit assembly. */
2251 if (HAVE_64BIT_GPRS
&&
2252 (*reloc_type
== BFD_RELOC_16
2253 || *reloc_type
== BFD_RELOC_32
2254 || *reloc_type
== BFD_RELOC_MIPS_JMP
2255 || *reloc_type
== BFD_RELOC_HI16_S
2256 || *reloc_type
== BFD_RELOC_LO16
2257 || *reloc_type
== BFD_RELOC_GPREL16
2258 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2259 || *reloc_type
== BFD_RELOC_GPREL32
2260 || *reloc_type
== BFD_RELOC_64
2261 || *reloc_type
== BFD_RELOC_CTOR
2262 || *reloc_type
== BFD_RELOC_MIPS_SUB
2263 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2264 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2265 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2266 || *reloc_type
== BFD_RELOC_MIPS_REL16
2267 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2268 fixp
[2]->fx_no_overflow
= 1;
2275 if (! mips_opts
.mips16
)
2277 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2279 dwarf2_emit_insn (4);
2282 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2284 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2285 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2287 dwarf2_emit_insn (4);
2294 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2297 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2299 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2303 /* Update the register mask information. */
2304 if (! mips_opts
.mips16
)
2306 if (pinfo
& INSN_WRITE_GPR_D
)
2307 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2308 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2309 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2310 if (pinfo
& INSN_READ_GPR_S
)
2311 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2312 if (pinfo
& INSN_WRITE_GPR_31
)
2313 mips_gprmask
|= 1 << RA
;
2314 if (pinfo
& INSN_WRITE_FPR_D
)
2315 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2316 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2317 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2318 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2319 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2320 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2321 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2322 if (pinfo
& INSN_COP
)
2324 /* We don't keep enough information to sort these cases out.
2325 The itbl support does keep this information however, although
2326 we currently don't support itbl fprmats as part of the cop
2327 instruction. May want to add this support in the future. */
2329 /* Never set the bit for $0, which is always zero. */
2330 mips_gprmask
&= ~1 << 0;
2334 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2335 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2336 & MIPS16OP_MASK_RX
);
2337 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2338 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2339 & MIPS16OP_MASK_RY
);
2340 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2341 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2342 & MIPS16OP_MASK_RZ
);
2343 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2344 mips_gprmask
|= 1 << TREG
;
2345 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2346 mips_gprmask
|= 1 << SP
;
2347 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2348 mips_gprmask
|= 1 << RA
;
2349 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2350 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2351 if (pinfo
& MIPS16_INSN_READ_Z
)
2352 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2353 & MIPS16OP_MASK_MOVE32Z
);
2354 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2355 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2356 & MIPS16OP_MASK_REGR32
);
2359 if (place
== NULL
&& ! mips_opts
.noreorder
)
2361 /* Filling the branch delay slot is more complex. We try to
2362 switch the branch with the previous instruction, which we can
2363 do if the previous instruction does not set up a condition
2364 that the branch tests and if the branch is not itself the
2365 target of any branch. */
2366 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2367 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2369 if (mips_optimize
< 2
2370 /* If we have seen .set volatile or .set nomove, don't
2372 || mips_opts
.nomove
!= 0
2373 /* If we had to emit any NOP instructions, then we
2374 already know we can not swap. */
2376 /* If we don't even know the previous insn, we can not
2378 || ! prev_insn_valid
2379 /* If the previous insn is already in a branch delay
2380 slot, then we can not swap. */
2381 || prev_insn_is_delay_slot
2382 /* If the previous previous insn was in a .set
2383 noreorder, we can't swap. Actually, the MIPS
2384 assembler will swap in this situation. However, gcc
2385 configured -with-gnu-as will generate code like
2391 in which we can not swap the bne and INSN. If gcc is
2392 not configured -with-gnu-as, it does not output the
2393 .set pseudo-ops. We don't have to check
2394 prev_insn_unreordered, because prev_insn_valid will
2395 be 0 in that case. We don't want to use
2396 prev_prev_insn_valid, because we do want to be able
2397 to swap at the start of a function. */
2398 || prev_prev_insn_unreordered
2399 /* If the branch is itself the target of a branch, we
2400 can not swap. We cheat on this; all we check for is
2401 whether there is a label on this instruction. If
2402 there are any branches to anything other than a
2403 label, users must use .set noreorder. */
2404 || insn_labels
!= NULL
2405 /* If the previous instruction is in a variant frag, we
2406 can not do the swap. This does not apply to the
2407 mips16, which uses variant frags for different
2409 || (! mips_opts
.mips16
2410 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2411 /* If the branch reads the condition codes, we don't
2412 even try to swap, because in the sequence
2417 we can not swap, and I don't feel like handling that
2419 || (! mips_opts
.mips16
2420 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2421 && (pinfo
& INSN_READ_COND_CODE
))
2422 /* We can not swap with an instruction that requires a
2423 delay slot, becase the target of the branch might
2424 interfere with that instruction. */
2425 || (! mips_opts
.mips16
2426 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2428 /* Itbl support may require additional care here. */
2429 & (INSN_LOAD_COPROC_DELAY
2430 | INSN_COPROC_MOVE_DELAY
2431 | INSN_WRITE_COND_CODE
)))
2432 || (! (hilo_interlocks
2433 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2437 || (! mips_opts
.mips16
2439 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2440 || (! mips_opts
.mips16
2441 && mips_opts
.isa
== ISA_MIPS1
2442 /* Itbl support may require additional care here. */
2443 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2444 /* We can not swap with a branch instruction. */
2446 & (INSN_UNCOND_BRANCH_DELAY
2447 | INSN_COND_BRANCH_DELAY
2448 | INSN_COND_BRANCH_LIKELY
))
2449 /* We do not swap with a trap instruction, since it
2450 complicates trap handlers to have the trap
2451 instruction be in a delay slot. */
2452 || (prev_pinfo
& INSN_TRAP
)
2453 /* If the branch reads a register that the previous
2454 instruction sets, we can not swap. */
2455 || (! mips_opts
.mips16
2456 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2457 && insn_uses_reg (ip
,
2458 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2461 || (! mips_opts
.mips16
2462 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2463 && insn_uses_reg (ip
,
2464 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2467 || (mips_opts
.mips16
2468 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2469 && insn_uses_reg (ip
,
2470 ((prev_insn
.insn_opcode
2472 & MIPS16OP_MASK_RX
),
2474 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2475 && insn_uses_reg (ip
,
2476 ((prev_insn
.insn_opcode
2478 & MIPS16OP_MASK_RY
),
2480 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2481 && insn_uses_reg (ip
,
2482 ((prev_insn
.insn_opcode
2484 & MIPS16OP_MASK_RZ
),
2486 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2487 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2488 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2489 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2490 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2491 && insn_uses_reg (ip
,
2492 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2495 /* If the branch writes a register that the previous
2496 instruction sets, we can not swap (we know that
2497 branches write only to RD or to $31). */
2498 || (! mips_opts
.mips16
2499 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2500 && (((pinfo
& INSN_WRITE_GPR_D
)
2501 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2502 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2503 || ((pinfo
& INSN_WRITE_GPR_31
)
2504 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2507 || (! mips_opts
.mips16
2508 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2509 && (((pinfo
& INSN_WRITE_GPR_D
)
2510 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2511 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2512 || ((pinfo
& INSN_WRITE_GPR_31
)
2513 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2516 || (mips_opts
.mips16
2517 && (pinfo
& MIPS16_INSN_WRITE_31
)
2518 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2519 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2520 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2522 /* If the branch writes a register that the previous
2523 instruction reads, we can not swap (we know that
2524 branches only write to RD or to $31). */
2525 || (! mips_opts
.mips16
2526 && (pinfo
& INSN_WRITE_GPR_D
)
2527 && insn_uses_reg (&prev_insn
,
2528 ((ip
->insn_opcode
>> OP_SH_RD
)
2531 || (! mips_opts
.mips16
2532 && (pinfo
& INSN_WRITE_GPR_31
)
2533 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2534 || (mips_opts
.mips16
2535 && (pinfo
& MIPS16_INSN_WRITE_31
)
2536 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2537 /* If we are generating embedded PIC code, the branch
2538 might be expanded into a sequence which uses $at, so
2539 we can't swap with an instruction which reads it. */
2540 || (mips_pic
== EMBEDDED_PIC
2541 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2542 /* If the previous previous instruction has a load
2543 delay, and sets a register that the branch reads, we
2545 || (! mips_opts
.mips16
2546 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2547 /* Itbl support may require additional care here. */
2548 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2549 || (! gpr_interlocks
2550 && (prev_prev_insn
.insn_mo
->pinfo
2551 & INSN_LOAD_MEMORY_DELAY
)))
2552 && insn_uses_reg (ip
,
2553 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2556 /* If one instruction sets a condition code and the
2557 other one uses a condition code, we can not swap. */
2558 || ((pinfo
& INSN_READ_COND_CODE
)
2559 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2560 || ((pinfo
& INSN_WRITE_COND_CODE
)
2561 && (prev_pinfo
& INSN_READ_COND_CODE
))
2562 /* If the previous instruction uses the PC, we can not
2564 || (mips_opts
.mips16
2565 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2566 /* If the previous instruction was extended, we can not
2568 || (mips_opts
.mips16
&& prev_insn_extended
)
2569 /* If the previous instruction had a fixup in mips16
2570 mode, we can not swap. This normally means that the
2571 previous instruction was a 4 byte branch anyhow. */
2572 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2573 /* If the previous instruction is a sync, sync.l, or
2574 sync.p, we can not swap. */
2575 || (prev_pinfo
& INSN_SYNC
))
2577 /* We could do even better for unconditional branches to
2578 portions of this object file; we could pick up the
2579 instruction at the destination, put it in the delay
2580 slot, and bump the destination address. */
2582 /* Update the previous insn information. */
2583 prev_prev_insn
= *ip
;
2584 prev_insn
.insn_mo
= &dummy_opcode
;
2588 /* It looks like we can actually do the swap. */
2589 if (! mips_opts
.mips16
)
2594 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2595 memcpy (temp
, prev_f
, 4);
2596 memcpy (prev_f
, f
, 4);
2597 memcpy (f
, temp
, 4);
2598 if (prev_insn_fixp
[0])
2600 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2601 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2603 if (prev_insn_fixp
[1])
2605 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2606 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2608 if (prev_insn_fixp
[2])
2610 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2611 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2613 if (prev_insn_fixp
[0] && HAVE_NEWABI
2614 && prev_insn_frag
!= frag_now
2615 && (prev_insn_fixp
[0]->fx_r_type
2616 == BFD_RELOC_MIPS_GOT_DISP
2617 || (prev_insn_fixp
[0]->fx_r_type
2618 == BFD_RELOC_MIPS_CALL16
)))
2620 /* To avoid confusion in tc_gen_reloc, we must
2621 ensure that this does not become a variant
2623 force_new_frag
= TRUE
;
2627 fixp
[0]->fx_frag
= prev_insn_frag
;
2628 fixp
[0]->fx_where
= prev_insn_where
;
2632 fixp
[1]->fx_frag
= prev_insn_frag
;
2633 fixp
[1]->fx_where
= prev_insn_where
;
2637 fixp
[2]->fx_frag
= prev_insn_frag
;
2638 fixp
[2]->fx_where
= prev_insn_where
;
2646 assert (prev_insn_fixp
[0] == NULL
);
2647 assert (prev_insn_fixp
[1] == NULL
);
2648 assert (prev_insn_fixp
[2] == NULL
);
2649 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2650 memcpy (temp
, prev_f
, 2);
2651 memcpy (prev_f
, f
, 2);
2652 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2654 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2655 memcpy (f
, temp
, 2);
2659 memcpy (f
, f
+ 2, 2);
2660 memcpy (f
+ 2, temp
, 2);
2664 fixp
[0]->fx_frag
= prev_insn_frag
;
2665 fixp
[0]->fx_where
= prev_insn_where
;
2669 fixp
[1]->fx_frag
= prev_insn_frag
;
2670 fixp
[1]->fx_where
= prev_insn_where
;
2674 fixp
[2]->fx_frag
= prev_insn_frag
;
2675 fixp
[2]->fx_where
= prev_insn_where
;
2679 /* Update the previous insn information; leave prev_insn
2681 prev_prev_insn
= *ip
;
2683 prev_insn_is_delay_slot
= 1;
2685 /* If that was an unconditional branch, forget the previous
2686 insn information. */
2687 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2689 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2690 prev_insn
.insn_mo
= &dummy_opcode
;
2693 prev_insn_fixp
[0] = NULL
;
2694 prev_insn_fixp
[1] = NULL
;
2695 prev_insn_fixp
[2] = NULL
;
2696 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2697 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2698 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2699 prev_insn_extended
= 0;
2701 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2703 /* We don't yet optimize a branch likely. What we should do
2704 is look at the target, copy the instruction found there
2705 into the delay slot, and increment the branch to jump to
2706 the next instruction. */
2708 /* Update the previous insn information. */
2709 prev_prev_insn
= *ip
;
2710 prev_insn
.insn_mo
= &dummy_opcode
;
2711 prev_insn_fixp
[0] = NULL
;
2712 prev_insn_fixp
[1] = NULL
;
2713 prev_insn_fixp
[2] = NULL
;
2714 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2715 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2716 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2717 prev_insn_extended
= 0;
2721 /* Update the previous insn information. */
2723 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2725 prev_prev_insn
= prev_insn
;
2728 /* Any time we see a branch, we always fill the delay slot
2729 immediately; since this insn is not a branch, we know it
2730 is not in a delay slot. */
2731 prev_insn_is_delay_slot
= 0;
2733 prev_insn_fixp
[0] = fixp
[0];
2734 prev_insn_fixp
[1] = fixp
[1];
2735 prev_insn_fixp
[2] = fixp
[2];
2736 prev_insn_reloc_type
[0] = reloc_type
[0];
2737 prev_insn_reloc_type
[1] = reloc_type
[1];
2738 prev_insn_reloc_type
[2] = reloc_type
[2];
2739 if (mips_opts
.mips16
)
2740 prev_insn_extended
= (ip
->use_extend
2741 || *reloc_type
> BFD_RELOC_UNUSED
);
2744 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2745 prev_insn_unreordered
= 0;
2746 prev_insn_frag
= frag_now
;
2747 prev_insn_where
= f
- frag_now
->fr_literal
;
2748 prev_insn_valid
= 1;
2750 else if (place
== NULL
)
2752 /* We need to record a bit of information even when we are not
2753 reordering, in order to determine the base address for mips16
2754 PC relative relocs. */
2755 prev_prev_insn
= prev_insn
;
2757 prev_insn_reloc_type
[0] = reloc_type
[0];
2758 prev_insn_reloc_type
[1] = reloc_type
[1];
2759 prev_insn_reloc_type
[2] = reloc_type
[2];
2760 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2761 prev_insn_unreordered
= 1;
2764 /* We just output an insn, so the next one doesn't have a label. */
2765 mips_clear_insn_labels ();
2767 /* We must ensure that the frag to which an instruction that was
2768 moved from a non-variant frag doesn't become a variant frag,
2769 otherwise tc_gen_reloc may get confused. */
2772 frag_wane (frag_now
);
2777 /* This function forgets that there was any previous instruction or
2778 label. If PRESERVE is non-zero, it remembers enough information to
2779 know whether nops are needed before a noreorder section. */
2782 mips_no_prev_insn (preserve
)
2787 prev_insn
.insn_mo
= &dummy_opcode
;
2788 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2789 prev_nop_frag
= NULL
;
2790 prev_nop_frag_holds
= 0;
2791 prev_nop_frag_required
= 0;
2792 prev_nop_frag_since
= 0;
2794 prev_insn_valid
= 0;
2795 prev_insn_is_delay_slot
= 0;
2796 prev_insn_unreordered
= 0;
2797 prev_insn_extended
= 0;
2798 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2799 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2800 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2801 prev_prev_insn_unreordered
= 0;
2802 mips_clear_insn_labels ();
2805 /* This function must be called whenever we turn on noreorder or emit
2806 something other than instructions. It inserts any NOPS which might
2807 be needed by the previous instruction, and clears the information
2808 kept for the previous instructions. The INSNS parameter is true if
2809 instructions are to follow. */
2812 mips_emit_delays (insns
)
2815 if (! mips_opts
.noreorder
)
2820 if ((! mips_opts
.mips16
2821 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2822 && (! cop_interlocks
2823 && (prev_insn
.insn_mo
->pinfo
2824 & (INSN_LOAD_COPROC_DELAY
2825 | INSN_COPROC_MOVE_DELAY
2826 | INSN_WRITE_COND_CODE
))))
2827 || (! hilo_interlocks
2828 && (prev_insn
.insn_mo
->pinfo
2831 || (! mips_opts
.mips16
2833 && (prev_insn
.insn_mo
->pinfo
2834 & INSN_LOAD_MEMORY_DELAY
))
2835 || (! mips_opts
.mips16
2836 && mips_opts
.isa
== ISA_MIPS1
2837 && (prev_insn
.insn_mo
->pinfo
2838 & INSN_COPROC_MEMORY_DELAY
)))
2840 /* Itbl support may require additional care here. */
2842 if ((! mips_opts
.mips16
2843 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2844 && (! cop_interlocks
2845 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2846 || (! hilo_interlocks
2847 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2848 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2851 if (prev_insn_unreordered
)
2854 else if ((! mips_opts
.mips16
2855 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2856 && (! cop_interlocks
2857 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2858 || (! hilo_interlocks
2859 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2860 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2862 /* Itbl support may require additional care here. */
2863 if (! prev_prev_insn_unreordered
)
2867 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2870 const char *pn
= prev_insn
.insn_mo
->name
;
2871 if (strncmp(pn
, "macc", 4) == 0
2872 || strncmp(pn
, "dmacc", 5) == 0
2873 || strncmp(pn
, "dmult", 5) == 0)
2877 if (nops
< min_nops
)
2883 struct insn_label_list
*l
;
2887 /* Record the frag which holds the nop instructions, so
2888 that we can remove them if we don't need them. */
2889 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2890 prev_nop_frag
= frag_now
;
2891 prev_nop_frag_holds
= nops
;
2892 prev_nop_frag_required
= 0;
2893 prev_nop_frag_since
= 0;
2896 for (; nops
> 0; --nops
)
2901 /* Move on to a new frag, so that it is safe to simply
2902 decrease the size of prev_nop_frag. */
2903 frag_wane (frag_now
);
2907 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2911 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2912 symbol_set_frag (l
->label
, frag_now
);
2913 val
= (valueT
) frag_now_fix ();
2914 /* mips16 text labels are stored as odd. */
2915 if (mips_opts
.mips16
)
2917 S_SET_VALUE (l
->label
, val
);
2922 /* Mark instruction labels in mips16 mode. */
2924 mips16_mark_labels ();
2926 mips_no_prev_insn (insns
);
2929 /* Build an instruction created by a macro expansion. This is passed
2930 a pointer to the count of instructions created so far, an
2931 expression, the name of the instruction to build, an operand format
2932 string, and corresponding arguments. */
2936 macro_build (char *place
,
2944 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2953 struct mips_cl_insn insn
;
2954 bfd_reloc_code_real_type r
[3];
2958 va_start (args
, fmt
);
2964 * If the macro is about to expand into a second instruction,
2965 * print a warning if needed. We need to pass ip as a parameter
2966 * to generate a better warning message here...
2968 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2969 as_warn (_("Macro instruction expanded into multiple instructions"));
2972 * If the macro is about to expand into a second instruction,
2973 * and it is in a delay slot, print a warning.
2977 && mips_opts
.noreorder
2978 && (prev_prev_insn
.insn_mo
->pinfo
2979 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2980 | INSN_COND_BRANCH_LIKELY
)) != 0)
2981 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2984 ++*counter
; /* bump instruction counter */
2986 if (mips_opts
.mips16
)
2988 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2993 r
[0] = BFD_RELOC_UNUSED
;
2994 r
[1] = BFD_RELOC_UNUSED
;
2995 r
[2] = BFD_RELOC_UNUSED
;
2996 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2997 assert (insn
.insn_mo
);
2998 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3000 /* Search until we get a match for NAME. */
3003 /* It is assumed here that macros will never generate
3004 MDMX or MIPS-3D instructions. */
3005 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3006 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3007 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3009 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3011 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3015 assert (insn
.insn_mo
->name
);
3016 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3019 insn
.insn_opcode
= insn
.insn_mo
->match
;
3035 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3039 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3044 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3050 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3055 int tmp
= va_arg (args
, int);
3057 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3058 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3064 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3071 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3075 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3079 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3083 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3087 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3094 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3100 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3101 assert (*r
== BFD_RELOC_GPREL16
3102 || *r
== BFD_RELOC_MIPS_LITERAL
3103 || *r
== BFD_RELOC_MIPS_HIGHER
3104 || *r
== BFD_RELOC_HI16_S
3105 || *r
== BFD_RELOC_LO16
3106 || *r
== BFD_RELOC_MIPS_GOT16
3107 || *r
== BFD_RELOC_MIPS_CALL16
3108 || *r
== BFD_RELOC_MIPS_GOT_DISP
3109 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3110 || *r
== BFD_RELOC_MIPS_GOT_OFST
3111 || *r
== BFD_RELOC_MIPS_GOT_LO16
3112 || *r
== BFD_RELOC_MIPS_CALL_LO16
3113 || (ep
->X_op
== O_subtract
3114 && *r
== BFD_RELOC_PCREL_LO16
));
3118 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3120 && (ep
->X_op
== O_constant
3121 || (ep
->X_op
== O_symbol
3122 && (*r
== BFD_RELOC_MIPS_HIGHEST
3123 || *r
== BFD_RELOC_HI16_S
3124 || *r
== BFD_RELOC_HI16
3125 || *r
== BFD_RELOC_GPREL16
3126 || *r
== BFD_RELOC_MIPS_GOT_HI16
3127 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3128 || (ep
->X_op
== O_subtract
3129 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3133 assert (ep
!= NULL
);
3135 * This allows macro() to pass an immediate expression for
3136 * creating short branches without creating a symbol.
3137 * Note that the expression still might come from the assembly
3138 * input, in which case the value is not checked for range nor
3139 * is a relocation entry generated (yuck).
3141 if (ep
->X_op
== O_constant
)
3143 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3147 *r
= BFD_RELOC_16_PCREL_S2
;
3151 assert (ep
!= NULL
);
3152 *r
= BFD_RELOC_MIPS_JMP
;
3156 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3165 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3167 append_insn (place
, &insn
, ep
, r
);
3171 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3173 int *counter ATTRIBUTE_UNUSED
;
3179 struct mips_cl_insn insn
;
3180 bfd_reloc_code_real_type r
[3]
3181 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3183 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3184 assert (insn
.insn_mo
);
3185 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3187 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3188 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3191 assert (insn
.insn_mo
->name
);
3192 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3195 insn
.insn_opcode
= insn
.insn_mo
->match
;
3196 insn
.use_extend
= FALSE
;
3215 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3220 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3224 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3228 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3238 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3245 regno
= va_arg (args
, int);
3246 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3247 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3268 assert (ep
!= NULL
);
3270 if (ep
->X_op
!= O_constant
)
3271 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3274 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3275 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3278 *r
= BFD_RELOC_UNUSED
;
3284 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3291 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3293 append_insn (place
, &insn
, ep
, r
);
3297 * Generate a "jalr" instruction with a relocation hint to the called
3298 * function. This occurs in NewABI PIC code.
3301 macro_build_jalr (icnt
, ep
)
3312 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3315 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3316 0, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3320 * Generate a "lui" instruction.
3323 macro_build_lui (place
, counter
, ep
, regnum
)
3329 expressionS high_expr
;
3330 struct mips_cl_insn insn
;
3331 bfd_reloc_code_real_type r
[3]
3332 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3333 const char *name
= "lui";
3334 const char *fmt
= "t,u";
3336 assert (! mips_opts
.mips16
);
3342 high_expr
.X_op
= O_constant
;
3343 high_expr
.X_add_number
= ep
->X_add_number
;
3346 if (high_expr
.X_op
== O_constant
)
3348 /* we can compute the instruction now without a relocation entry */
3349 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3351 *r
= BFD_RELOC_UNUSED
;
3355 assert (ep
->X_op
== O_symbol
);
3356 /* _gp_disp is a special case, used from s_cpload. */
3357 assert (mips_pic
== NO_PIC
3359 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3360 *r
= BFD_RELOC_HI16_S
;
3364 * If the macro is about to expand into a second instruction,
3365 * print a warning if needed. We need to pass ip as a parameter
3366 * to generate a better warning message here...
3368 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3369 as_warn (_("Macro instruction expanded into multiple instructions"));
3372 ++*counter
; /* bump instruction counter */
3374 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3375 assert (insn
.insn_mo
);
3376 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3377 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3379 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3380 if (*r
== BFD_RELOC_UNUSED
)
3382 insn
.insn_opcode
|= high_expr
.X_add_number
;
3383 append_insn (place
, &insn
, NULL
, r
);
3386 append_insn (place
, &insn
, &high_expr
, r
);
3389 /* Generate a sequence of instructions to do a load or store from a constant
3390 offset off of a base register (breg) into/from a target register (treg),
3391 using AT if necessary. */
3393 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3400 assert (ep
->X_op
== O_constant
);
3402 /* Right now, this routine can only handle signed 32-bit contants. */
3403 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3404 as_warn (_("operand overflow"));
3406 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3408 /* Signed 16-bit offset will fit in the op. Easy! */
3409 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3410 (int) BFD_RELOC_LO16
, breg
);
3414 /* 32-bit offset, need multiple instructions and AT, like:
3415 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3416 addu $tempreg,$tempreg,$breg
3417 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3418 to handle the complete offset. */
3419 macro_build_lui (place
, counter
, ep
, AT
);
3422 macro_build (place
, counter
, (expressionS
*) NULL
,
3423 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
3424 ? "add" : "addu" : "daddu",
3425 "d,v,t", AT
, AT
, breg
);
3428 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3429 (int) BFD_RELOC_LO16
, AT
);
3432 as_warn (_("Macro used $at after \".set noat\""));
3437 * Generates code to set the $at register to true (one)
3438 * if reg is less than the immediate expression.
3441 set_at (counter
, reg
, unsignedp
)
3446 if (imm_expr
.X_op
== O_constant
3447 && imm_expr
.X_add_number
>= -0x8000
3448 && imm_expr
.X_add_number
< 0x8000)
3449 macro_build ((char *) NULL
, counter
, &imm_expr
,
3450 unsignedp
? "sltiu" : "slti",
3451 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3454 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3455 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3456 unsignedp
? "sltu" : "slt",
3457 "d,v,t", AT
, reg
, AT
);
3461 /* Warn if an expression is not a constant. */
3464 check_absolute_expr (ip
, ex
)
3465 struct mips_cl_insn
*ip
;
3468 if (ex
->X_op
== O_big
)
3469 as_bad (_("unsupported large constant"));
3470 else if (ex
->X_op
!= O_constant
)
3471 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3474 /* Count the leading zeroes by performing a binary chop. This is a
3475 bulky bit of source, but performance is a LOT better for the
3476 majority of values than a simple loop to count the bits:
3477 for (lcnt = 0; (lcnt < 32); lcnt++)
3478 if ((v) & (1 << (31 - lcnt)))
3480 However it is not code size friendly, and the gain will drop a bit
3481 on certain cached systems.
3483 #define COUNT_TOP_ZEROES(v) \
3484 (((v) & ~0xffff) == 0 \
3485 ? ((v) & ~0xff) == 0 \
3486 ? ((v) & ~0xf) == 0 \
3487 ? ((v) & ~0x3) == 0 \
3488 ? ((v) & ~0x1) == 0 \
3493 : ((v) & ~0x7) == 0 \
3496 : ((v) & ~0x3f) == 0 \
3497 ? ((v) & ~0x1f) == 0 \
3500 : ((v) & ~0x7f) == 0 \
3503 : ((v) & ~0xfff) == 0 \
3504 ? ((v) & ~0x3ff) == 0 \
3505 ? ((v) & ~0x1ff) == 0 \
3508 : ((v) & ~0x7ff) == 0 \
3511 : ((v) & ~0x3fff) == 0 \
3512 ? ((v) & ~0x1fff) == 0 \
3515 : ((v) & ~0x7fff) == 0 \
3518 : ((v) & ~0xffffff) == 0 \
3519 ? ((v) & ~0xfffff) == 0 \
3520 ? ((v) & ~0x3ffff) == 0 \
3521 ? ((v) & ~0x1ffff) == 0 \
3524 : ((v) & ~0x7ffff) == 0 \
3527 : ((v) & ~0x3fffff) == 0 \
3528 ? ((v) & ~0x1fffff) == 0 \
3531 : ((v) & ~0x7fffff) == 0 \
3534 : ((v) & ~0xfffffff) == 0 \
3535 ? ((v) & ~0x3ffffff) == 0 \
3536 ? ((v) & ~0x1ffffff) == 0 \
3539 : ((v) & ~0x7ffffff) == 0 \
3542 : ((v) & ~0x3fffffff) == 0 \
3543 ? ((v) & ~0x1fffffff) == 0 \
3546 : ((v) & ~0x7fffffff) == 0 \
3551 * This routine generates the least number of instructions neccessary to load
3552 * an absolute expression value into a register.
3555 load_register (counter
, reg
, ep
, dbl
)
3562 expressionS hi32
, lo32
;
3564 if (ep
->X_op
!= O_big
)
3566 assert (ep
->X_op
== O_constant
);
3567 if (ep
->X_add_number
< 0x8000
3568 && (ep
->X_add_number
>= 0
3569 || (ep
->X_add_number
>= -0x8000
3572 || sizeof (ep
->X_add_number
) > 4))))
3574 /* We can handle 16 bit signed values with an addiu to
3575 $zero. No need to ever use daddiu here, since $zero and
3576 the result are always correct in 32 bit mode. */
3577 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3578 (int) BFD_RELOC_LO16
);
3581 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3583 /* We can handle 16 bit unsigned values with an ori to
3585 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3586 (int) BFD_RELOC_LO16
);
3589 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3592 || sizeof (ep
->X_add_number
) > 4
3593 || (ep
->X_add_number
& 0x80000000) == 0))
3594 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3595 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3598 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3599 == ~ (offsetT
) 0xffffffff)))
3601 /* 32 bit values require an lui. */
3602 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3603 (int) BFD_RELOC_HI16
);
3604 if ((ep
->X_add_number
& 0xffff) != 0)
3605 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3606 (int) BFD_RELOC_LO16
);
3611 /* The value is larger than 32 bits. */
3613 if (HAVE_32BIT_GPRS
)
3615 as_bad (_("Number (0x%lx) larger than 32 bits"),
3616 (unsigned long) ep
->X_add_number
);
3617 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3618 (int) BFD_RELOC_LO16
);
3622 if (ep
->X_op
!= O_big
)
3625 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3626 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3627 hi32
.X_add_number
&= 0xffffffff;
3629 lo32
.X_add_number
&= 0xffffffff;
3633 assert (ep
->X_add_number
> 2);
3634 if (ep
->X_add_number
== 3)
3635 generic_bignum
[3] = 0;
3636 else if (ep
->X_add_number
> 4)
3637 as_bad (_("Number larger than 64 bits"));
3638 lo32
.X_op
= O_constant
;
3639 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3640 hi32
.X_op
= O_constant
;
3641 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3644 if (hi32
.X_add_number
== 0)
3649 unsigned long hi
, lo
;
3651 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3653 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3655 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3656 reg
, 0, (int) BFD_RELOC_LO16
);
3659 if (lo32
.X_add_number
& 0x80000000)
3661 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3662 (int) BFD_RELOC_HI16
);
3663 if (lo32
.X_add_number
& 0xffff)
3664 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3665 reg
, reg
, (int) BFD_RELOC_LO16
);
3670 /* Check for 16bit shifted constant. We know that hi32 is
3671 non-zero, so start the mask on the first bit of the hi32
3676 unsigned long himask
, lomask
;
3680 himask
= 0xffff >> (32 - shift
);
3681 lomask
= (0xffff << shift
) & 0xffffffff;
3685 himask
= 0xffff << (shift
- 32);
3688 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3689 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3693 tmp
.X_op
= O_constant
;
3695 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3696 | (lo32
.X_add_number
>> shift
));
3698 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3699 macro_build ((char *) NULL
, counter
, &tmp
,
3700 "ori", "t,r,i", reg
, 0,
3701 (int) BFD_RELOC_LO16
);
3702 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3703 (shift
>= 32) ? "dsll32" : "dsll",
3705 (shift
>= 32) ? shift
- 32 : shift
);
3710 while (shift
<= (64 - 16));
3712 /* Find the bit number of the lowest one bit, and store the
3713 shifted value in hi/lo. */
3714 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3715 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3719 while ((lo
& 1) == 0)
3724 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3730 while ((hi
& 1) == 0)
3739 /* Optimize if the shifted value is a (power of 2) - 1. */
3740 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3741 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3743 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3748 /* This instruction will set the register to be all
3750 tmp
.X_op
= O_constant
;
3751 tmp
.X_add_number
= (offsetT
) -1;
3752 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3753 reg
, 0, (int) BFD_RELOC_LO16
);
3757 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3758 (bit
>= 32) ? "dsll32" : "dsll",
3760 (bit
>= 32) ? bit
- 32 : bit
);
3762 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3763 (shift
>= 32) ? "dsrl32" : "dsrl",
3765 (shift
>= 32) ? shift
- 32 : shift
);
3770 /* Sign extend hi32 before calling load_register, because we can
3771 generally get better code when we load a sign extended value. */
3772 if ((hi32
.X_add_number
& 0x80000000) != 0)
3773 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3774 load_register (counter
, reg
, &hi32
, 0);
3777 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3781 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3782 "dsll32", "d,w,<", reg
, freg
, 0);
3790 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3792 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3793 (int) BFD_RELOC_HI16
);
3794 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3795 "dsrl32", "d,w,<", reg
, reg
, 0);
3801 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3802 "d,w,<", reg
, freg
, 16);
3806 mid16
.X_add_number
>>= 16;
3807 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3808 freg
, (int) BFD_RELOC_LO16
);
3809 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3810 "d,w,<", reg
, reg
, 16);
3813 if ((lo32
.X_add_number
& 0xffff) != 0)
3814 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3815 (int) BFD_RELOC_LO16
);
3818 /* Load an address into a register. */
3821 load_address (counter
, reg
, ep
, used_at
)
3829 if (ep
->X_op
!= O_constant
3830 && ep
->X_op
!= O_symbol
)
3832 as_bad (_("expression too complex"));
3833 ep
->X_op
= O_constant
;
3836 if (ep
->X_op
== O_constant
)
3838 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3842 if (mips_pic
== NO_PIC
)
3844 /* If this is a reference to a GP relative symbol, we want
3845 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3847 lui $reg,<sym> (BFD_RELOC_HI16_S)
3848 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3849 If we have an addend, we always use the latter form.
3851 With 64bit address space and a usable $at we want
3852 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3853 lui $at,<sym> (BFD_RELOC_HI16_S)
3854 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3855 daddiu $at,<sym> (BFD_RELOC_LO16)
3859 If $at is already in use, we use a path which is suboptimal
3860 on superscalar processors.
3861 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3862 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3864 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3866 daddiu $reg,<sym> (BFD_RELOC_LO16)
3868 if (HAVE_64BIT_ADDRESSES
)
3870 /* We don't do GP optimization for now because RELAX_ENCODE can't
3871 hold the data for such large chunks. */
3873 if (*used_at
== 0 && ! mips_opts
.noat
)
3875 macro_build (p
, counter
, ep
, "lui", "t,u",
3876 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3877 macro_build (p
, counter
, ep
, "lui", "t,u",
3878 AT
, (int) BFD_RELOC_HI16_S
);
3879 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3880 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3881 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3882 AT
, AT
, (int) BFD_RELOC_LO16
);
3883 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3884 "d,w,<", reg
, reg
, 0);
3885 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3886 "d,v,t", reg
, reg
, AT
);
3891 macro_build (p
, counter
, ep
, "lui", "t,u",
3892 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3893 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3894 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3895 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3896 "d,w,<", reg
, reg
, 16);
3897 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3898 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3899 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3900 "d,w,<", reg
, reg
, 16);
3901 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3902 reg
, reg
, (int) BFD_RELOC_LO16
);
3907 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3908 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3911 macro_build ((char *) NULL
, counter
, ep
,
3912 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
3913 ? "addi" : "addiu" : "daddiu", "t,r,j",
3914 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3915 p
= frag_var (rs_machine_dependent
, 8, 0,
3916 RELAX_ENCODE (4, 8, 0, 4, 0,
3917 mips_opts
.warn_about_macros
),
3918 ep
->X_add_symbol
, 0, NULL
);
3920 macro_build_lui (p
, counter
, ep
, reg
);
3923 macro_build (p
, counter
, ep
,
3924 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
3925 ? "addi" : "addiu" : "daddiu",
3926 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3929 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3933 /* If this is a reference to an external symbol, we want
3934 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3936 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3938 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3939 If there is a constant, it must be added in after.
3941 If we have NewABI, we want
3942 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3943 unless we're referencing a global symbol with a non-zero
3944 offset, in which case cst must be added separately. */
3949 if (ep
->X_add_number
)
3951 frag_now
->tc_frag_data
.tc_fr_offset
=
3952 ex
.X_add_number
= ep
->X_add_number
;
3953 ep
->X_add_number
= 0;
3954 macro_build ((char *) NULL
, counter
, ep
,
3955 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3956 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3957 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3958 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3959 ex
.X_op
= O_constant
;
3960 macro_build ((char *) NULL
, counter
, &ex
,
3961 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
3962 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3963 p
= frag_var (rs_machine_dependent
, 8, 0,
3964 RELAX_ENCODE (8, 4, 0, 0, 0,
3965 mips_opts
.warn_about_macros
),
3966 ep
->X_add_symbol
, 0, (char *) NULL
);
3967 ep
->X_add_number
= ex
.X_add_number
;
3970 macro_build (p
, counter
, ep
,
3971 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3972 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3976 /* To avoid confusion in tc_gen_reloc, we must ensure
3977 that this does not become a variant frag. */
3978 frag_wane (frag_now
);
3984 ex
.X_add_number
= ep
->X_add_number
;
3985 ep
->X_add_number
= 0;
3987 macro_build ((char *) NULL
, counter
, ep
,
3988 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3989 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3990 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3991 p
= frag_var (rs_machine_dependent
, 4, 0,
3992 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3993 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3994 macro_build (p
, counter
, ep
,
3995 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3996 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3998 if (ex
.X_add_number
!= 0)
4000 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4001 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4002 ex
.X_op
= O_constant
;
4003 macro_build ((char *) NULL
, counter
, &ex
,
4004 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4005 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4009 else if (mips_pic
== SVR4_PIC
)
4014 /* This is the large GOT case. If this is a reference to an
4015 external symbol, we want
4016 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4018 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4020 Otherwise, for a reference to a local symbol in old ABI, we want
4021 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4023 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4024 If there is a constant, it must be added in after.
4026 In the NewABI, for local symbols, with or without offsets, we want:
4027 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4028 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4034 frag_now
->tc_frag_data
.tc_fr_offset
=
4035 ex
.X_add_number
= ep
->X_add_number
;
4036 ep
->X_add_number
= 0;
4037 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
4038 (int) BFD_RELOC_MIPS_GOT_HI16
);
4039 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4040 HAVE_32BIT_ADDRESSES
? "add" : "daddu", "d,v,t", reg
,
4041 reg
, mips_gp_register
);
4042 macro_build ((char *) NULL
, counter
, ep
,
4043 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4044 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
4045 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4046 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4047 else if (ex
.X_add_number
)
4049 ex
.X_op
= O_constant
;
4050 macro_build ((char *) NULL
, counter
, &ex
,
4051 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
4052 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4055 ep
->X_add_number
= ex
.X_add_number
;
4056 p
= frag_var (rs_machine_dependent
, 8, 0,
4057 RELAX_ENCODE (ex
.X_add_number
? 16 : 12, 8, 0, 4, 0,
4058 mips_opts
.warn_about_macros
),
4059 ep
->X_add_symbol
, 0, (char *) NULL
);
4060 macro_build (p
, counter
, ep
,
4061 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
4062 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4063 macro_build (p
+ 4, counter
, ep
,
4064 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu", "t,r,j",
4065 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
4069 ex
.X_add_number
= ep
->X_add_number
;
4070 ep
->X_add_number
= 0;
4071 if (reg_needs_delay (mips_gp_register
))
4076 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
4077 (int) BFD_RELOC_MIPS_GOT_HI16
);
4078 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4079 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
4080 reg
, mips_gp_register
);
4081 macro_build ((char *) NULL
, counter
, ep
,
4082 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4083 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
4084 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4085 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
4086 mips_opts
.warn_about_macros
),
4087 ep
->X_add_symbol
, 0, NULL
);
4090 /* We need a nop before loading from $gp. This special
4091 check is required because the lui which starts the main
4092 instruction stream does not refer to $gp, and so will not
4093 insert the nop which may be required. */
4094 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4097 macro_build (p
, counter
, ep
,
4098 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
4099 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4101 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4103 macro_build (p
, counter
, ep
,
4104 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4105 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4107 if (ex
.X_add_number
!= 0)
4109 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4110 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4111 ex
.X_op
= O_constant
;
4112 macro_build ((char *) NULL
, counter
, &ex
,
4113 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4114 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4118 else if (mips_pic
== EMBEDDED_PIC
)
4121 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4123 macro_build ((char *) NULL
, counter
, ep
,
4124 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4125 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
4131 /* Move the contents of register SOURCE into register DEST. */
4134 move_register (counter
, dest
, source
)
4139 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4140 HAVE_32BIT_GPRS
? "addu" : "daddu",
4141 "d,v,t", dest
, source
, 0);
4146 * This routine implements the seemingly endless macro or synthesized
4147 * instructions and addressing modes in the mips assembly language. Many
4148 * of these macros are simple and are similar to each other. These could
4149 * probably be handled by some kind of table or grammer aproach instead of
4150 * this verbose method. Others are not simple macros but are more like
4151 * optimizing code generation.
4152 * One interesting optimization is when several store macros appear
4153 * consecutivly that would load AT with the upper half of the same address.
4154 * The ensuing load upper instructions are ommited. This implies some kind
4155 * of global optimization. We currently only optimize within a single macro.
4156 * For many of the load and store macros if the address is specified as a
4157 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4158 * first load register 'at' with zero and use it as the base register. The
4159 * mips assembler simply uses register $zero. Just one tiny optimization
4164 struct mips_cl_insn
*ip
;
4166 register int treg
, sreg
, dreg
, breg
;
4182 bfd_reloc_code_real_type r
;
4183 int hold_mips_optimize
;
4185 assert (! mips_opts
.mips16
);
4187 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4188 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4189 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4190 mask
= ip
->insn_mo
->mask
;
4192 expr1
.X_op
= O_constant
;
4193 expr1
.X_op_symbol
= NULL
;
4194 expr1
.X_add_symbol
= NULL
;
4195 expr1
.X_add_number
= 1;
4197 /* Umatched fixups should not be put in the same frag as a relaxable
4198 macro. For example, suppose we have:
4202 addiu $4,$4,%lo(l1) # 3
4204 If instructions 1 and 2 were put in the same frag, md_frob_file would
4205 move the fixup for #1 after the fixups for the "unrelaxed" version of
4206 #2. This would confuse tc_gen_reloc, which expects the relocations
4207 for #2 to be the last for that frag.
4209 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4210 it assumes that they belong to a relaxable macro. We mustn't put
4211 other uses of such relocations into a variant frag.
4213 To avoid both problems, finish the current frag it contains a
4214 %reloc() operator. The macro then goes into a new frag. */
4215 if (prev_reloc_op_frag
== frag_now
)
4217 frag_wane (frag_now
);
4231 mips_emit_delays (TRUE
);
4232 ++mips_opts
.noreorder
;
4233 mips_any_noreorder
= 1;
4235 expr1
.X_add_number
= 8;
4236 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4238 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4241 move_register (&icnt
, dreg
, sreg
);
4242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4243 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4245 --mips_opts
.noreorder
;
4266 if (imm_expr
.X_op
== O_constant
4267 && imm_expr
.X_add_number
>= -0x8000
4268 && imm_expr
.X_add_number
< 0x8000)
4270 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4271 (int) BFD_RELOC_LO16
);
4274 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4275 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4295 if (imm_expr
.X_op
== O_constant
4296 && imm_expr
.X_add_number
>= 0
4297 && imm_expr
.X_add_number
< 0x10000)
4299 if (mask
!= M_NOR_I
)
4300 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4301 sreg
, (int) BFD_RELOC_LO16
);
4304 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4305 treg
, sreg
, (int) BFD_RELOC_LO16
);
4306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4307 "d,v,t", treg
, treg
, 0);
4312 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4313 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4331 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4333 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4337 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4338 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4346 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4347 likely
? "bgezl" : "bgez", "s,p", sreg
);
4352 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4353 likely
? "blezl" : "blez", "s,p", treg
);
4356 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4358 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4359 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4365 /* check for > max integer */
4366 maxnum
= 0x7fffffff;
4367 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4374 if (imm_expr
.X_op
== O_constant
4375 && imm_expr
.X_add_number
>= maxnum
4376 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4379 /* result is always false */
4383 as_warn (_("Branch %s is always false (nop)"),
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4391 as_warn (_("Branch likely %s is always false"),
4393 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4398 if (imm_expr
.X_op
!= O_constant
)
4399 as_bad (_("Unsupported large constant"));
4400 ++imm_expr
.X_add_number
;
4404 if (mask
== M_BGEL_I
)
4406 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4408 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4409 likely
? "bgezl" : "bgez", "s,p", sreg
);
4412 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4414 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4415 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4418 maxnum
= 0x7fffffff;
4419 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4426 maxnum
= - maxnum
- 1;
4427 if (imm_expr
.X_op
== O_constant
4428 && imm_expr
.X_add_number
<= maxnum
4429 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4432 /* result is always true */
4433 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4434 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4437 set_at (&icnt
, sreg
, 0);
4438 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4439 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4449 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4450 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4454 "d,v,t", AT
, sreg
, treg
);
4455 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4456 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4464 && imm_expr
.X_op
== O_constant
4465 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4467 if (imm_expr
.X_op
!= O_constant
)
4468 as_bad (_("Unsupported large constant"));
4469 ++imm_expr
.X_add_number
;
4473 if (mask
== M_BGEUL_I
)
4475 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4477 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4479 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4480 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4483 set_at (&icnt
, sreg
, 1);
4484 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4485 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4493 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4494 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4499 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4500 likely
? "bltzl" : "bltz", "s,p", treg
);
4503 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4506 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4514 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4515 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4521 "d,v,t", AT
, treg
, sreg
);
4522 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4523 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4532 likely
? "blezl" : "blez", "s,p", sreg
);
4537 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4538 likely
? "bgezl" : "bgez", "s,p", treg
);
4541 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4543 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4544 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4550 maxnum
= 0x7fffffff;
4551 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4558 if (imm_expr
.X_op
== O_constant
4559 && imm_expr
.X_add_number
>= maxnum
4560 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4562 if (imm_expr
.X_op
!= O_constant
)
4563 as_bad (_("Unsupported large constant"));
4564 ++imm_expr
.X_add_number
;
4568 if (mask
== M_BLTL_I
)
4570 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4572 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4573 likely
? "bltzl" : "bltz", "s,p", sreg
);
4576 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4579 likely
? "blezl" : "blez", "s,p", sreg
);
4582 set_at (&icnt
, sreg
, 0);
4583 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4584 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4592 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4593 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4598 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4599 "d,v,t", AT
, treg
, sreg
);
4600 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4601 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4609 && imm_expr
.X_op
== O_constant
4610 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4612 if (imm_expr
.X_op
!= O_constant
)
4613 as_bad (_("Unsupported large constant"));
4614 ++imm_expr
.X_add_number
;
4618 if (mask
== M_BLTUL_I
)
4620 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4622 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4624 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4625 likely
? "beql" : "beq",
4629 set_at (&icnt
, sreg
, 1);
4630 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4631 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4639 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4640 likely
? "bltzl" : "bltz", "s,p", sreg
);
4645 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4646 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4649 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4651 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4652 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4662 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4663 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4666 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4669 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4670 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4685 as_warn (_("Divide by zero."));
4687 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4690 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4695 mips_emit_delays (TRUE
);
4696 ++mips_opts
.noreorder
;
4697 mips_any_noreorder
= 1;
4700 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4701 "s,t,q", treg
, 0, 7);
4702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4703 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4707 expr1
.X_add_number
= 8;
4708 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4709 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4710 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4711 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4714 expr1
.X_add_number
= -1;
4715 macro_build ((char *) NULL
, &icnt
, &expr1
,
4716 dbl
? "daddiu" : "addiu",
4717 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4718 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4719 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4722 expr1
.X_add_number
= 1;
4723 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4724 (int) BFD_RELOC_LO16
);
4725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4726 "d,w,<", AT
, AT
, 31);
4730 expr1
.X_add_number
= 0x80000000;
4731 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4732 (int) BFD_RELOC_HI16
);
4736 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4737 "s,t,q", sreg
, AT
, 6);
4738 /* We want to close the noreorder block as soon as possible, so
4739 that later insns are available for delay slot filling. */
4740 --mips_opts
.noreorder
;
4744 expr1
.X_add_number
= 8;
4745 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4746 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4749 /* We want to close the noreorder block as soon as possible, so
4750 that later insns are available for delay slot filling. */
4751 --mips_opts
.noreorder
;
4753 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4795 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4797 as_warn (_("Divide by zero."));
4799 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4802 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4806 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4808 if (strcmp (s2
, "mflo") == 0)
4809 move_register (&icnt
, dreg
, sreg
);
4811 move_register (&icnt
, dreg
, 0);
4814 if (imm_expr
.X_op
== O_constant
4815 && imm_expr
.X_add_number
== -1
4816 && s
[strlen (s
) - 1] != 'u')
4818 if (strcmp (s2
, "mflo") == 0)
4820 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4821 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4824 move_register (&icnt
, dreg
, 0);
4828 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4831 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4850 mips_emit_delays (TRUE
);
4851 ++mips_opts
.noreorder
;
4852 mips_any_noreorder
= 1;
4855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4856 "s,t,q", treg
, 0, 7);
4857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4859 /* We want to close the noreorder block as soon as possible, so
4860 that later insns are available for delay slot filling. */
4861 --mips_opts
.noreorder
;
4865 expr1
.X_add_number
= 8;
4866 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4867 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4870 /* We want to close the noreorder block as soon as possible, so
4871 that later insns are available for delay slot filling. */
4872 --mips_opts
.noreorder
;
4873 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4876 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4882 /* Load the address of a symbol into a register. If breg is not
4883 zero, we then add a base register to it. */
4885 if (dbl
&& HAVE_32BIT_GPRS
)
4886 as_warn (_("dla used to load 32-bit register"));
4888 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4889 as_warn (_("la used to load 64-bit address"));
4891 if (offset_expr
.X_op
== O_constant
4892 && offset_expr
.X_add_number
>= -0x8000
4893 && offset_expr
.X_add_number
< 0x8000)
4895 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4896 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" :
4897 HAVE_NEWABI
? "addi" : "addiu",
4898 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4913 /* When generating embedded PIC code, we permit expressions of
4916 la $treg,foo-bar($breg)
4917 where bar is an address in the current section. These are used
4918 when getting the addresses of functions. We don't permit
4919 X_add_number to be non-zero, because if the symbol is
4920 external the relaxing code needs to know that any addend is
4921 purely the offset to X_op_symbol. */
4922 if (mips_pic
== EMBEDDED_PIC
4923 && offset_expr
.X_op
== O_subtract
4924 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4925 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4926 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4928 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4931 && (offset_expr
.X_add_number
== 0
4932 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4938 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4939 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4943 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4944 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4945 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4946 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4947 "d,v,t", tempreg
, tempreg
, breg
);
4949 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4950 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4951 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4957 if (offset_expr
.X_op
!= O_symbol
4958 && offset_expr
.X_op
!= O_constant
)
4960 as_bad (_("expression too complex"));
4961 offset_expr
.X_op
= O_constant
;
4964 if (offset_expr
.X_op
== O_constant
)
4965 load_register (&icnt
, tempreg
, &offset_expr
,
4966 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4967 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4968 : HAVE_64BIT_ADDRESSES
));
4969 else if (mips_pic
== NO_PIC
)
4971 /* If this is a reference to a GP relative symbol, we want
4972 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4974 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4975 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4976 If we have a constant, we need two instructions anyhow,
4977 so we may as well always use the latter form.
4979 With 64bit address space and a usable $at we want
4980 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4981 lui $at,<sym> (BFD_RELOC_HI16_S)
4982 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4983 daddiu $at,<sym> (BFD_RELOC_LO16)
4985 daddu $tempreg,$tempreg,$at
4987 If $at is already in use, we use a path which is suboptimal
4988 on superscalar processors.
4989 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4990 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4992 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4994 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4997 if (HAVE_64BIT_ADDRESSES
)
4999 /* We don't do GP optimization for now because RELAX_ENCODE can't
5000 hold the data for such large chunks. */
5002 if (used_at
== 0 && ! mips_opts
.noat
)
5004 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5005 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5006 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5007 AT
, (int) BFD_RELOC_HI16_S
);
5008 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5009 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5010 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5011 AT
, AT
, (int) BFD_RELOC_LO16
);
5012 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5013 "d,w,<", tempreg
, tempreg
, 0);
5014 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5015 "d,v,t", tempreg
, tempreg
, AT
);
5020 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5021 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5022 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5023 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5024 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
5025 tempreg
, tempreg
, 16);
5026 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5027 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5028 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
5029 tempreg
, tempreg
, 16);
5030 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5031 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5036 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5037 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5040 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5041 HAVE_NEWABI
? "addi" : "addiu",
5042 "t,r,j", tempreg
, mips_gp_register
,
5043 (int) BFD_RELOC_GPREL16
);
5044 p
= frag_var (rs_machine_dependent
, 8, 0,
5045 RELAX_ENCODE (4, 8, 0, 4, 0,
5046 mips_opts
.warn_about_macros
),
5047 offset_expr
.X_add_symbol
, 0, NULL
);
5049 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5052 macro_build (p
, &icnt
, &offset_expr
,
5053 HAVE_NEWABI
? "addi" : "addiu",
5054 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5057 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5059 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5061 /* If this is a reference to an external symbol, and there
5062 is no constant, we want
5063 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5064 or if tempreg is PIC_CALL_REG
5065 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5066 For a local symbol, we want
5067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5069 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5071 If we have a small constant, and this is a reference to
5072 an external symbol, we want
5073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5075 addiu $tempreg,$tempreg,<constant>
5076 For a local symbol, we want the same instruction
5077 sequence, but we output a BFD_RELOC_LO16 reloc on the
5080 If we have a large constant, and this is a reference to
5081 an external symbol, we want
5082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5083 lui $at,<hiconstant>
5084 addiu $at,$at,<loconstant>
5085 addu $tempreg,$tempreg,$at
5086 For a local symbol, we want the same instruction
5087 sequence, but we output a BFD_RELOC_LO16 reloc on the
5091 expr1
.X_add_number
= offset_expr
.X_add_number
;
5092 offset_expr
.X_add_number
= 0;
5094 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5095 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5096 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5097 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5098 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
5099 if (expr1
.X_add_number
== 0)
5108 /* We're going to put in an addu instruction using
5109 tempreg, so we may as well insert the nop right
5111 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5115 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
5116 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
5118 ? mips_opts
.warn_about_macros
5120 offset_expr
.X_add_symbol
, 0, NULL
);
5123 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5126 macro_build (p
, &icnt
, &expr1
,
5127 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5128 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5129 /* FIXME: If breg == 0, and the next instruction uses
5130 $tempreg, then if this variant case is used an extra
5131 nop will be generated. */
5133 else if (expr1
.X_add_number
>= -0x8000
5134 && expr1
.X_add_number
< 0x8000)
5136 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5138 macro_build ((char *) NULL
, &icnt
, &expr1
,
5139 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5140 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5141 frag_var (rs_machine_dependent
, 0, 0,
5142 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5143 offset_expr
.X_add_symbol
, 0, NULL
);
5149 /* If we are going to add in a base register, and the
5150 target register and the base register are the same,
5151 then we are using AT as a temporary register. Since
5152 we want to load the constant into AT, we add our
5153 current AT (from the global offset table) and the
5154 register into the register now, and pretend we were
5155 not using a base register. */
5160 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5163 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5164 "d,v,t", treg
, AT
, breg
);
5170 /* Set mips_optimize around the lui instruction to avoid
5171 inserting an unnecessary nop after the lw. */
5172 hold_mips_optimize
= mips_optimize
;
5174 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5175 mips_optimize
= hold_mips_optimize
;
5177 macro_build ((char *) NULL
, &icnt
, &expr1
,
5178 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5179 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5181 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5182 "d,v,t", tempreg
, tempreg
, AT
);
5183 frag_var (rs_machine_dependent
, 0, 0,
5184 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5185 offset_expr
.X_add_symbol
, 0, NULL
);
5189 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5192 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5195 /* If this is a reference to an external, and there is no
5196 constant, or local symbol (*), with or without a
5198 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5199 or if tempreg is PIC_CALL_REG
5200 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5202 If we have a small constant, and this is a reference to
5203 an external symbol, we want
5204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5205 addiu $tempreg,$tempreg,<constant>
5207 If we have a large constant, and this is a reference to
5208 an external symbol, we want
5209 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5210 lui $at,<hiconstant>
5211 addiu $at,$at,<loconstant>
5212 addu $tempreg,$tempreg,$at
5214 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5215 local symbols, even though it introduces an additional
5219 if (offset_expr
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5220 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5221 if (offset_expr
.X_add_number
)
5223 frag_now
->tc_frag_data
.tc_fr_offset
=
5224 expr1
.X_add_number
= offset_expr
.X_add_number
;
5225 offset_expr
.X_add_number
= 0;
5227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5228 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5229 "t,o(b)", tempreg
, lw_reloc_type
,
5232 if (expr1
.X_add_number
>= -0x8000
5233 && expr1
.X_add_number
< 0x8000)
5235 macro_build ((char *) NULL
, &icnt
, &expr1
,
5236 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5237 "t,r,j", tempreg
, tempreg
,
5238 (int) BFD_RELOC_LO16
);
5239 p
= frag_var (rs_machine_dependent
, 4, 0,
5240 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
5241 offset_expr
.X_add_symbol
, 0, NULL
);
5243 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
))
5247 /* If we are going to add in a base register, and the
5248 target register and the base register are the same,
5249 then we are using AT as a temporary register. Since
5250 we want to load the constant into AT, we add our
5251 current AT (from the global offset table) and the
5252 register into the register now, and pretend we were
5253 not using a base register. */
5258 assert (tempreg
== AT
);
5259 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5260 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5261 "d,v,t", treg
, AT
, breg
);
5266 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
5267 macro_build ((char *) NULL
, &icnt
, &expr1
,
5268 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5269 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5270 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5271 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5272 "d,v,t", dreg
, dreg
, AT
);
5274 p
= frag_var (rs_machine_dependent
, 4 + adj
, 0,
5275 RELAX_ENCODE (16 + adj
, 4 + adj
,
5277 offset_expr
.X_add_symbol
, 0, NULL
);
5282 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5284 offset_expr
.X_add_number
= expr1
.X_add_number
;
5286 macro_build (p
, &icnt
, &offset_expr
,
5287 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5288 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_DISP
,
5292 macro_build (p
+ 4, &icnt
, (expressionS
*) NULL
,
5293 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5294 "d,v,t", treg
, tempreg
, breg
);
5301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5302 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5303 "t,o(b)", tempreg
, lw_reloc_type
,
5305 if (lw_reloc_type
!= BFD_RELOC_MIPS_GOT_DISP
)
5306 p
= frag_var (rs_machine_dependent
, 0, 0,
5307 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5308 offset_expr
.X_add_symbol
, 0, NULL
);
5313 /* To avoid confusion in tc_gen_reloc, we must ensure
5314 that this does not become a variant frag. */
5315 frag_wane (frag_now
);
5319 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5323 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5324 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5325 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5327 /* This is the large GOT case. If this is a reference to an
5328 external symbol, and there is no constant, we want
5329 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5330 addu $tempreg,$tempreg,$gp
5331 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5332 or if tempreg is PIC_CALL_REG
5333 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5334 addu $tempreg,$tempreg,$gp
5335 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5336 For a local symbol, we want
5337 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5339 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5341 If we have a small constant, and this is a reference to
5342 an external symbol, we want
5343 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5344 addu $tempreg,$tempreg,$gp
5345 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5347 addiu $tempreg,$tempreg,<constant>
5348 For a local symbol, we want
5349 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5351 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5353 If we have a large constant, and this is a reference to
5354 an external symbol, we want
5355 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5356 addu $tempreg,$tempreg,$gp
5357 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5358 lui $at,<hiconstant>
5359 addiu $at,$at,<loconstant>
5360 addu $tempreg,$tempreg,$at
5361 For a local symbol, we want
5362 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5363 lui $at,<hiconstant>
5364 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5365 addu $tempreg,$tempreg,$at
5368 expr1
.X_add_number
= offset_expr
.X_add_number
;
5369 offset_expr
.X_add_number
= 0;
5371 if (reg_needs_delay (mips_gp_register
))
5375 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5377 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5378 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5380 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5381 tempreg
, lui_reloc_type
);
5382 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5383 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5384 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5385 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5386 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5387 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5388 if (expr1
.X_add_number
== 0)
5396 /* We're going to put in an addu instruction using
5397 tempreg, so we may as well insert the nop right
5399 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5404 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5405 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5408 ? mips_opts
.warn_about_macros
5410 offset_expr
.X_add_symbol
, 0, NULL
);
5412 else if (expr1
.X_add_number
>= -0x8000
5413 && expr1
.X_add_number
< 0x8000)
5415 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5417 macro_build ((char *) NULL
, &icnt
, &expr1
,
5418 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5419 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5421 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5422 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5424 ? mips_opts
.warn_about_macros
5426 offset_expr
.X_add_symbol
, 0, NULL
);
5432 /* If we are going to add in a base register, and the
5433 target register and the base register are the same,
5434 then we are using AT as a temporary register. Since
5435 we want to load the constant into AT, we add our
5436 current AT (from the global offset table) and the
5437 register into the register now, and pretend we were
5438 not using a base register. */
5446 assert (tempreg
== AT
);
5447 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5450 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5451 "d,v,t", treg
, AT
, breg
);
5456 /* Set mips_optimize around the lui instruction to avoid
5457 inserting an unnecessary nop after the lw. */
5458 hold_mips_optimize
= mips_optimize
;
5460 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5461 mips_optimize
= hold_mips_optimize
;
5463 macro_build ((char *) NULL
, &icnt
, &expr1
,
5464 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5465 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5467 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5468 "d,v,t", dreg
, dreg
, AT
);
5470 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5471 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5474 ? mips_opts
.warn_about_macros
5476 offset_expr
.X_add_symbol
, 0, NULL
);
5483 /* This is needed because this instruction uses $gp, but
5484 the first instruction on the main stream does not. */
5485 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5489 macro_build (p
, &icnt
, &offset_expr
,
5490 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5495 if (expr1
.X_add_number
>= -0x8000
5496 && expr1
.X_add_number
< 0x8000)
5498 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5500 macro_build (p
, &icnt
, &expr1
,
5501 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5502 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5503 /* FIXME: If add_number is 0, and there was no base
5504 register, the external symbol case ended with a load,
5505 so if the symbol turns out to not be external, and
5506 the next instruction uses tempreg, an unnecessary nop
5507 will be inserted. */
5513 /* We must add in the base register now, as in the
5514 external symbol case. */
5515 assert (tempreg
== AT
);
5516 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5518 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5519 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5520 "d,v,t", treg
, AT
, breg
);
5523 /* We set breg to 0 because we have arranged to add
5524 it in in both cases. */
5528 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5530 macro_build (p
, &icnt
, &expr1
,
5531 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5532 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5534 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5535 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5536 "d,v,t", tempreg
, tempreg
, AT
);
5540 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5543 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5544 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5547 /* This is the large GOT case. If this is a reference to an
5548 external symbol, and there is no constant, we want
5549 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5550 add $tempreg,$tempreg,$gp
5551 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5552 or if tempreg is PIC_CALL_REG
5553 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5554 add $tempreg,$tempreg,$gp
5555 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5557 If we have a small constant, and this is a reference to
5558 an external symbol, we want
5559 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5560 add $tempreg,$tempreg,$gp
5561 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5562 addi $tempreg,$tempreg,<constant>
5564 If we have a large constant, and this is a reference to
5565 an external symbol, we want
5566 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5567 addu $tempreg,$tempreg,$gp
5568 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5569 lui $at,<hiconstant>
5570 addi $at,$at,<loconstant>
5571 add $tempreg,$tempreg,$at
5573 If we have NewABI, and we know it's a local symbol, we want
5574 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5575 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5576 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5580 frag_now
->tc_frag_data
.tc_fr_offset
=
5581 expr1
.X_add_number
= offset_expr
.X_add_number
;
5582 offset_expr
.X_add_number
= 0;
5584 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5586 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5587 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5589 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5590 tempreg
, lui_reloc_type
);
5591 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5592 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5593 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5594 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5595 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5596 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5598 if (expr1
.X_add_number
== 0)
5600 p
= frag_var (rs_machine_dependent
, 8, 0,
5601 RELAX_ENCODE (12, 8, 0, 4, 0,
5602 mips_opts
.warn_about_macros
),
5603 offset_expr
.X_add_symbol
, 0, NULL
);
5605 else if (expr1
.X_add_number
>= -0x8000
5606 && expr1
.X_add_number
< 0x8000)
5608 macro_build ((char *) NULL
, &icnt
, &expr1
,
5609 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5610 "t,r,j", tempreg
, tempreg
,
5611 (int) BFD_RELOC_LO16
);
5612 p
= frag_var (rs_machine_dependent
, 8, 0,
5613 RELAX_ENCODE (16, 8, 0, 4, 0,
5614 mips_opts
.warn_about_macros
),
5615 offset_expr
.X_add_symbol
, 0, NULL
);
5617 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
))
5621 /* If we are going to add in a base register, and the
5622 target register and the base register are the same,
5623 then we are using AT as a temporary register. Since
5624 we want to load the constant into AT, we add our
5625 current AT (from the global offset table) and the
5626 register into the register now, and pretend we were
5627 not using a base register. */
5632 assert (tempreg
== AT
);
5633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5634 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5635 "d,v,t", treg
, AT
, breg
);
5640 /* Set mips_optimize around the lui instruction to avoid
5641 inserting an unnecessary nop after the lw. */
5642 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
5643 macro_build ((char *) NULL
, &icnt
, &expr1
,
5644 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5645 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5647 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5648 "d,v,t", dreg
, dreg
, AT
);
5650 p
= frag_var (rs_machine_dependent
, 8 + adj
, 0,
5651 RELAX_ENCODE (24 + adj
, 8 + adj
,
5654 ? mips_opts
.warn_about_macros
5656 offset_expr
.X_add_symbol
, 0, NULL
);
5661 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5663 offset_expr
.X_add_number
= expr1
.X_add_number
;
5664 macro_build (p
, &icnt
, &offset_expr
,
5665 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5667 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5668 macro_build (p
+ 4, &icnt
, &offset_expr
,
5669 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu", "t,r,j",
5670 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
5673 macro_build (p
+ 8, &icnt
, (expressionS
*) NULL
,
5674 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5675 "d,v,t", treg
, tempreg
, breg
);
5680 else if (mips_pic
== EMBEDDED_PIC
)
5683 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5685 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5686 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5687 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5696 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5697 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" :
5698 HAVE_NEWABI
? "add" : "addu";
5700 s
= HAVE_64BIT_ADDRESSES
? "daddu" : HAVE_NEWABI
? "add" : "addu";
5702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5703 "d,v,t", treg
, tempreg
, breg
);
5712 /* The j instruction may not be used in PIC code, since it
5713 requires an absolute address. We convert it to a b
5715 if (mips_pic
== NO_PIC
)
5716 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5718 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5721 /* The jal instructions must be handled as macros because when
5722 generating PIC code they expand to multi-instruction
5723 sequences. Normally they are simple instructions. */
5728 if (mips_pic
== NO_PIC
5729 || mips_pic
== EMBEDDED_PIC
)
5730 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5732 else if (mips_pic
== SVR4_PIC
)
5734 if (sreg
!= PIC_CALL_REG
)
5735 as_warn (_("MIPS PIC call to register other than $25"));
5737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5741 if (mips_cprestore_offset
< 0)
5742 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5745 if (! mips_frame_reg_valid
)
5747 as_warn (_("No .frame pseudo-op used in PIC code"));
5748 /* Quiet this warning. */
5749 mips_frame_reg_valid
= 1;
5751 if (! mips_cprestore_valid
)
5753 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5754 /* Quiet this warning. */
5755 mips_cprestore_valid
= 1;
5757 expr1
.X_add_number
= mips_cprestore_offset
;
5758 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5759 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5760 mips_gp_register
, mips_frame_reg
);
5770 if (mips_pic
== NO_PIC
)
5771 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5772 else if (mips_pic
== SVR4_PIC
)
5776 /* If this is a reference to an external symbol, and we are
5777 using a small GOT, we want
5778 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5782 lw $gp,cprestore($sp)
5783 The cprestore value is set using the .cprestore
5784 pseudo-op. If we are using a big GOT, we want
5785 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5787 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5791 lw $gp,cprestore($sp)
5792 If the symbol is not external, we want
5793 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5795 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5798 lw $gp,cprestore($sp)
5800 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5801 sequences above, minus nops, unless the symbol is local,
5802 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5809 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5810 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5811 "t,o(b)", PIC_CALL_REG
,
5812 (int) BFD_RELOC_MIPS_CALL16
,
5814 frag_var (rs_machine_dependent
, 0, 0,
5815 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5816 offset_expr
.X_add_symbol
, 0, NULL
);
5821 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5822 "t,u", PIC_CALL_REG
,
5823 (int) BFD_RELOC_MIPS_CALL_HI16
);
5824 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5825 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
5826 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5828 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5829 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5830 "t,o(b)", PIC_CALL_REG
,
5831 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5832 p
= frag_var (rs_machine_dependent
, 8, 0,
5833 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5834 offset_expr
.X_add_symbol
, 0, NULL
);
5835 macro_build (p
, &icnt
, &offset_expr
,
5836 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5837 tempreg
, (int) BFD_RELOC_MIPS_GOT_PAGE
,
5839 macro_build (p
+ 4, &icnt
, &offset_expr
,
5840 HAVE_32BIT_ADDRESSES
? "addi" : "daddiu",
5841 "t,r,j", tempreg
, tempreg
,
5842 (int) BFD_RELOC_MIPS_GOT_OFST
);
5845 macro_build_jalr (icnt
, &offset_expr
);
5852 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5853 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5854 "t,o(b)", PIC_CALL_REG
,
5855 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5856 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5858 p
= frag_var (rs_machine_dependent
, 4, 0,
5859 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5860 offset_expr
.X_add_symbol
, 0, NULL
);
5866 if (reg_needs_delay (mips_gp_register
))
5870 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5871 "t,u", PIC_CALL_REG
,
5872 (int) BFD_RELOC_MIPS_CALL_HI16
);
5873 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5874 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5875 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5877 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5878 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5879 "t,o(b)", PIC_CALL_REG
,
5880 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5881 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5883 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5884 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5886 offset_expr
.X_add_symbol
, 0, NULL
);
5889 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5892 macro_build (p
, &icnt
, &offset_expr
,
5893 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5894 "t,o(b)", PIC_CALL_REG
,
5895 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5897 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5900 macro_build (p
, &icnt
, &offset_expr
,
5901 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5902 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5903 (int) BFD_RELOC_LO16
);
5904 macro_build_jalr (icnt
, &offset_expr
);
5906 if (mips_cprestore_offset
< 0)
5907 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5910 if (! mips_frame_reg_valid
)
5912 as_warn (_("No .frame pseudo-op used in PIC code"));
5913 /* Quiet this warning. */
5914 mips_frame_reg_valid
= 1;
5916 if (! mips_cprestore_valid
)
5918 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5919 /* Quiet this warning. */
5920 mips_cprestore_valid
= 1;
5922 if (mips_opts
.noreorder
)
5923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5925 expr1
.X_add_number
= mips_cprestore_offset
;
5926 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5927 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5928 mips_gp_register
, mips_frame_reg
);
5932 else if (mips_pic
== EMBEDDED_PIC
)
5934 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5935 /* The linker may expand the call to a longer sequence which
5936 uses $at, so we must break rather than return. */
5961 /* Itbl support may require additional care here. */
5966 /* Itbl support may require additional care here. */
5971 /* Itbl support may require additional care here. */
5976 /* Itbl support may require additional care here. */
5988 if (mips_arch
== CPU_R4650
)
5990 as_bad (_("opcode not supported on this processor"));
5994 /* Itbl support may require additional care here. */
5999 /* Itbl support may require additional care here. */
6004 /* Itbl support may require additional care here. */
6024 if (breg
== treg
|| coproc
|| lr
)
6046 /* Itbl support may require additional care here. */
6051 /* Itbl support may require additional care here. */
6056 /* Itbl support may require additional care here. */
6061 /* Itbl support may require additional care here. */
6077 if (mips_arch
== CPU_R4650
)
6079 as_bad (_("opcode not supported on this processor"));
6084 /* Itbl support may require additional care here. */
6088 /* Itbl support may require additional care here. */
6093 /* Itbl support may require additional care here. */
6105 /* Itbl support may require additional care here. */
6106 if (mask
== M_LWC1_AB
6107 || mask
== M_SWC1_AB
6108 || mask
== M_LDC1_AB
6109 || mask
== M_SDC1_AB
6118 /* For embedded PIC, we allow loads where the offset is calculated
6119 by subtracting a symbol in the current segment from an unknown
6120 symbol, relative to a base register, e.g.:
6121 <op> $treg, <sym>-<localsym>($breg)
6122 This is used by the compiler for switch statements. */
6123 if (mips_pic
== EMBEDDED_PIC
6124 && offset_expr
.X_op
== O_subtract
6125 && (symbol_constant_p (offset_expr
.X_op_symbol
)
6126 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
6127 : (symbol_equated_p (offset_expr
.X_op_symbol
)
6129 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
6133 && (offset_expr
.X_add_number
== 0
6134 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
6136 /* For this case, we output the instructions:
6137 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
6138 addiu $tempreg,$tempreg,$breg
6139 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
6140 If the relocation would fit entirely in 16 bits, it would be
6142 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
6143 instead, but that seems quite difficult. */
6144 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6145 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
6146 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6147 ((bfd_arch_bits_per_address (stdoutput
) == 32
6148 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6149 ? HAVE_NEWABI
? "add" : "addu" : "daddu"),
6150 "d,v,t", tempreg
, tempreg
, breg
);
6151 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6152 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
6158 if (offset_expr
.X_op
!= O_constant
6159 && offset_expr
.X_op
!= O_symbol
)
6161 as_bad (_("expression too complex"));
6162 offset_expr
.X_op
= O_constant
;
6165 /* A constant expression in PIC code can be handled just as it
6166 is in non PIC code. */
6167 if (mips_pic
== NO_PIC
6168 || offset_expr
.X_op
== O_constant
)
6172 /* If this is a reference to a GP relative symbol, and there
6173 is no base register, we want
6174 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6175 Otherwise, if there is no base register, we want
6176 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6177 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6178 If we have a constant, we need two instructions anyhow,
6179 so we always use the latter form.
6181 If we have a base register, and this is a reference to a
6182 GP relative symbol, we want
6183 addu $tempreg,$breg,$gp
6184 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6186 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6187 addu $tempreg,$tempreg,$breg
6188 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6189 With a constant we always use the latter case.
6191 With 64bit address space and no base register and $at usable,
6193 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6194 lui $at,<sym> (BFD_RELOC_HI16_S)
6195 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6198 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6199 If we have a base register, we want
6200 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6201 lui $at,<sym> (BFD_RELOC_HI16_S)
6202 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6206 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6208 Without $at we can't generate the optimal path for superscalar
6209 processors here since this would require two temporary registers.
6210 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6211 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6213 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6215 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6216 If we have a base register, we want
6217 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6218 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6220 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6222 daddu $tempreg,$tempreg,$breg
6223 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6225 If we have 64-bit addresses, as an optimization, for
6226 addresses which are 32-bit constants (e.g. kseg0/kseg1
6227 addresses) we fall back to the 32-bit address generation
6228 mechanism since it is more efficient. Note that due to
6229 the signed offset used by memory operations, the 32-bit
6230 range is shifted down by 32768 here. This code should
6231 probably attempt to generate 64-bit constants more
6232 efficiently in general.
6234 As an extension for architectures with 64-bit registers,
6235 we don't truncate 64-bit addresses given as literal
6236 constants down to 32 bits, to support existing practice
6237 in the mips64 Linux (the kernel), that compiles source
6238 files with -mabi=64, assembling them as o32 or n32 (with
6239 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6240 the whole kernel is loaded into a memory region that is
6241 addressible with sign-extended 32-bit addresses, it is
6242 wasteful to compute the upper 32 bits of every
6243 non-literal address, that takes more space and time.
6244 Some day this should probably be implemented as an
6245 assembler option, such that the kernel doesn't have to
6246 use such ugly hacks, even though it will still have to
6247 end up converting the binary to ELF32 for a number of
6248 platforms whose boot loaders don't support ELF64
6250 if ((offset_expr
.X_op
!= O_constant
&& HAVE_64BIT_ADDRESSES
)
6251 || (offset_expr
.X_op
== O_constant
6252 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)
6253 && HAVE_64BIT_ADDRESS_CONSTANTS
))
6257 /* We don't do GP optimization for now because RELAX_ENCODE can't
6258 hold the data for such large chunks. */
6260 if (used_at
== 0 && ! mips_opts
.noat
)
6262 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6263 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
6264 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6265 AT
, (int) BFD_RELOC_HI16_S
);
6266 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6267 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
6269 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6270 "d,v,t", AT
, AT
, breg
);
6271 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
6272 "d,w,<", tempreg
, tempreg
, 0);
6273 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6274 "d,v,t", tempreg
, tempreg
, AT
);
6275 macro_build (p
, &icnt
, &offset_expr
, s
,
6276 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
6281 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6282 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
6283 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6284 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
6285 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
6286 "d,w,<", tempreg
, tempreg
, 16);
6287 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6288 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
6289 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
6290 "d,w,<", tempreg
, tempreg
, 16);
6292 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
6293 "d,v,t", tempreg
, tempreg
, breg
);
6294 macro_build (p
, &icnt
, &offset_expr
, s
,
6295 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
6300 else if (offset_expr
.X_op
== O_constant
6301 && !HAVE_64BIT_ADDRESS_CONSTANTS
6302 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6303 as_bad (_("load/store address overflow (max 32 bits)"));
6307 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6308 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6313 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6314 treg
, (int) BFD_RELOC_GPREL16
,
6316 p
= frag_var (rs_machine_dependent
, 8, 0,
6317 RELAX_ENCODE (4, 8, 0, 4, 0,
6318 (mips_opts
.warn_about_macros
6320 && mips_opts
.noat
))),
6321 offset_expr
.X_add_symbol
, 0, NULL
);
6324 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
6327 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6328 (int) BFD_RELOC_LO16
, tempreg
);
6332 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6333 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6338 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6339 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
6340 ? "add" : "addu" : "daddu",
6341 "d,v,t", tempreg
, breg
, mips_gp_register
);
6342 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6343 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6344 p
= frag_var (rs_machine_dependent
, 12, 0,
6345 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6346 offset_expr
.X_add_symbol
, 0, NULL
);
6348 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
6351 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6352 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
6353 ? "add" : "addu" : "daddu",
6354 "d,v,t", tempreg
, tempreg
, breg
);
6357 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6358 (int) BFD_RELOC_LO16
, tempreg
);
6361 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6364 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6366 /* If this is a reference to an external symbol, we want
6367 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6369 <op> $treg,0($tempreg)
6371 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6373 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6374 <op> $treg,0($tempreg)
6377 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6378 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6380 If there is a base register, we add it to $tempreg before
6381 the <op>. If there is a constant, we stick it in the
6382 <op> instruction. We don't handle constants larger than
6383 16 bits, because we have no way to load the upper 16 bits
6384 (actually, we could handle them for the subset of cases
6385 in which we are not using $at). */
6386 assert (offset_expr
.X_op
== O_symbol
);
6389 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6390 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6391 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
6394 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6395 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
6396 "d,v,t", tempreg
, tempreg
, breg
);
6397 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6398 (int) BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6405 expr1
.X_add_number
= offset_expr
.X_add_number
;
6406 offset_expr
.X_add_number
= 0;
6407 if (expr1
.X_add_number
< -0x8000
6408 || expr1
.X_add_number
>= 0x8000)
6409 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6411 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6412 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
6413 (int) lw_reloc_type
, mips_gp_register
);
6414 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6415 p
= frag_var (rs_machine_dependent
, 4, 0,
6416 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6417 offset_expr
.X_add_symbol
, 0, NULL
);
6418 macro_build (p
, &icnt
, &offset_expr
,
6419 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6420 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6422 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6423 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6424 "d,v,t", tempreg
, tempreg
, breg
);
6425 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6426 (int) BFD_RELOC_LO16
, tempreg
);
6428 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6433 /* If this is a reference to an external symbol, we want
6434 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6435 addu $tempreg,$tempreg,$gp
6436 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6437 <op> $treg,0($tempreg)
6439 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6441 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6442 <op> $treg,0($tempreg)
6443 If there is a base register, we add it to $tempreg before
6444 the <op>. If there is a constant, we stick it in the
6445 <op> instruction. We don't handle constants larger than
6446 16 bits, because we have no way to load the upper 16 bits
6447 (actually, we could handle them for the subset of cases
6448 in which we are not using $at). */
6449 assert (offset_expr
.X_op
== O_symbol
);
6450 expr1
.X_add_number
= offset_expr
.X_add_number
;
6451 offset_expr
.X_add_number
= 0;
6452 if (expr1
.X_add_number
< -0x8000
6453 || expr1
.X_add_number
>= 0x8000)
6454 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6455 if (reg_needs_delay (mips_gp_register
))
6460 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6461 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6463 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6464 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
6465 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6466 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6467 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6469 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
6470 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
6471 offset_expr
.X_add_symbol
, 0, NULL
);
6474 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6477 macro_build (p
, &icnt
, &offset_expr
,
6478 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6479 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
6482 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6484 macro_build (p
, &icnt
, &offset_expr
,
6485 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6486 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6489 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6490 "d,v,t", tempreg
, tempreg
, breg
);
6491 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6492 (int) BFD_RELOC_LO16
, tempreg
);
6494 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6497 int bregsz
= breg
!= 0 ? 4 : 0;
6499 /* If this is a reference to an external symbol, we want
6500 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6501 add $tempreg,$tempreg,$gp
6502 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6503 <op> $treg,<ofst>($tempreg)
6504 Otherwise, for local symbols, we want:
6505 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6506 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6507 assert (offset_expr
.X_op
== O_symbol
);
6508 frag_now
->tc_frag_data
.tc_fr_offset
=
6509 expr1
.X_add_number
= offset_expr
.X_add_number
;
6510 offset_expr
.X_add_number
= 0;
6511 if (expr1
.X_add_number
< -0x8000
6512 || expr1
.X_add_number
>= 0x8000)
6513 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6515 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6516 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6517 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6518 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
6519 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
6520 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6521 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6522 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6525 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6526 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
6527 "d,v,t", tempreg
, tempreg
, breg
);
6528 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6529 (int) BFD_RELOC_LO16
, tempreg
);
6531 offset_expr
.X_add_number
= expr1
.X_add_number
;
6532 p
= frag_var (rs_machine_dependent
, 12 + bregsz
, 0,
6533 RELAX_ENCODE (16 + bregsz
, 8 + bregsz
,
6534 0, 4 + bregsz
, 0, 0),
6535 offset_expr
.X_add_symbol
, 0, NULL
);
6536 macro_build (p
, &icnt
, &offset_expr
,
6537 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6539 (int) BFD_RELOC_MIPS_GOT_PAGE
,
6542 macro_build (p
+ 4, &icnt
, (expressionS
*) NULL
,
6543 HAVE_32BIT_ADDRESSES
? "add" : "daddu",
6544 "d,v,t", tempreg
, tempreg
, breg
);
6545 macro_build (p
+ 4 + bregsz
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6546 (int) BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6548 else if (mips_pic
== EMBEDDED_PIC
)
6550 /* If there is no base register, we want
6551 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6552 If there is a base register, we want
6553 addu $tempreg,$breg,$gp
6554 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6556 assert (offset_expr
.X_op
== O_symbol
);
6559 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6560 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
6565 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6566 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6567 "d,v,t", tempreg
, breg
, mips_gp_register
);
6568 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6569 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6582 load_register (&icnt
, treg
, &imm_expr
, 0);
6586 load_register (&icnt
, treg
, &imm_expr
, 1);
6590 if (imm_expr
.X_op
== O_constant
)
6592 load_register (&icnt
, AT
, &imm_expr
, 0);
6593 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6594 "mtc1", "t,G", AT
, treg
);
6599 assert (offset_expr
.X_op
== O_symbol
6600 && strcmp (segment_name (S_GET_SEGMENT
6601 (offset_expr
.X_add_symbol
)),
6603 && offset_expr
.X_add_number
== 0);
6604 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6605 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6610 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6611 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6612 order 32 bits of the value and the low order 32 bits are either
6613 zero or in OFFSET_EXPR. */
6614 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6616 if (HAVE_64BIT_GPRS
)
6617 load_register (&icnt
, treg
, &imm_expr
, 1);
6622 if (target_big_endian
)
6634 load_register (&icnt
, hreg
, &imm_expr
, 0);
6637 if (offset_expr
.X_op
== O_absent
)
6638 move_register (&icnt
, lreg
, 0);
6641 assert (offset_expr
.X_op
== O_constant
);
6642 load_register (&icnt
, lreg
, &offset_expr
, 0);
6649 /* We know that sym is in the .rdata section. First we get the
6650 upper 16 bits of the address. */
6651 if (mips_pic
== NO_PIC
)
6653 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6655 else if (mips_pic
== SVR4_PIC
)
6657 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6658 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6659 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6662 else if (mips_pic
== EMBEDDED_PIC
)
6664 /* For embedded PIC we pick up the entire address off $gp in
6665 a single instruction. */
6666 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6667 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
6668 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
6669 offset_expr
.X_op
= O_constant
;
6670 offset_expr
.X_add_number
= 0;
6675 /* Now we load the register(s). */
6676 if (HAVE_64BIT_GPRS
)
6677 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6678 treg
, (int) BFD_RELOC_LO16
, AT
);
6681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6682 treg
, (int) BFD_RELOC_LO16
, AT
);
6685 /* FIXME: How in the world do we deal with the possible
6687 offset_expr
.X_add_number
+= 4;
6688 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6689 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6693 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6694 does not become a variant frag. */
6695 frag_wane (frag_now
);
6701 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6702 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6703 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6704 the value and the low order 32 bits are either zero or in
6706 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6708 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6709 if (HAVE_64BIT_FPRS
)
6711 assert (HAVE_64BIT_GPRS
);
6712 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6713 "dmtc1", "t,S", AT
, treg
);
6717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6718 "mtc1", "t,G", AT
, treg
+ 1);
6719 if (offset_expr
.X_op
== O_absent
)
6720 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6721 "mtc1", "t,G", 0, treg
);
6724 assert (offset_expr
.X_op
== O_constant
);
6725 load_register (&icnt
, AT
, &offset_expr
, 0);
6726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6727 "mtc1", "t,G", AT
, treg
);
6733 assert (offset_expr
.X_op
== O_symbol
6734 && offset_expr
.X_add_number
== 0);
6735 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6736 if (strcmp (s
, ".lit8") == 0)
6738 if (mips_opts
.isa
!= ISA_MIPS1
)
6740 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6741 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6745 breg
= mips_gp_register
;
6746 r
= BFD_RELOC_MIPS_LITERAL
;
6751 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6752 if (mips_pic
== SVR4_PIC
)
6753 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6754 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6755 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6759 /* FIXME: This won't work for a 64 bit address. */
6760 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6763 if (mips_opts
.isa
!= ISA_MIPS1
)
6765 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6766 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6768 /* To avoid confusion in tc_gen_reloc, we must ensure
6769 that this does not become a variant frag. */
6770 frag_wane (frag_now
);
6781 if (mips_arch
== CPU_R4650
)
6783 as_bad (_("opcode not supported on this processor"));
6786 /* Even on a big endian machine $fn comes before $fn+1. We have
6787 to adjust when loading from memory. */
6790 assert (mips_opts
.isa
== ISA_MIPS1
);
6791 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6792 target_big_endian
? treg
+ 1 : treg
,
6794 /* FIXME: A possible overflow which I don't know how to deal
6796 offset_expr
.X_add_number
+= 4;
6797 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6798 target_big_endian
? treg
: treg
+ 1,
6801 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6802 does not become a variant frag. */
6803 frag_wane (frag_now
);
6812 * The MIPS assembler seems to check for X_add_number not
6813 * being double aligned and generating:
6816 * addiu at,at,%lo(foo+1)
6819 * But, the resulting address is the same after relocation so why
6820 * generate the extra instruction?
6822 if (mips_arch
== CPU_R4650
)
6824 as_bad (_("opcode not supported on this processor"));
6827 /* Itbl support may require additional care here. */
6829 if (mips_opts
.isa
!= ISA_MIPS1
)
6840 if (mips_arch
== CPU_R4650
)
6842 as_bad (_("opcode not supported on this processor"));
6846 if (mips_opts
.isa
!= ISA_MIPS1
)
6854 /* Itbl support may require additional care here. */
6859 if (HAVE_64BIT_GPRS
)
6870 if (HAVE_64BIT_GPRS
)
6880 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6881 loads for the case of doing a pair of loads to simulate an 'ld'.
6882 This is not currently done by the compiler, and assembly coders
6883 writing embedded-pic code can cope. */
6885 if (offset_expr
.X_op
!= O_symbol
6886 && offset_expr
.X_op
!= O_constant
)
6888 as_bad (_("expression too complex"));
6889 offset_expr
.X_op
= O_constant
;
6892 /* Even on a big endian machine $fn comes before $fn+1. We have
6893 to adjust when loading from memory. We set coproc if we must
6894 load $fn+1 first. */
6895 /* Itbl support may require additional care here. */
6896 if (! target_big_endian
)
6899 if (mips_pic
== NO_PIC
6900 || offset_expr
.X_op
== O_constant
)
6904 /* If this is a reference to a GP relative symbol, we want
6905 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6906 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6907 If we have a base register, we use this
6909 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6910 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6911 If this is not a GP relative symbol, we want
6912 lui $at,<sym> (BFD_RELOC_HI16_S)
6913 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6914 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6915 If there is a base register, we add it to $at after the
6916 lui instruction. If there is a constant, we always use
6918 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6919 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6931 tempreg
= mips_gp_register
;
6938 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6939 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
6940 ? "add" : "addu" : "daddu",
6941 "d,v,t", AT
, breg
, mips_gp_register
);
6947 /* Itbl support may require additional care here. */
6948 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6949 coproc
? treg
+ 1 : treg
,
6950 (int) BFD_RELOC_GPREL16
, tempreg
);
6951 offset_expr
.X_add_number
+= 4;
6953 /* Set mips_optimize to 2 to avoid inserting an
6955 hold_mips_optimize
= mips_optimize
;
6957 /* Itbl support may require additional care here. */
6958 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6959 coproc
? treg
: treg
+ 1,
6960 (int) BFD_RELOC_GPREL16
, tempreg
);
6961 mips_optimize
= hold_mips_optimize
;
6963 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6964 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6965 used_at
&& mips_opts
.noat
),
6966 offset_expr
.X_add_symbol
, 0, NULL
);
6968 /* We just generated two relocs. When tc_gen_reloc
6969 handles this case, it will skip the first reloc and
6970 handle the second. The second reloc already has an
6971 extra addend of 4, which we added above. We must
6972 subtract it out, and then subtract another 4 to make
6973 the first reloc come out right. The second reloc
6974 will come out right because we are going to add 4 to
6975 offset_expr when we build its instruction below.
6977 If we have a symbol, then we don't want to include
6978 the offset, because it will wind up being included
6979 when we generate the reloc. */
6981 if (offset_expr
.X_op
== O_constant
)
6982 offset_expr
.X_add_number
-= 8;
6985 offset_expr
.X_add_number
= -4;
6986 offset_expr
.X_op
= O_constant
;
6989 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6994 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6995 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
6996 ? "add" : "addu" : "daddu",
6997 "d,v,t", AT
, breg
, AT
);
7001 /* Itbl support may require additional care here. */
7002 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
7003 coproc
? treg
+ 1 : treg
,
7004 (int) BFD_RELOC_LO16
, AT
);
7007 /* FIXME: How do we handle overflow here? */
7008 offset_expr
.X_add_number
+= 4;
7009 /* Itbl support may require additional care here. */
7010 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
7011 coproc
? treg
: treg
+ 1,
7012 (int) BFD_RELOC_LO16
, AT
);
7014 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
7018 /* If this is a reference to an external symbol, we want
7019 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7024 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7026 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7027 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7028 If there is a base register we add it to $at before the
7029 lwc1 instructions. If there is a constant we include it
7030 in the lwc1 instructions. */
7032 expr1
.X_add_number
= offset_expr
.X_add_number
;
7033 offset_expr
.X_add_number
= 0;
7034 if (expr1
.X_add_number
< -0x8000
7035 || expr1
.X_add_number
>= 0x8000 - 4)
7036 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7041 frag_grow (24 + off
);
7042 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
7043 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
7044 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7045 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7047 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7048 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
7049 ? "add" : "addu" : "daddu",
7050 "d,v,t", AT
, breg
, AT
);
7051 /* Itbl support may require additional care here. */
7052 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7053 coproc
? treg
+ 1 : treg
,
7054 (int) BFD_RELOC_LO16
, AT
);
7055 expr1
.X_add_number
+= 4;
7057 /* Set mips_optimize to 2 to avoid inserting an undesired
7059 hold_mips_optimize
= mips_optimize
;
7061 /* Itbl support may require additional care here. */
7062 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7063 coproc
? treg
: treg
+ 1,
7064 (int) BFD_RELOC_LO16
, AT
);
7065 mips_optimize
= hold_mips_optimize
;
7067 (void) frag_var (rs_machine_dependent
, 0, 0,
7068 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
7069 offset_expr
.X_add_symbol
, 0, NULL
);
7071 else if (mips_pic
== SVR4_PIC
)
7076 /* If this is a reference to an external symbol, we want
7077 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7079 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7084 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7086 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7087 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7088 If there is a base register we add it to $at before the
7089 lwc1 instructions. If there is a constant we include it
7090 in the lwc1 instructions. */
7092 expr1
.X_add_number
= offset_expr
.X_add_number
;
7093 offset_expr
.X_add_number
= 0;
7094 if (expr1
.X_add_number
< -0x8000
7095 || expr1
.X_add_number
>= 0x8000 - 4)
7096 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7097 if (reg_needs_delay (mips_gp_register
))
7106 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
7107 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
7108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7109 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
7110 ? "add" : "addu" : "daddu",
7111 "d,v,t", AT
, AT
, mips_gp_register
);
7112 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
7113 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
7114 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
7115 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7117 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7118 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
7119 ? "add" : "addu" : "daddu",
7120 "d,v,t", AT
, breg
, AT
);
7121 /* Itbl support may require additional care here. */
7122 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7123 coproc
? treg
+ 1 : treg
,
7124 (int) BFD_RELOC_LO16
, AT
);
7125 expr1
.X_add_number
+= 4;
7127 /* Set mips_optimize to 2 to avoid inserting an undesired
7129 hold_mips_optimize
= mips_optimize
;
7131 /* Itbl support may require additional care here. */
7132 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
7133 coproc
? treg
: treg
+ 1,
7134 (int) BFD_RELOC_LO16
, AT
);
7135 mips_optimize
= hold_mips_optimize
;
7136 expr1
.X_add_number
-= 4;
7138 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
7139 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
7140 8 + gpdel
+ off
, 1, 0),
7141 offset_expr
.X_add_symbol
, 0, NULL
);
7144 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
7147 macro_build (p
, &icnt
, &offset_expr
,
7148 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
7149 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
7152 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
7156 macro_build (p
, &icnt
, (expressionS
*) NULL
,
7157 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
7158 ? "add" : "addu" : "daddu",
7159 "d,v,t", AT
, breg
, AT
);
7162 /* Itbl support may require additional care here. */
7163 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
7164 coproc
? treg
+ 1 : treg
,
7165 (int) BFD_RELOC_LO16
, AT
);
7167 expr1
.X_add_number
+= 4;
7169 /* Set mips_optimize to 2 to avoid inserting an undesired
7171 hold_mips_optimize
= mips_optimize
;
7173 /* Itbl support may require additional care here. */
7174 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
7175 coproc
? treg
: treg
+ 1,
7176 (int) BFD_RELOC_LO16
, AT
);
7177 mips_optimize
= hold_mips_optimize
;
7179 else if (mips_pic
== EMBEDDED_PIC
)
7181 /* If there is no base register, we use
7182 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7183 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7184 If we have a base register, we use
7186 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7187 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7191 tempreg
= mips_gp_register
;
7196 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7197 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7198 "d,v,t", AT
, breg
, mips_gp_register
);
7203 /* Itbl support may require additional care here. */
7204 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
7205 coproc
? treg
+ 1 : treg
,
7206 (int) BFD_RELOC_GPREL16
, tempreg
);
7207 offset_expr
.X_add_number
+= 4;
7208 /* Itbl support may require additional care here. */
7209 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
7210 coproc
? treg
: treg
+ 1,
7211 (int) BFD_RELOC_GPREL16
, tempreg
);
7227 assert (HAVE_32BIT_ADDRESSES
);
7228 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7229 (int) BFD_RELOC_LO16
, breg
);
7230 offset_expr
.X_add_number
+= 4;
7231 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
7232 (int) BFD_RELOC_LO16
, breg
);
7235 /* New code added to support COPZ instructions.
7236 This code builds table entries out of the macros in mip_opcodes.
7237 R4000 uses interlocks to handle coproc delays.
7238 Other chips (like the R3000) require nops to be inserted for delays.
7240 FIXME: Currently, we require that the user handle delays.
7241 In order to fill delay slots for non-interlocked chips,
7242 we must have a way to specify delays based on the coprocessor.
7243 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7244 What are the side-effects of the cop instruction?
7245 What cache support might we have and what are its effects?
7246 Both coprocessor & memory require delays. how long???
7247 What registers are read/set/modified?
7249 If an itbl is provided to interpret cop instructions,
7250 this knowledge can be encoded in the itbl spec. */
7264 /* For now we just do C (same as Cz). The parameter will be
7265 stored in insn_opcode by mips_ip. */
7266 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
7271 move_register (&icnt
, dreg
, sreg
);
7274 #ifdef LOSING_COMPILER
7276 /* Try and see if this is a new itbl instruction.
7277 This code builds table entries out of the macros in mip_opcodes.
7278 FIXME: For now we just assemble the expression and pass it's
7279 value along as a 32-bit immediate.
7280 We may want to have the assembler assemble this value,
7281 so that we gain the assembler's knowledge of delay slots,
7283 Would it be more efficient to use mask (id) here? */
7284 if (itbl_have_entries
7285 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7287 s
= ip
->insn_mo
->name
;
7289 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7290 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
7297 as_warn (_("Macro used $at after \".set noat\""));
7302 struct mips_cl_insn
*ip
;
7304 register int treg
, sreg
, dreg
, breg
;
7320 bfd_reloc_code_real_type r
;
7323 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7324 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7325 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7326 mask
= ip
->insn_mo
->mask
;
7328 expr1
.X_op
= O_constant
;
7329 expr1
.X_op_symbol
= NULL
;
7330 expr1
.X_add_symbol
= NULL
;
7331 expr1
.X_add_number
= 1;
7335 #endif /* LOSING_COMPILER */
7340 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7341 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7342 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7349 /* The MIPS assembler some times generates shifts and adds. I'm
7350 not trying to be that fancy. GCC should do this for us
7352 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7353 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7354 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7355 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7369 mips_emit_delays (TRUE
);
7370 ++mips_opts
.noreorder
;
7371 mips_any_noreorder
= 1;
7373 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7374 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7375 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7379 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7380 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
7383 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
7384 "s,t,q", dreg
, AT
, 6);
7387 expr1
.X_add_number
= 8;
7388 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
7390 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
7392 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7395 --mips_opts
.noreorder
;
7396 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
7409 mips_emit_delays (TRUE
);
7410 ++mips_opts
.noreorder
;
7411 mips_any_noreorder
= 1;
7413 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7414 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7415 dbl
? "dmultu" : "multu",
7416 "s,t", sreg
, imm
? AT
: treg
);
7417 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
7419 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
7422 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
7426 expr1
.X_add_number
= 8;
7427 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
7428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
7430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7433 --mips_opts
.noreorder
;
7437 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7449 macro_build ((char *) NULL
, &icnt
, NULL
, "dnegu",
7450 "d,w", tempreg
, treg
);
7451 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7452 "d,t,s", dreg
, sreg
, tempreg
);
7457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7458 "d,v,t", AT
, 0, treg
);
7459 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7460 "d,t,s", AT
, sreg
, AT
);
7461 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7462 "d,t,s", dreg
, sreg
, treg
);
7463 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7464 "d,v,t", dreg
, dreg
, AT
);
7468 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7480 macro_build ((char *) NULL
, &icnt
, NULL
, "negu",
7481 "d,w", tempreg
, treg
);
7482 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7483 "d,t,s", dreg
, sreg
, tempreg
);
7488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7489 "d,v,t", AT
, 0, treg
);
7490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7491 "d,t,s", AT
, sreg
, AT
);
7492 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7493 "d,t,s", dreg
, sreg
, treg
);
7494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7495 "d,v,t", dreg
, dreg
, AT
);
7503 if (imm_expr
.X_op
!= O_constant
)
7504 as_bad (_("Improper rotate count"));
7505 rot
= imm_expr
.X_add_number
& 0x3f;
7506 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7508 rot
= (64 - rot
) & 0x3f;
7510 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7511 "d,w,<", dreg
, sreg
, rot
- 32);
7513 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7514 "d,w,<", dreg
, sreg
, rot
);
7519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7520 "d,w,<", dreg
, sreg
, 0);
7523 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7524 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7526 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7527 "d,w,<", AT
, sreg
, rot
);
7528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7529 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7530 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7531 "d,v,t", dreg
, dreg
, AT
);
7539 if (imm_expr
.X_op
!= O_constant
)
7540 as_bad (_("Improper rotate count"));
7541 rot
= imm_expr
.X_add_number
& 0x1f;
7542 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7544 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7545 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7550 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7551 "d,w,<", dreg
, sreg
, 0);
7554 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7555 "d,w,<", AT
, sreg
, rot
);
7556 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7557 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7558 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7559 "d,v,t", dreg
, dreg
, AT
);
7564 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7566 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7567 "d,t,s", dreg
, sreg
, treg
);
7570 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7571 "d,v,t", AT
, 0, treg
);
7572 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7573 "d,t,s", AT
, sreg
, AT
);
7574 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7575 "d,t,s", dreg
, sreg
, treg
);
7576 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7577 "d,v,t", dreg
, dreg
, AT
);
7581 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7583 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7584 "d,t,s", dreg
, sreg
, treg
);
7587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7588 "d,v,t", AT
, 0, treg
);
7589 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7590 "d,t,s", AT
, sreg
, AT
);
7591 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7592 "d,t,s", dreg
, sreg
, treg
);
7593 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7594 "d,v,t", dreg
, dreg
, AT
);
7602 if (imm_expr
.X_op
!= O_constant
)
7603 as_bad (_("Improper rotate count"));
7604 rot
= imm_expr
.X_add_number
& 0x3f;
7605 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7608 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7609 "d,w,<", dreg
, sreg
, rot
- 32);
7611 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7612 "d,w,<", dreg
, sreg
, rot
);
7617 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7618 "d,w,<", dreg
, sreg
, 0);
7621 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7622 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7624 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7625 "d,w,<", AT
, sreg
, rot
);
7626 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7627 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7628 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7629 "d,v,t", dreg
, dreg
, AT
);
7637 if (imm_expr
.X_op
!= O_constant
)
7638 as_bad (_("Improper rotate count"));
7639 rot
= imm_expr
.X_add_number
& 0x1f;
7640 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7642 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7643 "d,w,<", dreg
, sreg
, rot
);
7648 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7649 "d,w,<", dreg
, sreg
, 0);
7652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7653 "d,w,<", AT
, sreg
, rot
);
7654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7655 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7656 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7657 "d,v,t", dreg
, dreg
, AT
);
7662 if (mips_arch
== CPU_R4650
)
7664 as_bad (_("opcode not supported on this processor"));
7667 assert (mips_opts
.isa
== ISA_MIPS1
);
7668 /* Even on a big endian machine $fn comes before $fn+1. We have
7669 to adjust when storing to memory. */
7670 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7671 target_big_endian
? treg
+ 1 : treg
,
7672 (int) BFD_RELOC_LO16
, breg
);
7673 offset_expr
.X_add_number
+= 4;
7674 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7675 target_big_endian
? treg
: treg
+ 1,
7676 (int) BFD_RELOC_LO16
, breg
);
7681 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7682 treg
, (int) BFD_RELOC_LO16
);
7684 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7685 sreg
, (int) BFD_RELOC_LO16
);
7688 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7689 "d,v,t", dreg
, sreg
, treg
);
7690 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7691 dreg
, (int) BFD_RELOC_LO16
);
7696 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7698 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7699 sreg
, (int) BFD_RELOC_LO16
);
7704 as_warn (_("Instruction %s: result is always false"),
7706 move_register (&icnt
, dreg
, 0);
7709 if (imm_expr
.X_op
== O_constant
7710 && imm_expr
.X_add_number
>= 0
7711 && imm_expr
.X_add_number
< 0x10000)
7713 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
7714 sreg
, (int) BFD_RELOC_LO16
);
7717 else if (imm_expr
.X_op
== O_constant
7718 && imm_expr
.X_add_number
> -0x8000
7719 && imm_expr
.X_add_number
< 0)
7721 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7722 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7723 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7724 "t,r,j", dreg
, sreg
,
7725 (int) BFD_RELOC_LO16
);
7730 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7731 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7732 "d,v,t", dreg
, sreg
, AT
);
7735 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7736 (int) BFD_RELOC_LO16
);
7741 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7749 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7750 (int) BFD_RELOC_LO16
);
7753 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7755 if (imm_expr
.X_op
== O_constant
7756 && imm_expr
.X_add_number
>= -0x8000
7757 && imm_expr
.X_add_number
< 0x8000)
7759 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7760 mask
== M_SGE_I
? "slti" : "sltiu",
7761 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7766 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7767 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7768 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7772 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7773 (int) BFD_RELOC_LO16
);
7778 case M_SGT
: /* sreg > treg <==> treg < sreg */
7784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7788 case M_SGT_I
: /* sreg > I <==> I < sreg */
7794 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7795 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7799 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7805 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7807 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7808 (int) BFD_RELOC_LO16
);
7811 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7817 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7818 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7820 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7821 (int) BFD_RELOC_LO16
);
7825 if (imm_expr
.X_op
== O_constant
7826 && imm_expr
.X_add_number
>= -0x8000
7827 && imm_expr
.X_add_number
< 0x8000)
7829 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7830 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7833 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7834 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7839 if (imm_expr
.X_op
== O_constant
7840 && imm_expr
.X_add_number
>= -0x8000
7841 && imm_expr
.X_add_number
< 0x8000)
7843 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7844 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7847 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7848 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7849 "d,v,t", dreg
, sreg
, AT
);
7854 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7855 "d,v,t", dreg
, 0, treg
);
7857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7858 "d,v,t", dreg
, 0, sreg
);
7861 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7862 "d,v,t", dreg
, sreg
, treg
);
7863 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7864 "d,v,t", dreg
, 0, dreg
);
7869 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7871 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7872 "d,v,t", dreg
, 0, sreg
);
7877 as_warn (_("Instruction %s: result is always true"),
7879 macro_build ((char *) NULL
, &icnt
, &expr1
,
7880 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7881 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7884 if (imm_expr
.X_op
== O_constant
7885 && imm_expr
.X_add_number
>= 0
7886 && imm_expr
.X_add_number
< 0x10000)
7888 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7889 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7892 else if (imm_expr
.X_op
== O_constant
7893 && imm_expr
.X_add_number
> -0x8000
7894 && imm_expr
.X_add_number
< 0)
7896 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7897 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7898 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7899 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7904 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7906 "d,v,t", dreg
, sreg
, AT
);
7909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7910 "d,v,t", dreg
, 0, dreg
);
7918 if (imm_expr
.X_op
== O_constant
7919 && imm_expr
.X_add_number
> -0x8000
7920 && imm_expr
.X_add_number
<= 0x8000)
7922 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7923 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7924 dbl
? "daddi" : "addi",
7925 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7928 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7929 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7930 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7936 if (imm_expr
.X_op
== O_constant
7937 && imm_expr
.X_add_number
> -0x8000
7938 && imm_expr
.X_add_number
<= 0x8000)
7940 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7941 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7942 dbl
? "daddiu" : "addiu",
7943 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7946 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7947 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7948 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7969 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7970 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7976 assert (mips_opts
.isa
== ISA_MIPS1
);
7977 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7978 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7981 * Is the double cfc1 instruction a bug in the mips assembler;
7982 * or is there a reason for it?
7984 mips_emit_delays (TRUE
);
7985 ++mips_opts
.noreorder
;
7986 mips_any_noreorder
= 1;
7987 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7991 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7992 expr1
.X_add_number
= 3;
7993 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7994 (int) BFD_RELOC_LO16
);
7995 expr1
.X_add_number
= 2;
7996 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7997 (int) BFD_RELOC_LO16
);
7998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
8000 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
8001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8002 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
8003 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
8005 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
8006 --mips_opts
.noreorder
;
8015 if (offset_expr
.X_add_number
>= 0x7fff)
8016 as_bad (_("operand overflow"));
8017 if (! target_big_endian
)
8018 ++offset_expr
.X_add_number
;
8019 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", AT
,
8020 (int) BFD_RELOC_LO16
, breg
);
8021 if (! target_big_endian
)
8022 --offset_expr
.X_add_number
;
8024 ++offset_expr
.X_add_number
;
8025 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", treg
,
8026 (int) BFD_RELOC_LO16
, breg
);
8027 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
8029 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
8043 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8044 as_bad (_("operand overflow"));
8049 if (! target_big_endian
)
8050 offset_expr
.X_add_number
+= off
;
8051 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", tempreg
,
8052 (int) BFD_RELOC_LO16
, breg
);
8053 if (! target_big_endian
)
8054 offset_expr
.X_add_number
-= off
;
8056 offset_expr
.X_add_number
+= off
;
8057 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", tempreg
,
8058 (int) BFD_RELOC_LO16
, breg
);
8060 /* If necessary, move the result in tempreg the final destination. */
8061 if (treg
== tempreg
)
8063 /* Protect second load's delay slot. */
8064 if (!gpr_interlocks
)
8065 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
8066 move_register (&icnt
, treg
, tempreg
);
8080 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8083 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
8084 ? "add" : "addu" : "daddu",
8085 "d,v,t", AT
, AT
, breg
);
8086 if (! target_big_endian
)
8087 expr1
.X_add_number
= off
;
8089 expr1
.X_add_number
= 0;
8090 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
8091 (int) BFD_RELOC_LO16
, AT
);
8092 if (! target_big_endian
)
8093 expr1
.X_add_number
= 0;
8095 expr1
.X_add_number
= off
;
8096 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
8097 (int) BFD_RELOC_LO16
, AT
);
8103 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8105 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8106 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
8107 ? "add" : "addu" : "daddu",
8108 "d,v,t", AT
, AT
, breg
);
8109 if (target_big_endian
)
8110 expr1
.X_add_number
= 0;
8111 macro_build ((char *) NULL
, &icnt
, &expr1
,
8112 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
8113 (int) BFD_RELOC_LO16
, AT
);
8114 if (target_big_endian
)
8115 expr1
.X_add_number
= 1;
8117 expr1
.X_add_number
= 0;
8118 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
8119 (int) BFD_RELOC_LO16
, AT
);
8120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
8122 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
8127 if (offset_expr
.X_add_number
>= 0x7fff)
8128 as_bad (_("operand overflow"));
8129 if (target_big_endian
)
8130 ++offset_expr
.X_add_number
;
8131 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
8132 (int) BFD_RELOC_LO16
, breg
);
8133 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
8135 if (target_big_endian
)
8136 --offset_expr
.X_add_number
;
8138 ++offset_expr
.X_add_number
;
8139 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
8140 (int) BFD_RELOC_LO16
, breg
);
8153 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8154 as_bad (_("operand overflow"));
8155 if (! target_big_endian
)
8156 offset_expr
.X_add_number
+= off
;
8157 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
8158 (int) BFD_RELOC_LO16
, breg
);
8159 if (! target_big_endian
)
8160 offset_expr
.X_add_number
-= off
;
8162 offset_expr
.X_add_number
+= off
;
8163 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
8164 (int) BFD_RELOC_LO16
, breg
);
8178 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8181 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
8182 ? "add" : "addu" : "daddu",
8183 "d,v,t", AT
, AT
, breg
);
8184 if (! target_big_endian
)
8185 expr1
.X_add_number
= off
;
8187 expr1
.X_add_number
= 0;
8188 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
8189 (int) BFD_RELOC_LO16
, AT
);
8190 if (! target_big_endian
)
8191 expr1
.X_add_number
= 0;
8193 expr1
.X_add_number
= off
;
8194 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
8195 (int) BFD_RELOC_LO16
, AT
);
8200 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
8202 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8203 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
8204 ? "add" : "addu" : "daddu",
8205 "d,v,t", AT
, AT
, breg
);
8206 if (! target_big_endian
)
8207 expr1
.X_add_number
= 0;
8208 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
8209 (int) BFD_RELOC_LO16
, AT
);
8210 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
8212 if (! target_big_endian
)
8213 expr1
.X_add_number
= 1;
8215 expr1
.X_add_number
= 0;
8216 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
8217 (int) BFD_RELOC_LO16
, AT
);
8218 if (! target_big_endian
)
8219 expr1
.X_add_number
= 0;
8221 expr1
.X_add_number
= 1;
8222 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
8223 (int) BFD_RELOC_LO16
, AT
);
8224 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
8226 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
8231 /* FIXME: Check if this is one of the itbl macros, since they
8232 are added dynamically. */
8233 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8237 as_warn (_("Macro used $at after \".set noat\""));
8240 /* Implement macros in mips16 mode. */
8244 struct mips_cl_insn
*ip
;
8247 int xreg
, yreg
, zreg
, tmp
;
8251 const char *s
, *s2
, *s3
;
8253 mask
= ip
->insn_mo
->mask
;
8255 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
8256 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
8257 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
8261 expr1
.X_op
= O_constant
;
8262 expr1
.X_op_symbol
= NULL
;
8263 expr1
.X_add_symbol
= NULL
;
8264 expr1
.X_add_number
= 1;
8283 mips_emit_delays (TRUE
);
8284 ++mips_opts
.noreorder
;
8285 mips_any_noreorder
= 1;
8286 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8287 dbl
? "ddiv" : "div",
8288 "0,x,y", xreg
, yreg
);
8289 expr1
.X_add_number
= 2;
8290 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
8291 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
8294 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8295 since that causes an overflow. We should do that as well,
8296 but I don't see how to do the comparisons without a temporary
8298 --mips_opts
.noreorder
;
8299 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
8318 mips_emit_delays (TRUE
);
8319 ++mips_opts
.noreorder
;
8320 mips_any_noreorder
= 1;
8321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
8323 expr1
.X_add_number
= 2;
8324 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
8325 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
8327 --mips_opts
.noreorder
;
8328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
8334 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8335 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
8345 if (imm_expr
.X_op
!= O_constant
)
8346 as_bad (_("Unsupported large constant"));
8347 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8348 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
8349 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8353 if (imm_expr
.X_op
!= O_constant
)
8354 as_bad (_("Unsupported large constant"));
8355 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8356 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
8361 if (imm_expr
.X_op
!= O_constant
)
8362 as_bad (_("Unsupported large constant"));
8363 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8364 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
8387 goto do_reverse_branch
;
8391 goto do_reverse_branch
;
8403 goto do_reverse_branch
;
8414 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
8416 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
8443 goto do_addone_branch_i
;
8448 goto do_addone_branch_i
;
8463 goto do_addone_branch_i
;
8470 if (imm_expr
.X_op
!= O_constant
)
8471 as_bad (_("Unsupported large constant"));
8472 ++imm_expr
.X_add_number
;
8475 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
8476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
8480 expr1
.X_add_number
= 0;
8481 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
8483 move_register (&icnt
, xreg
, yreg
);
8484 expr1
.X_add_number
= 2;
8485 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
8486 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8487 "neg", "x,w", xreg
, xreg
);
8491 /* For consistency checking, verify that all bits are specified either
8492 by the match/mask part of the instruction definition, or by the
8495 validate_mips_insn (opc
)
8496 const struct mips_opcode
*opc
;
8498 const char *p
= opc
->args
;
8500 unsigned long used_bits
= opc
->mask
;
8502 if ((used_bits
& opc
->match
) != opc
->match
)
8504 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8505 opc
->name
, opc
->args
);
8508 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8518 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8519 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8520 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8521 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8522 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8524 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8525 c
, opc
->name
, opc
->args
);
8529 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8530 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8532 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8533 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8534 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8535 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8537 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8538 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8540 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8541 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8543 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8544 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8545 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8546 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8547 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8548 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8549 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8550 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8551 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8552 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8553 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8554 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8555 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8556 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8557 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8558 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8559 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8561 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8562 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8563 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8564 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8566 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8567 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8568 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8569 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8570 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8571 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8572 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8573 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8574 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8577 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8578 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8579 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8580 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8581 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8585 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8586 c
, opc
->name
, opc
->args
);
8590 if (used_bits
!= 0xffffffff)
8592 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8593 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8599 /* This routine assembles an instruction into its binary format. As a
8600 side effect, it sets one of the global variables imm_reloc or
8601 offset_reloc to the type of relocation to do if one of the operands
8602 is an address expression. */
8607 struct mips_cl_insn
*ip
;
8612 struct mips_opcode
*insn
;
8615 unsigned int lastregno
= 0;
8616 unsigned int lastpos
= 0;
8617 unsigned int limlo
, limhi
;
8623 /* If the instruction contains a '.', we first try to match an instruction
8624 including the '.'. Then we try again without the '.'. */
8626 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8629 /* If we stopped on whitespace, then replace the whitespace with null for
8630 the call to hash_find. Save the character we replaced just in case we
8631 have to re-parse the instruction. */
8638 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8640 /* If we didn't find the instruction in the opcode table, try again, but
8641 this time with just the instruction up to, but not including the
8645 /* Restore the character we overwrite above (if any). */
8649 /* Scan up to the first '.' or whitespace. */
8651 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8655 /* If we did not find a '.', then we can quit now. */
8658 insn_error
= "unrecognized opcode";
8662 /* Lookup the instruction in the hash table. */
8664 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8666 insn_error
= "unrecognized opcode";
8676 assert (strcmp (insn
->name
, str
) == 0);
8678 if (OPCODE_IS_MEMBER (insn
,
8680 | (file_ase_mips16
? INSN_MIPS16
: 0)
8681 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8682 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8688 if (insn
->pinfo
!= INSN_MACRO
)
8690 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8696 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8697 && strcmp (insn
->name
, insn
[1].name
) == 0)
8706 static char buf
[100];
8707 if (mips_arch_info
->is_isa
)
8709 _("opcode not supported at this ISA level (%s)"),
8710 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8713 _("opcode not supported on this processor: %s (%s)"),
8714 mips_arch_info
->name
,
8715 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8725 ip
->insn_opcode
= insn
->match
;
8727 for (args
= insn
->args
;; ++args
)
8731 s
+= strspn (s
, " \t");
8735 case '\0': /* end of args */
8748 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8752 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8756 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8760 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8766 /* Handle optional base register.
8767 Either the base register is omitted or
8768 we must have a left paren. */
8769 /* This is dependent on the next operand specifier
8770 is a base register specification. */
8771 assert (args
[1] == 'b' || args
[1] == '5'
8772 || args
[1] == '-' || args
[1] == '4');
8776 case ')': /* these must match exactly */
8783 case '+': /* Opcode extension character. */
8786 case 'A': /* ins/ext position, becomes LSB. */
8789 my_getExpression (&imm_expr
, s
);
8790 check_absolute_expr (ip
, &imm_expr
);
8791 if ((unsigned long) imm_expr
.X_add_number
< limlo
8792 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8794 as_bad (_("Improper position (%lu)"),
8795 (unsigned long) imm_expr
.X_add_number
);
8796 imm_expr
.X_add_number
= limlo
;
8798 lastpos
= imm_expr
.X_add_number
;
8799 ip
->insn_opcode
|= (imm_expr
.X_add_number
8800 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8801 imm_expr
.X_op
= O_absent
;
8805 case 'B': /* ins size, becomes MSB. */
8808 my_getExpression (&imm_expr
, s
);
8809 check_absolute_expr (ip
, &imm_expr
);
8810 /* Check for negative input so that small negative numbers
8811 will not succeed incorrectly. The checks against
8812 (pos+size) transitively check "size" itself,
8813 assuming that "pos" is reasonable. */
8814 if ((long) imm_expr
.X_add_number
< 0
8815 || ((unsigned long) imm_expr
.X_add_number
8817 || ((unsigned long) imm_expr
.X_add_number
8820 as_bad (_("Improper insert size (%lu, position %lu)"),
8821 (unsigned long) imm_expr
.X_add_number
,
8822 (unsigned long) lastpos
);
8823 imm_expr
.X_add_number
= limlo
- lastpos
;
8825 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8826 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8827 imm_expr
.X_op
= O_absent
;
8831 case 'C': /* ext size, becomes MSBD. */
8834 my_getExpression (&imm_expr
, s
);
8835 check_absolute_expr (ip
, &imm_expr
);
8836 /* Check for negative input so that small negative numbers
8837 will not succeed incorrectly. The checks against
8838 (pos+size) transitively check "size" itself,
8839 assuming that "pos" is reasonable. */
8840 if ((long) imm_expr
.X_add_number
< 0
8841 || ((unsigned long) imm_expr
.X_add_number
8843 || ((unsigned long) imm_expr
.X_add_number
8846 as_bad (_("Improper extract size (%lu, position %lu)"),
8847 (unsigned long) imm_expr
.X_add_number
,
8848 (unsigned long) lastpos
);
8849 imm_expr
.X_add_number
= limlo
- lastpos
;
8851 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8852 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8853 imm_expr
.X_op
= O_absent
;
8858 /* +D is for disassembly only; never match. */
8862 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8863 *args
, insn
->name
, insn
->args
);
8864 /* Further processing is fruitless. */
8869 case '<': /* must be at least one digit */
8871 * According to the manual, if the shift amount is greater
8872 * than 31 or less than 0, then the shift amount should be
8873 * mod 32. In reality the mips assembler issues an error.
8874 * We issue a warning and mask out all but the low 5 bits.
8876 my_getExpression (&imm_expr
, s
);
8877 check_absolute_expr (ip
, &imm_expr
);
8878 if ((unsigned long) imm_expr
.X_add_number
> 31)
8880 as_warn (_("Improper shift amount (%lu)"),
8881 (unsigned long) imm_expr
.X_add_number
);
8882 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8884 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8885 imm_expr
.X_op
= O_absent
;
8889 case '>': /* shift amount minus 32 */
8890 my_getExpression (&imm_expr
, s
);
8891 check_absolute_expr (ip
, &imm_expr
);
8892 if ((unsigned long) imm_expr
.X_add_number
< 32
8893 || (unsigned long) imm_expr
.X_add_number
> 63)
8895 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8896 imm_expr
.X_op
= O_absent
;
8900 case 'k': /* cache code */
8901 case 'h': /* prefx code */
8902 my_getExpression (&imm_expr
, s
);
8903 check_absolute_expr (ip
, &imm_expr
);
8904 if ((unsigned long) imm_expr
.X_add_number
> 31)
8906 as_warn (_("Invalid value for `%s' (%lu)"),
8908 (unsigned long) imm_expr
.X_add_number
);
8909 imm_expr
.X_add_number
&= 0x1f;
8912 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8914 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8915 imm_expr
.X_op
= O_absent
;
8919 case 'c': /* break code */
8920 my_getExpression (&imm_expr
, s
);
8921 check_absolute_expr (ip
, &imm_expr
);
8922 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8924 as_warn (_("Illegal break code (%lu)"),
8925 (unsigned long) imm_expr
.X_add_number
);
8926 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8928 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8929 imm_expr
.X_op
= O_absent
;
8933 case 'q': /* lower break code */
8934 my_getExpression (&imm_expr
, s
);
8935 check_absolute_expr (ip
, &imm_expr
);
8936 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8938 as_warn (_("Illegal lower break code (%lu)"),
8939 (unsigned long) imm_expr
.X_add_number
);
8940 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8942 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8943 imm_expr
.X_op
= O_absent
;
8947 case 'B': /* 20-bit syscall/break code. */
8948 my_getExpression (&imm_expr
, s
);
8949 check_absolute_expr (ip
, &imm_expr
);
8950 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8951 as_warn (_("Illegal 20-bit code (%lu)"),
8952 (unsigned long) imm_expr
.X_add_number
);
8953 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8954 imm_expr
.X_op
= O_absent
;
8958 case 'C': /* Coprocessor code */
8959 my_getExpression (&imm_expr
, s
);
8960 check_absolute_expr (ip
, &imm_expr
);
8961 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8963 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8964 (unsigned long) imm_expr
.X_add_number
);
8965 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8967 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8968 imm_expr
.X_op
= O_absent
;
8972 case 'J': /* 19-bit wait code. */
8973 my_getExpression (&imm_expr
, s
);
8974 check_absolute_expr (ip
, &imm_expr
);
8975 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8976 as_warn (_("Illegal 19-bit code (%lu)"),
8977 (unsigned long) imm_expr
.X_add_number
);
8978 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8979 imm_expr
.X_op
= O_absent
;
8983 case 'P': /* Performance register */
8984 my_getExpression (&imm_expr
, s
);
8985 check_absolute_expr (ip
, &imm_expr
);
8986 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8988 as_warn (_("Invalid performance register (%lu)"),
8989 (unsigned long) imm_expr
.X_add_number
);
8990 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8992 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8993 imm_expr
.X_op
= O_absent
;
8997 case 'b': /* base register */
8998 case 'd': /* destination register */
8999 case 's': /* source register */
9000 case 't': /* target register */
9001 case 'r': /* both target and source */
9002 case 'v': /* both dest and source */
9003 case 'w': /* both dest and target */
9004 case 'E': /* coprocessor target register */
9005 case 'G': /* coprocessor destination register */
9006 case 'K': /* 'rdhwr' destination register */
9007 case 'x': /* ignore register name */
9008 case 'z': /* must be zero register */
9009 case 'U': /* destination register (clo/clz). */
9024 while (ISDIGIT (*s
));
9026 as_bad (_("Invalid register number (%d)"), regno
);
9028 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
9032 if (s
[1] == 'r' && s
[2] == 'a')
9037 else if (s
[1] == 'f' && s
[2] == 'p')
9042 else if (s
[1] == 's' && s
[2] == 'p')
9047 else if (s
[1] == 'g' && s
[2] == 'p')
9052 else if (s
[1] == 'a' && s
[2] == 't')
9057 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9062 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9067 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9072 else if (itbl_have_entries
)
9077 p
= s
+ 1; /* advance past '$' */
9078 n
= itbl_get_field (&p
); /* n is name */
9080 /* See if this is a register defined in an
9082 if (itbl_get_reg_val (n
, &r
))
9084 /* Get_field advances to the start of
9085 the next field, so we need to back
9086 rack to the end of the last field. */
9090 s
= strchr (s
, '\0');
9104 as_warn (_("Used $at without \".set noat\""));
9110 if (c
== 'r' || c
== 'v' || c
== 'w')
9117 /* 'z' only matches $0. */
9118 if (c
== 'z' && regno
!= 0)
9121 /* Now that we have assembled one operand, we use the args string
9122 * to figure out where it goes in the instruction. */
9129 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
9134 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
9137 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
9138 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
9143 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
9146 /* This case exists because on the r3000 trunc
9147 expands into a macro which requires a gp
9148 register. On the r6000 or r4000 it is
9149 assembled into a single instruction which
9150 ignores the register. Thus the insn version
9151 is MIPS_ISA2 and uses 'x', and the macro
9152 version is MIPS_ISA1 and uses 't'. */
9155 /* This case is for the div instruction, which
9156 acts differently if the destination argument
9157 is $0. This only matches $0, and is checked
9158 outside the switch. */
9161 /* Itbl operand; not yet implemented. FIXME ?? */
9163 /* What about all other operands like 'i', which
9164 can be specified in the opcode table? */
9174 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
9177 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
9182 case 'O': /* MDMX alignment immediate constant. */
9183 my_getExpression (&imm_expr
, s
);
9184 check_absolute_expr (ip
, &imm_expr
);
9185 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9187 as_warn ("Improper align amount (%ld), using low bits",
9188 (long) imm_expr
.X_add_number
);
9189 imm_expr
.X_add_number
&= OP_MASK_ALN
;
9191 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
9192 imm_expr
.X_op
= O_absent
;
9196 case 'Q': /* MDMX vector, element sel, or const. */
9199 /* MDMX Immediate. */
9200 my_getExpression (&imm_expr
, s
);
9201 check_absolute_expr (ip
, &imm_expr
);
9202 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9204 as_warn (_("Invalid MDMX Immediate (%ld)"),
9205 (long) imm_expr
.X_add_number
);
9206 imm_expr
.X_add_number
&= OP_MASK_FT
;
9208 imm_expr
.X_add_number
&= OP_MASK_FT
;
9209 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9210 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9212 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9213 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
9214 imm_expr
.X_op
= O_absent
;
9218 /* Not MDMX Immediate. Fall through. */
9219 case 'X': /* MDMX destination register. */
9220 case 'Y': /* MDMX source register. */
9221 case 'Z': /* MDMX target register. */
9223 case 'D': /* floating point destination register */
9224 case 'S': /* floating point source register */
9225 case 'T': /* floating point target register */
9226 case 'R': /* floating point source register */
9230 /* Accept $fN for FP and MDMX register numbers, and in
9231 addition accept $vN for MDMX register numbers. */
9232 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
9233 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
9244 while (ISDIGIT (*s
));
9247 as_bad (_("Invalid float register number (%d)"), regno
);
9249 if ((regno
& 1) != 0
9251 && ! (strcmp (str
, "mtc1") == 0
9252 || strcmp (str
, "mfc1") == 0
9253 || strcmp (str
, "lwc1") == 0
9254 || strcmp (str
, "swc1") == 0
9255 || strcmp (str
, "l.s") == 0
9256 || strcmp (str
, "s.s") == 0))
9257 as_warn (_("Float register should be even, was %d"),
9265 if (c
== 'V' || c
== 'W')
9276 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
9281 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
9284 /* This is like 'Z', but also needs to fix the MDMX
9285 vector/scalar select bits. Note that the
9286 scalar immediate case is handled above. */
9289 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9290 int max_el
= (is_qh
? 3 : 7);
9292 my_getExpression(&imm_expr
, s
);
9293 check_absolute_expr (ip
, &imm_expr
);
9295 if (imm_expr
.X_add_number
> max_el
)
9296 as_bad(_("Bad element selector %ld"),
9297 (long) imm_expr
.X_add_number
);
9298 imm_expr
.X_add_number
&= max_el
;
9299 ip
->insn_opcode
|= (imm_expr
.X_add_number
9303 as_warn(_("Expecting ']' found '%s'"), s
);
9309 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9310 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9313 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9320 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
9323 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
9333 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
9336 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
9342 my_getExpression (&imm_expr
, s
);
9343 if (imm_expr
.X_op
!= O_big
9344 && imm_expr
.X_op
!= O_constant
)
9345 insn_error
= _("absolute expression required");
9350 my_getExpression (&offset_expr
, s
);
9351 *imm_reloc
= BFD_RELOC_32
;
9364 unsigned char temp
[8];
9366 unsigned int length
;
9371 /* These only appear as the last operand in an
9372 instruction, and every instruction that accepts
9373 them in any variant accepts them in all variants.
9374 This means we don't have to worry about backing out
9375 any changes if the instruction does not match.
9377 The difference between them is the size of the
9378 floating point constant and where it goes. For 'F'
9379 and 'L' the constant is 64 bits; for 'f' and 'l' it
9380 is 32 bits. Where the constant is placed is based
9381 on how the MIPS assembler does things:
9384 f -- immediate value
9387 The .lit4 and .lit8 sections are only used if
9388 permitted by the -G argument.
9390 When generating embedded PIC code, we use the
9391 .lit8 section but not the .lit4 section (we can do
9392 .lit4 inline easily; we need to put .lit8
9393 somewhere in the data segment, and using .lit8
9394 permits the linker to eventually combine identical
9397 The code below needs to know whether the target register
9398 is 32 or 64 bits wide. It relies on the fact 'f' and
9399 'F' are used with GPR-based instructions and 'l' and
9400 'L' are used with FPR-based instructions. */
9402 f64
= *args
== 'F' || *args
== 'L';
9403 using_gprs
= *args
== 'F' || *args
== 'f';
9405 save_in
= input_line_pointer
;
9406 input_line_pointer
= s
;
9407 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9409 s
= input_line_pointer
;
9410 input_line_pointer
= save_in
;
9411 if (err
!= NULL
&& *err
!= '\0')
9413 as_bad (_("Bad floating point constant: %s"), err
);
9414 memset (temp
, '\0', sizeof temp
);
9415 length
= f64
? 8 : 4;
9418 assert (length
== (unsigned) (f64
? 8 : 4));
9422 && (! USE_GLOBAL_POINTER_OPT
9423 || mips_pic
== EMBEDDED_PIC
9424 || g_switch_value
< 4
9425 || (temp
[0] == 0 && temp
[1] == 0)
9426 || (temp
[2] == 0 && temp
[3] == 0))))
9428 imm_expr
.X_op
= O_constant
;
9429 if (! target_big_endian
)
9430 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9432 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9435 && ! mips_disable_float_construction
9436 /* Constants can only be constructed in GPRs and
9437 copied to FPRs if the GPRs are at least as wide
9438 as the FPRs. Force the constant into memory if
9439 we are using 64-bit FPRs but the GPRs are only
9442 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9443 && ((temp
[0] == 0 && temp
[1] == 0)
9444 || (temp
[2] == 0 && temp
[3] == 0))
9445 && ((temp
[4] == 0 && temp
[5] == 0)
9446 || (temp
[6] == 0 && temp
[7] == 0)))
9448 /* The value is simple enough to load with a couple of
9449 instructions. If using 32-bit registers, set
9450 imm_expr to the high order 32 bits and offset_expr to
9451 the low order 32 bits. Otherwise, set imm_expr to
9452 the entire 64 bit constant. */
9453 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9455 imm_expr
.X_op
= O_constant
;
9456 offset_expr
.X_op
= O_constant
;
9457 if (! target_big_endian
)
9459 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9460 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9464 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9465 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9467 if (offset_expr
.X_add_number
== 0)
9468 offset_expr
.X_op
= O_absent
;
9470 else if (sizeof (imm_expr
.X_add_number
) > 4)
9472 imm_expr
.X_op
= O_constant
;
9473 if (! target_big_endian
)
9474 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9476 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9480 imm_expr
.X_op
= O_big
;
9481 imm_expr
.X_add_number
= 4;
9482 if (! target_big_endian
)
9484 generic_bignum
[0] = bfd_getl16 (temp
);
9485 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9486 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9487 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9491 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9492 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9493 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9494 generic_bignum
[3] = bfd_getb16 (temp
);
9500 const char *newname
;
9503 /* Switch to the right section. */
9505 subseg
= now_subseg
;
9508 default: /* unused default case avoids warnings. */
9510 newname
= RDATA_SECTION_NAME
;
9511 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
9512 || mips_pic
== EMBEDDED_PIC
)
9516 if (mips_pic
== EMBEDDED_PIC
)
9519 newname
= RDATA_SECTION_NAME
;
9522 assert (!USE_GLOBAL_POINTER_OPT
9523 || g_switch_value
>= 4);
9527 new_seg
= subseg_new (newname
, (subsegT
) 0);
9528 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9529 bfd_set_section_flags (stdoutput
, new_seg
,
9534 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9535 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9536 && strcmp (TARGET_OS
, "elf") != 0)
9537 record_alignment (new_seg
, 4);
9539 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9541 as_bad (_("Can't use floating point insn in this section"));
9543 /* Set the argument to the current address in the
9545 offset_expr
.X_op
= O_symbol
;
9546 offset_expr
.X_add_symbol
=
9547 symbol_new ("L0\001", now_seg
,
9548 (valueT
) frag_now_fix (), frag_now
);
9549 offset_expr
.X_add_number
= 0;
9551 /* Put the floating point number into the section. */
9552 p
= frag_more ((int) length
);
9553 memcpy (p
, temp
, length
);
9555 /* Switch back to the original section. */
9556 subseg_set (seg
, subseg
);
9561 case 'i': /* 16 bit unsigned immediate */
9562 case 'j': /* 16 bit signed immediate */
9563 *imm_reloc
= BFD_RELOC_LO16
;
9564 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9567 offsetT minval
, maxval
;
9569 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9570 && strcmp (insn
->name
, insn
[1].name
) == 0);
9572 /* If the expression was written as an unsigned number,
9573 only treat it as signed if there are no more
9577 && sizeof (imm_expr
.X_add_number
) <= 4
9578 && imm_expr
.X_op
== O_constant
9579 && imm_expr
.X_add_number
< 0
9580 && imm_expr
.X_unsigned
9584 /* For compatibility with older assemblers, we accept
9585 0x8000-0xffff as signed 16-bit numbers when only
9586 signed numbers are allowed. */
9588 minval
= 0, maxval
= 0xffff;
9590 minval
= -0x8000, maxval
= 0x7fff;
9592 minval
= -0x8000, maxval
= 0xffff;
9594 if (imm_expr
.X_op
!= O_constant
9595 || imm_expr
.X_add_number
< minval
9596 || imm_expr
.X_add_number
> maxval
)
9600 if (imm_expr
.X_op
== O_constant
9601 || imm_expr
.X_op
== O_big
)
9602 as_bad (_("expression out of range"));
9608 case 'o': /* 16 bit offset */
9609 /* Check whether there is only a single bracketed expression
9610 left. If so, it must be the base register and the
9611 constant must be zero. */
9612 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9614 offset_expr
.X_op
= O_constant
;
9615 offset_expr
.X_add_number
= 0;
9619 /* If this value won't fit into a 16 bit offset, then go
9620 find a macro that will generate the 32 bit offset
9622 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9623 && (offset_expr
.X_op
!= O_constant
9624 || offset_expr
.X_add_number
>= 0x8000
9625 || offset_expr
.X_add_number
< -0x8000))
9631 case 'p': /* pc relative offset */
9632 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9633 my_getExpression (&offset_expr
, s
);
9637 case 'u': /* upper 16 bits */
9638 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9639 && imm_expr
.X_op
== O_constant
9640 && (imm_expr
.X_add_number
< 0
9641 || imm_expr
.X_add_number
>= 0x10000))
9642 as_bad (_("lui expression not in range 0..65535"));
9646 case 'a': /* 26 bit address */
9647 my_getExpression (&offset_expr
, s
);
9649 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9652 case 'N': /* 3 bit branch condition code */
9653 case 'M': /* 3 bit compare condition code */
9654 if (strncmp (s
, "$fcc", 4) != 0)
9664 while (ISDIGIT (*s
));
9666 as_bad (_("invalid condition code register $fcc%d"), regno
);
9668 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9670 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9674 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9685 while (ISDIGIT (*s
));
9688 c
= 8; /* Invalid sel value. */
9691 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9692 ip
->insn_opcode
|= c
;
9696 /* Must be at least one digit. */
9697 my_getExpression (&imm_expr
, s
);
9698 check_absolute_expr (ip
, &imm_expr
);
9700 if ((unsigned long) imm_expr
.X_add_number
9701 > (unsigned long) OP_MASK_VECBYTE
)
9703 as_bad (_("bad byte vector index (%ld)"),
9704 (long) imm_expr
.X_add_number
);
9705 imm_expr
.X_add_number
= 0;
9708 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9709 imm_expr
.X_op
= O_absent
;
9714 my_getExpression (&imm_expr
, s
);
9715 check_absolute_expr (ip
, &imm_expr
);
9717 if ((unsigned long) imm_expr
.X_add_number
9718 > (unsigned long) OP_MASK_VECALIGN
)
9720 as_bad (_("bad byte vector index (%ld)"),
9721 (long) imm_expr
.X_add_number
);
9722 imm_expr
.X_add_number
= 0;
9725 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9726 imm_expr
.X_op
= O_absent
;
9731 as_bad (_("bad char = '%c'\n"), *args
);
9736 /* Args don't match. */
9737 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9738 !strcmp (insn
->name
, insn
[1].name
))
9742 insn_error
= _("illegal operands");
9747 insn_error
= _("illegal operands");
9752 /* This routine assembles an instruction into its binary format when
9753 assembling for the mips16. As a side effect, it sets one of the
9754 global variables imm_reloc or offset_reloc to the type of
9755 relocation to do if one of the operands is an address expression.
9756 It also sets mips16_small and mips16_ext if the user explicitly
9757 requested a small or extended instruction. */
9762 struct mips_cl_insn
*ip
;
9766 struct mips_opcode
*insn
;
9769 unsigned int lastregno
= 0;
9774 mips16_small
= FALSE
;
9777 for (s
= str
; ISLOWER (*s
); ++s
)
9789 if (s
[1] == 't' && s
[2] == ' ')
9792 mips16_small
= TRUE
;
9796 else if (s
[1] == 'e' && s
[2] == ' ')
9805 insn_error
= _("unknown opcode");
9809 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9810 mips16_small
= TRUE
;
9812 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9814 insn_error
= _("unrecognized opcode");
9821 assert (strcmp (insn
->name
, str
) == 0);
9824 ip
->insn_opcode
= insn
->match
;
9825 ip
->use_extend
= FALSE
;
9826 imm_expr
.X_op
= O_absent
;
9827 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9828 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9829 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9830 offset_expr
.X_op
= O_absent
;
9831 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9832 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9833 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9834 for (args
= insn
->args
; 1; ++args
)
9841 /* In this switch statement we call break if we did not find
9842 a match, continue if we did find a match, or return if we
9851 /* Stuff the immediate value in now, if we can. */
9852 if (imm_expr
.X_op
== O_constant
9853 && *imm_reloc
> BFD_RELOC_UNUSED
9854 && insn
->pinfo
!= INSN_MACRO
)
9856 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9857 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9858 mips16_ext
, &ip
->insn_opcode
,
9859 &ip
->use_extend
, &ip
->extend
);
9860 imm_expr
.X_op
= O_absent
;
9861 *imm_reloc
= BFD_RELOC_UNUSED
;
9875 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9878 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9894 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9896 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9923 while (ISDIGIT (*s
));
9926 as_bad (_("invalid register number (%d)"), regno
);
9932 if (s
[1] == 'r' && s
[2] == 'a')
9937 else if (s
[1] == 'f' && s
[2] == 'p')
9942 else if (s
[1] == 's' && s
[2] == 'p')
9947 else if (s
[1] == 'g' && s
[2] == 'p')
9952 else if (s
[1] == 'a' && s
[2] == 't')
9957 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9962 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9967 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9980 if (c
== 'v' || c
== 'w')
9982 regno
= mips16_to_32_reg_map
[lastregno
];
9996 regno
= mips32_to_16_reg_map
[regno
];
10001 regno
= ILLEGAL_REG
;
10006 regno
= ILLEGAL_REG
;
10011 regno
= ILLEGAL_REG
;
10016 if (regno
== AT
&& ! mips_opts
.noat
)
10017 as_warn (_("used $at without \".set noat\""));
10024 if (regno
== ILLEGAL_REG
)
10031 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
10035 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
10038 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
10041 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
10047 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
10050 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10051 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
10061 if (strncmp (s
, "$pc", 3) == 0)
10085 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
10087 /* This is %gprel(SYMBOL). We need to read SYMBOL,
10088 and generate the appropriate reloc. If the text
10089 inside %gprel is not a symbol name with an
10090 optional offset, then we generate a normal reloc
10091 and will probably fail later. */
10092 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
10093 if (imm_expr
.X_op
== O_symbol
)
10096 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
10098 ip
->use_extend
= TRUE
;
10105 /* Just pick up a normal expression. */
10106 my_getExpression (&imm_expr
, s
);
10109 if (imm_expr
.X_op
== O_register
)
10111 /* What we thought was an expression turned out to
10114 if (s
[0] == '(' && args
[1] == '(')
10116 /* It looks like the expression was omitted
10117 before a register indirection, which means
10118 that the expression is implicitly zero. We
10119 still set up imm_expr, so that we handle
10120 explicit extensions correctly. */
10121 imm_expr
.X_op
= O_constant
;
10122 imm_expr
.X_add_number
= 0;
10123 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10130 /* We need to relax this instruction. */
10131 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10140 /* We use offset_reloc rather than imm_reloc for the PC
10141 relative operands. This lets macros with both
10142 immediate and address operands work correctly. */
10143 my_getExpression (&offset_expr
, s
);
10145 if (offset_expr
.X_op
== O_register
)
10148 /* We need to relax this instruction. */
10149 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10153 case '6': /* break code */
10154 my_getExpression (&imm_expr
, s
);
10155 check_absolute_expr (ip
, &imm_expr
);
10156 if ((unsigned long) imm_expr
.X_add_number
> 63)
10158 as_warn (_("Invalid value for `%s' (%lu)"),
10160 (unsigned long) imm_expr
.X_add_number
);
10161 imm_expr
.X_add_number
&= 0x3f;
10163 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
10164 imm_expr
.X_op
= O_absent
;
10168 case 'a': /* 26 bit address */
10169 my_getExpression (&offset_expr
, s
);
10171 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10172 ip
->insn_opcode
<<= 16;
10175 case 'l': /* register list for entry macro */
10176 case 'L': /* register list for exit macro */
10186 int freg
, reg1
, reg2
;
10188 while (*s
== ' ' || *s
== ',')
10192 as_bad (_("can't parse register list"));
10204 while (ISDIGIT (*s
))
10226 as_bad (_("invalid register list"));
10231 while (ISDIGIT (*s
))
10238 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10240 mask
&= ~ (7 << 3);
10243 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10245 mask
&= ~ (7 << 3);
10248 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10249 mask
|= (reg2
- 3) << 3;
10250 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10251 mask
|= (reg2
- 15) << 1;
10252 else if (reg1
== RA
&& reg2
== RA
)
10256 as_bad (_("invalid register list"));
10260 /* The mask is filled in in the opcode table for the
10261 benefit of the disassembler. We remove it before
10262 applying the actual mask. */
10263 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10264 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10268 case 'e': /* extend code */
10269 my_getExpression (&imm_expr
, s
);
10270 check_absolute_expr (ip
, &imm_expr
);
10271 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10273 as_warn (_("Invalid value for `%s' (%lu)"),
10275 (unsigned long) imm_expr
.X_add_number
);
10276 imm_expr
.X_add_number
&= 0x7ff;
10278 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10279 imm_expr
.X_op
= O_absent
;
10289 /* Args don't match. */
10290 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10291 strcmp (insn
->name
, insn
[1].name
) == 0)
10298 insn_error
= _("illegal operands");
10304 /* This structure holds information we know about a mips16 immediate
10307 struct mips16_immed_operand
10309 /* The type code used in the argument string in the opcode table. */
10311 /* The number of bits in the short form of the opcode. */
10313 /* The number of bits in the extended form of the opcode. */
10315 /* The amount by which the short form is shifted when it is used;
10316 for example, the sw instruction has a shift count of 2. */
10318 /* The amount by which the short form is shifted when it is stored
10319 into the instruction code. */
10321 /* Non-zero if the short form is unsigned. */
10323 /* Non-zero if the extended form is unsigned. */
10325 /* Non-zero if the value is PC relative. */
10329 /* The mips16 immediate operand types. */
10331 static const struct mips16_immed_operand mips16_immed_operands
[] =
10333 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10334 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10335 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10336 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10337 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10338 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10339 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10340 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10341 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10342 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10343 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10344 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10345 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10346 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10347 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10348 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10349 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10350 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10351 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10352 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10353 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10356 #define MIPS16_NUM_IMMED \
10357 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10359 /* Handle a mips16 instruction with an immediate value. This or's the
10360 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10361 whether an extended value is needed; if one is needed, it sets
10362 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10363 If SMALL is true, an unextended opcode was explicitly requested.
10364 If EXT is true, an extended opcode was explicitly requested. If
10365 WARN is true, warn if EXT does not match reality. */
10368 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
10377 unsigned long *insn
;
10378 bfd_boolean
*use_extend
;
10379 unsigned short *extend
;
10381 register const struct mips16_immed_operand
*op
;
10382 int mintiny
, maxtiny
;
10383 bfd_boolean needext
;
10385 op
= mips16_immed_operands
;
10386 while (op
->type
!= type
)
10389 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10394 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10397 maxtiny
= 1 << op
->nbits
;
10402 maxtiny
= (1 << op
->nbits
) - 1;
10407 mintiny
= - (1 << (op
->nbits
- 1));
10408 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10411 /* Branch offsets have an implicit 0 in the lowest bit. */
10412 if (type
== 'p' || type
== 'q')
10415 if ((val
& ((1 << op
->shift
) - 1)) != 0
10416 || val
< (mintiny
<< op
->shift
)
10417 || val
> (maxtiny
<< op
->shift
))
10422 if (warn
&& ext
&& ! needext
)
10423 as_warn_where (file
, line
,
10424 _("extended operand requested but not required"));
10425 if (small
&& needext
)
10426 as_bad_where (file
, line
, _("invalid unextended operand value"));
10428 if (small
|| (! ext
&& ! needext
))
10432 *use_extend
= FALSE
;
10433 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10434 insnval
<<= op
->op_shift
;
10439 long minext
, maxext
;
10445 maxext
= (1 << op
->extbits
) - 1;
10449 minext
= - (1 << (op
->extbits
- 1));
10450 maxext
= (1 << (op
->extbits
- 1)) - 1;
10452 if (val
< minext
|| val
> maxext
)
10453 as_bad_where (file
, line
,
10454 _("operand value out of range for instruction"));
10456 *use_extend
= TRUE
;
10457 if (op
->extbits
== 16)
10459 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10462 else if (op
->extbits
== 15)
10464 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10469 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10473 *extend
= (unsigned short) extval
;
10478 static const struct percent_op_match
10481 bfd_reloc_code_real_type reloc
;
10484 {"%lo", BFD_RELOC_LO16
},
10486 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10487 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10488 {"%call16", BFD_RELOC_MIPS_CALL16
},
10489 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10490 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10491 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10492 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10493 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10494 {"%got", BFD_RELOC_MIPS_GOT16
},
10495 {"%gp_rel", BFD_RELOC_GPREL16
},
10496 {"%half", BFD_RELOC_16
},
10497 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10498 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10499 {"%neg", BFD_RELOC_MIPS_SUB
},
10501 {"%hi", BFD_RELOC_HI16_S
}
10505 /* Return true if *STR points to a relocation operator. When returning true,
10506 move *STR over the operator and store its relocation code in *RELOC.
10507 Leave both *STR and *RELOC alone when returning false. */
10510 parse_relocation (str
, reloc
)
10512 bfd_reloc_code_real_type
*reloc
;
10516 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
10517 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10519 *str
+= strlen (percent_op
[i
].str
);
10520 *reloc
= percent_op
[i
].reloc
;
10522 /* Check whether the output BFD supports this relocation.
10523 If not, issue an error and fall back on something safe. */
10524 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10526 as_bad ("relocation %s isn't supported by the current ABI",
10527 percent_op
[i
].str
);
10528 *reloc
= BFD_RELOC_LO16
;
10536 /* Parse string STR as a 16-bit relocatable operand. Store the
10537 expression in *EP and the relocations in the array starting
10538 at RELOC. Return the number of relocation operators used.
10540 On exit, EXPR_END points to the first character after the expression.
10541 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10544 my_getSmallExpression (ep
, reloc
, str
)
10546 bfd_reloc_code_real_type
*reloc
;
10549 bfd_reloc_code_real_type reversed_reloc
[3];
10550 size_t reloc_index
, i
;
10551 int crux_depth
, str_depth
;
10554 /* Search for the start of the main expression, recoding relocations
10555 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10556 of the main expression and with CRUX_DEPTH containing the number
10557 of open brackets at that point. */
10564 crux_depth
= str_depth
;
10566 /* Skip over whitespace and brackets, keeping count of the number
10568 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10573 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10574 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10576 my_getExpression (ep
, crux
);
10579 /* Match every open bracket. */
10580 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10584 if (crux_depth
> 0)
10585 as_bad ("unclosed '('");
10589 if (reloc_index
== 0)
10590 reloc
[0] = BFD_RELOC_LO16
;
10593 prev_reloc_op_frag
= frag_now
;
10594 for (i
= 0; i
< reloc_index
; i
++)
10595 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10598 return reloc_index
;
10602 my_getExpression (ep
, str
)
10609 save_in
= input_line_pointer
;
10610 input_line_pointer
= str
;
10612 expr_end
= input_line_pointer
;
10613 input_line_pointer
= save_in
;
10615 /* If we are in mips16 mode, and this is an expression based on `.',
10616 then we bump the value of the symbol by 1 since that is how other
10617 text symbols are handled. We don't bother to handle complex
10618 expressions, just `.' plus or minus a constant. */
10619 if (mips_opts
.mips16
10620 && ep
->X_op
== O_symbol
10621 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10622 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10623 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10624 && symbol_constant_p (ep
->X_add_symbol
)
10625 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10626 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10629 /* Turn a string in input_line_pointer into a floating point constant
10630 of type TYPE, and store the appropriate bytes in *LITP. The number
10631 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10632 returned, or NULL on OK. */
10635 md_atof (type
, litP
, sizeP
)
10641 LITTLENUM_TYPE words
[4];
10657 return _("bad call to md_atof");
10660 t
= atof_ieee (input_line_pointer
, type
, words
);
10662 input_line_pointer
= t
;
10666 if (! target_big_endian
)
10668 for (i
= prec
- 1; i
>= 0; i
--)
10670 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10676 for (i
= 0; i
< prec
; i
++)
10678 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10687 md_number_to_chars (buf
, val
, n
)
10692 if (target_big_endian
)
10693 number_to_chars_bigendian (buf
, val
, n
);
10695 number_to_chars_littleendian (buf
, val
, n
);
10699 static int support_64bit_objects(void)
10701 const char **list
, **l
;
10704 list
= bfd_target_list ();
10705 for (l
= list
; *l
!= NULL
; l
++)
10707 /* This is traditional mips */
10708 if (strcmp (*l
, "elf64-tradbigmips") == 0
10709 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10711 if (strcmp (*l
, "elf64-bigmips") == 0
10712 || strcmp (*l
, "elf64-littlemips") == 0)
10715 yes
= (*l
!= NULL
);
10719 #endif /* OBJ_ELF */
10721 const char *md_shortopts
= "nO::g::G:";
10723 struct option md_longopts
[] =
10725 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10726 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10727 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10728 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10729 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10730 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10731 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10732 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10733 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10734 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10735 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10736 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10737 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10738 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10739 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10740 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10741 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10742 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10743 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10744 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10745 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10746 {"break", no_argument
, NULL
, OPTION_BREAK
},
10747 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10748 #define OPTION_EB (OPTION_MD_BASE + 11)
10749 {"EB", no_argument
, NULL
, OPTION_EB
},
10750 #define OPTION_EL (OPTION_MD_BASE + 12)
10751 {"EL", no_argument
, NULL
, OPTION_EL
},
10752 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10753 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10754 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10755 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10756 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10757 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10758 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10759 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10760 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10761 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10762 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10763 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10764 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10765 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10766 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10767 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10768 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10769 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10770 {"march", required_argument
, NULL
, OPTION_MARCH
},
10771 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10772 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10773 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10774 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10775 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10776 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10777 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10778 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10779 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10780 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10781 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10782 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10783 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10784 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10785 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10786 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10787 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10788 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10789 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10790 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10791 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10792 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10793 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10794 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10795 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10796 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10797 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10798 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10799 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10800 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10801 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10802 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10803 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10804 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10805 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10806 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10807 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10808 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10809 #define OPTION_MIPS32R2 (OPTION_MD_BASE + 41)
10810 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10812 #define OPTION_ELF_BASE (OPTION_MD_BASE + 42)
10813 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10814 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10815 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10816 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10817 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10818 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10819 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10820 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10821 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10822 #define OPTION_32 (OPTION_ELF_BASE + 4)
10823 {"32", no_argument
, NULL
, OPTION_32
},
10824 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10825 {"n32", no_argument
, NULL
, OPTION_N32
},
10826 #define OPTION_64 (OPTION_ELF_BASE + 6)
10827 {"64", no_argument
, NULL
, OPTION_64
},
10828 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10829 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10830 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10831 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10832 #endif /* OBJ_ELF */
10833 {NULL
, no_argument
, NULL
, 0}
10835 size_t md_longopts_size
= sizeof (md_longopts
);
10837 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10838 NEW_VALUE. Warn if another value was already specified. Note:
10839 we have to defer parsing the -march and -mtune arguments in order
10840 to handle 'from-abi' correctly, since the ABI might be specified
10841 in a later argument. */
10844 mips_set_option_string (string_ptr
, new_value
)
10845 const char **string_ptr
, *new_value
;
10847 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10848 as_warn (_("A different %s was already specified, is now %s"),
10849 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10852 *string_ptr
= new_value
;
10856 md_parse_option (c
, arg
)
10862 case OPTION_CONSTRUCT_FLOATS
:
10863 mips_disable_float_construction
= 0;
10866 case OPTION_NO_CONSTRUCT_FLOATS
:
10867 mips_disable_float_construction
= 1;
10879 target_big_endian
= 1;
10883 target_big_endian
= 0;
10891 if (arg
&& arg
[1] == '0')
10901 mips_debug
= atoi (arg
);
10902 /* When the MIPS assembler sees -g or -g2, it does not do
10903 optimizations which limit full symbolic debugging. We take
10904 that to be equivalent to -O0. */
10905 if (mips_debug
== 2)
10910 file_mips_isa
= ISA_MIPS1
;
10914 file_mips_isa
= ISA_MIPS2
;
10918 file_mips_isa
= ISA_MIPS3
;
10922 file_mips_isa
= ISA_MIPS4
;
10926 file_mips_isa
= ISA_MIPS5
;
10929 case OPTION_MIPS32
:
10930 file_mips_isa
= ISA_MIPS32
;
10933 case OPTION_MIPS32R2
:
10934 file_mips_isa
= ISA_MIPS32R2
;
10937 case OPTION_MIPS64
:
10938 file_mips_isa
= ISA_MIPS64
;
10942 mips_set_option_string (&mips_tune_string
, arg
);
10946 mips_set_option_string (&mips_arch_string
, arg
);
10950 mips_set_option_string (&mips_arch_string
, "4650");
10951 mips_set_option_string (&mips_tune_string
, "4650");
10954 case OPTION_NO_M4650
:
10958 mips_set_option_string (&mips_arch_string
, "4010");
10959 mips_set_option_string (&mips_tune_string
, "4010");
10962 case OPTION_NO_M4010
:
10966 mips_set_option_string (&mips_arch_string
, "4100");
10967 mips_set_option_string (&mips_tune_string
, "4100");
10970 case OPTION_NO_M4100
:
10974 mips_set_option_string (&mips_arch_string
, "3900");
10975 mips_set_option_string (&mips_tune_string
, "3900");
10978 case OPTION_NO_M3900
:
10982 mips_opts
.ase_mdmx
= 1;
10985 case OPTION_NO_MDMX
:
10986 mips_opts
.ase_mdmx
= 0;
10989 case OPTION_MIPS16
:
10990 mips_opts
.mips16
= 1;
10991 mips_no_prev_insn (FALSE
);
10994 case OPTION_NO_MIPS16
:
10995 mips_opts
.mips16
= 0;
10996 mips_no_prev_insn (FALSE
);
10999 case OPTION_MIPS3D
:
11000 mips_opts
.ase_mips3d
= 1;
11003 case OPTION_NO_MIPS3D
:
11004 mips_opts
.ase_mips3d
= 0;
11007 case OPTION_MEMBEDDED_PIC
:
11008 mips_pic
= EMBEDDED_PIC
;
11009 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
11011 as_bad (_("-G may not be used with embedded PIC code"));
11014 g_switch_value
= 0x7fffffff;
11017 case OPTION_FIX_VR4122
:
11018 mips_fix_4122_bugs
= 1;
11021 case OPTION_NO_FIX_VR4122
:
11022 mips_fix_4122_bugs
= 0;
11025 case OPTION_RELAX_BRANCH
:
11026 mips_relax_branch
= 1;
11029 case OPTION_NO_RELAX_BRANCH
:
11030 mips_relax_branch
= 0;
11034 /* When generating ELF code, we permit -KPIC and -call_shared to
11035 select SVR4_PIC, and -non_shared to select no PIC. This is
11036 intended to be compatible with Irix 5. */
11037 case OPTION_CALL_SHARED
:
11038 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11040 as_bad (_("-call_shared is supported only for ELF format"));
11043 mips_pic
= SVR4_PIC
;
11044 mips_abicalls
= TRUE
;
11045 if (g_switch_seen
&& g_switch_value
!= 0)
11047 as_bad (_("-G may not be used with SVR4 PIC code"));
11050 g_switch_value
= 0;
11053 case OPTION_NON_SHARED
:
11054 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11056 as_bad (_("-non_shared is supported only for ELF format"));
11060 mips_abicalls
= FALSE
;
11063 /* The -xgot option tells the assembler to use 32 offsets when
11064 accessing the got in SVR4_PIC mode. It is for Irix
11069 #endif /* OBJ_ELF */
11072 if (! USE_GLOBAL_POINTER_OPT
)
11074 as_bad (_("-G is not supported for this configuration"));
11077 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
11079 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
11083 g_switch_value
= atoi (arg
);
11088 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11091 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11093 as_bad (_("-32 is supported for ELF format only"));
11096 mips_abi
= O32_ABI
;
11100 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11102 as_bad (_("-n32 is supported for ELF format only"));
11105 mips_abi
= N32_ABI
;
11109 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11111 as_bad (_("-64 is supported for ELF format only"));
11114 mips_abi
= N64_ABI
;
11115 if (! support_64bit_objects())
11116 as_fatal (_("No compiled in support for 64 bit object file format"));
11118 #endif /* OBJ_ELF */
11121 file_mips_gp32
= 1;
11125 file_mips_gp32
= 0;
11129 file_mips_fp32
= 1;
11133 file_mips_fp32
= 0;
11138 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11140 as_bad (_("-mabi is supported for ELF format only"));
11143 if (strcmp (arg
, "32") == 0)
11144 mips_abi
= O32_ABI
;
11145 else if (strcmp (arg
, "o64") == 0)
11146 mips_abi
= O64_ABI
;
11147 else if (strcmp (arg
, "n32") == 0)
11148 mips_abi
= N32_ABI
;
11149 else if (strcmp (arg
, "64") == 0)
11151 mips_abi
= N64_ABI
;
11152 if (! support_64bit_objects())
11153 as_fatal (_("No compiled in support for 64 bit object file "
11156 else if (strcmp (arg
, "eabi") == 0)
11157 mips_abi
= EABI_ABI
;
11160 as_fatal (_("invalid abi -mabi=%s"), arg
);
11164 #endif /* OBJ_ELF */
11166 case OPTION_M7000_HILO_FIX
:
11167 mips_7000_hilo_fix
= TRUE
;
11170 case OPTION_MNO_7000_HILO_FIX
:
11171 mips_7000_hilo_fix
= FALSE
;
11175 case OPTION_MDEBUG
:
11176 mips_flag_mdebug
= TRUE
;
11179 case OPTION_NO_MDEBUG
:
11180 mips_flag_mdebug
= FALSE
;
11182 #endif /* OBJ_ELF */
11191 /* Set up globals to generate code for the ISA or processor
11192 described by INFO. */
11195 mips_set_architecture (info
)
11196 const struct mips_cpu_info
*info
;
11200 mips_arch_info
= info
;
11201 mips_arch
= info
->cpu
;
11202 mips_opts
.isa
= info
->isa
;
11207 /* Likewise for tuning. */
11210 mips_set_tune (info
)
11211 const struct mips_cpu_info
*info
;
11215 mips_tune_info
= info
;
11216 mips_tune
= info
->cpu
;
11222 mips_after_parse_args ()
11224 /* GP relative stuff not working for PE */
11225 if (strncmp (TARGET_OS
, "pe", 2) == 0
11226 && g_switch_value
!= 0)
11229 as_bad (_("-G not supported in this configuration."));
11230 g_switch_value
= 0;
11233 if (mips_abi
== NO_ABI
)
11234 mips_abi
= MIPS_DEFAULT_ABI
;
11236 /* The following code determines the architecture and register size.
11237 Similar code was added to GCC 3.3 (see override_options() in
11238 config/mips/mips.c). The GAS and GCC code should be kept in sync
11239 as much as possible. */
11241 if (mips_arch_string
!= 0)
11242 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
11244 if (mips_tune_string
!= 0)
11245 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
11247 if (file_mips_isa
!= ISA_UNKNOWN
)
11249 /* Handle -mipsN. At this point, file_mips_isa contains the
11250 ISA level specified by -mipsN, while mips_opts.isa contains
11251 the -march selection (if any). */
11252 if (mips_arch_info
!= 0)
11254 /* -march takes precedence over -mipsN, since it is more descriptive.
11255 There's no harm in specifying both as long as the ISA levels
11257 if (file_mips_isa
!= mips_opts
.isa
)
11258 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11259 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11260 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11263 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
11266 if (mips_arch_info
== 0)
11267 mips_set_architecture (mips_parse_cpu ("default CPU",
11268 MIPS_CPU_STRING_DEFAULT
));
11270 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11271 as_bad ("-march=%s is not compatible with the selected ABI",
11272 mips_arch_info
->name
);
11274 /* Optimize for mips_arch, unless -mtune selects a different processor. */
11275 if (mips_tune_info
== 0)
11276 mips_set_tune (mips_arch_info
);
11278 if (file_mips_gp32
>= 0)
11280 /* The user specified the size of the integer registers. Make sure
11281 it agrees with the ABI and ISA. */
11282 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11283 as_bad (_("-mgp64 used with a 32-bit processor"));
11284 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11285 as_bad (_("-mgp32 used with a 64-bit ABI"));
11286 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11287 as_bad (_("-mgp64 used with a 32-bit ABI"));
11291 /* Infer the integer register size from the ABI and processor.
11292 Restrict ourselves to 32-bit registers if that's all the
11293 processor has, or if the ABI cannot handle 64-bit registers. */
11294 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11295 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11298 /* ??? GAS treats single-float processors as though they had 64-bit
11299 float registers (although it complains when double-precision
11300 instructions are used). As things stand, saying they have 32-bit
11301 registers would lead to spurious "register must be even" messages.
11302 So here we assume float registers are always the same size as
11303 integer ones, unless the user says otherwise. */
11304 if (file_mips_fp32
< 0)
11305 file_mips_fp32
= file_mips_gp32
;
11307 /* End of GCC-shared inference code. */
11309 /* ??? When do we want this flag to be set? Who uses it? */
11310 if (file_mips_gp32
== 1
11311 && mips_abi
== NO_ABI
11312 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11313 mips_32bitmode
= 1;
11315 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11316 as_bad (_("trap exception not supported at ISA 1"));
11318 /* If the selected architecture includes support for ASEs, enable
11319 generation of code for them. */
11320 if (mips_opts
.mips16
== -1)
11321 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
11322 if (mips_opts
.ase_mips3d
== -1)
11323 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
11324 if (mips_opts
.ase_mdmx
== -1)
11325 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
11327 file_mips_isa
= mips_opts
.isa
;
11328 file_ase_mips16
= mips_opts
.mips16
;
11329 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11330 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11331 mips_opts
.gp32
= file_mips_gp32
;
11332 mips_opts
.fp32
= file_mips_fp32
;
11334 if (mips_flag_mdebug
< 0)
11336 #ifdef OBJ_MAYBE_ECOFF
11337 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11338 mips_flag_mdebug
= 1;
11340 #endif /* OBJ_MAYBE_ECOFF */
11341 mips_flag_mdebug
= 0;
11346 mips_init_after_args ()
11348 /* initialize opcodes */
11349 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11350 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11354 md_pcrel_from (fixP
)
11357 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
11358 && fixP
->fx_addsy
!= (symbolS
*) NULL
11359 && ! S_IS_DEFINED (fixP
->fx_addsy
))
11362 /* Return the address of the delay slot. */
11363 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11366 /* This is called before the symbol table is processed. In order to
11367 work with gcc when using mips-tfile, we must keep all local labels.
11368 However, in other cases, we want to discard them. If we were
11369 called with -g, but we didn't see any debugging information, it may
11370 mean that gcc is smuggling debugging information through to
11371 mips-tfile, in which case we must generate all local labels. */
11374 mips_frob_file_before_adjust ()
11376 #ifndef NO_ECOFF_DEBUGGING
11377 if (ECOFF_DEBUGGING
11379 && ! ecoff_debugging_seen
)
11380 flag_keep_locals
= 1;
11384 /* Sort any unmatched HI16_S relocs so that they immediately precede
11385 the corresponding LO reloc. This is called before md_apply_fix3 and
11386 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11387 explicit use of the %hi modifier. */
11392 struct mips_hi_fixup
*l
;
11394 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11396 segment_info_type
*seginfo
;
11399 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11401 /* If a GOT16 relocation turns out to be against a global symbol,
11402 there isn't supposed to be a matching LO. */
11403 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11404 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11407 /* Check quickly whether the next fixup happens to be a matching %lo. */
11408 if (fixup_has_matching_lo_p (l
->fixp
))
11411 /* Look through the fixups for this segment for a matching %lo.
11412 When we find one, move the %hi just in front of it. We do
11413 this in two passes. In the first pass, we try to find a
11414 unique %lo. In the second pass, we permit multiple %hi
11415 relocs for a single %lo (this is a GNU extension). */
11416 seginfo
= seg_info (l
->seg
);
11417 for (pass
= 0; pass
< 2; pass
++)
11422 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
11424 /* Check whether this is a %lo fixup which matches l->fixp. */
11425 if (f
->fx_r_type
== BFD_RELOC_LO16
11426 && f
->fx_addsy
== l
->fixp
->fx_addsy
11427 && f
->fx_offset
== l
->fixp
->fx_offset
11430 || !reloc_needs_lo_p (prev
->fx_r_type
)
11431 || !fixup_has_matching_lo_p (prev
)))
11435 /* Move l->fixp before f. */
11436 for (pf
= &seginfo
->fix_root
;
11438 pf
= &(*pf
)->fx_next
)
11439 assert (*pf
!= NULL
);
11441 *pf
= l
->fixp
->fx_next
;
11443 l
->fixp
->fx_next
= f
;
11445 seginfo
->fix_root
= l
->fixp
;
11447 prev
->fx_next
= l
->fixp
;
11458 #if 0 /* GCC code motion plus incomplete dead code elimination
11459 can leave a %hi without a %lo. */
11461 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
11462 _("Unmatched %%hi reloc"));
11468 /* When generating embedded PIC code we need to use a special
11469 relocation to represent the difference of two symbols in the .text
11470 section (switch tables use a difference of this sort). See
11471 include/coff/mips.h for details. This macro checks whether this
11472 fixup requires the special reloc. */
11473 #define SWITCH_TABLE(fixp) \
11474 ((fixp)->fx_r_type == BFD_RELOC_32 \
11475 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11476 && (fixp)->fx_addsy != NULL \
11477 && (fixp)->fx_subsy != NULL \
11478 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11479 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11481 /* When generating embedded PIC code we must keep all PC relative
11482 relocations, in case the linker has to relax a call. We also need
11483 to keep relocations for switch table entries.
11485 We may have combined relocations without symbols in the N32/N64 ABI.
11486 We have to prevent gas from dropping them. */
11489 mips_force_relocation (fixp
)
11492 if (generic_force_reloc (fixp
))
11496 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11497 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11498 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11499 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11502 return (mips_pic
== EMBEDDED_PIC
11504 || SWITCH_TABLE (fixp
)
11505 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
11506 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
11509 /* This hook is called before a fix is simplified. We don't really
11510 decide whether to skip a fix here. Rather, we turn global symbols
11511 used as branch targets into local symbols, such that they undergo
11512 simplification. We can only do this if the symbol is defined and
11513 it is in the same section as the branch. If this doesn't hold, we
11514 emit a better error message than just saying the relocation is not
11515 valid for the selected object format.
11517 FIXP is the fix-up we're going to try to simplify, SEG is the
11518 segment in which the fix up occurs. The return value should be
11519 non-zero to indicate the fix-up is valid for further
11520 simplifications. */
11523 mips_validate_fix (fixP
, seg
)
11527 /* There's a lot of discussion on whether it should be possible to
11528 use R_MIPS_PC16 to represent branch relocations. The outcome
11529 seems to be that it can, but gas/bfd are very broken in creating
11530 RELA relocations for this, so for now we only accept branches to
11531 symbols in the same section. Anything else is of dubious value,
11532 since there's no guarantee that at link time the symbol would be
11533 in range. Even for branches to local symbols this is arguably
11534 wrong, since it we assume the symbol is not going to be
11535 overridden, which should be possible per ELF library semantics,
11536 but then, there isn't a dynamic relocation that could be used to
11537 this effect, and the target would likely be out of range as well.
11539 Unfortunately, it seems that there is too much code out there
11540 that relies on branches to symbols that are global to be resolved
11541 as if they were local, like the IRIX tools do, so we do it as
11542 well, but with a warning so that people are reminded to fix their
11543 code. If we ever get back to using R_MIPS_PC16 for branch
11544 targets, this entire block should go away (and probably the
11545 whole function). */
11547 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11548 && (((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11549 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11550 && mips_pic
!= EMBEDDED_PIC
)
11551 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11554 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11557 _("Cannot branch to undefined symbol."));
11558 /* Avoid any further errors about this fixup. */
11561 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11564 _("Cannot branch to symbol in another section."));
11567 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11569 symbolS
*sym
= fixP
->fx_addsy
;
11571 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11572 _("Pretending global symbol used as branch target is local."));
11574 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11575 S_GET_SEGMENT (sym
),
11577 symbol_get_frag (sym
));
11578 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11579 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11580 assert (symbol_resolved_p (sym
));
11581 symbol_mark_resolved (fixP
->fx_addsy
);
11590 mips_need_elf_addend_fixup (fixP
)
11593 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
11595 if (mips_pic
== EMBEDDED_PIC
11596 && S_IS_WEAK (fixP
->fx_addsy
))
11598 if (mips_pic
!= EMBEDDED_PIC
11599 && (S_IS_WEAK (fixP
->fx_addsy
)
11600 || S_IS_EXTERNAL (fixP
->fx_addsy
))
11601 && !S_IS_COMMON (fixP
->fx_addsy
))
11603 if (((bfd_get_section_flags (stdoutput
,
11604 S_GET_SEGMENT (fixP
->fx_addsy
))
11605 & (SEC_LINK_ONCE
| SEC_MERGE
)) != 0)
11606 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
11608 sizeof (".gnu.linkonce") - 1))
11614 /* Apply a fixup to the object file. */
11617 md_apply_fix3 (fixP
, valP
, seg
)
11620 segT seg ATTRIBUTE_UNUSED
;
11625 static int previous_fx_r_type
= 0;
11627 /* FIXME: Maybe just return for all reloc types not listed below?
11628 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
11629 if (fixP
->fx_r_type
== BFD_RELOC_8
)
11632 assert (fixP
->fx_size
== 4
11633 || fixP
->fx_r_type
== BFD_RELOC_16
11634 || fixP
->fx_r_type
== BFD_RELOC_32
11635 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
11636 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
11637 || fixP
->fx_r_type
== BFD_RELOC_LO16
11638 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
11639 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
11640 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
11641 || fixP
->fx_r_type
== BFD_RELOC_64
11642 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11643 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11644 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
11645 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
11646 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
11647 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
11648 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
11649 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11650 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11651 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
11655 /* If we aren't adjusting this fixup to be against the section
11656 symbol, we need to adjust the value. */
11658 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11660 if (mips_need_elf_addend_fixup (fixP
))
11662 reloc_howto_type
*howto
;
11663 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
11667 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11668 if (value
!= 0 && howto
&& howto
->partial_inplace
)
11670 /* In this case, the bfd_install_relocation routine will
11671 incorrectly add the symbol value back in. We just want
11672 the addend to appear in the object file.
11674 The condition above used to include
11675 "&& (! fixP->fx_pcrel || howto->pcrel_offset)".
11677 However, howto can't be trusted here, because we
11678 might change the reloc type in tc_gen_reloc. We can
11679 check howto->partial_inplace because that conversion
11680 happens to preserve howto->partial_inplace; but it
11681 does not preserve howto->pcrel_offset. I've just
11682 eliminated the check, because all MIPS PC-relative
11683 relocations are marked howto->pcrel_offset.
11685 howto->pcrel_offset was originally added for
11686 R_MIPS_PC16, which is generated for code like
11697 /* Make sure the addend is still non-zero. If it became zero
11698 after the last operation, set it to a spurious value and
11699 subtract the same value from the object file's contents. */
11704 /* The in-place addends for LO16 relocations are signed;
11705 leave the matching HI16 in-place addends as zero. */
11706 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
11708 bfd_vma contents
, mask
, field
;
11710 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
11713 target_big_endian
);
11715 /* MASK has bits set where the relocation should go.
11716 FIELD is -value, shifted into the appropriate place
11717 for this relocation. */
11718 mask
= 1 << (howto
->bitsize
- 1);
11719 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
11720 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
11722 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
11723 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11725 target_big_endian
);
11731 /* This code was generated using trial and error and so is
11732 fragile and not trustworthy. If you change it, you should
11733 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11734 they still pass. */
11735 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
11737 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11739 /* BFD's REL handling, for MIPS, is _very_ weird.
11740 This gives the right results, but it can't possibly
11741 be the way things are supposed to work. */
11742 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11743 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
11744 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11749 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
11751 /* We are not done if this is a composite relocation to set up gp. */
11752 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11753 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11754 || (fixP
->fx_r_type
== BFD_RELOC_64
11755 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11756 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11757 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11758 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11759 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11761 previous_fx_r_type
= fixP
->fx_r_type
;
11763 switch (fixP
->fx_r_type
)
11765 case BFD_RELOC_MIPS_JMP
:
11766 case BFD_RELOC_MIPS_SHIFT5
:
11767 case BFD_RELOC_MIPS_SHIFT6
:
11768 case BFD_RELOC_MIPS_GOT_DISP
:
11769 case BFD_RELOC_MIPS_GOT_PAGE
:
11770 case BFD_RELOC_MIPS_GOT_OFST
:
11771 case BFD_RELOC_MIPS_SUB
:
11772 case BFD_RELOC_MIPS_INSERT_A
:
11773 case BFD_RELOC_MIPS_INSERT_B
:
11774 case BFD_RELOC_MIPS_DELETE
:
11775 case BFD_RELOC_MIPS_HIGHEST
:
11776 case BFD_RELOC_MIPS_HIGHER
:
11777 case BFD_RELOC_MIPS_SCN_DISP
:
11778 case BFD_RELOC_MIPS_REL16
:
11779 case BFD_RELOC_MIPS_RELGOT
:
11780 case BFD_RELOC_MIPS_JALR
:
11781 case BFD_RELOC_HI16
:
11782 case BFD_RELOC_HI16_S
:
11783 case BFD_RELOC_GPREL16
:
11784 case BFD_RELOC_MIPS_LITERAL
:
11785 case BFD_RELOC_MIPS_CALL16
:
11786 case BFD_RELOC_MIPS_GOT16
:
11787 case BFD_RELOC_GPREL32
:
11788 case BFD_RELOC_MIPS_GOT_HI16
:
11789 case BFD_RELOC_MIPS_GOT_LO16
:
11790 case BFD_RELOC_MIPS_CALL_HI16
:
11791 case BFD_RELOC_MIPS_CALL_LO16
:
11792 case BFD_RELOC_MIPS16_GPREL
:
11793 if (fixP
->fx_pcrel
)
11794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11795 _("Invalid PC relative reloc"));
11796 /* Nothing needed to do. The value comes from the reloc entry */
11799 case BFD_RELOC_MIPS16_JMP
:
11800 /* We currently always generate a reloc against a symbol, which
11801 means that we don't want an addend even if the symbol is
11803 fixP
->fx_addnumber
= 0;
11806 case BFD_RELOC_PCREL_HI16_S
:
11807 /* The addend for this is tricky if it is internal, so we just
11808 do everything here rather than in bfd_install_relocation. */
11809 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11814 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11816 /* For an external symbol adjust by the address to make it
11817 pcrel_offset. We use the address of the RELLO reloc
11818 which follows this one. */
11819 value
+= (fixP
->fx_next
->fx_frag
->fr_address
11820 + fixP
->fx_next
->fx_where
);
11822 value
= ((value
+ 0x8000) >> 16) & 0xffff;
11823 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11824 if (target_big_endian
)
11826 md_number_to_chars ((char *) buf
, value
, 2);
11829 case BFD_RELOC_PCREL_LO16
:
11830 /* The addend for this is tricky if it is internal, so we just
11831 do everything here rather than in bfd_install_relocation. */
11832 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11837 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11838 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11839 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11840 if (target_big_endian
)
11842 md_number_to_chars ((char *) buf
, value
, 2);
11846 /* This is handled like BFD_RELOC_32, but we output a sign
11847 extended value if we are only 32 bits. */
11849 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11851 if (8 <= sizeof (valueT
))
11852 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11859 w1
= w2
= fixP
->fx_where
;
11860 if (target_big_endian
)
11864 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
11865 if ((value
& 0x80000000) != 0)
11869 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
11874 case BFD_RELOC_RVA
:
11876 /* If we are deleting this reloc entry, we must fill in the
11877 value now. This can happen if we have a .word which is not
11878 resolved when it appears but is later defined. We also need
11879 to fill in the value if this is an embedded PIC switch table
11882 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11883 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11888 /* If we are deleting this reloc entry, we must fill in the
11890 assert (fixP
->fx_size
== 2);
11892 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11896 case BFD_RELOC_LO16
:
11897 /* When handling an embedded PIC switch statement, we can wind
11898 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11901 if (value
+ 0x8000 > 0xffff)
11902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11903 _("relocation overflow"));
11904 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11905 if (target_big_endian
)
11907 md_number_to_chars ((char *) buf
, value
, 2);
11911 case BFD_RELOC_16_PCREL_S2
:
11912 if ((value
& 0x3) != 0)
11913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11914 _("Branch to odd address (%lx)"), (long) value
);
11917 * We need to save the bits in the instruction since fixup_segment()
11918 * might be deleting the relocation entry (i.e., a branch within
11919 * the current segment).
11921 if (!fixP
->fx_done
&& (value
!= 0 || HAVE_NEWABI
))
11923 /* If 'value' is zero, the remaining reloc code won't actually
11924 do the store, so it must be done here. This is probably
11925 a bug somewhere. */
11927 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11928 || fixP
->fx_addsy
== NULL
/* ??? */
11929 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
11930 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11932 value
= (offsetT
) value
>> 2;
11934 /* update old instruction data */
11935 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11936 if (target_big_endian
)
11937 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11939 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11941 if (value
+ 0x8000 <= 0xffff)
11942 insn
|= value
& 0xffff;
11945 /* The branch offset is too large. If this is an
11946 unconditional branch, and we are not generating PIC code,
11947 we can convert it to an absolute jump instruction. */
11948 if (mips_pic
== NO_PIC
11950 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11951 && (fixP
->fx_frag
->fr_address
11952 < text_section
->vma
+ text_section
->_raw_size
)
11953 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11954 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11955 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11957 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11958 insn
= 0x0c000000; /* jal */
11960 insn
= 0x08000000; /* j */
11961 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11963 fixP
->fx_addsy
= section_symbol (text_section
);
11964 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11968 /* If we got here, we have branch-relaxation disabled,
11969 and there's nothing we can do to fix this instruction
11970 without turning it into a longer sequence. */
11971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11972 _("Branch out of range"));
11976 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11979 case BFD_RELOC_VTABLE_INHERIT
:
11982 && !S_IS_DEFINED (fixP
->fx_addsy
)
11983 && !S_IS_WEAK (fixP
->fx_addsy
))
11984 S_SET_WEAK (fixP
->fx_addsy
);
11987 case BFD_RELOC_VTABLE_ENTRY
:
12001 const struct mips_opcode
*p
;
12002 int treg
, sreg
, dreg
, shamt
;
12007 for (i
= 0; i
< NUMOPCODES
; ++i
)
12009 p
= &mips_opcodes
[i
];
12010 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
12012 printf ("%08lx %s\t", oc
, p
->name
);
12013 treg
= (oc
>> 16) & 0x1f;
12014 sreg
= (oc
>> 21) & 0x1f;
12015 dreg
= (oc
>> 11) & 0x1f;
12016 shamt
= (oc
>> 6) & 0x1f;
12018 for (args
= p
->args
;; ++args
)
12029 printf ("%c", *args
);
12033 assert (treg
== sreg
);
12034 printf ("$%d,$%d", treg
, sreg
);
12039 printf ("$%d", dreg
);
12044 printf ("$%d", treg
);
12048 printf ("0x%x", treg
);
12053 printf ("$%d", sreg
);
12057 printf ("0x%08lx", oc
& 0x1ffffff);
12064 printf ("%d", imm
);
12069 printf ("$%d", shamt
);
12080 printf (_("%08lx UNDEFINED\n"), oc
);
12091 name
= input_line_pointer
;
12092 c
= get_symbol_end ();
12093 p
= (symbolS
*) symbol_find_or_make (name
);
12094 *input_line_pointer
= c
;
12098 /* Align the current frag to a given power of two. The MIPS assembler
12099 also automatically adjusts any preceding label. */
12102 mips_align (to
, fill
, label
)
12107 mips_emit_delays (FALSE
);
12108 frag_align (to
, fill
, 0);
12109 record_alignment (now_seg
, to
);
12112 assert (S_GET_SEGMENT (label
) == now_seg
);
12113 symbol_set_frag (label
, frag_now
);
12114 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12118 /* Align to a given power of two. .align 0 turns off the automatic
12119 alignment used by the data creating pseudo-ops. */
12123 int x ATTRIBUTE_UNUSED
;
12126 register long temp_fill
;
12127 long max_alignment
= 15;
12131 o Note that the assembler pulls down any immediately preceeding label
12132 to the aligned address.
12133 o It's not documented but auto alignment is reinstated by
12134 a .align pseudo instruction.
12135 o Note also that after auto alignment is turned off the mips assembler
12136 issues an error on attempt to assemble an improperly aligned data item.
12141 temp
= get_absolute_expression ();
12142 if (temp
> max_alignment
)
12143 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12146 as_warn (_("Alignment negative: 0 assumed."));
12149 if (*input_line_pointer
== ',')
12151 ++input_line_pointer
;
12152 temp_fill
= get_absolute_expression ();
12159 mips_align (temp
, (int) temp_fill
,
12160 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
12167 demand_empty_rest_of_line ();
12171 mips_flush_pending_output ()
12173 mips_emit_delays (FALSE
);
12174 mips_clear_insn_labels ();
12183 /* When generating embedded PIC code, we only use the .text, .lit8,
12184 .sdata and .sbss sections. We change the .data and .rdata
12185 pseudo-ops to use .sdata. */
12186 if (mips_pic
== EMBEDDED_PIC
12187 && (sec
== 'd' || sec
== 'r'))
12191 /* The ELF backend needs to know that we are changing sections, so
12192 that .previous works correctly. We could do something like check
12193 for an obj_section_change_hook macro, but that might be confusing
12194 as it would not be appropriate to use it in the section changing
12195 functions in read.c, since obj-elf.c intercepts those. FIXME:
12196 This should be cleaner, somehow. */
12197 obj_elf_section_change_hook ();
12200 mips_emit_delays (FALSE
);
12210 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12211 demand_empty_rest_of_line ();
12215 if (USE_GLOBAL_POINTER_OPT
)
12217 seg
= subseg_new (RDATA_SECTION_NAME
,
12218 (subsegT
) get_absolute_expression ());
12219 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12221 bfd_set_section_flags (stdoutput
, seg
,
12227 if (strcmp (TARGET_OS
, "elf") != 0)
12228 record_alignment (seg
, 4);
12230 demand_empty_rest_of_line ();
12234 as_bad (_("No read only data section in this object file format"));
12235 demand_empty_rest_of_line ();
12241 if (USE_GLOBAL_POINTER_OPT
)
12243 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12244 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12246 bfd_set_section_flags (stdoutput
, seg
,
12247 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
12249 if (strcmp (TARGET_OS
, "elf") != 0)
12250 record_alignment (seg
, 4);
12252 demand_empty_rest_of_line ();
12257 as_bad (_("Global pointers not supported; recompile -G 0"));
12258 demand_empty_rest_of_line ();
12267 s_change_section (ignore
)
12268 int ignore ATTRIBUTE_UNUSED
;
12271 char *section_name
;
12276 int section_entry_size
;
12277 int section_alignment
;
12279 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12282 section_name
= input_line_pointer
;
12283 c
= get_symbol_end ();
12285 next_c
= *(input_line_pointer
+ 1);
12287 /* Do we have .section Name<,"flags">? */
12288 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12290 /* just after name is now '\0'. */
12291 *input_line_pointer
= c
;
12292 input_line_pointer
= section_name
;
12293 obj_elf_section (ignore
);
12296 input_line_pointer
++;
12298 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12300 section_type
= get_absolute_expression ();
12303 if (*input_line_pointer
++ == ',')
12304 section_flag
= get_absolute_expression ();
12307 if (*input_line_pointer
++ == ',')
12308 section_entry_size
= get_absolute_expression ();
12310 section_entry_size
= 0;
12311 if (*input_line_pointer
++ == ',')
12312 section_alignment
= get_absolute_expression ();
12314 section_alignment
= 0;
12316 section_name
= xstrdup (section_name
);
12318 obj_elf_change_section (section_name
, section_type
, section_flag
,
12319 section_entry_size
, 0, 0, 0);
12321 if (now_seg
->name
!= section_name
)
12322 free (section_name
);
12323 #endif /* OBJ_ELF */
12327 mips_enable_auto_align ()
12338 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12339 mips_emit_delays (FALSE
);
12340 if (log_size
> 0 && auto_align
)
12341 mips_align (log_size
, 0, label
);
12342 mips_clear_insn_labels ();
12343 cons (1 << log_size
);
12347 s_float_cons (type
)
12352 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12354 mips_emit_delays (FALSE
);
12359 mips_align (3, 0, label
);
12361 mips_align (2, 0, label
);
12364 mips_clear_insn_labels ();
12369 /* Handle .globl. We need to override it because on Irix 5 you are
12372 where foo is an undefined symbol, to mean that foo should be
12373 considered to be the address of a function. */
12377 int x ATTRIBUTE_UNUSED
;
12384 name
= input_line_pointer
;
12385 c
= get_symbol_end ();
12386 symbolP
= symbol_find_or_make (name
);
12387 *input_line_pointer
= c
;
12388 SKIP_WHITESPACE ();
12390 /* On Irix 5, every global symbol that is not explicitly labelled as
12391 being a function is apparently labelled as being an object. */
12394 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12399 secname
= input_line_pointer
;
12400 c
= get_symbol_end ();
12401 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12403 as_bad (_("%s: no such section"), secname
);
12404 *input_line_pointer
= c
;
12406 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12407 flag
= BSF_FUNCTION
;
12410 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12412 S_SET_EXTERNAL (symbolP
);
12413 demand_empty_rest_of_line ();
12418 int x ATTRIBUTE_UNUSED
;
12423 opt
= input_line_pointer
;
12424 c
= get_symbol_end ();
12428 /* FIXME: What does this mean? */
12430 else if (strncmp (opt
, "pic", 3) == 0)
12434 i
= atoi (opt
+ 3);
12439 mips_pic
= SVR4_PIC
;
12440 mips_abicalls
= TRUE
;
12443 as_bad (_(".option pic%d not supported"), i
);
12445 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
12447 if (g_switch_seen
&& g_switch_value
!= 0)
12448 as_warn (_("-G may not be used with SVR4 PIC code"));
12449 g_switch_value
= 0;
12450 bfd_set_gp_size (stdoutput
, 0);
12454 as_warn (_("Unrecognized option \"%s\""), opt
);
12456 *input_line_pointer
= c
;
12457 demand_empty_rest_of_line ();
12460 /* This structure is used to hold a stack of .set values. */
12462 struct mips_option_stack
12464 struct mips_option_stack
*next
;
12465 struct mips_set_options options
;
12468 static struct mips_option_stack
*mips_opts_stack
;
12470 /* Handle the .set pseudo-op. */
12474 int x ATTRIBUTE_UNUSED
;
12476 char *name
= input_line_pointer
, ch
;
12478 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12479 ++input_line_pointer
;
12480 ch
= *input_line_pointer
;
12481 *input_line_pointer
= '\0';
12483 if (strcmp (name
, "reorder") == 0)
12485 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
12487 /* If we still have pending nops, we can discard them. The
12488 usual nop handling will insert any that are still
12490 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12491 * (mips_opts
.mips16
? 2 : 4));
12492 prev_nop_frag
= NULL
;
12494 mips_opts
.noreorder
= 0;
12496 else if (strcmp (name
, "noreorder") == 0)
12498 mips_emit_delays (TRUE
);
12499 mips_opts
.noreorder
= 1;
12500 mips_any_noreorder
= 1;
12502 else if (strcmp (name
, "at") == 0)
12504 mips_opts
.noat
= 0;
12506 else if (strcmp (name
, "noat") == 0)
12508 mips_opts
.noat
= 1;
12510 else if (strcmp (name
, "macro") == 0)
12512 mips_opts
.warn_about_macros
= 0;
12514 else if (strcmp (name
, "nomacro") == 0)
12516 if (mips_opts
.noreorder
== 0)
12517 as_bad (_("`noreorder' must be set before `nomacro'"));
12518 mips_opts
.warn_about_macros
= 1;
12520 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12522 mips_opts
.nomove
= 0;
12524 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12526 mips_opts
.nomove
= 1;
12528 else if (strcmp (name
, "bopt") == 0)
12530 mips_opts
.nobopt
= 0;
12532 else if (strcmp (name
, "nobopt") == 0)
12534 mips_opts
.nobopt
= 1;
12536 else if (strcmp (name
, "mips16") == 0
12537 || strcmp (name
, "MIPS-16") == 0)
12538 mips_opts
.mips16
= 1;
12539 else if (strcmp (name
, "nomips16") == 0
12540 || strcmp (name
, "noMIPS-16") == 0)
12541 mips_opts
.mips16
= 0;
12542 else if (strcmp (name
, "mips3d") == 0)
12543 mips_opts
.ase_mips3d
= 1;
12544 else if (strcmp (name
, "nomips3d") == 0)
12545 mips_opts
.ase_mips3d
= 0;
12546 else if (strcmp (name
, "mdmx") == 0)
12547 mips_opts
.ase_mdmx
= 1;
12548 else if (strcmp (name
, "nomdmx") == 0)
12549 mips_opts
.ase_mdmx
= 0;
12550 else if (strncmp (name
, "mips", 4) == 0)
12554 /* Permit the user to change the ISA on the fly. Needless to
12555 say, misuse can cause serious problems. */
12556 if (strcmp (name
, "mips0") == 0)
12559 mips_opts
.isa
= file_mips_isa
;
12561 else if (strcmp (name
, "mips1") == 0)
12562 mips_opts
.isa
= ISA_MIPS1
;
12563 else if (strcmp (name
, "mips2") == 0)
12564 mips_opts
.isa
= ISA_MIPS2
;
12565 else if (strcmp (name
, "mips3") == 0)
12566 mips_opts
.isa
= ISA_MIPS3
;
12567 else if (strcmp (name
, "mips4") == 0)
12568 mips_opts
.isa
= ISA_MIPS4
;
12569 else if (strcmp (name
, "mips5") == 0)
12570 mips_opts
.isa
= ISA_MIPS5
;
12571 else if (strcmp (name
, "mips32") == 0)
12572 mips_opts
.isa
= ISA_MIPS32
;
12573 else if (strcmp (name
, "mips32r2") == 0)
12574 mips_opts
.isa
= ISA_MIPS32R2
;
12575 else if (strcmp (name
, "mips64") == 0)
12576 mips_opts
.isa
= ISA_MIPS64
;
12578 as_bad (_("unknown ISA level %s"), name
+ 4);
12580 switch (mips_opts
.isa
)
12588 mips_opts
.gp32
= 1;
12589 mips_opts
.fp32
= 1;
12595 mips_opts
.gp32
= 0;
12596 mips_opts
.fp32
= 0;
12599 as_bad (_("unknown ISA level %s"), name
+ 4);
12604 mips_opts
.gp32
= file_mips_gp32
;
12605 mips_opts
.fp32
= file_mips_fp32
;
12608 else if (strcmp (name
, "autoextend") == 0)
12609 mips_opts
.noautoextend
= 0;
12610 else if (strcmp (name
, "noautoextend") == 0)
12611 mips_opts
.noautoextend
= 1;
12612 else if (strcmp (name
, "push") == 0)
12614 struct mips_option_stack
*s
;
12616 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12617 s
->next
= mips_opts_stack
;
12618 s
->options
= mips_opts
;
12619 mips_opts_stack
= s
;
12621 else if (strcmp (name
, "pop") == 0)
12623 struct mips_option_stack
*s
;
12625 s
= mips_opts_stack
;
12627 as_bad (_(".set pop with no .set push"));
12630 /* If we're changing the reorder mode we need to handle
12631 delay slots correctly. */
12632 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12633 mips_emit_delays (TRUE
);
12634 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12636 if (prev_nop_frag
!= NULL
)
12638 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12639 * (mips_opts
.mips16
? 2 : 4));
12640 prev_nop_frag
= NULL
;
12644 mips_opts
= s
->options
;
12645 mips_opts_stack
= s
->next
;
12651 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12653 *input_line_pointer
= ch
;
12654 demand_empty_rest_of_line ();
12657 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12658 .option pic2. It means to generate SVR4 PIC calls. */
12661 s_abicalls (ignore
)
12662 int ignore ATTRIBUTE_UNUSED
;
12664 mips_pic
= SVR4_PIC
;
12665 mips_abicalls
= TRUE
;
12666 if (USE_GLOBAL_POINTER_OPT
)
12668 if (g_switch_seen
&& g_switch_value
!= 0)
12669 as_warn (_("-G may not be used with SVR4 PIC code"));
12670 g_switch_value
= 0;
12672 bfd_set_gp_size (stdoutput
, 0);
12673 demand_empty_rest_of_line ();
12676 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12677 PIC code. It sets the $gp register for the function based on the
12678 function address, which is in the register named in the argument.
12679 This uses a relocation against _gp_disp, which is handled specially
12680 by the linker. The result is:
12681 lui $gp,%hi(_gp_disp)
12682 addiu $gp,$gp,%lo(_gp_disp)
12683 addu $gp,$gp,.cpload argument
12684 The .cpload argument is normally $25 == $t9. */
12688 int ignore ATTRIBUTE_UNUSED
;
12693 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12694 .cpload is ignored. */
12695 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12701 /* .cpload should be in a .set noreorder section. */
12702 if (mips_opts
.noreorder
== 0)
12703 as_warn (_(".cpload not in noreorder section"));
12705 ex
.X_op
= O_symbol
;
12706 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12707 ex
.X_op_symbol
= NULL
;
12708 ex
.X_add_number
= 0;
12710 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12711 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12713 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12714 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
12715 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
12717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
12718 mips_gp_register
, mips_gp_register
, tc_get_register (0));
12720 demand_empty_rest_of_line ();
12723 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12724 .cpsetup $reg1, offset|$reg2, label
12726 If offset is given, this results in:
12727 sd $gp, offset($sp)
12728 lui $gp, %hi(%neg(%gp_rel(label)))
12729 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12730 daddu $gp, $gp, $reg1
12732 If $reg2 is given, this results in:
12733 daddu $reg2, $gp, $0
12734 lui $gp, %hi(%neg(%gp_rel(label)))
12735 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12736 daddu $gp, $gp, $reg1
12737 $reg1 is normally $25 == $t9. */
12740 int ignore ATTRIBUTE_UNUSED
;
12742 expressionS ex_off
;
12743 expressionS ex_sym
;
12748 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12749 We also need NewABI support. */
12750 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12756 reg1
= tc_get_register (0);
12757 SKIP_WHITESPACE ();
12758 if (*input_line_pointer
!= ',')
12760 as_bad (_("missing argument separator ',' for .cpsetup"));
12764 ++input_line_pointer
;
12765 SKIP_WHITESPACE ();
12766 if (*input_line_pointer
== '$')
12768 mips_cpreturn_register
= tc_get_register (0);
12769 mips_cpreturn_offset
= -1;
12773 mips_cpreturn_offset
= get_absolute_expression ();
12774 mips_cpreturn_register
= -1;
12776 SKIP_WHITESPACE ();
12777 if (*input_line_pointer
!= ',')
12779 as_bad (_("missing argument separator ',' for .cpsetup"));
12783 ++input_line_pointer
;
12784 SKIP_WHITESPACE ();
12785 expression (&ex_sym
);
12787 if (mips_cpreturn_register
== -1)
12789 ex_off
.X_op
= O_constant
;
12790 ex_off
.X_add_symbol
= NULL
;
12791 ex_off
.X_op_symbol
= NULL
;
12792 ex_off
.X_add_number
= mips_cpreturn_offset
;
12794 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
12795 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12798 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12799 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12801 /* Ensure there's room for the next two instructions, so that `f'
12802 doesn't end up with an address in the wrong frag. */
12805 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12806 (int) BFD_RELOC_GPREL16
);
12807 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12808 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12809 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12810 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12813 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12814 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12815 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12816 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12817 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12818 0, NULL
, 0, 0, BFD_RELOC_LO16
);
12820 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12821 HAVE_64BIT_ADDRESSES
? "daddu" : "add", "d,v,t",
12822 mips_gp_register
, mips_gp_register
, reg1
);
12824 demand_empty_rest_of_line ();
12829 int ignore ATTRIBUTE_UNUSED
;
12831 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12832 .cplocal is ignored. */
12833 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12839 mips_gp_register
= tc_get_register (0);
12840 demand_empty_rest_of_line ();
12843 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12844 offset from $sp. The offset is remembered, and after making a PIC
12845 call $gp is restored from that location. */
12848 s_cprestore (ignore
)
12849 int ignore ATTRIBUTE_UNUSED
;
12854 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12855 .cprestore is ignored. */
12856 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12862 mips_cprestore_offset
= get_absolute_expression ();
12863 mips_cprestore_valid
= 1;
12865 ex
.X_op
= O_constant
;
12866 ex
.X_add_symbol
= NULL
;
12867 ex
.X_op_symbol
= NULL
;
12868 ex
.X_add_number
= mips_cprestore_offset
;
12870 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
12871 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
12872 mips_gp_register
, SP
);
12874 demand_empty_rest_of_line ();
12877 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12878 was given in the preceeding .gpsetup, it results in:
12879 ld $gp, offset($sp)
12881 If a register $reg2 was given there, it results in:
12882 daddiu $gp, $gp, $reg2
12885 s_cpreturn (ignore
)
12886 int ignore ATTRIBUTE_UNUSED
;
12891 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12892 We also need NewABI support. */
12893 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12899 if (mips_cpreturn_register
== -1)
12901 ex
.X_op
= O_constant
;
12902 ex
.X_add_symbol
= NULL
;
12903 ex
.X_op_symbol
= NULL
;
12904 ex
.X_add_number
= mips_cpreturn_offset
;
12906 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12907 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12911 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12913 demand_empty_rest_of_line ();
12916 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12917 code. It sets the offset to use in gp_rel relocations. */
12921 int ignore ATTRIBUTE_UNUSED
;
12923 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12924 We also need NewABI support. */
12925 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12931 mips_gprel_offset
= get_absolute_expression ();
12933 demand_empty_rest_of_line ();
12936 /* Handle the .gpword pseudo-op. This is used when generating PIC
12937 code. It generates a 32 bit GP relative reloc. */
12941 int ignore ATTRIBUTE_UNUSED
;
12947 /* When not generating PIC code, this is treated as .word. */
12948 if (mips_pic
!= SVR4_PIC
)
12954 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12955 mips_emit_delays (TRUE
);
12957 mips_align (2, 0, label
);
12958 mips_clear_insn_labels ();
12962 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12964 as_bad (_("Unsupported use of .gpword"));
12965 ignore_rest_of_line ();
12969 md_number_to_chars (p
, (valueT
) 0, 4);
12970 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12971 BFD_RELOC_GPREL32
);
12973 demand_empty_rest_of_line ();
12978 int ignore ATTRIBUTE_UNUSED
;
12984 /* When not generating PIC code, this is treated as .dword. */
12985 if (mips_pic
!= SVR4_PIC
)
12991 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12992 mips_emit_delays (TRUE
);
12994 mips_align (3, 0, label
);
12995 mips_clear_insn_labels ();
12999 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13001 as_bad (_("Unsupported use of .gpdword"));
13002 ignore_rest_of_line ();
13006 md_number_to_chars (p
, (valueT
) 0, 8);
13007 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
13008 BFD_RELOC_GPREL32
);
13010 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13011 ex
.X_op
= O_absent
;
13012 ex
.X_add_symbol
= 0;
13013 ex
.X_add_number
= 0;
13014 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
13017 demand_empty_rest_of_line ();
13020 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13021 tables in SVR4 PIC code. */
13025 int ignore ATTRIBUTE_UNUSED
;
13030 /* This is ignored when not generating SVR4 PIC code. */
13031 if (mips_pic
!= SVR4_PIC
)
13037 /* Add $gp to the register named as an argument. */
13038 reg
= tc_get_register (0);
13039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
13040 HAVE_32BIT_ADDRESSES
? HAVE_NEWABI
? "add" : "addu" : "daddu",
13041 "d,v,t", reg
, reg
, mips_gp_register
);
13043 demand_empty_rest_of_line ();
13046 /* Handle the .insn pseudo-op. This marks instruction labels in
13047 mips16 mode. This permits the linker to handle them specially,
13048 such as generating jalx instructions when needed. We also make
13049 them odd for the duration of the assembly, in order to generate the
13050 right sort of code. We will make them even in the adjust_symtab
13051 routine, while leaving them marked. This is convenient for the
13052 debugger and the disassembler. The linker knows to make them odd
13057 int ignore ATTRIBUTE_UNUSED
;
13059 mips16_mark_labels ();
13061 demand_empty_rest_of_line ();
13064 /* Handle a .stabn directive. We need these in order to mark a label
13065 as being a mips16 text label correctly. Sometimes the compiler
13066 will emit a label, followed by a .stabn, and then switch sections.
13067 If the label and .stabn are in mips16 mode, then the label is
13068 really a mips16 text label. */
13075 mips16_mark_labels ();
13080 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
13084 s_mips_weakext (ignore
)
13085 int ignore ATTRIBUTE_UNUSED
;
13092 name
= input_line_pointer
;
13093 c
= get_symbol_end ();
13094 symbolP
= symbol_find_or_make (name
);
13095 S_SET_WEAK (symbolP
);
13096 *input_line_pointer
= c
;
13098 SKIP_WHITESPACE ();
13100 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13102 if (S_IS_DEFINED (symbolP
))
13104 as_bad ("ignoring attempt to redefine symbol %s",
13105 S_GET_NAME (symbolP
));
13106 ignore_rest_of_line ();
13110 if (*input_line_pointer
== ',')
13112 ++input_line_pointer
;
13113 SKIP_WHITESPACE ();
13117 if (exp
.X_op
!= O_symbol
)
13119 as_bad ("bad .weakext directive");
13120 ignore_rest_of_line ();
13123 symbol_set_value_expression (symbolP
, &exp
);
13126 demand_empty_rest_of_line ();
13129 /* Parse a register string into a number. Called from the ECOFF code
13130 to parse .frame. The argument is non-zero if this is the frame
13131 register, so that we can record it in mips_frame_reg. */
13134 tc_get_register (frame
)
13139 SKIP_WHITESPACE ();
13140 if (*input_line_pointer
++ != '$')
13142 as_warn (_("expected `$'"));
13145 else if (ISDIGIT (*input_line_pointer
))
13147 reg
= get_absolute_expression ();
13148 if (reg
< 0 || reg
>= 32)
13150 as_warn (_("Bad register number"));
13156 if (strncmp (input_line_pointer
, "ra", 2) == 0)
13159 input_line_pointer
+= 2;
13161 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
13164 input_line_pointer
+= 2;
13166 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
13169 input_line_pointer
+= 2;
13171 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
13174 input_line_pointer
+= 2;
13176 else if (strncmp (input_line_pointer
, "at", 2) == 0)
13179 input_line_pointer
+= 2;
13181 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
13184 input_line_pointer
+= 3;
13186 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
13189 input_line_pointer
+= 3;
13191 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
13194 input_line_pointer
+= 4;
13198 as_warn (_("Unrecognized register name"));
13200 while (ISALNUM(*input_line_pointer
))
13201 input_line_pointer
++;
13206 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13207 mips_frame_reg_valid
= 1;
13208 mips_cprestore_valid
= 0;
13214 md_section_align (seg
, addr
)
13218 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13221 /* We don't need to align ELF sections to the full alignment.
13222 However, Irix 5 may prefer that we align them at least to a 16
13223 byte boundary. We don't bother to align the sections if we are
13224 targeted for an embedded system. */
13225 if (strcmp (TARGET_OS
, "elf") == 0)
13231 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13234 /* Utility routine, called from above as well. If called while the
13235 input file is still being read, it's only an approximation. (For
13236 example, a symbol may later become defined which appeared to be
13237 undefined earlier.) */
13240 nopic_need_relax (sym
, before_relaxing
)
13242 int before_relaxing
;
13247 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
13249 const char *symname
;
13252 /* Find out whether this symbol can be referenced off the $gp
13253 register. It can be if it is smaller than the -G size or if
13254 it is in the .sdata or .sbss section. Certain symbols can
13255 not be referenced off the $gp, although it appears as though
13257 symname
= S_GET_NAME (sym
);
13258 if (symname
!= (const char *) NULL
13259 && (strcmp (symname
, "eprol") == 0
13260 || strcmp (symname
, "etext") == 0
13261 || strcmp (symname
, "_gp") == 0
13262 || strcmp (symname
, "edata") == 0
13263 || strcmp (symname
, "_fbss") == 0
13264 || strcmp (symname
, "_fdata") == 0
13265 || strcmp (symname
, "_ftext") == 0
13266 || strcmp (symname
, "end") == 0
13267 || strcmp (symname
, "_gp_disp") == 0))
13269 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13271 #ifndef NO_ECOFF_DEBUGGING
13272 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13273 && (symbol_get_obj (sym
)->ecoff_extern_size
13274 <= g_switch_value
))
13276 /* We must defer this decision until after the whole
13277 file has been read, since there might be a .extern
13278 after the first use of this symbol. */
13279 || (before_relaxing
13280 #ifndef NO_ECOFF_DEBUGGING
13281 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13283 && S_GET_VALUE (sym
) == 0)
13284 || (S_GET_VALUE (sym
) != 0
13285 && S_GET_VALUE (sym
) <= g_switch_value
)))
13289 const char *segname
;
13291 segname
= segment_name (S_GET_SEGMENT (sym
));
13292 assert (strcmp (segname
, ".lit8") != 0
13293 && strcmp (segname
, ".lit4") != 0);
13294 change
= (strcmp (segname
, ".sdata") != 0
13295 && strcmp (segname
, ".sbss") != 0
13296 && strncmp (segname
, ".sdata.", 7) != 0
13297 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13302 /* We are not optimizing for the $gp register. */
13307 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13310 pic_need_relax (sym
, segtype
)
13315 bfd_boolean linkonce
;
13317 /* Handle the case of a symbol equated to another symbol. */
13318 while (symbol_equated_reloc_p (sym
))
13322 /* It's possible to get a loop here in a badly written
13324 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13330 symsec
= S_GET_SEGMENT (sym
);
13332 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13334 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
13336 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13340 /* The GNU toolchain uses an extension for ELF: a section
13341 beginning with the magic string .gnu.linkonce is a linkonce
13343 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13344 sizeof ".gnu.linkonce" - 1) == 0)
13348 /* This must duplicate the test in adjust_reloc_syms. */
13349 return (symsec
!= &bfd_und_section
13350 && symsec
!= &bfd_abs_section
13351 && ! bfd_is_com_section (symsec
)
13354 /* A global or weak symbol is treated as external. */
13355 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13356 || (! S_IS_WEAK (sym
)
13357 && (! S_IS_EXTERNAL (sym
)
13358 || mips_pic
== EMBEDDED_PIC
)))
13364 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13365 extended opcode. SEC is the section the frag is in. */
13368 mips16_extended_frag (fragp
, sec
, stretch
)
13374 register const struct mips16_immed_operand
*op
;
13376 int mintiny
, maxtiny
;
13380 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13382 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13385 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13386 op
= mips16_immed_operands
;
13387 while (op
->type
!= type
)
13390 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13395 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13398 maxtiny
= 1 << op
->nbits
;
13403 maxtiny
= (1 << op
->nbits
) - 1;
13408 mintiny
= - (1 << (op
->nbits
- 1));
13409 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13412 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13413 val
= S_GET_VALUE (fragp
->fr_symbol
);
13414 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13420 /* We won't have the section when we are called from
13421 mips_relax_frag. However, we will always have been called
13422 from md_estimate_size_before_relax first. If this is a
13423 branch to a different section, we mark it as such. If SEC is
13424 NULL, and the frag is not marked, then it must be a branch to
13425 the same section. */
13428 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13433 /* Must have been called from md_estimate_size_before_relax. */
13436 fragp
->fr_subtype
=
13437 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13439 /* FIXME: We should support this, and let the linker
13440 catch branches and loads that are out of range. */
13441 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13442 _("unsupported PC relative reference to different section"));
13446 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13447 /* Assume non-extended on the first relaxation pass.
13448 The address we have calculated will be bogus if this is
13449 a forward branch to another frag, as the forward frag
13450 will have fr_address == 0. */
13454 /* In this case, we know for sure that the symbol fragment is in
13455 the same section. If the relax_marker of the symbol fragment
13456 differs from the relax_marker of this fragment, we have not
13457 yet adjusted the symbol fragment fr_address. We want to add
13458 in STRETCH in order to get a better estimate of the address.
13459 This particularly matters because of the shift bits. */
13461 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13465 /* Adjust stretch for any alignment frag. Note that if have
13466 been expanding the earlier code, the symbol may be
13467 defined in what appears to be an earlier frag. FIXME:
13468 This doesn't handle the fr_subtype field, which specifies
13469 a maximum number of bytes to skip when doing an
13471 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13473 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13476 stretch
= - ((- stretch
)
13477 & ~ ((1 << (int) f
->fr_offset
) - 1));
13479 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13488 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13490 /* The base address rules are complicated. The base address of
13491 a branch is the following instruction. The base address of a
13492 PC relative load or add is the instruction itself, but if it
13493 is in a delay slot (in which case it can not be extended) use
13494 the address of the instruction whose delay slot it is in. */
13495 if (type
== 'p' || type
== 'q')
13499 /* If we are currently assuming that this frag should be
13500 extended, then, the current address is two bytes
13502 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13505 /* Ignore the low bit in the target, since it will be set
13506 for a text label. */
13507 if ((val
& 1) != 0)
13510 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13512 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13515 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13517 /* Branch offsets have an implicit 0 in the lowest bit. */
13518 if (type
== 'p' || type
== 'q')
13521 /* If any of the shifted bits are set, we must use an extended
13522 opcode. If the address depends on the size of this
13523 instruction, this can lead to a loop, so we arrange to always
13524 use an extended opcode. We only check this when we are in
13525 the main relaxation loop, when SEC is NULL. */
13526 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13528 fragp
->fr_subtype
=
13529 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13533 /* If we are about to mark a frag as extended because the value
13534 is precisely maxtiny + 1, then there is a chance of an
13535 infinite loop as in the following code:
13540 In this case when the la is extended, foo is 0x3fc bytes
13541 away, so the la can be shrunk, but then foo is 0x400 away, so
13542 the la must be extended. To avoid this loop, we mark the
13543 frag as extended if it was small, and is about to become
13544 extended with a value of maxtiny + 1. */
13545 if (val
== ((maxtiny
+ 1) << op
->shift
)
13546 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13549 fragp
->fr_subtype
=
13550 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13554 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13555 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13557 if ((val
& ((1 << op
->shift
) - 1)) != 0
13558 || val
< (mintiny
<< op
->shift
)
13559 || val
> (maxtiny
<< op
->shift
))
13565 /* Compute the length of a branch sequence, and adjust the
13566 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13567 worst-case length is computed, with UPDATE being used to indicate
13568 whether an unconditional (-1), branch-likely (+1) or regular (0)
13569 branch is to be computed. */
13571 relaxed_branch_length (fragp
, sec
, update
)
13576 bfd_boolean toofar
;
13580 && S_IS_DEFINED (fragp
->fr_symbol
)
13581 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13586 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13588 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13592 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13595 /* If the symbol is not defined or it's in a different segment,
13596 assume the user knows what's going on and emit a short
13602 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13604 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13605 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13606 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13612 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13615 if (mips_pic
!= NO_PIC
)
13617 /* Additional space for PIC loading of target address. */
13619 if (mips_opts
.isa
== ISA_MIPS1
)
13620 /* Additional space for $at-stabilizing nop. */
13624 /* If branch is conditional. */
13625 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13632 /* Estimate the size of a frag before relaxing. Unless this is the
13633 mips16, we are not really relaxing here, and the final size is
13634 encoded in the subtype information. For the mips16, we have to
13635 decide whether we are using an extended opcode or not. */
13638 md_estimate_size_before_relax (fragp
, segtype
)
13644 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13647 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13649 return fragp
->fr_var
;
13652 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13653 /* We don't want to modify the EXTENDED bit here; it might get us
13654 into infinite loops. We change it only in mips_relax_frag(). */
13655 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13657 if (mips_pic
== NO_PIC
)
13658 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13659 else if (mips_pic
== SVR4_PIC
)
13660 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13666 /* Record the offset to the first reloc in the fr_opcode field.
13667 This lets md_convert_frag and tc_gen_reloc know that the code
13668 must be expanded. */
13669 fragp
->fr_opcode
= (fragp
->fr_literal
13671 - RELAX_OLD (fragp
->fr_subtype
)
13672 + RELAX_RELOC1 (fragp
->fr_subtype
));
13673 /* FIXME: This really needs as_warn_where. */
13674 if (RELAX_WARN (fragp
->fr_subtype
))
13675 as_warn (_("AT used after \".set noat\" or macro used after "
13676 "\".set nomacro\""));
13678 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13684 /* This is called to see whether a reloc against a defined symbol
13685 should be converted into a reloc against a section. Don't adjust
13686 MIPS16 jump relocations, so we don't have to worry about the format
13687 of the offset in the .o file. Don't adjust relocations against
13688 mips16 symbols, so that the linker can find them if it needs to set
13692 mips_fix_adjustable (fixp
)
13695 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13698 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13699 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13702 if (fixp
->fx_addsy
== NULL
)
13706 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13707 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13708 && fixp
->fx_subsy
== NULL
)
13715 /* Translate internal representation of relocation info to BFD target
13719 tc_gen_reloc (section
, fixp
)
13720 asection
*section ATTRIBUTE_UNUSED
;
13723 static arelent
*retval
[4];
13725 bfd_reloc_code_real_type code
;
13727 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
13730 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13731 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13732 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13734 if (mips_pic
== EMBEDDED_PIC
13735 && SWITCH_TABLE (fixp
))
13737 /* For a switch table entry we use a special reloc. The addend
13738 is actually the difference between the reloc address and the
13740 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13741 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13742 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13743 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13745 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
13747 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13748 reloc
->addend
= fixp
->fx_addnumber
;
13751 /* We use a special addend for an internal RELLO reloc. */
13752 if (symbol_section_p (fixp
->fx_addsy
))
13753 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13755 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13758 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13760 assert (fixp
->fx_next
!= NULL
13761 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13763 /* The reloc is relative to the RELLO; adjust the addend
13765 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13766 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
13769 /* We use a special addend for an internal RELHI reloc. */
13770 if (symbol_section_p (fixp
->fx_addsy
))
13771 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
13772 + fixp
->fx_next
->fx_where
13773 - S_GET_VALUE (fixp
->fx_subsy
));
13775 reloc
->addend
= (fixp
->fx_addnumber
13776 + fixp
->fx_next
->fx_frag
->fr_address
13777 + fixp
->fx_next
->fx_where
);
13780 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13781 reloc
->addend
= fixp
->fx_addnumber
;
13784 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13785 /* A gruesome hack which is a result of the gruesome gas reloc
13787 reloc
->addend
= reloc
->address
;
13789 reloc
->addend
= -reloc
->address
;
13792 /* If this is a variant frag, we may need to adjust the existing
13793 reloc and generate a new one. */
13794 if (fixp
->fx_frag
->fr_opcode
!= NULL
13795 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13797 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_DISP
13799 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13800 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13801 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13802 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13803 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13804 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13809 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13811 /* If this is not the last reloc in this frag, then we have two
13812 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13813 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13814 the second one handle all of them. */
13815 if (fixp
->fx_next
!= NULL
13816 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13818 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13819 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13820 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13821 && (fixp
->fx_next
->fx_r_type
13822 == BFD_RELOC_MIPS_GOT_LO16
))
13823 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13824 && (fixp
->fx_next
->fx_r_type
13825 == BFD_RELOC_MIPS_CALL_LO16
)));
13830 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13831 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13832 reloc
->addend
+= fixp
->fx_frag
->tc_frag_data
.tc_fr_offset
;
13833 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13835 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13836 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13837 reloc2
->address
= (reloc
->address
13838 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13839 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13840 reloc2
->addend
= fixp
->fx_addnumber
13841 + fixp
->fx_frag
->tc_frag_data
.tc_fr_offset
;
13842 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13843 assert (reloc2
->howto
!= NULL
);
13845 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13849 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13852 reloc3
->address
+= 4;
13855 if (mips_pic
== NO_PIC
)
13857 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13858 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13860 else if (mips_pic
== SVR4_PIC
)
13862 switch (fixp
->fx_r_type
)
13866 case BFD_RELOC_MIPS_GOT16
:
13868 case BFD_RELOC_MIPS_GOT_LO16
:
13869 case BFD_RELOC_MIPS_CALL_LO16
:
13872 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13873 reloc2
->howto
= bfd_reloc_type_lookup
13874 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13877 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13879 case BFD_RELOC_MIPS_CALL16
:
13880 case BFD_RELOC_MIPS_GOT_OFST
:
13881 case BFD_RELOC_MIPS_GOT_DISP
:
13884 /* It may seem nonsensical to relax GOT_DISP to
13885 GOT_DISP, but we're actually turning a GOT_DISP
13886 without offset into a GOT_DISP with an offset,
13887 getting rid of the separate addition, which we can
13888 do when the symbol is found to be local. */
13889 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13893 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13901 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13902 entry to be used in the relocation's section offset. */
13903 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13905 reloc
->address
= reloc
->addend
;
13909 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13910 fixup_segment converted a non-PC relative reloc into a PC
13911 relative reloc. In such a case, we need to convert the reloc
13913 code
= fixp
->fx_r_type
;
13914 if (fixp
->fx_pcrel
)
13919 code
= BFD_RELOC_8_PCREL
;
13922 code
= BFD_RELOC_16_PCREL
;
13925 code
= BFD_RELOC_32_PCREL
;
13928 code
= BFD_RELOC_64_PCREL
;
13930 case BFD_RELOC_8_PCREL
:
13931 case BFD_RELOC_16_PCREL
:
13932 case BFD_RELOC_32_PCREL
:
13933 case BFD_RELOC_64_PCREL
:
13934 case BFD_RELOC_16_PCREL_S2
:
13935 case BFD_RELOC_PCREL_HI16_S
:
13936 case BFD_RELOC_PCREL_LO16
:
13939 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13940 _("Cannot make %s relocation PC relative"),
13941 bfd_get_reloc_code_name (code
));
13946 /* md_apply_fix3 has a double-subtraction hack to get
13947 bfd_install_relocation to behave nicely. GPREL relocations are
13948 handled correctly without this hack, so undo it here. We can't
13949 stop md_apply_fix3 from subtracting twice in the first place since
13950 the fake addend is required for variant frags above. */
13951 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
13952 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
13953 && reloc
->addend
!= 0
13954 && mips_need_elf_addend_fixup (fixp
))
13956 /* If howto->partial_inplace is false, md_apply_fix3 will only
13957 subtract it once. */
13958 reloc_howto_type
*howto
;
13960 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
13961 if (howto
->partial_inplace
)
13962 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
13966 /* To support a PC relative reloc when generating embedded PIC code
13967 for ECOFF, we use a Cygnus extension. We check for that here to
13968 make sure that we don't let such a reloc escape normally. */
13969 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13970 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13971 && code
== BFD_RELOC_16_PCREL_S2
13972 && mips_pic
!= EMBEDDED_PIC
)
13973 reloc
->howto
= NULL
;
13975 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13977 if (reloc
->howto
== NULL
)
13979 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13980 _("Can not represent %s relocation in this object file format"),
13981 bfd_get_reloc_code_name (code
));
13988 /* Relax a machine dependent frag. This returns the amount by which
13989 the current size of the frag should change. */
13992 mips_relax_frag (sec
, fragp
, stretch
)
13997 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13999 offsetT old_var
= fragp
->fr_var
;
14001 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14003 return fragp
->fr_var
- old_var
;
14006 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14009 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14011 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14013 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14018 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14020 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14027 /* Convert a machine dependent frag. */
14030 md_convert_frag (abfd
, asec
, fragp
)
14031 bfd
*abfd ATTRIBUTE_UNUSED
;
14038 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14041 unsigned long insn
;
14045 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14047 if (target_big_endian
)
14048 insn
= bfd_getb32 (buf
);
14050 insn
= bfd_getl32 (buf
);
14052 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14054 /* We generate a fixup instead of applying it right now
14055 because, if there are linker relaxations, we're going to
14056 need the relocations. */
14057 exp
.X_op
= O_symbol
;
14058 exp
.X_add_symbol
= fragp
->fr_symbol
;
14059 exp
.X_add_number
= fragp
->fr_offset
;
14061 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14063 BFD_RELOC_16_PCREL_S2
);
14064 fixp
->fx_file
= fragp
->fr_file
;
14065 fixp
->fx_line
= fragp
->fr_line
;
14067 md_number_to_chars ((char *)buf
, insn
, 4);
14074 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14075 _("relaxed out-of-range branch into a jump"));
14077 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14080 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14082 /* Reverse the branch. */
14083 switch ((insn
>> 28) & 0xf)
14086 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14087 have the condition reversed by tweaking a single
14088 bit, and their opcodes all have 0x4???????. */
14089 assert ((insn
& 0xf1000000) == 0x41000000);
14090 insn
^= 0x00010000;
14094 /* bltz 0x04000000 bgez 0x04010000
14095 bltzal 0x04100000 bgezal 0x04110000 */
14096 assert ((insn
& 0xfc0e0000) == 0x04000000);
14097 insn
^= 0x00010000;
14101 /* beq 0x10000000 bne 0x14000000
14102 blez 0x18000000 bgtz 0x1c000000 */
14103 insn
^= 0x04000000;
14111 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14113 /* Clear the and-link bit. */
14114 assert ((insn
& 0xfc1c0000) == 0x04100000);
14116 /* bltzal 0x04100000 bgezal 0x04110000
14117 bltzall 0x04120000 bgezall 0x04130000 */
14118 insn
&= ~0x00100000;
14121 /* Branch over the branch (if the branch was likely) or the
14122 full jump (not likely case). Compute the offset from the
14123 current instruction to branch to. */
14124 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14128 /* How many bytes in instructions we've already emitted? */
14129 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14130 /* How many bytes in instructions from here to the end? */
14131 i
= fragp
->fr_var
- i
;
14133 /* Convert to instruction count. */
14135 /* Branch counts from the next instruction. */
14138 /* Branch over the jump. */
14139 md_number_to_chars ((char *)buf
, insn
, 4);
14143 md_number_to_chars ((char*)buf
, 0, 4);
14146 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14148 /* beql $0, $0, 2f */
14150 /* Compute the PC offset from the current instruction to
14151 the end of the variable frag. */
14152 /* How many bytes in instructions we've already emitted? */
14153 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14154 /* How many bytes in instructions from here to the end? */
14155 i
= fragp
->fr_var
- i
;
14156 /* Convert to instruction count. */
14158 /* Don't decrement i, because we want to branch over the
14162 md_number_to_chars ((char *)buf
, insn
, 4);
14165 md_number_to_chars ((char *)buf
, 0, 4);
14170 if (mips_pic
== NO_PIC
)
14173 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14174 ? 0x0c000000 : 0x08000000);
14175 exp
.X_op
= O_symbol
;
14176 exp
.X_add_symbol
= fragp
->fr_symbol
;
14177 exp
.X_add_number
= fragp
->fr_offset
;
14179 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14180 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
14181 fixp
->fx_file
= fragp
->fr_file
;
14182 fixp
->fx_line
= fragp
->fr_line
;
14184 md_number_to_chars ((char*)buf
, insn
, 4);
14189 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14190 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14191 exp
.X_op
= O_symbol
;
14192 exp
.X_add_symbol
= fragp
->fr_symbol
;
14193 exp
.X_add_number
= fragp
->fr_offset
;
14195 if (fragp
->fr_offset
)
14197 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14198 exp
.X_add_number
= 0;
14201 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14202 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
14203 fixp
->fx_file
= fragp
->fr_file
;
14204 fixp
->fx_line
= fragp
->fr_line
;
14206 md_number_to_chars ((char*)buf
, insn
, 4);
14209 if (mips_opts
.isa
== ISA_MIPS1
)
14212 md_number_to_chars ((char*)buf
, 0, 4);
14216 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14217 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14219 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14220 4, &exp
, 0, BFD_RELOC_LO16
);
14221 fixp
->fx_file
= fragp
->fr_file
;
14222 fixp
->fx_line
= fragp
->fr_line
;
14224 md_number_to_chars ((char*)buf
, insn
, 4);
14228 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14233 md_number_to_chars ((char*)buf
, insn
, 4);
14238 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14239 + fragp
->fr_fix
+ fragp
->fr_var
);
14241 fragp
->fr_fix
+= fragp
->fr_var
;
14246 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14249 register const struct mips16_immed_operand
*op
;
14250 bfd_boolean small
, ext
;
14253 unsigned long insn
;
14254 bfd_boolean use_extend
;
14255 unsigned short extend
;
14257 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14258 op
= mips16_immed_operands
;
14259 while (op
->type
!= type
)
14262 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14273 resolve_symbol_value (fragp
->fr_symbol
);
14274 val
= S_GET_VALUE (fragp
->fr_symbol
);
14279 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14281 /* The rules for the base address of a PC relative reloc are
14282 complicated; see mips16_extended_frag. */
14283 if (type
== 'p' || type
== 'q')
14288 /* Ignore the low bit in the target, since it will be
14289 set for a text label. */
14290 if ((val
& 1) != 0)
14293 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14295 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14298 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14301 /* Make sure the section winds up with the alignment we have
14304 record_alignment (asec
, op
->shift
);
14308 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14309 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14310 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14311 _("extended instruction in delay slot"));
14313 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14315 if (target_big_endian
)
14316 insn
= bfd_getb16 (buf
);
14318 insn
= bfd_getl16 (buf
);
14320 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14321 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14322 small
, ext
, &insn
, &use_extend
, &extend
);
14326 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14327 fragp
->fr_fix
+= 2;
14331 md_number_to_chars ((char *) buf
, insn
, 2);
14332 fragp
->fr_fix
+= 2;
14337 if (fragp
->fr_opcode
== NULL
)
14340 old
= RELAX_OLD (fragp
->fr_subtype
);
14341 new = RELAX_NEW (fragp
->fr_subtype
);
14342 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
14345 memmove (fixptr
- old
, fixptr
, new);
14347 fragp
->fr_fix
+= new - old
;
14353 /* This function is called after the relocs have been generated.
14354 We've been storing mips16 text labels as odd. Here we convert them
14355 back to even for the convenience of the debugger. */
14358 mips_frob_file_after_relocs ()
14361 unsigned int count
, i
;
14363 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
14366 syms
= bfd_get_outsymbols (stdoutput
);
14367 count
= bfd_get_symcount (stdoutput
);
14368 for (i
= 0; i
< count
; i
++, syms
++)
14370 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
14371 && ((*syms
)->value
& 1) != 0)
14373 (*syms
)->value
&= ~1;
14374 /* If the symbol has an odd size, it was probably computed
14375 incorrectly, so adjust that as well. */
14376 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14377 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14384 /* This function is called whenever a label is defined. It is used
14385 when handling branch delays; if a branch has a label, we assume we
14386 can not move it. */
14389 mips_define_label (sym
)
14392 struct insn_label_list
*l
;
14394 if (free_insn_labels
== NULL
)
14395 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14398 l
= free_insn_labels
;
14399 free_insn_labels
= l
->next
;
14403 l
->next
= insn_labels
;
14407 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14409 /* Some special processing for a MIPS ELF file. */
14412 mips_elf_final_processing ()
14414 /* Write out the register information. */
14415 if (mips_abi
!= N64_ABI
)
14419 s
.ri_gprmask
= mips_gprmask
;
14420 s
.ri_cprmask
[0] = mips_cprmask
[0];
14421 s
.ri_cprmask
[1] = mips_cprmask
[1];
14422 s
.ri_cprmask
[2] = mips_cprmask
[2];
14423 s
.ri_cprmask
[3] = mips_cprmask
[3];
14424 /* The gp_value field is set by the MIPS ELF backend. */
14426 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14427 ((Elf32_External_RegInfo
*)
14428 mips_regmask_frag
));
14432 Elf64_Internal_RegInfo s
;
14434 s
.ri_gprmask
= mips_gprmask
;
14436 s
.ri_cprmask
[0] = mips_cprmask
[0];
14437 s
.ri_cprmask
[1] = mips_cprmask
[1];
14438 s
.ri_cprmask
[2] = mips_cprmask
[2];
14439 s
.ri_cprmask
[3] = mips_cprmask
[3];
14440 /* The gp_value field is set by the MIPS ELF backend. */
14442 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14443 ((Elf64_External_RegInfo
*)
14444 mips_regmask_frag
));
14447 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14448 sort of BFD interface for this. */
14449 if (mips_any_noreorder
)
14450 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14451 if (mips_pic
!= NO_PIC
)
14453 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14454 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14457 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14459 /* Set MIPS ELF flags for ASEs. */
14460 if (file_ase_mips16
)
14461 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14462 #if 0 /* XXX FIXME */
14463 if (file_ase_mips3d
)
14464 elf_elfheader (stdoutput
)->e_flags
|= ???;
14467 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14469 /* Set the MIPS ELF ABI flags. */
14470 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14471 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14472 else if (mips_abi
== O64_ABI
)
14473 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14474 else if (mips_abi
== EABI_ABI
)
14476 if (!file_mips_gp32
)
14477 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14479 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14481 else if (mips_abi
== N32_ABI
)
14482 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14484 /* Nothing to do for N64_ABI. */
14486 if (mips_32bitmode
)
14487 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14490 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14492 typedef struct proc
{
14494 unsigned long reg_mask
;
14495 unsigned long reg_offset
;
14496 unsigned long fpreg_mask
;
14497 unsigned long fpreg_offset
;
14498 unsigned long frame_offset
;
14499 unsigned long frame_reg
;
14500 unsigned long pc_reg
;
14503 static procS cur_proc
;
14504 static procS
*cur_proc_ptr
;
14505 static int numprocs
;
14507 /* Fill in an rs_align_code fragment. */
14510 mips_handle_align (fragp
)
14513 if (fragp
->fr_type
!= rs_align_code
)
14516 if (mips_opts
.mips16
)
14518 static const unsigned char be_nop
[] = { 0x65, 0x00 };
14519 static const unsigned char le_nop
[] = { 0x00, 0x65 };
14524 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14525 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14533 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14537 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14548 /* check for premature end, nesting errors, etc */
14550 as_warn (_("missing .end at end of assembly"));
14559 if (*input_line_pointer
== '-')
14561 ++input_line_pointer
;
14564 if (!ISDIGIT (*input_line_pointer
))
14565 as_bad (_("expected simple number"));
14566 if (input_line_pointer
[0] == '0')
14568 if (input_line_pointer
[1] == 'x')
14570 input_line_pointer
+= 2;
14571 while (ISXDIGIT (*input_line_pointer
))
14574 val
|= hex_value (*input_line_pointer
++);
14576 return negative
? -val
: val
;
14580 ++input_line_pointer
;
14581 while (ISDIGIT (*input_line_pointer
))
14584 val
|= *input_line_pointer
++ - '0';
14586 return negative
? -val
: val
;
14589 if (!ISDIGIT (*input_line_pointer
))
14591 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14592 *input_line_pointer
, *input_line_pointer
);
14593 as_warn (_("invalid number"));
14596 while (ISDIGIT (*input_line_pointer
))
14599 val
+= *input_line_pointer
++ - '0';
14601 return negative
? -val
: val
;
14604 /* The .file directive; just like the usual .file directive, but there
14605 is an initial number which is the ECOFF file index. In the non-ECOFF
14606 case .file implies DWARF-2. */
14610 int x ATTRIBUTE_UNUSED
;
14612 static int first_file_directive
= 0;
14614 if (ECOFF_DEBUGGING
)
14623 filename
= dwarf2_directive_file (0);
14625 /* Versions of GCC up to 3.1 start files with a ".file"
14626 directive even for stabs output. Make sure that this
14627 ".file" is handled. Note that you need a version of GCC
14628 after 3.1 in order to support DWARF-2 on MIPS. */
14629 if (filename
!= NULL
&& ! first_file_directive
)
14631 (void) new_logical_line (filename
, -1);
14632 s_app_file_string (filename
);
14634 first_file_directive
= 1;
14638 /* The .loc directive, implying DWARF-2. */
14642 int x ATTRIBUTE_UNUSED
;
14644 if (!ECOFF_DEBUGGING
)
14645 dwarf2_directive_loc (0);
14648 /* The .end directive. */
14652 int x ATTRIBUTE_UNUSED
;
14656 /* Following functions need their own .frame and .cprestore directives. */
14657 mips_frame_reg_valid
= 0;
14658 mips_cprestore_valid
= 0;
14660 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14663 demand_empty_rest_of_line ();
14668 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14669 as_warn (_(".end not in text section"));
14673 as_warn (_(".end directive without a preceding .ent directive."));
14674 demand_empty_rest_of_line ();
14680 assert (S_GET_NAME (p
));
14681 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14682 as_warn (_(".end symbol does not match .ent symbol."));
14684 if (debug_type
== DEBUG_STABS
)
14685 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14689 as_warn (_(".end directive missing or unknown symbol"));
14692 /* Generate a .pdr section. */
14693 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14695 segT saved_seg
= now_seg
;
14696 subsegT saved_subseg
= now_subseg
;
14701 dot
= frag_now_fix ();
14703 #ifdef md_flush_pending_output
14704 md_flush_pending_output ();
14708 subseg_set (pdr_seg
, 0);
14710 /* Write the symbol. */
14711 exp
.X_op
= O_symbol
;
14712 exp
.X_add_symbol
= p
;
14713 exp
.X_add_number
= 0;
14714 emit_expr (&exp
, 4);
14716 fragp
= frag_more (7 * 4);
14718 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
14719 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
14720 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
14721 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
14722 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
14723 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
14724 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
14726 subseg_set (saved_seg
, saved_subseg
);
14728 #endif /* OBJ_ELF */
14730 cur_proc_ptr
= NULL
;
14733 /* The .aent and .ent directives. */
14741 symbolP
= get_symbol ();
14742 if (*input_line_pointer
== ',')
14743 ++input_line_pointer
;
14744 SKIP_WHITESPACE ();
14745 if (ISDIGIT (*input_line_pointer
)
14746 || *input_line_pointer
== '-')
14749 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14750 as_warn (_(".ent or .aent not in text section."));
14752 if (!aent
&& cur_proc_ptr
)
14753 as_warn (_("missing .end"));
14757 /* This function needs its own .frame and .cprestore directives. */
14758 mips_frame_reg_valid
= 0;
14759 mips_cprestore_valid
= 0;
14761 cur_proc_ptr
= &cur_proc
;
14762 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14764 cur_proc_ptr
->isym
= symbolP
;
14766 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14770 if (debug_type
== DEBUG_STABS
)
14771 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14772 S_GET_NAME (symbolP
));
14775 demand_empty_rest_of_line ();
14778 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14779 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14780 s_mips_frame is used so that we can set the PDR information correctly.
14781 We can't use the ecoff routines because they make reference to the ecoff
14782 symbol table (in the mdebug section). */
14785 s_mips_frame (ignore
)
14786 int ignore ATTRIBUTE_UNUSED
;
14789 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14793 if (cur_proc_ptr
== (procS
*) NULL
)
14795 as_warn (_(".frame outside of .ent"));
14796 demand_empty_rest_of_line ();
14800 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14802 SKIP_WHITESPACE ();
14803 if (*input_line_pointer
++ != ','
14804 || get_absolute_expression_and_terminator (&val
) != ',')
14806 as_warn (_("Bad .frame directive"));
14807 --input_line_pointer
;
14808 demand_empty_rest_of_line ();
14812 cur_proc_ptr
->frame_offset
= val
;
14813 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14815 demand_empty_rest_of_line ();
14818 #endif /* OBJ_ELF */
14822 /* The .fmask and .mask directives. If the mdebug section is present
14823 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14824 embedded targets, s_mips_mask is used so that we can set the PDR
14825 information correctly. We can't use the ecoff routines because they
14826 make reference to the ecoff symbol table (in the mdebug section). */
14829 s_mips_mask (reg_type
)
14833 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14837 if (cur_proc_ptr
== (procS
*) NULL
)
14839 as_warn (_(".mask/.fmask outside of .ent"));
14840 demand_empty_rest_of_line ();
14844 if (get_absolute_expression_and_terminator (&mask
) != ',')
14846 as_warn (_("Bad .mask/.fmask directive"));
14847 --input_line_pointer
;
14848 demand_empty_rest_of_line ();
14852 off
= get_absolute_expression ();
14854 if (reg_type
== 'F')
14856 cur_proc_ptr
->fpreg_mask
= mask
;
14857 cur_proc_ptr
->fpreg_offset
= off
;
14861 cur_proc_ptr
->reg_mask
= mask
;
14862 cur_proc_ptr
->reg_offset
= off
;
14865 demand_empty_rest_of_line ();
14868 #endif /* OBJ_ELF */
14869 s_ignore (reg_type
);
14872 /* The .loc directive. */
14883 assert (now_seg
== text_section
);
14885 lineno
= get_number ();
14886 addroff
= frag_now_fix ();
14888 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14889 S_SET_TYPE (symbolP
, N_SLINE
);
14890 S_SET_OTHER (symbolP
, 0);
14891 S_SET_DESC (symbolP
, lineno
);
14892 symbolP
->sy_segment
= now_seg
;
14896 /* A table describing all the processors gas knows about. Names are
14897 matched in the order listed.
14899 To ease comparison, please keep this table in the same order as
14900 gcc's mips_cpu_info_table[]. */
14901 static const struct mips_cpu_info mips_cpu_info_table
[] =
14903 /* Entries for generic ISAs */
14904 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14905 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14906 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14907 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14908 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14909 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14910 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14911 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14914 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14915 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14916 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14919 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14922 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14923 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14924 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14925 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14926 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14927 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14928 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14929 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14930 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14931 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14932 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14933 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14936 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14937 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14938 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14939 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14940 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14941 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14942 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14943 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14944 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14945 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14946 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14947 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
14950 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
14951 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14952 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14955 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14956 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14958 /* Broadcom SB-1 CPU core */
14959 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14966 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14967 with a final "000" replaced by "k". Ignore case.
14969 Note: this function is shared between GCC and GAS. */
14972 mips_strict_matching_cpu_name_p (canonical
, given
)
14973 const char *canonical
, *given
;
14975 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14976 given
++, canonical
++;
14978 return ((*given
== 0 && *canonical
== 0)
14979 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14983 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14984 CPU name. We've traditionally allowed a lot of variation here.
14986 Note: this function is shared between GCC and GAS. */
14989 mips_matching_cpu_name_p (canonical
, given
)
14990 const char *canonical
, *given
;
14992 /* First see if the name matches exactly, or with a final "000"
14993 turned into "k". */
14994 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14997 /* If not, try comparing based on numerical designation alone.
14998 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14999 if (TOLOWER (*given
) == 'r')
15001 if (!ISDIGIT (*given
))
15004 /* Skip over some well-known prefixes in the canonical name,
15005 hoping to find a number there too. */
15006 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15008 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15010 else if (TOLOWER (canonical
[0]) == 'r')
15013 return mips_strict_matching_cpu_name_p (canonical
, given
);
15017 /* Parse an option that takes the name of a processor as its argument.
15018 OPTION is the name of the option and CPU_STRING is the argument.
15019 Return the corresponding processor enumeration if the CPU_STRING is
15020 recognized, otherwise report an error and return null.
15022 A similar function exists in GCC. */
15024 static const struct mips_cpu_info
*
15025 mips_parse_cpu (option
, cpu_string
)
15026 const char *option
, *cpu_string
;
15028 const struct mips_cpu_info
*p
;
15030 /* 'from-abi' selects the most compatible architecture for the given
15031 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15032 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15033 version. Look first at the -mgp options, if given, otherwise base
15034 the choice on MIPS_DEFAULT_64BIT.
15036 Treat NO_ABI like the EABIs. One reason to do this is that the
15037 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15038 architecture. This code picks MIPS I for 'mips' and MIPS III for
15039 'mips64', just as we did in the days before 'from-abi'. */
15040 if (strcasecmp (cpu_string
, "from-abi") == 0)
15042 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15043 return mips_cpu_info_from_isa (ISA_MIPS1
);
15045 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15046 return mips_cpu_info_from_isa (ISA_MIPS3
);
15048 if (file_mips_gp32
>= 0)
15049 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15051 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15056 /* 'default' has traditionally been a no-op. Probably not very useful. */
15057 if (strcasecmp (cpu_string
, "default") == 0)
15060 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15061 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15064 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
15068 /* Return the canonical processor information for ISA (a member of the
15069 ISA_MIPS* enumeration). */
15071 static const struct mips_cpu_info
*
15072 mips_cpu_info_from_isa (isa
)
15077 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15078 if (mips_cpu_info_table
[i
].is_isa
15079 && isa
== mips_cpu_info_table
[i
].isa
)
15080 return (&mips_cpu_info_table
[i
]);
15086 show (stream
, string
, col_p
, first_p
)
15088 const char *string
;
15094 fprintf (stream
, "%24s", "");
15099 fprintf (stream
, ", ");
15103 if (*col_p
+ strlen (string
) > 72)
15105 fprintf (stream
, "\n%24s", "");
15109 fprintf (stream
, "%s", string
);
15110 *col_p
+= strlen (string
);
15116 md_show_usage (stream
)
15122 fprintf (stream
, _("\
15124 -membedded-pic generate embedded position independent code\n\
15125 -EB generate big endian output\n\
15126 -EL generate little endian output\n\
15127 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15128 -G NUM allow referencing objects up to NUM bytes\n\
15129 implicitly with the gp register [default 8]\n"));
15130 fprintf (stream
, _("\
15131 -mips1 generate MIPS ISA I instructions\n\
15132 -mips2 generate MIPS ISA II instructions\n\
15133 -mips3 generate MIPS ISA III instructions\n\
15134 -mips4 generate MIPS ISA IV instructions\n\
15135 -mips5 generate MIPS ISA V instructions\n\
15136 -mips32 generate MIPS32 ISA instructions\n\
15137 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15138 -mips64 generate MIPS64 ISA instructions\n\
15139 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15143 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15144 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15145 show (stream
, "from-abi", &column
, &first
);
15146 fputc ('\n', stream
);
15148 fprintf (stream
, _("\
15149 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15150 -no-mCPU don't generate code specific to CPU.\n\
15151 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15155 show (stream
, "3900", &column
, &first
);
15156 show (stream
, "4010", &column
, &first
);
15157 show (stream
, "4100", &column
, &first
);
15158 show (stream
, "4650", &column
, &first
);
15159 fputc ('\n', stream
);
15161 fprintf (stream
, _("\
15162 -mips16 generate mips16 instructions\n\
15163 -no-mips16 do not generate mips16 instructions\n"));
15164 fprintf (stream
, _("\
15165 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15166 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15167 -O0 remove unneeded NOPs, do not swap branches\n\
15168 -O remove unneeded NOPs and swap branches\n\
15169 -n warn about NOPs generated from macros\n\
15170 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
15171 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15172 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15174 fprintf (stream
, _("\
15175 -KPIC, -call_shared generate SVR4 position independent code\n\
15176 -non_shared do not generate position independent code\n\
15177 -xgot assume a 32 bit GOT\n\
15178 -mabi=ABI create ABI conformant object file for:\n"));
15182 show (stream
, "32", &column
, &first
);
15183 show (stream
, "o64", &column
, &first
);
15184 show (stream
, "n32", &column
, &first
);
15185 show (stream
, "64", &column
, &first
);
15186 show (stream
, "eabi", &column
, &first
);
15188 fputc ('\n', stream
);
15190 fprintf (stream
, _("\
15191 -32 create o32 ABI object file (default)\n\
15192 -n32 create n32 ABI object file\n\
15193 -64 create 64 ABI object file\n"));
15198 mips_dwarf2_format ()
15200 if (mips_abi
== N64_ABI
)
15203 return dwarf2_format_64bit_irix
;
15205 return dwarf2_format_64bit
;
15209 return dwarf2_format_32bit
;