1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
50 #undef OBJ_PROCESS_STAB
56 #undef TARGET_SYMBOL_FIELDS
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
80 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
81 static char *mips_regmask_frag
;
86 #define PIC_CALL_REG 25
94 #define ILLEGAL_REG (32)
96 /* Allow override of standard little-endian ECOFF format. */
98 #ifndef ECOFF_LITTLE_FORMAT
99 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
102 extern int target_big_endian
;
104 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
105 32 bit ABI. This has no meaning for ECOFF. */
108 /* The default target format to use. */
110 mips_target_format ()
112 switch (OUTPUT_FLAVOR
)
114 case bfd_target_aout_flavour
:
115 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
116 case bfd_target_ecoff_flavour
:
117 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
118 case bfd_target_elf_flavour
:
119 return (target_big_endian
120 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
121 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
127 /* The name of the readonly data section. */
128 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
130 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
132 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
136 /* These variables are filled in with the masks of registers used.
137 The object format code reads them and puts them in the appropriate
139 unsigned long mips_gprmask
;
140 unsigned long mips_cprmask
[4];
142 /* MIPS ISA (Instruction Set Architecture) level (may be changed
143 temporarily using .set mipsN). */
144 static int mips_isa
= -1;
146 /* MIPS ISA we are using for this output file. */
147 static int file_mips_isa
;
149 /* Whether we are assembling for the mips16 processor. */
150 static int mips16
= -1;
152 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
153 static int mips_cpu
= -1;
155 /* Whether the 4650 instructions (mad/madu) are permitted. */
156 static int mips_4650
= -1;
158 /* Whether the 4010 instructions are permitted. */
159 static int mips_4010
= -1;
161 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
162 static int mips_4100
= -1;
164 /* start-sanitize-r5900 */
165 /* Whether Toshiba r5900 instructions are permitted. */
166 static int mips_5900
= -1;
167 /* end-sanitize-r5900 */
169 /* Whether the processor uses hardware interlocks, and thus does not
170 require nops to be inserted. */
171 static int interlocks
= -1;
173 /* As with "interlocks" this is used by hardware that has FP
174 (co-processor) interlocks. */
175 /* Itbl support may require additional care here. */
176 static int cop_interlocks
= -1;
178 /* MIPS PIC level. */
182 /* Do not generate PIC code. */
185 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
186 not sure what it is supposed to do. */
189 /* Generate PIC code as in the SVR4 MIPS ABI. */
192 /* Generate PIC code without using a global offset table: the data
193 segment has a maximum size of 64K, all data references are off
194 the $gp register, and all text references are PC relative. This
195 is used on some embedded systems. */
199 static enum mips_pic_level mips_pic
;
201 /* 1 if we should generate 32 bit offsets from the GP register in
202 SVR4_PIC mode. Currently has no meaning in other modes. */
203 static int mips_big_got
;
205 /* 1 if trap instructions should used for overflow rather than break
207 static int mips_trap
;
209 /* 1 if we should autoextend mips16 instructions. */
210 static int mips16_autoextend
= 1;
212 static int mips_warn_about_macros
;
213 static int mips_noreorder
;
214 static int mips_any_noreorder
;
215 static int mips_nomove
;
216 static int mips_noat
;
217 static int mips_nobopt
;
219 /* The size of the small data section. */
220 static int g_switch_value
= 8;
221 /* Whether the -G option was used. */
222 static int g_switch_seen
= 0;
227 /* If we can determine in advance that GP optimization won't be
228 possible, we can skip the relaxation stuff that tries to produce
229 GP-relative references. This makes delay slot optimization work
232 This function can only provide a guess, but it seems to work for
233 gcc output. If it guesses wrong, the only loss should be in
234 efficiency; it shouldn't introduce any bugs.
236 I don't know if a fix is needed for the SVR4_PIC mode. I've only
237 fixed it for the non-PIC mode. KR 95/04/07 */
238 static int nopic_need_relax
PARAMS ((symbolS
*));
240 /* handle of the OPCODE hash table */
241 static struct hash_control
*op_hash
= NULL
;
243 /* The opcode hash table we use for the mips16. */
244 static struct hash_control
*mips16_op_hash
= NULL
;
246 /* This array holds the chars that always start a comment. If the
247 pre-processor is disabled, these aren't very useful */
248 const char comment_chars
[] = "#";
250 /* This array holds the chars that only start a comment at the beginning of
251 a line. If the line seems to have the form '# 123 filename'
252 .line and .file directives will appear in the pre-processed output */
253 /* Note that input_file.c hand checks for '#' at the beginning of the
254 first line of the input file. This is because the compiler outputs
255 #NO_APP at the beginning of its output. */
256 /* Also note that C style comments are always supported. */
257 const char line_comment_chars
[] = "#";
259 /* This array holds machine specific line separator characters. */
260 const char line_separator_chars
[] = "";
262 /* Chars that can be used to separate mant from exp in floating point nums */
263 const char EXP_CHARS
[] = "eE";
265 /* Chars that mean this number is a floating point constant */
268 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
270 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
271 changed in read.c . Ideally it shouldn't have to know about it at all,
272 but nothing is ideal around here.
275 static char *insn_error
;
277 static int auto_align
= 1;
279 /* When outputting SVR4 PIC code, the assembler needs to know the
280 offset in the stack frame from which to restore the $gp register.
281 This is set by the .cprestore pseudo-op, and saved in this
283 static offsetT mips_cprestore_offset
= -1;
285 /* This is the register which holds the stack frame, as set by the
286 .frame pseudo-op. This is needed to implement .cprestore. */
287 static int mips_frame_reg
= SP
;
289 /* To output NOP instructions correctly, we need to keep information
290 about the previous two instructions. */
292 /* Whether we are optimizing. The default value of 2 means to remove
293 unneeded NOPs and swap branch instructions when possible. A value
294 of 1 means to not swap branches. A value of 0 means to always
296 static int mips_optimize
= 2;
298 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
299 equivalent to seeing no -g option at all. */
300 static int mips_debug
= 0;
302 /* The previous instruction. */
303 static struct mips_cl_insn prev_insn
;
305 /* The instruction before prev_insn. */
306 static struct mips_cl_insn prev_prev_insn
;
308 /* If we don't want information for prev_insn or prev_prev_insn, we
309 point the insn_mo field at this dummy integer. */
310 static const struct mips_opcode dummy_opcode
= { 0 };
312 /* Non-zero if prev_insn is valid. */
313 static int prev_insn_valid
;
315 /* The frag for the previous instruction. */
316 static struct frag
*prev_insn_frag
;
318 /* The offset into prev_insn_frag for the previous instruction. */
319 static long prev_insn_where
;
321 /* The reloc type for the previous instruction, if any. */
322 static bfd_reloc_code_real_type prev_insn_reloc_type
;
324 /* The reloc for the previous instruction, if any. */
325 static fixS
*prev_insn_fixp
;
327 /* Non-zero if the previous instruction was in a delay slot. */
328 static int prev_insn_is_delay_slot
;
330 /* Non-zero if the previous instruction was in a .set noreorder. */
331 static int prev_insn_unreordered
;
333 /* Non-zero if the previous instruction uses an extend opcode (if
335 static int prev_insn_extended
;
337 /* Non-zero if the previous previous instruction was in a .set
339 static int prev_prev_insn_unreordered
;
341 /* If this is set, it points to a frag holding nop instructions which
342 were inserted before the start of a noreorder section. If those
343 nops turn out to be unnecessary, the size of the frag can be
345 static fragS
*prev_nop_frag
;
347 /* The number of nop instructions we created in prev_nop_frag. */
348 static int prev_nop_frag_holds
;
350 /* The number of nop instructions that we know we need in
352 static int prev_nop_frag_required
;
354 /* The number of instructions we've seen since prev_nop_frag. */
355 static int prev_nop_frag_since
;
357 /* For ECOFF and ELF, relocations against symbols are done in two
358 parts, with a HI relocation and a LO relocation. Each relocation
359 has only 16 bits of space to store an addend. This means that in
360 order for the linker to handle carries correctly, it must be able
361 to locate both the HI and the LO relocation. This means that the
362 relocations must appear in order in the relocation table.
364 In order to implement this, we keep track of each unmatched HI
365 relocation. We then sort them so that they immediately precede the
366 corresponding LO relocation. */
371 struct mips_hi_fixup
*next
;
374 /* The section this fixup is in. */
378 /* The list of unmatched HI relocs. */
380 static struct mips_hi_fixup
*mips_hi_fixup_list
;
382 /* Map normal MIPS register numbers to mips16 register numbers. */
384 #define X ILLEGAL_REG
385 static const int mips32_to_16_reg_map
[] =
387 X
, X
, 2, 3, 4, 5, 6, 7,
388 X
, X
, X
, X
, X
, X
, X
, X
,
389 0, 1, X
, X
, X
, X
, X
, X
,
390 X
, X
, X
, X
, X
, X
, X
, X
394 /* Map mips16 register numbers to normal MIPS register numbers. */
396 static const int mips16_to_32_reg_map
[] =
398 16, 17, 2, 3, 4, 5, 6, 7
401 /* Since the MIPS does not have multiple forms of PC relative
402 instructions, we do not have to do relaxing as is done on other
403 platforms. However, we do have to handle GP relative addressing
404 correctly, which turns out to be a similar problem.
406 Every macro that refers to a symbol can occur in (at least) two
407 forms, one with GP relative addressing and one without. For
408 example, loading a global variable into a register generally uses
409 a macro instruction like this:
411 If i can be addressed off the GP register (this is true if it is in
412 the .sbss or .sdata section, or if it is known to be smaller than
413 the -G argument) this will generate the following instruction:
415 This instruction will use a GPREL reloc. If i can not be addressed
416 off the GP register, the following instruction sequence will be used:
419 In this case the first instruction will have a HI16 reloc, and the
420 second reloc will have a LO16 reloc. Both relocs will be against
423 The issue here is that we may not know whether i is GP addressable
424 until after we see the instruction that uses it. Therefore, we
425 want to be able to choose the final instruction sequence only at
426 the end of the assembly. This is similar to the way other
427 platforms choose the size of a PC relative instruction only at the
430 When generating position independent code we do not use GP
431 addressing in quite the same way, but the issue still arises as
432 external symbols and local symbols must be handled differently.
434 We handle these issues by actually generating both possible
435 instruction sequences. The longer one is put in a frag_var with
436 type rs_machine_dependent. We encode what to do with the frag in
437 the subtype field. We encode (1) the number of existing bytes to
438 replace, (2) the number of new bytes to use, (3) the offset from
439 the start of the existing bytes to the first reloc we must generate
440 (that is, the offset is applied from the start of the existing
441 bytes after they are replaced by the new bytes, if any), (4) the
442 offset from the start of the existing bytes to the second reloc,
443 (5) whether a third reloc is needed (the third reloc is always four
444 bytes after the second reloc), and (6) whether to warn if this
445 variant is used (this is sometimes needed if .set nomacro or .set
446 noat is in effect). All these numbers are reasonably small.
448 Generating two instruction sequences must be handled carefully to
449 ensure that delay slots are handled correctly. Fortunately, there
450 are a limited number of cases. When the second instruction
451 sequence is generated, append_insn is directed to maintain the
452 existing delay slot information, so it continues to apply to any
453 code after the second instruction sequence. This means that the
454 second instruction sequence must not impose any requirements not
455 required by the first instruction sequence.
457 These variant frags are then handled in functions called by the
458 machine independent code. md_estimate_size_before_relax returns
459 the final size of the frag. md_convert_frag sets up the final form
460 of the frag. tc_gen_reloc adjust the first reloc and adds a second
462 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
466 | (((reloc1) + 64) << 9) \
467 | (((reloc2) + 64) << 2) \
468 | ((reloc3) ? (1 << 1) : 0) \
470 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
471 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
472 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
473 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
474 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
475 #define RELAX_WARN(i) ((i) & 1)
477 /* For mips16 code, we use an entirely different form of relaxation.
478 mips16 supports two versions of most instructions which take
479 immediate values: a small one which takes some small value, and a
480 larger one which takes a 16 bit value. Since branches also follow
481 this pattern, relaxing these values is required.
483 We can assemble both mips16 and normal MIPS code in a single
484 object. Therefore, we need to support this type of relaxation at
485 the same time that we support the relaxation described above. We
486 use the high bit of the subtype field to distinguish these cases.
488 The information we store for this type of relaxation is the
489 argument code found in the opcode file for this relocation, whether
490 the user explicitly requested a small or extended form, and whether
491 the relocation is in a jump or jal delay slot. That tells us the
492 size of the value, and how it should be stored. We also store
493 whether the fragment is considered to be extended or not. We also
494 store whether this is known to be a branch to a different section,
495 whether we have tried to relax this frag yet, and whether we have
496 ever extended a PC relative fragment because of a shift count. */
497 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
500 | ((small) ? 0x100 : 0) \
501 | ((ext) ? 0x200 : 0) \
502 | ((dslot) ? 0x400 : 0) \
503 | ((jal_dslot) ? 0x800 : 0))
504 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
505 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
506 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
507 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
508 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
509 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
510 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
511 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
512 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
513 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
514 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
515 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
517 /* Prototypes for static functions. */
520 #define internalError() \
521 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
523 #define internalError() as_fatal ("MIPS internal Error");
526 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
528 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
529 unsigned int reg
, enum mips_regclass
class));
530 static int reg_needs_delay
PARAMS ((int));
531 static void append_insn
PARAMS ((char *place
,
532 struct mips_cl_insn
* ip
,
534 bfd_reloc_code_real_type r
,
536 static void mips_no_prev_insn
PARAMS ((int));
537 static void mips_emit_delays
PARAMS ((boolean
));
539 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
540 const char *name
, const char *fmt
,
543 static void macro_build ();
545 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
546 const char *, const char *,
548 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
549 expressionS
* ep
, int regnum
));
550 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
551 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
553 static void load_register
PARAMS ((int *, int, expressionS
*, int));
554 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
555 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
556 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
557 #ifdef LOSING_COMPILER
558 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
560 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
561 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
562 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
563 boolean
, boolean
, unsigned long *,
564 boolean
*, unsigned short *));
565 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
566 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
567 static symbolS
*get_symbol
PARAMS ((void));
568 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
569 static void s_align
PARAMS ((int));
570 static void s_change_sec
PARAMS ((int));
571 static void s_cons
PARAMS ((int));
572 static void s_float_cons
PARAMS ((int));
573 static void s_mips_globl
PARAMS ((int));
574 static void s_option
PARAMS ((int));
575 static void s_mipsset
PARAMS ((int));
576 static void s_abicalls
PARAMS ((int));
577 static void s_cpload
PARAMS ((int));
578 static void s_cprestore
PARAMS ((int));
579 static void s_gpword
PARAMS ((int));
580 static void s_cpadd
PARAMS ((int));
581 static void s_insn
PARAMS ((int));
582 static void md_obj_begin
PARAMS ((void));
583 static void md_obj_end
PARAMS ((void));
584 static long get_number
PARAMS ((void));
585 static void s_ent
PARAMS ((int));
586 static void s_mipsend
PARAMS ((int));
587 static void s_file
PARAMS ((int));
588 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
592 The following pseudo-ops from the Kane and Heinrich MIPS book
593 should be defined here, but are currently unsupported: .alias,
594 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
596 The following pseudo-ops from the Kane and Heinrich MIPS book are
597 specific to the type of debugging information being generated, and
598 should be defined by the object format: .aent, .begin, .bend,
599 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
602 The following pseudo-ops from the Kane and Heinrich MIPS book are
603 not MIPS CPU specific, but are also not specific to the object file
604 format. This file is probably the best place to define them, but
605 they are not currently supported: .asm0, .endr, .lab, .repeat,
606 .struct, .weakext. */
608 static const pseudo_typeS mips_pseudo_table
[] =
610 /* MIPS specific pseudo-ops. */
611 {"option", s_option
, 0},
612 {"set", s_mipsset
, 0},
613 {"rdata", s_change_sec
, 'r'},
614 {"sdata", s_change_sec
, 's'},
615 {"livereg", s_ignore
, 0},
616 {"abicalls", s_abicalls
, 0},
617 {"cpload", s_cpload
, 0},
618 {"cprestore", s_cprestore
, 0},
619 {"gpword", s_gpword
, 0},
620 {"cpadd", s_cpadd
, 0},
623 /* Relatively generic pseudo-ops that happen to be used on MIPS
625 {"asciiz", stringer
, 1},
626 {"bss", s_change_sec
, 'b'},
629 {"dword", s_cons
, 3},
631 /* These pseudo-ops are defined in read.c, but must be overridden
632 here for one reason or another. */
633 {"align", s_align
, 0},
635 {"data", s_change_sec
, 'd'},
636 {"double", s_float_cons
, 'd'},
637 {"float", s_float_cons
, 'f'},
638 {"globl", s_mips_globl
, 0},
639 {"global", s_mips_globl
, 0},
640 {"hword", s_cons
, 1},
645 {"short", s_cons
, 1},
646 {"single", s_float_cons
, 'f'},
647 {"text", s_change_sec
, 't'},
652 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
653 /* These pseudo-ops should be defined by the object file format.
654 However, a.out doesn't support them, so we have versions here. */
656 {"bgnb", s_ignore
, 0},
657 {"end", s_mipsend
, 0},
658 {"endb", s_ignore
, 0},
661 {"fmask", s_ignore
, 'F'},
662 {"frame", s_ignore
, 0},
663 {"loc", s_ignore
, 0},
664 {"mask", s_ignore
, 'R'},
665 {"verstamp", s_ignore
, 0},
669 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
674 pop_insert (mips_pseudo_table
);
675 if (! ECOFF_DEBUGGING
)
676 pop_insert (mips_nonecoff_pseudo_table
);
679 /* Symbols labelling the current insn. */
681 struct insn_label_list
683 struct insn_label_list
*next
;
687 static struct insn_label_list
*insn_labels
;
688 static struct insn_label_list
*free_insn_labels
;
690 static void mips_clear_insn_labels
PARAMS ((void));
693 mips_clear_insn_labels ()
695 register struct insn_label_list
**pl
;
697 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
703 static char *expr_end
;
705 /* Expressions which appear in instructions. These are set by
708 static expressionS imm_expr
;
709 static expressionS offset_expr
;
711 /* Relocs associated with imm_expr and offset_expr. */
713 static bfd_reloc_code_real_type imm_reloc
;
714 static bfd_reloc_code_real_type offset_reloc
;
716 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
718 static boolean imm_unmatched_hi
;
720 /* These are set by mips16_ip if an explicit extension is used. */
722 static boolean mips16_small
, mips16_ext
;
725 * This function is called once, at assembler startup time. It should
726 * set up all the tables, etc. that the MD part of the assembler will need.
732 register const char *retval
= NULL
;
733 register unsigned int i
= 0;
741 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
743 a
= xmalloc (sizeof TARGET_CPU
);
744 strcpy (a
, TARGET_CPU
);
745 a
[(sizeof TARGET_CPU
) - 3] = '\0';
749 if (strcmp (cpu
, "mips") == 0)
755 else if (strcmp (cpu
, "r6000") == 0
756 || strcmp (cpu
, "mips2") == 0)
762 else if (strcmp (cpu
, "mips64") == 0
763 || strcmp (cpu
, "r4000") == 0
764 || strcmp (cpu
, "mips3") == 0)
770 else if (strcmp (cpu
, "r4400") == 0)
776 else if (strcmp (cpu
, "mips64orion") == 0
777 || strcmp (cpu
, "r4600") == 0)
783 else if (strcmp (cpu
, "r4650") == 0)
791 else if (strcmp (cpu
, "mips64vr4300") == 0)
797 else if (strcmp (cpu
, "mips64vr4100") == 0)
805 else if (strcmp (cpu
, "r4010") == 0)
813 else if (strcmp (cpu
, "r5000") == 0
814 || strcmp (cpu
, "mips64vr5000") == 0)
820 /* start-sanitize-r5900 */
821 else if (strcmp (cpu
, "r5900") == 0
822 || strcmp (cpu
, "mips64vr5900") == 0
823 || strcmp (cpu
, "mips64vr5900el") == 0)
831 /* end-sanitize-r5900 */
832 else if (strcmp (cpu
, "r8000") == 0
833 || strcmp (cpu
, "mips4") == 0)
839 else if (strcmp (cpu
, "r10000") == 0)
845 else if (strcmp (cpu
, "mips16") == 0)
849 mips_cpu
= 0; /* FIXME */
864 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
879 /* start-sanitize-r5900 */
882 /* end-sanitize-r5900 */
884 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
889 /* Itbl support may require additional care here. */
890 if (mips_cpu
== 4300)
895 if (mips_isa
< 2 && mips_trap
)
896 as_bad ("trap exception not supported at ISA 1");
901 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
904 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
907 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
910 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
914 as_warn ("Could not set architecture and machine");
916 file_mips_isa
= mips_isa
;
918 op_hash
= hash_new ();
920 for (i
= 0; i
< NUMOPCODES
;)
922 const char *name
= mips_opcodes
[i
].name
;
924 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
927 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
928 mips_opcodes
[i
].name
, retval
);
929 as_fatal ("Broken assembler. No assembly attempted.");
933 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
934 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
935 != mips_opcodes
[i
].match
))
937 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
938 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
939 as_fatal ("Broken assembler. No assembly attempted.");
943 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
946 mips16_op_hash
= hash_new ();
949 while (i
< bfd_mips16_num_opcodes
)
951 const char *name
= mips16_opcodes
[i
].name
;
953 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
955 as_fatal ("internal error: can't hash `%s': %s\n",
956 mips16_opcodes
[i
].name
, retval
);
959 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
960 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
961 != mips16_opcodes
[i
].match
))
962 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
963 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
966 while (i
< bfd_mips16_num_opcodes
967 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
970 /* We add all the general register names to the symbol table. This
971 helps us detect invalid uses of them. */
972 for (i
= 0; i
< 32; i
++)
976 sprintf (buf
, "$%d", i
);
977 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
978 &zero_address_frag
));
980 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
981 &zero_address_frag
));
982 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
983 &zero_address_frag
));
984 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
985 &zero_address_frag
));
986 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
987 &zero_address_frag
));
988 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
989 &zero_address_frag
));
990 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
991 &zero_address_frag
));
992 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
993 &zero_address_frag
));
995 mips_no_prev_insn (false);
1000 mips_cprmask
[2] = 0;
1001 mips_cprmask
[3] = 0;
1003 /* set the default alignment for the text section (2**2) */
1004 record_alignment (text_section
, 2);
1006 if (USE_GLOBAL_POINTER_OPT
)
1007 bfd_set_gp_size (stdoutput
, g_switch_value
);
1009 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1011 /* On a native system, sections must be aligned to 16 byte
1012 boundaries. When configured for an embedded ELF target, we
1014 if (strcmp (TARGET_OS
, "elf") != 0)
1016 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1017 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1018 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1021 /* Create a .reginfo section for register masks and a .mdebug
1022 section for debugging information. */
1030 subseg
= now_subseg
;
1032 /* The ABI says this section should be loaded so that the
1033 running program can access it. However, we don't load it
1034 if we are configured for an embedded target */
1035 flags
= SEC_READONLY
| SEC_DATA
;
1036 if (strcmp (TARGET_OS
, "elf") != 0)
1037 flags
|= SEC_ALLOC
| SEC_LOAD
;
1041 sec
= subseg_new (".reginfo", (subsegT
) 0);
1044 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1045 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1048 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1053 /* The 64-bit ABI uses a .MIPS.options section rather than
1054 .reginfo section. */
1055 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1056 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1057 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1060 /* Set up the option header. */
1062 Elf_Internal_Options opthdr
;
1065 opthdr
.kind
= ODK_REGINFO
;
1066 opthdr
.size
= (sizeof (Elf_External_Options
)
1067 + sizeof (Elf64_External_RegInfo
));
1070 f
= frag_more (sizeof (Elf_External_Options
));
1071 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1072 (Elf_External_Options
*) f
);
1074 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1079 if (ECOFF_DEBUGGING
)
1081 sec
= subseg_new (".mdebug", (subsegT
) 0);
1082 (void) bfd_set_section_flags (stdoutput
, sec
,
1083 SEC_HAS_CONTENTS
| SEC_READONLY
);
1084 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1087 subseg_set (seg
, subseg
);
1091 if (! ECOFF_DEBUGGING
)
1098 if (! ECOFF_DEBUGGING
)
1106 struct mips_cl_insn insn
;
1108 imm_expr
.X_op
= O_absent
;
1109 imm_reloc
= BFD_RELOC_UNUSED
;
1110 imm_unmatched_hi
= false;
1111 offset_expr
.X_op
= O_absent
;
1112 offset_reloc
= BFD_RELOC_UNUSED
;
1115 mips16_ip (str
, &insn
);
1118 mips_ip (str
, &insn
);
1119 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1120 str
, insn
.insn_opcode
));
1125 as_bad ("%s `%s'", insn_error
, str
);
1129 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1132 mips16_macro (&insn
);
1138 if (imm_expr
.X_op
!= O_absent
)
1139 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1141 else if (offset_expr
.X_op
!= O_absent
)
1142 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1144 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1148 /* See whether instruction IP reads register REG. CLASS is the type
1152 insn_uses_reg (ip
, reg
, class)
1153 struct mips_cl_insn
*ip
;
1155 enum mips_regclass
class;
1157 if (class == MIPS16_REG
)
1160 reg
= mips16_to_32_reg_map
[reg
];
1161 class = MIPS_GR_REG
;
1164 /* Don't report on general register 0, since it never changes. */
1165 if (class == MIPS_GR_REG
&& reg
== 0)
1168 if (class == MIPS_FP_REG
)
1171 /* If we are called with either $f0 or $f1, we must check $f0.
1172 This is not optimal, because it will introduce an unnecessary
1173 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1174 need to distinguish reading both $f0 and $f1 or just one of
1175 them. Note that we don't have to check the other way,
1176 because there is no instruction that sets both $f0 and $f1
1177 and requires a delay. */
1178 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1179 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1180 == (reg
&~ (unsigned) 1)))
1182 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1183 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1184 == (reg
&~ (unsigned) 1)))
1189 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1190 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1192 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1193 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1198 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1199 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1201 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1202 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1204 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1205 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1206 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1208 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1210 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1212 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1214 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1215 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1216 & MIPS16OP_MASK_REGR32
) == reg
)
1223 /* This function returns true if modifying a register requires a
1227 reg_needs_delay (reg
)
1230 unsigned long prev_pinfo
;
1232 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1233 if (! mips_noreorder
1235 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1237 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1239 /* A load from a coprocessor or from memory. All load
1240 delays delay the use of general register rt for one
1241 instruction on the r3000. The r6000 and r4000 use
1243 /* Itbl support may require additional care here. */
1244 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1245 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1252 /* Output an instruction. PLACE is where to put the instruction; if
1253 it is NULL, this uses frag_more to get room. IP is the instruction
1254 information. ADDRESS_EXPR is an operand of the instruction to be
1255 used with RELOC_TYPE. */
1258 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1260 struct mips_cl_insn
*ip
;
1261 expressionS
*address_expr
;
1262 bfd_reloc_code_real_type reloc_type
;
1263 boolean unmatched_hi
;
1265 register unsigned long prev_pinfo
, pinfo
;
1270 /* Mark instruction labels in mips16 mode. This permits the linker
1271 to handle them specially, such as generating jalx instructions
1272 when needed. We also make them odd for the duration of the
1273 assembly, in order to generate the right sort of code. We will
1274 make them even in the adjust_symtab routine, while leaving them
1275 marked. This is convenient for the debugger and the
1276 disassembler. The linker knows to make them odd again. */
1279 struct insn_label_list
*l
;
1281 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1284 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1285 S_SET_OTHER (l
->label
, STO_MIPS16
);
1287 ++l
->label
->sy_value
.X_add_number
;
1291 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1292 pinfo
= ip
->insn_mo
->pinfo
;
1294 if (place
== NULL
&& (! mips_noreorder
|| prev_nop_frag
!= NULL
))
1298 /* If the previous insn required any delay slots, see if we need
1299 to insert a NOP or two. There are eight kinds of possible
1300 hazards, of which an instruction can have at most one type.
1301 (1) a load from memory delay
1302 (2) a load from a coprocessor delay
1303 (3) an unconditional branch delay
1304 (4) a conditional branch delay
1305 (5) a move to coprocessor register delay
1306 (6) a load coprocessor register from memory delay
1307 (7) a coprocessor condition code delay
1308 (8) a HI/LO special register delay
1310 There are a lot of optimizations we could do that we don't.
1311 In particular, we do not, in general, reorder instructions.
1312 If you use gcc with optimization, it will reorder
1313 instructions and generally do much more optimization then we
1314 do here; repeating all that work in the assembler would only
1315 benefit hand written assembly code, and does not seem worth
1318 /* This is how a NOP is emitted. */
1319 #define emit_nop() \
1321 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1322 : md_number_to_chars (frag_more (4), 0, 4))
1324 /* The previous insn might require a delay slot, depending upon
1325 the contents of the current insn. */
1328 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1329 && ! cop_interlocks
)
1331 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1333 /* A load from a coprocessor or from memory. All load
1334 delays delay the use of general register rt for one
1335 instruction on the r3000. The r6000 and r4000 use
1337 /* Itbl support may require additional care here. */
1338 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1339 if (mips_optimize
== 0
1340 || insn_uses_reg (ip
,
1341 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1348 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1349 && ! cop_interlocks
)
1351 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1353 /* A generic coprocessor delay. The previous instruction
1354 modified a coprocessor general or control register. If
1355 it modified a control register, we need to avoid any
1356 coprocessor instruction (this is probably not always
1357 required, but it sometimes is). If it modified a general
1358 register, we avoid using that register.
1360 On the r6000 and r4000 loading a coprocessor register
1361 from memory is interlocked, and does not require a delay.
1363 This case is not handled very well. There is no special
1364 knowledge of CP0 handling, and the coprocessors other
1365 than the floating point unit are not distinguished at
1367 /* Itbl support may require additional care here. FIXME!
1368 Need to modify this to include knowledge about
1369 user specified delays! */
1370 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1372 if (mips_optimize
== 0
1373 || insn_uses_reg (ip
,
1374 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1379 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1381 if (mips_optimize
== 0
1382 || insn_uses_reg (ip
,
1383 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1390 /* We don't know exactly what the previous instruction
1391 does. If the current instruction uses a coprocessor
1392 register, we must insert a NOP. If previous
1393 instruction may set the condition codes, and the
1394 current instruction uses them, we must insert two
1396 /* Itbl support may require additional care here. */
1397 if (mips_optimize
== 0
1398 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1399 && (pinfo
& INSN_READ_COND_CODE
)))
1401 else if (pinfo
& INSN_COP
)
1407 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1408 && ! cop_interlocks
)
1410 /* The previous instruction sets the coprocessor condition
1411 codes, but does not require a general coprocessor delay
1412 (this means it is a floating point comparison
1413 instruction). If this instruction uses the condition
1414 codes, we need to insert a single NOP. */
1415 /* Itbl support may require additional care here. */
1416 if (mips_optimize
== 0
1417 || (pinfo
& INSN_READ_COND_CODE
))
1420 else if (prev_pinfo
& INSN_READ_LO
)
1422 /* The previous instruction reads the LO register; if the
1423 current instruction writes to the LO register, we must
1424 insert two NOPS. Some newer processors have interlocks. */
1426 && (mips_optimize
== 0
1427 || (pinfo
& INSN_WRITE_LO
)))
1430 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1432 /* The previous instruction reads the HI register; if the
1433 current instruction writes to the HI register, we must
1434 insert a NOP. Some newer processors have interlocks. */
1436 && (mips_optimize
== 0
1437 || (pinfo
& INSN_WRITE_HI
)))
1441 /* If the previous instruction was in a noreorder section, then
1442 we don't want to insert the nop after all. */
1443 /* Itbl support may require additional care here. */
1444 if (prev_insn_unreordered
)
1447 /* There are two cases which require two intervening
1448 instructions: 1) setting the condition codes using a move to
1449 coprocessor instruction which requires a general coprocessor
1450 delay and then reading the condition codes 2) reading the HI
1451 or LO register and then writing to it (except on processors
1452 which have interlocks). If we are not already emitting a NOP
1453 instruction, we must check for these cases compared to the
1454 instruction previous to the previous instruction. */
1457 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1458 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1459 && (pinfo
& INSN_READ_COND_CODE
)
1460 && ! cop_interlocks
)
1461 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1462 && (pinfo
& INSN_WRITE_LO
)
1464 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1465 && (pinfo
& INSN_WRITE_HI
)
1471 if (prev_prev_insn_unreordered
)
1474 if (prev_prev_nop
&& nops
== 0)
1477 /* If we are being given a nop instruction, don't bother with
1478 one of the nops we would otherwise output. This will only
1479 happen when a nop instruction is used with mips_optimize set
1483 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1486 /* Now emit the right number of NOP instructions. */
1487 if (nops
> 0 && ! mips_noreorder
)
1490 unsigned long old_frag_offset
;
1492 struct insn_label_list
*l
;
1494 old_frag
= frag_now
;
1495 old_frag_offset
= frag_now_fix ();
1497 for (i
= 0; i
< nops
; i
++)
1502 listing_prev_line ();
1503 /* We may be at the start of a variant frag. In case we
1504 are, make sure there is enough space for the frag
1505 after the frags created by listing_prev_line. The
1506 argument to frag_grow here must be at least as large
1507 as the argument to all other calls to frag_grow in
1508 this file. We don't have to worry about being in the
1509 middle of a variant frag, because the variants insert
1510 all needed nop instructions themselves. */
1514 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1516 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1517 l
->label
->sy_frag
= frag_now
;
1518 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1519 /* mips16 text labels are stored as odd. */
1521 ++l
->label
->sy_value
.X_add_number
;
1524 #ifndef NO_ECOFF_DEBUGGING
1525 if (ECOFF_DEBUGGING
)
1526 ecoff_fix_loc (old_frag
, old_frag_offset
);
1529 else if (prev_nop_frag
!= NULL
)
1531 /* We have a frag holding nops we may be able to remove. If
1532 we don't need any nops, we can decrease the size of
1533 prev_nop_frag by the size of one instruction. If we do
1534 need some nops, we count them in prev_nops_required. */
1535 if (prev_nop_frag_since
== 0)
1539 prev_nop_frag
->fr_fix
-= mips16
? 2 : 4;
1540 --prev_nop_frag_holds
;
1543 prev_nop_frag_required
+= nops
;
1547 if (prev_prev_nop
== 0)
1549 prev_nop_frag
->fr_fix
-= mips16
? 2 : 4;
1550 --prev_nop_frag_holds
;
1553 ++prev_nop_frag_required
;
1556 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1557 prev_nop_frag
= NULL
;
1559 ++prev_nop_frag_since
;
1561 /* Sanity check: by the time we reach the second instruction
1562 after prev_nop_frag, we should have used up all the nops
1563 one way or another. */
1564 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1568 if (reloc_type
> BFD_RELOC_UNUSED
)
1570 /* We need to set up a variant frag. */
1571 assert (mips16
&& address_expr
!= NULL
);
1572 f
= frag_var (rs_machine_dependent
, 4, 0,
1573 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1574 mips16_small
, mips16_ext
,
1576 & INSN_UNCOND_BRANCH_DELAY
),
1577 (prev_insn_reloc_type
1578 == BFD_RELOC_MIPS16_JMP
)),
1579 make_expr_symbol (address_expr
), (long) 0,
1582 else if (place
!= NULL
)
1584 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1586 /* Make sure there is enough room to swap this instruction with
1587 a following jump instruction. */
1595 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1596 as_warn ("extended instruction in delay slot");
1602 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1604 if (address_expr
->X_op
== O_constant
)
1609 ip
->insn_opcode
|= address_expr
->X_add_number
;
1612 case BFD_RELOC_LO16
:
1613 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1616 case BFD_RELOC_MIPS_JMP
:
1617 if ((address_expr
->X_add_number
& 3) != 0)
1618 as_bad ("jump to misaligned address (0x%lx)",
1619 (unsigned long) address_expr
->X_add_number
);
1620 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1623 case BFD_RELOC_MIPS16_JMP
:
1624 if ((address_expr
->X_add_number
& 3) != 0)
1625 as_bad ("jump to misaligned address (0x%lx)",
1626 (unsigned long) address_expr
->X_add_number
);
1628 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1629 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1630 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1633 case BFD_RELOC_16_PCREL_S2
:
1643 /* Don't generate a reloc if we are writing into a variant
1647 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1649 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1653 struct mips_hi_fixup
*hi_fixup
;
1655 assert (reloc_type
== BFD_RELOC_HI16_S
);
1656 hi_fixup
= ((struct mips_hi_fixup
*)
1657 xmalloc (sizeof (struct mips_hi_fixup
)));
1658 hi_fixup
->fixp
= fixp
;
1659 hi_fixup
->seg
= now_seg
;
1660 hi_fixup
->next
= mips_hi_fixup_list
;
1661 mips_hi_fixup_list
= hi_fixup
;
1668 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1669 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1671 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1672 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1678 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1681 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1684 /* Update the register mask information. */
1687 if (pinfo
& INSN_WRITE_GPR_D
)
1688 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1689 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1690 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1691 if (pinfo
& INSN_READ_GPR_S
)
1692 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1693 if (pinfo
& INSN_WRITE_GPR_31
)
1694 mips_gprmask
|= 1 << 31;
1695 if (pinfo
& INSN_WRITE_FPR_D
)
1696 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1697 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1698 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1699 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1700 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1701 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1702 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1703 if (pinfo
& INSN_COP
)
1705 /* We don't keep enough information to sort these cases out.
1706 The itbl support does keep this information however, although
1707 we currently don't support itbl fprmats as part of the cop
1708 instruction. May want to add this support in the future. */
1710 /* Never set the bit for $0, which is always zero. */
1711 mips_gprmask
&=~ 1 << 0;
1715 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1716 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1717 & MIPS16OP_MASK_RX
);
1718 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1719 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1720 & MIPS16OP_MASK_RY
);
1721 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1722 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1723 & MIPS16OP_MASK_RZ
);
1724 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1725 mips_gprmask
|= 1 << TREG
;
1726 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1727 mips_gprmask
|= 1 << SP
;
1728 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1729 mips_gprmask
|= 1 << RA
;
1730 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1731 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1732 if (pinfo
& MIPS16_INSN_READ_Z
)
1733 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1734 & MIPS16OP_MASK_MOVE32Z
);
1735 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1736 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1737 & MIPS16OP_MASK_REGR32
);
1740 if (place
== NULL
&& ! mips_noreorder
)
1742 /* Filling the branch delay slot is more complex. We try to
1743 switch the branch with the previous instruction, which we can
1744 do if the previous instruction does not set up a condition
1745 that the branch tests and if the branch is not itself the
1746 target of any branch. */
1747 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1748 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1750 if (mips_optimize
< 2
1751 /* If we have seen .set volatile or .set nomove, don't
1754 /* If we had to emit any NOP instructions, then we
1755 already know we can not swap. */
1757 /* If we don't even know the previous insn, we can not
1759 || ! prev_insn_valid
1760 /* If the previous insn is already in a branch delay
1761 slot, then we can not swap. */
1762 || prev_insn_is_delay_slot
1763 /* If the previous previous insn was in a .set
1764 noreorder, we can't swap. Actually, the MIPS
1765 assembler will swap in this situation. However, gcc
1766 configured -with-gnu-as will generate code like
1772 in which we can not swap the bne and INSN. If gcc is
1773 not configured -with-gnu-as, it does not output the
1774 .set pseudo-ops. We don't have to check
1775 prev_insn_unreordered, because prev_insn_valid will
1776 be 0 in that case. We don't want to use
1777 prev_prev_insn_valid, because we do want to be able
1778 to swap at the start of a function. */
1779 || prev_prev_insn_unreordered
1780 /* If the branch is itself the target of a branch, we
1781 can not swap. We cheat on this; all we check for is
1782 whether there is a label on this instruction. If
1783 there are any branches to anything other than a
1784 label, users must use .set noreorder. */
1785 || insn_labels
!= NULL
1786 /* If the previous instruction is in a variant frag, we
1787 can not do the swap. This does not apply to the
1788 mips16, which uses variant frags for different
1791 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1792 /* If the branch reads the condition codes, we don't
1793 even try to swap, because in the sequence
1798 we can not swap, and I don't feel like handling that
1802 && (pinfo
& INSN_READ_COND_CODE
))
1803 /* We can not swap with an instruction that requires a
1804 delay slot, becase the target of the branch might
1805 interfere with that instruction. */
1809 /* Itbl support may require additional care here. */
1810 & (INSN_LOAD_COPROC_DELAY
1811 | INSN_COPROC_MOVE_DELAY
1812 | INSN_WRITE_COND_CODE
)))
1820 & (INSN_LOAD_MEMORY_DELAY
1821 /* Itbl support may require additional care here. */
1822 | INSN_COPROC_MEMORY_DELAY
)))
1823 /* We can not swap with a branch instruction. */
1825 & (INSN_UNCOND_BRANCH_DELAY
1826 | INSN_COND_BRANCH_DELAY
1827 | INSN_COND_BRANCH_LIKELY
))
1828 /* We do not swap with a trap instruction, since it
1829 complicates trap handlers to have the trap
1830 instruction be in a delay slot. */
1831 || (prev_pinfo
& INSN_TRAP
)
1832 /* If the branch reads a register that the previous
1833 instruction sets, we can not swap. */
1835 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1836 && insn_uses_reg (ip
,
1837 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1841 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1842 && insn_uses_reg (ip
,
1843 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1847 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1848 && insn_uses_reg (ip
,
1849 ((prev_insn
.insn_opcode
1851 & MIPS16OP_MASK_RX
),
1853 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1854 && insn_uses_reg (ip
,
1855 ((prev_insn
.insn_opcode
1857 & MIPS16OP_MASK_RY
),
1859 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1860 && insn_uses_reg (ip
,
1861 ((prev_insn
.insn_opcode
1863 & MIPS16OP_MASK_RZ
),
1865 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1866 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1867 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1868 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1869 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1870 && insn_uses_reg (ip
,
1871 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1874 /* If the branch writes a register that the previous
1875 instruction sets, we can not swap (we know that
1876 branches write only to RD or to $31). */
1878 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1879 && (((pinfo
& INSN_WRITE_GPR_D
)
1880 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1881 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1882 || ((pinfo
& INSN_WRITE_GPR_31
)
1883 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1887 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1888 && (((pinfo
& INSN_WRITE_GPR_D
)
1889 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1890 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1891 || ((pinfo
& INSN_WRITE_GPR_31
)
1892 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1896 && (pinfo
& MIPS16_INSN_WRITE_31
)
1897 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1898 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1899 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1901 /* If the branch writes a register that the previous
1902 instruction reads, we can not swap (we know that
1903 branches only write to RD or to $31). */
1905 && (pinfo
& INSN_WRITE_GPR_D
)
1906 && insn_uses_reg (&prev_insn
,
1907 ((ip
->insn_opcode
>> OP_SH_RD
)
1911 && (pinfo
& INSN_WRITE_GPR_31
)
1912 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1914 && (pinfo
& MIPS16_INSN_WRITE_31
)
1915 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1916 /* If we are generating embedded PIC code, the branch
1917 might be expanded into a sequence which uses $at, so
1918 we can't swap with an instruction which reads it. */
1919 || (mips_pic
== EMBEDDED_PIC
1920 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1921 /* If the previous previous instruction has a load
1922 delay, and sets a register that the branch reads, we
1926 /* Itbl support may require additional care here. */
1927 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1929 && (prev_prev_insn
.insn_mo
->pinfo
1930 & INSN_LOAD_MEMORY_DELAY
)))
1931 && insn_uses_reg (ip
,
1932 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1935 /* If one instruction sets a condition code and the
1936 other one uses a condition code, we can not swap. */
1937 || ((pinfo
& INSN_READ_COND_CODE
)
1938 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1939 || ((pinfo
& INSN_WRITE_COND_CODE
)
1940 && (prev_pinfo
& INSN_READ_COND_CODE
))
1941 /* If the previous instruction uses the PC, we can not
1944 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1945 /* If the previous instruction was extended, we can not
1947 || (mips16
&& prev_insn_extended
)
1948 /* If the previous instruction had a fixup in mips16
1949 mode, we can not swap. This normally means that the
1950 previous instruction was a 4 byte branch anyhow. */
1951 || (mips16
&& prev_insn_fixp
))
1953 /* We could do even better for unconditional branches to
1954 portions of this object file; we could pick up the
1955 instruction at the destination, put it in the delay
1956 slot, and bump the destination address. */
1958 /* Update the previous insn information. */
1959 prev_prev_insn
= *ip
;
1960 prev_insn
.insn_mo
= &dummy_opcode
;
1964 /* It looks like we can actually do the swap. */
1970 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1971 memcpy (temp
, prev_f
, 4);
1972 memcpy (prev_f
, f
, 4);
1973 memcpy (f
, temp
, 4);
1976 prev_insn_fixp
->fx_frag
= frag_now
;
1977 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1981 fixp
->fx_frag
= prev_insn_frag
;
1982 fixp
->fx_where
= prev_insn_where
;
1990 assert (prev_insn_fixp
== NULL
);
1991 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1992 memcpy (temp
, prev_f
, 2);
1993 memcpy (prev_f
, f
, 2);
1994 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1996 assert (reloc_type
== BFD_RELOC_UNUSED
);
1997 memcpy (f
, temp
, 2);
2001 memcpy (f
, f
+ 2, 2);
2002 memcpy (f
+ 2, temp
, 2);
2006 fixp
->fx_frag
= prev_insn_frag
;
2007 fixp
->fx_where
= prev_insn_where
;
2011 /* Update the previous insn information; leave prev_insn
2013 prev_prev_insn
= *ip
;
2015 prev_insn_is_delay_slot
= 1;
2017 /* If that was an unconditional branch, forget the previous
2018 insn information. */
2019 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2021 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2022 prev_insn
.insn_mo
= &dummy_opcode
;
2025 prev_insn_fixp
= NULL
;
2026 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2027 prev_insn_extended
= 0;
2029 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2031 /* We don't yet optimize a branch likely. What we should do
2032 is look at the target, copy the instruction found there
2033 into the delay slot, and increment the branch to jump to
2034 the next instruction. */
2036 /* Update the previous insn information. */
2037 prev_prev_insn
= *ip
;
2038 prev_insn
.insn_mo
= &dummy_opcode
;
2039 prev_insn_fixp
= NULL
;
2040 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2041 prev_insn_extended
= 0;
2045 /* Update the previous insn information. */
2047 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2049 prev_prev_insn
= prev_insn
;
2052 /* Any time we see a branch, we always fill the delay slot
2053 immediately; since this insn is not a branch, we know it
2054 is not in a delay slot. */
2055 prev_insn_is_delay_slot
= 0;
2057 prev_insn_fixp
= fixp
;
2058 prev_insn_reloc_type
= reloc_type
;
2060 prev_insn_extended
= (ip
->use_extend
2061 || reloc_type
> BFD_RELOC_UNUSED
);
2064 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2065 prev_insn_unreordered
= 0;
2066 prev_insn_frag
= frag_now
;
2067 prev_insn_where
= f
- frag_now
->fr_literal
;
2068 prev_insn_valid
= 1;
2070 else if (place
== NULL
)
2072 /* We need to record a bit of information even when we are not
2073 reordering, in order to determine the base address for mips16
2074 PC relative relocs. */
2075 prev_prev_insn
= prev_insn
;
2077 prev_insn_reloc_type
= reloc_type
;
2078 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2079 prev_insn_unreordered
= 1;
2082 /* We just output an insn, so the next one doesn't have a label. */
2083 mips_clear_insn_labels ();
2086 /* This function forgets that there was any previous instruction or
2087 label. If PRESERVE is non-zero, it remembers enough information to
2088 know whether nops are needed before a noreorder section. */
2091 mips_no_prev_insn (preserve
)
2096 prev_insn
.insn_mo
= &dummy_opcode
;
2097 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2098 prev_nop_frag
= NULL
;
2099 prev_nop_frag_holds
= 0;
2100 prev_nop_frag_required
= 0;
2101 prev_nop_frag_since
= 0;
2103 prev_insn_valid
= 0;
2104 prev_insn_is_delay_slot
= 0;
2105 prev_insn_unreordered
= 0;
2106 prev_insn_extended
= 0;
2107 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2108 prev_prev_insn_unreordered
= 0;
2109 mips_clear_insn_labels ();
2112 /* This function must be called whenever we turn on noreorder or emit
2113 something other than instructions. It inserts any NOPS which might
2114 be needed by the previous instruction, and clears the information
2115 kept for the previous instructions. The INSNS parameter is true if
2116 instructions are to follow. */
2119 mips_emit_delays (insns
)
2122 if (! mips_noreorder
)
2129 && (! cop_interlocks
2130 && (prev_insn
.insn_mo
->pinfo
2131 & (INSN_LOAD_COPROC_DELAY
2132 | INSN_COPROC_MOVE_DELAY
2133 | INSN_WRITE_COND_CODE
))))
2135 && (prev_insn
.insn_mo
->pinfo
2140 && (prev_insn
.insn_mo
->pinfo
2141 & (INSN_LOAD_MEMORY_DELAY
2142 | INSN_COPROC_MEMORY_DELAY
))))
2144 /* Itbl support may require additional care here. */
2148 && (! cop_interlocks
2149 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2151 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2152 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2155 if (prev_insn_unreordered
)
2160 && (! cop_interlocks
2161 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2163 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2164 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2166 /* Itbl support may require additional care here. */
2167 if (! prev_prev_insn_unreordered
)
2173 struct insn_label_list
*l
;
2177 /* Record the frag which holds the nop instructions, so
2178 that we can remove them if we don't need them. */
2179 frag_grow (mips16
? nops
* 2 : nops
* 4);
2180 prev_nop_frag
= frag_now
;
2181 prev_nop_frag_holds
= nops
;
2182 prev_nop_frag_required
= 0;
2183 prev_nop_frag_since
= 0;
2186 for (; nops
> 0; --nops
)
2191 /* Move on to a new frag, so that it is safe to simply
2192 decrease the size of prev_nop_frag. */
2193 frag_wane (frag_now
);
2197 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2199 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2200 l
->label
->sy_frag
= frag_now
;
2201 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2202 /* mips16 text labels are stored as odd. */
2204 ++l
->label
->sy_value
.X_add_number
;
2209 /* Mark instruction labels in mips16 mode. This permits the linker
2210 to handle them specially, such as generating jalx instructions
2211 when needed. We also make them odd for the duration of the
2212 assembly, in order to generate the right sort of code. We will
2213 make them even in the adjust_symtab routine, while leaving them
2214 marked. This is convenient for the debugger and the
2215 disassembler. The linker knows to make them odd again. */
2216 if (mips16
&& insns
)
2218 struct insn_label_list
*l
;
2220 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2223 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2224 S_SET_OTHER (l
->label
, STO_MIPS16
);
2226 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2227 ++l
->label
->sy_value
.X_add_number
;
2231 mips_no_prev_insn (insns
);
2234 /* Build an instruction created by a macro expansion. This is passed
2235 a pointer to the count of instructions created so far, an
2236 expression, the name of the instruction to build, an operand format
2237 string, and corresponding arguments. */
2241 macro_build (char *place
,
2249 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2258 struct mips_cl_insn insn
;
2259 bfd_reloc_code_real_type r
;
2263 va_start (args
, fmt
);
2269 * If the macro is about to expand into a second instruction,
2270 * print a warning if needed. We need to pass ip as a parameter
2271 * to generate a better warning message here...
2273 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2274 as_warn ("Macro instruction expanded into multiple instructions");
2277 *counter
+= 1; /* bump instruction counter */
2281 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2286 r
= BFD_RELOC_UNUSED
;
2287 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2288 assert (insn
.insn_mo
);
2289 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2291 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2292 || insn
.insn_mo
->pinfo
== INSN_MACRO
2293 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2295 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2297 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2299 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2301 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2303 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2305 /* start-sanitize-r5900 */
2306 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2308 /* end-sanitize-r5900 */
2312 assert (insn
.insn_mo
->name
);
2313 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2315 insn
.insn_opcode
= insn
.insn_mo
->match
;
2331 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2337 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2342 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2347 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2354 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2358 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2362 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2369 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2375 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2376 assert (r
== BFD_RELOC_MIPS_GPREL
2377 || r
== BFD_RELOC_MIPS_LITERAL
2378 || r
== BFD_RELOC_LO16
2379 || r
== BFD_RELOC_MIPS_GOT16
2380 || r
== BFD_RELOC_MIPS_CALL16
2381 || r
== BFD_RELOC_MIPS_GOT_LO16
2382 || r
== BFD_RELOC_MIPS_CALL_LO16
2383 || (ep
->X_op
== O_subtract
2384 && now_seg
== text_section
2385 && r
== BFD_RELOC_PCREL_LO16
));
2389 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2391 && (ep
->X_op
== O_constant
2392 || (ep
->X_op
== O_symbol
2393 && (r
== BFD_RELOC_HI16_S
2394 || r
== BFD_RELOC_HI16
2395 || r
== BFD_RELOC_MIPS_GOT_HI16
2396 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2397 || (ep
->X_op
== O_subtract
2398 && now_seg
== text_section
2399 && r
== BFD_RELOC_PCREL_HI16_S
)));
2400 if (ep
->X_op
== O_constant
)
2402 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2404 r
= BFD_RELOC_UNUSED
;
2409 assert (ep
!= NULL
);
2411 * This allows macro() to pass an immediate expression for
2412 * creating short branches without creating a symbol.
2413 * Note that the expression still might come from the assembly
2414 * input, in which case the value is not checked for range nor
2415 * is a relocation entry generated (yuck).
2417 if (ep
->X_op
== O_constant
)
2419 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2423 r
= BFD_RELOC_16_PCREL_S2
;
2427 assert (ep
!= NULL
);
2428 r
= BFD_RELOC_MIPS_JMP
;
2437 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2439 append_insn (place
, &insn
, ep
, r
, false);
2443 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2451 struct mips_cl_insn insn
;
2452 bfd_reloc_code_real_type r
;
2454 r
= BFD_RELOC_UNUSED
;
2455 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2456 assert (insn
.insn_mo
);
2457 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2459 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2460 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2463 assert (insn
.insn_mo
->name
);
2464 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2467 insn
.insn_opcode
= insn
.insn_mo
->match
;
2468 insn
.use_extend
= false;
2487 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2492 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2496 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2500 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2510 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2517 regno
= va_arg (args
, int);
2518 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2519 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2540 assert (ep
!= NULL
);
2542 if (ep
->X_op
!= O_constant
)
2543 r
= BFD_RELOC_UNUSED
+ c
;
2546 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2547 false, false, &insn
.insn_opcode
,
2548 &insn
.use_extend
, &insn
.extend
);
2550 r
= BFD_RELOC_UNUSED
;
2556 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2563 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2565 append_insn (place
, &insn
, ep
, r
, false);
2569 * Generate a "lui" instruction.
2572 macro_build_lui (place
, counter
, ep
, regnum
)
2578 expressionS high_expr
;
2579 struct mips_cl_insn insn
;
2580 bfd_reloc_code_real_type r
;
2581 CONST
char *name
= "lui";
2582 CONST
char *fmt
= "t,u";
2590 high_expr
.X_op
= O_constant
;
2591 high_expr
.X_add_number
= ep
->X_add_number
;
2594 if (high_expr
.X_op
== O_constant
)
2596 /* we can compute the instruction now without a relocation entry */
2597 if (high_expr
.X_add_number
& 0x8000)
2598 high_expr
.X_add_number
+= 0x10000;
2599 high_expr
.X_add_number
=
2600 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2601 r
= BFD_RELOC_UNUSED
;
2605 assert (ep
->X_op
== O_symbol
);
2606 /* _gp_disp is a special case, used from s_cpload. */
2607 assert (mips_pic
== NO_PIC
2608 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2609 r
= BFD_RELOC_HI16_S
;
2613 * If the macro is about to expand into a second instruction,
2614 * print a warning if needed. We need to pass ip as a parameter
2615 * to generate a better warning message here...
2617 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2618 as_warn ("Macro instruction expanded into multiple instructions");
2621 *counter
+= 1; /* bump instruction counter */
2623 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2624 assert (insn
.insn_mo
);
2625 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2626 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2628 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2629 if (r
== BFD_RELOC_UNUSED
)
2631 insn
.insn_opcode
|= high_expr
.X_add_number
;
2632 append_insn (place
, &insn
, NULL
, r
, false);
2635 append_insn (place
, &insn
, &high_expr
, r
, false);
2639 * Generates code to set the $at register to true (one)
2640 * if reg is less than the immediate expression.
2643 set_at (counter
, reg
, unsignedp
)
2648 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2649 macro_build ((char *) NULL
, counter
, &imm_expr
,
2650 unsignedp
? "sltiu" : "slti",
2651 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2654 load_register (counter
, AT
, &imm_expr
, 0);
2655 macro_build ((char *) NULL
, counter
, NULL
,
2656 unsignedp
? "sltu" : "slt",
2657 "d,v,t", AT
, reg
, AT
);
2661 /* Warn if an expression is not a constant. */
2664 check_absolute_expr (ip
, ex
)
2665 struct mips_cl_insn
*ip
;
2668 if (ex
->X_op
!= O_constant
)
2669 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2672 /* Count the leading zeroes by performing a binary chop. This is a
2673 bulky bit of source, but performance is a LOT better for the
2674 majority of values than a simple loop to count the bits:
2675 for (lcnt = 0; (lcnt < 32); lcnt++)
2676 if ((v) & (1 << (31 - lcnt)))
2678 However it is not code size friendly, and the gain will drop a bit
2679 on certain cached systems.
2681 #define COUNT_TOP_ZEROES(v) \
2682 (((v) & ~0xffff) == 0 \
2683 ? ((v) & ~0xff) == 0 \
2684 ? ((v) & ~0xf) == 0 \
2685 ? ((v) & ~0x3) == 0 \
2686 ? ((v) & ~0x1) == 0 \
2691 : ((v) & ~0x7) == 0 \
2694 : ((v) & ~0x3f) == 0 \
2695 ? ((v) & ~0x1f) == 0 \
2698 : ((v) & ~0x7f) == 0 \
2701 : ((v) & ~0xfff) == 0 \
2702 ? ((v) & ~0x3ff) == 0 \
2703 ? ((v) & ~0x1ff) == 0 \
2706 : ((v) & ~0x7ff) == 0 \
2709 : ((v) & ~0x3fff) == 0 \
2710 ? ((v) & ~0x1fff) == 0 \
2713 : ((v) & ~0x7fff) == 0 \
2716 : ((v) & ~0xffffff) == 0 \
2717 ? ((v) & ~0xfffff) == 0 \
2718 ? ((v) & ~0x3ffff) == 0 \
2719 ? ((v) & ~0x1ffff) == 0 \
2722 : ((v) & ~0x7ffff) == 0 \
2725 : ((v) & ~0x3fffff) == 0 \
2726 ? ((v) & ~0x1fffff) == 0 \
2729 : ((v) & ~0x7fffff) == 0 \
2732 : ((v) & ~0xfffffff) == 0 \
2733 ? ((v) & ~0x3ffffff) == 0 \
2734 ? ((v) & ~0x1ffffff) == 0 \
2737 : ((v) & ~0x7ffffff) == 0 \
2740 : ((v) & ~0x3fffffff) == 0 \
2741 ? ((v) & ~0x1fffffff) == 0 \
2744 : ((v) & ~0x7fffffff) == 0 \
2749 * This routine generates the least number of instructions neccessary to load
2750 * an absolute expression value into a register.
2753 load_register (counter
, reg
, ep
, dbl
)
2760 expressionS hi32
, lo32
;
2762 if (ep
->X_op
!= O_big
)
2764 assert (ep
->X_op
== O_constant
);
2765 if (ep
->X_add_number
< 0x8000
2766 && (ep
->X_add_number
>= 0
2767 || (ep
->X_add_number
>= -0x8000
2770 || sizeof (ep
->X_add_number
) > 4))))
2772 /* We can handle 16 bit signed values with an addiu to
2773 $zero. No need to ever use daddiu here, since $zero and
2774 the result are always correct in 32 bit mode. */
2775 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2776 (int) BFD_RELOC_LO16
);
2779 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2781 /* We can handle 16 bit unsigned values with an ori to
2783 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2784 (int) BFD_RELOC_LO16
);
2787 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2788 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2789 == ~ (offsetT
) 0x7fffffff))
2792 || sizeof (ep
->X_add_number
) > 4
2793 || (ep
->X_add_number
& 0x80000000) == 0))
2794 || ((mips_isa
< 3 || !dbl
)
2795 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2797 /* 32 bit values require an lui. */
2798 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2799 (int) BFD_RELOC_HI16
);
2800 if ((ep
->X_add_number
& 0xffff) != 0)
2801 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2802 (int) BFD_RELOC_LO16
);
2807 /* The value is larger than 32 bits. */
2811 as_bad ("Number larger than 32 bits");
2812 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2813 (int) BFD_RELOC_LO16
);
2817 if (ep
->X_op
!= O_big
)
2820 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2821 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2822 hi32
.X_add_number
&= 0xffffffff;
2824 lo32
.X_add_number
&= 0xffffffff;
2828 assert (ep
->X_add_number
> 2);
2829 if (ep
->X_add_number
== 3)
2830 generic_bignum
[3] = 0;
2831 else if (ep
->X_add_number
> 4)
2832 as_bad ("Number larger than 64 bits");
2833 lo32
.X_op
= O_constant
;
2834 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2835 hi32
.X_op
= O_constant
;
2836 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2839 if (hi32
.X_add_number
== 0)
2844 unsigned long hi
, lo
;
2846 if (hi32
.X_add_number
== 0xffffffff)
2848 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2850 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2851 reg
, 0, (int) BFD_RELOC_LO16
);
2854 if (lo32
.X_add_number
& 0x80000000)
2856 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2857 (int) BFD_RELOC_HI16
);
2858 if (lo32
.X_add_number
& 0xffff)
2859 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2860 reg
, reg
, (int) BFD_RELOC_LO16
);
2865 /* Check for 16bit shifted constant. We know that hi32 is
2866 non-zero, so start the mask on the first bit of the hi32
2871 unsigned long himask
, lomask
;
2875 himask
= 0xffff >> (32 - shift
);
2876 lomask
= (0xffff << shift
) & 0xffffffff;
2880 himask
= 0xffff << (shift
- 32);
2883 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2884 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2888 tmp
.X_op
= O_constant
;
2890 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2891 | (lo32
.X_add_number
>> shift
));
2893 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2894 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2895 (int) BFD_RELOC_LO16
);
2896 macro_build ((char *) NULL
, counter
, NULL
,
2897 (shift
>= 32) ? "dsll32" : "dsll",
2899 (shift
>= 32) ? shift
- 32 : shift
);
2903 } while (shift
<= (64 - 16));
2905 /* Find the bit number of the lowest one bit, and store the
2906 shifted value in hi/lo. */
2907 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2908 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2912 while ((lo
& 1) == 0)
2917 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2923 while ((hi
& 1) == 0)
2932 /* Optimize if the shifted value is a (power of 2) - 1. */
2933 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2934 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2936 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2941 /* This instruction will set the register to be all
2943 tmp
.X_op
= O_constant
;
2944 tmp
.X_add_number
= (offsetT
) -1;
2945 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2946 reg
, 0, (int) BFD_RELOC_LO16
);
2950 macro_build ((char *) NULL
, counter
, NULL
,
2951 (bit
>= 32) ? "dsll32" : "dsll",
2953 (bit
>= 32) ? bit
- 32 : bit
);
2955 macro_build ((char *) NULL
, counter
, NULL
,
2956 (shift
>= 32) ? "dsrl32" : "dsrl",
2958 (shift
>= 32) ? shift
- 32 : shift
);
2963 /* Sign extend hi32 before calling load_register, because we can
2964 generally get better code when we load a sign extended value. */
2965 if ((hi32
.X_add_number
& 0x80000000) != 0)
2966 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2967 load_register (counter
, reg
, &hi32
, 0);
2970 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2974 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2983 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2985 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2986 (int) BFD_RELOC_HI16
);
2987 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2994 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2999 mid16
.X_add_number
>>= 16;
3000 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3001 freg
, (int) BFD_RELOC_LO16
);
3002 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3006 if ((lo32
.X_add_number
& 0xffff) != 0)
3007 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3008 (int) BFD_RELOC_LO16
);
3011 /* Load an address into a register. */
3014 load_address (counter
, reg
, ep
)
3021 if (ep
->X_op
!= O_constant
3022 && ep
->X_op
!= O_symbol
)
3024 as_bad ("expression too complex");
3025 ep
->X_op
= O_constant
;
3028 if (ep
->X_op
== O_constant
)
3030 load_register (counter
, reg
, ep
, 0);
3034 if (mips_pic
== NO_PIC
)
3036 /* If this is a reference to a GP relative symbol, we want
3037 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3039 lui $reg,<sym> (BFD_RELOC_HI16_S)
3040 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3041 If we have an addend, we always use the latter form. */
3042 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3043 || nopic_need_relax (ep
->X_add_symbol
))
3048 macro_build ((char *) NULL
, counter
, ep
,
3049 mips_isa
< 3 ? "addiu" : "daddiu",
3050 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3051 p
= frag_var (rs_machine_dependent
, 8, 0,
3052 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
3053 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3055 macro_build_lui (p
, counter
, ep
, reg
);
3058 macro_build (p
, counter
, ep
,
3059 mips_isa
< 3 ? "addiu" : "daddiu",
3060 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3062 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3066 /* If this is a reference to an external symbol, we want
3067 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3069 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3071 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3072 If there is a constant, it must be added in after. */
3073 ex
.X_add_number
= ep
->X_add_number
;
3074 ep
->X_add_number
= 0;
3076 macro_build ((char *) NULL
, counter
, ep
,
3077 mips_isa
< 3 ? "lw" : "ld",
3078 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3079 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3080 p
= frag_var (rs_machine_dependent
, 4, 0,
3081 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
3082 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3083 macro_build (p
, counter
, ep
,
3084 mips_isa
< 3 ? "addiu" : "daddiu",
3085 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3086 if (ex
.X_add_number
!= 0)
3088 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3089 as_bad ("PIC code offset overflow (max 16 signed bits)");
3090 ex
.X_op
= O_constant
;
3091 macro_build ((char *) NULL
, counter
, &ex
,
3092 mips_isa
< 3 ? "addiu" : "daddiu",
3093 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3096 else if (mips_pic
== SVR4_PIC
)
3101 /* This is the large GOT case. If this is a reference to an
3102 external symbol, we want
3103 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3105 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3106 Otherwise, for a reference to a local symbol, we want
3107 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3109 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3110 If there is a constant, it must be added in after. */
3111 ex
.X_add_number
= ep
->X_add_number
;
3112 ep
->X_add_number
= 0;
3113 if (reg_needs_delay (GP
))
3118 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3119 (int) BFD_RELOC_MIPS_GOT_HI16
);
3120 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3121 mips_isa
< 3 ? "addu" : "daddu",
3122 "d,v,t", reg
, reg
, GP
);
3123 macro_build ((char *) NULL
, counter
, ep
,
3124 mips_isa
< 3 ? "lw" : "ld",
3125 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3126 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3127 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3128 mips_warn_about_macros
),
3129 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3132 /* We need a nop before loading from $gp. This special
3133 check is required because the lui which starts the main
3134 instruction stream does not refer to $gp, and so will not
3135 insert the nop which may be required. */
3136 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3139 macro_build (p
, counter
, ep
,
3140 mips_isa
< 3 ? "lw" : "ld",
3141 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3143 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3145 macro_build (p
, counter
, ep
,
3146 mips_isa
< 3 ? "addiu" : "daddiu",
3147 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3148 if (ex
.X_add_number
!= 0)
3150 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3151 as_bad ("PIC code offset overflow (max 16 signed bits)");
3152 ex
.X_op
= O_constant
;
3153 macro_build ((char *) NULL
, counter
, &ex
,
3154 mips_isa
< 3 ? "addiu" : "daddiu",
3155 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3158 else if (mips_pic
== EMBEDDED_PIC
)
3161 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3163 macro_build ((char *) NULL
, counter
, ep
,
3164 mips_isa
< 3 ? "addiu" : "daddiu",
3165 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3173 * This routine implements the seemingly endless macro or synthesized
3174 * instructions and addressing modes in the mips assembly language. Many
3175 * of these macros are simple and are similar to each other. These could
3176 * probably be handled by some kind of table or grammer aproach instead of
3177 * this verbose method. Others are not simple macros but are more like
3178 * optimizing code generation.
3179 * One interesting optimization is when several store macros appear
3180 * consecutivly that would load AT with the upper half of the same address.
3181 * The ensuing load upper instructions are ommited. This implies some kind
3182 * of global optimization. We currently only optimize within a single macro.
3183 * For many of the load and store macros if the address is specified as a
3184 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3185 * first load register 'at' with zero and use it as the base register. The
3186 * mips assembler simply uses register $zero. Just one tiny optimization
3191 struct mips_cl_insn
*ip
;
3193 register int treg
, sreg
, dreg
, breg
;
3208 bfd_reloc_code_real_type r
;
3210 int hold_mips_optimize
;
3214 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3215 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3216 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3217 mask
= ip
->insn_mo
->mask
;
3219 expr1
.X_op
= O_constant
;
3220 expr1
.X_op_symbol
= NULL
;
3221 expr1
.X_add_symbol
= NULL
;
3222 expr1
.X_add_number
= 1;
3234 mips_emit_delays (true);
3236 mips_any_noreorder
= 1;
3238 expr1
.X_add_number
= 8;
3239 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3241 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3243 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3244 macro_build ((char *) NULL
, &icnt
, NULL
,
3245 dbl
? "dsub" : "sub",
3246 "d,v,t", dreg
, 0, sreg
);
3269 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3271 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3272 (int) BFD_RELOC_LO16
);
3275 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3276 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3295 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3297 if (mask
!= M_NOR_I
)
3298 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3299 sreg
, (int) BFD_RELOC_LO16
);
3302 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3303 treg
, sreg
, (int) BFD_RELOC_LO16
);
3304 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3310 load_register (&icnt
, AT
, &imm_expr
, 0);
3311 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3328 if (imm_expr
.X_add_number
== 0)
3330 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3334 load_register (&icnt
, AT
, &imm_expr
, 0);
3335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3343 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3344 likely
? "bgezl" : "bgez",
3350 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3351 likely
? "blezl" : "blez",
3355 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3356 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3357 likely
? "beql" : "beq",
3364 /* check for > max integer */
3365 maxnum
= 0x7fffffff;
3373 if (imm_expr
.X_add_number
>= maxnum
3374 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3377 /* result is always false */
3380 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3381 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3385 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3386 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3391 imm_expr
.X_add_number
++;
3395 if (mask
== M_BGEL_I
)
3397 if (imm_expr
.X_add_number
== 0)
3399 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3400 likely
? "bgezl" : "bgez",
3404 if (imm_expr
.X_add_number
== 1)
3406 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3407 likely
? "bgtzl" : "bgtz",
3411 maxnum
= 0x7fffffff;
3419 maxnum
= - maxnum
- 1;
3420 if (imm_expr
.X_add_number
<= maxnum
3421 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3424 /* result is always true */
3425 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3426 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3429 set_at (&icnt
, sreg
, 0);
3430 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3431 likely
? "beql" : "beq",
3442 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3443 likely
? "beql" : "beq",
3447 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3449 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3450 likely
? "beql" : "beq",
3457 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3459 imm_expr
.X_add_number
++;
3463 if (mask
== M_BGEUL_I
)
3465 if (imm_expr
.X_add_number
== 0)
3467 if (imm_expr
.X_add_number
== 1)
3469 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3470 likely
? "bnel" : "bne",
3474 set_at (&icnt
, sreg
, 1);
3475 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3476 likely
? "beql" : "beq",
3485 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3486 likely
? "bgtzl" : "bgtz",
3492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3493 likely
? "bltzl" : "bltz",
3497 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3499 likely
? "bnel" : "bne",
3508 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3509 likely
? "bnel" : "bne",
3515 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3517 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3518 likely
? "bnel" : "bne",
3527 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3528 likely
? "blezl" : "blez",
3534 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3535 likely
? "bgezl" : "bgez",
3539 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3541 likely
? "beql" : "beq",
3548 maxnum
= 0x7fffffff;
3556 if (imm_expr
.X_add_number
>= maxnum
3557 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3559 imm_expr
.X_add_number
++;
3563 if (mask
== M_BLTL_I
)
3565 if (imm_expr
.X_add_number
== 0)
3567 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3568 likely
? "bltzl" : "bltz",
3572 if (imm_expr
.X_add_number
== 1)
3574 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3575 likely
? "blezl" : "blez",
3579 set_at (&icnt
, sreg
, 0);
3580 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3581 likely
? "bnel" : "bne",
3590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3591 likely
? "beql" : "beq",
3597 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3599 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3600 likely
? "beql" : "beq",
3607 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3609 imm_expr
.X_add_number
++;
3613 if (mask
== M_BLTUL_I
)
3615 if (imm_expr
.X_add_number
== 0)
3617 if (imm_expr
.X_add_number
== 1)
3619 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3620 likely
? "beql" : "beq",
3624 set_at (&icnt
, sreg
, 1);
3625 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3626 likely
? "bnel" : "bne",
3635 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3636 likely
? "bltzl" : "bltz",
3642 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3643 likely
? "bgtzl" : "bgtz",
3647 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3648 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3649 likely
? "bnel" : "bne",
3660 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3661 likely
? "bnel" : "bne",
3665 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3667 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3668 likely
? "bnel" : "bne",
3684 as_warn ("Divide by zero.");
3686 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3688 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3692 mips_emit_delays (true);
3694 mips_any_noreorder
= 1;
3695 macro_build ((char *) NULL
, &icnt
, NULL
,
3696 dbl
? "ddiv" : "div",
3697 "z,s,t", sreg
, treg
);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3702 expr1
.X_add_number
= 8;
3703 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3704 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3705 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3707 expr1
.X_add_number
= -1;
3708 macro_build ((char *) NULL
, &icnt
, &expr1
,
3709 dbl
? "daddiu" : "addiu",
3710 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3711 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3712 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3715 expr1
.X_add_number
= 1;
3716 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3717 (int) BFD_RELOC_LO16
);
3718 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3723 expr1
.X_add_number
= 0x80000000;
3724 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3725 (int) BFD_RELOC_HI16
);
3728 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3731 expr1
.X_add_number
= 8;
3732 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3733 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3734 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3737 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3776 if (imm_expr
.X_add_number
== 0)
3778 as_warn ("Divide by zero.");
3780 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3782 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3785 if (imm_expr
.X_add_number
== 1)
3787 if (strcmp (s2
, "mflo") == 0)
3788 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3791 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3794 if (imm_expr
.X_add_number
== -1
3795 && s
[strlen (s
) - 1] != 'u')
3797 if (strcmp (s2
, "mflo") == 0)
3800 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3803 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3807 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3811 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3812 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3813 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3832 mips_emit_delays (true);
3834 mips_any_noreorder
= 1;
3835 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3837 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3840 expr1
.X_add_number
= 8;
3841 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3842 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3843 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3846 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3852 /* Load the address of a symbol into a register. If breg is not
3853 zero, we then add a base register to it. */
3855 /* When generating embedded PIC code, we permit expressions of
3858 where bar is an address in the .text section. These are used
3859 when getting the addresses of functions. We don't permit
3860 X_add_number to be non-zero, because if the symbol is
3861 external the relaxing code needs to know that any addend is
3862 purely the offset to X_op_symbol. */
3863 if (mips_pic
== EMBEDDED_PIC
3864 && offset_expr
.X_op
== O_subtract
3865 && now_seg
== text_section
3866 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3867 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3868 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3869 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3870 ->sy_value
.X_add_symbol
)
3873 && offset_expr
.X_add_number
== 0)
3875 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3876 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3877 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3878 mips_isa
< 3 ? "addiu" : "daddiu",
3879 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3883 if (offset_expr
.X_op
!= O_symbol
3884 && offset_expr
.X_op
!= O_constant
)
3886 as_bad ("expression too complex");
3887 offset_expr
.X_op
= O_constant
;
3901 if (offset_expr
.X_op
== O_constant
)
3902 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3903 else if (mips_pic
== NO_PIC
)
3905 /* If this is a reference to an GP relative symbol, we want
3906 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3908 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3909 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3910 If we have a constant, we need two instructions anyhow,
3911 so we may as well always use the latter form. */
3912 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3913 || nopic_need_relax (offset_expr
.X_add_symbol
))
3918 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3919 mips_isa
< 3 ? "addiu" : "daddiu",
3920 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3921 p
= frag_var (rs_machine_dependent
, 8, 0,
3922 RELAX_ENCODE (4, 8, 0, 4, 0,
3923 mips_warn_about_macros
),
3924 offset_expr
.X_add_symbol
, (long) 0,
3927 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3930 macro_build (p
, &icnt
, &offset_expr
,
3931 mips_isa
< 3 ? "addiu" : "daddiu",
3932 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3934 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3936 /* If this is a reference to an external symbol, and there
3937 is no constant, we want
3938 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3939 For a local symbol, we want
3940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3942 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3944 If we have a small constant, and this is a reference to
3945 an external symbol, we want
3946 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3948 addiu $tempreg,$tempreg,<constant>
3949 For a local symbol, we want the same instruction
3950 sequence, but we output a BFD_RELOC_LO16 reloc on the
3953 If we have a large constant, and this is a reference to
3954 an external symbol, we want
3955 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3956 lui $at,<hiconstant>
3957 addiu $at,$at,<loconstant>
3958 addu $tempreg,$tempreg,$at
3959 For a local symbol, we want the same instruction
3960 sequence, but we output a BFD_RELOC_LO16 reloc on the
3961 addiu instruction. */
3962 expr1
.X_add_number
= offset_expr
.X_add_number
;
3963 offset_expr
.X_add_number
= 0;
3965 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3967 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3968 if (expr1
.X_add_number
== 0)
3976 /* We're going to put in an addu instruction using
3977 tempreg, so we may as well insert the nop right
3979 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3983 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3984 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3986 ? mips_warn_about_macros
3988 offset_expr
.X_add_symbol
, (long) 0,
3992 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3995 macro_build (p
, &icnt
, &expr1
,
3996 mips_isa
< 3 ? "addiu" : "daddiu",
3997 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3998 /* FIXME: If breg == 0, and the next instruction uses
3999 $tempreg, then if this variant case is used an extra
4000 nop will be generated. */
4002 else if (expr1
.X_add_number
>= -0x8000
4003 && expr1
.X_add_number
< 0x8000)
4005 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4007 macro_build ((char *) NULL
, &icnt
, &expr1
,
4008 mips_isa
< 3 ? "addiu" : "daddiu",
4009 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4010 (void) frag_var (rs_machine_dependent
, 0, 0,
4011 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4012 offset_expr
.X_add_symbol
, (long) 0,
4019 /* If we are going to add in a base register, and the
4020 target register and the base register are the same,
4021 then we are using AT as a temporary register. Since
4022 we want to load the constant into AT, we add our
4023 current AT (from the global offset table) and the
4024 register into the register now, and pretend we were
4025 not using a base register. */
4030 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4032 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4033 mips_isa
< 3 ? "addu" : "daddu",
4034 "d,v,t", treg
, AT
, breg
);
4040 /* Set mips_optimize around the lui instruction to avoid
4041 inserting an unnecessary nop after the lw. */
4042 hold_mips_optimize
= mips_optimize
;
4044 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4045 mips_optimize
= hold_mips_optimize
;
4047 macro_build ((char *) NULL
, &icnt
, &expr1
,
4048 mips_isa
< 3 ? "addiu" : "daddiu",
4049 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4050 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4051 mips_isa
< 3 ? "addu" : "daddu",
4052 "d,v,t", tempreg
, tempreg
, AT
);
4053 (void) frag_var (rs_machine_dependent
, 0, 0,
4054 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4055 offset_expr
.X_add_symbol
, (long) 0,
4060 else if (mips_pic
== SVR4_PIC
)
4064 /* This is the large GOT case. If this is a reference to an
4065 external symbol, and there is no constant, we want
4066 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4067 addu $tempreg,$tempreg,$gp
4068 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4069 For a local symbol, we want
4070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4072 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4074 If we have a small constant, and this is a reference to
4075 an external symbol, we want
4076 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4077 addu $tempreg,$tempreg,$gp
4078 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4080 addiu $tempreg,$tempreg,<constant>
4081 For a local symbol, we want
4082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4084 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4086 If we have a large constant, and this is a reference to
4087 an external symbol, we want
4088 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4089 addu $tempreg,$tempreg,$gp
4090 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4091 lui $at,<hiconstant>
4092 addiu $at,$at,<loconstant>
4093 addu $tempreg,$tempreg,$at
4094 For a local symbol, we want
4095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4096 lui $at,<hiconstant>
4097 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4098 addu $tempreg,$tempreg,$at
4100 expr1
.X_add_number
= offset_expr
.X_add_number
;
4101 offset_expr
.X_add_number
= 0;
4103 if (reg_needs_delay (GP
))
4107 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4108 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4109 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4110 mips_isa
< 3 ? "addu" : "daddu",
4111 "d,v,t", tempreg
, tempreg
, GP
);
4112 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4114 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4116 if (expr1
.X_add_number
== 0)
4124 /* We're going to put in an addu instruction using
4125 tempreg, so we may as well insert the nop right
4127 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4132 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4133 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4136 ? mips_warn_about_macros
4138 offset_expr
.X_add_symbol
, (long) 0,
4141 else if (expr1
.X_add_number
>= -0x8000
4142 && expr1
.X_add_number
< 0x8000)
4144 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4146 macro_build ((char *) NULL
, &icnt
, &expr1
,
4147 mips_isa
< 3 ? "addiu" : "daddiu",
4148 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4150 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4151 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4153 ? mips_warn_about_macros
4155 offset_expr
.X_add_symbol
, (long) 0,
4162 /* If we are going to add in a base register, and the
4163 target register and the base register are the same,
4164 then we are using AT as a temporary register. Since
4165 we want to load the constant into AT, we add our
4166 current AT (from the global offset table) and the
4167 register into the register now, and pretend we were
4168 not using a base register. */
4176 assert (tempreg
== AT
);
4177 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4179 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4180 mips_isa
< 3 ? "addu" : "daddu",
4181 "d,v,t", treg
, AT
, breg
);
4186 /* Set mips_optimize around the lui instruction to avoid
4187 inserting an unnecessary nop after the lw. */
4188 hold_mips_optimize
= mips_optimize
;
4190 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4191 mips_optimize
= hold_mips_optimize
;
4193 macro_build ((char *) NULL
, &icnt
, &expr1
,
4194 mips_isa
< 3 ? "addiu" : "daddiu",
4195 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4196 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4197 mips_isa
< 3 ? "addu" : "daddu",
4198 "d,v,t", dreg
, dreg
, AT
);
4200 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4201 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4204 ? mips_warn_about_macros
4206 offset_expr
.X_add_symbol
, (long) 0,
4214 /* This is needed because this instruction uses $gp, but
4215 the first instruction on the main stream does not. */
4216 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4219 macro_build (p
, &icnt
, &offset_expr
,
4221 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4223 if (expr1
.X_add_number
>= -0x8000
4224 && expr1
.X_add_number
< 0x8000)
4226 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4228 macro_build (p
, &icnt
, &expr1
,
4229 mips_isa
< 3 ? "addiu" : "daddiu",
4230 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4231 /* FIXME: If add_number is 0, and there was no base
4232 register, the external symbol case ended with a load,
4233 so if the symbol turns out to not be external, and
4234 the next instruction uses tempreg, an unnecessary nop
4235 will be inserted. */
4241 /* We must add in the base register now, as in the
4242 external symbol case. */
4243 assert (tempreg
== AT
);
4244 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4246 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4247 mips_isa
< 3 ? "addu" : "daddu",
4248 "d,v,t", treg
, AT
, breg
);
4251 /* We set breg to 0 because we have arranged to add
4252 it in in both cases. */
4256 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4258 macro_build (p
, &icnt
, &expr1
,
4259 mips_isa
< 3 ? "addiu" : "daddiu",
4260 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4262 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4263 mips_isa
< 3 ? "addu" : "daddu",
4264 "d,v,t", tempreg
, tempreg
, AT
);
4268 else if (mips_pic
== EMBEDDED_PIC
)
4271 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4273 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4274 mips_isa
< 3 ? "addiu" : "daddiu",
4275 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4281 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4282 mips_isa
< 3 ? "addu" : "daddu",
4283 "d,v,t", treg
, tempreg
, breg
);
4291 /* The j instruction may not be used in PIC code, since it
4292 requires an absolute address. We convert it to a b
4294 if (mips_pic
== NO_PIC
)
4295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4297 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4300 /* The jal instructions must be handled as macros because when
4301 generating PIC code they expand to multi-instruction
4302 sequences. Normally they are simple instructions. */
4307 if (mips_pic
== NO_PIC
4308 || mips_pic
== EMBEDDED_PIC
)
4309 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4311 else if (mips_pic
== SVR4_PIC
)
4313 if (sreg
!= PIC_CALL_REG
)
4314 as_warn ("MIPS PIC call to register other than $25");
4316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4318 if (mips_cprestore_offset
< 0)
4319 as_warn ("No .cprestore pseudo-op used in PIC code");
4322 expr1
.X_add_number
= mips_cprestore_offset
;
4323 macro_build ((char *) NULL
, &icnt
, &expr1
,
4324 mips_isa
< 3 ? "lw" : "ld",
4325 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4334 if (mips_pic
== NO_PIC
)
4335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4336 else if (mips_pic
== SVR4_PIC
)
4338 /* If this is a reference to an external symbol, and we are
4339 using a small GOT, we want
4340 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4344 lw $gp,cprestore($sp)
4345 The cprestore value is set using the .cprestore
4346 pseudo-op. If we are using a big GOT, we want
4347 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4349 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4353 lw $gp,cprestore($sp)
4354 If the symbol is not external, we want
4355 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4357 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4360 lw $gp,cprestore($sp) */
4364 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4365 mips_isa
< 3 ? "lw" : "ld",
4366 "t,o(b)", PIC_CALL_REG
,
4367 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4368 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4370 p
= frag_var (rs_machine_dependent
, 4, 0,
4371 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4372 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4378 if (reg_needs_delay (GP
))
4382 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4383 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4385 mips_isa
< 3 ? "addu" : "daddu",
4386 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4387 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4388 mips_isa
< 3 ? "lw" : "ld",
4389 "t,o(b)", PIC_CALL_REG
,
4390 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4391 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4393 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4394 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4396 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4399 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4402 macro_build (p
, &icnt
, &offset_expr
,
4403 mips_isa
< 3 ? "lw" : "ld",
4404 "t,o(b)", PIC_CALL_REG
,
4405 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4407 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4410 macro_build (p
, &icnt
, &offset_expr
,
4411 mips_isa
< 3 ? "addiu" : "daddiu",
4412 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4413 (int) BFD_RELOC_LO16
);
4414 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4415 "jalr", "s", PIC_CALL_REG
);
4416 if (mips_cprestore_offset
< 0)
4417 as_warn ("No .cprestore pseudo-op used in PIC code");
4421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4423 expr1
.X_add_number
= mips_cprestore_offset
;
4424 macro_build ((char *) NULL
, &icnt
, &expr1
,
4425 mips_isa
< 3 ? "lw" : "ld",
4426 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4430 else if (mips_pic
== EMBEDDED_PIC
)
4432 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4433 /* The linker may expand the call to a longer sequence which
4434 uses $at, so we must break rather than return. */
4459 /* Itbl support may require additional care here. */
4464 /* Itbl support may require additional care here. */
4469 /* Itbl support may require additional care here. */
4474 /* Itbl support may require additional care here. */
4487 /* Itbl support may require additional care here. */
4492 /* Itbl support may require additional care here. */
4497 /* Itbl support may require additional care here. */
4517 if (breg
== treg
|| coproc
|| lr
)
4539 /* Itbl support may require additional care here. */
4544 /* Itbl support may require additional care here. */
4549 /* Itbl support may require additional care here. */
4554 /* Itbl support may require additional care here. */
4572 /* Itbl support may require additional care here. */
4576 /* Itbl support may require additional care here. */
4581 /* Itbl support may require additional care here. */
4593 /* Itbl support may require additional care here. */
4594 if (mask
== M_LWC1_AB
4595 || mask
== M_SWC1_AB
4596 || mask
== M_LDC1_AB
4597 || mask
== M_SDC1_AB
4606 if (offset_expr
.X_op
!= O_constant
4607 && offset_expr
.X_op
!= O_symbol
)
4609 as_bad ("expression too complex");
4610 offset_expr
.X_op
= O_constant
;
4613 /* A constant expression in PIC code can be handled just as it
4614 is in non PIC code. */
4615 if (mips_pic
== NO_PIC
4616 || offset_expr
.X_op
== O_constant
)
4618 /* If this is a reference to a GP relative symbol, and there
4619 is no base register, we want
4620 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4621 Otherwise, if there is no base register, we want
4622 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4623 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4624 If we have a constant, we need two instructions anyhow,
4625 so we always use the latter form.
4627 If we have a base register, and this is a reference to a
4628 GP relative symbol, we want
4629 addu $tempreg,$breg,$gp
4630 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4632 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4633 addu $tempreg,$tempreg,$breg
4634 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4635 With a constant we always use the latter case. */
4638 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4639 || nopic_need_relax (offset_expr
.X_add_symbol
))
4644 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4645 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4646 p
= frag_var (rs_machine_dependent
, 8, 0,
4647 RELAX_ENCODE (4, 8, 0, 4, 0,
4648 (mips_warn_about_macros
4649 || (used_at
&& mips_noat
))),
4650 offset_expr
.X_add_symbol
, (long) 0,
4654 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4657 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4658 (int) BFD_RELOC_LO16
, tempreg
);
4662 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4663 || nopic_need_relax (offset_expr
.X_add_symbol
))
4668 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4669 mips_isa
< 3 ? "addu" : "daddu",
4670 "d,v,t", tempreg
, breg
, GP
);
4671 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4672 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4673 p
= frag_var (rs_machine_dependent
, 12, 0,
4674 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4675 offset_expr
.X_add_symbol
, (long) 0,
4678 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4681 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4682 mips_isa
< 3 ? "addu" : "daddu",
4683 "d,v,t", tempreg
, tempreg
, breg
);
4686 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4687 (int) BFD_RELOC_LO16
, tempreg
);
4690 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4692 /* If this is a reference to an external symbol, we want
4693 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4695 <op> $treg,0($tempreg)
4697 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4699 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4700 <op> $treg,0($tempreg)
4701 If there is a base register, we add it to $tempreg before
4702 the <op>. If there is a constant, we stick it in the
4703 <op> instruction. We don't handle constants larger than
4704 16 bits, because we have no way to load the upper 16 bits
4705 (actually, we could handle them for the subset of cases
4706 in which we are not using $at). */
4707 assert (offset_expr
.X_op
== O_symbol
);
4708 expr1
.X_add_number
= offset_expr
.X_add_number
;
4709 offset_expr
.X_add_number
= 0;
4710 if (expr1
.X_add_number
< -0x8000
4711 || expr1
.X_add_number
>= 0x8000)
4712 as_bad ("PIC code offset overflow (max 16 signed bits)");
4714 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4715 mips_isa
< 3 ? "lw" : "ld",
4716 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4718 p
= frag_var (rs_machine_dependent
, 4, 0,
4719 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4720 offset_expr
.X_add_symbol
, (long) 0,
4722 macro_build (p
, &icnt
, &offset_expr
,
4723 mips_isa
< 3 ? "addiu" : "daddiu",
4724 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4727 mips_isa
< 3 ? "addu" : "daddu",
4728 "d,v,t", tempreg
, tempreg
, breg
);
4729 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4730 (int) BFD_RELOC_LO16
, tempreg
);
4732 else if (mips_pic
== SVR4_PIC
)
4736 /* If this is a reference to an external symbol, we want
4737 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4738 addu $tempreg,$tempreg,$gp
4739 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4740 <op> $treg,0($tempreg)
4742 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4744 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4745 <op> $treg,0($tempreg)
4746 If there is a base register, we add it to $tempreg before
4747 the <op>. If there is a constant, we stick it in the
4748 <op> instruction. We don't handle constants larger than
4749 16 bits, because we have no way to load the upper 16 bits
4750 (actually, we could handle them for the subset of cases
4751 in which we are not using $at). */
4752 assert (offset_expr
.X_op
== O_symbol
);
4753 expr1
.X_add_number
= offset_expr
.X_add_number
;
4754 offset_expr
.X_add_number
= 0;
4755 if (expr1
.X_add_number
< -0x8000
4756 || expr1
.X_add_number
>= 0x8000)
4757 as_bad ("PIC code offset overflow (max 16 signed bits)");
4758 if (reg_needs_delay (GP
))
4763 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4764 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4765 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4766 mips_isa
< 3 ? "addu" : "daddu",
4767 "d,v,t", tempreg
, tempreg
, GP
);
4768 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4769 mips_isa
< 3 ? "lw" : "ld",
4770 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4772 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4773 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4774 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4777 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4780 macro_build (p
, &icnt
, &offset_expr
,
4781 mips_isa
< 3 ? "lw" : "ld",
4782 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4784 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4786 macro_build (p
, &icnt
, &offset_expr
,
4787 mips_isa
< 3 ? "addiu" : "daddiu",
4788 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4790 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4791 mips_isa
< 3 ? "addu" : "daddu",
4792 "d,v,t", tempreg
, tempreg
, breg
);
4793 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4794 (int) BFD_RELOC_LO16
, tempreg
);
4796 else if (mips_pic
== EMBEDDED_PIC
)
4798 /* If there is no base register, we want
4799 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4800 If there is a base register, we want
4801 addu $tempreg,$breg,$gp
4802 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4804 assert (offset_expr
.X_op
== O_symbol
);
4807 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4808 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4813 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4814 mips_isa
< 3 ? "addu" : "daddu",
4815 "d,v,t", tempreg
, breg
, GP
);
4816 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4817 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4830 load_register (&icnt
, treg
, &imm_expr
, 0);
4834 load_register (&icnt
, treg
, &imm_expr
, 1);
4838 if (imm_expr
.X_op
== O_constant
)
4840 load_register (&icnt
, AT
, &imm_expr
, 0);
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4842 "mtc1", "t,G", AT
, treg
);
4847 assert (offset_expr
.X_op
== O_symbol
4848 && strcmp (segment_name (S_GET_SEGMENT
4849 (offset_expr
.X_add_symbol
)),
4851 && offset_expr
.X_add_number
== 0);
4852 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4853 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4858 /* We know that sym is in the .rdata section. First we get the
4859 upper 16 bits of the address. */
4860 if (mips_pic
== NO_PIC
)
4862 /* FIXME: This won't work for a 64 bit address. */
4863 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4865 else if (mips_pic
== SVR4_PIC
)
4867 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4868 mips_isa
< 3 ? "lw" : "ld",
4869 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4871 else if (mips_pic
== EMBEDDED_PIC
)
4873 /* For embedded PIC we pick up the entire address off $gp in
4874 a single instruction. */
4875 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4876 mips_isa
< 3 ? "addiu" : "daddiu",
4877 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4878 offset_expr
.X_op
= O_constant
;
4879 offset_expr
.X_add_number
= 0;
4884 /* Now we load the register(s). */
4886 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4887 treg
, (int) BFD_RELOC_LO16
, AT
);
4890 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4891 treg
, (int) BFD_RELOC_LO16
, AT
);
4894 /* FIXME: How in the world do we deal with the possible
4896 offset_expr
.X_add_number
+= 4;
4897 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4898 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4902 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4903 does not become a variant frag. */
4904 frag_wane (frag_now
);
4910 assert (offset_expr
.X_op
== O_symbol
4911 && offset_expr
.X_add_number
== 0);
4912 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4913 if (strcmp (s
, ".lit8") == 0)
4917 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4918 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4922 r
= BFD_RELOC_MIPS_LITERAL
;
4927 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4928 if (mips_pic
== SVR4_PIC
)
4929 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4930 mips_isa
< 3 ? "lw" : "ld",
4931 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4934 /* FIXME: This won't work for a 64 bit address. */
4935 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4940 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4941 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4943 /* To avoid confusion in tc_gen_reloc, we must ensure
4944 that this does not become a variant frag. */
4945 frag_wane (frag_now
);
4956 /* Even on a big endian machine $fn comes before $fn+1. We have
4957 to adjust when loading from memory. */
4960 assert (mips_isa
< 2);
4961 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4962 target_big_endian
? treg
+ 1 : treg
,
4964 /* FIXME: A possible overflow which I don't know how to deal
4966 offset_expr
.X_add_number
+= 4;
4967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4968 target_big_endian
? treg
: treg
+ 1,
4971 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4972 does not become a variant frag. */
4973 frag_wane (frag_now
);
4982 * The MIPS assembler seems to check for X_add_number not
4983 * being double aligned and generating:
4986 * addiu at,at,%lo(foo+1)
4989 * But, the resulting address is the same after relocation so why
4990 * generate the extra instruction?
4992 /* Itbl support may require additional care here. */
5013 /* Itbl support may require additional care here. */
5039 if (offset_expr
.X_op
!= O_symbol
5040 && offset_expr
.X_op
!= O_constant
)
5042 as_bad ("expression too complex");
5043 offset_expr
.X_op
= O_constant
;
5046 /* Even on a big endian machine $fn comes before $fn+1. We have
5047 to adjust when loading from memory. We set coproc if we must
5048 load $fn+1 first. */
5049 /* Itbl support may require additional care here. */
5050 if (! target_big_endian
)
5053 if (mips_pic
== NO_PIC
5054 || offset_expr
.X_op
== O_constant
)
5056 /* If this is a reference to a GP relative symbol, we want
5057 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5058 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5059 If we have a base register, we use this
5061 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5062 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5063 If this is not a GP relative symbol, we want
5064 lui $at,<sym> (BFD_RELOC_HI16_S)
5065 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5066 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5067 If there is a base register, we add it to $at after the
5068 lui instruction. If there is a constant, we always use
5070 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5071 || nopic_need_relax (offset_expr
.X_add_symbol
))
5090 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5091 mips_isa
< 3 ? "addu" : "daddu",
5092 "d,v,t", AT
, breg
, GP
);
5098 /* Itbl support may require additional care here. */
5099 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5100 coproc
? treg
+ 1 : treg
,
5101 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5102 offset_expr
.X_add_number
+= 4;
5104 /* Set mips_optimize to 2 to avoid inserting an
5106 hold_mips_optimize
= mips_optimize
;
5108 /* Itbl support may require additional care here. */
5109 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5110 coproc
? treg
: treg
+ 1,
5111 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5112 mips_optimize
= hold_mips_optimize
;
5114 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5115 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5116 used_at
&& mips_noat
),
5117 offset_expr
.X_add_symbol
, (long) 0,
5120 /* We just generated two relocs. When tc_gen_reloc
5121 handles this case, it will skip the first reloc and
5122 handle the second. The second reloc already has an
5123 extra addend of 4, which we added above. We must
5124 subtract it out, and then subtract another 4 to make
5125 the first reloc come out right. The second reloc
5126 will come out right because we are going to add 4 to
5127 offset_expr when we build its instruction below. */
5128 offset_expr
.X_add_number
-= 8;
5129 offset_expr
.X_op
= O_constant
;
5131 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5136 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5137 mips_isa
< 3 ? "addu" : "daddu",
5138 "d,v,t", AT
, breg
, AT
);
5142 /* Itbl support may require additional care here. */
5143 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5144 coproc
? treg
+ 1 : treg
,
5145 (int) BFD_RELOC_LO16
, AT
);
5148 /* FIXME: How do we handle overflow here? */
5149 offset_expr
.X_add_number
+= 4;
5150 /* Itbl support may require additional care here. */
5151 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5152 coproc
? treg
: treg
+ 1,
5153 (int) BFD_RELOC_LO16
, AT
);
5155 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5159 /* If this is a reference to an external symbol, we want
5160 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5165 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5167 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5168 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5169 If there is a base register we add it to $at before the
5170 lwc1 instructions. If there is a constant we include it
5171 in the lwc1 instructions. */
5173 expr1
.X_add_number
= offset_expr
.X_add_number
;
5174 offset_expr
.X_add_number
= 0;
5175 if (expr1
.X_add_number
< -0x8000
5176 || expr1
.X_add_number
>= 0x8000 - 4)
5177 as_bad ("PIC code offset overflow (max 16 signed bits)");
5182 frag_grow (24 + off
);
5183 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5184 mips_isa
< 3 ? "lw" : "ld",
5185 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5186 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5188 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5189 mips_isa
< 3 ? "addu" : "daddu",
5190 "d,v,t", AT
, breg
, AT
);
5191 /* Itbl support may require additional care here. */
5192 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5193 coproc
? treg
+ 1 : treg
,
5194 (int) BFD_RELOC_LO16
, AT
);
5195 expr1
.X_add_number
+= 4;
5197 /* Set mips_optimize to 2 to avoid inserting an undesired
5199 hold_mips_optimize
= mips_optimize
;
5201 /* Itbl support may require additional care here. */
5202 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5203 coproc
? treg
: treg
+ 1,
5204 (int) BFD_RELOC_LO16
, AT
);
5205 mips_optimize
= hold_mips_optimize
;
5207 (void) frag_var (rs_machine_dependent
, 0, 0,
5208 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5209 offset_expr
.X_add_symbol
, (long) 0,
5212 else if (mips_pic
== SVR4_PIC
)
5216 /* If this is a reference to an external symbol, we want
5217 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5219 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5224 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5226 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5227 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5228 If there is a base register we add it to $at before the
5229 lwc1 instructions. If there is a constant we include it
5230 in the lwc1 instructions. */
5232 expr1
.X_add_number
= offset_expr
.X_add_number
;
5233 offset_expr
.X_add_number
= 0;
5234 if (expr1
.X_add_number
< -0x8000
5235 || expr1
.X_add_number
>= 0x8000 - 4)
5236 as_bad ("PIC code offset overflow (max 16 signed bits)");
5237 if (reg_needs_delay (GP
))
5246 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5247 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5249 mips_isa
< 3 ? "addu" : "daddu",
5250 "d,v,t", AT
, AT
, GP
);
5251 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5252 mips_isa
< 3 ? "lw" : "ld",
5253 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5254 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5257 mips_isa
< 3 ? "addu" : "daddu",
5258 "d,v,t", AT
, breg
, AT
);
5259 /* Itbl support may require additional care here. */
5260 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5261 coproc
? treg
+ 1 : treg
,
5262 (int) BFD_RELOC_LO16
, AT
);
5263 expr1
.X_add_number
+= 4;
5265 /* Set mips_optimize to 2 to avoid inserting an undesired
5267 hold_mips_optimize
= mips_optimize
;
5269 /* Itbl support may require additional care here. */
5270 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5271 coproc
? treg
: treg
+ 1,
5272 (int) BFD_RELOC_LO16
, AT
);
5273 mips_optimize
= hold_mips_optimize
;
5274 expr1
.X_add_number
-= 4;
5276 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5277 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5278 8 + gpdel
+ off
, 1, 0),
5279 offset_expr
.X_add_symbol
, (long) 0,
5283 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5286 macro_build (p
, &icnt
, &offset_expr
,
5287 mips_isa
< 3 ? "lw" : "ld",
5288 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5290 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5294 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5295 mips_isa
< 3 ? "addu" : "daddu",
5296 "d,v,t", AT
, breg
, AT
);
5299 /* Itbl support may require additional care here. */
5300 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5301 coproc
? treg
+ 1 : treg
,
5302 (int) BFD_RELOC_LO16
, AT
);
5304 expr1
.X_add_number
+= 4;
5306 /* Set mips_optimize to 2 to avoid inserting an undesired
5308 hold_mips_optimize
= mips_optimize
;
5310 /* Itbl support may require additional care here. */
5311 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5312 coproc
? treg
: treg
+ 1,
5313 (int) BFD_RELOC_LO16
, AT
);
5314 mips_optimize
= hold_mips_optimize
;
5316 else if (mips_pic
== EMBEDDED_PIC
)
5318 /* If there is no base register, we use
5319 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5320 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5321 If we have a base register, we use
5323 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5324 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5333 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5334 mips_isa
< 3 ? "addu" : "daddu",
5335 "d,v,t", AT
, breg
, GP
);
5340 /* Itbl support may require additional care here. */
5341 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5342 coproc
? treg
+ 1 : treg
,
5343 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5344 offset_expr
.X_add_number
+= 4;
5345 /* Itbl support may require additional care here. */
5346 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5347 coproc
? treg
: treg
+ 1,
5348 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5364 assert (mips_isa
< 3);
5365 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5366 (int) BFD_RELOC_LO16
, breg
);
5367 offset_expr
.X_add_number
+= 4;
5368 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5369 (int) BFD_RELOC_LO16
, breg
);
5372 /* New code added to support COPZ instructions.
5373 This code builds table entries out of the macros in mip_opcodes.
5374 R4000 uses interlocks to handle coproc delays.
5375 Other chips (like the R3000) require nops to be inserted for delays.
5377 FIXME: Currently, we require that the user handle delays.
5378 In order to fill delay slots for non-interlocked chips,
5379 we must have a way to specify delays based on the coprocessor.
5380 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5381 What are the side-effects of the cop instruction?
5382 What cache support might we have and what are its effects?
5383 Both coprocessor & memory require delays. how long???
5384 What registers are read/set/modified?
5386 If an itbl is provided to interpret cop instructions,
5387 this knowledge can be encoded in the itbl spec. */
5401 /* For now we just do C (same as Cz). */
5402 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5405 #ifdef LOSING_COMPILER
5407 /* Try and see if this is a new itbl instruction.
5408 This code builds table entries out of the macros in mip_opcodes.
5409 FIXME: For now we just assemble the expression and pass it's
5410 value along as a 32-bit immediate.
5411 We may want to have the assembler assemble this value,
5412 so that we gain the assembler's knowledge of delay slots,
5414 Would it be more efficient to use mask (id) here? */
5415 if (itbl_have_entries
5416 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5418 s
= ip
->insn_mo
->name
;
5420 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5421 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5428 as_warn ("Macro used $at after \".set noat\"");
5433 struct mips_cl_insn
*ip
;
5435 register int treg
, sreg
, dreg
, breg
;
5450 bfd_reloc_code_real_type r
;
5453 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5454 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5455 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5456 mask
= ip
->insn_mo
->mask
;
5458 expr1
.X_op
= O_constant
;
5459 expr1
.X_op_symbol
= NULL
;
5460 expr1
.X_add_symbol
= NULL
;
5461 expr1
.X_add_number
= 1;
5465 #endif /* LOSING_COMPILER */
5470 macro_build ((char *) NULL
, &icnt
, NULL
,
5471 dbl
? "dmultu" : "multu",
5473 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5479 /* The MIPS assembler some times generates shifts and adds. I'm
5480 not trying to be that fancy. GCC should do this for us
5482 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5483 macro_build ((char *) NULL
, &icnt
, NULL
,
5484 dbl
? "dmult" : "mult",
5486 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5492 mips_emit_delays (true);
5494 mips_any_noreorder
= 1;
5495 macro_build ((char *) NULL
, &icnt
, NULL
,
5496 dbl
? "dmult" : "mult",
5498 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5499 macro_build ((char *) NULL
, &icnt
, NULL
,
5500 dbl
? "dsra32" : "sra",
5501 "d,w,<", dreg
, dreg
, 31);
5502 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5504 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5507 expr1
.X_add_number
= 8;
5508 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5509 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5510 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5513 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5519 mips_emit_delays (true);
5521 mips_any_noreorder
= 1;
5522 macro_build ((char *) NULL
, &icnt
, NULL
,
5523 dbl
? "dmultu" : "multu",
5525 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5526 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5528 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5531 expr1
.X_add_number
= 8;
5532 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5533 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5534 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5540 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5541 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5542 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5544 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5548 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5549 (int) (imm_expr
.X_add_number
& 0x1f));
5550 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5551 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5552 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5556 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5557 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5558 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5560 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5564 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5565 (int) (imm_expr
.X_add_number
& 0x1f));
5566 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5567 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5568 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5572 assert (mips_isa
< 2);
5573 /* Even on a big endian machine $fn comes before $fn+1. We have
5574 to adjust when storing to memory. */
5575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5576 target_big_endian
? treg
+ 1 : treg
,
5577 (int) BFD_RELOC_LO16
, breg
);
5578 offset_expr
.X_add_number
+= 4;
5579 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5580 target_big_endian
? treg
: treg
+ 1,
5581 (int) BFD_RELOC_LO16
, breg
);
5586 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5587 treg
, (int) BFD_RELOC_LO16
);
5589 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5590 sreg
, (int) BFD_RELOC_LO16
);
5593 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5595 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5596 dreg
, (int) BFD_RELOC_LO16
);
5601 if (imm_expr
.X_add_number
== 0)
5603 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5604 sreg
, (int) BFD_RELOC_LO16
);
5609 as_warn ("Instruction %s: result is always false",
5611 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5614 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5616 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5617 sreg
, (int) BFD_RELOC_LO16
);
5620 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5622 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5623 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5624 mips_isa
< 3 ? "addiu" : "daddiu",
5625 "t,r,j", dreg
, sreg
,
5626 (int) BFD_RELOC_LO16
);
5631 load_register (&icnt
, AT
, &imm_expr
, 0);
5632 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5636 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5637 (int) BFD_RELOC_LO16
);
5642 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5648 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5649 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5650 (int) BFD_RELOC_LO16
);
5653 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5655 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5657 macro_build ((char *) NULL
, &icnt
, &expr1
,
5658 mask
== M_SGE_I
? "slti" : "sltiu",
5659 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5664 load_register (&icnt
, AT
, &imm_expr
, 0);
5665 macro_build ((char *) NULL
, &icnt
, NULL
,
5666 mask
== M_SGE_I
? "slt" : "sltu",
5667 "d,v,t", dreg
, sreg
, AT
);
5670 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5671 (int) BFD_RELOC_LO16
);
5676 case M_SGT
: /* sreg > treg <==> treg < sreg */
5682 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5685 case M_SGT_I
: /* sreg > I <==> I < sreg */
5691 load_register (&icnt
, AT
, &imm_expr
, 0);
5692 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5695 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5701 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5702 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5703 (int) BFD_RELOC_LO16
);
5706 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5712 load_register (&icnt
, AT
, &imm_expr
, 0);
5713 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5714 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5715 (int) BFD_RELOC_LO16
);
5719 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5721 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5722 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5725 load_register (&icnt
, AT
, &imm_expr
, 0);
5726 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5730 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5732 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5733 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5736 load_register (&icnt
, AT
, &imm_expr
, 0);
5737 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5743 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5746 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5750 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5752 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5758 if (imm_expr
.X_add_number
== 0)
5760 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5766 as_warn ("Instruction %s: result is always true",
5768 macro_build ((char *) NULL
, &icnt
, &expr1
,
5769 mips_isa
< 3 ? "addiu" : "daddiu",
5770 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5773 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5775 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5776 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5779 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5781 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5782 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5783 mips_isa
< 3 ? "addiu" : "daddiu",
5784 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5789 load_register (&icnt
, AT
, &imm_expr
, 0);
5790 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5794 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5802 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5804 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5805 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5806 dbl
? "daddi" : "addi",
5807 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5810 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5811 macro_build ((char *) NULL
, &icnt
, NULL
,
5812 dbl
? "dsub" : "sub",
5813 "d,v,t", dreg
, sreg
, AT
);
5819 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5821 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5822 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5823 dbl
? "daddiu" : "addiu",
5824 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5827 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5828 macro_build ((char *) NULL
, &icnt
, NULL
,
5829 dbl
? "dsubu" : "subu",
5830 "d,v,t", dreg
, sreg
, AT
);
5851 load_register (&icnt
, AT
, &imm_expr
, 0);
5852 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5857 assert (mips_isa
< 2);
5858 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5859 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5862 * Is the double cfc1 instruction a bug in the mips assembler;
5863 * or is there a reason for it?
5865 mips_emit_delays (true);
5867 mips_any_noreorder
= 1;
5868 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5869 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5870 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5871 expr1
.X_add_number
= 3;
5872 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5873 (int) BFD_RELOC_LO16
);
5874 expr1
.X_add_number
= 2;
5875 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5876 (int) BFD_RELOC_LO16
);
5877 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5878 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5879 macro_build ((char *) NULL
, &icnt
, NULL
,
5880 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5881 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5882 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5892 if (offset_expr
.X_add_number
>= 0x7fff)
5893 as_bad ("operand overflow");
5894 /* avoid load delay */
5895 if (! target_big_endian
)
5896 offset_expr
.X_add_number
+= 1;
5897 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5898 (int) BFD_RELOC_LO16
, breg
);
5899 if (! target_big_endian
)
5900 offset_expr
.X_add_number
-= 1;
5902 offset_expr
.X_add_number
+= 1;
5903 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5904 (int) BFD_RELOC_LO16
, breg
);
5905 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5906 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5919 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5920 as_bad ("operand overflow");
5921 if (! target_big_endian
)
5922 offset_expr
.X_add_number
+= off
;
5923 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5924 (int) BFD_RELOC_LO16
, breg
);
5925 if (! target_big_endian
)
5926 offset_expr
.X_add_number
-= off
;
5928 offset_expr
.X_add_number
+= off
;
5929 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5930 (int) BFD_RELOC_LO16
, breg
);
5943 load_address (&icnt
, AT
, &offset_expr
);
5945 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5946 mips_isa
< 3 ? "addu" : "daddu",
5947 "d,v,t", AT
, AT
, breg
);
5948 if (! target_big_endian
)
5949 expr1
.X_add_number
= off
;
5951 expr1
.X_add_number
= 0;
5952 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5953 (int) BFD_RELOC_LO16
, AT
);
5954 if (! target_big_endian
)
5955 expr1
.X_add_number
= 0;
5957 expr1
.X_add_number
= off
;
5958 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5959 (int) BFD_RELOC_LO16
, AT
);
5964 load_address (&icnt
, AT
, &offset_expr
);
5966 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5967 mips_isa
< 3 ? "addu" : "daddu",
5968 "d,v,t", AT
, AT
, breg
);
5969 if (target_big_endian
)
5970 expr1
.X_add_number
= 0;
5971 macro_build ((char *) NULL
, &icnt
, &expr1
,
5972 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5973 (int) BFD_RELOC_LO16
, AT
);
5974 if (target_big_endian
)
5975 expr1
.X_add_number
= 1;
5977 expr1
.X_add_number
= 0;
5978 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5979 (int) BFD_RELOC_LO16
, AT
);
5980 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5982 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5987 if (offset_expr
.X_add_number
>= 0x7fff)
5988 as_bad ("operand overflow");
5989 if (target_big_endian
)
5990 offset_expr
.X_add_number
+= 1;
5991 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5992 (int) BFD_RELOC_LO16
, breg
);
5993 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5994 if (target_big_endian
)
5995 offset_expr
.X_add_number
-= 1;
5997 offset_expr
.X_add_number
+= 1;
5998 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5999 (int) BFD_RELOC_LO16
, breg
);
6012 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6013 as_bad ("operand overflow");
6014 if (! target_big_endian
)
6015 offset_expr
.X_add_number
+= off
;
6016 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6017 (int) BFD_RELOC_LO16
, breg
);
6018 if (! target_big_endian
)
6019 offset_expr
.X_add_number
-= off
;
6021 offset_expr
.X_add_number
+= off
;
6022 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6023 (int) BFD_RELOC_LO16
, breg
);
6036 load_address (&icnt
, AT
, &offset_expr
);
6038 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6039 mips_isa
< 3 ? "addu" : "daddu",
6040 "d,v,t", AT
, AT
, breg
);
6041 if (! target_big_endian
)
6042 expr1
.X_add_number
= off
;
6044 expr1
.X_add_number
= 0;
6045 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6046 (int) BFD_RELOC_LO16
, AT
);
6047 if (! target_big_endian
)
6048 expr1
.X_add_number
= 0;
6050 expr1
.X_add_number
= off
;
6051 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6052 (int) BFD_RELOC_LO16
, AT
);
6056 load_address (&icnt
, AT
, &offset_expr
);
6058 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6059 mips_isa
< 3 ? "addu" : "daddu",
6060 "d,v,t", AT
, AT
, breg
);
6061 if (! target_big_endian
)
6062 expr1
.X_add_number
= 0;
6063 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6064 (int) BFD_RELOC_LO16
, AT
);
6065 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6067 if (! target_big_endian
)
6068 expr1
.X_add_number
= 1;
6070 expr1
.X_add_number
= 0;
6071 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6072 (int) BFD_RELOC_LO16
, AT
);
6073 if (! target_big_endian
)
6074 expr1
.X_add_number
= 0;
6076 expr1
.X_add_number
= 1;
6077 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6078 (int) BFD_RELOC_LO16
, AT
);
6079 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6081 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6086 /* FIXME: Check if this is one of the itbl macros, since they
6087 are added dynamically. */
6088 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6092 as_warn ("Macro used $at after \".set noat\"");
6095 /* Implement macros in mips16 mode. */
6099 struct mips_cl_insn
*ip
;
6102 int xreg
, yreg
, zreg
, tmp
;
6106 const char *s
, *s2
, *s3
;
6108 mask
= ip
->insn_mo
->mask
;
6110 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6111 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6112 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6116 expr1
.X_op
= O_constant
;
6117 expr1
.X_op_symbol
= NULL
;
6118 expr1
.X_add_symbol
= NULL
;
6119 expr1
.X_add_number
= 1;
6138 mips_emit_delays (true);
6140 mips_any_noreorder
= 1;
6141 macro_build ((char *) NULL
, &icnt
, NULL
,
6142 dbl
? "ddiv" : "div",
6143 "0,x,y", xreg
, yreg
);
6144 expr1
.X_add_number
= 2;
6145 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6146 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6147 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6148 since that causes an overflow. We should do that as well,
6149 but I don't see how to do the comparisons without a temporary
6152 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6171 mips_emit_delays (true);
6173 mips_any_noreorder
= 1;
6174 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6175 expr1
.X_add_number
= 2;
6176 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6177 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6179 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6187 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6188 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6189 dbl
? "daddiu" : "addiu",
6190 "y,x,4", yreg
, xreg
);
6194 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6195 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6200 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6201 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6224 goto do_reverse_branch
;
6228 goto do_reverse_branch
;
6240 goto do_reverse_branch
;
6251 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6253 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6280 goto do_addone_branch_i
;
6285 goto do_addone_branch_i
;
6300 goto do_addone_branch_i
;
6307 ++imm_expr
.X_add_number
;
6310 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6311 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6315 expr1
.X_add_number
= 0;
6316 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6319 "move", "y,X", xreg
, yreg
);
6320 expr1
.X_add_number
= 2;
6321 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6322 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6323 "neg", "x,w", xreg
, xreg
);
6327 /* This routine assembles an instruction into its binary format. As a
6328 side effect, it sets one of the global variables imm_reloc or
6329 offset_reloc to the type of relocation to do if one of the operands
6330 is an address expression. */
6335 struct mips_cl_insn
*ip
;
6340 struct mips_opcode
*insn
;
6343 unsigned int lastregno
= 0;
6348 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6353 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6355 insn_error
= "unrecognized opcode";
6363 assert (strcmp (insn
->name
, str
) == 0);
6365 if (insn
->pinfo
== INSN_MACRO
)
6366 insn_isa
= insn
->match
;
6367 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6369 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6371 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6376 if (insn_isa
> mips_isa
6377 || (insn
->pinfo
!= INSN_MACRO
6378 && (((insn
->pinfo
& INSN_ISA
) == INSN_4650
6380 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6382 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6384 /* start-sanitize-r5900 */
6385 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6387 /* end-sanitize-r5900 */
6390 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6391 && strcmp (insn
->name
, insn
[1].name
) == 0)
6396 if (insn_isa
<= mips_isa
)
6397 insn_error
= "opcode not supported on this processor";
6400 static char buf
[100];
6402 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6409 ip
->insn_opcode
= insn
->match
;
6410 for (args
= insn
->args
;; ++args
)
6416 case '\0': /* end of args */
6429 ip
->insn_opcode
|= lastregno
<< 21;
6434 ip
->insn_opcode
|= lastregno
<< 16;
6438 ip
->insn_opcode
|= lastregno
<< 11;
6444 /* handle optional base register.
6445 Either the base register is omitted or
6446 we must have a left paren. */
6447 /* this is dependent on the next operand specifier
6448 is a 'b' for base register */
6449 assert (args
[1] == 'b');
6453 case ')': /* these must match exactly */
6458 case '<': /* must be at least one digit */
6460 * According to the manual, if the shift amount is greater
6461 * than 31 or less than 0 the the shift amount should be
6462 * mod 32. In reality the mips assembler issues an error.
6463 * We issue a warning and mask out all but the low 5 bits.
6465 my_getExpression (&imm_expr
, s
);
6466 check_absolute_expr (ip
, &imm_expr
);
6467 if ((unsigned long) imm_expr
.X_add_number
> 31)
6469 as_warn ("Improper shift amount (%ld)",
6470 (long) imm_expr
.X_add_number
);
6471 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6473 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6474 imm_expr
.X_op
= O_absent
;
6478 case '>': /* shift amount minus 32 */
6479 my_getExpression (&imm_expr
, s
);
6480 check_absolute_expr (ip
, &imm_expr
);
6481 if ((unsigned long) imm_expr
.X_add_number
< 32
6482 || (unsigned long) imm_expr
.X_add_number
> 63)
6484 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6485 imm_expr
.X_op
= O_absent
;
6489 case 'k': /* cache code */
6490 case 'h': /* prefx code */
6491 my_getExpression (&imm_expr
, s
);
6492 check_absolute_expr (ip
, &imm_expr
);
6493 if ((unsigned long) imm_expr
.X_add_number
> 31)
6495 as_warn ("Invalid value for `%s' (%lu)",
6497 (unsigned long) imm_expr
.X_add_number
);
6498 imm_expr
.X_add_number
&= 0x1f;
6501 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6503 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6504 imm_expr
.X_op
= O_absent
;
6508 case 'c': /* break code */
6509 my_getExpression (&imm_expr
, s
);
6510 check_absolute_expr (ip
, &imm_expr
);
6511 if ((unsigned) imm_expr
.X_add_number
> 1023)
6512 as_warn ("Illegal break code (%ld)",
6513 (long) imm_expr
.X_add_number
);
6514 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6515 imm_expr
.X_op
= O_absent
;
6519 case 'B': /* syscall code */
6520 my_getExpression (&imm_expr
, s
);
6521 check_absolute_expr (ip
, &imm_expr
);
6522 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6523 as_warn ("Illegal syscall code (%ld)",
6524 (long) imm_expr
.X_add_number
);
6525 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6526 imm_expr
.X_op
= O_absent
;
6530 case 'C': /* Coprocessor code */
6531 my_getExpression (&imm_expr
, s
);
6532 check_absolute_expr (ip
, &imm_expr
);
6533 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6535 as_warn ("Coproccesor code > 25 bits (%ld)",
6536 (long) imm_expr
.X_add_number
);
6537 imm_expr
.X_add_number
&= ((1<<25) - 1);
6539 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6540 imm_expr
.X_op
= O_absent
;
6544 case 'b': /* base register */
6545 case 'd': /* destination register */
6546 case 's': /* source register */
6547 case 't': /* target register */
6548 case 'r': /* both target and source */
6549 case 'v': /* both dest and source */
6550 case 'w': /* both dest and target */
6551 case 'E': /* coprocessor target register */
6552 case 'G': /* coprocessor destination register */
6553 case 'x': /* ignore register name */
6554 case 'z': /* must be zero register */
6568 while (isdigit (*s
));
6570 as_bad ("Invalid register number (%d)", regno
);
6572 else if (*args
== 'E' || *args
== 'G')
6576 if (s
[1] == 'f' && s
[2] == 'p')
6581 else if (s
[1] == 's' && s
[2] == 'p')
6586 else if (s
[1] == 'g' && s
[2] == 'p')
6591 else if (s
[1] == 'a' && s
[2] == 't')
6596 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6601 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6606 else if (itbl_have_entries
)
6611 p
= s
+1; /* advance past '$' */
6612 n
= itbl_get_field (&p
); /* n is name */
6614 /* See if this is a register defined in an
6616 r
= itbl_get_reg_val (n
);
6619 /* Get_field advances to the start of
6620 the next field, so we need to back
6621 rack to the end of the last field. */
6625 s
= strchr (s
,'\0');
6638 as_warn ("Used $at without \".set noat\"");
6644 if (c
== 'r' || c
== 'v' || c
== 'w')
6651 /* 'z' only matches $0. */
6652 if (c
== 'z' && regno
!= 0)
6655 /* Now that we have assembled one operand, we use the args string
6656 * to figure out where it goes in the instruction. */
6663 ip
->insn_opcode
|= regno
<< 21;
6667 ip
->insn_opcode
|= regno
<< 11;
6672 ip
->insn_opcode
|= regno
<< 16;
6675 /* This case exists because on the r3000 trunc
6676 expands into a macro which requires a gp
6677 register. On the r6000 or r4000 it is
6678 assembled into a single instruction which
6679 ignores the register. Thus the insn version
6680 is MIPS_ISA2 and uses 'x', and the macro
6681 version is MIPS_ISA1 and uses 't'. */
6684 /* This case is for the div instruction, which
6685 acts differently if the destination argument
6686 is $0. This only matches $0, and is checked
6687 outside the switch. */
6690 /* Itbl operand; not yet implemented. FIXME ?? */
6692 /* What about all other operands like 'i', which
6693 can be specified in the opcode table? */
6703 ip
->insn_opcode
|= lastregno
<< 21;
6706 ip
->insn_opcode
|= lastregno
<< 16;
6711 case 'D': /* floating point destination register */
6712 case 'S': /* floating point source register */
6713 case 'T': /* floating point target register */
6714 case 'R': /* floating point source register */
6718 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6728 while (isdigit (*s
));
6731 as_bad ("Invalid float register number (%d)", regno
);
6733 if ((regno
& 1) != 0
6735 && ! (strcmp (str
, "mtc1") == 0
6736 || strcmp (str
, "mfc1") == 0
6737 || strcmp (str
, "lwc1") == 0
6738 || strcmp (str
, "swc1") == 0
6739 || strcmp (str
, "l.s") == 0
6740 || strcmp (str
, "s.s") == 0))
6741 as_warn ("Float register should be even, was %d",
6749 if (c
== 'V' || c
== 'W')
6759 ip
->insn_opcode
|= regno
<< 6;
6763 ip
->insn_opcode
|= regno
<< 11;
6767 ip
->insn_opcode
|= regno
<< 16;
6770 ip
->insn_opcode
|= regno
<< 21;
6779 ip
->insn_opcode
|= lastregno
<< 11;
6782 ip
->insn_opcode
|= lastregno
<< 16;
6788 my_getExpression (&imm_expr
, s
);
6789 if (imm_expr
.X_op
!= O_big
6790 && imm_expr
.X_op
!= O_constant
)
6791 insn_error
= "absolute expression required";
6796 my_getExpression (&offset_expr
, s
);
6797 imm_reloc
= BFD_RELOC_32
;
6809 unsigned char temp
[8];
6811 unsigned int length
;
6816 /* These only appear as the last operand in an
6817 instruction, and every instruction that accepts
6818 them in any variant accepts them in all variants.
6819 This means we don't have to worry about backing out
6820 any changes if the instruction does not match.
6822 The difference between them is the size of the
6823 floating point constant and where it goes. For 'F'
6824 and 'L' the constant is 64 bits; for 'f' and 'l' it
6825 is 32 bits. Where the constant is placed is based
6826 on how the MIPS assembler does things:
6829 f -- immediate value
6832 The .lit4 and .lit8 sections are only used if
6833 permitted by the -G argument.
6835 When generating embedded PIC code, we use the
6836 .lit8 section but not the .lit4 section (we can do
6837 .lit4 inline easily; we need to put .lit8
6838 somewhere in the data segment, and using .lit8
6839 permits the linker to eventually combine identical
6842 f64
= *args
== 'F' || *args
== 'L';
6844 save_in
= input_line_pointer
;
6845 input_line_pointer
= s
;
6846 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6848 s
= input_line_pointer
;
6849 input_line_pointer
= save_in
;
6850 if (err
!= NULL
&& *err
!= '\0')
6852 as_bad ("Bad floating point constant: %s", err
);
6853 memset (temp
, '\0', sizeof temp
);
6854 length
= f64
? 8 : 4;
6857 assert (length
== (f64
? 8 : 4));
6861 && (! USE_GLOBAL_POINTER_OPT
6862 || mips_pic
== EMBEDDED_PIC
6863 || g_switch_value
< 4)
6866 imm_expr
.X_op
= O_constant
;
6867 if (! target_big_endian
)
6868 imm_expr
.X_add_number
=
6869 (((((((int) temp
[3] << 8)
6874 imm_expr
.X_add_number
=
6875 (((((((int) temp
[0] << 8)
6882 const char *newname
;
6885 /* Switch to the right section. */
6887 subseg
= now_subseg
;
6890 default: /* unused default case avoids warnings. */
6892 newname
= RDATA_SECTION_NAME
;
6893 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6897 newname
= RDATA_SECTION_NAME
;
6900 assert (!USE_GLOBAL_POINTER_OPT
6901 || g_switch_value
>= 4);
6905 new_seg
= subseg_new (newname
, (subsegT
) 0);
6906 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6907 bfd_set_section_flags (stdoutput
, new_seg
,
6912 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
6913 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
6914 && strcmp (TARGET_OS
, "elf") != 0)
6915 record_alignment (new_seg
, 4);
6917 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6919 as_bad ("Can't use floating point insn in this section");
6921 /* Set the argument to the current address in the
6923 offset_expr
.X_op
= O_symbol
;
6924 offset_expr
.X_add_symbol
=
6925 symbol_new ("L0\001", now_seg
,
6926 (valueT
) frag_now_fix (), frag_now
);
6927 offset_expr
.X_add_number
= 0;
6929 /* Put the floating point number into the section. */
6930 p
= frag_more ((int) length
);
6931 memcpy (p
, temp
, length
);
6933 /* Switch back to the original section. */
6934 subseg_set (seg
, subseg
);
6939 case 'i': /* 16 bit unsigned immediate */
6940 case 'j': /* 16 bit signed immediate */
6941 imm_reloc
= BFD_RELOC_LO16
;
6942 c
= my_getSmallExpression (&imm_expr
, s
);
6947 if (imm_expr
.X_op
== O_constant
)
6948 imm_expr
.X_add_number
=
6949 (imm_expr
.X_add_number
>> 16) & 0xffff;
6952 imm_reloc
= BFD_RELOC_HI16_S
;
6953 imm_unmatched_hi
= true;
6956 imm_reloc
= BFD_RELOC_HI16
;
6961 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6962 || ((imm_expr
.X_add_number
< 0
6963 || imm_expr
.X_add_number
>= 0x10000)
6964 && imm_expr
.X_op
== O_constant
))
6966 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6967 !strcmp (insn
->name
, insn
[1].name
))
6969 if (imm_expr
.X_op
!= O_constant
6970 && imm_expr
.X_op
!= O_big
)
6971 insn_error
= "absolute expression required";
6973 as_bad ("16 bit expression not in range 0..65535");
6981 /* The upper bound should be 0x8000, but
6982 unfortunately the MIPS assembler accepts numbers
6983 from 0x8000 to 0xffff and sign extends them, and
6984 we want to be compatible. We only permit this
6985 extended range for an instruction which does not
6986 provide any further alternates, since those
6987 alternates may handle other cases. People should
6988 use the numbers they mean, rather than relying on
6989 a mysterious sign extension. */
6990 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6991 strcmp (insn
->name
, insn
[1].name
) == 0);
6996 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6997 || ((imm_expr
.X_add_number
< -0x8000
6998 || imm_expr
.X_add_number
>= max
)
6999 && imm_expr
.X_op
== O_constant
)
7001 && imm_expr
.X_add_number
< 0
7003 && imm_expr
.X_unsigned
7004 && sizeof (imm_expr
.X_add_number
) <= 4))
7008 if (imm_expr
.X_op
!= O_constant
7009 && imm_expr
.X_op
!= O_big
)
7010 insn_error
= "absolute expression required";
7012 as_bad ("16 bit expression not in range -32768..32767");
7018 case 'o': /* 16 bit offset */
7019 c
= my_getSmallExpression (&offset_expr
, s
);
7021 /* If this value won't fit into a 16 bit offset, then go
7022 find a macro that will generate the 32 bit offset
7023 code pattern. As a special hack, we accept the
7024 difference of two local symbols as a constant. This
7025 is required to suppose embedded PIC switches, which
7026 use an instruction which looks like
7027 lw $4,$L12-$LS12($4)
7028 The problem with handling this in a more general
7029 fashion is that the macro function doesn't expect to
7030 see anything which can be handled in a single
7031 constant instruction. */
7033 && (offset_expr
.X_op
!= O_constant
7034 || offset_expr
.X_add_number
>= 0x8000
7035 || offset_expr
.X_add_number
< -0x8000)
7036 && (mips_pic
!= EMBEDDED_PIC
7037 || offset_expr
.X_op
!= O_subtract
7038 || now_seg
!= text_section
7039 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7043 offset_reloc
= BFD_RELOC_LO16
;
7044 if (c
== 'h' || c
== 'H')
7046 assert (offset_expr
.X_op
== O_constant
);
7047 offset_expr
.X_add_number
=
7048 (offset_expr
.X_add_number
>> 16) & 0xffff;
7053 case 'p': /* pc relative offset */
7054 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7055 my_getExpression (&offset_expr
, s
);
7059 case 'u': /* upper 16 bits */
7060 c
= my_getSmallExpression (&imm_expr
, s
);
7061 if (imm_expr
.X_op
== O_constant
7062 && (imm_expr
.X_add_number
< 0
7063 || imm_expr
.X_add_number
>= 0x10000))
7064 as_bad ("lui expression not in range 0..65535");
7065 imm_reloc
= BFD_RELOC_LO16
;
7070 if (imm_expr
.X_op
== O_constant
)
7071 imm_expr
.X_add_number
=
7072 (imm_expr
.X_add_number
>> 16) & 0xffff;
7075 imm_reloc
= BFD_RELOC_HI16_S
;
7076 imm_unmatched_hi
= true;
7079 imm_reloc
= BFD_RELOC_HI16
;
7085 case 'a': /* 26 bit address */
7086 my_getExpression (&offset_expr
, s
);
7088 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7091 case 'N': /* 3 bit branch condition code */
7092 case 'M': /* 3 bit compare condition code */
7093 if (strncmp (s
, "$fcc", 4) != 0)
7103 while (isdigit (*s
));
7105 as_bad ("invalid condition code register $fcc%d", regno
);
7107 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7109 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7113 fprintf (stderr
, "bad char = '%c'\n", *args
);
7118 /* Args don't match. */
7119 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7120 !strcmp (insn
->name
, insn
[1].name
))
7126 insn_error
= "illegal operands";
7131 /* This routine assembles an instruction into its binary format when
7132 assembling for the mips16. As a side effect, it sets one of the
7133 global variables imm_reloc or offset_reloc to the type of
7134 relocation to do if one of the operands is an address expression.
7135 It also sets mips16_small and mips16_ext if the user explicitly
7136 requested a small or extended instruction. */
7141 struct mips_cl_insn
*ip
;
7145 struct mips_opcode
*insn
;
7148 unsigned int lastregno
= 0;
7153 mips16_small
= false;
7156 for (s
= str
; islower (*s
); ++s
)
7168 if (s
[1] == 't' && s
[2] == ' ')
7171 mips16_small
= true;
7175 else if (s
[1] == 'e' && s
[2] == ' ')
7184 insn_error
= "unknown opcode";
7188 if (! mips16_autoextend
&& ! mips16_ext
)
7189 mips16_small
= true;
7191 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7193 insn_error
= "unrecognized opcode";
7200 assert (strcmp (insn
->name
, str
) == 0);
7203 ip
->insn_opcode
= insn
->match
;
7204 ip
->use_extend
= false;
7205 imm_expr
.X_op
= O_absent
;
7206 imm_reloc
= BFD_RELOC_UNUSED
;
7207 offset_expr
.X_op
= O_absent
;
7208 offset_reloc
= BFD_RELOC_UNUSED
;
7209 for (args
= insn
->args
; 1; ++args
)
7216 /* In this switch statement we call break if we did not find
7217 a match, continue if we did find a match, or return if we
7226 /* Stuff the immediate value in now, if we can. */
7227 if (imm_expr
.X_op
== O_constant
7228 && imm_reloc
> BFD_RELOC_UNUSED
7229 && insn
->pinfo
!= INSN_MACRO
)
7231 mips16_immed ((char *) NULL
, 0,
7232 imm_reloc
- BFD_RELOC_UNUSED
,
7233 imm_expr
.X_add_number
, true, mips16_small
,
7234 mips16_ext
, &ip
->insn_opcode
,
7235 &ip
->use_extend
, &ip
->extend
);
7236 imm_expr
.X_op
= O_absent
;
7237 imm_reloc
= BFD_RELOC_UNUSED
;
7251 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7254 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7270 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7272 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7299 while (isdigit (*s
));
7302 as_bad ("invalid register number (%d)", regno
);
7308 if (s
[1] == 'f' && s
[2] == 'p')
7313 else if (s
[1] == 's' && s
[2] == 'p')
7318 else if (s
[1] == 'g' && s
[2] == 'p')
7323 else if (s
[1] == 'a' && s
[2] == 't')
7328 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7333 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7346 if (c
== 'v' || c
== 'w')
7348 regno
= mips16_to_32_reg_map
[lastregno
];
7362 regno
= mips32_to_16_reg_map
[regno
];
7367 regno
= ILLEGAL_REG
;
7372 regno
= ILLEGAL_REG
;
7377 regno
= ILLEGAL_REG
;
7382 if (regno
== AT
&& ! mips_noat
)
7383 as_warn ("used $at without \".set noat\"");
7390 if (regno
== ILLEGAL_REG
)
7397 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7401 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7404 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7407 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7413 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7416 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7417 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7427 if (strncmp (s
, "$pc", 3) == 0)
7451 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7453 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7454 and generate the appropriate reloc. If the text
7455 inside %gprel is not a symbol name with an
7456 optional offset, then we generate a normal reloc
7457 and will probably fail later. */
7458 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7459 if (imm_expr
.X_op
== O_symbol
)
7462 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7464 ip
->use_extend
= true;
7471 /* Just pick up a normal expression. */
7472 my_getExpression (&imm_expr
, s
);
7475 if (imm_expr
.X_op
== O_register
)
7477 /* What we thought was an expression turned out to
7480 if (s
[0] == '(' && args
[1] == '(')
7482 /* It looks like the expression was omitted
7483 before a register indirection, which means
7484 that the expression is implicitly zero. We
7485 still set up imm_expr, so that we handle
7486 explicit extensions correctly. */
7487 imm_expr
.X_op
= O_constant
;
7488 imm_expr
.X_add_number
= 0;
7489 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7496 /* We need to relax this instruction. */
7497 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7506 /* We use offset_reloc rather than imm_reloc for the PC
7507 relative operands. This lets macros with both
7508 immediate and address operands work correctly. */
7509 my_getExpression (&offset_expr
, s
);
7511 if (offset_expr
.X_op
== O_register
)
7514 /* We need to relax this instruction. */
7515 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7519 case '6': /* break code */
7520 my_getExpression (&imm_expr
, s
);
7521 check_absolute_expr (ip
, &imm_expr
);
7522 if ((unsigned long) imm_expr
.X_add_number
> 63)
7524 as_warn ("Invalid value for `%s' (%lu)",
7526 (unsigned long) imm_expr
.X_add_number
);
7527 imm_expr
.X_add_number
&= 0x3f;
7529 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7530 imm_expr
.X_op
= O_absent
;
7534 case 'a': /* 26 bit address */
7535 my_getExpression (&offset_expr
, s
);
7537 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7538 ip
->insn_opcode
<<= 16;
7541 case 'l': /* register list for entry macro */
7542 case 'L': /* register list for exit macro */
7552 int freg
, reg1
, reg2
;
7554 while (*s
== ' ' || *s
== ',')
7558 as_bad ("can't parse register list");
7570 while (isdigit (*s
))
7592 as_bad ("invalid register list");
7597 while (isdigit (*s
))
7604 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7609 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7614 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7615 mask
|= (reg2
- 3) << 3;
7616 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7617 mask
|= (reg2
- 15) << 1;
7618 else if (reg1
== 31 && reg2
== 31)
7622 as_bad ("invalid register list");
7626 /* The mask is filled in in the opcode table for the
7627 benefit of the disassembler. We remove it before
7628 applying the actual mask. */
7629 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7630 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7634 case 'e': /* extend code */
7635 my_getExpression (&imm_expr
, s
);
7636 check_absolute_expr (ip
, &imm_expr
);
7637 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7639 as_warn ("Invalid value for `%s' (%lu)",
7641 (unsigned long) imm_expr
.X_add_number
);
7642 imm_expr
.X_add_number
&= 0x7ff;
7644 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7645 imm_expr
.X_op
= O_absent
;
7655 /* Args don't match. */
7656 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7657 strcmp (insn
->name
, insn
[1].name
) == 0)
7664 insn_error
= "illegal operands";
7670 /* This structure holds information we know about a mips16 immediate
7673 struct mips16_immed_operand
7675 /* The type code used in the argument string in the opcode table. */
7677 /* The number of bits in the short form of the opcode. */
7679 /* The number of bits in the extended form of the opcode. */
7681 /* The amount by which the short form is shifted when it is used;
7682 for example, the sw instruction has a shift count of 2. */
7684 /* The amount by which the short form is shifted when it is stored
7685 into the instruction code. */
7687 /* Non-zero if the short form is unsigned. */
7689 /* Non-zero if the extended form is unsigned. */
7691 /* Non-zero if the value is PC relative. */
7695 /* The mips16 immediate operand types. */
7697 static const struct mips16_immed_operand mips16_immed_operands
[] =
7699 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7700 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7701 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7702 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7703 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7704 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7705 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7706 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7707 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7708 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7709 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7710 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7711 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7712 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7713 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7714 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7715 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7716 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7717 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7718 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7719 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7722 #define MIPS16_NUM_IMMED \
7723 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7725 /* Handle a mips16 instruction with an immediate value. This or's the
7726 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7727 whether an extended value is needed; if one is needed, it sets
7728 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7729 If SMALL is true, an unextended opcode was explicitly requested.
7730 If EXT is true, an extended opcode was explicitly requested. If
7731 WARN is true, warn if EXT does not match reality. */
7734 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7743 unsigned long *insn
;
7744 boolean
*use_extend
;
7745 unsigned short *extend
;
7747 register const struct mips16_immed_operand
*op
;
7748 int mintiny
, maxtiny
;
7751 op
= mips16_immed_operands
;
7752 while (op
->type
!= type
)
7755 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7760 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7763 maxtiny
= 1 << op
->nbits
;
7768 maxtiny
= (1 << op
->nbits
) - 1;
7773 mintiny
= - (1 << (op
->nbits
- 1));
7774 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7777 /* Branch offsets have an implicit 0 in the lowest bit. */
7778 if (type
== 'p' || type
== 'q')
7781 if ((val
& ((1 << op
->shift
) - 1)) != 0
7782 || val
< (mintiny
<< op
->shift
)
7783 || val
> (maxtiny
<< op
->shift
))
7788 if (warn
&& ext
&& ! needext
)
7789 as_warn_where (file
, line
, "extended operand requested but not required");
7790 if (small
&& needext
)
7791 as_bad_where (file
, line
, "invalid unextended operand value");
7793 if (small
|| (! ext
&& ! needext
))
7797 *use_extend
= false;
7798 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7799 insnval
<<= op
->op_shift
;
7804 long minext
, maxext
;
7810 maxext
= (1 << op
->extbits
) - 1;
7814 minext
= - (1 << (op
->extbits
- 1));
7815 maxext
= (1 << (op
->extbits
- 1)) - 1;
7817 if (val
< minext
|| val
> maxext
)
7818 as_bad_where (file
, line
,
7819 "operand value out of range for instruction");
7822 if (op
->extbits
== 16)
7824 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7827 else if (op
->extbits
== 15)
7829 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7834 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7838 *extend
= (unsigned short) extval
;
7847 my_getSmallExpression (ep
, str
)
7858 ((str
[1] == 'h' && str
[2] == 'i')
7859 || (str
[1] == 'H' && str
[2] == 'I')
7860 || (str
[1] == 'l' && str
[2] == 'o'))
7872 * A small expression may be followed by a base register.
7873 * Scan to the end of this operand, and then back over a possible
7874 * base register. Then scan the small expression up to that
7875 * point. (Based on code in sparc.c...)
7877 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7879 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7881 if (isdigit (sp
[-2]))
7883 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7885 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7891 else if (sp
- 5 >= str
7894 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7895 || (sp
[-3] == 's' && sp
[-2] == 'p')
7896 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7897 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7903 /* no expression means zero offset */
7906 /* %xx(reg) is an error */
7907 ep
->X_op
= O_absent
;
7912 ep
->X_op
= O_constant
;
7915 ep
->X_add_symbol
= NULL
;
7916 ep
->X_op_symbol
= NULL
;
7917 ep
->X_add_number
= 0;
7922 my_getExpression (ep
, str
);
7929 my_getExpression (ep
, str
);
7930 return c
; /* => %hi or %lo encountered */
7934 my_getExpression (ep
, str
)
7940 save_in
= input_line_pointer
;
7941 input_line_pointer
= str
;
7943 expr_end
= input_line_pointer
;
7944 input_line_pointer
= save_in
;
7946 /* If we are in mips16 mode, and this is an expression based on `.',
7947 then we bump the value of the symbol by 1 since that is how other
7948 text symbols are handled. We don't bother to handle complex
7949 expressions, just `.' plus or minus a constant. */
7951 && ep
->X_op
== O_symbol
7952 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
7953 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
7954 && ep
->X_add_symbol
->sy_frag
== frag_now
7955 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
7956 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
7957 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
7960 /* Turn a string in input_line_pointer into a floating point constant
7961 of type type, and store the appropriate bytes in *litP. The number
7962 of LITTLENUMS emitted is stored in *sizeP . An error message is
7963 returned, or NULL on OK. */
7966 md_atof (type
, litP
, sizeP
)
7972 LITTLENUM_TYPE words
[4];
7988 return "bad call to md_atof";
7991 t
= atof_ieee (input_line_pointer
, type
, words
);
7993 input_line_pointer
= t
;
7997 if (! target_big_endian
)
7999 for (i
= prec
- 1; i
>= 0; i
--)
8001 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8007 for (i
= 0; i
< prec
; i
++)
8009 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8018 md_number_to_chars (buf
, val
, n
)
8023 if (target_big_endian
)
8024 number_to_chars_bigendian (buf
, val
, n
);
8026 number_to_chars_littleendian (buf
, val
, n
);
8029 CONST
char *md_shortopts
= "O::g::G:";
8031 struct option md_longopts
[] = {
8032 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8033 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8034 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8035 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8036 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8037 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8038 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8039 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8040 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8041 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8042 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8043 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8044 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8045 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8046 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8047 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8048 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8049 {"break", no_argument
, NULL
, OPTION_BREAK
},
8050 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8051 #define OPTION_EB (OPTION_MD_BASE + 11)
8052 {"EB", no_argument
, NULL
, OPTION_EB
},
8053 #define OPTION_EL (OPTION_MD_BASE + 12)
8054 {"EL", no_argument
, NULL
, OPTION_EL
},
8055 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8056 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8057 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8058 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8059 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8060 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8061 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8062 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8063 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8064 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8065 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8066 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8067 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8068 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8069 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8070 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8071 /* start-sanitize-r5900 */
8072 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8073 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8074 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8075 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8076 /* end-sanitize-r5900 */
8078 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8079 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8080 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8081 #define OPTION_32 (OPTION_MD_BASE + 20)
8082 #define OPTION_64 (OPTION_MD_BASE + 21)
8084 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8085 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8086 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8087 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8088 {"32", no_argument
, NULL
, OPTION_32
},
8089 {"64", no_argument
, NULL
, OPTION_64
},
8092 {NULL
, no_argument
, NULL
, 0}
8094 size_t md_longopts_size
= sizeof(md_longopts
);
8097 md_parse_option (c
, arg
)
8112 target_big_endian
= 1;
8116 target_big_endian
= 0;
8120 if (arg
&& arg
[1] == '0')
8130 mips_debug
= atoi (arg
);
8131 /* When the MIPS assembler sees -g or -g2, it does not do
8132 optimizations which limit full symbolic debugging. We take
8133 that to be equivalent to -O0. */
8134 if (mips_debug
== 2)
8166 /* Identify the processor type */
8168 if (strcmp (p
, "default") == 0
8169 || strcmp (p
, "DEFAULT") == 0)
8175 /* We need to cope with the various "vr" prefixes for the 4300
8177 if (*p
== 'v' || *p
== 'V')
8183 if (*p
== 'r' || *p
== 'R')
8190 if (strcmp (p
, "10000") == 0
8191 || strcmp (p
, "10k") == 0
8192 || strcmp (p
, "10K") == 0)
8197 if (strcmp (p
, "2000") == 0
8198 || strcmp (p
, "2k") == 0
8199 || strcmp (p
, "2K") == 0)
8204 if (strcmp (p
, "3000") == 0
8205 || strcmp (p
, "3k") == 0
8206 || strcmp (p
, "3K") == 0)
8211 if (strcmp (p
, "4000") == 0
8212 || strcmp (p
, "4k") == 0
8213 || strcmp (p
, "4K") == 0)
8215 else if (strcmp (p
, "4100") == 0)
8221 else if (strcmp (p
, "4300") == 0)
8223 else if (strcmp (p
, "4400") == 0)
8225 else if (strcmp (p
, "4600") == 0)
8227 else if (strcmp (p
, "4650") == 0)
8233 else if (strcmp (p
, "4010") == 0)
8242 if (strcmp (p
, "5000") == 0
8243 || strcmp (p
, "5k") == 0
8244 || strcmp (p
, "5K") == 0)
8246 /* start-sanitize-r5900 */
8247 else if (strcmp (p
, "5900") == 0)
8249 /* end-sanitize-r5900 */
8253 if (strcmp (p
, "6000") == 0
8254 || strcmp (p
, "6k") == 0
8255 || strcmp (p
, "6K") == 0)
8260 if (strcmp (p
, "8000") == 0
8261 || strcmp (p
, "8k") == 0
8262 || strcmp (p
, "8K") == 0)
8267 if (strcmp (p
, "orion") == 0)
8272 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8274 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8280 as_bad ("invalid architecture -mcpu=%s", arg
);
8291 case OPTION_NO_M4650
:
8299 case OPTION_NO_M4010
:
8307 case OPTION_NO_M4100
:
8311 /* start-sanitize-r5900 */
8316 case OPTION_NO_M5900
:
8319 /* end-sanitize-r5900 */
8323 mips_no_prev_insn (false);
8326 case OPTION_NO_MIPS16
:
8328 mips_no_prev_insn (false);
8331 case OPTION_MEMBEDDED_PIC
:
8332 mips_pic
= EMBEDDED_PIC
;
8333 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8335 as_bad ("-G may not be used with embedded PIC code");
8338 g_switch_value
= 0x7fffffff;
8341 /* When generating ELF code, we permit -KPIC and -call_shared to
8342 select SVR4_PIC, and -non_shared to select no PIC. This is
8343 intended to be compatible with Irix 5. */
8344 case OPTION_CALL_SHARED
:
8345 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8347 as_bad ("-call_shared is supported only for ELF format");
8350 mips_pic
= SVR4_PIC
;
8351 if (g_switch_seen
&& g_switch_value
!= 0)
8353 as_bad ("-G may not be used with SVR4 PIC code");
8359 case OPTION_NON_SHARED
:
8360 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8362 as_bad ("-non_shared is supported only for ELF format");
8368 /* The -xgot option tells the assembler to use 32 offsets when
8369 accessing the got in SVR4_PIC mode. It is for Irix
8376 if (! USE_GLOBAL_POINTER_OPT
)
8378 as_bad ("-G is not supported for this configuration");
8381 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8383 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8387 g_switch_value
= atoi (arg
);
8391 /* The -32 and -64 options tell the assembler to output the 32
8392 bit or the 64 bit MIPS ELF format. */
8399 const char **list
, **l
;
8401 list
= bfd_target_list ();
8402 for (l
= list
; *l
!= NULL
; l
++)
8403 if (strcmp (*l
, "elf64-bigmips") == 0
8404 || strcmp (*l
, "elf64-littlemips") == 0)
8407 as_fatal ("No compiled in support for 64 bit object file format");
8421 md_show_usage (stream
)
8426 -membedded-pic generate embedded position independent code\n\
8427 -EB generate big endian output\n\
8428 -EL generate little endian output\n\
8429 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8430 -G NUM allow referencing objects up to NUM bytes\n\
8431 implicitly with the gp register [default 8]\n");
8433 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8434 -mips2, -mcpu=r6000 generate code for r6000\n\
8435 -mips3, -mcpu=r4000 generate code for r4000\n\
8436 -mips4, -mcpu=r8000 generate code for r8000\n\
8437 -mcpu=vr4300 generate code for vr4300\n\
8438 -mcpu=vr4100 generate code for vr4100\n\
8439 -m4650 permit R4650 instructions\n\
8440 -no-m4650 do not permit R4650 instructions\n\
8441 -m4010 permit R4010 instructions\n\
8442 -no-m4010 do not permit R4010 instructions\n\
8443 -m4100 permit VR4100 instructions\n\
8444 -no-m4100 do not permit VR4100 instructions\n");
8446 -mips16 generate mips16 instructions\n\
8447 -no-mips16 do not generate mips16 instructions\n");
8449 -O0 remove unneeded NOPs, do not swap branches\n\
8450 -O remove unneeded NOPs and swap branches\n\
8451 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8452 --break, --no-trap break exception on div by 0 and mult overflow\n");
8455 -KPIC, -call_shared generate SVR4 position independent code\n\
8456 -non_shared do not generate position independent code\n\
8457 -xgot assume a 32 bit GOT\n\
8458 -32 create 32 bit object file (default)\n\
8459 -64 create 64 bit object file\n");
8464 mips_init_after_args ()
8466 /* initialize opcodes */
8467 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8468 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8472 md_pcrel_from (fixP
)
8475 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8476 && fixP
->fx_addsy
!= (symbolS
*) NULL
8477 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8479 /* This makes a branch to an undefined symbol be a branch to the
8480 current location. */
8484 /* return the address of the delay slot */
8485 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8488 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8489 reloc for a cons. We could use the definition there, except that
8490 we want to handle 64 bit relocs specially. */
8493 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8496 unsigned int nbytes
;
8500 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8502 if (nbytes
== 8 && ! mips_64
)
8504 if (target_big_endian
)
8510 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8511 as_bad ("Unsupported reloc size %d", nbytes
);
8513 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8516 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8519 /* This is called before the symbol table is processed. In order to
8520 work with gcc when using mips-tfile, we must keep all local labels.
8521 However, in other cases, we want to discard them. If we were
8522 called with -g, but we didn't see any debugging information, it may
8523 mean that gcc is smuggling debugging information through to
8524 mips-tfile, in which case we must generate all local labels. */
8527 mips_frob_file_before_adjust ()
8529 #ifndef NO_ECOFF_DEBUGGING
8532 && ! ecoff_debugging_seen
)
8533 flag_keep_locals
= 1;
8537 /* Sort any unmatched HI16_S relocs so that they immediately precede
8538 the corresponding LO reloc. This is called before md_apply_fix and
8539 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8540 explicit use of the %hi modifier. */
8545 struct mips_hi_fixup
*l
;
8547 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8549 segment_info_type
*seginfo
;
8552 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8554 /* Check quickly whether the next fixup happens to be a matching
8556 if (l
->fixp
->fx_next
!= NULL
8557 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8558 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8559 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8562 /* Look through the fixups for this segment for a matching %lo.
8563 When we find one, move the %hi just in front of it. We do
8564 this in two passes. In the first pass, we try to find a
8565 unique %lo. In the second pass, we permit multiple %hi
8566 relocs for a single %lo (this is a GNU extension). */
8567 seginfo
= seg_info (l
->seg
);
8568 for (pass
= 0; pass
< 2; pass
++)
8573 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8575 /* Check whether this is a %lo fixup which matches l->fixp. */
8576 if (f
->fx_r_type
== BFD_RELOC_LO16
8577 && f
->fx_addsy
== l
->fixp
->fx_addsy
8578 && f
->fx_offset
== l
->fixp
->fx_offset
8581 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8582 || prev
->fx_addsy
!= f
->fx_addsy
8583 || prev
->fx_offset
!= f
->fx_offset
))
8587 /* Move l->fixp before f. */
8588 for (pf
= &seginfo
->fix_root
;
8590 pf
= &(*pf
)->fx_next
)
8591 assert (*pf
!= NULL
);
8593 *pf
= l
->fixp
->fx_next
;
8595 l
->fixp
->fx_next
= f
;
8597 seginfo
->fix_root
= l
->fixp
;
8599 prev
->fx_next
= l
->fixp
;
8611 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8612 "Unmatched %%hi reloc");
8617 /* When generating embedded PIC code we need to use a special
8618 relocation to represent the difference of two symbols in the .text
8619 section (switch tables use a difference of this sort). See
8620 include/coff/mips.h for details. This macro checks whether this
8621 fixup requires the special reloc. */
8622 #define SWITCH_TABLE(fixp) \
8623 ((fixp)->fx_r_type == BFD_RELOC_32 \
8624 && (fixp)->fx_addsy != NULL \
8625 && (fixp)->fx_subsy != NULL \
8626 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8627 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8629 /* When generating embedded PIC code we must keep all PC relative
8630 relocations, in case the linker has to relax a call. We also need
8631 to keep relocations for switch table entries. */
8635 mips_force_relocation (fixp
)
8638 return (mips_pic
== EMBEDDED_PIC
8640 || SWITCH_TABLE (fixp
)
8641 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8642 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8645 /* Apply a fixup to the object file. */
8648 md_apply_fix (fixP
, valueP
)
8655 assert (fixP
->fx_size
== 4
8656 || fixP
->fx_r_type
== BFD_RELOC_16
8657 || fixP
->fx_r_type
== BFD_RELOC_64
);
8661 /* If we aren't adjusting this fixup to be against the section
8662 symbol, we need to adjust the value. */
8664 if (fixP
->fx_addsy
!= NULL
8665 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8666 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8668 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8669 if (value
!= 0 && ! fixP
->fx_pcrel
)
8671 /* In this case, the bfd_install_relocation routine will
8672 incorrectly add the symbol value back in. We just want
8673 the addend to appear in the object file. */
8674 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8679 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8681 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8684 switch (fixP
->fx_r_type
)
8686 case BFD_RELOC_MIPS_JMP
:
8687 case BFD_RELOC_HI16
:
8688 case BFD_RELOC_HI16_S
:
8689 case BFD_RELOC_MIPS_GPREL
:
8690 case BFD_RELOC_MIPS_LITERAL
:
8691 case BFD_RELOC_MIPS_CALL16
:
8692 case BFD_RELOC_MIPS_GOT16
:
8693 case BFD_RELOC_MIPS_GPREL32
:
8694 case BFD_RELOC_MIPS_GOT_HI16
:
8695 case BFD_RELOC_MIPS_GOT_LO16
:
8696 case BFD_RELOC_MIPS_CALL_HI16
:
8697 case BFD_RELOC_MIPS_CALL_LO16
:
8698 case BFD_RELOC_MIPS16_GPREL
:
8700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8701 "Invalid PC relative reloc");
8702 /* Nothing needed to do. The value comes from the reloc entry */
8705 case BFD_RELOC_MIPS16_JMP
:
8706 /* We currently always generate a reloc against a symbol, which
8707 means that we don't want an addend even if the symbol is
8709 fixP
->fx_addnumber
= 0;
8712 case BFD_RELOC_PCREL_HI16_S
:
8713 /* The addend for this is tricky if it is internal, so we just
8714 do everything here rather than in bfd_install_relocation. */
8715 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8717 /* For an external symbol adjust by the address to make it
8718 pcrel_offset. We use the address of the RELLO reloc
8719 which follows this one. */
8720 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8721 + fixP
->fx_next
->fx_where
);
8726 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8727 if (target_big_endian
)
8729 md_number_to_chars (buf
, value
, 2);
8732 case BFD_RELOC_PCREL_LO16
:
8733 /* The addend for this is tricky if it is internal, so we just
8734 do everything here rather than in bfd_install_relocation. */
8735 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8736 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8737 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8738 if (target_big_endian
)
8740 md_number_to_chars (buf
, value
, 2);
8744 /* This is handled like BFD_RELOC_32, but we output a sign
8745 extended value if we are only 32 bits. */
8747 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8749 if (8 <= sizeof (valueT
))
8750 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8757 w1
= w2
= fixP
->fx_where
;
8758 if (target_big_endian
)
8762 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8763 if ((value
& 0x80000000) != 0)
8767 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8773 /* If we are deleting this reloc entry, we must fill in the
8774 value now. This can happen if we have a .word which is not
8775 resolved when it appears but is later defined. We also need
8776 to fill in the value if this is an embedded PIC switch table
8779 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8780 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8785 /* If we are deleting this reloc entry, we must fill in the
8787 assert (fixP
->fx_size
== 2);
8789 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8793 case BFD_RELOC_LO16
:
8794 /* When handling an embedded PIC switch statement, we can wind
8795 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8798 if (value
< -0x8000 || value
> 0x7fff)
8799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8800 "relocation overflow");
8801 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8802 if (target_big_endian
)
8804 md_number_to_chars (buf
, value
, 2);
8808 case BFD_RELOC_16_PCREL_S2
:
8810 * We need to save the bits in the instruction since fixup_segment()
8811 * might be deleting the relocation entry (i.e., a branch within
8812 * the current segment).
8814 if ((value
& 0x3) != 0)
8815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8816 "Branch to odd address (%lx)", value
);
8819 /* update old instruction data */
8820 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8821 if (target_big_endian
)
8822 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8824 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8826 if (value
>= -0x8000 && value
< 0x8000)
8827 insn
|= value
& 0xffff;
8830 /* The branch offset is too large. If this is an
8831 unconditional branch, and we are not generating PIC code,
8832 we can convert it to an absolute jump instruction. */
8833 if (mips_pic
== NO_PIC
8835 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8836 && (fixP
->fx_frag
->fr_address
8837 < text_section
->vma
+ text_section
->_raw_size
)
8838 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8839 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8840 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8842 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8843 insn
= 0x0c000000; /* jal */
8845 insn
= 0x08000000; /* j */
8846 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8848 fixP
->fx_addsy
= section_symbol (text_section
);
8849 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8853 /* FIXME. It would be possible in principle to handle
8854 conditional branches which overflow. They could be
8855 transformed into a branch around a jump. This would
8856 require setting up variant frags for each different
8857 branch type. The native MIPS assembler attempts to
8858 handle these cases, but it appears to do it
8860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8861 "Branch out of range");
8865 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8880 const struct mips_opcode
*p
;
8881 int treg
, sreg
, dreg
, shamt
;
8886 for (i
= 0; i
< NUMOPCODES
; ++i
)
8888 p
= &mips_opcodes
[i
];
8889 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8891 printf ("%08lx %s\t", oc
, p
->name
);
8892 treg
= (oc
>> 16) & 0x1f;
8893 sreg
= (oc
>> 21) & 0x1f;
8894 dreg
= (oc
>> 11) & 0x1f;
8895 shamt
= (oc
>> 6) & 0x1f;
8897 for (args
= p
->args
;; ++args
)
8908 printf ("%c", *args
);
8912 assert (treg
== sreg
);
8913 printf ("$%d,$%d", treg
, sreg
);
8918 printf ("$%d", dreg
);
8923 printf ("$%d", treg
);
8927 printf ("0x%x", treg
);
8932 printf ("$%d", sreg
);
8936 printf ("0x%08lx", oc
& 0x1ffffff);
8948 printf ("$%d", shamt
);
8959 printf ("%08lx UNDEFINED\n", oc
);
8970 name
= input_line_pointer
;
8971 c
= get_symbol_end ();
8972 p
= (symbolS
*) symbol_find_or_make (name
);
8973 *input_line_pointer
= c
;
8977 /* Align the current frag to a given power of two. The MIPS assembler
8978 also automatically adjusts any preceding label. */
8981 mips_align (to
, fill
, label
)
8986 mips_emit_delays (false);
8987 frag_align (to
, fill
, 0);
8988 record_alignment (now_seg
, to
);
8991 assert (S_GET_SEGMENT (label
) == now_seg
);
8992 label
->sy_frag
= frag_now
;
8993 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8997 /* Align to a given power of two. .align 0 turns off the automatic
8998 alignment used by the data creating pseudo-ops. */
9005 register long temp_fill
;
9006 long max_alignment
= 15;
9010 o Note that the assembler pulls down any immediately preceeding label
9011 to the aligned address.
9012 o It's not documented but auto alignment is reinstated by
9013 a .align pseudo instruction.
9014 o Note also that after auto alignment is turned off the mips assembler
9015 issues an error on attempt to assemble an improperly aligned data item.
9020 temp
= get_absolute_expression ();
9021 if (temp
> max_alignment
)
9022 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9025 as_warn ("Alignment negative: 0 assumed.");
9028 if (*input_line_pointer
== ',')
9030 input_line_pointer
++;
9031 temp_fill
= get_absolute_expression ();
9038 mips_align (temp
, (int) temp_fill
,
9039 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9046 demand_empty_rest_of_line ();
9050 mips_flush_pending_output ()
9052 mips_emit_delays (false);
9053 mips_clear_insn_labels ();
9062 /* When generating embedded PIC code, we only use the .text, .lit8,
9063 .sdata and .sbss sections. We change the .data and .rdata
9064 pseudo-ops to use .sdata. */
9065 if (mips_pic
== EMBEDDED_PIC
9066 && (sec
== 'd' || sec
== 'r'))
9069 mips_emit_delays (false);
9079 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9080 demand_empty_rest_of_line ();
9084 if (USE_GLOBAL_POINTER_OPT
)
9086 seg
= subseg_new (RDATA_SECTION_NAME
,
9087 (subsegT
) get_absolute_expression ());
9088 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9090 bfd_set_section_flags (stdoutput
, seg
,
9096 if (strcmp (TARGET_OS
, "elf") != 0)
9097 bfd_set_section_alignment (stdoutput
, seg
, 4);
9099 demand_empty_rest_of_line ();
9103 as_bad ("No read only data section in this object file format");
9104 demand_empty_rest_of_line ();
9110 if (USE_GLOBAL_POINTER_OPT
)
9112 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9113 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9115 bfd_set_section_flags (stdoutput
, seg
,
9116 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9118 if (strcmp (TARGET_OS
, "elf") != 0)
9119 bfd_set_section_alignment (stdoutput
, seg
, 4);
9121 demand_empty_rest_of_line ();
9126 as_bad ("Global pointers not supported; recompile -G 0");
9127 demand_empty_rest_of_line ();
9136 mips_enable_auto_align ()
9147 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9148 mips_emit_delays (false);
9149 if (log_size
> 0 && auto_align
)
9150 mips_align (log_size
, 0, label
);
9151 mips_clear_insn_labels ();
9152 cons (1 << log_size
);
9161 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9163 mips_emit_delays (false);
9167 mips_align (3, 0, label
);
9169 mips_align (2, 0, label
);
9171 mips_clear_insn_labels ();
9176 /* Handle .globl. We need to override it because on Irix 5 you are
9179 where foo is an undefined symbol, to mean that foo should be
9180 considered to be the address of a function. */
9191 name
= input_line_pointer
;
9192 c
= get_symbol_end ();
9193 symbolP
= symbol_find_or_make (name
);
9194 *input_line_pointer
= c
;
9197 /* On Irix 5, every global symbol that is not explicitly labelled as
9198 being a function is apparently labelled as being an object. */
9201 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9206 secname
= input_line_pointer
;
9207 c
= get_symbol_end ();
9208 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9210 as_bad ("%s: no such section", secname
);
9211 *input_line_pointer
= c
;
9213 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9214 flag
= BSF_FUNCTION
;
9217 symbolP
->bsym
->flags
|= flag
;
9219 S_SET_EXTERNAL (symbolP
);
9220 demand_empty_rest_of_line ();
9230 opt
= input_line_pointer
;
9231 c
= get_symbol_end ();
9235 /* FIXME: What does this mean? */
9237 else if (strncmp (opt
, "pic", 3) == 0)
9245 mips_pic
= SVR4_PIC
;
9247 as_bad (".option pic%d not supported", i
);
9249 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9251 if (g_switch_seen
&& g_switch_value
!= 0)
9252 as_warn ("-G may not be used with SVR4 PIC code");
9254 bfd_set_gp_size (stdoutput
, 0);
9258 as_warn ("Unrecognized option \"%s\"", opt
);
9260 *input_line_pointer
= c
;
9261 demand_empty_rest_of_line ();
9268 char *name
= input_line_pointer
, ch
;
9270 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9271 input_line_pointer
++;
9272 ch
= *input_line_pointer
;
9273 *input_line_pointer
= '\0';
9275 if (strcmp (name
, "reorder") == 0)
9277 if (mips_noreorder
&& prev_nop_frag
!= NULL
)
9279 /* If we still have pending nops, we can discard them. The
9280 usual nop handling will insert any that are still
9282 prev_nop_frag
->fr_fix
-= prev_nop_frag_holds
* (mips16
? 2 : 4);
9283 prev_nop_frag
= NULL
;
9287 else if (strcmp (name
, "noreorder") == 0)
9289 mips_emit_delays (true);
9291 mips_any_noreorder
= 1;
9293 else if (strcmp (name
, "at") == 0)
9297 else if (strcmp (name
, "noat") == 0)
9301 else if (strcmp (name
, "macro") == 0)
9303 mips_warn_about_macros
= 0;
9305 else if (strcmp (name
, "nomacro") == 0)
9307 if (mips_noreorder
== 0)
9308 as_bad ("`noreorder' must be set before `nomacro'");
9309 mips_warn_about_macros
= 1;
9311 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9315 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9319 else if (strcmp (name
, "bopt") == 0)
9323 else if (strcmp (name
, "nobopt") == 0)
9327 else if (strcmp (name
, "mips16") == 0
9328 || strcmp (name
, "MIPS-16") == 0)
9330 else if (strcmp (name
, "nomips16") == 0
9331 || strcmp (name
, "noMIPS-16") == 0)
9333 else if (strncmp (name
, "mips", 4) == 0)
9337 /* Permit the user to change the ISA on the fly. Needless to
9338 say, misuse can cause serious problems. */
9339 isa
= atoi (name
+ 4);
9341 mips_isa
= file_mips_isa
;
9342 else if (isa
< 1 || isa
> 4)
9343 as_bad ("unknown ISA level");
9347 else if (strcmp (name
, "autoextend") == 0)
9348 mips16_autoextend
= 1;
9349 else if (strcmp (name
, "noautoextend") == 0)
9350 mips16_autoextend
= 0;
9353 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9355 *input_line_pointer
= ch
;
9356 demand_empty_rest_of_line ();
9359 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9360 .option pic2. It means to generate SVR4 PIC calls. */
9366 mips_pic
= SVR4_PIC
;
9367 if (USE_GLOBAL_POINTER_OPT
)
9369 if (g_switch_seen
&& g_switch_value
!= 0)
9370 as_warn ("-G may not be used with SVR4 PIC code");
9373 bfd_set_gp_size (stdoutput
, 0);
9374 demand_empty_rest_of_line ();
9377 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9378 PIC code. It sets the $gp register for the function based on the
9379 function address, which is in the register named in the argument.
9380 This uses a relocation against _gp_disp, which is handled specially
9381 by the linker. The result is:
9382 lui $gp,%hi(_gp_disp)
9383 addiu $gp,$gp,%lo(_gp_disp)
9384 addu $gp,$gp,.cpload argument
9385 The .cpload argument is normally $25 == $t9. */
9394 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9395 if (mips_pic
!= SVR4_PIC
)
9401 /* .cpload should be a in .set noreorder section. */
9402 if (mips_noreorder
== 0)
9403 as_warn (".cpload not in noreorder section");
9406 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9407 ex
.X_op_symbol
= NULL
;
9408 ex
.X_add_number
= 0;
9410 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9411 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9413 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9414 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9415 (int) BFD_RELOC_LO16
);
9417 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9418 GP
, GP
, tc_get_register (0));
9420 demand_empty_rest_of_line ();
9423 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9424 offset from $sp. The offset is remembered, and after making a PIC
9425 call $gp is restored from that location. */
9428 s_cprestore (ignore
)
9434 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9435 if (mips_pic
!= SVR4_PIC
)
9441 mips_cprestore_offset
= get_absolute_expression ();
9443 ex
.X_op
= O_constant
;
9444 ex
.X_add_symbol
= NULL
;
9445 ex
.X_op_symbol
= NULL
;
9446 ex
.X_add_number
= mips_cprestore_offset
;
9448 macro_build ((char *) NULL
, &icnt
, &ex
,
9449 mips_isa
< 3 ? "sw" : "sd",
9450 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9452 demand_empty_rest_of_line ();
9455 /* Handle the .gpword pseudo-op. This is used when generating PIC
9456 code. It generates a 32 bit GP relative reloc. */
9466 /* When not generating PIC code, this is treated as .word. */
9467 if (mips_pic
!= SVR4_PIC
)
9473 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9474 mips_emit_delays (true);
9476 mips_align (2, 0, label
);
9477 mips_clear_insn_labels ();
9481 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9483 as_bad ("Unsupported use of .gpword");
9484 ignore_rest_of_line ();
9488 md_number_to_chars (p
, (valueT
) 0, 4);
9489 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9490 BFD_RELOC_MIPS_GPREL32
);
9492 demand_empty_rest_of_line ();
9495 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9496 tables in SVR4 PIC code. */
9505 /* This is ignored when not generating SVR4 PIC code. */
9506 if (mips_pic
!= SVR4_PIC
)
9512 /* Add $gp to the register named as an argument. */
9513 reg
= tc_get_register (0);
9514 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9515 mips_isa
< 3 ? "addu" : "daddu",
9516 "d,v,t", reg
, reg
, GP
);
9518 demand_empty_rest_of_line ();
9521 /* Handle the .insn pseudo-op. This marks instruction labels in
9522 mips16 mode. This permits the linker to handle them specially,
9523 such as generating jalx instructions when needed. We also make
9524 them odd for the duration of the assembly, in order to generate the
9525 right sort of code. We will make them even in the adjust_symtab
9526 routine, while leaving them marked. This is convenient for the
9527 debugger and the disassembler. The linker knows to make them odd
9536 struct insn_label_list
*l
;
9538 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
9541 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9542 S_SET_OTHER (l
->label
, STO_MIPS16
);
9544 ++l
->label
->sy_value
.X_add_number
;
9547 mips_clear_insn_labels ();
9550 demand_empty_rest_of_line ();
9553 /* Parse a register string into a number. Called from the ECOFF code
9554 to parse .frame. The argument is non-zero if this is the frame
9555 register, so that we can record it in mips_frame_reg. */
9558 tc_get_register (frame
)
9564 if (*input_line_pointer
++ != '$')
9566 as_warn ("expected `$'");
9569 else if (isdigit ((unsigned char) *input_line_pointer
))
9571 reg
= get_absolute_expression ();
9572 if (reg
< 0 || reg
>= 32)
9574 as_warn ("Bad register number");
9580 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9582 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9584 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9586 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9590 as_warn ("Unrecognized register name");
9593 input_line_pointer
+= 2;
9596 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9601 md_section_align (seg
, addr
)
9605 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9608 /* We don't need to align ELF sections to the full alignment.
9609 However, Irix 5 may prefer that we align them at least to a 16
9610 byte boundary. We don't bother to align the sections if we are
9611 targeted for an embedded system. */
9612 if (strcmp (TARGET_OS
, "elf") == 0)
9618 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9621 /* Utility routine, called from above as well. If called while the
9622 input file is still being read, it's only an approximation. (For
9623 example, a symbol may later become defined which appeared to be
9624 undefined earlier.) */
9627 nopic_need_relax (sym
)
9633 if (USE_GLOBAL_POINTER_OPT
)
9635 const char *symname
;
9638 /* Find out whether this symbol can be referenced off the GP
9639 register. It can be if it is smaller than the -G size or if
9640 it is in the .sdata or .sbss section. Certain symbols can
9641 not be referenced off the GP, although it appears as though
9643 symname
= S_GET_NAME (sym
);
9644 if (symname
!= (const char *) NULL
9645 && (strcmp (symname
, "eprol") == 0
9646 || strcmp (symname
, "etext") == 0
9647 || strcmp (symname
, "_gp") == 0
9648 || strcmp (symname
, "edata") == 0
9649 || strcmp (symname
, "_fbss") == 0
9650 || strcmp (symname
, "_fdata") == 0
9651 || strcmp (symname
, "_ftext") == 0
9652 || strcmp (symname
, "end") == 0
9653 || strcmp (symname
, "_gp_disp") == 0))
9655 else if (! S_IS_DEFINED (sym
)
9657 #ifndef NO_ECOFF_DEBUGGING
9658 || (sym
->ecoff_extern_size
!= 0
9659 && sym
->ecoff_extern_size
<= g_switch_value
)
9661 || (S_GET_VALUE (sym
) != 0
9662 && S_GET_VALUE (sym
) <= g_switch_value
)))
9666 const char *segname
;
9668 segname
= segment_name (S_GET_SEGMENT (sym
));
9669 assert (strcmp (segname
, ".lit8") != 0
9670 && strcmp (segname
, ".lit4") != 0);
9671 change
= (strcmp (segname
, ".sdata") != 0
9672 && strcmp (segname
, ".sbss") != 0);
9677 /* We are not optimizing for the GP register. */
9681 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9682 extended opcode. SEC is the section the frag is in. */
9685 mips16_extended_frag (fragp
, sec
, stretch
)
9691 register const struct mips16_immed_operand
*op
;
9693 int mintiny
, maxtiny
;
9696 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9698 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9701 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9702 op
= mips16_immed_operands
;
9703 while (op
->type
!= type
)
9706 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9711 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9714 maxtiny
= 1 << op
->nbits
;
9719 maxtiny
= (1 << op
->nbits
) - 1;
9724 mintiny
= - (1 << (op
->nbits
- 1));
9725 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9728 /* We can't call S_GET_VALUE here, because we don't want to lock in
9729 a particular frag address. */
9730 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9732 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9733 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9734 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9736 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9737 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9740 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9741 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9742 + fragp
->fr_symbol
->sy_value
.X_add_number
9743 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9744 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9753 /* We won't have the section when we are called from
9754 mips_relax_frag. However, we will always have been called
9755 from md_estimate_size_before_relax first. If this is a
9756 branch to a different section, we mark it as such. If SEC is
9757 NULL, and the frag is not marked, then it must be a branch to
9758 the same section. */
9761 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9769 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9771 /* FIXME: We should support this, and let the linker
9772 catch branches and loads that are out of range. */
9773 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9774 "unsupported PC relative reference to different section");
9780 /* In this case, we know for sure that the symbol fragment is in
9781 the same section. If the fr_address of the symbol fragment
9782 is greater then the address of this fragment we want to add
9783 in STRETCH in order to get a better estimate of the address.
9784 This particularly matters because of the shift bits. */
9786 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9790 /* Adjust stretch for any alignment frag. Note that if have
9791 been expanding the earlier code, the symbol may be
9792 defined in what appears to be an earlier frag. FIXME:
9793 This doesn't handle the fr_subtype field, which specifies
9794 a maximum number of bytes to skip when doing an
9797 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
9800 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9803 stretch
= - ((- stretch
)
9804 & ~ ((1 << (int) f
->fr_offset
) - 1));
9806 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9815 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9817 /* The base address rules are complicated. The base address of
9818 a branch is the following instruction. The base address of a
9819 PC relative load or add is the instruction itself, but if it
9820 is in a delay slot (in which case it can not be extended) use
9821 the address of the instruction whose delay slot it is in. */
9822 if (type
== 'p' || type
== 'q')
9826 /* If we are currently assuming that this frag should be
9827 extended, then, the current address is two bytes
9829 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9832 /* Ignore the low bit in the target, since it will be set
9833 for a text label. */
9837 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9839 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9842 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9844 /* Branch offsets have an implicit 0 in the lowest bit. */
9845 if (type
== 'p' || type
== 'q')
9848 /* If any of the shifted bits are set, we must use an extended
9849 opcode. If the address depends on the size of this
9850 instruction, this can lead to a loop, so we arrange to always
9851 use an extended opcode. We only check this when we are in
9852 the main relaxation loop, when SEC is NULL. */
9853 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9856 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9860 /* If we are about to mark a frag as extended because the value
9861 is precisely maxtiny + 1, then there is a chance of an
9862 infinite loop as in the following code:
9867 In this case when the la is extended, foo is 0x3fc bytes
9868 away, so the la can be shrunk, but then foo is 0x400 away, so
9869 the la must be extended. To avoid this loop, we mark the
9870 frag as extended if it was small, and is about to become
9871 extended with a value of maxtiny + 1. */
9872 if (val
== ((maxtiny
+ 1) << op
->shift
)
9873 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9877 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9881 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9882 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9884 if ((val
& ((1 << op
->shift
) - 1)) != 0
9885 || val
< (mintiny
<< op
->shift
)
9886 || val
> (maxtiny
<< op
->shift
))
9892 /* Estimate the size of a frag before relaxing. Unless this is the
9893 mips16, we are not really relaxing here, and the final size is
9894 encoded in the subtype information. For the mips16, we have to
9895 decide whether we are using an extended opcode or not. */
9899 md_estimate_size_before_relax (fragp
, segtype
)
9905 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9907 if (mips16_extended_frag (fragp
, segtype
, 0))
9909 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9914 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9919 if (mips_pic
== NO_PIC
)
9921 change
= nopic_need_relax (fragp
->fr_symbol
);
9923 else if (mips_pic
== SVR4_PIC
)
9928 sym
= fragp
->fr_symbol
;
9930 /* Handle the case of a symbol equated to another symbol. */
9931 while (sym
->sy_value
.X_op
== O_symbol
9932 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
9936 /* It's possible to get a loop here in a badly written
9938 n
= sym
->sy_value
.X_add_symbol
;
9944 symsec
= S_GET_SEGMENT (sym
);
9946 /* This must duplicate the test in adjust_reloc_syms. */
9947 change
= (symsec
!= &bfd_und_section
9948 && symsec
!= &bfd_abs_section
9949 && ! bfd_is_com_section (symsec
));
9956 /* Record the offset to the first reloc in the fr_opcode field.
9957 This lets md_convert_frag and tc_gen_reloc know that the code
9958 must be expanded. */
9959 fragp
->fr_opcode
= (fragp
->fr_literal
9961 - RELAX_OLD (fragp
->fr_subtype
)
9962 + RELAX_RELOC1 (fragp
->fr_subtype
));
9963 /* FIXME: This really needs as_warn_where. */
9964 if (RELAX_WARN (fragp
->fr_subtype
))
9965 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9971 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9974 /* This is called to see whether a reloc against a defined symbol
9975 should be converted into a reloc against a section. Don't adjust
9976 MIPS16 jump relocations, so we don't have to worry about the format
9977 of the offset in the .o file. Don't adjust relocations against
9978 mips16 symbols, so that the linker can find them if it needs to set
9982 mips_fix_adjustable (fixp
)
9985 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9987 if (fixp
->fx_addsy
== NULL
)
9990 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9991 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
9992 && fixp
->fx_subsy
== NULL
)
9998 /* Translate internal representation of relocation info to BFD target
10002 tc_gen_reloc (section
, fixp
)
10006 static arelent
*retval
[4];
10008 bfd_reloc_code_real_type code
;
10010 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10013 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10014 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10016 if (mips_pic
== EMBEDDED_PIC
10017 && SWITCH_TABLE (fixp
))
10019 /* For a switch table entry we use a special reloc. The addend
10020 is actually the difference between the reloc address and the
10022 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10023 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10024 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10025 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10027 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10029 /* We use a special addend for an internal RELLO reloc. */
10030 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10031 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10033 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10035 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10037 assert (fixp
->fx_next
!= NULL
10038 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10039 /* We use a special addend for an internal RELHI reloc. The
10040 reloc is relative to the RELLO; adjust the addend
10042 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10043 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10044 + fixp
->fx_next
->fx_where
10045 - S_GET_VALUE (fixp
->fx_subsy
));
10047 reloc
->addend
= (fixp
->fx_addnumber
10048 + fixp
->fx_next
->fx_frag
->fr_address
10049 + fixp
->fx_next
->fx_where
);
10051 else if (fixp
->fx_pcrel
== 0)
10052 reloc
->addend
= fixp
->fx_addnumber
;
10055 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10056 /* A gruesome hack which is a result of the gruesome gas reloc
10058 reloc
->addend
= reloc
->address
;
10060 reloc
->addend
= -reloc
->address
;
10063 /* If this is a variant frag, we may need to adjust the existing
10064 reloc and generate a new one. */
10065 if (fixp
->fx_frag
->fr_opcode
!= NULL
10066 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10067 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10068 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10069 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10070 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10071 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10072 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10076 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10078 /* If this is not the last reloc in this frag, then we have two
10079 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10080 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10081 the second one handle all of them. */
10082 if (fixp
->fx_next
!= NULL
10083 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10085 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10086 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10087 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10088 && (fixp
->fx_next
->fx_r_type
10089 == BFD_RELOC_MIPS_GOT_LO16
))
10090 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10091 && (fixp
->fx_next
->fx_r_type
10092 == BFD_RELOC_MIPS_CALL_LO16
)));
10097 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10098 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10099 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10101 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10102 reloc2
->address
= (reloc
->address
10103 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10104 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10105 reloc2
->addend
= fixp
->fx_addnumber
;
10106 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10107 assert (reloc2
->howto
!= NULL
);
10109 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10113 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10116 reloc3
->address
+= 4;
10119 if (mips_pic
== NO_PIC
)
10121 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10122 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10124 else if (mips_pic
== SVR4_PIC
)
10126 switch (fixp
->fx_r_type
)
10130 case BFD_RELOC_MIPS_GOT16
:
10132 case BFD_RELOC_MIPS_CALL16
:
10133 case BFD_RELOC_MIPS_GOT_LO16
:
10134 case BFD_RELOC_MIPS_CALL_LO16
:
10135 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10143 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10144 fixup_segment converted a non-PC relative reloc into a PC
10145 relative reloc. In such a case, we need to convert the reloc
10147 code
= fixp
->fx_r_type
;
10148 if (fixp
->fx_pcrel
)
10153 code
= BFD_RELOC_8_PCREL
;
10156 code
= BFD_RELOC_16_PCREL
;
10159 code
= BFD_RELOC_32_PCREL
;
10162 code
= BFD_RELOC_64_PCREL
;
10164 case BFD_RELOC_8_PCREL
:
10165 case BFD_RELOC_16_PCREL
:
10166 case BFD_RELOC_32_PCREL
:
10167 case BFD_RELOC_64_PCREL
:
10168 case BFD_RELOC_16_PCREL_S2
:
10169 case BFD_RELOC_PCREL_HI16_S
:
10170 case BFD_RELOC_PCREL_LO16
:
10173 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10174 "Cannot make %s relocation PC relative",
10175 bfd_get_reloc_code_name (code
));
10179 /* To support a PC relative reloc when generating embedded PIC code
10180 for ECOFF, we use a Cygnus extension. We check for that here to
10181 make sure that we don't let such a reloc escape normally. */
10182 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10183 && code
== BFD_RELOC_16_PCREL_S2
10184 && mips_pic
!= EMBEDDED_PIC
)
10185 reloc
->howto
= NULL
;
10187 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10189 if (reloc
->howto
== NULL
)
10191 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10192 "Can not represent %s relocation in this object file format",
10193 bfd_get_reloc_code_name (code
));
10200 /* Relax a machine dependent frag. This returns the amount by which
10201 the current size of the frag should change. */
10204 mips_relax_frag (fragp
, stretch
)
10208 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10211 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10213 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10215 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10220 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10222 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10229 /* Convert a machine dependent frag. */
10232 md_convert_frag (abfd
, asec
, fragp
)
10240 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10243 register const struct mips16_immed_operand
*op
;
10244 boolean small
, ext
;
10247 unsigned long insn
;
10248 boolean use_extend
;
10249 unsigned short extend
;
10251 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10252 op
= mips16_immed_operands
;
10253 while (op
->type
!= type
)
10256 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10267 resolve_symbol_value (fragp
->fr_symbol
);
10268 val
= S_GET_VALUE (fragp
->fr_symbol
);
10273 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10275 /* The rules for the base address of a PC relative reloc are
10276 complicated; see mips16_extended_frag. */
10277 if (type
== 'p' || type
== 'q')
10282 /* Ignore the low bit in the target, since it will be
10283 set for a text label. */
10284 if ((val
& 1) != 0)
10287 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10289 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10292 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10295 /* Make sure the section winds up with the alignment we have
10298 record_alignment (asec
, op
->shift
);
10302 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10303 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10304 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10305 "extended instruction in delay slot");
10307 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10309 if (target_big_endian
)
10310 insn
= bfd_getb16 (buf
);
10312 insn
= bfd_getl16 (buf
);
10314 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10315 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10316 small
, ext
, &insn
, &use_extend
, &extend
);
10320 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10321 fragp
->fr_fix
+= 2;
10325 md_number_to_chars (buf
, insn
, 2);
10326 fragp
->fr_fix
+= 2;
10331 if (fragp
->fr_opcode
== NULL
)
10334 old
= RELAX_OLD (fragp
->fr_subtype
);
10335 new = RELAX_NEW (fragp
->fr_subtype
);
10336 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10339 memcpy (fixptr
- old
, fixptr
, new);
10341 fragp
->fr_fix
+= new - old
;
10347 /* This function is called after the relocs have been generated.
10348 We've been storing mips16 text labels as odd. Here we convert them
10349 back to even for the convenience of the debugger. */
10352 mips_frob_file_after_relocs ()
10355 unsigned int count
, i
;
10357 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10360 syms
= bfd_get_outsymbols (stdoutput
);
10361 count
= bfd_get_symcount (stdoutput
);
10362 for (i
= 0; i
< count
; i
++, syms
++)
10364 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10365 && ((*syms
)->value
& 1) != 0)
10367 (*syms
)->value
&= ~1;
10368 /* If the symbol has an odd size, it was probably computed
10369 incorrectly, so adjust that as well. */
10370 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10371 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10378 /* This function is called whenever a label is defined. It is used
10379 when handling branch delays; if a branch has a label, we assume we
10380 can not move it. */
10383 mips_define_label (sym
)
10386 struct insn_label_list
*l
;
10388 if (free_insn_labels
== NULL
)
10389 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10392 l
= free_insn_labels
;
10393 free_insn_labels
= l
->next
;
10397 l
->next
= insn_labels
;
10401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10403 /* Some special processing for a MIPS ELF file. */
10406 mips_elf_final_processing ()
10408 /* Write out the register information. */
10413 s
.ri_gprmask
= mips_gprmask
;
10414 s
.ri_cprmask
[0] = mips_cprmask
[0];
10415 s
.ri_cprmask
[1] = mips_cprmask
[1];
10416 s
.ri_cprmask
[2] = mips_cprmask
[2];
10417 s
.ri_cprmask
[3] = mips_cprmask
[3];
10418 /* The gp_value field is set by the MIPS ELF backend. */
10420 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10421 ((Elf32_External_RegInfo
*)
10422 mips_regmask_frag
));
10426 Elf64_Internal_RegInfo s
;
10428 s
.ri_gprmask
= mips_gprmask
;
10430 s
.ri_cprmask
[0] = mips_cprmask
[0];
10431 s
.ri_cprmask
[1] = mips_cprmask
[1];
10432 s
.ri_cprmask
[2] = mips_cprmask
[2];
10433 s
.ri_cprmask
[3] = mips_cprmask
[3];
10434 /* The gp_value field is set by the MIPS ELF backend. */
10436 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10437 ((Elf64_External_RegInfo
*)
10438 mips_regmask_frag
));
10441 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10442 sort of BFD interface for this. */
10443 if (mips_any_noreorder
)
10444 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10445 if (mips_pic
!= NO_PIC
)
10446 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10449 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10451 /* These functions should really be defined by the object file format,
10452 since they are related to debugging information. However, this
10453 code has to work for the a.out format, which does not define them,
10454 so we provide simple versions here. These don't actually generate
10455 any debugging information, but they do simple checking and someday
10456 somebody may make them useful. */
10460 struct loc
*loc_next
;
10461 unsigned long loc_fileno
;
10462 unsigned long loc_lineno
;
10463 unsigned long loc_offset
;
10464 unsigned short loc_delta
;
10465 unsigned short loc_count
;
10472 typedef struct proc
10474 struct proc
*proc_next
;
10475 struct symbol
*proc_isym
;
10476 struct symbol
*proc_end
;
10477 unsigned long proc_reg_mask
;
10478 unsigned long proc_reg_offset
;
10479 unsigned long proc_fpreg_mask
;
10480 unsigned long proc_fpreg_offset
;
10481 unsigned long proc_frameoffset
;
10482 unsigned long proc_framereg
;
10483 unsigned long proc_pcreg
;
10485 struct file
*proc_file
;
10490 typedef struct file
10492 struct file
*file_next
;
10493 unsigned long file_fileno
;
10494 struct symbol
*file_symbol
;
10495 struct symbol
*file_end
;
10496 struct proc
*file_proc
;
10501 static struct obstack proc_frags
;
10502 static procS
*proc_lastP
;
10503 static procS
*proc_rootP
;
10504 static int numprocs
;
10509 obstack_begin (&proc_frags
, 0x2000);
10515 /* check for premature end, nesting errors, etc */
10516 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10517 as_warn ("missing `.end' at end of assembly");
10526 if (*input_line_pointer
== '-')
10528 ++input_line_pointer
;
10531 if (!isdigit (*input_line_pointer
))
10532 as_bad ("Expected simple number.");
10533 if (input_line_pointer
[0] == '0')
10535 if (input_line_pointer
[1] == 'x')
10537 input_line_pointer
+= 2;
10538 while (isxdigit (*input_line_pointer
))
10541 val
|= hex_value (*input_line_pointer
++);
10543 return negative
? -val
: val
;
10547 ++input_line_pointer
;
10548 while (isdigit (*input_line_pointer
))
10551 val
|= *input_line_pointer
++ - '0';
10553 return negative
? -val
: val
;
10556 if (!isdigit (*input_line_pointer
))
10558 printf (" *input_line_pointer == '%c' 0x%02x\n",
10559 *input_line_pointer
, *input_line_pointer
);
10560 as_warn ("Invalid number");
10563 while (isdigit (*input_line_pointer
))
10566 val
+= *input_line_pointer
++ - '0';
10568 return negative
? -val
: val
;
10571 /* The .file directive; just like the usual .file directive, but there
10572 is an initial number which is the ECOFF file index. */
10580 line
= get_number ();
10585 /* The .end directive. */
10593 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10596 demand_empty_rest_of_line ();
10600 if (now_seg
!= text_section
)
10601 as_warn (".end not in text section");
10604 as_warn (".end and no .ent seen yet.");
10610 assert (S_GET_NAME (p
));
10611 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10612 as_warn (".end symbol does not match .ent symbol.");
10615 proc_lastP
->proc_end
= (symbolS
*) 1;
10618 /* The .aent and .ent directives. */
10628 symbolP
= get_symbol ();
10629 if (*input_line_pointer
== ',')
10630 input_line_pointer
++;
10631 SKIP_WHITESPACE ();
10632 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10633 number
= get_number ();
10634 if (now_seg
!= text_section
)
10635 as_warn (".ent or .aent not in text section.");
10637 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10638 as_warn ("missing `.end'");
10642 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10643 procP
->proc_isym
= symbolP
;
10644 procP
->proc_reg_mask
= 0;
10645 procP
->proc_reg_offset
= 0;
10646 procP
->proc_fpreg_mask
= 0;
10647 procP
->proc_fpreg_offset
= 0;
10648 procP
->proc_frameoffset
= 0;
10649 procP
->proc_framereg
= 0;
10650 procP
->proc_pcreg
= 0;
10651 procP
->proc_end
= NULL
;
10652 procP
->proc_next
= NULL
;
10654 proc_lastP
->proc_next
= procP
;
10656 proc_rootP
= procP
;
10657 proc_lastP
= procP
;
10660 demand_empty_rest_of_line ();
10663 /* The .frame directive. */
10676 frame_reg
= tc_get_register (1);
10677 if (*input_line_pointer
== ',')
10678 input_line_pointer
++;
10679 frame_off
= get_absolute_expression ();
10680 if (*input_line_pointer
== ',')
10681 input_line_pointer
++;
10682 pcreg
= tc_get_register (0);
10684 /* bob third eye */
10685 assert (proc_rootP
);
10686 proc_rootP
->proc_framereg
= frame_reg
;
10687 proc_rootP
->proc_frameoffset
= frame_off
;
10688 proc_rootP
->proc_pcreg
= pcreg
;
10689 /* bob macho .frame */
10691 /* We don't have to write out a frame stab for unoptimized code. */
10692 if (!(frame_reg
== FP
&& frame_off
== 0))
10695 as_warn ("No .ent for .frame to use.");
10696 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10697 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10698 S_SET_TYPE (symP
, N_RMASK
);
10699 S_SET_OTHER (symP
, 0);
10700 S_SET_DESC (symP
, 0);
10701 symP
->sy_forward
= proc_lastP
->proc_isym
;
10702 /* bob perhaps I should have used pseudo set */
10704 demand_empty_rest_of_line ();
10708 /* The .fmask and .mask directives. */
10715 char str
[100], *strP
;
10721 mask
= get_number ();
10722 if (*input_line_pointer
== ',')
10723 input_line_pointer
++;
10724 off
= get_absolute_expression ();
10726 /* bob only for coff */
10727 assert (proc_rootP
);
10728 if (reg_type
== 'F')
10730 proc_rootP
->proc_fpreg_mask
= mask
;
10731 proc_rootP
->proc_fpreg_offset
= off
;
10735 proc_rootP
->proc_reg_mask
= mask
;
10736 proc_rootP
->proc_reg_offset
= off
;
10739 /* bob macho .mask + .fmask */
10741 /* We don't have to write out a mask stab if no saved regs. */
10745 as_warn ("No .ent for .mask to use.");
10747 for (i
= 0; i
< 32; i
++)
10751 sprintf (strP
, "%c%d,", reg_type
, i
);
10752 strP
+= strlen (strP
);
10756 sprintf (strP
, ";%d,", off
);
10757 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10758 S_SET_TYPE (symP
, N_RMASK
);
10759 S_SET_OTHER (symP
, 0);
10760 S_SET_DESC (symP
, 0);
10761 symP
->sy_forward
= proc_lastP
->proc_isym
;
10762 /* bob perhaps I should have used pseudo set */
10767 /* The .loc directive. */
10778 assert (now_seg
== text_section
);
10780 lineno
= get_number ();
10781 addroff
= frag_now_fix ();
10783 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10784 S_SET_TYPE (symbolP
, N_SLINE
);
10785 S_SET_OTHER (symbolP
, 0);
10786 S_SET_DESC (symbolP
, lineno
);
10787 symbolP
->sy_segment
= now_seg
;