1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, pic, sym32, nomacro, \
1138 | ((pic) ? 0x100 : 0) \
1139 | ((sym32) ? 0x200 : 0) \
1140 | ((nomacro) ? 0x400 : 0) \
1141 | ((small) ? 0x800 : 0) \
1142 | ((ext) ? 0x1000 : 0) \
1143 | ((dslot) ? 0x2000 : 0) \
1144 | ((jal_dslot) ? 0x4000 : 0))
1146 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1147 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1148 #define RELAX_MIPS16_PIC(i) (((i) & 0x100) != 0)
1149 #define RELAX_MIPS16_SYM32(i) (((i) & 0x200) != 0)
1150 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x400) != 0)
1151 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x800) != 0)
1152 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x1000) != 0)
1153 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x2000) != 0)
1154 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x8000) != 0)
1157 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x8000)
1158 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x8000)
1159 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x10000) != 0)
1160 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x10000)
1161 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x10000)
1162 #define RELAX_MIPS16_MACRO(i) (((i) & 0x20000) != 0)
1163 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x20000)
1164 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x20000)
1166 /* For microMIPS code, we use relaxation similar to one we use for
1167 MIPS16 code. Some instructions that take immediate values support
1168 two encodings: a small one which takes some small value, and a
1169 larger one which takes a 16 bit value. As some branches also follow
1170 this pattern, relaxing these values is required.
1172 We can assemble both microMIPS and normal MIPS code in a single
1173 object. Therefore, we need to support this type of relaxation at
1174 the same time that we support the relaxation described above. We
1175 use one of the high bits of the subtype field to distinguish these
1178 The information we store for this type of relaxation is the argument
1179 code found in the opcode file for this relocation, the register
1180 selected as the assembler temporary, whether in the 32-bit
1181 instruction mode, whether the branch is unconditional, whether it is
1182 compact, whether there is no delay-slot instruction available to fill
1183 in, whether it stores the link address implicitly in $ra, whether
1184 relaxation of out-of-range 32-bit branches to a sequence of
1185 instructions is enabled, and whether the displacement of a branch is
1186 too large to fit as an immediate argument of a 16-bit and a 32-bit
1187 branch, respectively. */
1188 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1189 uncond, compact, link, nods, \
1190 relax32, toofar16, toofar32) \
1193 | (((at) & 0x1f) << 8) \
1194 | ((insn32) ? 0x2000 : 0) \
1195 | ((pic) ? 0x4000 : 0) \
1196 | ((uncond) ? 0x8000 : 0) \
1197 | ((compact) ? 0x10000 : 0) \
1198 | ((link) ? 0x20000 : 0) \
1199 | ((nods) ? 0x40000 : 0) \
1200 | ((relax32) ? 0x80000 : 0) \
1201 | ((toofar16) ? 0x100000 : 0) \
1202 | ((toofar32) ? 0x200000 : 0))
1203 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1204 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1205 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1206 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1207 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1208 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1209 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1210 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1211 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1212 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1214 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1215 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1216 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1217 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1218 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1219 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1221 /* Sign-extend 16-bit value X. */
1222 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1224 /* Is the given value a sign-extended 32-bit value? */
1225 #define IS_SEXT_32BIT_NUM(x) \
1226 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1227 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1229 /* Is the given value a sign-extended 16-bit value? */
1230 #define IS_SEXT_16BIT_NUM(x) \
1231 (((x) &~ (offsetT) 0x7fff) == 0 \
1232 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1234 /* Is the given value a sign-extended 12-bit value? */
1235 #define IS_SEXT_12BIT_NUM(x) \
1236 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1238 /* Is the given value a sign-extended 9-bit value? */
1239 #define IS_SEXT_9BIT_NUM(x) \
1240 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1242 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1243 #define IS_ZEXT_32BIT_NUM(x) \
1244 (((x) &~ (offsetT) 0xffffffff) == 0 \
1245 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1247 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1249 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1250 (((STRUCT) >> (SHIFT)) & (MASK))
1252 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1253 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1255 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1256 : EXTRACT_BITS ((INSN).insn_opcode, \
1257 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1258 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1259 EXTRACT_BITS ((INSN).insn_opcode, \
1260 MIPS16OP_MASK_##FIELD, \
1261 MIPS16OP_SH_##FIELD)
1263 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1264 #define MIPS16_EXTEND (0xf000U << 16)
1266 /* Whether or not we are emitting a branch-likely macro. */
1267 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1269 /* Global variables used when generating relaxable macros. See the
1270 comment above RELAX_ENCODE for more details about how relaxation
1273 /* 0 if we're not emitting a relaxable macro.
1274 1 if we're emitting the first of the two relaxation alternatives.
1275 2 if we're emitting the second alternative. */
1278 /* The first relaxable fixup in the current frag. (In other words,
1279 the first fixup that refers to relaxable code.) */
1282 /* sizes[0] says how many bytes of the first alternative are stored in
1283 the current frag. Likewise sizes[1] for the second alternative. */
1284 unsigned int sizes
[2];
1286 /* The symbol on which the choice of sequence depends. */
1290 /* Global variables used to decide whether a macro needs a warning. */
1292 /* True if the macro is in a branch delay slot. */
1293 bfd_boolean delay_slot_p
;
1295 /* Set to the length in bytes required if the macro is in a delay slot
1296 that requires a specific length of instruction, otherwise zero. */
1297 unsigned int delay_slot_length
;
1299 /* For relaxable macros, sizes[0] is the length of the first alternative
1300 in bytes and sizes[1] is the length of the second alternative.
1301 For non-relaxable macros, both elements give the length of the
1303 unsigned int sizes
[2];
1305 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1306 instruction of the first alternative in bytes and first_insn_sizes[1]
1307 is the length of the first instruction of the second alternative.
1308 For non-relaxable macros, both elements give the length of the first
1309 instruction in bytes.
1311 Set to zero if we haven't yet seen the first instruction. */
1312 unsigned int first_insn_sizes
[2];
1314 /* For relaxable macros, insns[0] is the number of instructions for the
1315 first alternative and insns[1] is the number of instructions for the
1318 For non-relaxable macros, both elements give the number of
1319 instructions for the macro. */
1320 unsigned int insns
[2];
1322 /* The first variant frag for this macro. */
1324 } mips_macro_warning
;
1326 /* Prototypes for static functions. */
1328 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1330 static void append_insn
1331 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1332 bfd_boolean expansionp
);
1333 static void mips_no_prev_insn (void);
1334 static void macro_build (expressionS
*, const char *, const char *, ...);
1335 static void mips16_macro_build
1336 (expressionS
*, const char *, const char *, va_list *);
1337 static void load_register (int, expressionS
*, int);
1338 static void macro_start (void);
1339 static void macro_end (void);
1340 static void macro (struct mips_cl_insn
*ip
, char *str
);
1341 static void mips16_macro (struct mips_cl_insn
* ip
);
1342 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1343 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1344 static void mips16_immed
1345 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1346 unsigned int, unsigned long *);
1347 static size_t my_getSmallExpression
1348 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1349 static void my_getExpression (expressionS
*, char *);
1350 static void s_align (int);
1351 static void s_change_sec (int);
1352 static void s_change_section (int);
1353 static void s_cons (int);
1354 static void s_float_cons (int);
1355 static void s_mips_globl (int);
1356 static void s_option (int);
1357 static void s_mipsset (int);
1358 static void s_abicalls (int);
1359 static void s_cpload (int);
1360 static void s_cpsetup (int);
1361 static void s_cplocal (int);
1362 static void s_cprestore (int);
1363 static void s_cpreturn (int);
1364 static void s_dtprelword (int);
1365 static void s_dtpreldword (int);
1366 static void s_tprelword (int);
1367 static void s_tpreldword (int);
1368 static void s_gpvalue (int);
1369 static void s_gpword (int);
1370 static void s_gpdword (int);
1371 static void s_ehword (int);
1372 static void s_cpadd (int);
1373 static void s_insn (int);
1374 static void s_nan (int);
1375 static void s_module (int);
1376 static void s_mips_ent (int);
1377 static void s_mips_end (int);
1378 static void s_mips_frame (int);
1379 static void s_mips_mask (int reg_type
);
1380 static void s_mips_stab (int);
1381 static void s_mips_weakext (int);
1382 static void s_mips_file (int);
1383 static void s_mips_loc (int);
1384 static bfd_boolean
pic_need_relax (symbolS
*);
1385 static int relaxed_branch_length (fragS
*, asection
*, int);
1386 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1387 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1388 static void file_mips_check_options (void);
1390 /* Table and functions used to map between CPU/ISA names, and
1391 ISA levels, and CPU numbers. */
1393 struct mips_cpu_info
1395 const char *name
; /* CPU or ISA name. */
1396 int flags
; /* MIPS_CPU_* flags. */
1397 int ase
; /* Set of ASEs implemented by the CPU. */
1398 int isa
; /* ISA level. */
1399 int cpu
; /* CPU number (default CPU if ISA). */
1402 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1404 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1405 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1406 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1408 /* Command-line options. */
1409 const char *md_shortopts
= "O::g::G:";
1413 OPTION_MARCH
= OPTION_MD_BASE
,
1445 OPTION_NO_SMARTMIPS
,
1455 OPTION_NO_MICROMIPS
,
1458 OPTION_COMPAT_ARCH_BASE
,
1467 OPTION_M7000_HILO_FIX
,
1468 OPTION_MNO_7000_HILO_FIX
,
1472 OPTION_NO_FIX_RM7000
,
1473 OPTION_FIX_LOONGSON2F_JUMP
,
1474 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1475 OPTION_FIX_LOONGSON2F_NOP
,
1476 OPTION_NO_FIX_LOONGSON2F_NOP
,
1478 OPTION_NO_FIX_VR4120
,
1480 OPTION_NO_FIX_VR4130
,
1481 OPTION_FIX_CN63XXP1
,
1482 OPTION_NO_FIX_CN63XXP1
,
1489 OPTION_CONSTRUCT_FLOATS
,
1490 OPTION_NO_CONSTRUCT_FLOATS
,
1494 OPTION_RELAX_BRANCH
,
1495 OPTION_NO_RELAX_BRANCH
,
1496 OPTION_IGNORE_BRANCH_ISA
,
1497 OPTION_NO_IGNORE_BRANCH_ISA
,
1506 OPTION_SINGLE_FLOAT
,
1507 OPTION_DOUBLE_FLOAT
,
1520 OPTION_MVXWORKS_PIC
,
1523 OPTION_NO_ODD_SPREG
,
1527 struct option md_longopts
[] =
1529 /* Options which specify architecture. */
1530 {"march", required_argument
, NULL
, OPTION_MARCH
},
1531 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1532 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1533 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1534 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1535 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1536 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1537 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1538 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1539 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1540 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1541 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1542 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1543 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1544 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1545 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1546 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1547 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1549 /* Options which specify Application Specific Extensions (ASEs). */
1550 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1551 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1552 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1553 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1554 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1555 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1556 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1557 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1558 {"mmt", no_argument
, NULL
, OPTION_MT
},
1559 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1560 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1561 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1562 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1563 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1564 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1565 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1566 {"meva", no_argument
, NULL
, OPTION_EVA
},
1567 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1568 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1569 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1570 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1571 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1572 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1573 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1574 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1575 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1576 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1577 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1579 /* Old-style architecture options. Don't add more of these. */
1580 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1581 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1582 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1583 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1584 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1585 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1586 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1587 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1589 /* Options which enable bug fixes. */
1590 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1591 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1592 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1593 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1594 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1595 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1596 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1597 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1598 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1599 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1600 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1601 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1602 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1603 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1604 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1605 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1606 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1608 /* Miscellaneous options. */
1609 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1610 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1611 {"break", no_argument
, NULL
, OPTION_BREAK
},
1612 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1613 {"EB", no_argument
, NULL
, OPTION_EB
},
1614 {"EL", no_argument
, NULL
, OPTION_EL
},
1615 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1616 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1617 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1618 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1619 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1620 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1621 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1622 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1623 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1624 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1625 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1626 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1627 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1628 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1629 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1630 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1631 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1632 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1633 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1634 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1635 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1636 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1637 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1639 /* Strictly speaking this next option is ELF specific,
1640 but we allow it for other ports as well in order to
1641 make testing easier. */
1642 {"32", no_argument
, NULL
, OPTION_32
},
1644 /* ELF-specific options. */
1645 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1646 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1647 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1648 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1649 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1650 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1651 {"n32", no_argument
, NULL
, OPTION_N32
},
1652 {"64", no_argument
, NULL
, OPTION_64
},
1653 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1654 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1655 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1656 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1657 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1658 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1660 {NULL
, no_argument
, NULL
, 0}
1662 size_t md_longopts_size
= sizeof (md_longopts
);
1664 /* Information about either an Application Specific Extension or an
1665 optional architecture feature that, for simplicity, we treat in the
1666 same way as an ASE. */
1669 /* The name of the ASE, used in both the command-line and .set options. */
1672 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1673 and 64-bit architectures, the flags here refer to the subset that
1674 is available on both. */
1677 /* The ASE_* flag used for instructions that are available on 64-bit
1678 architectures but that are not included in FLAGS. */
1679 unsigned int flags64
;
1681 /* The command-line options that turn the ASE on and off. */
1685 /* The minimum required architecture revisions for MIPS32, MIPS64,
1686 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1689 int micromips32_rev
;
1690 int micromips64_rev
;
1692 /* The architecture where the ASE was removed or -1 if the extension has not
1697 /* A table of all supported ASEs. */
1698 static const struct mips_ase mips_ases
[] = {
1699 { "dsp", ASE_DSP
, ASE_DSP64
,
1700 OPTION_DSP
, OPTION_NO_DSP
,
1704 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1705 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1709 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1710 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1714 { "eva", ASE_EVA
, 0,
1715 OPTION_EVA
, OPTION_NO_EVA
,
1719 { "mcu", ASE_MCU
, 0,
1720 OPTION_MCU
, OPTION_NO_MCU
,
1724 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1725 { "mdmx", ASE_MDMX
, 0,
1726 OPTION_MDMX
, OPTION_NO_MDMX
,
1730 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1731 { "mips3d", ASE_MIPS3D
, 0,
1732 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1737 OPTION_MT
, OPTION_NO_MT
,
1741 { "smartmips", ASE_SMARTMIPS
, 0,
1742 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1746 { "virt", ASE_VIRT
, ASE_VIRT64
,
1747 OPTION_VIRT
, OPTION_NO_VIRT
,
1751 { "msa", ASE_MSA
, ASE_MSA64
,
1752 OPTION_MSA
, OPTION_NO_MSA
,
1756 { "xpa", ASE_XPA
, 0,
1757 OPTION_XPA
, OPTION_NO_XPA
,
1762 /* The set of ASEs that require -mfp64. */
1763 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1765 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1766 static const unsigned int mips_ase_groups
[] = {
1767 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1772 The following pseudo-ops from the Kane and Heinrich MIPS book
1773 should be defined here, but are currently unsupported: .alias,
1774 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1776 The following pseudo-ops from the Kane and Heinrich MIPS book are
1777 specific to the type of debugging information being generated, and
1778 should be defined by the object format: .aent, .begin, .bend,
1779 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1782 The following pseudo-ops from the Kane and Heinrich MIPS book are
1783 not MIPS CPU specific, but are also not specific to the object file
1784 format. This file is probably the best place to define them, but
1785 they are not currently supported: .asm0, .endr, .lab, .struct. */
1787 static const pseudo_typeS mips_pseudo_table
[] =
1789 /* MIPS specific pseudo-ops. */
1790 {"option", s_option
, 0},
1791 {"set", s_mipsset
, 0},
1792 {"rdata", s_change_sec
, 'r'},
1793 {"sdata", s_change_sec
, 's'},
1794 {"livereg", s_ignore
, 0},
1795 {"abicalls", s_abicalls
, 0},
1796 {"cpload", s_cpload
, 0},
1797 {"cpsetup", s_cpsetup
, 0},
1798 {"cplocal", s_cplocal
, 0},
1799 {"cprestore", s_cprestore
, 0},
1800 {"cpreturn", s_cpreturn
, 0},
1801 {"dtprelword", s_dtprelword
, 0},
1802 {"dtpreldword", s_dtpreldword
, 0},
1803 {"tprelword", s_tprelword
, 0},
1804 {"tpreldword", s_tpreldword
, 0},
1805 {"gpvalue", s_gpvalue
, 0},
1806 {"gpword", s_gpword
, 0},
1807 {"gpdword", s_gpdword
, 0},
1808 {"ehword", s_ehword
, 0},
1809 {"cpadd", s_cpadd
, 0},
1810 {"insn", s_insn
, 0},
1812 {"module", s_module
, 0},
1814 /* Relatively generic pseudo-ops that happen to be used on MIPS
1816 {"asciiz", stringer
, 8 + 1},
1817 {"bss", s_change_sec
, 'b'},
1819 {"half", s_cons
, 1},
1820 {"dword", s_cons
, 3},
1821 {"weakext", s_mips_weakext
, 0},
1822 {"origin", s_org
, 0},
1823 {"repeat", s_rept
, 0},
1825 /* For MIPS this is non-standard, but we define it for consistency. */
1826 {"sbss", s_change_sec
, 'B'},
1828 /* These pseudo-ops are defined in read.c, but must be overridden
1829 here for one reason or another. */
1830 {"align", s_align
, 0},
1831 {"byte", s_cons
, 0},
1832 {"data", s_change_sec
, 'd'},
1833 {"double", s_float_cons
, 'd'},
1834 {"float", s_float_cons
, 'f'},
1835 {"globl", s_mips_globl
, 0},
1836 {"global", s_mips_globl
, 0},
1837 {"hword", s_cons
, 1},
1839 {"long", s_cons
, 2},
1840 {"octa", s_cons
, 4},
1841 {"quad", s_cons
, 3},
1842 {"section", s_change_section
, 0},
1843 {"short", s_cons
, 1},
1844 {"single", s_float_cons
, 'f'},
1845 {"stabd", s_mips_stab
, 'd'},
1846 {"stabn", s_mips_stab
, 'n'},
1847 {"stabs", s_mips_stab
, 's'},
1848 {"text", s_change_sec
, 't'},
1849 {"word", s_cons
, 2},
1851 { "extern", ecoff_directive_extern
, 0},
1856 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1858 /* These pseudo-ops should be defined by the object file format.
1859 However, a.out doesn't support them, so we have versions here. */
1860 {"aent", s_mips_ent
, 1},
1861 {"bgnb", s_ignore
, 0},
1862 {"end", s_mips_end
, 0},
1863 {"endb", s_ignore
, 0},
1864 {"ent", s_mips_ent
, 0},
1865 {"file", s_mips_file
, 0},
1866 {"fmask", s_mips_mask
, 'F'},
1867 {"frame", s_mips_frame
, 0},
1868 {"loc", s_mips_loc
, 0},
1869 {"mask", s_mips_mask
, 'R'},
1870 {"verstamp", s_ignore
, 0},
1874 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1875 purpose of the `.dc.a' internal pseudo-op. */
1878 mips_address_bytes (void)
1880 file_mips_check_options ();
1881 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1884 extern void pop_insert (const pseudo_typeS
*);
1887 mips_pop_insert (void)
1889 pop_insert (mips_pseudo_table
);
1890 if (! ECOFF_DEBUGGING
)
1891 pop_insert (mips_nonecoff_pseudo_table
);
1894 /* Symbols labelling the current insn. */
1896 struct insn_label_list
1898 struct insn_label_list
*next
;
1902 static struct insn_label_list
*free_insn_labels
;
1903 #define label_list tc_segment_info_data.labels
1905 static void mips_clear_insn_labels (void);
1906 static void mips_mark_labels (void);
1907 static void mips_compressed_mark_labels (void);
1910 mips_clear_insn_labels (void)
1912 struct insn_label_list
**pl
;
1913 segment_info_type
*si
;
1917 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1920 si
= seg_info (now_seg
);
1921 *pl
= si
->label_list
;
1922 si
->label_list
= NULL
;
1926 /* Mark instruction labels in MIPS16/microMIPS mode. */
1929 mips_mark_labels (void)
1931 if (HAVE_CODE_COMPRESSION
)
1932 mips_compressed_mark_labels ();
1935 static char *expr_end
;
1937 /* An expression in a macro instruction. This is set by mips_ip and
1938 mips16_ip and when populated is always an O_constant. */
1940 static expressionS imm_expr
;
1942 /* The relocatable field in an instruction and the relocs associated
1943 with it. These variables are used for instructions like LUI and
1944 JAL as well as true offsets. They are also used for address
1945 operands in macros. */
1947 static expressionS offset_expr
;
1948 static bfd_reloc_code_real_type offset_reloc
[3]
1949 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1951 /* This is set to the resulting size of the instruction to be produced
1952 by mips16_ip if an explicit extension is used or by mips_ip if an
1953 explicit size is supplied. */
1955 static unsigned int forced_insn_length
;
1957 /* True if we are assembling an instruction. All dot symbols defined during
1958 this time should be treated as code labels. */
1960 static bfd_boolean mips_assembling_insn
;
1962 /* The pdr segment for per procedure frame/regmask info. Not used for
1965 static segT pdr_seg
;
1967 /* The default target format to use. */
1969 #if defined (TE_FreeBSD)
1970 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1971 #elif defined (TE_TMIPS)
1972 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1974 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1978 mips_target_format (void)
1980 switch (OUTPUT_FLAVOR
)
1982 case bfd_target_elf_flavour
:
1984 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1985 return (target_big_endian
1986 ? "elf32-bigmips-vxworks"
1987 : "elf32-littlemips-vxworks");
1989 return (target_big_endian
1990 ? (HAVE_64BIT_OBJECTS
1991 ? ELF_TARGET ("elf64-", "big")
1993 ? ELF_TARGET ("elf32-n", "big")
1994 : ELF_TARGET ("elf32-", "big")))
1995 : (HAVE_64BIT_OBJECTS
1996 ? ELF_TARGET ("elf64-", "little")
1998 ? ELF_TARGET ("elf32-n", "little")
1999 : ELF_TARGET ("elf32-", "little"))));
2006 /* Return the ISA revision that is currently in use, or 0 if we are
2007 generating code for MIPS V or below. */
2012 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2015 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2018 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2021 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2024 /* microMIPS implies revision 2 or above. */
2025 if (mips_opts
.micromips
)
2028 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2034 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2037 mips_ase_mask (unsigned int flags
)
2041 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2042 if (flags
& mips_ase_groups
[i
])
2043 flags
|= mips_ase_groups
[i
];
2047 /* Check whether the current ISA supports ASE. Issue a warning if
2051 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2055 static unsigned int warned_isa
;
2056 static unsigned int warned_fp32
;
2058 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2059 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2061 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2062 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2063 && (warned_isa
& ase
->flags
) != ase
->flags
)
2065 warned_isa
|= ase
->flags
;
2066 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2067 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2069 as_warn (_("the %d-bit %s architecture does not support the"
2070 " `%s' extension"), size
, base
, ase
->name
);
2072 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2073 ase
->name
, base
, size
, min_rev
);
2075 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2076 && (warned_isa
& ase
->flags
) != ase
->flags
)
2078 warned_isa
|= ase
->flags
;
2079 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2080 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2081 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2082 ase
->name
, base
, size
, ase
->rem_rev
);
2085 if ((ase
->flags
& FP64_ASES
)
2086 && mips_opts
.fp
!= 64
2087 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2089 warned_fp32
|= ase
->flags
;
2090 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2094 /* Check all enabled ASEs to see whether they are supported by the
2095 chosen architecture. */
2098 mips_check_isa_supports_ases (void)
2100 unsigned int i
, mask
;
2102 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2104 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2105 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2106 mips_check_isa_supports_ase (&mips_ases
[i
]);
2110 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2111 that were affected. */
2114 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2115 bfd_boolean enabled_p
)
2119 mask
= mips_ase_mask (ase
->flags
);
2122 opts
->ase
|= ase
->flags
;
2126 /* Return the ASE called NAME, or null if none. */
2128 static const struct mips_ase
*
2129 mips_lookup_ase (const char *name
)
2133 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2134 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2135 return &mips_ases
[i
];
2139 /* Return the length of a microMIPS instruction in bytes. If bits of
2140 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2141 otherwise it is a 32-bit instruction. */
2143 static inline unsigned int
2144 micromips_insn_length (const struct mips_opcode
*mo
)
2146 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2149 /* Return the length of MIPS16 instruction OPCODE. */
2151 static inline unsigned int
2152 mips16_opcode_length (unsigned long opcode
)
2154 return (opcode
>> 16) == 0 ? 2 : 4;
2157 /* Return the length of instruction INSN. */
2159 static inline unsigned int
2160 insn_length (const struct mips_cl_insn
*insn
)
2162 if (mips_opts
.micromips
)
2163 return micromips_insn_length (insn
->insn_mo
);
2164 else if (mips_opts
.mips16
)
2165 return mips16_opcode_length (insn
->insn_opcode
);
2170 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2173 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2178 insn
->insn_opcode
= mo
->match
;
2181 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2182 insn
->fixp
[i
] = NULL
;
2183 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2184 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2185 insn
->mips16_absolute_jump_p
= 0;
2186 insn
->complete_p
= 0;
2187 insn
->cleared_p
= 0;
2190 /* Get a list of all the operands in INSN. */
2192 static const struct mips_operand_array
*
2193 insn_operands (const struct mips_cl_insn
*insn
)
2195 if (insn
->insn_mo
>= &mips_opcodes
[0]
2196 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2197 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2199 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2200 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2201 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2203 if (insn
->insn_mo
>= µmips_opcodes
[0]
2204 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2205 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2210 /* Get a description of operand OPNO of INSN. */
2212 static const struct mips_operand
*
2213 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2215 const struct mips_operand_array
*operands
;
2217 operands
= insn_operands (insn
);
2218 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2220 return operands
->operand
[opno
];
2223 /* Install UVAL as the value of OPERAND in INSN. */
2226 insn_insert_operand (struct mips_cl_insn
*insn
,
2227 const struct mips_operand
*operand
, unsigned int uval
)
2229 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2232 /* Extract the value of OPERAND from INSN. */
2234 static inline unsigned
2235 insn_extract_operand (const struct mips_cl_insn
*insn
,
2236 const struct mips_operand
*operand
)
2238 return mips_extract_operand (operand
, insn
->insn_opcode
);
2241 /* Record the current MIPS16/microMIPS mode in now_seg. */
2244 mips_record_compressed_mode (void)
2246 segment_info_type
*si
;
2248 si
= seg_info (now_seg
);
2249 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2250 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2251 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2252 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2255 /* Read a standard MIPS instruction from BUF. */
2257 static unsigned long
2258 read_insn (char *buf
)
2260 if (target_big_endian
)
2261 return bfd_getb32 ((bfd_byte
*) buf
);
2263 return bfd_getl32 ((bfd_byte
*) buf
);
2266 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2270 write_insn (char *buf
, unsigned int insn
)
2272 md_number_to_chars (buf
, insn
, 4);
2276 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2277 has length LENGTH. */
2279 static unsigned long
2280 read_compressed_insn (char *buf
, unsigned int length
)
2286 for (i
= 0; i
< length
; i
+= 2)
2289 if (target_big_endian
)
2290 insn
|= bfd_getb16 ((char *) buf
);
2292 insn
|= bfd_getl16 ((char *) buf
);
2298 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2299 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2302 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2306 for (i
= 0; i
< length
; i
+= 2)
2307 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2308 return buf
+ length
;
2311 /* Install INSN at the location specified by its "frag" and "where" fields. */
2314 install_insn (const struct mips_cl_insn
*insn
)
2316 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2317 if (HAVE_CODE_COMPRESSION
)
2318 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2320 write_insn (f
, insn
->insn_opcode
);
2321 mips_record_compressed_mode ();
2324 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2325 and install the opcode in the new location. */
2328 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2333 insn
->where
= where
;
2334 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2335 if (insn
->fixp
[i
] != NULL
)
2337 insn
->fixp
[i
]->fx_frag
= frag
;
2338 insn
->fixp
[i
]->fx_where
= where
;
2340 install_insn (insn
);
2343 /* Add INSN to the end of the output. */
2346 add_fixed_insn (struct mips_cl_insn
*insn
)
2348 char *f
= frag_more (insn_length (insn
));
2349 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2352 /* Start a variant frag and move INSN to the start of the variant part,
2353 marking it as fixed. The other arguments are as for frag_var. */
2356 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2357 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2359 frag_grow (max_chars
);
2360 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2362 frag_var (rs_machine_dependent
, max_chars
, var
,
2363 subtype
, symbol
, offset
, NULL
);
2366 /* Insert N copies of INSN into the history buffer, starting at
2367 position FIRST. Neither FIRST nor N need to be clipped. */
2370 insert_into_history (unsigned int first
, unsigned int n
,
2371 const struct mips_cl_insn
*insn
)
2373 if (mips_relax
.sequence
!= 2)
2377 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2379 history
[i
] = history
[i
- n
];
2385 /* Clear the error in insn_error. */
2388 clear_insn_error (void)
2390 memset (&insn_error
, 0, sizeof (insn_error
));
2393 /* Possibly record error message MSG for the current instruction.
2394 If the error is about a particular argument, ARGNUM is the 1-based
2395 number of that argument, otherwise it is 0. FORMAT is the format
2396 of MSG. Return true if MSG was used, false if the current message
2400 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2405 /* Give priority to errors against specific arguments, and to
2406 the first whole-instruction message. */
2412 /* Keep insn_error if it is against a later argument. */
2413 if (argnum
< insn_error
.min_argnum
)
2416 /* If both errors are against the same argument but are different,
2417 give up on reporting a specific error for this argument.
2418 See the comment about mips_insn_error for details. */
2419 if (argnum
== insn_error
.min_argnum
2421 && strcmp (insn_error
.msg
, msg
) != 0)
2424 insn_error
.min_argnum
+= 1;
2428 insn_error
.min_argnum
= argnum
;
2429 insn_error
.format
= format
;
2430 insn_error
.msg
= msg
;
2434 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2435 as for set_insn_error_format. */
2438 set_insn_error (int argnum
, const char *msg
)
2440 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2443 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2444 as for set_insn_error_format. */
2447 set_insn_error_i (int argnum
, const char *msg
, int i
)
2449 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2453 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2454 are as for set_insn_error_format. */
2457 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2459 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2461 insn_error
.u
.ss
[0] = s1
;
2462 insn_error
.u
.ss
[1] = s2
;
2466 /* Report the error in insn_error, which is against assembly code STR. */
2469 report_insn_error (const char *str
)
2471 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2473 switch (insn_error
.format
)
2480 as_bad (msg
, insn_error
.u
.i
, str
);
2484 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2488 free ((char *) msg
);
2491 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2492 the idea is to make it obvious at a glance that each errata is
2496 init_vr4120_conflicts (void)
2498 #define CONFLICT(FIRST, SECOND) \
2499 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2501 /* Errata 21 - [D]DIV[U] after [D]MACC */
2502 CONFLICT (MACC
, DIV
);
2503 CONFLICT (DMACC
, DIV
);
2505 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2506 CONFLICT (DMULT
, DMULT
);
2507 CONFLICT (DMULT
, DMACC
);
2508 CONFLICT (DMACC
, DMULT
);
2509 CONFLICT (DMACC
, DMACC
);
2511 /* Errata 24 - MT{LO,HI} after [D]MACC */
2512 CONFLICT (MACC
, MTHILO
);
2513 CONFLICT (DMACC
, MTHILO
);
2515 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2516 instruction is executed immediately after a MACC or DMACC
2517 instruction, the result of [either instruction] is incorrect." */
2518 CONFLICT (MACC
, MULT
);
2519 CONFLICT (MACC
, DMULT
);
2520 CONFLICT (DMACC
, MULT
);
2521 CONFLICT (DMACC
, DMULT
);
2523 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2524 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2525 DDIV or DDIVU instruction, the result of the MACC or
2526 DMACC instruction is incorrect.". */
2527 CONFLICT (DMULT
, MACC
);
2528 CONFLICT (DMULT
, DMACC
);
2529 CONFLICT (DIV
, MACC
);
2530 CONFLICT (DIV
, DMACC
);
2540 #define RNUM_MASK 0x00000ff
2541 #define RTYPE_MASK 0x0ffff00
2542 #define RTYPE_NUM 0x0000100
2543 #define RTYPE_FPU 0x0000200
2544 #define RTYPE_FCC 0x0000400
2545 #define RTYPE_VEC 0x0000800
2546 #define RTYPE_GP 0x0001000
2547 #define RTYPE_CP0 0x0002000
2548 #define RTYPE_PC 0x0004000
2549 #define RTYPE_ACC 0x0008000
2550 #define RTYPE_CCC 0x0010000
2551 #define RTYPE_VI 0x0020000
2552 #define RTYPE_VF 0x0040000
2553 #define RTYPE_R5900_I 0x0080000
2554 #define RTYPE_R5900_Q 0x0100000
2555 #define RTYPE_R5900_R 0x0200000
2556 #define RTYPE_R5900_ACC 0x0400000
2557 #define RTYPE_MSA 0x0800000
2558 #define RWARN 0x8000000
2560 #define GENERIC_REGISTER_NUMBERS \
2561 {"$0", RTYPE_NUM | 0}, \
2562 {"$1", RTYPE_NUM | 1}, \
2563 {"$2", RTYPE_NUM | 2}, \
2564 {"$3", RTYPE_NUM | 3}, \
2565 {"$4", RTYPE_NUM | 4}, \
2566 {"$5", RTYPE_NUM | 5}, \
2567 {"$6", RTYPE_NUM | 6}, \
2568 {"$7", RTYPE_NUM | 7}, \
2569 {"$8", RTYPE_NUM | 8}, \
2570 {"$9", RTYPE_NUM | 9}, \
2571 {"$10", RTYPE_NUM | 10}, \
2572 {"$11", RTYPE_NUM | 11}, \
2573 {"$12", RTYPE_NUM | 12}, \
2574 {"$13", RTYPE_NUM | 13}, \
2575 {"$14", RTYPE_NUM | 14}, \
2576 {"$15", RTYPE_NUM | 15}, \
2577 {"$16", RTYPE_NUM | 16}, \
2578 {"$17", RTYPE_NUM | 17}, \
2579 {"$18", RTYPE_NUM | 18}, \
2580 {"$19", RTYPE_NUM | 19}, \
2581 {"$20", RTYPE_NUM | 20}, \
2582 {"$21", RTYPE_NUM | 21}, \
2583 {"$22", RTYPE_NUM | 22}, \
2584 {"$23", RTYPE_NUM | 23}, \
2585 {"$24", RTYPE_NUM | 24}, \
2586 {"$25", RTYPE_NUM | 25}, \
2587 {"$26", RTYPE_NUM | 26}, \
2588 {"$27", RTYPE_NUM | 27}, \
2589 {"$28", RTYPE_NUM | 28}, \
2590 {"$29", RTYPE_NUM | 29}, \
2591 {"$30", RTYPE_NUM | 30}, \
2592 {"$31", RTYPE_NUM | 31}
2594 #define FPU_REGISTER_NAMES \
2595 {"$f0", RTYPE_FPU | 0}, \
2596 {"$f1", RTYPE_FPU | 1}, \
2597 {"$f2", RTYPE_FPU | 2}, \
2598 {"$f3", RTYPE_FPU | 3}, \
2599 {"$f4", RTYPE_FPU | 4}, \
2600 {"$f5", RTYPE_FPU | 5}, \
2601 {"$f6", RTYPE_FPU | 6}, \
2602 {"$f7", RTYPE_FPU | 7}, \
2603 {"$f8", RTYPE_FPU | 8}, \
2604 {"$f9", RTYPE_FPU | 9}, \
2605 {"$f10", RTYPE_FPU | 10}, \
2606 {"$f11", RTYPE_FPU | 11}, \
2607 {"$f12", RTYPE_FPU | 12}, \
2608 {"$f13", RTYPE_FPU | 13}, \
2609 {"$f14", RTYPE_FPU | 14}, \
2610 {"$f15", RTYPE_FPU | 15}, \
2611 {"$f16", RTYPE_FPU | 16}, \
2612 {"$f17", RTYPE_FPU | 17}, \
2613 {"$f18", RTYPE_FPU | 18}, \
2614 {"$f19", RTYPE_FPU | 19}, \
2615 {"$f20", RTYPE_FPU | 20}, \
2616 {"$f21", RTYPE_FPU | 21}, \
2617 {"$f22", RTYPE_FPU | 22}, \
2618 {"$f23", RTYPE_FPU | 23}, \
2619 {"$f24", RTYPE_FPU | 24}, \
2620 {"$f25", RTYPE_FPU | 25}, \
2621 {"$f26", RTYPE_FPU | 26}, \
2622 {"$f27", RTYPE_FPU | 27}, \
2623 {"$f28", RTYPE_FPU | 28}, \
2624 {"$f29", RTYPE_FPU | 29}, \
2625 {"$f30", RTYPE_FPU | 30}, \
2626 {"$f31", RTYPE_FPU | 31}
2628 #define FPU_CONDITION_CODE_NAMES \
2629 {"$fcc0", RTYPE_FCC | 0}, \
2630 {"$fcc1", RTYPE_FCC | 1}, \
2631 {"$fcc2", RTYPE_FCC | 2}, \
2632 {"$fcc3", RTYPE_FCC | 3}, \
2633 {"$fcc4", RTYPE_FCC | 4}, \
2634 {"$fcc5", RTYPE_FCC | 5}, \
2635 {"$fcc6", RTYPE_FCC | 6}, \
2636 {"$fcc7", RTYPE_FCC | 7}
2638 #define COPROC_CONDITION_CODE_NAMES \
2639 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2640 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2641 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2642 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2643 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2644 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2645 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2646 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2648 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2649 {"$a4", RTYPE_GP | 8}, \
2650 {"$a5", RTYPE_GP | 9}, \
2651 {"$a6", RTYPE_GP | 10}, \
2652 {"$a7", RTYPE_GP | 11}, \
2653 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2654 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2655 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2656 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2657 {"$t0", RTYPE_GP | 12}, \
2658 {"$t1", RTYPE_GP | 13}, \
2659 {"$t2", RTYPE_GP | 14}, \
2660 {"$t3", RTYPE_GP | 15}
2662 #define O32_SYMBOLIC_REGISTER_NAMES \
2663 {"$t0", RTYPE_GP | 8}, \
2664 {"$t1", RTYPE_GP | 9}, \
2665 {"$t2", RTYPE_GP | 10}, \
2666 {"$t3", RTYPE_GP | 11}, \
2667 {"$t4", RTYPE_GP | 12}, \
2668 {"$t5", RTYPE_GP | 13}, \
2669 {"$t6", RTYPE_GP | 14}, \
2670 {"$t7", RTYPE_GP | 15}, \
2671 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2672 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2673 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2674 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2676 /* Remaining symbolic register names */
2677 #define SYMBOLIC_REGISTER_NAMES \
2678 {"$zero", RTYPE_GP | 0}, \
2679 {"$at", RTYPE_GP | 1}, \
2680 {"$AT", RTYPE_GP | 1}, \
2681 {"$v0", RTYPE_GP | 2}, \
2682 {"$v1", RTYPE_GP | 3}, \
2683 {"$a0", RTYPE_GP | 4}, \
2684 {"$a1", RTYPE_GP | 5}, \
2685 {"$a2", RTYPE_GP | 6}, \
2686 {"$a3", RTYPE_GP | 7}, \
2687 {"$s0", RTYPE_GP | 16}, \
2688 {"$s1", RTYPE_GP | 17}, \
2689 {"$s2", RTYPE_GP | 18}, \
2690 {"$s3", RTYPE_GP | 19}, \
2691 {"$s4", RTYPE_GP | 20}, \
2692 {"$s5", RTYPE_GP | 21}, \
2693 {"$s6", RTYPE_GP | 22}, \
2694 {"$s7", RTYPE_GP | 23}, \
2695 {"$t8", RTYPE_GP | 24}, \
2696 {"$t9", RTYPE_GP | 25}, \
2697 {"$k0", RTYPE_GP | 26}, \
2698 {"$kt0", RTYPE_GP | 26}, \
2699 {"$k1", RTYPE_GP | 27}, \
2700 {"$kt1", RTYPE_GP | 27}, \
2701 {"$gp", RTYPE_GP | 28}, \
2702 {"$sp", RTYPE_GP | 29}, \
2703 {"$s8", RTYPE_GP | 30}, \
2704 {"$fp", RTYPE_GP | 30}, \
2705 {"$ra", RTYPE_GP | 31}
2707 #define MIPS16_SPECIAL_REGISTER_NAMES \
2708 {"$pc", RTYPE_PC | 0}
2710 #define MDMX_VECTOR_REGISTER_NAMES \
2711 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2712 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2713 {"$v2", RTYPE_VEC | 2}, \
2714 {"$v3", RTYPE_VEC | 3}, \
2715 {"$v4", RTYPE_VEC | 4}, \
2716 {"$v5", RTYPE_VEC | 5}, \
2717 {"$v6", RTYPE_VEC | 6}, \
2718 {"$v7", RTYPE_VEC | 7}, \
2719 {"$v8", RTYPE_VEC | 8}, \
2720 {"$v9", RTYPE_VEC | 9}, \
2721 {"$v10", RTYPE_VEC | 10}, \
2722 {"$v11", RTYPE_VEC | 11}, \
2723 {"$v12", RTYPE_VEC | 12}, \
2724 {"$v13", RTYPE_VEC | 13}, \
2725 {"$v14", RTYPE_VEC | 14}, \
2726 {"$v15", RTYPE_VEC | 15}, \
2727 {"$v16", RTYPE_VEC | 16}, \
2728 {"$v17", RTYPE_VEC | 17}, \
2729 {"$v18", RTYPE_VEC | 18}, \
2730 {"$v19", RTYPE_VEC | 19}, \
2731 {"$v20", RTYPE_VEC | 20}, \
2732 {"$v21", RTYPE_VEC | 21}, \
2733 {"$v22", RTYPE_VEC | 22}, \
2734 {"$v23", RTYPE_VEC | 23}, \
2735 {"$v24", RTYPE_VEC | 24}, \
2736 {"$v25", RTYPE_VEC | 25}, \
2737 {"$v26", RTYPE_VEC | 26}, \
2738 {"$v27", RTYPE_VEC | 27}, \
2739 {"$v28", RTYPE_VEC | 28}, \
2740 {"$v29", RTYPE_VEC | 29}, \
2741 {"$v30", RTYPE_VEC | 30}, \
2742 {"$v31", RTYPE_VEC | 31}
2744 #define R5900_I_NAMES \
2745 {"$I", RTYPE_R5900_I | 0}
2747 #define R5900_Q_NAMES \
2748 {"$Q", RTYPE_R5900_Q | 0}
2750 #define R5900_R_NAMES \
2751 {"$R", RTYPE_R5900_R | 0}
2753 #define R5900_ACC_NAMES \
2754 {"$ACC", RTYPE_R5900_ACC | 0 }
2756 #define MIPS_DSP_ACCUMULATOR_NAMES \
2757 {"$ac0", RTYPE_ACC | 0}, \
2758 {"$ac1", RTYPE_ACC | 1}, \
2759 {"$ac2", RTYPE_ACC | 2}, \
2760 {"$ac3", RTYPE_ACC | 3}
2762 static const struct regname reg_names
[] = {
2763 GENERIC_REGISTER_NUMBERS
,
2765 FPU_CONDITION_CODE_NAMES
,
2766 COPROC_CONDITION_CODE_NAMES
,
2768 /* The $txx registers depends on the abi,
2769 these will be added later into the symbol table from
2770 one of the tables below once mips_abi is set after
2771 parsing of arguments from the command line. */
2772 SYMBOLIC_REGISTER_NAMES
,
2774 MIPS16_SPECIAL_REGISTER_NAMES
,
2775 MDMX_VECTOR_REGISTER_NAMES
,
2780 MIPS_DSP_ACCUMULATOR_NAMES
,
2784 static const struct regname reg_names_o32
[] = {
2785 O32_SYMBOLIC_REGISTER_NAMES
,
2789 static const struct regname reg_names_n32n64
[] = {
2790 N32N64_SYMBOLIC_REGISTER_NAMES
,
2794 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2795 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2796 of these register symbols, return the associated vector register,
2797 otherwise return SYMVAL itself. */
2800 mips_prefer_vec_regno (unsigned int symval
)
2802 if ((symval
& -2) == (RTYPE_GP
| 2))
2803 return RTYPE_VEC
| (symval
& 1);
2807 /* Return true if string [S, E) is a valid register name, storing its
2808 symbol value in *SYMVAL_PTR if so. */
2811 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2816 /* Terminate name. */
2820 /* Look up the name. */
2821 symbol
= symbol_find (s
);
2824 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2827 *symval_ptr
= S_GET_VALUE (symbol
);
2831 /* Return true if the string at *SPTR is a valid register name. Allow it
2832 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2835 When returning true, move *SPTR past the register, store the
2836 register's symbol value in *SYMVAL_PTR and the channel mask in
2837 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2838 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2839 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2842 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2843 unsigned int *channels_ptr
)
2847 unsigned int channels
, symval
, bit
;
2849 /* Find end of name. */
2851 if (is_name_beginner (*e
))
2853 while (is_part_of_name (*e
))
2857 if (!mips_parse_register_1 (s
, e
, &symval
))
2862 /* Eat characters from the end of the string that are valid
2863 channel suffixes. The preceding register must be $ACC or
2864 end with a digit, so there is no ambiguity. */
2867 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2868 if (m
> s
&& m
[-1] == *q
)
2875 || !mips_parse_register_1 (s
, m
, &symval
)
2876 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2881 *symval_ptr
= symval
;
2883 *channels_ptr
= channels
;
2887 /* Check if SPTR points at a valid register specifier according to TYPES.
2888 If so, then return 1, advance S to consume the specifier and store
2889 the register's number in REGNOP, otherwise return 0. */
2892 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2896 if (mips_parse_register (s
, ®no
, NULL
))
2898 if (types
& RTYPE_VEC
)
2899 regno
= mips_prefer_vec_regno (regno
);
2908 as_warn (_("unrecognized register name `%s'"), *s
);
2913 return regno
<= RNUM_MASK
;
2916 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2917 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2920 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2925 for (i
= 0; i
< 4; i
++)
2926 if (*s
== "xyzw"[i
])
2928 *channels
|= 1 << (3 - i
);
2934 /* Token types for parsed operand lists. */
2935 enum mips_operand_token_type
{
2936 /* A plain register, e.g. $f2. */
2939 /* A 4-bit XYZW channel mask. */
2942 /* A constant vector index, e.g. [1]. */
2945 /* A register vector index, e.g. [$2]. */
2948 /* A continuous range of registers, e.g. $s0-$s4. */
2951 /* A (possibly relocated) expression. */
2954 /* A floating-point value. */
2957 /* A single character. This can be '(', ')' or ',', but '(' only appears
2961 /* A doubled character, either "--" or "++". */
2964 /* The end of the operand list. */
2968 /* A parsed operand token. */
2969 struct mips_operand_token
2971 /* The type of token. */
2972 enum mips_operand_token_type type
;
2975 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2978 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2979 unsigned int channels
;
2981 /* The integer value of an OT_INTEGER_INDEX. */
2984 /* The two register symbol values involved in an OT_REG_RANGE. */
2986 unsigned int regno1
;
2987 unsigned int regno2
;
2990 /* The value of an OT_INTEGER. The value is represented as an
2991 expression and the relocation operators that were applied to
2992 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2993 relocation operators were used. */
2996 bfd_reloc_code_real_type relocs
[3];
2999 /* The binary data for an OT_FLOAT constant, and the number of bytes
3002 unsigned char data
[8];
3006 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3011 /* An obstack used to construct lists of mips_operand_tokens. */
3012 static struct obstack mips_operand_tokens
;
3014 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3017 mips_add_token (struct mips_operand_token
*token
,
3018 enum mips_operand_token_type type
)
3021 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3024 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3025 and OT_REG tokens for them if so, and return a pointer to the first
3026 unconsumed character. Return null otherwise. */
3029 mips_parse_base_start (char *s
)
3031 struct mips_operand_token token
;
3032 unsigned int regno
, channels
;
3033 bfd_boolean decrement_p
;
3039 SKIP_SPACE_TABS (s
);
3041 /* Only match "--" as part of a base expression. In other contexts "--X"
3042 is a double negative. */
3043 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3047 SKIP_SPACE_TABS (s
);
3050 /* Allow a channel specifier because that leads to better error messages
3051 than treating something like "$vf0x++" as an expression. */
3052 if (!mips_parse_register (&s
, ®no
, &channels
))
3056 mips_add_token (&token
, OT_CHAR
);
3061 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3064 token
.u
.regno
= regno
;
3065 mips_add_token (&token
, OT_REG
);
3069 token
.u
.channels
= channels
;
3070 mips_add_token (&token
, OT_CHANNELS
);
3073 /* For consistency, only match "++" as part of base expressions too. */
3074 SKIP_SPACE_TABS (s
);
3075 if (s
[0] == '+' && s
[1] == '+')
3079 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3085 /* Parse one or more tokens from S. Return a pointer to the first
3086 unconsumed character on success. Return null if an error was found
3087 and store the error text in insn_error. FLOAT_FORMAT is as for
3088 mips_parse_arguments. */
3091 mips_parse_argument_token (char *s
, char float_format
)
3093 char *end
, *save_in
;
3095 unsigned int regno1
, regno2
, channels
;
3096 struct mips_operand_token token
;
3098 /* First look for "($reg", since we want to treat that as an
3099 OT_CHAR and OT_REG rather than an expression. */
3100 end
= mips_parse_base_start (s
);
3104 /* Handle other characters that end up as OT_CHARs. */
3105 if (*s
== ')' || *s
== ',')
3108 mips_add_token (&token
, OT_CHAR
);
3113 /* Handle tokens that start with a register. */
3114 if (mips_parse_register (&s
, ®no1
, &channels
))
3118 /* A register and a VU0 channel suffix. */
3119 token
.u
.regno
= regno1
;
3120 mips_add_token (&token
, OT_REG
);
3122 token
.u
.channels
= channels
;
3123 mips_add_token (&token
, OT_CHANNELS
);
3127 SKIP_SPACE_TABS (s
);
3130 /* A register range. */
3132 SKIP_SPACE_TABS (s
);
3133 if (!mips_parse_register (&s
, ®no2
, NULL
))
3135 set_insn_error (0, _("invalid register range"));
3139 token
.u
.reg_range
.regno1
= regno1
;
3140 token
.u
.reg_range
.regno2
= regno2
;
3141 mips_add_token (&token
, OT_REG_RANGE
);
3145 /* Add the register itself. */
3146 token
.u
.regno
= regno1
;
3147 mips_add_token (&token
, OT_REG
);
3149 /* Check for a vector index. */
3153 SKIP_SPACE_TABS (s
);
3154 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3155 mips_add_token (&token
, OT_REG_INDEX
);
3158 expressionS element
;
3160 my_getExpression (&element
, s
);
3161 if (element
.X_op
!= O_constant
)
3163 set_insn_error (0, _("vector element must be constant"));
3167 token
.u
.index
= element
.X_add_number
;
3168 mips_add_token (&token
, OT_INTEGER_INDEX
);
3170 SKIP_SPACE_TABS (s
);
3173 set_insn_error (0, _("missing `]'"));
3183 /* First try to treat expressions as floats. */
3184 save_in
= input_line_pointer
;
3185 input_line_pointer
= s
;
3186 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3187 &token
.u
.flt
.length
);
3188 end
= input_line_pointer
;
3189 input_line_pointer
= save_in
;
3192 set_insn_error (0, err
);
3197 mips_add_token (&token
, OT_FLOAT
);
3202 /* Treat everything else as an integer expression. */
3203 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3204 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3205 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3206 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3208 mips_add_token (&token
, OT_INTEGER
);
3212 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3213 if expressions should be treated as 32-bit floating-point constants,
3214 'd' if they should be treated as 64-bit floating-point constants,
3215 or 0 if they should be treated as integer expressions (the usual case).
3217 Return a list of tokens on success, otherwise return 0. The caller
3218 must obstack_free the list after use. */
3220 static struct mips_operand_token
*
3221 mips_parse_arguments (char *s
, char float_format
)
3223 struct mips_operand_token token
;
3225 SKIP_SPACE_TABS (s
);
3228 s
= mips_parse_argument_token (s
, float_format
);
3231 obstack_free (&mips_operand_tokens
,
3232 obstack_finish (&mips_operand_tokens
));
3235 SKIP_SPACE_TABS (s
);
3237 mips_add_token (&token
, OT_END
);
3238 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3241 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3242 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3245 is_opcode_valid (const struct mips_opcode
*mo
)
3247 int isa
= mips_opts
.isa
;
3248 int ase
= mips_opts
.ase
;
3252 if (ISA_HAS_64BIT_REGS (isa
))
3253 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3254 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3255 ase
|= mips_ases
[i
].flags64
;
3257 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3260 /* Check whether the instruction or macro requires single-precision or
3261 double-precision floating-point support. Note that this information is
3262 stored differently in the opcode table for insns and macros. */
3263 if (mo
->pinfo
== INSN_MACRO
)
3265 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3266 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3270 fp_s
= mo
->pinfo
& FP_S
;
3271 fp_d
= mo
->pinfo
& FP_D
;
3274 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3277 if (fp_s
&& mips_opts
.soft_float
)
3283 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3284 selected ISA and architecture. */
3287 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3289 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3292 /* Return TRUE if the size of the microMIPS opcode MO matches one
3293 explicitly requested. Always TRUE in the standard MIPS mode.
3294 Use is_size_valid_16 for MIPS16 opcodes. */
3297 is_size_valid (const struct mips_opcode
*mo
)
3299 if (!mips_opts
.micromips
)
3302 if (mips_opts
.insn32
)
3304 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3306 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3309 if (!forced_insn_length
)
3311 if (mo
->pinfo
== INSN_MACRO
)
3313 return forced_insn_length
== micromips_insn_length (mo
);
3316 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3317 explicitly requested. */
3320 is_size_valid_16 (const struct mips_opcode
*mo
)
3322 if (!forced_insn_length
)
3324 if (mo
->pinfo
== INSN_MACRO
)
3326 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3328 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3333 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3334 of the preceding instruction. Always TRUE in the standard MIPS mode.
3336 We don't accept macros in 16-bit delay slots to avoid a case where
3337 a macro expansion fails because it relies on a preceding 32-bit real
3338 instruction to have matched and does not handle the operands correctly.
3339 The only macros that may expand to 16-bit instructions are JAL that
3340 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3341 and BGT (that likewise cannot be placed in a delay slot) that decay to
3342 a NOP. In all these cases the macros precede any corresponding real
3343 instruction definitions in the opcode table, so they will match in the
3344 second pass where the size of the delay slot is ignored and therefore
3345 produce correct code. */
3348 is_delay_slot_valid (const struct mips_opcode
*mo
)
3350 if (!mips_opts
.micromips
)
3353 if (mo
->pinfo
== INSN_MACRO
)
3354 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3355 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3356 && micromips_insn_length (mo
) != 4)
3358 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3359 && micromips_insn_length (mo
) != 2)
3365 /* For consistency checking, verify that all bits of OPCODE are specified
3366 either by the match/mask part of the instruction definition, or by the
3367 operand list. Also build up a list of operands in OPERANDS.
3369 INSN_BITS says which bits of the instruction are significant.
3370 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3371 provides the mips_operand description of each operand. DECODE_OPERAND
3372 is null for MIPS16 instructions. */
3375 validate_mips_insn (const struct mips_opcode
*opcode
,
3376 unsigned long insn_bits
,
3377 const struct mips_operand
*(*decode_operand
) (const char *),
3378 struct mips_operand_array
*operands
)
3381 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3382 const struct mips_operand
*operand
;
3384 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3385 if ((mask
& opcode
->match
) != opcode
->match
)
3387 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3388 opcode
->name
, opcode
->args
);
3393 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3394 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3395 for (s
= opcode
->args
; *s
; ++s
)
3408 if (!decode_operand
)
3409 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3411 operand
= decode_operand (s
);
3412 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3414 as_bad (_("internal: unknown operand type: %s %s"),
3415 opcode
->name
, opcode
->args
);
3418 gas_assert (opno
< MAX_OPERANDS
);
3419 operands
->operand
[opno
] = operand
;
3420 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3422 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3423 if (operand
->type
== OP_MDMX_IMM_REG
)
3424 /* Bit 5 is the format selector (OB vs QH). The opcode table
3425 has separate entries for each format. */
3426 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3427 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3428 used_bits
&= ~(mask
& 0x700);
3430 /* Skip prefix characters. */
3431 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3436 doubled
= used_bits
& mask
& insn_bits
;
3439 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3440 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3444 undefined
= ~used_bits
& insn_bits
;
3445 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3447 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3448 undefined
, opcode
->name
, opcode
->args
);
3451 used_bits
&= ~insn_bits
;
3454 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3455 used_bits
, opcode
->name
, opcode
->args
);
3461 /* The MIPS16 version of validate_mips_insn. */
3464 validate_mips16_insn (const struct mips_opcode
*opcode
,
3465 struct mips_operand_array
*operands
)
3467 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3469 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3472 /* The microMIPS version of validate_mips_insn. */
3475 validate_micromips_insn (const struct mips_opcode
*opc
,
3476 struct mips_operand_array
*operands
)
3478 unsigned long insn_bits
;
3479 unsigned long major
;
3480 unsigned int length
;
3482 if (opc
->pinfo
== INSN_MACRO
)
3483 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3486 length
= micromips_insn_length (opc
);
3487 if (length
!= 2 && length
!= 4)
3489 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3490 "%s %s"), length
, opc
->name
, opc
->args
);
3493 major
= opc
->match
>> (10 + 8 * (length
- 2));
3494 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3495 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3497 as_bad (_("internal error: bad microMIPS opcode "
3498 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3502 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3503 insn_bits
= 1 << 4 * length
;
3504 insn_bits
<<= 4 * length
;
3506 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3510 /* This function is called once, at assembler startup time. It should set up
3511 all the tables, etc. that the MD part of the assembler will need. */
3516 const char *retval
= NULL
;
3520 if (mips_pic
!= NO_PIC
)
3522 if (g_switch_seen
&& g_switch_value
!= 0)
3523 as_bad (_("-G may not be used in position-independent code"));
3526 else if (mips_abicalls
)
3528 if (g_switch_seen
&& g_switch_value
!= 0)
3529 as_bad (_("-G may not be used with abicalls"));
3533 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3534 as_warn (_("could not set architecture and machine"));
3536 op_hash
= hash_new ();
3538 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3539 for (i
= 0; i
< NUMOPCODES
;)
3541 const char *name
= mips_opcodes
[i
].name
;
3543 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3546 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3547 mips_opcodes
[i
].name
, retval
);
3548 /* Probably a memory allocation problem? Give up now. */
3549 as_fatal (_("broken assembler, no assembly attempted"));
3553 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3554 decode_mips_operand
, &mips_operands
[i
]))
3556 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3558 create_insn (&nop_insn
, mips_opcodes
+ i
);
3559 if (mips_fix_loongson2f_nop
)
3560 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3561 nop_insn
.fixed_p
= 1;
3565 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3568 mips16_op_hash
= hash_new ();
3569 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3570 bfd_mips16_num_opcodes
);
3573 while (i
< bfd_mips16_num_opcodes
)
3575 const char *name
= mips16_opcodes
[i
].name
;
3577 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3579 as_fatal (_("internal: can't hash `%s': %s"),
3580 mips16_opcodes
[i
].name
, retval
);
3583 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3585 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3587 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3588 mips16_nop_insn
.fixed_p
= 1;
3592 while (i
< bfd_mips16_num_opcodes
3593 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3596 micromips_op_hash
= hash_new ();
3597 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3598 bfd_micromips_num_opcodes
);
3601 while (i
< bfd_micromips_num_opcodes
)
3603 const char *name
= micromips_opcodes
[i
].name
;
3605 retval
= hash_insert (micromips_op_hash
, name
,
3606 (void *) µmips_opcodes
[i
]);
3608 as_fatal (_("internal: can't hash `%s': %s"),
3609 micromips_opcodes
[i
].name
, retval
);
3612 struct mips_cl_insn
*micromips_nop_insn
;
3614 if (!validate_micromips_insn (µmips_opcodes
[i
],
3615 µmips_operands
[i
]))
3618 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3620 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3621 micromips_nop_insn
= µmips_nop16_insn
;
3622 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3623 micromips_nop_insn
= µmips_nop32_insn
;
3627 if (micromips_nop_insn
->insn_mo
== NULL
3628 && strcmp (name
, "nop") == 0)
3630 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3631 micromips_nop_insn
->fixed_p
= 1;
3635 while (++i
< bfd_micromips_num_opcodes
3636 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3640 as_fatal (_("broken assembler, no assembly attempted"));
3642 /* We add all the general register names to the symbol table. This
3643 helps us detect invalid uses of them. */
3644 for (i
= 0; reg_names
[i
].name
; i
++)
3645 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3646 reg_names
[i
].num
, /* & RNUM_MASK, */
3647 &zero_address_frag
));
3649 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3650 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3651 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3652 &zero_address_frag
));
3654 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3655 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3656 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3657 &zero_address_frag
));
3659 for (i
= 0; i
< 32; i
++)
3663 /* R5900 VU0 floating-point register. */
3664 sprintf (regname
, "$vf%d", i
);
3665 symbol_table_insert (symbol_new (regname
, reg_section
,
3666 RTYPE_VF
| i
, &zero_address_frag
));
3668 /* R5900 VU0 integer register. */
3669 sprintf (regname
, "$vi%d", i
);
3670 symbol_table_insert (symbol_new (regname
, reg_section
,
3671 RTYPE_VI
| i
, &zero_address_frag
));
3674 sprintf (regname
, "$w%d", i
);
3675 symbol_table_insert (symbol_new (regname
, reg_section
,
3676 RTYPE_MSA
| i
, &zero_address_frag
));
3679 obstack_init (&mips_operand_tokens
);
3681 mips_no_prev_insn ();
3684 mips_cprmask
[0] = 0;
3685 mips_cprmask
[1] = 0;
3686 mips_cprmask
[2] = 0;
3687 mips_cprmask
[3] = 0;
3689 /* set the default alignment for the text section (2**2) */
3690 record_alignment (text_section
, 2);
3692 bfd_set_gp_size (stdoutput
, g_switch_value
);
3694 /* On a native system other than VxWorks, sections must be aligned
3695 to 16 byte boundaries. When configured for an embedded ELF
3696 target, we don't bother. */
3697 if (strncmp (TARGET_OS
, "elf", 3) != 0
3698 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3700 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3701 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3702 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3705 /* Create a .reginfo section for register masks and a .mdebug
3706 section for debugging information. */
3714 subseg
= now_subseg
;
3716 /* The ABI says this section should be loaded so that the
3717 running program can access it. However, we don't load it
3718 if we are configured for an embedded target */
3719 flags
= SEC_READONLY
| SEC_DATA
;
3720 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3721 flags
|= SEC_ALLOC
| SEC_LOAD
;
3723 if (mips_abi
!= N64_ABI
)
3725 sec
= subseg_new (".reginfo", (subsegT
) 0);
3727 bfd_set_section_flags (stdoutput
, sec
, flags
);
3728 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3730 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3734 /* The 64-bit ABI uses a .MIPS.options section rather than
3735 .reginfo section. */
3736 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3737 bfd_set_section_flags (stdoutput
, sec
, flags
);
3738 bfd_set_section_alignment (stdoutput
, sec
, 3);
3740 /* Set up the option header. */
3742 Elf_Internal_Options opthdr
;
3745 opthdr
.kind
= ODK_REGINFO
;
3746 opthdr
.size
= (sizeof (Elf_External_Options
)
3747 + sizeof (Elf64_External_RegInfo
));
3750 f
= frag_more (sizeof (Elf_External_Options
));
3751 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3752 (Elf_External_Options
*) f
);
3754 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3758 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3759 bfd_set_section_flags (stdoutput
, sec
,
3760 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3761 bfd_set_section_alignment (stdoutput
, sec
, 3);
3762 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3764 if (ECOFF_DEBUGGING
)
3766 sec
= subseg_new (".mdebug", (subsegT
) 0);
3767 (void) bfd_set_section_flags (stdoutput
, sec
,
3768 SEC_HAS_CONTENTS
| SEC_READONLY
);
3769 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3771 else if (mips_flag_pdr
)
3773 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3774 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3775 SEC_READONLY
| SEC_RELOC
3777 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3780 subseg_set (seg
, subseg
);
3783 if (mips_fix_vr4120
)
3784 init_vr4120_conflicts ();
3788 fpabi_incompatible_with (int fpabi
, const char *what
)
3790 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3791 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3795 fpabi_requires (int fpabi
, const char *what
)
3797 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3798 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3801 /* Check -mabi and register sizes against the specified FP ABI. */
3803 check_fpabi (int fpabi
)
3807 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3808 if (file_mips_opts
.soft_float
)
3809 fpabi_incompatible_with (fpabi
, "softfloat");
3810 else if (file_mips_opts
.single_float
)
3811 fpabi_incompatible_with (fpabi
, "singlefloat");
3812 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3813 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3814 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3815 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3818 case Val_GNU_MIPS_ABI_FP_XX
:
3819 if (mips_abi
!= O32_ABI
)
3820 fpabi_requires (fpabi
, "-mabi=32");
3821 else if (file_mips_opts
.soft_float
)
3822 fpabi_incompatible_with (fpabi
, "softfloat");
3823 else if (file_mips_opts
.single_float
)
3824 fpabi_incompatible_with (fpabi
, "singlefloat");
3825 else if (file_mips_opts
.fp
!= 0)
3826 fpabi_requires (fpabi
, "fp=xx");
3829 case Val_GNU_MIPS_ABI_FP_64A
:
3830 case Val_GNU_MIPS_ABI_FP_64
:
3831 if (mips_abi
!= O32_ABI
)
3832 fpabi_requires (fpabi
, "-mabi=32");
3833 else if (file_mips_opts
.soft_float
)
3834 fpabi_incompatible_with (fpabi
, "softfloat");
3835 else if (file_mips_opts
.single_float
)
3836 fpabi_incompatible_with (fpabi
, "singlefloat");
3837 else if (file_mips_opts
.fp
!= 64)
3838 fpabi_requires (fpabi
, "fp=64");
3839 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3840 fpabi_incompatible_with (fpabi
, "nooddspreg");
3841 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3842 fpabi_requires (fpabi
, "nooddspreg");
3845 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3846 if (file_mips_opts
.soft_float
)
3847 fpabi_incompatible_with (fpabi
, "softfloat");
3848 else if (!file_mips_opts
.single_float
)
3849 fpabi_requires (fpabi
, "singlefloat");
3852 case Val_GNU_MIPS_ABI_FP_SOFT
:
3853 if (!file_mips_opts
.soft_float
)
3854 fpabi_requires (fpabi
, "softfloat");
3857 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3858 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3859 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3862 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3863 /* Silently ignore compatibility value. */
3867 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3868 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3873 /* Perform consistency checks on the current options. */
3876 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3878 /* Check the size of integer registers agrees with the ABI and ISA. */
3879 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3880 as_bad (_("`gp=64' used with a 32-bit processor"));
3882 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3883 as_bad (_("`gp=32' used with a 64-bit ABI"));
3885 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3886 as_bad (_("`gp=64' used with a 32-bit ABI"));
3888 /* Check the size of the float registers agrees with the ABI and ISA. */
3892 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3893 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3894 else if (opts
->single_float
== 1)
3895 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3898 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3899 as_bad (_("`fp=64' used with a 32-bit fpu"));
3901 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3902 && !ISA_HAS_MXHC1 (opts
->isa
))
3903 as_warn (_("`fp=64' used with a 32-bit ABI"));
3907 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3908 as_warn (_("`fp=32' used with a 64-bit ABI"));
3909 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3910 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3913 as_bad (_("Unknown size of floating point registers"));
3917 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3918 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3920 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3921 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3922 else if (ISA_IS_R6 (opts
->isa
)
3923 && (opts
->micromips
== 1
3924 || opts
->mips16
== 1))
3925 as_fatal (_("`%s' cannot be used with `%s'"),
3926 opts
->micromips
? "micromips" : "mips16",
3927 mips_cpu_info_from_isa (opts
->isa
)->name
);
3929 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3930 as_fatal (_("branch relaxation is not supported in `%s'"),
3931 mips_cpu_info_from_isa (opts
->isa
)->name
);
3934 /* Perform consistency checks on the module level options exactly once.
3935 This is a deferred check that happens:
3936 at the first .set directive
3937 or, at the first pseudo op that generates code (inc .dc.a)
3938 or, at the first instruction
3942 file_mips_check_options (void)
3944 const struct mips_cpu_info
*arch_info
= 0;
3946 if (file_mips_opts_checked
)
3949 /* The following code determines the register size.
3950 Similar code was added to GCC 3.3 (see override_options() in
3951 config/mips/mips.c). The GAS and GCC code should be kept in sync
3952 as much as possible. */
3954 if (file_mips_opts
.gp
< 0)
3956 /* Infer the integer register size from the ABI and processor.
3957 Restrict ourselves to 32-bit registers if that's all the
3958 processor has, or if the ABI cannot handle 64-bit registers. */
3959 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3960 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3964 if (file_mips_opts
.fp
< 0)
3966 /* No user specified float register size.
3967 ??? GAS treats single-float processors as though they had 64-bit
3968 float registers (although it complains when double-precision
3969 instructions are used). As things stand, saying they have 32-bit
3970 registers would lead to spurious "register must be even" messages.
3971 So here we assume float registers are never smaller than the
3973 if (file_mips_opts
.gp
== 64)
3974 /* 64-bit integer registers implies 64-bit float registers. */
3975 file_mips_opts
.fp
= 64;
3976 else if ((file_mips_opts
.ase
& FP64_ASES
)
3977 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3978 /* Handle ASEs that require 64-bit float registers, if possible. */
3979 file_mips_opts
.fp
= 64;
3980 else if (ISA_IS_R6 (mips_opts
.isa
))
3981 /* R6 implies 64-bit float registers. */
3982 file_mips_opts
.fp
= 64;
3984 /* 32-bit float registers. */
3985 file_mips_opts
.fp
= 32;
3988 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3990 /* Disable operations on odd-numbered floating-point registers by default
3991 when using the FPXX ABI. */
3992 if (file_mips_opts
.oddspreg
< 0)
3994 if (file_mips_opts
.fp
== 0)
3995 file_mips_opts
.oddspreg
= 0;
3997 file_mips_opts
.oddspreg
= 1;
4000 /* End of GCC-shared inference code. */
4002 /* This flag is set when we have a 64-bit capable CPU but use only
4003 32-bit wide registers. Note that EABI does not use it. */
4004 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4005 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4006 || mips_abi
== O32_ABI
))
4009 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4010 as_bad (_("trap exception not supported at ISA 1"));
4012 /* If the selected architecture includes support for ASEs, enable
4013 generation of code for them. */
4014 if (file_mips_opts
.mips16
== -1)
4015 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4016 if (file_mips_opts
.micromips
== -1)
4017 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4020 if (mips_nan2008
== -1)
4021 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4022 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4023 as_fatal (_("`%s' does not support legacy NaN"),
4024 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4026 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4027 being selected implicitly. */
4028 if (file_mips_opts
.fp
!= 64)
4029 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4031 /* If the user didn't explicitly select or deselect a particular ASE,
4032 use the default setting for the CPU. */
4033 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4035 /* Set up the current options. These may change throughout assembly. */
4036 mips_opts
= file_mips_opts
;
4038 mips_check_isa_supports_ases ();
4039 mips_check_options (&file_mips_opts
, TRUE
);
4040 file_mips_opts_checked
= TRUE
;
4042 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4043 as_warn (_("could not set architecture and machine"));
4047 md_assemble (char *str
)
4049 struct mips_cl_insn insn
;
4050 bfd_reloc_code_real_type unused_reloc
[3]
4051 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4053 file_mips_check_options ();
4055 imm_expr
.X_op
= O_absent
;
4056 offset_expr
.X_op
= O_absent
;
4057 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4058 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4059 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4061 mips_mark_labels ();
4062 mips_assembling_insn
= TRUE
;
4063 clear_insn_error ();
4065 if (mips_opts
.mips16
)
4066 mips16_ip (str
, &insn
);
4069 mips_ip (str
, &insn
);
4070 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4071 str
, insn
.insn_opcode
));
4075 report_insn_error (str
);
4076 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4079 if (mips_opts
.mips16
)
4080 mips16_macro (&insn
);
4087 if (offset_expr
.X_op
!= O_absent
)
4088 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4090 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4093 mips_assembling_insn
= FALSE
;
4096 /* Convenience functions for abstracting away the differences between
4097 MIPS16 and non-MIPS16 relocations. */
4099 static inline bfd_boolean
4100 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4104 case BFD_RELOC_MIPS16_JMP
:
4105 case BFD_RELOC_MIPS16_GPREL
:
4106 case BFD_RELOC_MIPS16_GOT16
:
4107 case BFD_RELOC_MIPS16_CALL16
:
4108 case BFD_RELOC_MIPS16_HI16_S
:
4109 case BFD_RELOC_MIPS16_HI16
:
4110 case BFD_RELOC_MIPS16_LO16
:
4111 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4119 static inline bfd_boolean
4120 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4124 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4125 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4126 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4127 case BFD_RELOC_MICROMIPS_GPREL16
:
4128 case BFD_RELOC_MICROMIPS_JMP
:
4129 case BFD_RELOC_MICROMIPS_HI16
:
4130 case BFD_RELOC_MICROMIPS_HI16_S
:
4131 case BFD_RELOC_MICROMIPS_LO16
:
4132 case BFD_RELOC_MICROMIPS_LITERAL
:
4133 case BFD_RELOC_MICROMIPS_GOT16
:
4134 case BFD_RELOC_MICROMIPS_CALL16
:
4135 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4136 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4137 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4138 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4139 case BFD_RELOC_MICROMIPS_SUB
:
4140 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4141 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4142 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4143 case BFD_RELOC_MICROMIPS_HIGHEST
:
4144 case BFD_RELOC_MICROMIPS_HIGHER
:
4145 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4146 case BFD_RELOC_MICROMIPS_JALR
:
4154 static inline bfd_boolean
4155 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4157 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4160 static inline bfd_boolean
4161 b_reloc_p (bfd_reloc_code_real_type reloc
)
4163 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4164 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4165 || reloc
== BFD_RELOC_16_PCREL_S2
4166 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4167 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4168 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4169 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4172 static inline bfd_boolean
4173 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4175 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4176 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4179 static inline bfd_boolean
4180 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4182 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4183 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4186 static inline bfd_boolean
4187 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4189 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4190 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4193 static inline bfd_boolean
4194 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4196 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4199 static inline bfd_boolean
4200 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4202 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4203 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4206 /* Return true if RELOC is a PC-relative relocation that does not have
4207 full address range. */
4209 static inline bfd_boolean
4210 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4214 case BFD_RELOC_16_PCREL_S2
:
4215 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4216 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4217 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4218 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4219 case BFD_RELOC_MIPS_21_PCREL_S2
:
4220 case BFD_RELOC_MIPS_26_PCREL_S2
:
4221 case BFD_RELOC_MIPS_18_PCREL_S3
:
4222 case BFD_RELOC_MIPS_19_PCREL_S2
:
4225 case BFD_RELOC_32_PCREL
:
4226 case BFD_RELOC_HI16_S_PCREL
:
4227 case BFD_RELOC_LO16_PCREL
:
4228 return HAVE_64BIT_ADDRESSES
;
4235 /* Return true if the given relocation might need a matching %lo().
4236 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4237 need a matching %lo() when applied to local symbols. */
4239 static inline bfd_boolean
4240 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4242 return (HAVE_IN_PLACE_ADDENDS
4243 && (hi16_reloc_p (reloc
)
4244 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4245 all GOT16 relocations evaluate to "G". */
4246 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4249 /* Return the type of %lo() reloc needed by RELOC, given that
4250 reloc_needs_lo_p. */
4252 static inline bfd_reloc_code_real_type
4253 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4255 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4256 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4260 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4263 static inline bfd_boolean
4264 fixup_has_matching_lo_p (fixS
*fixp
)
4266 return (fixp
->fx_next
!= NULL
4267 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4268 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4269 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4272 /* Move all labels in LABELS to the current insertion point. TEXT_P
4273 says whether the labels refer to text or data. */
4276 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4278 struct insn_label_list
*l
;
4281 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4283 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4284 symbol_set_frag (l
->label
, frag_now
);
4285 val
= (valueT
) frag_now_fix ();
4286 /* MIPS16/microMIPS text labels are stored as odd. */
4287 if (text_p
&& HAVE_CODE_COMPRESSION
)
4289 S_SET_VALUE (l
->label
, val
);
4293 /* Move all labels in insn_labels to the current insertion point
4294 and treat them as text labels. */
4297 mips_move_text_labels (void)
4299 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4302 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4305 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4307 bfd_boolean linkonce
= FALSE
;
4308 segT symseg
= S_GET_SEGMENT (sym
);
4310 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4312 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4314 /* The GNU toolchain uses an extension for ELF: a section
4315 beginning with the magic string .gnu.linkonce is a
4316 linkonce section. */
4317 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4318 sizeof ".gnu.linkonce" - 1) == 0)
4324 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4325 linker to handle them specially, such as generating jalx instructions
4326 when needed. We also make them odd for the duration of the assembly,
4327 in order to generate the right sort of code. We will make them even
4328 in the adjust_symtab routine, while leaving them marked. This is
4329 convenient for the debugger and the disassembler. The linker knows
4330 to make them odd again. */
4333 mips_compressed_mark_label (symbolS
*label
)
4335 gas_assert (HAVE_CODE_COMPRESSION
);
4337 if (mips_opts
.mips16
)
4338 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4340 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4341 if ((S_GET_VALUE (label
) & 1) == 0
4342 /* Don't adjust the address if the label is global or weak, or
4343 in a link-once section, since we'll be emitting symbol reloc
4344 references to it which will be patched up by the linker, and
4345 the final value of the symbol may or may not be MIPS16/microMIPS. */
4346 && !S_IS_WEAK (label
)
4347 && !S_IS_EXTERNAL (label
)
4348 && !s_is_linkonce (label
, now_seg
))
4349 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4352 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4355 mips_compressed_mark_labels (void)
4357 struct insn_label_list
*l
;
4359 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4360 mips_compressed_mark_label (l
->label
);
4363 /* End the current frag. Make it a variant frag and record the
4367 relax_close_frag (void)
4369 mips_macro_warning
.first_frag
= frag_now
;
4370 frag_var (rs_machine_dependent
, 0, 0,
4371 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4372 mips_pic
!= NO_PIC
),
4373 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4375 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4376 mips_relax
.first_fixup
= 0;
4379 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4380 See the comment above RELAX_ENCODE for more details. */
4383 relax_start (symbolS
*symbol
)
4385 gas_assert (mips_relax
.sequence
== 0);
4386 mips_relax
.sequence
= 1;
4387 mips_relax
.symbol
= symbol
;
4390 /* Start generating the second version of a relaxable sequence.
4391 See the comment above RELAX_ENCODE for more details. */
4396 gas_assert (mips_relax
.sequence
== 1);
4397 mips_relax
.sequence
= 2;
4400 /* End the current relaxable sequence. */
4405 gas_assert (mips_relax
.sequence
== 2);
4406 relax_close_frag ();
4407 mips_relax
.sequence
= 0;
4410 /* Return true if IP is a delayed branch or jump. */
4412 static inline bfd_boolean
4413 delayed_branch_p (const struct mips_cl_insn
*ip
)
4415 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4416 | INSN_COND_BRANCH_DELAY
4417 | INSN_COND_BRANCH_LIKELY
)) != 0;
4420 /* Return true if IP is a compact branch or jump. */
4422 static inline bfd_boolean
4423 compact_branch_p (const struct mips_cl_insn
*ip
)
4425 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4426 | INSN2_COND_BRANCH
)) != 0;
4429 /* Return true if IP is an unconditional branch or jump. */
4431 static inline bfd_boolean
4432 uncond_branch_p (const struct mips_cl_insn
*ip
)
4434 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4435 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4438 /* Return true if IP is a branch-likely instruction. */
4440 static inline bfd_boolean
4441 branch_likely_p (const struct mips_cl_insn
*ip
)
4443 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4446 /* Return the type of nop that should be used to fill the delay slot
4447 of delayed branch IP. */
4449 static struct mips_cl_insn
*
4450 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4452 if (mips_opts
.micromips
4453 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4454 return µmips_nop32_insn
;
4458 /* Return a mask that has bit N set if OPCODE reads the register(s)
4462 insn_read_mask (const struct mips_opcode
*opcode
)
4464 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4467 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4471 insn_write_mask (const struct mips_opcode
*opcode
)
4473 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4476 /* Return a mask of the registers specified by operand OPERAND of INSN.
4477 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4481 operand_reg_mask (const struct mips_cl_insn
*insn
,
4482 const struct mips_operand
*operand
,
4483 unsigned int type_mask
)
4485 unsigned int uval
, vsel
;
4487 switch (operand
->type
)
4494 case OP_ADDIUSP_INT
:
4495 case OP_ENTRY_EXIT_LIST
:
4496 case OP_REPEAT_DEST_REG
:
4497 case OP_REPEAT_PREV_REG
:
4500 case OP_VU0_MATCH_SUFFIX
:
4505 case OP_OPTIONAL_REG
:
4507 const struct mips_reg_operand
*reg_op
;
4509 reg_op
= (const struct mips_reg_operand
*) operand
;
4510 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4512 uval
= insn_extract_operand (insn
, operand
);
4513 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4518 const struct mips_reg_pair_operand
*pair_op
;
4520 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4521 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4523 uval
= insn_extract_operand (insn
, operand
);
4524 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4527 case OP_CLO_CLZ_DEST
:
4528 if (!(type_mask
& (1 << OP_REG_GP
)))
4530 uval
= insn_extract_operand (insn
, operand
);
4531 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4534 if (!(type_mask
& (1 << OP_REG_GP
)))
4536 uval
= insn_extract_operand (insn
, operand
);
4537 gas_assert ((uval
& 31) == (uval
>> 5));
4538 return 1 << (uval
& 31);
4541 case OP_NON_ZERO_REG
:
4542 if (!(type_mask
& (1 << OP_REG_GP
)))
4544 uval
= insn_extract_operand (insn
, operand
);
4545 return 1 << (uval
& 31);
4547 case OP_LWM_SWM_LIST
:
4550 case OP_SAVE_RESTORE_LIST
:
4553 case OP_MDMX_IMM_REG
:
4554 if (!(type_mask
& (1 << OP_REG_VEC
)))
4556 uval
= insn_extract_operand (insn
, operand
);
4558 if ((vsel
& 0x18) == 0x18)
4560 return 1 << (uval
& 31);
4563 if (!(type_mask
& (1 << OP_REG_GP
)))
4565 return 1 << insn_extract_operand (insn
, operand
);
4570 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4571 where bit N of OPNO_MASK is set if operand N should be included.
4572 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4576 insn_reg_mask (const struct mips_cl_insn
*insn
,
4577 unsigned int type_mask
, unsigned int opno_mask
)
4579 unsigned int opno
, reg_mask
;
4583 while (opno_mask
!= 0)
4586 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4593 /* Return the mask of core registers that IP reads. */
4596 gpr_read_mask (const struct mips_cl_insn
*ip
)
4598 unsigned long pinfo
, pinfo2
;
4601 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4602 pinfo
= ip
->insn_mo
->pinfo
;
4603 pinfo2
= ip
->insn_mo
->pinfo2
;
4604 if (pinfo
& INSN_UDI
)
4606 /* UDI instructions have traditionally been assumed to read RS
4608 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4609 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4611 if (pinfo
& INSN_READ_GPR_24
)
4613 if (pinfo2
& INSN2_READ_GPR_16
)
4615 if (pinfo2
& INSN2_READ_SP
)
4617 if (pinfo2
& INSN2_READ_GPR_31
)
4619 /* Don't include register 0. */
4623 /* Return the mask of core registers that IP writes. */
4626 gpr_write_mask (const struct mips_cl_insn
*ip
)
4628 unsigned long pinfo
, pinfo2
;
4631 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4632 pinfo
= ip
->insn_mo
->pinfo
;
4633 pinfo2
= ip
->insn_mo
->pinfo2
;
4634 if (pinfo
& INSN_WRITE_GPR_24
)
4636 if (pinfo
& INSN_WRITE_GPR_31
)
4638 if (pinfo
& INSN_UDI
)
4639 /* UDI instructions have traditionally been assumed to write to RD. */
4640 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4641 if (pinfo2
& INSN2_WRITE_SP
)
4643 /* Don't include register 0. */
4647 /* Return the mask of floating-point registers that IP reads. */
4650 fpr_read_mask (const struct mips_cl_insn
*ip
)
4652 unsigned long pinfo
;
4655 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4656 | (1 << OP_REG_MSA
)),
4657 insn_read_mask (ip
->insn_mo
));
4658 pinfo
= ip
->insn_mo
->pinfo
;
4659 /* Conservatively treat all operands to an FP_D instruction are doubles.
4660 (This is overly pessimistic for things like cvt.d.s.) */
4661 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4666 /* Return the mask of floating-point registers that IP writes. */
4669 fpr_write_mask (const struct mips_cl_insn
*ip
)
4671 unsigned long pinfo
;
4674 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4675 | (1 << OP_REG_MSA
)),
4676 insn_write_mask (ip
->insn_mo
));
4677 pinfo
= ip
->insn_mo
->pinfo
;
4678 /* Conservatively treat all operands to an FP_D instruction are doubles.
4679 (This is overly pessimistic for things like cvt.s.d.) */
4680 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4685 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4686 Check whether that is allowed. */
4689 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4691 const char *s
= insn
->name
;
4692 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4694 && mips_opts
.oddspreg
;
4696 if (insn
->pinfo
== INSN_MACRO
)
4697 /* Let a macro pass, we'll catch it later when it is expanded. */
4700 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4701 otherwise it depends on oddspreg. */
4702 if ((insn
->pinfo
& FP_S
)
4703 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4704 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4705 return FPR_SIZE
== 32 || oddspreg
;
4707 /* Allow odd registers for single-precision ops and double-precision if the
4708 floating-point registers are 64-bit wide. */
4709 switch (insn
->pinfo
& (FP_S
| FP_D
))
4715 return FPR_SIZE
== 64;
4720 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4721 s
= strchr (insn
->name
, '.');
4722 if (s
!= NULL
&& opnum
== 2)
4723 s
= strchr (s
+ 1, '.');
4724 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4727 return FPR_SIZE
== 64;
4730 /* Information about an instruction argument that we're trying to match. */
4731 struct mips_arg_info
4733 /* The instruction so far. */
4734 struct mips_cl_insn
*insn
;
4736 /* The first unconsumed operand token. */
4737 struct mips_operand_token
*token
;
4739 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4742 /* The 1-based argument number, for error reporting. This does not
4743 count elided optional registers, etc.. */
4746 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4747 unsigned int last_regno
;
4749 /* If the first operand was an OP_REG, this is the register that it
4750 specified, otherwise it is ILLEGAL_REG. */
4751 unsigned int dest_regno
;
4753 /* The value of the last OP_INT operand. Only used for OP_MSB,
4754 where it gives the lsb position. */
4755 unsigned int last_op_int
;
4757 /* If true, match routines should assume that no later instruction
4758 alternative matches and should therefore be as accommodating as
4759 possible. Match routines should not report errors if something
4760 is only invalid for !LAX_MATCH. */
4761 bfd_boolean lax_match
;
4763 /* True if a reference to the current AT register was seen. */
4764 bfd_boolean seen_at
;
4767 /* Record that the argument is out of range. */
4770 match_out_of_range (struct mips_arg_info
*arg
)
4772 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4775 /* Record that the argument isn't constant but needs to be. */
4778 match_not_constant (struct mips_arg_info
*arg
)
4780 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4784 /* Try to match an OT_CHAR token for character CH. Consume the token
4785 and return true on success, otherwise return false. */
4788 match_char (struct mips_arg_info
*arg
, char ch
)
4790 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4800 /* Try to get an expression from the next tokens in ARG. Consume the
4801 tokens and return true on success, storing the expression value in
4802 VALUE and relocation types in R. */
4805 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4806 bfd_reloc_code_real_type
*r
)
4808 /* If the next token is a '(' that was parsed as being part of a base
4809 expression, assume we have an elided offset. The later match will fail
4810 if this turns out to be wrong. */
4811 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4813 value
->X_op
= O_constant
;
4814 value
->X_add_number
= 0;
4815 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4819 /* Reject register-based expressions such as "0+$2" and "(($2))".
4820 For plain registers the default error seems more appropriate. */
4821 if (arg
->token
->type
== OT_INTEGER
4822 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4824 set_insn_error (arg
->argnum
, _("register value used as expression"));
4828 if (arg
->token
->type
== OT_INTEGER
)
4830 *value
= arg
->token
->u
.integer
.value
;
4831 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4837 (arg
->argnum
, _("operand %d must be an immediate expression"),
4842 /* Try to get a constant expression from the next tokens in ARG. Consume
4843 the tokens and return return true on success, storing the constant value
4847 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4850 bfd_reloc_code_real_type r
[3];
4852 if (!match_expression (arg
, &ex
, r
))
4855 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4856 *value
= ex
.X_add_number
;
4859 match_not_constant (arg
);
4865 /* Return the RTYPE_* flags for a register operand of type TYPE that
4866 appears in instruction OPCODE. */
4869 convert_reg_type (const struct mips_opcode
*opcode
,
4870 enum mips_reg_operand_type type
)
4875 return RTYPE_NUM
| RTYPE_GP
;
4878 /* Allow vector register names for MDMX if the instruction is a 64-bit
4879 FPR load, store or move (including moves to and from GPRs). */
4880 if ((mips_opts
.ase
& ASE_MDMX
)
4881 && (opcode
->pinfo
& FP_D
)
4882 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4883 | INSN_COPROC_MEMORY_DELAY
4886 | INSN_STORE_MEMORY
)))
4887 return RTYPE_FPU
| RTYPE_VEC
;
4891 if (opcode
->pinfo
& (FP_D
| FP_S
))
4892 return RTYPE_CCC
| RTYPE_FCC
;
4896 if (opcode
->membership
& INSN_5400
)
4898 return RTYPE_FPU
| RTYPE_VEC
;
4904 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4905 return RTYPE_NUM
| RTYPE_CP0
;
4912 return RTYPE_NUM
| RTYPE_VI
;
4915 return RTYPE_NUM
| RTYPE_VF
;
4917 case OP_REG_R5900_I
:
4918 return RTYPE_R5900_I
;
4920 case OP_REG_R5900_Q
:
4921 return RTYPE_R5900_Q
;
4923 case OP_REG_R5900_R
:
4924 return RTYPE_R5900_R
;
4926 case OP_REG_R5900_ACC
:
4927 return RTYPE_R5900_ACC
;
4932 case OP_REG_MSA_CTRL
:
4938 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4941 check_regno (struct mips_arg_info
*arg
,
4942 enum mips_reg_operand_type type
, unsigned int regno
)
4944 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4945 arg
->seen_at
= TRUE
;
4947 if (type
== OP_REG_FP
4949 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4951 /* This was a warning prior to introducing O32 FPXX and FP64 support
4952 so maintain a warning for FP32 but raise an error for the new
4955 as_warn (_("float register should be even, was %d"), regno
);
4957 as_bad (_("float register should be even, was %d"), regno
);
4960 if (type
== OP_REG_CCC
)
4965 name
= arg
->insn
->insn_mo
->name
;
4966 length
= strlen (name
);
4967 if ((regno
& 1) != 0
4968 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4969 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4970 as_warn (_("condition code register should be even for %s, was %d"),
4973 if ((regno
& 3) != 0
4974 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4975 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4980 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4981 a register of type TYPE. Return true on success, storing the register
4982 number in *REGNO and warning about any dubious uses. */
4985 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4986 unsigned int symval
, unsigned int *regno
)
4988 if (type
== OP_REG_VEC
)
4989 symval
= mips_prefer_vec_regno (symval
);
4990 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4993 *regno
= symval
& RNUM_MASK
;
4994 check_regno (arg
, type
, *regno
);
4998 /* Try to interpret the next token in ARG as a register of type TYPE.
4999 Consume the token and return true on success, storing the register
5000 number in *REGNO. Return false on failure. */
5003 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5004 unsigned int *regno
)
5006 if (arg
->token
->type
== OT_REG
5007 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5015 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5016 Consume the token and return true on success, storing the register numbers
5017 in *REGNO1 and *REGNO2. Return false on failure. */
5020 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5021 unsigned int *regno1
, unsigned int *regno2
)
5023 if (match_reg (arg
, type
, regno1
))
5028 if (arg
->token
->type
== OT_REG_RANGE
5029 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5030 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5031 && *regno1
<= *regno2
)
5039 /* OP_INT matcher. */
5042 match_int_operand (struct mips_arg_info
*arg
,
5043 const struct mips_operand
*operand_base
)
5045 const struct mips_int_operand
*operand
;
5047 int min_val
, max_val
, factor
;
5050 operand
= (const struct mips_int_operand
*) operand_base
;
5051 factor
= 1 << operand
->shift
;
5052 min_val
= mips_int_operand_min (operand
);
5053 max_val
= mips_int_operand_max (operand
);
5055 if (operand_base
->lsb
== 0
5056 && operand_base
->size
== 16
5057 && operand
->shift
== 0
5058 && operand
->bias
== 0
5059 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5061 /* The operand can be relocated. */
5062 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5065 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5066 /* Relocation operators were used. Accept the argument and
5067 leave the relocation value in offset_expr and offset_relocs
5068 for the caller to process. */
5071 if (offset_expr
.X_op
!= O_constant
)
5073 /* Accept non-constant operands if no later alternative matches,
5074 leaving it for the caller to process. */
5075 if (!arg
->lax_match
)
5077 offset_reloc
[0] = BFD_RELOC_LO16
;
5081 /* Clear the global state; we're going to install the operand
5083 sval
= offset_expr
.X_add_number
;
5084 offset_expr
.X_op
= O_absent
;
5086 /* For compatibility with older assemblers, we accept
5087 0x8000-0xffff as signed 16-bit numbers when only
5088 signed numbers are allowed. */
5091 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5092 if (!arg
->lax_match
&& sval
<= max_val
)
5098 if (!match_const_int (arg
, &sval
))
5102 arg
->last_op_int
= sval
;
5104 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5106 match_out_of_range (arg
);
5110 uval
= (unsigned int) sval
>> operand
->shift
;
5111 uval
-= operand
->bias
;
5113 /* Handle -mfix-cn63xxp1. */
5115 && mips_fix_cn63xxp1
5116 && !mips_opts
.micromips
5117 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5132 /* The rest must be changed to 28. */
5137 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5141 /* OP_MAPPED_INT matcher. */
5144 match_mapped_int_operand (struct mips_arg_info
*arg
,
5145 const struct mips_operand
*operand_base
)
5147 const struct mips_mapped_int_operand
*operand
;
5148 unsigned int uval
, num_vals
;
5151 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5152 if (!match_const_int (arg
, &sval
))
5155 num_vals
= 1 << operand_base
->size
;
5156 for (uval
= 0; uval
< num_vals
; uval
++)
5157 if (operand
->int_map
[uval
] == sval
)
5159 if (uval
== num_vals
)
5161 match_out_of_range (arg
);
5165 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5169 /* OP_MSB matcher. */
5172 match_msb_operand (struct mips_arg_info
*arg
,
5173 const struct mips_operand
*operand_base
)
5175 const struct mips_msb_operand
*operand
;
5176 int min_val
, max_val
, max_high
;
5177 offsetT size
, sval
, high
;
5179 operand
= (const struct mips_msb_operand
*) operand_base
;
5180 min_val
= operand
->bias
;
5181 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5182 max_high
= operand
->opsize
;
5184 if (!match_const_int (arg
, &size
))
5187 high
= size
+ arg
->last_op_int
;
5188 sval
= operand
->add_lsb
? high
: size
;
5190 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5192 match_out_of_range (arg
);
5195 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5199 /* OP_REG matcher. */
5202 match_reg_operand (struct mips_arg_info
*arg
,
5203 const struct mips_operand
*operand_base
)
5205 const struct mips_reg_operand
*operand
;
5206 unsigned int regno
, uval
, num_vals
;
5208 operand
= (const struct mips_reg_operand
*) operand_base
;
5209 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5212 if (operand
->reg_map
)
5214 num_vals
= 1 << operand
->root
.size
;
5215 for (uval
= 0; uval
< num_vals
; uval
++)
5216 if (operand
->reg_map
[uval
] == regno
)
5218 if (num_vals
== uval
)
5224 arg
->last_regno
= regno
;
5225 if (arg
->opnum
== 1)
5226 arg
->dest_regno
= regno
;
5227 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5231 /* OP_REG_PAIR matcher. */
5234 match_reg_pair_operand (struct mips_arg_info
*arg
,
5235 const struct mips_operand
*operand_base
)
5237 const struct mips_reg_pair_operand
*operand
;
5238 unsigned int regno1
, regno2
, uval
, num_vals
;
5240 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5241 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5242 || !match_char (arg
, ',')
5243 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5246 num_vals
= 1 << operand_base
->size
;
5247 for (uval
= 0; uval
< num_vals
; uval
++)
5248 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5250 if (uval
== num_vals
)
5253 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5257 /* OP_PCREL matcher. The caller chooses the relocation type. */
5260 match_pcrel_operand (struct mips_arg_info
*arg
)
5262 bfd_reloc_code_real_type r
[3];
5264 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5267 /* OP_PERF_REG matcher. */
5270 match_perf_reg_operand (struct mips_arg_info
*arg
,
5271 const struct mips_operand
*operand
)
5275 if (!match_const_int (arg
, &sval
))
5280 || (mips_opts
.arch
== CPU_R5900
5281 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5282 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5284 set_insn_error (arg
->argnum
, _("invalid performance register"));
5288 insn_insert_operand (arg
->insn
, operand
, sval
);
5292 /* OP_ADDIUSP matcher. */
5295 match_addiusp_operand (struct mips_arg_info
*arg
,
5296 const struct mips_operand
*operand
)
5301 if (!match_const_int (arg
, &sval
))
5306 match_out_of_range (arg
);
5311 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5313 match_out_of_range (arg
);
5317 uval
= (unsigned int) sval
;
5318 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5319 insn_insert_operand (arg
->insn
, operand
, uval
);
5323 /* OP_CLO_CLZ_DEST matcher. */
5326 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5327 const struct mips_operand
*operand
)
5331 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5334 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5338 /* OP_CHECK_PREV matcher. */
5341 match_check_prev_operand (struct mips_arg_info
*arg
,
5342 const struct mips_operand
*operand_base
)
5344 const struct mips_check_prev_operand
*operand
;
5347 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5349 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5352 if (!operand
->zero_ok
&& regno
== 0)
5355 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5356 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5357 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5359 arg
->last_regno
= regno
;
5360 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5367 /* OP_SAME_RS_RT matcher. */
5370 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5371 const struct mips_operand
*operand
)
5375 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5380 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5384 arg
->last_regno
= regno
;
5386 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5390 /* OP_LWM_SWM_LIST matcher. */
5393 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5394 const struct mips_operand
*operand
)
5396 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5397 struct mips_arg_info reset
;
5400 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5404 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5409 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5412 while (match_char (arg
, ',')
5413 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5416 if (operand
->size
== 2)
5418 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5424 and any permutations of these. */
5425 if ((reglist
& 0xfff1ffff) != 0x80010000)
5428 sregs
= (reglist
>> 17) & 7;
5433 /* The list must include at least one of ra and s0-sN,
5434 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5435 which are $23 and $30 respectively.) E.g.:
5443 and any permutations of these. */
5444 if ((reglist
& 0x3f00ffff) != 0)
5447 ra
= (reglist
>> 27) & 0x10;
5448 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5451 if ((sregs
& -sregs
) != sregs
)
5454 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5458 /* OP_ENTRY_EXIT_LIST matcher. */
5461 match_entry_exit_operand (struct mips_arg_info
*arg
,
5462 const struct mips_operand
*operand
)
5465 bfd_boolean is_exit
;
5467 /* The format is the same for both ENTRY and EXIT, but the constraints
5469 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5470 mask
= (is_exit
? 7 << 3 : 0);
5473 unsigned int regno1
, regno2
;
5474 bfd_boolean is_freg
;
5476 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5478 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5483 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5486 mask
|= (5 + regno2
) << 3;
5488 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5489 mask
|= (regno2
- 3) << 3;
5490 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5491 mask
|= (regno2
- 15) << 1;
5492 else if (regno1
== RA
&& regno2
== RA
)
5497 while (match_char (arg
, ','));
5499 insn_insert_operand (arg
->insn
, operand
, mask
);
5503 /* OP_SAVE_RESTORE_LIST matcher. */
5506 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5508 unsigned int opcode
, args
, statics
, sregs
;
5509 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5512 opcode
= arg
->insn
->insn_opcode
;
5514 num_frame_sizes
= 0;
5520 unsigned int regno1
, regno2
;
5522 if (arg
->token
->type
== OT_INTEGER
)
5524 /* Handle the frame size. */
5525 if (!match_const_int (arg
, &frame_size
))
5527 num_frame_sizes
+= 1;
5531 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5534 while (regno1
<= regno2
)
5536 if (regno1
>= 4 && regno1
<= 7)
5538 if (num_frame_sizes
== 0)
5540 args
|= 1 << (regno1
- 4);
5542 /* statics $a0-$a3 */
5543 statics
|= 1 << (regno1
- 4);
5545 else if (regno1
>= 16 && regno1
<= 23)
5547 sregs
|= 1 << (regno1
- 16);
5548 else if (regno1
== 30)
5551 else if (regno1
== 31)
5552 /* Add $ra to insn. */
5562 while (match_char (arg
, ','));
5564 /* Encode args/statics combination. */
5567 else if (args
== 0xf)
5568 /* All $a0-$a3 are args. */
5569 opcode
|= MIPS16_ALL_ARGS
<< 16;
5570 else if (statics
== 0xf)
5571 /* All $a0-$a3 are statics. */
5572 opcode
|= MIPS16_ALL_STATICS
<< 16;
5575 /* Count arg registers. */
5585 /* Count static registers. */
5587 while (statics
& 0x8)
5589 statics
= (statics
<< 1) & 0xf;
5595 /* Encode args/statics. */
5596 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5599 /* Encode $s0/$s1. */
5600 if (sregs
& (1 << 0)) /* $s0 */
5602 if (sregs
& (1 << 1)) /* $s1 */
5606 /* Encode $s2-$s8. */
5615 opcode
|= num_sregs
<< 24;
5617 /* Encode frame size. */
5618 if (num_frame_sizes
== 0)
5620 set_insn_error (arg
->argnum
, _("missing frame size"));
5623 if (num_frame_sizes
> 1)
5625 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5628 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5630 set_insn_error (arg
->argnum
, _("invalid frame size"));
5633 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5636 opcode
|= (((frame_size
& 0xf0) << 16)
5637 | (frame_size
& 0x0f));
5640 /* Finally build the instruction. */
5641 if ((opcode
>> 16) != 0 || frame_size
== 0)
5642 opcode
|= MIPS16_EXTEND
;
5643 arg
->insn
->insn_opcode
= opcode
;
5647 /* OP_MDMX_IMM_REG matcher. */
5650 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5651 const struct mips_operand
*operand
)
5653 unsigned int regno
, uval
;
5655 const struct mips_opcode
*opcode
;
5657 /* The mips_opcode records whether this is an octobyte or quadhalf
5658 instruction. Start out with that bit in place. */
5659 opcode
= arg
->insn
->insn_mo
;
5660 uval
= mips_extract_operand (operand
, opcode
->match
);
5661 is_qh
= (uval
!= 0);
5663 if (arg
->token
->type
== OT_REG
)
5665 if ((opcode
->membership
& INSN_5400
)
5666 && strcmp (opcode
->name
, "rzu.ob") == 0)
5668 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5673 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5677 /* Check whether this is a vector register or a broadcast of
5678 a single element. */
5679 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5681 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5683 set_insn_error (arg
->argnum
, _("invalid element selector"));
5686 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5691 /* A full vector. */
5692 if ((opcode
->membership
& INSN_5400
)
5693 && (strcmp (opcode
->name
, "sll.ob") == 0
5694 || strcmp (opcode
->name
, "srl.ob") == 0))
5696 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5702 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5704 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5712 if (!match_const_int (arg
, &sval
))
5714 if (sval
< 0 || sval
> 31)
5716 match_out_of_range (arg
);
5719 uval
|= (sval
& 31);
5721 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5723 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5725 insn_insert_operand (arg
->insn
, operand
, uval
);
5729 /* OP_IMM_INDEX matcher. */
5732 match_imm_index_operand (struct mips_arg_info
*arg
,
5733 const struct mips_operand
*operand
)
5735 unsigned int max_val
;
5737 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5740 max_val
= (1 << operand
->size
) - 1;
5741 if (arg
->token
->u
.index
> max_val
)
5743 match_out_of_range (arg
);
5746 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5751 /* OP_REG_INDEX matcher. */
5754 match_reg_index_operand (struct mips_arg_info
*arg
,
5755 const struct mips_operand
*operand
)
5759 if (arg
->token
->type
!= OT_REG_INDEX
)
5762 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5765 insn_insert_operand (arg
->insn
, operand
, regno
);
5770 /* OP_PC matcher. */
5773 match_pc_operand (struct mips_arg_info
*arg
)
5775 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5783 /* OP_NON_ZERO_REG matcher. */
5786 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5787 const struct mips_operand
*operand
)
5791 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5797 arg
->last_regno
= regno
;
5798 insn_insert_operand (arg
->insn
, operand
, regno
);
5802 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5803 register that we need to match. */
5806 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5810 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5813 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5814 the length of the value in bytes (4 for float, 8 for double) and
5815 USING_GPRS says whether the destination is a GPR rather than an FPR.
5817 Return the constant in IMM and OFFSET as follows:
5819 - If the constant should be loaded via memory, set IMM to O_absent and
5820 OFFSET to the memory address.
5822 - Otherwise, if the constant should be loaded into two 32-bit registers,
5823 set IMM to the O_constant to load into the high register and OFFSET
5824 to the corresponding value for the low register.
5826 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5828 These constants only appear as the last operand in an instruction,
5829 and every instruction that accepts them in any variant accepts them
5830 in all variants. This means we don't have to worry about backing out
5831 any changes if the instruction does not match. We just match
5832 unconditionally and report an error if the constant is invalid. */
5835 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5836 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5841 const char *newname
;
5842 unsigned char *data
;
5844 /* Where the constant is placed is based on how the MIPS assembler
5847 length == 4 && using_gprs -- immediate value only
5848 length == 8 && using_gprs -- .rdata or immediate value
5849 length == 4 && !using_gprs -- .lit4 or immediate value
5850 length == 8 && !using_gprs -- .lit8 or immediate value
5852 The .lit4 and .lit8 sections are only used if permitted by the
5854 if (arg
->token
->type
!= OT_FLOAT
)
5856 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5860 gas_assert (arg
->token
->u
.flt
.length
== length
);
5861 data
= arg
->token
->u
.flt
.data
;
5864 /* Handle 32-bit constants for which an immediate value is best. */
5867 || g_switch_value
< 4
5868 || (data
[0] == 0 && data
[1] == 0)
5869 || (data
[2] == 0 && data
[3] == 0)))
5871 imm
->X_op
= O_constant
;
5872 if (!target_big_endian
)
5873 imm
->X_add_number
= bfd_getl32 (data
);
5875 imm
->X_add_number
= bfd_getb32 (data
);
5876 offset
->X_op
= O_absent
;
5880 /* Handle 64-bit constants for which an immediate value is best. */
5882 && !mips_disable_float_construction
5883 /* Constants can only be constructed in GPRs and copied to FPRs if the
5884 GPRs are at least as wide as the FPRs or MTHC1 is available.
5885 Unlike most tests for 32-bit floating-point registers this check
5886 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5887 permit 64-bit moves without MXHC1.
5888 Force the constant into memory otherwise. */
5891 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5893 && ((data
[0] == 0 && data
[1] == 0)
5894 || (data
[2] == 0 && data
[3] == 0))
5895 && ((data
[4] == 0 && data
[5] == 0)
5896 || (data
[6] == 0 && data
[7] == 0)))
5898 /* The value is simple enough to load with a couple of instructions.
5899 If using 32-bit registers, set IMM to the high order 32 bits and
5900 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5902 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5904 imm
->X_op
= O_constant
;
5905 offset
->X_op
= O_constant
;
5906 if (!target_big_endian
)
5908 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5909 offset
->X_add_number
= bfd_getl32 (data
);
5913 imm
->X_add_number
= bfd_getb32 (data
);
5914 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5916 if (offset
->X_add_number
== 0)
5917 offset
->X_op
= O_absent
;
5921 imm
->X_op
= O_constant
;
5922 if (!target_big_endian
)
5923 imm
->X_add_number
= bfd_getl64 (data
);
5925 imm
->X_add_number
= bfd_getb64 (data
);
5926 offset
->X_op
= O_absent
;
5931 /* Switch to the right section. */
5933 subseg
= now_subseg
;
5936 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5941 if (using_gprs
|| g_switch_value
< 8)
5942 newname
= RDATA_SECTION_NAME
;
5947 new_seg
= subseg_new (newname
, (subsegT
) 0);
5948 bfd_set_section_flags (stdoutput
, new_seg
,
5949 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5950 frag_align (length
== 4 ? 2 : 3, 0, 0);
5951 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5952 record_alignment (new_seg
, 4);
5954 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5956 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5958 /* Set the argument to the current address in the section. */
5959 imm
->X_op
= O_absent
;
5960 offset
->X_op
= O_symbol
;
5961 offset
->X_add_symbol
= symbol_temp_new_now ();
5962 offset
->X_add_number
= 0;
5964 /* Put the floating point number into the section. */
5965 p
= frag_more (length
);
5966 memcpy (p
, data
, length
);
5968 /* Switch back to the original section. */
5969 subseg_set (seg
, subseg
);
5973 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5977 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5978 const struct mips_operand
*operand
,
5979 bfd_boolean match_p
)
5983 /* The operand can be an XYZW mask or a single 2-bit channel index
5984 (with X being 0). */
5985 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5987 /* The suffix can be omitted when it is already part of the opcode. */
5988 if (arg
->token
->type
!= OT_CHANNELS
)
5991 uval
= arg
->token
->u
.channels
;
5992 if (operand
->size
== 2)
5994 /* Check that a single bit is set and convert it into a 2-bit index. */
5995 if ((uval
& -uval
) != uval
)
5997 uval
= 4 - ffs (uval
);
6000 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6005 insn_insert_operand (arg
->insn
, operand
, uval
);
6009 /* S is the text seen for ARG. Match it against OPERAND. Return the end
6010 of the argument text if the match is successful, otherwise return null. */
6013 match_operand (struct mips_arg_info
*arg
,
6014 const struct mips_operand
*operand
)
6016 switch (operand
->type
)
6019 return match_int_operand (arg
, operand
);
6022 return match_mapped_int_operand (arg
, operand
);
6025 return match_msb_operand (arg
, operand
);
6028 case OP_OPTIONAL_REG
:
6029 return match_reg_operand (arg
, operand
);
6032 return match_reg_pair_operand (arg
, operand
);
6035 return match_pcrel_operand (arg
);
6038 return match_perf_reg_operand (arg
, operand
);
6040 case OP_ADDIUSP_INT
:
6041 return match_addiusp_operand (arg
, operand
);
6043 case OP_CLO_CLZ_DEST
:
6044 return match_clo_clz_dest_operand (arg
, operand
);
6046 case OP_LWM_SWM_LIST
:
6047 return match_lwm_swm_list_operand (arg
, operand
);
6049 case OP_ENTRY_EXIT_LIST
:
6050 return match_entry_exit_operand (arg
, operand
);
6052 case OP_SAVE_RESTORE_LIST
:
6053 return match_save_restore_list_operand (arg
);
6055 case OP_MDMX_IMM_REG
:
6056 return match_mdmx_imm_reg_operand (arg
, operand
);
6058 case OP_REPEAT_DEST_REG
:
6059 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6061 case OP_REPEAT_PREV_REG
:
6062 return match_tied_reg_operand (arg
, arg
->last_regno
);
6065 return match_pc_operand (arg
);
6068 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6070 case OP_VU0_MATCH_SUFFIX
:
6071 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6074 return match_imm_index_operand (arg
, operand
);
6077 return match_reg_index_operand (arg
, operand
);
6080 return match_same_rs_rt_operand (arg
, operand
);
6083 return match_check_prev_operand (arg
, operand
);
6085 case OP_NON_ZERO_REG
:
6086 return match_non_zero_reg_operand (arg
, operand
);
6091 /* ARG is the state after successfully matching an instruction.
6092 Issue any queued-up warnings. */
6095 check_completed_insn (struct mips_arg_info
*arg
)
6100 as_warn (_("used $at without \".set noat\""));
6102 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6106 /* Return true if modifying general-purpose register REG needs a delay. */
6109 reg_needs_delay (unsigned int reg
)
6111 unsigned long prev_pinfo
;
6113 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6114 if (!mips_opts
.noreorder
6115 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6116 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6117 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6123 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6124 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6125 by VR4120 errata. */
6128 classify_vr4120_insn (const char *name
)
6130 if (strncmp (name
, "macc", 4) == 0)
6131 return FIX_VR4120_MACC
;
6132 if (strncmp (name
, "dmacc", 5) == 0)
6133 return FIX_VR4120_DMACC
;
6134 if (strncmp (name
, "mult", 4) == 0)
6135 return FIX_VR4120_MULT
;
6136 if (strncmp (name
, "dmult", 5) == 0)
6137 return FIX_VR4120_DMULT
;
6138 if (strstr (name
, "div"))
6139 return FIX_VR4120_DIV
;
6140 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6141 return FIX_VR4120_MTHILO
;
6142 return NUM_FIX_VR4120_CLASSES
;
6145 #define INSN_ERET 0x42000018
6146 #define INSN_DERET 0x4200001f
6147 #define INSN_DMULT 0x1c
6148 #define INSN_DMULTU 0x1d
6150 /* Return the number of instructions that must separate INSN1 and INSN2,
6151 where INSN1 is the earlier instruction. Return the worst-case value
6152 for any INSN2 if INSN2 is null. */
6155 insns_between (const struct mips_cl_insn
*insn1
,
6156 const struct mips_cl_insn
*insn2
)
6158 unsigned long pinfo1
, pinfo2
;
6161 /* If INFO2 is null, pessimistically assume that all flags are set for
6162 the second instruction. */
6163 pinfo1
= insn1
->insn_mo
->pinfo
;
6164 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6166 /* For most targets, write-after-read dependencies on the HI and LO
6167 registers must be separated by at least two instructions. */
6168 if (!hilo_interlocks
)
6170 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6172 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6176 /* If we're working around r7000 errata, there must be two instructions
6177 between an mfhi or mflo and any instruction that uses the result. */
6178 if (mips_7000_hilo_fix
6179 && !mips_opts
.micromips
6180 && MF_HILO_INSN (pinfo1
)
6181 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6184 /* If we're working around 24K errata, one instruction is required
6185 if an ERET or DERET is followed by a branch instruction. */
6186 if (mips_fix_24k
&& !mips_opts
.micromips
)
6188 if (insn1
->insn_opcode
== INSN_ERET
6189 || insn1
->insn_opcode
== INSN_DERET
)
6192 || insn2
->insn_opcode
== INSN_ERET
6193 || insn2
->insn_opcode
== INSN_DERET
6194 || delayed_branch_p (insn2
))
6199 /* If we're working around PMC RM7000 errata, there must be three
6200 nops between a dmult and a load instruction. */
6201 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6203 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6204 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6206 if (pinfo2
& INSN_LOAD_MEMORY
)
6211 /* If working around VR4120 errata, check for combinations that need
6212 a single intervening instruction. */
6213 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6215 unsigned int class1
, class2
;
6217 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6218 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6222 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6223 if (vr4120_conflicts
[class1
] & (1 << class2
))
6228 if (!HAVE_CODE_COMPRESSION
)
6230 /* Check for GPR or coprocessor load delays. All such delays
6231 are on the RT register. */
6232 /* Itbl support may require additional care here. */
6233 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6234 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6236 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6240 /* Check for generic coprocessor hazards.
6242 This case is not handled very well. There is no special
6243 knowledge of CP0 handling, and the coprocessors other than
6244 the floating point unit are not distinguished at all. */
6245 /* Itbl support may require additional care here. FIXME!
6246 Need to modify this to include knowledge about
6247 user specified delays! */
6248 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6249 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6251 /* Handle cases where INSN1 writes to a known general coprocessor
6252 register. There must be a one instruction delay before INSN2
6253 if INSN2 reads that register, otherwise no delay is needed. */
6254 mask
= fpr_write_mask (insn1
);
6257 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6262 /* Read-after-write dependencies on the control registers
6263 require a two-instruction gap. */
6264 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6265 && (pinfo2
& INSN_READ_COND_CODE
))
6268 /* We don't know exactly what INSN1 does. If INSN2 is
6269 also a coprocessor instruction, assume there must be
6270 a one instruction gap. */
6271 if (pinfo2
& INSN_COP
)
6276 /* Check for read-after-write dependencies on the coprocessor
6277 control registers in cases where INSN1 does not need a general
6278 coprocessor delay. This means that INSN1 is a floating point
6279 comparison instruction. */
6280 /* Itbl support may require additional care here. */
6281 else if (!cop_interlocks
6282 && (pinfo1
& INSN_WRITE_COND_CODE
)
6283 && (pinfo2
& INSN_READ_COND_CODE
))
6287 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6288 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6290 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6291 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6292 || (insn2
&& delayed_branch_p (insn2
))))
6298 /* Return the number of nops that would be needed to work around the
6299 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6300 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6301 that are contained within the first IGNORE instructions of HIST. */
6304 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6305 const struct mips_cl_insn
*insn
)
6310 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6311 are not affected by the errata. */
6313 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6314 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6315 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6318 /* Search for the first MFLO or MFHI. */
6319 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6320 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6322 /* Extract the destination register. */
6323 mask
= gpr_write_mask (&hist
[i
]);
6325 /* No nops are needed if INSN reads that register. */
6326 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6329 /* ...or if any of the intervening instructions do. */
6330 for (j
= 0; j
< i
; j
++)
6331 if (gpr_read_mask (&hist
[j
]) & mask
)
6335 return MAX_VR4130_NOPS
- i
;
6340 #define BASE_REG_EQ(INSN1, INSN2) \
6341 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6342 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6344 /* Return the minimum alignment for this store instruction. */
6347 fix_24k_align_to (const struct mips_opcode
*mo
)
6349 if (strcmp (mo
->name
, "sh") == 0)
6352 if (strcmp (mo
->name
, "swc1") == 0
6353 || strcmp (mo
->name
, "swc2") == 0
6354 || strcmp (mo
->name
, "sw") == 0
6355 || strcmp (mo
->name
, "sc") == 0
6356 || strcmp (mo
->name
, "s.s") == 0)
6359 if (strcmp (mo
->name
, "sdc1") == 0
6360 || strcmp (mo
->name
, "sdc2") == 0
6361 || strcmp (mo
->name
, "s.d") == 0)
6368 struct fix_24k_store_info
6370 /* Immediate offset, if any, for this store instruction. */
6372 /* Alignment required by this store instruction. */
6374 /* True for register offsets. */
6375 int register_offset
;
6378 /* Comparison function used by qsort. */
6381 fix_24k_sort (const void *a
, const void *b
)
6383 const struct fix_24k_store_info
*pos1
= a
;
6384 const struct fix_24k_store_info
*pos2
= b
;
6386 return (pos1
->off
- pos2
->off
);
6389 /* INSN is a store instruction. Try to record the store information
6390 in STINFO. Return false if the information isn't known. */
6393 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6394 const struct mips_cl_insn
*insn
)
6396 /* The instruction must have a known offset. */
6397 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6400 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6401 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6405 /* Return the number of nops that would be needed to work around the 24k
6406 "lost data on stores during refill" errata if instruction INSN
6407 immediately followed the 2 instructions described by HIST.
6408 Ignore hazards that are contained within the first IGNORE
6409 instructions of HIST.
6411 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6412 for the data cache refills and store data. The following describes
6413 the scenario where the store data could be lost.
6415 * A data cache miss, due to either a load or a store, causing fill
6416 data to be supplied by the memory subsystem
6417 * The first three doublewords of fill data are returned and written
6419 * A sequence of four stores occurs in consecutive cycles around the
6420 final doubleword of the fill:
6424 * Zero, One or more instructions
6427 The four stores A-D must be to different doublewords of the line that
6428 is being filled. The fourth instruction in the sequence above permits
6429 the fill of the final doubleword to be transferred from the FSB into
6430 the cache. In the sequence above, the stores may be either integer
6431 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6432 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6433 different doublewords on the line. If the floating point unit is
6434 running in 1:2 mode, it is not possible to create the sequence above
6435 using only floating point store instructions.
6437 In this case, the cache line being filled is incorrectly marked
6438 invalid, thereby losing the data from any store to the line that
6439 occurs between the original miss and the completion of the five
6440 cycle sequence shown above.
6442 The workarounds are:
6444 * Run the data cache in write-through mode.
6445 * Insert a non-store instruction between
6446 Store A and Store B or Store B and Store C. */
6449 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6450 const struct mips_cl_insn
*insn
)
6452 struct fix_24k_store_info pos
[3];
6453 int align
, i
, base_offset
;
6458 /* If the previous instruction wasn't a store, there's nothing to
6460 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6463 /* If the instructions after the previous one are unknown, we have
6464 to assume the worst. */
6468 /* Check whether we are dealing with three consecutive stores. */
6469 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6470 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6473 /* If we don't know the relationship between the store addresses,
6474 assume the worst. */
6475 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6476 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6479 if (!fix_24k_record_store_info (&pos
[0], insn
)
6480 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6481 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6484 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6486 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6487 X bytes and such that the base register + X is known to be aligned
6490 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6494 align
= pos
[0].align_to
;
6495 base_offset
= pos
[0].off
;
6496 for (i
= 1; i
< 3; i
++)
6497 if (align
< pos
[i
].align_to
)
6499 align
= pos
[i
].align_to
;
6500 base_offset
= pos
[i
].off
;
6502 for (i
= 0; i
< 3; i
++)
6503 pos
[i
].off
-= base_offset
;
6506 pos
[0].off
&= ~align
+ 1;
6507 pos
[1].off
&= ~align
+ 1;
6508 pos
[2].off
&= ~align
+ 1;
6510 /* If any two stores write to the same chunk, they also write to the
6511 same doubleword. The offsets are still sorted at this point. */
6512 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6515 /* A range of at least 9 bytes is needed for the stores to be in
6516 non-overlapping doublewords. */
6517 if (pos
[2].off
- pos
[0].off
<= 8)
6520 if (pos
[2].off
- pos
[1].off
>= 24
6521 || pos
[1].off
- pos
[0].off
>= 24
6522 || pos
[2].off
- pos
[0].off
>= 32)
6528 /* Return the number of nops that would be needed if instruction INSN
6529 immediately followed the MAX_NOPS instructions given by HIST,
6530 where HIST[0] is the most recent instruction. Ignore hazards
6531 between INSN and the first IGNORE instructions in HIST.
6533 If INSN is null, return the worse-case number of nops for any
6537 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6538 const struct mips_cl_insn
*insn
)
6540 int i
, nops
, tmp_nops
;
6543 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6545 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6546 if (tmp_nops
> nops
)
6550 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6552 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6553 if (tmp_nops
> nops
)
6557 if (mips_fix_24k
&& !mips_opts
.micromips
)
6559 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6560 if (tmp_nops
> nops
)
6567 /* The variable arguments provide NUM_INSNS extra instructions that
6568 might be added to HIST. Return the largest number of nops that
6569 would be needed after the extended sequence, ignoring hazards
6570 in the first IGNORE instructions. */
6573 nops_for_sequence (int num_insns
, int ignore
,
6574 const struct mips_cl_insn
*hist
, ...)
6577 struct mips_cl_insn buffer
[MAX_NOPS
];
6578 struct mips_cl_insn
*cursor
;
6581 va_start (args
, hist
);
6582 cursor
= buffer
+ num_insns
;
6583 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6584 while (cursor
> buffer
)
6585 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6587 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6592 /* Like nops_for_insn, but if INSN is a branch, take into account the
6593 worst-case delay for the branch target. */
6596 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6597 const struct mips_cl_insn
*insn
)
6601 nops
= nops_for_insn (ignore
, hist
, insn
);
6602 if (delayed_branch_p (insn
))
6604 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6605 hist
, insn
, get_delay_slot_nop (insn
));
6606 if (tmp_nops
> nops
)
6609 else if (compact_branch_p (insn
))
6611 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6612 if (tmp_nops
> nops
)
6618 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6621 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6623 gas_assert (!HAVE_CODE_COMPRESSION
);
6624 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6625 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6628 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6629 jr target pc &= 'hffff_ffff_cfff_ffff. */
6632 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6634 gas_assert (!HAVE_CODE_COMPRESSION
);
6635 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6636 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6637 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6645 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6646 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6649 ep
.X_op
= O_constant
;
6650 ep
.X_add_number
= 0xcfff0000;
6651 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6652 ep
.X_add_number
= 0xffff;
6653 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6654 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6659 fix_loongson2f (struct mips_cl_insn
* ip
)
6661 if (mips_fix_loongson2f_nop
)
6662 fix_loongson2f_nop (ip
);
6664 if (mips_fix_loongson2f_jump
)
6665 fix_loongson2f_jump (ip
);
6668 /* IP is a branch that has a delay slot, and we need to fill it
6669 automatically. Return true if we can do that by swapping IP
6670 with the previous instruction.
6671 ADDRESS_EXPR is an operand of the instruction to be used with
6675 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6676 bfd_reloc_code_real_type
*reloc_type
)
6678 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6679 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6680 unsigned int fpr_read
, prev_fpr_write
;
6682 /* -O2 and above is required for this optimization. */
6683 if (mips_optimize
< 2)
6686 /* If we have seen .set volatile or .set nomove, don't optimize. */
6687 if (mips_opts
.nomove
)
6690 /* We can't swap if the previous instruction's position is fixed. */
6691 if (history
[0].fixed_p
)
6694 /* If the previous previous insn was in a .set noreorder, we can't
6695 swap. Actually, the MIPS assembler will swap in this situation.
6696 However, gcc configured -with-gnu-as will generate code like
6704 in which we can not swap the bne and INSN. If gcc is not configured
6705 -with-gnu-as, it does not output the .set pseudo-ops. */
6706 if (history
[1].noreorder_p
)
6709 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6710 This means that the previous instruction was a 4-byte one anyhow. */
6711 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6714 /* If the branch is itself the target of a branch, we can not swap.
6715 We cheat on this; all we check for is whether there is a label on
6716 this instruction. If there are any branches to anything other than
6717 a label, users must use .set noreorder. */
6718 if (seg_info (now_seg
)->label_list
)
6721 /* If the previous instruction is in a variant frag other than this
6722 branch's one, we cannot do the swap. This does not apply to
6723 MIPS16 code, which uses variant frags for different purposes. */
6724 if (!mips_opts
.mips16
6726 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6729 /* We do not swap with instructions that cannot architecturally
6730 be placed in a branch delay slot, such as SYNC or ERET. We
6731 also refrain from swapping with a trap instruction, since it
6732 complicates trap handlers to have the trap instruction be in
6734 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6735 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6738 /* Check for conflicts between the branch and the instructions
6739 before the candidate delay slot. */
6740 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6743 /* Check for conflicts between the swapped sequence and the
6744 target of the branch. */
6745 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6748 /* If the branch reads a register that the previous
6749 instruction sets, we can not swap. */
6750 gpr_read
= gpr_read_mask (ip
);
6751 prev_gpr_write
= gpr_write_mask (&history
[0]);
6752 if (gpr_read
& prev_gpr_write
)
6755 fpr_read
= fpr_read_mask (ip
);
6756 prev_fpr_write
= fpr_write_mask (&history
[0]);
6757 if (fpr_read
& prev_fpr_write
)
6760 /* If the branch writes a register that the previous
6761 instruction sets, we can not swap. */
6762 gpr_write
= gpr_write_mask (ip
);
6763 if (gpr_write
& prev_gpr_write
)
6766 /* If the branch writes a register that the previous
6767 instruction reads, we can not swap. */
6768 prev_gpr_read
= gpr_read_mask (&history
[0]);
6769 if (gpr_write
& prev_gpr_read
)
6772 /* If one instruction sets a condition code and the
6773 other one uses a condition code, we can not swap. */
6774 pinfo
= ip
->insn_mo
->pinfo
;
6775 if ((pinfo
& INSN_READ_COND_CODE
)
6776 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6778 if ((pinfo
& INSN_WRITE_COND_CODE
)
6779 && (prev_pinfo
& INSN_READ_COND_CODE
))
6782 /* If the previous instruction uses the PC, we can not swap. */
6783 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6784 if (prev_pinfo2
& INSN2_READ_PC
)
6787 /* If the previous instruction has an incorrect size for a fixed
6788 branch delay slot in microMIPS mode, we cannot swap. */
6789 pinfo2
= ip
->insn_mo
->pinfo2
;
6790 if (mips_opts
.micromips
6791 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6792 && insn_length (history
) != 2)
6794 if (mips_opts
.micromips
6795 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6796 && insn_length (history
) != 4)
6799 /* On R5900 short loops need to be fixed by inserting a nop in
6800 the branch delay slots.
6801 A short loop can be terminated too early. */
6802 if (mips_opts
.arch
== CPU_R5900
6803 /* Check if instruction has a parameter, ignore "j $31". */
6804 && (address_expr
!= NULL
)
6805 /* Parameter must be 16 bit. */
6806 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6807 /* Branch to same segment. */
6808 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6809 /* Branch to same code fragment. */
6810 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6811 /* Can only calculate branch offset if value is known. */
6812 && symbol_constant_p (address_expr
->X_add_symbol
)
6813 /* Check if branch is really conditional. */
6814 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6815 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6816 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6819 /* Check if loop is shorter than 6 instructions including
6820 branch and delay slot. */
6821 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6828 /* When the loop includes branches or jumps,
6829 it is not a short loop. */
6830 for (i
= 0; i
< (distance
/ 4); i
++)
6832 if ((history
[i
].cleared_p
)
6833 || delayed_branch_p (&history
[i
]))
6841 /* Insert nop after branch to fix short loop. */
6850 /* Decide how we should add IP to the instruction stream.
6851 ADDRESS_EXPR is an operand of the instruction to be used with
6854 static enum append_method
6855 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6856 bfd_reloc_code_real_type
*reloc_type
)
6858 /* The relaxed version of a macro sequence must be inherently
6860 if (mips_relax
.sequence
== 2)
6863 /* We must not dabble with instructions in a ".set noreorder" block. */
6864 if (mips_opts
.noreorder
)
6867 /* Otherwise, it's our responsibility to fill branch delay slots. */
6868 if (delayed_branch_p (ip
))
6870 if (!branch_likely_p (ip
)
6871 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6874 if (mips_opts
.mips16
6875 && ISA_SUPPORTS_MIPS16E
6876 && gpr_read_mask (ip
) != 0)
6877 return APPEND_ADD_COMPACT
;
6879 if (mips_opts
.micromips
6880 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
6881 || (!forced_insn_length
6882 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
6883 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
6884 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
6885 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
6886 return APPEND_ADD_COMPACT
;
6888 return APPEND_ADD_WITH_NOP
;
6894 /* IP is an instruction whose opcode we have just changed, END points
6895 to the end of the opcode table processed. Point IP->insn_mo to the
6896 new opcode's definition. */
6899 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
6901 const struct mips_opcode
*mo
;
6903 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6904 if (mo
->pinfo
!= INSN_MACRO
6905 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6913 /* IP is a MIPS16 instruction whose opcode we have just changed.
6914 Point IP->insn_mo to the new opcode's definition. */
6917 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6919 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
6922 /* IP is a microMIPS instruction whose opcode we have just changed.
6923 Point IP->insn_mo to the new opcode's definition. */
6926 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
6928 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
6931 /* For microMIPS macros, we need to generate a local number label
6932 as the target of branches. */
6933 #define MICROMIPS_LABEL_CHAR '\037'
6934 static unsigned long micromips_target_label
;
6935 static char micromips_target_name
[32];
6938 micromips_label_name (void)
6940 char *p
= micromips_target_name
;
6941 char symbol_name_temporary
[24];
6949 l
= micromips_target_label
;
6950 #ifdef LOCAL_LABEL_PREFIX
6951 *p
++ = LOCAL_LABEL_PREFIX
;
6954 *p
++ = MICROMIPS_LABEL_CHAR
;
6957 symbol_name_temporary
[i
++] = l
% 10 + '0';
6962 *p
++ = symbol_name_temporary
[--i
];
6965 return micromips_target_name
;
6969 micromips_label_expr (expressionS
*label_expr
)
6971 label_expr
->X_op
= O_symbol
;
6972 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6973 label_expr
->X_add_number
= 0;
6977 micromips_label_inc (void)
6979 micromips_target_label
++;
6980 *micromips_target_name
= '\0';
6984 micromips_add_label (void)
6988 s
= colon (micromips_label_name ());
6989 micromips_label_inc ();
6990 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6993 /* If assembling microMIPS code, then return the microMIPS reloc
6994 corresponding to the requested one if any. Otherwise return
6995 the reloc unchanged. */
6997 static bfd_reloc_code_real_type
6998 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7000 static const bfd_reloc_code_real_type relocs
[][2] =
7002 /* Keep sorted incrementally by the left-hand key. */
7003 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7004 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7005 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7006 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7007 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7008 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7009 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7010 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7011 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7012 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7013 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7014 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7015 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7016 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7017 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7018 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7019 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7020 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7021 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7022 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7023 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7024 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7025 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7026 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7027 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7028 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7029 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7031 bfd_reloc_code_real_type r
;
7034 if (!mips_opts
.micromips
)
7036 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7042 return relocs
[i
][1];
7047 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7048 Return true on success, storing the resolved value in RESULT. */
7051 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7056 case BFD_RELOC_MIPS_HIGHEST
:
7057 case BFD_RELOC_MICROMIPS_HIGHEST
:
7058 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7061 case BFD_RELOC_MIPS_HIGHER
:
7062 case BFD_RELOC_MICROMIPS_HIGHER
:
7063 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7066 case BFD_RELOC_HI16_S
:
7067 case BFD_RELOC_HI16_S_PCREL
:
7068 case BFD_RELOC_MICROMIPS_HI16_S
:
7069 case BFD_RELOC_MIPS16_HI16_S
:
7070 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7073 case BFD_RELOC_HI16
:
7074 case BFD_RELOC_MICROMIPS_HI16
:
7075 case BFD_RELOC_MIPS16_HI16
:
7076 *result
= (operand
>> 16) & 0xffff;
7079 case BFD_RELOC_LO16
:
7080 case BFD_RELOC_LO16_PCREL
:
7081 case BFD_RELOC_MICROMIPS_LO16
:
7082 case BFD_RELOC_MIPS16_LO16
:
7083 *result
= operand
& 0xffff;
7086 case BFD_RELOC_UNUSED
:
7095 /* Output an instruction. IP is the instruction information.
7096 ADDRESS_EXPR is an operand of the instruction to be used with
7097 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7098 a macro expansion. */
7101 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7102 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7104 unsigned long prev_pinfo2
, pinfo
;
7105 bfd_boolean relaxed_branch
= FALSE
;
7106 enum append_method method
;
7107 bfd_boolean relax32
;
7110 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7111 fix_loongson2f (ip
);
7113 file_ase_mips16
|= mips_opts
.mips16
;
7114 file_ase_micromips
|= mips_opts
.micromips
;
7116 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7117 pinfo
= ip
->insn_mo
->pinfo
;
7119 /* Don't raise alarm about `nods' frags as they'll fill in the right
7120 kind of nop in relaxation if required. */
7121 if (mips_opts
.micromips
7123 && !(history
[0].frag
7124 && history
[0].frag
->fr_type
== rs_machine_dependent
7125 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7126 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7127 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7128 && micromips_insn_length (ip
->insn_mo
) != 2)
7129 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7130 && micromips_insn_length (ip
->insn_mo
) != 4)))
7131 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7132 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7134 if (address_expr
== NULL
)
7136 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7137 && reloc_type
[1] == BFD_RELOC_UNUSED
7138 && reloc_type
[2] == BFD_RELOC_UNUSED
7139 && address_expr
->X_op
== O_constant
)
7141 switch (*reloc_type
)
7143 case BFD_RELOC_MIPS_JMP
:
7147 /* Shift is 2, unusually, for microMIPS JALX. */
7148 shift
= (mips_opts
.micromips
7149 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7150 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7151 as_bad (_("jump to misaligned address (0x%lx)"),
7152 (unsigned long) address_expr
->X_add_number
);
7153 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7159 case BFD_RELOC_MIPS16_JMP
:
7160 if ((address_expr
->X_add_number
& 3) != 0)
7161 as_bad (_("jump to misaligned address (0x%lx)"),
7162 (unsigned long) address_expr
->X_add_number
);
7164 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7165 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7166 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7170 case BFD_RELOC_16_PCREL_S2
:
7174 shift
= mips_opts
.micromips
? 1 : 2;
7175 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7176 as_bad (_("branch to misaligned address (0x%lx)"),
7177 (unsigned long) address_expr
->X_add_number
);
7178 if (!mips_relax_branch
)
7180 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7181 & ~((1 << (shift
+ 16)) - 1))
7182 as_bad (_("branch address range overflow (0x%lx)"),
7183 (unsigned long) address_expr
->X_add_number
);
7184 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7190 case BFD_RELOC_MIPS_21_PCREL_S2
:
7195 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7196 as_bad (_("branch to misaligned address (0x%lx)"),
7197 (unsigned long) address_expr
->X_add_number
);
7198 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7199 & ~((1 << (shift
+ 21)) - 1))
7200 as_bad (_("branch address range overflow (0x%lx)"),
7201 (unsigned long) address_expr
->X_add_number
);
7202 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7207 case BFD_RELOC_MIPS_26_PCREL_S2
:
7212 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7213 as_bad (_("branch to misaligned address (0x%lx)"),
7214 (unsigned long) address_expr
->X_add_number
);
7215 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7216 & ~((1 << (shift
+ 26)) - 1))
7217 as_bad (_("branch address range overflow (0x%lx)"),
7218 (unsigned long) address_expr
->X_add_number
);
7219 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7228 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7231 ip
->insn_opcode
|= value
& 0xffff;
7239 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7241 /* There are a lot of optimizations we could do that we don't.
7242 In particular, we do not, in general, reorder instructions.
7243 If you use gcc with optimization, it will reorder
7244 instructions and generally do much more optimization then we
7245 do here; repeating all that work in the assembler would only
7246 benefit hand written assembly code, and does not seem worth
7248 int nops
= (mips_optimize
== 0
7249 ? nops_for_insn (0, history
, NULL
)
7250 : nops_for_insn_or_target (0, history
, ip
));
7254 unsigned long old_frag_offset
;
7257 old_frag
= frag_now
;
7258 old_frag_offset
= frag_now_fix ();
7260 for (i
= 0; i
< nops
; i
++)
7261 add_fixed_insn (NOP_INSN
);
7262 insert_into_history (0, nops
, NOP_INSN
);
7266 listing_prev_line ();
7267 /* We may be at the start of a variant frag. In case we
7268 are, make sure there is enough space for the frag
7269 after the frags created by listing_prev_line. The
7270 argument to frag_grow here must be at least as large
7271 as the argument to all other calls to frag_grow in
7272 this file. We don't have to worry about being in the
7273 middle of a variant frag, because the variants insert
7274 all needed nop instructions themselves. */
7278 mips_move_text_labels ();
7280 #ifndef NO_ECOFF_DEBUGGING
7281 if (ECOFF_DEBUGGING
)
7282 ecoff_fix_loc (old_frag
, old_frag_offset
);
7286 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7290 /* Work out how many nops in prev_nop_frag are needed by IP,
7291 ignoring hazards generated by the first prev_nop_frag_since
7293 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7294 gas_assert (nops
<= prev_nop_frag_holds
);
7296 /* Enforce NOPS as a minimum. */
7297 if (nops
> prev_nop_frag_required
)
7298 prev_nop_frag_required
= nops
;
7300 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7302 /* Settle for the current number of nops. Update the history
7303 accordingly (for the benefit of any future .set reorder code). */
7304 prev_nop_frag
= NULL
;
7305 insert_into_history (prev_nop_frag_since
,
7306 prev_nop_frag_holds
, NOP_INSN
);
7310 /* Allow this instruction to replace one of the nops that was
7311 tentatively added to prev_nop_frag. */
7312 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7313 prev_nop_frag_holds
--;
7314 prev_nop_frag_since
++;
7318 method
= get_append_method (ip
, address_expr
, reloc_type
);
7319 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7321 dwarf2_emit_insn (0);
7322 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7323 so "move" the instruction address accordingly.
7325 Also, it doesn't seem appropriate for the assembler to reorder .loc
7326 entries. If this instruction is a branch that we are going to swap
7327 with the previous instruction, the two instructions should be
7328 treated as a unit, and the debug information for both instructions
7329 should refer to the start of the branch sequence. Using the
7330 current position is certainly wrong when swapping a 32-bit branch
7331 and a 16-bit delay slot, since the current position would then be
7332 in the middle of a branch. */
7333 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7335 relax32
= (mips_relax_branch
7336 /* Don't try branch relaxation within .set nomacro, or within
7337 .set noat if we use $at for PIC computations. If it turns
7338 out that the branch was out-of-range, we'll get an error. */
7339 && !mips_opts
.warn_about_macros
7340 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7341 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7342 as they have no complementing branches. */
7343 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7345 if (!HAVE_CODE_COMPRESSION
7348 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7349 && delayed_branch_p (ip
))
7351 relaxed_branch
= TRUE
;
7352 add_relaxed_insn (ip
, (relaxed_branch_length
7354 uncond_branch_p (ip
) ? -1
7355 : branch_likely_p (ip
) ? 1
7358 (AT
, mips_pic
!= NO_PIC
,
7359 uncond_branch_p (ip
),
7360 branch_likely_p (ip
),
7361 pinfo
& INSN_WRITE_GPR_31
,
7363 address_expr
->X_add_symbol
,
7364 address_expr
->X_add_number
);
7365 *reloc_type
= BFD_RELOC_UNUSED
;
7367 else if (mips_opts
.micromips
7369 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7370 || *reloc_type
> BFD_RELOC_UNUSED
)
7371 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7372 /* Don't try branch relaxation when users specify
7373 16-bit/32-bit instructions. */
7374 && !forced_insn_length
)
7376 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7377 && *reloc_type
> BFD_RELOC_UNUSED
);
7378 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7379 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7380 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7381 int nods
= method
== APPEND_ADD_WITH_NOP
;
7382 int al
= pinfo
& INSN_WRITE_GPR_31
;
7383 int length32
= nods
? 8 : 4;
7385 gas_assert (address_expr
!= NULL
);
7386 gas_assert (!mips_relax
.sequence
);
7388 relaxed_branch
= TRUE
;
7390 method
= APPEND_ADD
;
7392 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7393 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7394 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7396 uncond
, compact
, al
, nods
,
7398 address_expr
->X_add_symbol
,
7399 address_expr
->X_add_number
);
7400 *reloc_type
= BFD_RELOC_UNUSED
;
7402 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7404 bfd_boolean require_unextended
;
7405 bfd_boolean require_extended
;
7409 if (forced_insn_length
!= 0)
7411 require_unextended
= forced_insn_length
== 2;
7412 require_extended
= forced_insn_length
== 4;
7416 require_unextended
= (mips_opts
.noautoextend
7417 && !mips_opcode_32bit_p (ip
->insn_mo
));
7418 require_extended
= 0;
7421 /* We need to set up a variant frag. */
7422 gas_assert (address_expr
!= NULL
);
7423 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7424 symbol created by `make_expr_symbol' may not get a necessary
7425 external relocation produced. */
7426 if (address_expr
->X_op
== O_symbol
)
7428 symbol
= address_expr
->X_add_symbol
;
7429 offset
= address_expr
->X_add_number
;
7433 symbol
= make_expr_symbol (address_expr
);
7434 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7437 add_relaxed_insn (ip
, 12, 0,
7439 (*reloc_type
- BFD_RELOC_UNUSED
,
7442 mips_opts
.warn_about_macros
,
7443 require_unextended
, require_extended
,
7444 delayed_branch_p (&history
[0]),
7445 history
[0].mips16_absolute_jump_p
),
7448 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7450 if (!delayed_branch_p (ip
))
7451 /* Make sure there is enough room to swap this instruction with
7452 a following jump instruction. */
7454 add_fixed_insn (ip
);
7458 if (mips_opts
.mips16
7459 && mips_opts
.noreorder
7460 && delayed_branch_p (&history
[0]))
7461 as_warn (_("extended instruction in delay slot"));
7463 if (mips_relax
.sequence
)
7465 /* If we've reached the end of this frag, turn it into a variant
7466 frag and record the information for the instructions we've
7468 if (frag_room () < 4)
7469 relax_close_frag ();
7470 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7473 if (mips_relax
.sequence
!= 2)
7475 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7476 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7477 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7478 mips_macro_warning
.insns
[0]++;
7480 if (mips_relax
.sequence
!= 1)
7482 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7483 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7484 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7485 mips_macro_warning
.insns
[1]++;
7488 if (mips_opts
.mips16
)
7491 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7493 add_fixed_insn (ip
);
7496 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7498 bfd_reloc_code_real_type final_type
[3];
7499 reloc_howto_type
*howto0
;
7500 reloc_howto_type
*howto
;
7503 /* Perform any necessary conversion to microMIPS relocations
7504 and find out how many relocations there actually are. */
7505 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7506 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7508 /* In a compound relocation, it is the final (outermost)
7509 operator that determines the relocated field. */
7510 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7515 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7516 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7517 bfd_get_reloc_size (howto
),
7519 howto0
&& howto0
->pc_relative
,
7521 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7522 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7524 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7525 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7526 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7528 /* These relocations can have an addend that won't fit in
7529 4 octets for 64bit assembly. */
7531 && ! howto
->partial_inplace
7532 && (reloc_type
[0] == BFD_RELOC_16
7533 || reloc_type
[0] == BFD_RELOC_32
7534 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7535 || reloc_type
[0] == BFD_RELOC_GPREL16
7536 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7537 || reloc_type
[0] == BFD_RELOC_GPREL32
7538 || reloc_type
[0] == BFD_RELOC_64
7539 || reloc_type
[0] == BFD_RELOC_CTOR
7540 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7541 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7542 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7543 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7544 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7545 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7546 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7547 || hi16_reloc_p (reloc_type
[0])
7548 || lo16_reloc_p (reloc_type
[0])))
7549 ip
->fixp
[0]->fx_no_overflow
= 1;
7551 /* These relocations can have an addend that won't fit in 2 octets. */
7552 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7553 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7554 ip
->fixp
[0]->fx_no_overflow
= 1;
7556 if (mips_relax
.sequence
)
7558 if (mips_relax
.first_fixup
== 0)
7559 mips_relax
.first_fixup
= ip
->fixp
[0];
7561 else if (reloc_needs_lo_p (*reloc_type
))
7563 struct mips_hi_fixup
*hi_fixup
;
7565 /* Reuse the last entry if it already has a matching %lo. */
7566 hi_fixup
= mips_hi_fixup_list
;
7568 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7570 hi_fixup
= XNEW (struct mips_hi_fixup
);
7571 hi_fixup
->next
= mips_hi_fixup_list
;
7572 mips_hi_fixup_list
= hi_fixup
;
7574 hi_fixup
->fixp
= ip
->fixp
[0];
7575 hi_fixup
->seg
= now_seg
;
7578 /* Add fixups for the second and third relocations, if given.
7579 Note that the ABI allows the second relocation to be
7580 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7581 moment we only use RSS_UNDEF, but we could add support
7582 for the others if it ever becomes necessary. */
7583 for (i
= 1; i
< 3; i
++)
7584 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7586 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7587 ip
->fixp
[0]->fx_size
, NULL
, 0,
7588 FALSE
, final_type
[i
]);
7590 /* Use fx_tcbit to mark compound relocs. */
7591 ip
->fixp
[0]->fx_tcbit
= 1;
7592 ip
->fixp
[i
]->fx_tcbit
= 1;
7596 /* Update the register mask information. */
7597 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7598 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7603 insert_into_history (0, 1, ip
);
7606 case APPEND_ADD_WITH_NOP
:
7608 struct mips_cl_insn
*nop
;
7610 insert_into_history (0, 1, ip
);
7611 nop
= get_delay_slot_nop (ip
);
7612 add_fixed_insn (nop
);
7613 insert_into_history (0, 1, nop
);
7614 if (mips_relax
.sequence
)
7615 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7619 case APPEND_ADD_COMPACT
:
7620 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7621 if (mips_opts
.mips16
)
7623 ip
->insn_opcode
|= 0x0080;
7624 find_altered_mips16_opcode (ip
);
7626 /* Convert microMIPS instructions. */
7627 else if (mips_opts
.micromips
)
7630 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7631 ip
->insn_opcode
|= 0x0020;
7633 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7634 ip
->insn_opcode
= 0x40e00000;
7635 /* beqz16->beqzc, bnez16->bnezc */
7636 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7638 unsigned long regno
;
7640 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7641 regno
&= MICROMIPSOP_MASK_MD
;
7642 regno
= micromips_to_32_reg_d_map
[regno
];
7643 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7644 | (regno
<< MICROMIPSOP_SH_RS
)
7645 | 0x40a00000) ^ 0x00400000;
7647 /* beqz->beqzc, bnez->bnezc */
7648 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7649 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7650 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7651 | 0x40a00000) ^ 0x00400000;
7652 /* beq $0->beqzc, bne $0->bnezc */
7653 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7654 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7655 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7656 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7657 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7658 | 0x40a00000) ^ 0x00400000;
7661 find_altered_micromips_opcode (ip
);
7666 insert_into_history (0, 1, ip
);
7671 struct mips_cl_insn delay
= history
[0];
7673 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7675 /* Add the delay slot instruction to the end of the
7676 current frag and shrink the fixed part of the
7677 original frag. If the branch occupies the tail of
7678 the latter, move it backwards to cover the gap. */
7679 delay
.frag
->fr_fix
-= branch_disp
;
7680 if (delay
.frag
== ip
->frag
)
7681 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7682 add_fixed_insn (&delay
);
7686 /* If this is not a relaxed branch and we are in the
7687 same frag, then just swap the instructions. */
7688 move_insn (ip
, delay
.frag
, delay
.where
);
7689 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7693 insert_into_history (0, 1, &delay
);
7698 /* If we have just completed an unconditional branch, clear the history. */
7699 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7700 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7704 mips_no_prev_insn ();
7706 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7707 history
[i
].cleared_p
= 1;
7710 /* We need to emit a label at the end of branch-likely macros. */
7711 if (emit_branch_likely_macro
)
7713 emit_branch_likely_macro
= FALSE
;
7714 micromips_add_label ();
7717 /* We just output an insn, so the next one doesn't have a label. */
7718 mips_clear_insn_labels ();
7721 /* Forget that there was any previous instruction or label.
7722 When BRANCH is true, the branch history is also flushed. */
7725 mips_no_prev_insn (void)
7727 prev_nop_frag
= NULL
;
7728 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7729 mips_clear_insn_labels ();
7732 /* This function must be called before we emit something other than
7733 instructions. It is like mips_no_prev_insn except that it inserts
7734 any NOPS that might be needed by previous instructions. */
7737 mips_emit_delays (void)
7739 if (! mips_opts
.noreorder
)
7741 int nops
= nops_for_insn (0, history
, NULL
);
7745 add_fixed_insn (NOP_INSN
);
7746 mips_move_text_labels ();
7749 mips_no_prev_insn ();
7752 /* Start a (possibly nested) noreorder block. */
7755 start_noreorder (void)
7757 if (mips_opts
.noreorder
== 0)
7762 /* None of the instructions before the .set noreorder can be moved. */
7763 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7764 history
[i
].fixed_p
= 1;
7766 /* Insert any nops that might be needed between the .set noreorder
7767 block and the previous instructions. We will later remove any
7768 nops that turn out not to be needed. */
7769 nops
= nops_for_insn (0, history
, NULL
);
7772 if (mips_optimize
!= 0)
7774 /* Record the frag which holds the nop instructions, so
7775 that we can remove them if we don't need them. */
7776 frag_grow (nops
* NOP_INSN_SIZE
);
7777 prev_nop_frag
= frag_now
;
7778 prev_nop_frag_holds
= nops
;
7779 prev_nop_frag_required
= 0;
7780 prev_nop_frag_since
= 0;
7783 for (; nops
> 0; --nops
)
7784 add_fixed_insn (NOP_INSN
);
7786 /* Move on to a new frag, so that it is safe to simply
7787 decrease the size of prev_nop_frag. */
7788 frag_wane (frag_now
);
7790 mips_move_text_labels ();
7792 mips_mark_labels ();
7793 mips_clear_insn_labels ();
7795 mips_opts
.noreorder
++;
7796 mips_any_noreorder
= 1;
7799 /* End a nested noreorder block. */
7802 end_noreorder (void)
7804 mips_opts
.noreorder
--;
7805 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7807 /* Commit to inserting prev_nop_frag_required nops and go back to
7808 handling nop insertion the .set reorder way. */
7809 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7811 insert_into_history (prev_nop_frag_since
,
7812 prev_nop_frag_required
, NOP_INSN
);
7813 prev_nop_frag
= NULL
;
7817 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7818 higher bits unset. */
7821 normalize_constant_expr (expressionS
*ex
)
7823 if (ex
->X_op
== O_constant
7824 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7825 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7829 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7830 all higher bits unset. */
7833 normalize_address_expr (expressionS
*ex
)
7835 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7836 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7837 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7838 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7842 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7843 Return true if the match was successful.
7845 OPCODE_EXTRA is a value that should be ORed into the opcode
7846 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7847 there are more alternatives after OPCODE and SOFT_MATCH is
7848 as for mips_arg_info. */
7851 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7852 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7853 bfd_boolean lax_match
, bfd_boolean complete_p
)
7856 struct mips_arg_info arg
;
7857 const struct mips_operand
*operand
;
7860 imm_expr
.X_op
= O_absent
;
7861 offset_expr
.X_op
= O_absent
;
7862 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7863 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7864 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7866 create_insn (insn
, opcode
);
7867 /* When no opcode suffix is specified, assume ".xyzw". */
7868 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7869 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7871 insn
->insn_opcode
|= opcode_extra
;
7872 memset (&arg
, 0, sizeof (arg
));
7876 arg
.last_regno
= ILLEGAL_REG
;
7877 arg
.dest_regno
= ILLEGAL_REG
;
7878 arg
.lax_match
= lax_match
;
7879 for (args
= opcode
->args
;; ++args
)
7881 if (arg
.token
->type
== OT_END
)
7883 /* Handle unary instructions in which only one operand is given.
7884 The source is then the same as the destination. */
7885 if (arg
.opnum
== 1 && *args
== ',')
7887 operand
= (mips_opts
.micromips
7888 ? decode_micromips_operand (args
+ 1)
7889 : decode_mips_operand (args
+ 1));
7890 if (operand
&& mips_optional_operand_p (operand
))
7898 /* Treat elided base registers as $0. */
7899 if (strcmp (args
, "(b)") == 0)
7907 /* The register suffix is optional. */
7912 /* Fail the match if there were too few operands. */
7916 /* Successful match. */
7919 clear_insn_error ();
7920 if (arg
.dest_regno
== arg
.last_regno
7921 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7925 (0, _("source and destination must be different"));
7926 else if (arg
.last_regno
== 31)
7928 (0, _("a destination register must be supplied"));
7930 else if (arg
.last_regno
== 31
7931 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7932 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7933 set_insn_error (0, _("the source register must not be $31"));
7934 check_completed_insn (&arg
);
7938 /* Fail the match if the line has too many operands. */
7942 /* Handle characters that need to match exactly. */
7943 if (*args
== '(' || *args
== ')' || *args
== ',')
7945 if (match_char (&arg
, *args
))
7952 if (arg
.token
->type
== OT_DOUBLE_CHAR
7953 && arg
.token
->u
.ch
== *args
)
7961 /* Handle special macro operands. Work out the properties of
7970 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7974 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7983 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7987 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
7991 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
7997 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7999 imm_expr
.X_op
= O_constant
;
8001 normalize_constant_expr (&imm_expr
);
8005 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8007 /* Assume that the offset has been elided and that what
8008 we saw was a base register. The match will fail later
8009 if that assumption turns out to be wrong. */
8010 offset_expr
.X_op
= O_constant
;
8011 offset_expr
.X_add_number
= 0;
8015 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8017 normalize_address_expr (&offset_expr
);
8022 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8028 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8034 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8040 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8046 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8050 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8054 gas_assert (mips_opts
.micromips
);
8060 if (!forced_insn_length
)
8061 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8063 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8065 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8071 operand
= (mips_opts
.micromips
8072 ? decode_micromips_operand (args
)
8073 : decode_mips_operand (args
));
8077 /* Skip prefixes. */
8078 if (*args
== '+' || *args
== 'm' || *args
== '-')
8081 if (mips_optional_operand_p (operand
)
8083 && (arg
.token
[0].type
!= OT_REG
8084 || arg
.token
[1].type
== OT_END
))
8086 /* Assume that the register has been elided and is the
8087 same as the first operand. */
8092 if (!match_operand (&arg
, operand
))
8097 /* Like match_insn, but for MIPS16. */
8100 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8101 struct mips_operand_token
*tokens
)
8104 const struct mips_operand
*operand
;
8105 const struct mips_operand
*ext_operand
;
8106 bfd_boolean pcrel
= FALSE
;
8107 int required_insn_length
;
8108 struct mips_arg_info arg
;
8111 if (forced_insn_length
)
8112 required_insn_length
= forced_insn_length
;
8113 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8114 required_insn_length
= 2;
8116 required_insn_length
= 0;
8118 create_insn (insn
, opcode
);
8119 imm_expr
.X_op
= O_absent
;
8120 offset_expr
.X_op
= O_absent
;
8121 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8122 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8123 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8126 memset (&arg
, 0, sizeof (arg
));
8130 arg
.last_regno
= ILLEGAL_REG
;
8131 arg
.dest_regno
= ILLEGAL_REG
;
8133 for (args
= opcode
->args
;; ++args
)
8137 if (arg
.token
->type
== OT_END
)
8141 /* Handle unary instructions in which only one operand is given.
8142 The source is then the same as the destination. */
8143 if (arg
.opnum
== 1 && *args
== ',')
8145 operand
= decode_mips16_operand (args
[1], FALSE
);
8146 if (operand
&& mips_optional_operand_p (operand
))
8154 /* Fail the match if there were too few operands. */
8158 /* Successful match. Stuff the immediate value in now, if
8160 clear_insn_error ();
8161 if (opcode
->pinfo
== INSN_MACRO
)
8163 gas_assert (relax_char
== 0 || relax_char
== 'p');
8164 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8167 && offset_expr
.X_op
== O_constant
8169 && calculate_reloc (*offset_reloc
,
8170 offset_expr
.X_add_number
,
8173 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8174 required_insn_length
, &insn
->insn_opcode
);
8175 offset_expr
.X_op
= O_absent
;
8176 *offset_reloc
= BFD_RELOC_UNUSED
;
8178 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8180 if (required_insn_length
== 2)
8181 set_insn_error (0, _("invalid unextended operand value"));
8184 forced_insn_length
= 4;
8185 insn
->insn_opcode
|= MIPS16_EXTEND
;
8188 else if (relax_char
)
8189 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8191 check_completed_insn (&arg
);
8195 /* Fail the match if the line has too many operands. */
8199 /* Handle characters that need to match exactly. */
8200 if (*args
== '(' || *args
== ')' || *args
== ',')
8202 if (match_char (&arg
, *args
))
8220 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8222 imm_expr
.X_op
= O_constant
;
8224 normalize_constant_expr (&imm_expr
);
8229 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8233 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8237 if (operand
->type
== OP_PCREL
)
8241 ext_operand
= decode_mips16_operand (c
, TRUE
);
8242 if (operand
!= ext_operand
)
8244 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8246 offset_expr
.X_op
= O_constant
;
8247 offset_expr
.X_add_number
= 0;
8252 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8255 /* '8' is used for SLTI(U) and has traditionally not
8256 been allowed to take relocation operators. */
8257 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8258 && (ext_operand
->size
!= 16 || c
== '8'))
8260 match_not_constant (&arg
);
8269 if (mips_optional_operand_p (operand
)
8271 && (arg
.token
[0].type
!= OT_REG
8272 || arg
.token
[1].type
== OT_END
))
8274 /* Assume that the register has been elided and is the
8275 same as the first operand. */
8280 if (!match_operand (&arg
, operand
))
8285 /* Record that the current instruction is invalid for the current ISA. */
8288 match_invalid_for_isa (void)
8291 (0, _("opcode not supported on this processor: %s (%s)"),
8292 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8293 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8296 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8297 Return true if a definite match or failure was found, storing any match
8298 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8299 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8300 tried and failed to match under normal conditions and now want to try a
8301 more relaxed match. */
8304 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8305 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8306 int opcode_extra
, bfd_boolean lax_match
)
8308 const struct mips_opcode
*opcode
;
8309 const struct mips_opcode
*invalid_delay_slot
;
8310 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8312 /* Search for a match, ignoring alternatives that don't satisfy the
8313 current ISA or forced_length. */
8314 invalid_delay_slot
= 0;
8315 seen_valid_for_isa
= FALSE
;
8316 seen_valid_for_size
= FALSE
;
8320 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8321 if (is_opcode_valid (opcode
))
8323 seen_valid_for_isa
= TRUE
;
8324 if (is_size_valid (opcode
))
8326 bfd_boolean delay_slot_ok
;
8328 seen_valid_for_size
= TRUE
;
8329 delay_slot_ok
= is_delay_slot_valid (opcode
);
8330 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8331 lax_match
, delay_slot_ok
))
8335 if (!invalid_delay_slot
)
8336 invalid_delay_slot
= opcode
;
8345 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8347 /* If the only matches we found had the wrong length for the delay slot,
8348 pick the first such match. We'll issue an appropriate warning later. */
8349 if (invalid_delay_slot
)
8351 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8357 /* Handle the case where we didn't try to match an instruction because
8358 all the alternatives were incompatible with the current ISA. */
8359 if (!seen_valid_for_isa
)
8361 match_invalid_for_isa ();
8365 /* Handle the case where we didn't try to match an instruction because
8366 all the alternatives were of the wrong size. */
8367 if (!seen_valid_for_size
)
8369 if (mips_opts
.insn32
)
8370 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8373 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8374 8 * forced_insn_length
);
8381 /* Like match_insns, but for MIPS16. */
8384 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8385 struct mips_operand_token
*tokens
)
8387 const struct mips_opcode
*opcode
;
8388 bfd_boolean seen_valid_for_isa
;
8389 bfd_boolean seen_valid_for_size
;
8391 /* Search for a match, ignoring alternatives that don't satisfy the
8392 current ISA. There are no separate entries for extended forms so
8393 we deal with forced_length later. */
8394 seen_valid_for_isa
= FALSE
;
8395 seen_valid_for_size
= FALSE
;
8399 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8400 if (is_opcode_valid_16 (opcode
))
8402 seen_valid_for_isa
= TRUE
;
8403 if (is_size_valid_16 (opcode
))
8405 seen_valid_for_size
= TRUE
;
8406 if (match_mips16_insn (insn
, opcode
, tokens
))
8412 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8413 && strcmp (opcode
->name
, first
->name
) == 0);
8415 /* Handle the case where we didn't try to match an instruction because
8416 all the alternatives were incompatible with the current ISA. */
8417 if (!seen_valid_for_isa
)
8419 match_invalid_for_isa ();
8423 /* Handle the case where we didn't try to match an instruction because
8424 all the alternatives were of the wrong size. */
8425 if (!seen_valid_for_size
)
8427 if (forced_insn_length
== 2)
8429 (0, _("unrecognized unextended version of MIPS16 opcode"));
8432 (0, _("unrecognized extended version of MIPS16 opcode"));
8439 /* Set up global variables for the start of a new macro. */
8444 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8445 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8446 sizeof (mips_macro_warning
.first_insn_sizes
));
8447 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8448 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8449 && delayed_branch_p (&history
[0]));
8451 && history
[0].frag
->fr_type
== rs_machine_dependent
8452 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8453 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8454 mips_macro_warning
.delay_slot_length
= 0;
8456 switch (history
[0].insn_mo
->pinfo2
8457 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8459 case INSN2_BRANCH_DELAY_32BIT
:
8460 mips_macro_warning
.delay_slot_length
= 4;
8462 case INSN2_BRANCH_DELAY_16BIT
:
8463 mips_macro_warning
.delay_slot_length
= 2;
8466 mips_macro_warning
.delay_slot_length
= 0;
8469 mips_macro_warning
.first_frag
= NULL
;
8472 /* Given that a macro is longer than one instruction or of the wrong size,
8473 return the appropriate warning for it. Return null if no warning is
8474 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8475 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8476 and RELAX_NOMACRO. */
8479 macro_warning (relax_substateT subtype
)
8481 if (subtype
& RELAX_DELAY_SLOT
)
8482 return _("macro instruction expanded into multiple instructions"
8483 " in a branch delay slot");
8484 else if (subtype
& RELAX_NOMACRO
)
8485 return _("macro instruction expanded into multiple instructions");
8486 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8487 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8488 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8489 ? _("macro instruction expanded into a wrong size instruction"
8490 " in a 16-bit branch delay slot")
8491 : _("macro instruction expanded into a wrong size instruction"
8492 " in a 32-bit branch delay slot"));
8497 /* Finish up a macro. Emit warnings as appropriate. */
8502 /* Relaxation warning flags. */
8503 relax_substateT subtype
= 0;
8505 /* Check delay slot size requirements. */
8506 if (mips_macro_warning
.delay_slot_length
== 2)
8507 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8508 if (mips_macro_warning
.delay_slot_length
!= 0)
8510 if (mips_macro_warning
.delay_slot_length
8511 != mips_macro_warning
.first_insn_sizes
[0])
8512 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8513 if (mips_macro_warning
.delay_slot_length
8514 != mips_macro_warning
.first_insn_sizes
[1])
8515 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8518 /* Check instruction count requirements. */
8519 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8521 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8522 subtype
|= RELAX_SECOND_LONGER
;
8523 if (mips_opts
.warn_about_macros
)
8524 subtype
|= RELAX_NOMACRO
;
8525 if (mips_macro_warning
.delay_slot_p
)
8526 subtype
|= RELAX_DELAY_SLOT
;
8529 /* If both alternatives fail to fill a delay slot correctly,
8530 emit the warning now. */
8531 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8532 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8537 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8538 | RELAX_DELAY_SLOT_SIZE_FIRST
8539 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8540 msg
= macro_warning (s
);
8542 as_warn ("%s", msg
);
8546 /* If both implementations are longer than 1 instruction, then emit the
8548 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8553 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8554 msg
= macro_warning (s
);
8556 as_warn ("%s", msg
);
8560 /* If any flags still set, then one implementation might need a warning
8561 and the other either will need one of a different kind or none at all.
8562 Pass any remaining flags over to relaxation. */
8563 if (mips_macro_warning
.first_frag
!= NULL
)
8564 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8567 /* Instruction operand formats used in macros that vary between
8568 standard MIPS and microMIPS code. */
8570 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8571 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8572 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8573 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8574 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8575 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8576 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8577 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8579 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8580 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8581 : cop12_fmt[mips_opts.micromips])
8582 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8583 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8584 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8585 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8586 : mem12_fmt[mips_opts.micromips])
8587 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8588 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8589 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8591 /* Read a macro's relocation codes from *ARGS and store them in *R.
8592 The first argument in *ARGS will be either the code for a single
8593 relocation or -1 followed by the three codes that make up a
8594 composite relocation. */
8597 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8601 next
= va_arg (*args
, int);
8603 r
[0] = (bfd_reloc_code_real_type
) next
;
8606 for (i
= 0; i
< 3; i
++)
8607 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8608 /* This function is only used for 16-bit relocation fields.
8609 To make the macro code simpler, treat an unrelocated value
8610 in the same way as BFD_RELOC_LO16. */
8611 if (r
[0] == BFD_RELOC_UNUSED
)
8612 r
[0] = BFD_RELOC_LO16
;
8616 /* Build an instruction created by a macro expansion. This is passed
8617 a pointer to the count of instructions created so far, an
8618 expression, the name of the instruction to build, an operand format
8619 string, and corresponding arguments. */
8622 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8624 const struct mips_opcode
*mo
= NULL
;
8625 bfd_reloc_code_real_type r
[3];
8626 const struct mips_opcode
*amo
;
8627 const struct mips_operand
*operand
;
8628 struct hash_control
*hash
;
8629 struct mips_cl_insn insn
;
8633 va_start (args
, fmt
);
8635 if (mips_opts
.mips16
)
8637 mips16_macro_build (ep
, name
, fmt
, &args
);
8642 r
[0] = BFD_RELOC_UNUSED
;
8643 r
[1] = BFD_RELOC_UNUSED
;
8644 r
[2] = BFD_RELOC_UNUSED
;
8645 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8646 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8648 gas_assert (strcmp (name
, amo
->name
) == 0);
8652 /* Search until we get a match for NAME. It is assumed here that
8653 macros will never generate MDMX, MIPS-3D, or MT instructions.
8654 We try to match an instruction that fulfills the branch delay
8655 slot instruction length requirement (if any) of the previous
8656 instruction. While doing this we record the first instruction
8657 seen that matches all the other conditions and use it anyway
8658 if the requirement cannot be met; we will issue an appropriate
8659 warning later on. */
8660 if (strcmp (fmt
, amo
->args
) == 0
8661 && amo
->pinfo
!= INSN_MACRO
8662 && is_opcode_valid (amo
)
8663 && is_size_valid (amo
))
8665 if (is_delay_slot_valid (amo
))
8675 gas_assert (amo
->name
);
8677 while (strcmp (name
, amo
->name
) == 0);
8680 create_insn (&insn
, mo
);
8693 macro_read_relocs (&args
, r
);
8694 gas_assert (*r
== BFD_RELOC_GPREL16
8695 || *r
== BFD_RELOC_MIPS_HIGHER
8696 || *r
== BFD_RELOC_HI16_S
8697 || *r
== BFD_RELOC_LO16
8698 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8702 macro_read_relocs (&args
, r
);
8706 macro_read_relocs (&args
, r
);
8707 gas_assert (ep
!= NULL
8708 && (ep
->X_op
== O_constant
8709 || (ep
->X_op
== O_symbol
8710 && (*r
== BFD_RELOC_MIPS_HIGHEST
8711 || *r
== BFD_RELOC_HI16_S
8712 || *r
== BFD_RELOC_HI16
8713 || *r
== BFD_RELOC_GPREL16
8714 || *r
== BFD_RELOC_MIPS_GOT_HI16
8715 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8719 gas_assert (ep
!= NULL
);
8722 * This allows macro() to pass an immediate expression for
8723 * creating short branches without creating a symbol.
8725 * We don't allow branch relaxation for these branches, as
8726 * they should only appear in ".set nomacro" anyway.
8728 if (ep
->X_op
== O_constant
)
8730 /* For microMIPS we always use relocations for branches.
8731 So we should not resolve immediate values. */
8732 gas_assert (!mips_opts
.micromips
);
8734 if ((ep
->X_add_number
& 3) != 0)
8735 as_bad (_("branch to misaligned address (0x%lx)"),
8736 (unsigned long) ep
->X_add_number
);
8737 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8738 as_bad (_("branch address range overflow (0x%lx)"),
8739 (unsigned long) ep
->X_add_number
);
8740 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8744 *r
= BFD_RELOC_16_PCREL_S2
;
8748 gas_assert (ep
!= NULL
);
8749 *r
= BFD_RELOC_MIPS_JMP
;
8753 operand
= (mips_opts
.micromips
8754 ? decode_micromips_operand (fmt
)
8755 : decode_mips_operand (fmt
));
8759 uval
= va_arg (args
, int);
8760 if (operand
->type
== OP_CLO_CLZ_DEST
)
8761 uval
|= (uval
<< 5);
8762 insn_insert_operand (&insn
, operand
, uval
);
8764 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8770 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8772 append_insn (&insn
, ep
, r
, TRUE
);
8776 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8779 struct mips_opcode
*mo
;
8780 struct mips_cl_insn insn
;
8781 const struct mips_operand
*operand
;
8782 bfd_reloc_code_real_type r
[3]
8783 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8785 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8787 gas_assert (strcmp (name
, mo
->name
) == 0);
8789 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8792 gas_assert (mo
->name
);
8793 gas_assert (strcmp (name
, mo
->name
) == 0);
8796 create_insn (&insn
, mo
);
8833 gas_assert (ep
!= NULL
);
8835 if (ep
->X_op
!= O_constant
)
8836 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8837 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8839 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8841 *r
= BFD_RELOC_UNUSED
;
8847 operand
= decode_mips16_operand (c
, FALSE
);
8851 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8856 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8858 append_insn (&insn
, ep
, r
, TRUE
);
8862 * Generate a "jalr" instruction with a relocation hint to the called
8863 * function. This occurs in NewABI PIC code.
8866 macro_build_jalr (expressionS
*ep
, int cprestore
)
8868 static const bfd_reloc_code_real_type jalr_relocs
[2]
8869 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8870 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8874 if (MIPS_JALR_HINT_P (ep
))
8879 if (mips_opts
.micromips
)
8881 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8882 ? "jalr" : "jalrs");
8883 if (MIPS_JALR_HINT_P (ep
)
8885 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8886 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8888 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8891 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8892 if (MIPS_JALR_HINT_P (ep
))
8893 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8897 * Generate a "lui" instruction.
8900 macro_build_lui (expressionS
*ep
, int regnum
)
8902 gas_assert (! mips_opts
.mips16
);
8904 if (ep
->X_op
!= O_constant
)
8906 gas_assert (ep
->X_op
== O_symbol
);
8907 /* _gp_disp is a special case, used from s_cpload.
8908 __gnu_local_gp is used if mips_no_shared. */
8909 gas_assert (mips_pic
== NO_PIC
8911 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8912 || (! mips_in_shared
8913 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8914 "__gnu_local_gp") == 0));
8917 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8920 /* Generate a sequence of instructions to do a load or store from a constant
8921 offset off of a base register (breg) into/from a target register (treg),
8922 using AT if necessary. */
8924 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8925 int treg
, int breg
, int dbl
)
8927 gas_assert (ep
->X_op
== O_constant
);
8929 /* Sign-extending 32-bit constants makes their handling easier. */
8931 normalize_constant_expr (ep
);
8933 /* Right now, this routine can only handle signed 32-bit constants. */
8934 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8935 as_warn (_("operand overflow"));
8937 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8939 /* Signed 16-bit offset will fit in the op. Easy! */
8940 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8944 /* 32-bit offset, need multiple instructions and AT, like:
8945 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8946 addu $tempreg,$tempreg,$breg
8947 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8948 to handle the complete offset. */
8949 macro_build_lui (ep
, AT
);
8950 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8951 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8954 as_bad (_("macro used $at after \".set noat\""));
8959 * Generates code to set the $at register to true (one)
8960 * if reg is less than the immediate expression.
8963 set_at (int reg
, int unsignedp
)
8965 if (imm_expr
.X_add_number
>= -0x8000
8966 && imm_expr
.X_add_number
< 0x8000)
8967 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8968 AT
, reg
, BFD_RELOC_LO16
);
8971 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8972 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8976 /* Count the leading zeroes by performing a binary chop. This is a
8977 bulky bit of source, but performance is a LOT better for the
8978 majority of values than a simple loop to count the bits:
8979 for (lcnt = 0; (lcnt < 32); lcnt++)
8980 if ((v) & (1 << (31 - lcnt)))
8982 However it is not code size friendly, and the gain will drop a bit
8983 on certain cached systems.
8985 #define COUNT_TOP_ZEROES(v) \
8986 (((v) & ~0xffff) == 0 \
8987 ? ((v) & ~0xff) == 0 \
8988 ? ((v) & ~0xf) == 0 \
8989 ? ((v) & ~0x3) == 0 \
8990 ? ((v) & ~0x1) == 0 \
8995 : ((v) & ~0x7) == 0 \
8998 : ((v) & ~0x3f) == 0 \
8999 ? ((v) & ~0x1f) == 0 \
9002 : ((v) & ~0x7f) == 0 \
9005 : ((v) & ~0xfff) == 0 \
9006 ? ((v) & ~0x3ff) == 0 \
9007 ? ((v) & ~0x1ff) == 0 \
9010 : ((v) & ~0x7ff) == 0 \
9013 : ((v) & ~0x3fff) == 0 \
9014 ? ((v) & ~0x1fff) == 0 \
9017 : ((v) & ~0x7fff) == 0 \
9020 : ((v) & ~0xffffff) == 0 \
9021 ? ((v) & ~0xfffff) == 0 \
9022 ? ((v) & ~0x3ffff) == 0 \
9023 ? ((v) & ~0x1ffff) == 0 \
9026 : ((v) & ~0x7ffff) == 0 \
9029 : ((v) & ~0x3fffff) == 0 \
9030 ? ((v) & ~0x1fffff) == 0 \
9033 : ((v) & ~0x7fffff) == 0 \
9036 : ((v) & ~0xfffffff) == 0 \
9037 ? ((v) & ~0x3ffffff) == 0 \
9038 ? ((v) & ~0x1ffffff) == 0 \
9041 : ((v) & ~0x7ffffff) == 0 \
9044 : ((v) & ~0x3fffffff) == 0 \
9045 ? ((v) & ~0x1fffffff) == 0 \
9048 : ((v) & ~0x7fffffff) == 0 \
9053 * This routine generates the least number of instructions necessary to load
9054 * an absolute expression value into a register.
9057 load_register (int reg
, expressionS
*ep
, int dbl
)
9060 expressionS hi32
, lo32
;
9062 if (ep
->X_op
!= O_big
)
9064 gas_assert (ep
->X_op
== O_constant
);
9066 /* Sign-extending 32-bit constants makes their handling easier. */
9068 normalize_constant_expr (ep
);
9070 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9072 /* We can handle 16 bit signed values with an addiu to
9073 $zero. No need to ever use daddiu here, since $zero and
9074 the result are always correct in 32 bit mode. */
9075 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9078 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9080 /* We can handle 16 bit unsigned values with an ori to
9082 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9085 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9087 /* 32 bit values require an lui. */
9088 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9089 if ((ep
->X_add_number
& 0xffff) != 0)
9090 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9095 /* The value is larger than 32 bits. */
9097 if (!dbl
|| GPR_SIZE
== 32)
9101 sprintf_vma (value
, ep
->X_add_number
);
9102 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9103 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9107 if (ep
->X_op
!= O_big
)
9110 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9111 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9112 hi32
.X_add_number
&= 0xffffffff;
9114 lo32
.X_add_number
&= 0xffffffff;
9118 gas_assert (ep
->X_add_number
> 2);
9119 if (ep
->X_add_number
== 3)
9120 generic_bignum
[3] = 0;
9121 else if (ep
->X_add_number
> 4)
9122 as_bad (_("number larger than 64 bits"));
9123 lo32
.X_op
= O_constant
;
9124 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9125 hi32
.X_op
= O_constant
;
9126 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9129 if (hi32
.X_add_number
== 0)
9134 unsigned long hi
, lo
;
9136 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9138 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9140 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9143 if (lo32
.X_add_number
& 0x80000000)
9145 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9146 if (lo32
.X_add_number
& 0xffff)
9147 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9152 /* Check for 16bit shifted constant. We know that hi32 is
9153 non-zero, so start the mask on the first bit of the hi32
9158 unsigned long himask
, lomask
;
9162 himask
= 0xffff >> (32 - shift
);
9163 lomask
= (0xffff << shift
) & 0xffffffff;
9167 himask
= 0xffff << (shift
- 32);
9170 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9171 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9175 tmp
.X_op
= O_constant
;
9177 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9178 | (lo32
.X_add_number
>> shift
));
9180 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9181 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9182 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9183 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9188 while (shift
<= (64 - 16));
9190 /* Find the bit number of the lowest one bit, and store the
9191 shifted value in hi/lo. */
9192 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9193 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9197 while ((lo
& 1) == 0)
9202 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9208 while ((hi
& 1) == 0)
9217 /* Optimize if the shifted value is a (power of 2) - 1. */
9218 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9219 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9221 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9226 /* This instruction will set the register to be all
9228 tmp
.X_op
= O_constant
;
9229 tmp
.X_add_number
= (offsetT
) -1;
9230 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9234 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9235 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9237 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9238 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9243 /* Sign extend hi32 before calling load_register, because we can
9244 generally get better code when we load a sign extended value. */
9245 if ((hi32
.X_add_number
& 0x80000000) != 0)
9246 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9247 load_register (reg
, &hi32
, 0);
9250 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9254 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9262 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9264 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9265 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9271 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9275 mid16
.X_add_number
>>= 16;
9276 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9277 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9280 if ((lo32
.X_add_number
& 0xffff) != 0)
9281 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9285 load_delay_nop (void)
9287 if (!gpr_interlocks
)
9288 macro_build (NULL
, "nop", "");
9291 /* Load an address into a register. */
9294 load_address (int reg
, expressionS
*ep
, int *used_at
)
9296 if (ep
->X_op
!= O_constant
9297 && ep
->X_op
!= O_symbol
)
9299 as_bad (_("expression too complex"));
9300 ep
->X_op
= O_constant
;
9303 if (ep
->X_op
== O_constant
)
9305 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9309 if (mips_pic
== NO_PIC
)
9311 /* If this is a reference to a GP relative symbol, we want
9312 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9314 lui $reg,<sym> (BFD_RELOC_HI16_S)
9315 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9316 If we have an addend, we always use the latter form.
9318 With 64bit address space and a usable $at we want
9319 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9320 lui $at,<sym> (BFD_RELOC_HI16_S)
9321 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9322 daddiu $at,<sym> (BFD_RELOC_LO16)
9326 If $at is already in use, we use a path which is suboptimal
9327 on superscalar processors.
9328 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9329 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9331 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9333 daddiu $reg,<sym> (BFD_RELOC_LO16)
9335 For GP relative symbols in 64bit address space we can use
9336 the same sequence as in 32bit address space. */
9337 if (HAVE_64BIT_SYMBOLS
)
9339 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9340 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9342 relax_start (ep
->X_add_symbol
);
9343 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9344 mips_gp_register
, BFD_RELOC_GPREL16
);
9348 if (*used_at
== 0 && mips_opts
.at
)
9350 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9351 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9352 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9353 BFD_RELOC_MIPS_HIGHER
);
9354 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9355 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9356 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9361 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9362 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9363 BFD_RELOC_MIPS_HIGHER
);
9364 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9365 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9366 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9367 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9370 if (mips_relax
.sequence
)
9375 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9376 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9378 relax_start (ep
->X_add_symbol
);
9379 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9380 mips_gp_register
, BFD_RELOC_GPREL16
);
9383 macro_build_lui (ep
, reg
);
9384 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9385 reg
, reg
, BFD_RELOC_LO16
);
9386 if (mips_relax
.sequence
)
9390 else if (!mips_big_got
)
9394 /* If this is a reference to an external symbol, we want
9395 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9397 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9399 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9400 If there is a constant, it must be added in after.
9402 If we have NewABI, we want
9403 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9404 unless we're referencing a global symbol with a non-zero
9405 offset, in which case cst must be added separately. */
9408 if (ep
->X_add_number
)
9410 ex
.X_add_number
= ep
->X_add_number
;
9411 ep
->X_add_number
= 0;
9412 relax_start (ep
->X_add_symbol
);
9413 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9414 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9415 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9416 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9417 ex
.X_op
= O_constant
;
9418 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9419 reg
, reg
, BFD_RELOC_LO16
);
9420 ep
->X_add_number
= ex
.X_add_number
;
9423 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9424 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9425 if (mips_relax
.sequence
)
9430 ex
.X_add_number
= ep
->X_add_number
;
9431 ep
->X_add_number
= 0;
9432 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9433 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9435 relax_start (ep
->X_add_symbol
);
9437 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9441 if (ex
.X_add_number
!= 0)
9443 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9444 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9445 ex
.X_op
= O_constant
;
9446 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9447 reg
, reg
, BFD_RELOC_LO16
);
9451 else if (mips_big_got
)
9455 /* This is the large GOT case. If this is a reference to an
9456 external symbol, we want
9457 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9459 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9461 Otherwise, for a reference to a local symbol in old ABI, we want
9462 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9464 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9465 If there is a constant, it must be added in after.
9467 In the NewABI, for local symbols, with or without offsets, we want:
9468 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9469 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9473 ex
.X_add_number
= ep
->X_add_number
;
9474 ep
->X_add_number
= 0;
9475 relax_start (ep
->X_add_symbol
);
9476 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9477 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9478 reg
, reg
, mips_gp_register
);
9479 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9480 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9481 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9482 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9483 else if (ex
.X_add_number
)
9485 ex
.X_op
= O_constant
;
9486 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9490 ep
->X_add_number
= ex
.X_add_number
;
9492 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9493 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9494 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9495 BFD_RELOC_MIPS_GOT_OFST
);
9500 ex
.X_add_number
= ep
->X_add_number
;
9501 ep
->X_add_number
= 0;
9502 relax_start (ep
->X_add_symbol
);
9503 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9504 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9505 reg
, reg
, mips_gp_register
);
9506 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9507 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9509 if (reg_needs_delay (mips_gp_register
))
9511 /* We need a nop before loading from $gp. This special
9512 check is required because the lui which starts the main
9513 instruction stream does not refer to $gp, and so will not
9514 insert the nop which may be required. */
9515 macro_build (NULL
, "nop", "");
9517 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9518 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9520 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9524 if (ex
.X_add_number
!= 0)
9526 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9527 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9528 ex
.X_op
= O_constant
;
9529 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9537 if (!mips_opts
.at
&& *used_at
== 1)
9538 as_bad (_("macro used $at after \".set noat\""));
9541 /* Move the contents of register SOURCE into register DEST. */
9544 move_register (int dest
, int source
)
9546 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9547 instruction specifically requires a 32-bit one. */
9548 if (mips_opts
.micromips
9549 && !mips_opts
.insn32
9550 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9551 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9553 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9556 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9557 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9558 The two alternatives are:
9560 Global symbol Local symbol
9561 ------------- ------------
9562 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9564 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9566 load_got_offset emits the first instruction and add_got_offset
9567 emits the second for a 16-bit offset or add_got_offset_hilo emits
9568 a sequence to add a 32-bit offset using a scratch register. */
9571 load_got_offset (int dest
, expressionS
*local
)
9576 global
.X_add_number
= 0;
9578 relax_start (local
->X_add_symbol
);
9579 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9580 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9582 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9583 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9588 add_got_offset (int dest
, expressionS
*local
)
9592 global
.X_op
= O_constant
;
9593 global
.X_op_symbol
= NULL
;
9594 global
.X_add_symbol
= NULL
;
9595 global
.X_add_number
= local
->X_add_number
;
9597 relax_start (local
->X_add_symbol
);
9598 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9599 dest
, dest
, BFD_RELOC_LO16
);
9601 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9606 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9609 int hold_mips_optimize
;
9611 global
.X_op
= O_constant
;
9612 global
.X_op_symbol
= NULL
;
9613 global
.X_add_symbol
= NULL
;
9614 global
.X_add_number
= local
->X_add_number
;
9616 relax_start (local
->X_add_symbol
);
9617 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9619 /* Set mips_optimize around the lui instruction to avoid
9620 inserting an unnecessary nop after the lw. */
9621 hold_mips_optimize
= mips_optimize
;
9623 macro_build_lui (&global
, tmp
);
9624 mips_optimize
= hold_mips_optimize
;
9625 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9628 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9631 /* Emit a sequence of instructions to emulate a branch likely operation.
9632 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9633 is its complementing branch with the original condition negated.
9634 CALL is set if the original branch specified the link operation.
9635 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9637 Code like this is produced in the noreorder mode:
9642 delay slot (executed only if branch taken)
9650 delay slot (executed only if branch taken)
9653 In the reorder mode the delay slot would be filled with a nop anyway,
9654 so code produced is simply:
9659 This function is used when producing code for the microMIPS ASE that
9660 does not implement branch likely instructions in hardware. */
9663 macro_build_branch_likely (const char *br
, const char *brneg
,
9664 int call
, expressionS
*ep
, const char *fmt
,
9665 unsigned int sreg
, unsigned int treg
)
9667 int noreorder
= mips_opts
.noreorder
;
9670 gas_assert (mips_opts
.micromips
);
9674 micromips_label_expr (&expr1
);
9675 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9676 macro_build (NULL
, "nop", "");
9677 macro_build (ep
, call
? "bal" : "b", "p");
9679 /* Set to true so that append_insn adds a label. */
9680 emit_branch_likely_macro
= TRUE
;
9684 macro_build (ep
, br
, fmt
, sreg
, treg
);
9685 macro_build (NULL
, "nop", "");
9690 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9691 the condition code tested. EP specifies the branch target. */
9694 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9721 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9724 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9725 the register tested. EP specifies the branch target. */
9728 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9730 const char *brneg
= NULL
;
9740 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9744 gas_assert (mips_opts
.micromips
);
9745 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9753 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9760 br
= mips_opts
.micromips
? "blez" : "blezl";
9767 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9771 gas_assert (mips_opts
.micromips
);
9772 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9779 if (mips_opts
.micromips
&& brneg
)
9780 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9782 macro_build (ep
, br
, "s,p", sreg
);
9785 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9786 TREG as the registers tested. EP specifies the branch target. */
9789 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9790 unsigned int sreg
, unsigned int treg
)
9792 const char *brneg
= NULL
;
9804 br
= mips_opts
.micromips
? "beq" : "beql";
9813 br
= mips_opts
.micromips
? "bne" : "bnel";
9819 if (mips_opts
.micromips
&& brneg
)
9820 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9822 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9825 /* Return the high part that should be loaded in order to make the low
9826 part of VALUE accessible using an offset of OFFBITS bits. */
9829 offset_high_part (offsetT value
, unsigned int offbits
)
9836 bias
= 1 << (offbits
- 1);
9837 low_mask
= bias
* 2 - 1;
9838 return (value
+ bias
) & ~low_mask
;
9841 /* Return true if the value stored in offset_expr and offset_reloc
9842 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9843 amount that the caller wants to add without inducing overflow
9844 and ALIGN is the known alignment of the value in bytes. */
9847 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9851 /* Accept any relocation operator if overflow isn't a concern. */
9852 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9855 /* These relocations are guaranteed not to overflow in correct links. */
9856 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9857 || gprel16_reloc_p (*offset_reloc
))
9860 if (offset_expr
.X_op
== O_constant
9861 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9862 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9869 * This routine implements the seemingly endless macro or synthesized
9870 * instructions and addressing modes in the mips assembly language. Many
9871 * of these macros are simple and are similar to each other. These could
9872 * probably be handled by some kind of table or grammar approach instead of
9873 * this verbose method. Others are not simple macros but are more like
9874 * optimizing code generation.
9875 * One interesting optimization is when several store macros appear
9876 * consecutively that would load AT with the upper half of the same address.
9877 * The ensuing load upper instructions are omitted. This implies some kind
9878 * of global optimization. We currently only optimize within a single macro.
9879 * For many of the load and store macros if the address is specified as a
9880 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9881 * first load register 'at' with zero and use it as the base register. The
9882 * mips assembler simply uses register $zero. Just one tiny optimization
9886 macro (struct mips_cl_insn
*ip
, char *str
)
9888 const struct mips_operand_array
*operands
;
9889 unsigned int breg
, i
;
9890 unsigned int tempreg
;
9893 expressionS label_expr
;
9908 bfd_boolean large_offset
;
9910 int hold_mips_optimize
;
9912 unsigned int op
[MAX_OPERANDS
];
9914 gas_assert (! mips_opts
.mips16
);
9916 operands
= insn_operands (ip
);
9917 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9918 if (operands
->operand
[i
])
9919 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9923 mask
= ip
->insn_mo
->mask
;
9925 label_expr
.X_op
= O_constant
;
9926 label_expr
.X_op_symbol
= NULL
;
9927 label_expr
.X_add_symbol
= NULL
;
9928 label_expr
.X_add_number
= 0;
9930 expr1
.X_op
= O_constant
;
9931 expr1
.X_op_symbol
= NULL
;
9932 expr1
.X_add_symbol
= NULL
;
9933 expr1
.X_add_number
= 1;
9950 if (mips_opts
.micromips
)
9951 micromips_label_expr (&label_expr
);
9953 label_expr
.X_add_number
= 8;
9954 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9956 macro_build (NULL
, "nop", "");
9958 move_register (op
[0], op
[1]);
9959 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9960 if (mips_opts
.micromips
)
9961 micromips_add_label ();
9978 if (!mips_opts
.micromips
)
9980 if (imm_expr
.X_add_number
>= -0x200
9981 && imm_expr
.X_add_number
< 0x200)
9983 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9984 (int) imm_expr
.X_add_number
);
9993 if (imm_expr
.X_add_number
>= -0x8000
9994 && imm_expr
.X_add_number
< 0x8000)
9996 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10001 load_register (AT
, &imm_expr
, dbl
);
10002 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10021 if (imm_expr
.X_add_number
>= 0
10022 && imm_expr
.X_add_number
< 0x10000)
10024 if (mask
!= M_NOR_I
)
10025 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10028 macro_build (&imm_expr
, "ori", "t,r,i",
10029 op
[0], op
[1], BFD_RELOC_LO16
);
10030 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10036 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10037 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10041 switch (imm_expr
.X_add_number
)
10044 macro_build (NULL
, "nop", "");
10047 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10051 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10052 (int) imm_expr
.X_add_number
);
10055 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10056 (unsigned long) imm_expr
.X_add_number
);
10065 gas_assert (mips_opts
.micromips
);
10066 macro_build_branch_ccl (mask
, &offset_expr
,
10067 EXTRACT_OPERAND (1, BCC
, *ip
));
10074 if (imm_expr
.X_add_number
== 0)
10080 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10082 /* Fall through. */
10085 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10090 /* Fall through. */
10093 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10094 else if (op
[0] == 0)
10095 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10099 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10100 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10101 &offset_expr
, AT
, ZERO
);
10111 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10116 /* Fall through. */
10118 /* Check for > max integer. */
10119 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10122 /* Result is always false. */
10124 macro_build (NULL
, "nop", "");
10126 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10129 ++imm_expr
.X_add_number
;
10133 if (mask
== M_BGEL_I
)
10135 if (imm_expr
.X_add_number
== 0)
10137 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10138 &offset_expr
, op
[0]);
10141 if (imm_expr
.X_add_number
== 1)
10143 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10144 &offset_expr
, op
[0]);
10147 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10150 /* result is always true */
10151 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10152 macro_build (&offset_expr
, "b", "p");
10157 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10158 &offset_expr
, AT
, ZERO
);
10163 /* Fall through. */
10167 else if (op
[0] == 0)
10168 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10169 &offset_expr
, ZERO
, op
[1]);
10173 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10174 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10175 &offset_expr
, AT
, ZERO
);
10181 /* Fall through. */
10185 && imm_expr
.X_add_number
== -1))
10187 ++imm_expr
.X_add_number
;
10191 if (mask
== M_BGEUL_I
)
10193 if (imm_expr
.X_add_number
== 0)
10195 else if (imm_expr
.X_add_number
== 1)
10196 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10197 &offset_expr
, op
[0], ZERO
);
10202 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10203 &offset_expr
, AT
, ZERO
);
10209 /* Fall through. */
10212 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10213 else if (op
[0] == 0)
10214 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10218 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10219 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10220 &offset_expr
, AT
, ZERO
);
10226 /* Fall through. */
10229 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10230 &offset_expr
, op
[0], ZERO
);
10231 else if (op
[0] == 0)
10236 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10237 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10238 &offset_expr
, AT
, ZERO
);
10244 /* Fall through. */
10247 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10248 else if (op
[0] == 0)
10249 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10253 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10254 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10255 &offset_expr
, AT
, ZERO
);
10261 /* Fall through. */
10263 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10265 ++imm_expr
.X_add_number
;
10269 if (mask
== M_BLTL_I
)
10271 if (imm_expr
.X_add_number
== 0)
10272 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10273 else if (imm_expr
.X_add_number
== 1)
10274 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10279 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10280 &offset_expr
, AT
, ZERO
);
10286 /* Fall through. */
10289 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10290 &offset_expr
, op
[0], ZERO
);
10291 else if (op
[0] == 0)
10296 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10297 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10298 &offset_expr
, AT
, ZERO
);
10304 /* Fall through. */
10308 && imm_expr
.X_add_number
== -1))
10310 ++imm_expr
.X_add_number
;
10314 if (mask
== M_BLTUL_I
)
10316 if (imm_expr
.X_add_number
== 0)
10318 else if (imm_expr
.X_add_number
== 1)
10319 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10320 &offset_expr
, op
[0], ZERO
);
10325 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10326 &offset_expr
, AT
, ZERO
);
10332 /* Fall through. */
10335 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10336 else if (op
[0] == 0)
10337 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10341 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10342 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10343 &offset_expr
, AT
, ZERO
);
10349 /* Fall through. */
10353 else if (op
[0] == 0)
10354 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10355 &offset_expr
, ZERO
, op
[1]);
10359 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10360 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10361 &offset_expr
, AT
, ZERO
);
10367 /* Fall through. */
10373 /* Fall through. */
10379 as_warn (_("divide by zero"));
10381 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10383 macro_build (NULL
, "break", BRK_FMT
, 7);
10387 start_noreorder ();
10390 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10391 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10395 if (mips_opts
.micromips
)
10396 micromips_label_expr (&label_expr
);
10398 label_expr
.X_add_number
= 8;
10399 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10400 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10401 macro_build (NULL
, "break", BRK_FMT
, 7);
10402 if (mips_opts
.micromips
)
10403 micromips_add_label ();
10405 expr1
.X_add_number
= -1;
10407 load_register (AT
, &expr1
, dbl
);
10408 if (mips_opts
.micromips
)
10409 micromips_label_expr (&label_expr
);
10411 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10412 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10415 expr1
.X_add_number
= 1;
10416 load_register (AT
, &expr1
, dbl
);
10417 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10421 expr1
.X_add_number
= 0x80000000;
10422 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10426 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10427 /* We want to close the noreorder block as soon as possible, so
10428 that later insns are available for delay slot filling. */
10433 if (mips_opts
.micromips
)
10434 micromips_label_expr (&label_expr
);
10436 label_expr
.X_add_number
= 8;
10437 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10438 macro_build (NULL
, "nop", "");
10440 /* We want to close the noreorder block as soon as possible, so
10441 that later insns are available for delay slot filling. */
10444 macro_build (NULL
, "break", BRK_FMT
, 6);
10446 if (mips_opts
.micromips
)
10447 micromips_add_label ();
10448 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10487 if (imm_expr
.X_add_number
== 0)
10489 as_warn (_("divide by zero"));
10491 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10493 macro_build (NULL
, "break", BRK_FMT
, 7);
10496 if (imm_expr
.X_add_number
== 1)
10498 if (strcmp (s2
, "mflo") == 0)
10499 move_register (op
[0], op
[1]);
10501 move_register (op
[0], ZERO
);
10504 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10506 if (strcmp (s2
, "mflo") == 0)
10507 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10509 move_register (op
[0], ZERO
);
10514 load_register (AT
, &imm_expr
, dbl
);
10515 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10516 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10535 start_noreorder ();
10538 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10539 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10540 /* We want to close the noreorder block as soon as possible, so
10541 that later insns are available for delay slot filling. */
10546 if (mips_opts
.micromips
)
10547 micromips_label_expr (&label_expr
);
10549 label_expr
.X_add_number
= 8;
10550 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10551 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10553 /* We want to close the noreorder block as soon as possible, so
10554 that later insns are available for delay slot filling. */
10556 macro_build (NULL
, "break", BRK_FMT
, 7);
10557 if (mips_opts
.micromips
)
10558 micromips_add_label ();
10560 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10565 /* Fall through. */
10571 /* Fall through. */
10574 /* Load the address of a symbol into a register. If breg is not
10575 zero, we then add a base register to it. */
10578 if (dbl
&& GPR_SIZE
== 32)
10579 as_warn (_("dla used to load 32-bit register; recommend using la "
10582 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10583 as_warn (_("la used to load 64-bit address; recommend using dla "
10586 if (small_offset_p (0, align
, 16))
10588 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10589 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10593 if (mips_opts
.at
&& (op
[0] == breg
))
10601 if (offset_expr
.X_op
!= O_symbol
10602 && offset_expr
.X_op
!= O_constant
)
10604 as_bad (_("expression too complex"));
10605 offset_expr
.X_op
= O_constant
;
10608 if (offset_expr
.X_op
== O_constant
)
10609 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10610 else if (mips_pic
== NO_PIC
)
10612 /* If this is a reference to a GP relative symbol, we want
10613 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10615 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10616 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10617 If we have a constant, we need two instructions anyhow,
10618 so we may as well always use the latter form.
10620 With 64bit address space and a usable $at we want
10621 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10622 lui $at,<sym> (BFD_RELOC_HI16_S)
10623 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10624 daddiu $at,<sym> (BFD_RELOC_LO16)
10626 daddu $tempreg,$tempreg,$at
10628 If $at is already in use, we use a path which is suboptimal
10629 on superscalar processors.
10630 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10631 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10633 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10635 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10637 For GP relative symbols in 64bit address space we can use
10638 the same sequence as in 32bit address space. */
10639 if (HAVE_64BIT_SYMBOLS
)
10641 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10642 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10644 relax_start (offset_expr
.X_add_symbol
);
10645 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10646 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10650 if (used_at
== 0 && mips_opts
.at
)
10652 macro_build (&offset_expr
, "lui", LUI_FMT
,
10653 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10654 macro_build (&offset_expr
, "lui", LUI_FMT
,
10655 AT
, BFD_RELOC_HI16_S
);
10656 macro_build (&offset_expr
, "daddiu", "t,r,j",
10657 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10658 macro_build (&offset_expr
, "daddiu", "t,r,j",
10659 AT
, AT
, BFD_RELOC_LO16
);
10660 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10661 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10666 macro_build (&offset_expr
, "lui", LUI_FMT
,
10667 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10668 macro_build (&offset_expr
, "daddiu", "t,r,j",
10669 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10670 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10671 macro_build (&offset_expr
, "daddiu", "t,r,j",
10672 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10673 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10674 macro_build (&offset_expr
, "daddiu", "t,r,j",
10675 tempreg
, tempreg
, BFD_RELOC_LO16
);
10678 if (mips_relax
.sequence
)
10683 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10684 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10686 relax_start (offset_expr
.X_add_symbol
);
10687 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10688 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10691 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10692 as_bad (_("offset too large"));
10693 macro_build_lui (&offset_expr
, tempreg
);
10694 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10695 tempreg
, tempreg
, BFD_RELOC_LO16
);
10696 if (mips_relax
.sequence
)
10700 else if (!mips_big_got
&& !HAVE_NEWABI
)
10702 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10704 /* If this is a reference to an external symbol, and there
10705 is no constant, we want
10706 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10707 or for lca or if tempreg is PIC_CALL_REG
10708 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10709 For a local symbol, we want
10710 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10712 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10714 If we have a small constant, and this is a reference to
10715 an external symbol, we want
10716 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10718 addiu $tempreg,$tempreg,<constant>
10719 For a local symbol, we want the same instruction
10720 sequence, but we output a BFD_RELOC_LO16 reloc on the
10723 If we have a large constant, and this is a reference to
10724 an external symbol, we want
10725 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10726 lui $at,<hiconstant>
10727 addiu $at,$at,<loconstant>
10728 addu $tempreg,$tempreg,$at
10729 For a local symbol, we want the same instruction
10730 sequence, but we output a BFD_RELOC_LO16 reloc on the
10734 if (offset_expr
.X_add_number
== 0)
10736 if (mips_pic
== SVR4_PIC
10738 && (call
|| tempreg
== PIC_CALL_REG
))
10739 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10741 relax_start (offset_expr
.X_add_symbol
);
10742 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10743 lw_reloc_type
, mips_gp_register
);
10746 /* We're going to put in an addu instruction using
10747 tempreg, so we may as well insert the nop right
10752 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10753 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10755 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10756 tempreg
, tempreg
, BFD_RELOC_LO16
);
10758 /* FIXME: If breg == 0, and the next instruction uses
10759 $tempreg, then if this variant case is used an extra
10760 nop will be generated. */
10762 else if (offset_expr
.X_add_number
>= -0x8000
10763 && offset_expr
.X_add_number
< 0x8000)
10765 load_got_offset (tempreg
, &offset_expr
);
10767 add_got_offset (tempreg
, &offset_expr
);
10771 expr1
.X_add_number
= offset_expr
.X_add_number
;
10772 offset_expr
.X_add_number
=
10773 SEXT_16BIT (offset_expr
.X_add_number
);
10774 load_got_offset (tempreg
, &offset_expr
);
10775 offset_expr
.X_add_number
= expr1
.X_add_number
;
10776 /* If we are going to add in a base register, and the
10777 target register and the base register are the same,
10778 then we are using AT as a temporary register. Since
10779 we want to load the constant into AT, we add our
10780 current AT (from the global offset table) and the
10781 register into the register now, and pretend we were
10782 not using a base register. */
10786 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10791 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10795 else if (!mips_big_got
&& HAVE_NEWABI
)
10797 int add_breg_early
= 0;
10799 /* If this is a reference to an external, and there is no
10800 constant, or local symbol (*), with or without a
10802 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10803 or for lca or if tempreg is PIC_CALL_REG
10804 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10806 If we have a small constant, and this is a reference to
10807 an external symbol, we want
10808 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10809 addiu $tempreg,$tempreg,<constant>
10811 If we have a large constant, and this is a reference to
10812 an external symbol, we want
10813 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10814 lui $at,<hiconstant>
10815 addiu $at,$at,<loconstant>
10816 addu $tempreg,$tempreg,$at
10818 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10819 local symbols, even though it introduces an additional
10822 if (offset_expr
.X_add_number
)
10824 expr1
.X_add_number
= offset_expr
.X_add_number
;
10825 offset_expr
.X_add_number
= 0;
10827 relax_start (offset_expr
.X_add_symbol
);
10828 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10829 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10831 if (expr1
.X_add_number
>= -0x8000
10832 && expr1
.X_add_number
< 0x8000)
10834 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10835 tempreg
, tempreg
, BFD_RELOC_LO16
);
10837 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10841 /* If we are going to add in a base register, and the
10842 target register and the base register are the same,
10843 then we are using AT as a temporary register. Since
10844 we want to load the constant into AT, we add our
10845 current AT (from the global offset table) and the
10846 register into the register now, and pretend we were
10847 not using a base register. */
10852 gas_assert (tempreg
== AT
);
10853 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10856 add_breg_early
= 1;
10859 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10860 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10866 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10869 offset_expr
.X_add_number
= expr1
.X_add_number
;
10871 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10872 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10873 if (add_breg_early
)
10875 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10876 op
[0], tempreg
, breg
);
10882 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10884 relax_start (offset_expr
.X_add_symbol
);
10885 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10886 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10888 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10889 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10894 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10895 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10898 else if (mips_big_got
&& !HAVE_NEWABI
)
10901 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10902 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10903 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10905 /* This is the large GOT case. If this is a reference to an
10906 external symbol, and there is no constant, we want
10907 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10908 addu $tempreg,$tempreg,$gp
10909 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10910 or for lca or if tempreg is PIC_CALL_REG
10911 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10912 addu $tempreg,$tempreg,$gp
10913 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10914 For a local symbol, we want
10915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10917 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10919 If we have a small constant, and this is a reference to
10920 an external symbol, we want
10921 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10922 addu $tempreg,$tempreg,$gp
10923 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10925 addiu $tempreg,$tempreg,<constant>
10926 For a local symbol, we want
10927 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10929 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10931 If we have a large constant, and this is a reference to
10932 an external symbol, we want
10933 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10934 addu $tempreg,$tempreg,$gp
10935 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10936 lui $at,<hiconstant>
10937 addiu $at,$at,<loconstant>
10938 addu $tempreg,$tempreg,$at
10939 For a local symbol, we want
10940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10941 lui $at,<hiconstant>
10942 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10943 addu $tempreg,$tempreg,$at
10946 expr1
.X_add_number
= offset_expr
.X_add_number
;
10947 offset_expr
.X_add_number
= 0;
10948 relax_start (offset_expr
.X_add_symbol
);
10949 gpdelay
= reg_needs_delay (mips_gp_register
);
10950 if (expr1
.X_add_number
== 0 && breg
== 0
10951 && (call
|| tempreg
== PIC_CALL_REG
))
10953 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10954 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10956 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10957 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10958 tempreg
, tempreg
, mips_gp_register
);
10959 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10960 tempreg
, lw_reloc_type
, tempreg
);
10961 if (expr1
.X_add_number
== 0)
10965 /* We're going to put in an addu instruction using
10966 tempreg, so we may as well insert the nop right
10971 else if (expr1
.X_add_number
>= -0x8000
10972 && expr1
.X_add_number
< 0x8000)
10975 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10976 tempreg
, tempreg
, BFD_RELOC_LO16
);
10982 /* If we are going to add in a base register, and the
10983 target register and the base register are the same,
10984 then we are using AT as a temporary register. Since
10985 we want to load the constant into AT, we add our
10986 current AT (from the global offset table) and the
10987 register into the register now, and pretend we were
10988 not using a base register. */
10993 gas_assert (tempreg
== AT
);
10995 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11000 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11001 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11005 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11010 /* This is needed because this instruction uses $gp, but
11011 the first instruction on the main stream does not. */
11012 macro_build (NULL
, "nop", "");
11015 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11016 local_reloc_type
, mips_gp_register
);
11017 if (expr1
.X_add_number
>= -0x8000
11018 && expr1
.X_add_number
< 0x8000)
11021 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11022 tempreg
, tempreg
, BFD_RELOC_LO16
);
11023 /* FIXME: If add_number is 0, and there was no base
11024 register, the external symbol case ended with a load,
11025 so if the symbol turns out to not be external, and
11026 the next instruction uses tempreg, an unnecessary nop
11027 will be inserted. */
11033 /* We must add in the base register now, as in the
11034 external symbol case. */
11035 gas_assert (tempreg
== AT
);
11037 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11040 /* We set breg to 0 because we have arranged to add
11041 it in in both cases. */
11045 macro_build_lui (&expr1
, AT
);
11046 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11047 AT
, AT
, BFD_RELOC_LO16
);
11048 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11049 tempreg
, tempreg
, AT
);
11054 else if (mips_big_got
&& HAVE_NEWABI
)
11056 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11057 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11058 int add_breg_early
= 0;
11060 /* This is the large GOT case. If this is a reference to an
11061 external symbol, and there is no constant, we want
11062 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11063 add $tempreg,$tempreg,$gp
11064 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11065 or for lca or if tempreg is PIC_CALL_REG
11066 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11067 add $tempreg,$tempreg,$gp
11068 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11070 If we have a small constant, and this is a reference to
11071 an external symbol, we want
11072 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11073 add $tempreg,$tempreg,$gp
11074 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11075 addi $tempreg,$tempreg,<constant>
11077 If we have a large constant, and this is a reference to
11078 an external symbol, we want
11079 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11080 addu $tempreg,$tempreg,$gp
11081 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11082 lui $at,<hiconstant>
11083 addi $at,$at,<loconstant>
11084 add $tempreg,$tempreg,$at
11086 If we have NewABI, and we know it's a local symbol, we want
11087 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11088 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11089 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11091 relax_start (offset_expr
.X_add_symbol
);
11093 expr1
.X_add_number
= offset_expr
.X_add_number
;
11094 offset_expr
.X_add_number
= 0;
11096 if (expr1
.X_add_number
== 0 && breg
== 0
11097 && (call
|| tempreg
== PIC_CALL_REG
))
11099 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11100 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11102 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11103 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11104 tempreg
, tempreg
, mips_gp_register
);
11105 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11106 tempreg
, lw_reloc_type
, tempreg
);
11108 if (expr1
.X_add_number
== 0)
11110 else if (expr1
.X_add_number
>= -0x8000
11111 && expr1
.X_add_number
< 0x8000)
11113 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11114 tempreg
, tempreg
, BFD_RELOC_LO16
);
11116 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11120 /* If we are going to add in a base register, and the
11121 target register and the base register are the same,
11122 then we are using AT as a temporary register. Since
11123 we want to load the constant into AT, we add our
11124 current AT (from the global offset table) and the
11125 register into the register now, and pretend we were
11126 not using a base register. */
11131 gas_assert (tempreg
== AT
);
11132 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11135 add_breg_early
= 1;
11138 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11144 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11147 offset_expr
.X_add_number
= expr1
.X_add_number
;
11148 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11149 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11150 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11151 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11152 if (add_breg_early
)
11154 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11155 op
[0], tempreg
, breg
);
11165 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11169 gas_assert (!mips_opts
.micromips
);
11170 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11174 gas_assert (!mips_opts
.micromips
);
11175 macro_build (NULL
, "c2", "C", 0x02);
11179 gas_assert (!mips_opts
.micromips
);
11180 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11184 gas_assert (!mips_opts
.micromips
);
11185 macro_build (NULL
, "c2", "C", 3);
11189 gas_assert (!mips_opts
.micromips
);
11190 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11194 /* The j instruction may not be used in PIC code, since it
11195 requires an absolute address. We convert it to a b
11197 if (mips_pic
== NO_PIC
)
11198 macro_build (&offset_expr
, "j", "a");
11200 macro_build (&offset_expr
, "b", "p");
11203 /* The jal instructions must be handled as macros because when
11204 generating PIC code they expand to multi-instruction
11205 sequences. Normally they are simple instructions. */
11209 /* Fall through. */
11211 gas_assert (mips_opts
.micromips
);
11212 if (mips_opts
.insn32
)
11214 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11222 /* Fall through. */
11225 if (mips_pic
== NO_PIC
)
11227 s
= jals
? "jalrs" : "jalr";
11228 if (mips_opts
.micromips
11229 && !mips_opts
.insn32
11231 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11232 macro_build (NULL
, s
, "mj", op
[1]);
11234 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11238 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11239 && mips_cprestore_offset
>= 0);
11241 if (op
[1] != PIC_CALL_REG
)
11242 as_warn (_("MIPS PIC call to register other than $25"));
11244 s
= ((mips_opts
.micromips
11245 && !mips_opts
.insn32
11246 && (!mips_opts
.noreorder
|| cprestore
))
11247 ? "jalrs" : "jalr");
11248 if (mips_opts
.micromips
11249 && !mips_opts
.insn32
11251 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11252 macro_build (NULL
, s
, "mj", op
[1]);
11254 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11255 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11257 if (mips_cprestore_offset
< 0)
11258 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11261 if (!mips_frame_reg_valid
)
11263 as_warn (_("no .frame pseudo-op used in PIC code"));
11264 /* Quiet this warning. */
11265 mips_frame_reg_valid
= 1;
11267 if (!mips_cprestore_valid
)
11269 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11270 /* Quiet this warning. */
11271 mips_cprestore_valid
= 1;
11273 if (mips_opts
.noreorder
)
11274 macro_build (NULL
, "nop", "");
11275 expr1
.X_add_number
= mips_cprestore_offset
;
11276 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11279 HAVE_64BIT_ADDRESSES
);
11287 gas_assert (mips_opts
.micromips
);
11288 if (mips_opts
.insn32
)
11290 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11294 /* Fall through. */
11296 if (mips_pic
== NO_PIC
)
11297 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11298 else if (mips_pic
== SVR4_PIC
)
11300 /* If this is a reference to an external symbol, and we are
11301 using a small GOT, we want
11302 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11306 lw $gp,cprestore($sp)
11307 The cprestore value is set using the .cprestore
11308 pseudo-op. If we are using a big GOT, we want
11309 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11311 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11315 lw $gp,cprestore($sp)
11316 If the symbol is not external, we want
11317 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11319 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11322 lw $gp,cprestore($sp)
11324 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11325 sequences above, minus nops, unless the symbol is local,
11326 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11332 relax_start (offset_expr
.X_add_symbol
);
11333 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11334 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11337 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11338 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11344 relax_start (offset_expr
.X_add_symbol
);
11345 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11346 BFD_RELOC_MIPS_CALL_HI16
);
11347 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11348 PIC_CALL_REG
, mips_gp_register
);
11349 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11350 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11353 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11354 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11356 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11357 PIC_CALL_REG
, PIC_CALL_REG
,
11358 BFD_RELOC_MIPS_GOT_OFST
);
11362 macro_build_jalr (&offset_expr
, 0);
11366 relax_start (offset_expr
.X_add_symbol
);
11369 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11370 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11379 gpdelay
= reg_needs_delay (mips_gp_register
);
11380 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11381 BFD_RELOC_MIPS_CALL_HI16
);
11382 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11383 PIC_CALL_REG
, mips_gp_register
);
11384 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11385 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11390 macro_build (NULL
, "nop", "");
11392 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11393 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11396 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11397 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11399 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11401 if (mips_cprestore_offset
< 0)
11402 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11405 if (!mips_frame_reg_valid
)
11407 as_warn (_("no .frame pseudo-op used in PIC code"));
11408 /* Quiet this warning. */
11409 mips_frame_reg_valid
= 1;
11411 if (!mips_cprestore_valid
)
11413 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11414 /* Quiet this warning. */
11415 mips_cprestore_valid
= 1;
11417 if (mips_opts
.noreorder
)
11418 macro_build (NULL
, "nop", "");
11419 expr1
.X_add_number
= mips_cprestore_offset
;
11420 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11423 HAVE_64BIT_ADDRESSES
);
11427 else if (mips_pic
== VXWORKS_PIC
)
11428 as_bad (_("non-PIC jump used in PIC library"));
11535 gas_assert (!mips_opts
.micromips
);
11538 /* Itbl support may require additional care here. */
11544 /* Itbl support may require additional care here. */
11550 offbits
= (mips_opts
.micromips
? 12
11551 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11553 /* Itbl support may require additional care here. */
11557 gas_assert (!mips_opts
.micromips
);
11560 /* Itbl support may require additional care here. */
11566 offbits
= (mips_opts
.micromips
? 12 : 16);
11571 offbits
= (mips_opts
.micromips
? 12 : 16);
11576 /* Itbl support may require additional care here. */
11582 offbits
= (mips_opts
.micromips
? 12
11583 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11585 /* Itbl support may require additional care here. */
11591 /* Itbl support may require additional care here. */
11597 /* Itbl support may require additional care here. */
11603 offbits
= (mips_opts
.micromips
? 12 : 16);
11608 offbits
= (mips_opts
.micromips
? 12 : 16);
11613 offbits
= (mips_opts
.micromips
? 12
11614 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11620 offbits
= (mips_opts
.micromips
? 12
11621 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11627 offbits
= (mips_opts
.micromips
? 12 : 16);
11630 gas_assert (mips_opts
.micromips
);
11637 gas_assert (mips_opts
.micromips
);
11644 gas_assert (mips_opts
.micromips
);
11650 gas_assert (mips_opts
.micromips
);
11657 /* We don't want to use $0 as tempreg. */
11658 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11661 tempreg
= op
[0] + lp
;
11677 gas_assert (!mips_opts
.micromips
);
11680 /* Itbl support may require additional care here. */
11686 /* Itbl support may require additional care here. */
11692 offbits
= (mips_opts
.micromips
? 12
11693 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11695 /* Itbl support may require additional care here. */
11699 gas_assert (!mips_opts
.micromips
);
11702 /* Itbl support may require additional care here. */
11708 offbits
= (mips_opts
.micromips
? 12 : 16);
11713 offbits
= (mips_opts
.micromips
? 12 : 16);
11718 offbits
= (mips_opts
.micromips
? 12
11719 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11725 offbits
= (mips_opts
.micromips
? 12
11726 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11731 fmt
= (mips_opts
.micromips
? "k,~(b)"
11732 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11734 offbits
= (mips_opts
.micromips
? 12
11735 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11745 fmt
= (mips_opts
.micromips
? "k,~(b)"
11746 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11748 offbits
= (mips_opts
.micromips
? 12
11749 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11761 /* Itbl support may require additional care here. */
11766 offbits
= (mips_opts
.micromips
? 12
11767 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11769 /* Itbl support may require additional care here. */
11775 /* Itbl support may require additional care here. */
11779 gas_assert (!mips_opts
.micromips
);
11782 /* Itbl support may require additional care here. */
11788 offbits
= (mips_opts
.micromips
? 12 : 16);
11793 offbits
= (mips_opts
.micromips
? 12 : 16);
11796 gas_assert (mips_opts
.micromips
);
11802 gas_assert (mips_opts
.micromips
);
11808 gas_assert (mips_opts
.micromips
);
11814 gas_assert (mips_opts
.micromips
);
11823 if (small_offset_p (0, align
, 16))
11825 /* The first case exists for M_LD_AB and M_SD_AB, which are
11826 macros for o32 but which should act like normal instructions
11829 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11830 offset_reloc
[1], offset_reloc
[2], breg
);
11831 else if (small_offset_p (0, align
, offbits
))
11834 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11836 macro_build (NULL
, s
, fmt
, op
[0],
11837 (int) offset_expr
.X_add_number
, breg
);
11843 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11844 tempreg
, breg
, -1, offset_reloc
[0],
11845 offset_reloc
[1], offset_reloc
[2]);
11847 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11849 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11857 if (offset_expr
.X_op
!= O_constant
11858 && offset_expr
.X_op
!= O_symbol
)
11860 as_bad (_("expression too complex"));
11861 offset_expr
.X_op
= O_constant
;
11864 if (HAVE_32BIT_ADDRESSES
11865 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11869 sprintf_vma (value
, offset_expr
.X_add_number
);
11870 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11873 /* A constant expression in PIC code can be handled just as it
11874 is in non PIC code. */
11875 if (offset_expr
.X_op
== O_constant
)
11877 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11878 offbits
== 0 ? 16 : offbits
);
11879 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11881 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11883 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11884 tempreg
, tempreg
, breg
);
11887 if (offset_expr
.X_add_number
!= 0)
11888 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11889 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11890 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11892 else if (offbits
== 16)
11893 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11895 macro_build (NULL
, s
, fmt
, op
[0],
11896 (int) offset_expr
.X_add_number
, tempreg
);
11898 else if (offbits
!= 16)
11900 /* The offset field is too narrow to be used for a low-part
11901 relocation, so load the whole address into the auxiliary
11903 load_address (tempreg
, &offset_expr
, &used_at
);
11905 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11906 tempreg
, tempreg
, breg
);
11908 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11910 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11912 else if (mips_pic
== NO_PIC
)
11914 /* If this is a reference to a GP relative symbol, and there
11915 is no base register, we want
11916 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11917 Otherwise, if there is no base register, we want
11918 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11919 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11920 If we have a constant, we need two instructions anyhow,
11921 so we always use the latter form.
11923 If we have a base register, and this is a reference to a
11924 GP relative symbol, we want
11925 addu $tempreg,$breg,$gp
11926 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11928 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11929 addu $tempreg,$tempreg,$breg
11930 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11931 With a constant we always use the latter case.
11933 With 64bit address space and no base register and $at usable,
11935 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11936 lui $at,<sym> (BFD_RELOC_HI16_S)
11937 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11940 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11941 If we have a base register, we want
11942 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11943 lui $at,<sym> (BFD_RELOC_HI16_S)
11944 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11948 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11950 Without $at we can't generate the optimal path for superscalar
11951 processors here since this would require two temporary registers.
11952 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11953 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11955 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11957 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11958 If we have a base register, we want
11959 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11960 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11962 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11964 daddu $tempreg,$tempreg,$breg
11965 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11967 For GP relative symbols in 64bit address space we can use
11968 the same sequence as in 32bit address space. */
11969 if (HAVE_64BIT_SYMBOLS
)
11971 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11972 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11974 relax_start (offset_expr
.X_add_symbol
);
11977 macro_build (&offset_expr
, s
, fmt
, op
[0],
11978 BFD_RELOC_GPREL16
, mips_gp_register
);
11982 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11983 tempreg
, breg
, mips_gp_register
);
11984 macro_build (&offset_expr
, s
, fmt
, op
[0],
11985 BFD_RELOC_GPREL16
, tempreg
);
11990 if (used_at
== 0 && mips_opts
.at
)
11992 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11993 BFD_RELOC_MIPS_HIGHEST
);
11994 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11996 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11997 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11999 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12000 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12001 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12002 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12008 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12009 BFD_RELOC_MIPS_HIGHEST
);
12010 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12011 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12012 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12013 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12014 tempreg
, BFD_RELOC_HI16_S
);
12015 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12017 macro_build (NULL
, "daddu", "d,v,t",
12018 tempreg
, tempreg
, breg
);
12019 macro_build (&offset_expr
, s
, fmt
, op
[0],
12020 BFD_RELOC_LO16
, tempreg
);
12023 if (mips_relax
.sequence
)
12030 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12031 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12033 relax_start (offset_expr
.X_add_symbol
);
12034 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12038 macro_build_lui (&offset_expr
, tempreg
);
12039 macro_build (&offset_expr
, s
, fmt
, op
[0],
12040 BFD_RELOC_LO16
, tempreg
);
12041 if (mips_relax
.sequence
)
12046 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12047 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12049 relax_start (offset_expr
.X_add_symbol
);
12050 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12051 tempreg
, breg
, mips_gp_register
);
12052 macro_build (&offset_expr
, s
, fmt
, op
[0],
12053 BFD_RELOC_GPREL16
, tempreg
);
12056 macro_build_lui (&offset_expr
, tempreg
);
12057 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12058 tempreg
, tempreg
, breg
);
12059 macro_build (&offset_expr
, s
, fmt
, op
[0],
12060 BFD_RELOC_LO16
, tempreg
);
12061 if (mips_relax
.sequence
)
12065 else if (!mips_big_got
)
12067 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12069 /* If this is a reference to an external symbol, we want
12070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12072 <op> op[0],0($tempreg)
12074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12076 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12077 <op> op[0],0($tempreg)
12079 For NewABI, we want
12080 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12081 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12083 If there is a base register, we add it to $tempreg before
12084 the <op>. If there is a constant, we stick it in the
12085 <op> instruction. We don't handle constants larger than
12086 16 bits, because we have no way to load the upper 16 bits
12087 (actually, we could handle them for the subset of cases
12088 in which we are not using $at). */
12089 gas_assert (offset_expr
.X_op
== O_symbol
);
12092 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12093 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12095 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12096 tempreg
, tempreg
, breg
);
12097 macro_build (&offset_expr
, s
, fmt
, op
[0],
12098 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12101 expr1
.X_add_number
= offset_expr
.X_add_number
;
12102 offset_expr
.X_add_number
= 0;
12103 if (expr1
.X_add_number
< -0x8000
12104 || expr1
.X_add_number
>= 0x8000)
12105 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12106 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12107 lw_reloc_type
, mips_gp_register
);
12109 relax_start (offset_expr
.X_add_symbol
);
12111 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12112 tempreg
, BFD_RELOC_LO16
);
12115 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12116 tempreg
, tempreg
, breg
);
12117 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12119 else if (mips_big_got
&& !HAVE_NEWABI
)
12123 /* If this is a reference to an external symbol, we want
12124 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12125 addu $tempreg,$tempreg,$gp
12126 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12127 <op> op[0],0($tempreg)
12129 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12131 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12132 <op> op[0],0($tempreg)
12133 If there is a base register, we add it to $tempreg before
12134 the <op>. If there is a constant, we stick it in the
12135 <op> instruction. We don't handle constants larger than
12136 16 bits, because we have no way to load the upper 16 bits
12137 (actually, we could handle them for the subset of cases
12138 in which we are not using $at). */
12139 gas_assert (offset_expr
.X_op
== O_symbol
);
12140 expr1
.X_add_number
= offset_expr
.X_add_number
;
12141 offset_expr
.X_add_number
= 0;
12142 if (expr1
.X_add_number
< -0x8000
12143 || expr1
.X_add_number
>= 0x8000)
12144 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12145 gpdelay
= reg_needs_delay (mips_gp_register
);
12146 relax_start (offset_expr
.X_add_symbol
);
12147 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12148 BFD_RELOC_MIPS_GOT_HI16
);
12149 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12151 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12152 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12155 macro_build (NULL
, "nop", "");
12156 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12157 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12159 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12160 tempreg
, BFD_RELOC_LO16
);
12164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12165 tempreg
, tempreg
, breg
);
12166 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12168 else if (mips_big_got
&& HAVE_NEWABI
)
12170 /* If this is a reference to an external symbol, we want
12171 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12172 add $tempreg,$tempreg,$gp
12173 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12174 <op> op[0],<ofst>($tempreg)
12175 Otherwise, for local symbols, we want:
12176 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12177 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12178 gas_assert (offset_expr
.X_op
== O_symbol
);
12179 expr1
.X_add_number
= offset_expr
.X_add_number
;
12180 offset_expr
.X_add_number
= 0;
12181 if (expr1
.X_add_number
< -0x8000
12182 || expr1
.X_add_number
>= 0x8000)
12183 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12184 relax_start (offset_expr
.X_add_symbol
);
12185 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12186 BFD_RELOC_MIPS_GOT_HI16
);
12187 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12189 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12190 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12192 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12193 tempreg
, tempreg
, breg
);
12194 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12197 offset_expr
.X_add_number
= expr1
.X_add_number
;
12198 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12199 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12201 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12202 tempreg
, tempreg
, breg
);
12203 macro_build (&offset_expr
, s
, fmt
, op
[0],
12204 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12213 gas_assert (mips_opts
.micromips
);
12214 gas_assert (mips_opts
.insn32
);
12215 start_noreorder ();
12216 macro_build (NULL
, "jr", "s", RA
);
12217 expr1
.X_add_number
= op
[0] << 2;
12218 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12223 gas_assert (mips_opts
.micromips
);
12224 gas_assert (mips_opts
.insn32
);
12225 macro_build (NULL
, "jr", "s", op
[0]);
12226 if (mips_opts
.noreorder
)
12227 macro_build (NULL
, "nop", "");
12232 load_register (op
[0], &imm_expr
, 0);
12236 load_register (op
[0], &imm_expr
, 1);
12240 if (imm_expr
.X_op
== O_constant
)
12243 load_register (AT
, &imm_expr
, 0);
12244 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12249 gas_assert (imm_expr
.X_op
== O_absent
12250 && offset_expr
.X_op
== O_symbol
12251 && strcmp (segment_name (S_GET_SEGMENT
12252 (offset_expr
.X_add_symbol
)),
12254 && offset_expr
.X_add_number
== 0);
12255 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12256 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12261 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12262 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12263 order 32 bits of the value and the low order 32 bits are either
12264 zero or in OFFSET_EXPR. */
12265 if (imm_expr
.X_op
== O_constant
)
12267 if (GPR_SIZE
== 64)
12268 load_register (op
[0], &imm_expr
, 1);
12273 if (target_big_endian
)
12285 load_register (hreg
, &imm_expr
, 0);
12288 if (offset_expr
.X_op
== O_absent
)
12289 move_register (lreg
, 0);
12292 gas_assert (offset_expr
.X_op
== O_constant
);
12293 load_register (lreg
, &offset_expr
, 0);
12299 gas_assert (imm_expr
.X_op
== O_absent
);
12301 /* We know that sym is in the .rdata section. First we get the
12302 upper 16 bits of the address. */
12303 if (mips_pic
== NO_PIC
)
12305 macro_build_lui (&offset_expr
, AT
);
12310 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12311 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12315 /* Now we load the register(s). */
12316 if (GPR_SIZE
== 64)
12319 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12320 BFD_RELOC_LO16
, AT
);
12325 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12326 BFD_RELOC_LO16
, AT
);
12329 /* FIXME: How in the world do we deal with the possible
12331 offset_expr
.X_add_number
+= 4;
12332 macro_build (&offset_expr
, "lw", "t,o(b)",
12333 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12339 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12340 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12341 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12342 the value and the low order 32 bits are either zero or in
12344 if (imm_expr
.X_op
== O_constant
)
12347 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12348 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12349 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12352 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12353 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12354 else if (FPR_SIZE
!= 32)
12355 as_bad (_("Unable to generate `%s' compliant code "
12357 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12359 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12360 if (offset_expr
.X_op
== O_absent
)
12361 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12364 gas_assert (offset_expr
.X_op
== O_constant
);
12365 load_register (AT
, &offset_expr
, 0);
12366 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12372 gas_assert (imm_expr
.X_op
== O_absent
12373 && offset_expr
.X_op
== O_symbol
12374 && offset_expr
.X_add_number
== 0);
12375 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12376 if (strcmp (s
, ".lit8") == 0)
12378 op
[2] = mips_gp_register
;
12379 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12380 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12381 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12385 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12387 if (mips_pic
!= NO_PIC
)
12388 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12389 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12392 /* FIXME: This won't work for a 64 bit address. */
12393 macro_build_lui (&offset_expr
, AT
);
12397 offset_reloc
[0] = BFD_RELOC_LO16
;
12398 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12399 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12406 * The MIPS assembler seems to check for X_add_number not
12407 * being double aligned and generating:
12408 * lui at,%hi(foo+1)
12410 * addiu at,at,%lo(foo+1)
12413 * But, the resulting address is the same after relocation so why
12414 * generate the extra instruction?
12416 /* Itbl support may require additional care here. */
12419 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12428 gas_assert (!mips_opts
.micromips
);
12429 /* Itbl support may require additional care here. */
12432 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12452 if (GPR_SIZE
== 64)
12462 if (GPR_SIZE
== 64)
12470 /* Even on a big endian machine $fn comes before $fn+1. We have
12471 to adjust when loading from memory. We set coproc if we must
12472 load $fn+1 first. */
12473 /* Itbl support may require additional care here. */
12474 if (!target_big_endian
)
12478 if (small_offset_p (0, align
, 16))
12481 if (!small_offset_p (4, align
, 16))
12483 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12484 -1, offset_reloc
[0], offset_reloc
[1],
12486 expr1
.X_add_number
= 0;
12490 offset_reloc
[0] = BFD_RELOC_LO16
;
12491 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12492 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12494 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12496 ep
->X_add_number
+= 4;
12497 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12498 offset_reloc
[1], offset_reloc
[2], breg
);
12499 ep
->X_add_number
-= 4;
12500 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12501 offset_reloc
[1], offset_reloc
[2], breg
);
12505 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12506 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12508 ep
->X_add_number
+= 4;
12509 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12510 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12516 if (offset_expr
.X_op
!= O_symbol
12517 && offset_expr
.X_op
!= O_constant
)
12519 as_bad (_("expression too complex"));
12520 offset_expr
.X_op
= O_constant
;
12523 if (HAVE_32BIT_ADDRESSES
12524 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12528 sprintf_vma (value
, offset_expr
.X_add_number
);
12529 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12532 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12534 /* If this is a reference to a GP relative symbol, we want
12535 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12536 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12537 If we have a base register, we use this
12539 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12540 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12541 If this is not a GP relative symbol, we want
12542 lui $at,<sym> (BFD_RELOC_HI16_S)
12543 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12544 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12545 If there is a base register, we add it to $at after the
12546 lui instruction. If there is a constant, we always use
12548 if (offset_expr
.X_op
== O_symbol
12549 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12550 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12552 relax_start (offset_expr
.X_add_symbol
);
12555 tempreg
= mips_gp_register
;
12559 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12560 AT
, breg
, mips_gp_register
);
12565 /* Itbl support may require additional care here. */
12566 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12567 BFD_RELOC_GPREL16
, tempreg
);
12568 offset_expr
.X_add_number
+= 4;
12570 /* Set mips_optimize to 2 to avoid inserting an
12572 hold_mips_optimize
= mips_optimize
;
12574 /* Itbl support may require additional care here. */
12575 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12576 BFD_RELOC_GPREL16
, tempreg
);
12577 mips_optimize
= hold_mips_optimize
;
12581 offset_expr
.X_add_number
-= 4;
12584 if (offset_high_part (offset_expr
.X_add_number
, 16)
12585 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12587 load_address (AT
, &offset_expr
, &used_at
);
12588 offset_expr
.X_op
= O_constant
;
12589 offset_expr
.X_add_number
= 0;
12592 macro_build_lui (&offset_expr
, AT
);
12594 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12595 /* Itbl support may require additional care here. */
12596 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12597 BFD_RELOC_LO16
, AT
);
12598 /* FIXME: How do we handle overflow here? */
12599 offset_expr
.X_add_number
+= 4;
12600 /* Itbl support may require additional care here. */
12601 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12602 BFD_RELOC_LO16
, AT
);
12603 if (mips_relax
.sequence
)
12606 else if (!mips_big_got
)
12608 /* If this is a reference to an external symbol, we want
12609 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12612 <op> op[0]+1,4($at)
12614 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12616 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12617 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12618 If there is a base register we add it to $at before the
12619 lwc1 instructions. If there is a constant we include it
12620 in the lwc1 instructions. */
12622 expr1
.X_add_number
= offset_expr
.X_add_number
;
12623 if (expr1
.X_add_number
< -0x8000
12624 || expr1
.X_add_number
>= 0x8000 - 4)
12625 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12626 load_got_offset (AT
, &offset_expr
);
12629 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12631 /* Set mips_optimize to 2 to avoid inserting an undesired
12633 hold_mips_optimize
= mips_optimize
;
12636 /* Itbl support may require additional care here. */
12637 relax_start (offset_expr
.X_add_symbol
);
12638 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12639 BFD_RELOC_LO16
, AT
);
12640 expr1
.X_add_number
+= 4;
12641 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12642 BFD_RELOC_LO16
, AT
);
12644 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12645 BFD_RELOC_LO16
, AT
);
12646 offset_expr
.X_add_number
+= 4;
12647 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12648 BFD_RELOC_LO16
, AT
);
12651 mips_optimize
= hold_mips_optimize
;
12653 else if (mips_big_got
)
12657 /* If this is a reference to an external symbol, we want
12658 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12660 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12663 <op> op[0]+1,4($at)
12665 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12667 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12668 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12669 If there is a base register we add it to $at before the
12670 lwc1 instructions. If there is a constant we include it
12671 in the lwc1 instructions. */
12673 expr1
.X_add_number
= offset_expr
.X_add_number
;
12674 offset_expr
.X_add_number
= 0;
12675 if (expr1
.X_add_number
< -0x8000
12676 || expr1
.X_add_number
>= 0x8000 - 4)
12677 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12678 gpdelay
= reg_needs_delay (mips_gp_register
);
12679 relax_start (offset_expr
.X_add_symbol
);
12680 macro_build (&offset_expr
, "lui", LUI_FMT
,
12681 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12682 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12683 AT
, AT
, mips_gp_register
);
12684 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12685 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12688 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12689 /* Itbl support may require additional care here. */
12690 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12691 BFD_RELOC_LO16
, AT
);
12692 expr1
.X_add_number
+= 4;
12694 /* Set mips_optimize to 2 to avoid inserting an undesired
12696 hold_mips_optimize
= mips_optimize
;
12698 /* Itbl support may require additional care here. */
12699 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12700 BFD_RELOC_LO16
, AT
);
12701 mips_optimize
= hold_mips_optimize
;
12702 expr1
.X_add_number
-= 4;
12705 offset_expr
.X_add_number
= expr1
.X_add_number
;
12707 macro_build (NULL
, "nop", "");
12708 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12709 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12712 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12713 /* Itbl support may require additional care here. */
12714 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12715 BFD_RELOC_LO16
, AT
);
12716 offset_expr
.X_add_number
+= 4;
12718 /* Set mips_optimize to 2 to avoid inserting an undesired
12720 hold_mips_optimize
= mips_optimize
;
12722 /* Itbl support may require additional care here. */
12723 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12724 BFD_RELOC_LO16
, AT
);
12725 mips_optimize
= hold_mips_optimize
;
12739 gas_assert (!mips_opts
.micromips
);
12744 /* New code added to support COPZ instructions.
12745 This code builds table entries out of the macros in mip_opcodes.
12746 R4000 uses interlocks to handle coproc delays.
12747 Other chips (like the R3000) require nops to be inserted for delays.
12749 FIXME: Currently, we require that the user handle delays.
12750 In order to fill delay slots for non-interlocked chips,
12751 we must have a way to specify delays based on the coprocessor.
12752 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12753 What are the side-effects of the cop instruction?
12754 What cache support might we have and what are its effects?
12755 Both coprocessor & memory require delays. how long???
12756 What registers are read/set/modified?
12758 If an itbl is provided to interpret cop instructions,
12759 this knowledge can be encoded in the itbl spec. */
12773 gas_assert (!mips_opts
.micromips
);
12774 /* For now we just do C (same as Cz). The parameter will be
12775 stored in insn_opcode by mips_ip. */
12776 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12780 move_register (op
[0], op
[1]);
12784 gas_assert (mips_opts
.micromips
);
12785 gas_assert (mips_opts
.insn32
);
12786 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12787 micromips_to_32_reg_m_map
[op
[1]]);
12788 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12789 micromips_to_32_reg_n_map
[op
[2]]);
12794 /* Fall through. */
12796 if (mips_opts
.arch
== CPU_R5900
)
12797 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12801 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12802 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12808 /* Fall through. */
12810 /* The MIPS assembler some times generates shifts and adds. I'm
12811 not trying to be that fancy. GCC should do this for us
12814 load_register (AT
, &imm_expr
, dbl
);
12815 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12816 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12821 /* Fall through. */
12828 /* Fall through. */
12831 start_noreorder ();
12834 load_register (AT
, &imm_expr
, dbl
);
12835 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12836 op
[1], imm
? AT
: op
[2]);
12837 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12838 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12839 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12841 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12844 if (mips_opts
.micromips
)
12845 micromips_label_expr (&label_expr
);
12847 label_expr
.X_add_number
= 8;
12848 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12849 macro_build (NULL
, "nop", "");
12850 macro_build (NULL
, "break", BRK_FMT
, 6);
12851 if (mips_opts
.micromips
)
12852 micromips_add_label ();
12855 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12860 /* Fall through. */
12867 /* Fall through. */
12870 start_noreorder ();
12873 load_register (AT
, &imm_expr
, dbl
);
12874 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12875 op
[1], imm
? AT
: op
[2]);
12876 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12877 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12879 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12882 if (mips_opts
.micromips
)
12883 micromips_label_expr (&label_expr
);
12885 label_expr
.X_add_number
= 8;
12886 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12887 macro_build (NULL
, "nop", "");
12888 macro_build (NULL
, "break", BRK_FMT
, 6);
12889 if (mips_opts
.micromips
)
12890 micromips_add_label ();
12896 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12898 if (op
[0] == op
[1])
12905 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12906 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12910 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12911 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12912 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12913 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12917 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12919 if (op
[0] == op
[1])
12926 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12927 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12931 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12932 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12933 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12934 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12943 rot
= imm_expr
.X_add_number
& 0x3f;
12944 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12946 rot
= (64 - rot
) & 0x3f;
12948 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12950 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12955 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12958 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12959 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12962 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12963 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12964 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12972 rot
= imm_expr
.X_add_number
& 0x1f;
12973 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12975 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12976 (32 - rot
) & 0x1f);
12981 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12985 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12986 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12987 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12992 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12994 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12998 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12999 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13000 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13001 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13005 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13007 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13011 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13012 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13013 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13014 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13023 rot
= imm_expr
.X_add_number
& 0x3f;
13024 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13027 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13029 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13034 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13037 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13038 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13041 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13042 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13043 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13051 rot
= imm_expr
.X_add_number
& 0x1f;
13052 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13054 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13059 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13063 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13064 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13065 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13071 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13072 else if (op
[2] == 0)
13073 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13076 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13077 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13082 if (imm_expr
.X_add_number
== 0)
13084 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13089 as_warn (_("instruction %s: result is always false"),
13090 ip
->insn_mo
->name
);
13091 move_register (op
[0], 0);
13094 if (CPU_HAS_SEQ (mips_opts
.arch
)
13095 && -512 <= imm_expr
.X_add_number
13096 && imm_expr
.X_add_number
< 512)
13098 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13099 (int) imm_expr
.X_add_number
);
13102 if (imm_expr
.X_add_number
>= 0
13103 && imm_expr
.X_add_number
< 0x10000)
13104 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13105 else if (imm_expr
.X_add_number
> -0x8000
13106 && imm_expr
.X_add_number
< 0)
13108 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13109 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13110 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13112 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13115 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13116 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13121 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13122 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13125 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13128 case M_SGE
: /* X >= Y <==> not (X < Y) */
13134 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13135 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13138 case M_SGE_I
: /* X >= I <==> not (X < I) */
13140 if (imm_expr
.X_add_number
>= -0x8000
13141 && imm_expr
.X_add_number
< 0x8000)
13142 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13143 op
[0], op
[1], BFD_RELOC_LO16
);
13146 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13147 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13151 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13154 case M_SGT
: /* X > Y <==> Y < X */
13160 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13163 case M_SGT_I
: /* X > I <==> I < X */
13170 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13171 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13174 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13180 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13181 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13184 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13191 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13192 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13193 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13197 if (imm_expr
.X_add_number
>= -0x8000
13198 && imm_expr
.X_add_number
< 0x8000)
13200 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13205 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13206 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13210 if (imm_expr
.X_add_number
>= -0x8000
13211 && imm_expr
.X_add_number
< 0x8000)
13213 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13218 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13219 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13224 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13225 else if (op
[2] == 0)
13226 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13229 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13230 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13235 if (imm_expr
.X_add_number
== 0)
13237 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13242 as_warn (_("instruction %s: result is always true"),
13243 ip
->insn_mo
->name
);
13244 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13245 op
[0], 0, BFD_RELOC_LO16
);
13248 if (CPU_HAS_SEQ (mips_opts
.arch
)
13249 && -512 <= imm_expr
.X_add_number
13250 && imm_expr
.X_add_number
< 512)
13252 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13253 (int) imm_expr
.X_add_number
);
13256 if (imm_expr
.X_add_number
>= 0
13257 && imm_expr
.X_add_number
< 0x10000)
13259 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13262 else if (imm_expr
.X_add_number
> -0x8000
13263 && imm_expr
.X_add_number
< 0)
13265 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13266 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13267 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13269 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13272 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13273 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13278 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13279 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13282 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13297 if (!mips_opts
.micromips
)
13299 if (imm_expr
.X_add_number
> -0x200
13300 && imm_expr
.X_add_number
<= 0x200)
13302 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13303 (int) -imm_expr
.X_add_number
);
13312 if (imm_expr
.X_add_number
> -0x8000
13313 && imm_expr
.X_add_number
<= 0x8000)
13315 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13316 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13321 load_register (AT
, &imm_expr
, dbl
);
13322 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13344 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13345 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13350 gas_assert (!mips_opts
.micromips
);
13351 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13355 * Is the double cfc1 instruction a bug in the mips assembler;
13356 * or is there a reason for it?
13358 start_noreorder ();
13359 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13360 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13361 macro_build (NULL
, "nop", "");
13362 expr1
.X_add_number
= 3;
13363 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13364 expr1
.X_add_number
= 2;
13365 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13366 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13367 macro_build (NULL
, "nop", "");
13368 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13370 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13371 macro_build (NULL
, "nop", "");
13388 offbits
= (mips_opts
.micromips
? 12 : 16);
13394 offbits
= (mips_opts
.micromips
? 12 : 16);
13406 offbits
= (mips_opts
.micromips
? 12 : 16);
13413 offbits
= (mips_opts
.micromips
? 12 : 16);
13419 large_offset
= !small_offset_p (off
, align
, offbits
);
13421 expr1
.X_add_number
= 0;
13426 if (small_offset_p (0, align
, 16))
13427 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13428 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13431 load_address (tempreg
, ep
, &used_at
);
13433 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13434 tempreg
, tempreg
, breg
);
13436 offset_reloc
[0] = BFD_RELOC_LO16
;
13437 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13438 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13443 else if (!ust
&& op
[0] == breg
)
13454 if (!target_big_endian
)
13455 ep
->X_add_number
+= off
;
13457 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13459 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13460 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13462 if (!target_big_endian
)
13463 ep
->X_add_number
-= off
;
13465 ep
->X_add_number
+= off
;
13467 macro_build (NULL
, s2
, "t,~(b)",
13468 tempreg
, (int) ep
->X_add_number
, breg
);
13470 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13471 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13473 /* If necessary, move the result in tempreg to the final destination. */
13474 if (!ust
&& op
[0] != tempreg
)
13476 /* Protect second load's delay slot. */
13478 move_register (op
[0], tempreg
);
13484 if (target_big_endian
== ust
)
13485 ep
->X_add_number
+= off
;
13486 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13487 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13488 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13490 /* For halfword transfers we need a temporary register to shuffle
13491 bytes. Unfortunately for M_USH_A we have none available before
13492 the next store as AT holds the base address. We deal with this
13493 case by clobbering TREG and then restoring it as with ULH. */
13494 tempreg
= ust
== large_offset
? op
[0] : AT
;
13496 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13498 if (target_big_endian
== ust
)
13499 ep
->X_add_number
-= off
;
13501 ep
->X_add_number
+= off
;
13502 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13503 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13505 /* For M_USH_A re-retrieve the LSB. */
13506 if (ust
&& large_offset
)
13508 if (target_big_endian
)
13509 ep
->X_add_number
+= off
;
13511 ep
->X_add_number
-= off
;
13512 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13513 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13515 /* For ULH and M_USH_A OR the LSB in. */
13516 if (!ust
|| large_offset
)
13518 tempreg
= !large_offset
? AT
: op
[0];
13519 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13520 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13525 /* FIXME: Check if this is one of the itbl macros, since they
13526 are added dynamically. */
13527 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13530 if (!mips_opts
.at
&& used_at
)
13531 as_bad (_("macro used $at after \".set noat\""));
13534 /* Implement macros in mips16 mode. */
13537 mips16_macro (struct mips_cl_insn
*ip
)
13539 const struct mips_operand_array
*operands
;
13544 const char *s
, *s2
, *s3
;
13545 unsigned int op
[MAX_OPERANDS
];
13548 mask
= ip
->insn_mo
->mask
;
13550 operands
= insn_operands (ip
);
13551 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13552 if (operands
->operand
[i
])
13553 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13557 expr1
.X_op
= O_constant
;
13558 expr1
.X_op_symbol
= NULL
;
13559 expr1
.X_add_symbol
= NULL
;
13560 expr1
.X_add_number
= 1;
13571 /* Fall through. */
13577 /* Fall through. */
13581 start_noreorder ();
13582 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13583 expr1
.X_add_number
= 2;
13584 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13585 macro_build (NULL
, "break", "6", 7);
13587 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13588 since that causes an overflow. We should do that as well,
13589 but I don't see how to do the comparisons without a temporary
13592 macro_build (NULL
, s
, "x", op
[0]);
13611 start_noreorder ();
13612 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13613 expr1
.X_add_number
= 2;
13614 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13615 macro_build (NULL
, "break", "6", 7);
13617 macro_build (NULL
, s2
, "x", op
[0]);
13622 /* Fall through. */
13624 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13625 macro_build (NULL
, "mflo", "x", op
[0]);
13633 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13634 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13638 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13639 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13643 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13644 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13666 goto do_reverse_branch
;
13670 goto do_reverse_branch
;
13682 goto do_reverse_branch
;
13693 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13694 macro_build (&offset_expr
, s2
, "p");
13721 goto do_addone_branch_i
;
13726 goto do_addone_branch_i
;
13741 goto do_addone_branch_i
;
13747 do_addone_branch_i
:
13748 ++imm_expr
.X_add_number
;
13751 macro_build (&imm_expr
, s
, s3
, op
[0]);
13752 macro_build (&offset_expr
, s2
, "p");
13756 expr1
.X_add_number
= 0;
13757 macro_build (&expr1
, "slti", "x,8", op
[1]);
13758 if (op
[0] != op
[1])
13759 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13760 expr1
.X_add_number
= 2;
13761 macro_build (&expr1
, "bteqz", "p");
13762 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13767 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13768 opcode bits in *OPCODE_EXTRA. */
13770 static struct mips_opcode
*
13771 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13772 ssize_t length
, unsigned int *opcode_extra
)
13774 char *name
, *dot
, *p
;
13775 unsigned int mask
, suffix
;
13777 struct mips_opcode
*insn
;
13779 /* Make a copy of the instruction so that we can fiddle with it. */
13780 name
= xstrndup (start
, length
);
13782 /* Look up the instruction as-is. */
13783 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13787 dot
= strchr (name
, '.');
13790 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13791 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13792 if (*p
== 0 && mask
!= 0)
13795 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13797 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13799 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13805 if (mips_opts
.micromips
)
13807 /* See if there's an instruction size override suffix,
13808 either `16' or `32', at the end of the mnemonic proper,
13809 that defines the operation, i.e. before the first `.'
13810 character if any. Strip it and retry. */
13811 opend
= dot
!= NULL
? dot
- name
: length
;
13812 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13814 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13820 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13821 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13824 forced_insn_length
= suffix
;
13836 /* Assemble an instruction into its binary format. If the instruction
13837 is a macro, set imm_expr and offset_expr to the values associated
13838 with "I" and "A" operands respectively. Otherwise store the value
13839 of the relocatable field (if any) in offset_expr. In both cases
13840 set offset_reloc to the relocation operators applied to offset_expr. */
13843 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13845 const struct mips_opcode
*first
, *past
;
13846 struct hash_control
*hash
;
13849 struct mips_operand_token
*tokens
;
13850 unsigned int opcode_extra
;
13852 if (mips_opts
.micromips
)
13854 hash
= micromips_op_hash
;
13855 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13860 past
= &mips_opcodes
[NUMOPCODES
];
13862 forced_insn_length
= 0;
13865 /* We first try to match an instruction up to a space or to the end. */
13866 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13869 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13872 set_insn_error (0, _("unrecognized opcode"));
13876 if (strcmp (first
->name
, "li.s") == 0)
13878 else if (strcmp (first
->name
, "li.d") == 0)
13882 tokens
= mips_parse_arguments (str
+ end
, format
);
13886 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13887 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13888 set_insn_error (0, _("invalid operands"));
13890 obstack_free (&mips_operand_tokens
, tokens
);
13893 /* As for mips_ip, but used when assembling MIPS16 code.
13894 Also set forced_insn_length to the resulting instruction size in
13895 bytes if the user explicitly requested a small or extended instruction. */
13898 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13901 struct mips_opcode
*first
;
13902 struct mips_operand_token
*tokens
;
13905 for (s
= str
; ISLOWER (*s
); ++s
)
13927 else if (*s
== 'e')
13934 else if (*s
++ == ' ')
13936 /* Fall through. */
13938 set_insn_error (0, _("unrecognized opcode"));
13941 forced_insn_length
= l
;
13944 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13949 set_insn_error (0, _("unrecognized opcode"));
13953 tokens
= mips_parse_arguments (s
, 0);
13957 if (!match_mips16_insns (insn
, first
, tokens
))
13958 set_insn_error (0, _("invalid operands"));
13960 obstack_free (&mips_operand_tokens
, tokens
);
13963 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13964 NBITS is the number of significant bits in VAL. */
13966 static unsigned long
13967 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13972 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13975 else if (nbits
== 15)
13977 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13982 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13985 return (extval
<< 16) | val
;
13988 /* Like decode_mips16_operand, but require the operand to be defined and
13989 require it to be an integer. */
13991 static const struct mips_int_operand
*
13992 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13994 const struct mips_operand
*operand
;
13996 operand
= decode_mips16_operand (type
, extended_p
);
13997 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13999 return (const struct mips_int_operand
*) operand
;
14002 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14005 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14006 bfd_reloc_code_real_type reloc
, offsetT sval
)
14008 int min_val
, max_val
;
14010 min_val
= mips_int_operand_min (operand
);
14011 max_val
= mips_int_operand_max (operand
);
14012 if (reloc
!= BFD_RELOC_UNUSED
)
14015 sval
= SEXT_16BIT (sval
);
14020 return (sval
>= min_val
14022 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14025 /* Install immediate value VAL into MIPS16 instruction *INSN,
14026 extending it if necessary. The instruction in *INSN may
14027 already be extended.
14029 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14030 if none. In the former case, VAL is a 16-bit number with no
14031 defined signedness.
14033 TYPE is the type of the immediate field. USER_INSN_LENGTH
14034 is the length that the user requested, or 0 if none. */
14037 mips16_immed (const char *file
, unsigned int line
, int type
,
14038 bfd_reloc_code_real_type reloc
, offsetT val
,
14039 unsigned int user_insn_length
, unsigned long *insn
)
14041 const struct mips_int_operand
*operand
;
14042 unsigned int uval
, length
;
14044 operand
= mips16_immed_operand (type
, FALSE
);
14045 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14047 /* We need an extended instruction. */
14048 if (user_insn_length
== 2)
14049 as_bad_where (file
, line
, _("invalid unextended operand value"));
14051 *insn
|= MIPS16_EXTEND
;
14053 else if (user_insn_length
== 4)
14055 /* The operand doesn't force an unextended instruction to be extended.
14056 Warn if the user wanted an extended instruction anyway. */
14057 *insn
|= MIPS16_EXTEND
;
14058 as_warn_where (file
, line
,
14059 _("extended operand requested but not required"));
14062 length
= mips16_opcode_length (*insn
);
14065 operand
= mips16_immed_operand (type
, TRUE
);
14066 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14067 as_bad_where (file
, line
,
14068 _("operand value out of range for instruction"));
14070 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14071 if (length
== 2 || operand
->root
.lsb
!= 0)
14072 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14074 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14077 struct percent_op_match
14080 bfd_reloc_code_real_type reloc
;
14083 static const struct percent_op_match mips_percent_op
[] =
14085 {"%lo", BFD_RELOC_LO16
},
14086 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14087 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14088 {"%call16", BFD_RELOC_MIPS_CALL16
},
14089 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14090 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14091 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14092 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14093 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14094 {"%got", BFD_RELOC_MIPS_GOT16
},
14095 {"%gp_rel", BFD_RELOC_GPREL16
},
14096 {"%gprel", BFD_RELOC_GPREL16
},
14097 {"%half", BFD_RELOC_16
},
14098 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14099 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14100 {"%neg", BFD_RELOC_MIPS_SUB
},
14101 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14102 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14103 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14104 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14105 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14106 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14107 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14108 {"%hi", BFD_RELOC_HI16_S
},
14109 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14110 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14113 static const struct percent_op_match mips16_percent_op
[] =
14115 {"%lo", BFD_RELOC_MIPS16_LO16
},
14116 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14117 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14118 {"%got", BFD_RELOC_MIPS16_GOT16
},
14119 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14120 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14121 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14122 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14123 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14124 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14125 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14126 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14127 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14131 /* Return true if *STR points to a relocation operator. When returning true,
14132 move *STR over the operator and store its relocation code in *RELOC.
14133 Leave both *STR and *RELOC alone when returning false. */
14136 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14138 const struct percent_op_match
*percent_op
;
14141 if (mips_opts
.mips16
)
14143 percent_op
= mips16_percent_op
;
14144 limit
= ARRAY_SIZE (mips16_percent_op
);
14148 percent_op
= mips_percent_op
;
14149 limit
= ARRAY_SIZE (mips_percent_op
);
14152 for (i
= 0; i
< limit
; i
++)
14153 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14155 int len
= strlen (percent_op
[i
].str
);
14157 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14160 *str
+= strlen (percent_op
[i
].str
);
14161 *reloc
= percent_op
[i
].reloc
;
14163 /* Check whether the output BFD supports this relocation.
14164 If not, issue an error and fall back on something safe. */
14165 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14167 as_bad (_("relocation %s isn't supported by the current ABI"),
14168 percent_op
[i
].str
);
14169 *reloc
= BFD_RELOC_UNUSED
;
14177 /* Parse string STR as a 16-bit relocatable operand. Store the
14178 expression in *EP and the relocations in the array starting
14179 at RELOC. Return the number of relocation operators used.
14181 On exit, EXPR_END points to the first character after the expression. */
14184 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14187 bfd_reloc_code_real_type reversed_reloc
[3];
14188 size_t reloc_index
, i
;
14189 int crux_depth
, str_depth
;
14192 /* Search for the start of the main expression, recoding relocations
14193 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14194 of the main expression and with CRUX_DEPTH containing the number
14195 of open brackets at that point. */
14202 crux_depth
= str_depth
;
14204 /* Skip over whitespace and brackets, keeping count of the number
14206 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14211 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14212 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14214 my_getExpression (ep
, crux
);
14217 /* Match every open bracket. */
14218 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14222 if (crux_depth
> 0)
14223 as_bad (_("unclosed '('"));
14227 if (reloc_index
!= 0)
14229 prev_reloc_op_frag
= frag_now
;
14230 for (i
= 0; i
< reloc_index
; i
++)
14231 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14234 return reloc_index
;
14238 my_getExpression (expressionS
*ep
, char *str
)
14242 save_in
= input_line_pointer
;
14243 input_line_pointer
= str
;
14245 expr_end
= input_line_pointer
;
14246 input_line_pointer
= save_in
;
14250 md_atof (int type
, char *litP
, int *sizeP
)
14252 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14256 md_number_to_chars (char *buf
, valueT val
, int n
)
14258 if (target_big_endian
)
14259 number_to_chars_bigendian (buf
, val
, n
);
14261 number_to_chars_littleendian (buf
, val
, n
);
14264 static int support_64bit_objects(void)
14266 const char **list
, **l
;
14269 list
= bfd_target_list ();
14270 for (l
= list
; *l
!= NULL
; l
++)
14271 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14272 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14274 yes
= (*l
!= NULL
);
14279 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14280 NEW_VALUE. Warn if another value was already specified. Note:
14281 we have to defer parsing the -march and -mtune arguments in order
14282 to handle 'from-abi' correctly, since the ABI might be specified
14283 in a later argument. */
14286 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14288 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14289 as_warn (_("a different %s was already specified, is now %s"),
14290 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14293 *string_ptr
= new_value
;
14297 md_parse_option (int c
, const char *arg
)
14301 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14302 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14304 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14305 c
== mips_ases
[i
].option_on
);
14311 case OPTION_CONSTRUCT_FLOATS
:
14312 mips_disable_float_construction
= 0;
14315 case OPTION_NO_CONSTRUCT_FLOATS
:
14316 mips_disable_float_construction
= 1;
14328 target_big_endian
= 1;
14332 target_big_endian
= 0;
14338 else if (arg
[0] == '0')
14340 else if (arg
[0] == '1')
14350 mips_debug
= atoi (arg
);
14354 file_mips_opts
.isa
= ISA_MIPS1
;
14358 file_mips_opts
.isa
= ISA_MIPS2
;
14362 file_mips_opts
.isa
= ISA_MIPS3
;
14366 file_mips_opts
.isa
= ISA_MIPS4
;
14370 file_mips_opts
.isa
= ISA_MIPS5
;
14373 case OPTION_MIPS32
:
14374 file_mips_opts
.isa
= ISA_MIPS32
;
14377 case OPTION_MIPS32R2
:
14378 file_mips_opts
.isa
= ISA_MIPS32R2
;
14381 case OPTION_MIPS32R3
:
14382 file_mips_opts
.isa
= ISA_MIPS32R3
;
14385 case OPTION_MIPS32R5
:
14386 file_mips_opts
.isa
= ISA_MIPS32R5
;
14389 case OPTION_MIPS32R6
:
14390 file_mips_opts
.isa
= ISA_MIPS32R6
;
14393 case OPTION_MIPS64R2
:
14394 file_mips_opts
.isa
= ISA_MIPS64R2
;
14397 case OPTION_MIPS64R3
:
14398 file_mips_opts
.isa
= ISA_MIPS64R3
;
14401 case OPTION_MIPS64R5
:
14402 file_mips_opts
.isa
= ISA_MIPS64R5
;
14405 case OPTION_MIPS64R6
:
14406 file_mips_opts
.isa
= ISA_MIPS64R6
;
14409 case OPTION_MIPS64
:
14410 file_mips_opts
.isa
= ISA_MIPS64
;
14414 mips_set_option_string (&mips_tune_string
, arg
);
14418 mips_set_option_string (&mips_arch_string
, arg
);
14422 mips_set_option_string (&mips_arch_string
, "4650");
14423 mips_set_option_string (&mips_tune_string
, "4650");
14426 case OPTION_NO_M4650
:
14430 mips_set_option_string (&mips_arch_string
, "4010");
14431 mips_set_option_string (&mips_tune_string
, "4010");
14434 case OPTION_NO_M4010
:
14438 mips_set_option_string (&mips_arch_string
, "4100");
14439 mips_set_option_string (&mips_tune_string
, "4100");
14442 case OPTION_NO_M4100
:
14446 mips_set_option_string (&mips_arch_string
, "3900");
14447 mips_set_option_string (&mips_tune_string
, "3900");
14450 case OPTION_NO_M3900
:
14453 case OPTION_MICROMIPS
:
14454 if (file_mips_opts
.mips16
== 1)
14456 as_bad (_("-mmicromips cannot be used with -mips16"));
14459 file_mips_opts
.micromips
= 1;
14460 mips_no_prev_insn ();
14463 case OPTION_NO_MICROMIPS
:
14464 file_mips_opts
.micromips
= 0;
14465 mips_no_prev_insn ();
14468 case OPTION_MIPS16
:
14469 if (file_mips_opts
.micromips
== 1)
14471 as_bad (_("-mips16 cannot be used with -micromips"));
14474 file_mips_opts
.mips16
= 1;
14475 mips_no_prev_insn ();
14478 case OPTION_NO_MIPS16
:
14479 file_mips_opts
.mips16
= 0;
14480 mips_no_prev_insn ();
14483 case OPTION_FIX_24K
:
14487 case OPTION_NO_FIX_24K
:
14491 case OPTION_FIX_RM7000
:
14492 mips_fix_rm7000
= 1;
14495 case OPTION_NO_FIX_RM7000
:
14496 mips_fix_rm7000
= 0;
14499 case OPTION_FIX_LOONGSON2F_JUMP
:
14500 mips_fix_loongson2f_jump
= TRUE
;
14503 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14504 mips_fix_loongson2f_jump
= FALSE
;
14507 case OPTION_FIX_LOONGSON2F_NOP
:
14508 mips_fix_loongson2f_nop
= TRUE
;
14511 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14512 mips_fix_loongson2f_nop
= FALSE
;
14515 case OPTION_FIX_VR4120
:
14516 mips_fix_vr4120
= 1;
14519 case OPTION_NO_FIX_VR4120
:
14520 mips_fix_vr4120
= 0;
14523 case OPTION_FIX_VR4130
:
14524 mips_fix_vr4130
= 1;
14527 case OPTION_NO_FIX_VR4130
:
14528 mips_fix_vr4130
= 0;
14531 case OPTION_FIX_CN63XXP1
:
14532 mips_fix_cn63xxp1
= TRUE
;
14535 case OPTION_NO_FIX_CN63XXP1
:
14536 mips_fix_cn63xxp1
= FALSE
;
14539 case OPTION_RELAX_BRANCH
:
14540 mips_relax_branch
= 1;
14543 case OPTION_NO_RELAX_BRANCH
:
14544 mips_relax_branch
= 0;
14547 case OPTION_IGNORE_BRANCH_ISA
:
14548 mips_ignore_branch_isa
= TRUE
;
14551 case OPTION_NO_IGNORE_BRANCH_ISA
:
14552 mips_ignore_branch_isa
= FALSE
;
14555 case OPTION_INSN32
:
14556 file_mips_opts
.insn32
= TRUE
;
14559 case OPTION_NO_INSN32
:
14560 file_mips_opts
.insn32
= FALSE
;
14563 case OPTION_MSHARED
:
14564 mips_in_shared
= TRUE
;
14567 case OPTION_MNO_SHARED
:
14568 mips_in_shared
= FALSE
;
14571 case OPTION_MSYM32
:
14572 file_mips_opts
.sym32
= TRUE
;
14575 case OPTION_MNO_SYM32
:
14576 file_mips_opts
.sym32
= FALSE
;
14579 /* When generating ELF code, we permit -KPIC and -call_shared to
14580 select SVR4_PIC, and -non_shared to select no PIC. This is
14581 intended to be compatible with Irix 5. */
14582 case OPTION_CALL_SHARED
:
14583 mips_pic
= SVR4_PIC
;
14584 mips_abicalls
= TRUE
;
14587 case OPTION_CALL_NONPIC
:
14589 mips_abicalls
= TRUE
;
14592 case OPTION_NON_SHARED
:
14594 mips_abicalls
= FALSE
;
14597 /* The -xgot option tells the assembler to use 32 bit offsets
14598 when accessing the got in SVR4_PIC mode. It is for Irix
14605 g_switch_value
= atoi (arg
);
14609 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14612 mips_abi
= O32_ABI
;
14616 mips_abi
= N32_ABI
;
14620 mips_abi
= N64_ABI
;
14621 if (!support_64bit_objects())
14622 as_fatal (_("no compiled in support for 64 bit object file format"));
14626 file_mips_opts
.gp
= 32;
14630 file_mips_opts
.gp
= 64;
14634 file_mips_opts
.fp
= 32;
14638 file_mips_opts
.fp
= 0;
14642 file_mips_opts
.fp
= 64;
14645 case OPTION_ODD_SPREG
:
14646 file_mips_opts
.oddspreg
= 1;
14649 case OPTION_NO_ODD_SPREG
:
14650 file_mips_opts
.oddspreg
= 0;
14653 case OPTION_SINGLE_FLOAT
:
14654 file_mips_opts
.single_float
= 1;
14657 case OPTION_DOUBLE_FLOAT
:
14658 file_mips_opts
.single_float
= 0;
14661 case OPTION_SOFT_FLOAT
:
14662 file_mips_opts
.soft_float
= 1;
14665 case OPTION_HARD_FLOAT
:
14666 file_mips_opts
.soft_float
= 0;
14670 if (strcmp (arg
, "32") == 0)
14671 mips_abi
= O32_ABI
;
14672 else if (strcmp (arg
, "o64") == 0)
14673 mips_abi
= O64_ABI
;
14674 else if (strcmp (arg
, "n32") == 0)
14675 mips_abi
= N32_ABI
;
14676 else if (strcmp (arg
, "64") == 0)
14678 mips_abi
= N64_ABI
;
14679 if (! support_64bit_objects())
14680 as_fatal (_("no compiled in support for 64 bit object file "
14683 else if (strcmp (arg
, "eabi") == 0)
14684 mips_abi
= EABI_ABI
;
14687 as_fatal (_("invalid abi -mabi=%s"), arg
);
14692 case OPTION_M7000_HILO_FIX
:
14693 mips_7000_hilo_fix
= TRUE
;
14696 case OPTION_MNO_7000_HILO_FIX
:
14697 mips_7000_hilo_fix
= FALSE
;
14700 case OPTION_MDEBUG
:
14701 mips_flag_mdebug
= TRUE
;
14704 case OPTION_NO_MDEBUG
:
14705 mips_flag_mdebug
= FALSE
;
14709 mips_flag_pdr
= TRUE
;
14712 case OPTION_NO_PDR
:
14713 mips_flag_pdr
= FALSE
;
14716 case OPTION_MVXWORKS_PIC
:
14717 mips_pic
= VXWORKS_PIC
;
14721 if (strcmp (arg
, "2008") == 0)
14723 else if (strcmp (arg
, "legacy") == 0)
14727 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14736 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14741 /* Set up globals to tune for the ISA or processor described by INFO. */
14744 mips_set_tune (const struct mips_cpu_info
*info
)
14747 mips_tune
= info
->cpu
;
14752 mips_after_parse_args (void)
14754 const struct mips_cpu_info
*arch_info
= 0;
14755 const struct mips_cpu_info
*tune_info
= 0;
14757 /* GP relative stuff not working for PE */
14758 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14760 if (g_switch_seen
&& g_switch_value
!= 0)
14761 as_bad (_("-G not supported in this configuration"));
14762 g_switch_value
= 0;
14765 if (mips_abi
== NO_ABI
)
14766 mips_abi
= MIPS_DEFAULT_ABI
;
14768 /* The following code determines the architecture.
14769 Similar code was added to GCC 3.3 (see override_options() in
14770 config/mips/mips.c). The GAS and GCC code should be kept in sync
14771 as much as possible. */
14773 if (mips_arch_string
!= 0)
14774 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14776 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14778 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14779 ISA level specified by -mipsN, while arch_info->isa contains
14780 the -march selection (if any). */
14781 if (arch_info
!= 0)
14783 /* -march takes precedence over -mipsN, since it is more descriptive.
14784 There's no harm in specifying both as long as the ISA levels
14786 if (file_mips_opts
.isa
!= arch_info
->isa
)
14787 as_bad (_("-%s conflicts with the other architecture options,"
14788 " which imply -%s"),
14789 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14790 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14793 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14796 if (arch_info
== 0)
14798 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14799 gas_assert (arch_info
);
14802 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14803 as_bad (_("-march=%s is not compatible with the selected ABI"),
14806 file_mips_opts
.arch
= arch_info
->cpu
;
14807 file_mips_opts
.isa
= arch_info
->isa
;
14809 /* Set up initial mips_opts state. */
14810 mips_opts
= file_mips_opts
;
14812 /* The register size inference code is now placed in
14813 file_mips_check_options. */
14815 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14817 if (mips_tune_string
!= 0)
14818 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14820 if (tune_info
== 0)
14821 mips_set_tune (arch_info
);
14823 mips_set_tune (tune_info
);
14825 if (mips_flag_mdebug
< 0)
14826 mips_flag_mdebug
= 0;
14830 mips_init_after_args (void)
14832 /* initialize opcodes */
14833 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14834 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14838 md_pcrel_from (fixS
*fixP
)
14840 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14841 switch (fixP
->fx_r_type
)
14843 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14844 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14845 /* Return the address of the delay slot. */
14848 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14849 case BFD_RELOC_MICROMIPS_JMP
:
14850 case BFD_RELOC_MIPS16_16_PCREL_S1
:
14851 case BFD_RELOC_16_PCREL_S2
:
14852 case BFD_RELOC_MIPS_21_PCREL_S2
:
14853 case BFD_RELOC_MIPS_26_PCREL_S2
:
14854 case BFD_RELOC_MIPS_JMP
:
14855 /* Return the address of the delay slot. */
14858 case BFD_RELOC_MIPS_18_PCREL_S3
:
14859 /* Return the aligned address of the doubleword containing
14860 the instruction. */
14868 /* This is called before the symbol table is processed. In order to
14869 work with gcc when using mips-tfile, we must keep all local labels.
14870 However, in other cases, we want to discard them. If we were
14871 called with -g, but we didn't see any debugging information, it may
14872 mean that gcc is smuggling debugging information through to
14873 mips-tfile, in which case we must generate all local labels. */
14876 mips_frob_file_before_adjust (void)
14878 #ifndef NO_ECOFF_DEBUGGING
14879 if (ECOFF_DEBUGGING
14881 && ! ecoff_debugging_seen
)
14882 flag_keep_locals
= 1;
14886 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14887 the corresponding LO16 reloc. This is called before md_apply_fix and
14888 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14889 relocation operators.
14891 For our purposes, a %lo() expression matches a %got() or %hi()
14894 (a) it refers to the same symbol; and
14895 (b) the offset applied in the %lo() expression is no lower than
14896 the offset applied in the %got() or %hi().
14898 (b) allows us to cope with code like:
14901 lh $4,%lo(foo+2)($4)
14903 ...which is legal on RELA targets, and has a well-defined behaviour
14904 if the user knows that adding 2 to "foo" will not induce a carry to
14907 When several %lo()s match a particular %got() or %hi(), we use the
14908 following rules to distinguish them:
14910 (1) %lo()s with smaller offsets are a better match than %lo()s with
14913 (2) %lo()s with no matching %got() or %hi() are better than those
14914 that already have a matching %got() or %hi().
14916 (3) later %lo()s are better than earlier %lo()s.
14918 These rules are applied in order.
14920 (1) means, among other things, that %lo()s with identical offsets are
14921 chosen if they exist.
14923 (2) means that we won't associate several high-part relocations with
14924 the same low-part relocation unless there's no alternative. Having
14925 several high parts for the same low part is a GNU extension; this rule
14926 allows careful users to avoid it.
14928 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14929 with the last high-part relocation being at the front of the list.
14930 It therefore makes sense to choose the last matching low-part
14931 relocation, all other things being equal. It's also easier
14932 to code that way. */
14935 mips_frob_file (void)
14937 struct mips_hi_fixup
*l
;
14938 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14940 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14942 segment_info_type
*seginfo
;
14943 bfd_boolean matched_lo_p
;
14944 fixS
**hi_pos
, **lo_pos
, **pos
;
14946 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14948 /* If a GOT16 relocation turns out to be against a global symbol,
14949 there isn't supposed to be a matching LO. Ignore %gots against
14950 constants; we'll report an error for those later. */
14951 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14952 && !(l
->fixp
->fx_addsy
14953 && pic_need_relax (l
->fixp
->fx_addsy
)))
14956 /* Check quickly whether the next fixup happens to be a matching %lo. */
14957 if (fixup_has_matching_lo_p (l
->fixp
))
14960 seginfo
= seg_info (l
->seg
);
14962 /* Set HI_POS to the position of this relocation in the chain.
14963 Set LO_POS to the position of the chosen low-part relocation.
14964 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14965 relocation that matches an immediately-preceding high-part
14969 matched_lo_p
= FALSE
;
14970 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14972 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14974 if (*pos
== l
->fixp
)
14977 if ((*pos
)->fx_r_type
== looking_for_rtype
14978 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14979 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14981 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14983 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14986 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14987 && fixup_has_matching_lo_p (*pos
));
14990 /* If we found a match, remove the high-part relocation from its
14991 current position and insert it before the low-part relocation.
14992 Make the offsets match so that fixup_has_matching_lo_p()
14995 We don't warn about unmatched high-part relocations since some
14996 versions of gcc have been known to emit dead "lui ...%hi(...)"
14998 if (lo_pos
!= NULL
)
15000 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15001 if (l
->fixp
->fx_next
!= *lo_pos
)
15003 *hi_pos
= l
->fixp
->fx_next
;
15004 l
->fixp
->fx_next
= *lo_pos
;
15012 mips_force_relocation (fixS
*fixp
)
15014 if (generic_force_reloc (fixp
))
15017 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15018 so that the linker relaxation can update targets. */
15019 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15020 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15021 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15024 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15025 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15026 microMIPS symbols so that we can do cross-mode branch diagnostics
15027 and BAL to JALX conversion by the linker. */
15028 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15029 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15030 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15032 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15035 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15036 if (ISA_IS_R6 (file_mips_opts
.isa
)
15037 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15038 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15039 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15040 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15041 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15042 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15043 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15049 /* Implement TC_FORCE_RELOCATION_ABS. */
15052 mips_force_relocation_abs (fixS
*fixp
)
15054 if (generic_force_reloc (fixp
))
15057 /* These relocations do not have enough bits in the in-place addend
15058 to hold an arbitrary absolute section's offset. */
15059 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15065 /* Read the instruction associated with RELOC from BUF. */
15067 static unsigned int
15068 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15070 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15071 return read_compressed_insn (buf
, 4);
15073 return read_insn (buf
);
15076 /* Write instruction INSN to BUF, given that it has been relocated
15080 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15081 unsigned long insn
)
15083 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15084 write_compressed_insn (buf
, insn
, 4);
15086 write_insn (buf
, insn
);
15089 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15090 to a symbol in another ISA mode, which cannot be converted to JALX. */
15093 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15095 unsigned long opcode
;
15099 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15102 other
= S_GET_OTHER (fixP
->fx_addsy
);
15103 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15104 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15105 switch (fixP
->fx_r_type
)
15107 case BFD_RELOC_MIPS_JMP
:
15108 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15109 case BFD_RELOC_MICROMIPS_JMP
:
15110 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15116 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15117 jump to a symbol in the same ISA mode. */
15120 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15122 unsigned long opcode
;
15126 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15129 other
= S_GET_OTHER (fixP
->fx_addsy
);
15130 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15131 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15132 switch (fixP
->fx_r_type
)
15134 case BFD_RELOC_MIPS_JMP
:
15135 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15136 case BFD_RELOC_MIPS16_JMP
:
15137 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15138 case BFD_RELOC_MICROMIPS_JMP
:
15139 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15145 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15146 to a symbol whose value plus addend is not aligned according to the
15147 ultimate (after linker relaxation) jump instruction's immediate field
15148 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15149 regular MIPS code, to (1 << 2). */
15152 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15154 bfd_boolean micro_to_mips_p
;
15158 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15161 other
= S_GET_OTHER (fixP
->fx_addsy
);
15162 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15163 val
+= fixP
->fx_offset
;
15164 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15165 && !ELF_ST_IS_MICROMIPS (other
));
15166 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15167 != ELF_ST_IS_COMPRESSED (other
));
15170 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15171 to a symbol whose annotation indicates another ISA mode. For absolute
15172 symbols check the ISA bit instead.
15174 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15175 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15176 MIPS symbols and associated with BAL instructions as these instructions
15177 may be be converted to JALX by the linker. */
15180 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15182 bfd_boolean absolute_p
;
15183 unsigned long opcode
;
15189 if (mips_ignore_branch_isa
)
15192 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15195 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15196 absolute_p
= bfd_is_abs_section (symsec
);
15198 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15199 other
= S_GET_OTHER (fixP
->fx_addsy
);
15201 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15202 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15203 switch (fixP
->fx_r_type
)
15205 case BFD_RELOC_16_PCREL_S2
:
15206 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15207 && opcode
!= 0x0411);
15208 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15209 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15210 && opcode
!= 0x4060);
15211 case BFD_RELOC_MIPS_21_PCREL_S2
:
15212 case BFD_RELOC_MIPS_26_PCREL_S2
:
15213 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15214 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15215 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15216 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15217 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15218 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15224 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15225 branch instruction pointed to by FIXP is not aligned according to the
15226 branch instruction's immediate field requirement. We need the addend
15227 to preserve the ISA bit and also the sum must not have bit 2 set. We
15228 must explicitly OR in the ISA bit from symbol annotation as the bit
15229 won't be set in the symbol's value then. */
15232 fix_bad_misaligned_branch_p (fixS
*fixP
)
15234 bfd_boolean absolute_p
;
15241 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15244 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15245 absolute_p
= bfd_is_abs_section (symsec
);
15247 val
= S_GET_VALUE (fixP
->fx_addsy
);
15248 other
= S_GET_OTHER (fixP
->fx_addsy
);
15249 off
= fixP
->fx_offset
;
15251 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15252 val
|= ELF_ST_IS_COMPRESSED (other
);
15254 return (val
& 0x3) != isa_bit
;
15257 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15258 and its calculated value VAL. */
15261 fix_validate_branch (fixS
*fixP
, valueT val
)
15263 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15265 _("branch to misaligned address (0x%lx)"),
15266 (long) (val
+ md_pcrel_from (fixP
)));
15267 else if (fix_bad_cross_mode_branch_p (fixP
))
15268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15269 _("branch to a symbol in another ISA mode"));
15270 else if (fix_bad_misaligned_branch_p (fixP
))
15271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15272 _("branch to misaligned address (0x%lx)"),
15273 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15274 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15276 _("cannot encode misaligned addend "
15277 "in the relocatable field (0x%lx)"),
15278 (long) fixP
->fx_offset
);
15281 /* Apply a fixup to the object file. */
15284 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15287 unsigned long insn
;
15288 reloc_howto_type
*howto
;
15290 if (fixP
->fx_pcrel
)
15291 switch (fixP
->fx_r_type
)
15293 case BFD_RELOC_16_PCREL_S2
:
15294 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15295 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15296 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15297 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15298 case BFD_RELOC_32_PCREL
:
15299 case BFD_RELOC_MIPS_21_PCREL_S2
:
15300 case BFD_RELOC_MIPS_26_PCREL_S2
:
15301 case BFD_RELOC_MIPS_18_PCREL_S3
:
15302 case BFD_RELOC_MIPS_19_PCREL_S2
:
15303 case BFD_RELOC_HI16_S_PCREL
:
15304 case BFD_RELOC_LO16_PCREL
:
15308 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15313 _("PC-relative reference to a different section"));
15317 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15318 that have no MIPS ELF equivalent. */
15319 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15321 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15326 gas_assert (fixP
->fx_size
== 2
15327 || fixP
->fx_size
== 4
15328 || fixP
->fx_r_type
== BFD_RELOC_8
15329 || fixP
->fx_r_type
== BFD_RELOC_16
15330 || fixP
->fx_r_type
== BFD_RELOC_64
15331 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15332 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15333 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15334 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15335 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15336 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15337 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15339 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15341 /* Don't treat parts of a composite relocation as done. There are two
15344 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15345 should nevertheless be emitted if the first part is.
15347 (2) In normal usage, composite relocations are never assembly-time
15348 constants. The easiest way of dealing with the pathological
15349 exceptions is to generate a relocation against STN_UNDEF and
15350 leave everything up to the linker. */
15351 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15354 switch (fixP
->fx_r_type
)
15356 case BFD_RELOC_MIPS_TLS_GD
:
15357 case BFD_RELOC_MIPS_TLS_LDM
:
15358 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15359 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15360 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15361 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15362 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15363 case BFD_RELOC_MIPS_TLS_TPREL32
:
15364 case BFD_RELOC_MIPS_TLS_TPREL64
:
15365 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15366 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15367 case BFD_RELOC_MICROMIPS_TLS_GD
:
15368 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15369 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15370 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15371 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15372 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15373 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15374 case BFD_RELOC_MIPS16_TLS_GD
:
15375 case BFD_RELOC_MIPS16_TLS_LDM
:
15376 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15377 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15378 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15379 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15380 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15381 if (fixP
->fx_addsy
)
15382 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15385 _("TLS relocation against a constant"));
15388 case BFD_RELOC_MIPS_JMP
:
15389 case BFD_RELOC_MIPS16_JMP
:
15390 case BFD_RELOC_MICROMIPS_JMP
:
15394 gas_assert (!fixP
->fx_done
);
15396 /* Shift is 2, unusually, for microMIPS JALX. */
15397 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15398 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15403 if (fix_bad_cross_mode_jump_p (fixP
))
15404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15405 _("jump to a symbol in another ISA mode"));
15406 else if (fix_bad_same_mode_jalx_p (fixP
))
15407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15408 _("JALX to a symbol in the same ISA mode"));
15409 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15411 _("jump to misaligned address (0x%lx)"),
15412 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15413 + fixP
->fx_offset
));
15414 else if (HAVE_IN_PLACE_ADDENDS
15415 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15417 _("cannot encode misaligned addend "
15418 "in the relocatable field (0x%lx)"),
15419 (long) fixP
->fx_offset
);
15421 /* Fall through. */
15423 case BFD_RELOC_MIPS_SHIFT5
:
15424 case BFD_RELOC_MIPS_SHIFT6
:
15425 case BFD_RELOC_MIPS_GOT_DISP
:
15426 case BFD_RELOC_MIPS_GOT_PAGE
:
15427 case BFD_RELOC_MIPS_GOT_OFST
:
15428 case BFD_RELOC_MIPS_SUB
:
15429 case BFD_RELOC_MIPS_INSERT_A
:
15430 case BFD_RELOC_MIPS_INSERT_B
:
15431 case BFD_RELOC_MIPS_DELETE
:
15432 case BFD_RELOC_MIPS_HIGHEST
:
15433 case BFD_RELOC_MIPS_HIGHER
:
15434 case BFD_RELOC_MIPS_SCN_DISP
:
15435 case BFD_RELOC_MIPS_REL16
:
15436 case BFD_RELOC_MIPS_RELGOT
:
15437 case BFD_RELOC_MIPS_JALR
:
15438 case BFD_RELOC_HI16
:
15439 case BFD_RELOC_HI16_S
:
15440 case BFD_RELOC_LO16
:
15441 case BFD_RELOC_GPREL16
:
15442 case BFD_RELOC_MIPS_LITERAL
:
15443 case BFD_RELOC_MIPS_CALL16
:
15444 case BFD_RELOC_MIPS_GOT16
:
15445 case BFD_RELOC_GPREL32
:
15446 case BFD_RELOC_MIPS_GOT_HI16
:
15447 case BFD_RELOC_MIPS_GOT_LO16
:
15448 case BFD_RELOC_MIPS_CALL_HI16
:
15449 case BFD_RELOC_MIPS_CALL_LO16
:
15450 case BFD_RELOC_HI16_S_PCREL
:
15451 case BFD_RELOC_LO16_PCREL
:
15452 case BFD_RELOC_MIPS16_GPREL
:
15453 case BFD_RELOC_MIPS16_GOT16
:
15454 case BFD_RELOC_MIPS16_CALL16
:
15455 case BFD_RELOC_MIPS16_HI16
:
15456 case BFD_RELOC_MIPS16_HI16_S
:
15457 case BFD_RELOC_MIPS16_LO16
:
15458 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15459 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15460 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15461 case BFD_RELOC_MICROMIPS_SUB
:
15462 case BFD_RELOC_MICROMIPS_HIGHEST
:
15463 case BFD_RELOC_MICROMIPS_HIGHER
:
15464 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15465 case BFD_RELOC_MICROMIPS_JALR
:
15466 case BFD_RELOC_MICROMIPS_HI16
:
15467 case BFD_RELOC_MICROMIPS_HI16_S
:
15468 case BFD_RELOC_MICROMIPS_LO16
:
15469 case BFD_RELOC_MICROMIPS_GPREL16
:
15470 case BFD_RELOC_MICROMIPS_LITERAL
:
15471 case BFD_RELOC_MICROMIPS_CALL16
:
15472 case BFD_RELOC_MICROMIPS_GOT16
:
15473 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15474 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15475 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15476 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15477 case BFD_RELOC_MIPS_EH
:
15482 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15484 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15485 if (mips16_reloc_p (fixP
->fx_r_type
))
15486 insn
|= mips16_immed_extend (value
, 16);
15488 insn
|= (value
& 0xffff);
15489 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15492 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15493 _("unsupported constant in relocation"));
15498 /* This is handled like BFD_RELOC_32, but we output a sign
15499 extended value if we are only 32 bits. */
15502 if (8 <= sizeof (valueT
))
15503 md_number_to_chars (buf
, *valP
, 8);
15508 if ((*valP
& 0x80000000) != 0)
15512 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15513 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15518 case BFD_RELOC_RVA
:
15520 case BFD_RELOC_32_PCREL
:
15523 /* If we are deleting this reloc entry, we must fill in the
15524 value now. This can happen if we have a .word which is not
15525 resolved when it appears but is later defined. */
15527 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15530 case BFD_RELOC_MIPS_21_PCREL_S2
:
15531 fix_validate_branch (fixP
, *valP
);
15532 if (!fixP
->fx_done
)
15535 if (*valP
+ 0x400000 <= 0x7fffff)
15537 insn
= read_insn (buf
);
15538 insn
|= (*valP
>> 2) & 0x1fffff;
15539 write_insn (buf
, insn
);
15542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15543 _("branch out of range"));
15546 case BFD_RELOC_MIPS_26_PCREL_S2
:
15547 fix_validate_branch (fixP
, *valP
);
15548 if (!fixP
->fx_done
)
15551 if (*valP
+ 0x8000000 <= 0xfffffff)
15553 insn
= read_insn (buf
);
15554 insn
|= (*valP
>> 2) & 0x3ffffff;
15555 write_insn (buf
, insn
);
15558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15559 _("branch out of range"));
15562 case BFD_RELOC_MIPS_18_PCREL_S3
:
15563 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15565 _("PC-relative access using misaligned symbol (%lx)"),
15566 (long) S_GET_VALUE (fixP
->fx_addsy
));
15567 if ((fixP
->fx_offset
& 0x7) != 0)
15568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15569 _("PC-relative access using misaligned offset (%lx)"),
15570 (long) fixP
->fx_offset
);
15571 if (!fixP
->fx_done
)
15574 if (*valP
+ 0x100000 <= 0x1fffff)
15576 insn
= read_insn (buf
);
15577 insn
|= (*valP
>> 3) & 0x3ffff;
15578 write_insn (buf
, insn
);
15581 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15582 _("PC-relative access out of range"));
15585 case BFD_RELOC_MIPS_19_PCREL_S2
:
15586 if ((*valP
& 0x3) != 0)
15587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15588 _("PC-relative access to misaligned address (%lx)"),
15590 if (!fixP
->fx_done
)
15593 if (*valP
+ 0x100000 <= 0x1fffff)
15595 insn
= read_insn (buf
);
15596 insn
|= (*valP
>> 2) & 0x7ffff;
15597 write_insn (buf
, insn
);
15600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15601 _("PC-relative access out of range"));
15604 case BFD_RELOC_16_PCREL_S2
:
15605 fix_validate_branch (fixP
, *valP
);
15607 /* We need to save the bits in the instruction since fixup_segment()
15608 might be deleting the relocation entry (i.e., a branch within
15609 the current segment). */
15610 if (! fixP
->fx_done
)
15613 /* Update old instruction data. */
15614 insn
= read_insn (buf
);
15616 if (*valP
+ 0x20000 <= 0x3ffff)
15618 insn
|= (*valP
>> 2) & 0xffff;
15619 write_insn (buf
, insn
);
15621 else if (fixP
->fx_tcbit2
15623 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15624 && (fixP
->fx_frag
->fr_address
15625 < text_section
->vma
+ bfd_get_section_size (text_section
))
15626 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15627 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15628 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15630 /* The branch offset is too large. If this is an
15631 unconditional branch, and we are not generating PIC code,
15632 we can convert it to an absolute jump instruction. */
15633 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15634 insn
= 0x0c000000; /* jal */
15636 insn
= 0x08000000; /* j */
15637 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15639 fixP
->fx_addsy
= section_symbol (text_section
);
15640 *valP
+= md_pcrel_from (fixP
);
15641 write_insn (buf
, insn
);
15645 /* If we got here, we have branch-relaxation disabled,
15646 and there's nothing we can do to fix this instruction
15647 without turning it into a longer sequence. */
15648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15649 _("branch out of range"));
15653 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15654 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15655 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15656 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15657 gas_assert (!fixP
->fx_done
);
15658 if (fix_bad_cross_mode_branch_p (fixP
))
15659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15660 _("branch to a symbol in another ISA mode"));
15661 else if (fixP
->fx_addsy
15662 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15663 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15664 && (fixP
->fx_offset
& 0x1) != 0)
15665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15666 _("branch to misaligned address (0x%lx)"),
15667 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15668 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15670 _("cannot encode misaligned addend "
15671 "in the relocatable field (0x%lx)"),
15672 (long) fixP
->fx_offset
);
15675 case BFD_RELOC_VTABLE_INHERIT
:
15678 && !S_IS_DEFINED (fixP
->fx_addsy
)
15679 && !S_IS_WEAK (fixP
->fx_addsy
))
15680 S_SET_WEAK (fixP
->fx_addsy
);
15683 case BFD_RELOC_NONE
:
15684 case BFD_RELOC_VTABLE_ENTRY
:
15692 /* Remember value for tc_gen_reloc. */
15693 fixP
->fx_addnumber
= *valP
;
15703 c
= get_symbol_name (&name
);
15704 p
= (symbolS
*) symbol_find_or_make (name
);
15705 (void) restore_line_pointer (c
);
15709 /* Align the current frag to a given power of two. If a particular
15710 fill byte should be used, FILL points to an integer that contains
15711 that byte, otherwise FILL is null.
15713 This function used to have the comment:
15715 The MIPS assembler also automatically adjusts any preceding label.
15717 The implementation therefore applied the adjustment to a maximum of
15718 one label. However, other label adjustments are applied to batches
15719 of labels, and adjusting just one caused problems when new labels
15720 were added for the sake of debugging or unwind information.
15721 We therefore adjust all preceding labels (given as LABELS) instead. */
15724 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15726 mips_emit_delays ();
15727 mips_record_compressed_mode ();
15728 if (fill
== NULL
&& subseg_text_p (now_seg
))
15729 frag_align_code (to
, 0);
15731 frag_align (to
, fill
? *fill
: 0, 0);
15732 record_alignment (now_seg
, to
);
15733 mips_move_labels (labels
, FALSE
);
15736 /* Align to a given power of two. .align 0 turns off the automatic
15737 alignment used by the data creating pseudo-ops. */
15740 s_align (int x ATTRIBUTE_UNUSED
)
15742 int temp
, fill_value
, *fill_ptr
;
15743 long max_alignment
= 28;
15745 /* o Note that the assembler pulls down any immediately preceding label
15746 to the aligned address.
15747 o It's not documented but auto alignment is reinstated by
15748 a .align pseudo instruction.
15749 o Note also that after auto alignment is turned off the mips assembler
15750 issues an error on attempt to assemble an improperly aligned data item.
15753 temp
= get_absolute_expression ();
15754 if (temp
> max_alignment
)
15755 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15758 as_warn (_("alignment negative, 0 assumed"));
15761 if (*input_line_pointer
== ',')
15763 ++input_line_pointer
;
15764 fill_value
= get_absolute_expression ();
15765 fill_ptr
= &fill_value
;
15771 segment_info_type
*si
= seg_info (now_seg
);
15772 struct insn_label_list
*l
= si
->label_list
;
15773 /* Auto alignment should be switched on by next section change. */
15775 mips_align (temp
, fill_ptr
, l
);
15782 demand_empty_rest_of_line ();
15786 s_change_sec (int sec
)
15790 /* The ELF backend needs to know that we are changing sections, so
15791 that .previous works correctly. We could do something like check
15792 for an obj_section_change_hook macro, but that might be confusing
15793 as it would not be appropriate to use it in the section changing
15794 functions in read.c, since obj-elf.c intercepts those. FIXME:
15795 This should be cleaner, somehow. */
15796 obj_elf_section_change_hook ();
15798 mips_emit_delays ();
15809 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15810 demand_empty_rest_of_line ();
15814 seg
= subseg_new (RDATA_SECTION_NAME
,
15815 (subsegT
) get_absolute_expression ());
15816 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15817 | SEC_READONLY
| SEC_RELOC
15819 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15820 record_alignment (seg
, 4);
15821 demand_empty_rest_of_line ();
15825 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15826 bfd_set_section_flags (stdoutput
, seg
,
15827 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15828 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15829 record_alignment (seg
, 4);
15830 demand_empty_rest_of_line ();
15834 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15835 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15836 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15837 record_alignment (seg
, 4);
15838 demand_empty_rest_of_line ();
15846 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15849 char *section_name
;
15854 int section_entry_size
;
15855 int section_alignment
;
15857 saved_ilp
= input_line_pointer
;
15858 endc
= get_symbol_name (§ion_name
);
15859 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
15861 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
15863 /* Do we have .section Name<,"flags">? */
15864 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15866 /* Just after name is now '\0'. */
15867 (void) restore_line_pointer (endc
);
15868 input_line_pointer
= saved_ilp
;
15869 obj_elf_section (ignore
);
15873 section_name
= xstrdup (section_name
);
15874 c
= restore_line_pointer (endc
);
15876 input_line_pointer
++;
15878 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15880 section_type
= get_absolute_expression ();
15884 if (*input_line_pointer
++ == ',')
15885 section_flag
= get_absolute_expression ();
15889 if (*input_line_pointer
++ == ',')
15890 section_entry_size
= get_absolute_expression ();
15892 section_entry_size
= 0;
15894 if (*input_line_pointer
++ == ',')
15895 section_alignment
= get_absolute_expression ();
15897 section_alignment
= 0;
15899 /* FIXME: really ignore? */
15900 (void) section_alignment
;
15902 /* When using the generic form of .section (as implemented by obj-elf.c),
15903 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15904 traditionally had to fall back on the more common @progbits instead.
15906 There's nothing really harmful in this, since bfd will correct
15907 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15908 means that, for backwards compatibility, the special_section entries
15909 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15911 Even so, we shouldn't force users of the MIPS .section syntax to
15912 incorrectly label the sections as SHT_PROGBITS. The best compromise
15913 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15914 generic type-checking code. */
15915 if (section_type
== SHT_MIPS_DWARF
)
15916 section_type
= SHT_PROGBITS
;
15918 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
15919 section_entry_size
, 0, 0, 0);
15921 if (now_seg
->name
!= section_name
)
15922 free (section_name
);
15926 mips_enable_auto_align (void)
15932 s_cons (int log_size
)
15934 segment_info_type
*si
= seg_info (now_seg
);
15935 struct insn_label_list
*l
= si
->label_list
;
15937 mips_emit_delays ();
15938 if (log_size
> 0 && auto_align
)
15939 mips_align (log_size
, 0, l
);
15940 cons (1 << log_size
);
15941 mips_clear_insn_labels ();
15945 s_float_cons (int type
)
15947 segment_info_type
*si
= seg_info (now_seg
);
15948 struct insn_label_list
*l
= si
->label_list
;
15950 mips_emit_delays ();
15955 mips_align (3, 0, l
);
15957 mips_align (2, 0, l
);
15961 mips_clear_insn_labels ();
15964 /* Handle .globl. We need to override it because on Irix 5 you are
15967 where foo is an undefined symbol, to mean that foo should be
15968 considered to be the address of a function. */
15971 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15980 c
= get_symbol_name (&name
);
15981 symbolP
= symbol_find_or_make (name
);
15982 S_SET_EXTERNAL (symbolP
);
15984 *input_line_pointer
= c
;
15985 SKIP_WHITESPACE_AFTER_NAME ();
15987 /* On Irix 5, every global symbol that is not explicitly labelled as
15988 being a function is apparently labelled as being an object. */
15991 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15992 && (*input_line_pointer
!= ','))
15997 c
= get_symbol_name (&secname
);
15998 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16000 as_bad (_("%s: no such section"), secname
);
16001 (void) restore_line_pointer (c
);
16003 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16004 flag
= BSF_FUNCTION
;
16007 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16009 c
= *input_line_pointer
;
16012 input_line_pointer
++;
16013 SKIP_WHITESPACE ();
16014 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16020 demand_empty_rest_of_line ();
16024 s_option (int x ATTRIBUTE_UNUSED
)
16029 c
= get_symbol_name (&opt
);
16033 /* FIXME: What does this mean? */
16035 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16039 i
= atoi (opt
+ 3);
16040 if (i
!= 0 && i
!= 2)
16041 as_bad (_(".option pic%d not supported"), i
);
16042 else if (mips_pic
== VXWORKS_PIC
)
16043 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16048 mips_pic
= SVR4_PIC
;
16049 mips_abicalls
= TRUE
;
16052 if (mips_pic
== SVR4_PIC
)
16054 if (g_switch_seen
&& g_switch_value
!= 0)
16055 as_warn (_("-G may not be used with SVR4 PIC code"));
16056 g_switch_value
= 0;
16057 bfd_set_gp_size (stdoutput
, 0);
16061 as_warn (_("unrecognized option \"%s\""), opt
);
16063 (void) restore_line_pointer (c
);
16064 demand_empty_rest_of_line ();
16067 /* This structure is used to hold a stack of .set values. */
16069 struct mips_option_stack
16071 struct mips_option_stack
*next
;
16072 struct mips_set_options options
;
16075 static struct mips_option_stack
*mips_opts_stack
;
16077 /* Return status for .set/.module option handling. */
16079 enum code_option_type
16081 /* Unrecognized option. */
16082 OPTION_TYPE_BAD
= -1,
16084 /* Ordinary option. */
16085 OPTION_TYPE_NORMAL
,
16087 /* ISA changing option. */
16091 /* Handle common .set/.module options. Return status indicating option
16094 static enum code_option_type
16095 parse_code_option (char * name
)
16097 bfd_boolean isa_set
= FALSE
;
16098 const struct mips_ase
*ase
;
16100 if (strncmp (name
, "at=", 3) == 0)
16102 char *s
= name
+ 3;
16104 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16105 as_bad (_("unrecognized register name `%s'"), s
);
16107 else if (strcmp (name
, "at") == 0)
16108 mips_opts
.at
= ATREG
;
16109 else if (strcmp (name
, "noat") == 0)
16110 mips_opts
.at
= ZERO
;
16111 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16112 mips_opts
.nomove
= 0;
16113 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16114 mips_opts
.nomove
= 1;
16115 else if (strcmp (name
, "bopt") == 0)
16116 mips_opts
.nobopt
= 0;
16117 else if (strcmp (name
, "nobopt") == 0)
16118 mips_opts
.nobopt
= 1;
16119 else if (strcmp (name
, "gp=32") == 0)
16121 else if (strcmp (name
, "gp=64") == 0)
16123 else if (strcmp (name
, "fp=32") == 0)
16125 else if (strcmp (name
, "fp=xx") == 0)
16127 else if (strcmp (name
, "fp=64") == 0)
16129 else if (strcmp (name
, "softfloat") == 0)
16130 mips_opts
.soft_float
= 1;
16131 else if (strcmp (name
, "hardfloat") == 0)
16132 mips_opts
.soft_float
= 0;
16133 else if (strcmp (name
, "singlefloat") == 0)
16134 mips_opts
.single_float
= 1;
16135 else if (strcmp (name
, "doublefloat") == 0)
16136 mips_opts
.single_float
= 0;
16137 else if (strcmp (name
, "nooddspreg") == 0)
16138 mips_opts
.oddspreg
= 0;
16139 else if (strcmp (name
, "oddspreg") == 0)
16140 mips_opts
.oddspreg
= 1;
16141 else if (strcmp (name
, "mips16") == 0
16142 || strcmp (name
, "MIPS-16") == 0)
16143 mips_opts
.mips16
= 1;
16144 else if (strcmp (name
, "nomips16") == 0
16145 || strcmp (name
, "noMIPS-16") == 0)
16146 mips_opts
.mips16
= 0;
16147 else if (strcmp (name
, "micromips") == 0)
16148 mips_opts
.micromips
= 1;
16149 else if (strcmp (name
, "nomicromips") == 0)
16150 mips_opts
.micromips
= 0;
16151 else if (name
[0] == 'n'
16153 && (ase
= mips_lookup_ase (name
+ 2)))
16154 mips_set_ase (ase
, &mips_opts
, FALSE
);
16155 else if ((ase
= mips_lookup_ase (name
)))
16156 mips_set_ase (ase
, &mips_opts
, TRUE
);
16157 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16159 /* Permit the user to change the ISA and architecture on the fly.
16160 Needless to say, misuse can cause serious problems. */
16161 if (strncmp (name
, "arch=", 5) == 0)
16163 const struct mips_cpu_info
*p
;
16165 p
= mips_parse_cpu ("internal use", name
+ 5);
16167 as_bad (_("unknown architecture %s"), name
+ 5);
16170 mips_opts
.arch
= p
->cpu
;
16171 mips_opts
.isa
= p
->isa
;
16175 else if (strncmp (name
, "mips", 4) == 0)
16177 const struct mips_cpu_info
*p
;
16179 p
= mips_parse_cpu ("internal use", name
);
16181 as_bad (_("unknown ISA level %s"), name
+ 4);
16184 mips_opts
.arch
= p
->cpu
;
16185 mips_opts
.isa
= p
->isa
;
16190 as_bad (_("unknown ISA or architecture %s"), name
);
16192 else if (strcmp (name
, "autoextend") == 0)
16193 mips_opts
.noautoextend
= 0;
16194 else if (strcmp (name
, "noautoextend") == 0)
16195 mips_opts
.noautoextend
= 1;
16196 else if (strcmp (name
, "insn32") == 0)
16197 mips_opts
.insn32
= TRUE
;
16198 else if (strcmp (name
, "noinsn32") == 0)
16199 mips_opts
.insn32
= FALSE
;
16200 else if (strcmp (name
, "sym32") == 0)
16201 mips_opts
.sym32
= TRUE
;
16202 else if (strcmp (name
, "nosym32") == 0)
16203 mips_opts
.sym32
= FALSE
;
16205 return OPTION_TYPE_BAD
;
16207 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16210 /* Handle the .set pseudo-op. */
16213 s_mipsset (int x ATTRIBUTE_UNUSED
)
16215 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16216 char *name
= input_line_pointer
, ch
;
16218 file_mips_check_options ();
16220 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16221 ++input_line_pointer
;
16222 ch
= *input_line_pointer
;
16223 *input_line_pointer
= '\0';
16225 if (strchr (name
, ','))
16227 /* Generic ".set" directive; use the generic handler. */
16228 *input_line_pointer
= ch
;
16229 input_line_pointer
= name
;
16234 if (strcmp (name
, "reorder") == 0)
16236 if (mips_opts
.noreorder
)
16239 else if (strcmp (name
, "noreorder") == 0)
16241 if (!mips_opts
.noreorder
)
16242 start_noreorder ();
16244 else if (strcmp (name
, "macro") == 0)
16245 mips_opts
.warn_about_macros
= 0;
16246 else if (strcmp (name
, "nomacro") == 0)
16248 if (mips_opts
.noreorder
== 0)
16249 as_bad (_("`noreorder' must be set before `nomacro'"));
16250 mips_opts
.warn_about_macros
= 1;
16252 else if (strcmp (name
, "gp=default") == 0)
16253 mips_opts
.gp
= file_mips_opts
.gp
;
16254 else if (strcmp (name
, "fp=default") == 0)
16255 mips_opts
.fp
= file_mips_opts
.fp
;
16256 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16258 mips_opts
.isa
= file_mips_opts
.isa
;
16259 mips_opts
.arch
= file_mips_opts
.arch
;
16260 mips_opts
.gp
= file_mips_opts
.gp
;
16261 mips_opts
.fp
= file_mips_opts
.fp
;
16263 else if (strcmp (name
, "push") == 0)
16265 struct mips_option_stack
*s
;
16267 s
= XNEW (struct mips_option_stack
);
16268 s
->next
= mips_opts_stack
;
16269 s
->options
= mips_opts
;
16270 mips_opts_stack
= s
;
16272 else if (strcmp (name
, "pop") == 0)
16274 struct mips_option_stack
*s
;
16276 s
= mips_opts_stack
;
16278 as_bad (_(".set pop with no .set push"));
16281 /* If we're changing the reorder mode we need to handle
16282 delay slots correctly. */
16283 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16284 start_noreorder ();
16285 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16288 mips_opts
= s
->options
;
16289 mips_opts_stack
= s
->next
;
16295 type
= parse_code_option (name
);
16296 if (type
== OPTION_TYPE_BAD
)
16297 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16300 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16301 registers based on what is supported by the arch/cpu. */
16302 if (type
== OPTION_TYPE_ISA
)
16304 switch (mips_opts
.isa
)
16309 /* MIPS I cannot support FPXX. */
16311 /* fall-through. */
16318 if (mips_opts
.fp
!= 0)
16334 if (mips_opts
.fp
!= 0)
16336 if (mips_opts
.arch
== CPU_R5900
)
16343 as_bad (_("unknown ISA level %s"), name
+ 4);
16348 mips_check_options (&mips_opts
, FALSE
);
16350 mips_check_isa_supports_ases ();
16351 *input_line_pointer
= ch
;
16352 demand_empty_rest_of_line ();
16355 /* Handle the .module pseudo-op. */
16358 s_module (int ignore ATTRIBUTE_UNUSED
)
16360 char *name
= input_line_pointer
, ch
;
16362 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16363 ++input_line_pointer
;
16364 ch
= *input_line_pointer
;
16365 *input_line_pointer
= '\0';
16367 if (!file_mips_opts_checked
)
16369 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16370 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16372 /* Update module level settings from mips_opts. */
16373 file_mips_opts
= mips_opts
;
16376 as_bad (_(".module is not permitted after generating code"));
16378 *input_line_pointer
= ch
;
16379 demand_empty_rest_of_line ();
16382 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16383 .option pic2. It means to generate SVR4 PIC calls. */
16386 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16388 mips_pic
= SVR4_PIC
;
16389 mips_abicalls
= TRUE
;
16391 if (g_switch_seen
&& g_switch_value
!= 0)
16392 as_warn (_("-G may not be used with SVR4 PIC code"));
16393 g_switch_value
= 0;
16395 bfd_set_gp_size (stdoutput
, 0);
16396 demand_empty_rest_of_line ();
16399 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16400 PIC code. It sets the $gp register for the function based on the
16401 function address, which is in the register named in the argument.
16402 This uses a relocation against _gp_disp, which is handled specially
16403 by the linker. The result is:
16404 lui $gp,%hi(_gp_disp)
16405 addiu $gp,$gp,%lo(_gp_disp)
16406 addu $gp,$gp,.cpload argument
16407 The .cpload argument is normally $25 == $t9.
16409 The -mno-shared option changes this to:
16410 lui $gp,%hi(__gnu_local_gp)
16411 addiu $gp,$gp,%lo(__gnu_local_gp)
16412 and the argument is ignored. This saves an instruction, but the
16413 resulting code is not position independent; it uses an absolute
16414 address for __gnu_local_gp. Thus code assembled with -mno-shared
16415 can go into an ordinary executable, but not into a shared library. */
16418 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16424 file_mips_check_options ();
16426 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16427 .cpload is ignored. */
16428 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16434 if (mips_opts
.mips16
)
16436 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16437 ignore_rest_of_line ();
16441 /* .cpload should be in a .set noreorder section. */
16442 if (mips_opts
.noreorder
== 0)
16443 as_warn (_(".cpload not in noreorder section"));
16445 reg
= tc_get_register (0);
16447 /* If we need to produce a 64-bit address, we are better off using
16448 the default instruction sequence. */
16449 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16451 ex
.X_op
= O_symbol
;
16452 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16454 ex
.X_op_symbol
= NULL
;
16455 ex
.X_add_number
= 0;
16457 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16458 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16460 mips_mark_labels ();
16461 mips_assembling_insn
= TRUE
;
16464 macro_build_lui (&ex
, mips_gp_register
);
16465 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16466 mips_gp_register
, BFD_RELOC_LO16
);
16468 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16469 mips_gp_register
, reg
);
16472 mips_assembling_insn
= FALSE
;
16473 demand_empty_rest_of_line ();
16476 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16477 .cpsetup $reg1, offset|$reg2, label
16479 If offset is given, this results in:
16480 sd $gp, offset($sp)
16481 lui $gp, %hi(%neg(%gp_rel(label)))
16482 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16483 daddu $gp, $gp, $reg1
16485 If $reg2 is given, this results in:
16487 lui $gp, %hi(%neg(%gp_rel(label)))
16488 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16489 daddu $gp, $gp, $reg1
16490 $reg1 is normally $25 == $t9.
16492 The -mno-shared option replaces the last three instructions with
16494 addiu $gp,$gp,%lo(_gp) */
16497 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16499 expressionS ex_off
;
16500 expressionS ex_sym
;
16503 file_mips_check_options ();
16505 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16506 We also need NewABI support. */
16507 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16513 if (mips_opts
.mips16
)
16515 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16516 ignore_rest_of_line ();
16520 reg1
= tc_get_register (0);
16521 SKIP_WHITESPACE ();
16522 if (*input_line_pointer
!= ',')
16524 as_bad (_("missing argument separator ',' for .cpsetup"));
16528 ++input_line_pointer
;
16529 SKIP_WHITESPACE ();
16530 if (*input_line_pointer
== '$')
16532 mips_cpreturn_register
= tc_get_register (0);
16533 mips_cpreturn_offset
= -1;
16537 mips_cpreturn_offset
= get_absolute_expression ();
16538 mips_cpreturn_register
= -1;
16540 SKIP_WHITESPACE ();
16541 if (*input_line_pointer
!= ',')
16543 as_bad (_("missing argument separator ',' for .cpsetup"));
16547 ++input_line_pointer
;
16548 SKIP_WHITESPACE ();
16549 expression (&ex_sym
);
16551 mips_mark_labels ();
16552 mips_assembling_insn
= TRUE
;
16555 if (mips_cpreturn_register
== -1)
16557 ex_off
.X_op
= O_constant
;
16558 ex_off
.X_add_symbol
= NULL
;
16559 ex_off
.X_op_symbol
= NULL
;
16560 ex_off
.X_add_number
= mips_cpreturn_offset
;
16562 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16563 BFD_RELOC_LO16
, SP
);
16566 move_register (mips_cpreturn_register
, mips_gp_register
);
16568 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16570 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16571 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16574 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16575 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16576 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16578 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16579 mips_gp_register
, reg1
);
16585 ex
.X_op
= O_symbol
;
16586 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16587 ex
.X_op_symbol
= NULL
;
16588 ex
.X_add_number
= 0;
16590 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16591 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16593 macro_build_lui (&ex
, mips_gp_register
);
16594 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16595 mips_gp_register
, BFD_RELOC_LO16
);
16600 mips_assembling_insn
= FALSE
;
16601 demand_empty_rest_of_line ();
16605 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16607 file_mips_check_options ();
16609 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16610 .cplocal is ignored. */
16611 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16617 if (mips_opts
.mips16
)
16619 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16620 ignore_rest_of_line ();
16624 mips_gp_register
= tc_get_register (0);
16625 demand_empty_rest_of_line ();
16628 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16629 offset from $sp. The offset is remembered, and after making a PIC
16630 call $gp is restored from that location. */
16633 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16637 file_mips_check_options ();
16639 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16640 .cprestore is ignored. */
16641 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16647 if (mips_opts
.mips16
)
16649 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16650 ignore_rest_of_line ();
16654 mips_cprestore_offset
= get_absolute_expression ();
16655 mips_cprestore_valid
= 1;
16657 ex
.X_op
= O_constant
;
16658 ex
.X_add_symbol
= NULL
;
16659 ex
.X_op_symbol
= NULL
;
16660 ex
.X_add_number
= mips_cprestore_offset
;
16662 mips_mark_labels ();
16663 mips_assembling_insn
= TRUE
;
16666 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16667 SP
, HAVE_64BIT_ADDRESSES
);
16670 mips_assembling_insn
= FALSE
;
16671 demand_empty_rest_of_line ();
16674 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16675 was given in the preceding .cpsetup, it results in:
16676 ld $gp, offset($sp)
16678 If a register $reg2 was given there, it results in:
16679 or $gp, $reg2, $0 */
16682 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16686 file_mips_check_options ();
16688 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16689 We also need NewABI support. */
16690 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16696 if (mips_opts
.mips16
)
16698 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16699 ignore_rest_of_line ();
16703 mips_mark_labels ();
16704 mips_assembling_insn
= TRUE
;
16707 if (mips_cpreturn_register
== -1)
16709 ex
.X_op
= O_constant
;
16710 ex
.X_add_symbol
= NULL
;
16711 ex
.X_op_symbol
= NULL
;
16712 ex
.X_add_number
= mips_cpreturn_offset
;
16714 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16717 move_register (mips_gp_register
, mips_cpreturn_register
);
16721 mips_assembling_insn
= FALSE
;
16722 demand_empty_rest_of_line ();
16725 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16726 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16727 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16728 debug information or MIPS16 TLS. */
16731 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16732 bfd_reloc_code_real_type rtype
)
16739 if (ex
.X_op
!= O_symbol
)
16741 as_bad (_("unsupported use of %s"), dirstr
);
16742 ignore_rest_of_line ();
16745 p
= frag_more (bytes
);
16746 md_number_to_chars (p
, 0, bytes
);
16747 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16748 demand_empty_rest_of_line ();
16749 mips_clear_insn_labels ();
16752 /* Handle .dtprelword. */
16755 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16757 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16760 /* Handle .dtpreldword. */
16763 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16765 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16768 /* Handle .tprelword. */
16771 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16773 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16776 /* Handle .tpreldword. */
16779 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16781 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16784 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16785 code. It sets the offset to use in gp_rel relocations. */
16788 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16790 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16791 We also need NewABI support. */
16792 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16798 mips_gprel_offset
= get_absolute_expression ();
16800 demand_empty_rest_of_line ();
16803 /* Handle the .gpword pseudo-op. This is used when generating PIC
16804 code. It generates a 32 bit GP relative reloc. */
16807 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16809 segment_info_type
*si
;
16810 struct insn_label_list
*l
;
16814 /* When not generating PIC code, this is treated as .word. */
16815 if (mips_pic
!= SVR4_PIC
)
16821 si
= seg_info (now_seg
);
16822 l
= si
->label_list
;
16823 mips_emit_delays ();
16825 mips_align (2, 0, l
);
16828 mips_clear_insn_labels ();
16830 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16832 as_bad (_("unsupported use of .gpword"));
16833 ignore_rest_of_line ();
16837 md_number_to_chars (p
, 0, 4);
16838 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16839 BFD_RELOC_GPREL32
);
16841 demand_empty_rest_of_line ();
16845 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16847 segment_info_type
*si
;
16848 struct insn_label_list
*l
;
16852 /* When not generating PIC code, this is treated as .dword. */
16853 if (mips_pic
!= SVR4_PIC
)
16859 si
= seg_info (now_seg
);
16860 l
= si
->label_list
;
16861 mips_emit_delays ();
16863 mips_align (3, 0, l
);
16866 mips_clear_insn_labels ();
16868 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16870 as_bad (_("unsupported use of .gpdword"));
16871 ignore_rest_of_line ();
16875 md_number_to_chars (p
, 0, 8);
16876 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16877 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16879 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16880 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16881 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16883 demand_empty_rest_of_line ();
16886 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16887 tables. It generates a R_MIPS_EH reloc. */
16890 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16895 mips_emit_delays ();
16898 mips_clear_insn_labels ();
16900 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16902 as_bad (_("unsupported use of .ehword"));
16903 ignore_rest_of_line ();
16907 md_number_to_chars (p
, 0, 4);
16908 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16909 BFD_RELOC_32_PCREL
);
16911 demand_empty_rest_of_line ();
16914 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16915 tables in SVR4 PIC code. */
16918 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16922 file_mips_check_options ();
16924 /* This is ignored when not generating SVR4 PIC code. */
16925 if (mips_pic
!= SVR4_PIC
)
16931 mips_mark_labels ();
16932 mips_assembling_insn
= TRUE
;
16934 /* Add $gp to the register named as an argument. */
16936 reg
= tc_get_register (0);
16937 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16940 mips_assembling_insn
= FALSE
;
16941 demand_empty_rest_of_line ();
16944 /* Handle the .insn pseudo-op. This marks instruction labels in
16945 mips16/micromips mode. This permits the linker to handle them specially,
16946 such as generating jalx instructions when needed. We also make
16947 them odd for the duration of the assembly, in order to generate the
16948 right sort of code. We will make them even in the adjust_symtab
16949 routine, while leaving them marked. This is convenient for the
16950 debugger and the disassembler. The linker knows to make them odd
16954 s_insn (int ignore ATTRIBUTE_UNUSED
)
16956 file_mips_check_options ();
16957 file_ase_mips16
|= mips_opts
.mips16
;
16958 file_ase_micromips
|= mips_opts
.micromips
;
16960 mips_mark_labels ();
16962 demand_empty_rest_of_line ();
16965 /* Handle the .nan pseudo-op. */
16968 s_nan (int ignore ATTRIBUTE_UNUSED
)
16970 static const char str_legacy
[] = "legacy";
16971 static const char str_2008
[] = "2008";
16974 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16976 if (i
== sizeof (str_2008
) - 1
16977 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16979 else if (i
== sizeof (str_legacy
) - 1
16980 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16982 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
16985 as_bad (_("`%s' does not support legacy NaN"),
16986 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
16989 as_bad (_("bad .nan directive"));
16991 input_line_pointer
+= i
;
16992 demand_empty_rest_of_line ();
16995 /* Handle a .stab[snd] directive. Ideally these directives would be
16996 implemented in a transparent way, so that removing them would not
16997 have any effect on the generated instructions. However, s_stab
16998 internally changes the section, so in practice we need to decide
16999 now whether the preceding label marks compressed code. We do not
17000 support changing the compression mode of a label after a .stab*
17001 directive, such as in:
17007 so the current mode wins. */
17010 s_mips_stab (int type
)
17012 mips_mark_labels ();
17016 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17019 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17026 c
= get_symbol_name (&name
);
17027 symbolP
= symbol_find_or_make (name
);
17028 S_SET_WEAK (symbolP
);
17029 *input_line_pointer
= c
;
17031 SKIP_WHITESPACE_AFTER_NAME ();
17033 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17035 if (S_IS_DEFINED (symbolP
))
17037 as_bad (_("ignoring attempt to redefine symbol %s"),
17038 S_GET_NAME (symbolP
));
17039 ignore_rest_of_line ();
17043 if (*input_line_pointer
== ',')
17045 ++input_line_pointer
;
17046 SKIP_WHITESPACE ();
17050 if (exp
.X_op
!= O_symbol
)
17052 as_bad (_("bad .weakext directive"));
17053 ignore_rest_of_line ();
17056 symbol_set_value_expression (symbolP
, &exp
);
17059 demand_empty_rest_of_line ();
17062 /* Parse a register string into a number. Called from the ECOFF code
17063 to parse .frame. The argument is non-zero if this is the frame
17064 register, so that we can record it in mips_frame_reg. */
17067 tc_get_register (int frame
)
17071 SKIP_WHITESPACE ();
17072 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17076 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17077 mips_frame_reg_valid
= 1;
17078 mips_cprestore_valid
= 0;
17084 md_section_align (asection
*seg
, valueT addr
)
17086 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17088 /* We don't need to align ELF sections to the full alignment.
17089 However, Irix 5 may prefer that we align them at least to a 16
17090 byte boundary. We don't bother to align the sections if we
17091 are targeted for an embedded system. */
17092 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17097 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17100 /* Utility routine, called from above as well. If called while the
17101 input file is still being read, it's only an approximation. (For
17102 example, a symbol may later become defined which appeared to be
17103 undefined earlier.) */
17106 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17111 if (g_switch_value
> 0)
17113 const char *symname
;
17116 /* Find out whether this symbol can be referenced off the $gp
17117 register. It can be if it is smaller than the -G size or if
17118 it is in the .sdata or .sbss section. Certain symbols can
17119 not be referenced off the $gp, although it appears as though
17121 symname
= S_GET_NAME (sym
);
17122 if (symname
!= (const char *) NULL
17123 && (strcmp (symname
, "eprol") == 0
17124 || strcmp (symname
, "etext") == 0
17125 || strcmp (symname
, "_gp") == 0
17126 || strcmp (symname
, "edata") == 0
17127 || strcmp (symname
, "_fbss") == 0
17128 || strcmp (symname
, "_fdata") == 0
17129 || strcmp (symname
, "_ftext") == 0
17130 || strcmp (symname
, "end") == 0
17131 || strcmp (symname
, "_gp_disp") == 0))
17133 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17135 #ifndef NO_ECOFF_DEBUGGING
17136 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17137 && (symbol_get_obj (sym
)->ecoff_extern_size
17138 <= g_switch_value
))
17140 /* We must defer this decision until after the whole
17141 file has been read, since there might be a .extern
17142 after the first use of this symbol. */
17143 || (before_relaxing
17144 #ifndef NO_ECOFF_DEBUGGING
17145 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17147 && S_GET_VALUE (sym
) == 0)
17148 || (S_GET_VALUE (sym
) != 0
17149 && S_GET_VALUE (sym
) <= g_switch_value
)))
17153 const char *segname
;
17155 segname
= segment_name (S_GET_SEGMENT (sym
));
17156 gas_assert (strcmp (segname
, ".lit8") != 0
17157 && strcmp (segname
, ".lit4") != 0);
17158 change
= (strcmp (segname
, ".sdata") != 0
17159 && strcmp (segname
, ".sbss") != 0
17160 && strncmp (segname
, ".sdata.", 7) != 0
17161 && strncmp (segname
, ".sbss.", 6) != 0
17162 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17163 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17168 /* We are not optimizing for the $gp register. */
17173 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17176 pic_need_relax (symbolS
*sym
)
17180 /* Handle the case of a symbol equated to another symbol. */
17181 while (symbol_equated_reloc_p (sym
))
17185 /* It's possible to get a loop here in a badly written program. */
17186 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17192 if (symbol_section_p (sym
))
17195 symsec
= S_GET_SEGMENT (sym
);
17197 /* This must duplicate the test in adjust_reloc_syms. */
17198 return (!bfd_is_und_section (symsec
)
17199 && !bfd_is_abs_section (symsec
)
17200 && !bfd_is_com_section (symsec
)
17201 /* A global or weak symbol is treated as external. */
17202 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17205 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17206 convert a section-relative value VAL to the equivalent PC-relative
17210 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17211 offsetT val
, long stretch
)
17216 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17218 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17220 /* If the relax_marker of the symbol fragment differs from the
17221 relax_marker of this fragment, we have not yet adjusted the
17222 symbol fragment fr_address. We want to add in STRETCH in
17223 order to get a better estimate of the address. This
17224 particularly matters because of the shift bits. */
17225 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17229 /* Adjust stretch for any alignment frag. Note that if have
17230 been expanding the earlier code, the symbol may be
17231 defined in what appears to be an earlier frag. FIXME:
17232 This doesn't handle the fr_subtype field, which specifies
17233 a maximum number of bytes to skip when doing an
17235 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17237 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17240 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17242 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17251 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17253 /* The base address rules are complicated. The base address of
17254 a branch is the following instruction. The base address of a
17255 PC relative load or add is the instruction itself, but if it
17256 is in a delay slot (in which case it can not be extended) use
17257 the address of the instruction whose delay slot it is in. */
17258 if (pcrel_op
->include_isa_bit
)
17262 /* If we are currently assuming that this frag should be
17263 extended, then the current address is two bytes higher. */
17264 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17267 /* Ignore the low bit in the target, since it will be set
17268 for a text label. */
17271 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17273 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17276 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17281 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17282 extended opcode. SEC is the section the frag is in. */
17285 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17287 const struct mips_int_operand
*operand
;
17292 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17294 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17297 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17298 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17299 operand
= mips16_immed_operand (type
, FALSE
);
17300 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17301 || (operand
->root
.type
== OP_PCREL
17303 : !bfd_is_abs_section (symsec
)))
17306 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17308 if (operand
->root
.type
== OP_PCREL
)
17310 const struct mips_pcrel_operand
*pcrel_op
;
17313 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17316 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17317 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17319 /* If any of the shifted bits are set, we must use an extended
17320 opcode. If the address depends on the size of this
17321 instruction, this can lead to a loop, so we arrange to always
17322 use an extended opcode. */
17323 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17325 fragp
->fr_subtype
=
17326 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17330 /* If we are about to mark a frag as extended because the value
17331 is precisely the next value above maxtiny, then there is a
17332 chance of an infinite loop as in the following code:
17337 In this case when the la is extended, foo is 0x3fc bytes
17338 away, so the la can be shrunk, but then foo is 0x400 away, so
17339 the la must be extended. To avoid this loop, we mark the
17340 frag as extended if it was small, and is about to become
17341 extended with the next value above maxtiny. */
17342 maxtiny
= mips_int_operand_max (operand
);
17343 if (val
== maxtiny
+ (1 << operand
->shift
)
17344 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17346 fragp
->fr_subtype
=
17347 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17352 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17355 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17356 macro expansion. SEC is the section the frag is in. We only
17357 support PC-relative instructions (LA, DLA, LW, LD) here, in
17358 non-PIC code using 32-bit addressing. */
17361 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17363 const struct mips_pcrel_operand
*pcrel_op
;
17364 const struct mips_int_operand
*operand
;
17369 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17371 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17373 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17376 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17382 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17383 if (bfd_is_abs_section (symsec
))
17385 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17387 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17390 operand
= mips16_immed_operand (type
, TRUE
);
17391 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17392 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17393 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17395 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17402 /* Compute the length of a branch sequence, and adjust the
17403 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17404 worst-case length is computed, with UPDATE being used to indicate
17405 whether an unconditional (-1), branch-likely (+1) or regular (0)
17406 branch is to be computed. */
17408 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17410 bfd_boolean toofar
;
17414 && S_IS_DEFINED (fragp
->fr_symbol
)
17415 && !S_IS_WEAK (fragp
->fr_symbol
)
17416 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17421 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17423 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17427 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17430 /* If the symbol is not defined or it's in a different segment,
17431 we emit the long sequence. */
17434 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17436 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17437 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17438 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17439 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17440 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17446 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17449 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17451 /* Additional space for PIC loading of target address. */
17453 if (mips_opts
.isa
== ISA_MIPS1
)
17454 /* Additional space for $at-stabilizing nop. */
17458 /* If branch is conditional. */
17459 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17466 /* Get a FRAG's branch instruction delay slot size, either from the
17467 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17468 or SHORT_INSN_SIZE otherwise. */
17471 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17473 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17476 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17478 return short_insn_size
;
17481 /* Compute the length of a branch sequence, and adjust the
17482 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17483 worst-case length is computed, with UPDATE being used to indicate
17484 whether an unconditional (-1), or regular (0) branch is to be
17488 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17490 bfd_boolean insn32
= TRUE
;
17491 bfd_boolean nods
= TRUE
;
17492 bfd_boolean pic
= TRUE
;
17493 bfd_boolean al
= TRUE
;
17494 int short_insn_size
;
17495 bfd_boolean toofar
;
17500 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17501 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17502 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17503 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17505 short_insn_size
= insn32
? 4 : 2;
17508 && S_IS_DEFINED (fragp
->fr_symbol
)
17509 && !S_IS_WEAK (fragp
->fr_symbol
)
17510 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17515 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17516 /* Ignore the low bit in the target, since it will be set
17517 for a text label. */
17518 if ((val
& 1) != 0)
17521 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17525 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17528 /* If the symbol is not defined or it's in a different segment,
17529 we emit the long sequence. */
17532 if (fragp
&& update
17533 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17534 fragp
->fr_subtype
= (toofar
17535 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17536 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17541 bfd_boolean compact_known
= fragp
!= NULL
;
17542 bfd_boolean compact
= FALSE
;
17543 bfd_boolean uncond
;
17547 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17548 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17551 uncond
= update
< 0;
17553 /* If label is out of range, we turn branch <br>:
17555 <br> label # 4 bytes
17562 # compact && (!PIC || insn32)
17565 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17566 length
+= short_insn_size
;
17568 /* If assembling PIC code, we further turn:
17574 lw/ld at, %got(label)(gp) # 4 bytes
17575 d/addiu at, %lo(label) # 4 bytes
17576 jr/c at # 2/4 bytes
17579 length
+= 4 + short_insn_size
;
17581 /* Add an extra nop if the jump has no compact form and we need
17582 to fill the delay slot. */
17583 if ((!pic
|| al
) && nods
)
17585 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17586 : short_insn_size
);
17588 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17590 <brneg> 0f # 4 bytes
17591 nop # 2/4 bytes if !compact
17594 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17598 /* Add an extra nop to fill the delay slot. */
17599 gas_assert (fragp
);
17600 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17606 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17607 bit accordingly. */
17610 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17612 bfd_boolean toofar
;
17615 && S_IS_DEFINED (fragp
->fr_symbol
)
17616 && !S_IS_WEAK (fragp
->fr_symbol
)
17617 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17623 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17624 /* Ignore the low bit in the target, since it will be set
17625 for a text label. */
17626 if ((val
& 1) != 0)
17629 /* Assume this is a 2-byte branch. */
17630 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17632 /* We try to avoid the infinite loop by not adding 2 more bytes for
17637 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17639 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17640 else if (type
== 'E')
17641 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17646 /* If the symbol is not defined or it's in a different segment,
17647 we emit a normal 32-bit branch. */
17650 if (fragp
&& update
17651 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17653 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17654 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17662 /* Estimate the size of a frag before relaxing. Unless this is the
17663 mips16, we are not really relaxing here, and the final size is
17664 encoded in the subtype information. For the mips16, we have to
17665 decide whether we are using an extended opcode or not. */
17668 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17672 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17675 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17677 return fragp
->fr_var
;
17680 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17682 /* We don't want to modify the EXTENDED bit here; it might get us
17683 into infinite loops. We change it only in mips_relax_frag(). */
17684 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17687 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17690 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17694 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17695 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17696 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17697 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17698 fragp
->fr_var
= length
;
17703 if (mips_pic
== VXWORKS_PIC
)
17704 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17706 else if (RELAX_PIC (fragp
->fr_subtype
))
17707 change
= pic_need_relax (fragp
->fr_symbol
);
17709 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17713 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17714 return -RELAX_FIRST (fragp
->fr_subtype
);
17717 return -RELAX_SECOND (fragp
->fr_subtype
);
17720 /* This is called to see whether a reloc against a defined symbol
17721 should be converted into a reloc against a section. */
17724 mips_fix_adjustable (fixS
*fixp
)
17726 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17727 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17730 if (fixp
->fx_addsy
== NULL
)
17733 /* Allow relocs used for EH tables. */
17734 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17737 /* If symbol SYM is in a mergeable section, relocations of the form
17738 SYM + 0 can usually be made section-relative. The mergeable data
17739 is then identified by the section offset rather than by the symbol.
17741 However, if we're generating REL LO16 relocations, the offset is split
17742 between the LO16 and partnering high part relocation. The linker will
17743 need to recalculate the complete offset in order to correctly identify
17746 The linker has traditionally not looked for the partnering high part
17747 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17748 placed anywhere. Rather than break backwards compatibility by changing
17749 this, it seems better not to force the issue, and instead keep the
17750 original symbol. This will work with either linker behavior. */
17751 if ((lo16_reloc_p (fixp
->fx_r_type
)
17752 || reloc_needs_lo_p (fixp
->fx_r_type
))
17753 && HAVE_IN_PLACE_ADDENDS
17754 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17757 /* There is no place to store an in-place offset for JALR relocations. */
17758 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17761 /* Likewise an in-range offset of limited PC-relative relocations may
17762 overflow the in-place relocatable field if recalculated against the
17763 start address of the symbol's containing section.
17765 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17766 section relative to allow linker relaxations to be performed later on. */
17767 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17768 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17771 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17772 to a floating-point stub. The same is true for non-R_MIPS16_26
17773 relocations against MIPS16 functions; in this case, the stub becomes
17774 the function's canonical address.
17776 Floating-point stubs are stored in unique .mips16.call.* or
17777 .mips16.fn.* sections. If a stub T for function F is in section S,
17778 the first relocation in section S must be against F; this is how the
17779 linker determines the target function. All relocations that might
17780 resolve to T must also be against F. We therefore have the following
17781 restrictions, which are given in an intentionally-redundant way:
17783 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17786 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17787 if that stub might be used.
17789 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17792 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17793 that stub might be used.
17795 There is a further restriction:
17797 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17798 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17799 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17800 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17801 against MIPS16 or microMIPS symbols because we need to keep the
17802 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17803 detection and JAL or BAL to JALX instruction conversion in the
17806 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17807 against a MIPS16 symbol. We deal with (5) by additionally leaving
17808 alone any jump and branch relocations against a microMIPS symbol.
17810 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17811 relocation against some symbol R, no relocation against R may be
17812 reduced. (Note that this deals with (2) as well as (1) because
17813 relocations against global symbols will never be reduced on ELF
17814 targets.) This approach is a little simpler than trying to detect
17815 stub sections, and gives the "all or nothing" per-symbol consistency
17816 that we have for MIPS16 symbols. */
17817 if (fixp
->fx_subsy
== NULL
17818 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17819 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17820 && (jmp_reloc_p (fixp
->fx_r_type
)
17821 || b_reloc_p (fixp
->fx_r_type
)))
17822 || *symbol_get_tc (fixp
->fx_addsy
)))
17828 /* Translate internal representation of relocation info to BFD target
17832 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17834 static arelent
*retval
[4];
17836 bfd_reloc_code_real_type code
;
17838 memset (retval
, 0, sizeof(retval
));
17839 reloc
= retval
[0] = XCNEW (arelent
);
17840 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
17841 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17842 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17844 if (fixp
->fx_pcrel
)
17846 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17847 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
17848 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17849 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17850 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17851 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17852 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17853 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17854 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17855 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17856 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17857 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17859 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17860 Relocations want only the symbol offset. */
17861 switch (fixp
->fx_r_type
)
17863 case BFD_RELOC_MIPS_18_PCREL_S3
:
17864 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
17867 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17871 else if (HAVE_IN_PLACE_ADDENDS
17872 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
17873 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
17874 + fixp
->fx_where
, 4) >> 26) == 0x3c)
17876 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17877 addend accordingly. */
17878 reloc
->addend
= fixp
->fx_addnumber
>> 1;
17881 reloc
->addend
= fixp
->fx_addnumber
;
17883 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17884 entry to be used in the relocation's section offset. */
17885 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17887 reloc
->address
= reloc
->addend
;
17891 code
= fixp
->fx_r_type
;
17893 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17894 if (reloc
->howto
== NULL
)
17896 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17897 _("cannot represent %s relocation in this object file"
17899 bfd_get_reloc_code_name (code
));
17906 /* Relax a machine dependent frag. This returns the amount by which
17907 the current size of the frag should change. */
17910 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17912 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17914 offsetT old_var
= fragp
->fr_var
;
17916 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17918 return fragp
->fr_var
- old_var
;
17921 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17923 offsetT old_var
= fragp
->fr_var
;
17924 offsetT new_var
= 4;
17926 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17927 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17928 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17929 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17930 fragp
->fr_var
= new_var
;
17932 return new_var
- old_var
;
17935 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17938 if (!mips16_extended_frag (fragp
, sec
, stretch
))
17940 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17942 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
17945 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17947 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17953 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
17955 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17957 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
17958 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17961 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17963 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17971 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17973 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17975 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17976 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
17981 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
17989 /* Convert a machine dependent frag. */
17992 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17994 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17997 unsigned long insn
;
18001 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18002 insn
= read_insn (buf
);
18004 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18006 /* We generate a fixup instead of applying it right now
18007 because, if there are linker relaxations, we're going to
18008 need the relocations. */
18009 exp
.X_op
= O_symbol
;
18010 exp
.X_add_symbol
= fragp
->fr_symbol
;
18011 exp
.X_add_number
= fragp
->fr_offset
;
18013 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18014 BFD_RELOC_16_PCREL_S2
);
18015 fixp
->fx_file
= fragp
->fr_file
;
18016 fixp
->fx_line
= fragp
->fr_line
;
18018 buf
= write_insn (buf
, insn
);
18024 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18025 _("relaxed out-of-range branch into a jump"));
18027 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18030 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18032 /* Reverse the branch. */
18033 switch ((insn
>> 28) & 0xf)
18036 if ((insn
& 0xff000000) == 0x47000000
18037 || (insn
& 0xff600000) == 0x45600000)
18039 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18040 reversed by tweaking bit 23. */
18041 insn
^= 0x00800000;
18045 /* bc[0-3][tf]l? instructions can have the condition
18046 reversed by tweaking a single TF bit, and their
18047 opcodes all have 0x4???????. */
18048 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18049 insn
^= 0x00010000;
18054 /* bltz 0x04000000 bgez 0x04010000
18055 bltzal 0x04100000 bgezal 0x04110000 */
18056 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18057 insn
^= 0x00010000;
18061 /* beq 0x10000000 bne 0x14000000
18062 blez 0x18000000 bgtz 0x1c000000 */
18063 insn
^= 0x04000000;
18071 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18073 /* Clear the and-link bit. */
18074 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18076 /* bltzal 0x04100000 bgezal 0x04110000
18077 bltzall 0x04120000 bgezall 0x04130000 */
18078 insn
&= ~0x00100000;
18081 /* Branch over the branch (if the branch was likely) or the
18082 full jump (not likely case). Compute the offset from the
18083 current instruction to branch to. */
18084 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18088 /* How many bytes in instructions we've already emitted? */
18089 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18090 /* How many bytes in instructions from here to the end? */
18091 i
= fragp
->fr_var
- i
;
18093 /* Convert to instruction count. */
18095 /* Branch counts from the next instruction. */
18098 /* Branch over the jump. */
18099 buf
= write_insn (buf
, insn
);
18102 buf
= write_insn (buf
, 0);
18104 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18106 /* beql $0, $0, 2f */
18108 /* Compute the PC offset from the current instruction to
18109 the end of the variable frag. */
18110 /* How many bytes in instructions we've already emitted? */
18111 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18112 /* How many bytes in instructions from here to the end? */
18113 i
= fragp
->fr_var
- i
;
18114 /* Convert to instruction count. */
18116 /* Don't decrement i, because we want to branch over the
18120 buf
= write_insn (buf
, insn
);
18121 buf
= write_insn (buf
, 0);
18125 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18128 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18129 ? 0x0c000000 : 0x08000000);
18130 exp
.X_op
= O_symbol
;
18131 exp
.X_add_symbol
= fragp
->fr_symbol
;
18132 exp
.X_add_number
= fragp
->fr_offset
;
18134 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18135 FALSE
, BFD_RELOC_MIPS_JMP
);
18136 fixp
->fx_file
= fragp
->fr_file
;
18137 fixp
->fx_line
= fragp
->fr_line
;
18139 buf
= write_insn (buf
, insn
);
18143 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18145 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18146 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18147 insn
|= at
<< OP_SH_RT
;
18148 exp
.X_op
= O_symbol
;
18149 exp
.X_add_symbol
= fragp
->fr_symbol
;
18150 exp
.X_add_number
= fragp
->fr_offset
;
18152 if (fragp
->fr_offset
)
18154 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18155 exp
.X_add_number
= 0;
18158 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18159 FALSE
, BFD_RELOC_MIPS_GOT16
);
18160 fixp
->fx_file
= fragp
->fr_file
;
18161 fixp
->fx_line
= fragp
->fr_line
;
18163 buf
= write_insn (buf
, insn
);
18165 if (mips_opts
.isa
== ISA_MIPS1
)
18167 buf
= write_insn (buf
, 0);
18169 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18170 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18171 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18173 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18174 FALSE
, BFD_RELOC_LO16
);
18175 fixp
->fx_file
= fragp
->fr_file
;
18176 fixp
->fx_line
= fragp
->fr_line
;
18178 buf
= write_insn (buf
, insn
);
18181 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18185 insn
|= at
<< OP_SH_RS
;
18187 buf
= write_insn (buf
, insn
);
18191 fragp
->fr_fix
+= fragp
->fr_var
;
18192 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18196 /* Relax microMIPS branches. */
18197 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18199 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18200 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18201 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18202 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18203 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18204 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18205 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18206 bfd_boolean short_ds
;
18207 unsigned long insn
;
18211 exp
.X_op
= O_symbol
;
18212 exp
.X_add_symbol
= fragp
->fr_symbol
;
18213 exp
.X_add_number
= fragp
->fr_offset
;
18215 fragp
->fr_fix
+= fragp
->fr_var
;
18217 /* Handle 16-bit branches that fit or are forced to fit. */
18218 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18220 /* We generate a fixup instead of applying it right now,
18221 because if there is linker relaxation, we're going to
18222 need the relocations. */
18224 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18225 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18226 else if (type
== 'E')
18227 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18228 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18232 fixp
->fx_file
= fragp
->fr_file
;
18233 fixp
->fx_line
= fragp
->fr_line
;
18235 /* These relocations can have an addend that won't fit in
18237 fixp
->fx_no_overflow
= 1;
18242 /* Handle 32-bit branches that fit or are forced to fit. */
18243 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18244 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18246 /* We generate a fixup instead of applying it right now,
18247 because if there is linker relaxation, we're going to
18248 need the relocations. */
18249 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18250 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18251 fixp
->fx_file
= fragp
->fr_file
;
18252 fixp
->fx_line
= fragp
->fr_line
;
18256 insn
= read_compressed_insn (buf
, 4);
18261 /* Check the short-delay-slot bit. */
18262 if (!al
|| (insn
& 0x02000000) != 0)
18263 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18265 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18268 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18273 /* Relax 16-bit branches to 32-bit branches. */
18276 insn
= read_compressed_insn (buf
, 2);
18278 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18279 insn
= 0x94000000; /* beq */
18280 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18282 unsigned long regno
;
18284 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18285 regno
= micromips_to_32_reg_d_map
[regno
];
18286 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18287 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18292 /* Nothing else to do, just write it out. */
18293 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18294 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18296 buf
= write_compressed_insn (buf
, insn
, 4);
18298 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18299 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18304 insn
= read_compressed_insn (buf
, 4);
18306 /* Relax 32-bit branches to a sequence of instructions. */
18307 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18308 _("relaxed out-of-range branch into a jump"));
18310 /* Set the short-delay-slot bit. */
18311 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18313 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18317 /* Reverse the branch. */
18318 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18319 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18320 insn
^= 0x20000000;
18321 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18322 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18323 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18324 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18325 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18326 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18327 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18328 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18329 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18330 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18331 insn
^= 0x00400000;
18332 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18333 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18334 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18335 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18336 insn
^= 0x00200000;
18337 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18339 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18341 insn
^= 0x00800000;
18347 /* Clear the and-link and short-delay-slot bits. */
18348 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18350 /* bltzal 0x40200000 bgezal 0x40600000 */
18351 /* bltzals 0x42200000 bgezals 0x42600000 */
18352 insn
&= ~0x02200000;
18355 /* Make a label at the end for use with the branch. */
18356 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18357 micromips_label_inc ();
18358 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18361 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18362 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18363 fixp
->fx_file
= fragp
->fr_file
;
18364 fixp
->fx_line
= fragp
->fr_line
;
18366 /* Branch over the jump. */
18367 buf
= write_compressed_insn (buf
, insn
, 4);
18373 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18375 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18381 unsigned long jal
= (short_ds
|| nods
18382 ? 0x74000000 : 0xf4000000); /* jal/s */
18384 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18385 insn
= al
? jal
: 0xd4000000;
18387 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18388 BFD_RELOC_MICROMIPS_JMP
);
18389 fixp
->fx_file
= fragp
->fr_file
;
18390 fixp
->fx_line
= fragp
->fr_line
;
18392 buf
= write_compressed_insn (buf
, insn
, 4);
18394 if (compact
|| nods
)
18398 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18400 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18405 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18407 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18408 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18409 insn
|= at
<< MICROMIPSOP_SH_RT
;
18411 if (exp
.X_add_number
)
18413 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18414 exp
.X_add_number
= 0;
18417 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18418 BFD_RELOC_MICROMIPS_GOT16
);
18419 fixp
->fx_file
= fragp
->fr_file
;
18420 fixp
->fx_line
= fragp
->fr_line
;
18422 buf
= write_compressed_insn (buf
, insn
, 4);
18424 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18425 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18426 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18428 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18429 BFD_RELOC_MICROMIPS_LO16
);
18430 fixp
->fx_file
= fragp
->fr_file
;
18431 fixp
->fx_line
= fragp
->fr_line
;
18433 buf
= write_compressed_insn (buf
, insn
, 4);
18438 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18439 insn
|= at
<< MICROMIPSOP_SH_RS
;
18441 buf
= write_compressed_insn (buf
, insn
, 4);
18443 if (compact
|| nods
)
18445 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18449 /* jr/jrc/jalr/jalrs $at */
18450 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18451 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18453 insn
= al
? jalr
: jr
;
18454 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18456 buf
= write_compressed_insn (buf
, insn
, 2);
18461 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18463 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18468 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18472 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18475 const struct mips_int_operand
*operand
;
18478 unsigned int user_length
;
18479 bfd_boolean need_reloc
;
18480 unsigned long insn
;
18485 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18486 operand
= mips16_immed_operand (type
, FALSE
);
18488 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18489 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18490 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18492 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18493 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18494 || (operand
->root
.type
== OP_PCREL
&& !mac
18496 : !bfd_is_abs_section (symsec
)));
18498 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18500 const struct mips_pcrel_operand
*pcrel_op
;
18502 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18504 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18506 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18507 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18508 _("branch to a symbol in another ISA mode"));
18509 else if ((fragp
->fr_offset
& 0x1) != 0)
18510 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18511 _("branch to misaligned address (0x%lx)"),
18515 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18517 /* Make sure the section winds up with the alignment we have
18519 if (operand
->shift
> 0)
18520 record_alignment (asec
, operand
->shift
);
18523 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18524 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18527 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18528 _("macro instruction expanded into multiple "
18529 "instructions in a branch delay slot"));
18531 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18532 _("extended instruction in a branch delay slot"));
18534 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18535 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18536 _("macro instruction expanded into multiple "
18539 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18541 insn
= read_compressed_insn (buf
, 2);
18543 insn
|= MIPS16_EXTEND
;
18545 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18547 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18558 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18559 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18565 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18567 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18568 fragp
->fr_symbol
, fragp
->fr_offset
,
18569 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18570 fixp
->fx_file
= fragp
->fr_file
;
18571 fixp
->fx_line
= fragp
->fr_line
;
18573 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ 8, 4,
18574 fragp
->fr_symbol
, fragp
->fr_offset
,
18575 FALSE
, BFD_RELOC_MIPS16_LO16
);
18576 fixp
->fx_file
= fragp
->fr_file
;
18577 fixp
->fx_line
= fragp
->fr_line
;
18582 switch (insn
& 0xf800)
18584 case 0x0800: /* ADDIU */
18585 reg
= (insn
>> 8) & 0x7;
18586 op
= 0xf0004800 | (reg
<< 8);
18588 case 0xb000: /* LW */
18589 reg
= (insn
>> 8) & 0x7;
18590 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18592 case 0xf800: /* I64 */
18593 reg
= (insn
>> 5) & 0x7;
18594 switch (insn
& 0x0700)
18596 case 0x0400: /* LD */
18597 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18599 case 0x0600: /* DADDIU */
18600 op
= 0xf000fd00 | (reg
<< 5);
18610 new = 0xf0006800 | (reg
<< 8); /* LI */
18611 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18612 buf
= write_compressed_insn (buf
, new, 4);
18613 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18614 buf
= write_compressed_insn (buf
, new, 4);
18615 op
|= mips16_immed_extend (val
, 16);
18616 buf
= write_compressed_insn (buf
, op
, 4);
18618 fragp
->fr_fix
+= 12;
18622 unsigned int length
= ext
? 4 : 2;
18626 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18634 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18639 if (mac
|| reloc
== BFD_RELOC_NONE
)
18640 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18641 _("unsupported relocation"));
18644 exp
.X_op
= O_symbol
;
18645 exp
.X_add_symbol
= fragp
->fr_symbol
;
18646 exp
.X_add_number
= fragp
->fr_offset
;
18648 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18651 fixp
->fx_file
= fragp
->fr_file
;
18652 fixp
->fx_line
= fragp
->fr_line
;
18655 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18656 _("invalid unextended operand value"));
18659 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18660 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18662 gas_assert (mips16_opcode_length (insn
) == length
);
18663 write_compressed_insn (buf
, insn
, length
);
18664 fragp
->fr_fix
+= length
;
18669 relax_substateT subtype
= fragp
->fr_subtype
;
18670 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18671 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18675 first
= RELAX_FIRST (subtype
);
18676 second
= RELAX_SECOND (subtype
);
18677 fixp
= (fixS
*) fragp
->fr_opcode
;
18679 /* If the delay slot chosen does not match the size of the instruction,
18680 then emit a warning. */
18681 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18682 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18687 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18688 | RELAX_DELAY_SLOT_SIZE_FIRST
18689 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18690 msg
= macro_warning (s
);
18692 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18696 /* Possibly emit a warning if we've chosen the longer option. */
18697 if (use_second
== second_longer
)
18703 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18704 msg
= macro_warning (s
);
18706 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18710 /* Go through all the fixups for the first sequence. Disable them
18711 (by marking them as done) if we're going to use the second
18712 sequence instead. */
18714 && fixp
->fx_frag
== fragp
18715 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18717 if (subtype
& RELAX_USE_SECOND
)
18719 fixp
= fixp
->fx_next
;
18722 /* Go through the fixups for the second sequence. Disable them if
18723 we're going to use the first sequence, otherwise adjust their
18724 addresses to account for the relaxation. */
18725 while (fixp
&& fixp
->fx_frag
== fragp
)
18727 if (subtype
& RELAX_USE_SECOND
)
18728 fixp
->fx_where
-= first
;
18731 fixp
= fixp
->fx_next
;
18734 /* Now modify the frag contents. */
18735 if (subtype
& RELAX_USE_SECOND
)
18739 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18740 memmove (start
, start
+ first
, second
);
18741 fragp
->fr_fix
-= first
;
18744 fragp
->fr_fix
-= second
;
18748 /* This function is called after the relocs have been generated.
18749 We've been storing mips16 text labels as odd. Here we convert them
18750 back to even for the convenience of the debugger. */
18753 mips_frob_file_after_relocs (void)
18756 unsigned int count
, i
;
18758 syms
= bfd_get_outsymbols (stdoutput
);
18759 count
= bfd_get_symcount (stdoutput
);
18760 for (i
= 0; i
< count
; i
++, syms
++)
18761 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18762 && ((*syms
)->value
& 1) != 0)
18764 (*syms
)->value
&= ~1;
18765 /* If the symbol has an odd size, it was probably computed
18766 incorrectly, so adjust that as well. */
18767 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18768 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18772 /* This function is called whenever a label is defined, including fake
18773 labels instantiated off the dot special symbol. It is used when
18774 handling branch delays; if a branch has a label, we assume we cannot
18775 move it. This also bumps the value of the symbol by 1 in compressed
18779 mips_record_label (symbolS
*sym
)
18781 segment_info_type
*si
= seg_info (now_seg
);
18782 struct insn_label_list
*l
;
18784 if (free_insn_labels
== NULL
)
18785 l
= XNEW (struct insn_label_list
);
18788 l
= free_insn_labels
;
18789 free_insn_labels
= l
->next
;
18793 l
->next
= si
->label_list
;
18794 si
->label_list
= l
;
18797 /* This function is called as tc_frob_label() whenever a label is defined
18798 and adds a DWARF-2 record we only want for true labels. */
18801 mips_define_label (symbolS
*sym
)
18803 mips_record_label (sym
);
18804 dwarf2_emit_label (sym
);
18807 /* This function is called by tc_new_dot_label whenever a new dot symbol
18811 mips_add_dot_label (symbolS
*sym
)
18813 mips_record_label (sym
);
18814 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18815 mips_compressed_mark_label (sym
);
18818 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18819 static unsigned int
18820 mips_convert_ase_flags (int ase
)
18822 unsigned int ext_ases
= 0;
18825 ext_ases
|= AFL_ASE_DSP
;
18826 if (ase
& ASE_DSPR2
)
18827 ext_ases
|= AFL_ASE_DSPR2
;
18828 if (ase
& ASE_DSPR3
)
18829 ext_ases
|= AFL_ASE_DSPR3
;
18831 ext_ases
|= AFL_ASE_EVA
;
18833 ext_ases
|= AFL_ASE_MCU
;
18834 if (ase
& ASE_MDMX
)
18835 ext_ases
|= AFL_ASE_MDMX
;
18836 if (ase
& ASE_MIPS3D
)
18837 ext_ases
|= AFL_ASE_MIPS3D
;
18839 ext_ases
|= AFL_ASE_MT
;
18840 if (ase
& ASE_SMARTMIPS
)
18841 ext_ases
|= AFL_ASE_SMARTMIPS
;
18842 if (ase
& ASE_VIRT
)
18843 ext_ases
|= AFL_ASE_VIRT
;
18845 ext_ases
|= AFL_ASE_MSA
;
18847 ext_ases
|= AFL_ASE_XPA
;
18851 /* Some special processing for a MIPS ELF file. */
18854 mips_elf_final_processing (void)
18857 Elf_Internal_ABIFlags_v0 flags
;
18861 switch (file_mips_opts
.isa
)
18864 flags
.isa_level
= 1;
18867 flags
.isa_level
= 2;
18870 flags
.isa_level
= 3;
18873 flags
.isa_level
= 4;
18876 flags
.isa_level
= 5;
18879 flags
.isa_level
= 32;
18883 flags
.isa_level
= 32;
18887 flags
.isa_level
= 32;
18891 flags
.isa_level
= 32;
18895 flags
.isa_level
= 32;
18899 flags
.isa_level
= 64;
18903 flags
.isa_level
= 64;
18907 flags
.isa_level
= 64;
18911 flags
.isa_level
= 64;
18915 flags
.isa_level
= 64;
18920 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18921 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18922 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18923 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18925 flags
.cpr2_size
= AFL_REG_NONE
;
18926 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18927 Tag_GNU_MIPS_ABI_FP
);
18928 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18929 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18930 if (file_ase_mips16
)
18931 flags
.ases
|= AFL_ASE_MIPS16
;
18932 if (file_ase_micromips
)
18933 flags
.ases
|= AFL_ASE_MICROMIPS
;
18935 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18936 || file_mips_opts
.fp
== 64)
18937 && file_mips_opts
.oddspreg
)
18938 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18941 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18942 ((Elf_External_ABIFlags_v0
*)
18945 /* Write out the register information. */
18946 if (mips_abi
!= N64_ABI
)
18950 s
.ri_gprmask
= mips_gprmask
;
18951 s
.ri_cprmask
[0] = mips_cprmask
[0];
18952 s
.ri_cprmask
[1] = mips_cprmask
[1];
18953 s
.ri_cprmask
[2] = mips_cprmask
[2];
18954 s
.ri_cprmask
[3] = mips_cprmask
[3];
18955 /* The gp_value field is set by the MIPS ELF backend. */
18957 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18958 ((Elf32_External_RegInfo
*)
18959 mips_regmask_frag
));
18963 Elf64_Internal_RegInfo s
;
18965 s
.ri_gprmask
= mips_gprmask
;
18967 s
.ri_cprmask
[0] = mips_cprmask
[0];
18968 s
.ri_cprmask
[1] = mips_cprmask
[1];
18969 s
.ri_cprmask
[2] = mips_cprmask
[2];
18970 s
.ri_cprmask
[3] = mips_cprmask
[3];
18971 /* The gp_value field is set by the MIPS ELF backend. */
18973 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18974 ((Elf64_External_RegInfo
*)
18975 mips_regmask_frag
));
18978 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18979 sort of BFD interface for this. */
18980 if (mips_any_noreorder
)
18981 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18982 if (mips_pic
!= NO_PIC
)
18984 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18985 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18988 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18990 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18991 defined at present; this might need to change in future. */
18992 if (file_ase_mips16
)
18993 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18994 if (file_ase_micromips
)
18995 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18996 if (file_mips_opts
.ase
& ASE_MDMX
)
18997 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18999 /* Set the MIPS ELF ABI flags. */
19000 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19001 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19002 else if (mips_abi
== O64_ABI
)
19003 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19004 else if (mips_abi
== EABI_ABI
)
19006 if (file_mips_opts
.gp
== 64)
19007 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19009 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19011 else if (mips_abi
== N32_ABI
)
19012 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
19014 /* Nothing to do for N64_ABI. */
19016 if (mips_32bitmode
)
19017 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19019 if (mips_nan2008
== 1)
19020 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19022 /* 32 bit code with 64 bit FP registers. */
19023 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19024 Tag_GNU_MIPS_ABI_FP
);
19025 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19026 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19029 typedef struct proc
{
19031 symbolS
*func_end_sym
;
19032 unsigned long reg_mask
;
19033 unsigned long reg_offset
;
19034 unsigned long fpreg_mask
;
19035 unsigned long fpreg_offset
;
19036 unsigned long frame_offset
;
19037 unsigned long frame_reg
;
19038 unsigned long pc_reg
;
19041 static procS cur_proc
;
19042 static procS
*cur_proc_ptr
;
19043 static int numprocs
;
19045 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19046 as "2", and a normal nop as "0". */
19048 #define NOP_OPCODE_MIPS 0
19049 #define NOP_OPCODE_MIPS16 1
19050 #define NOP_OPCODE_MICROMIPS 2
19053 mips_nop_opcode (void)
19055 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19056 return NOP_OPCODE_MICROMIPS
;
19057 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19058 return NOP_OPCODE_MIPS16
;
19060 return NOP_OPCODE_MIPS
;
19063 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19064 32-bit microMIPS NOPs here (if applicable). */
19067 mips_handle_align (fragS
*fragp
)
19071 int bytes
, size
, excess
;
19074 if (fragp
->fr_type
!= rs_align_code
)
19077 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19079 switch (nop_opcode
)
19081 case NOP_OPCODE_MICROMIPS
:
19082 opcode
= micromips_nop32_insn
.insn_opcode
;
19085 case NOP_OPCODE_MIPS16
:
19086 opcode
= mips16_nop_insn
.insn_opcode
;
19089 case NOP_OPCODE_MIPS
:
19091 opcode
= nop_insn
.insn_opcode
;
19096 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19097 excess
= bytes
% size
;
19099 /* Handle the leading part if we're not inserting a whole number of
19100 instructions, and make it the end of the fixed part of the frag.
19101 Try to fit in a short microMIPS NOP if applicable and possible,
19102 and use zeroes otherwise. */
19103 gas_assert (excess
< 4);
19104 fragp
->fr_fix
+= excess
;
19109 /* Fall through. */
19111 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19113 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19117 /* Fall through. */
19120 /* Fall through. */
19125 md_number_to_chars (p
, opcode
, size
);
19126 fragp
->fr_var
= size
;
19135 if (*input_line_pointer
== '-')
19137 ++input_line_pointer
;
19140 if (!ISDIGIT (*input_line_pointer
))
19141 as_bad (_("expected simple number"));
19142 if (input_line_pointer
[0] == '0')
19144 if (input_line_pointer
[1] == 'x')
19146 input_line_pointer
+= 2;
19147 while (ISXDIGIT (*input_line_pointer
))
19150 val
|= hex_value (*input_line_pointer
++);
19152 return negative
? -val
: val
;
19156 ++input_line_pointer
;
19157 while (ISDIGIT (*input_line_pointer
))
19160 val
|= *input_line_pointer
++ - '0';
19162 return negative
? -val
: val
;
19165 if (!ISDIGIT (*input_line_pointer
))
19167 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19168 *input_line_pointer
, *input_line_pointer
);
19169 as_warn (_("invalid number"));
19172 while (ISDIGIT (*input_line_pointer
))
19175 val
+= *input_line_pointer
++ - '0';
19177 return negative
? -val
: val
;
19180 /* The .file directive; just like the usual .file directive, but there
19181 is an initial number which is the ECOFF file index. In the non-ECOFF
19182 case .file implies DWARF-2. */
19185 s_mips_file (int x ATTRIBUTE_UNUSED
)
19187 static int first_file_directive
= 0;
19189 if (ECOFF_DEBUGGING
)
19198 filename
= dwarf2_directive_file (0);
19200 /* Versions of GCC up to 3.1 start files with a ".file"
19201 directive even for stabs output. Make sure that this
19202 ".file" is handled. Note that you need a version of GCC
19203 after 3.1 in order to support DWARF-2 on MIPS. */
19204 if (filename
!= NULL
&& ! first_file_directive
)
19206 (void) new_logical_line (filename
, -1);
19207 s_app_file_string (filename
, 0);
19209 first_file_directive
= 1;
19213 /* The .loc directive, implying DWARF-2. */
19216 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19218 if (!ECOFF_DEBUGGING
)
19219 dwarf2_directive_loc (0);
19222 /* The .end directive. */
19225 s_mips_end (int x ATTRIBUTE_UNUSED
)
19229 /* Following functions need their own .frame and .cprestore directives. */
19230 mips_frame_reg_valid
= 0;
19231 mips_cprestore_valid
= 0;
19233 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19236 demand_empty_rest_of_line ();
19241 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19242 as_warn (_(".end not in text section"));
19246 as_warn (_(".end directive without a preceding .ent directive"));
19247 demand_empty_rest_of_line ();
19253 gas_assert (S_GET_NAME (p
));
19254 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19255 as_warn (_(".end symbol does not match .ent symbol"));
19257 if (debug_type
== DEBUG_STABS
)
19258 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19262 as_warn (_(".end directive missing or unknown symbol"));
19264 /* Create an expression to calculate the size of the function. */
19265 if (p
&& cur_proc_ptr
)
19267 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19268 expressionS
*exp
= XNEW (expressionS
);
19271 exp
->X_op
= O_subtract
;
19272 exp
->X_add_symbol
= symbol_temp_new_now ();
19273 exp
->X_op_symbol
= p
;
19274 exp
->X_add_number
= 0;
19276 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19279 #ifdef md_flush_pending_output
19280 md_flush_pending_output ();
19283 /* Generate a .pdr section. */
19284 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19286 segT saved_seg
= now_seg
;
19287 subsegT saved_subseg
= now_subseg
;
19291 gas_assert (pdr_seg
);
19292 subseg_set (pdr_seg
, 0);
19294 /* Write the symbol. */
19295 exp
.X_op
= O_symbol
;
19296 exp
.X_add_symbol
= p
;
19297 exp
.X_add_number
= 0;
19298 emit_expr (&exp
, 4);
19300 fragp
= frag_more (7 * 4);
19302 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19303 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19304 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19305 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19306 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19307 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19308 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19310 subseg_set (saved_seg
, saved_subseg
);
19313 cur_proc_ptr
= NULL
;
19316 /* The .aent and .ent directives. */
19319 s_mips_ent (int aent
)
19323 symbolP
= get_symbol ();
19324 if (*input_line_pointer
== ',')
19325 ++input_line_pointer
;
19326 SKIP_WHITESPACE ();
19327 if (ISDIGIT (*input_line_pointer
)
19328 || *input_line_pointer
== '-')
19331 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19332 as_warn (_(".ent or .aent not in text section"));
19334 if (!aent
&& cur_proc_ptr
)
19335 as_warn (_("missing .end"));
19339 /* This function needs its own .frame and .cprestore directives. */
19340 mips_frame_reg_valid
= 0;
19341 mips_cprestore_valid
= 0;
19343 cur_proc_ptr
= &cur_proc
;
19344 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19346 cur_proc_ptr
->func_sym
= symbolP
;
19350 if (debug_type
== DEBUG_STABS
)
19351 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19352 S_GET_NAME (symbolP
));
19355 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19357 demand_empty_rest_of_line ();
19360 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19361 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19362 s_mips_frame is used so that we can set the PDR information correctly.
19363 We can't use the ecoff routines because they make reference to the ecoff
19364 symbol table (in the mdebug section). */
19367 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19369 if (ECOFF_DEBUGGING
)
19375 if (cur_proc_ptr
== (procS
*) NULL
)
19377 as_warn (_(".frame outside of .ent"));
19378 demand_empty_rest_of_line ();
19382 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19384 SKIP_WHITESPACE ();
19385 if (*input_line_pointer
++ != ','
19386 || get_absolute_expression_and_terminator (&val
) != ',')
19388 as_warn (_("bad .frame directive"));
19389 --input_line_pointer
;
19390 demand_empty_rest_of_line ();
19394 cur_proc_ptr
->frame_offset
= val
;
19395 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19397 demand_empty_rest_of_line ();
19401 /* The .fmask and .mask directives. If the mdebug section is present
19402 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19403 embedded targets, s_mips_mask is used so that we can set the PDR
19404 information correctly. We can't use the ecoff routines because they
19405 make reference to the ecoff symbol table (in the mdebug section). */
19408 s_mips_mask (int reg_type
)
19410 if (ECOFF_DEBUGGING
)
19411 s_ignore (reg_type
);
19416 if (cur_proc_ptr
== (procS
*) NULL
)
19418 as_warn (_(".mask/.fmask outside of .ent"));
19419 demand_empty_rest_of_line ();
19423 if (get_absolute_expression_and_terminator (&mask
) != ',')
19425 as_warn (_("bad .mask/.fmask directive"));
19426 --input_line_pointer
;
19427 demand_empty_rest_of_line ();
19431 off
= get_absolute_expression ();
19433 if (reg_type
== 'F')
19435 cur_proc_ptr
->fpreg_mask
= mask
;
19436 cur_proc_ptr
->fpreg_offset
= off
;
19440 cur_proc_ptr
->reg_mask
= mask
;
19441 cur_proc_ptr
->reg_offset
= off
;
19444 demand_empty_rest_of_line ();
19448 /* A table describing all the processors gas knows about. Names are
19449 matched in the order listed.
19451 To ease comparison, please keep this table in the same order as
19452 gcc's mips_cpu_info_table[]. */
19453 static const struct mips_cpu_info mips_cpu_info_table
[] =
19455 /* Entries for generic ISAs */
19456 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19457 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19458 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19459 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19460 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19461 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19462 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19463 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19464 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19465 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19466 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19467 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19468 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19469 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19470 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19473 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19474 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19475 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19478 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19481 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19482 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19483 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19484 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19485 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19486 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19487 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19488 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19489 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19490 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19491 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19492 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19493 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19494 /* ST Microelectronics Loongson 2E and 2F cores */
19495 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19496 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19499 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19500 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19501 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19502 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19503 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19504 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19505 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19506 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19507 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19508 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19509 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19510 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19511 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19512 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19513 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19516 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19517 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19518 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19519 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19521 /* MIPS 32 Release 2 */
19522 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19523 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19524 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19525 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19526 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19527 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19528 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19529 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19530 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19531 ISA_MIPS32R2
, CPU_MIPS32R2
},
19532 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19533 ISA_MIPS32R2
, CPU_MIPS32R2
},
19534 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19535 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19536 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19537 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19538 /* Deprecated forms of the above. */
19539 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19540 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19541 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19542 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19543 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19544 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19545 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19546 /* Deprecated forms of the above. */
19547 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19548 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19549 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19550 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19551 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19552 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19553 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19554 /* Deprecated forms of the above. */
19555 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19556 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19557 /* 34Kn is a 34kc without DSP. */
19558 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19559 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19560 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19561 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19562 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19563 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19564 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19565 /* Deprecated forms of the above. */
19566 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19567 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19568 /* 1004K cores are multiprocessor versions of the 34K. */
19569 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19570 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19571 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19572 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19573 /* interaptiv is the new name for 1004kf */
19574 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19576 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19577 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19578 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19579 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19582 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19583 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19584 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19585 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19587 /* Broadcom SB-1 CPU core */
19588 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19589 /* Broadcom SB-1A CPU core */
19590 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19592 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19594 /* MIPS 64 Release 2 */
19596 /* Cavium Networks Octeon CPU core */
19597 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19598 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19599 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19600 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19603 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19606 XLP is mostly like XLR, with the prominent exception that it is
19607 MIPS64R2 rather than MIPS64. */
19608 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19610 /* MIPS 64 Release 6 */
19611 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19612 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19615 { NULL
, 0, 0, 0, 0 }
19619 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19620 with a final "000" replaced by "k". Ignore case.
19622 Note: this function is shared between GCC and GAS. */
19625 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19627 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19628 given
++, canonical
++;
19630 return ((*given
== 0 && *canonical
== 0)
19631 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19635 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19636 CPU name. We've traditionally allowed a lot of variation here.
19638 Note: this function is shared between GCC and GAS. */
19641 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19643 /* First see if the name matches exactly, or with a final "000"
19644 turned into "k". */
19645 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19648 /* If not, try comparing based on numerical designation alone.
19649 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19650 if (TOLOWER (*given
) == 'r')
19652 if (!ISDIGIT (*given
))
19655 /* Skip over some well-known prefixes in the canonical name,
19656 hoping to find a number there too. */
19657 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19659 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19661 else if (TOLOWER (canonical
[0]) == 'r')
19664 return mips_strict_matching_cpu_name_p (canonical
, given
);
19668 /* Parse an option that takes the name of a processor as its argument.
19669 OPTION is the name of the option and CPU_STRING is the argument.
19670 Return the corresponding processor enumeration if the CPU_STRING is
19671 recognized, otherwise report an error and return null.
19673 A similar function exists in GCC. */
19675 static const struct mips_cpu_info
*
19676 mips_parse_cpu (const char *option
, const char *cpu_string
)
19678 const struct mips_cpu_info
*p
;
19680 /* 'from-abi' selects the most compatible architecture for the given
19681 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19682 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19683 version. Look first at the -mgp options, if given, otherwise base
19684 the choice on MIPS_DEFAULT_64BIT.
19686 Treat NO_ABI like the EABIs. One reason to do this is that the
19687 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19688 architecture. This code picks MIPS I for 'mips' and MIPS III for
19689 'mips64', just as we did in the days before 'from-abi'. */
19690 if (strcasecmp (cpu_string
, "from-abi") == 0)
19692 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19693 return mips_cpu_info_from_isa (ISA_MIPS1
);
19695 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19696 return mips_cpu_info_from_isa (ISA_MIPS3
);
19698 if (file_mips_opts
.gp
>= 0)
19699 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19700 ? ISA_MIPS1
: ISA_MIPS3
);
19702 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19707 /* 'default' has traditionally been a no-op. Probably not very useful. */
19708 if (strcasecmp (cpu_string
, "default") == 0)
19711 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19712 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19715 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19719 /* Return the canonical processor information for ISA (a member of the
19720 ISA_MIPS* enumeration). */
19722 static const struct mips_cpu_info
*
19723 mips_cpu_info_from_isa (int isa
)
19727 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19728 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19729 && isa
== mips_cpu_info_table
[i
].isa
)
19730 return (&mips_cpu_info_table
[i
]);
19735 static const struct mips_cpu_info
*
19736 mips_cpu_info_from_arch (int arch
)
19740 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19741 if (arch
== mips_cpu_info_table
[i
].cpu
)
19742 return (&mips_cpu_info_table
[i
]);
19748 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19752 fprintf (stream
, "%24s", "");
19757 fprintf (stream
, ", ");
19761 if (*col_p
+ strlen (string
) > 72)
19763 fprintf (stream
, "\n%24s", "");
19767 fprintf (stream
, "%s", string
);
19768 *col_p
+= strlen (string
);
19774 md_show_usage (FILE *stream
)
19779 fprintf (stream
, _("\
19781 -EB generate big endian output\n\
19782 -EL generate little endian output\n\
19783 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19784 -G NUM allow referencing objects up to NUM bytes\n\
19785 implicitly with the gp register [default 8]\n"));
19786 fprintf (stream
, _("\
19787 -mips1 generate MIPS ISA I instructions\n\
19788 -mips2 generate MIPS ISA II instructions\n\
19789 -mips3 generate MIPS ISA III instructions\n\
19790 -mips4 generate MIPS ISA IV instructions\n\
19791 -mips5 generate MIPS ISA V instructions\n\
19792 -mips32 generate MIPS32 ISA instructions\n\
19793 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19794 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19795 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19796 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19797 -mips64 generate MIPS64 ISA instructions\n\
19798 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19799 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19800 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19801 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19802 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19806 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19807 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19808 show (stream
, "from-abi", &column
, &first
);
19809 fputc ('\n', stream
);
19811 fprintf (stream
, _("\
19812 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19813 -no-mCPU don't generate code specific to CPU.\n\
19814 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19818 show (stream
, "3900", &column
, &first
);
19819 show (stream
, "4010", &column
, &first
);
19820 show (stream
, "4100", &column
, &first
);
19821 show (stream
, "4650", &column
, &first
);
19822 fputc ('\n', stream
);
19824 fprintf (stream
, _("\
19825 -mips16 generate mips16 instructions\n\
19826 -no-mips16 do not generate mips16 instructions\n"));
19827 fprintf (stream
, _("\
19828 -mmicromips generate microMIPS instructions\n\
19829 -mno-micromips do not generate microMIPS instructions\n"));
19830 fprintf (stream
, _("\
19831 -msmartmips generate smartmips instructions\n\
19832 -mno-smartmips do not generate smartmips instructions\n"));
19833 fprintf (stream
, _("\
19834 -mdsp generate DSP instructions\n\
19835 -mno-dsp do not generate DSP instructions\n"));
19836 fprintf (stream
, _("\
19837 -mdspr2 generate DSP R2 instructions\n\
19838 -mno-dspr2 do not generate DSP R2 instructions\n"));
19839 fprintf (stream
, _("\
19840 -mdspr3 generate DSP R3 instructions\n\
19841 -mno-dspr3 do not generate DSP R3 instructions\n"));
19842 fprintf (stream
, _("\
19843 -mmt generate MT instructions\n\
19844 -mno-mt do not generate MT instructions\n"));
19845 fprintf (stream
, _("\
19846 -mmcu generate MCU instructions\n\
19847 -mno-mcu do not generate MCU instructions\n"));
19848 fprintf (stream
, _("\
19849 -mmsa generate MSA instructions\n\
19850 -mno-msa do not generate MSA instructions\n"));
19851 fprintf (stream
, _("\
19852 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19853 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19854 fprintf (stream
, _("\
19855 -mvirt generate Virtualization instructions\n\
19856 -mno-virt do not generate Virtualization instructions\n"));
19857 fprintf (stream
, _("\
19858 -minsn32 only generate 32-bit microMIPS instructions\n\
19859 -mno-insn32 generate all microMIPS instructions\n"));
19860 fprintf (stream
, _("\
19861 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19862 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19863 -mfix-vr4120 work around certain VR4120 errata\n\
19864 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19865 -mfix-24k insert a nop after ERET and DERET instructions\n\
19866 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19867 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19868 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19869 -msym32 assume all symbols have 32-bit values\n\
19870 -O0 remove unneeded NOPs, do not swap branches\n\
19871 -O remove unneeded NOPs and swap branches\n\
19872 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19873 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19874 fprintf (stream
, _("\
19875 -mhard-float allow floating-point instructions\n\
19876 -msoft-float do not allow floating-point instructions\n\
19877 -msingle-float only allow 32-bit floating-point operations\n\
19878 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19879 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19880 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19881 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
19882 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
19883 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19887 show (stream
, "legacy", &column
, &first
);
19888 show (stream
, "2008", &column
, &first
);
19890 fputc ('\n', stream
);
19892 fprintf (stream
, _("\
19893 -KPIC, -call_shared generate SVR4 position independent code\n\
19894 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19895 -mvxworks-pic generate VxWorks position independent code\n\
19896 -non_shared do not generate code that can operate with DSOs\n\
19897 -xgot assume a 32 bit GOT\n\
19898 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19899 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19900 position dependent (non shared) code\n\
19901 -mabi=ABI create ABI conformant object file for:\n"));
19905 show (stream
, "32", &column
, &first
);
19906 show (stream
, "o64", &column
, &first
);
19907 show (stream
, "n32", &column
, &first
);
19908 show (stream
, "64", &column
, &first
);
19909 show (stream
, "eabi", &column
, &first
);
19911 fputc ('\n', stream
);
19913 fprintf (stream
, _("\
19914 -32 create o32 ABI object file (default)\n\
19915 -n32 create n32 ABI object file\n\
19916 -64 create 64 ABI object file\n"));
19921 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19923 if (HAVE_64BIT_SYMBOLS
)
19924 return dwarf2_format_64bit_irix
;
19926 return dwarf2_format_32bit
;
19931 mips_dwarf2_addr_size (void)
19933 if (HAVE_64BIT_OBJECTS
)
19939 /* Standard calling conventions leave the CFA at SP on entry. */
19941 mips_cfi_frame_initial_instructions (void)
19943 cfi_add_CFA_def_cfa_register (SP
);
19947 tc_mips_regname_to_dw2regnum (char *regname
)
19949 unsigned int regnum
= -1;
19952 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19958 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19959 Given a symbolic attribute NAME, return the proper integer value.
19960 Returns -1 if the attribute is not known. */
19963 mips_convert_symbolic_attribute (const char *name
)
19965 static const struct
19970 attribute_table
[] =
19972 #define T(tag) {#tag, tag}
19973 T (Tag_GNU_MIPS_ABI_FP
),
19974 T (Tag_GNU_MIPS_ABI_MSA
),
19982 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
19983 if (streq (name
, attribute_table
[i
].name
))
19984 return attribute_table
[i
].tag
;
19992 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
19994 mips_emit_delays ();
19996 as_warn (_("missing .end at end of assembly"));
19998 /* Just in case no code was emitted, do the consistency check. */
19999 file_mips_check_options ();
20001 /* Set a floating-point ABI if the user did not. */
20002 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20004 /* Perform consistency checks on the floating-point ABI. */
20005 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20006 Tag_GNU_MIPS_ABI_FP
);
20007 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20008 check_fpabi (fpabi
);
20012 /* Soft-float gets precedence over single-float, the two options should
20013 not be used together so this should not matter. */
20014 if (file_mips_opts
.soft_float
== 1)
20015 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20016 /* Single-float gets precedence over all double_float cases. */
20017 else if (file_mips_opts
.single_float
== 1)
20018 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20021 switch (file_mips_opts
.fp
)
20024 if (file_mips_opts
.gp
== 32)
20025 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20028 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20031 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20032 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20033 else if (file_mips_opts
.gp
== 32)
20034 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20036 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20041 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20042 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20046 /* Returns the relocation type required for a particular CFI encoding. */
20048 bfd_reloc_code_real_type
20049 mips_cfi_reloc_for_encoding (int encoding
)
20051 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20052 return BFD_RELOC_32_PCREL
;
20053 else return BFD_RELOC_NONE
;