1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
159 /* The ABI to use. */
170 /* MIPS ABI we are using for this output file. */
171 static enum mips_abi_level mips_abi
= NO_ABI
;
173 /* Whether or not we have code that can call pic code. */
174 int mips_abicalls
= FALSE
;
176 /* Whether or not we have code which can be put into a shared
178 static bfd_boolean mips_in_shared
= TRUE
;
180 /* This is the set of options which may be modified by the .set
181 pseudo-op. We use a struct so that .set push and .set pop are more
184 struct mips_set_options
186 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
187 if it has not been initialized. Changed by `.set mipsN', and the
188 -mipsN command line option, and the default CPU. */
190 /* Enabled Application Specific Extensions (ASEs). These are set to -1
191 if they have not been initialized. Changed by `.set <asename>', by
192 command line options, and based on the default architecture. */
195 /* Whether we are assembling for the mips16 processor. 0 if we are
196 not, 1 if we are, and -1 if the value has not been initialized.
197 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
198 -nomips16 command line options, and the default CPU. */
200 /* Non-zero if we should not reorder instructions. Changed by `.set
201 reorder' and `.set noreorder'. */
203 /* Non-zero if we should not permit the $at ($1) register to be used
204 in instructions. Changed by `.set at' and `.set noat'. */
206 /* Non-zero if we should warn when a macro instruction expands into
207 more than one machine instruction. Changed by `.set nomacro' and
209 int warn_about_macros
;
210 /* Non-zero if we should not move instructions. Changed by `.set
211 move', `.set volatile', `.set nomove', and `.set novolatile'. */
213 /* Non-zero if we should not optimize branches by moving the target
214 of the branch into the delay slot. Actually, we don't perform
215 this optimization anyhow. Changed by `.set bopt' and `.set
218 /* Non-zero if we should not autoextend mips16 instructions.
219 Changed by `.set autoextend' and `.set noautoextend'. */
221 /* Restrict general purpose registers and floating point registers
222 to 32 bit. This is initially determined when -mgp32 or -mfp32
223 is passed but can changed if the assembler code uses .set mipsN. */
226 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
227 command line option, and the default CPU. */
229 /* True if ".set sym32" is in effect. */
233 /* True if -mgp32 was passed. */
234 static int file_mips_gp32
= -1;
236 /* True if -mfp32 was passed. */
237 static int file_mips_fp32
= -1;
239 /* This is the struct we use to hold the current set of options. Note
240 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
241 -1 to indicate that they have not been initialized. */
243 static struct mips_set_options mips_opts
=
245 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
248 /* These variables are filled in with the masks of registers used.
249 The object format code reads them and puts them in the appropriate
251 unsigned long mips_gprmask
;
252 unsigned long mips_cprmask
[4];
254 /* MIPS ISA we are using for this output file. */
255 static int file_mips_isa
= ISA_UNKNOWN
;
257 /* True if -mips16 was passed or implied by arguments passed on the
258 command line (e.g., by -march). */
259 static int file_ase_mips16
;
261 /* True if -mips3d was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips3d
;
265 /* True if -mdmx was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mdmx
;
269 /* The argument of the -march= flag. The architecture we are assembling. */
270 static int file_mips_arch
= CPU_UNKNOWN
;
271 static const char *mips_arch_string
;
273 /* The argument of the -mtune= flag. The architecture for which we
275 static int mips_tune
= CPU_UNKNOWN
;
276 static const char *mips_tune_string
;
278 /* True when generating 32-bit code for a 64-bit processor. */
279 static int mips_32bitmode
= 0;
281 /* True if the given ABI requires 32-bit registers. */
282 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
284 /* Likewise 64-bit registers. */
285 #define ABI_NEEDS_64BIT_REGS(ABI) \
287 || (ABI) == N64_ABI \
290 /* Return true if ISA supports 64 bit gp register instructions. */
291 #define ISA_HAS_64BIT_REGS(ISA) ( \
293 || (ISA) == ISA_MIPS4 \
294 || (ISA) == ISA_MIPS5 \
295 || (ISA) == ISA_MIPS64 \
296 || (ISA) == ISA_MIPS64R2 \
299 /* Return true if ISA supports 64-bit right rotate (dror et al.)
301 #define ISA_HAS_DROR(ISA) ( \
302 (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 32-bit right rotate (ror et al.)
307 #define ISA_HAS_ROR(ISA) ( \
308 (ISA) == ISA_MIPS32R2 \
309 || (ISA) == ISA_MIPS64R2 \
312 #define HAVE_32BIT_GPRS \
313 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
315 #define HAVE_32BIT_FPRS \
316 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
318 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
319 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
321 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
323 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
325 /* True if relocations are stored in-place. */
326 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
328 /* The ABI-derived address size. */
329 #define HAVE_64BIT_ADDRESSES \
330 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
331 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
333 /* The size of symbolic constants (i.e., expressions of the form
334 "SYMBOL" or "SYMBOL + OFFSET"). */
335 #define HAVE_32BIT_SYMBOLS \
336 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
337 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
339 /* Addresses are loaded in different ways, depending on the address size
340 in use. The n32 ABI Documentation also mandates the use of additions
341 with overflow checking, but existing implementations don't follow it. */
342 #define ADDRESS_ADD_INSN \
343 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
345 #define ADDRESS_ADDI_INSN \
346 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
348 #define ADDRESS_LOAD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
351 #define ADDRESS_STORE_INSN \
352 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
354 /* Return true if the given CPU supports the MIPS16 ASE. */
355 #define CPU_HAS_MIPS16(cpu) \
356 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
357 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
359 /* Return true if the given CPU supports the MIPS3D ASE. */
360 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
363 /* Return true if the given CPU supports the MDMX ASE. */
364 #define CPU_HAS_MDMX(cpu) (FALSE \
367 /* True if CPU has a dror instruction. */
368 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
370 /* True if CPU has a ror instruction. */
371 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
373 /* True if mflo and mfhi can be immediately followed by instructions
374 which write to the HI and LO registers.
376 According to MIPS specifications, MIPS ISAs I, II, and III need
377 (at least) two instructions between the reads of HI/LO and
378 instructions which write them, and later ISAs do not. Contradicting
379 the MIPS specifications, some MIPS IV processor user manuals (e.g.
380 the UM for the NEC Vr5000) document needing the instructions between
381 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
382 MIPS64 and later ISAs to have the interlocks, plus any specific
383 earlier-ISA CPUs for which CPU documentation declares that the
384 instructions are really interlocked. */
385 #define hilo_interlocks \
386 (mips_opts.isa == ISA_MIPS32 \
387 || mips_opts.isa == ISA_MIPS32R2 \
388 || mips_opts.isa == ISA_MIPS64 \
389 || mips_opts.isa == ISA_MIPS64R2 \
390 || mips_opts.arch == CPU_R4010 \
391 || mips_opts.arch == CPU_R10000 \
392 || mips_opts.arch == CPU_R12000 \
393 || mips_opts.arch == CPU_RM7000 \
394 || mips_opts.arch == CPU_VR5500 \
397 /* Whether the processor uses hardware interlocks to protect reads
398 from the GPRs after they are loaded from memory, and thus does not
399 require nops to be inserted. This applies to instructions marked
400 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
402 #define gpr_interlocks \
403 (mips_opts.isa != ISA_MIPS1 \
404 || mips_opts.arch == CPU_R3900)
406 /* Whether the processor uses hardware interlocks to avoid delays
407 required by coprocessor instructions, and thus does not require
408 nops to be inserted. This applies to instructions marked
409 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
410 between instructions marked INSN_WRITE_COND_CODE and ones marked
411 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
412 levels I, II, and III. */
413 /* Itbl support may require additional care here. */
414 #define cop_interlocks \
415 ((mips_opts.isa != ISA_MIPS1 \
416 && mips_opts.isa != ISA_MIPS2 \
417 && mips_opts.isa != ISA_MIPS3) \
418 || mips_opts.arch == CPU_R4300 \
421 /* Whether the processor uses hardware interlocks to protect reads
422 from coprocessor registers after they are loaded from memory, and
423 thus does not require nops to be inserted. This applies to
424 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
425 requires at MIPS ISA level I. */
426 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
428 /* Is this a mfhi or mflo instruction? */
429 #define MF_HILO_INSN(PINFO) \
430 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
432 /* MIPS PIC level. */
434 enum mips_pic_level mips_pic
;
436 /* 1 if we should generate 32 bit offsets from the $gp register in
437 SVR4_PIC mode. Currently has no meaning in other modes. */
438 static int mips_big_got
= 0;
440 /* 1 if trap instructions should used for overflow rather than break
442 static int mips_trap
= 0;
444 /* 1 if double width floating point constants should not be constructed
445 by assembling two single width halves into two single width floating
446 point registers which just happen to alias the double width destination
447 register. On some architectures this aliasing can be disabled by a bit
448 in the status register, and the setting of this bit cannot be determined
449 automatically at assemble time. */
450 static int mips_disable_float_construction
;
452 /* Non-zero if any .set noreorder directives were used. */
454 static int mips_any_noreorder
;
456 /* Non-zero if nops should be inserted when the register referenced in
457 an mfhi/mflo instruction is read in the next two instructions. */
458 static int mips_7000_hilo_fix
;
460 /* The size of the small data section. */
461 static unsigned int g_switch_value
= 8;
462 /* Whether the -G option was used. */
463 static int g_switch_seen
= 0;
468 /* If we can determine in advance that GP optimization won't be
469 possible, we can skip the relaxation stuff that tries to produce
470 GP-relative references. This makes delay slot optimization work
473 This function can only provide a guess, but it seems to work for
474 gcc output. It needs to guess right for gcc, otherwise gcc
475 will put what it thinks is a GP-relative instruction in a branch
478 I don't know if a fix is needed for the SVR4_PIC mode. I've only
479 fixed it for the non-PIC mode. KR 95/04/07 */
480 static int nopic_need_relax (symbolS
*, int);
482 /* handle of the OPCODE hash table */
483 static struct hash_control
*op_hash
= NULL
;
485 /* The opcode hash table we use for the mips16. */
486 static struct hash_control
*mips16_op_hash
= NULL
;
488 /* This array holds the chars that always start a comment. If the
489 pre-processor is disabled, these aren't very useful */
490 const char comment_chars
[] = "#";
492 /* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
494 .line and .file directives will appear in the pre-processed output */
495 /* Note that input_file.c hand checks for '#' at the beginning of the
496 first line of the input file. This is because the compiler outputs
497 #NO_APP at the beginning of its output. */
498 /* Also note that C style comments are always supported. */
499 const char line_comment_chars
[] = "#";
501 /* This array holds machine specific line separator characters. */
502 const char line_separator_chars
[] = ";";
504 /* Chars that can be used to separate mant from exp in floating point nums */
505 const char EXP_CHARS
[] = "eE";
507 /* Chars that mean this number is a floating point constant */
510 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
512 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
513 changed in read.c . Ideally it shouldn't have to know about it at all,
514 but nothing is ideal around here.
517 static char *insn_error
;
519 static int auto_align
= 1;
521 /* When outputting SVR4 PIC code, the assembler needs to know the
522 offset in the stack frame from which to restore the $gp register.
523 This is set by the .cprestore pseudo-op, and saved in this
525 static offsetT mips_cprestore_offset
= -1;
527 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
528 more optimizations, it can use a register value instead of a memory-saved
529 offset and even an other register than $gp as global pointer. */
530 static offsetT mips_cpreturn_offset
= -1;
531 static int mips_cpreturn_register
= -1;
532 static int mips_gp_register
= GP
;
533 static int mips_gprel_offset
= 0;
535 /* Whether mips_cprestore_offset has been set in the current function
536 (or whether it has already been warned about, if not). */
537 static int mips_cprestore_valid
= 0;
539 /* This is the register which holds the stack frame, as set by the
540 .frame pseudo-op. This is needed to implement .cprestore. */
541 static int mips_frame_reg
= SP
;
543 /* Whether mips_frame_reg has been set in the current function
544 (or whether it has already been warned about, if not). */
545 static int mips_frame_reg_valid
= 0;
547 /* To output NOP instructions correctly, we need to keep information
548 about the previous two instructions. */
550 /* Whether we are optimizing. The default value of 2 means to remove
551 unneeded NOPs and swap branch instructions when possible. A value
552 of 1 means to not swap branches. A value of 0 means to always
554 static int mips_optimize
= 2;
556 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
557 equivalent to seeing no -g option at all. */
558 static int mips_debug
= 0;
560 /* A list of previous instructions, with index 0 being the most recent. */
561 static struct mips_cl_insn history
[2];
563 /* Nop instructions used by emit_nop. */
564 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
566 /* The appropriate nop for the current mode. */
567 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
569 /* If this is set, it points to a frag holding nop instructions which
570 were inserted before the start of a noreorder section. If those
571 nops turn out to be unnecessary, the size of the frag can be
573 static fragS
*prev_nop_frag
;
575 /* The number of nop instructions we created in prev_nop_frag. */
576 static int prev_nop_frag_holds
;
578 /* The number of nop instructions that we know we need in
580 static int prev_nop_frag_required
;
582 /* The number of instructions we've seen since prev_nop_frag. */
583 static int prev_nop_frag_since
;
585 /* For ECOFF and ELF, relocations against symbols are done in two
586 parts, with a HI relocation and a LO relocation. Each relocation
587 has only 16 bits of space to store an addend. This means that in
588 order for the linker to handle carries correctly, it must be able
589 to locate both the HI and the LO relocation. This means that the
590 relocations must appear in order in the relocation table.
592 In order to implement this, we keep track of each unmatched HI
593 relocation. We then sort them so that they immediately precede the
594 corresponding LO relocation. */
599 struct mips_hi_fixup
*next
;
602 /* The section this fixup is in. */
606 /* The list of unmatched HI relocs. */
608 static struct mips_hi_fixup
*mips_hi_fixup_list
;
610 /* The frag containing the last explicit relocation operator.
611 Null if explicit relocations have not been used. */
613 static fragS
*prev_reloc_op_frag
;
615 /* Map normal MIPS register numbers to mips16 register numbers. */
617 #define X ILLEGAL_REG
618 static const int mips32_to_16_reg_map
[] =
620 X
, X
, 2, 3, 4, 5, 6, 7,
621 X
, X
, X
, X
, X
, X
, X
, X
,
622 0, 1, X
, X
, X
, X
, X
, X
,
623 X
, X
, X
, X
, X
, X
, X
, X
627 /* Map mips16 register numbers to normal MIPS register numbers. */
629 static const unsigned int mips16_to_32_reg_map
[] =
631 16, 17, 2, 3, 4, 5, 6, 7
634 static int mips_fix_vr4120
;
636 /* We don't relax branches by default, since this causes us to expand
637 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
638 fail to compute the offset before expanding the macro to the most
639 efficient expansion. */
641 static int mips_relax_branch
;
643 /* The expansion of many macros depends on the type of symbol that
644 they refer to. For example, when generating position-dependent code,
645 a macro that refers to a symbol may have two different expansions,
646 one which uses GP-relative addresses and one which uses absolute
647 addresses. When generating SVR4-style PIC, a macro may have
648 different expansions for local and global symbols.
650 We handle these situations by generating both sequences and putting
651 them in variant frags. In position-dependent code, the first sequence
652 will be the GP-relative one and the second sequence will be the
653 absolute one. In SVR4 PIC, the first sequence will be for global
654 symbols and the second will be for local symbols.
656 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
657 SECOND are the lengths of the two sequences in bytes. These fields
658 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
659 the subtype has the following flags:
662 Set if it has been decided that we should use the second
663 sequence instead of the first.
666 Set in the first variant frag if the macro's second implementation
667 is longer than its first. This refers to the macro as a whole,
668 not an individual relaxation.
671 Set in the first variant frag if the macro appeared in a .set nomacro
672 block and if one alternative requires a warning but the other does not.
675 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
678 The frag's "opcode" points to the first fixup for relaxable code.
680 Relaxable macros are generated using a sequence such as:
682 relax_start (SYMBOL);
683 ... generate first expansion ...
685 ... generate second expansion ...
688 The code and fixups for the unwanted alternative are discarded
689 by md_convert_frag. */
690 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
692 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
693 #define RELAX_SECOND(X) ((X) & 0xff)
694 #define RELAX_USE_SECOND 0x10000
695 #define RELAX_SECOND_LONGER 0x20000
696 #define RELAX_NOMACRO 0x40000
697 #define RELAX_DELAY_SLOT 0x80000
699 /* Branch without likely bit. If label is out of range, we turn:
701 beq reg1, reg2, label
711 with the following opcode replacements:
718 bltzal <-> bgezal (with jal label instead of j label)
720 Even though keeping the delay slot instruction in the delay slot of
721 the branch would be more efficient, it would be very tricky to do
722 correctly, because we'd have to introduce a variable frag *after*
723 the delay slot instruction, and expand that instead. Let's do it
724 the easy way for now, even if the branch-not-taken case now costs
725 one additional instruction. Out-of-range branches are not supposed
726 to be common, anyway.
728 Branch likely. If label is out of range, we turn:
730 beql reg1, reg2, label
731 delay slot (annulled if branch not taken)
740 delay slot (executed only if branch taken)
743 It would be possible to generate a shorter sequence by losing the
744 likely bit, generating something like:
749 delay slot (executed only if branch taken)
761 bltzall -> bgezal (with jal label instead of j label)
762 bgezall -> bltzal (ditto)
765 but it's not clear that it would actually improve performance. */
766 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
769 | ((toofar) ? 1 : 0) \
771 | ((likely) ? 4 : 0) \
772 | ((uncond) ? 8 : 0)))
773 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
774 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
775 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
776 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
777 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
779 /* For mips16 code, we use an entirely different form of relaxation.
780 mips16 supports two versions of most instructions which take
781 immediate values: a small one which takes some small value, and a
782 larger one which takes a 16 bit value. Since branches also follow
783 this pattern, relaxing these values is required.
785 We can assemble both mips16 and normal MIPS code in a single
786 object. Therefore, we need to support this type of relaxation at
787 the same time that we support the relaxation described above. We
788 use the high bit of the subtype field to distinguish these cases.
790 The information we store for this type of relaxation is the
791 argument code found in the opcode file for this relocation, whether
792 the user explicitly requested a small or extended form, and whether
793 the relocation is in a jump or jal delay slot. That tells us the
794 size of the value, and how it should be stored. We also store
795 whether the fragment is considered to be extended or not. We also
796 store whether this is known to be a branch to a different section,
797 whether we have tried to relax this frag yet, and whether we have
798 ever extended a PC relative fragment because of a shift count. */
799 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
802 | ((small) ? 0x100 : 0) \
803 | ((ext) ? 0x200 : 0) \
804 | ((dslot) ? 0x400 : 0) \
805 | ((jal_dslot) ? 0x800 : 0))
806 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
807 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
808 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
809 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
810 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
811 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
812 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
813 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
814 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
815 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
816 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
817 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
819 /* Is the given value a sign-extended 32-bit value? */
820 #define IS_SEXT_32BIT_NUM(x) \
821 (((x) &~ (offsetT) 0x7fffffff) == 0 \
822 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
824 /* Is the given value a sign-extended 16-bit value? */
825 #define IS_SEXT_16BIT_NUM(x) \
826 (((x) &~ (offsetT) 0x7fff) == 0 \
827 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
829 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
830 VALUE << SHIFT. VALUE is evaluated exactly once. */
831 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
832 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
833 | (((VALUE) & (MASK)) << (SHIFT)))
835 /* Extract bits MASK << SHIFT from STRUCT and shift them right
837 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
838 (((STRUCT) >> (SHIFT)) & (MASK))
840 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
841 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
843 include/opcode/mips.h specifies operand fields using the macros
844 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
845 with "MIPS16OP" instead of "OP". */
846 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
847 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
848 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
849 INSERT_BITS ((INSN).insn_opcode, VALUE, \
850 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
852 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
853 #define EXTRACT_OPERAND(FIELD, INSN) \
854 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
855 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
856 EXTRACT_BITS ((INSN).insn_opcode, \
857 MIPS16OP_MASK_##FIELD, \
860 /* Global variables used when generating relaxable macros. See the
861 comment above RELAX_ENCODE for more details about how relaxation
864 /* 0 if we're not emitting a relaxable macro.
865 1 if we're emitting the first of the two relaxation alternatives.
866 2 if we're emitting the second alternative. */
869 /* The first relaxable fixup in the current frag. (In other words,
870 the first fixup that refers to relaxable code.) */
873 /* sizes[0] says how many bytes of the first alternative are stored in
874 the current frag. Likewise sizes[1] for the second alternative. */
875 unsigned int sizes
[2];
877 /* The symbol on which the choice of sequence depends. */
881 /* Global variables used to decide whether a macro needs a warning. */
883 /* True if the macro is in a branch delay slot. */
884 bfd_boolean delay_slot_p
;
886 /* For relaxable macros, sizes[0] is the length of the first alternative
887 in bytes and sizes[1] is the length of the second alternative.
888 For non-relaxable macros, both elements give the length of the
890 unsigned int sizes
[2];
892 /* The first variant frag for this macro. */
894 } mips_macro_warning
;
896 /* Prototypes for static functions. */
898 #define internalError() \
899 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
901 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
903 static void append_insn
904 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
905 static void mips_no_prev_insn (int);
906 static void mips16_macro_build
907 (expressionS
*, const char *, const char *, va_list);
908 static void load_register (int, expressionS
*, int);
909 static void macro_start (void);
910 static void macro_end (void);
911 static void macro (struct mips_cl_insn
* ip
);
912 static void mips16_macro (struct mips_cl_insn
* ip
);
913 #ifdef LOSING_COMPILER
914 static void macro2 (struct mips_cl_insn
* ip
);
916 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
917 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
918 static void mips16_immed
919 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
920 unsigned long *, bfd_boolean
*, unsigned short *);
921 static size_t my_getSmallExpression
922 (expressionS
*, bfd_reloc_code_real_type
*, char *);
923 static void my_getExpression (expressionS
*, char *);
924 static void s_align (int);
925 static void s_change_sec (int);
926 static void s_change_section (int);
927 static void s_cons (int);
928 static void s_float_cons (int);
929 static void s_mips_globl (int);
930 static void s_option (int);
931 static void s_mipsset (int);
932 static void s_abicalls (int);
933 static void s_cpload (int);
934 static void s_cpsetup (int);
935 static void s_cplocal (int);
936 static void s_cprestore (int);
937 static void s_cpreturn (int);
938 static void s_gpvalue (int);
939 static void s_gpword (int);
940 static void s_gpdword (int);
941 static void s_cpadd (int);
942 static void s_insn (int);
943 static void md_obj_begin (void);
944 static void md_obj_end (void);
945 static void s_mips_ent (int);
946 static void s_mips_end (int);
947 static void s_mips_frame (int);
948 static void s_mips_mask (int reg_type
);
949 static void s_mips_stab (int);
950 static void s_mips_weakext (int);
951 static void s_mips_file (int);
952 static void s_mips_loc (int);
953 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
954 static int relaxed_branch_length (fragS
*, asection
*, int);
955 static int validate_mips_insn (const struct mips_opcode
*);
957 /* Table and functions used to map between CPU/ISA names, and
958 ISA levels, and CPU numbers. */
962 const char *name
; /* CPU or ISA name. */
963 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
964 int isa
; /* ISA level. */
965 int cpu
; /* CPU number (default CPU if ISA). */
968 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
969 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
970 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
974 The following pseudo-ops from the Kane and Heinrich MIPS book
975 should be defined here, but are currently unsupported: .alias,
976 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
978 The following pseudo-ops from the Kane and Heinrich MIPS book are
979 specific to the type of debugging information being generated, and
980 should be defined by the object format: .aent, .begin, .bend,
981 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
984 The following pseudo-ops from the Kane and Heinrich MIPS book are
985 not MIPS CPU specific, but are also not specific to the object file
986 format. This file is probably the best place to define them, but
987 they are not currently supported: .asm0, .endr, .lab, .repeat,
990 static const pseudo_typeS mips_pseudo_table
[] =
992 /* MIPS specific pseudo-ops. */
993 {"option", s_option
, 0},
994 {"set", s_mipsset
, 0},
995 {"rdata", s_change_sec
, 'r'},
996 {"sdata", s_change_sec
, 's'},
997 {"livereg", s_ignore
, 0},
998 {"abicalls", s_abicalls
, 0},
999 {"cpload", s_cpload
, 0},
1000 {"cpsetup", s_cpsetup
, 0},
1001 {"cplocal", s_cplocal
, 0},
1002 {"cprestore", s_cprestore
, 0},
1003 {"cpreturn", s_cpreturn
, 0},
1004 {"gpvalue", s_gpvalue
, 0},
1005 {"gpword", s_gpword
, 0},
1006 {"gpdword", s_gpdword
, 0},
1007 {"cpadd", s_cpadd
, 0},
1008 {"insn", s_insn
, 0},
1010 /* Relatively generic pseudo-ops that happen to be used on MIPS
1012 {"asciiz", stringer
, 1},
1013 {"bss", s_change_sec
, 'b'},
1015 {"half", s_cons
, 1},
1016 {"dword", s_cons
, 3},
1017 {"weakext", s_mips_weakext
, 0},
1019 /* These pseudo-ops are defined in read.c, but must be overridden
1020 here for one reason or another. */
1021 {"align", s_align
, 0},
1022 {"byte", s_cons
, 0},
1023 {"data", s_change_sec
, 'd'},
1024 {"double", s_float_cons
, 'd'},
1025 {"float", s_float_cons
, 'f'},
1026 {"globl", s_mips_globl
, 0},
1027 {"global", s_mips_globl
, 0},
1028 {"hword", s_cons
, 1},
1030 {"long", s_cons
, 2},
1031 {"octa", s_cons
, 4},
1032 {"quad", s_cons
, 3},
1033 {"section", s_change_section
, 0},
1034 {"short", s_cons
, 1},
1035 {"single", s_float_cons
, 'f'},
1036 {"stabn", s_mips_stab
, 'n'},
1037 {"text", s_change_sec
, 't'},
1038 {"word", s_cons
, 2},
1040 { "extern", ecoff_directive_extern
, 0},
1045 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1047 /* These pseudo-ops should be defined by the object file format.
1048 However, a.out doesn't support them, so we have versions here. */
1049 {"aent", s_mips_ent
, 1},
1050 {"bgnb", s_ignore
, 0},
1051 {"end", s_mips_end
, 0},
1052 {"endb", s_ignore
, 0},
1053 {"ent", s_mips_ent
, 0},
1054 {"file", s_mips_file
, 0},
1055 {"fmask", s_mips_mask
, 'F'},
1056 {"frame", s_mips_frame
, 0},
1057 {"loc", s_mips_loc
, 0},
1058 {"mask", s_mips_mask
, 'R'},
1059 {"verstamp", s_ignore
, 0},
1063 extern void pop_insert (const pseudo_typeS
*);
1066 mips_pop_insert (void)
1068 pop_insert (mips_pseudo_table
);
1069 if (! ECOFF_DEBUGGING
)
1070 pop_insert (mips_nonecoff_pseudo_table
);
1073 /* Symbols labelling the current insn. */
1075 struct insn_label_list
1077 struct insn_label_list
*next
;
1081 static struct insn_label_list
*insn_labels
;
1082 static struct insn_label_list
*free_insn_labels
;
1084 static void mips_clear_insn_labels (void);
1087 mips_clear_insn_labels (void)
1089 register struct insn_label_list
**pl
;
1091 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1097 static char *expr_end
;
1099 /* Expressions which appear in instructions. These are set by
1102 static expressionS imm_expr
;
1103 static expressionS imm2_expr
;
1104 static expressionS offset_expr
;
1106 /* Relocs associated with imm_expr and offset_expr. */
1108 static bfd_reloc_code_real_type imm_reloc
[3]
1109 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1110 static bfd_reloc_code_real_type offset_reloc
[3]
1111 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1113 /* These are set by mips16_ip if an explicit extension is used. */
1115 static bfd_boolean mips16_small
, mips16_ext
;
1118 /* The pdr segment for per procedure frame/regmask info. Not used for
1121 static segT pdr_seg
;
1124 /* The default target format to use. */
1127 mips_target_format (void)
1129 switch (OUTPUT_FLAVOR
)
1131 case bfd_target_ecoff_flavour
:
1132 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1133 case bfd_target_coff_flavour
:
1135 case bfd_target_elf_flavour
:
1137 /* This is traditional mips. */
1138 return (target_big_endian
1139 ? (HAVE_64BIT_OBJECTS
1140 ? "elf64-tradbigmips"
1142 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1143 : (HAVE_64BIT_OBJECTS
1144 ? "elf64-tradlittlemips"
1146 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1148 return (target_big_endian
1149 ? (HAVE_64BIT_OBJECTS
1152 ? "elf32-nbigmips" : "elf32-bigmips"))
1153 : (HAVE_64BIT_OBJECTS
1154 ? "elf64-littlemips"
1156 ? "elf32-nlittlemips" : "elf32-littlemips")));
1164 /* Return the length of instruction INSN. */
1166 static inline unsigned int
1167 insn_length (const struct mips_cl_insn
*insn
)
1169 if (!mips_opts
.mips16
)
1171 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1174 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1177 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1182 insn
->use_extend
= FALSE
;
1184 insn
->insn_opcode
= mo
->match
;
1187 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1188 insn
->fixp
[i
] = NULL
;
1189 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1190 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1191 insn
->mips16_absolute_jump_p
= 0;
1194 /* Install INSN at the location specified by its "frag" and "where" fields. */
1197 install_insn (const struct mips_cl_insn
*insn
)
1199 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1200 if (!mips_opts
.mips16
)
1201 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1202 else if (insn
->mips16_absolute_jump_p
)
1204 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1205 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1209 if (insn
->use_extend
)
1211 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1214 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1218 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1219 and install the opcode in the new location. */
1222 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1227 insn
->where
= where
;
1228 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1229 if (insn
->fixp
[i
] != NULL
)
1231 insn
->fixp
[i
]->fx_frag
= frag
;
1232 insn
->fixp
[i
]->fx_where
= where
;
1234 install_insn (insn
);
1237 /* Add INSN to the end of the output. */
1240 add_fixed_insn (struct mips_cl_insn
*insn
)
1242 char *f
= frag_more (insn_length (insn
));
1243 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1246 /* Start a variant frag and move INSN to the start of the variant part,
1247 marking it as fixed. The other arguments are as for frag_var. */
1250 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1251 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1253 frag_grow (max_chars
);
1254 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1256 frag_var (rs_machine_dependent
, max_chars
, var
,
1257 subtype
, symbol
, offset
, NULL
);
1260 /* Insert N copies of INSN into the history buffer, starting at
1261 position FIRST. Neither FIRST nor N need to be clipped. */
1264 insert_into_history (unsigned int first
, unsigned int n
,
1265 const struct mips_cl_insn
*insn
)
1267 if (mips_relax
.sequence
!= 2)
1271 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1273 history
[i
] = history
[i
- n
];
1279 /* Emit a nop instruction, recording it in the history buffer. */
1284 add_fixed_insn (NOP_INSN
);
1285 insert_into_history (0, 1, NOP_INSN
);
1288 /* This function is called once, at assembler startup time. It should
1289 set up all the tables, etc. that the MD part of the assembler will need. */
1294 register const char *retval
= NULL
;
1298 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1299 as_warn (_("Could not set architecture and machine"));
1301 op_hash
= hash_new ();
1303 for (i
= 0; i
< NUMOPCODES
;)
1305 const char *name
= mips_opcodes
[i
].name
;
1307 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1310 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1311 mips_opcodes
[i
].name
, retval
);
1312 /* Probably a memory allocation problem? Give up now. */
1313 as_fatal (_("Broken assembler. No assembly attempted."));
1317 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1319 if (!validate_mips_insn (&mips_opcodes
[i
]))
1321 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1323 create_insn (&nop_insn
, mips_opcodes
+ i
);
1324 nop_insn
.fixed_p
= 1;
1329 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1332 mips16_op_hash
= hash_new ();
1335 while (i
< bfd_mips16_num_opcodes
)
1337 const char *name
= mips16_opcodes
[i
].name
;
1339 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1341 as_fatal (_("internal: can't hash `%s': %s"),
1342 mips16_opcodes
[i
].name
, retval
);
1345 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1346 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1347 != mips16_opcodes
[i
].match
))
1349 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1350 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1353 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1355 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1356 mips16_nop_insn
.fixed_p
= 1;
1360 while (i
< bfd_mips16_num_opcodes
1361 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1365 as_fatal (_("Broken assembler. No assembly attempted."));
1367 /* We add all the general register names to the symbol table. This
1368 helps us detect invalid uses of them. */
1369 for (i
= 0; i
< 32; i
++)
1373 sprintf (buf
, "$%d", i
);
1374 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1375 &zero_address_frag
));
1377 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1378 &zero_address_frag
));
1379 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1380 &zero_address_frag
));
1381 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1382 &zero_address_frag
));
1383 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1384 &zero_address_frag
));
1385 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1386 &zero_address_frag
));
1387 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1388 &zero_address_frag
));
1389 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1390 &zero_address_frag
));
1391 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1392 &zero_address_frag
));
1393 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1394 &zero_address_frag
));
1396 /* If we don't add these register names to the symbol table, they
1397 may end up being added as regular symbols by operand(), and then
1398 make it to the object file as undefined in case they're not
1399 regarded as local symbols. They're local in o32, since `$' is a
1400 local symbol prefix, but not in n32 or n64. */
1401 for (i
= 0; i
< 8; i
++)
1405 sprintf (buf
, "$fcc%i", i
);
1406 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1407 &zero_address_frag
));
1410 mips_no_prev_insn (FALSE
);
1413 mips_cprmask
[0] = 0;
1414 mips_cprmask
[1] = 0;
1415 mips_cprmask
[2] = 0;
1416 mips_cprmask
[3] = 0;
1418 /* set the default alignment for the text section (2**2) */
1419 record_alignment (text_section
, 2);
1421 bfd_set_gp_size (stdoutput
, g_switch_value
);
1423 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1425 /* On a native system, sections must be aligned to 16 byte
1426 boundaries. When configured for an embedded ELF target, we
1428 if (strcmp (TARGET_OS
, "elf") != 0)
1430 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1431 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1432 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1435 /* Create a .reginfo section for register masks and a .mdebug
1436 section for debugging information. */
1444 subseg
= now_subseg
;
1446 /* The ABI says this section should be loaded so that the
1447 running program can access it. However, we don't load it
1448 if we are configured for an embedded target */
1449 flags
= SEC_READONLY
| SEC_DATA
;
1450 if (strcmp (TARGET_OS
, "elf") != 0)
1451 flags
|= SEC_ALLOC
| SEC_LOAD
;
1453 if (mips_abi
!= N64_ABI
)
1455 sec
= subseg_new (".reginfo", (subsegT
) 0);
1457 bfd_set_section_flags (stdoutput
, sec
, flags
);
1458 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1461 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1466 /* The 64-bit ABI uses a .MIPS.options section rather than
1467 .reginfo section. */
1468 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1469 bfd_set_section_flags (stdoutput
, sec
, flags
);
1470 bfd_set_section_alignment (stdoutput
, sec
, 3);
1473 /* Set up the option header. */
1475 Elf_Internal_Options opthdr
;
1478 opthdr
.kind
= ODK_REGINFO
;
1479 opthdr
.size
= (sizeof (Elf_External_Options
)
1480 + sizeof (Elf64_External_RegInfo
));
1483 f
= frag_more (sizeof (Elf_External_Options
));
1484 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1485 (Elf_External_Options
*) f
);
1487 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1492 if (ECOFF_DEBUGGING
)
1494 sec
= subseg_new (".mdebug", (subsegT
) 0);
1495 (void) bfd_set_section_flags (stdoutput
, sec
,
1496 SEC_HAS_CONTENTS
| SEC_READONLY
);
1497 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1500 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1502 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1503 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1504 SEC_READONLY
| SEC_RELOC
1506 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1510 subseg_set (seg
, subseg
);
1514 if (! ECOFF_DEBUGGING
)
1521 if (! ECOFF_DEBUGGING
)
1526 md_assemble (char *str
)
1528 struct mips_cl_insn insn
;
1529 bfd_reloc_code_real_type unused_reloc
[3]
1530 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1532 imm_expr
.X_op
= O_absent
;
1533 imm2_expr
.X_op
= O_absent
;
1534 offset_expr
.X_op
= O_absent
;
1535 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1536 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1537 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1538 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1539 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1540 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1542 if (mips_opts
.mips16
)
1543 mips16_ip (str
, &insn
);
1546 mips_ip (str
, &insn
);
1547 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1548 str
, insn
.insn_opcode
));
1553 as_bad ("%s `%s'", insn_error
, str
);
1557 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1560 if (mips_opts
.mips16
)
1561 mips16_macro (&insn
);
1568 if (imm_expr
.X_op
!= O_absent
)
1569 append_insn (&insn
, &imm_expr
, imm_reloc
);
1570 else if (offset_expr
.X_op
!= O_absent
)
1571 append_insn (&insn
, &offset_expr
, offset_reloc
);
1573 append_insn (&insn
, NULL
, unused_reloc
);
1577 /* Return true if the given relocation might need a matching %lo().
1578 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1579 applied to local symbols. */
1581 static inline bfd_boolean
1582 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1584 return (HAVE_IN_PLACE_ADDENDS
1585 && (reloc
== BFD_RELOC_HI16_S
1586 || reloc
== BFD_RELOC_MIPS_GOT16
1587 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1590 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1593 static inline bfd_boolean
1594 fixup_has_matching_lo_p (fixS
*fixp
)
1596 return (fixp
->fx_next
!= NULL
1597 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1598 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1599 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1600 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1603 /* See whether instruction IP reads register REG. CLASS is the type
1607 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1608 enum mips_regclass
class)
1610 if (class == MIPS16_REG
)
1612 assert (mips_opts
.mips16
);
1613 reg
= mips16_to_32_reg_map
[reg
];
1614 class = MIPS_GR_REG
;
1617 /* Don't report on general register ZERO, since it never changes. */
1618 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1621 if (class == MIPS_FP_REG
)
1623 assert (! mips_opts
.mips16
);
1624 /* If we are called with either $f0 or $f1, we must check $f0.
1625 This is not optimal, because it will introduce an unnecessary
1626 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1627 need to distinguish reading both $f0 and $f1 or just one of
1628 them. Note that we don't have to check the other way,
1629 because there is no instruction that sets both $f0 and $f1
1630 and requires a delay. */
1631 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1632 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1633 == (reg
&~ (unsigned) 1)))
1635 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1636 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1637 == (reg
&~ (unsigned) 1)))
1640 else if (! mips_opts
.mips16
)
1642 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1643 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1645 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1646 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1651 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1652 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1654 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1655 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1657 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1658 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1661 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1663 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1665 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1667 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1668 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1675 /* This function returns true if modifying a register requires a
1679 reg_needs_delay (unsigned int reg
)
1681 unsigned long prev_pinfo
;
1683 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1684 if (! mips_opts
.noreorder
1685 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1686 && ! gpr_interlocks
)
1687 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1688 && ! cop_interlocks
)))
1690 /* A load from a coprocessor or from memory. All load delays
1691 delay the use of general register rt for one instruction. */
1692 /* Itbl support may require additional care here. */
1693 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1694 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1701 /* Mark instruction labels in mips16 mode. This permits the linker to
1702 handle them specially, such as generating jalx instructions when
1703 needed. We also make them odd for the duration of the assembly, in
1704 order to generate the right sort of code. We will make them even
1705 in the adjust_symtab routine, while leaving them marked. This is
1706 convenient for the debugger and the disassembler. The linker knows
1707 to make them odd again. */
1710 mips16_mark_labels (void)
1712 if (mips_opts
.mips16
)
1714 struct insn_label_list
*l
;
1717 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1720 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1721 S_SET_OTHER (l
->label
, STO_MIPS16
);
1723 val
= S_GET_VALUE (l
->label
);
1725 S_SET_VALUE (l
->label
, val
+ 1);
1730 /* End the current frag. Make it a variant frag and record the
1734 relax_close_frag (void)
1736 mips_macro_warning
.first_frag
= frag_now
;
1737 frag_var (rs_machine_dependent
, 0, 0,
1738 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1739 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1741 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1742 mips_relax
.first_fixup
= 0;
1745 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1746 See the comment above RELAX_ENCODE for more details. */
1749 relax_start (symbolS
*symbol
)
1751 assert (mips_relax
.sequence
== 0);
1752 mips_relax
.sequence
= 1;
1753 mips_relax
.symbol
= symbol
;
1756 /* Start generating the second version of a relaxable sequence.
1757 See the comment above RELAX_ENCODE for more details. */
1762 assert (mips_relax
.sequence
== 1);
1763 mips_relax
.sequence
= 2;
1766 /* End the current relaxable sequence. */
1771 assert (mips_relax
.sequence
== 2);
1772 relax_close_frag ();
1773 mips_relax
.sequence
= 0;
1776 /* Output an instruction. IP is the instruction information.
1777 ADDRESS_EXPR is an operand of the instruction to be used with
1781 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1782 bfd_reloc_code_real_type
*reloc_type
)
1784 register unsigned long prev_pinfo
, pinfo
;
1786 relax_stateT prev_insn_frag_type
= 0;
1787 bfd_boolean relaxed_branch
= FALSE
;
1789 /* Mark instruction labels in mips16 mode. */
1790 mips16_mark_labels ();
1792 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1793 pinfo
= ip
->insn_mo
->pinfo
;
1795 if (mips_relax
.sequence
!= 2
1796 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1800 /* If the previous insn required any delay slots, see if we need
1801 to insert a NOP or two. There are eight kinds of possible
1802 hazards, of which an instruction can have at most one type.
1803 (1) a load from memory delay
1804 (2) a load from a coprocessor delay
1805 (3) an unconditional branch delay
1806 (4) a conditional branch delay
1807 (5) a move to coprocessor register delay
1808 (6) a load coprocessor register from memory delay
1809 (7) a coprocessor condition code delay
1810 (8) a HI/LO special register delay
1812 There are a lot of optimizations we could do that we don't.
1813 In particular, we do not, in general, reorder instructions.
1814 If you use gcc with optimization, it will reorder
1815 instructions and generally do much more optimization then we
1816 do here; repeating all that work in the assembler would only
1817 benefit hand written assembly code, and does not seem worth
1820 /* The previous insn might require a delay slot, depending upon
1821 the contents of the current insn. */
1822 if (! mips_opts
.mips16
1823 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1824 && ! gpr_interlocks
)
1825 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1826 && ! cop_interlocks
)))
1828 /* A load from a coprocessor or from memory. All load
1829 delays delay the use of general register rt for one
1831 /* Itbl support may require additional care here. */
1832 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1833 if (mips_optimize
== 0
1834 || insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
1838 else if (! mips_opts
.mips16
1839 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1840 && ! cop_interlocks
)
1841 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1842 && ! cop_mem_interlocks
)))
1844 /* A generic coprocessor delay. The previous instruction
1845 modified a coprocessor general or control register. If
1846 it modified a control register, we need to avoid any
1847 coprocessor instruction (this is probably not always
1848 required, but it sometimes is). If it modified a general
1849 register, we avoid using that register.
1851 This case is not handled very well. There is no special
1852 knowledge of CP0 handling, and the coprocessors other
1853 than the floating point unit are not distinguished at
1855 /* Itbl support may require additional care here. FIXME!
1856 Need to modify this to include knowledge about
1857 user specified delays! */
1858 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1860 if (mips_optimize
== 0
1861 || insn_uses_reg (ip
, EXTRACT_OPERAND (FT
, history
[0]),
1865 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1867 if (mips_optimize
== 0
1868 || insn_uses_reg (ip
, EXTRACT_OPERAND (FS
, history
[0]),
1874 /* We don't know exactly what the previous instruction
1875 does. If the current instruction uses a coprocessor
1876 register, we must insert a NOP. If previous
1877 instruction may set the condition codes, and the
1878 current instruction uses them, we must insert two
1880 /* Itbl support may require additional care here. */
1881 if (mips_optimize
== 0
1882 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1883 && (pinfo
& INSN_READ_COND_CODE
)))
1885 else if (pinfo
& INSN_COP
)
1889 else if (! mips_opts
.mips16
1890 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1891 && ! cop_interlocks
)
1893 /* The previous instruction sets the coprocessor condition
1894 codes, but does not require a general coprocessor delay
1895 (this means it is a floating point comparison
1896 instruction). If this instruction uses the condition
1897 codes, we need to insert a single NOP. */
1898 /* Itbl support may require additional care here. */
1899 if (mips_optimize
== 0
1900 || (pinfo
& INSN_READ_COND_CODE
))
1904 /* If we're fixing up mfhi/mflo for the r7000 and the
1905 previous insn was an mfhi/mflo and the current insn
1906 reads the register that the mfhi/mflo wrote to, then
1909 else if (mips_7000_hilo_fix
1910 && MF_HILO_INSN (prev_pinfo
)
1911 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
1917 /* If we're fixing up mfhi/mflo for the r7000 and the
1918 2nd previous insn was an mfhi/mflo and the current insn
1919 reads the register that the mfhi/mflo wrote to, then
1922 else if (mips_7000_hilo_fix
1923 && MF_HILO_INSN (history
[1].insn_opcode
)
1924 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[1]),
1931 else if (prev_pinfo
& INSN_READ_LO
)
1933 /* The previous instruction reads the LO register; if the
1934 current instruction writes to the LO register, we must
1935 insert two NOPS. Some newer processors have interlocks.
1936 Also the tx39's multiply instructions can be executed
1937 immediately after a read from HI/LO (without the delay),
1938 though the tx39's divide insns still do require the
1940 if (! (hilo_interlocks
1941 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1942 && (mips_optimize
== 0
1943 || (pinfo
& INSN_WRITE_LO
)))
1945 /* Most mips16 branch insns don't have a delay slot.
1946 If a read from LO is immediately followed by a branch
1947 to a write to LO we have a read followed by a write
1948 less than 2 insns away. We assume the target of
1949 a branch might be a write to LO, and insert a nop
1950 between a read and an immediately following branch. */
1951 else if (mips_opts
.mips16
1952 && (mips_optimize
== 0
1953 || (pinfo
& MIPS16_INSN_BRANCH
)))
1956 else if (history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
1958 /* The previous instruction reads the HI register; if the
1959 current instruction writes to the HI register, we must
1960 insert a NOP. Some newer processors have interlocks.
1961 Also the note tx39's multiply above. */
1962 if (! (hilo_interlocks
1963 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1964 && (mips_optimize
== 0
1965 || (pinfo
& INSN_WRITE_HI
)))
1967 /* Most mips16 branch insns don't have a delay slot.
1968 If a read from HI is immediately followed by a branch
1969 to a write to HI we have a read followed by a write
1970 less than 2 insns away. We assume the target of
1971 a branch might be a write to HI, and insert a nop
1972 between a read and an immediately following branch. */
1973 else if (mips_opts
.mips16
1974 && (mips_optimize
== 0
1975 || (pinfo
& MIPS16_INSN_BRANCH
)))
1979 /* If the previous instruction was in a noreorder section, then
1980 we don't want to insert the nop after all. */
1981 /* Itbl support may require additional care here. */
1982 if (history
[0].noreorder_p
)
1985 /* There are two cases which require two intervening
1986 instructions: 1) setting the condition codes using a move to
1987 coprocessor instruction which requires a general coprocessor
1988 delay and then reading the condition codes 2) reading the HI
1989 or LO register and then writing to it (except on processors
1990 which have interlocks). If we are not already emitting a NOP
1991 instruction, we must check for these cases compared to the
1992 instruction previous to the previous instruction. */
1993 if ((! mips_opts
.mips16
1994 && (history
[1].insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1995 && (history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1996 && (pinfo
& INSN_READ_COND_CODE
)
1997 && ! cop_interlocks
)
1998 || ((history
[1].insn_mo
->pinfo
& INSN_READ_LO
)
1999 && (pinfo
& INSN_WRITE_LO
)
2000 && ! (hilo_interlocks
2001 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
2002 || ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
2003 && (pinfo
& INSN_WRITE_HI
)
2004 && ! (hilo_interlocks
2005 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
2010 if (history
[1].noreorder_p
)
2013 if (prev_prev_nop
&& nops
== 0)
2016 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
2018 /* We're out of bits in pinfo, so we must resort to string
2019 ops here. Shortcuts are selected based on opcodes being
2020 limited to the VR4120 instruction set. */
2022 const char *pn
= history
[0].insn_mo
->name
;
2023 const char *tn
= ip
->insn_mo
->name
;
2024 if (strncmp (pn
, "macc", 4) == 0
2025 || strncmp (pn
, "dmacc", 5) == 0)
2027 /* Errata 21 - [D]DIV[U] after [D]MACC */
2028 if (strstr (tn
, "div"))
2031 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2032 instruction is executed immediately after a MACC or
2033 DMACC instruction, the result of [either instruction]
2035 if (strncmp (tn
, "mult", 4) == 0
2036 || strncmp (tn
, "dmult", 5) == 0)
2039 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
2040 Applies on top of VR4181A MD(1) errata. */
2041 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
2044 /* Errata 24 - MT{LO,HI} after [D]MACC */
2045 if (strcmp (tn
, "mtlo") == 0
2046 || strcmp (tn
, "mthi") == 0)
2049 else if (strncmp (pn
, "dmult", 5) == 0
2050 && (strncmp (tn
, "dmult", 5) == 0
2051 || strncmp (tn
, "dmacc", 5) == 0))
2053 /* Here is the rest of errata 23. */
2056 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
2057 && (strncmp (tn
, "macc", 4) == 0
2058 || strncmp (tn
, "dmacc", 5) == 0))
2060 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2061 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2062 DDIV or DDIVU instruction, the result of the MACC or
2063 DMACC instruction is incorrect.". This partly overlaps
2064 the workaround for errata 23. */
2067 if (nops
< min_nops
)
2071 /* If we are being given a nop instruction, don't bother with
2072 one of the nops we would otherwise output. This will only
2073 happen when a nop instruction is used with mips_optimize set
2076 && ! mips_opts
.noreorder
2077 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
2080 /* Now emit the right number of NOP instructions. */
2081 if (nops
> 0 && ! mips_opts
.noreorder
)
2084 unsigned long old_frag_offset
;
2086 struct insn_label_list
*l
;
2088 old_frag
= frag_now
;
2089 old_frag_offset
= frag_now_fix ();
2091 for (i
= 0; i
< nops
; i
++)
2096 listing_prev_line ();
2097 /* We may be at the start of a variant frag. In case we
2098 are, make sure there is enough space for the frag
2099 after the frags created by listing_prev_line. The
2100 argument to frag_grow here must be at least as large
2101 as the argument to all other calls to frag_grow in
2102 this file. We don't have to worry about being in the
2103 middle of a variant frag, because the variants insert
2104 all needed nop instructions themselves. */
2108 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2112 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2113 symbol_set_frag (l
->label
, frag_now
);
2114 val
= (valueT
) frag_now_fix ();
2115 /* mips16 text labels are stored as odd. */
2116 if (mips_opts
.mips16
)
2118 S_SET_VALUE (l
->label
, val
);
2121 #ifndef NO_ECOFF_DEBUGGING
2122 if (ECOFF_DEBUGGING
)
2123 ecoff_fix_loc (old_frag
, old_frag_offset
);
2126 else if (prev_nop_frag
!= NULL
)
2128 /* We have a frag holding nops we may be able to remove. If
2129 we don't need any nops, we can decrease the size of
2130 prev_nop_frag by the size of one instruction. If we do
2131 need some nops, we count them in prev_nops_required. */
2132 if (prev_nop_frag_since
== 0)
2136 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2137 --prev_nop_frag_holds
;
2140 prev_nop_frag_required
+= nops
;
2144 if (prev_prev_nop
== 0)
2146 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2147 --prev_nop_frag_holds
;
2150 ++prev_nop_frag_required
;
2153 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2154 prev_nop_frag
= NULL
;
2156 ++prev_nop_frag_since
;
2158 /* Sanity check: by the time we reach the second instruction
2159 after prev_nop_frag, we should have used up all the nops
2160 one way or another. */
2161 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2166 /* The value passed to dwarf2_emit_insn is the distance between
2167 the beginning of the current instruction and the address that
2168 should be recorded in the debug tables. For MIPS16 debug info
2169 we want to use ISA-encoded addresses, so we pass -1 for an
2170 address higher by one than the current. */
2171 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2174 /* Record the frag type before frag_var. */
2175 if (history
[0].frag
)
2176 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2179 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2180 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2181 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2182 && mips_relax_branch
2183 /* Don't try branch relaxation within .set nomacro, or within
2184 .set noat if we use $at for PIC computations. If it turns
2185 out that the branch was out-of-range, we'll get an error. */
2186 && !mips_opts
.warn_about_macros
2187 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2188 && !mips_opts
.mips16
)
2190 relaxed_branch
= TRUE
;
2191 add_relaxed_insn (ip
, (relaxed_branch_length
2193 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2194 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2197 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2198 pinfo
& INSN_COND_BRANCH_LIKELY
,
2199 pinfo
& INSN_WRITE_GPR_31
,
2201 address_expr
->X_add_symbol
,
2202 address_expr
->X_add_number
);
2203 *reloc_type
= BFD_RELOC_UNUSED
;
2205 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2207 /* We need to set up a variant frag. */
2208 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2209 add_relaxed_insn (ip
, 4, 0,
2211 (*reloc_type
- BFD_RELOC_UNUSED
,
2212 mips16_small
, mips16_ext
,
2213 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2214 history
[0].mips16_absolute_jump_p
),
2215 make_expr_symbol (address_expr
), 0);
2217 else if (mips_opts
.mips16
2219 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2221 /* Make sure there is enough room to swap this instruction with
2222 a following jump instruction. */
2224 add_fixed_insn (ip
);
2228 if (mips_opts
.mips16
2229 && mips_opts
.noreorder
2230 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2231 as_warn (_("extended instruction in delay slot"));
2233 if (mips_relax
.sequence
)
2235 /* If we've reached the end of this frag, turn it into a variant
2236 frag and record the information for the instructions we've
2238 if (frag_room () < 4)
2239 relax_close_frag ();
2240 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2243 if (mips_relax
.sequence
!= 2)
2244 mips_macro_warning
.sizes
[0] += 4;
2245 if (mips_relax
.sequence
!= 1)
2246 mips_macro_warning
.sizes
[1] += 4;
2248 if (mips_opts
.mips16
)
2251 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2253 add_fixed_insn (ip
);
2256 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2258 if (address_expr
->X_op
== O_constant
)
2262 switch (*reloc_type
)
2265 ip
->insn_opcode
|= address_expr
->X_add_number
;
2268 case BFD_RELOC_MIPS_HIGHEST
:
2269 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2270 ip
->insn_opcode
|= tmp
& 0xffff;
2273 case BFD_RELOC_MIPS_HIGHER
:
2274 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2275 ip
->insn_opcode
|= tmp
& 0xffff;
2278 case BFD_RELOC_HI16_S
:
2279 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2280 ip
->insn_opcode
|= tmp
& 0xffff;
2283 case BFD_RELOC_HI16
:
2284 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2287 case BFD_RELOC_UNUSED
:
2288 case BFD_RELOC_LO16
:
2289 case BFD_RELOC_MIPS_GOT_DISP
:
2290 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2293 case BFD_RELOC_MIPS_JMP
:
2294 if ((address_expr
->X_add_number
& 3) != 0)
2295 as_bad (_("jump to misaligned address (0x%lx)"),
2296 (unsigned long) address_expr
->X_add_number
);
2297 if (address_expr
->X_add_number
& ~0xfffffff)
2298 as_bad (_("jump address range overflow (0x%lx)"),
2299 (unsigned long) address_expr
->X_add_number
);
2300 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2303 case BFD_RELOC_MIPS16_JMP
:
2304 if ((address_expr
->X_add_number
& 3) != 0)
2305 as_bad (_("jump to misaligned address (0x%lx)"),
2306 (unsigned long) address_expr
->X_add_number
);
2307 if (address_expr
->X_add_number
& ~0xfffffff)
2308 as_bad (_("jump address range overflow (0x%lx)"),
2309 (unsigned long) address_expr
->X_add_number
);
2311 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2312 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2313 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2316 case BFD_RELOC_16_PCREL_S2
:
2323 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2326 reloc_howto_type
*howto
;
2329 /* In a compound relocation, it is the final (outermost)
2330 operator that determines the relocated field. */
2331 for (i
= 1; i
< 3; i
++)
2332 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2335 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2336 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2337 bfd_get_reloc_size (howto
),
2339 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2342 /* These relocations can have an addend that won't fit in
2343 4 octets for 64bit assembly. */
2345 && ! howto
->partial_inplace
2346 && (reloc_type
[0] == BFD_RELOC_16
2347 || reloc_type
[0] == BFD_RELOC_32
2348 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2349 || reloc_type
[0] == BFD_RELOC_HI16_S
2350 || reloc_type
[0] == BFD_RELOC_LO16
2351 || reloc_type
[0] == BFD_RELOC_GPREL16
2352 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2353 || reloc_type
[0] == BFD_RELOC_GPREL32
2354 || reloc_type
[0] == BFD_RELOC_64
2355 || reloc_type
[0] == BFD_RELOC_CTOR
2356 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2357 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2358 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2359 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2360 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2361 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2362 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2363 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2364 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2365 ip
->fixp
[0]->fx_no_overflow
= 1;
2367 if (mips_relax
.sequence
)
2369 if (mips_relax
.first_fixup
== 0)
2370 mips_relax
.first_fixup
= ip
->fixp
[0];
2372 else if (reloc_needs_lo_p (*reloc_type
))
2374 struct mips_hi_fixup
*hi_fixup
;
2376 /* Reuse the last entry if it already has a matching %lo. */
2377 hi_fixup
= mips_hi_fixup_list
;
2379 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2381 hi_fixup
= ((struct mips_hi_fixup
*)
2382 xmalloc (sizeof (struct mips_hi_fixup
)));
2383 hi_fixup
->next
= mips_hi_fixup_list
;
2384 mips_hi_fixup_list
= hi_fixup
;
2386 hi_fixup
->fixp
= ip
->fixp
[0];
2387 hi_fixup
->seg
= now_seg
;
2390 /* Add fixups for the second and third relocations, if given.
2391 Note that the ABI allows the second relocation to be
2392 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2393 moment we only use RSS_UNDEF, but we could add support
2394 for the others if it ever becomes necessary. */
2395 for (i
= 1; i
< 3; i
++)
2396 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2398 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2399 ip
->fixp
[0]->fx_size
, NULL
, 0,
2400 FALSE
, reloc_type
[i
]);
2402 /* Use fx_tcbit to mark compound relocs. */
2403 ip
->fixp
[0]->fx_tcbit
= 1;
2404 ip
->fixp
[i
]->fx_tcbit
= 1;
2410 /* Update the register mask information. */
2411 if (! mips_opts
.mips16
)
2413 if (pinfo
& INSN_WRITE_GPR_D
)
2414 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2415 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2416 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2417 if (pinfo
& INSN_READ_GPR_S
)
2418 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2419 if (pinfo
& INSN_WRITE_GPR_31
)
2420 mips_gprmask
|= 1 << RA
;
2421 if (pinfo
& INSN_WRITE_FPR_D
)
2422 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2423 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2424 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2425 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2426 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2427 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2428 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2429 if (pinfo
& INSN_COP
)
2431 /* We don't keep enough information to sort these cases out.
2432 The itbl support does keep this information however, although
2433 we currently don't support itbl fprmats as part of the cop
2434 instruction. May want to add this support in the future. */
2436 /* Never set the bit for $0, which is always zero. */
2437 mips_gprmask
&= ~1 << 0;
2441 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2442 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2443 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2444 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2445 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2446 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2447 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2448 mips_gprmask
|= 1 << TREG
;
2449 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2450 mips_gprmask
|= 1 << SP
;
2451 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2452 mips_gprmask
|= 1 << RA
;
2453 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2454 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2455 if (pinfo
& MIPS16_INSN_READ_Z
)
2456 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2457 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2458 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2461 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2463 /* Filling the branch delay slot is more complex. We try to
2464 switch the branch with the previous instruction, which we can
2465 do if the previous instruction does not set up a condition
2466 that the branch tests and if the branch is not itself the
2467 target of any branch. */
2468 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2469 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2471 if (mips_optimize
< 2
2472 /* If we have seen .set volatile or .set nomove, don't
2474 || mips_opts
.nomove
!= 0
2475 /* If we had to emit any NOP instructions, then we
2476 already know we can not swap. */
2478 /* We can't swap if the previous instruction's position
2480 || history
[0].fixed_p
2481 /* If the previous previous insn was in a .set
2482 noreorder, we can't swap. Actually, the MIPS
2483 assembler will swap in this situation. However, gcc
2484 configured -with-gnu-as will generate code like
2490 in which we can not swap the bne and INSN. If gcc is
2491 not configured -with-gnu-as, it does not output the
2493 || history
[1].noreorder_p
2494 /* If the branch is itself the target of a branch, we
2495 can not swap. We cheat on this; all we check for is
2496 whether there is a label on this instruction. If
2497 there are any branches to anything other than a
2498 label, users must use .set noreorder. */
2499 || insn_labels
!= NULL
2500 /* If the previous instruction is in a variant frag
2501 other than this branch's one, we cannot do the swap.
2502 This does not apply to the mips16, which uses variant
2503 frags for different purposes. */
2504 || (! mips_opts
.mips16
2505 && prev_insn_frag_type
== rs_machine_dependent
)
2506 /* If the branch reads the condition codes, we don't
2507 even try to swap, because in the sequence
2512 we can not swap, and I don't feel like handling that
2514 || (! mips_opts
.mips16
2515 && (pinfo
& INSN_READ_COND_CODE
)
2516 && ! cop_interlocks
)
2517 /* We can not swap with an instruction that requires a
2518 delay slot, because the target of the branch might
2519 interfere with that instruction. */
2520 || (! mips_opts
.mips16
2522 /* Itbl support may require additional care here. */
2523 & (INSN_LOAD_COPROC_DELAY
2524 | INSN_COPROC_MOVE_DELAY
2525 | INSN_WRITE_COND_CODE
))
2526 && ! cop_interlocks
)
2527 || (! (hilo_interlocks
2528 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2532 || (! mips_opts
.mips16
2533 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2534 && ! gpr_interlocks
)
2535 || (! mips_opts
.mips16
2536 /* Itbl support may require additional care here. */
2537 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2538 && ! cop_mem_interlocks
)
2539 /* We can not swap with a branch instruction. */
2541 & (INSN_UNCOND_BRANCH_DELAY
2542 | INSN_COND_BRANCH_DELAY
2543 | INSN_COND_BRANCH_LIKELY
))
2544 /* We do not swap with a trap instruction, since it
2545 complicates trap handlers to have the trap
2546 instruction be in a delay slot. */
2547 || (prev_pinfo
& INSN_TRAP
)
2548 /* If the branch reads a register that the previous
2549 instruction sets, we can not swap. */
2550 || (! mips_opts
.mips16
2551 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2552 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2554 || (! mips_opts
.mips16
2555 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2556 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2558 || (mips_opts
.mips16
2559 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2561 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2563 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2565 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2567 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2569 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2571 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2572 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2573 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2574 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2575 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2576 && insn_uses_reg (ip
,
2577 MIPS16OP_EXTRACT_REG32R
2578 (history
[0].insn_opcode
),
2580 /* If the branch writes a register that the previous
2581 instruction sets, we can not swap (we know that
2582 branches write only to RD or to $31). */
2583 || (! mips_opts
.mips16
2584 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2585 && (((pinfo
& INSN_WRITE_GPR_D
)
2586 && (EXTRACT_OPERAND (RT
, history
[0])
2587 == EXTRACT_OPERAND (RD
, *ip
)))
2588 || ((pinfo
& INSN_WRITE_GPR_31
)
2589 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2590 || (! mips_opts
.mips16
2591 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2592 && (((pinfo
& INSN_WRITE_GPR_D
)
2593 && (EXTRACT_OPERAND (RD
, history
[0])
2594 == EXTRACT_OPERAND (RD
, *ip
)))
2595 || ((pinfo
& INSN_WRITE_GPR_31
)
2596 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2597 || (mips_opts
.mips16
2598 && (pinfo
& MIPS16_INSN_WRITE_31
)
2599 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2600 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2601 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2603 /* If the branch writes a register that the previous
2604 instruction reads, we can not swap (we know that
2605 branches only write to RD or to $31). */
2606 || (! mips_opts
.mips16
2607 && (pinfo
& INSN_WRITE_GPR_D
)
2608 && insn_uses_reg (&history
[0],
2609 EXTRACT_OPERAND (RD
, *ip
),
2611 || (! mips_opts
.mips16
2612 && (pinfo
& INSN_WRITE_GPR_31
)
2613 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2614 || (mips_opts
.mips16
2615 && (pinfo
& MIPS16_INSN_WRITE_31
)
2616 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2617 /* If the previous previous instruction has a load
2618 delay, and sets a register that the branch reads, we
2620 || (! mips_opts
.mips16
2621 /* Itbl support may require additional care here. */
2622 && (((history
[1].insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2623 && ! cop_interlocks
)
2624 || ((history
[1].insn_mo
->pinfo
2625 & INSN_LOAD_MEMORY_DELAY
)
2626 && ! gpr_interlocks
))
2627 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[1]),
2629 /* If one instruction sets a condition code and the
2630 other one uses a condition code, we can not swap. */
2631 || ((pinfo
& INSN_READ_COND_CODE
)
2632 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2633 || ((pinfo
& INSN_WRITE_COND_CODE
)
2634 && (prev_pinfo
& INSN_READ_COND_CODE
))
2635 /* If the previous instruction uses the PC, we can not
2637 || (mips_opts
.mips16
2638 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2639 /* If the previous instruction had a fixup in mips16
2640 mode, we can not swap. This normally means that the
2641 previous instruction was a 4 byte branch anyhow. */
2642 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2643 /* If the previous instruction is a sync, sync.l, or
2644 sync.p, we can not swap. */
2645 || (prev_pinfo
& INSN_SYNC
))
2647 /* We could do even better for unconditional branches to
2648 portions of this object file; we could pick up the
2649 instruction at the destination, put it in the delay
2650 slot, and bump the destination address. */
2651 insert_into_history (0, 1, ip
);
2653 if (mips_relax
.sequence
)
2654 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2658 /* It looks like we can actually do the swap. */
2659 struct mips_cl_insn delay
= history
[0];
2660 if (mips_opts
.mips16
)
2662 know (delay
.frag
== ip
->frag
);
2663 move_insn (ip
, delay
.frag
, delay
.where
);
2664 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2666 else if (relaxed_branch
)
2668 /* Add the delay slot instruction to the end of the
2669 current frag and shrink the fixed part of the
2670 original frag. If the branch occupies the tail of
2671 the latter, move it backwards to cover the gap. */
2672 delay
.frag
->fr_fix
-= 4;
2673 if (delay
.frag
== ip
->frag
)
2674 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2675 add_fixed_insn (&delay
);
2679 move_insn (&delay
, ip
->frag
, ip
->where
);
2680 move_insn (ip
, history
[0].frag
, history
[0].where
);
2684 insert_into_history (0, 1, &delay
);
2687 /* If that was an unconditional branch, forget the previous
2688 insn information. */
2689 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2690 mips_no_prev_insn (FALSE
);
2692 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2694 /* We don't yet optimize a branch likely. What we should do
2695 is look at the target, copy the instruction found there
2696 into the delay slot, and increment the branch to jump to
2697 the next instruction. */
2698 insert_into_history (0, 1, ip
);
2702 insert_into_history (0, 1, ip
);
2705 insert_into_history (0, 1, ip
);
2707 /* We just output an insn, so the next one doesn't have a label. */
2708 mips_clear_insn_labels ();
2711 /* This function forgets that there was any previous instruction or
2712 label. If PRESERVE is non-zero, it remembers enough information to
2713 know whether nops are needed before a noreorder section. */
2716 mips_no_prev_insn (int preserve
)
2722 prev_nop_frag
= NULL
;
2723 prev_nop_frag_holds
= 0;
2724 prev_nop_frag_required
= 0;
2725 prev_nop_frag_since
= 0;
2726 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2727 history
[i
] = (mips_opts
.mips16
? mips16_nop_insn
: nop_insn
);
2730 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2732 history
[i
].fixed_p
= 1;
2733 history
[i
].noreorder_p
= 0;
2734 history
[i
].mips16_absolute_jump_p
= 0;
2736 mips_clear_insn_labels ();
2739 /* This function must be called whenever we turn on noreorder or emit
2740 something other than instructions. It inserts any NOPS which might
2741 be needed by the previous instruction, and clears the information
2742 kept for the previous instructions. The INSNS parameter is true if
2743 instructions are to follow. */
2746 mips_emit_delays (bfd_boolean insns
)
2748 if (! mips_opts
.noreorder
)
2753 if ((! mips_opts
.mips16
2754 && ((history
[0].insn_mo
->pinfo
2755 & (INSN_LOAD_COPROC_DELAY
2756 | INSN_COPROC_MOVE_DELAY
2757 | INSN_WRITE_COND_CODE
))
2758 && ! cop_interlocks
))
2759 || (! hilo_interlocks
2760 && (history
[0].insn_mo
->pinfo
2763 || (! mips_opts
.mips16
2764 && (history
[0].insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2765 && ! gpr_interlocks
)
2766 || (! mips_opts
.mips16
2767 && (history
[0].insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2768 && ! cop_mem_interlocks
))
2770 /* Itbl support may require additional care here. */
2772 if ((! mips_opts
.mips16
2773 && ((history
[0].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2774 && ! cop_interlocks
))
2775 || (! hilo_interlocks
2776 && ((history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
2777 || (history
[0].insn_mo
->pinfo
& INSN_READ_LO
))))
2780 if (history
[0].noreorder_p
)
2783 else if ((! mips_opts
.mips16
2784 && ((history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2785 && ! cop_interlocks
))
2786 || (! hilo_interlocks
2787 && ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
2788 || (history
[1].insn_mo
->pinfo
& INSN_READ_LO
))))
2790 /* Itbl support may require additional care here. */
2791 if (! history
[1].noreorder_p
)
2795 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
2798 const char *pn
= history
[0].insn_mo
->name
;
2799 if (strncmp (pn
, "macc", 4) == 0
2800 || strncmp (pn
, "dmacc", 5) == 0
2801 || strncmp (pn
, "dmult", 5) == 0
2802 || strstr (pn
, "div"))
2804 if (nops
< min_nops
)
2810 struct insn_label_list
*l
;
2814 /* Record the frag which holds the nop instructions, so
2815 that we can remove them if we don't need them. */
2816 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2817 prev_nop_frag
= frag_now
;
2818 prev_nop_frag_holds
= nops
;
2819 prev_nop_frag_required
= 0;
2820 prev_nop_frag_since
= 0;
2823 for (; nops
> 0; --nops
)
2824 add_fixed_insn (NOP_INSN
);
2828 /* Move on to a new frag, so that it is safe to simply
2829 decrease the size of prev_nop_frag. */
2830 frag_wane (frag_now
);
2834 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2838 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2839 symbol_set_frag (l
->label
, frag_now
);
2840 val
= (valueT
) frag_now_fix ();
2841 /* mips16 text labels are stored as odd. */
2842 if (mips_opts
.mips16
)
2844 S_SET_VALUE (l
->label
, val
);
2849 /* Mark instruction labels in mips16 mode. */
2851 mips16_mark_labels ();
2853 mips_no_prev_insn (insns
);
2856 /* Set up global variables for the start of a new macro. */
2861 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2862 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2863 && (history
[0].insn_mo
->pinfo
2864 & (INSN_UNCOND_BRANCH_DELAY
2865 | INSN_COND_BRANCH_DELAY
2866 | INSN_COND_BRANCH_LIKELY
)) != 0);
2869 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2870 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2871 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2874 macro_warning (relax_substateT subtype
)
2876 if (subtype
& RELAX_DELAY_SLOT
)
2877 return _("Macro instruction expanded into multiple instructions"
2878 " in a branch delay slot");
2879 else if (subtype
& RELAX_NOMACRO
)
2880 return _("Macro instruction expanded into multiple instructions");
2885 /* Finish up a macro. Emit warnings as appropriate. */
2890 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2892 relax_substateT subtype
;
2894 /* Set up the relaxation warning flags. */
2896 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2897 subtype
|= RELAX_SECOND_LONGER
;
2898 if (mips_opts
.warn_about_macros
)
2899 subtype
|= RELAX_NOMACRO
;
2900 if (mips_macro_warning
.delay_slot_p
)
2901 subtype
|= RELAX_DELAY_SLOT
;
2903 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2905 /* Either the macro has a single implementation or both
2906 implementations are longer than 4 bytes. Emit the
2908 const char *msg
= macro_warning (subtype
);
2914 /* One implementation might need a warning but the other
2915 definitely doesn't. */
2916 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2921 /* Read a macro's relocation codes from *ARGS and store them in *R.
2922 The first argument in *ARGS will be either the code for a single
2923 relocation or -1 followed by the three codes that make up a
2924 composite relocation. */
2927 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2931 next
= va_arg (*args
, int);
2933 r
[0] = (bfd_reloc_code_real_type
) next
;
2935 for (i
= 0; i
< 3; i
++)
2936 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2939 /* Build an instruction created by a macro expansion. This is passed
2940 a pointer to the count of instructions created so far, an
2941 expression, the name of the instruction to build, an operand format
2942 string, and corresponding arguments. */
2945 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2947 const struct mips_opcode
*mo
;
2948 struct mips_cl_insn insn
;
2949 bfd_reloc_code_real_type r
[3];
2952 va_start (args
, fmt
);
2954 if (mips_opts
.mips16
)
2956 mips16_macro_build (ep
, name
, fmt
, args
);
2961 r
[0] = BFD_RELOC_UNUSED
;
2962 r
[1] = BFD_RELOC_UNUSED
;
2963 r
[2] = BFD_RELOC_UNUSED
;
2964 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2966 assert (strcmp (name
, mo
->name
) == 0);
2968 /* Search until we get a match for NAME. It is assumed here that
2969 macros will never generate MDMX or MIPS-3D instructions. */
2970 while (strcmp (fmt
, mo
->args
) != 0
2971 || mo
->pinfo
== INSN_MACRO
2972 || !OPCODE_IS_MEMBER (mo
,
2974 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2976 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2980 assert (strcmp (name
, mo
->name
) == 0);
2983 create_insn (&insn
, mo
);
3001 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3006 /* Note that in the macro case, these arguments are already
3007 in MSB form. (When handling the instruction in the
3008 non-macro case, these arguments are sizes from which
3009 MSB values must be calculated.) */
3010 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3016 /* Note that in the macro case, these arguments are already
3017 in MSBD form. (When handling the instruction in the
3018 non-macro case, these arguments are sizes from which
3019 MSBD values must be calculated.) */
3020 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3031 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3035 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3040 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3046 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3051 int tmp
= va_arg (args
, int);
3053 INSERT_OPERAND (RT
, insn
, tmp
);
3054 INSERT_OPERAND (RD
, insn
, tmp
);
3060 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3067 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3071 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3075 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3079 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3083 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3090 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3096 macro_read_relocs (&args
, r
);
3097 assert (*r
== BFD_RELOC_GPREL16
3098 || *r
== BFD_RELOC_MIPS_LITERAL
3099 || *r
== BFD_RELOC_MIPS_HIGHER
3100 || *r
== BFD_RELOC_HI16_S
3101 || *r
== BFD_RELOC_LO16
3102 || *r
== BFD_RELOC_MIPS_GOT16
3103 || *r
== BFD_RELOC_MIPS_CALL16
3104 || *r
== BFD_RELOC_MIPS_GOT_DISP
3105 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3106 || *r
== BFD_RELOC_MIPS_GOT_OFST
3107 || *r
== BFD_RELOC_MIPS_GOT_LO16
3108 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3112 macro_read_relocs (&args
, r
);
3114 && (ep
->X_op
== O_constant
3115 || (ep
->X_op
== O_symbol
3116 && (*r
== BFD_RELOC_MIPS_HIGHEST
3117 || *r
== BFD_RELOC_HI16_S
3118 || *r
== BFD_RELOC_HI16
3119 || *r
== BFD_RELOC_GPREL16
3120 || *r
== BFD_RELOC_MIPS_GOT_HI16
3121 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3125 assert (ep
!= NULL
);
3127 * This allows macro() to pass an immediate expression for
3128 * creating short branches without creating a symbol.
3129 * Note that the expression still might come from the assembly
3130 * input, in which case the value is not checked for range nor
3131 * is a relocation entry generated (yuck).
3133 if (ep
->X_op
== O_constant
)
3135 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3139 *r
= BFD_RELOC_16_PCREL_S2
;
3143 assert (ep
!= NULL
);
3144 *r
= BFD_RELOC_MIPS_JMP
;
3148 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3157 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3159 append_insn (&insn
, ep
, r
);
3163 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3166 struct mips_opcode
*mo
;
3167 struct mips_cl_insn insn
;
3168 bfd_reloc_code_real_type r
[3]
3169 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3171 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3173 assert (strcmp (name
, mo
->name
) == 0);
3175 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3179 assert (strcmp (name
, mo
->name
) == 0);
3182 create_insn (&insn
, mo
);
3200 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3205 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3209 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3213 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3223 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3230 regno
= va_arg (args
, int);
3231 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3232 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3253 assert (ep
!= NULL
);
3255 if (ep
->X_op
!= O_constant
)
3256 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3259 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3260 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3263 *r
= BFD_RELOC_UNUSED
;
3269 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3276 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3278 append_insn (&insn
, ep
, r
);
3282 * Generate a "jalr" instruction with a relocation hint to the called
3283 * function. This occurs in NewABI PIC code.
3286 macro_build_jalr (expressionS
*ep
)
3295 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3297 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3298 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3302 * Generate a "lui" instruction.
3305 macro_build_lui (expressionS
*ep
, int regnum
)
3307 expressionS high_expr
;
3308 const struct mips_opcode
*mo
;
3309 struct mips_cl_insn insn
;
3310 bfd_reloc_code_real_type r
[3]
3311 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3312 const char *name
= "lui";
3313 const char *fmt
= "t,u";
3315 assert (! mips_opts
.mips16
);
3319 if (high_expr
.X_op
== O_constant
)
3321 /* we can compute the instruction now without a relocation entry */
3322 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3324 *r
= BFD_RELOC_UNUSED
;
3328 assert (ep
->X_op
== O_symbol
);
3329 /* _gp_disp is a special case, used from s_cpload.
3330 __gnu_local_gp is used if mips_no_shared. */
3331 assert (mips_pic
== NO_PIC
3333 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3334 || (! mips_in_shared
3335 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3336 "__gnu_local_gp") == 0));
3337 *r
= BFD_RELOC_HI16_S
;
3340 mo
= hash_find (op_hash
, name
);
3341 assert (strcmp (name
, mo
->name
) == 0);
3342 assert (strcmp (fmt
, mo
->args
) == 0);
3343 create_insn (&insn
, mo
);
3345 insn
.insn_opcode
= insn
.insn_mo
->match
;
3346 INSERT_OPERAND (RT
, insn
, regnum
);
3347 if (*r
== BFD_RELOC_UNUSED
)
3349 insn
.insn_opcode
|= high_expr
.X_add_number
;
3350 append_insn (&insn
, NULL
, r
);
3353 append_insn (&insn
, &high_expr
, r
);
3356 /* Generate a sequence of instructions to do a load or store from a constant
3357 offset off of a base register (breg) into/from a target register (treg),
3358 using AT if necessary. */
3360 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3361 int treg
, int breg
, int dbl
)
3363 assert (ep
->X_op
== O_constant
);
3365 /* Sign-extending 32-bit constants makes their handling easier. */
3366 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3367 == ~((bfd_vma
) 0x7fffffff)))
3369 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3370 as_bad (_("constant too large"));
3372 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3376 /* Right now, this routine can only handle signed 32-bit constants. */
3377 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3378 as_warn (_("operand overflow"));
3380 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3382 /* Signed 16-bit offset will fit in the op. Easy! */
3383 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3387 /* 32-bit offset, need multiple instructions and AT, like:
3388 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3389 addu $tempreg,$tempreg,$breg
3390 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3391 to handle the complete offset. */
3392 macro_build_lui (ep
, AT
);
3393 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3394 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3397 as_bad (_("Macro used $at after \".set noat\""));
3402 * Generates code to set the $at register to true (one)
3403 * if reg is less than the immediate expression.
3406 set_at (int reg
, int unsignedp
)
3408 if (imm_expr
.X_op
== O_constant
3409 && imm_expr
.X_add_number
>= -0x8000
3410 && imm_expr
.X_add_number
< 0x8000)
3411 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3412 AT
, reg
, BFD_RELOC_LO16
);
3415 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3416 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3421 normalize_constant_expr (expressionS
*ex
)
3423 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3424 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3428 /* Warn if an expression is not a constant. */
3431 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3433 if (ex
->X_op
== O_big
)
3434 as_bad (_("unsupported large constant"));
3435 else if (ex
->X_op
!= O_constant
)
3436 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3438 normalize_constant_expr (ex
);
3441 /* Count the leading zeroes by performing a binary chop. This is a
3442 bulky bit of source, but performance is a LOT better for the
3443 majority of values than a simple loop to count the bits:
3444 for (lcnt = 0; (lcnt < 32); lcnt++)
3445 if ((v) & (1 << (31 - lcnt)))
3447 However it is not code size friendly, and the gain will drop a bit
3448 on certain cached systems.
3450 #define COUNT_TOP_ZEROES(v) \
3451 (((v) & ~0xffff) == 0 \
3452 ? ((v) & ~0xff) == 0 \
3453 ? ((v) & ~0xf) == 0 \
3454 ? ((v) & ~0x3) == 0 \
3455 ? ((v) & ~0x1) == 0 \
3460 : ((v) & ~0x7) == 0 \
3463 : ((v) & ~0x3f) == 0 \
3464 ? ((v) & ~0x1f) == 0 \
3467 : ((v) & ~0x7f) == 0 \
3470 : ((v) & ~0xfff) == 0 \
3471 ? ((v) & ~0x3ff) == 0 \
3472 ? ((v) & ~0x1ff) == 0 \
3475 : ((v) & ~0x7ff) == 0 \
3478 : ((v) & ~0x3fff) == 0 \
3479 ? ((v) & ~0x1fff) == 0 \
3482 : ((v) & ~0x7fff) == 0 \
3485 : ((v) & ~0xffffff) == 0 \
3486 ? ((v) & ~0xfffff) == 0 \
3487 ? ((v) & ~0x3ffff) == 0 \
3488 ? ((v) & ~0x1ffff) == 0 \
3491 : ((v) & ~0x7ffff) == 0 \
3494 : ((v) & ~0x3fffff) == 0 \
3495 ? ((v) & ~0x1fffff) == 0 \
3498 : ((v) & ~0x7fffff) == 0 \
3501 : ((v) & ~0xfffffff) == 0 \
3502 ? ((v) & ~0x3ffffff) == 0 \
3503 ? ((v) & ~0x1ffffff) == 0 \
3506 : ((v) & ~0x7ffffff) == 0 \
3509 : ((v) & ~0x3fffffff) == 0 \
3510 ? ((v) & ~0x1fffffff) == 0 \
3513 : ((v) & ~0x7fffffff) == 0 \
3518 * This routine generates the least number of instructions necessary to load
3519 * an absolute expression value into a register.
3522 load_register (int reg
, expressionS
*ep
, int dbl
)
3525 expressionS hi32
, lo32
;
3527 if (ep
->X_op
!= O_big
)
3529 assert (ep
->X_op
== O_constant
);
3531 /* Sign-extending 32-bit constants makes their handling easier. */
3532 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3533 == ~((bfd_vma
) 0x7fffffff)))
3535 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3536 as_bad (_("constant too large"));
3538 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3542 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3544 /* We can handle 16 bit signed values with an addiu to
3545 $zero. No need to ever use daddiu here, since $zero and
3546 the result are always correct in 32 bit mode. */
3547 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3550 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3552 /* We can handle 16 bit unsigned values with an ori to
3554 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3557 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3559 /* 32 bit values require an lui. */
3560 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3561 if ((ep
->X_add_number
& 0xffff) != 0)
3562 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3567 /* The value is larger than 32 bits. */
3569 if (HAVE_32BIT_GPRS
)
3571 as_bad (_("Number (0x%lx) larger than 32 bits"),
3572 (unsigned long) ep
->X_add_number
);
3573 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3577 if (ep
->X_op
!= O_big
)
3580 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3581 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3582 hi32
.X_add_number
&= 0xffffffff;
3584 lo32
.X_add_number
&= 0xffffffff;
3588 assert (ep
->X_add_number
> 2);
3589 if (ep
->X_add_number
== 3)
3590 generic_bignum
[3] = 0;
3591 else if (ep
->X_add_number
> 4)
3592 as_bad (_("Number larger than 64 bits"));
3593 lo32
.X_op
= O_constant
;
3594 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3595 hi32
.X_op
= O_constant
;
3596 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3599 if (hi32
.X_add_number
== 0)
3604 unsigned long hi
, lo
;
3606 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3608 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3610 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3613 if (lo32
.X_add_number
& 0x80000000)
3615 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3616 if (lo32
.X_add_number
& 0xffff)
3617 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3622 /* Check for 16bit shifted constant. We know that hi32 is
3623 non-zero, so start the mask on the first bit of the hi32
3628 unsigned long himask
, lomask
;
3632 himask
= 0xffff >> (32 - shift
);
3633 lomask
= (0xffff << shift
) & 0xffffffff;
3637 himask
= 0xffff << (shift
- 32);
3640 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3641 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3645 tmp
.X_op
= O_constant
;
3647 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3648 | (lo32
.X_add_number
>> shift
));
3650 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3651 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3652 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3653 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3658 while (shift
<= (64 - 16));
3660 /* Find the bit number of the lowest one bit, and store the
3661 shifted value in hi/lo. */
3662 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3663 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3667 while ((lo
& 1) == 0)
3672 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3678 while ((hi
& 1) == 0)
3687 /* Optimize if the shifted value is a (power of 2) - 1. */
3688 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3689 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3691 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3696 /* This instruction will set the register to be all
3698 tmp
.X_op
= O_constant
;
3699 tmp
.X_add_number
= (offsetT
) -1;
3700 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3704 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3705 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3707 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3708 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3713 /* Sign extend hi32 before calling load_register, because we can
3714 generally get better code when we load a sign extended value. */
3715 if ((hi32
.X_add_number
& 0x80000000) != 0)
3716 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3717 load_register (reg
, &hi32
, 0);
3720 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3724 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3732 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3734 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3735 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3741 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3745 mid16
.X_add_number
>>= 16;
3746 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3747 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3750 if ((lo32
.X_add_number
& 0xffff) != 0)
3751 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3755 load_delay_nop (void)
3757 if (!gpr_interlocks
)
3758 macro_build (NULL
, "nop", "");
3761 /* Load an address into a register. */
3764 load_address (int reg
, expressionS
*ep
, int *used_at
)
3766 if (ep
->X_op
!= O_constant
3767 && ep
->X_op
!= O_symbol
)
3769 as_bad (_("expression too complex"));
3770 ep
->X_op
= O_constant
;
3773 if (ep
->X_op
== O_constant
)
3775 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3779 if (mips_pic
== NO_PIC
)
3781 /* If this is a reference to a GP relative symbol, we want
3782 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3784 lui $reg,<sym> (BFD_RELOC_HI16_S)
3785 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3786 If we have an addend, we always use the latter form.
3788 With 64bit address space and a usable $at we want
3789 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3790 lui $at,<sym> (BFD_RELOC_HI16_S)
3791 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3792 daddiu $at,<sym> (BFD_RELOC_LO16)
3796 If $at is already in use, we use a path which is suboptimal
3797 on superscalar processors.
3798 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3799 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3801 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3803 daddiu $reg,<sym> (BFD_RELOC_LO16)
3805 For GP relative symbols in 64bit address space we can use
3806 the same sequence as in 32bit address space. */
3807 if (HAVE_64BIT_SYMBOLS
)
3809 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3810 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3812 relax_start (ep
->X_add_symbol
);
3813 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3814 mips_gp_register
, BFD_RELOC_GPREL16
);
3818 if (*used_at
== 0 && !mips_opts
.noat
)
3820 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3821 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3822 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3823 BFD_RELOC_MIPS_HIGHER
);
3824 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3825 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3826 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3831 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3832 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3833 BFD_RELOC_MIPS_HIGHER
);
3834 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3835 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3836 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3837 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3840 if (mips_relax
.sequence
)
3845 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3846 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3848 relax_start (ep
->X_add_symbol
);
3849 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3850 mips_gp_register
, BFD_RELOC_GPREL16
);
3853 macro_build_lui (ep
, reg
);
3854 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3855 reg
, reg
, BFD_RELOC_LO16
);
3856 if (mips_relax
.sequence
)
3860 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3864 /* If this is a reference to an external symbol, we want
3865 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3867 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3869 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3870 If there is a constant, it must be added in after.
3872 If we have NewABI, we want
3873 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3874 unless we're referencing a global symbol with a non-zero
3875 offset, in which case cst must be added separately. */
3878 if (ep
->X_add_number
)
3880 ex
.X_add_number
= ep
->X_add_number
;
3881 ep
->X_add_number
= 0;
3882 relax_start (ep
->X_add_symbol
);
3883 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3884 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3885 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3886 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3887 ex
.X_op
= O_constant
;
3888 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3889 reg
, reg
, BFD_RELOC_LO16
);
3890 ep
->X_add_number
= ex
.X_add_number
;
3893 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3894 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3895 if (mips_relax
.sequence
)
3900 ex
.X_add_number
= ep
->X_add_number
;
3901 ep
->X_add_number
= 0;
3902 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3903 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3905 relax_start (ep
->X_add_symbol
);
3907 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3911 if (ex
.X_add_number
!= 0)
3913 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3914 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3915 ex
.X_op
= O_constant
;
3916 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3917 reg
, reg
, BFD_RELOC_LO16
);
3921 else if (mips_pic
== SVR4_PIC
)
3925 /* This is the large GOT case. If this is a reference to an
3926 external symbol, we want
3927 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3929 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3931 Otherwise, for a reference to a local symbol in old ABI, we want
3932 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3934 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3935 If there is a constant, it must be added in after.
3937 In the NewABI, for local symbols, with or without offsets, we want:
3938 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3939 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3943 ex
.X_add_number
= ep
->X_add_number
;
3944 ep
->X_add_number
= 0;
3945 relax_start (ep
->X_add_symbol
);
3946 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3947 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3948 reg
, reg
, mips_gp_register
);
3949 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3950 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3951 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3952 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3953 else if (ex
.X_add_number
)
3955 ex
.X_op
= O_constant
;
3956 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3960 ep
->X_add_number
= ex
.X_add_number
;
3962 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3963 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3964 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3965 BFD_RELOC_MIPS_GOT_OFST
);
3970 ex
.X_add_number
= ep
->X_add_number
;
3971 ep
->X_add_number
= 0;
3972 relax_start (ep
->X_add_symbol
);
3973 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3974 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3975 reg
, reg
, mips_gp_register
);
3976 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3977 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3979 if (reg_needs_delay (mips_gp_register
))
3981 /* We need a nop before loading from $gp. This special
3982 check is required because the lui which starts the main
3983 instruction stream does not refer to $gp, and so will not
3984 insert the nop which may be required. */
3985 macro_build (NULL
, "nop", "");
3987 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3988 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3990 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3994 if (ex
.X_add_number
!= 0)
3996 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3997 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3998 ex
.X_op
= O_constant
;
3999 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4007 if (mips_opts
.noat
&& *used_at
== 1)
4008 as_bad (_("Macro used $at after \".set noat\""));
4011 /* Move the contents of register SOURCE into register DEST. */
4014 move_register (int dest
, int source
)
4016 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4020 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4021 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4022 The two alternatives are:
4024 Global symbol Local sybmol
4025 ------------- ------------
4026 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4028 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4030 load_got_offset emits the first instruction and add_got_offset
4031 emits the second for a 16-bit offset or add_got_offset_hilo emits
4032 a sequence to add a 32-bit offset using a scratch register. */
4035 load_got_offset (int dest
, expressionS
*local
)
4040 global
.X_add_number
= 0;
4042 relax_start (local
->X_add_symbol
);
4043 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4044 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4046 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4047 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4052 add_got_offset (int dest
, expressionS
*local
)
4056 global
.X_op
= O_constant
;
4057 global
.X_op_symbol
= NULL
;
4058 global
.X_add_symbol
= NULL
;
4059 global
.X_add_number
= local
->X_add_number
;
4061 relax_start (local
->X_add_symbol
);
4062 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4063 dest
, dest
, BFD_RELOC_LO16
);
4065 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4070 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4073 int hold_mips_optimize
;
4075 global
.X_op
= O_constant
;
4076 global
.X_op_symbol
= NULL
;
4077 global
.X_add_symbol
= NULL
;
4078 global
.X_add_number
= local
->X_add_number
;
4080 relax_start (local
->X_add_symbol
);
4081 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4083 /* Set mips_optimize around the lui instruction to avoid
4084 inserting an unnecessary nop after the lw. */
4085 hold_mips_optimize
= mips_optimize
;
4087 macro_build_lui (&global
, tmp
);
4088 mips_optimize
= hold_mips_optimize
;
4089 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4092 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4097 * This routine implements the seemingly endless macro or synthesized
4098 * instructions and addressing modes in the mips assembly language. Many
4099 * of these macros are simple and are similar to each other. These could
4100 * probably be handled by some kind of table or grammar approach instead of
4101 * this verbose method. Others are not simple macros but are more like
4102 * optimizing code generation.
4103 * One interesting optimization is when several store macros appear
4104 * consecutively that would load AT with the upper half of the same address.
4105 * The ensuing load upper instructions are ommited. This implies some kind
4106 * of global optimization. We currently only optimize within a single macro.
4107 * For many of the load and store macros if the address is specified as a
4108 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4109 * first load register 'at' with zero and use it as the base register. The
4110 * mips assembler simply uses register $zero. Just one tiny optimization
4114 macro (struct mips_cl_insn
*ip
)
4116 register int treg
, sreg
, dreg
, breg
;
4132 bfd_reloc_code_real_type r
;
4133 int hold_mips_optimize
;
4135 assert (! mips_opts
.mips16
);
4137 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4138 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4139 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4140 mask
= ip
->insn_mo
->mask
;
4142 expr1
.X_op
= O_constant
;
4143 expr1
.X_op_symbol
= NULL
;
4144 expr1
.X_add_symbol
= NULL
;
4145 expr1
.X_add_number
= 1;
4157 mips_emit_delays (TRUE
);
4158 ++mips_opts
.noreorder
;
4159 mips_any_noreorder
= 1;
4161 expr1
.X_add_number
= 8;
4162 macro_build (&expr1
, "bgez", "s,p", sreg
);
4164 macro_build (NULL
, "nop", "", 0);
4166 move_register (dreg
, sreg
);
4167 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4169 --mips_opts
.noreorder
;
4190 if (imm_expr
.X_op
== O_constant
4191 && imm_expr
.X_add_number
>= -0x8000
4192 && imm_expr
.X_add_number
< 0x8000)
4194 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4198 load_register (AT
, &imm_expr
, dbl
);
4199 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4218 if (imm_expr
.X_op
== O_constant
4219 && imm_expr
.X_add_number
>= 0
4220 && imm_expr
.X_add_number
< 0x10000)
4222 if (mask
!= M_NOR_I
)
4223 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4226 macro_build (&imm_expr
, "ori", "t,r,i",
4227 treg
, sreg
, BFD_RELOC_LO16
);
4228 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4234 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4235 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4252 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4254 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4258 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4259 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4267 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4272 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4276 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4277 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4283 /* check for > max integer */
4284 maxnum
= 0x7fffffff;
4285 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4292 if (imm_expr
.X_op
== O_constant
4293 && imm_expr
.X_add_number
>= maxnum
4294 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4297 /* result is always false */
4299 macro_build (NULL
, "nop", "", 0);
4301 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4304 if (imm_expr
.X_op
!= O_constant
)
4305 as_bad (_("Unsupported large constant"));
4306 ++imm_expr
.X_add_number
;
4310 if (mask
== M_BGEL_I
)
4312 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4314 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4317 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4319 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4322 maxnum
= 0x7fffffff;
4323 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4330 maxnum
= - maxnum
- 1;
4331 if (imm_expr
.X_op
== O_constant
4332 && imm_expr
.X_add_number
<= maxnum
4333 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4336 /* result is always true */
4337 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4338 macro_build (&offset_expr
, "b", "p");
4343 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4353 macro_build (&offset_expr
, likely
? "beql" : "beq",
4358 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4359 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4367 && imm_expr
.X_op
== O_constant
4368 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4370 if (imm_expr
.X_op
!= O_constant
)
4371 as_bad (_("Unsupported large constant"));
4372 ++imm_expr
.X_add_number
;
4376 if (mask
== M_BGEUL_I
)
4378 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4380 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4382 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4388 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4396 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4401 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4405 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4406 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4414 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4421 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4422 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4430 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4435 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4439 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4440 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4446 maxnum
= 0x7fffffff;
4447 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4454 if (imm_expr
.X_op
== O_constant
4455 && imm_expr
.X_add_number
>= maxnum
4456 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4458 if (imm_expr
.X_op
!= O_constant
)
4459 as_bad (_("Unsupported large constant"));
4460 ++imm_expr
.X_add_number
;
4464 if (mask
== M_BLTL_I
)
4466 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4468 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4471 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4473 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4478 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4486 macro_build (&offset_expr
, likely
? "beql" : "beq",
4493 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4494 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4502 && imm_expr
.X_op
== O_constant
4503 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4505 if (imm_expr
.X_op
!= O_constant
)
4506 as_bad (_("Unsupported large constant"));
4507 ++imm_expr
.X_add_number
;
4511 if (mask
== M_BLTUL_I
)
4513 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4515 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4517 macro_build (&offset_expr
, likely
? "beql" : "beq",
4523 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4531 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4536 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4540 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4541 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4551 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4556 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4557 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4565 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4567 as_bad (_("Unsupported large constant"));
4572 pos
= (unsigned long) imm_expr
.X_add_number
;
4573 size
= (unsigned long) imm2_expr
.X_add_number
;
4578 as_bad (_("Improper position (%lu)"), pos
);
4581 if (size
== 0 || size
> 64
4582 || (pos
+ size
- 1) > 63)
4584 as_bad (_("Improper extract size (%lu, position %lu)"),
4589 if (size
<= 32 && pos
< 32)
4594 else if (size
<= 32)
4604 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4613 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4615 as_bad (_("Unsupported large constant"));
4620 pos
= (unsigned long) imm_expr
.X_add_number
;
4621 size
= (unsigned long) imm2_expr
.X_add_number
;
4626 as_bad (_("Improper position (%lu)"), pos
);
4629 if (size
== 0 || size
> 64
4630 || (pos
+ size
- 1) > 63)
4632 as_bad (_("Improper insert size (%lu, position %lu)"),
4637 if (pos
< 32 && (pos
+ size
- 1) < 32)
4652 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4669 as_warn (_("Divide by zero."));
4671 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4673 macro_build (NULL
, "break", "c", 7);
4677 mips_emit_delays (TRUE
);
4678 ++mips_opts
.noreorder
;
4679 mips_any_noreorder
= 1;
4682 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4683 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4687 expr1
.X_add_number
= 8;
4688 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4689 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4690 macro_build (NULL
, "break", "c", 7);
4692 expr1
.X_add_number
= -1;
4694 load_register (AT
, &expr1
, dbl
);
4695 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4696 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4699 expr1
.X_add_number
= 1;
4700 load_register (AT
, &expr1
, dbl
);
4701 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4705 expr1
.X_add_number
= 0x80000000;
4706 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4710 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4711 /* We want to close the noreorder block as soon as possible, so
4712 that later insns are available for delay slot filling. */
4713 --mips_opts
.noreorder
;
4717 expr1
.X_add_number
= 8;
4718 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4719 macro_build (NULL
, "nop", "", 0);
4721 /* We want to close the noreorder block as soon as possible, so
4722 that later insns are available for delay slot filling. */
4723 --mips_opts
.noreorder
;
4725 macro_build (NULL
, "break", "c", 6);
4727 macro_build (NULL
, s
, "d", dreg
);
4766 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4768 as_warn (_("Divide by zero."));
4770 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4772 macro_build (NULL
, "break", "c", 7);
4775 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4777 if (strcmp (s2
, "mflo") == 0)
4778 move_register (dreg
, sreg
);
4780 move_register (dreg
, 0);
4783 if (imm_expr
.X_op
== O_constant
4784 && imm_expr
.X_add_number
== -1
4785 && s
[strlen (s
) - 1] != 'u')
4787 if (strcmp (s2
, "mflo") == 0)
4789 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4792 move_register (dreg
, 0);
4797 load_register (AT
, &imm_expr
, dbl
);
4798 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4799 macro_build (NULL
, s2
, "d", dreg
);
4818 mips_emit_delays (TRUE
);
4819 ++mips_opts
.noreorder
;
4820 mips_any_noreorder
= 1;
4823 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4824 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4825 /* We want to close the noreorder block as soon as possible, so
4826 that later insns are available for delay slot filling. */
4827 --mips_opts
.noreorder
;
4831 expr1
.X_add_number
= 8;
4832 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4833 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4835 /* We want to close the noreorder block as soon as possible, so
4836 that later insns are available for delay slot filling. */
4837 --mips_opts
.noreorder
;
4838 macro_build (NULL
, "break", "c", 7);
4840 macro_build (NULL
, s2
, "d", dreg
);
4852 /* Load the address of a symbol into a register. If breg is not
4853 zero, we then add a base register to it. */
4855 if (dbl
&& HAVE_32BIT_GPRS
)
4856 as_warn (_("dla used to load 32-bit register"));
4858 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4859 as_warn (_("la used to load 64-bit address"));
4861 if (offset_expr
.X_op
== O_constant
4862 && offset_expr
.X_add_number
>= -0x8000
4863 && offset_expr
.X_add_number
< 0x8000)
4865 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4866 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4870 if (!mips_opts
.noat
&& (treg
== breg
))
4880 if (offset_expr
.X_op
!= O_symbol
4881 && offset_expr
.X_op
!= O_constant
)
4883 as_bad (_("expression too complex"));
4884 offset_expr
.X_op
= O_constant
;
4887 if (offset_expr
.X_op
== O_constant
)
4888 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4889 else if (mips_pic
== NO_PIC
)
4891 /* If this is a reference to a GP relative symbol, we want
4892 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4894 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4895 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4896 If we have a constant, we need two instructions anyhow,
4897 so we may as well always use the latter form.
4899 With 64bit address space and a usable $at we want
4900 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4901 lui $at,<sym> (BFD_RELOC_HI16_S)
4902 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4903 daddiu $at,<sym> (BFD_RELOC_LO16)
4905 daddu $tempreg,$tempreg,$at
4907 If $at is already in use, we use a path which is suboptimal
4908 on superscalar processors.
4909 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4910 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4912 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4914 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4916 For GP relative symbols in 64bit address space we can use
4917 the same sequence as in 32bit address space. */
4918 if (HAVE_64BIT_SYMBOLS
)
4920 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4921 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4923 relax_start (offset_expr
.X_add_symbol
);
4924 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4925 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4929 if (used_at
== 0 && !mips_opts
.noat
)
4931 macro_build (&offset_expr
, "lui", "t,u",
4932 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4933 macro_build (&offset_expr
, "lui", "t,u",
4934 AT
, BFD_RELOC_HI16_S
);
4935 macro_build (&offset_expr
, "daddiu", "t,r,j",
4936 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4937 macro_build (&offset_expr
, "daddiu", "t,r,j",
4938 AT
, AT
, BFD_RELOC_LO16
);
4939 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4940 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4945 macro_build (&offset_expr
, "lui", "t,u",
4946 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4947 macro_build (&offset_expr
, "daddiu", "t,r,j",
4948 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4949 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4950 macro_build (&offset_expr
, "daddiu", "t,r,j",
4951 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4952 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4953 macro_build (&offset_expr
, "daddiu", "t,r,j",
4954 tempreg
, tempreg
, BFD_RELOC_LO16
);
4957 if (mips_relax
.sequence
)
4962 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4963 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4965 relax_start (offset_expr
.X_add_symbol
);
4966 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4967 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4970 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4971 as_bad (_("offset too large"));
4972 macro_build_lui (&offset_expr
, tempreg
);
4973 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4974 tempreg
, tempreg
, BFD_RELOC_LO16
);
4975 if (mips_relax
.sequence
)
4979 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4981 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4983 /* If this is a reference to an external symbol, and there
4984 is no constant, we want
4985 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4986 or for lca or if tempreg is PIC_CALL_REG
4987 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4988 For a local symbol, we want
4989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4991 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4993 If we have a small constant, and this is a reference to
4994 an external symbol, we want
4995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4997 addiu $tempreg,$tempreg,<constant>
4998 For a local symbol, we want the same instruction
4999 sequence, but we output a BFD_RELOC_LO16 reloc on the
5002 If we have a large constant, and this is a reference to
5003 an external symbol, we want
5004 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5005 lui $at,<hiconstant>
5006 addiu $at,$at,<loconstant>
5007 addu $tempreg,$tempreg,$at
5008 For a local symbol, we want the same instruction
5009 sequence, but we output a BFD_RELOC_LO16 reloc on the
5013 if (offset_expr
.X_add_number
== 0)
5015 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5016 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5018 relax_start (offset_expr
.X_add_symbol
);
5019 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5020 lw_reloc_type
, mips_gp_register
);
5023 /* We're going to put in an addu instruction using
5024 tempreg, so we may as well insert the nop right
5029 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5030 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5032 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5033 tempreg
, tempreg
, BFD_RELOC_LO16
);
5035 /* FIXME: If breg == 0, and the next instruction uses
5036 $tempreg, then if this variant case is used an extra
5037 nop will be generated. */
5039 else if (offset_expr
.X_add_number
>= -0x8000
5040 && offset_expr
.X_add_number
< 0x8000)
5042 load_got_offset (tempreg
, &offset_expr
);
5044 add_got_offset (tempreg
, &offset_expr
);
5048 expr1
.X_add_number
= offset_expr
.X_add_number
;
5049 offset_expr
.X_add_number
=
5050 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5051 load_got_offset (tempreg
, &offset_expr
);
5052 offset_expr
.X_add_number
= expr1
.X_add_number
;
5053 /* If we are going to add in a base register, and the
5054 target register and the base register are the same,
5055 then we are using AT as a temporary register. Since
5056 we want to load the constant into AT, we add our
5057 current AT (from the global offset table) and the
5058 register into the register now, and pretend we were
5059 not using a base register. */
5063 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5068 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5072 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5074 int add_breg_early
= 0;
5076 /* If this is a reference to an external, and there is no
5077 constant, or local symbol (*), with or without a
5079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5080 or for lca or if tempreg is PIC_CALL_REG
5081 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5083 If we have a small constant, and this is a reference to
5084 an external symbol, we want
5085 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5086 addiu $tempreg,$tempreg,<constant>
5088 If we have a large constant, and this is a reference to
5089 an external symbol, we want
5090 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5091 lui $at,<hiconstant>
5092 addiu $at,$at,<loconstant>
5093 addu $tempreg,$tempreg,$at
5095 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5096 local symbols, even though it introduces an additional
5099 if (offset_expr
.X_add_number
)
5101 expr1
.X_add_number
= offset_expr
.X_add_number
;
5102 offset_expr
.X_add_number
= 0;
5104 relax_start (offset_expr
.X_add_symbol
);
5105 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5106 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5108 if (expr1
.X_add_number
>= -0x8000
5109 && expr1
.X_add_number
< 0x8000)
5111 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5112 tempreg
, tempreg
, BFD_RELOC_LO16
);
5114 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5118 /* If we are going to add in a base register, and the
5119 target register and the base register are the same,
5120 then we are using AT as a temporary register. Since
5121 we want to load the constant into AT, we add our
5122 current AT (from the global offset table) and the
5123 register into the register now, and pretend we were
5124 not using a base register. */
5129 assert (tempreg
== AT
);
5130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5136 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5137 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5143 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5146 offset_expr
.X_add_number
= expr1
.X_add_number
;
5148 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5149 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5152 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5153 treg
, tempreg
, breg
);
5159 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5161 relax_start (offset_expr
.X_add_symbol
);
5162 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5163 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5165 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5166 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5171 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5172 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5175 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5178 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5179 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5180 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5182 /* This is the large GOT case. If this is a reference to an
5183 external symbol, and there is no constant, we want
5184 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5185 addu $tempreg,$tempreg,$gp
5186 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5187 or for lca or if tempreg is PIC_CALL_REG
5188 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5189 addu $tempreg,$tempreg,$gp
5190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5191 For a local symbol, we want
5192 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5194 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5196 If we have a small constant, and this is a reference to
5197 an external symbol, we want
5198 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5199 addu $tempreg,$tempreg,$gp
5200 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5202 addiu $tempreg,$tempreg,<constant>
5203 For a local symbol, we want
5204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5206 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5208 If we have a large constant, and this is a reference to
5209 an external symbol, we want
5210 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5211 addu $tempreg,$tempreg,$gp
5212 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5213 lui $at,<hiconstant>
5214 addiu $at,$at,<loconstant>
5215 addu $tempreg,$tempreg,$at
5216 For a local symbol, we want
5217 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5218 lui $at,<hiconstant>
5219 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5220 addu $tempreg,$tempreg,$at
5223 expr1
.X_add_number
= offset_expr
.X_add_number
;
5224 offset_expr
.X_add_number
= 0;
5225 relax_start (offset_expr
.X_add_symbol
);
5226 gpdelay
= reg_needs_delay (mips_gp_register
);
5227 if (expr1
.X_add_number
== 0 && breg
== 0
5228 && (call
|| tempreg
== PIC_CALL_REG
))
5230 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5231 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5233 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5234 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5235 tempreg
, tempreg
, mips_gp_register
);
5236 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5237 tempreg
, lw_reloc_type
, tempreg
);
5238 if (expr1
.X_add_number
== 0)
5242 /* We're going to put in an addu instruction using
5243 tempreg, so we may as well insert the nop right
5248 else if (expr1
.X_add_number
>= -0x8000
5249 && expr1
.X_add_number
< 0x8000)
5252 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5253 tempreg
, tempreg
, BFD_RELOC_LO16
);
5259 /* If we are going to add in a base register, and the
5260 target register and the base register are the same,
5261 then we are using AT as a temporary register. Since
5262 we want to load the constant into AT, we add our
5263 current AT (from the global offset table) and the
5264 register into the register now, and pretend we were
5265 not using a base register. */
5270 assert (tempreg
== AT
);
5272 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5277 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5278 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5282 offset_expr
.X_add_number
=
5283 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5288 /* This is needed because this instruction uses $gp, but
5289 the first instruction on the main stream does not. */
5290 macro_build (NULL
, "nop", "");
5293 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5294 local_reloc_type
, mips_gp_register
);
5295 if (expr1
.X_add_number
>= -0x8000
5296 && expr1
.X_add_number
< 0x8000)
5299 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5300 tempreg
, tempreg
, BFD_RELOC_LO16
);
5301 /* FIXME: If add_number is 0, and there was no base
5302 register, the external symbol case ended with a load,
5303 so if the symbol turns out to not be external, and
5304 the next instruction uses tempreg, an unnecessary nop
5305 will be inserted. */
5311 /* We must add in the base register now, as in the
5312 external symbol case. */
5313 assert (tempreg
== AT
);
5315 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5318 /* We set breg to 0 because we have arranged to add
5319 it in in both cases. */
5323 macro_build_lui (&expr1
, AT
);
5324 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5325 AT
, AT
, BFD_RELOC_LO16
);
5326 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5327 tempreg
, tempreg
, AT
);
5332 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5334 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5335 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5336 int add_breg_early
= 0;
5338 /* This is the large GOT case. If this is a reference to an
5339 external symbol, and there is no constant, we want
5340 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5341 add $tempreg,$tempreg,$gp
5342 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5343 or for lca or if tempreg is PIC_CALL_REG
5344 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5345 add $tempreg,$tempreg,$gp
5346 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5348 If we have a small constant, and this is a reference to
5349 an external symbol, we want
5350 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5351 add $tempreg,$tempreg,$gp
5352 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5353 addi $tempreg,$tempreg,<constant>
5355 If we have a large constant, and this is a reference to
5356 an external symbol, we want
5357 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5358 addu $tempreg,$tempreg,$gp
5359 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5360 lui $at,<hiconstant>
5361 addi $at,$at,<loconstant>
5362 add $tempreg,$tempreg,$at
5364 If we have NewABI, and we know it's a local symbol, we want
5365 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5366 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5367 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5369 relax_start (offset_expr
.X_add_symbol
);
5371 expr1
.X_add_number
= offset_expr
.X_add_number
;
5372 offset_expr
.X_add_number
= 0;
5374 if (expr1
.X_add_number
== 0 && breg
== 0
5375 && (call
|| tempreg
== PIC_CALL_REG
))
5377 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5378 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5380 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5381 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5382 tempreg
, tempreg
, mips_gp_register
);
5383 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5384 tempreg
, lw_reloc_type
, tempreg
);
5386 if (expr1
.X_add_number
== 0)
5388 else if (expr1
.X_add_number
>= -0x8000
5389 && expr1
.X_add_number
< 0x8000)
5391 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5392 tempreg
, tempreg
, BFD_RELOC_LO16
);
5394 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5398 /* If we are going to add in a base register, and the
5399 target register and the base register are the same,
5400 then we are using AT as a temporary register. Since
5401 we want to load the constant into AT, we add our
5402 current AT (from the global offset table) and the
5403 register into the register now, and pretend we were
5404 not using a base register. */
5409 assert (tempreg
== AT
);
5410 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5416 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5417 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5422 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5425 offset_expr
.X_add_number
= expr1
.X_add_number
;
5426 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5427 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5428 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5429 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5432 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5433 treg
, tempreg
, breg
);
5443 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5447 /* The j instruction may not be used in PIC code, since it
5448 requires an absolute address. We convert it to a b
5450 if (mips_pic
== NO_PIC
)
5451 macro_build (&offset_expr
, "j", "a");
5453 macro_build (&offset_expr
, "b", "p");
5456 /* The jal instructions must be handled as macros because when
5457 generating PIC code they expand to multi-instruction
5458 sequences. Normally they are simple instructions. */
5463 if (mips_pic
== NO_PIC
)
5464 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5465 else if (mips_pic
== SVR4_PIC
)
5467 if (sreg
!= PIC_CALL_REG
)
5468 as_warn (_("MIPS PIC call to register other than $25"));
5470 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5473 if (mips_cprestore_offset
< 0)
5474 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5477 if (! mips_frame_reg_valid
)
5479 as_warn (_("No .frame pseudo-op used in PIC code"));
5480 /* Quiet this warning. */
5481 mips_frame_reg_valid
= 1;
5483 if (! mips_cprestore_valid
)
5485 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5486 /* Quiet this warning. */
5487 mips_cprestore_valid
= 1;
5489 expr1
.X_add_number
= mips_cprestore_offset
;
5490 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5493 HAVE_64BIT_ADDRESSES
);
5503 if (mips_pic
== NO_PIC
)
5504 macro_build (&offset_expr
, "jal", "a");
5505 else if (mips_pic
== SVR4_PIC
)
5507 /* If this is a reference to an external symbol, and we are
5508 using a small GOT, we want
5509 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5513 lw $gp,cprestore($sp)
5514 The cprestore value is set using the .cprestore
5515 pseudo-op. If we are using a big GOT, we want
5516 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5518 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5522 lw $gp,cprestore($sp)
5523 If the symbol is not external, we want
5524 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5526 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5529 lw $gp,cprestore($sp)
5531 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5532 sequences above, minus nops, unless the symbol is local,
5533 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5539 relax_start (offset_expr
.X_add_symbol
);
5540 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5541 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5544 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5545 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5551 relax_start (offset_expr
.X_add_symbol
);
5552 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5553 BFD_RELOC_MIPS_CALL_HI16
);
5554 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5555 PIC_CALL_REG
, mips_gp_register
);
5556 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5557 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5560 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5561 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5563 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5564 PIC_CALL_REG
, PIC_CALL_REG
,
5565 BFD_RELOC_MIPS_GOT_OFST
);
5569 macro_build_jalr (&offset_expr
);
5573 relax_start (offset_expr
.X_add_symbol
);
5576 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5577 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5586 gpdelay
= reg_needs_delay (mips_gp_register
);
5587 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5588 BFD_RELOC_MIPS_CALL_HI16
);
5589 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5590 PIC_CALL_REG
, mips_gp_register
);
5591 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5592 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5597 macro_build (NULL
, "nop", "");
5599 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5600 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5603 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5604 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5606 macro_build_jalr (&offset_expr
);
5608 if (mips_cprestore_offset
< 0)
5609 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5612 if (! mips_frame_reg_valid
)
5614 as_warn (_("No .frame pseudo-op used in PIC code"));
5615 /* Quiet this warning. */
5616 mips_frame_reg_valid
= 1;
5618 if (! mips_cprestore_valid
)
5620 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5621 /* Quiet this warning. */
5622 mips_cprestore_valid
= 1;
5624 if (mips_opts
.noreorder
)
5625 macro_build (NULL
, "nop", "");
5626 expr1
.X_add_number
= mips_cprestore_offset
;
5627 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5630 HAVE_64BIT_ADDRESSES
);
5656 /* Itbl support may require additional care here. */
5661 /* Itbl support may require additional care here. */
5666 /* Itbl support may require additional care here. */
5671 /* Itbl support may require additional care here. */
5683 if (mips_opts
.arch
== CPU_R4650
)
5685 as_bad (_("opcode not supported on this processor"));
5689 /* Itbl support may require additional care here. */
5694 /* Itbl support may require additional care here. */
5699 /* Itbl support may require additional care here. */
5719 if (breg
== treg
|| coproc
|| lr
)
5740 /* Itbl support may require additional care here. */
5745 /* Itbl support may require additional care here. */
5750 /* Itbl support may require additional care here. */
5755 /* Itbl support may require additional care here. */
5771 if (mips_opts
.arch
== CPU_R4650
)
5773 as_bad (_("opcode not supported on this processor"));
5778 /* Itbl support may require additional care here. */
5782 /* Itbl support may require additional care here. */
5787 /* Itbl support may require additional care here. */
5799 /* Itbl support may require additional care here. */
5800 if (mask
== M_LWC1_AB
5801 || mask
== M_SWC1_AB
5802 || mask
== M_LDC1_AB
5803 || mask
== M_SDC1_AB
5812 if (offset_expr
.X_op
!= O_constant
5813 && offset_expr
.X_op
!= O_symbol
)
5815 as_bad (_("expression too complex"));
5816 offset_expr
.X_op
= O_constant
;
5819 /* A constant expression in PIC code can be handled just as it
5820 is in non PIC code. */
5821 if (offset_expr
.X_op
== O_constant
)
5823 if (HAVE_32BIT_ADDRESSES
5824 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5825 as_bad (_("constant too large"));
5827 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5828 & ~(bfd_vma
) 0xffff);
5829 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5831 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5832 tempreg
, tempreg
, breg
);
5833 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5835 else if (mips_pic
== NO_PIC
)
5837 /* If this is a reference to a GP relative symbol, and there
5838 is no base register, we want
5839 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5840 Otherwise, if there is no base register, we want
5841 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5842 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5843 If we have a constant, we need two instructions anyhow,
5844 so we always use the latter form.
5846 If we have a base register, and this is a reference to a
5847 GP relative symbol, we want
5848 addu $tempreg,$breg,$gp
5849 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5851 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5852 addu $tempreg,$tempreg,$breg
5853 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5854 With a constant we always use the latter case.
5856 With 64bit address space and no base register and $at usable,
5858 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5859 lui $at,<sym> (BFD_RELOC_HI16_S)
5860 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5863 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5864 If we have a base register, we want
5865 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5866 lui $at,<sym> (BFD_RELOC_HI16_S)
5867 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5871 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5873 Without $at we can't generate the optimal path for superscalar
5874 processors here since this would require two temporary registers.
5875 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5876 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5878 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5880 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5881 If we have a base register, we want
5882 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5883 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5885 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5887 daddu $tempreg,$tempreg,$breg
5888 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5890 For GP relative symbols in 64bit address space we can use
5891 the same sequence as in 32bit address space. */
5892 if (HAVE_64BIT_SYMBOLS
)
5894 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5895 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5897 relax_start (offset_expr
.X_add_symbol
);
5900 macro_build (&offset_expr
, s
, fmt
, treg
,
5901 BFD_RELOC_GPREL16
, mips_gp_register
);
5905 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5906 tempreg
, breg
, mips_gp_register
);
5907 macro_build (&offset_expr
, s
, fmt
, treg
,
5908 BFD_RELOC_GPREL16
, tempreg
);
5913 if (used_at
== 0 && !mips_opts
.noat
)
5915 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5916 BFD_RELOC_MIPS_HIGHEST
);
5917 macro_build (&offset_expr
, "lui", "t,u", AT
,
5919 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5920 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5922 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5923 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5924 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5925 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5931 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5932 BFD_RELOC_MIPS_HIGHEST
);
5933 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5934 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5935 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5936 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5937 tempreg
, BFD_RELOC_HI16_S
);
5938 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5940 macro_build (NULL
, "daddu", "d,v,t",
5941 tempreg
, tempreg
, breg
);
5942 macro_build (&offset_expr
, s
, fmt
, treg
,
5943 BFD_RELOC_LO16
, tempreg
);
5946 if (mips_relax
.sequence
)
5953 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5954 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5956 relax_start (offset_expr
.X_add_symbol
);
5957 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5961 macro_build_lui (&offset_expr
, tempreg
);
5962 macro_build (&offset_expr
, s
, fmt
, treg
,
5963 BFD_RELOC_LO16
, tempreg
);
5964 if (mips_relax
.sequence
)
5969 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5970 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5972 relax_start (offset_expr
.X_add_symbol
);
5973 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5974 tempreg
, breg
, mips_gp_register
);
5975 macro_build (&offset_expr
, s
, fmt
, treg
,
5976 BFD_RELOC_GPREL16
, tempreg
);
5979 macro_build_lui (&offset_expr
, tempreg
);
5980 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5981 tempreg
, tempreg
, breg
);
5982 macro_build (&offset_expr
, s
, fmt
, treg
,
5983 BFD_RELOC_LO16
, tempreg
);
5984 if (mips_relax
.sequence
)
5988 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5990 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5992 /* If this is a reference to an external symbol, we want
5993 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5995 <op> $treg,0($tempreg)
5997 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5999 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6000 <op> $treg,0($tempreg)
6003 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6004 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6006 If there is a base register, we add it to $tempreg before
6007 the <op>. If there is a constant, we stick it in the
6008 <op> instruction. We don't handle constants larger than
6009 16 bits, because we have no way to load the upper 16 bits
6010 (actually, we could handle them for the subset of cases
6011 in which we are not using $at). */
6012 assert (offset_expr
.X_op
== O_symbol
);
6015 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6016 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6018 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6019 tempreg
, tempreg
, breg
);
6020 macro_build (&offset_expr
, s
, fmt
, treg
,
6021 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6024 expr1
.X_add_number
= offset_expr
.X_add_number
;
6025 offset_expr
.X_add_number
= 0;
6026 if (expr1
.X_add_number
< -0x8000
6027 || expr1
.X_add_number
>= 0x8000)
6028 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6029 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6030 lw_reloc_type
, mips_gp_register
);
6032 relax_start (offset_expr
.X_add_symbol
);
6034 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6035 tempreg
, BFD_RELOC_LO16
);
6038 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6039 tempreg
, tempreg
, breg
);
6040 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6042 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6046 /* If this is a reference to an external symbol, we want
6047 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6048 addu $tempreg,$tempreg,$gp
6049 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6050 <op> $treg,0($tempreg)
6052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6054 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6055 <op> $treg,0($tempreg)
6056 If there is a base register, we add it to $tempreg before
6057 the <op>. If there is a constant, we stick it in the
6058 <op> instruction. We don't handle constants larger than
6059 16 bits, because we have no way to load the upper 16 bits
6060 (actually, we could handle them for the subset of cases
6061 in which we are not using $at). */
6062 assert (offset_expr
.X_op
== O_symbol
);
6063 expr1
.X_add_number
= offset_expr
.X_add_number
;
6064 offset_expr
.X_add_number
= 0;
6065 if (expr1
.X_add_number
< -0x8000
6066 || expr1
.X_add_number
>= 0x8000)
6067 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6068 gpdelay
= reg_needs_delay (mips_gp_register
);
6069 relax_start (offset_expr
.X_add_symbol
);
6070 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6071 BFD_RELOC_MIPS_GOT_HI16
);
6072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6074 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6075 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6078 macro_build (NULL
, "nop", "");
6079 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6080 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6082 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6083 tempreg
, BFD_RELOC_LO16
);
6087 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6088 tempreg
, tempreg
, breg
);
6089 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6091 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6093 /* If this is a reference to an external symbol, we want
6094 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6095 add $tempreg,$tempreg,$gp
6096 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6097 <op> $treg,<ofst>($tempreg)
6098 Otherwise, for local symbols, we want:
6099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6100 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6101 assert (offset_expr
.X_op
== O_symbol
);
6102 expr1
.X_add_number
= offset_expr
.X_add_number
;
6103 offset_expr
.X_add_number
= 0;
6104 if (expr1
.X_add_number
< -0x8000
6105 || expr1
.X_add_number
>= 0x8000)
6106 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6107 relax_start (offset_expr
.X_add_symbol
);
6108 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6109 BFD_RELOC_MIPS_GOT_HI16
);
6110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6112 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6113 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6115 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6116 tempreg
, tempreg
, breg
);
6117 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6120 offset_expr
.X_add_number
= expr1
.X_add_number
;
6121 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6122 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6124 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6125 tempreg
, tempreg
, breg
);
6126 macro_build (&offset_expr
, s
, fmt
, treg
,
6127 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6137 load_register (treg
, &imm_expr
, 0);
6141 load_register (treg
, &imm_expr
, 1);
6145 if (imm_expr
.X_op
== O_constant
)
6148 load_register (AT
, &imm_expr
, 0);
6149 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6154 assert (offset_expr
.X_op
== O_symbol
6155 && strcmp (segment_name (S_GET_SEGMENT
6156 (offset_expr
.X_add_symbol
)),
6158 && offset_expr
.X_add_number
== 0);
6159 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6160 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6165 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6166 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6167 order 32 bits of the value and the low order 32 bits are either
6168 zero or in OFFSET_EXPR. */
6169 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6171 if (HAVE_64BIT_GPRS
)
6172 load_register (treg
, &imm_expr
, 1);
6177 if (target_big_endian
)
6189 load_register (hreg
, &imm_expr
, 0);
6192 if (offset_expr
.X_op
== O_absent
)
6193 move_register (lreg
, 0);
6196 assert (offset_expr
.X_op
== O_constant
);
6197 load_register (lreg
, &offset_expr
, 0);
6204 /* We know that sym is in the .rdata section. First we get the
6205 upper 16 bits of the address. */
6206 if (mips_pic
== NO_PIC
)
6208 macro_build_lui (&offset_expr
, AT
);
6211 else if (mips_pic
== SVR4_PIC
)
6213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6214 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6220 /* Now we load the register(s). */
6221 if (HAVE_64BIT_GPRS
)
6224 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6229 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6232 /* FIXME: How in the world do we deal with the possible
6234 offset_expr
.X_add_number
+= 4;
6235 macro_build (&offset_expr
, "lw", "t,o(b)",
6236 treg
+ 1, BFD_RELOC_LO16
, AT
);
6242 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6243 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6244 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6245 the value and the low order 32 bits are either zero or in
6247 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6250 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6251 if (HAVE_64BIT_FPRS
)
6253 assert (HAVE_64BIT_GPRS
);
6254 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6258 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6259 if (offset_expr
.X_op
== O_absent
)
6260 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6263 assert (offset_expr
.X_op
== O_constant
);
6264 load_register (AT
, &offset_expr
, 0);
6265 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6271 assert (offset_expr
.X_op
== O_symbol
6272 && offset_expr
.X_add_number
== 0);
6273 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6274 if (strcmp (s
, ".lit8") == 0)
6276 if (mips_opts
.isa
!= ISA_MIPS1
)
6278 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6279 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6282 breg
= mips_gp_register
;
6283 r
= BFD_RELOC_MIPS_LITERAL
;
6288 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6290 if (mips_pic
== SVR4_PIC
)
6291 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6292 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6295 /* FIXME: This won't work for a 64 bit address. */
6296 macro_build_lui (&offset_expr
, AT
);
6299 if (mips_opts
.isa
!= ISA_MIPS1
)
6301 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6302 treg
, BFD_RELOC_LO16
, AT
);
6311 if (mips_opts
.arch
== CPU_R4650
)
6313 as_bad (_("opcode not supported on this processor"));
6316 /* Even on a big endian machine $fn comes before $fn+1. We have
6317 to adjust when loading from memory. */
6320 assert (mips_opts
.isa
== ISA_MIPS1
);
6321 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6322 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6323 /* FIXME: A possible overflow which I don't know how to deal
6325 offset_expr
.X_add_number
+= 4;
6326 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6327 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6332 * The MIPS assembler seems to check for X_add_number not
6333 * being double aligned and generating:
6336 * addiu at,at,%lo(foo+1)
6339 * But, the resulting address is the same after relocation so why
6340 * generate the extra instruction?
6342 if (mips_opts
.arch
== CPU_R4650
)
6344 as_bad (_("opcode not supported on this processor"));
6347 /* Itbl support may require additional care here. */
6349 if (mips_opts
.isa
!= ISA_MIPS1
)
6360 if (mips_opts
.arch
== CPU_R4650
)
6362 as_bad (_("opcode not supported on this processor"));
6366 if (mips_opts
.isa
!= ISA_MIPS1
)
6374 /* Itbl support may require additional care here. */
6379 if (HAVE_64BIT_GPRS
)
6390 if (HAVE_64BIT_GPRS
)
6400 if (offset_expr
.X_op
!= O_symbol
6401 && offset_expr
.X_op
!= O_constant
)
6403 as_bad (_("expression too complex"));
6404 offset_expr
.X_op
= O_constant
;
6407 /* Even on a big endian machine $fn comes before $fn+1. We have
6408 to adjust when loading from memory. We set coproc if we must
6409 load $fn+1 first. */
6410 /* Itbl support may require additional care here. */
6411 if (! target_big_endian
)
6414 if (mips_pic
== NO_PIC
6415 || offset_expr
.X_op
== O_constant
)
6417 /* If this is a reference to a GP relative symbol, we want
6418 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6419 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6420 If we have a base register, we use this
6422 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6423 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6424 If this is not a GP relative symbol, we want
6425 lui $at,<sym> (BFD_RELOC_HI16_S)
6426 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6427 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6428 If there is a base register, we add it to $at after the
6429 lui instruction. If there is a constant, we always use
6431 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6432 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6434 relax_start (offset_expr
.X_add_symbol
);
6437 tempreg
= mips_gp_register
;
6441 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6442 AT
, breg
, mips_gp_register
);
6447 /* Itbl support may require additional care here. */
6448 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6449 BFD_RELOC_GPREL16
, tempreg
);
6450 offset_expr
.X_add_number
+= 4;
6452 /* Set mips_optimize to 2 to avoid inserting an
6454 hold_mips_optimize
= mips_optimize
;
6456 /* Itbl support may require additional care here. */
6457 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6458 BFD_RELOC_GPREL16
, tempreg
);
6459 mips_optimize
= hold_mips_optimize
;
6463 /* We just generated two relocs. When tc_gen_reloc
6464 handles this case, it will skip the first reloc and
6465 handle the second. The second reloc already has an
6466 extra addend of 4, which we added above. We must
6467 subtract it out, and then subtract another 4 to make
6468 the first reloc come out right. The second reloc
6469 will come out right because we are going to add 4 to
6470 offset_expr when we build its instruction below.
6472 If we have a symbol, then we don't want to include
6473 the offset, because it will wind up being included
6474 when we generate the reloc. */
6476 if (offset_expr
.X_op
== O_constant
)
6477 offset_expr
.X_add_number
-= 8;
6480 offset_expr
.X_add_number
= -4;
6481 offset_expr
.X_op
= O_constant
;
6485 macro_build_lui (&offset_expr
, AT
);
6487 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6488 /* Itbl support may require additional care here. */
6489 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6490 BFD_RELOC_LO16
, AT
);
6491 /* FIXME: How do we handle overflow here? */
6492 offset_expr
.X_add_number
+= 4;
6493 /* Itbl support may require additional care here. */
6494 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6495 BFD_RELOC_LO16
, AT
);
6496 if (mips_relax
.sequence
)
6499 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6501 /* If this is a reference to an external symbol, we want
6502 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6507 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6509 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6510 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6511 If there is a base register we add it to $at before the
6512 lwc1 instructions. If there is a constant we include it
6513 in the lwc1 instructions. */
6515 expr1
.X_add_number
= offset_expr
.X_add_number
;
6516 if (expr1
.X_add_number
< -0x8000
6517 || expr1
.X_add_number
>= 0x8000 - 4)
6518 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6519 load_got_offset (AT
, &offset_expr
);
6522 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6524 /* Set mips_optimize to 2 to avoid inserting an undesired
6526 hold_mips_optimize
= mips_optimize
;
6529 /* Itbl support may require additional care here. */
6530 relax_start (offset_expr
.X_add_symbol
);
6531 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6532 BFD_RELOC_LO16
, AT
);
6533 expr1
.X_add_number
+= 4;
6534 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6535 BFD_RELOC_LO16
, AT
);
6537 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6538 BFD_RELOC_LO16
, AT
);
6539 offset_expr
.X_add_number
+= 4;
6540 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6541 BFD_RELOC_LO16
, AT
);
6544 mips_optimize
= hold_mips_optimize
;
6546 else if (mips_pic
== SVR4_PIC
)
6550 /* If this is a reference to an external symbol, we want
6551 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6553 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6558 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6560 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6561 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6562 If there is a base register we add it to $at before the
6563 lwc1 instructions. If there is a constant we include it
6564 in the lwc1 instructions. */
6566 expr1
.X_add_number
= offset_expr
.X_add_number
;
6567 offset_expr
.X_add_number
= 0;
6568 if (expr1
.X_add_number
< -0x8000
6569 || expr1
.X_add_number
>= 0x8000 - 4)
6570 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6571 gpdelay
= reg_needs_delay (mips_gp_register
);
6572 relax_start (offset_expr
.X_add_symbol
);
6573 macro_build (&offset_expr
, "lui", "t,u",
6574 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6575 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6576 AT
, AT
, mips_gp_register
);
6577 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6578 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6581 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6582 /* Itbl support may require additional care here. */
6583 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6584 BFD_RELOC_LO16
, AT
);
6585 expr1
.X_add_number
+= 4;
6587 /* Set mips_optimize to 2 to avoid inserting an undesired
6589 hold_mips_optimize
= mips_optimize
;
6591 /* Itbl support may require additional care here. */
6592 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6593 BFD_RELOC_LO16
, AT
);
6594 mips_optimize
= hold_mips_optimize
;
6595 expr1
.X_add_number
-= 4;
6598 offset_expr
.X_add_number
= expr1
.X_add_number
;
6600 macro_build (NULL
, "nop", "");
6601 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6602 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6605 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6606 /* Itbl support may require additional care here. */
6607 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6608 BFD_RELOC_LO16
, AT
);
6609 offset_expr
.X_add_number
+= 4;
6611 /* Set mips_optimize to 2 to avoid inserting an undesired
6613 hold_mips_optimize
= mips_optimize
;
6615 /* Itbl support may require additional care here. */
6616 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6617 BFD_RELOC_LO16
, AT
);
6618 mips_optimize
= hold_mips_optimize
;
6632 assert (HAVE_32BIT_ADDRESSES
);
6633 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6634 offset_expr
.X_add_number
+= 4;
6635 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6638 /* New code added to support COPZ instructions.
6639 This code builds table entries out of the macros in mip_opcodes.
6640 R4000 uses interlocks to handle coproc delays.
6641 Other chips (like the R3000) require nops to be inserted for delays.
6643 FIXME: Currently, we require that the user handle delays.
6644 In order to fill delay slots for non-interlocked chips,
6645 we must have a way to specify delays based on the coprocessor.
6646 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6647 What are the side-effects of the cop instruction?
6648 What cache support might we have and what are its effects?
6649 Both coprocessor & memory require delays. how long???
6650 What registers are read/set/modified?
6652 If an itbl is provided to interpret cop instructions,
6653 this knowledge can be encoded in the itbl spec. */
6667 /* For now we just do C (same as Cz). The parameter will be
6668 stored in insn_opcode by mips_ip. */
6669 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6673 move_register (dreg
, sreg
);
6676 #ifdef LOSING_COMPILER
6678 /* Try and see if this is a new itbl instruction.
6679 This code builds table entries out of the macros in mip_opcodes.
6680 FIXME: For now we just assemble the expression and pass it's
6681 value along as a 32-bit immediate.
6682 We may want to have the assembler assemble this value,
6683 so that we gain the assembler's knowledge of delay slots,
6685 Would it be more efficient to use mask (id) here? */
6686 if (itbl_have_entries
6687 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6689 s
= ip
->insn_mo
->name
;
6691 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6692 macro_build (&immed_expr
, s
, "C");
6698 if (mips_opts
.noat
&& used_at
)
6699 as_bad (_("Macro used $at after \".set noat\""));
6703 macro2 (struct mips_cl_insn
*ip
)
6705 register int treg
, sreg
, dreg
, breg
;
6720 bfd_reloc_code_real_type r
;
6722 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6723 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6724 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6725 mask
= ip
->insn_mo
->mask
;
6727 expr1
.X_op
= O_constant
;
6728 expr1
.X_op_symbol
= NULL
;
6729 expr1
.X_add_symbol
= NULL
;
6730 expr1
.X_add_number
= 1;
6734 #endif /* LOSING_COMPILER */
6739 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6740 macro_build (NULL
, "mflo", "d", dreg
);
6746 /* The MIPS assembler some times generates shifts and adds. I'm
6747 not trying to be that fancy. GCC should do this for us
6750 load_register (AT
, &imm_expr
, dbl
);
6751 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6752 macro_build (NULL
, "mflo", "d", dreg
);
6765 mips_emit_delays (TRUE
);
6766 ++mips_opts
.noreorder
;
6767 mips_any_noreorder
= 1;
6770 load_register (AT
, &imm_expr
, dbl
);
6771 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6772 macro_build (NULL
, "mflo", "d", dreg
);
6773 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6774 macro_build (NULL
, "mfhi", "d", AT
);
6776 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6779 expr1
.X_add_number
= 8;
6780 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6781 macro_build (NULL
, "nop", "", 0);
6782 macro_build (NULL
, "break", "c", 6);
6784 --mips_opts
.noreorder
;
6785 macro_build (NULL
, "mflo", "d", dreg
);
6798 mips_emit_delays (TRUE
);
6799 ++mips_opts
.noreorder
;
6800 mips_any_noreorder
= 1;
6803 load_register (AT
, &imm_expr
, dbl
);
6804 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6805 sreg
, imm
? AT
: treg
);
6806 macro_build (NULL
, "mfhi", "d", AT
);
6807 macro_build (NULL
, "mflo", "d", dreg
);
6809 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6812 expr1
.X_add_number
= 8;
6813 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6814 macro_build (NULL
, "nop", "", 0);
6815 macro_build (NULL
, "break", "c", 6);
6817 --mips_opts
.noreorder
;
6821 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6832 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6833 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6837 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6838 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6839 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6840 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6844 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6855 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6856 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6860 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6861 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6862 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6863 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6871 if (imm_expr
.X_op
!= O_constant
)
6872 as_bad (_("Improper rotate count"));
6873 rot
= imm_expr
.X_add_number
& 0x3f;
6874 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6876 rot
= (64 - rot
) & 0x3f;
6878 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6880 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6885 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6888 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6889 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6892 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6893 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6894 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6902 if (imm_expr
.X_op
!= O_constant
)
6903 as_bad (_("Improper rotate count"));
6904 rot
= imm_expr
.X_add_number
& 0x1f;
6905 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6907 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6912 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6916 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6917 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6918 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6923 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6925 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6929 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6930 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6931 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6932 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6936 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6938 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6942 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6943 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6944 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6945 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6953 if (imm_expr
.X_op
!= O_constant
)
6954 as_bad (_("Improper rotate count"));
6955 rot
= imm_expr
.X_add_number
& 0x3f;
6956 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6959 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6961 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6966 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6969 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6970 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6973 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6974 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6975 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6983 if (imm_expr
.X_op
!= O_constant
)
6984 as_bad (_("Improper rotate count"));
6985 rot
= imm_expr
.X_add_number
& 0x1f;
6986 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6988 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6993 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6997 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6998 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6999 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7004 if (mips_opts
.arch
== CPU_R4650
)
7006 as_bad (_("opcode not supported on this processor"));
7009 assert (mips_opts
.isa
== ISA_MIPS1
);
7010 /* Even on a big endian machine $fn comes before $fn+1. We have
7011 to adjust when storing to memory. */
7012 macro_build (&offset_expr
, "swc1", "T,o(b)",
7013 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7014 offset_expr
.X_add_number
+= 4;
7015 macro_build (&offset_expr
, "swc1", "T,o(b)",
7016 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7021 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7023 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7026 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7027 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7032 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7034 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7039 as_warn (_("Instruction %s: result is always false"),
7041 move_register (dreg
, 0);
7044 if (imm_expr
.X_op
== O_constant
7045 && imm_expr
.X_add_number
>= 0
7046 && imm_expr
.X_add_number
< 0x10000)
7048 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7050 else if (imm_expr
.X_op
== O_constant
7051 && imm_expr
.X_add_number
> -0x8000
7052 && imm_expr
.X_add_number
< 0)
7054 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7055 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7056 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7060 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7061 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7064 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7067 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7073 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7074 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7077 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7079 if (imm_expr
.X_op
== O_constant
7080 && imm_expr
.X_add_number
>= -0x8000
7081 && imm_expr
.X_add_number
< 0x8000)
7083 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7084 dreg
, sreg
, BFD_RELOC_LO16
);
7088 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7089 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7093 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7096 case M_SGT
: /* sreg > treg <==> treg < sreg */
7102 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7105 case M_SGT_I
: /* sreg > I <==> I < sreg */
7112 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7113 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7116 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7122 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7123 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7126 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7133 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7134 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7135 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7139 if (imm_expr
.X_op
== O_constant
7140 && imm_expr
.X_add_number
>= -0x8000
7141 && imm_expr
.X_add_number
< 0x8000)
7143 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7147 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7148 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7152 if (imm_expr
.X_op
== O_constant
7153 && imm_expr
.X_add_number
>= -0x8000
7154 && imm_expr
.X_add_number
< 0x8000)
7156 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7161 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7162 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7167 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7169 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7172 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7173 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7178 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7180 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7185 as_warn (_("Instruction %s: result is always true"),
7187 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7188 dreg
, 0, BFD_RELOC_LO16
);
7191 if (imm_expr
.X_op
== O_constant
7192 && imm_expr
.X_add_number
>= 0
7193 && imm_expr
.X_add_number
< 0x10000)
7195 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7197 else if (imm_expr
.X_op
== O_constant
7198 && imm_expr
.X_add_number
> -0x8000
7199 && imm_expr
.X_add_number
< 0)
7201 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7202 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7203 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7207 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7208 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7211 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7217 if (imm_expr
.X_op
== O_constant
7218 && imm_expr
.X_add_number
> -0x8000
7219 && imm_expr
.X_add_number
<= 0x8000)
7221 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7222 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7223 dreg
, sreg
, BFD_RELOC_LO16
);
7227 load_register (AT
, &imm_expr
, dbl
);
7228 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7234 if (imm_expr
.X_op
== O_constant
7235 && imm_expr
.X_add_number
> -0x8000
7236 && imm_expr
.X_add_number
<= 0x8000)
7238 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7239 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7240 dreg
, sreg
, BFD_RELOC_LO16
);
7244 load_register (AT
, &imm_expr
, dbl
);
7245 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7267 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7268 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7273 assert (mips_opts
.isa
== ISA_MIPS1
);
7275 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7276 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7279 * Is the double cfc1 instruction a bug in the mips assembler;
7280 * or is there a reason for it?
7282 mips_emit_delays (TRUE
);
7283 ++mips_opts
.noreorder
;
7284 mips_any_noreorder
= 1;
7285 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7286 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7287 macro_build (NULL
, "nop", "");
7288 expr1
.X_add_number
= 3;
7289 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7290 expr1
.X_add_number
= 2;
7291 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7292 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7293 macro_build (NULL
, "nop", "");
7294 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7296 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7297 macro_build (NULL
, "nop", "");
7298 --mips_opts
.noreorder
;
7308 if (offset_expr
.X_add_number
>= 0x7fff)
7309 as_bad (_("operand overflow"));
7310 if (! target_big_endian
)
7311 ++offset_expr
.X_add_number
;
7312 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7313 if (! target_big_endian
)
7314 --offset_expr
.X_add_number
;
7316 ++offset_expr
.X_add_number
;
7317 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7318 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7319 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7332 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7333 as_bad (_("operand overflow"));
7341 if (! target_big_endian
)
7342 offset_expr
.X_add_number
+= off
;
7343 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7344 if (! target_big_endian
)
7345 offset_expr
.X_add_number
-= off
;
7347 offset_expr
.X_add_number
+= off
;
7348 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7350 /* If necessary, move the result in tempreg the final destination. */
7351 if (treg
== tempreg
)
7353 /* Protect second load's delay slot. */
7355 move_register (treg
, tempreg
);
7369 load_address (AT
, &offset_expr
, &used_at
);
7371 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7372 if (! target_big_endian
)
7373 expr1
.X_add_number
= off
;
7375 expr1
.X_add_number
= 0;
7376 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7377 if (! target_big_endian
)
7378 expr1
.X_add_number
= 0;
7380 expr1
.X_add_number
= off
;
7381 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7387 load_address (AT
, &offset_expr
, &used_at
);
7389 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7390 if (target_big_endian
)
7391 expr1
.X_add_number
= 0;
7392 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7393 treg
, BFD_RELOC_LO16
, AT
);
7394 if (target_big_endian
)
7395 expr1
.X_add_number
= 1;
7397 expr1
.X_add_number
= 0;
7398 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7399 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7400 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7405 if (offset_expr
.X_add_number
>= 0x7fff)
7406 as_bad (_("operand overflow"));
7407 if (target_big_endian
)
7408 ++offset_expr
.X_add_number
;
7409 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7410 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7411 if (target_big_endian
)
7412 --offset_expr
.X_add_number
;
7414 ++offset_expr
.X_add_number
;
7415 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7428 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7429 as_bad (_("operand overflow"));
7430 if (! target_big_endian
)
7431 offset_expr
.X_add_number
+= off
;
7432 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7433 if (! target_big_endian
)
7434 offset_expr
.X_add_number
-= off
;
7436 offset_expr
.X_add_number
+= off
;
7437 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7451 load_address (AT
, &offset_expr
, &used_at
);
7453 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7454 if (! target_big_endian
)
7455 expr1
.X_add_number
= off
;
7457 expr1
.X_add_number
= 0;
7458 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7459 if (! target_big_endian
)
7460 expr1
.X_add_number
= 0;
7462 expr1
.X_add_number
= off
;
7463 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7468 load_address (AT
, &offset_expr
, &used_at
);
7470 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7471 if (! target_big_endian
)
7472 expr1
.X_add_number
= 0;
7473 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7474 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7475 if (! target_big_endian
)
7476 expr1
.X_add_number
= 1;
7478 expr1
.X_add_number
= 0;
7479 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7480 if (! target_big_endian
)
7481 expr1
.X_add_number
= 0;
7483 expr1
.X_add_number
= 1;
7484 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7485 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7486 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7490 /* FIXME: Check if this is one of the itbl macros, since they
7491 are added dynamically. */
7492 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7495 if (mips_opts
.noat
&& used_at
)
7496 as_bad (_("Macro used $at after \".set noat\""));
7499 /* Implement macros in mips16 mode. */
7502 mips16_macro (struct mips_cl_insn
*ip
)
7505 int xreg
, yreg
, zreg
, tmp
;
7508 const char *s
, *s2
, *s3
;
7510 mask
= ip
->insn_mo
->mask
;
7512 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7513 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7514 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7516 expr1
.X_op
= O_constant
;
7517 expr1
.X_op_symbol
= NULL
;
7518 expr1
.X_add_symbol
= NULL
;
7519 expr1
.X_add_number
= 1;
7538 mips_emit_delays (TRUE
);
7539 ++mips_opts
.noreorder
;
7540 mips_any_noreorder
= 1;
7541 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7542 expr1
.X_add_number
= 2;
7543 macro_build (&expr1
, "bnez", "x,p", yreg
);
7544 macro_build (NULL
, "break", "6", 7);
7546 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7547 since that causes an overflow. We should do that as well,
7548 but I don't see how to do the comparisons without a temporary
7550 --mips_opts
.noreorder
;
7551 macro_build (NULL
, s
, "x", zreg
);
7570 mips_emit_delays (TRUE
);
7571 ++mips_opts
.noreorder
;
7572 mips_any_noreorder
= 1;
7573 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7574 expr1
.X_add_number
= 2;
7575 macro_build (&expr1
, "bnez", "x,p", yreg
);
7576 macro_build (NULL
, "break", "6", 7);
7577 --mips_opts
.noreorder
;
7578 macro_build (NULL
, s2
, "x", zreg
);
7584 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7585 macro_build (NULL
, "mflo", "x", zreg
);
7593 if (imm_expr
.X_op
!= O_constant
)
7594 as_bad (_("Unsupported large constant"));
7595 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7596 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7600 if (imm_expr
.X_op
!= O_constant
)
7601 as_bad (_("Unsupported large constant"));
7602 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7603 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7607 if (imm_expr
.X_op
!= O_constant
)
7608 as_bad (_("Unsupported large constant"));
7609 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7610 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7632 goto do_reverse_branch
;
7636 goto do_reverse_branch
;
7648 goto do_reverse_branch
;
7659 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7660 macro_build (&offset_expr
, s2
, "p");
7687 goto do_addone_branch_i
;
7692 goto do_addone_branch_i
;
7707 goto do_addone_branch_i
;
7714 if (imm_expr
.X_op
!= O_constant
)
7715 as_bad (_("Unsupported large constant"));
7716 ++imm_expr
.X_add_number
;
7719 macro_build (&imm_expr
, s
, s3
, xreg
);
7720 macro_build (&offset_expr
, s2
, "p");
7724 expr1
.X_add_number
= 0;
7725 macro_build (&expr1
, "slti", "x,8", yreg
);
7727 move_register (xreg
, yreg
);
7728 expr1
.X_add_number
= 2;
7729 macro_build (&expr1
, "bteqz", "p");
7730 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7734 /* For consistency checking, verify that all bits are specified either
7735 by the match/mask part of the instruction definition, or by the
7738 validate_mips_insn (const struct mips_opcode
*opc
)
7740 const char *p
= opc
->args
;
7742 unsigned long used_bits
= opc
->mask
;
7744 if ((used_bits
& opc
->match
) != opc
->match
)
7746 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7747 opc
->name
, opc
->args
);
7750 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7760 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7761 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7762 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7763 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7764 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7765 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7766 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7767 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7768 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7771 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7772 c
, opc
->name
, opc
->args
);
7776 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7777 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7779 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7780 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7781 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7782 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7784 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7785 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7787 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7788 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7790 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7791 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7792 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7793 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7794 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7795 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7796 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7797 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7798 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7799 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7800 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7801 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7802 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7803 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7804 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7805 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7806 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7808 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7809 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7810 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7811 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7813 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7814 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7815 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7816 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7817 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7818 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7819 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7820 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7821 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7824 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7825 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7826 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7827 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7828 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7832 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7833 c
, opc
->name
, opc
->args
);
7837 if (used_bits
!= 0xffffffff)
7839 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7840 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7846 /* This routine assembles an instruction into its binary format. As a
7847 side effect, it sets one of the global variables imm_reloc or
7848 offset_reloc to the type of relocation to do if one of the operands
7849 is an address expression. */
7852 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7857 struct mips_opcode
*insn
;
7860 unsigned int lastregno
= 0;
7861 unsigned int lastpos
= 0;
7862 unsigned int limlo
, limhi
;
7868 /* If the instruction contains a '.', we first try to match an instruction
7869 including the '.'. Then we try again without the '.'. */
7871 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7874 /* If we stopped on whitespace, then replace the whitespace with null for
7875 the call to hash_find. Save the character we replaced just in case we
7876 have to re-parse the instruction. */
7883 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7885 /* If we didn't find the instruction in the opcode table, try again, but
7886 this time with just the instruction up to, but not including the
7890 /* Restore the character we overwrite above (if any). */
7894 /* Scan up to the first '.' or whitespace. */
7896 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7900 /* If we did not find a '.', then we can quit now. */
7903 insn_error
= "unrecognized opcode";
7907 /* Lookup the instruction in the hash table. */
7909 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7911 insn_error
= "unrecognized opcode";
7921 assert (strcmp (insn
->name
, str
) == 0);
7923 if (OPCODE_IS_MEMBER (insn
,
7925 | (file_ase_mips16
? INSN_MIPS16
: 0)
7926 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7927 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7933 if (insn
->pinfo
!= INSN_MACRO
)
7935 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7941 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7942 && strcmp (insn
->name
, insn
[1].name
) == 0)
7951 static char buf
[100];
7953 _("opcode not supported on this processor: %s (%s)"),
7954 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7955 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7964 create_insn (ip
, insn
);
7966 for (args
= insn
->args
;; ++args
)
7970 s
+= strspn (s
, " \t");
7974 case '\0': /* end of args */
7987 INSERT_OPERAND (RS
, *ip
, lastregno
);
7991 INSERT_OPERAND (RT
, *ip
, lastregno
);
7995 INSERT_OPERAND (FT
, *ip
, lastregno
);
7999 INSERT_OPERAND (FS
, *ip
, lastregno
);
8005 /* Handle optional base register.
8006 Either the base register is omitted or
8007 we must have a left paren. */
8008 /* This is dependent on the next operand specifier
8009 is a base register specification. */
8010 assert (args
[1] == 'b' || args
[1] == '5'
8011 || args
[1] == '-' || args
[1] == '4');
8015 case ')': /* these must match exactly */
8022 case '+': /* Opcode extension character. */
8025 case 'A': /* ins/ext position, becomes LSB. */
8034 my_getExpression (&imm_expr
, s
);
8035 check_absolute_expr (ip
, &imm_expr
);
8036 if ((unsigned long) imm_expr
.X_add_number
< limlo
8037 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8039 as_bad (_("Improper position (%lu)"),
8040 (unsigned long) imm_expr
.X_add_number
);
8041 imm_expr
.X_add_number
= limlo
;
8043 lastpos
= imm_expr
.X_add_number
;
8044 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8045 imm_expr
.X_op
= O_absent
;
8049 case 'B': /* ins size, becomes MSB. */
8058 my_getExpression (&imm_expr
, s
);
8059 check_absolute_expr (ip
, &imm_expr
);
8060 /* Check for negative input so that small negative numbers
8061 will not succeed incorrectly. The checks against
8062 (pos+size) transitively check "size" itself,
8063 assuming that "pos" is reasonable. */
8064 if ((long) imm_expr
.X_add_number
< 0
8065 || ((unsigned long) imm_expr
.X_add_number
8067 || ((unsigned long) imm_expr
.X_add_number
8070 as_bad (_("Improper insert size (%lu, position %lu)"),
8071 (unsigned long) imm_expr
.X_add_number
,
8072 (unsigned long) lastpos
);
8073 imm_expr
.X_add_number
= limlo
- lastpos
;
8075 INSERT_OPERAND (INSMSB
, *ip
,
8076 lastpos
+ imm_expr
.X_add_number
- 1);
8077 imm_expr
.X_op
= O_absent
;
8081 case 'C': /* ext size, becomes MSBD. */
8094 my_getExpression (&imm_expr
, s
);
8095 check_absolute_expr (ip
, &imm_expr
);
8096 /* Check for negative input so that small negative numbers
8097 will not succeed incorrectly. The checks against
8098 (pos+size) transitively check "size" itself,
8099 assuming that "pos" is reasonable. */
8100 if ((long) imm_expr
.X_add_number
< 0
8101 || ((unsigned long) imm_expr
.X_add_number
8103 || ((unsigned long) imm_expr
.X_add_number
8106 as_bad (_("Improper extract size (%lu, position %lu)"),
8107 (unsigned long) imm_expr
.X_add_number
,
8108 (unsigned long) lastpos
);
8109 imm_expr
.X_add_number
= limlo
- lastpos
;
8111 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8112 imm_expr
.X_op
= O_absent
;
8117 /* +D is for disassembly only; never match. */
8121 /* "+I" is like "I", except that imm2_expr is used. */
8122 my_getExpression (&imm2_expr
, s
);
8123 if (imm2_expr
.X_op
!= O_big
8124 && imm2_expr
.X_op
!= O_constant
)
8125 insn_error
= _("absolute expression required");
8126 normalize_constant_expr (&imm2_expr
);
8131 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8132 *args
, insn
->name
, insn
->args
);
8133 /* Further processing is fruitless. */
8138 case '<': /* must be at least one digit */
8140 * According to the manual, if the shift amount is greater
8141 * than 31 or less than 0, then the shift amount should be
8142 * mod 32. In reality the mips assembler issues an error.
8143 * We issue a warning and mask out all but the low 5 bits.
8145 my_getExpression (&imm_expr
, s
);
8146 check_absolute_expr (ip
, &imm_expr
);
8147 if ((unsigned long) imm_expr
.X_add_number
> 31)
8148 as_warn (_("Improper shift amount (%lu)"),
8149 (unsigned long) imm_expr
.X_add_number
);
8150 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8151 imm_expr
.X_op
= O_absent
;
8155 case '>': /* shift amount minus 32 */
8156 my_getExpression (&imm_expr
, s
);
8157 check_absolute_expr (ip
, &imm_expr
);
8158 if ((unsigned long) imm_expr
.X_add_number
< 32
8159 || (unsigned long) imm_expr
.X_add_number
> 63)
8161 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8162 imm_expr
.X_op
= O_absent
;
8166 case 'k': /* cache code */
8167 case 'h': /* prefx code */
8168 my_getExpression (&imm_expr
, s
);
8169 check_absolute_expr (ip
, &imm_expr
);
8170 if ((unsigned long) imm_expr
.X_add_number
> 31)
8171 as_warn (_("Invalid value for `%s' (%lu)"),
8173 (unsigned long) imm_expr
.X_add_number
);
8175 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8177 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8178 imm_expr
.X_op
= O_absent
;
8182 case 'c': /* break code */
8183 my_getExpression (&imm_expr
, s
);
8184 check_absolute_expr (ip
, &imm_expr
);
8185 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8186 as_warn (_("Illegal break code (%lu)"),
8187 (unsigned long) imm_expr
.X_add_number
);
8188 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8189 imm_expr
.X_op
= O_absent
;
8193 case 'q': /* lower break code */
8194 my_getExpression (&imm_expr
, s
);
8195 check_absolute_expr (ip
, &imm_expr
);
8196 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8197 as_warn (_("Illegal lower break code (%lu)"),
8198 (unsigned long) imm_expr
.X_add_number
);
8199 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8200 imm_expr
.X_op
= O_absent
;
8204 case 'B': /* 20-bit syscall/break code. */
8205 my_getExpression (&imm_expr
, s
);
8206 check_absolute_expr (ip
, &imm_expr
);
8207 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8208 as_warn (_("Illegal 20-bit code (%lu)"),
8209 (unsigned long) imm_expr
.X_add_number
);
8210 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8211 imm_expr
.X_op
= O_absent
;
8215 case 'C': /* Coprocessor code */
8216 my_getExpression (&imm_expr
, s
);
8217 check_absolute_expr (ip
, &imm_expr
);
8218 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8220 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8221 (unsigned long) imm_expr
.X_add_number
);
8222 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8224 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8225 imm_expr
.X_op
= O_absent
;
8229 case 'J': /* 19-bit wait code. */
8230 my_getExpression (&imm_expr
, s
);
8231 check_absolute_expr (ip
, &imm_expr
);
8232 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8233 as_warn (_("Illegal 19-bit code (%lu)"),
8234 (unsigned long) imm_expr
.X_add_number
);
8235 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8236 imm_expr
.X_op
= O_absent
;
8240 case 'P': /* Performance register */
8241 my_getExpression (&imm_expr
, s
);
8242 check_absolute_expr (ip
, &imm_expr
);
8243 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8244 as_warn (_("Invalid performance register (%lu)"),
8245 (unsigned long) imm_expr
.X_add_number
);
8246 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8247 imm_expr
.X_op
= O_absent
;
8251 case 'b': /* base register */
8252 case 'd': /* destination register */
8253 case 's': /* source register */
8254 case 't': /* target register */
8255 case 'r': /* both target and source */
8256 case 'v': /* both dest and source */
8257 case 'w': /* both dest and target */
8258 case 'E': /* coprocessor target register */
8259 case 'G': /* coprocessor destination register */
8260 case 'K': /* 'rdhwr' destination register */
8261 case 'x': /* ignore register name */
8262 case 'z': /* must be zero register */
8263 case 'U': /* destination register (clo/clz). */
8278 while (ISDIGIT (*s
));
8280 as_bad (_("Invalid register number (%d)"), regno
);
8282 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8286 if (s
[1] == 'r' && s
[2] == 'a')
8291 else if (s
[1] == 'f' && s
[2] == 'p')
8296 else if (s
[1] == 's' && s
[2] == 'p')
8301 else if (s
[1] == 'g' && s
[2] == 'p')
8306 else if (s
[1] == 'a' && s
[2] == 't')
8311 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8316 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8321 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8326 else if (itbl_have_entries
)
8331 p
= s
+ 1; /* advance past '$' */
8332 n
= itbl_get_field (&p
); /* n is name */
8334 /* See if this is a register defined in an
8336 if (itbl_get_reg_val (n
, &r
))
8338 /* Get_field advances to the start of
8339 the next field, so we need to back
8340 rack to the end of the last field. */
8344 s
= strchr (s
, '\0');
8358 as_warn (_("Used $at without \".set noat\""));
8364 if (c
== 'r' || c
== 'v' || c
== 'w')
8371 /* 'z' only matches $0. */
8372 if (c
== 'z' && regno
!= 0)
8375 /* Now that we have assembled one operand, we use the args string
8376 * to figure out where it goes in the instruction. */
8383 INSERT_OPERAND (RS
, *ip
, regno
);
8388 INSERT_OPERAND (RD
, *ip
, regno
);
8391 INSERT_OPERAND (RD
, *ip
, regno
);
8392 INSERT_OPERAND (RT
, *ip
, regno
);
8397 INSERT_OPERAND (RT
, *ip
, regno
);
8400 /* This case exists because on the r3000 trunc
8401 expands into a macro which requires a gp
8402 register. On the r6000 or r4000 it is
8403 assembled into a single instruction which
8404 ignores the register. Thus the insn version
8405 is MIPS_ISA2 and uses 'x', and the macro
8406 version is MIPS_ISA1 and uses 't'. */
8409 /* This case is for the div instruction, which
8410 acts differently if the destination argument
8411 is $0. This only matches $0, and is checked
8412 outside the switch. */
8415 /* Itbl operand; not yet implemented. FIXME ?? */
8417 /* What about all other operands like 'i', which
8418 can be specified in the opcode table? */
8428 INSERT_OPERAND (RS
, *ip
, lastregno
);
8431 INSERT_OPERAND (RT
, *ip
, lastregno
);
8436 case 'O': /* MDMX alignment immediate constant. */
8437 my_getExpression (&imm_expr
, s
);
8438 check_absolute_expr (ip
, &imm_expr
);
8439 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8440 as_warn ("Improper align amount (%ld), using low bits",
8441 (long) imm_expr
.X_add_number
);
8442 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8443 imm_expr
.X_op
= O_absent
;
8447 case 'Q': /* MDMX vector, element sel, or const. */
8450 /* MDMX Immediate. */
8451 my_getExpression (&imm_expr
, s
);
8452 check_absolute_expr (ip
, &imm_expr
);
8453 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8454 as_warn (_("Invalid MDMX Immediate (%ld)"),
8455 (long) imm_expr
.X_add_number
);
8456 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8457 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8458 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8460 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8461 imm_expr
.X_op
= O_absent
;
8465 /* Not MDMX Immediate. Fall through. */
8466 case 'X': /* MDMX destination register. */
8467 case 'Y': /* MDMX source register. */
8468 case 'Z': /* MDMX target register. */
8470 case 'D': /* floating point destination register */
8471 case 'S': /* floating point source register */
8472 case 'T': /* floating point target register */
8473 case 'R': /* floating point source register */
8477 /* Accept $fN for FP and MDMX register numbers, and in
8478 addition accept $vN for MDMX register numbers. */
8479 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8480 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8491 while (ISDIGIT (*s
));
8494 as_bad (_("Invalid float register number (%d)"), regno
);
8496 if ((regno
& 1) != 0
8498 && ! (strcmp (str
, "mtc1") == 0
8499 || strcmp (str
, "mfc1") == 0
8500 || strcmp (str
, "lwc1") == 0
8501 || strcmp (str
, "swc1") == 0
8502 || strcmp (str
, "l.s") == 0
8503 || strcmp (str
, "s.s") == 0))
8504 as_warn (_("Float register should be even, was %d"),
8512 if (c
== 'V' || c
== 'W')
8523 INSERT_OPERAND (FD
, *ip
, regno
);
8528 INSERT_OPERAND (FS
, *ip
, regno
);
8531 /* This is like 'Z', but also needs to fix the MDMX
8532 vector/scalar select bits. Note that the
8533 scalar immediate case is handled above. */
8536 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8537 int max_el
= (is_qh
? 3 : 7);
8539 my_getExpression(&imm_expr
, s
);
8540 check_absolute_expr (ip
, &imm_expr
);
8542 if (imm_expr
.X_add_number
> max_el
)
8543 as_bad(_("Bad element selector %ld"),
8544 (long) imm_expr
.X_add_number
);
8545 imm_expr
.X_add_number
&= max_el
;
8546 ip
->insn_opcode
|= (imm_expr
.X_add_number
8549 imm_expr
.X_op
= O_absent
;
8551 as_warn(_("Expecting ']' found '%s'"), s
);
8557 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8558 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8561 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8568 INSERT_OPERAND (FT
, *ip
, regno
);
8571 INSERT_OPERAND (FR
, *ip
, regno
);
8581 INSERT_OPERAND (FS
, *ip
, lastregno
);
8584 INSERT_OPERAND (FT
, *ip
, lastregno
);
8590 my_getExpression (&imm_expr
, s
);
8591 if (imm_expr
.X_op
!= O_big
8592 && imm_expr
.X_op
!= O_constant
)
8593 insn_error
= _("absolute expression required");
8594 normalize_constant_expr (&imm_expr
);
8599 my_getExpression (&offset_expr
, s
);
8600 *imm_reloc
= BFD_RELOC_32
;
8613 unsigned char temp
[8];
8615 unsigned int length
;
8620 /* These only appear as the last operand in an
8621 instruction, and every instruction that accepts
8622 them in any variant accepts them in all variants.
8623 This means we don't have to worry about backing out
8624 any changes if the instruction does not match.
8626 The difference between them is the size of the
8627 floating point constant and where it goes. For 'F'
8628 and 'L' the constant is 64 bits; for 'f' and 'l' it
8629 is 32 bits. Where the constant is placed is based
8630 on how the MIPS assembler does things:
8633 f -- immediate value
8636 The .lit4 and .lit8 sections are only used if
8637 permitted by the -G argument.
8639 The code below needs to know whether the target register
8640 is 32 or 64 bits wide. It relies on the fact 'f' and
8641 'F' are used with GPR-based instructions and 'l' and
8642 'L' are used with FPR-based instructions. */
8644 f64
= *args
== 'F' || *args
== 'L';
8645 using_gprs
= *args
== 'F' || *args
== 'f';
8647 save_in
= input_line_pointer
;
8648 input_line_pointer
= s
;
8649 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8651 s
= input_line_pointer
;
8652 input_line_pointer
= save_in
;
8653 if (err
!= NULL
&& *err
!= '\0')
8655 as_bad (_("Bad floating point constant: %s"), err
);
8656 memset (temp
, '\0', sizeof temp
);
8657 length
= f64
? 8 : 4;
8660 assert (length
== (unsigned) (f64
? 8 : 4));
8664 && (g_switch_value
< 4
8665 || (temp
[0] == 0 && temp
[1] == 0)
8666 || (temp
[2] == 0 && temp
[3] == 0))))
8668 imm_expr
.X_op
= O_constant
;
8669 if (! target_big_endian
)
8670 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8672 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8675 && ! mips_disable_float_construction
8676 /* Constants can only be constructed in GPRs and
8677 copied to FPRs if the GPRs are at least as wide
8678 as the FPRs. Force the constant into memory if
8679 we are using 64-bit FPRs but the GPRs are only
8682 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8683 && ((temp
[0] == 0 && temp
[1] == 0)
8684 || (temp
[2] == 0 && temp
[3] == 0))
8685 && ((temp
[4] == 0 && temp
[5] == 0)
8686 || (temp
[6] == 0 && temp
[7] == 0)))
8688 /* The value is simple enough to load with a couple of
8689 instructions. If using 32-bit registers, set
8690 imm_expr to the high order 32 bits and offset_expr to
8691 the low order 32 bits. Otherwise, set imm_expr to
8692 the entire 64 bit constant. */
8693 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8695 imm_expr
.X_op
= O_constant
;
8696 offset_expr
.X_op
= O_constant
;
8697 if (! target_big_endian
)
8699 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8700 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8704 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8705 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8707 if (offset_expr
.X_add_number
== 0)
8708 offset_expr
.X_op
= O_absent
;
8710 else if (sizeof (imm_expr
.X_add_number
) > 4)
8712 imm_expr
.X_op
= O_constant
;
8713 if (! target_big_endian
)
8714 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8716 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8720 imm_expr
.X_op
= O_big
;
8721 imm_expr
.X_add_number
= 4;
8722 if (! target_big_endian
)
8724 generic_bignum
[0] = bfd_getl16 (temp
);
8725 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8726 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8727 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8731 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8732 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8733 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8734 generic_bignum
[3] = bfd_getb16 (temp
);
8740 const char *newname
;
8743 /* Switch to the right section. */
8745 subseg
= now_subseg
;
8748 default: /* unused default case avoids warnings. */
8750 newname
= RDATA_SECTION_NAME
;
8751 if (g_switch_value
>= 8)
8755 newname
= RDATA_SECTION_NAME
;
8758 assert (g_switch_value
>= 4);
8762 new_seg
= subseg_new (newname
, (subsegT
) 0);
8763 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8764 bfd_set_section_flags (stdoutput
, new_seg
,
8769 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8770 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8771 && strcmp (TARGET_OS
, "elf") != 0)
8772 record_alignment (new_seg
, 4);
8774 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8776 as_bad (_("Can't use floating point insn in this section"));
8778 /* Set the argument to the current address in the
8780 offset_expr
.X_op
= O_symbol
;
8781 offset_expr
.X_add_symbol
=
8782 symbol_new ("L0\001", now_seg
,
8783 (valueT
) frag_now_fix (), frag_now
);
8784 offset_expr
.X_add_number
= 0;
8786 /* Put the floating point number into the section. */
8787 p
= frag_more ((int) length
);
8788 memcpy (p
, temp
, length
);
8790 /* Switch back to the original section. */
8791 subseg_set (seg
, subseg
);
8796 case 'i': /* 16 bit unsigned immediate */
8797 case 'j': /* 16 bit signed immediate */
8798 *imm_reloc
= BFD_RELOC_LO16
;
8799 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8802 offsetT minval
, maxval
;
8804 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8805 && strcmp (insn
->name
, insn
[1].name
) == 0);
8807 /* If the expression was written as an unsigned number,
8808 only treat it as signed if there are no more
8812 && sizeof (imm_expr
.X_add_number
) <= 4
8813 && imm_expr
.X_op
== O_constant
8814 && imm_expr
.X_add_number
< 0
8815 && imm_expr
.X_unsigned
8819 /* For compatibility with older assemblers, we accept
8820 0x8000-0xffff as signed 16-bit numbers when only
8821 signed numbers are allowed. */
8823 minval
= 0, maxval
= 0xffff;
8825 minval
= -0x8000, maxval
= 0x7fff;
8827 minval
= -0x8000, maxval
= 0xffff;
8829 if (imm_expr
.X_op
!= O_constant
8830 || imm_expr
.X_add_number
< minval
8831 || imm_expr
.X_add_number
> maxval
)
8835 if (imm_expr
.X_op
== O_constant
8836 || imm_expr
.X_op
== O_big
)
8837 as_bad (_("expression out of range"));
8843 case 'o': /* 16 bit offset */
8844 /* Check whether there is only a single bracketed expression
8845 left. If so, it must be the base register and the
8846 constant must be zero. */
8847 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8849 offset_expr
.X_op
= O_constant
;
8850 offset_expr
.X_add_number
= 0;
8854 /* If this value won't fit into a 16 bit offset, then go
8855 find a macro that will generate the 32 bit offset
8857 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8858 && (offset_expr
.X_op
!= O_constant
8859 || offset_expr
.X_add_number
>= 0x8000
8860 || offset_expr
.X_add_number
< -0x8000))
8866 case 'p': /* pc relative offset */
8867 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8868 my_getExpression (&offset_expr
, s
);
8872 case 'u': /* upper 16 bits */
8873 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8874 && imm_expr
.X_op
== O_constant
8875 && (imm_expr
.X_add_number
< 0
8876 || imm_expr
.X_add_number
>= 0x10000))
8877 as_bad (_("lui expression not in range 0..65535"));
8881 case 'a': /* 26 bit address */
8882 my_getExpression (&offset_expr
, s
);
8884 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8887 case 'N': /* 3 bit branch condition code */
8888 case 'M': /* 3 bit compare condition code */
8889 if (strncmp (s
, "$fcc", 4) != 0)
8899 while (ISDIGIT (*s
));
8901 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8902 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8903 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8904 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8905 && (regno
& 1) != 0)
8906 as_warn(_("Condition code register should be even for %s, was %d"),
8908 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8909 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8910 && (regno
& 3) != 0)
8911 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8914 INSERT_OPERAND (BCC
, *ip
, regno
);
8916 INSERT_OPERAND (CCC
, *ip
, regno
);
8920 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8931 while (ISDIGIT (*s
));
8934 c
= 8; /* Invalid sel value. */
8937 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8938 ip
->insn_opcode
|= c
;
8942 /* Must be at least one digit. */
8943 my_getExpression (&imm_expr
, s
);
8944 check_absolute_expr (ip
, &imm_expr
);
8946 if ((unsigned long) imm_expr
.X_add_number
8947 > (unsigned long) OP_MASK_VECBYTE
)
8949 as_bad (_("bad byte vector index (%ld)"),
8950 (long) imm_expr
.X_add_number
);
8951 imm_expr
.X_add_number
= 0;
8954 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8955 imm_expr
.X_op
= O_absent
;
8960 my_getExpression (&imm_expr
, s
);
8961 check_absolute_expr (ip
, &imm_expr
);
8963 if ((unsigned long) imm_expr
.X_add_number
8964 > (unsigned long) OP_MASK_VECALIGN
)
8966 as_bad (_("bad byte vector index (%ld)"),
8967 (long) imm_expr
.X_add_number
);
8968 imm_expr
.X_add_number
= 0;
8971 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8972 imm_expr
.X_op
= O_absent
;
8977 as_bad (_("bad char = '%c'\n"), *args
);
8982 /* Args don't match. */
8983 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8984 !strcmp (insn
->name
, insn
[1].name
))
8988 insn_error
= _("illegal operands");
8993 insn_error
= _("illegal operands");
8998 /* This routine assembles an instruction into its binary format when
8999 assembling for the mips16. As a side effect, it sets one of the
9000 global variables imm_reloc or offset_reloc to the type of
9001 relocation to do if one of the operands is an address expression.
9002 It also sets mips16_small and mips16_ext if the user explicitly
9003 requested a small or extended instruction. */
9006 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9010 struct mips_opcode
*insn
;
9013 unsigned int lastregno
= 0;
9019 mips16_small
= FALSE
;
9022 for (s
= str
; ISLOWER (*s
); ++s
)
9034 if (s
[1] == 't' && s
[2] == ' ')
9037 mips16_small
= TRUE
;
9041 else if (s
[1] == 'e' && s
[2] == ' ')
9050 insn_error
= _("unknown opcode");
9054 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9055 mips16_small
= TRUE
;
9057 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9059 insn_error
= _("unrecognized opcode");
9066 assert (strcmp (insn
->name
, str
) == 0);
9068 create_insn (ip
, insn
);
9069 imm_expr
.X_op
= O_absent
;
9070 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9071 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9072 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9073 imm2_expr
.X_op
= O_absent
;
9074 offset_expr
.X_op
= O_absent
;
9075 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9076 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9077 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9078 for (args
= insn
->args
; 1; ++args
)
9085 /* In this switch statement we call break if we did not find
9086 a match, continue if we did find a match, or return if we
9095 /* Stuff the immediate value in now, if we can. */
9096 if (imm_expr
.X_op
== O_constant
9097 && *imm_reloc
> BFD_RELOC_UNUSED
9098 && insn
->pinfo
!= INSN_MACRO
)
9102 switch (*offset_reloc
)
9104 case BFD_RELOC_MIPS16_HI16_S
:
9105 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9108 case BFD_RELOC_MIPS16_HI16
:
9109 tmp
= imm_expr
.X_add_number
>> 16;
9112 case BFD_RELOC_MIPS16_LO16
:
9113 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9117 case BFD_RELOC_UNUSED
:
9118 tmp
= imm_expr
.X_add_number
;
9124 *offset_reloc
= BFD_RELOC_UNUSED
;
9126 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9127 tmp
, TRUE
, mips16_small
,
9128 mips16_ext
, &ip
->insn_opcode
,
9129 &ip
->use_extend
, &ip
->extend
);
9130 imm_expr
.X_op
= O_absent
;
9131 *imm_reloc
= BFD_RELOC_UNUSED
;
9145 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9148 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9164 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9166 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9193 while (ISDIGIT (*s
));
9196 as_bad (_("invalid register number (%d)"), regno
);
9202 if (s
[1] == 'r' && s
[2] == 'a')
9207 else if (s
[1] == 'f' && s
[2] == 'p')
9212 else if (s
[1] == 's' && s
[2] == 'p')
9217 else if (s
[1] == 'g' && s
[2] == 'p')
9222 else if (s
[1] == 'a' && s
[2] == 't')
9227 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9232 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9237 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9250 if (c
== 'v' || c
== 'w')
9252 regno
= mips16_to_32_reg_map
[lastregno
];
9266 regno
= mips32_to_16_reg_map
[regno
];
9271 regno
= ILLEGAL_REG
;
9276 regno
= ILLEGAL_REG
;
9281 regno
= ILLEGAL_REG
;
9286 if (regno
== AT
&& ! mips_opts
.noat
)
9287 as_warn (_("used $at without \".set noat\""));
9294 if (regno
== ILLEGAL_REG
)
9301 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9305 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9308 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9311 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9317 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9320 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9321 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9331 if (strncmp (s
, "$pc", 3) == 0)
9348 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9351 if (imm_expr
.X_op
!= O_constant
)
9354 ip
->use_extend
= TRUE
;
9359 /* We need to relax this instruction. */
9360 *offset_reloc
= *imm_reloc
;
9361 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9366 *imm_reloc
= BFD_RELOC_UNUSED
;
9374 my_getExpression (&imm_expr
, s
);
9375 if (imm_expr
.X_op
== O_register
)
9377 /* What we thought was an expression turned out to
9380 if (s
[0] == '(' && args
[1] == '(')
9382 /* It looks like the expression was omitted
9383 before a register indirection, which means
9384 that the expression is implicitly zero. We
9385 still set up imm_expr, so that we handle
9386 explicit extensions correctly. */
9387 imm_expr
.X_op
= O_constant
;
9388 imm_expr
.X_add_number
= 0;
9389 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9396 /* We need to relax this instruction. */
9397 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9406 /* We use offset_reloc rather than imm_reloc for the PC
9407 relative operands. This lets macros with both
9408 immediate and address operands work correctly. */
9409 my_getExpression (&offset_expr
, s
);
9411 if (offset_expr
.X_op
== O_register
)
9414 /* We need to relax this instruction. */
9415 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9419 case '6': /* break code */
9420 my_getExpression (&imm_expr
, s
);
9421 check_absolute_expr (ip
, &imm_expr
);
9422 if ((unsigned long) imm_expr
.X_add_number
> 63)
9423 as_warn (_("Invalid value for `%s' (%lu)"),
9425 (unsigned long) imm_expr
.X_add_number
);
9426 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9427 imm_expr
.X_op
= O_absent
;
9431 case 'a': /* 26 bit address */
9432 my_getExpression (&offset_expr
, s
);
9434 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9435 ip
->insn_opcode
<<= 16;
9438 case 'l': /* register list for entry macro */
9439 case 'L': /* register list for exit macro */
9449 int freg
, reg1
, reg2
;
9451 while (*s
== ' ' || *s
== ',')
9455 as_bad (_("can't parse register list"));
9467 while (ISDIGIT (*s
))
9489 as_bad (_("invalid register list"));
9494 while (ISDIGIT (*s
))
9501 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9506 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9511 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9512 mask
|= (reg2
- 3) << 3;
9513 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9514 mask
|= (reg2
- 15) << 1;
9515 else if (reg1
== RA
&& reg2
== RA
)
9519 as_bad (_("invalid register list"));
9523 /* The mask is filled in in the opcode table for the
9524 benefit of the disassembler. We remove it before
9525 applying the actual mask. */
9526 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9527 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9531 case 'e': /* extend code */
9532 my_getExpression (&imm_expr
, s
);
9533 check_absolute_expr (ip
, &imm_expr
);
9534 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9536 as_warn (_("Invalid value for `%s' (%lu)"),
9538 (unsigned long) imm_expr
.X_add_number
);
9539 imm_expr
.X_add_number
&= 0x7ff;
9541 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9542 imm_expr
.X_op
= O_absent
;
9552 /* Args don't match. */
9553 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9554 strcmp (insn
->name
, insn
[1].name
) == 0)
9561 insn_error
= _("illegal operands");
9567 /* This structure holds information we know about a mips16 immediate
9570 struct mips16_immed_operand
9572 /* The type code used in the argument string in the opcode table. */
9574 /* The number of bits in the short form of the opcode. */
9576 /* The number of bits in the extended form of the opcode. */
9578 /* The amount by which the short form is shifted when it is used;
9579 for example, the sw instruction has a shift count of 2. */
9581 /* The amount by which the short form is shifted when it is stored
9582 into the instruction code. */
9584 /* Non-zero if the short form is unsigned. */
9586 /* Non-zero if the extended form is unsigned. */
9588 /* Non-zero if the value is PC relative. */
9592 /* The mips16 immediate operand types. */
9594 static const struct mips16_immed_operand mips16_immed_operands
[] =
9596 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9597 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9598 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9599 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9600 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9601 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9602 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9603 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9604 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9605 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9606 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9607 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9608 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9609 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9610 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9611 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9612 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9613 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9614 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9615 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9616 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9619 #define MIPS16_NUM_IMMED \
9620 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9622 /* Handle a mips16 instruction with an immediate value. This or's the
9623 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9624 whether an extended value is needed; if one is needed, it sets
9625 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9626 If SMALL is true, an unextended opcode was explicitly requested.
9627 If EXT is true, an extended opcode was explicitly requested. If
9628 WARN is true, warn if EXT does not match reality. */
9631 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9632 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9633 unsigned long *insn
, bfd_boolean
*use_extend
,
9634 unsigned short *extend
)
9636 register const struct mips16_immed_operand
*op
;
9637 int mintiny
, maxtiny
;
9638 bfd_boolean needext
;
9640 op
= mips16_immed_operands
;
9641 while (op
->type
!= type
)
9644 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9649 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9652 maxtiny
= 1 << op
->nbits
;
9657 maxtiny
= (1 << op
->nbits
) - 1;
9662 mintiny
= - (1 << (op
->nbits
- 1));
9663 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9666 /* Branch offsets have an implicit 0 in the lowest bit. */
9667 if (type
== 'p' || type
== 'q')
9670 if ((val
& ((1 << op
->shift
) - 1)) != 0
9671 || val
< (mintiny
<< op
->shift
)
9672 || val
> (maxtiny
<< op
->shift
))
9677 if (warn
&& ext
&& ! needext
)
9678 as_warn_where (file
, line
,
9679 _("extended operand requested but not required"));
9680 if (small
&& needext
)
9681 as_bad_where (file
, line
, _("invalid unextended operand value"));
9683 if (small
|| (! ext
&& ! needext
))
9687 *use_extend
= FALSE
;
9688 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9689 insnval
<<= op
->op_shift
;
9694 long minext
, maxext
;
9700 maxext
= (1 << op
->extbits
) - 1;
9704 minext
= - (1 << (op
->extbits
- 1));
9705 maxext
= (1 << (op
->extbits
- 1)) - 1;
9707 if (val
< minext
|| val
> maxext
)
9708 as_bad_where (file
, line
,
9709 _("operand value out of range for instruction"));
9712 if (op
->extbits
== 16)
9714 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9717 else if (op
->extbits
== 15)
9719 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9724 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9728 *extend
= (unsigned short) extval
;
9733 struct percent_op_match
9736 bfd_reloc_code_real_type reloc
;
9739 static const struct percent_op_match mips_percent_op
[] =
9741 {"%lo", BFD_RELOC_LO16
},
9743 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9744 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9745 {"%call16", BFD_RELOC_MIPS_CALL16
},
9746 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9747 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9748 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9749 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9750 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9751 {"%got", BFD_RELOC_MIPS_GOT16
},
9752 {"%gp_rel", BFD_RELOC_GPREL16
},
9753 {"%half", BFD_RELOC_16
},
9754 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9755 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9756 {"%neg", BFD_RELOC_MIPS_SUB
},
9757 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9758 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9759 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9760 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9761 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9762 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9763 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9765 {"%hi", BFD_RELOC_HI16_S
}
9768 static const struct percent_op_match mips16_percent_op
[] =
9770 {"%lo", BFD_RELOC_MIPS16_LO16
},
9771 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9772 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9776 /* Return true if *STR points to a relocation operator. When returning true,
9777 move *STR over the operator and store its relocation code in *RELOC.
9778 Leave both *STR and *RELOC alone when returning false. */
9781 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9783 const struct percent_op_match
*percent_op
;
9786 if (mips_opts
.mips16
)
9788 percent_op
= mips16_percent_op
;
9789 limit
= ARRAY_SIZE (mips16_percent_op
);
9793 percent_op
= mips_percent_op
;
9794 limit
= ARRAY_SIZE (mips_percent_op
);
9797 for (i
= 0; i
< limit
; i
++)
9798 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9800 int len
= strlen (percent_op
[i
].str
);
9802 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9805 *str
+= strlen (percent_op
[i
].str
);
9806 *reloc
= percent_op
[i
].reloc
;
9808 /* Check whether the output BFD supports this relocation.
9809 If not, issue an error and fall back on something safe. */
9810 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9812 as_bad ("relocation %s isn't supported by the current ABI",
9814 *reloc
= BFD_RELOC_UNUSED
;
9822 /* Parse string STR as a 16-bit relocatable operand. Store the
9823 expression in *EP and the relocations in the array starting
9824 at RELOC. Return the number of relocation operators used.
9826 On exit, EXPR_END points to the first character after the expression. */
9829 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9832 bfd_reloc_code_real_type reversed_reloc
[3];
9833 size_t reloc_index
, i
;
9834 int crux_depth
, str_depth
;
9837 /* Search for the start of the main expression, recoding relocations
9838 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9839 of the main expression and with CRUX_DEPTH containing the number
9840 of open brackets at that point. */
9847 crux_depth
= str_depth
;
9849 /* Skip over whitespace and brackets, keeping count of the number
9851 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9856 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9857 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9859 my_getExpression (ep
, crux
);
9862 /* Match every open bracket. */
9863 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9868 as_bad ("unclosed '('");
9872 if (reloc_index
!= 0)
9874 prev_reloc_op_frag
= frag_now
;
9875 for (i
= 0; i
< reloc_index
; i
++)
9876 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9883 my_getExpression (expressionS
*ep
, char *str
)
9888 save_in
= input_line_pointer
;
9889 input_line_pointer
= str
;
9891 expr_end
= input_line_pointer
;
9892 input_line_pointer
= save_in
;
9894 /* If we are in mips16 mode, and this is an expression based on `.',
9895 then we bump the value of the symbol by 1 since that is how other
9896 text symbols are handled. We don't bother to handle complex
9897 expressions, just `.' plus or minus a constant. */
9898 if (mips_opts
.mips16
9899 && ep
->X_op
== O_symbol
9900 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9901 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9902 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9903 && symbol_constant_p (ep
->X_add_symbol
)
9904 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9905 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9908 /* Turn a string in input_line_pointer into a floating point constant
9909 of type TYPE, and store the appropriate bytes in *LITP. The number
9910 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9911 returned, or NULL on OK. */
9914 md_atof (int type
, char *litP
, int *sizeP
)
9917 LITTLENUM_TYPE words
[4];
9933 return _("bad call to md_atof");
9936 t
= atof_ieee (input_line_pointer
, type
, words
);
9938 input_line_pointer
= t
;
9942 if (! target_big_endian
)
9944 for (i
= prec
- 1; i
>= 0; i
--)
9946 md_number_to_chars (litP
, words
[i
], 2);
9952 for (i
= 0; i
< prec
; i
++)
9954 md_number_to_chars (litP
, words
[i
], 2);
9963 md_number_to_chars (char *buf
, valueT val
, int n
)
9965 if (target_big_endian
)
9966 number_to_chars_bigendian (buf
, val
, n
);
9968 number_to_chars_littleendian (buf
, val
, n
);
9972 static int support_64bit_objects(void)
9974 const char **list
, **l
;
9977 list
= bfd_target_list ();
9978 for (l
= list
; *l
!= NULL
; l
++)
9980 /* This is traditional mips */
9981 if (strcmp (*l
, "elf64-tradbigmips") == 0
9982 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9984 if (strcmp (*l
, "elf64-bigmips") == 0
9985 || strcmp (*l
, "elf64-littlemips") == 0)
9992 #endif /* OBJ_ELF */
9994 const char *md_shortopts
= "O::g::G:";
9996 struct option md_longopts
[] =
9998 /* Options which specify architecture. */
9999 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10000 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10001 {"march", required_argument
, NULL
, OPTION_MARCH
},
10002 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10003 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10004 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10005 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10006 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10007 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10008 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10009 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10010 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10011 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10012 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10013 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10014 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10015 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10016 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10017 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10018 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10019 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10020 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10021 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10022 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10024 /* Options which specify Application Specific Extensions (ASEs). */
10025 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10026 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10027 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10028 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10029 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10030 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10031 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10032 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10033 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10034 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10035 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10036 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10037 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10039 /* Old-style architecture options. Don't add more of these. */
10040 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10041 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10042 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10043 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10044 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10045 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10046 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10047 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10048 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10049 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10050 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10051 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10052 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10053 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10054 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10055 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10056 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10058 /* Options which enable bug fixes. */
10059 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10060 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10061 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10062 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10063 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10064 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10065 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10066 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10067 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10068 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10070 /* Miscellaneous options. */
10071 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10072 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10073 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10074 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10075 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10076 {"break", no_argument
, NULL
, OPTION_BREAK
},
10077 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10078 #define OPTION_EB (OPTION_MISC_BASE + 2)
10079 {"EB", no_argument
, NULL
, OPTION_EB
},
10080 #define OPTION_EL (OPTION_MISC_BASE + 3)
10081 {"EL", no_argument
, NULL
, OPTION_EL
},
10082 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10083 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10084 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10085 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10086 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10087 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10088 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10089 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10090 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10091 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10092 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10093 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10094 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10095 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10096 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10097 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10098 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10099 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10100 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10101 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10102 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10103 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10104 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10105 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10107 /* ELF-specific options. */
10109 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10110 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10111 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10112 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10113 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10114 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10115 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10116 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10117 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10118 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10119 #define OPTION_32 (OPTION_ELF_BASE + 4)
10120 {"32", no_argument
, NULL
, OPTION_32
},
10121 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10122 {"n32", no_argument
, NULL
, OPTION_N32
},
10123 #define OPTION_64 (OPTION_ELF_BASE + 6)
10124 {"64", no_argument
, NULL
, OPTION_64
},
10125 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10126 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10127 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10128 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10129 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10130 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10131 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10132 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10133 #endif /* OBJ_ELF */
10135 {NULL
, no_argument
, NULL
, 0}
10137 size_t md_longopts_size
= sizeof (md_longopts
);
10139 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10140 NEW_VALUE. Warn if another value was already specified. Note:
10141 we have to defer parsing the -march and -mtune arguments in order
10142 to handle 'from-abi' correctly, since the ABI might be specified
10143 in a later argument. */
10146 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10148 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10149 as_warn (_("A different %s was already specified, is now %s"),
10150 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10153 *string_ptr
= new_value
;
10157 md_parse_option (int c
, char *arg
)
10161 case OPTION_CONSTRUCT_FLOATS
:
10162 mips_disable_float_construction
= 0;
10165 case OPTION_NO_CONSTRUCT_FLOATS
:
10166 mips_disable_float_construction
= 1;
10178 target_big_endian
= 1;
10182 target_big_endian
= 0;
10186 if (arg
&& arg
[1] == '0')
10196 mips_debug
= atoi (arg
);
10197 /* When the MIPS assembler sees -g or -g2, it does not do
10198 optimizations which limit full symbolic debugging. We take
10199 that to be equivalent to -O0. */
10200 if (mips_debug
== 2)
10205 file_mips_isa
= ISA_MIPS1
;
10209 file_mips_isa
= ISA_MIPS2
;
10213 file_mips_isa
= ISA_MIPS3
;
10217 file_mips_isa
= ISA_MIPS4
;
10221 file_mips_isa
= ISA_MIPS5
;
10224 case OPTION_MIPS32
:
10225 file_mips_isa
= ISA_MIPS32
;
10228 case OPTION_MIPS32R2
:
10229 file_mips_isa
= ISA_MIPS32R2
;
10232 case OPTION_MIPS64R2
:
10233 file_mips_isa
= ISA_MIPS64R2
;
10236 case OPTION_MIPS64
:
10237 file_mips_isa
= ISA_MIPS64
;
10241 mips_set_option_string (&mips_tune_string
, arg
);
10245 mips_set_option_string (&mips_arch_string
, arg
);
10249 mips_set_option_string (&mips_arch_string
, "4650");
10250 mips_set_option_string (&mips_tune_string
, "4650");
10253 case OPTION_NO_M4650
:
10257 mips_set_option_string (&mips_arch_string
, "4010");
10258 mips_set_option_string (&mips_tune_string
, "4010");
10261 case OPTION_NO_M4010
:
10265 mips_set_option_string (&mips_arch_string
, "4100");
10266 mips_set_option_string (&mips_tune_string
, "4100");
10269 case OPTION_NO_M4100
:
10273 mips_set_option_string (&mips_arch_string
, "3900");
10274 mips_set_option_string (&mips_tune_string
, "3900");
10277 case OPTION_NO_M3900
:
10281 mips_opts
.ase_mdmx
= 1;
10284 case OPTION_NO_MDMX
:
10285 mips_opts
.ase_mdmx
= 0;
10288 case OPTION_MIPS16
:
10289 mips_opts
.mips16
= 1;
10290 mips_no_prev_insn (FALSE
);
10293 case OPTION_NO_MIPS16
:
10294 mips_opts
.mips16
= 0;
10295 mips_no_prev_insn (FALSE
);
10298 case OPTION_MIPS3D
:
10299 mips_opts
.ase_mips3d
= 1;
10302 case OPTION_NO_MIPS3D
:
10303 mips_opts
.ase_mips3d
= 0;
10306 case OPTION_FIX_VR4120
:
10307 mips_fix_vr4120
= 1;
10310 case OPTION_NO_FIX_VR4120
:
10311 mips_fix_vr4120
= 0;
10314 case OPTION_RELAX_BRANCH
:
10315 mips_relax_branch
= 1;
10318 case OPTION_NO_RELAX_BRANCH
:
10319 mips_relax_branch
= 0;
10322 case OPTION_MSHARED
:
10323 mips_in_shared
= TRUE
;
10326 case OPTION_MNO_SHARED
:
10327 mips_in_shared
= FALSE
;
10330 case OPTION_MSYM32
:
10331 mips_opts
.sym32
= TRUE
;
10334 case OPTION_MNO_SYM32
:
10335 mips_opts
.sym32
= FALSE
;
10339 /* When generating ELF code, we permit -KPIC and -call_shared to
10340 select SVR4_PIC, and -non_shared to select no PIC. This is
10341 intended to be compatible with Irix 5. */
10342 case OPTION_CALL_SHARED
:
10343 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10345 as_bad (_("-call_shared is supported only for ELF format"));
10348 mips_pic
= SVR4_PIC
;
10349 mips_abicalls
= TRUE
;
10350 if (g_switch_seen
&& g_switch_value
!= 0)
10352 as_bad (_("-G may not be used with SVR4 PIC code"));
10355 g_switch_value
= 0;
10358 case OPTION_NON_SHARED
:
10359 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10361 as_bad (_("-non_shared is supported only for ELF format"));
10365 mips_abicalls
= FALSE
;
10368 /* The -xgot option tells the assembler to use 32 offsets when
10369 accessing the got in SVR4_PIC mode. It is for Irix
10374 #endif /* OBJ_ELF */
10377 g_switch_value
= atoi (arg
);
10379 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10381 as_bad (_("-G may not be used with SVR4 PIC code"));
10387 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10390 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10392 as_bad (_("-32 is supported for ELF format only"));
10395 mips_abi
= O32_ABI
;
10399 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10401 as_bad (_("-n32 is supported for ELF format only"));
10404 mips_abi
= N32_ABI
;
10408 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10410 as_bad (_("-64 is supported for ELF format only"));
10413 mips_abi
= N64_ABI
;
10414 if (! support_64bit_objects())
10415 as_fatal (_("No compiled in support for 64 bit object file format"));
10417 #endif /* OBJ_ELF */
10420 file_mips_gp32
= 1;
10424 file_mips_gp32
= 0;
10428 file_mips_fp32
= 1;
10432 file_mips_fp32
= 0;
10437 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10439 as_bad (_("-mabi is supported for ELF format only"));
10442 if (strcmp (arg
, "32") == 0)
10443 mips_abi
= O32_ABI
;
10444 else if (strcmp (arg
, "o64") == 0)
10445 mips_abi
= O64_ABI
;
10446 else if (strcmp (arg
, "n32") == 0)
10447 mips_abi
= N32_ABI
;
10448 else if (strcmp (arg
, "64") == 0)
10450 mips_abi
= N64_ABI
;
10451 if (! support_64bit_objects())
10452 as_fatal (_("No compiled in support for 64 bit object file "
10455 else if (strcmp (arg
, "eabi") == 0)
10456 mips_abi
= EABI_ABI
;
10459 as_fatal (_("invalid abi -mabi=%s"), arg
);
10463 #endif /* OBJ_ELF */
10465 case OPTION_M7000_HILO_FIX
:
10466 mips_7000_hilo_fix
= TRUE
;
10469 case OPTION_MNO_7000_HILO_FIX
:
10470 mips_7000_hilo_fix
= FALSE
;
10474 case OPTION_MDEBUG
:
10475 mips_flag_mdebug
= TRUE
;
10478 case OPTION_NO_MDEBUG
:
10479 mips_flag_mdebug
= FALSE
;
10483 mips_flag_pdr
= TRUE
;
10486 case OPTION_NO_PDR
:
10487 mips_flag_pdr
= FALSE
;
10489 #endif /* OBJ_ELF */
10498 /* Set up globals to generate code for the ISA or processor
10499 described by INFO. */
10502 mips_set_architecture (const struct mips_cpu_info
*info
)
10506 file_mips_arch
= info
->cpu
;
10507 mips_opts
.arch
= info
->cpu
;
10508 mips_opts
.isa
= info
->isa
;
10513 /* Likewise for tuning. */
10516 mips_set_tune (const struct mips_cpu_info
*info
)
10519 mips_tune
= info
->cpu
;
10524 mips_after_parse_args (void)
10526 const struct mips_cpu_info
*arch_info
= 0;
10527 const struct mips_cpu_info
*tune_info
= 0;
10529 /* GP relative stuff not working for PE */
10530 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10532 if (g_switch_seen
&& g_switch_value
!= 0)
10533 as_bad (_("-G not supported in this configuration."));
10534 g_switch_value
= 0;
10537 if (mips_abi
== NO_ABI
)
10538 mips_abi
= MIPS_DEFAULT_ABI
;
10540 /* The following code determines the architecture and register size.
10541 Similar code was added to GCC 3.3 (see override_options() in
10542 config/mips/mips.c). The GAS and GCC code should be kept in sync
10543 as much as possible. */
10545 if (mips_arch_string
!= 0)
10546 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10548 if (file_mips_isa
!= ISA_UNKNOWN
)
10550 /* Handle -mipsN. At this point, file_mips_isa contains the
10551 ISA level specified by -mipsN, while arch_info->isa contains
10552 the -march selection (if any). */
10553 if (arch_info
!= 0)
10555 /* -march takes precedence over -mipsN, since it is more descriptive.
10556 There's no harm in specifying both as long as the ISA levels
10558 if (file_mips_isa
!= arch_info
->isa
)
10559 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10560 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10561 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10564 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10567 if (arch_info
== 0)
10568 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10570 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10571 as_bad ("-march=%s is not compatible with the selected ABI",
10574 mips_set_architecture (arch_info
);
10576 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10577 if (mips_tune_string
!= 0)
10578 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10580 if (tune_info
== 0)
10581 mips_set_tune (arch_info
);
10583 mips_set_tune (tune_info
);
10585 if (file_mips_gp32
>= 0)
10587 /* The user specified the size of the integer registers. Make sure
10588 it agrees with the ABI and ISA. */
10589 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10590 as_bad (_("-mgp64 used with a 32-bit processor"));
10591 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10592 as_bad (_("-mgp32 used with a 64-bit ABI"));
10593 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10594 as_bad (_("-mgp64 used with a 32-bit ABI"));
10598 /* Infer the integer register size from the ABI and processor.
10599 Restrict ourselves to 32-bit registers if that's all the
10600 processor has, or if the ABI cannot handle 64-bit registers. */
10601 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10602 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10605 /* ??? GAS treats single-float processors as though they had 64-bit
10606 float registers (although it complains when double-precision
10607 instructions are used). As things stand, saying they have 32-bit
10608 registers would lead to spurious "register must be even" messages.
10609 So here we assume float registers are always the same size as
10610 integer ones, unless the user says otherwise. */
10611 if (file_mips_fp32
< 0)
10612 file_mips_fp32
= file_mips_gp32
;
10614 /* End of GCC-shared inference code. */
10616 /* This flag is set when we have a 64-bit capable CPU but use only
10617 32-bit wide registers. Note that EABI does not use it. */
10618 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10619 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10620 || mips_abi
== O32_ABI
))
10621 mips_32bitmode
= 1;
10623 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10624 as_bad (_("trap exception not supported at ISA 1"));
10626 /* If the selected architecture includes support for ASEs, enable
10627 generation of code for them. */
10628 if (mips_opts
.mips16
== -1)
10629 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10630 if (mips_opts
.ase_mips3d
== -1)
10631 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10632 if (mips_opts
.ase_mdmx
== -1)
10633 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10635 file_mips_isa
= mips_opts
.isa
;
10636 file_ase_mips16
= mips_opts
.mips16
;
10637 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10638 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10639 mips_opts
.gp32
= file_mips_gp32
;
10640 mips_opts
.fp32
= file_mips_fp32
;
10642 if (mips_flag_mdebug
< 0)
10644 #ifdef OBJ_MAYBE_ECOFF
10645 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10646 mips_flag_mdebug
= 1;
10648 #endif /* OBJ_MAYBE_ECOFF */
10649 mips_flag_mdebug
= 0;
10654 mips_init_after_args (void)
10656 /* initialize opcodes */
10657 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10658 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10662 md_pcrel_from (fixS
*fixP
)
10664 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10665 switch (fixP
->fx_r_type
)
10667 case BFD_RELOC_16_PCREL_S2
:
10668 case BFD_RELOC_MIPS_JMP
:
10669 /* Return the address of the delay slot. */
10676 /* This is called before the symbol table is processed. In order to
10677 work with gcc when using mips-tfile, we must keep all local labels.
10678 However, in other cases, we want to discard them. If we were
10679 called with -g, but we didn't see any debugging information, it may
10680 mean that gcc is smuggling debugging information through to
10681 mips-tfile, in which case we must generate all local labels. */
10684 mips_frob_file_before_adjust (void)
10686 #ifndef NO_ECOFF_DEBUGGING
10687 if (ECOFF_DEBUGGING
10689 && ! ecoff_debugging_seen
)
10690 flag_keep_locals
= 1;
10694 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10695 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10696 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10697 relocation operators.
10699 For our purposes, a %lo() expression matches a %got() or %hi()
10702 (a) it refers to the same symbol; and
10703 (b) the offset applied in the %lo() expression is no lower than
10704 the offset applied in the %got() or %hi().
10706 (b) allows us to cope with code like:
10709 lh $4,%lo(foo+2)($4)
10711 ...which is legal on RELA targets, and has a well-defined behaviour
10712 if the user knows that adding 2 to "foo" will not induce a carry to
10715 When several %lo()s match a particular %got() or %hi(), we use the
10716 following rules to distinguish them:
10718 (1) %lo()s with smaller offsets are a better match than %lo()s with
10721 (2) %lo()s with no matching %got() or %hi() are better than those
10722 that already have a matching %got() or %hi().
10724 (3) later %lo()s are better than earlier %lo()s.
10726 These rules are applied in order.
10728 (1) means, among other things, that %lo()s with identical offsets are
10729 chosen if they exist.
10731 (2) means that we won't associate several high-part relocations with
10732 the same low-part relocation unless there's no alternative. Having
10733 several high parts for the same low part is a GNU extension; this rule
10734 allows careful users to avoid it.
10736 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10737 with the last high-part relocation being at the front of the list.
10738 It therefore makes sense to choose the last matching low-part
10739 relocation, all other things being equal. It's also easier
10740 to code that way. */
10743 mips_frob_file (void)
10745 struct mips_hi_fixup
*l
;
10747 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10749 segment_info_type
*seginfo
;
10750 bfd_boolean matched_lo_p
;
10751 fixS
**hi_pos
, **lo_pos
, **pos
;
10753 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10755 /* If a GOT16 relocation turns out to be against a global symbol,
10756 there isn't supposed to be a matching LO. */
10757 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10758 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10761 /* Check quickly whether the next fixup happens to be a matching %lo. */
10762 if (fixup_has_matching_lo_p (l
->fixp
))
10765 seginfo
= seg_info (l
->seg
);
10767 /* Set HI_POS to the position of this relocation in the chain.
10768 Set LO_POS to the position of the chosen low-part relocation.
10769 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10770 relocation that matches an immediately-preceding high-part
10774 matched_lo_p
= FALSE
;
10775 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10777 if (*pos
== l
->fixp
)
10780 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10781 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10782 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10784 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10786 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10789 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10790 && fixup_has_matching_lo_p (*pos
));
10793 /* If we found a match, remove the high-part relocation from its
10794 current position and insert it before the low-part relocation.
10795 Make the offsets match so that fixup_has_matching_lo_p()
10798 We don't warn about unmatched high-part relocations since some
10799 versions of gcc have been known to emit dead "lui ...%hi(...)"
10801 if (lo_pos
!= NULL
)
10803 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10804 if (l
->fixp
->fx_next
!= *lo_pos
)
10806 *hi_pos
= l
->fixp
->fx_next
;
10807 l
->fixp
->fx_next
= *lo_pos
;
10814 /* We may have combined relocations without symbols in the N32/N64 ABI.
10815 We have to prevent gas from dropping them. */
10818 mips_force_relocation (fixS
*fixp
)
10820 if (generic_force_reloc (fixp
))
10824 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10825 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10826 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10827 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10833 /* This hook is called before a fix is simplified. We don't really
10834 decide whether to skip a fix here. Rather, we turn global symbols
10835 used as branch targets into local symbols, such that they undergo
10836 simplification. We can only do this if the symbol is defined and
10837 it is in the same section as the branch. If this doesn't hold, we
10838 emit a better error message than just saying the relocation is not
10839 valid for the selected object format.
10841 FIXP is the fix-up we're going to try to simplify, SEG is the
10842 segment in which the fix up occurs. The return value should be
10843 non-zero to indicate the fix-up is valid for further
10844 simplifications. */
10847 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10849 /* There's a lot of discussion on whether it should be possible to
10850 use R_MIPS_PC16 to represent branch relocations. The outcome
10851 seems to be that it can, but gas/bfd are very broken in creating
10852 RELA relocations for this, so for now we only accept branches to
10853 symbols in the same section. Anything else is of dubious value,
10854 since there's no guarantee that at link time the symbol would be
10855 in range. Even for branches to local symbols this is arguably
10856 wrong, since it we assume the symbol is not going to be
10857 overridden, which should be possible per ELF library semantics,
10858 but then, there isn't a dynamic relocation that could be used to
10859 this effect, and the target would likely be out of range as well.
10861 Unfortunately, it seems that there is too much code out there
10862 that relies on branches to symbols that are global to be resolved
10863 as if they were local, like the IRIX tools do, so we do it as
10864 well, but with a warning so that people are reminded to fix their
10865 code. If we ever get back to using R_MIPS_PC16 for branch
10866 targets, this entire block should go away (and probably the
10867 whole function). */
10869 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10870 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10871 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10872 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10875 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10878 _("Cannot branch to undefined symbol."));
10879 /* Avoid any further errors about this fixup. */
10882 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10885 _("Cannot branch to symbol in another section."));
10888 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10890 symbolS
*sym
= fixP
->fx_addsy
;
10892 if (mips_pic
== SVR4_PIC
)
10893 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10894 _("Pretending global symbol used as branch target is local."));
10896 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10897 S_GET_SEGMENT (sym
),
10899 symbol_get_frag (sym
));
10900 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10901 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10902 assert (symbol_resolved_p (sym
));
10903 symbol_mark_resolved (fixP
->fx_addsy
);
10910 /* Apply a fixup to the object file. */
10913 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10917 reloc_howto_type
*howto
;
10919 /* We ignore generic BFD relocations we don't know about. */
10920 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10924 assert (fixP
->fx_size
== 4
10925 || fixP
->fx_r_type
== BFD_RELOC_16
10926 || fixP
->fx_r_type
== BFD_RELOC_64
10927 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10928 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10929 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10930 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10932 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10934 assert (! fixP
->fx_pcrel
);
10936 /* Don't treat parts of a composite relocation as done. There are two
10939 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10940 should nevertheless be emitted if the first part is.
10942 (2) In normal usage, composite relocations are never assembly-time
10943 constants. The easiest way of dealing with the pathological
10944 exceptions is to generate a relocation against STN_UNDEF and
10945 leave everything up to the linker. */
10946 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10949 switch (fixP
->fx_r_type
)
10951 case BFD_RELOC_MIPS_TLS_GD
:
10952 case BFD_RELOC_MIPS_TLS_LDM
:
10953 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10954 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10955 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10956 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10957 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10958 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10961 case BFD_RELOC_MIPS_JMP
:
10962 case BFD_RELOC_MIPS_SHIFT5
:
10963 case BFD_RELOC_MIPS_SHIFT6
:
10964 case BFD_RELOC_MIPS_GOT_DISP
:
10965 case BFD_RELOC_MIPS_GOT_PAGE
:
10966 case BFD_RELOC_MIPS_GOT_OFST
:
10967 case BFD_RELOC_MIPS_SUB
:
10968 case BFD_RELOC_MIPS_INSERT_A
:
10969 case BFD_RELOC_MIPS_INSERT_B
:
10970 case BFD_RELOC_MIPS_DELETE
:
10971 case BFD_RELOC_MIPS_HIGHEST
:
10972 case BFD_RELOC_MIPS_HIGHER
:
10973 case BFD_RELOC_MIPS_SCN_DISP
:
10974 case BFD_RELOC_MIPS_REL16
:
10975 case BFD_RELOC_MIPS_RELGOT
:
10976 case BFD_RELOC_MIPS_JALR
:
10977 case BFD_RELOC_HI16
:
10978 case BFD_RELOC_HI16_S
:
10979 case BFD_RELOC_GPREL16
:
10980 case BFD_RELOC_MIPS_LITERAL
:
10981 case BFD_RELOC_MIPS_CALL16
:
10982 case BFD_RELOC_MIPS_GOT16
:
10983 case BFD_RELOC_GPREL32
:
10984 case BFD_RELOC_MIPS_GOT_HI16
:
10985 case BFD_RELOC_MIPS_GOT_LO16
:
10986 case BFD_RELOC_MIPS_CALL_HI16
:
10987 case BFD_RELOC_MIPS_CALL_LO16
:
10988 case BFD_RELOC_MIPS16_GPREL
:
10989 case BFD_RELOC_MIPS16_HI16
:
10990 case BFD_RELOC_MIPS16_HI16_S
:
10991 assert (! fixP
->fx_pcrel
);
10992 /* Nothing needed to do. The value comes from the reloc entry */
10995 case BFD_RELOC_MIPS16_JMP
:
10996 /* We currently always generate a reloc against a symbol, which
10997 means that we don't want an addend even if the symbol is
11003 /* This is handled like BFD_RELOC_32, but we output a sign
11004 extended value if we are only 32 bits. */
11007 if (8 <= sizeof (valueT
))
11008 md_number_to_chars ((char *) buf
, *valP
, 8);
11013 if ((*valP
& 0x80000000) != 0)
11017 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11019 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11025 case BFD_RELOC_RVA
:
11027 /* If we are deleting this reloc entry, we must fill in the
11028 value now. This can happen if we have a .word which is not
11029 resolved when it appears but is later defined. */
11031 md_number_to_chars ((char *) buf
, *valP
, 4);
11035 /* If we are deleting this reloc entry, we must fill in the
11038 md_number_to_chars ((char *) buf
, *valP
, 2);
11041 case BFD_RELOC_LO16
:
11042 case BFD_RELOC_MIPS16_LO16
:
11043 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11044 may be safe to remove, but if so it's not obvious. */
11045 /* When handling an embedded PIC switch statement, we can wind
11046 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11049 if (*valP
+ 0x8000 > 0xffff)
11050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11051 _("relocation overflow"));
11052 if (target_big_endian
)
11054 md_number_to_chars ((char *) buf
, *valP
, 2);
11058 case BFD_RELOC_16_PCREL_S2
:
11059 if ((*valP
& 0x3) != 0)
11060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11061 _("Branch to odd address (%lx)"), (long) *valP
);
11064 * We need to save the bits in the instruction since fixup_segment()
11065 * might be deleting the relocation entry (i.e., a branch within
11066 * the current segment).
11068 if (! fixP
->fx_done
)
11071 /* update old instruction data */
11072 if (target_big_endian
)
11073 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11075 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11077 if (*valP
+ 0x20000 <= 0x3ffff)
11079 insn
|= (*valP
>> 2) & 0xffff;
11080 md_number_to_chars ((char *) buf
, insn
, 4);
11082 else if (mips_pic
== NO_PIC
11084 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11085 && (fixP
->fx_frag
->fr_address
11086 < text_section
->vma
+ bfd_get_section_size (text_section
))
11087 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11088 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11089 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11091 /* The branch offset is too large. If this is an
11092 unconditional branch, and we are not generating PIC code,
11093 we can convert it to an absolute jump instruction. */
11094 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11095 insn
= 0x0c000000; /* jal */
11097 insn
= 0x08000000; /* j */
11098 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11100 fixP
->fx_addsy
= section_symbol (text_section
);
11101 *valP
+= md_pcrel_from (fixP
);
11102 md_number_to_chars ((char *) buf
, insn
, 4);
11106 /* If we got here, we have branch-relaxation disabled,
11107 and there's nothing we can do to fix this instruction
11108 without turning it into a longer sequence. */
11109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11110 _("Branch out of range"));
11114 case BFD_RELOC_VTABLE_INHERIT
:
11117 && !S_IS_DEFINED (fixP
->fx_addsy
)
11118 && !S_IS_WEAK (fixP
->fx_addsy
))
11119 S_SET_WEAK (fixP
->fx_addsy
);
11122 case BFD_RELOC_VTABLE_ENTRY
:
11130 /* Remember value for tc_gen_reloc. */
11131 fixP
->fx_addnumber
= *valP
;
11141 name
= input_line_pointer
;
11142 c
= get_symbol_end ();
11143 p
= (symbolS
*) symbol_find_or_make (name
);
11144 *input_line_pointer
= c
;
11148 /* Align the current frag to a given power of two. The MIPS assembler
11149 also automatically adjusts any preceding label. */
11152 mips_align (int to
, int fill
, symbolS
*label
)
11154 mips_emit_delays (FALSE
);
11155 frag_align (to
, fill
, 0);
11156 record_alignment (now_seg
, to
);
11159 assert (S_GET_SEGMENT (label
) == now_seg
);
11160 symbol_set_frag (label
, frag_now
);
11161 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11165 /* Align to a given power of two. .align 0 turns off the automatic
11166 alignment used by the data creating pseudo-ops. */
11169 s_align (int x ATTRIBUTE_UNUSED
)
11172 register long temp_fill
;
11173 long max_alignment
= 15;
11177 o Note that the assembler pulls down any immediately preceding label
11178 to the aligned address.
11179 o It's not documented but auto alignment is reinstated by
11180 a .align pseudo instruction.
11181 o Note also that after auto alignment is turned off the mips assembler
11182 issues an error on attempt to assemble an improperly aligned data item.
11187 temp
= get_absolute_expression ();
11188 if (temp
> max_alignment
)
11189 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11192 as_warn (_("Alignment negative: 0 assumed."));
11195 if (*input_line_pointer
== ',')
11197 ++input_line_pointer
;
11198 temp_fill
= get_absolute_expression ();
11205 mips_align (temp
, (int) temp_fill
,
11206 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11213 demand_empty_rest_of_line ();
11217 mips_flush_pending_output (void)
11219 mips_emit_delays (FALSE
);
11220 mips_clear_insn_labels ();
11224 s_change_sec (int sec
)
11229 /* The ELF backend needs to know that we are changing sections, so
11230 that .previous works correctly. We could do something like check
11231 for an obj_section_change_hook macro, but that might be confusing
11232 as it would not be appropriate to use it in the section changing
11233 functions in read.c, since obj-elf.c intercepts those. FIXME:
11234 This should be cleaner, somehow. */
11235 obj_elf_section_change_hook ();
11238 mips_emit_delays (FALSE
);
11248 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11249 demand_empty_rest_of_line ();
11253 seg
= subseg_new (RDATA_SECTION_NAME
,
11254 (subsegT
) get_absolute_expression ());
11255 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11257 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11258 | SEC_READONLY
| SEC_RELOC
11260 if (strcmp (TARGET_OS
, "elf") != 0)
11261 record_alignment (seg
, 4);
11263 demand_empty_rest_of_line ();
11267 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11268 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11270 bfd_set_section_flags (stdoutput
, seg
,
11271 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11272 if (strcmp (TARGET_OS
, "elf") != 0)
11273 record_alignment (seg
, 4);
11275 demand_empty_rest_of_line ();
11283 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11286 char *section_name
;
11291 int section_entry_size
;
11292 int section_alignment
;
11294 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11297 section_name
= input_line_pointer
;
11298 c
= get_symbol_end ();
11300 next_c
= *(input_line_pointer
+ 1);
11302 /* Do we have .section Name<,"flags">? */
11303 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11305 /* just after name is now '\0'. */
11306 *input_line_pointer
= c
;
11307 input_line_pointer
= section_name
;
11308 obj_elf_section (ignore
);
11311 input_line_pointer
++;
11313 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11315 section_type
= get_absolute_expression ();
11318 if (*input_line_pointer
++ == ',')
11319 section_flag
= get_absolute_expression ();
11322 if (*input_line_pointer
++ == ',')
11323 section_entry_size
= get_absolute_expression ();
11325 section_entry_size
= 0;
11326 if (*input_line_pointer
++ == ',')
11327 section_alignment
= get_absolute_expression ();
11329 section_alignment
= 0;
11331 section_name
= xstrdup (section_name
);
11333 /* When using the generic form of .section (as implemented by obj-elf.c),
11334 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11335 traditionally had to fall back on the more common @progbits instead.
11337 There's nothing really harmful in this, since bfd will correct
11338 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11339 means that, for backwards compatibiltiy, the special_section entries
11340 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11342 Even so, we shouldn't force users of the MIPS .section syntax to
11343 incorrectly label the sections as SHT_PROGBITS. The best compromise
11344 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11345 generic type-checking code. */
11346 if (section_type
== SHT_MIPS_DWARF
)
11347 section_type
= SHT_PROGBITS
;
11349 obj_elf_change_section (section_name
, section_type
, section_flag
,
11350 section_entry_size
, 0, 0, 0);
11352 if (now_seg
->name
!= section_name
)
11353 free (section_name
);
11354 #endif /* OBJ_ELF */
11358 mips_enable_auto_align (void)
11364 s_cons (int log_size
)
11368 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11369 mips_emit_delays (FALSE
);
11370 if (log_size
> 0 && auto_align
)
11371 mips_align (log_size
, 0, label
);
11372 mips_clear_insn_labels ();
11373 cons (1 << log_size
);
11377 s_float_cons (int type
)
11381 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11383 mips_emit_delays (FALSE
);
11388 mips_align (3, 0, label
);
11390 mips_align (2, 0, label
);
11393 mips_clear_insn_labels ();
11398 /* Handle .globl. We need to override it because on Irix 5 you are
11401 where foo is an undefined symbol, to mean that foo should be
11402 considered to be the address of a function. */
11405 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11412 name
= input_line_pointer
;
11413 c
= get_symbol_end ();
11414 symbolP
= symbol_find_or_make (name
);
11415 *input_line_pointer
= c
;
11416 SKIP_WHITESPACE ();
11418 /* On Irix 5, every global symbol that is not explicitly labelled as
11419 being a function is apparently labelled as being an object. */
11422 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11427 secname
= input_line_pointer
;
11428 c
= get_symbol_end ();
11429 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11431 as_bad (_("%s: no such section"), secname
);
11432 *input_line_pointer
= c
;
11434 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11435 flag
= BSF_FUNCTION
;
11438 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11440 S_SET_EXTERNAL (symbolP
);
11441 demand_empty_rest_of_line ();
11445 s_option (int x ATTRIBUTE_UNUSED
)
11450 opt
= input_line_pointer
;
11451 c
= get_symbol_end ();
11455 /* FIXME: What does this mean? */
11457 else if (strncmp (opt
, "pic", 3) == 0)
11461 i
= atoi (opt
+ 3);
11466 mips_pic
= SVR4_PIC
;
11467 mips_abicalls
= TRUE
;
11470 as_bad (_(".option pic%d not supported"), i
);
11472 if (mips_pic
== SVR4_PIC
)
11474 if (g_switch_seen
&& g_switch_value
!= 0)
11475 as_warn (_("-G may not be used with SVR4 PIC code"));
11476 g_switch_value
= 0;
11477 bfd_set_gp_size (stdoutput
, 0);
11481 as_warn (_("Unrecognized option \"%s\""), opt
);
11483 *input_line_pointer
= c
;
11484 demand_empty_rest_of_line ();
11487 /* This structure is used to hold a stack of .set values. */
11489 struct mips_option_stack
11491 struct mips_option_stack
*next
;
11492 struct mips_set_options options
;
11495 static struct mips_option_stack
*mips_opts_stack
;
11497 /* Handle the .set pseudo-op. */
11500 s_mipsset (int x ATTRIBUTE_UNUSED
)
11502 char *name
= input_line_pointer
, ch
;
11504 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11505 ++input_line_pointer
;
11506 ch
= *input_line_pointer
;
11507 *input_line_pointer
= '\0';
11509 if (strcmp (name
, "reorder") == 0)
11511 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11513 /* If we still have pending nops, we can discard them. The
11514 usual nop handling will insert any that are still
11516 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11517 * (mips_opts
.mips16
? 2 : 4));
11518 prev_nop_frag
= NULL
;
11520 mips_opts
.noreorder
= 0;
11522 else if (strcmp (name
, "noreorder") == 0)
11524 mips_emit_delays (TRUE
);
11525 mips_opts
.noreorder
= 1;
11526 mips_any_noreorder
= 1;
11528 else if (strcmp (name
, "at") == 0)
11530 mips_opts
.noat
= 0;
11532 else if (strcmp (name
, "noat") == 0)
11534 mips_opts
.noat
= 1;
11536 else if (strcmp (name
, "macro") == 0)
11538 mips_opts
.warn_about_macros
= 0;
11540 else if (strcmp (name
, "nomacro") == 0)
11542 if (mips_opts
.noreorder
== 0)
11543 as_bad (_("`noreorder' must be set before `nomacro'"));
11544 mips_opts
.warn_about_macros
= 1;
11546 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11548 mips_opts
.nomove
= 0;
11550 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11552 mips_opts
.nomove
= 1;
11554 else if (strcmp (name
, "bopt") == 0)
11556 mips_opts
.nobopt
= 0;
11558 else if (strcmp (name
, "nobopt") == 0)
11560 mips_opts
.nobopt
= 1;
11562 else if (strcmp (name
, "mips16") == 0
11563 || strcmp (name
, "MIPS-16") == 0)
11564 mips_opts
.mips16
= 1;
11565 else if (strcmp (name
, "nomips16") == 0
11566 || strcmp (name
, "noMIPS-16") == 0)
11567 mips_opts
.mips16
= 0;
11568 else if (strcmp (name
, "mips3d") == 0)
11569 mips_opts
.ase_mips3d
= 1;
11570 else if (strcmp (name
, "nomips3d") == 0)
11571 mips_opts
.ase_mips3d
= 0;
11572 else if (strcmp (name
, "mdmx") == 0)
11573 mips_opts
.ase_mdmx
= 1;
11574 else if (strcmp (name
, "nomdmx") == 0)
11575 mips_opts
.ase_mdmx
= 0;
11576 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11580 /* Permit the user to change the ISA and architecture on the fly.
11581 Needless to say, misuse can cause serious problems. */
11582 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11585 mips_opts
.isa
= file_mips_isa
;
11586 mips_opts
.arch
= file_mips_arch
;
11588 else if (strncmp (name
, "arch=", 5) == 0)
11590 const struct mips_cpu_info
*p
;
11592 p
= mips_parse_cpu("internal use", name
+ 5);
11594 as_bad (_("unknown architecture %s"), name
+ 5);
11597 mips_opts
.arch
= p
->cpu
;
11598 mips_opts
.isa
= p
->isa
;
11601 else if (strncmp (name
, "mips", 4) == 0)
11603 const struct mips_cpu_info
*p
;
11605 p
= mips_parse_cpu("internal use", name
);
11607 as_bad (_("unknown ISA level %s"), name
+ 4);
11610 mips_opts
.arch
= p
->cpu
;
11611 mips_opts
.isa
= p
->isa
;
11615 as_bad (_("unknown ISA or architecture %s"), name
);
11617 switch (mips_opts
.isa
)
11625 mips_opts
.gp32
= 1;
11626 mips_opts
.fp32
= 1;
11633 mips_opts
.gp32
= 0;
11634 mips_opts
.fp32
= 0;
11637 as_bad (_("unknown ISA level %s"), name
+ 4);
11642 mips_opts
.gp32
= file_mips_gp32
;
11643 mips_opts
.fp32
= file_mips_fp32
;
11646 else if (strcmp (name
, "autoextend") == 0)
11647 mips_opts
.noautoextend
= 0;
11648 else if (strcmp (name
, "noautoextend") == 0)
11649 mips_opts
.noautoextend
= 1;
11650 else if (strcmp (name
, "push") == 0)
11652 struct mips_option_stack
*s
;
11654 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11655 s
->next
= mips_opts_stack
;
11656 s
->options
= mips_opts
;
11657 mips_opts_stack
= s
;
11659 else if (strcmp (name
, "pop") == 0)
11661 struct mips_option_stack
*s
;
11663 s
= mips_opts_stack
;
11665 as_bad (_(".set pop with no .set push"));
11668 /* If we're changing the reorder mode we need to handle
11669 delay slots correctly. */
11670 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11671 mips_emit_delays (TRUE
);
11672 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11674 if (prev_nop_frag
!= NULL
)
11676 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11677 * (mips_opts
.mips16
? 2 : 4));
11678 prev_nop_frag
= NULL
;
11682 mips_opts
= s
->options
;
11683 mips_opts_stack
= s
->next
;
11687 else if (strcmp (name
, "sym32") == 0)
11688 mips_opts
.sym32
= TRUE
;
11689 else if (strcmp (name
, "nosym32") == 0)
11690 mips_opts
.sym32
= FALSE
;
11693 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11695 *input_line_pointer
= ch
;
11696 demand_empty_rest_of_line ();
11699 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11700 .option pic2. It means to generate SVR4 PIC calls. */
11703 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11705 mips_pic
= SVR4_PIC
;
11706 mips_abicalls
= TRUE
;
11708 if (g_switch_seen
&& g_switch_value
!= 0)
11709 as_warn (_("-G may not be used with SVR4 PIC code"));
11710 g_switch_value
= 0;
11712 bfd_set_gp_size (stdoutput
, 0);
11713 demand_empty_rest_of_line ();
11716 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11717 PIC code. It sets the $gp register for the function based on the
11718 function address, which is in the register named in the argument.
11719 This uses a relocation against _gp_disp, which is handled specially
11720 by the linker. The result is:
11721 lui $gp,%hi(_gp_disp)
11722 addiu $gp,$gp,%lo(_gp_disp)
11723 addu $gp,$gp,.cpload argument
11724 The .cpload argument is normally $25 == $t9.
11726 The -mno-shared option changes this to:
11727 lui $gp,%hi(__gnu_local_gp)
11728 addiu $gp,$gp,%lo(__gnu_local_gp)
11729 and the argument is ignored. This saves an instruction, but the
11730 resulting code is not position independent; it uses an absolute
11731 address for __gnu_local_gp. Thus code assembled with -mno-shared
11732 can go into an ordinary executable, but not into a shared library. */
11735 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11741 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11742 .cpload is ignored. */
11743 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11749 /* .cpload should be in a .set noreorder section. */
11750 if (mips_opts
.noreorder
== 0)
11751 as_warn (_(".cpload not in noreorder section"));
11753 reg
= tc_get_register (0);
11755 /* If we need to produce a 64-bit address, we are better off using
11756 the default instruction sequence. */
11757 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11759 ex
.X_op
= O_symbol
;
11760 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11762 ex
.X_op_symbol
= NULL
;
11763 ex
.X_add_number
= 0;
11765 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11766 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11769 macro_build_lui (&ex
, mips_gp_register
);
11770 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11771 mips_gp_register
, BFD_RELOC_LO16
);
11773 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11774 mips_gp_register
, reg
);
11777 demand_empty_rest_of_line ();
11780 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11781 .cpsetup $reg1, offset|$reg2, label
11783 If offset is given, this results in:
11784 sd $gp, offset($sp)
11785 lui $gp, %hi(%neg(%gp_rel(label)))
11786 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11787 daddu $gp, $gp, $reg1
11789 If $reg2 is given, this results in:
11790 daddu $reg2, $gp, $0
11791 lui $gp, %hi(%neg(%gp_rel(label)))
11792 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11793 daddu $gp, $gp, $reg1
11794 $reg1 is normally $25 == $t9.
11796 The -mno-shared option replaces the last three instructions with
11798 addiu $gp,$gp,%lo(_gp)
11802 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11804 expressionS ex_off
;
11805 expressionS ex_sym
;
11808 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11809 We also need NewABI support. */
11810 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11816 reg1
= tc_get_register (0);
11817 SKIP_WHITESPACE ();
11818 if (*input_line_pointer
!= ',')
11820 as_bad (_("missing argument separator ',' for .cpsetup"));
11824 ++input_line_pointer
;
11825 SKIP_WHITESPACE ();
11826 if (*input_line_pointer
== '$')
11828 mips_cpreturn_register
= tc_get_register (0);
11829 mips_cpreturn_offset
= -1;
11833 mips_cpreturn_offset
= get_absolute_expression ();
11834 mips_cpreturn_register
= -1;
11836 SKIP_WHITESPACE ();
11837 if (*input_line_pointer
!= ',')
11839 as_bad (_("missing argument separator ',' for .cpsetup"));
11843 ++input_line_pointer
;
11844 SKIP_WHITESPACE ();
11845 expression (&ex_sym
);
11848 if (mips_cpreturn_register
== -1)
11850 ex_off
.X_op
= O_constant
;
11851 ex_off
.X_add_symbol
= NULL
;
11852 ex_off
.X_op_symbol
= NULL
;
11853 ex_off
.X_add_number
= mips_cpreturn_offset
;
11855 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11856 BFD_RELOC_LO16
, SP
);
11859 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11860 mips_gp_register
, 0);
11862 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11864 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11865 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11868 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11869 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11870 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11872 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11873 mips_gp_register
, reg1
);
11879 ex
.X_op
= O_symbol
;
11880 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11881 ex
.X_op_symbol
= NULL
;
11882 ex
.X_add_number
= 0;
11884 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11885 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11887 macro_build_lui (&ex
, mips_gp_register
);
11888 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11889 mips_gp_register
, BFD_RELOC_LO16
);
11894 demand_empty_rest_of_line ();
11898 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11900 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11901 .cplocal is ignored. */
11902 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11908 mips_gp_register
= tc_get_register (0);
11909 demand_empty_rest_of_line ();
11912 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11913 offset from $sp. The offset is remembered, and after making a PIC
11914 call $gp is restored from that location. */
11917 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11921 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11922 .cprestore is ignored. */
11923 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11929 mips_cprestore_offset
= get_absolute_expression ();
11930 mips_cprestore_valid
= 1;
11932 ex
.X_op
= O_constant
;
11933 ex
.X_add_symbol
= NULL
;
11934 ex
.X_op_symbol
= NULL
;
11935 ex
.X_add_number
= mips_cprestore_offset
;
11938 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11939 SP
, HAVE_64BIT_ADDRESSES
);
11942 demand_empty_rest_of_line ();
11945 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11946 was given in the preceding .cpsetup, it results in:
11947 ld $gp, offset($sp)
11949 If a register $reg2 was given there, it results in:
11950 daddu $gp, $reg2, $0
11953 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11957 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11958 We also need NewABI support. */
11959 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11966 if (mips_cpreturn_register
== -1)
11968 ex
.X_op
= O_constant
;
11969 ex
.X_add_symbol
= NULL
;
11970 ex
.X_op_symbol
= NULL
;
11971 ex
.X_add_number
= mips_cpreturn_offset
;
11973 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11976 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11977 mips_cpreturn_register
, 0);
11980 demand_empty_rest_of_line ();
11983 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11984 code. It sets the offset to use in gp_rel relocations. */
11987 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11989 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11990 We also need NewABI support. */
11991 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11997 mips_gprel_offset
= get_absolute_expression ();
11999 demand_empty_rest_of_line ();
12002 /* Handle the .gpword pseudo-op. This is used when generating PIC
12003 code. It generates a 32 bit GP relative reloc. */
12006 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12012 /* When not generating PIC code, this is treated as .word. */
12013 if (mips_pic
!= SVR4_PIC
)
12019 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12020 mips_emit_delays (TRUE
);
12022 mips_align (2, 0, label
);
12023 mips_clear_insn_labels ();
12027 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12029 as_bad (_("Unsupported use of .gpword"));
12030 ignore_rest_of_line ();
12034 md_number_to_chars (p
, 0, 4);
12035 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12036 BFD_RELOC_GPREL32
);
12038 demand_empty_rest_of_line ();
12042 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12048 /* When not generating PIC code, this is treated as .dword. */
12049 if (mips_pic
!= SVR4_PIC
)
12055 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12056 mips_emit_delays (TRUE
);
12058 mips_align (3, 0, label
);
12059 mips_clear_insn_labels ();
12063 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12065 as_bad (_("Unsupported use of .gpdword"));
12066 ignore_rest_of_line ();
12070 md_number_to_chars (p
, 0, 8);
12071 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12072 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12074 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12075 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12076 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12078 demand_empty_rest_of_line ();
12081 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12082 tables in SVR4 PIC code. */
12085 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12089 /* This is ignored when not generating SVR4 PIC code. */
12090 if (mips_pic
!= SVR4_PIC
)
12096 /* Add $gp to the register named as an argument. */
12098 reg
= tc_get_register (0);
12099 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12102 demand_empty_rest_of_line ();
12105 /* Handle the .insn pseudo-op. This marks instruction labels in
12106 mips16 mode. This permits the linker to handle them specially,
12107 such as generating jalx instructions when needed. We also make
12108 them odd for the duration of the assembly, in order to generate the
12109 right sort of code. We will make them even in the adjust_symtab
12110 routine, while leaving them marked. This is convenient for the
12111 debugger and the disassembler. The linker knows to make them odd
12115 s_insn (int ignore ATTRIBUTE_UNUSED
)
12117 mips16_mark_labels ();
12119 demand_empty_rest_of_line ();
12122 /* Handle a .stabn directive. We need these in order to mark a label
12123 as being a mips16 text label correctly. Sometimes the compiler
12124 will emit a label, followed by a .stabn, and then switch sections.
12125 If the label and .stabn are in mips16 mode, then the label is
12126 really a mips16 text label. */
12129 s_mips_stab (int type
)
12132 mips16_mark_labels ();
12137 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12141 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12148 name
= input_line_pointer
;
12149 c
= get_symbol_end ();
12150 symbolP
= symbol_find_or_make (name
);
12151 S_SET_WEAK (symbolP
);
12152 *input_line_pointer
= c
;
12154 SKIP_WHITESPACE ();
12156 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12158 if (S_IS_DEFINED (symbolP
))
12160 as_bad ("ignoring attempt to redefine symbol %s",
12161 S_GET_NAME (symbolP
));
12162 ignore_rest_of_line ();
12166 if (*input_line_pointer
== ',')
12168 ++input_line_pointer
;
12169 SKIP_WHITESPACE ();
12173 if (exp
.X_op
!= O_symbol
)
12175 as_bad ("bad .weakext directive");
12176 ignore_rest_of_line ();
12179 symbol_set_value_expression (symbolP
, &exp
);
12182 demand_empty_rest_of_line ();
12185 /* Parse a register string into a number. Called from the ECOFF code
12186 to parse .frame. The argument is non-zero if this is the frame
12187 register, so that we can record it in mips_frame_reg. */
12190 tc_get_register (int frame
)
12194 SKIP_WHITESPACE ();
12195 if (*input_line_pointer
++ != '$')
12197 as_warn (_("expected `$'"));
12200 else if (ISDIGIT (*input_line_pointer
))
12202 reg
= get_absolute_expression ();
12203 if (reg
< 0 || reg
>= 32)
12205 as_warn (_("Bad register number"));
12211 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12214 input_line_pointer
+= 2;
12216 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12219 input_line_pointer
+= 2;
12221 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12224 input_line_pointer
+= 2;
12226 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12229 input_line_pointer
+= 2;
12231 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12234 input_line_pointer
+= 2;
12236 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12239 input_line_pointer
+= 3;
12241 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12244 input_line_pointer
+= 3;
12246 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12249 input_line_pointer
+= 4;
12253 as_warn (_("Unrecognized register name"));
12255 while (ISALNUM(*input_line_pointer
))
12256 input_line_pointer
++;
12261 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12262 mips_frame_reg_valid
= 1;
12263 mips_cprestore_valid
= 0;
12269 md_section_align (asection
*seg
, valueT addr
)
12271 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12274 /* We don't need to align ELF sections to the full alignment.
12275 However, Irix 5 may prefer that we align them at least to a 16
12276 byte boundary. We don't bother to align the sections if we are
12277 targeted for an embedded system. */
12278 if (strcmp (TARGET_OS
, "elf") == 0)
12284 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12287 /* Utility routine, called from above as well. If called while the
12288 input file is still being read, it's only an approximation. (For
12289 example, a symbol may later become defined which appeared to be
12290 undefined earlier.) */
12293 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12298 if (g_switch_value
> 0)
12300 const char *symname
;
12303 /* Find out whether this symbol can be referenced off the $gp
12304 register. It can be if it is smaller than the -G size or if
12305 it is in the .sdata or .sbss section. Certain symbols can
12306 not be referenced off the $gp, although it appears as though
12308 symname
= S_GET_NAME (sym
);
12309 if (symname
!= (const char *) NULL
12310 && (strcmp (symname
, "eprol") == 0
12311 || strcmp (symname
, "etext") == 0
12312 || strcmp (symname
, "_gp") == 0
12313 || strcmp (symname
, "edata") == 0
12314 || strcmp (symname
, "_fbss") == 0
12315 || strcmp (symname
, "_fdata") == 0
12316 || strcmp (symname
, "_ftext") == 0
12317 || strcmp (symname
, "end") == 0
12318 || strcmp (symname
, "_gp_disp") == 0))
12320 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12322 #ifndef NO_ECOFF_DEBUGGING
12323 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12324 && (symbol_get_obj (sym
)->ecoff_extern_size
12325 <= g_switch_value
))
12327 /* We must defer this decision until after the whole
12328 file has been read, since there might be a .extern
12329 after the first use of this symbol. */
12330 || (before_relaxing
12331 #ifndef NO_ECOFF_DEBUGGING
12332 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12334 && S_GET_VALUE (sym
) == 0)
12335 || (S_GET_VALUE (sym
) != 0
12336 && S_GET_VALUE (sym
) <= g_switch_value
)))
12340 const char *segname
;
12342 segname
= segment_name (S_GET_SEGMENT (sym
));
12343 assert (strcmp (segname
, ".lit8") != 0
12344 && strcmp (segname
, ".lit4") != 0);
12345 change
= (strcmp (segname
, ".sdata") != 0
12346 && strcmp (segname
, ".sbss") != 0
12347 && strncmp (segname
, ".sdata.", 7) != 0
12348 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12353 /* We are not optimizing for the $gp register. */
12358 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12361 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12364 bfd_boolean linkonce
;
12366 /* Handle the case of a symbol equated to another symbol. */
12367 while (symbol_equated_reloc_p (sym
))
12371 /* It's possible to get a loop here in a badly written
12373 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12379 symsec
= S_GET_SEGMENT (sym
);
12381 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12383 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12385 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12389 /* The GNU toolchain uses an extension for ELF: a section
12390 beginning with the magic string .gnu.linkonce is a linkonce
12392 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12393 sizeof ".gnu.linkonce" - 1) == 0)
12397 /* This must duplicate the test in adjust_reloc_syms. */
12398 return (symsec
!= &bfd_und_section
12399 && symsec
!= &bfd_abs_section
12400 && ! bfd_is_com_section (symsec
)
12403 /* A global or weak symbol is treated as external. */
12404 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12405 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12411 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12412 extended opcode. SEC is the section the frag is in. */
12415 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12418 register const struct mips16_immed_operand
*op
;
12420 int mintiny
, maxtiny
;
12424 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12426 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12429 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12430 op
= mips16_immed_operands
;
12431 while (op
->type
!= type
)
12434 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12439 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12442 maxtiny
= 1 << op
->nbits
;
12447 maxtiny
= (1 << op
->nbits
) - 1;
12452 mintiny
= - (1 << (op
->nbits
- 1));
12453 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12456 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12457 val
= S_GET_VALUE (fragp
->fr_symbol
);
12458 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12464 /* We won't have the section when we are called from
12465 mips_relax_frag. However, we will always have been called
12466 from md_estimate_size_before_relax first. If this is a
12467 branch to a different section, we mark it as such. If SEC is
12468 NULL, and the frag is not marked, then it must be a branch to
12469 the same section. */
12472 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12477 /* Must have been called from md_estimate_size_before_relax. */
12480 fragp
->fr_subtype
=
12481 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12483 /* FIXME: We should support this, and let the linker
12484 catch branches and loads that are out of range. */
12485 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12486 _("unsupported PC relative reference to different section"));
12490 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12491 /* Assume non-extended on the first relaxation pass.
12492 The address we have calculated will be bogus if this is
12493 a forward branch to another frag, as the forward frag
12494 will have fr_address == 0. */
12498 /* In this case, we know for sure that the symbol fragment is in
12499 the same section. If the relax_marker of the symbol fragment
12500 differs from the relax_marker of this fragment, we have not
12501 yet adjusted the symbol fragment fr_address. We want to add
12502 in STRETCH in order to get a better estimate of the address.
12503 This particularly matters because of the shift bits. */
12505 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12509 /* Adjust stretch for any alignment frag. Note that if have
12510 been expanding the earlier code, the symbol may be
12511 defined in what appears to be an earlier frag. FIXME:
12512 This doesn't handle the fr_subtype field, which specifies
12513 a maximum number of bytes to skip when doing an
12515 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12517 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12520 stretch
= - ((- stretch
)
12521 & ~ ((1 << (int) f
->fr_offset
) - 1));
12523 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12532 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12534 /* The base address rules are complicated. The base address of
12535 a branch is the following instruction. The base address of a
12536 PC relative load or add is the instruction itself, but if it
12537 is in a delay slot (in which case it can not be extended) use
12538 the address of the instruction whose delay slot it is in. */
12539 if (type
== 'p' || type
== 'q')
12543 /* If we are currently assuming that this frag should be
12544 extended, then, the current address is two bytes
12546 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12549 /* Ignore the low bit in the target, since it will be set
12550 for a text label. */
12551 if ((val
& 1) != 0)
12554 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12556 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12559 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12561 /* Branch offsets have an implicit 0 in the lowest bit. */
12562 if (type
== 'p' || type
== 'q')
12565 /* If any of the shifted bits are set, we must use an extended
12566 opcode. If the address depends on the size of this
12567 instruction, this can lead to a loop, so we arrange to always
12568 use an extended opcode. We only check this when we are in
12569 the main relaxation loop, when SEC is NULL. */
12570 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12572 fragp
->fr_subtype
=
12573 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12577 /* If we are about to mark a frag as extended because the value
12578 is precisely maxtiny + 1, then there is a chance of an
12579 infinite loop as in the following code:
12584 In this case when the la is extended, foo is 0x3fc bytes
12585 away, so the la can be shrunk, but then foo is 0x400 away, so
12586 the la must be extended. To avoid this loop, we mark the
12587 frag as extended if it was small, and is about to become
12588 extended with a value of maxtiny + 1. */
12589 if (val
== ((maxtiny
+ 1) << op
->shift
)
12590 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12593 fragp
->fr_subtype
=
12594 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12598 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12599 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12601 if ((val
& ((1 << op
->shift
) - 1)) != 0
12602 || val
< (mintiny
<< op
->shift
)
12603 || val
> (maxtiny
<< op
->shift
))
12609 /* Compute the length of a branch sequence, and adjust the
12610 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12611 worst-case length is computed, with UPDATE being used to indicate
12612 whether an unconditional (-1), branch-likely (+1) or regular (0)
12613 branch is to be computed. */
12615 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12617 bfd_boolean toofar
;
12621 && S_IS_DEFINED (fragp
->fr_symbol
)
12622 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12627 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12629 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12633 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12636 /* If the symbol is not defined or it's in a different segment,
12637 assume the user knows what's going on and emit a short
12643 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12645 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12646 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12647 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12653 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12656 if (mips_pic
!= NO_PIC
)
12658 /* Additional space for PIC loading of target address. */
12660 if (mips_opts
.isa
== ISA_MIPS1
)
12661 /* Additional space for $at-stabilizing nop. */
12665 /* If branch is conditional. */
12666 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12673 /* Estimate the size of a frag before relaxing. Unless this is the
12674 mips16, we are not really relaxing here, and the final size is
12675 encoded in the subtype information. For the mips16, we have to
12676 decide whether we are using an extended opcode or not. */
12679 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12683 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12686 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12688 return fragp
->fr_var
;
12691 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12692 /* We don't want to modify the EXTENDED bit here; it might get us
12693 into infinite loops. We change it only in mips_relax_frag(). */
12694 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12696 if (mips_pic
== NO_PIC
)
12697 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12698 else if (mips_pic
== SVR4_PIC
)
12699 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12705 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12706 return -RELAX_FIRST (fragp
->fr_subtype
);
12709 return -RELAX_SECOND (fragp
->fr_subtype
);
12712 /* This is called to see whether a reloc against a defined symbol
12713 should be converted into a reloc against a section. */
12716 mips_fix_adjustable (fixS
*fixp
)
12718 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12719 about the format of the offset in the .o file. */
12720 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12723 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12724 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12727 if (fixp
->fx_addsy
== NULL
)
12730 /* If symbol SYM is in a mergeable section, relocations of the form
12731 SYM + 0 can usually be made section-relative. The mergeable data
12732 is then identified by the section offset rather than by the symbol.
12734 However, if we're generating REL LO16 relocations, the offset is split
12735 between the LO16 and parterning high part relocation. The linker will
12736 need to recalculate the complete offset in order to correctly identify
12739 The linker has traditionally not looked for the parterning high part
12740 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12741 placed anywhere. Rather than break backwards compatibility by changing
12742 this, it seems better not to force the issue, and instead keep the
12743 original symbol. This will work with either linker behavior. */
12744 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12745 && HAVE_IN_PLACE_ADDENDS
12746 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12750 /* Don't adjust relocations against mips16 symbols, so that the linker
12751 can find them if it needs to set up a stub. */
12752 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12753 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12754 && fixp
->fx_subsy
== NULL
)
12761 /* Translate internal representation of relocation info to BFD target
12765 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12767 static arelent
*retval
[4];
12769 bfd_reloc_code_real_type code
;
12771 memset (retval
, 0, sizeof(retval
));
12772 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12773 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12774 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12775 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12777 assert (! fixp
->fx_pcrel
);
12778 reloc
->addend
= fixp
->fx_addnumber
;
12780 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12781 entry to be used in the relocation's section offset. */
12782 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12784 reloc
->address
= reloc
->addend
;
12788 code
= fixp
->fx_r_type
;
12790 /* To support a PC relative reloc, we used a Cygnus extension.
12791 We check for that here to make sure that we don't let such a
12792 reloc escape normally. (FIXME: This was formerly used by
12793 embedded-PIC support, but is now used by branch handling in
12794 general. That probably should be fixed.) */
12795 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12796 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12797 && code
== BFD_RELOC_16_PCREL_S2
)
12798 reloc
->howto
= NULL
;
12800 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12802 if (reloc
->howto
== NULL
)
12804 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12805 _("Can not represent %s relocation in this object file format"),
12806 bfd_get_reloc_code_name (code
));
12813 /* Relax a machine dependent frag. This returns the amount by which
12814 the current size of the frag should change. */
12817 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12819 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12821 offsetT old_var
= fragp
->fr_var
;
12823 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12825 return fragp
->fr_var
- old_var
;
12828 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12831 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12833 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12835 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12840 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12842 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12849 /* Convert a machine dependent frag. */
12852 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12854 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12857 unsigned long insn
;
12861 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12863 if (target_big_endian
)
12864 insn
= bfd_getb32 (buf
);
12866 insn
= bfd_getl32 (buf
);
12868 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12870 /* We generate a fixup instead of applying it right now
12871 because, if there are linker relaxations, we're going to
12872 need the relocations. */
12873 exp
.X_op
= O_symbol
;
12874 exp
.X_add_symbol
= fragp
->fr_symbol
;
12875 exp
.X_add_number
= fragp
->fr_offset
;
12877 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12879 BFD_RELOC_16_PCREL_S2
);
12880 fixp
->fx_file
= fragp
->fr_file
;
12881 fixp
->fx_line
= fragp
->fr_line
;
12883 md_number_to_chars ((char *) buf
, insn
, 4);
12890 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12891 _("relaxed out-of-range branch into a jump"));
12893 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12896 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12898 /* Reverse the branch. */
12899 switch ((insn
>> 28) & 0xf)
12902 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12903 have the condition reversed by tweaking a single
12904 bit, and their opcodes all have 0x4???????. */
12905 assert ((insn
& 0xf1000000) == 0x41000000);
12906 insn
^= 0x00010000;
12910 /* bltz 0x04000000 bgez 0x04010000
12911 bltzal 0x04100000 bgezal 0x04110000 */
12912 assert ((insn
& 0xfc0e0000) == 0x04000000);
12913 insn
^= 0x00010000;
12917 /* beq 0x10000000 bne 0x14000000
12918 blez 0x18000000 bgtz 0x1c000000 */
12919 insn
^= 0x04000000;
12927 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12929 /* Clear the and-link bit. */
12930 assert ((insn
& 0xfc1c0000) == 0x04100000);
12932 /* bltzal 0x04100000 bgezal 0x04110000
12933 bltzall 0x04120000 bgezall 0x04130000 */
12934 insn
&= ~0x00100000;
12937 /* Branch over the branch (if the branch was likely) or the
12938 full jump (not likely case). Compute the offset from the
12939 current instruction to branch to. */
12940 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12944 /* How many bytes in instructions we've already emitted? */
12945 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12946 /* How many bytes in instructions from here to the end? */
12947 i
= fragp
->fr_var
- i
;
12949 /* Convert to instruction count. */
12951 /* Branch counts from the next instruction. */
12954 /* Branch over the jump. */
12955 md_number_to_chars ((char *) buf
, insn
, 4);
12959 md_number_to_chars ((char *) buf
, 0, 4);
12962 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12964 /* beql $0, $0, 2f */
12966 /* Compute the PC offset from the current instruction to
12967 the end of the variable frag. */
12968 /* How many bytes in instructions we've already emitted? */
12969 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12970 /* How many bytes in instructions from here to the end? */
12971 i
= fragp
->fr_var
- i
;
12972 /* Convert to instruction count. */
12974 /* Don't decrement i, because we want to branch over the
12978 md_number_to_chars ((char *) buf
, insn
, 4);
12981 md_number_to_chars ((char *) buf
, 0, 4);
12986 if (mips_pic
== NO_PIC
)
12989 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12990 ? 0x0c000000 : 0x08000000);
12991 exp
.X_op
= O_symbol
;
12992 exp
.X_add_symbol
= fragp
->fr_symbol
;
12993 exp
.X_add_number
= fragp
->fr_offset
;
12995 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12996 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12997 fixp
->fx_file
= fragp
->fr_file
;
12998 fixp
->fx_line
= fragp
->fr_line
;
13000 md_number_to_chars ((char *) buf
, insn
, 4);
13005 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13006 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13007 exp
.X_op
= O_symbol
;
13008 exp
.X_add_symbol
= fragp
->fr_symbol
;
13009 exp
.X_add_number
= fragp
->fr_offset
;
13011 if (fragp
->fr_offset
)
13013 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13014 exp
.X_add_number
= 0;
13017 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13018 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13019 fixp
->fx_file
= fragp
->fr_file
;
13020 fixp
->fx_line
= fragp
->fr_line
;
13022 md_number_to_chars ((char *) buf
, insn
, 4);
13025 if (mips_opts
.isa
== ISA_MIPS1
)
13028 md_number_to_chars ((char *) buf
, 0, 4);
13032 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13033 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13035 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13036 4, &exp
, 0, BFD_RELOC_LO16
);
13037 fixp
->fx_file
= fragp
->fr_file
;
13038 fixp
->fx_line
= fragp
->fr_line
;
13040 md_number_to_chars ((char *) buf
, insn
, 4);
13044 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13049 md_number_to_chars ((char *) buf
, insn
, 4);
13054 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13055 + fragp
->fr_fix
+ fragp
->fr_var
);
13057 fragp
->fr_fix
+= fragp
->fr_var
;
13062 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13065 register const struct mips16_immed_operand
*op
;
13066 bfd_boolean small
, ext
;
13069 unsigned long insn
;
13070 bfd_boolean use_extend
;
13071 unsigned short extend
;
13073 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13074 op
= mips16_immed_operands
;
13075 while (op
->type
!= type
)
13078 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13089 resolve_symbol_value (fragp
->fr_symbol
);
13090 val
= S_GET_VALUE (fragp
->fr_symbol
);
13095 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13097 /* The rules for the base address of a PC relative reloc are
13098 complicated; see mips16_extended_frag. */
13099 if (type
== 'p' || type
== 'q')
13104 /* Ignore the low bit in the target, since it will be
13105 set for a text label. */
13106 if ((val
& 1) != 0)
13109 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13111 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13114 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13117 /* Make sure the section winds up with the alignment we have
13120 record_alignment (asec
, op
->shift
);
13124 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13125 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13126 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13127 _("extended instruction in delay slot"));
13129 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13131 if (target_big_endian
)
13132 insn
= bfd_getb16 (buf
);
13134 insn
= bfd_getl16 (buf
);
13136 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13137 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13138 small
, ext
, &insn
, &use_extend
, &extend
);
13142 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13143 fragp
->fr_fix
+= 2;
13147 md_number_to_chars ((char *) buf
, insn
, 2);
13148 fragp
->fr_fix
+= 2;
13156 first
= RELAX_FIRST (fragp
->fr_subtype
);
13157 second
= RELAX_SECOND (fragp
->fr_subtype
);
13158 fixp
= (fixS
*) fragp
->fr_opcode
;
13160 /* Possibly emit a warning if we've chosen the longer option. */
13161 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13162 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13164 const char *msg
= macro_warning (fragp
->fr_subtype
);
13166 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13169 /* Go through all the fixups for the first sequence. Disable them
13170 (by marking them as done) if we're going to use the second
13171 sequence instead. */
13173 && fixp
->fx_frag
== fragp
13174 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13176 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13178 fixp
= fixp
->fx_next
;
13181 /* Go through the fixups for the second sequence. Disable them if
13182 we're going to use the first sequence, otherwise adjust their
13183 addresses to account for the relaxation. */
13184 while (fixp
&& fixp
->fx_frag
== fragp
)
13186 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13187 fixp
->fx_where
-= first
;
13190 fixp
= fixp
->fx_next
;
13193 /* Now modify the frag contents. */
13194 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13198 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13199 memmove (start
, start
+ first
, second
);
13200 fragp
->fr_fix
-= first
;
13203 fragp
->fr_fix
-= second
;
13209 /* This function is called after the relocs have been generated.
13210 We've been storing mips16 text labels as odd. Here we convert them
13211 back to even for the convenience of the debugger. */
13214 mips_frob_file_after_relocs (void)
13217 unsigned int count
, i
;
13219 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13222 syms
= bfd_get_outsymbols (stdoutput
);
13223 count
= bfd_get_symcount (stdoutput
);
13224 for (i
= 0; i
< count
; i
++, syms
++)
13226 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13227 && ((*syms
)->value
& 1) != 0)
13229 (*syms
)->value
&= ~1;
13230 /* If the symbol has an odd size, it was probably computed
13231 incorrectly, so adjust that as well. */
13232 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13233 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13240 /* This function is called whenever a label is defined. It is used
13241 when handling branch delays; if a branch has a label, we assume we
13242 can not move it. */
13245 mips_define_label (symbolS
*sym
)
13247 struct insn_label_list
*l
;
13249 if (free_insn_labels
== NULL
)
13250 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13253 l
= free_insn_labels
;
13254 free_insn_labels
= l
->next
;
13258 l
->next
= insn_labels
;
13262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13264 /* Some special processing for a MIPS ELF file. */
13267 mips_elf_final_processing (void)
13269 /* Write out the register information. */
13270 if (mips_abi
!= N64_ABI
)
13274 s
.ri_gprmask
= mips_gprmask
;
13275 s
.ri_cprmask
[0] = mips_cprmask
[0];
13276 s
.ri_cprmask
[1] = mips_cprmask
[1];
13277 s
.ri_cprmask
[2] = mips_cprmask
[2];
13278 s
.ri_cprmask
[3] = mips_cprmask
[3];
13279 /* The gp_value field is set by the MIPS ELF backend. */
13281 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13282 ((Elf32_External_RegInfo
*)
13283 mips_regmask_frag
));
13287 Elf64_Internal_RegInfo s
;
13289 s
.ri_gprmask
= mips_gprmask
;
13291 s
.ri_cprmask
[0] = mips_cprmask
[0];
13292 s
.ri_cprmask
[1] = mips_cprmask
[1];
13293 s
.ri_cprmask
[2] = mips_cprmask
[2];
13294 s
.ri_cprmask
[3] = mips_cprmask
[3];
13295 /* The gp_value field is set by the MIPS ELF backend. */
13297 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13298 ((Elf64_External_RegInfo
*)
13299 mips_regmask_frag
));
13302 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13303 sort of BFD interface for this. */
13304 if (mips_any_noreorder
)
13305 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13306 if (mips_pic
!= NO_PIC
)
13308 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13309 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13312 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13314 /* Set MIPS ELF flags for ASEs. */
13315 if (file_ase_mips16
)
13316 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13317 #if 0 /* XXX FIXME */
13318 if (file_ase_mips3d
)
13319 elf_elfheader (stdoutput
)->e_flags
|= ???;
13322 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13324 /* Set the MIPS ELF ABI flags. */
13325 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13326 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13327 else if (mips_abi
== O64_ABI
)
13328 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13329 else if (mips_abi
== EABI_ABI
)
13331 if (!file_mips_gp32
)
13332 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13334 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13336 else if (mips_abi
== N32_ABI
)
13337 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13339 /* Nothing to do for N64_ABI. */
13341 if (mips_32bitmode
)
13342 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13345 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13347 typedef struct proc
{
13349 symbolS
*func_end_sym
;
13350 unsigned long reg_mask
;
13351 unsigned long reg_offset
;
13352 unsigned long fpreg_mask
;
13353 unsigned long fpreg_offset
;
13354 unsigned long frame_offset
;
13355 unsigned long frame_reg
;
13356 unsigned long pc_reg
;
13359 static procS cur_proc
;
13360 static procS
*cur_proc_ptr
;
13361 static int numprocs
;
13363 /* Fill in an rs_align_code fragment. */
13366 mips_handle_align (fragS
*fragp
)
13368 if (fragp
->fr_type
!= rs_align_code
)
13371 if (mips_opts
.mips16
)
13373 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13374 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13379 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13380 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13388 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13392 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13396 md_obj_begin (void)
13403 /* check for premature end, nesting errors, etc */
13405 as_warn (_("missing .end at end of assembly"));
13414 if (*input_line_pointer
== '-')
13416 ++input_line_pointer
;
13419 if (!ISDIGIT (*input_line_pointer
))
13420 as_bad (_("expected simple number"));
13421 if (input_line_pointer
[0] == '0')
13423 if (input_line_pointer
[1] == 'x')
13425 input_line_pointer
+= 2;
13426 while (ISXDIGIT (*input_line_pointer
))
13429 val
|= hex_value (*input_line_pointer
++);
13431 return negative
? -val
: val
;
13435 ++input_line_pointer
;
13436 while (ISDIGIT (*input_line_pointer
))
13439 val
|= *input_line_pointer
++ - '0';
13441 return negative
? -val
: val
;
13444 if (!ISDIGIT (*input_line_pointer
))
13446 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13447 *input_line_pointer
, *input_line_pointer
);
13448 as_warn (_("invalid number"));
13451 while (ISDIGIT (*input_line_pointer
))
13454 val
+= *input_line_pointer
++ - '0';
13456 return negative
? -val
: val
;
13459 /* The .file directive; just like the usual .file directive, but there
13460 is an initial number which is the ECOFF file index. In the non-ECOFF
13461 case .file implies DWARF-2. */
13464 s_mips_file (int x ATTRIBUTE_UNUSED
)
13466 static int first_file_directive
= 0;
13468 if (ECOFF_DEBUGGING
)
13477 filename
= dwarf2_directive_file (0);
13479 /* Versions of GCC up to 3.1 start files with a ".file"
13480 directive even for stabs output. Make sure that this
13481 ".file" is handled. Note that you need a version of GCC
13482 after 3.1 in order to support DWARF-2 on MIPS. */
13483 if (filename
!= NULL
&& ! first_file_directive
)
13485 (void) new_logical_line (filename
, -1);
13486 s_app_file_string (filename
, 0);
13488 first_file_directive
= 1;
13492 /* The .loc directive, implying DWARF-2. */
13495 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13497 if (!ECOFF_DEBUGGING
)
13498 dwarf2_directive_loc (0);
13501 /* The .end directive. */
13504 s_mips_end (int x ATTRIBUTE_UNUSED
)
13508 /* Following functions need their own .frame and .cprestore directives. */
13509 mips_frame_reg_valid
= 0;
13510 mips_cprestore_valid
= 0;
13512 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13515 demand_empty_rest_of_line ();
13520 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13521 as_warn (_(".end not in text section"));
13525 as_warn (_(".end directive without a preceding .ent directive."));
13526 demand_empty_rest_of_line ();
13532 assert (S_GET_NAME (p
));
13533 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13534 as_warn (_(".end symbol does not match .ent symbol."));
13536 if (debug_type
== DEBUG_STABS
)
13537 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13541 as_warn (_(".end directive missing or unknown symbol"));
13544 /* Create an expression to calculate the size of the function. */
13545 if (p
&& cur_proc_ptr
)
13547 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13548 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13551 exp
->X_op
= O_subtract
;
13552 exp
->X_add_symbol
= symbol_temp_new_now ();
13553 exp
->X_op_symbol
= p
;
13554 exp
->X_add_number
= 0;
13556 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13559 /* Generate a .pdr section. */
13560 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13563 segT saved_seg
= now_seg
;
13564 subsegT saved_subseg
= now_subseg
;
13569 dot
= frag_now_fix ();
13571 #ifdef md_flush_pending_output
13572 md_flush_pending_output ();
13576 subseg_set (pdr_seg
, 0);
13578 /* Write the symbol. */
13579 exp
.X_op
= O_symbol
;
13580 exp
.X_add_symbol
= p
;
13581 exp
.X_add_number
= 0;
13582 emit_expr (&exp
, 4);
13584 fragp
= frag_more (7 * 4);
13586 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13587 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13588 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13589 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13590 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13591 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13592 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13594 subseg_set (saved_seg
, saved_subseg
);
13596 #endif /* OBJ_ELF */
13598 cur_proc_ptr
= NULL
;
13601 /* The .aent and .ent directives. */
13604 s_mips_ent (int aent
)
13608 symbolP
= get_symbol ();
13609 if (*input_line_pointer
== ',')
13610 ++input_line_pointer
;
13611 SKIP_WHITESPACE ();
13612 if (ISDIGIT (*input_line_pointer
)
13613 || *input_line_pointer
== '-')
13616 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13617 as_warn (_(".ent or .aent not in text section."));
13619 if (!aent
&& cur_proc_ptr
)
13620 as_warn (_("missing .end"));
13624 /* This function needs its own .frame and .cprestore directives. */
13625 mips_frame_reg_valid
= 0;
13626 mips_cprestore_valid
= 0;
13628 cur_proc_ptr
= &cur_proc
;
13629 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13631 cur_proc_ptr
->func_sym
= symbolP
;
13633 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13637 if (debug_type
== DEBUG_STABS
)
13638 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13639 S_GET_NAME (symbolP
));
13642 demand_empty_rest_of_line ();
13645 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13646 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13647 s_mips_frame is used so that we can set the PDR information correctly.
13648 We can't use the ecoff routines because they make reference to the ecoff
13649 symbol table (in the mdebug section). */
13652 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13655 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13659 if (cur_proc_ptr
== (procS
*) NULL
)
13661 as_warn (_(".frame outside of .ent"));
13662 demand_empty_rest_of_line ();
13666 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13668 SKIP_WHITESPACE ();
13669 if (*input_line_pointer
++ != ','
13670 || get_absolute_expression_and_terminator (&val
) != ',')
13672 as_warn (_("Bad .frame directive"));
13673 --input_line_pointer
;
13674 demand_empty_rest_of_line ();
13678 cur_proc_ptr
->frame_offset
= val
;
13679 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13681 demand_empty_rest_of_line ();
13684 #endif /* OBJ_ELF */
13688 /* The .fmask and .mask directives. If the mdebug section is present
13689 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13690 embedded targets, s_mips_mask is used so that we can set the PDR
13691 information correctly. We can't use the ecoff routines because they
13692 make reference to the ecoff symbol table (in the mdebug section). */
13695 s_mips_mask (int reg_type
)
13698 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13702 if (cur_proc_ptr
== (procS
*) NULL
)
13704 as_warn (_(".mask/.fmask outside of .ent"));
13705 demand_empty_rest_of_line ();
13709 if (get_absolute_expression_and_terminator (&mask
) != ',')
13711 as_warn (_("Bad .mask/.fmask directive"));
13712 --input_line_pointer
;
13713 demand_empty_rest_of_line ();
13717 off
= get_absolute_expression ();
13719 if (reg_type
== 'F')
13721 cur_proc_ptr
->fpreg_mask
= mask
;
13722 cur_proc_ptr
->fpreg_offset
= off
;
13726 cur_proc_ptr
->reg_mask
= mask
;
13727 cur_proc_ptr
->reg_offset
= off
;
13730 demand_empty_rest_of_line ();
13733 #endif /* OBJ_ELF */
13734 s_ignore (reg_type
);
13737 /* A table describing all the processors gas knows about. Names are
13738 matched in the order listed.
13740 To ease comparison, please keep this table in the same order as
13741 gcc's mips_cpu_info_table[]. */
13742 static const struct mips_cpu_info mips_cpu_info_table
[] =
13744 /* Entries for generic ISAs */
13745 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13746 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13747 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13748 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13749 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13750 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13751 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13752 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13753 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13756 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13757 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13758 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13761 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13764 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13765 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13766 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13767 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13768 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13769 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13770 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13771 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13772 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13773 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13774 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13775 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13778 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13779 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13780 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13781 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13782 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13783 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13784 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13785 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13786 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13787 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13788 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13789 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13790 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13793 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13794 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13795 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13798 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13799 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13801 /* Broadcom SB-1 CPU core */
13802 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13809 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13810 with a final "000" replaced by "k". Ignore case.
13812 Note: this function is shared between GCC and GAS. */
13815 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13817 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13818 given
++, canonical
++;
13820 return ((*given
== 0 && *canonical
== 0)
13821 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13825 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13826 CPU name. We've traditionally allowed a lot of variation here.
13828 Note: this function is shared between GCC and GAS. */
13831 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13833 /* First see if the name matches exactly, or with a final "000"
13834 turned into "k". */
13835 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13838 /* If not, try comparing based on numerical designation alone.
13839 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13840 if (TOLOWER (*given
) == 'r')
13842 if (!ISDIGIT (*given
))
13845 /* Skip over some well-known prefixes in the canonical name,
13846 hoping to find a number there too. */
13847 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13849 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13851 else if (TOLOWER (canonical
[0]) == 'r')
13854 return mips_strict_matching_cpu_name_p (canonical
, given
);
13858 /* Parse an option that takes the name of a processor as its argument.
13859 OPTION is the name of the option and CPU_STRING is the argument.
13860 Return the corresponding processor enumeration if the CPU_STRING is
13861 recognized, otherwise report an error and return null.
13863 A similar function exists in GCC. */
13865 static const struct mips_cpu_info
*
13866 mips_parse_cpu (const char *option
, const char *cpu_string
)
13868 const struct mips_cpu_info
*p
;
13870 /* 'from-abi' selects the most compatible architecture for the given
13871 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13872 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13873 version. Look first at the -mgp options, if given, otherwise base
13874 the choice on MIPS_DEFAULT_64BIT.
13876 Treat NO_ABI like the EABIs. One reason to do this is that the
13877 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13878 architecture. This code picks MIPS I for 'mips' and MIPS III for
13879 'mips64', just as we did in the days before 'from-abi'. */
13880 if (strcasecmp (cpu_string
, "from-abi") == 0)
13882 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13883 return mips_cpu_info_from_isa (ISA_MIPS1
);
13885 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13886 return mips_cpu_info_from_isa (ISA_MIPS3
);
13888 if (file_mips_gp32
>= 0)
13889 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13891 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13896 /* 'default' has traditionally been a no-op. Probably not very useful. */
13897 if (strcasecmp (cpu_string
, "default") == 0)
13900 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13901 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13904 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13908 /* Return the canonical processor information for ISA (a member of the
13909 ISA_MIPS* enumeration). */
13911 static const struct mips_cpu_info
*
13912 mips_cpu_info_from_isa (int isa
)
13916 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13917 if (mips_cpu_info_table
[i
].is_isa
13918 && isa
== mips_cpu_info_table
[i
].isa
)
13919 return (&mips_cpu_info_table
[i
]);
13924 static const struct mips_cpu_info
*
13925 mips_cpu_info_from_arch (int arch
)
13929 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13930 if (arch
== mips_cpu_info_table
[i
].cpu
)
13931 return (&mips_cpu_info_table
[i
]);
13937 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13941 fprintf (stream
, "%24s", "");
13946 fprintf (stream
, ", ");
13950 if (*col_p
+ strlen (string
) > 72)
13952 fprintf (stream
, "\n%24s", "");
13956 fprintf (stream
, "%s", string
);
13957 *col_p
+= strlen (string
);
13963 md_show_usage (FILE *stream
)
13968 fprintf (stream
, _("\
13970 -EB generate big endian output\n\
13971 -EL generate little endian output\n\
13972 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13973 -G NUM allow referencing objects up to NUM bytes\n\
13974 implicitly with the gp register [default 8]\n"));
13975 fprintf (stream
, _("\
13976 -mips1 generate MIPS ISA I instructions\n\
13977 -mips2 generate MIPS ISA II instructions\n\
13978 -mips3 generate MIPS ISA III instructions\n\
13979 -mips4 generate MIPS ISA IV instructions\n\
13980 -mips5 generate MIPS ISA V instructions\n\
13981 -mips32 generate MIPS32 ISA instructions\n\
13982 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13983 -mips64 generate MIPS64 ISA instructions\n\
13984 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13985 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13989 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13990 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13991 show (stream
, "from-abi", &column
, &first
);
13992 fputc ('\n', stream
);
13994 fprintf (stream
, _("\
13995 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13996 -no-mCPU don't generate code specific to CPU.\n\
13997 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14001 show (stream
, "3900", &column
, &first
);
14002 show (stream
, "4010", &column
, &first
);
14003 show (stream
, "4100", &column
, &first
);
14004 show (stream
, "4650", &column
, &first
);
14005 fputc ('\n', stream
);
14007 fprintf (stream
, _("\
14008 -mips16 generate mips16 instructions\n\
14009 -no-mips16 do not generate mips16 instructions\n"));
14010 fprintf (stream
, _("\
14011 -mfix-vr4120 work around certain VR4120 errata\n\
14012 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14013 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14014 -mno-shared optimize output for executables\n\
14015 -msym32 assume all symbols have 32-bit values\n\
14016 -O0 remove unneeded NOPs, do not swap branches\n\
14017 -O remove unneeded NOPs and swap branches\n\
14018 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14019 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14020 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14022 fprintf (stream
, _("\
14023 -KPIC, -call_shared generate SVR4 position independent code\n\
14024 -non_shared do not generate position independent code\n\
14025 -xgot assume a 32 bit GOT\n\
14026 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14027 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14029 -mabi=ABI create ABI conformant object file for:\n"));
14033 show (stream
, "32", &column
, &first
);
14034 show (stream
, "o64", &column
, &first
);
14035 show (stream
, "n32", &column
, &first
);
14036 show (stream
, "64", &column
, &first
);
14037 show (stream
, "eabi", &column
, &first
);
14039 fputc ('\n', stream
);
14041 fprintf (stream
, _("\
14042 -32 create o32 ABI object file (default)\n\
14043 -n32 create n32 ABI object file\n\
14044 -64 create 64 ABI object file\n"));
14049 mips_dwarf2_format (void)
14051 if (mips_abi
== N64_ABI
)
14054 return dwarf2_format_64bit_irix
;
14056 return dwarf2_format_64bit
;
14060 return dwarf2_format_32bit
;
14064 mips_dwarf2_addr_size (void)
14066 if (mips_abi
== N64_ABI
)