1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, pic, sym32, nomacro, \
1138 | ((pic) ? 0x100 : 0) \
1139 | ((sym32) ? 0x200 : 0) \
1140 | ((nomacro) ? 0x400 : 0) \
1141 | ((small) ? 0x800 : 0) \
1142 | ((ext) ? 0x1000 : 0) \
1143 | ((dslot) ? 0x2000 : 0) \
1144 | ((jal_dslot) ? 0x4000 : 0))
1146 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1147 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1148 #define RELAX_MIPS16_PIC(i) (((i) & 0x100) != 0)
1149 #define RELAX_MIPS16_SYM32(i) (((i) & 0x200) != 0)
1150 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x400) != 0)
1151 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x800) != 0)
1152 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x1000) != 0)
1153 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x2000) != 0)
1154 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x8000) != 0)
1157 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x8000)
1158 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x8000)
1159 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x10000) != 0)
1160 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x10000)
1161 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x10000)
1162 #define RELAX_MIPS16_MACRO(i) (((i) & 0x20000) != 0)
1163 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x20000)
1164 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x20000)
1166 /* For microMIPS code, we use relaxation similar to one we use for
1167 MIPS16 code. Some instructions that take immediate values support
1168 two encodings: a small one which takes some small value, and a
1169 larger one which takes a 16 bit value. As some branches also follow
1170 this pattern, relaxing these values is required.
1172 We can assemble both microMIPS and normal MIPS code in a single
1173 object. Therefore, we need to support this type of relaxation at
1174 the same time that we support the relaxation described above. We
1175 use one of the high bits of the subtype field to distinguish these
1178 The information we store for this type of relaxation is the argument
1179 code found in the opcode file for this relocation, the register
1180 selected as the assembler temporary, whether in the 32-bit
1181 instruction mode, whether the branch is unconditional, whether it is
1182 compact, whether there is no delay-slot instruction available to fill
1183 in, whether it stores the link address implicitly in $ra, whether
1184 relaxation of out-of-range 32-bit branches to a sequence of
1185 instructions is enabled, and whether the displacement of a branch is
1186 too large to fit as an immediate argument of a 16-bit and a 32-bit
1187 branch, respectively. */
1188 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1189 uncond, compact, link, nods, \
1190 relax32, toofar16, toofar32) \
1193 | (((at) & 0x1f) << 8) \
1194 | ((insn32) ? 0x2000 : 0) \
1195 | ((pic) ? 0x4000 : 0) \
1196 | ((uncond) ? 0x8000 : 0) \
1197 | ((compact) ? 0x10000 : 0) \
1198 | ((link) ? 0x20000 : 0) \
1199 | ((nods) ? 0x40000 : 0) \
1200 | ((relax32) ? 0x80000 : 0) \
1201 | ((toofar16) ? 0x100000 : 0) \
1202 | ((toofar32) ? 0x200000 : 0))
1203 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1204 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1205 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1206 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1207 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1208 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1209 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1210 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1211 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1212 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1214 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1215 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1216 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1217 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1218 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1219 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1221 /* Sign-extend 16-bit value X. */
1222 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1224 /* Is the given value a sign-extended 32-bit value? */
1225 #define IS_SEXT_32BIT_NUM(x) \
1226 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1227 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1229 /* Is the given value a sign-extended 16-bit value? */
1230 #define IS_SEXT_16BIT_NUM(x) \
1231 (((x) &~ (offsetT) 0x7fff) == 0 \
1232 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1234 /* Is the given value a sign-extended 12-bit value? */
1235 #define IS_SEXT_12BIT_NUM(x) \
1236 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1238 /* Is the given value a sign-extended 9-bit value? */
1239 #define IS_SEXT_9BIT_NUM(x) \
1240 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1242 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1243 #define IS_ZEXT_32BIT_NUM(x) \
1244 (((x) &~ (offsetT) 0xffffffff) == 0 \
1245 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1247 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1249 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1250 (((STRUCT) >> (SHIFT)) & (MASK))
1252 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1253 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1255 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1256 : EXTRACT_BITS ((INSN).insn_opcode, \
1257 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1258 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1259 EXTRACT_BITS ((INSN).insn_opcode, \
1260 MIPS16OP_MASK_##FIELD, \
1261 MIPS16OP_SH_##FIELD)
1263 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1264 #define MIPS16_EXTEND (0xf000U << 16)
1266 /* Whether or not we are emitting a branch-likely macro. */
1267 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1269 /* Global variables used when generating relaxable macros. See the
1270 comment above RELAX_ENCODE for more details about how relaxation
1273 /* 0 if we're not emitting a relaxable macro.
1274 1 if we're emitting the first of the two relaxation alternatives.
1275 2 if we're emitting the second alternative. */
1278 /* The first relaxable fixup in the current frag. (In other words,
1279 the first fixup that refers to relaxable code.) */
1282 /* sizes[0] says how many bytes of the first alternative are stored in
1283 the current frag. Likewise sizes[1] for the second alternative. */
1284 unsigned int sizes
[2];
1286 /* The symbol on which the choice of sequence depends. */
1290 /* Global variables used to decide whether a macro needs a warning. */
1292 /* True if the macro is in a branch delay slot. */
1293 bfd_boolean delay_slot_p
;
1295 /* Set to the length in bytes required if the macro is in a delay slot
1296 that requires a specific length of instruction, otherwise zero. */
1297 unsigned int delay_slot_length
;
1299 /* For relaxable macros, sizes[0] is the length of the first alternative
1300 in bytes and sizes[1] is the length of the second alternative.
1301 For non-relaxable macros, both elements give the length of the
1303 unsigned int sizes
[2];
1305 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1306 instruction of the first alternative in bytes and first_insn_sizes[1]
1307 is the length of the first instruction of the second alternative.
1308 For non-relaxable macros, both elements give the length of the first
1309 instruction in bytes.
1311 Set to zero if we haven't yet seen the first instruction. */
1312 unsigned int first_insn_sizes
[2];
1314 /* For relaxable macros, insns[0] is the number of instructions for the
1315 first alternative and insns[1] is the number of instructions for the
1318 For non-relaxable macros, both elements give the number of
1319 instructions for the macro. */
1320 unsigned int insns
[2];
1322 /* The first variant frag for this macro. */
1324 } mips_macro_warning
;
1326 /* Prototypes for static functions. */
1328 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1330 static void append_insn
1331 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1332 bfd_boolean expansionp
);
1333 static void mips_no_prev_insn (void);
1334 static void macro_build (expressionS
*, const char *, const char *, ...);
1335 static void mips16_macro_build
1336 (expressionS
*, const char *, const char *, va_list *);
1337 static void load_register (int, expressionS
*, int);
1338 static void macro_start (void);
1339 static void macro_end (void);
1340 static void macro (struct mips_cl_insn
*ip
, char *str
);
1341 static void mips16_macro (struct mips_cl_insn
* ip
);
1342 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1343 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1344 static void mips16_immed
1345 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1346 unsigned int, unsigned long *);
1347 static size_t my_getSmallExpression
1348 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1349 static void my_getExpression (expressionS
*, char *);
1350 static void s_align (int);
1351 static void s_change_sec (int);
1352 static void s_change_section (int);
1353 static void s_cons (int);
1354 static void s_float_cons (int);
1355 static void s_mips_globl (int);
1356 static void s_option (int);
1357 static void s_mipsset (int);
1358 static void s_abicalls (int);
1359 static void s_cpload (int);
1360 static void s_cpsetup (int);
1361 static void s_cplocal (int);
1362 static void s_cprestore (int);
1363 static void s_cpreturn (int);
1364 static void s_dtprelword (int);
1365 static void s_dtpreldword (int);
1366 static void s_tprelword (int);
1367 static void s_tpreldword (int);
1368 static void s_gpvalue (int);
1369 static void s_gpword (int);
1370 static void s_gpdword (int);
1371 static void s_ehword (int);
1372 static void s_cpadd (int);
1373 static void s_insn (int);
1374 static void s_nan (int);
1375 static void s_module (int);
1376 static void s_mips_ent (int);
1377 static void s_mips_end (int);
1378 static void s_mips_frame (int);
1379 static void s_mips_mask (int reg_type
);
1380 static void s_mips_stab (int);
1381 static void s_mips_weakext (int);
1382 static void s_mips_file (int);
1383 static void s_mips_loc (int);
1384 static bfd_boolean
pic_need_relax (symbolS
*);
1385 static int relaxed_branch_length (fragS
*, asection
*, int);
1386 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1387 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1388 static void file_mips_check_options (void);
1390 /* Table and functions used to map between CPU/ISA names, and
1391 ISA levels, and CPU numbers. */
1393 struct mips_cpu_info
1395 const char *name
; /* CPU or ISA name. */
1396 int flags
; /* MIPS_CPU_* flags. */
1397 int ase
; /* Set of ASEs implemented by the CPU. */
1398 int isa
; /* ISA level. */
1399 int cpu
; /* CPU number (default CPU if ISA). */
1402 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1404 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1405 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1406 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1408 /* Command-line options. */
1409 const char *md_shortopts
= "O::g::G:";
1413 OPTION_MARCH
= OPTION_MD_BASE
,
1445 OPTION_NO_SMARTMIPS
,
1455 OPTION_NO_MICROMIPS
,
1458 OPTION_COMPAT_ARCH_BASE
,
1467 OPTION_M7000_HILO_FIX
,
1468 OPTION_MNO_7000_HILO_FIX
,
1472 OPTION_NO_FIX_RM7000
,
1473 OPTION_FIX_LOONGSON2F_JUMP
,
1474 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1475 OPTION_FIX_LOONGSON2F_NOP
,
1476 OPTION_NO_FIX_LOONGSON2F_NOP
,
1478 OPTION_NO_FIX_VR4120
,
1480 OPTION_NO_FIX_VR4130
,
1481 OPTION_FIX_CN63XXP1
,
1482 OPTION_NO_FIX_CN63XXP1
,
1489 OPTION_CONSTRUCT_FLOATS
,
1490 OPTION_NO_CONSTRUCT_FLOATS
,
1494 OPTION_RELAX_BRANCH
,
1495 OPTION_NO_RELAX_BRANCH
,
1496 OPTION_IGNORE_BRANCH_ISA
,
1497 OPTION_NO_IGNORE_BRANCH_ISA
,
1506 OPTION_SINGLE_FLOAT
,
1507 OPTION_DOUBLE_FLOAT
,
1520 OPTION_MVXWORKS_PIC
,
1523 OPTION_NO_ODD_SPREG
,
1527 struct option md_longopts
[] =
1529 /* Options which specify architecture. */
1530 {"march", required_argument
, NULL
, OPTION_MARCH
},
1531 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1532 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1533 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1534 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1535 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1536 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1537 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1538 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1539 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1540 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1541 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1542 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1543 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1544 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1545 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1546 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1547 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1549 /* Options which specify Application Specific Extensions (ASEs). */
1550 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1551 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1552 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1553 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1554 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1555 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1556 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1557 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1558 {"mmt", no_argument
, NULL
, OPTION_MT
},
1559 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1560 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1561 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1562 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1563 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1564 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1565 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1566 {"meva", no_argument
, NULL
, OPTION_EVA
},
1567 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1568 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1569 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1570 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1571 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1572 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1573 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1574 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1575 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1576 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1577 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1579 /* Old-style architecture options. Don't add more of these. */
1580 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1581 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1582 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1583 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1584 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1585 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1586 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1587 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1589 /* Options which enable bug fixes. */
1590 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1591 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1592 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1593 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1594 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1595 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1596 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1597 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1598 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1599 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1600 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1601 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1602 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1603 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1604 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1605 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1606 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1608 /* Miscellaneous options. */
1609 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1610 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1611 {"break", no_argument
, NULL
, OPTION_BREAK
},
1612 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1613 {"EB", no_argument
, NULL
, OPTION_EB
},
1614 {"EL", no_argument
, NULL
, OPTION_EL
},
1615 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1616 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1617 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1618 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1619 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1620 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1621 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1622 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1623 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1624 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1625 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1626 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1627 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1628 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1629 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1630 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1631 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1632 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1633 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1634 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1635 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1636 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1637 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1639 /* Strictly speaking this next option is ELF specific,
1640 but we allow it for other ports as well in order to
1641 make testing easier. */
1642 {"32", no_argument
, NULL
, OPTION_32
},
1644 /* ELF-specific options. */
1645 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1646 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1647 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1648 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1649 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1650 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1651 {"n32", no_argument
, NULL
, OPTION_N32
},
1652 {"64", no_argument
, NULL
, OPTION_64
},
1653 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1654 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1655 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1656 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1657 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1658 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1660 {NULL
, no_argument
, NULL
, 0}
1662 size_t md_longopts_size
= sizeof (md_longopts
);
1664 /* Information about either an Application Specific Extension or an
1665 optional architecture feature that, for simplicity, we treat in the
1666 same way as an ASE. */
1669 /* The name of the ASE, used in both the command-line and .set options. */
1672 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1673 and 64-bit architectures, the flags here refer to the subset that
1674 is available on both. */
1677 /* The ASE_* flag used for instructions that are available on 64-bit
1678 architectures but that are not included in FLAGS. */
1679 unsigned int flags64
;
1681 /* The command-line options that turn the ASE on and off. */
1685 /* The minimum required architecture revisions for MIPS32, MIPS64,
1686 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1689 int micromips32_rev
;
1690 int micromips64_rev
;
1692 /* The architecture where the ASE was removed or -1 if the extension has not
1697 /* A table of all supported ASEs. */
1698 static const struct mips_ase mips_ases
[] = {
1699 { "dsp", ASE_DSP
, ASE_DSP64
,
1700 OPTION_DSP
, OPTION_NO_DSP
,
1704 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1705 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1709 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1710 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1714 { "eva", ASE_EVA
, 0,
1715 OPTION_EVA
, OPTION_NO_EVA
,
1719 { "mcu", ASE_MCU
, 0,
1720 OPTION_MCU
, OPTION_NO_MCU
,
1724 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1725 { "mdmx", ASE_MDMX
, 0,
1726 OPTION_MDMX
, OPTION_NO_MDMX
,
1730 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1731 { "mips3d", ASE_MIPS3D
, 0,
1732 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1737 OPTION_MT
, OPTION_NO_MT
,
1741 { "smartmips", ASE_SMARTMIPS
, 0,
1742 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1746 { "virt", ASE_VIRT
, ASE_VIRT64
,
1747 OPTION_VIRT
, OPTION_NO_VIRT
,
1751 { "msa", ASE_MSA
, ASE_MSA64
,
1752 OPTION_MSA
, OPTION_NO_MSA
,
1756 { "xpa", ASE_XPA
, 0,
1757 OPTION_XPA
, OPTION_NO_XPA
,
1762 /* The set of ASEs that require -mfp64. */
1763 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1765 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1766 static const unsigned int mips_ase_groups
[] = {
1767 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1772 The following pseudo-ops from the Kane and Heinrich MIPS book
1773 should be defined here, but are currently unsupported: .alias,
1774 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1776 The following pseudo-ops from the Kane and Heinrich MIPS book are
1777 specific to the type of debugging information being generated, and
1778 should be defined by the object format: .aent, .begin, .bend,
1779 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1782 The following pseudo-ops from the Kane and Heinrich MIPS book are
1783 not MIPS CPU specific, but are also not specific to the object file
1784 format. This file is probably the best place to define them, but
1785 they are not currently supported: .asm0, .endr, .lab, .struct. */
1787 static const pseudo_typeS mips_pseudo_table
[] =
1789 /* MIPS specific pseudo-ops. */
1790 {"option", s_option
, 0},
1791 {"set", s_mipsset
, 0},
1792 {"rdata", s_change_sec
, 'r'},
1793 {"sdata", s_change_sec
, 's'},
1794 {"livereg", s_ignore
, 0},
1795 {"abicalls", s_abicalls
, 0},
1796 {"cpload", s_cpload
, 0},
1797 {"cpsetup", s_cpsetup
, 0},
1798 {"cplocal", s_cplocal
, 0},
1799 {"cprestore", s_cprestore
, 0},
1800 {"cpreturn", s_cpreturn
, 0},
1801 {"dtprelword", s_dtprelword
, 0},
1802 {"dtpreldword", s_dtpreldword
, 0},
1803 {"tprelword", s_tprelword
, 0},
1804 {"tpreldword", s_tpreldword
, 0},
1805 {"gpvalue", s_gpvalue
, 0},
1806 {"gpword", s_gpword
, 0},
1807 {"gpdword", s_gpdword
, 0},
1808 {"ehword", s_ehword
, 0},
1809 {"cpadd", s_cpadd
, 0},
1810 {"insn", s_insn
, 0},
1812 {"module", s_module
, 0},
1814 /* Relatively generic pseudo-ops that happen to be used on MIPS
1816 {"asciiz", stringer
, 8 + 1},
1817 {"bss", s_change_sec
, 'b'},
1819 {"half", s_cons
, 1},
1820 {"dword", s_cons
, 3},
1821 {"weakext", s_mips_weakext
, 0},
1822 {"origin", s_org
, 0},
1823 {"repeat", s_rept
, 0},
1825 /* For MIPS this is non-standard, but we define it for consistency. */
1826 {"sbss", s_change_sec
, 'B'},
1828 /* These pseudo-ops are defined in read.c, but must be overridden
1829 here for one reason or another. */
1830 {"align", s_align
, 0},
1831 {"byte", s_cons
, 0},
1832 {"data", s_change_sec
, 'd'},
1833 {"double", s_float_cons
, 'd'},
1834 {"float", s_float_cons
, 'f'},
1835 {"globl", s_mips_globl
, 0},
1836 {"global", s_mips_globl
, 0},
1837 {"hword", s_cons
, 1},
1839 {"long", s_cons
, 2},
1840 {"octa", s_cons
, 4},
1841 {"quad", s_cons
, 3},
1842 {"section", s_change_section
, 0},
1843 {"short", s_cons
, 1},
1844 {"single", s_float_cons
, 'f'},
1845 {"stabd", s_mips_stab
, 'd'},
1846 {"stabn", s_mips_stab
, 'n'},
1847 {"stabs", s_mips_stab
, 's'},
1848 {"text", s_change_sec
, 't'},
1849 {"word", s_cons
, 2},
1851 { "extern", ecoff_directive_extern
, 0},
1856 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1858 /* These pseudo-ops should be defined by the object file format.
1859 However, a.out doesn't support them, so we have versions here. */
1860 {"aent", s_mips_ent
, 1},
1861 {"bgnb", s_ignore
, 0},
1862 {"end", s_mips_end
, 0},
1863 {"endb", s_ignore
, 0},
1864 {"ent", s_mips_ent
, 0},
1865 {"file", s_mips_file
, 0},
1866 {"fmask", s_mips_mask
, 'F'},
1867 {"frame", s_mips_frame
, 0},
1868 {"loc", s_mips_loc
, 0},
1869 {"mask", s_mips_mask
, 'R'},
1870 {"verstamp", s_ignore
, 0},
1874 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1875 purpose of the `.dc.a' internal pseudo-op. */
1878 mips_address_bytes (void)
1880 file_mips_check_options ();
1881 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1884 extern void pop_insert (const pseudo_typeS
*);
1887 mips_pop_insert (void)
1889 pop_insert (mips_pseudo_table
);
1890 if (! ECOFF_DEBUGGING
)
1891 pop_insert (mips_nonecoff_pseudo_table
);
1894 /* Symbols labelling the current insn. */
1896 struct insn_label_list
1898 struct insn_label_list
*next
;
1902 static struct insn_label_list
*free_insn_labels
;
1903 #define label_list tc_segment_info_data.labels
1905 static void mips_clear_insn_labels (void);
1906 static void mips_mark_labels (void);
1907 static void mips_compressed_mark_labels (void);
1910 mips_clear_insn_labels (void)
1912 struct insn_label_list
**pl
;
1913 segment_info_type
*si
;
1917 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1920 si
= seg_info (now_seg
);
1921 *pl
= si
->label_list
;
1922 si
->label_list
= NULL
;
1926 /* Mark instruction labels in MIPS16/microMIPS mode. */
1929 mips_mark_labels (void)
1931 if (HAVE_CODE_COMPRESSION
)
1932 mips_compressed_mark_labels ();
1935 static char *expr_end
;
1937 /* An expression in a macro instruction. This is set by mips_ip and
1938 mips16_ip and when populated is always an O_constant. */
1940 static expressionS imm_expr
;
1942 /* The relocatable field in an instruction and the relocs associated
1943 with it. These variables are used for instructions like LUI and
1944 JAL as well as true offsets. They are also used for address
1945 operands in macros. */
1947 static expressionS offset_expr
;
1948 static bfd_reloc_code_real_type offset_reloc
[3]
1949 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1951 /* This is set to the resulting size of the instruction to be produced
1952 by mips16_ip if an explicit extension is used or by mips_ip if an
1953 explicit size is supplied. */
1955 static unsigned int forced_insn_length
;
1957 /* True if we are assembling an instruction. All dot symbols defined during
1958 this time should be treated as code labels. */
1960 static bfd_boolean mips_assembling_insn
;
1962 /* The pdr segment for per procedure frame/regmask info. Not used for
1965 static segT pdr_seg
;
1967 /* The default target format to use. */
1969 #if defined (TE_FreeBSD)
1970 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1971 #elif defined (TE_TMIPS)
1972 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1974 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1978 mips_target_format (void)
1980 switch (OUTPUT_FLAVOR
)
1982 case bfd_target_elf_flavour
:
1984 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1985 return (target_big_endian
1986 ? "elf32-bigmips-vxworks"
1987 : "elf32-littlemips-vxworks");
1989 return (target_big_endian
1990 ? (HAVE_64BIT_OBJECTS
1991 ? ELF_TARGET ("elf64-", "big")
1993 ? ELF_TARGET ("elf32-n", "big")
1994 : ELF_TARGET ("elf32-", "big")))
1995 : (HAVE_64BIT_OBJECTS
1996 ? ELF_TARGET ("elf64-", "little")
1998 ? ELF_TARGET ("elf32-n", "little")
1999 : ELF_TARGET ("elf32-", "little"))));
2006 /* Return the ISA revision that is currently in use, or 0 if we are
2007 generating code for MIPS V or below. */
2012 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2015 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2018 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2021 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2024 /* microMIPS implies revision 2 or above. */
2025 if (mips_opts
.micromips
)
2028 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2034 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2037 mips_ase_mask (unsigned int flags
)
2041 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2042 if (flags
& mips_ase_groups
[i
])
2043 flags
|= mips_ase_groups
[i
];
2047 /* Check whether the current ISA supports ASE. Issue a warning if
2051 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2055 static unsigned int warned_isa
;
2056 static unsigned int warned_fp32
;
2058 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2059 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2061 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2062 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2063 && (warned_isa
& ase
->flags
) != ase
->flags
)
2065 warned_isa
|= ase
->flags
;
2066 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2067 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2069 as_warn (_("the %d-bit %s architecture does not support the"
2070 " `%s' extension"), size
, base
, ase
->name
);
2072 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2073 ase
->name
, base
, size
, min_rev
);
2075 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2076 && (warned_isa
& ase
->flags
) != ase
->flags
)
2078 warned_isa
|= ase
->flags
;
2079 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2080 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2081 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2082 ase
->name
, base
, size
, ase
->rem_rev
);
2085 if ((ase
->flags
& FP64_ASES
)
2086 && mips_opts
.fp
!= 64
2087 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2089 warned_fp32
|= ase
->flags
;
2090 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2094 /* Check all enabled ASEs to see whether they are supported by the
2095 chosen architecture. */
2098 mips_check_isa_supports_ases (void)
2100 unsigned int i
, mask
;
2102 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2104 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2105 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2106 mips_check_isa_supports_ase (&mips_ases
[i
]);
2110 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2111 that were affected. */
2114 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2115 bfd_boolean enabled_p
)
2119 mask
= mips_ase_mask (ase
->flags
);
2122 opts
->ase
|= ase
->flags
;
2126 /* Return the ASE called NAME, or null if none. */
2128 static const struct mips_ase
*
2129 mips_lookup_ase (const char *name
)
2133 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2134 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2135 return &mips_ases
[i
];
2139 /* Return the length of a microMIPS instruction in bytes. If bits of
2140 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2141 otherwise it is a 32-bit instruction. */
2143 static inline unsigned int
2144 micromips_insn_length (const struct mips_opcode
*mo
)
2146 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2149 /* Return the length of MIPS16 instruction OPCODE. */
2151 static inline unsigned int
2152 mips16_opcode_length (unsigned long opcode
)
2154 return (opcode
>> 16) == 0 ? 2 : 4;
2157 /* Return the length of instruction INSN. */
2159 static inline unsigned int
2160 insn_length (const struct mips_cl_insn
*insn
)
2162 if (mips_opts
.micromips
)
2163 return micromips_insn_length (insn
->insn_mo
);
2164 else if (mips_opts
.mips16
)
2165 return mips16_opcode_length (insn
->insn_opcode
);
2170 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2173 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2178 insn
->insn_opcode
= mo
->match
;
2181 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2182 insn
->fixp
[i
] = NULL
;
2183 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2184 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2185 insn
->mips16_absolute_jump_p
= 0;
2186 insn
->complete_p
= 0;
2187 insn
->cleared_p
= 0;
2190 /* Get a list of all the operands in INSN. */
2192 static const struct mips_operand_array
*
2193 insn_operands (const struct mips_cl_insn
*insn
)
2195 if (insn
->insn_mo
>= &mips_opcodes
[0]
2196 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2197 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2199 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2200 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2201 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2203 if (insn
->insn_mo
>= µmips_opcodes
[0]
2204 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2205 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2210 /* Get a description of operand OPNO of INSN. */
2212 static const struct mips_operand
*
2213 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2215 const struct mips_operand_array
*operands
;
2217 operands
= insn_operands (insn
);
2218 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2220 return operands
->operand
[opno
];
2223 /* Install UVAL as the value of OPERAND in INSN. */
2226 insn_insert_operand (struct mips_cl_insn
*insn
,
2227 const struct mips_operand
*operand
, unsigned int uval
)
2229 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2232 /* Extract the value of OPERAND from INSN. */
2234 static inline unsigned
2235 insn_extract_operand (const struct mips_cl_insn
*insn
,
2236 const struct mips_operand
*operand
)
2238 return mips_extract_operand (operand
, insn
->insn_opcode
);
2241 /* Record the current MIPS16/microMIPS mode in now_seg. */
2244 mips_record_compressed_mode (void)
2246 segment_info_type
*si
;
2248 si
= seg_info (now_seg
);
2249 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2250 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2251 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2252 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2255 /* Read a standard MIPS instruction from BUF. */
2257 static unsigned long
2258 read_insn (char *buf
)
2260 if (target_big_endian
)
2261 return bfd_getb32 ((bfd_byte
*) buf
);
2263 return bfd_getl32 ((bfd_byte
*) buf
);
2266 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2270 write_insn (char *buf
, unsigned int insn
)
2272 md_number_to_chars (buf
, insn
, 4);
2276 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2277 has length LENGTH. */
2279 static unsigned long
2280 read_compressed_insn (char *buf
, unsigned int length
)
2286 for (i
= 0; i
< length
; i
+= 2)
2289 if (target_big_endian
)
2290 insn
|= bfd_getb16 ((char *) buf
);
2292 insn
|= bfd_getl16 ((char *) buf
);
2298 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2299 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2302 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2306 for (i
= 0; i
< length
; i
+= 2)
2307 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2308 return buf
+ length
;
2311 /* Install INSN at the location specified by its "frag" and "where" fields. */
2314 install_insn (const struct mips_cl_insn
*insn
)
2316 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2317 if (HAVE_CODE_COMPRESSION
)
2318 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2320 write_insn (f
, insn
->insn_opcode
);
2321 mips_record_compressed_mode ();
2324 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2325 and install the opcode in the new location. */
2328 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2333 insn
->where
= where
;
2334 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2335 if (insn
->fixp
[i
] != NULL
)
2337 insn
->fixp
[i
]->fx_frag
= frag
;
2338 insn
->fixp
[i
]->fx_where
= where
;
2340 install_insn (insn
);
2343 /* Add INSN to the end of the output. */
2346 add_fixed_insn (struct mips_cl_insn
*insn
)
2348 char *f
= frag_more (insn_length (insn
));
2349 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2352 /* Start a variant frag and move INSN to the start of the variant part,
2353 marking it as fixed. The other arguments are as for frag_var. */
2356 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2357 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2359 frag_grow (max_chars
);
2360 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2362 frag_var (rs_machine_dependent
, max_chars
, var
,
2363 subtype
, symbol
, offset
, NULL
);
2366 /* Insert N copies of INSN into the history buffer, starting at
2367 position FIRST. Neither FIRST nor N need to be clipped. */
2370 insert_into_history (unsigned int first
, unsigned int n
,
2371 const struct mips_cl_insn
*insn
)
2373 if (mips_relax
.sequence
!= 2)
2377 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2379 history
[i
] = history
[i
- n
];
2385 /* Clear the error in insn_error. */
2388 clear_insn_error (void)
2390 memset (&insn_error
, 0, sizeof (insn_error
));
2393 /* Possibly record error message MSG for the current instruction.
2394 If the error is about a particular argument, ARGNUM is the 1-based
2395 number of that argument, otherwise it is 0. FORMAT is the format
2396 of MSG. Return true if MSG was used, false if the current message
2400 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2405 /* Give priority to errors against specific arguments, and to
2406 the first whole-instruction message. */
2412 /* Keep insn_error if it is against a later argument. */
2413 if (argnum
< insn_error
.min_argnum
)
2416 /* If both errors are against the same argument but are different,
2417 give up on reporting a specific error for this argument.
2418 See the comment about mips_insn_error for details. */
2419 if (argnum
== insn_error
.min_argnum
2421 && strcmp (insn_error
.msg
, msg
) != 0)
2424 insn_error
.min_argnum
+= 1;
2428 insn_error
.min_argnum
= argnum
;
2429 insn_error
.format
= format
;
2430 insn_error
.msg
= msg
;
2434 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2435 as for set_insn_error_format. */
2438 set_insn_error (int argnum
, const char *msg
)
2440 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2443 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2444 as for set_insn_error_format. */
2447 set_insn_error_i (int argnum
, const char *msg
, int i
)
2449 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2453 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2454 are as for set_insn_error_format. */
2457 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2459 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2461 insn_error
.u
.ss
[0] = s1
;
2462 insn_error
.u
.ss
[1] = s2
;
2466 /* Report the error in insn_error, which is against assembly code STR. */
2469 report_insn_error (const char *str
)
2471 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2473 switch (insn_error
.format
)
2480 as_bad (msg
, insn_error
.u
.i
, str
);
2484 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2488 free ((char *) msg
);
2491 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2492 the idea is to make it obvious at a glance that each errata is
2496 init_vr4120_conflicts (void)
2498 #define CONFLICT(FIRST, SECOND) \
2499 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2501 /* Errata 21 - [D]DIV[U] after [D]MACC */
2502 CONFLICT (MACC
, DIV
);
2503 CONFLICT (DMACC
, DIV
);
2505 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2506 CONFLICT (DMULT
, DMULT
);
2507 CONFLICT (DMULT
, DMACC
);
2508 CONFLICT (DMACC
, DMULT
);
2509 CONFLICT (DMACC
, DMACC
);
2511 /* Errata 24 - MT{LO,HI} after [D]MACC */
2512 CONFLICT (MACC
, MTHILO
);
2513 CONFLICT (DMACC
, MTHILO
);
2515 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2516 instruction is executed immediately after a MACC or DMACC
2517 instruction, the result of [either instruction] is incorrect." */
2518 CONFLICT (MACC
, MULT
);
2519 CONFLICT (MACC
, DMULT
);
2520 CONFLICT (DMACC
, MULT
);
2521 CONFLICT (DMACC
, DMULT
);
2523 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2524 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2525 DDIV or DDIVU instruction, the result of the MACC or
2526 DMACC instruction is incorrect.". */
2527 CONFLICT (DMULT
, MACC
);
2528 CONFLICT (DMULT
, DMACC
);
2529 CONFLICT (DIV
, MACC
);
2530 CONFLICT (DIV
, DMACC
);
2540 #define RNUM_MASK 0x00000ff
2541 #define RTYPE_MASK 0x0ffff00
2542 #define RTYPE_NUM 0x0000100
2543 #define RTYPE_FPU 0x0000200
2544 #define RTYPE_FCC 0x0000400
2545 #define RTYPE_VEC 0x0000800
2546 #define RTYPE_GP 0x0001000
2547 #define RTYPE_CP0 0x0002000
2548 #define RTYPE_PC 0x0004000
2549 #define RTYPE_ACC 0x0008000
2550 #define RTYPE_CCC 0x0010000
2551 #define RTYPE_VI 0x0020000
2552 #define RTYPE_VF 0x0040000
2553 #define RTYPE_R5900_I 0x0080000
2554 #define RTYPE_R5900_Q 0x0100000
2555 #define RTYPE_R5900_R 0x0200000
2556 #define RTYPE_R5900_ACC 0x0400000
2557 #define RTYPE_MSA 0x0800000
2558 #define RWARN 0x8000000
2560 #define GENERIC_REGISTER_NUMBERS \
2561 {"$0", RTYPE_NUM | 0}, \
2562 {"$1", RTYPE_NUM | 1}, \
2563 {"$2", RTYPE_NUM | 2}, \
2564 {"$3", RTYPE_NUM | 3}, \
2565 {"$4", RTYPE_NUM | 4}, \
2566 {"$5", RTYPE_NUM | 5}, \
2567 {"$6", RTYPE_NUM | 6}, \
2568 {"$7", RTYPE_NUM | 7}, \
2569 {"$8", RTYPE_NUM | 8}, \
2570 {"$9", RTYPE_NUM | 9}, \
2571 {"$10", RTYPE_NUM | 10}, \
2572 {"$11", RTYPE_NUM | 11}, \
2573 {"$12", RTYPE_NUM | 12}, \
2574 {"$13", RTYPE_NUM | 13}, \
2575 {"$14", RTYPE_NUM | 14}, \
2576 {"$15", RTYPE_NUM | 15}, \
2577 {"$16", RTYPE_NUM | 16}, \
2578 {"$17", RTYPE_NUM | 17}, \
2579 {"$18", RTYPE_NUM | 18}, \
2580 {"$19", RTYPE_NUM | 19}, \
2581 {"$20", RTYPE_NUM | 20}, \
2582 {"$21", RTYPE_NUM | 21}, \
2583 {"$22", RTYPE_NUM | 22}, \
2584 {"$23", RTYPE_NUM | 23}, \
2585 {"$24", RTYPE_NUM | 24}, \
2586 {"$25", RTYPE_NUM | 25}, \
2587 {"$26", RTYPE_NUM | 26}, \
2588 {"$27", RTYPE_NUM | 27}, \
2589 {"$28", RTYPE_NUM | 28}, \
2590 {"$29", RTYPE_NUM | 29}, \
2591 {"$30", RTYPE_NUM | 30}, \
2592 {"$31", RTYPE_NUM | 31}
2594 #define FPU_REGISTER_NAMES \
2595 {"$f0", RTYPE_FPU | 0}, \
2596 {"$f1", RTYPE_FPU | 1}, \
2597 {"$f2", RTYPE_FPU | 2}, \
2598 {"$f3", RTYPE_FPU | 3}, \
2599 {"$f4", RTYPE_FPU | 4}, \
2600 {"$f5", RTYPE_FPU | 5}, \
2601 {"$f6", RTYPE_FPU | 6}, \
2602 {"$f7", RTYPE_FPU | 7}, \
2603 {"$f8", RTYPE_FPU | 8}, \
2604 {"$f9", RTYPE_FPU | 9}, \
2605 {"$f10", RTYPE_FPU | 10}, \
2606 {"$f11", RTYPE_FPU | 11}, \
2607 {"$f12", RTYPE_FPU | 12}, \
2608 {"$f13", RTYPE_FPU | 13}, \
2609 {"$f14", RTYPE_FPU | 14}, \
2610 {"$f15", RTYPE_FPU | 15}, \
2611 {"$f16", RTYPE_FPU | 16}, \
2612 {"$f17", RTYPE_FPU | 17}, \
2613 {"$f18", RTYPE_FPU | 18}, \
2614 {"$f19", RTYPE_FPU | 19}, \
2615 {"$f20", RTYPE_FPU | 20}, \
2616 {"$f21", RTYPE_FPU | 21}, \
2617 {"$f22", RTYPE_FPU | 22}, \
2618 {"$f23", RTYPE_FPU | 23}, \
2619 {"$f24", RTYPE_FPU | 24}, \
2620 {"$f25", RTYPE_FPU | 25}, \
2621 {"$f26", RTYPE_FPU | 26}, \
2622 {"$f27", RTYPE_FPU | 27}, \
2623 {"$f28", RTYPE_FPU | 28}, \
2624 {"$f29", RTYPE_FPU | 29}, \
2625 {"$f30", RTYPE_FPU | 30}, \
2626 {"$f31", RTYPE_FPU | 31}
2628 #define FPU_CONDITION_CODE_NAMES \
2629 {"$fcc0", RTYPE_FCC | 0}, \
2630 {"$fcc1", RTYPE_FCC | 1}, \
2631 {"$fcc2", RTYPE_FCC | 2}, \
2632 {"$fcc3", RTYPE_FCC | 3}, \
2633 {"$fcc4", RTYPE_FCC | 4}, \
2634 {"$fcc5", RTYPE_FCC | 5}, \
2635 {"$fcc6", RTYPE_FCC | 6}, \
2636 {"$fcc7", RTYPE_FCC | 7}
2638 #define COPROC_CONDITION_CODE_NAMES \
2639 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2640 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2641 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2642 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2643 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2644 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2645 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2646 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2648 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2649 {"$a4", RTYPE_GP | 8}, \
2650 {"$a5", RTYPE_GP | 9}, \
2651 {"$a6", RTYPE_GP | 10}, \
2652 {"$a7", RTYPE_GP | 11}, \
2653 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2654 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2655 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2656 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2657 {"$t0", RTYPE_GP | 12}, \
2658 {"$t1", RTYPE_GP | 13}, \
2659 {"$t2", RTYPE_GP | 14}, \
2660 {"$t3", RTYPE_GP | 15}
2662 #define O32_SYMBOLIC_REGISTER_NAMES \
2663 {"$t0", RTYPE_GP | 8}, \
2664 {"$t1", RTYPE_GP | 9}, \
2665 {"$t2", RTYPE_GP | 10}, \
2666 {"$t3", RTYPE_GP | 11}, \
2667 {"$t4", RTYPE_GP | 12}, \
2668 {"$t5", RTYPE_GP | 13}, \
2669 {"$t6", RTYPE_GP | 14}, \
2670 {"$t7", RTYPE_GP | 15}, \
2671 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2672 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2673 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2674 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2676 /* Remaining symbolic register names */
2677 #define SYMBOLIC_REGISTER_NAMES \
2678 {"$zero", RTYPE_GP | 0}, \
2679 {"$at", RTYPE_GP | 1}, \
2680 {"$AT", RTYPE_GP | 1}, \
2681 {"$v0", RTYPE_GP | 2}, \
2682 {"$v1", RTYPE_GP | 3}, \
2683 {"$a0", RTYPE_GP | 4}, \
2684 {"$a1", RTYPE_GP | 5}, \
2685 {"$a2", RTYPE_GP | 6}, \
2686 {"$a3", RTYPE_GP | 7}, \
2687 {"$s0", RTYPE_GP | 16}, \
2688 {"$s1", RTYPE_GP | 17}, \
2689 {"$s2", RTYPE_GP | 18}, \
2690 {"$s3", RTYPE_GP | 19}, \
2691 {"$s4", RTYPE_GP | 20}, \
2692 {"$s5", RTYPE_GP | 21}, \
2693 {"$s6", RTYPE_GP | 22}, \
2694 {"$s7", RTYPE_GP | 23}, \
2695 {"$t8", RTYPE_GP | 24}, \
2696 {"$t9", RTYPE_GP | 25}, \
2697 {"$k0", RTYPE_GP | 26}, \
2698 {"$kt0", RTYPE_GP | 26}, \
2699 {"$k1", RTYPE_GP | 27}, \
2700 {"$kt1", RTYPE_GP | 27}, \
2701 {"$gp", RTYPE_GP | 28}, \
2702 {"$sp", RTYPE_GP | 29}, \
2703 {"$s8", RTYPE_GP | 30}, \
2704 {"$fp", RTYPE_GP | 30}, \
2705 {"$ra", RTYPE_GP | 31}
2707 #define MIPS16_SPECIAL_REGISTER_NAMES \
2708 {"$pc", RTYPE_PC | 0}
2710 #define MDMX_VECTOR_REGISTER_NAMES \
2711 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2712 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2713 {"$v2", RTYPE_VEC | 2}, \
2714 {"$v3", RTYPE_VEC | 3}, \
2715 {"$v4", RTYPE_VEC | 4}, \
2716 {"$v5", RTYPE_VEC | 5}, \
2717 {"$v6", RTYPE_VEC | 6}, \
2718 {"$v7", RTYPE_VEC | 7}, \
2719 {"$v8", RTYPE_VEC | 8}, \
2720 {"$v9", RTYPE_VEC | 9}, \
2721 {"$v10", RTYPE_VEC | 10}, \
2722 {"$v11", RTYPE_VEC | 11}, \
2723 {"$v12", RTYPE_VEC | 12}, \
2724 {"$v13", RTYPE_VEC | 13}, \
2725 {"$v14", RTYPE_VEC | 14}, \
2726 {"$v15", RTYPE_VEC | 15}, \
2727 {"$v16", RTYPE_VEC | 16}, \
2728 {"$v17", RTYPE_VEC | 17}, \
2729 {"$v18", RTYPE_VEC | 18}, \
2730 {"$v19", RTYPE_VEC | 19}, \
2731 {"$v20", RTYPE_VEC | 20}, \
2732 {"$v21", RTYPE_VEC | 21}, \
2733 {"$v22", RTYPE_VEC | 22}, \
2734 {"$v23", RTYPE_VEC | 23}, \
2735 {"$v24", RTYPE_VEC | 24}, \
2736 {"$v25", RTYPE_VEC | 25}, \
2737 {"$v26", RTYPE_VEC | 26}, \
2738 {"$v27", RTYPE_VEC | 27}, \
2739 {"$v28", RTYPE_VEC | 28}, \
2740 {"$v29", RTYPE_VEC | 29}, \
2741 {"$v30", RTYPE_VEC | 30}, \
2742 {"$v31", RTYPE_VEC | 31}
2744 #define R5900_I_NAMES \
2745 {"$I", RTYPE_R5900_I | 0}
2747 #define R5900_Q_NAMES \
2748 {"$Q", RTYPE_R5900_Q | 0}
2750 #define R5900_R_NAMES \
2751 {"$R", RTYPE_R5900_R | 0}
2753 #define R5900_ACC_NAMES \
2754 {"$ACC", RTYPE_R5900_ACC | 0 }
2756 #define MIPS_DSP_ACCUMULATOR_NAMES \
2757 {"$ac0", RTYPE_ACC | 0}, \
2758 {"$ac1", RTYPE_ACC | 1}, \
2759 {"$ac2", RTYPE_ACC | 2}, \
2760 {"$ac3", RTYPE_ACC | 3}
2762 static const struct regname reg_names
[] = {
2763 GENERIC_REGISTER_NUMBERS
,
2765 FPU_CONDITION_CODE_NAMES
,
2766 COPROC_CONDITION_CODE_NAMES
,
2768 /* The $txx registers depends on the abi,
2769 these will be added later into the symbol table from
2770 one of the tables below once mips_abi is set after
2771 parsing of arguments from the command line. */
2772 SYMBOLIC_REGISTER_NAMES
,
2774 MIPS16_SPECIAL_REGISTER_NAMES
,
2775 MDMX_VECTOR_REGISTER_NAMES
,
2780 MIPS_DSP_ACCUMULATOR_NAMES
,
2784 static const struct regname reg_names_o32
[] = {
2785 O32_SYMBOLIC_REGISTER_NAMES
,
2789 static const struct regname reg_names_n32n64
[] = {
2790 N32N64_SYMBOLIC_REGISTER_NAMES
,
2794 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2795 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2796 of these register symbols, return the associated vector register,
2797 otherwise return SYMVAL itself. */
2800 mips_prefer_vec_regno (unsigned int symval
)
2802 if ((symval
& -2) == (RTYPE_GP
| 2))
2803 return RTYPE_VEC
| (symval
& 1);
2807 /* Return true if string [S, E) is a valid register name, storing its
2808 symbol value in *SYMVAL_PTR if so. */
2811 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2816 /* Terminate name. */
2820 /* Look up the name. */
2821 symbol
= symbol_find (s
);
2824 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2827 *symval_ptr
= S_GET_VALUE (symbol
);
2831 /* Return true if the string at *SPTR is a valid register name. Allow it
2832 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2835 When returning true, move *SPTR past the register, store the
2836 register's symbol value in *SYMVAL_PTR and the channel mask in
2837 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2838 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2839 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2842 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2843 unsigned int *channels_ptr
)
2847 unsigned int channels
, symval
, bit
;
2849 /* Find end of name. */
2851 if (is_name_beginner (*e
))
2853 while (is_part_of_name (*e
))
2857 if (!mips_parse_register_1 (s
, e
, &symval
))
2862 /* Eat characters from the end of the string that are valid
2863 channel suffixes. The preceding register must be $ACC or
2864 end with a digit, so there is no ambiguity. */
2867 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2868 if (m
> s
&& m
[-1] == *q
)
2875 || !mips_parse_register_1 (s
, m
, &symval
)
2876 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2881 *symval_ptr
= symval
;
2883 *channels_ptr
= channels
;
2887 /* Check if SPTR points at a valid register specifier according to TYPES.
2888 If so, then return 1, advance S to consume the specifier and store
2889 the register's number in REGNOP, otherwise return 0. */
2892 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2896 if (mips_parse_register (s
, ®no
, NULL
))
2898 if (types
& RTYPE_VEC
)
2899 regno
= mips_prefer_vec_regno (regno
);
2908 as_warn (_("unrecognized register name `%s'"), *s
);
2913 return regno
<= RNUM_MASK
;
2916 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2917 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2920 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2925 for (i
= 0; i
< 4; i
++)
2926 if (*s
== "xyzw"[i
])
2928 *channels
|= 1 << (3 - i
);
2934 /* Token types for parsed operand lists. */
2935 enum mips_operand_token_type
{
2936 /* A plain register, e.g. $f2. */
2939 /* A 4-bit XYZW channel mask. */
2942 /* A constant vector index, e.g. [1]. */
2945 /* A register vector index, e.g. [$2]. */
2948 /* A continuous range of registers, e.g. $s0-$s4. */
2951 /* A (possibly relocated) expression. */
2954 /* A floating-point value. */
2957 /* A single character. This can be '(', ')' or ',', but '(' only appears
2961 /* A doubled character, either "--" or "++". */
2964 /* The end of the operand list. */
2968 /* A parsed operand token. */
2969 struct mips_operand_token
2971 /* The type of token. */
2972 enum mips_operand_token_type type
;
2975 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2978 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2979 unsigned int channels
;
2981 /* The integer value of an OT_INTEGER_INDEX. */
2984 /* The two register symbol values involved in an OT_REG_RANGE. */
2986 unsigned int regno1
;
2987 unsigned int regno2
;
2990 /* The value of an OT_INTEGER. The value is represented as an
2991 expression and the relocation operators that were applied to
2992 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2993 relocation operators were used. */
2996 bfd_reloc_code_real_type relocs
[3];
2999 /* The binary data for an OT_FLOAT constant, and the number of bytes
3002 unsigned char data
[8];
3006 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3011 /* An obstack used to construct lists of mips_operand_tokens. */
3012 static struct obstack mips_operand_tokens
;
3014 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3017 mips_add_token (struct mips_operand_token
*token
,
3018 enum mips_operand_token_type type
)
3021 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3024 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3025 and OT_REG tokens for them if so, and return a pointer to the first
3026 unconsumed character. Return null otherwise. */
3029 mips_parse_base_start (char *s
)
3031 struct mips_operand_token token
;
3032 unsigned int regno
, channels
;
3033 bfd_boolean decrement_p
;
3039 SKIP_SPACE_TABS (s
);
3041 /* Only match "--" as part of a base expression. In other contexts "--X"
3042 is a double negative. */
3043 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3047 SKIP_SPACE_TABS (s
);
3050 /* Allow a channel specifier because that leads to better error messages
3051 than treating something like "$vf0x++" as an expression. */
3052 if (!mips_parse_register (&s
, ®no
, &channels
))
3056 mips_add_token (&token
, OT_CHAR
);
3061 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3064 token
.u
.regno
= regno
;
3065 mips_add_token (&token
, OT_REG
);
3069 token
.u
.channels
= channels
;
3070 mips_add_token (&token
, OT_CHANNELS
);
3073 /* For consistency, only match "++" as part of base expressions too. */
3074 SKIP_SPACE_TABS (s
);
3075 if (s
[0] == '+' && s
[1] == '+')
3079 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3085 /* Parse one or more tokens from S. Return a pointer to the first
3086 unconsumed character on success. Return null if an error was found
3087 and store the error text in insn_error. FLOAT_FORMAT is as for
3088 mips_parse_arguments. */
3091 mips_parse_argument_token (char *s
, char float_format
)
3093 char *end
, *save_in
;
3095 unsigned int regno1
, regno2
, channels
;
3096 struct mips_operand_token token
;
3098 /* First look for "($reg", since we want to treat that as an
3099 OT_CHAR and OT_REG rather than an expression. */
3100 end
= mips_parse_base_start (s
);
3104 /* Handle other characters that end up as OT_CHARs. */
3105 if (*s
== ')' || *s
== ',')
3108 mips_add_token (&token
, OT_CHAR
);
3113 /* Handle tokens that start with a register. */
3114 if (mips_parse_register (&s
, ®no1
, &channels
))
3118 /* A register and a VU0 channel suffix. */
3119 token
.u
.regno
= regno1
;
3120 mips_add_token (&token
, OT_REG
);
3122 token
.u
.channels
= channels
;
3123 mips_add_token (&token
, OT_CHANNELS
);
3127 SKIP_SPACE_TABS (s
);
3130 /* A register range. */
3132 SKIP_SPACE_TABS (s
);
3133 if (!mips_parse_register (&s
, ®no2
, NULL
))
3135 set_insn_error (0, _("invalid register range"));
3139 token
.u
.reg_range
.regno1
= regno1
;
3140 token
.u
.reg_range
.regno2
= regno2
;
3141 mips_add_token (&token
, OT_REG_RANGE
);
3145 /* Add the register itself. */
3146 token
.u
.regno
= regno1
;
3147 mips_add_token (&token
, OT_REG
);
3149 /* Check for a vector index. */
3153 SKIP_SPACE_TABS (s
);
3154 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3155 mips_add_token (&token
, OT_REG_INDEX
);
3158 expressionS element
;
3160 my_getExpression (&element
, s
);
3161 if (element
.X_op
!= O_constant
)
3163 set_insn_error (0, _("vector element must be constant"));
3167 token
.u
.index
= element
.X_add_number
;
3168 mips_add_token (&token
, OT_INTEGER_INDEX
);
3170 SKIP_SPACE_TABS (s
);
3173 set_insn_error (0, _("missing `]'"));
3183 /* First try to treat expressions as floats. */
3184 save_in
= input_line_pointer
;
3185 input_line_pointer
= s
;
3186 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3187 &token
.u
.flt
.length
);
3188 end
= input_line_pointer
;
3189 input_line_pointer
= save_in
;
3192 set_insn_error (0, err
);
3197 mips_add_token (&token
, OT_FLOAT
);
3202 /* Treat everything else as an integer expression. */
3203 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3204 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3205 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3206 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3208 mips_add_token (&token
, OT_INTEGER
);
3212 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3213 if expressions should be treated as 32-bit floating-point constants,
3214 'd' if they should be treated as 64-bit floating-point constants,
3215 or 0 if they should be treated as integer expressions (the usual case).
3217 Return a list of tokens on success, otherwise return 0. The caller
3218 must obstack_free the list after use. */
3220 static struct mips_operand_token
*
3221 mips_parse_arguments (char *s
, char float_format
)
3223 struct mips_operand_token token
;
3225 SKIP_SPACE_TABS (s
);
3228 s
= mips_parse_argument_token (s
, float_format
);
3231 obstack_free (&mips_operand_tokens
,
3232 obstack_finish (&mips_operand_tokens
));
3235 SKIP_SPACE_TABS (s
);
3237 mips_add_token (&token
, OT_END
);
3238 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3241 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3242 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3245 is_opcode_valid (const struct mips_opcode
*mo
)
3247 int isa
= mips_opts
.isa
;
3248 int ase
= mips_opts
.ase
;
3252 if (ISA_HAS_64BIT_REGS (isa
))
3253 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3254 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3255 ase
|= mips_ases
[i
].flags64
;
3257 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3260 /* Check whether the instruction or macro requires single-precision or
3261 double-precision floating-point support. Note that this information is
3262 stored differently in the opcode table for insns and macros. */
3263 if (mo
->pinfo
== INSN_MACRO
)
3265 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3266 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3270 fp_s
= mo
->pinfo
& FP_S
;
3271 fp_d
= mo
->pinfo
& FP_D
;
3274 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3277 if (fp_s
&& mips_opts
.soft_float
)
3283 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3284 selected ISA and architecture. */
3287 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3289 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3292 /* Return TRUE if the size of the microMIPS opcode MO matches one
3293 explicitly requested. Always TRUE in the standard MIPS mode.
3294 Use is_size_valid_16 for MIPS16 opcodes. */
3297 is_size_valid (const struct mips_opcode
*mo
)
3299 if (!mips_opts
.micromips
)
3302 if (mips_opts
.insn32
)
3304 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3306 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3309 if (!forced_insn_length
)
3311 if (mo
->pinfo
== INSN_MACRO
)
3313 return forced_insn_length
== micromips_insn_length (mo
);
3316 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3317 explicitly requested. */
3320 is_size_valid_16 (const struct mips_opcode
*mo
)
3322 if (!forced_insn_length
)
3324 if (mo
->pinfo
== INSN_MACRO
)
3326 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3328 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3333 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3334 of the preceding instruction. Always TRUE in the standard MIPS mode.
3336 We don't accept macros in 16-bit delay slots to avoid a case where
3337 a macro expansion fails because it relies on a preceding 32-bit real
3338 instruction to have matched and does not handle the operands correctly.
3339 The only macros that may expand to 16-bit instructions are JAL that
3340 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3341 and BGT (that likewise cannot be placed in a delay slot) that decay to
3342 a NOP. In all these cases the macros precede any corresponding real
3343 instruction definitions in the opcode table, so they will match in the
3344 second pass where the size of the delay slot is ignored and therefore
3345 produce correct code. */
3348 is_delay_slot_valid (const struct mips_opcode
*mo
)
3350 if (!mips_opts
.micromips
)
3353 if (mo
->pinfo
== INSN_MACRO
)
3354 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3355 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3356 && micromips_insn_length (mo
) != 4)
3358 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3359 && micromips_insn_length (mo
) != 2)
3365 /* For consistency checking, verify that all bits of OPCODE are specified
3366 either by the match/mask part of the instruction definition, or by the
3367 operand list. Also build up a list of operands in OPERANDS.
3369 INSN_BITS says which bits of the instruction are significant.
3370 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3371 provides the mips_operand description of each operand. DECODE_OPERAND
3372 is null for MIPS16 instructions. */
3375 validate_mips_insn (const struct mips_opcode
*opcode
,
3376 unsigned long insn_bits
,
3377 const struct mips_operand
*(*decode_operand
) (const char *),
3378 struct mips_operand_array
*operands
)
3381 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3382 const struct mips_operand
*operand
;
3384 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3385 if ((mask
& opcode
->match
) != opcode
->match
)
3387 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3388 opcode
->name
, opcode
->args
);
3393 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3394 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3395 for (s
= opcode
->args
; *s
; ++s
)
3408 if (!decode_operand
)
3409 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3411 operand
= decode_operand (s
);
3412 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3414 as_bad (_("internal: unknown operand type: %s %s"),
3415 opcode
->name
, opcode
->args
);
3418 gas_assert (opno
< MAX_OPERANDS
);
3419 operands
->operand
[opno
] = operand
;
3420 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3422 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3423 if (operand
->type
== OP_MDMX_IMM_REG
)
3424 /* Bit 5 is the format selector (OB vs QH). The opcode table
3425 has separate entries for each format. */
3426 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3427 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3428 used_bits
&= ~(mask
& 0x700);
3430 /* Skip prefix characters. */
3431 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3436 doubled
= used_bits
& mask
& insn_bits
;
3439 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3440 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3444 undefined
= ~used_bits
& insn_bits
;
3445 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3447 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3448 undefined
, opcode
->name
, opcode
->args
);
3451 used_bits
&= ~insn_bits
;
3454 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3455 used_bits
, opcode
->name
, opcode
->args
);
3461 /* The MIPS16 version of validate_mips_insn. */
3464 validate_mips16_insn (const struct mips_opcode
*opcode
,
3465 struct mips_operand_array
*operands
)
3467 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3469 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3472 /* The microMIPS version of validate_mips_insn. */
3475 validate_micromips_insn (const struct mips_opcode
*opc
,
3476 struct mips_operand_array
*operands
)
3478 unsigned long insn_bits
;
3479 unsigned long major
;
3480 unsigned int length
;
3482 if (opc
->pinfo
== INSN_MACRO
)
3483 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3486 length
= micromips_insn_length (opc
);
3487 if (length
!= 2 && length
!= 4)
3489 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3490 "%s %s"), length
, opc
->name
, opc
->args
);
3493 major
= opc
->match
>> (10 + 8 * (length
- 2));
3494 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3495 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3497 as_bad (_("internal error: bad microMIPS opcode "
3498 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3502 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3503 insn_bits
= 1 << 4 * length
;
3504 insn_bits
<<= 4 * length
;
3506 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3510 /* This function is called once, at assembler startup time. It should set up
3511 all the tables, etc. that the MD part of the assembler will need. */
3516 const char *retval
= NULL
;
3520 if (mips_pic
!= NO_PIC
)
3522 if (g_switch_seen
&& g_switch_value
!= 0)
3523 as_bad (_("-G may not be used in position-independent code"));
3526 else if (mips_abicalls
)
3528 if (g_switch_seen
&& g_switch_value
!= 0)
3529 as_bad (_("-G may not be used with abicalls"));
3533 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3534 as_warn (_("could not set architecture and machine"));
3536 op_hash
= hash_new ();
3538 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3539 for (i
= 0; i
< NUMOPCODES
;)
3541 const char *name
= mips_opcodes
[i
].name
;
3543 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3546 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3547 mips_opcodes
[i
].name
, retval
);
3548 /* Probably a memory allocation problem? Give up now. */
3549 as_fatal (_("broken assembler, no assembly attempted"));
3553 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3554 decode_mips_operand
, &mips_operands
[i
]))
3556 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3558 create_insn (&nop_insn
, mips_opcodes
+ i
);
3559 if (mips_fix_loongson2f_nop
)
3560 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3561 nop_insn
.fixed_p
= 1;
3565 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3568 mips16_op_hash
= hash_new ();
3569 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3570 bfd_mips16_num_opcodes
);
3573 while (i
< bfd_mips16_num_opcodes
)
3575 const char *name
= mips16_opcodes
[i
].name
;
3577 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3579 as_fatal (_("internal: can't hash `%s': %s"),
3580 mips16_opcodes
[i
].name
, retval
);
3583 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3585 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3587 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3588 mips16_nop_insn
.fixed_p
= 1;
3592 while (i
< bfd_mips16_num_opcodes
3593 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3596 micromips_op_hash
= hash_new ();
3597 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3598 bfd_micromips_num_opcodes
);
3601 while (i
< bfd_micromips_num_opcodes
)
3603 const char *name
= micromips_opcodes
[i
].name
;
3605 retval
= hash_insert (micromips_op_hash
, name
,
3606 (void *) µmips_opcodes
[i
]);
3608 as_fatal (_("internal: can't hash `%s': %s"),
3609 micromips_opcodes
[i
].name
, retval
);
3612 struct mips_cl_insn
*micromips_nop_insn
;
3614 if (!validate_micromips_insn (µmips_opcodes
[i
],
3615 µmips_operands
[i
]))
3618 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3620 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3621 micromips_nop_insn
= µmips_nop16_insn
;
3622 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3623 micromips_nop_insn
= µmips_nop32_insn
;
3627 if (micromips_nop_insn
->insn_mo
== NULL
3628 && strcmp (name
, "nop") == 0)
3630 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3631 micromips_nop_insn
->fixed_p
= 1;
3635 while (++i
< bfd_micromips_num_opcodes
3636 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3640 as_fatal (_("broken assembler, no assembly attempted"));
3642 /* We add all the general register names to the symbol table. This
3643 helps us detect invalid uses of them. */
3644 for (i
= 0; reg_names
[i
].name
; i
++)
3645 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3646 reg_names
[i
].num
, /* & RNUM_MASK, */
3647 &zero_address_frag
));
3649 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3650 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3651 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3652 &zero_address_frag
));
3654 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3655 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3656 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3657 &zero_address_frag
));
3659 for (i
= 0; i
< 32; i
++)
3663 /* R5900 VU0 floating-point register. */
3664 sprintf (regname
, "$vf%d", i
);
3665 symbol_table_insert (symbol_new (regname
, reg_section
,
3666 RTYPE_VF
| i
, &zero_address_frag
));
3668 /* R5900 VU0 integer register. */
3669 sprintf (regname
, "$vi%d", i
);
3670 symbol_table_insert (symbol_new (regname
, reg_section
,
3671 RTYPE_VI
| i
, &zero_address_frag
));
3674 sprintf (regname
, "$w%d", i
);
3675 symbol_table_insert (symbol_new (regname
, reg_section
,
3676 RTYPE_MSA
| i
, &zero_address_frag
));
3679 obstack_init (&mips_operand_tokens
);
3681 mips_no_prev_insn ();
3684 mips_cprmask
[0] = 0;
3685 mips_cprmask
[1] = 0;
3686 mips_cprmask
[2] = 0;
3687 mips_cprmask
[3] = 0;
3689 /* set the default alignment for the text section (2**2) */
3690 record_alignment (text_section
, 2);
3692 bfd_set_gp_size (stdoutput
, g_switch_value
);
3694 /* On a native system other than VxWorks, sections must be aligned
3695 to 16 byte boundaries. When configured for an embedded ELF
3696 target, we don't bother. */
3697 if (strncmp (TARGET_OS
, "elf", 3) != 0
3698 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3700 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3701 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3702 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3705 /* Create a .reginfo section for register masks and a .mdebug
3706 section for debugging information. */
3714 subseg
= now_subseg
;
3716 /* The ABI says this section should be loaded so that the
3717 running program can access it. However, we don't load it
3718 if we are configured for an embedded target */
3719 flags
= SEC_READONLY
| SEC_DATA
;
3720 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3721 flags
|= SEC_ALLOC
| SEC_LOAD
;
3723 if (mips_abi
!= N64_ABI
)
3725 sec
= subseg_new (".reginfo", (subsegT
) 0);
3727 bfd_set_section_flags (stdoutput
, sec
, flags
);
3728 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3730 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3734 /* The 64-bit ABI uses a .MIPS.options section rather than
3735 .reginfo section. */
3736 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3737 bfd_set_section_flags (stdoutput
, sec
, flags
);
3738 bfd_set_section_alignment (stdoutput
, sec
, 3);
3740 /* Set up the option header. */
3742 Elf_Internal_Options opthdr
;
3745 opthdr
.kind
= ODK_REGINFO
;
3746 opthdr
.size
= (sizeof (Elf_External_Options
)
3747 + sizeof (Elf64_External_RegInfo
));
3750 f
= frag_more (sizeof (Elf_External_Options
));
3751 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3752 (Elf_External_Options
*) f
);
3754 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3758 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3759 bfd_set_section_flags (stdoutput
, sec
,
3760 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3761 bfd_set_section_alignment (stdoutput
, sec
, 3);
3762 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3764 if (ECOFF_DEBUGGING
)
3766 sec
= subseg_new (".mdebug", (subsegT
) 0);
3767 (void) bfd_set_section_flags (stdoutput
, sec
,
3768 SEC_HAS_CONTENTS
| SEC_READONLY
);
3769 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3771 else if (mips_flag_pdr
)
3773 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3774 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3775 SEC_READONLY
| SEC_RELOC
3777 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3780 subseg_set (seg
, subseg
);
3783 if (mips_fix_vr4120
)
3784 init_vr4120_conflicts ();
3788 fpabi_incompatible_with (int fpabi
, const char *what
)
3790 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3791 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3795 fpabi_requires (int fpabi
, const char *what
)
3797 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3798 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3801 /* Check -mabi and register sizes against the specified FP ABI. */
3803 check_fpabi (int fpabi
)
3807 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3808 if (file_mips_opts
.soft_float
)
3809 fpabi_incompatible_with (fpabi
, "softfloat");
3810 else if (file_mips_opts
.single_float
)
3811 fpabi_incompatible_with (fpabi
, "singlefloat");
3812 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3813 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3814 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3815 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3818 case Val_GNU_MIPS_ABI_FP_XX
:
3819 if (mips_abi
!= O32_ABI
)
3820 fpabi_requires (fpabi
, "-mabi=32");
3821 else if (file_mips_opts
.soft_float
)
3822 fpabi_incompatible_with (fpabi
, "softfloat");
3823 else if (file_mips_opts
.single_float
)
3824 fpabi_incompatible_with (fpabi
, "singlefloat");
3825 else if (file_mips_opts
.fp
!= 0)
3826 fpabi_requires (fpabi
, "fp=xx");
3829 case Val_GNU_MIPS_ABI_FP_64A
:
3830 case Val_GNU_MIPS_ABI_FP_64
:
3831 if (mips_abi
!= O32_ABI
)
3832 fpabi_requires (fpabi
, "-mabi=32");
3833 else if (file_mips_opts
.soft_float
)
3834 fpabi_incompatible_with (fpabi
, "softfloat");
3835 else if (file_mips_opts
.single_float
)
3836 fpabi_incompatible_with (fpabi
, "singlefloat");
3837 else if (file_mips_opts
.fp
!= 64)
3838 fpabi_requires (fpabi
, "fp=64");
3839 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3840 fpabi_incompatible_with (fpabi
, "nooddspreg");
3841 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3842 fpabi_requires (fpabi
, "nooddspreg");
3845 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3846 if (file_mips_opts
.soft_float
)
3847 fpabi_incompatible_with (fpabi
, "softfloat");
3848 else if (!file_mips_opts
.single_float
)
3849 fpabi_requires (fpabi
, "singlefloat");
3852 case Val_GNU_MIPS_ABI_FP_SOFT
:
3853 if (!file_mips_opts
.soft_float
)
3854 fpabi_requires (fpabi
, "softfloat");
3857 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3858 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3859 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3862 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3863 /* Silently ignore compatibility value. */
3867 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3868 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3873 /* Perform consistency checks on the current options. */
3876 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3878 /* Check the size of integer registers agrees with the ABI and ISA. */
3879 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3880 as_bad (_("`gp=64' used with a 32-bit processor"));
3882 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3883 as_bad (_("`gp=32' used with a 64-bit ABI"));
3885 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3886 as_bad (_("`gp=64' used with a 32-bit ABI"));
3888 /* Check the size of the float registers agrees with the ABI and ISA. */
3892 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3893 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3894 else if (opts
->single_float
== 1)
3895 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3898 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3899 as_bad (_("`fp=64' used with a 32-bit fpu"));
3901 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3902 && !ISA_HAS_MXHC1 (opts
->isa
))
3903 as_warn (_("`fp=64' used with a 32-bit ABI"));
3907 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3908 as_warn (_("`fp=32' used with a 64-bit ABI"));
3909 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3910 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3913 as_bad (_("Unknown size of floating point registers"));
3917 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3918 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3920 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3921 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3922 else if (ISA_IS_R6 (opts
->isa
)
3923 && (opts
->micromips
== 1
3924 || opts
->mips16
== 1))
3925 as_fatal (_("`%s' cannot be used with `%s'"),
3926 opts
->micromips
? "micromips" : "mips16",
3927 mips_cpu_info_from_isa (opts
->isa
)->name
);
3929 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3930 as_fatal (_("branch relaxation is not supported in `%s'"),
3931 mips_cpu_info_from_isa (opts
->isa
)->name
);
3934 /* Perform consistency checks on the module level options exactly once.
3935 This is a deferred check that happens:
3936 at the first .set directive
3937 or, at the first pseudo op that generates code (inc .dc.a)
3938 or, at the first instruction
3942 file_mips_check_options (void)
3944 const struct mips_cpu_info
*arch_info
= 0;
3946 if (file_mips_opts_checked
)
3949 /* The following code determines the register size.
3950 Similar code was added to GCC 3.3 (see override_options() in
3951 config/mips/mips.c). The GAS and GCC code should be kept in sync
3952 as much as possible. */
3954 if (file_mips_opts
.gp
< 0)
3956 /* Infer the integer register size from the ABI and processor.
3957 Restrict ourselves to 32-bit registers if that's all the
3958 processor has, or if the ABI cannot handle 64-bit registers. */
3959 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3960 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3964 if (file_mips_opts
.fp
< 0)
3966 /* No user specified float register size.
3967 ??? GAS treats single-float processors as though they had 64-bit
3968 float registers (although it complains when double-precision
3969 instructions are used). As things stand, saying they have 32-bit
3970 registers would lead to spurious "register must be even" messages.
3971 So here we assume float registers are never smaller than the
3973 if (file_mips_opts
.gp
== 64)
3974 /* 64-bit integer registers implies 64-bit float registers. */
3975 file_mips_opts
.fp
= 64;
3976 else if ((file_mips_opts
.ase
& FP64_ASES
)
3977 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3978 /* Handle ASEs that require 64-bit float registers, if possible. */
3979 file_mips_opts
.fp
= 64;
3980 else if (ISA_IS_R6 (mips_opts
.isa
))
3981 /* R6 implies 64-bit float registers. */
3982 file_mips_opts
.fp
= 64;
3984 /* 32-bit float registers. */
3985 file_mips_opts
.fp
= 32;
3988 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3990 /* Disable operations on odd-numbered floating-point registers by default
3991 when using the FPXX ABI. */
3992 if (file_mips_opts
.oddspreg
< 0)
3994 if (file_mips_opts
.fp
== 0)
3995 file_mips_opts
.oddspreg
= 0;
3997 file_mips_opts
.oddspreg
= 1;
4000 /* End of GCC-shared inference code. */
4002 /* This flag is set when we have a 64-bit capable CPU but use only
4003 32-bit wide registers. Note that EABI does not use it. */
4004 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4005 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4006 || mips_abi
== O32_ABI
))
4009 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4010 as_bad (_("trap exception not supported at ISA 1"));
4012 /* If the selected architecture includes support for ASEs, enable
4013 generation of code for them. */
4014 if (file_mips_opts
.mips16
== -1)
4015 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4016 if (file_mips_opts
.micromips
== -1)
4017 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4020 if (mips_nan2008
== -1)
4021 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4022 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4023 as_fatal (_("`%s' does not support legacy NaN"),
4024 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4026 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4027 being selected implicitly. */
4028 if (file_mips_opts
.fp
!= 64)
4029 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4031 /* If the user didn't explicitly select or deselect a particular ASE,
4032 use the default setting for the CPU. */
4033 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4035 /* Set up the current options. These may change throughout assembly. */
4036 mips_opts
= file_mips_opts
;
4038 mips_check_isa_supports_ases ();
4039 mips_check_options (&file_mips_opts
, TRUE
);
4040 file_mips_opts_checked
= TRUE
;
4042 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4043 as_warn (_("could not set architecture and machine"));
4047 md_assemble (char *str
)
4049 struct mips_cl_insn insn
;
4050 bfd_reloc_code_real_type unused_reloc
[3]
4051 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4053 file_mips_check_options ();
4055 imm_expr
.X_op
= O_absent
;
4056 offset_expr
.X_op
= O_absent
;
4057 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4058 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4059 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4061 mips_mark_labels ();
4062 mips_assembling_insn
= TRUE
;
4063 clear_insn_error ();
4065 if (mips_opts
.mips16
)
4066 mips16_ip (str
, &insn
);
4069 mips_ip (str
, &insn
);
4070 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4071 str
, insn
.insn_opcode
));
4075 report_insn_error (str
);
4076 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4079 if (mips_opts
.mips16
)
4080 mips16_macro (&insn
);
4087 if (offset_expr
.X_op
!= O_absent
)
4088 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4090 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4093 mips_assembling_insn
= FALSE
;
4096 /* Convenience functions for abstracting away the differences between
4097 MIPS16 and non-MIPS16 relocations. */
4099 static inline bfd_boolean
4100 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4104 case BFD_RELOC_MIPS16_JMP
:
4105 case BFD_RELOC_MIPS16_GPREL
:
4106 case BFD_RELOC_MIPS16_GOT16
:
4107 case BFD_RELOC_MIPS16_CALL16
:
4108 case BFD_RELOC_MIPS16_HI16_S
:
4109 case BFD_RELOC_MIPS16_HI16
:
4110 case BFD_RELOC_MIPS16_LO16
:
4111 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4119 static inline bfd_boolean
4120 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4124 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4125 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4126 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4127 case BFD_RELOC_MICROMIPS_GPREL16
:
4128 case BFD_RELOC_MICROMIPS_JMP
:
4129 case BFD_RELOC_MICROMIPS_HI16
:
4130 case BFD_RELOC_MICROMIPS_HI16_S
:
4131 case BFD_RELOC_MICROMIPS_LO16
:
4132 case BFD_RELOC_MICROMIPS_LITERAL
:
4133 case BFD_RELOC_MICROMIPS_GOT16
:
4134 case BFD_RELOC_MICROMIPS_CALL16
:
4135 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4136 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4137 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4138 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4139 case BFD_RELOC_MICROMIPS_SUB
:
4140 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4141 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4142 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4143 case BFD_RELOC_MICROMIPS_HIGHEST
:
4144 case BFD_RELOC_MICROMIPS_HIGHER
:
4145 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4146 case BFD_RELOC_MICROMIPS_JALR
:
4154 static inline bfd_boolean
4155 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4157 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4160 static inline bfd_boolean
4161 b_reloc_p (bfd_reloc_code_real_type reloc
)
4163 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4164 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4165 || reloc
== BFD_RELOC_16_PCREL_S2
4166 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4167 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4168 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4169 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4172 static inline bfd_boolean
4173 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4175 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4176 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4179 static inline bfd_boolean
4180 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4182 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4183 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4186 static inline bfd_boolean
4187 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4189 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4190 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4193 static inline bfd_boolean
4194 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4196 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4199 static inline bfd_boolean
4200 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4202 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4203 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4206 /* Return true if RELOC is a PC-relative relocation that does not have
4207 full address range. */
4209 static inline bfd_boolean
4210 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4214 case BFD_RELOC_16_PCREL_S2
:
4215 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4216 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4217 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4218 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4219 case BFD_RELOC_MIPS_21_PCREL_S2
:
4220 case BFD_RELOC_MIPS_26_PCREL_S2
:
4221 case BFD_RELOC_MIPS_18_PCREL_S3
:
4222 case BFD_RELOC_MIPS_19_PCREL_S2
:
4225 case BFD_RELOC_32_PCREL
:
4226 case BFD_RELOC_HI16_S_PCREL
:
4227 case BFD_RELOC_LO16_PCREL
:
4228 return HAVE_64BIT_ADDRESSES
;
4235 /* Return true if the given relocation might need a matching %lo().
4236 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4237 need a matching %lo() when applied to local symbols. */
4239 static inline bfd_boolean
4240 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4242 return (HAVE_IN_PLACE_ADDENDS
4243 && (hi16_reloc_p (reloc
)
4244 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4245 all GOT16 relocations evaluate to "G". */
4246 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4249 /* Return the type of %lo() reloc needed by RELOC, given that
4250 reloc_needs_lo_p. */
4252 static inline bfd_reloc_code_real_type
4253 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4255 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4256 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4260 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4263 static inline bfd_boolean
4264 fixup_has_matching_lo_p (fixS
*fixp
)
4266 return (fixp
->fx_next
!= NULL
4267 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4268 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4269 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4272 /* Move all labels in LABELS to the current insertion point. TEXT_P
4273 says whether the labels refer to text or data. */
4276 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4278 struct insn_label_list
*l
;
4281 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4283 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4284 symbol_set_frag (l
->label
, frag_now
);
4285 val
= (valueT
) frag_now_fix ();
4286 /* MIPS16/microMIPS text labels are stored as odd. */
4287 if (text_p
&& HAVE_CODE_COMPRESSION
)
4289 S_SET_VALUE (l
->label
, val
);
4293 /* Move all labels in insn_labels to the current insertion point
4294 and treat them as text labels. */
4297 mips_move_text_labels (void)
4299 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4302 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4305 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4307 bfd_boolean linkonce
= FALSE
;
4308 segT symseg
= S_GET_SEGMENT (sym
);
4310 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4312 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4314 /* The GNU toolchain uses an extension for ELF: a section
4315 beginning with the magic string .gnu.linkonce is a
4316 linkonce section. */
4317 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4318 sizeof ".gnu.linkonce" - 1) == 0)
4324 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4325 linker to handle them specially, such as generating jalx instructions
4326 when needed. We also make them odd for the duration of the assembly,
4327 in order to generate the right sort of code. We will make them even
4328 in the adjust_symtab routine, while leaving them marked. This is
4329 convenient for the debugger and the disassembler. The linker knows
4330 to make them odd again. */
4333 mips_compressed_mark_label (symbolS
*label
)
4335 gas_assert (HAVE_CODE_COMPRESSION
);
4337 if (mips_opts
.mips16
)
4338 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4340 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4341 if ((S_GET_VALUE (label
) & 1) == 0
4342 /* Don't adjust the address if the label is global or weak, or
4343 in a link-once section, since we'll be emitting symbol reloc
4344 references to it which will be patched up by the linker, and
4345 the final value of the symbol may or may not be MIPS16/microMIPS. */
4346 && !S_IS_WEAK (label
)
4347 && !S_IS_EXTERNAL (label
)
4348 && !s_is_linkonce (label
, now_seg
))
4349 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4352 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4355 mips_compressed_mark_labels (void)
4357 struct insn_label_list
*l
;
4359 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4360 mips_compressed_mark_label (l
->label
);
4363 /* End the current frag. Make it a variant frag and record the
4367 relax_close_frag (void)
4369 mips_macro_warning
.first_frag
= frag_now
;
4370 frag_var (rs_machine_dependent
, 0, 0,
4371 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4372 mips_pic
!= NO_PIC
),
4373 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4375 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4376 mips_relax
.first_fixup
= 0;
4379 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4380 See the comment above RELAX_ENCODE for more details. */
4383 relax_start (symbolS
*symbol
)
4385 gas_assert (mips_relax
.sequence
== 0);
4386 mips_relax
.sequence
= 1;
4387 mips_relax
.symbol
= symbol
;
4390 /* Start generating the second version of a relaxable sequence.
4391 See the comment above RELAX_ENCODE for more details. */
4396 gas_assert (mips_relax
.sequence
== 1);
4397 mips_relax
.sequence
= 2;
4400 /* End the current relaxable sequence. */
4405 gas_assert (mips_relax
.sequence
== 2);
4406 relax_close_frag ();
4407 mips_relax
.sequence
= 0;
4410 /* Return true if IP is a delayed branch or jump. */
4412 static inline bfd_boolean
4413 delayed_branch_p (const struct mips_cl_insn
*ip
)
4415 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4416 | INSN_COND_BRANCH_DELAY
4417 | INSN_COND_BRANCH_LIKELY
)) != 0;
4420 /* Return true if IP is a compact branch or jump. */
4422 static inline bfd_boolean
4423 compact_branch_p (const struct mips_cl_insn
*ip
)
4425 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4426 | INSN2_COND_BRANCH
)) != 0;
4429 /* Return true if IP is an unconditional branch or jump. */
4431 static inline bfd_boolean
4432 uncond_branch_p (const struct mips_cl_insn
*ip
)
4434 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4435 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4438 /* Return true if IP is a branch-likely instruction. */
4440 static inline bfd_boolean
4441 branch_likely_p (const struct mips_cl_insn
*ip
)
4443 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4446 /* Return the type of nop that should be used to fill the delay slot
4447 of delayed branch IP. */
4449 static struct mips_cl_insn
*
4450 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4452 if (mips_opts
.micromips
4453 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4454 return µmips_nop32_insn
;
4458 /* Return a mask that has bit N set if OPCODE reads the register(s)
4462 insn_read_mask (const struct mips_opcode
*opcode
)
4464 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4467 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4471 insn_write_mask (const struct mips_opcode
*opcode
)
4473 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4476 /* Return a mask of the registers specified by operand OPERAND of INSN.
4477 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4481 operand_reg_mask (const struct mips_cl_insn
*insn
,
4482 const struct mips_operand
*operand
,
4483 unsigned int type_mask
)
4485 unsigned int uval
, vsel
;
4487 switch (operand
->type
)
4494 case OP_ADDIUSP_INT
:
4495 case OP_ENTRY_EXIT_LIST
:
4496 case OP_REPEAT_DEST_REG
:
4497 case OP_REPEAT_PREV_REG
:
4500 case OP_VU0_MATCH_SUFFIX
:
4505 case OP_OPTIONAL_REG
:
4507 const struct mips_reg_operand
*reg_op
;
4509 reg_op
= (const struct mips_reg_operand
*) operand
;
4510 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4512 uval
= insn_extract_operand (insn
, operand
);
4513 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4518 const struct mips_reg_pair_operand
*pair_op
;
4520 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4521 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4523 uval
= insn_extract_operand (insn
, operand
);
4524 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4527 case OP_CLO_CLZ_DEST
:
4528 if (!(type_mask
& (1 << OP_REG_GP
)))
4530 uval
= insn_extract_operand (insn
, operand
);
4531 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4534 if (!(type_mask
& (1 << OP_REG_GP
)))
4536 uval
= insn_extract_operand (insn
, operand
);
4537 gas_assert ((uval
& 31) == (uval
>> 5));
4538 return 1 << (uval
& 31);
4541 case OP_NON_ZERO_REG
:
4542 if (!(type_mask
& (1 << OP_REG_GP
)))
4544 uval
= insn_extract_operand (insn
, operand
);
4545 return 1 << (uval
& 31);
4547 case OP_LWM_SWM_LIST
:
4550 case OP_SAVE_RESTORE_LIST
:
4553 case OP_MDMX_IMM_REG
:
4554 if (!(type_mask
& (1 << OP_REG_VEC
)))
4556 uval
= insn_extract_operand (insn
, operand
);
4558 if ((vsel
& 0x18) == 0x18)
4560 return 1 << (uval
& 31);
4563 if (!(type_mask
& (1 << OP_REG_GP
)))
4565 return 1 << insn_extract_operand (insn
, operand
);
4570 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4571 where bit N of OPNO_MASK is set if operand N should be included.
4572 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4576 insn_reg_mask (const struct mips_cl_insn
*insn
,
4577 unsigned int type_mask
, unsigned int opno_mask
)
4579 unsigned int opno
, reg_mask
;
4583 while (opno_mask
!= 0)
4586 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4593 /* Return the mask of core registers that IP reads. */
4596 gpr_read_mask (const struct mips_cl_insn
*ip
)
4598 unsigned long pinfo
, pinfo2
;
4601 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4602 pinfo
= ip
->insn_mo
->pinfo
;
4603 pinfo2
= ip
->insn_mo
->pinfo2
;
4604 if (pinfo
& INSN_UDI
)
4606 /* UDI instructions have traditionally been assumed to read RS
4608 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4609 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4611 if (pinfo
& INSN_READ_GPR_24
)
4613 if (pinfo2
& INSN2_READ_GPR_16
)
4615 if (pinfo2
& INSN2_READ_SP
)
4617 if (pinfo2
& INSN2_READ_GPR_31
)
4619 /* Don't include register 0. */
4623 /* Return the mask of core registers that IP writes. */
4626 gpr_write_mask (const struct mips_cl_insn
*ip
)
4628 unsigned long pinfo
, pinfo2
;
4631 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4632 pinfo
= ip
->insn_mo
->pinfo
;
4633 pinfo2
= ip
->insn_mo
->pinfo2
;
4634 if (pinfo
& INSN_WRITE_GPR_24
)
4636 if (pinfo
& INSN_WRITE_GPR_31
)
4638 if (pinfo
& INSN_UDI
)
4639 /* UDI instructions have traditionally been assumed to write to RD. */
4640 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4641 if (pinfo2
& INSN2_WRITE_SP
)
4643 /* Don't include register 0. */
4647 /* Return the mask of floating-point registers that IP reads. */
4650 fpr_read_mask (const struct mips_cl_insn
*ip
)
4652 unsigned long pinfo
;
4655 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4656 | (1 << OP_REG_MSA
)),
4657 insn_read_mask (ip
->insn_mo
));
4658 pinfo
= ip
->insn_mo
->pinfo
;
4659 /* Conservatively treat all operands to an FP_D instruction are doubles.
4660 (This is overly pessimistic for things like cvt.d.s.) */
4661 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4666 /* Return the mask of floating-point registers that IP writes. */
4669 fpr_write_mask (const struct mips_cl_insn
*ip
)
4671 unsigned long pinfo
;
4674 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4675 | (1 << OP_REG_MSA
)),
4676 insn_write_mask (ip
->insn_mo
));
4677 pinfo
= ip
->insn_mo
->pinfo
;
4678 /* Conservatively treat all operands to an FP_D instruction are doubles.
4679 (This is overly pessimistic for things like cvt.s.d.) */
4680 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4685 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4686 Check whether that is allowed. */
4689 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4691 const char *s
= insn
->name
;
4692 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4694 && mips_opts
.oddspreg
;
4696 if (insn
->pinfo
== INSN_MACRO
)
4697 /* Let a macro pass, we'll catch it later when it is expanded. */
4700 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4701 otherwise it depends on oddspreg. */
4702 if ((insn
->pinfo
& FP_S
)
4703 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4704 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4705 return FPR_SIZE
== 32 || oddspreg
;
4707 /* Allow odd registers for single-precision ops and double-precision if the
4708 floating-point registers are 64-bit wide. */
4709 switch (insn
->pinfo
& (FP_S
| FP_D
))
4715 return FPR_SIZE
== 64;
4720 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4721 s
= strchr (insn
->name
, '.');
4722 if (s
!= NULL
&& opnum
== 2)
4723 s
= strchr (s
+ 1, '.');
4724 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4727 return FPR_SIZE
== 64;
4730 /* Information about an instruction argument that we're trying to match. */
4731 struct mips_arg_info
4733 /* The instruction so far. */
4734 struct mips_cl_insn
*insn
;
4736 /* The first unconsumed operand token. */
4737 struct mips_operand_token
*token
;
4739 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4742 /* The 1-based argument number, for error reporting. This does not
4743 count elided optional registers, etc.. */
4746 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4747 unsigned int last_regno
;
4749 /* If the first operand was an OP_REG, this is the register that it
4750 specified, otherwise it is ILLEGAL_REG. */
4751 unsigned int dest_regno
;
4753 /* The value of the last OP_INT operand. Only used for OP_MSB,
4754 where it gives the lsb position. */
4755 unsigned int last_op_int
;
4757 /* If true, match routines should assume that no later instruction
4758 alternative matches and should therefore be as accommodating as
4759 possible. Match routines should not report errors if something
4760 is only invalid for !LAX_MATCH. */
4761 bfd_boolean lax_match
;
4763 /* True if a reference to the current AT register was seen. */
4764 bfd_boolean seen_at
;
4767 /* Record that the argument is out of range. */
4770 match_out_of_range (struct mips_arg_info
*arg
)
4772 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4775 /* Record that the argument isn't constant but needs to be. */
4778 match_not_constant (struct mips_arg_info
*arg
)
4780 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4784 /* Try to match an OT_CHAR token for character CH. Consume the token
4785 and return true on success, otherwise return false. */
4788 match_char (struct mips_arg_info
*arg
, char ch
)
4790 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4800 /* Try to get an expression from the next tokens in ARG. Consume the
4801 tokens and return true on success, storing the expression value in
4802 VALUE and relocation types in R. */
4805 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4806 bfd_reloc_code_real_type
*r
)
4808 /* If the next token is a '(' that was parsed as being part of a base
4809 expression, assume we have an elided offset. The later match will fail
4810 if this turns out to be wrong. */
4811 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4813 value
->X_op
= O_constant
;
4814 value
->X_add_number
= 0;
4815 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4819 /* Reject register-based expressions such as "0+$2" and "(($2))".
4820 For plain registers the default error seems more appropriate. */
4821 if (arg
->token
->type
== OT_INTEGER
4822 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4824 set_insn_error (arg
->argnum
, _("register value used as expression"));
4828 if (arg
->token
->type
== OT_INTEGER
)
4830 *value
= arg
->token
->u
.integer
.value
;
4831 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4837 (arg
->argnum
, _("operand %d must be an immediate expression"),
4842 /* Try to get a constant expression from the next tokens in ARG. Consume
4843 the tokens and return return true on success, storing the constant value
4847 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4850 bfd_reloc_code_real_type r
[3];
4852 if (!match_expression (arg
, &ex
, r
))
4855 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4856 *value
= ex
.X_add_number
;
4859 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4860 match_out_of_range (arg
);
4862 match_not_constant (arg
);
4868 /* Return the RTYPE_* flags for a register operand of type TYPE that
4869 appears in instruction OPCODE. */
4872 convert_reg_type (const struct mips_opcode
*opcode
,
4873 enum mips_reg_operand_type type
)
4878 return RTYPE_NUM
| RTYPE_GP
;
4881 /* Allow vector register names for MDMX if the instruction is a 64-bit
4882 FPR load, store or move (including moves to and from GPRs). */
4883 if ((mips_opts
.ase
& ASE_MDMX
)
4884 && (opcode
->pinfo
& FP_D
)
4885 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4886 | INSN_COPROC_MEMORY_DELAY
4889 | INSN_STORE_MEMORY
)))
4890 return RTYPE_FPU
| RTYPE_VEC
;
4894 if (opcode
->pinfo
& (FP_D
| FP_S
))
4895 return RTYPE_CCC
| RTYPE_FCC
;
4899 if (opcode
->membership
& INSN_5400
)
4901 return RTYPE_FPU
| RTYPE_VEC
;
4907 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4908 return RTYPE_NUM
| RTYPE_CP0
;
4915 return RTYPE_NUM
| RTYPE_VI
;
4918 return RTYPE_NUM
| RTYPE_VF
;
4920 case OP_REG_R5900_I
:
4921 return RTYPE_R5900_I
;
4923 case OP_REG_R5900_Q
:
4924 return RTYPE_R5900_Q
;
4926 case OP_REG_R5900_R
:
4927 return RTYPE_R5900_R
;
4929 case OP_REG_R5900_ACC
:
4930 return RTYPE_R5900_ACC
;
4935 case OP_REG_MSA_CTRL
:
4941 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4944 check_regno (struct mips_arg_info
*arg
,
4945 enum mips_reg_operand_type type
, unsigned int regno
)
4947 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4948 arg
->seen_at
= TRUE
;
4950 if (type
== OP_REG_FP
4952 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4954 /* This was a warning prior to introducing O32 FPXX and FP64 support
4955 so maintain a warning for FP32 but raise an error for the new
4958 as_warn (_("float register should be even, was %d"), regno
);
4960 as_bad (_("float register should be even, was %d"), regno
);
4963 if (type
== OP_REG_CCC
)
4968 name
= arg
->insn
->insn_mo
->name
;
4969 length
= strlen (name
);
4970 if ((regno
& 1) != 0
4971 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4972 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4973 as_warn (_("condition code register should be even for %s, was %d"),
4976 if ((regno
& 3) != 0
4977 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4978 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4983 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4984 a register of type TYPE. Return true on success, storing the register
4985 number in *REGNO and warning about any dubious uses. */
4988 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4989 unsigned int symval
, unsigned int *regno
)
4991 if (type
== OP_REG_VEC
)
4992 symval
= mips_prefer_vec_regno (symval
);
4993 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4996 *regno
= symval
& RNUM_MASK
;
4997 check_regno (arg
, type
, *regno
);
5001 /* Try to interpret the next token in ARG as a register of type TYPE.
5002 Consume the token and return true on success, storing the register
5003 number in *REGNO. Return false on failure. */
5006 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5007 unsigned int *regno
)
5009 if (arg
->token
->type
== OT_REG
5010 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5018 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5019 Consume the token and return true on success, storing the register numbers
5020 in *REGNO1 and *REGNO2. Return false on failure. */
5023 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5024 unsigned int *regno1
, unsigned int *regno2
)
5026 if (match_reg (arg
, type
, regno1
))
5031 if (arg
->token
->type
== OT_REG_RANGE
5032 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5033 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5034 && *regno1
<= *regno2
)
5042 /* OP_INT matcher. */
5045 match_int_operand (struct mips_arg_info
*arg
,
5046 const struct mips_operand
*operand_base
)
5048 const struct mips_int_operand
*operand
;
5050 int min_val
, max_val
, factor
;
5053 operand
= (const struct mips_int_operand
*) operand_base
;
5054 factor
= 1 << operand
->shift
;
5055 min_val
= mips_int_operand_min (operand
);
5056 max_val
= mips_int_operand_max (operand
);
5058 if (operand_base
->lsb
== 0
5059 && operand_base
->size
== 16
5060 && operand
->shift
== 0
5061 && operand
->bias
== 0
5062 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5064 /* The operand can be relocated. */
5065 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5068 if (offset_expr
.X_op
== O_big
)
5070 match_out_of_range (arg
);
5074 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5075 /* Relocation operators were used. Accept the argument and
5076 leave the relocation value in offset_expr and offset_relocs
5077 for the caller to process. */
5080 if (offset_expr
.X_op
!= O_constant
)
5082 /* Accept non-constant operands if no later alternative matches,
5083 leaving it for the caller to process. */
5084 if (!arg
->lax_match
)
5086 match_not_constant (arg
);
5089 offset_reloc
[0] = BFD_RELOC_LO16
;
5093 /* Clear the global state; we're going to install the operand
5095 sval
= offset_expr
.X_add_number
;
5096 offset_expr
.X_op
= O_absent
;
5098 /* For compatibility with older assemblers, we accept
5099 0x8000-0xffff as signed 16-bit numbers when only
5100 signed numbers are allowed. */
5103 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5104 if (!arg
->lax_match
&& sval
<= max_val
)
5106 match_out_of_range (arg
);
5113 if (!match_const_int (arg
, &sval
))
5117 arg
->last_op_int
= sval
;
5119 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5121 match_out_of_range (arg
);
5125 uval
= (unsigned int) sval
>> operand
->shift
;
5126 uval
-= operand
->bias
;
5128 /* Handle -mfix-cn63xxp1. */
5130 && mips_fix_cn63xxp1
5131 && !mips_opts
.micromips
5132 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5147 /* The rest must be changed to 28. */
5152 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5156 /* OP_MAPPED_INT matcher. */
5159 match_mapped_int_operand (struct mips_arg_info
*arg
,
5160 const struct mips_operand
*operand_base
)
5162 const struct mips_mapped_int_operand
*operand
;
5163 unsigned int uval
, num_vals
;
5166 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5167 if (!match_const_int (arg
, &sval
))
5170 num_vals
= 1 << operand_base
->size
;
5171 for (uval
= 0; uval
< num_vals
; uval
++)
5172 if (operand
->int_map
[uval
] == sval
)
5174 if (uval
== num_vals
)
5176 match_out_of_range (arg
);
5180 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5184 /* OP_MSB matcher. */
5187 match_msb_operand (struct mips_arg_info
*arg
,
5188 const struct mips_operand
*operand_base
)
5190 const struct mips_msb_operand
*operand
;
5191 int min_val
, max_val
, max_high
;
5192 offsetT size
, sval
, high
;
5194 operand
= (const struct mips_msb_operand
*) operand_base
;
5195 min_val
= operand
->bias
;
5196 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5197 max_high
= operand
->opsize
;
5199 if (!match_const_int (arg
, &size
))
5202 high
= size
+ arg
->last_op_int
;
5203 sval
= operand
->add_lsb
? high
: size
;
5205 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5207 match_out_of_range (arg
);
5210 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5214 /* OP_REG matcher. */
5217 match_reg_operand (struct mips_arg_info
*arg
,
5218 const struct mips_operand
*operand_base
)
5220 const struct mips_reg_operand
*operand
;
5221 unsigned int regno
, uval
, num_vals
;
5223 operand
= (const struct mips_reg_operand
*) operand_base
;
5224 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5227 if (operand
->reg_map
)
5229 num_vals
= 1 << operand
->root
.size
;
5230 for (uval
= 0; uval
< num_vals
; uval
++)
5231 if (operand
->reg_map
[uval
] == regno
)
5233 if (num_vals
== uval
)
5239 arg
->last_regno
= regno
;
5240 if (arg
->opnum
== 1)
5241 arg
->dest_regno
= regno
;
5242 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5246 /* OP_REG_PAIR matcher. */
5249 match_reg_pair_operand (struct mips_arg_info
*arg
,
5250 const struct mips_operand
*operand_base
)
5252 const struct mips_reg_pair_operand
*operand
;
5253 unsigned int regno1
, regno2
, uval
, num_vals
;
5255 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5256 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5257 || !match_char (arg
, ',')
5258 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5261 num_vals
= 1 << operand_base
->size
;
5262 for (uval
= 0; uval
< num_vals
; uval
++)
5263 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5265 if (uval
== num_vals
)
5268 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5272 /* OP_PCREL matcher. The caller chooses the relocation type. */
5275 match_pcrel_operand (struct mips_arg_info
*arg
)
5277 bfd_reloc_code_real_type r
[3];
5279 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5282 /* OP_PERF_REG matcher. */
5285 match_perf_reg_operand (struct mips_arg_info
*arg
,
5286 const struct mips_operand
*operand
)
5290 if (!match_const_int (arg
, &sval
))
5295 || (mips_opts
.arch
== CPU_R5900
5296 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5297 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5299 set_insn_error (arg
->argnum
, _("invalid performance register"));
5303 insn_insert_operand (arg
->insn
, operand
, sval
);
5307 /* OP_ADDIUSP matcher. */
5310 match_addiusp_operand (struct mips_arg_info
*arg
,
5311 const struct mips_operand
*operand
)
5316 if (!match_const_int (arg
, &sval
))
5321 match_out_of_range (arg
);
5326 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5328 match_out_of_range (arg
);
5332 uval
= (unsigned int) sval
;
5333 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5334 insn_insert_operand (arg
->insn
, operand
, uval
);
5338 /* OP_CLO_CLZ_DEST matcher. */
5341 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5342 const struct mips_operand
*operand
)
5346 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5349 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5353 /* OP_CHECK_PREV matcher. */
5356 match_check_prev_operand (struct mips_arg_info
*arg
,
5357 const struct mips_operand
*operand_base
)
5359 const struct mips_check_prev_operand
*operand
;
5362 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5364 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5367 if (!operand
->zero_ok
&& regno
== 0)
5370 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5371 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5372 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5374 arg
->last_regno
= regno
;
5375 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5382 /* OP_SAME_RS_RT matcher. */
5385 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5386 const struct mips_operand
*operand
)
5390 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5395 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5399 arg
->last_regno
= regno
;
5401 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5405 /* OP_LWM_SWM_LIST matcher. */
5408 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5409 const struct mips_operand
*operand
)
5411 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5412 struct mips_arg_info reset
;
5415 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5419 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5424 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5427 while (match_char (arg
, ',')
5428 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5431 if (operand
->size
== 2)
5433 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5439 and any permutations of these. */
5440 if ((reglist
& 0xfff1ffff) != 0x80010000)
5443 sregs
= (reglist
>> 17) & 7;
5448 /* The list must include at least one of ra and s0-sN,
5449 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5450 which are $23 and $30 respectively.) E.g.:
5458 and any permutations of these. */
5459 if ((reglist
& 0x3f00ffff) != 0)
5462 ra
= (reglist
>> 27) & 0x10;
5463 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5466 if ((sregs
& -sregs
) != sregs
)
5469 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5473 /* OP_ENTRY_EXIT_LIST matcher. */
5476 match_entry_exit_operand (struct mips_arg_info
*arg
,
5477 const struct mips_operand
*operand
)
5480 bfd_boolean is_exit
;
5482 /* The format is the same for both ENTRY and EXIT, but the constraints
5484 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5485 mask
= (is_exit
? 7 << 3 : 0);
5488 unsigned int regno1
, regno2
;
5489 bfd_boolean is_freg
;
5491 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5493 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5498 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5501 mask
|= (5 + regno2
) << 3;
5503 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5504 mask
|= (regno2
- 3) << 3;
5505 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5506 mask
|= (regno2
- 15) << 1;
5507 else if (regno1
== RA
&& regno2
== RA
)
5512 while (match_char (arg
, ','));
5514 insn_insert_operand (arg
->insn
, operand
, mask
);
5518 /* OP_SAVE_RESTORE_LIST matcher. */
5521 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5523 unsigned int opcode
, args
, statics
, sregs
;
5524 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5527 opcode
= arg
->insn
->insn_opcode
;
5529 num_frame_sizes
= 0;
5535 unsigned int regno1
, regno2
;
5537 if (arg
->token
->type
== OT_INTEGER
)
5539 /* Handle the frame size. */
5540 if (!match_const_int (arg
, &frame_size
))
5542 num_frame_sizes
+= 1;
5546 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5549 while (regno1
<= regno2
)
5551 if (regno1
>= 4 && regno1
<= 7)
5553 if (num_frame_sizes
== 0)
5555 args
|= 1 << (regno1
- 4);
5557 /* statics $a0-$a3 */
5558 statics
|= 1 << (regno1
- 4);
5560 else if (regno1
>= 16 && regno1
<= 23)
5562 sregs
|= 1 << (regno1
- 16);
5563 else if (regno1
== 30)
5566 else if (regno1
== 31)
5567 /* Add $ra to insn. */
5577 while (match_char (arg
, ','));
5579 /* Encode args/statics combination. */
5582 else if (args
== 0xf)
5583 /* All $a0-$a3 are args. */
5584 opcode
|= MIPS16_ALL_ARGS
<< 16;
5585 else if (statics
== 0xf)
5586 /* All $a0-$a3 are statics. */
5587 opcode
|= MIPS16_ALL_STATICS
<< 16;
5590 /* Count arg registers. */
5600 /* Count static registers. */
5602 while (statics
& 0x8)
5604 statics
= (statics
<< 1) & 0xf;
5610 /* Encode args/statics. */
5611 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5614 /* Encode $s0/$s1. */
5615 if (sregs
& (1 << 0)) /* $s0 */
5617 if (sregs
& (1 << 1)) /* $s1 */
5621 /* Encode $s2-$s8. */
5630 opcode
|= num_sregs
<< 24;
5632 /* Encode frame size. */
5633 if (num_frame_sizes
== 0)
5635 set_insn_error (arg
->argnum
, _("missing frame size"));
5638 if (num_frame_sizes
> 1)
5640 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5643 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5645 set_insn_error (arg
->argnum
, _("invalid frame size"));
5648 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5651 opcode
|= (((frame_size
& 0xf0) << 16)
5652 | (frame_size
& 0x0f));
5655 /* Finally build the instruction. */
5656 if ((opcode
>> 16) != 0 || frame_size
== 0)
5657 opcode
|= MIPS16_EXTEND
;
5658 arg
->insn
->insn_opcode
= opcode
;
5662 /* OP_MDMX_IMM_REG matcher. */
5665 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5666 const struct mips_operand
*operand
)
5668 unsigned int regno
, uval
;
5670 const struct mips_opcode
*opcode
;
5672 /* The mips_opcode records whether this is an octobyte or quadhalf
5673 instruction. Start out with that bit in place. */
5674 opcode
= arg
->insn
->insn_mo
;
5675 uval
= mips_extract_operand (operand
, opcode
->match
);
5676 is_qh
= (uval
!= 0);
5678 if (arg
->token
->type
== OT_REG
)
5680 if ((opcode
->membership
& INSN_5400
)
5681 && strcmp (opcode
->name
, "rzu.ob") == 0)
5683 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5688 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5692 /* Check whether this is a vector register or a broadcast of
5693 a single element. */
5694 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5696 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5698 set_insn_error (arg
->argnum
, _("invalid element selector"));
5701 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5706 /* A full vector. */
5707 if ((opcode
->membership
& INSN_5400
)
5708 && (strcmp (opcode
->name
, "sll.ob") == 0
5709 || strcmp (opcode
->name
, "srl.ob") == 0))
5711 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5717 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5719 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5727 if (!match_const_int (arg
, &sval
))
5729 if (sval
< 0 || sval
> 31)
5731 match_out_of_range (arg
);
5734 uval
|= (sval
& 31);
5736 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5738 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5740 insn_insert_operand (arg
->insn
, operand
, uval
);
5744 /* OP_IMM_INDEX matcher. */
5747 match_imm_index_operand (struct mips_arg_info
*arg
,
5748 const struct mips_operand
*operand
)
5750 unsigned int max_val
;
5752 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5755 max_val
= (1 << operand
->size
) - 1;
5756 if (arg
->token
->u
.index
> max_val
)
5758 match_out_of_range (arg
);
5761 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5766 /* OP_REG_INDEX matcher. */
5769 match_reg_index_operand (struct mips_arg_info
*arg
,
5770 const struct mips_operand
*operand
)
5774 if (arg
->token
->type
!= OT_REG_INDEX
)
5777 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5780 insn_insert_operand (arg
->insn
, operand
, regno
);
5785 /* OP_PC matcher. */
5788 match_pc_operand (struct mips_arg_info
*arg
)
5790 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5798 /* OP_NON_ZERO_REG matcher. */
5801 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5802 const struct mips_operand
*operand
)
5806 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5812 arg
->last_regno
= regno
;
5813 insn_insert_operand (arg
->insn
, operand
, regno
);
5817 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5818 register that we need to match. */
5821 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5825 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5828 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5829 the length of the value in bytes (4 for float, 8 for double) and
5830 USING_GPRS says whether the destination is a GPR rather than an FPR.
5832 Return the constant in IMM and OFFSET as follows:
5834 - If the constant should be loaded via memory, set IMM to O_absent and
5835 OFFSET to the memory address.
5837 - Otherwise, if the constant should be loaded into two 32-bit registers,
5838 set IMM to the O_constant to load into the high register and OFFSET
5839 to the corresponding value for the low register.
5841 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5843 These constants only appear as the last operand in an instruction,
5844 and every instruction that accepts them in any variant accepts them
5845 in all variants. This means we don't have to worry about backing out
5846 any changes if the instruction does not match. We just match
5847 unconditionally and report an error if the constant is invalid. */
5850 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5851 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5856 const char *newname
;
5857 unsigned char *data
;
5859 /* Where the constant is placed is based on how the MIPS assembler
5862 length == 4 && using_gprs -- immediate value only
5863 length == 8 && using_gprs -- .rdata or immediate value
5864 length == 4 && !using_gprs -- .lit4 or immediate value
5865 length == 8 && !using_gprs -- .lit8 or immediate value
5867 The .lit4 and .lit8 sections are only used if permitted by the
5869 if (arg
->token
->type
!= OT_FLOAT
)
5871 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5875 gas_assert (arg
->token
->u
.flt
.length
== length
);
5876 data
= arg
->token
->u
.flt
.data
;
5879 /* Handle 32-bit constants for which an immediate value is best. */
5882 || g_switch_value
< 4
5883 || (data
[0] == 0 && data
[1] == 0)
5884 || (data
[2] == 0 && data
[3] == 0)))
5886 imm
->X_op
= O_constant
;
5887 if (!target_big_endian
)
5888 imm
->X_add_number
= bfd_getl32 (data
);
5890 imm
->X_add_number
= bfd_getb32 (data
);
5891 offset
->X_op
= O_absent
;
5895 /* Handle 64-bit constants for which an immediate value is best. */
5897 && !mips_disable_float_construction
5898 /* Constants can only be constructed in GPRs and copied to FPRs if the
5899 GPRs are at least as wide as the FPRs or MTHC1 is available.
5900 Unlike most tests for 32-bit floating-point registers this check
5901 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5902 permit 64-bit moves without MXHC1.
5903 Force the constant into memory otherwise. */
5906 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5908 && ((data
[0] == 0 && data
[1] == 0)
5909 || (data
[2] == 0 && data
[3] == 0))
5910 && ((data
[4] == 0 && data
[5] == 0)
5911 || (data
[6] == 0 && data
[7] == 0)))
5913 /* The value is simple enough to load with a couple of instructions.
5914 If using 32-bit registers, set IMM to the high order 32 bits and
5915 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5917 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5919 imm
->X_op
= O_constant
;
5920 offset
->X_op
= O_constant
;
5921 if (!target_big_endian
)
5923 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5924 offset
->X_add_number
= bfd_getl32 (data
);
5928 imm
->X_add_number
= bfd_getb32 (data
);
5929 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5931 if (offset
->X_add_number
== 0)
5932 offset
->X_op
= O_absent
;
5936 imm
->X_op
= O_constant
;
5937 if (!target_big_endian
)
5938 imm
->X_add_number
= bfd_getl64 (data
);
5940 imm
->X_add_number
= bfd_getb64 (data
);
5941 offset
->X_op
= O_absent
;
5946 /* Switch to the right section. */
5948 subseg
= now_subseg
;
5951 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5956 if (using_gprs
|| g_switch_value
< 8)
5957 newname
= RDATA_SECTION_NAME
;
5962 new_seg
= subseg_new (newname
, (subsegT
) 0);
5963 bfd_set_section_flags (stdoutput
, new_seg
,
5964 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5965 frag_align (length
== 4 ? 2 : 3, 0, 0);
5966 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5967 record_alignment (new_seg
, 4);
5969 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5971 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5973 /* Set the argument to the current address in the section. */
5974 imm
->X_op
= O_absent
;
5975 offset
->X_op
= O_symbol
;
5976 offset
->X_add_symbol
= symbol_temp_new_now ();
5977 offset
->X_add_number
= 0;
5979 /* Put the floating point number into the section. */
5980 p
= frag_more (length
);
5981 memcpy (p
, data
, length
);
5983 /* Switch back to the original section. */
5984 subseg_set (seg
, subseg
);
5988 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5992 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5993 const struct mips_operand
*operand
,
5994 bfd_boolean match_p
)
5998 /* The operand can be an XYZW mask or a single 2-bit channel index
5999 (with X being 0). */
6000 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6002 /* The suffix can be omitted when it is already part of the opcode. */
6003 if (arg
->token
->type
!= OT_CHANNELS
)
6006 uval
= arg
->token
->u
.channels
;
6007 if (operand
->size
== 2)
6009 /* Check that a single bit is set and convert it into a 2-bit index. */
6010 if ((uval
& -uval
) != uval
)
6012 uval
= 4 - ffs (uval
);
6015 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6020 insn_insert_operand (arg
->insn
, operand
, uval
);
6024 /* S is the text seen for ARG. Match it against OPERAND. Return the end
6025 of the argument text if the match is successful, otherwise return null. */
6028 match_operand (struct mips_arg_info
*arg
,
6029 const struct mips_operand
*operand
)
6031 switch (operand
->type
)
6034 return match_int_operand (arg
, operand
);
6037 return match_mapped_int_operand (arg
, operand
);
6040 return match_msb_operand (arg
, operand
);
6043 case OP_OPTIONAL_REG
:
6044 return match_reg_operand (arg
, operand
);
6047 return match_reg_pair_operand (arg
, operand
);
6050 return match_pcrel_operand (arg
);
6053 return match_perf_reg_operand (arg
, operand
);
6055 case OP_ADDIUSP_INT
:
6056 return match_addiusp_operand (arg
, operand
);
6058 case OP_CLO_CLZ_DEST
:
6059 return match_clo_clz_dest_operand (arg
, operand
);
6061 case OP_LWM_SWM_LIST
:
6062 return match_lwm_swm_list_operand (arg
, operand
);
6064 case OP_ENTRY_EXIT_LIST
:
6065 return match_entry_exit_operand (arg
, operand
);
6067 case OP_SAVE_RESTORE_LIST
:
6068 return match_save_restore_list_operand (arg
);
6070 case OP_MDMX_IMM_REG
:
6071 return match_mdmx_imm_reg_operand (arg
, operand
);
6073 case OP_REPEAT_DEST_REG
:
6074 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6076 case OP_REPEAT_PREV_REG
:
6077 return match_tied_reg_operand (arg
, arg
->last_regno
);
6080 return match_pc_operand (arg
);
6083 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6085 case OP_VU0_MATCH_SUFFIX
:
6086 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6089 return match_imm_index_operand (arg
, operand
);
6092 return match_reg_index_operand (arg
, operand
);
6095 return match_same_rs_rt_operand (arg
, operand
);
6098 return match_check_prev_operand (arg
, operand
);
6100 case OP_NON_ZERO_REG
:
6101 return match_non_zero_reg_operand (arg
, operand
);
6106 /* ARG is the state after successfully matching an instruction.
6107 Issue any queued-up warnings. */
6110 check_completed_insn (struct mips_arg_info
*arg
)
6115 as_warn (_("used $at without \".set noat\""));
6117 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6121 /* Return true if modifying general-purpose register REG needs a delay. */
6124 reg_needs_delay (unsigned int reg
)
6126 unsigned long prev_pinfo
;
6128 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6129 if (!mips_opts
.noreorder
6130 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6131 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6132 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6138 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6139 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6140 by VR4120 errata. */
6143 classify_vr4120_insn (const char *name
)
6145 if (strncmp (name
, "macc", 4) == 0)
6146 return FIX_VR4120_MACC
;
6147 if (strncmp (name
, "dmacc", 5) == 0)
6148 return FIX_VR4120_DMACC
;
6149 if (strncmp (name
, "mult", 4) == 0)
6150 return FIX_VR4120_MULT
;
6151 if (strncmp (name
, "dmult", 5) == 0)
6152 return FIX_VR4120_DMULT
;
6153 if (strstr (name
, "div"))
6154 return FIX_VR4120_DIV
;
6155 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6156 return FIX_VR4120_MTHILO
;
6157 return NUM_FIX_VR4120_CLASSES
;
6160 #define INSN_ERET 0x42000018
6161 #define INSN_DERET 0x4200001f
6162 #define INSN_DMULT 0x1c
6163 #define INSN_DMULTU 0x1d
6165 /* Return the number of instructions that must separate INSN1 and INSN2,
6166 where INSN1 is the earlier instruction. Return the worst-case value
6167 for any INSN2 if INSN2 is null. */
6170 insns_between (const struct mips_cl_insn
*insn1
,
6171 const struct mips_cl_insn
*insn2
)
6173 unsigned long pinfo1
, pinfo2
;
6176 /* If INFO2 is null, pessimistically assume that all flags are set for
6177 the second instruction. */
6178 pinfo1
= insn1
->insn_mo
->pinfo
;
6179 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6181 /* For most targets, write-after-read dependencies on the HI and LO
6182 registers must be separated by at least two instructions. */
6183 if (!hilo_interlocks
)
6185 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6187 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6191 /* If we're working around r7000 errata, there must be two instructions
6192 between an mfhi or mflo and any instruction that uses the result. */
6193 if (mips_7000_hilo_fix
6194 && !mips_opts
.micromips
6195 && MF_HILO_INSN (pinfo1
)
6196 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6199 /* If we're working around 24K errata, one instruction is required
6200 if an ERET or DERET is followed by a branch instruction. */
6201 if (mips_fix_24k
&& !mips_opts
.micromips
)
6203 if (insn1
->insn_opcode
== INSN_ERET
6204 || insn1
->insn_opcode
== INSN_DERET
)
6207 || insn2
->insn_opcode
== INSN_ERET
6208 || insn2
->insn_opcode
== INSN_DERET
6209 || delayed_branch_p (insn2
))
6214 /* If we're working around PMC RM7000 errata, there must be three
6215 nops between a dmult and a load instruction. */
6216 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6218 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6219 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6221 if (pinfo2
& INSN_LOAD_MEMORY
)
6226 /* If working around VR4120 errata, check for combinations that need
6227 a single intervening instruction. */
6228 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6230 unsigned int class1
, class2
;
6232 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6233 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6237 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6238 if (vr4120_conflicts
[class1
] & (1 << class2
))
6243 if (!HAVE_CODE_COMPRESSION
)
6245 /* Check for GPR or coprocessor load delays. All such delays
6246 are on the RT register. */
6247 /* Itbl support may require additional care here. */
6248 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6249 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6251 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6255 /* Check for generic coprocessor hazards.
6257 This case is not handled very well. There is no special
6258 knowledge of CP0 handling, and the coprocessors other than
6259 the floating point unit are not distinguished at all. */
6260 /* Itbl support may require additional care here. FIXME!
6261 Need to modify this to include knowledge about
6262 user specified delays! */
6263 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6264 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6266 /* Handle cases where INSN1 writes to a known general coprocessor
6267 register. There must be a one instruction delay before INSN2
6268 if INSN2 reads that register, otherwise no delay is needed. */
6269 mask
= fpr_write_mask (insn1
);
6272 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6277 /* Read-after-write dependencies on the control registers
6278 require a two-instruction gap. */
6279 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6280 && (pinfo2
& INSN_READ_COND_CODE
))
6283 /* We don't know exactly what INSN1 does. If INSN2 is
6284 also a coprocessor instruction, assume there must be
6285 a one instruction gap. */
6286 if (pinfo2
& INSN_COP
)
6291 /* Check for read-after-write dependencies on the coprocessor
6292 control registers in cases where INSN1 does not need a general
6293 coprocessor delay. This means that INSN1 is a floating point
6294 comparison instruction. */
6295 /* Itbl support may require additional care here. */
6296 else if (!cop_interlocks
6297 && (pinfo1
& INSN_WRITE_COND_CODE
)
6298 && (pinfo2
& INSN_READ_COND_CODE
))
6302 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6303 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6305 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6306 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6307 || (insn2
&& delayed_branch_p (insn2
))))
6313 /* Return the number of nops that would be needed to work around the
6314 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6315 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6316 that are contained within the first IGNORE instructions of HIST. */
6319 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6320 const struct mips_cl_insn
*insn
)
6325 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6326 are not affected by the errata. */
6328 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6329 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6330 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6333 /* Search for the first MFLO or MFHI. */
6334 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6335 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6337 /* Extract the destination register. */
6338 mask
= gpr_write_mask (&hist
[i
]);
6340 /* No nops are needed if INSN reads that register. */
6341 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6344 /* ...or if any of the intervening instructions do. */
6345 for (j
= 0; j
< i
; j
++)
6346 if (gpr_read_mask (&hist
[j
]) & mask
)
6350 return MAX_VR4130_NOPS
- i
;
6355 #define BASE_REG_EQ(INSN1, INSN2) \
6356 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6357 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6359 /* Return the minimum alignment for this store instruction. */
6362 fix_24k_align_to (const struct mips_opcode
*mo
)
6364 if (strcmp (mo
->name
, "sh") == 0)
6367 if (strcmp (mo
->name
, "swc1") == 0
6368 || strcmp (mo
->name
, "swc2") == 0
6369 || strcmp (mo
->name
, "sw") == 0
6370 || strcmp (mo
->name
, "sc") == 0
6371 || strcmp (mo
->name
, "s.s") == 0)
6374 if (strcmp (mo
->name
, "sdc1") == 0
6375 || strcmp (mo
->name
, "sdc2") == 0
6376 || strcmp (mo
->name
, "s.d") == 0)
6383 struct fix_24k_store_info
6385 /* Immediate offset, if any, for this store instruction. */
6387 /* Alignment required by this store instruction. */
6389 /* True for register offsets. */
6390 int register_offset
;
6393 /* Comparison function used by qsort. */
6396 fix_24k_sort (const void *a
, const void *b
)
6398 const struct fix_24k_store_info
*pos1
= a
;
6399 const struct fix_24k_store_info
*pos2
= b
;
6401 return (pos1
->off
- pos2
->off
);
6404 /* INSN is a store instruction. Try to record the store information
6405 in STINFO. Return false if the information isn't known. */
6408 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6409 const struct mips_cl_insn
*insn
)
6411 /* The instruction must have a known offset. */
6412 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6415 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6416 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6420 /* Return the number of nops that would be needed to work around the 24k
6421 "lost data on stores during refill" errata if instruction INSN
6422 immediately followed the 2 instructions described by HIST.
6423 Ignore hazards that are contained within the first IGNORE
6424 instructions of HIST.
6426 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6427 for the data cache refills and store data. The following describes
6428 the scenario where the store data could be lost.
6430 * A data cache miss, due to either a load or a store, causing fill
6431 data to be supplied by the memory subsystem
6432 * The first three doublewords of fill data are returned and written
6434 * A sequence of four stores occurs in consecutive cycles around the
6435 final doubleword of the fill:
6439 * Zero, One or more instructions
6442 The four stores A-D must be to different doublewords of the line that
6443 is being filled. The fourth instruction in the sequence above permits
6444 the fill of the final doubleword to be transferred from the FSB into
6445 the cache. In the sequence above, the stores may be either integer
6446 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6447 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6448 different doublewords on the line. If the floating point unit is
6449 running in 1:2 mode, it is not possible to create the sequence above
6450 using only floating point store instructions.
6452 In this case, the cache line being filled is incorrectly marked
6453 invalid, thereby losing the data from any store to the line that
6454 occurs between the original miss and the completion of the five
6455 cycle sequence shown above.
6457 The workarounds are:
6459 * Run the data cache in write-through mode.
6460 * Insert a non-store instruction between
6461 Store A and Store B or Store B and Store C. */
6464 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6465 const struct mips_cl_insn
*insn
)
6467 struct fix_24k_store_info pos
[3];
6468 int align
, i
, base_offset
;
6473 /* If the previous instruction wasn't a store, there's nothing to
6475 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6478 /* If the instructions after the previous one are unknown, we have
6479 to assume the worst. */
6483 /* Check whether we are dealing with three consecutive stores. */
6484 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6485 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6488 /* If we don't know the relationship between the store addresses,
6489 assume the worst. */
6490 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6491 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6494 if (!fix_24k_record_store_info (&pos
[0], insn
)
6495 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6496 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6499 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6501 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6502 X bytes and such that the base register + X is known to be aligned
6505 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6509 align
= pos
[0].align_to
;
6510 base_offset
= pos
[0].off
;
6511 for (i
= 1; i
< 3; i
++)
6512 if (align
< pos
[i
].align_to
)
6514 align
= pos
[i
].align_to
;
6515 base_offset
= pos
[i
].off
;
6517 for (i
= 0; i
< 3; i
++)
6518 pos
[i
].off
-= base_offset
;
6521 pos
[0].off
&= ~align
+ 1;
6522 pos
[1].off
&= ~align
+ 1;
6523 pos
[2].off
&= ~align
+ 1;
6525 /* If any two stores write to the same chunk, they also write to the
6526 same doubleword. The offsets are still sorted at this point. */
6527 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6530 /* A range of at least 9 bytes is needed for the stores to be in
6531 non-overlapping doublewords. */
6532 if (pos
[2].off
- pos
[0].off
<= 8)
6535 if (pos
[2].off
- pos
[1].off
>= 24
6536 || pos
[1].off
- pos
[0].off
>= 24
6537 || pos
[2].off
- pos
[0].off
>= 32)
6543 /* Return the number of nops that would be needed if instruction INSN
6544 immediately followed the MAX_NOPS instructions given by HIST,
6545 where HIST[0] is the most recent instruction. Ignore hazards
6546 between INSN and the first IGNORE instructions in HIST.
6548 If INSN is null, return the worse-case number of nops for any
6552 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6553 const struct mips_cl_insn
*insn
)
6555 int i
, nops
, tmp_nops
;
6558 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6560 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6561 if (tmp_nops
> nops
)
6565 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6567 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6568 if (tmp_nops
> nops
)
6572 if (mips_fix_24k
&& !mips_opts
.micromips
)
6574 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6575 if (tmp_nops
> nops
)
6582 /* The variable arguments provide NUM_INSNS extra instructions that
6583 might be added to HIST. Return the largest number of nops that
6584 would be needed after the extended sequence, ignoring hazards
6585 in the first IGNORE instructions. */
6588 nops_for_sequence (int num_insns
, int ignore
,
6589 const struct mips_cl_insn
*hist
, ...)
6592 struct mips_cl_insn buffer
[MAX_NOPS
];
6593 struct mips_cl_insn
*cursor
;
6596 va_start (args
, hist
);
6597 cursor
= buffer
+ num_insns
;
6598 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6599 while (cursor
> buffer
)
6600 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6602 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6607 /* Like nops_for_insn, but if INSN is a branch, take into account the
6608 worst-case delay for the branch target. */
6611 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6612 const struct mips_cl_insn
*insn
)
6616 nops
= nops_for_insn (ignore
, hist
, insn
);
6617 if (delayed_branch_p (insn
))
6619 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6620 hist
, insn
, get_delay_slot_nop (insn
));
6621 if (tmp_nops
> nops
)
6624 else if (compact_branch_p (insn
))
6626 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6627 if (tmp_nops
> nops
)
6633 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6636 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6638 gas_assert (!HAVE_CODE_COMPRESSION
);
6639 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6640 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6643 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6644 jr target pc &= 'hffff_ffff_cfff_ffff. */
6647 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6649 gas_assert (!HAVE_CODE_COMPRESSION
);
6650 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6651 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6652 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6660 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6661 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6664 ep
.X_op
= O_constant
;
6665 ep
.X_add_number
= 0xcfff0000;
6666 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6667 ep
.X_add_number
= 0xffff;
6668 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6669 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6674 fix_loongson2f (struct mips_cl_insn
* ip
)
6676 if (mips_fix_loongson2f_nop
)
6677 fix_loongson2f_nop (ip
);
6679 if (mips_fix_loongson2f_jump
)
6680 fix_loongson2f_jump (ip
);
6683 /* IP is a branch that has a delay slot, and we need to fill it
6684 automatically. Return true if we can do that by swapping IP
6685 with the previous instruction.
6686 ADDRESS_EXPR is an operand of the instruction to be used with
6690 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6691 bfd_reloc_code_real_type
*reloc_type
)
6693 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6694 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6695 unsigned int fpr_read
, prev_fpr_write
;
6697 /* -O2 and above is required for this optimization. */
6698 if (mips_optimize
< 2)
6701 /* If we have seen .set volatile or .set nomove, don't optimize. */
6702 if (mips_opts
.nomove
)
6705 /* We can't swap if the previous instruction's position is fixed. */
6706 if (history
[0].fixed_p
)
6709 /* If the previous previous insn was in a .set noreorder, we can't
6710 swap. Actually, the MIPS assembler will swap in this situation.
6711 However, gcc configured -with-gnu-as will generate code like
6719 in which we can not swap the bne and INSN. If gcc is not configured
6720 -with-gnu-as, it does not output the .set pseudo-ops. */
6721 if (history
[1].noreorder_p
)
6724 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6725 This means that the previous instruction was a 4-byte one anyhow. */
6726 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6729 /* If the branch is itself the target of a branch, we can not swap.
6730 We cheat on this; all we check for is whether there is a label on
6731 this instruction. If there are any branches to anything other than
6732 a label, users must use .set noreorder. */
6733 if (seg_info (now_seg
)->label_list
)
6736 /* If the previous instruction is in a variant frag other than this
6737 branch's one, we cannot do the swap. This does not apply to
6738 MIPS16 code, which uses variant frags for different purposes. */
6739 if (!mips_opts
.mips16
6741 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6744 /* We do not swap with instructions that cannot architecturally
6745 be placed in a branch delay slot, such as SYNC or ERET. We
6746 also refrain from swapping with a trap instruction, since it
6747 complicates trap handlers to have the trap instruction be in
6749 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6750 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6753 /* Check for conflicts between the branch and the instructions
6754 before the candidate delay slot. */
6755 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6758 /* Check for conflicts between the swapped sequence and the
6759 target of the branch. */
6760 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6763 /* If the branch reads a register that the previous
6764 instruction sets, we can not swap. */
6765 gpr_read
= gpr_read_mask (ip
);
6766 prev_gpr_write
= gpr_write_mask (&history
[0]);
6767 if (gpr_read
& prev_gpr_write
)
6770 fpr_read
= fpr_read_mask (ip
);
6771 prev_fpr_write
= fpr_write_mask (&history
[0]);
6772 if (fpr_read
& prev_fpr_write
)
6775 /* If the branch writes a register that the previous
6776 instruction sets, we can not swap. */
6777 gpr_write
= gpr_write_mask (ip
);
6778 if (gpr_write
& prev_gpr_write
)
6781 /* If the branch writes a register that the previous
6782 instruction reads, we can not swap. */
6783 prev_gpr_read
= gpr_read_mask (&history
[0]);
6784 if (gpr_write
& prev_gpr_read
)
6787 /* If one instruction sets a condition code and the
6788 other one uses a condition code, we can not swap. */
6789 pinfo
= ip
->insn_mo
->pinfo
;
6790 if ((pinfo
& INSN_READ_COND_CODE
)
6791 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6793 if ((pinfo
& INSN_WRITE_COND_CODE
)
6794 && (prev_pinfo
& INSN_READ_COND_CODE
))
6797 /* If the previous instruction uses the PC, we can not swap. */
6798 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6799 if (prev_pinfo2
& INSN2_READ_PC
)
6802 /* If the previous instruction has an incorrect size for a fixed
6803 branch delay slot in microMIPS mode, we cannot swap. */
6804 pinfo2
= ip
->insn_mo
->pinfo2
;
6805 if (mips_opts
.micromips
6806 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6807 && insn_length (history
) != 2)
6809 if (mips_opts
.micromips
6810 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6811 && insn_length (history
) != 4)
6814 /* On R5900 short loops need to be fixed by inserting a nop in
6815 the branch delay slots.
6816 A short loop can be terminated too early. */
6817 if (mips_opts
.arch
== CPU_R5900
6818 /* Check if instruction has a parameter, ignore "j $31". */
6819 && (address_expr
!= NULL
)
6820 /* Parameter must be 16 bit. */
6821 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6822 /* Branch to same segment. */
6823 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6824 /* Branch to same code fragment. */
6825 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6826 /* Can only calculate branch offset if value is known. */
6827 && symbol_constant_p (address_expr
->X_add_symbol
)
6828 /* Check if branch is really conditional. */
6829 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6830 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6831 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6834 /* Check if loop is shorter than 6 instructions including
6835 branch and delay slot. */
6836 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6843 /* When the loop includes branches or jumps,
6844 it is not a short loop. */
6845 for (i
= 0; i
< (distance
/ 4); i
++)
6847 if ((history
[i
].cleared_p
)
6848 || delayed_branch_p (&history
[i
]))
6856 /* Insert nop after branch to fix short loop. */
6865 /* Decide how we should add IP to the instruction stream.
6866 ADDRESS_EXPR is an operand of the instruction to be used with
6869 static enum append_method
6870 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6871 bfd_reloc_code_real_type
*reloc_type
)
6873 /* The relaxed version of a macro sequence must be inherently
6875 if (mips_relax
.sequence
== 2)
6878 /* We must not dabble with instructions in a ".set noreorder" block. */
6879 if (mips_opts
.noreorder
)
6882 /* Otherwise, it's our responsibility to fill branch delay slots. */
6883 if (delayed_branch_p (ip
))
6885 if (!branch_likely_p (ip
)
6886 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6889 if (mips_opts
.mips16
6890 && ISA_SUPPORTS_MIPS16E
6891 && gpr_read_mask (ip
) != 0)
6892 return APPEND_ADD_COMPACT
;
6894 if (mips_opts
.micromips
6895 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
6896 || (!forced_insn_length
6897 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
6898 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
6899 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
6900 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
6901 return APPEND_ADD_COMPACT
;
6903 return APPEND_ADD_WITH_NOP
;
6909 /* IP is an instruction whose opcode we have just changed, END points
6910 to the end of the opcode table processed. Point IP->insn_mo to the
6911 new opcode's definition. */
6914 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
6916 const struct mips_opcode
*mo
;
6918 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6919 if (mo
->pinfo
!= INSN_MACRO
6920 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6928 /* IP is a MIPS16 instruction whose opcode we have just changed.
6929 Point IP->insn_mo to the new opcode's definition. */
6932 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6934 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
6937 /* IP is a microMIPS instruction whose opcode we have just changed.
6938 Point IP->insn_mo to the new opcode's definition. */
6941 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
6943 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
6946 /* For microMIPS macros, we need to generate a local number label
6947 as the target of branches. */
6948 #define MICROMIPS_LABEL_CHAR '\037'
6949 static unsigned long micromips_target_label
;
6950 static char micromips_target_name
[32];
6953 micromips_label_name (void)
6955 char *p
= micromips_target_name
;
6956 char symbol_name_temporary
[24];
6964 l
= micromips_target_label
;
6965 #ifdef LOCAL_LABEL_PREFIX
6966 *p
++ = LOCAL_LABEL_PREFIX
;
6969 *p
++ = MICROMIPS_LABEL_CHAR
;
6972 symbol_name_temporary
[i
++] = l
% 10 + '0';
6977 *p
++ = symbol_name_temporary
[--i
];
6980 return micromips_target_name
;
6984 micromips_label_expr (expressionS
*label_expr
)
6986 label_expr
->X_op
= O_symbol
;
6987 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6988 label_expr
->X_add_number
= 0;
6992 micromips_label_inc (void)
6994 micromips_target_label
++;
6995 *micromips_target_name
= '\0';
6999 micromips_add_label (void)
7003 s
= colon (micromips_label_name ());
7004 micromips_label_inc ();
7005 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7008 /* If assembling microMIPS code, then return the microMIPS reloc
7009 corresponding to the requested one if any. Otherwise return
7010 the reloc unchanged. */
7012 static bfd_reloc_code_real_type
7013 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7015 static const bfd_reloc_code_real_type relocs
[][2] =
7017 /* Keep sorted incrementally by the left-hand key. */
7018 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7019 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7020 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7021 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7022 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7023 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7024 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7025 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7026 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7027 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7028 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7029 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7030 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7031 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7032 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7033 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7034 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7035 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7036 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7037 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7038 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7039 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7040 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7041 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7042 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7043 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7044 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7046 bfd_reloc_code_real_type r
;
7049 if (!mips_opts
.micromips
)
7051 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7057 return relocs
[i
][1];
7062 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7063 Return true on success, storing the resolved value in RESULT. */
7066 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7071 case BFD_RELOC_MIPS_HIGHEST
:
7072 case BFD_RELOC_MICROMIPS_HIGHEST
:
7073 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7076 case BFD_RELOC_MIPS_HIGHER
:
7077 case BFD_RELOC_MICROMIPS_HIGHER
:
7078 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7081 case BFD_RELOC_HI16_S
:
7082 case BFD_RELOC_HI16_S_PCREL
:
7083 case BFD_RELOC_MICROMIPS_HI16_S
:
7084 case BFD_RELOC_MIPS16_HI16_S
:
7085 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7088 case BFD_RELOC_HI16
:
7089 case BFD_RELOC_MICROMIPS_HI16
:
7090 case BFD_RELOC_MIPS16_HI16
:
7091 *result
= (operand
>> 16) & 0xffff;
7094 case BFD_RELOC_LO16
:
7095 case BFD_RELOC_LO16_PCREL
:
7096 case BFD_RELOC_MICROMIPS_LO16
:
7097 case BFD_RELOC_MIPS16_LO16
:
7098 *result
= operand
& 0xffff;
7101 case BFD_RELOC_UNUSED
:
7110 /* Output an instruction. IP is the instruction information.
7111 ADDRESS_EXPR is an operand of the instruction to be used with
7112 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7113 a macro expansion. */
7116 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7117 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7119 unsigned long prev_pinfo2
, pinfo
;
7120 bfd_boolean relaxed_branch
= FALSE
;
7121 enum append_method method
;
7122 bfd_boolean relax32
;
7125 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7126 fix_loongson2f (ip
);
7128 file_ase_mips16
|= mips_opts
.mips16
;
7129 file_ase_micromips
|= mips_opts
.micromips
;
7131 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7132 pinfo
= ip
->insn_mo
->pinfo
;
7134 /* Don't raise alarm about `nods' frags as they'll fill in the right
7135 kind of nop in relaxation if required. */
7136 if (mips_opts
.micromips
7138 && !(history
[0].frag
7139 && history
[0].frag
->fr_type
== rs_machine_dependent
7140 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7141 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7142 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7143 && micromips_insn_length (ip
->insn_mo
) != 2)
7144 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7145 && micromips_insn_length (ip
->insn_mo
) != 4)))
7146 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7147 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7149 if (address_expr
== NULL
)
7151 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7152 && reloc_type
[1] == BFD_RELOC_UNUSED
7153 && reloc_type
[2] == BFD_RELOC_UNUSED
7154 && address_expr
->X_op
== O_constant
)
7156 switch (*reloc_type
)
7158 case BFD_RELOC_MIPS_JMP
:
7162 /* Shift is 2, unusually, for microMIPS JALX. */
7163 shift
= (mips_opts
.micromips
7164 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7165 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7166 as_bad (_("jump to misaligned address (0x%lx)"),
7167 (unsigned long) address_expr
->X_add_number
);
7168 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7174 case BFD_RELOC_MIPS16_JMP
:
7175 if ((address_expr
->X_add_number
& 3) != 0)
7176 as_bad (_("jump to misaligned address (0x%lx)"),
7177 (unsigned long) address_expr
->X_add_number
);
7179 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7180 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7181 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7185 case BFD_RELOC_16_PCREL_S2
:
7189 shift
= mips_opts
.micromips
? 1 : 2;
7190 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7191 as_bad (_("branch to misaligned address (0x%lx)"),
7192 (unsigned long) address_expr
->X_add_number
);
7193 if (!mips_relax_branch
)
7195 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7196 & ~((1 << (shift
+ 16)) - 1))
7197 as_bad (_("branch address range overflow (0x%lx)"),
7198 (unsigned long) address_expr
->X_add_number
);
7199 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7205 case BFD_RELOC_MIPS_21_PCREL_S2
:
7210 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7211 as_bad (_("branch to misaligned address (0x%lx)"),
7212 (unsigned long) address_expr
->X_add_number
);
7213 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7214 & ~((1 << (shift
+ 21)) - 1))
7215 as_bad (_("branch address range overflow (0x%lx)"),
7216 (unsigned long) address_expr
->X_add_number
);
7217 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7222 case BFD_RELOC_MIPS_26_PCREL_S2
:
7227 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7228 as_bad (_("branch to misaligned address (0x%lx)"),
7229 (unsigned long) address_expr
->X_add_number
);
7230 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7231 & ~((1 << (shift
+ 26)) - 1))
7232 as_bad (_("branch address range overflow (0x%lx)"),
7233 (unsigned long) address_expr
->X_add_number
);
7234 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7243 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7246 ip
->insn_opcode
|= value
& 0xffff;
7254 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7256 /* There are a lot of optimizations we could do that we don't.
7257 In particular, we do not, in general, reorder instructions.
7258 If you use gcc with optimization, it will reorder
7259 instructions and generally do much more optimization then we
7260 do here; repeating all that work in the assembler would only
7261 benefit hand written assembly code, and does not seem worth
7263 int nops
= (mips_optimize
== 0
7264 ? nops_for_insn (0, history
, NULL
)
7265 : nops_for_insn_or_target (0, history
, ip
));
7269 unsigned long old_frag_offset
;
7272 old_frag
= frag_now
;
7273 old_frag_offset
= frag_now_fix ();
7275 for (i
= 0; i
< nops
; i
++)
7276 add_fixed_insn (NOP_INSN
);
7277 insert_into_history (0, nops
, NOP_INSN
);
7281 listing_prev_line ();
7282 /* We may be at the start of a variant frag. In case we
7283 are, make sure there is enough space for the frag
7284 after the frags created by listing_prev_line. The
7285 argument to frag_grow here must be at least as large
7286 as the argument to all other calls to frag_grow in
7287 this file. We don't have to worry about being in the
7288 middle of a variant frag, because the variants insert
7289 all needed nop instructions themselves. */
7293 mips_move_text_labels ();
7295 #ifndef NO_ECOFF_DEBUGGING
7296 if (ECOFF_DEBUGGING
)
7297 ecoff_fix_loc (old_frag
, old_frag_offset
);
7301 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7305 /* Work out how many nops in prev_nop_frag are needed by IP,
7306 ignoring hazards generated by the first prev_nop_frag_since
7308 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7309 gas_assert (nops
<= prev_nop_frag_holds
);
7311 /* Enforce NOPS as a minimum. */
7312 if (nops
> prev_nop_frag_required
)
7313 prev_nop_frag_required
= nops
;
7315 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7317 /* Settle for the current number of nops. Update the history
7318 accordingly (for the benefit of any future .set reorder code). */
7319 prev_nop_frag
= NULL
;
7320 insert_into_history (prev_nop_frag_since
,
7321 prev_nop_frag_holds
, NOP_INSN
);
7325 /* Allow this instruction to replace one of the nops that was
7326 tentatively added to prev_nop_frag. */
7327 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7328 prev_nop_frag_holds
--;
7329 prev_nop_frag_since
++;
7333 method
= get_append_method (ip
, address_expr
, reloc_type
);
7334 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7336 dwarf2_emit_insn (0);
7337 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7338 so "move" the instruction address accordingly.
7340 Also, it doesn't seem appropriate for the assembler to reorder .loc
7341 entries. If this instruction is a branch that we are going to swap
7342 with the previous instruction, the two instructions should be
7343 treated as a unit, and the debug information for both instructions
7344 should refer to the start of the branch sequence. Using the
7345 current position is certainly wrong when swapping a 32-bit branch
7346 and a 16-bit delay slot, since the current position would then be
7347 in the middle of a branch. */
7348 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7350 relax32
= (mips_relax_branch
7351 /* Don't try branch relaxation within .set nomacro, or within
7352 .set noat if we use $at for PIC computations. If it turns
7353 out that the branch was out-of-range, we'll get an error. */
7354 && !mips_opts
.warn_about_macros
7355 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7356 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7357 as they have no complementing branches. */
7358 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7360 if (!HAVE_CODE_COMPRESSION
7363 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7364 && delayed_branch_p (ip
))
7366 relaxed_branch
= TRUE
;
7367 add_relaxed_insn (ip
, (relaxed_branch_length
7369 uncond_branch_p (ip
) ? -1
7370 : branch_likely_p (ip
) ? 1
7373 (AT
, mips_pic
!= NO_PIC
,
7374 uncond_branch_p (ip
),
7375 branch_likely_p (ip
),
7376 pinfo
& INSN_WRITE_GPR_31
,
7378 address_expr
->X_add_symbol
,
7379 address_expr
->X_add_number
);
7380 *reloc_type
= BFD_RELOC_UNUSED
;
7382 else if (mips_opts
.micromips
7384 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7385 || *reloc_type
> BFD_RELOC_UNUSED
)
7386 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7387 /* Don't try branch relaxation when users specify
7388 16-bit/32-bit instructions. */
7389 && !forced_insn_length
)
7391 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7392 && *reloc_type
> BFD_RELOC_UNUSED
);
7393 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7394 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7395 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7396 int nods
= method
== APPEND_ADD_WITH_NOP
;
7397 int al
= pinfo
& INSN_WRITE_GPR_31
;
7398 int length32
= nods
? 8 : 4;
7400 gas_assert (address_expr
!= NULL
);
7401 gas_assert (!mips_relax
.sequence
);
7403 relaxed_branch
= TRUE
;
7405 method
= APPEND_ADD
;
7407 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7408 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7409 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7411 uncond
, compact
, al
, nods
,
7413 address_expr
->X_add_symbol
,
7414 address_expr
->X_add_number
);
7415 *reloc_type
= BFD_RELOC_UNUSED
;
7417 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7419 bfd_boolean require_unextended
;
7420 bfd_boolean require_extended
;
7424 if (forced_insn_length
!= 0)
7426 require_unextended
= forced_insn_length
== 2;
7427 require_extended
= forced_insn_length
== 4;
7431 require_unextended
= (mips_opts
.noautoextend
7432 && !mips_opcode_32bit_p (ip
->insn_mo
));
7433 require_extended
= 0;
7436 /* We need to set up a variant frag. */
7437 gas_assert (address_expr
!= NULL
);
7438 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7439 symbol created by `make_expr_symbol' may not get a necessary
7440 external relocation produced. */
7441 if (address_expr
->X_op
== O_symbol
)
7443 symbol
= address_expr
->X_add_symbol
;
7444 offset
= address_expr
->X_add_number
;
7448 symbol
= make_expr_symbol (address_expr
);
7449 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7452 add_relaxed_insn (ip
, 12, 0,
7454 (*reloc_type
- BFD_RELOC_UNUSED
,
7457 mips_opts
.warn_about_macros
,
7458 require_unextended
, require_extended
,
7459 delayed_branch_p (&history
[0]),
7460 history
[0].mips16_absolute_jump_p
),
7463 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7465 if (!delayed_branch_p (ip
))
7466 /* Make sure there is enough room to swap this instruction with
7467 a following jump instruction. */
7469 add_fixed_insn (ip
);
7473 if (mips_opts
.mips16
7474 && mips_opts
.noreorder
7475 && delayed_branch_p (&history
[0]))
7476 as_warn (_("extended instruction in delay slot"));
7478 if (mips_relax
.sequence
)
7480 /* If we've reached the end of this frag, turn it into a variant
7481 frag and record the information for the instructions we've
7483 if (frag_room () < 4)
7484 relax_close_frag ();
7485 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7488 if (mips_relax
.sequence
!= 2)
7490 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7491 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7492 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7493 mips_macro_warning
.insns
[0]++;
7495 if (mips_relax
.sequence
!= 1)
7497 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7498 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7499 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7500 mips_macro_warning
.insns
[1]++;
7503 if (mips_opts
.mips16
)
7506 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7508 add_fixed_insn (ip
);
7511 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7513 bfd_reloc_code_real_type final_type
[3];
7514 reloc_howto_type
*howto0
;
7515 reloc_howto_type
*howto
;
7518 /* Perform any necessary conversion to microMIPS relocations
7519 and find out how many relocations there actually are. */
7520 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7521 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7523 /* In a compound relocation, it is the final (outermost)
7524 operator that determines the relocated field. */
7525 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7530 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7531 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7532 bfd_get_reloc_size (howto
),
7534 howto0
&& howto0
->pc_relative
,
7536 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7537 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7539 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7540 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7541 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7543 /* These relocations can have an addend that won't fit in
7544 4 octets for 64bit assembly. */
7546 && ! howto
->partial_inplace
7547 && (reloc_type
[0] == BFD_RELOC_16
7548 || reloc_type
[0] == BFD_RELOC_32
7549 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7550 || reloc_type
[0] == BFD_RELOC_GPREL16
7551 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7552 || reloc_type
[0] == BFD_RELOC_GPREL32
7553 || reloc_type
[0] == BFD_RELOC_64
7554 || reloc_type
[0] == BFD_RELOC_CTOR
7555 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7556 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7557 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7558 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7559 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7560 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7561 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7562 || hi16_reloc_p (reloc_type
[0])
7563 || lo16_reloc_p (reloc_type
[0])))
7564 ip
->fixp
[0]->fx_no_overflow
= 1;
7566 /* These relocations can have an addend that won't fit in 2 octets. */
7567 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7568 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7569 ip
->fixp
[0]->fx_no_overflow
= 1;
7571 if (mips_relax
.sequence
)
7573 if (mips_relax
.first_fixup
== 0)
7574 mips_relax
.first_fixup
= ip
->fixp
[0];
7576 else if (reloc_needs_lo_p (*reloc_type
))
7578 struct mips_hi_fixup
*hi_fixup
;
7580 /* Reuse the last entry if it already has a matching %lo. */
7581 hi_fixup
= mips_hi_fixup_list
;
7583 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7585 hi_fixup
= XNEW (struct mips_hi_fixup
);
7586 hi_fixup
->next
= mips_hi_fixup_list
;
7587 mips_hi_fixup_list
= hi_fixup
;
7589 hi_fixup
->fixp
= ip
->fixp
[0];
7590 hi_fixup
->seg
= now_seg
;
7593 /* Add fixups for the second and third relocations, if given.
7594 Note that the ABI allows the second relocation to be
7595 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7596 moment we only use RSS_UNDEF, but we could add support
7597 for the others if it ever becomes necessary. */
7598 for (i
= 1; i
< 3; i
++)
7599 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7601 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7602 ip
->fixp
[0]->fx_size
, NULL
, 0,
7603 FALSE
, final_type
[i
]);
7605 /* Use fx_tcbit to mark compound relocs. */
7606 ip
->fixp
[0]->fx_tcbit
= 1;
7607 ip
->fixp
[i
]->fx_tcbit
= 1;
7611 /* Update the register mask information. */
7612 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7613 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7618 insert_into_history (0, 1, ip
);
7621 case APPEND_ADD_WITH_NOP
:
7623 struct mips_cl_insn
*nop
;
7625 insert_into_history (0, 1, ip
);
7626 nop
= get_delay_slot_nop (ip
);
7627 add_fixed_insn (nop
);
7628 insert_into_history (0, 1, nop
);
7629 if (mips_relax
.sequence
)
7630 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7634 case APPEND_ADD_COMPACT
:
7635 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7636 if (mips_opts
.mips16
)
7638 ip
->insn_opcode
|= 0x0080;
7639 find_altered_mips16_opcode (ip
);
7641 /* Convert microMIPS instructions. */
7642 else if (mips_opts
.micromips
)
7645 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7646 ip
->insn_opcode
|= 0x0020;
7648 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7649 ip
->insn_opcode
= 0x40e00000;
7650 /* beqz16->beqzc, bnez16->bnezc */
7651 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7653 unsigned long regno
;
7655 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7656 regno
&= MICROMIPSOP_MASK_MD
;
7657 regno
= micromips_to_32_reg_d_map
[regno
];
7658 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7659 | (regno
<< MICROMIPSOP_SH_RS
)
7660 | 0x40a00000) ^ 0x00400000;
7662 /* beqz->beqzc, bnez->bnezc */
7663 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7664 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7665 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7666 | 0x40a00000) ^ 0x00400000;
7667 /* beq $0->beqzc, bne $0->bnezc */
7668 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7669 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7670 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7671 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7672 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7673 | 0x40a00000) ^ 0x00400000;
7676 find_altered_micromips_opcode (ip
);
7681 insert_into_history (0, 1, ip
);
7686 struct mips_cl_insn delay
= history
[0];
7688 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7690 /* Add the delay slot instruction to the end of the
7691 current frag and shrink the fixed part of the
7692 original frag. If the branch occupies the tail of
7693 the latter, move it backwards to cover the gap. */
7694 delay
.frag
->fr_fix
-= branch_disp
;
7695 if (delay
.frag
== ip
->frag
)
7696 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7697 add_fixed_insn (&delay
);
7701 /* If this is not a relaxed branch and we are in the
7702 same frag, then just swap the instructions. */
7703 move_insn (ip
, delay
.frag
, delay
.where
);
7704 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7708 insert_into_history (0, 1, &delay
);
7713 /* If we have just completed an unconditional branch, clear the history. */
7714 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7715 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7719 mips_no_prev_insn ();
7721 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7722 history
[i
].cleared_p
= 1;
7725 /* We need to emit a label at the end of branch-likely macros. */
7726 if (emit_branch_likely_macro
)
7728 emit_branch_likely_macro
= FALSE
;
7729 micromips_add_label ();
7732 /* We just output an insn, so the next one doesn't have a label. */
7733 mips_clear_insn_labels ();
7736 /* Forget that there was any previous instruction or label.
7737 When BRANCH is true, the branch history is also flushed. */
7740 mips_no_prev_insn (void)
7742 prev_nop_frag
= NULL
;
7743 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7744 mips_clear_insn_labels ();
7747 /* This function must be called before we emit something other than
7748 instructions. It is like mips_no_prev_insn except that it inserts
7749 any NOPS that might be needed by previous instructions. */
7752 mips_emit_delays (void)
7754 if (! mips_opts
.noreorder
)
7756 int nops
= nops_for_insn (0, history
, NULL
);
7760 add_fixed_insn (NOP_INSN
);
7761 mips_move_text_labels ();
7764 mips_no_prev_insn ();
7767 /* Start a (possibly nested) noreorder block. */
7770 start_noreorder (void)
7772 if (mips_opts
.noreorder
== 0)
7777 /* None of the instructions before the .set noreorder can be moved. */
7778 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7779 history
[i
].fixed_p
= 1;
7781 /* Insert any nops that might be needed between the .set noreorder
7782 block and the previous instructions. We will later remove any
7783 nops that turn out not to be needed. */
7784 nops
= nops_for_insn (0, history
, NULL
);
7787 if (mips_optimize
!= 0)
7789 /* Record the frag which holds the nop instructions, so
7790 that we can remove them if we don't need them. */
7791 frag_grow (nops
* NOP_INSN_SIZE
);
7792 prev_nop_frag
= frag_now
;
7793 prev_nop_frag_holds
= nops
;
7794 prev_nop_frag_required
= 0;
7795 prev_nop_frag_since
= 0;
7798 for (; nops
> 0; --nops
)
7799 add_fixed_insn (NOP_INSN
);
7801 /* Move on to a new frag, so that it is safe to simply
7802 decrease the size of prev_nop_frag. */
7803 frag_wane (frag_now
);
7805 mips_move_text_labels ();
7807 mips_mark_labels ();
7808 mips_clear_insn_labels ();
7810 mips_opts
.noreorder
++;
7811 mips_any_noreorder
= 1;
7814 /* End a nested noreorder block. */
7817 end_noreorder (void)
7819 mips_opts
.noreorder
--;
7820 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7822 /* Commit to inserting prev_nop_frag_required nops and go back to
7823 handling nop insertion the .set reorder way. */
7824 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7826 insert_into_history (prev_nop_frag_since
,
7827 prev_nop_frag_required
, NOP_INSN
);
7828 prev_nop_frag
= NULL
;
7832 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7833 higher bits unset. */
7836 normalize_constant_expr (expressionS
*ex
)
7838 if (ex
->X_op
== O_constant
7839 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7840 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7844 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7845 all higher bits unset. */
7848 normalize_address_expr (expressionS
*ex
)
7850 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7851 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7852 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7853 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7857 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7858 Return true if the match was successful.
7860 OPCODE_EXTRA is a value that should be ORed into the opcode
7861 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7862 there are more alternatives after OPCODE and SOFT_MATCH is
7863 as for mips_arg_info. */
7866 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7867 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7868 bfd_boolean lax_match
, bfd_boolean complete_p
)
7871 struct mips_arg_info arg
;
7872 const struct mips_operand
*operand
;
7875 imm_expr
.X_op
= O_absent
;
7876 offset_expr
.X_op
= O_absent
;
7877 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7878 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7879 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7881 create_insn (insn
, opcode
);
7882 /* When no opcode suffix is specified, assume ".xyzw". */
7883 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7884 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7886 insn
->insn_opcode
|= opcode_extra
;
7887 memset (&arg
, 0, sizeof (arg
));
7891 arg
.last_regno
= ILLEGAL_REG
;
7892 arg
.dest_regno
= ILLEGAL_REG
;
7893 arg
.lax_match
= lax_match
;
7894 for (args
= opcode
->args
;; ++args
)
7896 if (arg
.token
->type
== OT_END
)
7898 /* Handle unary instructions in which only one operand is given.
7899 The source is then the same as the destination. */
7900 if (arg
.opnum
== 1 && *args
== ',')
7902 operand
= (mips_opts
.micromips
7903 ? decode_micromips_operand (args
+ 1)
7904 : decode_mips_operand (args
+ 1));
7905 if (operand
&& mips_optional_operand_p (operand
))
7913 /* Treat elided base registers as $0. */
7914 if (strcmp (args
, "(b)") == 0)
7922 /* The register suffix is optional. */
7927 /* Fail the match if there were too few operands. */
7931 /* Successful match. */
7934 clear_insn_error ();
7935 if (arg
.dest_regno
== arg
.last_regno
7936 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7940 (0, _("source and destination must be different"));
7941 else if (arg
.last_regno
== 31)
7943 (0, _("a destination register must be supplied"));
7945 else if (arg
.last_regno
== 31
7946 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7947 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7948 set_insn_error (0, _("the source register must not be $31"));
7949 check_completed_insn (&arg
);
7953 /* Fail the match if the line has too many operands. */
7957 /* Handle characters that need to match exactly. */
7958 if (*args
== '(' || *args
== ')' || *args
== ',')
7960 if (match_char (&arg
, *args
))
7967 if (arg
.token
->type
== OT_DOUBLE_CHAR
7968 && arg
.token
->u
.ch
== *args
)
7976 /* Handle special macro operands. Work out the properties of
7985 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7989 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7998 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8002 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8006 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8012 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8014 imm_expr
.X_op
= O_constant
;
8016 normalize_constant_expr (&imm_expr
);
8020 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8022 /* Assume that the offset has been elided and that what
8023 we saw was a base register. The match will fail later
8024 if that assumption turns out to be wrong. */
8025 offset_expr
.X_op
= O_constant
;
8026 offset_expr
.X_add_number
= 0;
8030 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8032 normalize_address_expr (&offset_expr
);
8037 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8043 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8049 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8055 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8061 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8065 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8069 gas_assert (mips_opts
.micromips
);
8075 if (!forced_insn_length
)
8076 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8078 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8080 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8086 operand
= (mips_opts
.micromips
8087 ? decode_micromips_operand (args
)
8088 : decode_mips_operand (args
));
8092 /* Skip prefixes. */
8093 if (*args
== '+' || *args
== 'm' || *args
== '-')
8096 if (mips_optional_operand_p (operand
)
8098 && (arg
.token
[0].type
!= OT_REG
8099 || arg
.token
[1].type
== OT_END
))
8101 /* Assume that the register has been elided and is the
8102 same as the first operand. */
8107 if (!match_operand (&arg
, operand
))
8112 /* Like match_insn, but for MIPS16. */
8115 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8116 struct mips_operand_token
*tokens
)
8119 const struct mips_operand
*operand
;
8120 const struct mips_operand
*ext_operand
;
8121 bfd_boolean pcrel
= FALSE
;
8122 int required_insn_length
;
8123 struct mips_arg_info arg
;
8126 if (forced_insn_length
)
8127 required_insn_length
= forced_insn_length
;
8128 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8129 required_insn_length
= 2;
8131 required_insn_length
= 0;
8133 create_insn (insn
, opcode
);
8134 imm_expr
.X_op
= O_absent
;
8135 offset_expr
.X_op
= O_absent
;
8136 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8137 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8138 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8141 memset (&arg
, 0, sizeof (arg
));
8145 arg
.last_regno
= ILLEGAL_REG
;
8146 arg
.dest_regno
= ILLEGAL_REG
;
8148 for (args
= opcode
->args
;; ++args
)
8152 if (arg
.token
->type
== OT_END
)
8156 /* Handle unary instructions in which only one operand is given.
8157 The source is then the same as the destination. */
8158 if (arg
.opnum
== 1 && *args
== ',')
8160 operand
= decode_mips16_operand (args
[1], FALSE
);
8161 if (operand
&& mips_optional_operand_p (operand
))
8169 /* Fail the match if there were too few operands. */
8173 /* Successful match. Stuff the immediate value in now, if
8175 clear_insn_error ();
8176 if (opcode
->pinfo
== INSN_MACRO
)
8178 gas_assert (relax_char
== 0 || relax_char
== 'p');
8179 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8182 && offset_expr
.X_op
== O_constant
8184 && calculate_reloc (*offset_reloc
,
8185 offset_expr
.X_add_number
,
8188 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8189 required_insn_length
, &insn
->insn_opcode
);
8190 offset_expr
.X_op
= O_absent
;
8191 *offset_reloc
= BFD_RELOC_UNUSED
;
8193 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8195 if (required_insn_length
== 2)
8196 set_insn_error (0, _("invalid unextended operand value"));
8199 forced_insn_length
= 4;
8200 insn
->insn_opcode
|= MIPS16_EXTEND
;
8203 else if (relax_char
)
8204 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8206 check_completed_insn (&arg
);
8210 /* Fail the match if the line has too many operands. */
8214 /* Handle characters that need to match exactly. */
8215 if (*args
== '(' || *args
== ')' || *args
== ',')
8217 if (match_char (&arg
, *args
))
8235 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8237 imm_expr
.X_op
= O_constant
;
8239 normalize_constant_expr (&imm_expr
);
8244 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8248 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8252 if (operand
->type
== OP_PCREL
)
8256 ext_operand
= decode_mips16_operand (c
, TRUE
);
8257 if (operand
!= ext_operand
)
8259 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8261 offset_expr
.X_op
= O_constant
;
8262 offset_expr
.X_add_number
= 0;
8267 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8270 /* '8' is used for SLTI(U) and has traditionally not
8271 been allowed to take relocation operators. */
8272 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8273 && (ext_operand
->size
!= 16 || c
== '8'))
8275 match_not_constant (&arg
);
8279 if (offset_expr
.X_op
== O_big
)
8281 match_out_of_range (&arg
);
8290 if (mips_optional_operand_p (operand
)
8292 && (arg
.token
[0].type
!= OT_REG
8293 || arg
.token
[1].type
== OT_END
))
8295 /* Assume that the register has been elided and is the
8296 same as the first operand. */
8301 if (!match_operand (&arg
, operand
))
8306 /* Record that the current instruction is invalid for the current ISA. */
8309 match_invalid_for_isa (void)
8312 (0, _("opcode not supported on this processor: %s (%s)"),
8313 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8314 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8317 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8318 Return true if a definite match or failure was found, storing any match
8319 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8320 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8321 tried and failed to match under normal conditions and now want to try a
8322 more relaxed match. */
8325 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8326 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8327 int opcode_extra
, bfd_boolean lax_match
)
8329 const struct mips_opcode
*opcode
;
8330 const struct mips_opcode
*invalid_delay_slot
;
8331 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8333 /* Search for a match, ignoring alternatives that don't satisfy the
8334 current ISA or forced_length. */
8335 invalid_delay_slot
= 0;
8336 seen_valid_for_isa
= FALSE
;
8337 seen_valid_for_size
= FALSE
;
8341 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8342 if (is_opcode_valid (opcode
))
8344 seen_valid_for_isa
= TRUE
;
8345 if (is_size_valid (opcode
))
8347 bfd_boolean delay_slot_ok
;
8349 seen_valid_for_size
= TRUE
;
8350 delay_slot_ok
= is_delay_slot_valid (opcode
);
8351 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8352 lax_match
, delay_slot_ok
))
8356 if (!invalid_delay_slot
)
8357 invalid_delay_slot
= opcode
;
8366 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8368 /* If the only matches we found had the wrong length for the delay slot,
8369 pick the first such match. We'll issue an appropriate warning later. */
8370 if (invalid_delay_slot
)
8372 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8378 /* Handle the case where we didn't try to match an instruction because
8379 all the alternatives were incompatible with the current ISA. */
8380 if (!seen_valid_for_isa
)
8382 match_invalid_for_isa ();
8386 /* Handle the case where we didn't try to match an instruction because
8387 all the alternatives were of the wrong size. */
8388 if (!seen_valid_for_size
)
8390 if (mips_opts
.insn32
)
8391 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8394 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8395 8 * forced_insn_length
);
8402 /* Like match_insns, but for MIPS16. */
8405 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8406 struct mips_operand_token
*tokens
)
8408 const struct mips_opcode
*opcode
;
8409 bfd_boolean seen_valid_for_isa
;
8410 bfd_boolean seen_valid_for_size
;
8412 /* Search for a match, ignoring alternatives that don't satisfy the
8413 current ISA. There are no separate entries for extended forms so
8414 we deal with forced_length later. */
8415 seen_valid_for_isa
= FALSE
;
8416 seen_valid_for_size
= FALSE
;
8420 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8421 if (is_opcode_valid_16 (opcode
))
8423 seen_valid_for_isa
= TRUE
;
8424 if (is_size_valid_16 (opcode
))
8426 seen_valid_for_size
= TRUE
;
8427 if (match_mips16_insn (insn
, opcode
, tokens
))
8433 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8434 && strcmp (opcode
->name
, first
->name
) == 0);
8436 /* Handle the case where we didn't try to match an instruction because
8437 all the alternatives were incompatible with the current ISA. */
8438 if (!seen_valid_for_isa
)
8440 match_invalid_for_isa ();
8444 /* Handle the case where we didn't try to match an instruction because
8445 all the alternatives were of the wrong size. */
8446 if (!seen_valid_for_size
)
8448 if (forced_insn_length
== 2)
8450 (0, _("unrecognized unextended version of MIPS16 opcode"));
8453 (0, _("unrecognized extended version of MIPS16 opcode"));
8460 /* Set up global variables for the start of a new macro. */
8465 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8466 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8467 sizeof (mips_macro_warning
.first_insn_sizes
));
8468 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8469 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8470 && delayed_branch_p (&history
[0]));
8472 && history
[0].frag
->fr_type
== rs_machine_dependent
8473 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8474 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8475 mips_macro_warning
.delay_slot_length
= 0;
8477 switch (history
[0].insn_mo
->pinfo2
8478 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8480 case INSN2_BRANCH_DELAY_32BIT
:
8481 mips_macro_warning
.delay_slot_length
= 4;
8483 case INSN2_BRANCH_DELAY_16BIT
:
8484 mips_macro_warning
.delay_slot_length
= 2;
8487 mips_macro_warning
.delay_slot_length
= 0;
8490 mips_macro_warning
.first_frag
= NULL
;
8493 /* Given that a macro is longer than one instruction or of the wrong size,
8494 return the appropriate warning for it. Return null if no warning is
8495 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8496 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8497 and RELAX_NOMACRO. */
8500 macro_warning (relax_substateT subtype
)
8502 if (subtype
& RELAX_DELAY_SLOT
)
8503 return _("macro instruction expanded into multiple instructions"
8504 " in a branch delay slot");
8505 else if (subtype
& RELAX_NOMACRO
)
8506 return _("macro instruction expanded into multiple instructions");
8507 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8508 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8509 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8510 ? _("macro instruction expanded into a wrong size instruction"
8511 " in a 16-bit branch delay slot")
8512 : _("macro instruction expanded into a wrong size instruction"
8513 " in a 32-bit branch delay slot"));
8518 /* Finish up a macro. Emit warnings as appropriate. */
8523 /* Relaxation warning flags. */
8524 relax_substateT subtype
= 0;
8526 /* Check delay slot size requirements. */
8527 if (mips_macro_warning
.delay_slot_length
== 2)
8528 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8529 if (mips_macro_warning
.delay_slot_length
!= 0)
8531 if (mips_macro_warning
.delay_slot_length
8532 != mips_macro_warning
.first_insn_sizes
[0])
8533 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8534 if (mips_macro_warning
.delay_slot_length
8535 != mips_macro_warning
.first_insn_sizes
[1])
8536 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8539 /* Check instruction count requirements. */
8540 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8542 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8543 subtype
|= RELAX_SECOND_LONGER
;
8544 if (mips_opts
.warn_about_macros
)
8545 subtype
|= RELAX_NOMACRO
;
8546 if (mips_macro_warning
.delay_slot_p
)
8547 subtype
|= RELAX_DELAY_SLOT
;
8550 /* If both alternatives fail to fill a delay slot correctly,
8551 emit the warning now. */
8552 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8553 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8558 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8559 | RELAX_DELAY_SLOT_SIZE_FIRST
8560 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8561 msg
= macro_warning (s
);
8563 as_warn ("%s", msg
);
8567 /* If both implementations are longer than 1 instruction, then emit the
8569 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8574 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8575 msg
= macro_warning (s
);
8577 as_warn ("%s", msg
);
8581 /* If any flags still set, then one implementation might need a warning
8582 and the other either will need one of a different kind or none at all.
8583 Pass any remaining flags over to relaxation. */
8584 if (mips_macro_warning
.first_frag
!= NULL
)
8585 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8588 /* Instruction operand formats used in macros that vary between
8589 standard MIPS and microMIPS code. */
8591 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8592 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8593 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8594 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8595 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8596 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8597 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8598 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8600 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8601 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8602 : cop12_fmt[mips_opts.micromips])
8603 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8604 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8605 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8606 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8607 : mem12_fmt[mips_opts.micromips])
8608 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8609 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8610 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8612 /* Read a macro's relocation codes from *ARGS and store them in *R.
8613 The first argument in *ARGS will be either the code for a single
8614 relocation or -1 followed by the three codes that make up a
8615 composite relocation. */
8618 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8622 next
= va_arg (*args
, int);
8624 r
[0] = (bfd_reloc_code_real_type
) next
;
8627 for (i
= 0; i
< 3; i
++)
8628 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8629 /* This function is only used for 16-bit relocation fields.
8630 To make the macro code simpler, treat an unrelocated value
8631 in the same way as BFD_RELOC_LO16. */
8632 if (r
[0] == BFD_RELOC_UNUSED
)
8633 r
[0] = BFD_RELOC_LO16
;
8637 /* Build an instruction created by a macro expansion. This is passed
8638 a pointer to the count of instructions created so far, an
8639 expression, the name of the instruction to build, an operand format
8640 string, and corresponding arguments. */
8643 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8645 const struct mips_opcode
*mo
= NULL
;
8646 bfd_reloc_code_real_type r
[3];
8647 const struct mips_opcode
*amo
;
8648 const struct mips_operand
*operand
;
8649 struct hash_control
*hash
;
8650 struct mips_cl_insn insn
;
8654 va_start (args
, fmt
);
8656 if (mips_opts
.mips16
)
8658 mips16_macro_build (ep
, name
, fmt
, &args
);
8663 r
[0] = BFD_RELOC_UNUSED
;
8664 r
[1] = BFD_RELOC_UNUSED
;
8665 r
[2] = BFD_RELOC_UNUSED
;
8666 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8667 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8669 gas_assert (strcmp (name
, amo
->name
) == 0);
8673 /* Search until we get a match for NAME. It is assumed here that
8674 macros will never generate MDMX, MIPS-3D, or MT instructions.
8675 We try to match an instruction that fulfills the branch delay
8676 slot instruction length requirement (if any) of the previous
8677 instruction. While doing this we record the first instruction
8678 seen that matches all the other conditions and use it anyway
8679 if the requirement cannot be met; we will issue an appropriate
8680 warning later on. */
8681 if (strcmp (fmt
, amo
->args
) == 0
8682 && amo
->pinfo
!= INSN_MACRO
8683 && is_opcode_valid (amo
)
8684 && is_size_valid (amo
))
8686 if (is_delay_slot_valid (amo
))
8696 gas_assert (amo
->name
);
8698 while (strcmp (name
, amo
->name
) == 0);
8701 create_insn (&insn
, mo
);
8714 macro_read_relocs (&args
, r
);
8715 gas_assert (*r
== BFD_RELOC_GPREL16
8716 || *r
== BFD_RELOC_MIPS_HIGHER
8717 || *r
== BFD_RELOC_HI16_S
8718 || *r
== BFD_RELOC_LO16
8719 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8723 macro_read_relocs (&args
, r
);
8727 macro_read_relocs (&args
, r
);
8728 gas_assert (ep
!= NULL
8729 && (ep
->X_op
== O_constant
8730 || (ep
->X_op
== O_symbol
8731 && (*r
== BFD_RELOC_MIPS_HIGHEST
8732 || *r
== BFD_RELOC_HI16_S
8733 || *r
== BFD_RELOC_HI16
8734 || *r
== BFD_RELOC_GPREL16
8735 || *r
== BFD_RELOC_MIPS_GOT_HI16
8736 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8740 gas_assert (ep
!= NULL
);
8743 * This allows macro() to pass an immediate expression for
8744 * creating short branches without creating a symbol.
8746 * We don't allow branch relaxation for these branches, as
8747 * they should only appear in ".set nomacro" anyway.
8749 if (ep
->X_op
== O_constant
)
8751 /* For microMIPS we always use relocations for branches.
8752 So we should not resolve immediate values. */
8753 gas_assert (!mips_opts
.micromips
);
8755 if ((ep
->X_add_number
& 3) != 0)
8756 as_bad (_("branch to misaligned address (0x%lx)"),
8757 (unsigned long) ep
->X_add_number
);
8758 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8759 as_bad (_("branch address range overflow (0x%lx)"),
8760 (unsigned long) ep
->X_add_number
);
8761 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8765 *r
= BFD_RELOC_16_PCREL_S2
;
8769 gas_assert (ep
!= NULL
);
8770 *r
= BFD_RELOC_MIPS_JMP
;
8774 operand
= (mips_opts
.micromips
8775 ? decode_micromips_operand (fmt
)
8776 : decode_mips_operand (fmt
));
8780 uval
= va_arg (args
, int);
8781 if (operand
->type
== OP_CLO_CLZ_DEST
)
8782 uval
|= (uval
<< 5);
8783 insn_insert_operand (&insn
, operand
, uval
);
8785 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8791 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8793 append_insn (&insn
, ep
, r
, TRUE
);
8797 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8800 struct mips_opcode
*mo
;
8801 struct mips_cl_insn insn
;
8802 const struct mips_operand
*operand
;
8803 bfd_reloc_code_real_type r
[3]
8804 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8806 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8808 gas_assert (strcmp (name
, mo
->name
) == 0);
8810 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8813 gas_assert (mo
->name
);
8814 gas_assert (strcmp (name
, mo
->name
) == 0);
8817 create_insn (&insn
, mo
);
8854 gas_assert (ep
!= NULL
);
8856 if (ep
->X_op
!= O_constant
)
8857 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8858 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8860 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8862 *r
= BFD_RELOC_UNUSED
;
8868 operand
= decode_mips16_operand (c
, FALSE
);
8872 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8877 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8879 append_insn (&insn
, ep
, r
, TRUE
);
8883 * Generate a "jalr" instruction with a relocation hint to the called
8884 * function. This occurs in NewABI PIC code.
8887 macro_build_jalr (expressionS
*ep
, int cprestore
)
8889 static const bfd_reloc_code_real_type jalr_relocs
[2]
8890 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8891 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8895 if (MIPS_JALR_HINT_P (ep
))
8900 if (mips_opts
.micromips
)
8902 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8903 ? "jalr" : "jalrs");
8904 if (MIPS_JALR_HINT_P (ep
)
8906 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8907 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8909 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8912 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8913 if (MIPS_JALR_HINT_P (ep
))
8914 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8918 * Generate a "lui" instruction.
8921 macro_build_lui (expressionS
*ep
, int regnum
)
8923 gas_assert (! mips_opts
.mips16
);
8925 if (ep
->X_op
!= O_constant
)
8927 gas_assert (ep
->X_op
== O_symbol
);
8928 /* _gp_disp is a special case, used from s_cpload.
8929 __gnu_local_gp is used if mips_no_shared. */
8930 gas_assert (mips_pic
== NO_PIC
8932 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8933 || (! mips_in_shared
8934 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8935 "__gnu_local_gp") == 0));
8938 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8941 /* Generate a sequence of instructions to do a load or store from a constant
8942 offset off of a base register (breg) into/from a target register (treg),
8943 using AT if necessary. */
8945 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8946 int treg
, int breg
, int dbl
)
8948 gas_assert (ep
->X_op
== O_constant
);
8950 /* Sign-extending 32-bit constants makes their handling easier. */
8952 normalize_constant_expr (ep
);
8954 /* Right now, this routine can only handle signed 32-bit constants. */
8955 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8956 as_warn (_("operand overflow"));
8958 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8960 /* Signed 16-bit offset will fit in the op. Easy! */
8961 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8965 /* 32-bit offset, need multiple instructions and AT, like:
8966 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8967 addu $tempreg,$tempreg,$breg
8968 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8969 to handle the complete offset. */
8970 macro_build_lui (ep
, AT
);
8971 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8972 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8975 as_bad (_("macro used $at after \".set noat\""));
8980 * Generates code to set the $at register to true (one)
8981 * if reg is less than the immediate expression.
8984 set_at (int reg
, int unsignedp
)
8986 if (imm_expr
.X_add_number
>= -0x8000
8987 && imm_expr
.X_add_number
< 0x8000)
8988 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8989 AT
, reg
, BFD_RELOC_LO16
);
8992 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8993 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8997 /* Count the leading zeroes by performing a binary chop. This is a
8998 bulky bit of source, but performance is a LOT better for the
8999 majority of values than a simple loop to count the bits:
9000 for (lcnt = 0; (lcnt < 32); lcnt++)
9001 if ((v) & (1 << (31 - lcnt)))
9003 However it is not code size friendly, and the gain will drop a bit
9004 on certain cached systems.
9006 #define COUNT_TOP_ZEROES(v) \
9007 (((v) & ~0xffff) == 0 \
9008 ? ((v) & ~0xff) == 0 \
9009 ? ((v) & ~0xf) == 0 \
9010 ? ((v) & ~0x3) == 0 \
9011 ? ((v) & ~0x1) == 0 \
9016 : ((v) & ~0x7) == 0 \
9019 : ((v) & ~0x3f) == 0 \
9020 ? ((v) & ~0x1f) == 0 \
9023 : ((v) & ~0x7f) == 0 \
9026 : ((v) & ~0xfff) == 0 \
9027 ? ((v) & ~0x3ff) == 0 \
9028 ? ((v) & ~0x1ff) == 0 \
9031 : ((v) & ~0x7ff) == 0 \
9034 : ((v) & ~0x3fff) == 0 \
9035 ? ((v) & ~0x1fff) == 0 \
9038 : ((v) & ~0x7fff) == 0 \
9041 : ((v) & ~0xffffff) == 0 \
9042 ? ((v) & ~0xfffff) == 0 \
9043 ? ((v) & ~0x3ffff) == 0 \
9044 ? ((v) & ~0x1ffff) == 0 \
9047 : ((v) & ~0x7ffff) == 0 \
9050 : ((v) & ~0x3fffff) == 0 \
9051 ? ((v) & ~0x1fffff) == 0 \
9054 : ((v) & ~0x7fffff) == 0 \
9057 : ((v) & ~0xfffffff) == 0 \
9058 ? ((v) & ~0x3ffffff) == 0 \
9059 ? ((v) & ~0x1ffffff) == 0 \
9062 : ((v) & ~0x7ffffff) == 0 \
9065 : ((v) & ~0x3fffffff) == 0 \
9066 ? ((v) & ~0x1fffffff) == 0 \
9069 : ((v) & ~0x7fffffff) == 0 \
9074 * This routine generates the least number of instructions necessary to load
9075 * an absolute expression value into a register.
9078 load_register (int reg
, expressionS
*ep
, int dbl
)
9081 expressionS hi32
, lo32
;
9083 if (ep
->X_op
!= O_big
)
9085 gas_assert (ep
->X_op
== O_constant
);
9087 /* Sign-extending 32-bit constants makes their handling easier. */
9089 normalize_constant_expr (ep
);
9091 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9093 /* We can handle 16 bit signed values with an addiu to
9094 $zero. No need to ever use daddiu here, since $zero and
9095 the result are always correct in 32 bit mode. */
9096 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9099 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9101 /* We can handle 16 bit unsigned values with an ori to
9103 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9106 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9108 /* 32 bit values require an lui. */
9109 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9110 if ((ep
->X_add_number
& 0xffff) != 0)
9111 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9116 /* The value is larger than 32 bits. */
9118 if (!dbl
|| GPR_SIZE
== 32)
9122 sprintf_vma (value
, ep
->X_add_number
);
9123 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9124 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9128 if (ep
->X_op
!= O_big
)
9131 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9132 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9133 hi32
.X_add_number
&= 0xffffffff;
9135 lo32
.X_add_number
&= 0xffffffff;
9139 gas_assert (ep
->X_add_number
> 2);
9140 if (ep
->X_add_number
== 3)
9141 generic_bignum
[3] = 0;
9142 else if (ep
->X_add_number
> 4)
9143 as_bad (_("number larger than 64 bits"));
9144 lo32
.X_op
= O_constant
;
9145 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9146 hi32
.X_op
= O_constant
;
9147 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9150 if (hi32
.X_add_number
== 0)
9155 unsigned long hi
, lo
;
9157 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9159 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9161 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9164 if (lo32
.X_add_number
& 0x80000000)
9166 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9167 if (lo32
.X_add_number
& 0xffff)
9168 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9173 /* Check for 16bit shifted constant. We know that hi32 is
9174 non-zero, so start the mask on the first bit of the hi32
9179 unsigned long himask
, lomask
;
9183 himask
= 0xffff >> (32 - shift
);
9184 lomask
= (0xffff << shift
) & 0xffffffff;
9188 himask
= 0xffff << (shift
- 32);
9191 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9192 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9196 tmp
.X_op
= O_constant
;
9198 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9199 | (lo32
.X_add_number
>> shift
));
9201 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9202 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9203 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9204 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9209 while (shift
<= (64 - 16));
9211 /* Find the bit number of the lowest one bit, and store the
9212 shifted value in hi/lo. */
9213 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9214 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9218 while ((lo
& 1) == 0)
9223 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9229 while ((hi
& 1) == 0)
9238 /* Optimize if the shifted value is a (power of 2) - 1. */
9239 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9240 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9242 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9247 /* This instruction will set the register to be all
9249 tmp
.X_op
= O_constant
;
9250 tmp
.X_add_number
= (offsetT
) -1;
9251 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9255 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9256 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9258 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9259 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9264 /* Sign extend hi32 before calling load_register, because we can
9265 generally get better code when we load a sign extended value. */
9266 if ((hi32
.X_add_number
& 0x80000000) != 0)
9267 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9268 load_register (reg
, &hi32
, 0);
9271 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9275 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9283 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9285 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9286 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9292 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9296 mid16
.X_add_number
>>= 16;
9297 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9298 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9301 if ((lo32
.X_add_number
& 0xffff) != 0)
9302 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9306 load_delay_nop (void)
9308 if (!gpr_interlocks
)
9309 macro_build (NULL
, "nop", "");
9312 /* Load an address into a register. */
9315 load_address (int reg
, expressionS
*ep
, int *used_at
)
9317 if (ep
->X_op
!= O_constant
9318 && ep
->X_op
!= O_symbol
)
9320 as_bad (_("expression too complex"));
9321 ep
->X_op
= O_constant
;
9324 if (ep
->X_op
== O_constant
)
9326 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9330 if (mips_pic
== NO_PIC
)
9332 /* If this is a reference to a GP relative symbol, we want
9333 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9335 lui $reg,<sym> (BFD_RELOC_HI16_S)
9336 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9337 If we have an addend, we always use the latter form.
9339 With 64bit address space and a usable $at we want
9340 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9341 lui $at,<sym> (BFD_RELOC_HI16_S)
9342 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9343 daddiu $at,<sym> (BFD_RELOC_LO16)
9347 If $at is already in use, we use a path which is suboptimal
9348 on superscalar processors.
9349 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9350 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9352 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9354 daddiu $reg,<sym> (BFD_RELOC_LO16)
9356 For GP relative symbols in 64bit address space we can use
9357 the same sequence as in 32bit address space. */
9358 if (HAVE_64BIT_SYMBOLS
)
9360 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9361 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9363 relax_start (ep
->X_add_symbol
);
9364 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9365 mips_gp_register
, BFD_RELOC_GPREL16
);
9369 if (*used_at
== 0 && mips_opts
.at
)
9371 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9372 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9373 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9374 BFD_RELOC_MIPS_HIGHER
);
9375 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9376 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9377 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9382 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9383 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9384 BFD_RELOC_MIPS_HIGHER
);
9385 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9386 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9387 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9388 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9391 if (mips_relax
.sequence
)
9396 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9397 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9399 relax_start (ep
->X_add_symbol
);
9400 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9401 mips_gp_register
, BFD_RELOC_GPREL16
);
9404 macro_build_lui (ep
, reg
);
9405 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9406 reg
, reg
, BFD_RELOC_LO16
);
9407 if (mips_relax
.sequence
)
9411 else if (!mips_big_got
)
9415 /* If this is a reference to an external symbol, we want
9416 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9418 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9420 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9421 If there is a constant, it must be added in after.
9423 If we have NewABI, we want
9424 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9425 unless we're referencing a global symbol with a non-zero
9426 offset, in which case cst must be added separately. */
9429 if (ep
->X_add_number
)
9431 ex
.X_add_number
= ep
->X_add_number
;
9432 ep
->X_add_number
= 0;
9433 relax_start (ep
->X_add_symbol
);
9434 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9435 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9436 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9437 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9438 ex
.X_op
= O_constant
;
9439 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9440 reg
, reg
, BFD_RELOC_LO16
);
9441 ep
->X_add_number
= ex
.X_add_number
;
9444 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9445 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9446 if (mips_relax
.sequence
)
9451 ex
.X_add_number
= ep
->X_add_number
;
9452 ep
->X_add_number
= 0;
9453 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9454 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9456 relax_start (ep
->X_add_symbol
);
9458 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9462 if (ex
.X_add_number
!= 0)
9464 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9465 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9466 ex
.X_op
= O_constant
;
9467 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9468 reg
, reg
, BFD_RELOC_LO16
);
9472 else if (mips_big_got
)
9476 /* This is the large GOT case. If this is a reference to an
9477 external symbol, we want
9478 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9480 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9482 Otherwise, for a reference to a local symbol in old ABI, we want
9483 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9485 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9486 If there is a constant, it must be added in after.
9488 In the NewABI, for local symbols, with or without offsets, we want:
9489 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9490 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9494 ex
.X_add_number
= ep
->X_add_number
;
9495 ep
->X_add_number
= 0;
9496 relax_start (ep
->X_add_symbol
);
9497 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9498 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9499 reg
, reg
, mips_gp_register
);
9500 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9501 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9502 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9503 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9504 else if (ex
.X_add_number
)
9506 ex
.X_op
= O_constant
;
9507 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9511 ep
->X_add_number
= ex
.X_add_number
;
9513 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9514 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9515 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9516 BFD_RELOC_MIPS_GOT_OFST
);
9521 ex
.X_add_number
= ep
->X_add_number
;
9522 ep
->X_add_number
= 0;
9523 relax_start (ep
->X_add_symbol
);
9524 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9525 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9526 reg
, reg
, mips_gp_register
);
9527 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9528 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9530 if (reg_needs_delay (mips_gp_register
))
9532 /* We need a nop before loading from $gp. This special
9533 check is required because the lui which starts the main
9534 instruction stream does not refer to $gp, and so will not
9535 insert the nop which may be required. */
9536 macro_build (NULL
, "nop", "");
9538 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9539 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9541 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9545 if (ex
.X_add_number
!= 0)
9547 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9548 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9549 ex
.X_op
= O_constant
;
9550 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9558 if (!mips_opts
.at
&& *used_at
== 1)
9559 as_bad (_("macro used $at after \".set noat\""));
9562 /* Move the contents of register SOURCE into register DEST. */
9565 move_register (int dest
, int source
)
9567 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9568 instruction specifically requires a 32-bit one. */
9569 if (mips_opts
.micromips
9570 && !mips_opts
.insn32
9571 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9572 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9574 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9577 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9578 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9579 The two alternatives are:
9581 Global symbol Local symbol
9582 ------------- ------------
9583 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9585 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9587 load_got_offset emits the first instruction and add_got_offset
9588 emits the second for a 16-bit offset or add_got_offset_hilo emits
9589 a sequence to add a 32-bit offset using a scratch register. */
9592 load_got_offset (int dest
, expressionS
*local
)
9597 global
.X_add_number
= 0;
9599 relax_start (local
->X_add_symbol
);
9600 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9601 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9603 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9604 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9609 add_got_offset (int dest
, expressionS
*local
)
9613 global
.X_op
= O_constant
;
9614 global
.X_op_symbol
= NULL
;
9615 global
.X_add_symbol
= NULL
;
9616 global
.X_add_number
= local
->X_add_number
;
9618 relax_start (local
->X_add_symbol
);
9619 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9620 dest
, dest
, BFD_RELOC_LO16
);
9622 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9627 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9630 int hold_mips_optimize
;
9632 global
.X_op
= O_constant
;
9633 global
.X_op_symbol
= NULL
;
9634 global
.X_add_symbol
= NULL
;
9635 global
.X_add_number
= local
->X_add_number
;
9637 relax_start (local
->X_add_symbol
);
9638 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9640 /* Set mips_optimize around the lui instruction to avoid
9641 inserting an unnecessary nop after the lw. */
9642 hold_mips_optimize
= mips_optimize
;
9644 macro_build_lui (&global
, tmp
);
9645 mips_optimize
= hold_mips_optimize
;
9646 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9649 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9652 /* Emit a sequence of instructions to emulate a branch likely operation.
9653 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9654 is its complementing branch with the original condition negated.
9655 CALL is set if the original branch specified the link operation.
9656 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9658 Code like this is produced in the noreorder mode:
9663 delay slot (executed only if branch taken)
9671 delay slot (executed only if branch taken)
9674 In the reorder mode the delay slot would be filled with a nop anyway,
9675 so code produced is simply:
9680 This function is used when producing code for the microMIPS ASE that
9681 does not implement branch likely instructions in hardware. */
9684 macro_build_branch_likely (const char *br
, const char *brneg
,
9685 int call
, expressionS
*ep
, const char *fmt
,
9686 unsigned int sreg
, unsigned int treg
)
9688 int noreorder
= mips_opts
.noreorder
;
9691 gas_assert (mips_opts
.micromips
);
9695 micromips_label_expr (&expr1
);
9696 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9697 macro_build (NULL
, "nop", "");
9698 macro_build (ep
, call
? "bal" : "b", "p");
9700 /* Set to true so that append_insn adds a label. */
9701 emit_branch_likely_macro
= TRUE
;
9705 macro_build (ep
, br
, fmt
, sreg
, treg
);
9706 macro_build (NULL
, "nop", "");
9711 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9712 the condition code tested. EP specifies the branch target. */
9715 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9742 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9745 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9746 the register tested. EP specifies the branch target. */
9749 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9751 const char *brneg
= NULL
;
9761 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9765 gas_assert (mips_opts
.micromips
);
9766 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9774 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9781 br
= mips_opts
.micromips
? "blez" : "blezl";
9788 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9792 gas_assert (mips_opts
.micromips
);
9793 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9800 if (mips_opts
.micromips
&& brneg
)
9801 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9803 macro_build (ep
, br
, "s,p", sreg
);
9806 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9807 TREG as the registers tested. EP specifies the branch target. */
9810 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9811 unsigned int sreg
, unsigned int treg
)
9813 const char *brneg
= NULL
;
9825 br
= mips_opts
.micromips
? "beq" : "beql";
9834 br
= mips_opts
.micromips
? "bne" : "bnel";
9840 if (mips_opts
.micromips
&& brneg
)
9841 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9843 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9846 /* Return the high part that should be loaded in order to make the low
9847 part of VALUE accessible using an offset of OFFBITS bits. */
9850 offset_high_part (offsetT value
, unsigned int offbits
)
9857 bias
= 1 << (offbits
- 1);
9858 low_mask
= bias
* 2 - 1;
9859 return (value
+ bias
) & ~low_mask
;
9862 /* Return true if the value stored in offset_expr and offset_reloc
9863 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9864 amount that the caller wants to add without inducing overflow
9865 and ALIGN is the known alignment of the value in bytes. */
9868 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9872 /* Accept any relocation operator if overflow isn't a concern. */
9873 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9876 /* These relocations are guaranteed not to overflow in correct links. */
9877 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9878 || gprel16_reloc_p (*offset_reloc
))
9881 if (offset_expr
.X_op
== O_constant
9882 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9883 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9890 * This routine implements the seemingly endless macro or synthesized
9891 * instructions and addressing modes in the mips assembly language. Many
9892 * of these macros are simple and are similar to each other. These could
9893 * probably be handled by some kind of table or grammar approach instead of
9894 * this verbose method. Others are not simple macros but are more like
9895 * optimizing code generation.
9896 * One interesting optimization is when several store macros appear
9897 * consecutively that would load AT with the upper half of the same address.
9898 * The ensuing load upper instructions are omitted. This implies some kind
9899 * of global optimization. We currently only optimize within a single macro.
9900 * For many of the load and store macros if the address is specified as a
9901 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9902 * first load register 'at' with zero and use it as the base register. The
9903 * mips assembler simply uses register $zero. Just one tiny optimization
9907 macro (struct mips_cl_insn
*ip
, char *str
)
9909 const struct mips_operand_array
*operands
;
9910 unsigned int breg
, i
;
9911 unsigned int tempreg
;
9914 expressionS label_expr
;
9929 bfd_boolean large_offset
;
9931 int hold_mips_optimize
;
9933 unsigned int op
[MAX_OPERANDS
];
9935 gas_assert (! mips_opts
.mips16
);
9937 operands
= insn_operands (ip
);
9938 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9939 if (operands
->operand
[i
])
9940 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9944 mask
= ip
->insn_mo
->mask
;
9946 label_expr
.X_op
= O_constant
;
9947 label_expr
.X_op_symbol
= NULL
;
9948 label_expr
.X_add_symbol
= NULL
;
9949 label_expr
.X_add_number
= 0;
9951 expr1
.X_op
= O_constant
;
9952 expr1
.X_op_symbol
= NULL
;
9953 expr1
.X_add_symbol
= NULL
;
9954 expr1
.X_add_number
= 1;
9971 if (mips_opts
.micromips
)
9972 micromips_label_expr (&label_expr
);
9974 label_expr
.X_add_number
= 8;
9975 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9977 macro_build (NULL
, "nop", "");
9979 move_register (op
[0], op
[1]);
9980 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9981 if (mips_opts
.micromips
)
9982 micromips_add_label ();
9999 if (!mips_opts
.micromips
)
10001 if (imm_expr
.X_add_number
>= -0x200
10002 && imm_expr
.X_add_number
< 0x200)
10004 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10005 (int) imm_expr
.X_add_number
);
10014 if (imm_expr
.X_add_number
>= -0x8000
10015 && imm_expr
.X_add_number
< 0x8000)
10017 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10022 load_register (AT
, &imm_expr
, dbl
);
10023 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10042 if (imm_expr
.X_add_number
>= 0
10043 && imm_expr
.X_add_number
< 0x10000)
10045 if (mask
!= M_NOR_I
)
10046 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10049 macro_build (&imm_expr
, "ori", "t,r,i",
10050 op
[0], op
[1], BFD_RELOC_LO16
);
10051 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10057 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10058 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10062 switch (imm_expr
.X_add_number
)
10065 macro_build (NULL
, "nop", "");
10068 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10072 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10073 (int) imm_expr
.X_add_number
);
10076 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10077 (unsigned long) imm_expr
.X_add_number
);
10086 gas_assert (mips_opts
.micromips
);
10087 macro_build_branch_ccl (mask
, &offset_expr
,
10088 EXTRACT_OPERAND (1, BCC
, *ip
));
10095 if (imm_expr
.X_add_number
== 0)
10101 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10103 /* Fall through. */
10106 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10111 /* Fall through. */
10114 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10115 else if (op
[0] == 0)
10116 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10120 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10121 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10122 &offset_expr
, AT
, ZERO
);
10132 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10137 /* Fall through. */
10139 /* Check for > max integer. */
10140 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10143 /* Result is always false. */
10145 macro_build (NULL
, "nop", "");
10147 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10150 ++imm_expr
.X_add_number
;
10154 if (mask
== M_BGEL_I
)
10156 if (imm_expr
.X_add_number
== 0)
10158 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10159 &offset_expr
, op
[0]);
10162 if (imm_expr
.X_add_number
== 1)
10164 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10165 &offset_expr
, op
[0]);
10168 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10171 /* result is always true */
10172 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10173 macro_build (&offset_expr
, "b", "p");
10178 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10179 &offset_expr
, AT
, ZERO
);
10184 /* Fall through. */
10188 else if (op
[0] == 0)
10189 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10190 &offset_expr
, ZERO
, op
[1]);
10194 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10195 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10196 &offset_expr
, AT
, ZERO
);
10202 /* Fall through. */
10206 && imm_expr
.X_add_number
== -1))
10208 ++imm_expr
.X_add_number
;
10212 if (mask
== M_BGEUL_I
)
10214 if (imm_expr
.X_add_number
== 0)
10216 else if (imm_expr
.X_add_number
== 1)
10217 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10218 &offset_expr
, op
[0], ZERO
);
10223 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10224 &offset_expr
, AT
, ZERO
);
10230 /* Fall through. */
10233 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10234 else if (op
[0] == 0)
10235 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10239 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10240 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10241 &offset_expr
, AT
, ZERO
);
10247 /* Fall through. */
10250 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10251 &offset_expr
, op
[0], ZERO
);
10252 else if (op
[0] == 0)
10257 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10258 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10259 &offset_expr
, AT
, ZERO
);
10265 /* Fall through. */
10268 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10269 else if (op
[0] == 0)
10270 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10274 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10275 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10276 &offset_expr
, AT
, ZERO
);
10282 /* Fall through. */
10284 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10286 ++imm_expr
.X_add_number
;
10290 if (mask
== M_BLTL_I
)
10292 if (imm_expr
.X_add_number
== 0)
10293 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10294 else if (imm_expr
.X_add_number
== 1)
10295 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10300 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10301 &offset_expr
, AT
, ZERO
);
10307 /* Fall through. */
10310 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10311 &offset_expr
, op
[0], ZERO
);
10312 else if (op
[0] == 0)
10317 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10318 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10319 &offset_expr
, AT
, ZERO
);
10325 /* Fall through. */
10329 && imm_expr
.X_add_number
== -1))
10331 ++imm_expr
.X_add_number
;
10335 if (mask
== M_BLTUL_I
)
10337 if (imm_expr
.X_add_number
== 0)
10339 else if (imm_expr
.X_add_number
== 1)
10340 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10341 &offset_expr
, op
[0], ZERO
);
10346 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10347 &offset_expr
, AT
, ZERO
);
10353 /* Fall through. */
10356 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10357 else if (op
[0] == 0)
10358 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10362 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10363 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10364 &offset_expr
, AT
, ZERO
);
10370 /* Fall through. */
10374 else if (op
[0] == 0)
10375 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10376 &offset_expr
, ZERO
, op
[1]);
10380 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10381 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10382 &offset_expr
, AT
, ZERO
);
10388 /* Fall through. */
10394 /* Fall through. */
10400 as_warn (_("divide by zero"));
10402 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10404 macro_build (NULL
, "break", BRK_FMT
, 7);
10408 start_noreorder ();
10411 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10412 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10416 if (mips_opts
.micromips
)
10417 micromips_label_expr (&label_expr
);
10419 label_expr
.X_add_number
= 8;
10420 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10421 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10422 macro_build (NULL
, "break", BRK_FMT
, 7);
10423 if (mips_opts
.micromips
)
10424 micromips_add_label ();
10426 expr1
.X_add_number
= -1;
10428 load_register (AT
, &expr1
, dbl
);
10429 if (mips_opts
.micromips
)
10430 micromips_label_expr (&label_expr
);
10432 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10433 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10436 expr1
.X_add_number
= 1;
10437 load_register (AT
, &expr1
, dbl
);
10438 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10442 expr1
.X_add_number
= 0x80000000;
10443 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10447 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10448 /* We want to close the noreorder block as soon as possible, so
10449 that later insns are available for delay slot filling. */
10454 if (mips_opts
.micromips
)
10455 micromips_label_expr (&label_expr
);
10457 label_expr
.X_add_number
= 8;
10458 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10459 macro_build (NULL
, "nop", "");
10461 /* We want to close the noreorder block as soon as possible, so
10462 that later insns are available for delay slot filling. */
10465 macro_build (NULL
, "break", BRK_FMT
, 6);
10467 if (mips_opts
.micromips
)
10468 micromips_add_label ();
10469 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10508 if (imm_expr
.X_add_number
== 0)
10510 as_warn (_("divide by zero"));
10512 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10514 macro_build (NULL
, "break", BRK_FMT
, 7);
10517 if (imm_expr
.X_add_number
== 1)
10519 if (strcmp (s2
, "mflo") == 0)
10520 move_register (op
[0], op
[1]);
10522 move_register (op
[0], ZERO
);
10525 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10527 if (strcmp (s2
, "mflo") == 0)
10528 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10530 move_register (op
[0], ZERO
);
10535 load_register (AT
, &imm_expr
, dbl
);
10536 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10537 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10556 start_noreorder ();
10559 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10560 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10561 /* We want to close the noreorder block as soon as possible, so
10562 that later insns are available for delay slot filling. */
10567 if (mips_opts
.micromips
)
10568 micromips_label_expr (&label_expr
);
10570 label_expr
.X_add_number
= 8;
10571 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10572 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10574 /* We want to close the noreorder block as soon as possible, so
10575 that later insns are available for delay slot filling. */
10577 macro_build (NULL
, "break", BRK_FMT
, 7);
10578 if (mips_opts
.micromips
)
10579 micromips_add_label ();
10581 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10586 /* Fall through. */
10592 /* Fall through. */
10595 /* Load the address of a symbol into a register. If breg is not
10596 zero, we then add a base register to it. */
10599 if (dbl
&& GPR_SIZE
== 32)
10600 as_warn (_("dla used to load 32-bit register; recommend using la "
10603 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10604 as_warn (_("la used to load 64-bit address; recommend using dla "
10607 if (small_offset_p (0, align
, 16))
10609 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10610 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10614 if (mips_opts
.at
&& (op
[0] == breg
))
10622 if (offset_expr
.X_op
!= O_symbol
10623 && offset_expr
.X_op
!= O_constant
)
10625 as_bad (_("expression too complex"));
10626 offset_expr
.X_op
= O_constant
;
10629 if (offset_expr
.X_op
== O_constant
)
10630 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10631 else if (mips_pic
== NO_PIC
)
10633 /* If this is a reference to a GP relative symbol, we want
10634 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10636 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10637 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10638 If we have a constant, we need two instructions anyhow,
10639 so we may as well always use the latter form.
10641 With 64bit address space and a usable $at we want
10642 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10643 lui $at,<sym> (BFD_RELOC_HI16_S)
10644 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10645 daddiu $at,<sym> (BFD_RELOC_LO16)
10647 daddu $tempreg,$tempreg,$at
10649 If $at is already in use, we use a path which is suboptimal
10650 on superscalar processors.
10651 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10652 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10654 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10656 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10658 For GP relative symbols in 64bit address space we can use
10659 the same sequence as in 32bit address space. */
10660 if (HAVE_64BIT_SYMBOLS
)
10662 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10663 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10665 relax_start (offset_expr
.X_add_symbol
);
10666 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10667 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10671 if (used_at
== 0 && mips_opts
.at
)
10673 macro_build (&offset_expr
, "lui", LUI_FMT
,
10674 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10675 macro_build (&offset_expr
, "lui", LUI_FMT
,
10676 AT
, BFD_RELOC_HI16_S
);
10677 macro_build (&offset_expr
, "daddiu", "t,r,j",
10678 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10679 macro_build (&offset_expr
, "daddiu", "t,r,j",
10680 AT
, AT
, BFD_RELOC_LO16
);
10681 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10682 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10687 macro_build (&offset_expr
, "lui", LUI_FMT
,
10688 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10689 macro_build (&offset_expr
, "daddiu", "t,r,j",
10690 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10691 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10692 macro_build (&offset_expr
, "daddiu", "t,r,j",
10693 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10694 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10695 macro_build (&offset_expr
, "daddiu", "t,r,j",
10696 tempreg
, tempreg
, BFD_RELOC_LO16
);
10699 if (mips_relax
.sequence
)
10704 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10705 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10707 relax_start (offset_expr
.X_add_symbol
);
10708 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10709 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10712 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10713 as_bad (_("offset too large"));
10714 macro_build_lui (&offset_expr
, tempreg
);
10715 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10716 tempreg
, tempreg
, BFD_RELOC_LO16
);
10717 if (mips_relax
.sequence
)
10721 else if (!mips_big_got
&& !HAVE_NEWABI
)
10723 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10725 /* If this is a reference to an external symbol, and there
10726 is no constant, we want
10727 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10728 or for lca or if tempreg is PIC_CALL_REG
10729 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10730 For a local symbol, we want
10731 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10733 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10735 If we have a small constant, and this is a reference to
10736 an external symbol, we want
10737 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10739 addiu $tempreg,$tempreg,<constant>
10740 For a local symbol, we want the same instruction
10741 sequence, but we output a BFD_RELOC_LO16 reloc on the
10744 If we have a large constant, and this is a reference to
10745 an external symbol, we want
10746 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10747 lui $at,<hiconstant>
10748 addiu $at,$at,<loconstant>
10749 addu $tempreg,$tempreg,$at
10750 For a local symbol, we want the same instruction
10751 sequence, but we output a BFD_RELOC_LO16 reloc on the
10755 if (offset_expr
.X_add_number
== 0)
10757 if (mips_pic
== SVR4_PIC
10759 && (call
|| tempreg
== PIC_CALL_REG
))
10760 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10762 relax_start (offset_expr
.X_add_symbol
);
10763 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10764 lw_reloc_type
, mips_gp_register
);
10767 /* We're going to put in an addu instruction using
10768 tempreg, so we may as well insert the nop right
10773 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10774 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10776 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10777 tempreg
, tempreg
, BFD_RELOC_LO16
);
10779 /* FIXME: If breg == 0, and the next instruction uses
10780 $tempreg, then if this variant case is used an extra
10781 nop will be generated. */
10783 else if (offset_expr
.X_add_number
>= -0x8000
10784 && offset_expr
.X_add_number
< 0x8000)
10786 load_got_offset (tempreg
, &offset_expr
);
10788 add_got_offset (tempreg
, &offset_expr
);
10792 expr1
.X_add_number
= offset_expr
.X_add_number
;
10793 offset_expr
.X_add_number
=
10794 SEXT_16BIT (offset_expr
.X_add_number
);
10795 load_got_offset (tempreg
, &offset_expr
);
10796 offset_expr
.X_add_number
= expr1
.X_add_number
;
10797 /* If we are going to add in a base register, and the
10798 target register and the base register are the same,
10799 then we are using AT as a temporary register. Since
10800 we want to load the constant into AT, we add our
10801 current AT (from the global offset table) and the
10802 register into the register now, and pretend we were
10803 not using a base register. */
10807 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10812 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10816 else if (!mips_big_got
&& HAVE_NEWABI
)
10818 int add_breg_early
= 0;
10820 /* If this is a reference to an external, and there is no
10821 constant, or local symbol (*), with or without a
10823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10824 or for lca or if tempreg is PIC_CALL_REG
10825 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10827 If we have a small constant, and this is a reference to
10828 an external symbol, we want
10829 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10830 addiu $tempreg,$tempreg,<constant>
10832 If we have a large constant, and this is a reference to
10833 an external symbol, we want
10834 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10835 lui $at,<hiconstant>
10836 addiu $at,$at,<loconstant>
10837 addu $tempreg,$tempreg,$at
10839 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10840 local symbols, even though it introduces an additional
10843 if (offset_expr
.X_add_number
)
10845 expr1
.X_add_number
= offset_expr
.X_add_number
;
10846 offset_expr
.X_add_number
= 0;
10848 relax_start (offset_expr
.X_add_symbol
);
10849 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10850 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10852 if (expr1
.X_add_number
>= -0x8000
10853 && expr1
.X_add_number
< 0x8000)
10855 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10856 tempreg
, tempreg
, BFD_RELOC_LO16
);
10858 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10862 /* If we are going to add in a base register, and the
10863 target register and the base register are the same,
10864 then we are using AT as a temporary register. Since
10865 we want to load the constant into AT, we add our
10866 current AT (from the global offset table) and the
10867 register into the register now, and pretend we were
10868 not using a base register. */
10873 gas_assert (tempreg
== AT
);
10874 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10877 add_breg_early
= 1;
10880 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10881 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10887 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10890 offset_expr
.X_add_number
= expr1
.X_add_number
;
10892 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10893 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10894 if (add_breg_early
)
10896 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10897 op
[0], tempreg
, breg
);
10903 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10905 relax_start (offset_expr
.X_add_symbol
);
10906 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10907 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10909 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10910 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10915 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10916 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10919 else if (mips_big_got
&& !HAVE_NEWABI
)
10922 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10923 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10924 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10926 /* This is the large GOT case. If this is a reference to an
10927 external symbol, and there is no constant, we want
10928 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10929 addu $tempreg,$tempreg,$gp
10930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10931 or for lca or if tempreg is PIC_CALL_REG
10932 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10933 addu $tempreg,$tempreg,$gp
10934 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10935 For a local symbol, we want
10936 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10938 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10940 If we have a small constant, and this is a reference to
10941 an external symbol, we want
10942 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10943 addu $tempreg,$tempreg,$gp
10944 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10946 addiu $tempreg,$tempreg,<constant>
10947 For a local symbol, we want
10948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10950 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10952 If we have a large constant, and this is a reference to
10953 an external symbol, we want
10954 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10955 addu $tempreg,$tempreg,$gp
10956 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10957 lui $at,<hiconstant>
10958 addiu $at,$at,<loconstant>
10959 addu $tempreg,$tempreg,$at
10960 For a local symbol, we want
10961 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10962 lui $at,<hiconstant>
10963 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10964 addu $tempreg,$tempreg,$at
10967 expr1
.X_add_number
= offset_expr
.X_add_number
;
10968 offset_expr
.X_add_number
= 0;
10969 relax_start (offset_expr
.X_add_symbol
);
10970 gpdelay
= reg_needs_delay (mips_gp_register
);
10971 if (expr1
.X_add_number
== 0 && breg
== 0
10972 && (call
|| tempreg
== PIC_CALL_REG
))
10974 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10975 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10977 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10978 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10979 tempreg
, tempreg
, mips_gp_register
);
10980 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10981 tempreg
, lw_reloc_type
, tempreg
);
10982 if (expr1
.X_add_number
== 0)
10986 /* We're going to put in an addu instruction using
10987 tempreg, so we may as well insert the nop right
10992 else if (expr1
.X_add_number
>= -0x8000
10993 && expr1
.X_add_number
< 0x8000)
10996 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10997 tempreg
, tempreg
, BFD_RELOC_LO16
);
11003 /* If we are going to add in a base register, and the
11004 target register and the base register are the same,
11005 then we are using AT as a temporary register. Since
11006 we want to load the constant into AT, we add our
11007 current AT (from the global offset table) and the
11008 register into the register now, and pretend we were
11009 not using a base register. */
11014 gas_assert (tempreg
== AT
);
11016 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11021 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11022 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11026 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11031 /* This is needed because this instruction uses $gp, but
11032 the first instruction on the main stream does not. */
11033 macro_build (NULL
, "nop", "");
11036 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11037 local_reloc_type
, mips_gp_register
);
11038 if (expr1
.X_add_number
>= -0x8000
11039 && expr1
.X_add_number
< 0x8000)
11042 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11043 tempreg
, tempreg
, BFD_RELOC_LO16
);
11044 /* FIXME: If add_number is 0, and there was no base
11045 register, the external symbol case ended with a load,
11046 so if the symbol turns out to not be external, and
11047 the next instruction uses tempreg, an unnecessary nop
11048 will be inserted. */
11054 /* We must add in the base register now, as in the
11055 external symbol case. */
11056 gas_assert (tempreg
== AT
);
11058 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11061 /* We set breg to 0 because we have arranged to add
11062 it in in both cases. */
11066 macro_build_lui (&expr1
, AT
);
11067 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11068 AT
, AT
, BFD_RELOC_LO16
);
11069 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11070 tempreg
, tempreg
, AT
);
11075 else if (mips_big_got
&& HAVE_NEWABI
)
11077 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11078 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11079 int add_breg_early
= 0;
11081 /* This is the large GOT case. If this is a reference to an
11082 external symbol, and there is no constant, we want
11083 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11084 add $tempreg,$tempreg,$gp
11085 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11086 or for lca or if tempreg is PIC_CALL_REG
11087 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11088 add $tempreg,$tempreg,$gp
11089 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11091 If we have a small constant, and this is a reference to
11092 an external symbol, we want
11093 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11094 add $tempreg,$tempreg,$gp
11095 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11096 addi $tempreg,$tempreg,<constant>
11098 If we have a large constant, and this is a reference to
11099 an external symbol, we want
11100 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11101 addu $tempreg,$tempreg,$gp
11102 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11103 lui $at,<hiconstant>
11104 addi $at,$at,<loconstant>
11105 add $tempreg,$tempreg,$at
11107 If we have NewABI, and we know it's a local symbol, we want
11108 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11109 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11110 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11112 relax_start (offset_expr
.X_add_symbol
);
11114 expr1
.X_add_number
= offset_expr
.X_add_number
;
11115 offset_expr
.X_add_number
= 0;
11117 if (expr1
.X_add_number
== 0 && breg
== 0
11118 && (call
|| tempreg
== PIC_CALL_REG
))
11120 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11121 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11123 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11124 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11125 tempreg
, tempreg
, mips_gp_register
);
11126 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11127 tempreg
, lw_reloc_type
, tempreg
);
11129 if (expr1
.X_add_number
== 0)
11131 else if (expr1
.X_add_number
>= -0x8000
11132 && expr1
.X_add_number
< 0x8000)
11134 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11135 tempreg
, tempreg
, BFD_RELOC_LO16
);
11137 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11141 /* If we are going to add in a base register, and the
11142 target register and the base register are the same,
11143 then we are using AT as a temporary register. Since
11144 we want to load the constant into AT, we add our
11145 current AT (from the global offset table) and the
11146 register into the register now, and pretend we were
11147 not using a base register. */
11152 gas_assert (tempreg
== AT
);
11153 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11156 add_breg_early
= 1;
11159 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11160 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11165 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11168 offset_expr
.X_add_number
= expr1
.X_add_number
;
11169 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11170 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11171 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11172 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11173 if (add_breg_early
)
11175 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11176 op
[0], tempreg
, breg
);
11186 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11190 gas_assert (!mips_opts
.micromips
);
11191 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11195 gas_assert (!mips_opts
.micromips
);
11196 macro_build (NULL
, "c2", "C", 0x02);
11200 gas_assert (!mips_opts
.micromips
);
11201 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11205 gas_assert (!mips_opts
.micromips
);
11206 macro_build (NULL
, "c2", "C", 3);
11210 gas_assert (!mips_opts
.micromips
);
11211 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11215 /* The j instruction may not be used in PIC code, since it
11216 requires an absolute address. We convert it to a b
11218 if (mips_pic
== NO_PIC
)
11219 macro_build (&offset_expr
, "j", "a");
11221 macro_build (&offset_expr
, "b", "p");
11224 /* The jal instructions must be handled as macros because when
11225 generating PIC code they expand to multi-instruction
11226 sequences. Normally they are simple instructions. */
11230 /* Fall through. */
11232 gas_assert (mips_opts
.micromips
);
11233 if (mips_opts
.insn32
)
11235 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11243 /* Fall through. */
11246 if (mips_pic
== NO_PIC
)
11248 s
= jals
? "jalrs" : "jalr";
11249 if (mips_opts
.micromips
11250 && !mips_opts
.insn32
11252 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11253 macro_build (NULL
, s
, "mj", op
[1]);
11255 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11259 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11260 && mips_cprestore_offset
>= 0);
11262 if (op
[1] != PIC_CALL_REG
)
11263 as_warn (_("MIPS PIC call to register other than $25"));
11265 s
= ((mips_opts
.micromips
11266 && !mips_opts
.insn32
11267 && (!mips_opts
.noreorder
|| cprestore
))
11268 ? "jalrs" : "jalr");
11269 if (mips_opts
.micromips
11270 && !mips_opts
.insn32
11272 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11273 macro_build (NULL
, s
, "mj", op
[1]);
11275 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11276 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11278 if (mips_cprestore_offset
< 0)
11279 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11282 if (!mips_frame_reg_valid
)
11284 as_warn (_("no .frame pseudo-op used in PIC code"));
11285 /* Quiet this warning. */
11286 mips_frame_reg_valid
= 1;
11288 if (!mips_cprestore_valid
)
11290 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11291 /* Quiet this warning. */
11292 mips_cprestore_valid
= 1;
11294 if (mips_opts
.noreorder
)
11295 macro_build (NULL
, "nop", "");
11296 expr1
.X_add_number
= mips_cprestore_offset
;
11297 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11300 HAVE_64BIT_ADDRESSES
);
11308 gas_assert (mips_opts
.micromips
);
11309 if (mips_opts
.insn32
)
11311 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11315 /* Fall through. */
11317 if (mips_pic
== NO_PIC
)
11318 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11319 else if (mips_pic
== SVR4_PIC
)
11321 /* If this is a reference to an external symbol, and we are
11322 using a small GOT, we want
11323 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11327 lw $gp,cprestore($sp)
11328 The cprestore value is set using the .cprestore
11329 pseudo-op. If we are using a big GOT, we want
11330 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11332 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11336 lw $gp,cprestore($sp)
11337 If the symbol is not external, we want
11338 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11340 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11343 lw $gp,cprestore($sp)
11345 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11346 sequences above, minus nops, unless the symbol is local,
11347 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11353 relax_start (offset_expr
.X_add_symbol
);
11354 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11355 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11358 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11359 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11365 relax_start (offset_expr
.X_add_symbol
);
11366 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11367 BFD_RELOC_MIPS_CALL_HI16
);
11368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11369 PIC_CALL_REG
, mips_gp_register
);
11370 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11371 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11374 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11375 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11377 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11378 PIC_CALL_REG
, PIC_CALL_REG
,
11379 BFD_RELOC_MIPS_GOT_OFST
);
11383 macro_build_jalr (&offset_expr
, 0);
11387 relax_start (offset_expr
.X_add_symbol
);
11390 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11391 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11400 gpdelay
= reg_needs_delay (mips_gp_register
);
11401 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11402 BFD_RELOC_MIPS_CALL_HI16
);
11403 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11404 PIC_CALL_REG
, mips_gp_register
);
11405 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11406 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11411 macro_build (NULL
, "nop", "");
11413 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11414 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11417 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11418 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11420 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11422 if (mips_cprestore_offset
< 0)
11423 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11426 if (!mips_frame_reg_valid
)
11428 as_warn (_("no .frame pseudo-op used in PIC code"));
11429 /* Quiet this warning. */
11430 mips_frame_reg_valid
= 1;
11432 if (!mips_cprestore_valid
)
11434 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11435 /* Quiet this warning. */
11436 mips_cprestore_valid
= 1;
11438 if (mips_opts
.noreorder
)
11439 macro_build (NULL
, "nop", "");
11440 expr1
.X_add_number
= mips_cprestore_offset
;
11441 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11444 HAVE_64BIT_ADDRESSES
);
11448 else if (mips_pic
== VXWORKS_PIC
)
11449 as_bad (_("non-PIC jump used in PIC library"));
11556 gas_assert (!mips_opts
.micromips
);
11559 /* Itbl support may require additional care here. */
11565 /* Itbl support may require additional care here. */
11571 offbits
= (mips_opts
.micromips
? 12
11572 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11574 /* Itbl support may require additional care here. */
11578 gas_assert (!mips_opts
.micromips
);
11581 /* Itbl support may require additional care here. */
11587 offbits
= (mips_opts
.micromips
? 12 : 16);
11592 offbits
= (mips_opts
.micromips
? 12 : 16);
11597 /* Itbl support may require additional care here. */
11603 offbits
= (mips_opts
.micromips
? 12
11604 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11606 /* Itbl support may require additional care here. */
11612 /* Itbl support may require additional care here. */
11618 /* Itbl support may require additional care here. */
11624 offbits
= (mips_opts
.micromips
? 12 : 16);
11629 offbits
= (mips_opts
.micromips
? 12 : 16);
11634 offbits
= (mips_opts
.micromips
? 12
11635 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11641 offbits
= (mips_opts
.micromips
? 12
11642 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11648 offbits
= (mips_opts
.micromips
? 12 : 16);
11651 gas_assert (mips_opts
.micromips
);
11658 gas_assert (mips_opts
.micromips
);
11665 gas_assert (mips_opts
.micromips
);
11671 gas_assert (mips_opts
.micromips
);
11678 /* We don't want to use $0 as tempreg. */
11679 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11682 tempreg
= op
[0] + lp
;
11698 gas_assert (!mips_opts
.micromips
);
11701 /* Itbl support may require additional care here. */
11707 /* Itbl support may require additional care here. */
11713 offbits
= (mips_opts
.micromips
? 12
11714 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11716 /* Itbl support may require additional care here. */
11720 gas_assert (!mips_opts
.micromips
);
11723 /* Itbl support may require additional care here. */
11729 offbits
= (mips_opts
.micromips
? 12 : 16);
11734 offbits
= (mips_opts
.micromips
? 12 : 16);
11739 offbits
= (mips_opts
.micromips
? 12
11740 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11746 offbits
= (mips_opts
.micromips
? 12
11747 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11752 fmt
= (mips_opts
.micromips
? "k,~(b)"
11753 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11755 offbits
= (mips_opts
.micromips
? 12
11756 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11766 fmt
= (mips_opts
.micromips
? "k,~(b)"
11767 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11769 offbits
= (mips_opts
.micromips
? 12
11770 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11782 /* Itbl support may require additional care here. */
11787 offbits
= (mips_opts
.micromips
? 12
11788 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11790 /* Itbl support may require additional care here. */
11796 /* Itbl support may require additional care here. */
11800 gas_assert (!mips_opts
.micromips
);
11803 /* Itbl support may require additional care here. */
11809 offbits
= (mips_opts
.micromips
? 12 : 16);
11814 offbits
= (mips_opts
.micromips
? 12 : 16);
11817 gas_assert (mips_opts
.micromips
);
11823 gas_assert (mips_opts
.micromips
);
11829 gas_assert (mips_opts
.micromips
);
11835 gas_assert (mips_opts
.micromips
);
11844 if (small_offset_p (0, align
, 16))
11846 /* The first case exists for M_LD_AB and M_SD_AB, which are
11847 macros for o32 but which should act like normal instructions
11850 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11851 offset_reloc
[1], offset_reloc
[2], breg
);
11852 else if (small_offset_p (0, align
, offbits
))
11855 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11857 macro_build (NULL
, s
, fmt
, op
[0],
11858 (int) offset_expr
.X_add_number
, breg
);
11864 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11865 tempreg
, breg
, -1, offset_reloc
[0],
11866 offset_reloc
[1], offset_reloc
[2]);
11868 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11870 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11878 if (offset_expr
.X_op
!= O_constant
11879 && offset_expr
.X_op
!= O_symbol
)
11881 as_bad (_("expression too complex"));
11882 offset_expr
.X_op
= O_constant
;
11885 if (HAVE_32BIT_ADDRESSES
11886 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11890 sprintf_vma (value
, offset_expr
.X_add_number
);
11891 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11894 /* A constant expression in PIC code can be handled just as it
11895 is in non PIC code. */
11896 if (offset_expr
.X_op
== O_constant
)
11898 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11899 offbits
== 0 ? 16 : offbits
);
11900 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11902 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11904 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11905 tempreg
, tempreg
, breg
);
11908 if (offset_expr
.X_add_number
!= 0)
11909 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11910 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11911 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11913 else if (offbits
== 16)
11914 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11916 macro_build (NULL
, s
, fmt
, op
[0],
11917 (int) offset_expr
.X_add_number
, tempreg
);
11919 else if (offbits
!= 16)
11921 /* The offset field is too narrow to be used for a low-part
11922 relocation, so load the whole address into the auxiliary
11924 load_address (tempreg
, &offset_expr
, &used_at
);
11926 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11927 tempreg
, tempreg
, breg
);
11929 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11931 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11933 else if (mips_pic
== NO_PIC
)
11935 /* If this is a reference to a GP relative symbol, and there
11936 is no base register, we want
11937 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11938 Otherwise, if there is no base register, we want
11939 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11940 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11941 If we have a constant, we need two instructions anyhow,
11942 so we always use the latter form.
11944 If we have a base register, and this is a reference to a
11945 GP relative symbol, we want
11946 addu $tempreg,$breg,$gp
11947 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11949 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11950 addu $tempreg,$tempreg,$breg
11951 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11952 With a constant we always use the latter case.
11954 With 64bit address space and no base register and $at usable,
11956 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11957 lui $at,<sym> (BFD_RELOC_HI16_S)
11958 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11961 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11962 If we have a base register, we want
11963 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11964 lui $at,<sym> (BFD_RELOC_HI16_S)
11965 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11969 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11971 Without $at we can't generate the optimal path for superscalar
11972 processors here since this would require two temporary registers.
11973 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11974 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11976 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11978 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11979 If we have a base register, we want
11980 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11981 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11983 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11985 daddu $tempreg,$tempreg,$breg
11986 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11988 For GP relative symbols in 64bit address space we can use
11989 the same sequence as in 32bit address space. */
11990 if (HAVE_64BIT_SYMBOLS
)
11992 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11993 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11995 relax_start (offset_expr
.X_add_symbol
);
11998 macro_build (&offset_expr
, s
, fmt
, op
[0],
11999 BFD_RELOC_GPREL16
, mips_gp_register
);
12003 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12004 tempreg
, breg
, mips_gp_register
);
12005 macro_build (&offset_expr
, s
, fmt
, op
[0],
12006 BFD_RELOC_GPREL16
, tempreg
);
12011 if (used_at
== 0 && mips_opts
.at
)
12013 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12014 BFD_RELOC_MIPS_HIGHEST
);
12015 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12017 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12018 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12020 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12021 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12022 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12023 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12029 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12030 BFD_RELOC_MIPS_HIGHEST
);
12031 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12032 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12033 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12034 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12035 tempreg
, BFD_RELOC_HI16_S
);
12036 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12038 macro_build (NULL
, "daddu", "d,v,t",
12039 tempreg
, tempreg
, breg
);
12040 macro_build (&offset_expr
, s
, fmt
, op
[0],
12041 BFD_RELOC_LO16
, tempreg
);
12044 if (mips_relax
.sequence
)
12051 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12052 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12054 relax_start (offset_expr
.X_add_symbol
);
12055 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12059 macro_build_lui (&offset_expr
, tempreg
);
12060 macro_build (&offset_expr
, s
, fmt
, op
[0],
12061 BFD_RELOC_LO16
, tempreg
);
12062 if (mips_relax
.sequence
)
12067 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12068 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12070 relax_start (offset_expr
.X_add_symbol
);
12071 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12072 tempreg
, breg
, mips_gp_register
);
12073 macro_build (&offset_expr
, s
, fmt
, op
[0],
12074 BFD_RELOC_GPREL16
, tempreg
);
12077 macro_build_lui (&offset_expr
, tempreg
);
12078 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12079 tempreg
, tempreg
, breg
);
12080 macro_build (&offset_expr
, s
, fmt
, op
[0],
12081 BFD_RELOC_LO16
, tempreg
);
12082 if (mips_relax
.sequence
)
12086 else if (!mips_big_got
)
12088 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12090 /* If this is a reference to an external symbol, we want
12091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12093 <op> op[0],0($tempreg)
12095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12097 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12098 <op> op[0],0($tempreg)
12100 For NewABI, we want
12101 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12102 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12104 If there is a base register, we add it to $tempreg before
12105 the <op>. If there is a constant, we stick it in the
12106 <op> instruction. We don't handle constants larger than
12107 16 bits, because we have no way to load the upper 16 bits
12108 (actually, we could handle them for the subset of cases
12109 in which we are not using $at). */
12110 gas_assert (offset_expr
.X_op
== O_symbol
);
12113 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12114 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12116 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12117 tempreg
, tempreg
, breg
);
12118 macro_build (&offset_expr
, s
, fmt
, op
[0],
12119 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12122 expr1
.X_add_number
= offset_expr
.X_add_number
;
12123 offset_expr
.X_add_number
= 0;
12124 if (expr1
.X_add_number
< -0x8000
12125 || expr1
.X_add_number
>= 0x8000)
12126 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12127 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12128 lw_reloc_type
, mips_gp_register
);
12130 relax_start (offset_expr
.X_add_symbol
);
12132 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12133 tempreg
, BFD_RELOC_LO16
);
12136 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12137 tempreg
, tempreg
, breg
);
12138 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12140 else if (mips_big_got
&& !HAVE_NEWABI
)
12144 /* If this is a reference to an external symbol, we want
12145 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12146 addu $tempreg,$tempreg,$gp
12147 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12148 <op> op[0],0($tempreg)
12150 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12152 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12153 <op> op[0],0($tempreg)
12154 If there is a base register, we add it to $tempreg before
12155 the <op>. If there is a constant, we stick it in the
12156 <op> instruction. We don't handle constants larger than
12157 16 bits, because we have no way to load the upper 16 bits
12158 (actually, we could handle them for the subset of cases
12159 in which we are not using $at). */
12160 gas_assert (offset_expr
.X_op
== O_symbol
);
12161 expr1
.X_add_number
= offset_expr
.X_add_number
;
12162 offset_expr
.X_add_number
= 0;
12163 if (expr1
.X_add_number
< -0x8000
12164 || expr1
.X_add_number
>= 0x8000)
12165 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12166 gpdelay
= reg_needs_delay (mips_gp_register
);
12167 relax_start (offset_expr
.X_add_symbol
);
12168 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12169 BFD_RELOC_MIPS_GOT_HI16
);
12170 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12172 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12173 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12176 macro_build (NULL
, "nop", "");
12177 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12178 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12180 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12181 tempreg
, BFD_RELOC_LO16
);
12185 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12186 tempreg
, tempreg
, breg
);
12187 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12189 else if (mips_big_got
&& HAVE_NEWABI
)
12191 /* If this is a reference to an external symbol, we want
12192 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12193 add $tempreg,$tempreg,$gp
12194 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12195 <op> op[0],<ofst>($tempreg)
12196 Otherwise, for local symbols, we want:
12197 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12198 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12199 gas_assert (offset_expr
.X_op
== O_symbol
);
12200 expr1
.X_add_number
= offset_expr
.X_add_number
;
12201 offset_expr
.X_add_number
= 0;
12202 if (expr1
.X_add_number
< -0x8000
12203 || expr1
.X_add_number
>= 0x8000)
12204 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12205 relax_start (offset_expr
.X_add_symbol
);
12206 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12207 BFD_RELOC_MIPS_GOT_HI16
);
12208 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12210 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12211 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12213 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12214 tempreg
, tempreg
, breg
);
12215 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12218 offset_expr
.X_add_number
= expr1
.X_add_number
;
12219 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12220 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12222 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12223 tempreg
, tempreg
, breg
);
12224 macro_build (&offset_expr
, s
, fmt
, op
[0],
12225 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12234 gas_assert (mips_opts
.micromips
);
12235 gas_assert (mips_opts
.insn32
);
12236 start_noreorder ();
12237 macro_build (NULL
, "jr", "s", RA
);
12238 expr1
.X_add_number
= op
[0] << 2;
12239 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12244 gas_assert (mips_opts
.micromips
);
12245 gas_assert (mips_opts
.insn32
);
12246 macro_build (NULL
, "jr", "s", op
[0]);
12247 if (mips_opts
.noreorder
)
12248 macro_build (NULL
, "nop", "");
12253 load_register (op
[0], &imm_expr
, 0);
12257 load_register (op
[0], &imm_expr
, 1);
12261 if (imm_expr
.X_op
== O_constant
)
12264 load_register (AT
, &imm_expr
, 0);
12265 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12270 gas_assert (imm_expr
.X_op
== O_absent
12271 && offset_expr
.X_op
== O_symbol
12272 && strcmp (segment_name (S_GET_SEGMENT
12273 (offset_expr
.X_add_symbol
)),
12275 && offset_expr
.X_add_number
== 0);
12276 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12277 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12282 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12283 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12284 order 32 bits of the value and the low order 32 bits are either
12285 zero or in OFFSET_EXPR. */
12286 if (imm_expr
.X_op
== O_constant
)
12288 if (GPR_SIZE
== 64)
12289 load_register (op
[0], &imm_expr
, 1);
12294 if (target_big_endian
)
12306 load_register (hreg
, &imm_expr
, 0);
12309 if (offset_expr
.X_op
== O_absent
)
12310 move_register (lreg
, 0);
12313 gas_assert (offset_expr
.X_op
== O_constant
);
12314 load_register (lreg
, &offset_expr
, 0);
12320 gas_assert (imm_expr
.X_op
== O_absent
);
12322 /* We know that sym is in the .rdata section. First we get the
12323 upper 16 bits of the address. */
12324 if (mips_pic
== NO_PIC
)
12326 macro_build_lui (&offset_expr
, AT
);
12331 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12332 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12336 /* Now we load the register(s). */
12337 if (GPR_SIZE
== 64)
12340 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12341 BFD_RELOC_LO16
, AT
);
12346 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12347 BFD_RELOC_LO16
, AT
);
12350 /* FIXME: How in the world do we deal with the possible
12352 offset_expr
.X_add_number
+= 4;
12353 macro_build (&offset_expr
, "lw", "t,o(b)",
12354 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12360 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12361 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12362 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12363 the value and the low order 32 bits are either zero or in
12365 if (imm_expr
.X_op
== O_constant
)
12368 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12369 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12370 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12373 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12374 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12375 else if (FPR_SIZE
!= 32)
12376 as_bad (_("Unable to generate `%s' compliant code "
12378 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12380 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12381 if (offset_expr
.X_op
== O_absent
)
12382 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12385 gas_assert (offset_expr
.X_op
== O_constant
);
12386 load_register (AT
, &offset_expr
, 0);
12387 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12393 gas_assert (imm_expr
.X_op
== O_absent
12394 && offset_expr
.X_op
== O_symbol
12395 && offset_expr
.X_add_number
== 0);
12396 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12397 if (strcmp (s
, ".lit8") == 0)
12399 op
[2] = mips_gp_register
;
12400 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12401 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12402 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12406 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12408 if (mips_pic
!= NO_PIC
)
12409 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12410 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12413 /* FIXME: This won't work for a 64 bit address. */
12414 macro_build_lui (&offset_expr
, AT
);
12418 offset_reloc
[0] = BFD_RELOC_LO16
;
12419 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12420 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12427 * The MIPS assembler seems to check for X_add_number not
12428 * being double aligned and generating:
12429 * lui at,%hi(foo+1)
12431 * addiu at,at,%lo(foo+1)
12434 * But, the resulting address is the same after relocation so why
12435 * generate the extra instruction?
12437 /* Itbl support may require additional care here. */
12440 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12449 gas_assert (!mips_opts
.micromips
);
12450 /* Itbl support may require additional care here. */
12453 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12473 if (GPR_SIZE
== 64)
12483 if (GPR_SIZE
== 64)
12491 /* Even on a big endian machine $fn comes before $fn+1. We have
12492 to adjust when loading from memory. We set coproc if we must
12493 load $fn+1 first. */
12494 /* Itbl support may require additional care here. */
12495 if (!target_big_endian
)
12499 if (small_offset_p (0, align
, 16))
12502 if (!small_offset_p (4, align
, 16))
12504 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12505 -1, offset_reloc
[0], offset_reloc
[1],
12507 expr1
.X_add_number
= 0;
12511 offset_reloc
[0] = BFD_RELOC_LO16
;
12512 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12513 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12515 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12517 ep
->X_add_number
+= 4;
12518 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12519 offset_reloc
[1], offset_reloc
[2], breg
);
12520 ep
->X_add_number
-= 4;
12521 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12522 offset_reloc
[1], offset_reloc
[2], breg
);
12526 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12527 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12529 ep
->X_add_number
+= 4;
12530 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12531 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12537 if (offset_expr
.X_op
!= O_symbol
12538 && offset_expr
.X_op
!= O_constant
)
12540 as_bad (_("expression too complex"));
12541 offset_expr
.X_op
= O_constant
;
12544 if (HAVE_32BIT_ADDRESSES
12545 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12549 sprintf_vma (value
, offset_expr
.X_add_number
);
12550 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12553 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12555 /* If this is a reference to a GP relative symbol, we want
12556 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12557 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12558 If we have a base register, we use this
12560 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12561 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12562 If this is not a GP relative symbol, we want
12563 lui $at,<sym> (BFD_RELOC_HI16_S)
12564 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12565 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12566 If there is a base register, we add it to $at after the
12567 lui instruction. If there is a constant, we always use
12569 if (offset_expr
.X_op
== O_symbol
12570 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12571 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12573 relax_start (offset_expr
.X_add_symbol
);
12576 tempreg
= mips_gp_register
;
12580 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12581 AT
, breg
, mips_gp_register
);
12586 /* Itbl support may require additional care here. */
12587 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12588 BFD_RELOC_GPREL16
, tempreg
);
12589 offset_expr
.X_add_number
+= 4;
12591 /* Set mips_optimize to 2 to avoid inserting an
12593 hold_mips_optimize
= mips_optimize
;
12595 /* Itbl support may require additional care here. */
12596 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12597 BFD_RELOC_GPREL16
, tempreg
);
12598 mips_optimize
= hold_mips_optimize
;
12602 offset_expr
.X_add_number
-= 4;
12605 if (offset_high_part (offset_expr
.X_add_number
, 16)
12606 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12608 load_address (AT
, &offset_expr
, &used_at
);
12609 offset_expr
.X_op
= O_constant
;
12610 offset_expr
.X_add_number
= 0;
12613 macro_build_lui (&offset_expr
, AT
);
12615 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12616 /* Itbl support may require additional care here. */
12617 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12618 BFD_RELOC_LO16
, AT
);
12619 /* FIXME: How do we handle overflow here? */
12620 offset_expr
.X_add_number
+= 4;
12621 /* Itbl support may require additional care here. */
12622 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12623 BFD_RELOC_LO16
, AT
);
12624 if (mips_relax
.sequence
)
12627 else if (!mips_big_got
)
12629 /* If this is a reference to an external symbol, we want
12630 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12633 <op> op[0]+1,4($at)
12635 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12637 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12638 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12639 If there is a base register we add it to $at before the
12640 lwc1 instructions. If there is a constant we include it
12641 in the lwc1 instructions. */
12643 expr1
.X_add_number
= offset_expr
.X_add_number
;
12644 if (expr1
.X_add_number
< -0x8000
12645 || expr1
.X_add_number
>= 0x8000 - 4)
12646 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12647 load_got_offset (AT
, &offset_expr
);
12650 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12652 /* Set mips_optimize to 2 to avoid inserting an undesired
12654 hold_mips_optimize
= mips_optimize
;
12657 /* Itbl support may require additional care here. */
12658 relax_start (offset_expr
.X_add_symbol
);
12659 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12660 BFD_RELOC_LO16
, AT
);
12661 expr1
.X_add_number
+= 4;
12662 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12663 BFD_RELOC_LO16
, AT
);
12665 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12666 BFD_RELOC_LO16
, AT
);
12667 offset_expr
.X_add_number
+= 4;
12668 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12669 BFD_RELOC_LO16
, AT
);
12672 mips_optimize
= hold_mips_optimize
;
12674 else if (mips_big_got
)
12678 /* If this is a reference to an external symbol, we want
12679 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12681 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12684 <op> op[0]+1,4($at)
12686 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12688 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12689 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12690 If there is a base register we add it to $at before the
12691 lwc1 instructions. If there is a constant we include it
12692 in the lwc1 instructions. */
12694 expr1
.X_add_number
= offset_expr
.X_add_number
;
12695 offset_expr
.X_add_number
= 0;
12696 if (expr1
.X_add_number
< -0x8000
12697 || expr1
.X_add_number
>= 0x8000 - 4)
12698 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12699 gpdelay
= reg_needs_delay (mips_gp_register
);
12700 relax_start (offset_expr
.X_add_symbol
);
12701 macro_build (&offset_expr
, "lui", LUI_FMT
,
12702 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12703 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12704 AT
, AT
, mips_gp_register
);
12705 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12706 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12709 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12710 /* Itbl support may require additional care here. */
12711 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12712 BFD_RELOC_LO16
, AT
);
12713 expr1
.X_add_number
+= 4;
12715 /* Set mips_optimize to 2 to avoid inserting an undesired
12717 hold_mips_optimize
= mips_optimize
;
12719 /* Itbl support may require additional care here. */
12720 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12721 BFD_RELOC_LO16
, AT
);
12722 mips_optimize
= hold_mips_optimize
;
12723 expr1
.X_add_number
-= 4;
12726 offset_expr
.X_add_number
= expr1
.X_add_number
;
12728 macro_build (NULL
, "nop", "");
12729 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12730 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12733 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12734 /* Itbl support may require additional care here. */
12735 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12736 BFD_RELOC_LO16
, AT
);
12737 offset_expr
.X_add_number
+= 4;
12739 /* Set mips_optimize to 2 to avoid inserting an undesired
12741 hold_mips_optimize
= mips_optimize
;
12743 /* Itbl support may require additional care here. */
12744 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12745 BFD_RELOC_LO16
, AT
);
12746 mips_optimize
= hold_mips_optimize
;
12760 gas_assert (!mips_opts
.micromips
);
12765 /* New code added to support COPZ instructions.
12766 This code builds table entries out of the macros in mip_opcodes.
12767 R4000 uses interlocks to handle coproc delays.
12768 Other chips (like the R3000) require nops to be inserted for delays.
12770 FIXME: Currently, we require that the user handle delays.
12771 In order to fill delay slots for non-interlocked chips,
12772 we must have a way to specify delays based on the coprocessor.
12773 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12774 What are the side-effects of the cop instruction?
12775 What cache support might we have and what are its effects?
12776 Both coprocessor & memory require delays. how long???
12777 What registers are read/set/modified?
12779 If an itbl is provided to interpret cop instructions,
12780 this knowledge can be encoded in the itbl spec. */
12794 gas_assert (!mips_opts
.micromips
);
12795 /* For now we just do C (same as Cz). The parameter will be
12796 stored in insn_opcode by mips_ip. */
12797 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12801 move_register (op
[0], op
[1]);
12805 gas_assert (mips_opts
.micromips
);
12806 gas_assert (mips_opts
.insn32
);
12807 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12808 micromips_to_32_reg_m_map
[op
[1]]);
12809 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12810 micromips_to_32_reg_n_map
[op
[2]]);
12815 /* Fall through. */
12817 if (mips_opts
.arch
== CPU_R5900
)
12818 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12822 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12823 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12829 /* Fall through. */
12831 /* The MIPS assembler some times generates shifts and adds. I'm
12832 not trying to be that fancy. GCC should do this for us
12835 load_register (AT
, &imm_expr
, dbl
);
12836 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12837 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12842 /* Fall through. */
12849 /* Fall through. */
12852 start_noreorder ();
12855 load_register (AT
, &imm_expr
, dbl
);
12856 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12857 op
[1], imm
? AT
: op
[2]);
12858 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12859 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12860 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12862 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12865 if (mips_opts
.micromips
)
12866 micromips_label_expr (&label_expr
);
12868 label_expr
.X_add_number
= 8;
12869 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12870 macro_build (NULL
, "nop", "");
12871 macro_build (NULL
, "break", BRK_FMT
, 6);
12872 if (mips_opts
.micromips
)
12873 micromips_add_label ();
12876 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12881 /* Fall through. */
12888 /* Fall through. */
12891 start_noreorder ();
12894 load_register (AT
, &imm_expr
, dbl
);
12895 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12896 op
[1], imm
? AT
: op
[2]);
12897 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12898 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12900 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12903 if (mips_opts
.micromips
)
12904 micromips_label_expr (&label_expr
);
12906 label_expr
.X_add_number
= 8;
12907 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12908 macro_build (NULL
, "nop", "");
12909 macro_build (NULL
, "break", BRK_FMT
, 6);
12910 if (mips_opts
.micromips
)
12911 micromips_add_label ();
12917 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12919 if (op
[0] == op
[1])
12926 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12927 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12931 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12932 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12933 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12934 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12938 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12940 if (op
[0] == op
[1])
12947 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12948 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12952 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12953 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12954 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12955 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12964 rot
= imm_expr
.X_add_number
& 0x3f;
12965 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12967 rot
= (64 - rot
) & 0x3f;
12969 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12971 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12976 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12979 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12980 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12983 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12984 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12985 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12993 rot
= imm_expr
.X_add_number
& 0x1f;
12994 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12996 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12997 (32 - rot
) & 0x1f);
13002 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13006 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13007 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13008 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13013 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13015 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13019 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13020 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13021 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13022 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13026 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13028 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13032 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13033 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13034 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13035 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13044 rot
= imm_expr
.X_add_number
& 0x3f;
13045 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13048 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13050 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13055 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13058 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13059 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13062 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13063 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13064 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13072 rot
= imm_expr
.X_add_number
& 0x1f;
13073 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13075 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13080 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13084 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13085 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13086 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13092 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13093 else if (op
[2] == 0)
13094 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13097 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13098 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13103 if (imm_expr
.X_add_number
== 0)
13105 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13110 as_warn (_("instruction %s: result is always false"),
13111 ip
->insn_mo
->name
);
13112 move_register (op
[0], 0);
13115 if (CPU_HAS_SEQ (mips_opts
.arch
)
13116 && -512 <= imm_expr
.X_add_number
13117 && imm_expr
.X_add_number
< 512)
13119 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13120 (int) imm_expr
.X_add_number
);
13123 if (imm_expr
.X_add_number
>= 0
13124 && imm_expr
.X_add_number
< 0x10000)
13125 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13126 else if (imm_expr
.X_add_number
> -0x8000
13127 && imm_expr
.X_add_number
< 0)
13129 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13130 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13131 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13133 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13136 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13137 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13142 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13143 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13146 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13149 case M_SGE
: /* X >= Y <==> not (X < Y) */
13155 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13156 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13159 case M_SGE_I
: /* X >= I <==> not (X < I) */
13161 if (imm_expr
.X_add_number
>= -0x8000
13162 && imm_expr
.X_add_number
< 0x8000)
13163 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13164 op
[0], op
[1], BFD_RELOC_LO16
);
13167 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13168 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13172 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13175 case M_SGT
: /* X > Y <==> Y < X */
13181 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13184 case M_SGT_I
: /* X > I <==> I < X */
13191 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13192 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13195 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13201 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13202 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13205 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13212 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13213 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13214 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13218 if (imm_expr
.X_add_number
>= -0x8000
13219 && imm_expr
.X_add_number
< 0x8000)
13221 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13226 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13227 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13231 if (imm_expr
.X_add_number
>= -0x8000
13232 && imm_expr
.X_add_number
< 0x8000)
13234 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13239 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13240 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13245 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13246 else if (op
[2] == 0)
13247 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13250 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13251 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13256 if (imm_expr
.X_add_number
== 0)
13258 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13263 as_warn (_("instruction %s: result is always true"),
13264 ip
->insn_mo
->name
);
13265 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13266 op
[0], 0, BFD_RELOC_LO16
);
13269 if (CPU_HAS_SEQ (mips_opts
.arch
)
13270 && -512 <= imm_expr
.X_add_number
13271 && imm_expr
.X_add_number
< 512)
13273 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13274 (int) imm_expr
.X_add_number
);
13277 if (imm_expr
.X_add_number
>= 0
13278 && imm_expr
.X_add_number
< 0x10000)
13280 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13283 else if (imm_expr
.X_add_number
> -0x8000
13284 && imm_expr
.X_add_number
< 0)
13286 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13287 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13288 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13290 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13293 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13294 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13299 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13300 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13303 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13318 if (!mips_opts
.micromips
)
13320 if (imm_expr
.X_add_number
> -0x200
13321 && imm_expr
.X_add_number
<= 0x200)
13323 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13324 (int) -imm_expr
.X_add_number
);
13333 if (imm_expr
.X_add_number
> -0x8000
13334 && imm_expr
.X_add_number
<= 0x8000)
13336 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13337 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13342 load_register (AT
, &imm_expr
, dbl
);
13343 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13365 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13366 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13371 gas_assert (!mips_opts
.micromips
);
13372 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13376 * Is the double cfc1 instruction a bug in the mips assembler;
13377 * or is there a reason for it?
13379 start_noreorder ();
13380 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13381 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13382 macro_build (NULL
, "nop", "");
13383 expr1
.X_add_number
= 3;
13384 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13385 expr1
.X_add_number
= 2;
13386 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13387 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13388 macro_build (NULL
, "nop", "");
13389 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13391 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13392 macro_build (NULL
, "nop", "");
13409 offbits
= (mips_opts
.micromips
? 12 : 16);
13415 offbits
= (mips_opts
.micromips
? 12 : 16);
13427 offbits
= (mips_opts
.micromips
? 12 : 16);
13434 offbits
= (mips_opts
.micromips
? 12 : 16);
13440 large_offset
= !small_offset_p (off
, align
, offbits
);
13442 expr1
.X_add_number
= 0;
13447 if (small_offset_p (0, align
, 16))
13448 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13449 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13452 load_address (tempreg
, ep
, &used_at
);
13454 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13455 tempreg
, tempreg
, breg
);
13457 offset_reloc
[0] = BFD_RELOC_LO16
;
13458 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13459 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13464 else if (!ust
&& op
[0] == breg
)
13475 if (!target_big_endian
)
13476 ep
->X_add_number
+= off
;
13478 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13480 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13481 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13483 if (!target_big_endian
)
13484 ep
->X_add_number
-= off
;
13486 ep
->X_add_number
+= off
;
13488 macro_build (NULL
, s2
, "t,~(b)",
13489 tempreg
, (int) ep
->X_add_number
, breg
);
13491 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13492 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13494 /* If necessary, move the result in tempreg to the final destination. */
13495 if (!ust
&& op
[0] != tempreg
)
13497 /* Protect second load's delay slot. */
13499 move_register (op
[0], tempreg
);
13505 if (target_big_endian
== ust
)
13506 ep
->X_add_number
+= off
;
13507 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13508 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13509 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13511 /* For halfword transfers we need a temporary register to shuffle
13512 bytes. Unfortunately for M_USH_A we have none available before
13513 the next store as AT holds the base address. We deal with this
13514 case by clobbering TREG and then restoring it as with ULH. */
13515 tempreg
= ust
== large_offset
? op
[0] : AT
;
13517 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13519 if (target_big_endian
== ust
)
13520 ep
->X_add_number
-= off
;
13522 ep
->X_add_number
+= off
;
13523 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13524 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13526 /* For M_USH_A re-retrieve the LSB. */
13527 if (ust
&& large_offset
)
13529 if (target_big_endian
)
13530 ep
->X_add_number
+= off
;
13532 ep
->X_add_number
-= off
;
13533 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13534 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13536 /* For ULH and M_USH_A OR the LSB in. */
13537 if (!ust
|| large_offset
)
13539 tempreg
= !large_offset
? AT
: op
[0];
13540 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13541 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13546 /* FIXME: Check if this is one of the itbl macros, since they
13547 are added dynamically. */
13548 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13551 if (!mips_opts
.at
&& used_at
)
13552 as_bad (_("macro used $at after \".set noat\""));
13555 /* Implement macros in mips16 mode. */
13558 mips16_macro (struct mips_cl_insn
*ip
)
13560 const struct mips_operand_array
*operands
;
13565 const char *s
, *s2
, *s3
;
13566 unsigned int op
[MAX_OPERANDS
];
13569 mask
= ip
->insn_mo
->mask
;
13571 operands
= insn_operands (ip
);
13572 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13573 if (operands
->operand
[i
])
13574 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13578 expr1
.X_op
= O_constant
;
13579 expr1
.X_op_symbol
= NULL
;
13580 expr1
.X_add_symbol
= NULL
;
13581 expr1
.X_add_number
= 1;
13592 /* Fall through. */
13598 /* Fall through. */
13602 start_noreorder ();
13603 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13604 expr1
.X_add_number
= 2;
13605 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13606 macro_build (NULL
, "break", "6", 7);
13608 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13609 since that causes an overflow. We should do that as well,
13610 but I don't see how to do the comparisons without a temporary
13613 macro_build (NULL
, s
, "x", op
[0]);
13632 start_noreorder ();
13633 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13634 expr1
.X_add_number
= 2;
13635 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13636 macro_build (NULL
, "break", "6", 7);
13638 macro_build (NULL
, s2
, "x", op
[0]);
13643 /* Fall through. */
13645 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13646 macro_build (NULL
, "mflo", "x", op
[0]);
13654 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13655 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13659 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13660 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13664 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13665 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13687 goto do_reverse_branch
;
13691 goto do_reverse_branch
;
13703 goto do_reverse_branch
;
13714 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13715 macro_build (&offset_expr
, s2
, "p");
13742 goto do_addone_branch_i
;
13747 goto do_addone_branch_i
;
13762 goto do_addone_branch_i
;
13768 do_addone_branch_i
:
13769 ++imm_expr
.X_add_number
;
13772 macro_build (&imm_expr
, s
, s3
, op
[0]);
13773 macro_build (&offset_expr
, s2
, "p");
13777 expr1
.X_add_number
= 0;
13778 macro_build (&expr1
, "slti", "x,8", op
[1]);
13779 if (op
[0] != op
[1])
13780 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13781 expr1
.X_add_number
= 2;
13782 macro_build (&expr1
, "bteqz", "p");
13783 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13788 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13789 opcode bits in *OPCODE_EXTRA. */
13791 static struct mips_opcode
*
13792 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13793 ssize_t length
, unsigned int *opcode_extra
)
13795 char *name
, *dot
, *p
;
13796 unsigned int mask
, suffix
;
13798 struct mips_opcode
*insn
;
13800 /* Make a copy of the instruction so that we can fiddle with it. */
13801 name
= xstrndup (start
, length
);
13803 /* Look up the instruction as-is. */
13804 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13808 dot
= strchr (name
, '.');
13811 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13812 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13813 if (*p
== 0 && mask
!= 0)
13816 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13818 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13820 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13826 if (mips_opts
.micromips
)
13828 /* See if there's an instruction size override suffix,
13829 either `16' or `32', at the end of the mnemonic proper,
13830 that defines the operation, i.e. before the first `.'
13831 character if any. Strip it and retry. */
13832 opend
= dot
!= NULL
? dot
- name
: length
;
13833 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13835 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13841 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13842 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13845 forced_insn_length
= suffix
;
13857 /* Assemble an instruction into its binary format. If the instruction
13858 is a macro, set imm_expr and offset_expr to the values associated
13859 with "I" and "A" operands respectively. Otherwise store the value
13860 of the relocatable field (if any) in offset_expr. In both cases
13861 set offset_reloc to the relocation operators applied to offset_expr. */
13864 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13866 const struct mips_opcode
*first
, *past
;
13867 struct hash_control
*hash
;
13870 struct mips_operand_token
*tokens
;
13871 unsigned int opcode_extra
;
13873 if (mips_opts
.micromips
)
13875 hash
= micromips_op_hash
;
13876 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13881 past
= &mips_opcodes
[NUMOPCODES
];
13883 forced_insn_length
= 0;
13886 /* We first try to match an instruction up to a space or to the end. */
13887 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13890 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13893 set_insn_error (0, _("unrecognized opcode"));
13897 if (strcmp (first
->name
, "li.s") == 0)
13899 else if (strcmp (first
->name
, "li.d") == 0)
13903 tokens
= mips_parse_arguments (str
+ end
, format
);
13907 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13908 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13909 set_insn_error (0, _("invalid operands"));
13911 obstack_free (&mips_operand_tokens
, tokens
);
13914 /* As for mips_ip, but used when assembling MIPS16 code.
13915 Also set forced_insn_length to the resulting instruction size in
13916 bytes if the user explicitly requested a small or extended instruction. */
13919 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13922 struct mips_opcode
*first
;
13923 struct mips_operand_token
*tokens
;
13926 for (s
= str
; ISLOWER (*s
); ++s
)
13948 else if (*s
== 'e')
13955 else if (*s
++ == ' ')
13957 /* Fall through. */
13959 set_insn_error (0, _("unrecognized opcode"));
13962 forced_insn_length
= l
;
13965 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13970 set_insn_error (0, _("unrecognized opcode"));
13974 tokens
= mips_parse_arguments (s
, 0);
13978 if (!match_mips16_insns (insn
, first
, tokens
))
13979 set_insn_error (0, _("invalid operands"));
13981 obstack_free (&mips_operand_tokens
, tokens
);
13984 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13985 NBITS is the number of significant bits in VAL. */
13987 static unsigned long
13988 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13993 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13996 else if (nbits
== 15)
13998 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14003 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14006 return (extval
<< 16) | val
;
14009 /* Like decode_mips16_operand, but require the operand to be defined and
14010 require it to be an integer. */
14012 static const struct mips_int_operand
*
14013 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14015 const struct mips_operand
*operand
;
14017 operand
= decode_mips16_operand (type
, extended_p
);
14018 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14020 return (const struct mips_int_operand
*) operand
;
14023 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14026 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14027 bfd_reloc_code_real_type reloc
, offsetT sval
)
14029 int min_val
, max_val
;
14031 min_val
= mips_int_operand_min (operand
);
14032 max_val
= mips_int_operand_max (operand
);
14033 if (reloc
!= BFD_RELOC_UNUSED
)
14036 sval
= SEXT_16BIT (sval
);
14041 return (sval
>= min_val
14043 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14046 /* Install immediate value VAL into MIPS16 instruction *INSN,
14047 extending it if necessary. The instruction in *INSN may
14048 already be extended.
14050 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14051 if none. In the former case, VAL is a 16-bit number with no
14052 defined signedness.
14054 TYPE is the type of the immediate field. USER_INSN_LENGTH
14055 is the length that the user requested, or 0 if none. */
14058 mips16_immed (const char *file
, unsigned int line
, int type
,
14059 bfd_reloc_code_real_type reloc
, offsetT val
,
14060 unsigned int user_insn_length
, unsigned long *insn
)
14062 const struct mips_int_operand
*operand
;
14063 unsigned int uval
, length
;
14065 operand
= mips16_immed_operand (type
, FALSE
);
14066 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14068 /* We need an extended instruction. */
14069 if (user_insn_length
== 2)
14070 as_bad_where (file
, line
, _("invalid unextended operand value"));
14072 *insn
|= MIPS16_EXTEND
;
14074 else if (user_insn_length
== 4)
14076 /* The operand doesn't force an unextended instruction to be extended.
14077 Warn if the user wanted an extended instruction anyway. */
14078 *insn
|= MIPS16_EXTEND
;
14079 as_warn_where (file
, line
,
14080 _("extended operand requested but not required"));
14083 length
= mips16_opcode_length (*insn
);
14086 operand
= mips16_immed_operand (type
, TRUE
);
14087 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14088 as_bad_where (file
, line
,
14089 _("operand value out of range for instruction"));
14091 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14092 if (length
== 2 || operand
->root
.lsb
!= 0)
14093 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14095 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14098 struct percent_op_match
14101 bfd_reloc_code_real_type reloc
;
14104 static const struct percent_op_match mips_percent_op
[] =
14106 {"%lo", BFD_RELOC_LO16
},
14107 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14108 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14109 {"%call16", BFD_RELOC_MIPS_CALL16
},
14110 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14111 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14112 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14113 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14114 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14115 {"%got", BFD_RELOC_MIPS_GOT16
},
14116 {"%gp_rel", BFD_RELOC_GPREL16
},
14117 {"%gprel", BFD_RELOC_GPREL16
},
14118 {"%half", BFD_RELOC_16
},
14119 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14120 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14121 {"%neg", BFD_RELOC_MIPS_SUB
},
14122 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14123 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14124 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14125 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14126 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14127 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14128 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14129 {"%hi", BFD_RELOC_HI16_S
},
14130 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14131 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14134 static const struct percent_op_match mips16_percent_op
[] =
14136 {"%lo", BFD_RELOC_MIPS16_LO16
},
14137 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14138 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14139 {"%got", BFD_RELOC_MIPS16_GOT16
},
14140 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14141 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14142 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14143 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14144 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14145 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14146 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14147 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14148 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14152 /* Return true if *STR points to a relocation operator. When returning true,
14153 move *STR over the operator and store its relocation code in *RELOC.
14154 Leave both *STR and *RELOC alone when returning false. */
14157 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14159 const struct percent_op_match
*percent_op
;
14162 if (mips_opts
.mips16
)
14164 percent_op
= mips16_percent_op
;
14165 limit
= ARRAY_SIZE (mips16_percent_op
);
14169 percent_op
= mips_percent_op
;
14170 limit
= ARRAY_SIZE (mips_percent_op
);
14173 for (i
= 0; i
< limit
; i
++)
14174 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14176 int len
= strlen (percent_op
[i
].str
);
14178 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14181 *str
+= strlen (percent_op
[i
].str
);
14182 *reloc
= percent_op
[i
].reloc
;
14184 /* Check whether the output BFD supports this relocation.
14185 If not, issue an error and fall back on something safe. */
14186 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14188 as_bad (_("relocation %s isn't supported by the current ABI"),
14189 percent_op
[i
].str
);
14190 *reloc
= BFD_RELOC_UNUSED
;
14198 /* Parse string STR as a 16-bit relocatable operand. Store the
14199 expression in *EP and the relocations in the array starting
14200 at RELOC. Return the number of relocation operators used.
14202 On exit, EXPR_END points to the first character after the expression. */
14205 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14208 bfd_reloc_code_real_type reversed_reloc
[3];
14209 size_t reloc_index
, i
;
14210 int crux_depth
, str_depth
;
14213 /* Search for the start of the main expression, recoding relocations
14214 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14215 of the main expression and with CRUX_DEPTH containing the number
14216 of open brackets at that point. */
14223 crux_depth
= str_depth
;
14225 /* Skip over whitespace and brackets, keeping count of the number
14227 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14232 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14233 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14235 my_getExpression (ep
, crux
);
14238 /* Match every open bracket. */
14239 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14243 if (crux_depth
> 0)
14244 as_bad (_("unclosed '('"));
14248 if (reloc_index
!= 0)
14250 prev_reloc_op_frag
= frag_now
;
14251 for (i
= 0; i
< reloc_index
; i
++)
14252 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14255 return reloc_index
;
14259 my_getExpression (expressionS
*ep
, char *str
)
14263 save_in
= input_line_pointer
;
14264 input_line_pointer
= str
;
14266 expr_end
= input_line_pointer
;
14267 input_line_pointer
= save_in
;
14271 md_atof (int type
, char *litP
, int *sizeP
)
14273 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14277 md_number_to_chars (char *buf
, valueT val
, int n
)
14279 if (target_big_endian
)
14280 number_to_chars_bigendian (buf
, val
, n
);
14282 number_to_chars_littleendian (buf
, val
, n
);
14285 static int support_64bit_objects(void)
14287 const char **list
, **l
;
14290 list
= bfd_target_list ();
14291 for (l
= list
; *l
!= NULL
; l
++)
14292 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14293 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14295 yes
= (*l
!= NULL
);
14300 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14301 NEW_VALUE. Warn if another value was already specified. Note:
14302 we have to defer parsing the -march and -mtune arguments in order
14303 to handle 'from-abi' correctly, since the ABI might be specified
14304 in a later argument. */
14307 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14309 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14310 as_warn (_("a different %s was already specified, is now %s"),
14311 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14314 *string_ptr
= new_value
;
14318 md_parse_option (int c
, const char *arg
)
14322 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14323 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14325 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14326 c
== mips_ases
[i
].option_on
);
14332 case OPTION_CONSTRUCT_FLOATS
:
14333 mips_disable_float_construction
= 0;
14336 case OPTION_NO_CONSTRUCT_FLOATS
:
14337 mips_disable_float_construction
= 1;
14349 target_big_endian
= 1;
14353 target_big_endian
= 0;
14359 else if (arg
[0] == '0')
14361 else if (arg
[0] == '1')
14371 mips_debug
= atoi (arg
);
14375 file_mips_opts
.isa
= ISA_MIPS1
;
14379 file_mips_opts
.isa
= ISA_MIPS2
;
14383 file_mips_opts
.isa
= ISA_MIPS3
;
14387 file_mips_opts
.isa
= ISA_MIPS4
;
14391 file_mips_opts
.isa
= ISA_MIPS5
;
14394 case OPTION_MIPS32
:
14395 file_mips_opts
.isa
= ISA_MIPS32
;
14398 case OPTION_MIPS32R2
:
14399 file_mips_opts
.isa
= ISA_MIPS32R2
;
14402 case OPTION_MIPS32R3
:
14403 file_mips_opts
.isa
= ISA_MIPS32R3
;
14406 case OPTION_MIPS32R5
:
14407 file_mips_opts
.isa
= ISA_MIPS32R5
;
14410 case OPTION_MIPS32R6
:
14411 file_mips_opts
.isa
= ISA_MIPS32R6
;
14414 case OPTION_MIPS64R2
:
14415 file_mips_opts
.isa
= ISA_MIPS64R2
;
14418 case OPTION_MIPS64R3
:
14419 file_mips_opts
.isa
= ISA_MIPS64R3
;
14422 case OPTION_MIPS64R5
:
14423 file_mips_opts
.isa
= ISA_MIPS64R5
;
14426 case OPTION_MIPS64R6
:
14427 file_mips_opts
.isa
= ISA_MIPS64R6
;
14430 case OPTION_MIPS64
:
14431 file_mips_opts
.isa
= ISA_MIPS64
;
14435 mips_set_option_string (&mips_tune_string
, arg
);
14439 mips_set_option_string (&mips_arch_string
, arg
);
14443 mips_set_option_string (&mips_arch_string
, "4650");
14444 mips_set_option_string (&mips_tune_string
, "4650");
14447 case OPTION_NO_M4650
:
14451 mips_set_option_string (&mips_arch_string
, "4010");
14452 mips_set_option_string (&mips_tune_string
, "4010");
14455 case OPTION_NO_M4010
:
14459 mips_set_option_string (&mips_arch_string
, "4100");
14460 mips_set_option_string (&mips_tune_string
, "4100");
14463 case OPTION_NO_M4100
:
14467 mips_set_option_string (&mips_arch_string
, "3900");
14468 mips_set_option_string (&mips_tune_string
, "3900");
14471 case OPTION_NO_M3900
:
14474 case OPTION_MICROMIPS
:
14475 if (file_mips_opts
.mips16
== 1)
14477 as_bad (_("-mmicromips cannot be used with -mips16"));
14480 file_mips_opts
.micromips
= 1;
14481 mips_no_prev_insn ();
14484 case OPTION_NO_MICROMIPS
:
14485 file_mips_opts
.micromips
= 0;
14486 mips_no_prev_insn ();
14489 case OPTION_MIPS16
:
14490 if (file_mips_opts
.micromips
== 1)
14492 as_bad (_("-mips16 cannot be used with -micromips"));
14495 file_mips_opts
.mips16
= 1;
14496 mips_no_prev_insn ();
14499 case OPTION_NO_MIPS16
:
14500 file_mips_opts
.mips16
= 0;
14501 mips_no_prev_insn ();
14504 case OPTION_FIX_24K
:
14508 case OPTION_NO_FIX_24K
:
14512 case OPTION_FIX_RM7000
:
14513 mips_fix_rm7000
= 1;
14516 case OPTION_NO_FIX_RM7000
:
14517 mips_fix_rm7000
= 0;
14520 case OPTION_FIX_LOONGSON2F_JUMP
:
14521 mips_fix_loongson2f_jump
= TRUE
;
14524 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14525 mips_fix_loongson2f_jump
= FALSE
;
14528 case OPTION_FIX_LOONGSON2F_NOP
:
14529 mips_fix_loongson2f_nop
= TRUE
;
14532 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14533 mips_fix_loongson2f_nop
= FALSE
;
14536 case OPTION_FIX_VR4120
:
14537 mips_fix_vr4120
= 1;
14540 case OPTION_NO_FIX_VR4120
:
14541 mips_fix_vr4120
= 0;
14544 case OPTION_FIX_VR4130
:
14545 mips_fix_vr4130
= 1;
14548 case OPTION_NO_FIX_VR4130
:
14549 mips_fix_vr4130
= 0;
14552 case OPTION_FIX_CN63XXP1
:
14553 mips_fix_cn63xxp1
= TRUE
;
14556 case OPTION_NO_FIX_CN63XXP1
:
14557 mips_fix_cn63xxp1
= FALSE
;
14560 case OPTION_RELAX_BRANCH
:
14561 mips_relax_branch
= 1;
14564 case OPTION_NO_RELAX_BRANCH
:
14565 mips_relax_branch
= 0;
14568 case OPTION_IGNORE_BRANCH_ISA
:
14569 mips_ignore_branch_isa
= TRUE
;
14572 case OPTION_NO_IGNORE_BRANCH_ISA
:
14573 mips_ignore_branch_isa
= FALSE
;
14576 case OPTION_INSN32
:
14577 file_mips_opts
.insn32
= TRUE
;
14580 case OPTION_NO_INSN32
:
14581 file_mips_opts
.insn32
= FALSE
;
14584 case OPTION_MSHARED
:
14585 mips_in_shared
= TRUE
;
14588 case OPTION_MNO_SHARED
:
14589 mips_in_shared
= FALSE
;
14592 case OPTION_MSYM32
:
14593 file_mips_opts
.sym32
= TRUE
;
14596 case OPTION_MNO_SYM32
:
14597 file_mips_opts
.sym32
= FALSE
;
14600 /* When generating ELF code, we permit -KPIC and -call_shared to
14601 select SVR4_PIC, and -non_shared to select no PIC. This is
14602 intended to be compatible with Irix 5. */
14603 case OPTION_CALL_SHARED
:
14604 mips_pic
= SVR4_PIC
;
14605 mips_abicalls
= TRUE
;
14608 case OPTION_CALL_NONPIC
:
14610 mips_abicalls
= TRUE
;
14613 case OPTION_NON_SHARED
:
14615 mips_abicalls
= FALSE
;
14618 /* The -xgot option tells the assembler to use 32 bit offsets
14619 when accessing the got in SVR4_PIC mode. It is for Irix
14626 g_switch_value
= atoi (arg
);
14630 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14633 mips_abi
= O32_ABI
;
14637 mips_abi
= N32_ABI
;
14641 mips_abi
= N64_ABI
;
14642 if (!support_64bit_objects())
14643 as_fatal (_("no compiled in support for 64 bit object file format"));
14647 file_mips_opts
.gp
= 32;
14651 file_mips_opts
.gp
= 64;
14655 file_mips_opts
.fp
= 32;
14659 file_mips_opts
.fp
= 0;
14663 file_mips_opts
.fp
= 64;
14666 case OPTION_ODD_SPREG
:
14667 file_mips_opts
.oddspreg
= 1;
14670 case OPTION_NO_ODD_SPREG
:
14671 file_mips_opts
.oddspreg
= 0;
14674 case OPTION_SINGLE_FLOAT
:
14675 file_mips_opts
.single_float
= 1;
14678 case OPTION_DOUBLE_FLOAT
:
14679 file_mips_opts
.single_float
= 0;
14682 case OPTION_SOFT_FLOAT
:
14683 file_mips_opts
.soft_float
= 1;
14686 case OPTION_HARD_FLOAT
:
14687 file_mips_opts
.soft_float
= 0;
14691 if (strcmp (arg
, "32") == 0)
14692 mips_abi
= O32_ABI
;
14693 else if (strcmp (arg
, "o64") == 0)
14694 mips_abi
= O64_ABI
;
14695 else if (strcmp (arg
, "n32") == 0)
14696 mips_abi
= N32_ABI
;
14697 else if (strcmp (arg
, "64") == 0)
14699 mips_abi
= N64_ABI
;
14700 if (! support_64bit_objects())
14701 as_fatal (_("no compiled in support for 64 bit object file "
14704 else if (strcmp (arg
, "eabi") == 0)
14705 mips_abi
= EABI_ABI
;
14708 as_fatal (_("invalid abi -mabi=%s"), arg
);
14713 case OPTION_M7000_HILO_FIX
:
14714 mips_7000_hilo_fix
= TRUE
;
14717 case OPTION_MNO_7000_HILO_FIX
:
14718 mips_7000_hilo_fix
= FALSE
;
14721 case OPTION_MDEBUG
:
14722 mips_flag_mdebug
= TRUE
;
14725 case OPTION_NO_MDEBUG
:
14726 mips_flag_mdebug
= FALSE
;
14730 mips_flag_pdr
= TRUE
;
14733 case OPTION_NO_PDR
:
14734 mips_flag_pdr
= FALSE
;
14737 case OPTION_MVXWORKS_PIC
:
14738 mips_pic
= VXWORKS_PIC
;
14742 if (strcmp (arg
, "2008") == 0)
14744 else if (strcmp (arg
, "legacy") == 0)
14748 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14757 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14762 /* Set up globals to tune for the ISA or processor described by INFO. */
14765 mips_set_tune (const struct mips_cpu_info
*info
)
14768 mips_tune
= info
->cpu
;
14773 mips_after_parse_args (void)
14775 const struct mips_cpu_info
*arch_info
= 0;
14776 const struct mips_cpu_info
*tune_info
= 0;
14778 /* GP relative stuff not working for PE */
14779 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14781 if (g_switch_seen
&& g_switch_value
!= 0)
14782 as_bad (_("-G not supported in this configuration"));
14783 g_switch_value
= 0;
14786 if (mips_abi
== NO_ABI
)
14787 mips_abi
= MIPS_DEFAULT_ABI
;
14789 /* The following code determines the architecture.
14790 Similar code was added to GCC 3.3 (see override_options() in
14791 config/mips/mips.c). The GAS and GCC code should be kept in sync
14792 as much as possible. */
14794 if (mips_arch_string
!= 0)
14795 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14797 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14799 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14800 ISA level specified by -mipsN, while arch_info->isa contains
14801 the -march selection (if any). */
14802 if (arch_info
!= 0)
14804 /* -march takes precedence over -mipsN, since it is more descriptive.
14805 There's no harm in specifying both as long as the ISA levels
14807 if (file_mips_opts
.isa
!= arch_info
->isa
)
14808 as_bad (_("-%s conflicts with the other architecture options,"
14809 " which imply -%s"),
14810 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14811 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14814 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14817 if (arch_info
== 0)
14819 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14820 gas_assert (arch_info
);
14823 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14824 as_bad (_("-march=%s is not compatible with the selected ABI"),
14827 file_mips_opts
.arch
= arch_info
->cpu
;
14828 file_mips_opts
.isa
= arch_info
->isa
;
14830 /* Set up initial mips_opts state. */
14831 mips_opts
= file_mips_opts
;
14833 /* The register size inference code is now placed in
14834 file_mips_check_options. */
14836 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14838 if (mips_tune_string
!= 0)
14839 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14841 if (tune_info
== 0)
14842 mips_set_tune (arch_info
);
14844 mips_set_tune (tune_info
);
14846 if (mips_flag_mdebug
< 0)
14847 mips_flag_mdebug
= 0;
14851 mips_init_after_args (void)
14853 /* initialize opcodes */
14854 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14855 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14859 md_pcrel_from (fixS
*fixP
)
14861 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14862 switch (fixP
->fx_r_type
)
14864 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14865 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14866 /* Return the address of the delay slot. */
14869 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14870 case BFD_RELOC_MICROMIPS_JMP
:
14871 case BFD_RELOC_MIPS16_16_PCREL_S1
:
14872 case BFD_RELOC_16_PCREL_S2
:
14873 case BFD_RELOC_MIPS_21_PCREL_S2
:
14874 case BFD_RELOC_MIPS_26_PCREL_S2
:
14875 case BFD_RELOC_MIPS_JMP
:
14876 /* Return the address of the delay slot. */
14879 case BFD_RELOC_MIPS_18_PCREL_S3
:
14880 /* Return the aligned address of the doubleword containing
14881 the instruction. */
14889 /* This is called before the symbol table is processed. In order to
14890 work with gcc when using mips-tfile, we must keep all local labels.
14891 However, in other cases, we want to discard them. If we were
14892 called with -g, but we didn't see any debugging information, it may
14893 mean that gcc is smuggling debugging information through to
14894 mips-tfile, in which case we must generate all local labels. */
14897 mips_frob_file_before_adjust (void)
14899 #ifndef NO_ECOFF_DEBUGGING
14900 if (ECOFF_DEBUGGING
14902 && ! ecoff_debugging_seen
)
14903 flag_keep_locals
= 1;
14907 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14908 the corresponding LO16 reloc. This is called before md_apply_fix and
14909 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14910 relocation operators.
14912 For our purposes, a %lo() expression matches a %got() or %hi()
14915 (a) it refers to the same symbol; and
14916 (b) the offset applied in the %lo() expression is no lower than
14917 the offset applied in the %got() or %hi().
14919 (b) allows us to cope with code like:
14922 lh $4,%lo(foo+2)($4)
14924 ...which is legal on RELA targets, and has a well-defined behaviour
14925 if the user knows that adding 2 to "foo" will not induce a carry to
14928 When several %lo()s match a particular %got() or %hi(), we use the
14929 following rules to distinguish them:
14931 (1) %lo()s with smaller offsets are a better match than %lo()s with
14934 (2) %lo()s with no matching %got() or %hi() are better than those
14935 that already have a matching %got() or %hi().
14937 (3) later %lo()s are better than earlier %lo()s.
14939 These rules are applied in order.
14941 (1) means, among other things, that %lo()s with identical offsets are
14942 chosen if they exist.
14944 (2) means that we won't associate several high-part relocations with
14945 the same low-part relocation unless there's no alternative. Having
14946 several high parts for the same low part is a GNU extension; this rule
14947 allows careful users to avoid it.
14949 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14950 with the last high-part relocation being at the front of the list.
14951 It therefore makes sense to choose the last matching low-part
14952 relocation, all other things being equal. It's also easier
14953 to code that way. */
14956 mips_frob_file (void)
14958 struct mips_hi_fixup
*l
;
14959 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14961 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14963 segment_info_type
*seginfo
;
14964 bfd_boolean matched_lo_p
;
14965 fixS
**hi_pos
, **lo_pos
, **pos
;
14967 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14969 /* If a GOT16 relocation turns out to be against a global symbol,
14970 there isn't supposed to be a matching LO. Ignore %gots against
14971 constants; we'll report an error for those later. */
14972 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14973 && !(l
->fixp
->fx_addsy
14974 && pic_need_relax (l
->fixp
->fx_addsy
)))
14977 /* Check quickly whether the next fixup happens to be a matching %lo. */
14978 if (fixup_has_matching_lo_p (l
->fixp
))
14981 seginfo
= seg_info (l
->seg
);
14983 /* Set HI_POS to the position of this relocation in the chain.
14984 Set LO_POS to the position of the chosen low-part relocation.
14985 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14986 relocation that matches an immediately-preceding high-part
14990 matched_lo_p
= FALSE
;
14991 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14993 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14995 if (*pos
== l
->fixp
)
14998 if ((*pos
)->fx_r_type
== looking_for_rtype
14999 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15000 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15002 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15004 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15007 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15008 && fixup_has_matching_lo_p (*pos
));
15011 /* If we found a match, remove the high-part relocation from its
15012 current position and insert it before the low-part relocation.
15013 Make the offsets match so that fixup_has_matching_lo_p()
15016 We don't warn about unmatched high-part relocations since some
15017 versions of gcc have been known to emit dead "lui ...%hi(...)"
15019 if (lo_pos
!= NULL
)
15021 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15022 if (l
->fixp
->fx_next
!= *lo_pos
)
15024 *hi_pos
= l
->fixp
->fx_next
;
15025 l
->fixp
->fx_next
= *lo_pos
;
15033 mips_force_relocation (fixS
*fixp
)
15035 if (generic_force_reloc (fixp
))
15038 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15039 so that the linker relaxation can update targets. */
15040 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15041 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15042 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15045 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15046 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15047 microMIPS symbols so that we can do cross-mode branch diagnostics
15048 and BAL to JALX conversion by the linker. */
15049 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15050 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15051 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15053 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15056 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15057 if (ISA_IS_R6 (file_mips_opts
.isa
)
15058 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15059 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15060 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15061 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15062 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15063 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15064 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15070 /* Implement TC_FORCE_RELOCATION_ABS. */
15073 mips_force_relocation_abs (fixS
*fixp
)
15075 if (generic_force_reloc (fixp
))
15078 /* These relocations do not have enough bits in the in-place addend
15079 to hold an arbitrary absolute section's offset. */
15080 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15086 /* Read the instruction associated with RELOC from BUF. */
15088 static unsigned int
15089 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15091 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15092 return read_compressed_insn (buf
, 4);
15094 return read_insn (buf
);
15097 /* Write instruction INSN to BUF, given that it has been relocated
15101 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15102 unsigned long insn
)
15104 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15105 write_compressed_insn (buf
, insn
, 4);
15107 write_insn (buf
, insn
);
15110 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15111 to a symbol in another ISA mode, which cannot be converted to JALX. */
15114 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15116 unsigned long opcode
;
15120 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15123 other
= S_GET_OTHER (fixP
->fx_addsy
);
15124 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15125 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15126 switch (fixP
->fx_r_type
)
15128 case BFD_RELOC_MIPS_JMP
:
15129 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15130 case BFD_RELOC_MICROMIPS_JMP
:
15131 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15137 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15138 jump to a symbol in the same ISA mode. */
15141 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15143 unsigned long opcode
;
15147 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15150 other
= S_GET_OTHER (fixP
->fx_addsy
);
15151 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15152 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15153 switch (fixP
->fx_r_type
)
15155 case BFD_RELOC_MIPS_JMP
:
15156 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15157 case BFD_RELOC_MIPS16_JMP
:
15158 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15159 case BFD_RELOC_MICROMIPS_JMP
:
15160 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15166 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15167 to a symbol whose value plus addend is not aligned according to the
15168 ultimate (after linker relaxation) jump instruction's immediate field
15169 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15170 regular MIPS code, to (1 << 2). */
15173 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15175 bfd_boolean micro_to_mips_p
;
15179 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15182 other
= S_GET_OTHER (fixP
->fx_addsy
);
15183 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15184 val
+= fixP
->fx_offset
;
15185 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15186 && !ELF_ST_IS_MICROMIPS (other
));
15187 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15188 != ELF_ST_IS_COMPRESSED (other
));
15191 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15192 to a symbol whose annotation indicates another ISA mode. For absolute
15193 symbols check the ISA bit instead.
15195 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15196 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15197 MIPS symbols and associated with BAL instructions as these instructions
15198 may be be converted to JALX by the linker. */
15201 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15203 bfd_boolean absolute_p
;
15204 unsigned long opcode
;
15210 if (mips_ignore_branch_isa
)
15213 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15216 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15217 absolute_p
= bfd_is_abs_section (symsec
);
15219 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15220 other
= S_GET_OTHER (fixP
->fx_addsy
);
15222 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15223 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15224 switch (fixP
->fx_r_type
)
15226 case BFD_RELOC_16_PCREL_S2
:
15227 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15228 && opcode
!= 0x0411);
15229 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15230 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15231 && opcode
!= 0x4060);
15232 case BFD_RELOC_MIPS_21_PCREL_S2
:
15233 case BFD_RELOC_MIPS_26_PCREL_S2
:
15234 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15235 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15236 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15237 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15238 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15239 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15245 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15246 branch instruction pointed to by FIXP is not aligned according to the
15247 branch instruction's immediate field requirement. We need the addend
15248 to preserve the ISA bit and also the sum must not have bit 2 set. We
15249 must explicitly OR in the ISA bit from symbol annotation as the bit
15250 won't be set in the symbol's value then. */
15253 fix_bad_misaligned_branch_p (fixS
*fixP
)
15255 bfd_boolean absolute_p
;
15262 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15265 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15266 absolute_p
= bfd_is_abs_section (symsec
);
15268 val
= S_GET_VALUE (fixP
->fx_addsy
);
15269 other
= S_GET_OTHER (fixP
->fx_addsy
);
15270 off
= fixP
->fx_offset
;
15272 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15273 val
|= ELF_ST_IS_COMPRESSED (other
);
15275 return (val
& 0x3) != isa_bit
;
15278 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15279 and its calculated value VAL. */
15282 fix_validate_branch (fixS
*fixP
, valueT val
)
15284 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15285 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15286 _("branch to misaligned address (0x%lx)"),
15287 (long) (val
+ md_pcrel_from (fixP
)));
15288 else if (fix_bad_cross_mode_branch_p (fixP
))
15289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15290 _("branch to a symbol in another ISA mode"));
15291 else if (fix_bad_misaligned_branch_p (fixP
))
15292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15293 _("branch to misaligned address (0x%lx)"),
15294 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15295 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15297 _("cannot encode misaligned addend "
15298 "in the relocatable field (0x%lx)"),
15299 (long) fixP
->fx_offset
);
15302 /* Apply a fixup to the object file. */
15305 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15308 unsigned long insn
;
15309 reloc_howto_type
*howto
;
15311 if (fixP
->fx_pcrel
)
15312 switch (fixP
->fx_r_type
)
15314 case BFD_RELOC_16_PCREL_S2
:
15315 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15316 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15317 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15318 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15319 case BFD_RELOC_32_PCREL
:
15320 case BFD_RELOC_MIPS_21_PCREL_S2
:
15321 case BFD_RELOC_MIPS_26_PCREL_S2
:
15322 case BFD_RELOC_MIPS_18_PCREL_S3
:
15323 case BFD_RELOC_MIPS_19_PCREL_S2
:
15324 case BFD_RELOC_HI16_S_PCREL
:
15325 case BFD_RELOC_LO16_PCREL
:
15329 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15334 _("PC-relative reference to a different section"));
15338 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15339 that have no MIPS ELF equivalent. */
15340 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15342 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15347 gas_assert (fixP
->fx_size
== 2
15348 || fixP
->fx_size
== 4
15349 || fixP
->fx_r_type
== BFD_RELOC_8
15350 || fixP
->fx_r_type
== BFD_RELOC_16
15351 || fixP
->fx_r_type
== BFD_RELOC_64
15352 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15353 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15354 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15355 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15356 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15357 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15358 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15360 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15362 /* Don't treat parts of a composite relocation as done. There are two
15365 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15366 should nevertheless be emitted if the first part is.
15368 (2) In normal usage, composite relocations are never assembly-time
15369 constants. The easiest way of dealing with the pathological
15370 exceptions is to generate a relocation against STN_UNDEF and
15371 leave everything up to the linker. */
15372 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15375 switch (fixP
->fx_r_type
)
15377 case BFD_RELOC_MIPS_TLS_GD
:
15378 case BFD_RELOC_MIPS_TLS_LDM
:
15379 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15380 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15381 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15382 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15383 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15384 case BFD_RELOC_MIPS_TLS_TPREL32
:
15385 case BFD_RELOC_MIPS_TLS_TPREL64
:
15386 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15387 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15388 case BFD_RELOC_MICROMIPS_TLS_GD
:
15389 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15390 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15391 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15392 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15393 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15394 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15395 case BFD_RELOC_MIPS16_TLS_GD
:
15396 case BFD_RELOC_MIPS16_TLS_LDM
:
15397 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15398 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15399 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15400 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15401 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15402 if (fixP
->fx_addsy
)
15403 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15406 _("TLS relocation against a constant"));
15409 case BFD_RELOC_MIPS_JMP
:
15410 case BFD_RELOC_MIPS16_JMP
:
15411 case BFD_RELOC_MICROMIPS_JMP
:
15415 gas_assert (!fixP
->fx_done
);
15417 /* Shift is 2, unusually, for microMIPS JALX. */
15418 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15419 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15424 if (fix_bad_cross_mode_jump_p (fixP
))
15425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15426 _("jump to a symbol in another ISA mode"));
15427 else if (fix_bad_same_mode_jalx_p (fixP
))
15428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15429 _("JALX to a symbol in the same ISA mode"));
15430 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15431 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15432 _("jump to misaligned address (0x%lx)"),
15433 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15434 + fixP
->fx_offset
));
15435 else if (HAVE_IN_PLACE_ADDENDS
15436 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15438 _("cannot encode misaligned addend "
15439 "in the relocatable field (0x%lx)"),
15440 (long) fixP
->fx_offset
);
15442 /* Fall through. */
15444 case BFD_RELOC_MIPS_SHIFT5
:
15445 case BFD_RELOC_MIPS_SHIFT6
:
15446 case BFD_RELOC_MIPS_GOT_DISP
:
15447 case BFD_RELOC_MIPS_GOT_PAGE
:
15448 case BFD_RELOC_MIPS_GOT_OFST
:
15449 case BFD_RELOC_MIPS_SUB
:
15450 case BFD_RELOC_MIPS_INSERT_A
:
15451 case BFD_RELOC_MIPS_INSERT_B
:
15452 case BFD_RELOC_MIPS_DELETE
:
15453 case BFD_RELOC_MIPS_HIGHEST
:
15454 case BFD_RELOC_MIPS_HIGHER
:
15455 case BFD_RELOC_MIPS_SCN_DISP
:
15456 case BFD_RELOC_MIPS_REL16
:
15457 case BFD_RELOC_MIPS_RELGOT
:
15458 case BFD_RELOC_MIPS_JALR
:
15459 case BFD_RELOC_HI16
:
15460 case BFD_RELOC_HI16_S
:
15461 case BFD_RELOC_LO16
:
15462 case BFD_RELOC_GPREL16
:
15463 case BFD_RELOC_MIPS_LITERAL
:
15464 case BFD_RELOC_MIPS_CALL16
:
15465 case BFD_RELOC_MIPS_GOT16
:
15466 case BFD_RELOC_GPREL32
:
15467 case BFD_RELOC_MIPS_GOT_HI16
:
15468 case BFD_RELOC_MIPS_GOT_LO16
:
15469 case BFD_RELOC_MIPS_CALL_HI16
:
15470 case BFD_RELOC_MIPS_CALL_LO16
:
15471 case BFD_RELOC_HI16_S_PCREL
:
15472 case BFD_RELOC_LO16_PCREL
:
15473 case BFD_RELOC_MIPS16_GPREL
:
15474 case BFD_RELOC_MIPS16_GOT16
:
15475 case BFD_RELOC_MIPS16_CALL16
:
15476 case BFD_RELOC_MIPS16_HI16
:
15477 case BFD_RELOC_MIPS16_HI16_S
:
15478 case BFD_RELOC_MIPS16_LO16
:
15479 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15480 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15481 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15482 case BFD_RELOC_MICROMIPS_SUB
:
15483 case BFD_RELOC_MICROMIPS_HIGHEST
:
15484 case BFD_RELOC_MICROMIPS_HIGHER
:
15485 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15486 case BFD_RELOC_MICROMIPS_JALR
:
15487 case BFD_RELOC_MICROMIPS_HI16
:
15488 case BFD_RELOC_MICROMIPS_HI16_S
:
15489 case BFD_RELOC_MICROMIPS_LO16
:
15490 case BFD_RELOC_MICROMIPS_GPREL16
:
15491 case BFD_RELOC_MICROMIPS_LITERAL
:
15492 case BFD_RELOC_MICROMIPS_CALL16
:
15493 case BFD_RELOC_MICROMIPS_GOT16
:
15494 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15495 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15496 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15497 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15498 case BFD_RELOC_MIPS_EH
:
15503 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15505 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15506 if (mips16_reloc_p (fixP
->fx_r_type
))
15507 insn
|= mips16_immed_extend (value
, 16);
15509 insn
|= (value
& 0xffff);
15510 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15514 _("unsupported constant in relocation"));
15519 /* This is handled like BFD_RELOC_32, but we output a sign
15520 extended value if we are only 32 bits. */
15523 if (8 <= sizeof (valueT
))
15524 md_number_to_chars (buf
, *valP
, 8);
15529 if ((*valP
& 0x80000000) != 0)
15533 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15534 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15539 case BFD_RELOC_RVA
:
15541 case BFD_RELOC_32_PCREL
:
15544 /* If we are deleting this reloc entry, we must fill in the
15545 value now. This can happen if we have a .word which is not
15546 resolved when it appears but is later defined. */
15548 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15551 case BFD_RELOC_MIPS_21_PCREL_S2
:
15552 fix_validate_branch (fixP
, *valP
);
15553 if (!fixP
->fx_done
)
15556 if (*valP
+ 0x400000 <= 0x7fffff)
15558 insn
= read_insn (buf
);
15559 insn
|= (*valP
>> 2) & 0x1fffff;
15560 write_insn (buf
, insn
);
15563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15564 _("branch out of range"));
15567 case BFD_RELOC_MIPS_26_PCREL_S2
:
15568 fix_validate_branch (fixP
, *valP
);
15569 if (!fixP
->fx_done
)
15572 if (*valP
+ 0x8000000 <= 0xfffffff)
15574 insn
= read_insn (buf
);
15575 insn
|= (*valP
>> 2) & 0x3ffffff;
15576 write_insn (buf
, insn
);
15579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15580 _("branch out of range"));
15583 case BFD_RELOC_MIPS_18_PCREL_S3
:
15584 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15585 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15586 _("PC-relative access using misaligned symbol (%lx)"),
15587 (long) S_GET_VALUE (fixP
->fx_addsy
));
15588 if ((fixP
->fx_offset
& 0x7) != 0)
15589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15590 _("PC-relative access using misaligned offset (%lx)"),
15591 (long) fixP
->fx_offset
);
15592 if (!fixP
->fx_done
)
15595 if (*valP
+ 0x100000 <= 0x1fffff)
15597 insn
= read_insn (buf
);
15598 insn
|= (*valP
>> 3) & 0x3ffff;
15599 write_insn (buf
, insn
);
15602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15603 _("PC-relative access out of range"));
15606 case BFD_RELOC_MIPS_19_PCREL_S2
:
15607 if ((*valP
& 0x3) != 0)
15608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15609 _("PC-relative access to misaligned address (%lx)"),
15611 if (!fixP
->fx_done
)
15614 if (*valP
+ 0x100000 <= 0x1fffff)
15616 insn
= read_insn (buf
);
15617 insn
|= (*valP
>> 2) & 0x7ffff;
15618 write_insn (buf
, insn
);
15621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15622 _("PC-relative access out of range"));
15625 case BFD_RELOC_16_PCREL_S2
:
15626 fix_validate_branch (fixP
, *valP
);
15628 /* We need to save the bits in the instruction since fixup_segment()
15629 might be deleting the relocation entry (i.e., a branch within
15630 the current segment). */
15631 if (! fixP
->fx_done
)
15634 /* Update old instruction data. */
15635 insn
= read_insn (buf
);
15637 if (*valP
+ 0x20000 <= 0x3ffff)
15639 insn
|= (*valP
>> 2) & 0xffff;
15640 write_insn (buf
, insn
);
15642 else if (fixP
->fx_tcbit2
15644 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15645 && (fixP
->fx_frag
->fr_address
15646 < text_section
->vma
+ bfd_get_section_size (text_section
))
15647 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15648 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15649 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15651 /* The branch offset is too large. If this is an
15652 unconditional branch, and we are not generating PIC code,
15653 we can convert it to an absolute jump instruction. */
15654 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15655 insn
= 0x0c000000; /* jal */
15657 insn
= 0x08000000; /* j */
15658 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15660 fixP
->fx_addsy
= section_symbol (text_section
);
15661 *valP
+= md_pcrel_from (fixP
);
15662 write_insn (buf
, insn
);
15666 /* If we got here, we have branch-relaxation disabled,
15667 and there's nothing we can do to fix this instruction
15668 without turning it into a longer sequence. */
15669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15670 _("branch out of range"));
15674 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15675 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15676 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15677 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15678 gas_assert (!fixP
->fx_done
);
15679 if (fix_bad_cross_mode_branch_p (fixP
))
15680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15681 _("branch to a symbol in another ISA mode"));
15682 else if (fixP
->fx_addsy
15683 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15684 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15685 && (fixP
->fx_offset
& 0x1) != 0)
15686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15687 _("branch to misaligned address (0x%lx)"),
15688 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15689 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15691 _("cannot encode misaligned addend "
15692 "in the relocatable field (0x%lx)"),
15693 (long) fixP
->fx_offset
);
15696 case BFD_RELOC_VTABLE_INHERIT
:
15699 && !S_IS_DEFINED (fixP
->fx_addsy
)
15700 && !S_IS_WEAK (fixP
->fx_addsy
))
15701 S_SET_WEAK (fixP
->fx_addsy
);
15704 case BFD_RELOC_NONE
:
15705 case BFD_RELOC_VTABLE_ENTRY
:
15713 /* Remember value for tc_gen_reloc. */
15714 fixP
->fx_addnumber
= *valP
;
15724 c
= get_symbol_name (&name
);
15725 p
= (symbolS
*) symbol_find_or_make (name
);
15726 (void) restore_line_pointer (c
);
15730 /* Align the current frag to a given power of two. If a particular
15731 fill byte should be used, FILL points to an integer that contains
15732 that byte, otherwise FILL is null.
15734 This function used to have the comment:
15736 The MIPS assembler also automatically adjusts any preceding label.
15738 The implementation therefore applied the adjustment to a maximum of
15739 one label. However, other label adjustments are applied to batches
15740 of labels, and adjusting just one caused problems when new labels
15741 were added for the sake of debugging or unwind information.
15742 We therefore adjust all preceding labels (given as LABELS) instead. */
15745 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15747 mips_emit_delays ();
15748 mips_record_compressed_mode ();
15749 if (fill
== NULL
&& subseg_text_p (now_seg
))
15750 frag_align_code (to
, 0);
15752 frag_align (to
, fill
? *fill
: 0, 0);
15753 record_alignment (now_seg
, to
);
15754 mips_move_labels (labels
, FALSE
);
15757 /* Align to a given power of two. .align 0 turns off the automatic
15758 alignment used by the data creating pseudo-ops. */
15761 s_align (int x ATTRIBUTE_UNUSED
)
15763 int temp
, fill_value
, *fill_ptr
;
15764 long max_alignment
= 28;
15766 /* o Note that the assembler pulls down any immediately preceding label
15767 to the aligned address.
15768 o It's not documented but auto alignment is reinstated by
15769 a .align pseudo instruction.
15770 o Note also that after auto alignment is turned off the mips assembler
15771 issues an error on attempt to assemble an improperly aligned data item.
15774 temp
= get_absolute_expression ();
15775 if (temp
> max_alignment
)
15776 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15779 as_warn (_("alignment negative, 0 assumed"));
15782 if (*input_line_pointer
== ',')
15784 ++input_line_pointer
;
15785 fill_value
= get_absolute_expression ();
15786 fill_ptr
= &fill_value
;
15792 segment_info_type
*si
= seg_info (now_seg
);
15793 struct insn_label_list
*l
= si
->label_list
;
15794 /* Auto alignment should be switched on by next section change. */
15796 mips_align (temp
, fill_ptr
, l
);
15803 demand_empty_rest_of_line ();
15807 s_change_sec (int sec
)
15811 /* The ELF backend needs to know that we are changing sections, so
15812 that .previous works correctly. We could do something like check
15813 for an obj_section_change_hook macro, but that might be confusing
15814 as it would not be appropriate to use it in the section changing
15815 functions in read.c, since obj-elf.c intercepts those. FIXME:
15816 This should be cleaner, somehow. */
15817 obj_elf_section_change_hook ();
15819 mips_emit_delays ();
15830 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15831 demand_empty_rest_of_line ();
15835 seg
= subseg_new (RDATA_SECTION_NAME
,
15836 (subsegT
) get_absolute_expression ());
15837 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15838 | SEC_READONLY
| SEC_RELOC
15840 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15841 record_alignment (seg
, 4);
15842 demand_empty_rest_of_line ();
15846 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15847 bfd_set_section_flags (stdoutput
, seg
,
15848 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15849 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15850 record_alignment (seg
, 4);
15851 demand_empty_rest_of_line ();
15855 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15856 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15857 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15858 record_alignment (seg
, 4);
15859 demand_empty_rest_of_line ();
15867 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15870 char *section_name
;
15875 int section_entry_size
;
15876 int section_alignment
;
15878 saved_ilp
= input_line_pointer
;
15879 endc
= get_symbol_name (§ion_name
);
15880 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
15882 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
15884 /* Do we have .section Name<,"flags">? */
15885 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15887 /* Just after name is now '\0'. */
15888 (void) restore_line_pointer (endc
);
15889 input_line_pointer
= saved_ilp
;
15890 obj_elf_section (ignore
);
15894 section_name
= xstrdup (section_name
);
15895 c
= restore_line_pointer (endc
);
15897 input_line_pointer
++;
15899 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15901 section_type
= get_absolute_expression ();
15905 if (*input_line_pointer
++ == ',')
15906 section_flag
= get_absolute_expression ();
15910 if (*input_line_pointer
++ == ',')
15911 section_entry_size
= get_absolute_expression ();
15913 section_entry_size
= 0;
15915 if (*input_line_pointer
++ == ',')
15916 section_alignment
= get_absolute_expression ();
15918 section_alignment
= 0;
15920 /* FIXME: really ignore? */
15921 (void) section_alignment
;
15923 /* When using the generic form of .section (as implemented by obj-elf.c),
15924 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15925 traditionally had to fall back on the more common @progbits instead.
15927 There's nothing really harmful in this, since bfd will correct
15928 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15929 means that, for backwards compatibility, the special_section entries
15930 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15932 Even so, we shouldn't force users of the MIPS .section syntax to
15933 incorrectly label the sections as SHT_PROGBITS. The best compromise
15934 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15935 generic type-checking code. */
15936 if (section_type
== SHT_MIPS_DWARF
)
15937 section_type
= SHT_PROGBITS
;
15939 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
15940 section_entry_size
, 0, 0, 0);
15942 if (now_seg
->name
!= section_name
)
15943 free (section_name
);
15947 mips_enable_auto_align (void)
15953 s_cons (int log_size
)
15955 segment_info_type
*si
= seg_info (now_seg
);
15956 struct insn_label_list
*l
= si
->label_list
;
15958 mips_emit_delays ();
15959 if (log_size
> 0 && auto_align
)
15960 mips_align (log_size
, 0, l
);
15961 cons (1 << log_size
);
15962 mips_clear_insn_labels ();
15966 s_float_cons (int type
)
15968 segment_info_type
*si
= seg_info (now_seg
);
15969 struct insn_label_list
*l
= si
->label_list
;
15971 mips_emit_delays ();
15976 mips_align (3, 0, l
);
15978 mips_align (2, 0, l
);
15982 mips_clear_insn_labels ();
15985 /* Handle .globl. We need to override it because on Irix 5 you are
15988 where foo is an undefined symbol, to mean that foo should be
15989 considered to be the address of a function. */
15992 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16001 c
= get_symbol_name (&name
);
16002 symbolP
= symbol_find_or_make (name
);
16003 S_SET_EXTERNAL (symbolP
);
16005 *input_line_pointer
= c
;
16006 SKIP_WHITESPACE_AFTER_NAME ();
16008 /* On Irix 5, every global symbol that is not explicitly labelled as
16009 being a function is apparently labelled as being an object. */
16012 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16013 && (*input_line_pointer
!= ','))
16018 c
= get_symbol_name (&secname
);
16019 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16021 as_bad (_("%s: no such section"), secname
);
16022 (void) restore_line_pointer (c
);
16024 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16025 flag
= BSF_FUNCTION
;
16028 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16030 c
= *input_line_pointer
;
16033 input_line_pointer
++;
16034 SKIP_WHITESPACE ();
16035 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16041 demand_empty_rest_of_line ();
16045 s_option (int x ATTRIBUTE_UNUSED
)
16050 c
= get_symbol_name (&opt
);
16054 /* FIXME: What does this mean? */
16056 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16060 i
= atoi (opt
+ 3);
16061 if (i
!= 0 && i
!= 2)
16062 as_bad (_(".option pic%d not supported"), i
);
16063 else if (mips_pic
== VXWORKS_PIC
)
16064 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16069 mips_pic
= SVR4_PIC
;
16070 mips_abicalls
= TRUE
;
16073 if (mips_pic
== SVR4_PIC
)
16075 if (g_switch_seen
&& g_switch_value
!= 0)
16076 as_warn (_("-G may not be used with SVR4 PIC code"));
16077 g_switch_value
= 0;
16078 bfd_set_gp_size (stdoutput
, 0);
16082 as_warn (_("unrecognized option \"%s\""), opt
);
16084 (void) restore_line_pointer (c
);
16085 demand_empty_rest_of_line ();
16088 /* This structure is used to hold a stack of .set values. */
16090 struct mips_option_stack
16092 struct mips_option_stack
*next
;
16093 struct mips_set_options options
;
16096 static struct mips_option_stack
*mips_opts_stack
;
16098 /* Return status for .set/.module option handling. */
16100 enum code_option_type
16102 /* Unrecognized option. */
16103 OPTION_TYPE_BAD
= -1,
16105 /* Ordinary option. */
16106 OPTION_TYPE_NORMAL
,
16108 /* ISA changing option. */
16112 /* Handle common .set/.module options. Return status indicating option
16115 static enum code_option_type
16116 parse_code_option (char * name
)
16118 bfd_boolean isa_set
= FALSE
;
16119 const struct mips_ase
*ase
;
16121 if (strncmp (name
, "at=", 3) == 0)
16123 char *s
= name
+ 3;
16125 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16126 as_bad (_("unrecognized register name `%s'"), s
);
16128 else if (strcmp (name
, "at") == 0)
16129 mips_opts
.at
= ATREG
;
16130 else if (strcmp (name
, "noat") == 0)
16131 mips_opts
.at
= ZERO
;
16132 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16133 mips_opts
.nomove
= 0;
16134 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16135 mips_opts
.nomove
= 1;
16136 else if (strcmp (name
, "bopt") == 0)
16137 mips_opts
.nobopt
= 0;
16138 else if (strcmp (name
, "nobopt") == 0)
16139 mips_opts
.nobopt
= 1;
16140 else if (strcmp (name
, "gp=32") == 0)
16142 else if (strcmp (name
, "gp=64") == 0)
16144 else if (strcmp (name
, "fp=32") == 0)
16146 else if (strcmp (name
, "fp=xx") == 0)
16148 else if (strcmp (name
, "fp=64") == 0)
16150 else if (strcmp (name
, "softfloat") == 0)
16151 mips_opts
.soft_float
= 1;
16152 else if (strcmp (name
, "hardfloat") == 0)
16153 mips_opts
.soft_float
= 0;
16154 else if (strcmp (name
, "singlefloat") == 0)
16155 mips_opts
.single_float
= 1;
16156 else if (strcmp (name
, "doublefloat") == 0)
16157 mips_opts
.single_float
= 0;
16158 else if (strcmp (name
, "nooddspreg") == 0)
16159 mips_opts
.oddspreg
= 0;
16160 else if (strcmp (name
, "oddspreg") == 0)
16161 mips_opts
.oddspreg
= 1;
16162 else if (strcmp (name
, "mips16") == 0
16163 || strcmp (name
, "MIPS-16") == 0)
16164 mips_opts
.mips16
= 1;
16165 else if (strcmp (name
, "nomips16") == 0
16166 || strcmp (name
, "noMIPS-16") == 0)
16167 mips_opts
.mips16
= 0;
16168 else if (strcmp (name
, "micromips") == 0)
16169 mips_opts
.micromips
= 1;
16170 else if (strcmp (name
, "nomicromips") == 0)
16171 mips_opts
.micromips
= 0;
16172 else if (name
[0] == 'n'
16174 && (ase
= mips_lookup_ase (name
+ 2)))
16175 mips_set_ase (ase
, &mips_opts
, FALSE
);
16176 else if ((ase
= mips_lookup_ase (name
)))
16177 mips_set_ase (ase
, &mips_opts
, TRUE
);
16178 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16180 /* Permit the user to change the ISA and architecture on the fly.
16181 Needless to say, misuse can cause serious problems. */
16182 if (strncmp (name
, "arch=", 5) == 0)
16184 const struct mips_cpu_info
*p
;
16186 p
= mips_parse_cpu ("internal use", name
+ 5);
16188 as_bad (_("unknown architecture %s"), name
+ 5);
16191 mips_opts
.arch
= p
->cpu
;
16192 mips_opts
.isa
= p
->isa
;
16196 else if (strncmp (name
, "mips", 4) == 0)
16198 const struct mips_cpu_info
*p
;
16200 p
= mips_parse_cpu ("internal use", name
);
16202 as_bad (_("unknown ISA level %s"), name
+ 4);
16205 mips_opts
.arch
= p
->cpu
;
16206 mips_opts
.isa
= p
->isa
;
16211 as_bad (_("unknown ISA or architecture %s"), name
);
16213 else if (strcmp (name
, "autoextend") == 0)
16214 mips_opts
.noautoextend
= 0;
16215 else if (strcmp (name
, "noautoextend") == 0)
16216 mips_opts
.noautoextend
= 1;
16217 else if (strcmp (name
, "insn32") == 0)
16218 mips_opts
.insn32
= TRUE
;
16219 else if (strcmp (name
, "noinsn32") == 0)
16220 mips_opts
.insn32
= FALSE
;
16221 else if (strcmp (name
, "sym32") == 0)
16222 mips_opts
.sym32
= TRUE
;
16223 else if (strcmp (name
, "nosym32") == 0)
16224 mips_opts
.sym32
= FALSE
;
16226 return OPTION_TYPE_BAD
;
16228 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16231 /* Handle the .set pseudo-op. */
16234 s_mipsset (int x ATTRIBUTE_UNUSED
)
16236 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16237 char *name
= input_line_pointer
, ch
;
16239 file_mips_check_options ();
16241 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16242 ++input_line_pointer
;
16243 ch
= *input_line_pointer
;
16244 *input_line_pointer
= '\0';
16246 if (strchr (name
, ','))
16248 /* Generic ".set" directive; use the generic handler. */
16249 *input_line_pointer
= ch
;
16250 input_line_pointer
= name
;
16255 if (strcmp (name
, "reorder") == 0)
16257 if (mips_opts
.noreorder
)
16260 else if (strcmp (name
, "noreorder") == 0)
16262 if (!mips_opts
.noreorder
)
16263 start_noreorder ();
16265 else if (strcmp (name
, "macro") == 0)
16266 mips_opts
.warn_about_macros
= 0;
16267 else if (strcmp (name
, "nomacro") == 0)
16269 if (mips_opts
.noreorder
== 0)
16270 as_bad (_("`noreorder' must be set before `nomacro'"));
16271 mips_opts
.warn_about_macros
= 1;
16273 else if (strcmp (name
, "gp=default") == 0)
16274 mips_opts
.gp
= file_mips_opts
.gp
;
16275 else if (strcmp (name
, "fp=default") == 0)
16276 mips_opts
.fp
= file_mips_opts
.fp
;
16277 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16279 mips_opts
.isa
= file_mips_opts
.isa
;
16280 mips_opts
.arch
= file_mips_opts
.arch
;
16281 mips_opts
.gp
= file_mips_opts
.gp
;
16282 mips_opts
.fp
= file_mips_opts
.fp
;
16284 else if (strcmp (name
, "push") == 0)
16286 struct mips_option_stack
*s
;
16288 s
= XNEW (struct mips_option_stack
);
16289 s
->next
= mips_opts_stack
;
16290 s
->options
= mips_opts
;
16291 mips_opts_stack
= s
;
16293 else if (strcmp (name
, "pop") == 0)
16295 struct mips_option_stack
*s
;
16297 s
= mips_opts_stack
;
16299 as_bad (_(".set pop with no .set push"));
16302 /* If we're changing the reorder mode we need to handle
16303 delay slots correctly. */
16304 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16305 start_noreorder ();
16306 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16309 mips_opts
= s
->options
;
16310 mips_opts_stack
= s
->next
;
16316 type
= parse_code_option (name
);
16317 if (type
== OPTION_TYPE_BAD
)
16318 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16321 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16322 registers based on what is supported by the arch/cpu. */
16323 if (type
== OPTION_TYPE_ISA
)
16325 switch (mips_opts
.isa
)
16330 /* MIPS I cannot support FPXX. */
16332 /* fall-through. */
16339 if (mips_opts
.fp
!= 0)
16355 if (mips_opts
.fp
!= 0)
16357 if (mips_opts
.arch
== CPU_R5900
)
16364 as_bad (_("unknown ISA level %s"), name
+ 4);
16369 mips_check_options (&mips_opts
, FALSE
);
16371 mips_check_isa_supports_ases ();
16372 *input_line_pointer
= ch
;
16373 demand_empty_rest_of_line ();
16376 /* Handle the .module pseudo-op. */
16379 s_module (int ignore ATTRIBUTE_UNUSED
)
16381 char *name
= input_line_pointer
, ch
;
16383 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16384 ++input_line_pointer
;
16385 ch
= *input_line_pointer
;
16386 *input_line_pointer
= '\0';
16388 if (!file_mips_opts_checked
)
16390 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16391 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16393 /* Update module level settings from mips_opts. */
16394 file_mips_opts
= mips_opts
;
16397 as_bad (_(".module is not permitted after generating code"));
16399 *input_line_pointer
= ch
;
16400 demand_empty_rest_of_line ();
16403 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16404 .option pic2. It means to generate SVR4 PIC calls. */
16407 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16409 mips_pic
= SVR4_PIC
;
16410 mips_abicalls
= TRUE
;
16412 if (g_switch_seen
&& g_switch_value
!= 0)
16413 as_warn (_("-G may not be used with SVR4 PIC code"));
16414 g_switch_value
= 0;
16416 bfd_set_gp_size (stdoutput
, 0);
16417 demand_empty_rest_of_line ();
16420 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16421 PIC code. It sets the $gp register for the function based on the
16422 function address, which is in the register named in the argument.
16423 This uses a relocation against _gp_disp, which is handled specially
16424 by the linker. The result is:
16425 lui $gp,%hi(_gp_disp)
16426 addiu $gp,$gp,%lo(_gp_disp)
16427 addu $gp,$gp,.cpload argument
16428 The .cpload argument is normally $25 == $t9.
16430 The -mno-shared option changes this to:
16431 lui $gp,%hi(__gnu_local_gp)
16432 addiu $gp,$gp,%lo(__gnu_local_gp)
16433 and the argument is ignored. This saves an instruction, but the
16434 resulting code is not position independent; it uses an absolute
16435 address for __gnu_local_gp. Thus code assembled with -mno-shared
16436 can go into an ordinary executable, but not into a shared library. */
16439 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16445 file_mips_check_options ();
16447 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16448 .cpload is ignored. */
16449 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16455 if (mips_opts
.mips16
)
16457 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16458 ignore_rest_of_line ();
16462 /* .cpload should be in a .set noreorder section. */
16463 if (mips_opts
.noreorder
== 0)
16464 as_warn (_(".cpload not in noreorder section"));
16466 reg
= tc_get_register (0);
16468 /* If we need to produce a 64-bit address, we are better off using
16469 the default instruction sequence. */
16470 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16472 ex
.X_op
= O_symbol
;
16473 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16475 ex
.X_op_symbol
= NULL
;
16476 ex
.X_add_number
= 0;
16478 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16479 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16481 mips_mark_labels ();
16482 mips_assembling_insn
= TRUE
;
16485 macro_build_lui (&ex
, mips_gp_register
);
16486 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16487 mips_gp_register
, BFD_RELOC_LO16
);
16489 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16490 mips_gp_register
, reg
);
16493 mips_assembling_insn
= FALSE
;
16494 demand_empty_rest_of_line ();
16497 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16498 .cpsetup $reg1, offset|$reg2, label
16500 If offset is given, this results in:
16501 sd $gp, offset($sp)
16502 lui $gp, %hi(%neg(%gp_rel(label)))
16503 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16504 daddu $gp, $gp, $reg1
16506 If $reg2 is given, this results in:
16508 lui $gp, %hi(%neg(%gp_rel(label)))
16509 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16510 daddu $gp, $gp, $reg1
16511 $reg1 is normally $25 == $t9.
16513 The -mno-shared option replaces the last three instructions with
16515 addiu $gp,$gp,%lo(_gp) */
16518 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16520 expressionS ex_off
;
16521 expressionS ex_sym
;
16524 file_mips_check_options ();
16526 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16527 We also need NewABI support. */
16528 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16534 if (mips_opts
.mips16
)
16536 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16537 ignore_rest_of_line ();
16541 reg1
= tc_get_register (0);
16542 SKIP_WHITESPACE ();
16543 if (*input_line_pointer
!= ',')
16545 as_bad (_("missing argument separator ',' for .cpsetup"));
16549 ++input_line_pointer
;
16550 SKIP_WHITESPACE ();
16551 if (*input_line_pointer
== '$')
16553 mips_cpreturn_register
= tc_get_register (0);
16554 mips_cpreturn_offset
= -1;
16558 mips_cpreturn_offset
= get_absolute_expression ();
16559 mips_cpreturn_register
= -1;
16561 SKIP_WHITESPACE ();
16562 if (*input_line_pointer
!= ',')
16564 as_bad (_("missing argument separator ',' for .cpsetup"));
16568 ++input_line_pointer
;
16569 SKIP_WHITESPACE ();
16570 expression (&ex_sym
);
16572 mips_mark_labels ();
16573 mips_assembling_insn
= TRUE
;
16576 if (mips_cpreturn_register
== -1)
16578 ex_off
.X_op
= O_constant
;
16579 ex_off
.X_add_symbol
= NULL
;
16580 ex_off
.X_op_symbol
= NULL
;
16581 ex_off
.X_add_number
= mips_cpreturn_offset
;
16583 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16584 BFD_RELOC_LO16
, SP
);
16587 move_register (mips_cpreturn_register
, mips_gp_register
);
16589 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16591 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16592 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16595 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16596 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16597 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16599 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16600 mips_gp_register
, reg1
);
16606 ex
.X_op
= O_symbol
;
16607 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16608 ex
.X_op_symbol
= NULL
;
16609 ex
.X_add_number
= 0;
16611 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16612 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16614 macro_build_lui (&ex
, mips_gp_register
);
16615 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16616 mips_gp_register
, BFD_RELOC_LO16
);
16621 mips_assembling_insn
= FALSE
;
16622 demand_empty_rest_of_line ();
16626 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16628 file_mips_check_options ();
16630 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16631 .cplocal is ignored. */
16632 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16638 if (mips_opts
.mips16
)
16640 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16641 ignore_rest_of_line ();
16645 mips_gp_register
= tc_get_register (0);
16646 demand_empty_rest_of_line ();
16649 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16650 offset from $sp. The offset is remembered, and after making a PIC
16651 call $gp is restored from that location. */
16654 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16658 file_mips_check_options ();
16660 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16661 .cprestore is ignored. */
16662 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16668 if (mips_opts
.mips16
)
16670 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16671 ignore_rest_of_line ();
16675 mips_cprestore_offset
= get_absolute_expression ();
16676 mips_cprestore_valid
= 1;
16678 ex
.X_op
= O_constant
;
16679 ex
.X_add_symbol
= NULL
;
16680 ex
.X_op_symbol
= NULL
;
16681 ex
.X_add_number
= mips_cprestore_offset
;
16683 mips_mark_labels ();
16684 mips_assembling_insn
= TRUE
;
16687 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16688 SP
, HAVE_64BIT_ADDRESSES
);
16691 mips_assembling_insn
= FALSE
;
16692 demand_empty_rest_of_line ();
16695 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16696 was given in the preceding .cpsetup, it results in:
16697 ld $gp, offset($sp)
16699 If a register $reg2 was given there, it results in:
16700 or $gp, $reg2, $0 */
16703 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16707 file_mips_check_options ();
16709 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16710 We also need NewABI support. */
16711 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16717 if (mips_opts
.mips16
)
16719 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16720 ignore_rest_of_line ();
16724 mips_mark_labels ();
16725 mips_assembling_insn
= TRUE
;
16728 if (mips_cpreturn_register
== -1)
16730 ex
.X_op
= O_constant
;
16731 ex
.X_add_symbol
= NULL
;
16732 ex
.X_op_symbol
= NULL
;
16733 ex
.X_add_number
= mips_cpreturn_offset
;
16735 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16738 move_register (mips_gp_register
, mips_cpreturn_register
);
16742 mips_assembling_insn
= FALSE
;
16743 demand_empty_rest_of_line ();
16746 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16747 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16748 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16749 debug information or MIPS16 TLS. */
16752 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16753 bfd_reloc_code_real_type rtype
)
16760 if (ex
.X_op
!= O_symbol
)
16762 as_bad (_("unsupported use of %s"), dirstr
);
16763 ignore_rest_of_line ();
16766 p
= frag_more (bytes
);
16767 md_number_to_chars (p
, 0, bytes
);
16768 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16769 demand_empty_rest_of_line ();
16770 mips_clear_insn_labels ();
16773 /* Handle .dtprelword. */
16776 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16778 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16781 /* Handle .dtpreldword. */
16784 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16786 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16789 /* Handle .tprelword. */
16792 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16794 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16797 /* Handle .tpreldword. */
16800 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16802 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16805 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16806 code. It sets the offset to use in gp_rel relocations. */
16809 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16811 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16812 We also need NewABI support. */
16813 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16819 mips_gprel_offset
= get_absolute_expression ();
16821 demand_empty_rest_of_line ();
16824 /* Handle the .gpword pseudo-op. This is used when generating PIC
16825 code. It generates a 32 bit GP relative reloc. */
16828 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16830 segment_info_type
*si
;
16831 struct insn_label_list
*l
;
16835 /* When not generating PIC code, this is treated as .word. */
16836 if (mips_pic
!= SVR4_PIC
)
16842 si
= seg_info (now_seg
);
16843 l
= si
->label_list
;
16844 mips_emit_delays ();
16846 mips_align (2, 0, l
);
16849 mips_clear_insn_labels ();
16851 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16853 as_bad (_("unsupported use of .gpword"));
16854 ignore_rest_of_line ();
16858 md_number_to_chars (p
, 0, 4);
16859 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16860 BFD_RELOC_GPREL32
);
16862 demand_empty_rest_of_line ();
16866 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16868 segment_info_type
*si
;
16869 struct insn_label_list
*l
;
16873 /* When not generating PIC code, this is treated as .dword. */
16874 if (mips_pic
!= SVR4_PIC
)
16880 si
= seg_info (now_seg
);
16881 l
= si
->label_list
;
16882 mips_emit_delays ();
16884 mips_align (3, 0, l
);
16887 mips_clear_insn_labels ();
16889 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16891 as_bad (_("unsupported use of .gpdword"));
16892 ignore_rest_of_line ();
16896 md_number_to_chars (p
, 0, 8);
16897 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16898 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16900 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16901 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16902 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16904 demand_empty_rest_of_line ();
16907 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16908 tables. It generates a R_MIPS_EH reloc. */
16911 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16916 mips_emit_delays ();
16919 mips_clear_insn_labels ();
16921 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16923 as_bad (_("unsupported use of .ehword"));
16924 ignore_rest_of_line ();
16928 md_number_to_chars (p
, 0, 4);
16929 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16930 BFD_RELOC_32_PCREL
);
16932 demand_empty_rest_of_line ();
16935 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16936 tables in SVR4 PIC code. */
16939 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16943 file_mips_check_options ();
16945 /* This is ignored when not generating SVR4 PIC code. */
16946 if (mips_pic
!= SVR4_PIC
)
16952 mips_mark_labels ();
16953 mips_assembling_insn
= TRUE
;
16955 /* Add $gp to the register named as an argument. */
16957 reg
= tc_get_register (0);
16958 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16961 mips_assembling_insn
= FALSE
;
16962 demand_empty_rest_of_line ();
16965 /* Handle the .insn pseudo-op. This marks instruction labels in
16966 mips16/micromips mode. This permits the linker to handle them specially,
16967 such as generating jalx instructions when needed. We also make
16968 them odd for the duration of the assembly, in order to generate the
16969 right sort of code. We will make them even in the adjust_symtab
16970 routine, while leaving them marked. This is convenient for the
16971 debugger and the disassembler. The linker knows to make them odd
16975 s_insn (int ignore ATTRIBUTE_UNUSED
)
16977 file_mips_check_options ();
16978 file_ase_mips16
|= mips_opts
.mips16
;
16979 file_ase_micromips
|= mips_opts
.micromips
;
16981 mips_mark_labels ();
16983 demand_empty_rest_of_line ();
16986 /* Handle the .nan pseudo-op. */
16989 s_nan (int ignore ATTRIBUTE_UNUSED
)
16991 static const char str_legacy
[] = "legacy";
16992 static const char str_2008
[] = "2008";
16995 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16997 if (i
== sizeof (str_2008
) - 1
16998 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17000 else if (i
== sizeof (str_legacy
) - 1
17001 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17003 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17006 as_bad (_("`%s' does not support legacy NaN"),
17007 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17010 as_bad (_("bad .nan directive"));
17012 input_line_pointer
+= i
;
17013 demand_empty_rest_of_line ();
17016 /* Handle a .stab[snd] directive. Ideally these directives would be
17017 implemented in a transparent way, so that removing them would not
17018 have any effect on the generated instructions. However, s_stab
17019 internally changes the section, so in practice we need to decide
17020 now whether the preceding label marks compressed code. We do not
17021 support changing the compression mode of a label after a .stab*
17022 directive, such as in:
17028 so the current mode wins. */
17031 s_mips_stab (int type
)
17033 mips_mark_labels ();
17037 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17040 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17047 c
= get_symbol_name (&name
);
17048 symbolP
= symbol_find_or_make (name
);
17049 S_SET_WEAK (symbolP
);
17050 *input_line_pointer
= c
;
17052 SKIP_WHITESPACE_AFTER_NAME ();
17054 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17056 if (S_IS_DEFINED (symbolP
))
17058 as_bad (_("ignoring attempt to redefine symbol %s"),
17059 S_GET_NAME (symbolP
));
17060 ignore_rest_of_line ();
17064 if (*input_line_pointer
== ',')
17066 ++input_line_pointer
;
17067 SKIP_WHITESPACE ();
17071 if (exp
.X_op
!= O_symbol
)
17073 as_bad (_("bad .weakext directive"));
17074 ignore_rest_of_line ();
17077 symbol_set_value_expression (symbolP
, &exp
);
17080 demand_empty_rest_of_line ();
17083 /* Parse a register string into a number. Called from the ECOFF code
17084 to parse .frame. The argument is non-zero if this is the frame
17085 register, so that we can record it in mips_frame_reg. */
17088 tc_get_register (int frame
)
17092 SKIP_WHITESPACE ();
17093 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17097 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17098 mips_frame_reg_valid
= 1;
17099 mips_cprestore_valid
= 0;
17105 md_section_align (asection
*seg
, valueT addr
)
17107 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17109 /* We don't need to align ELF sections to the full alignment.
17110 However, Irix 5 may prefer that we align them at least to a 16
17111 byte boundary. We don't bother to align the sections if we
17112 are targeted for an embedded system. */
17113 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17118 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17121 /* Utility routine, called from above as well. If called while the
17122 input file is still being read, it's only an approximation. (For
17123 example, a symbol may later become defined which appeared to be
17124 undefined earlier.) */
17127 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17132 if (g_switch_value
> 0)
17134 const char *symname
;
17137 /* Find out whether this symbol can be referenced off the $gp
17138 register. It can be if it is smaller than the -G size or if
17139 it is in the .sdata or .sbss section. Certain symbols can
17140 not be referenced off the $gp, although it appears as though
17142 symname
= S_GET_NAME (sym
);
17143 if (symname
!= (const char *) NULL
17144 && (strcmp (symname
, "eprol") == 0
17145 || strcmp (symname
, "etext") == 0
17146 || strcmp (symname
, "_gp") == 0
17147 || strcmp (symname
, "edata") == 0
17148 || strcmp (symname
, "_fbss") == 0
17149 || strcmp (symname
, "_fdata") == 0
17150 || strcmp (symname
, "_ftext") == 0
17151 || strcmp (symname
, "end") == 0
17152 || strcmp (symname
, "_gp_disp") == 0))
17154 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17156 #ifndef NO_ECOFF_DEBUGGING
17157 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17158 && (symbol_get_obj (sym
)->ecoff_extern_size
17159 <= g_switch_value
))
17161 /* We must defer this decision until after the whole
17162 file has been read, since there might be a .extern
17163 after the first use of this symbol. */
17164 || (before_relaxing
17165 #ifndef NO_ECOFF_DEBUGGING
17166 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17168 && S_GET_VALUE (sym
) == 0)
17169 || (S_GET_VALUE (sym
) != 0
17170 && S_GET_VALUE (sym
) <= g_switch_value
)))
17174 const char *segname
;
17176 segname
= segment_name (S_GET_SEGMENT (sym
));
17177 gas_assert (strcmp (segname
, ".lit8") != 0
17178 && strcmp (segname
, ".lit4") != 0);
17179 change
= (strcmp (segname
, ".sdata") != 0
17180 && strcmp (segname
, ".sbss") != 0
17181 && strncmp (segname
, ".sdata.", 7) != 0
17182 && strncmp (segname
, ".sbss.", 6) != 0
17183 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17184 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17189 /* We are not optimizing for the $gp register. */
17194 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17197 pic_need_relax (symbolS
*sym
)
17201 /* Handle the case of a symbol equated to another symbol. */
17202 while (symbol_equated_reloc_p (sym
))
17206 /* It's possible to get a loop here in a badly written program. */
17207 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17213 if (symbol_section_p (sym
))
17216 symsec
= S_GET_SEGMENT (sym
);
17218 /* This must duplicate the test in adjust_reloc_syms. */
17219 return (!bfd_is_und_section (symsec
)
17220 && !bfd_is_abs_section (symsec
)
17221 && !bfd_is_com_section (symsec
)
17222 /* A global or weak symbol is treated as external. */
17223 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17226 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17227 convert a section-relative value VAL to the equivalent PC-relative
17231 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17232 offsetT val
, long stretch
)
17237 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17239 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17241 /* If the relax_marker of the symbol fragment differs from the
17242 relax_marker of this fragment, we have not yet adjusted the
17243 symbol fragment fr_address. We want to add in STRETCH in
17244 order to get a better estimate of the address. This
17245 particularly matters because of the shift bits. */
17246 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17250 /* Adjust stretch for any alignment frag. Note that if have
17251 been expanding the earlier code, the symbol may be
17252 defined in what appears to be an earlier frag. FIXME:
17253 This doesn't handle the fr_subtype field, which specifies
17254 a maximum number of bytes to skip when doing an
17256 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17258 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17261 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17263 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17272 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17274 /* The base address rules are complicated. The base address of
17275 a branch is the following instruction. The base address of a
17276 PC relative load or add is the instruction itself, but if it
17277 is in a delay slot (in which case it can not be extended) use
17278 the address of the instruction whose delay slot it is in. */
17279 if (pcrel_op
->include_isa_bit
)
17283 /* If we are currently assuming that this frag should be
17284 extended, then the current address is two bytes higher. */
17285 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17288 /* Ignore the low bit in the target, since it will be set
17289 for a text label. */
17292 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17294 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17297 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17302 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17303 extended opcode. SEC is the section the frag is in. */
17306 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17308 const struct mips_int_operand
*operand
;
17313 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17315 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17318 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17319 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17320 operand
= mips16_immed_operand (type
, FALSE
);
17321 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17322 || (operand
->root
.type
== OP_PCREL
17324 : !bfd_is_abs_section (symsec
)))
17327 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17329 if (operand
->root
.type
== OP_PCREL
)
17331 const struct mips_pcrel_operand
*pcrel_op
;
17334 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17337 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17338 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17340 /* If any of the shifted bits are set, we must use an extended
17341 opcode. If the address depends on the size of this
17342 instruction, this can lead to a loop, so we arrange to always
17343 use an extended opcode. */
17344 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17346 fragp
->fr_subtype
=
17347 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17351 /* If we are about to mark a frag as extended because the value
17352 is precisely the next value above maxtiny, then there is a
17353 chance of an infinite loop as in the following code:
17358 In this case when the la is extended, foo is 0x3fc bytes
17359 away, so the la can be shrunk, but then foo is 0x400 away, so
17360 the la must be extended. To avoid this loop, we mark the
17361 frag as extended if it was small, and is about to become
17362 extended with the next value above maxtiny. */
17363 maxtiny
= mips_int_operand_max (operand
);
17364 if (val
== maxtiny
+ (1 << operand
->shift
)
17365 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17367 fragp
->fr_subtype
=
17368 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17373 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17376 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17377 macro expansion. SEC is the section the frag is in. We only
17378 support PC-relative instructions (LA, DLA, LW, LD) here, in
17379 non-PIC code using 32-bit addressing. */
17382 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17384 const struct mips_pcrel_operand
*pcrel_op
;
17385 const struct mips_int_operand
*operand
;
17390 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17392 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17394 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17397 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17403 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17404 if (bfd_is_abs_section (symsec
))
17406 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17408 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17411 operand
= mips16_immed_operand (type
, TRUE
);
17412 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17413 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17414 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17416 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17423 /* Compute the length of a branch sequence, and adjust the
17424 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17425 worst-case length is computed, with UPDATE being used to indicate
17426 whether an unconditional (-1), branch-likely (+1) or regular (0)
17427 branch is to be computed. */
17429 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17431 bfd_boolean toofar
;
17435 && S_IS_DEFINED (fragp
->fr_symbol
)
17436 && !S_IS_WEAK (fragp
->fr_symbol
)
17437 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17442 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17444 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17448 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17451 /* If the symbol is not defined or it's in a different segment,
17452 we emit the long sequence. */
17455 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17457 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17458 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17459 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17460 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17461 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17467 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17470 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17472 /* Additional space for PIC loading of target address. */
17474 if (mips_opts
.isa
== ISA_MIPS1
)
17475 /* Additional space for $at-stabilizing nop. */
17479 /* If branch is conditional. */
17480 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17487 /* Get a FRAG's branch instruction delay slot size, either from the
17488 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17489 or SHORT_INSN_SIZE otherwise. */
17492 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17494 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17497 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17499 return short_insn_size
;
17502 /* Compute the length of a branch sequence, and adjust the
17503 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17504 worst-case length is computed, with UPDATE being used to indicate
17505 whether an unconditional (-1), or regular (0) branch is to be
17509 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17511 bfd_boolean insn32
= TRUE
;
17512 bfd_boolean nods
= TRUE
;
17513 bfd_boolean pic
= TRUE
;
17514 bfd_boolean al
= TRUE
;
17515 int short_insn_size
;
17516 bfd_boolean toofar
;
17521 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17522 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17523 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17524 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17526 short_insn_size
= insn32
? 4 : 2;
17529 && S_IS_DEFINED (fragp
->fr_symbol
)
17530 && !S_IS_WEAK (fragp
->fr_symbol
)
17531 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17536 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17537 /* Ignore the low bit in the target, since it will be set
17538 for a text label. */
17539 if ((val
& 1) != 0)
17542 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17546 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17549 /* If the symbol is not defined or it's in a different segment,
17550 we emit the long sequence. */
17553 if (fragp
&& update
17554 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17555 fragp
->fr_subtype
= (toofar
17556 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17557 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17562 bfd_boolean compact_known
= fragp
!= NULL
;
17563 bfd_boolean compact
= FALSE
;
17564 bfd_boolean uncond
;
17568 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17569 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17572 uncond
= update
< 0;
17574 /* If label is out of range, we turn branch <br>:
17576 <br> label # 4 bytes
17583 # compact && (!PIC || insn32)
17586 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17587 length
+= short_insn_size
;
17589 /* If assembling PIC code, we further turn:
17595 lw/ld at, %got(label)(gp) # 4 bytes
17596 d/addiu at, %lo(label) # 4 bytes
17597 jr/c at # 2/4 bytes
17600 length
+= 4 + short_insn_size
;
17602 /* Add an extra nop if the jump has no compact form and we need
17603 to fill the delay slot. */
17604 if ((!pic
|| al
) && nods
)
17606 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17607 : short_insn_size
);
17609 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17611 <brneg> 0f # 4 bytes
17612 nop # 2/4 bytes if !compact
17615 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17619 /* Add an extra nop to fill the delay slot. */
17620 gas_assert (fragp
);
17621 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17627 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17628 bit accordingly. */
17631 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17633 bfd_boolean toofar
;
17636 && S_IS_DEFINED (fragp
->fr_symbol
)
17637 && !S_IS_WEAK (fragp
->fr_symbol
)
17638 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17644 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17645 /* Ignore the low bit in the target, since it will be set
17646 for a text label. */
17647 if ((val
& 1) != 0)
17650 /* Assume this is a 2-byte branch. */
17651 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17653 /* We try to avoid the infinite loop by not adding 2 more bytes for
17658 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17660 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17661 else if (type
== 'E')
17662 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17667 /* If the symbol is not defined or it's in a different segment,
17668 we emit a normal 32-bit branch. */
17671 if (fragp
&& update
17672 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17674 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17675 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17683 /* Estimate the size of a frag before relaxing. Unless this is the
17684 mips16, we are not really relaxing here, and the final size is
17685 encoded in the subtype information. For the mips16, we have to
17686 decide whether we are using an extended opcode or not. */
17689 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17693 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17696 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17698 return fragp
->fr_var
;
17701 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17703 /* We don't want to modify the EXTENDED bit here; it might get us
17704 into infinite loops. We change it only in mips_relax_frag(). */
17705 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17708 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17711 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17715 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17716 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17717 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17718 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17719 fragp
->fr_var
= length
;
17724 if (mips_pic
== VXWORKS_PIC
)
17725 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17727 else if (RELAX_PIC (fragp
->fr_subtype
))
17728 change
= pic_need_relax (fragp
->fr_symbol
);
17730 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17734 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17735 return -RELAX_FIRST (fragp
->fr_subtype
);
17738 return -RELAX_SECOND (fragp
->fr_subtype
);
17741 /* This is called to see whether a reloc against a defined symbol
17742 should be converted into a reloc against a section. */
17745 mips_fix_adjustable (fixS
*fixp
)
17747 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17748 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17751 if (fixp
->fx_addsy
== NULL
)
17754 /* Allow relocs used for EH tables. */
17755 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17758 /* If symbol SYM is in a mergeable section, relocations of the form
17759 SYM + 0 can usually be made section-relative. The mergeable data
17760 is then identified by the section offset rather than by the symbol.
17762 However, if we're generating REL LO16 relocations, the offset is split
17763 between the LO16 and partnering high part relocation. The linker will
17764 need to recalculate the complete offset in order to correctly identify
17767 The linker has traditionally not looked for the partnering high part
17768 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17769 placed anywhere. Rather than break backwards compatibility by changing
17770 this, it seems better not to force the issue, and instead keep the
17771 original symbol. This will work with either linker behavior. */
17772 if ((lo16_reloc_p (fixp
->fx_r_type
)
17773 || reloc_needs_lo_p (fixp
->fx_r_type
))
17774 && HAVE_IN_PLACE_ADDENDS
17775 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17778 /* There is no place to store an in-place offset for JALR relocations. */
17779 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17782 /* Likewise an in-range offset of limited PC-relative relocations may
17783 overflow the in-place relocatable field if recalculated against the
17784 start address of the symbol's containing section.
17786 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17787 section relative to allow linker relaxations to be performed later on. */
17788 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17789 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17792 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17793 to a floating-point stub. The same is true for non-R_MIPS16_26
17794 relocations against MIPS16 functions; in this case, the stub becomes
17795 the function's canonical address.
17797 Floating-point stubs are stored in unique .mips16.call.* or
17798 .mips16.fn.* sections. If a stub T for function F is in section S,
17799 the first relocation in section S must be against F; this is how the
17800 linker determines the target function. All relocations that might
17801 resolve to T must also be against F. We therefore have the following
17802 restrictions, which are given in an intentionally-redundant way:
17804 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17807 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17808 if that stub might be used.
17810 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17813 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17814 that stub might be used.
17816 There is a further restriction:
17818 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17819 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17820 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17821 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17822 against MIPS16 or microMIPS symbols because we need to keep the
17823 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17824 detection and JAL or BAL to JALX instruction conversion in the
17827 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17828 against a MIPS16 symbol. We deal with (5) by additionally leaving
17829 alone any jump and branch relocations against a microMIPS symbol.
17831 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17832 relocation against some symbol R, no relocation against R may be
17833 reduced. (Note that this deals with (2) as well as (1) because
17834 relocations against global symbols will never be reduced on ELF
17835 targets.) This approach is a little simpler than trying to detect
17836 stub sections, and gives the "all or nothing" per-symbol consistency
17837 that we have for MIPS16 symbols. */
17838 if (fixp
->fx_subsy
== NULL
17839 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17840 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17841 && (jmp_reloc_p (fixp
->fx_r_type
)
17842 || b_reloc_p (fixp
->fx_r_type
)))
17843 || *symbol_get_tc (fixp
->fx_addsy
)))
17849 /* Translate internal representation of relocation info to BFD target
17853 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17855 static arelent
*retval
[4];
17857 bfd_reloc_code_real_type code
;
17859 memset (retval
, 0, sizeof(retval
));
17860 reloc
= retval
[0] = XCNEW (arelent
);
17861 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
17862 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17863 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17865 if (fixp
->fx_pcrel
)
17867 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17868 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
17869 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17870 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17871 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17872 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17873 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17874 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17875 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17876 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17877 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17878 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17880 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17881 Relocations want only the symbol offset. */
17882 switch (fixp
->fx_r_type
)
17884 case BFD_RELOC_MIPS_18_PCREL_S3
:
17885 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
17888 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17892 else if (HAVE_IN_PLACE_ADDENDS
17893 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
17894 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
17895 + fixp
->fx_where
, 4) >> 26) == 0x3c)
17897 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17898 addend accordingly. */
17899 reloc
->addend
= fixp
->fx_addnumber
>> 1;
17902 reloc
->addend
= fixp
->fx_addnumber
;
17904 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17905 entry to be used in the relocation's section offset. */
17906 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17908 reloc
->address
= reloc
->addend
;
17912 code
= fixp
->fx_r_type
;
17914 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17915 if (reloc
->howto
== NULL
)
17917 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17918 _("cannot represent %s relocation in this object file"
17920 bfd_get_reloc_code_name (code
));
17927 /* Relax a machine dependent frag. This returns the amount by which
17928 the current size of the frag should change. */
17931 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17933 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17935 offsetT old_var
= fragp
->fr_var
;
17937 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17939 return fragp
->fr_var
- old_var
;
17942 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17944 offsetT old_var
= fragp
->fr_var
;
17945 offsetT new_var
= 4;
17947 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17948 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17949 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17950 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17951 fragp
->fr_var
= new_var
;
17953 return new_var
- old_var
;
17956 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17959 if (!mips16_extended_frag (fragp
, sec
, stretch
))
17961 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17963 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
17966 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17968 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17974 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
17976 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17978 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
17979 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17982 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17984 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17992 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17994 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17996 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17997 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18002 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18010 /* Convert a machine dependent frag. */
18013 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18015 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18018 unsigned long insn
;
18022 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18023 insn
= read_insn (buf
);
18025 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18027 /* We generate a fixup instead of applying it right now
18028 because, if there are linker relaxations, we're going to
18029 need the relocations. */
18030 exp
.X_op
= O_symbol
;
18031 exp
.X_add_symbol
= fragp
->fr_symbol
;
18032 exp
.X_add_number
= fragp
->fr_offset
;
18034 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18035 BFD_RELOC_16_PCREL_S2
);
18036 fixp
->fx_file
= fragp
->fr_file
;
18037 fixp
->fx_line
= fragp
->fr_line
;
18039 buf
= write_insn (buf
, insn
);
18045 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18046 _("relaxed out-of-range branch into a jump"));
18048 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18051 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18053 /* Reverse the branch. */
18054 switch ((insn
>> 28) & 0xf)
18057 if ((insn
& 0xff000000) == 0x47000000
18058 || (insn
& 0xff600000) == 0x45600000)
18060 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18061 reversed by tweaking bit 23. */
18062 insn
^= 0x00800000;
18066 /* bc[0-3][tf]l? instructions can have the condition
18067 reversed by tweaking a single TF bit, and their
18068 opcodes all have 0x4???????. */
18069 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18070 insn
^= 0x00010000;
18075 /* bltz 0x04000000 bgez 0x04010000
18076 bltzal 0x04100000 bgezal 0x04110000 */
18077 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18078 insn
^= 0x00010000;
18082 /* beq 0x10000000 bne 0x14000000
18083 blez 0x18000000 bgtz 0x1c000000 */
18084 insn
^= 0x04000000;
18092 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18094 /* Clear the and-link bit. */
18095 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18097 /* bltzal 0x04100000 bgezal 0x04110000
18098 bltzall 0x04120000 bgezall 0x04130000 */
18099 insn
&= ~0x00100000;
18102 /* Branch over the branch (if the branch was likely) or the
18103 full jump (not likely case). Compute the offset from the
18104 current instruction to branch to. */
18105 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18109 /* How many bytes in instructions we've already emitted? */
18110 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18111 /* How many bytes in instructions from here to the end? */
18112 i
= fragp
->fr_var
- i
;
18114 /* Convert to instruction count. */
18116 /* Branch counts from the next instruction. */
18119 /* Branch over the jump. */
18120 buf
= write_insn (buf
, insn
);
18123 buf
= write_insn (buf
, 0);
18125 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18127 /* beql $0, $0, 2f */
18129 /* Compute the PC offset from the current instruction to
18130 the end of the variable frag. */
18131 /* How many bytes in instructions we've already emitted? */
18132 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18133 /* How many bytes in instructions from here to the end? */
18134 i
= fragp
->fr_var
- i
;
18135 /* Convert to instruction count. */
18137 /* Don't decrement i, because we want to branch over the
18141 buf
= write_insn (buf
, insn
);
18142 buf
= write_insn (buf
, 0);
18146 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18149 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18150 ? 0x0c000000 : 0x08000000);
18151 exp
.X_op
= O_symbol
;
18152 exp
.X_add_symbol
= fragp
->fr_symbol
;
18153 exp
.X_add_number
= fragp
->fr_offset
;
18155 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18156 FALSE
, BFD_RELOC_MIPS_JMP
);
18157 fixp
->fx_file
= fragp
->fr_file
;
18158 fixp
->fx_line
= fragp
->fr_line
;
18160 buf
= write_insn (buf
, insn
);
18164 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18166 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18167 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18168 insn
|= at
<< OP_SH_RT
;
18169 exp
.X_op
= O_symbol
;
18170 exp
.X_add_symbol
= fragp
->fr_symbol
;
18171 exp
.X_add_number
= fragp
->fr_offset
;
18173 if (fragp
->fr_offset
)
18175 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18176 exp
.X_add_number
= 0;
18179 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18180 FALSE
, BFD_RELOC_MIPS_GOT16
);
18181 fixp
->fx_file
= fragp
->fr_file
;
18182 fixp
->fx_line
= fragp
->fr_line
;
18184 buf
= write_insn (buf
, insn
);
18186 if (mips_opts
.isa
== ISA_MIPS1
)
18188 buf
= write_insn (buf
, 0);
18190 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18191 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18192 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18194 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18195 FALSE
, BFD_RELOC_LO16
);
18196 fixp
->fx_file
= fragp
->fr_file
;
18197 fixp
->fx_line
= fragp
->fr_line
;
18199 buf
= write_insn (buf
, insn
);
18202 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18206 insn
|= at
<< OP_SH_RS
;
18208 buf
= write_insn (buf
, insn
);
18212 fragp
->fr_fix
+= fragp
->fr_var
;
18213 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18217 /* Relax microMIPS branches. */
18218 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18220 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18221 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18222 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18223 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18224 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18225 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18226 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18227 bfd_boolean short_ds
;
18228 unsigned long insn
;
18232 exp
.X_op
= O_symbol
;
18233 exp
.X_add_symbol
= fragp
->fr_symbol
;
18234 exp
.X_add_number
= fragp
->fr_offset
;
18236 fragp
->fr_fix
+= fragp
->fr_var
;
18238 /* Handle 16-bit branches that fit or are forced to fit. */
18239 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18241 /* We generate a fixup instead of applying it right now,
18242 because if there is linker relaxation, we're going to
18243 need the relocations. */
18245 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18246 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18247 else if (type
== 'E')
18248 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18249 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18253 fixp
->fx_file
= fragp
->fr_file
;
18254 fixp
->fx_line
= fragp
->fr_line
;
18256 /* These relocations can have an addend that won't fit in
18258 fixp
->fx_no_overflow
= 1;
18263 /* Handle 32-bit branches that fit or are forced to fit. */
18264 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18265 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18267 /* We generate a fixup instead of applying it right now,
18268 because if there is linker relaxation, we're going to
18269 need the relocations. */
18270 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18271 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18272 fixp
->fx_file
= fragp
->fr_file
;
18273 fixp
->fx_line
= fragp
->fr_line
;
18277 insn
= read_compressed_insn (buf
, 4);
18282 /* Check the short-delay-slot bit. */
18283 if (!al
|| (insn
& 0x02000000) != 0)
18284 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18286 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18289 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18294 /* Relax 16-bit branches to 32-bit branches. */
18297 insn
= read_compressed_insn (buf
, 2);
18299 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18300 insn
= 0x94000000; /* beq */
18301 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18303 unsigned long regno
;
18305 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18306 regno
= micromips_to_32_reg_d_map
[regno
];
18307 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18308 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18313 /* Nothing else to do, just write it out. */
18314 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18315 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18317 buf
= write_compressed_insn (buf
, insn
, 4);
18319 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18320 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18325 insn
= read_compressed_insn (buf
, 4);
18327 /* Relax 32-bit branches to a sequence of instructions. */
18328 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18329 _("relaxed out-of-range branch into a jump"));
18331 /* Set the short-delay-slot bit. */
18332 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18334 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18338 /* Reverse the branch. */
18339 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18340 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18341 insn
^= 0x20000000;
18342 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18343 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18344 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18345 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18346 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18347 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18348 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18349 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18350 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18351 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18352 insn
^= 0x00400000;
18353 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18354 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18355 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18356 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18357 insn
^= 0x00200000;
18358 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18360 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18362 insn
^= 0x00800000;
18368 /* Clear the and-link and short-delay-slot bits. */
18369 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18371 /* bltzal 0x40200000 bgezal 0x40600000 */
18372 /* bltzals 0x42200000 bgezals 0x42600000 */
18373 insn
&= ~0x02200000;
18376 /* Make a label at the end for use with the branch. */
18377 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18378 micromips_label_inc ();
18379 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18382 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18383 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18384 fixp
->fx_file
= fragp
->fr_file
;
18385 fixp
->fx_line
= fragp
->fr_line
;
18387 /* Branch over the jump. */
18388 buf
= write_compressed_insn (buf
, insn
, 4);
18394 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18396 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18402 unsigned long jal
= (short_ds
|| nods
18403 ? 0x74000000 : 0xf4000000); /* jal/s */
18405 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18406 insn
= al
? jal
: 0xd4000000;
18408 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18409 BFD_RELOC_MICROMIPS_JMP
);
18410 fixp
->fx_file
= fragp
->fr_file
;
18411 fixp
->fx_line
= fragp
->fr_line
;
18413 buf
= write_compressed_insn (buf
, insn
, 4);
18415 if (compact
|| nods
)
18419 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18421 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18426 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18428 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18429 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18430 insn
|= at
<< MICROMIPSOP_SH_RT
;
18432 if (exp
.X_add_number
)
18434 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18435 exp
.X_add_number
= 0;
18438 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18439 BFD_RELOC_MICROMIPS_GOT16
);
18440 fixp
->fx_file
= fragp
->fr_file
;
18441 fixp
->fx_line
= fragp
->fr_line
;
18443 buf
= write_compressed_insn (buf
, insn
, 4);
18445 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18446 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18447 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18449 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18450 BFD_RELOC_MICROMIPS_LO16
);
18451 fixp
->fx_file
= fragp
->fr_file
;
18452 fixp
->fx_line
= fragp
->fr_line
;
18454 buf
= write_compressed_insn (buf
, insn
, 4);
18459 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18460 insn
|= at
<< MICROMIPSOP_SH_RS
;
18462 buf
= write_compressed_insn (buf
, insn
, 4);
18464 if (compact
|| nods
)
18466 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18470 /* jr/jrc/jalr/jalrs $at */
18471 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18472 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18474 insn
= al
? jalr
: jr
;
18475 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18477 buf
= write_compressed_insn (buf
, insn
, 2);
18482 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18484 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18489 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18493 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18496 const struct mips_int_operand
*operand
;
18499 unsigned int user_length
;
18500 bfd_boolean need_reloc
;
18501 unsigned long insn
;
18506 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18507 operand
= mips16_immed_operand (type
, FALSE
);
18509 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18510 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18511 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18513 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18514 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18515 || (operand
->root
.type
== OP_PCREL
&& !mac
18517 : !bfd_is_abs_section (symsec
)));
18519 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18521 const struct mips_pcrel_operand
*pcrel_op
;
18523 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18525 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18527 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18528 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18529 _("branch to a symbol in another ISA mode"));
18530 else if ((fragp
->fr_offset
& 0x1) != 0)
18531 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18532 _("branch to misaligned address (0x%lx)"),
18536 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18538 /* Make sure the section winds up with the alignment we have
18540 if (operand
->shift
> 0)
18541 record_alignment (asec
, operand
->shift
);
18544 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18545 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18548 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18549 _("macro instruction expanded into multiple "
18550 "instructions in a branch delay slot"));
18552 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18553 _("extended instruction in a branch delay slot"));
18555 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18556 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18557 _("macro instruction expanded into multiple "
18560 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18562 insn
= read_compressed_insn (buf
, 2);
18564 insn
|= MIPS16_EXTEND
;
18566 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18568 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18579 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18580 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18586 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18588 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18589 fragp
->fr_symbol
, fragp
->fr_offset
,
18590 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18591 fixp
->fx_file
= fragp
->fr_file
;
18592 fixp
->fx_line
= fragp
->fr_line
;
18594 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ 8, 4,
18595 fragp
->fr_symbol
, fragp
->fr_offset
,
18596 FALSE
, BFD_RELOC_MIPS16_LO16
);
18597 fixp
->fx_file
= fragp
->fr_file
;
18598 fixp
->fx_line
= fragp
->fr_line
;
18603 switch (insn
& 0xf800)
18605 case 0x0800: /* ADDIU */
18606 reg
= (insn
>> 8) & 0x7;
18607 op
= 0xf0004800 | (reg
<< 8);
18609 case 0xb000: /* LW */
18610 reg
= (insn
>> 8) & 0x7;
18611 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18613 case 0xf800: /* I64 */
18614 reg
= (insn
>> 5) & 0x7;
18615 switch (insn
& 0x0700)
18617 case 0x0400: /* LD */
18618 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18620 case 0x0600: /* DADDIU */
18621 op
= 0xf000fd00 | (reg
<< 5);
18631 new = 0xf0006800 | (reg
<< 8); /* LI */
18632 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18633 buf
= write_compressed_insn (buf
, new, 4);
18634 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18635 buf
= write_compressed_insn (buf
, new, 4);
18636 op
|= mips16_immed_extend (val
, 16);
18637 buf
= write_compressed_insn (buf
, op
, 4);
18639 fragp
->fr_fix
+= 12;
18643 unsigned int length
= ext
? 4 : 2;
18647 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18655 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18660 if (mac
|| reloc
== BFD_RELOC_NONE
)
18661 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18662 _("unsupported relocation"));
18665 exp
.X_op
= O_symbol
;
18666 exp
.X_add_symbol
= fragp
->fr_symbol
;
18667 exp
.X_add_number
= fragp
->fr_offset
;
18669 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18672 fixp
->fx_file
= fragp
->fr_file
;
18673 fixp
->fx_line
= fragp
->fr_line
;
18676 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18677 _("invalid unextended operand value"));
18680 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18681 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18683 gas_assert (mips16_opcode_length (insn
) == length
);
18684 write_compressed_insn (buf
, insn
, length
);
18685 fragp
->fr_fix
+= length
;
18690 relax_substateT subtype
= fragp
->fr_subtype
;
18691 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18692 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18696 first
= RELAX_FIRST (subtype
);
18697 second
= RELAX_SECOND (subtype
);
18698 fixp
= (fixS
*) fragp
->fr_opcode
;
18700 /* If the delay slot chosen does not match the size of the instruction,
18701 then emit a warning. */
18702 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18703 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18708 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18709 | RELAX_DELAY_SLOT_SIZE_FIRST
18710 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18711 msg
= macro_warning (s
);
18713 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18717 /* Possibly emit a warning if we've chosen the longer option. */
18718 if (use_second
== second_longer
)
18724 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18725 msg
= macro_warning (s
);
18727 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18731 /* Go through all the fixups for the first sequence. Disable them
18732 (by marking them as done) if we're going to use the second
18733 sequence instead. */
18735 && fixp
->fx_frag
== fragp
18736 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18738 if (subtype
& RELAX_USE_SECOND
)
18740 fixp
= fixp
->fx_next
;
18743 /* Go through the fixups for the second sequence. Disable them if
18744 we're going to use the first sequence, otherwise adjust their
18745 addresses to account for the relaxation. */
18746 while (fixp
&& fixp
->fx_frag
== fragp
)
18748 if (subtype
& RELAX_USE_SECOND
)
18749 fixp
->fx_where
-= first
;
18752 fixp
= fixp
->fx_next
;
18755 /* Now modify the frag contents. */
18756 if (subtype
& RELAX_USE_SECOND
)
18760 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18761 memmove (start
, start
+ first
, second
);
18762 fragp
->fr_fix
-= first
;
18765 fragp
->fr_fix
-= second
;
18769 /* This function is called after the relocs have been generated.
18770 We've been storing mips16 text labels as odd. Here we convert them
18771 back to even for the convenience of the debugger. */
18774 mips_frob_file_after_relocs (void)
18777 unsigned int count
, i
;
18779 syms
= bfd_get_outsymbols (stdoutput
);
18780 count
= bfd_get_symcount (stdoutput
);
18781 for (i
= 0; i
< count
; i
++, syms
++)
18782 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18783 && ((*syms
)->value
& 1) != 0)
18785 (*syms
)->value
&= ~1;
18786 /* If the symbol has an odd size, it was probably computed
18787 incorrectly, so adjust that as well. */
18788 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18789 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18793 /* This function is called whenever a label is defined, including fake
18794 labels instantiated off the dot special symbol. It is used when
18795 handling branch delays; if a branch has a label, we assume we cannot
18796 move it. This also bumps the value of the symbol by 1 in compressed
18800 mips_record_label (symbolS
*sym
)
18802 segment_info_type
*si
= seg_info (now_seg
);
18803 struct insn_label_list
*l
;
18805 if (free_insn_labels
== NULL
)
18806 l
= XNEW (struct insn_label_list
);
18809 l
= free_insn_labels
;
18810 free_insn_labels
= l
->next
;
18814 l
->next
= si
->label_list
;
18815 si
->label_list
= l
;
18818 /* This function is called as tc_frob_label() whenever a label is defined
18819 and adds a DWARF-2 record we only want for true labels. */
18822 mips_define_label (symbolS
*sym
)
18824 mips_record_label (sym
);
18825 dwarf2_emit_label (sym
);
18828 /* This function is called by tc_new_dot_label whenever a new dot symbol
18832 mips_add_dot_label (symbolS
*sym
)
18834 mips_record_label (sym
);
18835 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18836 mips_compressed_mark_label (sym
);
18839 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18840 static unsigned int
18841 mips_convert_ase_flags (int ase
)
18843 unsigned int ext_ases
= 0;
18846 ext_ases
|= AFL_ASE_DSP
;
18847 if (ase
& ASE_DSPR2
)
18848 ext_ases
|= AFL_ASE_DSPR2
;
18849 if (ase
& ASE_DSPR3
)
18850 ext_ases
|= AFL_ASE_DSPR3
;
18852 ext_ases
|= AFL_ASE_EVA
;
18854 ext_ases
|= AFL_ASE_MCU
;
18855 if (ase
& ASE_MDMX
)
18856 ext_ases
|= AFL_ASE_MDMX
;
18857 if (ase
& ASE_MIPS3D
)
18858 ext_ases
|= AFL_ASE_MIPS3D
;
18860 ext_ases
|= AFL_ASE_MT
;
18861 if (ase
& ASE_SMARTMIPS
)
18862 ext_ases
|= AFL_ASE_SMARTMIPS
;
18863 if (ase
& ASE_VIRT
)
18864 ext_ases
|= AFL_ASE_VIRT
;
18866 ext_ases
|= AFL_ASE_MSA
;
18868 ext_ases
|= AFL_ASE_XPA
;
18872 /* Some special processing for a MIPS ELF file. */
18875 mips_elf_final_processing (void)
18878 Elf_Internal_ABIFlags_v0 flags
;
18882 switch (file_mips_opts
.isa
)
18885 flags
.isa_level
= 1;
18888 flags
.isa_level
= 2;
18891 flags
.isa_level
= 3;
18894 flags
.isa_level
= 4;
18897 flags
.isa_level
= 5;
18900 flags
.isa_level
= 32;
18904 flags
.isa_level
= 32;
18908 flags
.isa_level
= 32;
18912 flags
.isa_level
= 32;
18916 flags
.isa_level
= 32;
18920 flags
.isa_level
= 64;
18924 flags
.isa_level
= 64;
18928 flags
.isa_level
= 64;
18932 flags
.isa_level
= 64;
18936 flags
.isa_level
= 64;
18941 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18942 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18943 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18944 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18946 flags
.cpr2_size
= AFL_REG_NONE
;
18947 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18948 Tag_GNU_MIPS_ABI_FP
);
18949 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18950 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18951 if (file_ase_mips16
)
18952 flags
.ases
|= AFL_ASE_MIPS16
;
18953 if (file_ase_micromips
)
18954 flags
.ases
|= AFL_ASE_MICROMIPS
;
18956 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18957 || file_mips_opts
.fp
== 64)
18958 && file_mips_opts
.oddspreg
)
18959 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18962 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18963 ((Elf_External_ABIFlags_v0
*)
18966 /* Write out the register information. */
18967 if (mips_abi
!= N64_ABI
)
18971 s
.ri_gprmask
= mips_gprmask
;
18972 s
.ri_cprmask
[0] = mips_cprmask
[0];
18973 s
.ri_cprmask
[1] = mips_cprmask
[1];
18974 s
.ri_cprmask
[2] = mips_cprmask
[2];
18975 s
.ri_cprmask
[3] = mips_cprmask
[3];
18976 /* The gp_value field is set by the MIPS ELF backend. */
18978 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18979 ((Elf32_External_RegInfo
*)
18980 mips_regmask_frag
));
18984 Elf64_Internal_RegInfo s
;
18986 s
.ri_gprmask
= mips_gprmask
;
18988 s
.ri_cprmask
[0] = mips_cprmask
[0];
18989 s
.ri_cprmask
[1] = mips_cprmask
[1];
18990 s
.ri_cprmask
[2] = mips_cprmask
[2];
18991 s
.ri_cprmask
[3] = mips_cprmask
[3];
18992 /* The gp_value field is set by the MIPS ELF backend. */
18994 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18995 ((Elf64_External_RegInfo
*)
18996 mips_regmask_frag
));
18999 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19000 sort of BFD interface for this. */
19001 if (mips_any_noreorder
)
19002 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19003 if (mips_pic
!= NO_PIC
)
19005 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19006 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19009 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19011 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19012 defined at present; this might need to change in future. */
19013 if (file_ase_mips16
)
19014 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19015 if (file_ase_micromips
)
19016 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19017 if (file_mips_opts
.ase
& ASE_MDMX
)
19018 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19020 /* Set the MIPS ELF ABI flags. */
19021 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19022 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19023 else if (mips_abi
== O64_ABI
)
19024 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19025 else if (mips_abi
== EABI_ABI
)
19027 if (file_mips_opts
.gp
== 64)
19028 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19030 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19032 else if (mips_abi
== N32_ABI
)
19033 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
19035 /* Nothing to do for N64_ABI. */
19037 if (mips_32bitmode
)
19038 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19040 if (mips_nan2008
== 1)
19041 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19043 /* 32 bit code with 64 bit FP registers. */
19044 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19045 Tag_GNU_MIPS_ABI_FP
);
19046 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19047 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19050 typedef struct proc
{
19052 symbolS
*func_end_sym
;
19053 unsigned long reg_mask
;
19054 unsigned long reg_offset
;
19055 unsigned long fpreg_mask
;
19056 unsigned long fpreg_offset
;
19057 unsigned long frame_offset
;
19058 unsigned long frame_reg
;
19059 unsigned long pc_reg
;
19062 static procS cur_proc
;
19063 static procS
*cur_proc_ptr
;
19064 static int numprocs
;
19066 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19067 as "2", and a normal nop as "0". */
19069 #define NOP_OPCODE_MIPS 0
19070 #define NOP_OPCODE_MIPS16 1
19071 #define NOP_OPCODE_MICROMIPS 2
19074 mips_nop_opcode (void)
19076 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19077 return NOP_OPCODE_MICROMIPS
;
19078 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19079 return NOP_OPCODE_MIPS16
;
19081 return NOP_OPCODE_MIPS
;
19084 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19085 32-bit microMIPS NOPs here (if applicable). */
19088 mips_handle_align (fragS
*fragp
)
19092 int bytes
, size
, excess
;
19095 if (fragp
->fr_type
!= rs_align_code
)
19098 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19100 switch (nop_opcode
)
19102 case NOP_OPCODE_MICROMIPS
:
19103 opcode
= micromips_nop32_insn
.insn_opcode
;
19106 case NOP_OPCODE_MIPS16
:
19107 opcode
= mips16_nop_insn
.insn_opcode
;
19110 case NOP_OPCODE_MIPS
:
19112 opcode
= nop_insn
.insn_opcode
;
19117 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19118 excess
= bytes
% size
;
19120 /* Handle the leading part if we're not inserting a whole number of
19121 instructions, and make it the end of the fixed part of the frag.
19122 Try to fit in a short microMIPS NOP if applicable and possible,
19123 and use zeroes otherwise. */
19124 gas_assert (excess
< 4);
19125 fragp
->fr_fix
+= excess
;
19130 /* Fall through. */
19132 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19134 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19138 /* Fall through. */
19141 /* Fall through. */
19146 md_number_to_chars (p
, opcode
, size
);
19147 fragp
->fr_var
= size
;
19156 if (*input_line_pointer
== '-')
19158 ++input_line_pointer
;
19161 if (!ISDIGIT (*input_line_pointer
))
19162 as_bad (_("expected simple number"));
19163 if (input_line_pointer
[0] == '0')
19165 if (input_line_pointer
[1] == 'x')
19167 input_line_pointer
+= 2;
19168 while (ISXDIGIT (*input_line_pointer
))
19171 val
|= hex_value (*input_line_pointer
++);
19173 return negative
? -val
: val
;
19177 ++input_line_pointer
;
19178 while (ISDIGIT (*input_line_pointer
))
19181 val
|= *input_line_pointer
++ - '0';
19183 return negative
? -val
: val
;
19186 if (!ISDIGIT (*input_line_pointer
))
19188 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19189 *input_line_pointer
, *input_line_pointer
);
19190 as_warn (_("invalid number"));
19193 while (ISDIGIT (*input_line_pointer
))
19196 val
+= *input_line_pointer
++ - '0';
19198 return negative
? -val
: val
;
19201 /* The .file directive; just like the usual .file directive, but there
19202 is an initial number which is the ECOFF file index. In the non-ECOFF
19203 case .file implies DWARF-2. */
19206 s_mips_file (int x ATTRIBUTE_UNUSED
)
19208 static int first_file_directive
= 0;
19210 if (ECOFF_DEBUGGING
)
19219 filename
= dwarf2_directive_file (0);
19221 /* Versions of GCC up to 3.1 start files with a ".file"
19222 directive even for stabs output. Make sure that this
19223 ".file" is handled. Note that you need a version of GCC
19224 after 3.1 in order to support DWARF-2 on MIPS. */
19225 if (filename
!= NULL
&& ! first_file_directive
)
19227 (void) new_logical_line (filename
, -1);
19228 s_app_file_string (filename
, 0);
19230 first_file_directive
= 1;
19234 /* The .loc directive, implying DWARF-2. */
19237 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19239 if (!ECOFF_DEBUGGING
)
19240 dwarf2_directive_loc (0);
19243 /* The .end directive. */
19246 s_mips_end (int x ATTRIBUTE_UNUSED
)
19250 /* Following functions need their own .frame and .cprestore directives. */
19251 mips_frame_reg_valid
= 0;
19252 mips_cprestore_valid
= 0;
19254 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19257 demand_empty_rest_of_line ();
19262 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19263 as_warn (_(".end not in text section"));
19267 as_warn (_(".end directive without a preceding .ent directive"));
19268 demand_empty_rest_of_line ();
19274 gas_assert (S_GET_NAME (p
));
19275 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19276 as_warn (_(".end symbol does not match .ent symbol"));
19278 if (debug_type
== DEBUG_STABS
)
19279 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19283 as_warn (_(".end directive missing or unknown symbol"));
19285 /* Create an expression to calculate the size of the function. */
19286 if (p
&& cur_proc_ptr
)
19288 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19289 expressionS
*exp
= XNEW (expressionS
);
19292 exp
->X_op
= O_subtract
;
19293 exp
->X_add_symbol
= symbol_temp_new_now ();
19294 exp
->X_op_symbol
= p
;
19295 exp
->X_add_number
= 0;
19297 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19300 #ifdef md_flush_pending_output
19301 md_flush_pending_output ();
19304 /* Generate a .pdr section. */
19305 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19307 segT saved_seg
= now_seg
;
19308 subsegT saved_subseg
= now_subseg
;
19312 gas_assert (pdr_seg
);
19313 subseg_set (pdr_seg
, 0);
19315 /* Write the symbol. */
19316 exp
.X_op
= O_symbol
;
19317 exp
.X_add_symbol
= p
;
19318 exp
.X_add_number
= 0;
19319 emit_expr (&exp
, 4);
19321 fragp
= frag_more (7 * 4);
19323 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19324 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19325 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19326 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19327 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19328 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19329 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19331 subseg_set (saved_seg
, saved_subseg
);
19334 cur_proc_ptr
= NULL
;
19337 /* The .aent and .ent directives. */
19340 s_mips_ent (int aent
)
19344 symbolP
= get_symbol ();
19345 if (*input_line_pointer
== ',')
19346 ++input_line_pointer
;
19347 SKIP_WHITESPACE ();
19348 if (ISDIGIT (*input_line_pointer
)
19349 || *input_line_pointer
== '-')
19352 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19353 as_warn (_(".ent or .aent not in text section"));
19355 if (!aent
&& cur_proc_ptr
)
19356 as_warn (_("missing .end"));
19360 /* This function needs its own .frame and .cprestore directives. */
19361 mips_frame_reg_valid
= 0;
19362 mips_cprestore_valid
= 0;
19364 cur_proc_ptr
= &cur_proc
;
19365 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19367 cur_proc_ptr
->func_sym
= symbolP
;
19371 if (debug_type
== DEBUG_STABS
)
19372 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19373 S_GET_NAME (symbolP
));
19376 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19378 demand_empty_rest_of_line ();
19381 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19382 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19383 s_mips_frame is used so that we can set the PDR information correctly.
19384 We can't use the ecoff routines because they make reference to the ecoff
19385 symbol table (in the mdebug section). */
19388 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19390 if (ECOFF_DEBUGGING
)
19396 if (cur_proc_ptr
== (procS
*) NULL
)
19398 as_warn (_(".frame outside of .ent"));
19399 demand_empty_rest_of_line ();
19403 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19405 SKIP_WHITESPACE ();
19406 if (*input_line_pointer
++ != ','
19407 || get_absolute_expression_and_terminator (&val
) != ',')
19409 as_warn (_("bad .frame directive"));
19410 --input_line_pointer
;
19411 demand_empty_rest_of_line ();
19415 cur_proc_ptr
->frame_offset
= val
;
19416 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19418 demand_empty_rest_of_line ();
19422 /* The .fmask and .mask directives. If the mdebug section is present
19423 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19424 embedded targets, s_mips_mask is used so that we can set the PDR
19425 information correctly. We can't use the ecoff routines because they
19426 make reference to the ecoff symbol table (in the mdebug section). */
19429 s_mips_mask (int reg_type
)
19431 if (ECOFF_DEBUGGING
)
19432 s_ignore (reg_type
);
19437 if (cur_proc_ptr
== (procS
*) NULL
)
19439 as_warn (_(".mask/.fmask outside of .ent"));
19440 demand_empty_rest_of_line ();
19444 if (get_absolute_expression_and_terminator (&mask
) != ',')
19446 as_warn (_("bad .mask/.fmask directive"));
19447 --input_line_pointer
;
19448 demand_empty_rest_of_line ();
19452 off
= get_absolute_expression ();
19454 if (reg_type
== 'F')
19456 cur_proc_ptr
->fpreg_mask
= mask
;
19457 cur_proc_ptr
->fpreg_offset
= off
;
19461 cur_proc_ptr
->reg_mask
= mask
;
19462 cur_proc_ptr
->reg_offset
= off
;
19465 demand_empty_rest_of_line ();
19469 /* A table describing all the processors gas knows about. Names are
19470 matched in the order listed.
19472 To ease comparison, please keep this table in the same order as
19473 gcc's mips_cpu_info_table[]. */
19474 static const struct mips_cpu_info mips_cpu_info_table
[] =
19476 /* Entries for generic ISAs */
19477 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19478 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19479 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19480 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19481 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19482 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19483 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19484 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19485 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19486 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19487 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19488 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19489 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19490 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19491 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19494 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19495 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19496 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19499 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19502 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19503 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19504 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19505 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19506 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19507 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19508 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19509 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19510 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19511 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19512 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19513 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19514 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19515 /* ST Microelectronics Loongson 2E and 2F cores */
19516 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19517 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19520 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19521 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19522 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19523 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19524 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19525 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19526 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19527 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19528 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19529 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19530 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19531 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19532 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19533 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19534 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19537 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19538 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19539 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19540 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19542 /* MIPS 32 Release 2 */
19543 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19544 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19545 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19546 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19547 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19548 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19549 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19550 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19551 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19552 ISA_MIPS32R2
, CPU_MIPS32R2
},
19553 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19554 ISA_MIPS32R2
, CPU_MIPS32R2
},
19555 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19556 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19557 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19558 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19559 /* Deprecated forms of the above. */
19560 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19561 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19562 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19563 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19564 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19565 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19566 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19567 /* Deprecated forms of the above. */
19568 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19569 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19570 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19571 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19572 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19573 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19574 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19575 /* Deprecated forms of the above. */
19576 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19577 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19578 /* 34Kn is a 34kc without DSP. */
19579 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19580 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19581 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19582 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19583 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19584 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19585 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19586 /* Deprecated forms of the above. */
19587 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19588 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19589 /* 1004K cores are multiprocessor versions of the 34K. */
19590 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19591 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19592 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19593 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19594 /* interaptiv is the new name for 1004kf */
19595 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19597 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19598 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19599 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19600 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19603 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19604 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19605 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19606 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19608 /* Broadcom SB-1 CPU core */
19609 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19610 /* Broadcom SB-1A CPU core */
19611 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19613 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19615 /* MIPS 64 Release 2 */
19617 /* Cavium Networks Octeon CPU core */
19618 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19619 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19620 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19621 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19624 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19627 XLP is mostly like XLR, with the prominent exception that it is
19628 MIPS64R2 rather than MIPS64. */
19629 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19631 /* MIPS 64 Release 6 */
19632 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19633 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19636 { NULL
, 0, 0, 0, 0 }
19640 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19641 with a final "000" replaced by "k". Ignore case.
19643 Note: this function is shared between GCC and GAS. */
19646 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19648 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19649 given
++, canonical
++;
19651 return ((*given
== 0 && *canonical
== 0)
19652 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19656 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19657 CPU name. We've traditionally allowed a lot of variation here.
19659 Note: this function is shared between GCC and GAS. */
19662 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19664 /* First see if the name matches exactly, or with a final "000"
19665 turned into "k". */
19666 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19669 /* If not, try comparing based on numerical designation alone.
19670 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19671 if (TOLOWER (*given
) == 'r')
19673 if (!ISDIGIT (*given
))
19676 /* Skip over some well-known prefixes in the canonical name,
19677 hoping to find a number there too. */
19678 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19680 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19682 else if (TOLOWER (canonical
[0]) == 'r')
19685 return mips_strict_matching_cpu_name_p (canonical
, given
);
19689 /* Parse an option that takes the name of a processor as its argument.
19690 OPTION is the name of the option and CPU_STRING is the argument.
19691 Return the corresponding processor enumeration if the CPU_STRING is
19692 recognized, otherwise report an error and return null.
19694 A similar function exists in GCC. */
19696 static const struct mips_cpu_info
*
19697 mips_parse_cpu (const char *option
, const char *cpu_string
)
19699 const struct mips_cpu_info
*p
;
19701 /* 'from-abi' selects the most compatible architecture for the given
19702 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19703 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19704 version. Look first at the -mgp options, if given, otherwise base
19705 the choice on MIPS_DEFAULT_64BIT.
19707 Treat NO_ABI like the EABIs. One reason to do this is that the
19708 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19709 architecture. This code picks MIPS I for 'mips' and MIPS III for
19710 'mips64', just as we did in the days before 'from-abi'. */
19711 if (strcasecmp (cpu_string
, "from-abi") == 0)
19713 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19714 return mips_cpu_info_from_isa (ISA_MIPS1
);
19716 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19717 return mips_cpu_info_from_isa (ISA_MIPS3
);
19719 if (file_mips_opts
.gp
>= 0)
19720 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19721 ? ISA_MIPS1
: ISA_MIPS3
);
19723 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19728 /* 'default' has traditionally been a no-op. Probably not very useful. */
19729 if (strcasecmp (cpu_string
, "default") == 0)
19732 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19733 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19736 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19740 /* Return the canonical processor information for ISA (a member of the
19741 ISA_MIPS* enumeration). */
19743 static const struct mips_cpu_info
*
19744 mips_cpu_info_from_isa (int isa
)
19748 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19749 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19750 && isa
== mips_cpu_info_table
[i
].isa
)
19751 return (&mips_cpu_info_table
[i
]);
19756 static const struct mips_cpu_info
*
19757 mips_cpu_info_from_arch (int arch
)
19761 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19762 if (arch
== mips_cpu_info_table
[i
].cpu
)
19763 return (&mips_cpu_info_table
[i
]);
19769 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19773 fprintf (stream
, "%24s", "");
19778 fprintf (stream
, ", ");
19782 if (*col_p
+ strlen (string
) > 72)
19784 fprintf (stream
, "\n%24s", "");
19788 fprintf (stream
, "%s", string
);
19789 *col_p
+= strlen (string
);
19795 md_show_usage (FILE *stream
)
19800 fprintf (stream
, _("\
19802 -EB generate big endian output\n\
19803 -EL generate little endian output\n\
19804 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19805 -G NUM allow referencing objects up to NUM bytes\n\
19806 implicitly with the gp register [default 8]\n"));
19807 fprintf (stream
, _("\
19808 -mips1 generate MIPS ISA I instructions\n\
19809 -mips2 generate MIPS ISA II instructions\n\
19810 -mips3 generate MIPS ISA III instructions\n\
19811 -mips4 generate MIPS ISA IV instructions\n\
19812 -mips5 generate MIPS ISA V instructions\n\
19813 -mips32 generate MIPS32 ISA instructions\n\
19814 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19815 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19816 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19817 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19818 -mips64 generate MIPS64 ISA instructions\n\
19819 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19820 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19821 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19822 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19823 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19827 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19828 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19829 show (stream
, "from-abi", &column
, &first
);
19830 fputc ('\n', stream
);
19832 fprintf (stream
, _("\
19833 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19834 -no-mCPU don't generate code specific to CPU.\n\
19835 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19839 show (stream
, "3900", &column
, &first
);
19840 show (stream
, "4010", &column
, &first
);
19841 show (stream
, "4100", &column
, &first
);
19842 show (stream
, "4650", &column
, &first
);
19843 fputc ('\n', stream
);
19845 fprintf (stream
, _("\
19846 -mips16 generate mips16 instructions\n\
19847 -no-mips16 do not generate mips16 instructions\n"));
19848 fprintf (stream
, _("\
19849 -mmicromips generate microMIPS instructions\n\
19850 -mno-micromips do not generate microMIPS instructions\n"));
19851 fprintf (stream
, _("\
19852 -msmartmips generate smartmips instructions\n\
19853 -mno-smartmips do not generate smartmips instructions\n"));
19854 fprintf (stream
, _("\
19855 -mdsp generate DSP instructions\n\
19856 -mno-dsp do not generate DSP instructions\n"));
19857 fprintf (stream
, _("\
19858 -mdspr2 generate DSP R2 instructions\n\
19859 -mno-dspr2 do not generate DSP R2 instructions\n"));
19860 fprintf (stream
, _("\
19861 -mdspr3 generate DSP R3 instructions\n\
19862 -mno-dspr3 do not generate DSP R3 instructions\n"));
19863 fprintf (stream
, _("\
19864 -mmt generate MT instructions\n\
19865 -mno-mt do not generate MT instructions\n"));
19866 fprintf (stream
, _("\
19867 -mmcu generate MCU instructions\n\
19868 -mno-mcu do not generate MCU instructions\n"));
19869 fprintf (stream
, _("\
19870 -mmsa generate MSA instructions\n\
19871 -mno-msa do not generate MSA instructions\n"));
19872 fprintf (stream
, _("\
19873 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19874 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19875 fprintf (stream
, _("\
19876 -mvirt generate Virtualization instructions\n\
19877 -mno-virt do not generate Virtualization instructions\n"));
19878 fprintf (stream
, _("\
19879 -minsn32 only generate 32-bit microMIPS instructions\n\
19880 -mno-insn32 generate all microMIPS instructions\n"));
19881 fprintf (stream
, _("\
19882 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19883 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19884 -mfix-vr4120 work around certain VR4120 errata\n\
19885 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19886 -mfix-24k insert a nop after ERET and DERET instructions\n\
19887 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19888 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19889 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19890 -msym32 assume all symbols have 32-bit values\n\
19891 -O0 remove unneeded NOPs, do not swap branches\n\
19892 -O remove unneeded NOPs and swap branches\n\
19893 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19894 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19895 fprintf (stream
, _("\
19896 -mhard-float allow floating-point instructions\n\
19897 -msoft-float do not allow floating-point instructions\n\
19898 -msingle-float only allow 32-bit floating-point operations\n\
19899 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19900 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19901 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19902 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
19903 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
19904 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19908 show (stream
, "legacy", &column
, &first
);
19909 show (stream
, "2008", &column
, &first
);
19911 fputc ('\n', stream
);
19913 fprintf (stream
, _("\
19914 -KPIC, -call_shared generate SVR4 position independent code\n\
19915 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19916 -mvxworks-pic generate VxWorks position independent code\n\
19917 -non_shared do not generate code that can operate with DSOs\n\
19918 -xgot assume a 32 bit GOT\n\
19919 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19920 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19921 position dependent (non shared) code\n\
19922 -mabi=ABI create ABI conformant object file for:\n"));
19926 show (stream
, "32", &column
, &first
);
19927 show (stream
, "o64", &column
, &first
);
19928 show (stream
, "n32", &column
, &first
);
19929 show (stream
, "64", &column
, &first
);
19930 show (stream
, "eabi", &column
, &first
);
19932 fputc ('\n', stream
);
19934 fprintf (stream
, _("\
19935 -32 create o32 ABI object file (default)\n\
19936 -n32 create n32 ABI object file\n\
19937 -64 create 64 ABI object file\n"));
19942 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19944 if (HAVE_64BIT_SYMBOLS
)
19945 return dwarf2_format_64bit_irix
;
19947 return dwarf2_format_32bit
;
19952 mips_dwarf2_addr_size (void)
19954 if (HAVE_64BIT_OBJECTS
)
19960 /* Standard calling conventions leave the CFA at SP on entry. */
19962 mips_cfi_frame_initial_instructions (void)
19964 cfi_add_CFA_def_cfa_register (SP
);
19968 tc_mips_regname_to_dw2regnum (char *regname
)
19970 unsigned int regnum
= -1;
19973 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19979 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19980 Given a symbolic attribute NAME, return the proper integer value.
19981 Returns -1 if the attribute is not known. */
19984 mips_convert_symbolic_attribute (const char *name
)
19986 static const struct
19991 attribute_table
[] =
19993 #define T(tag) {#tag, tag}
19994 T (Tag_GNU_MIPS_ABI_FP
),
19995 T (Tag_GNU_MIPS_ABI_MSA
),
20003 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20004 if (streq (name
, attribute_table
[i
].name
))
20005 return attribute_table
[i
].tag
;
20013 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20015 mips_emit_delays ();
20017 as_warn (_("missing .end at end of assembly"));
20019 /* Just in case no code was emitted, do the consistency check. */
20020 file_mips_check_options ();
20022 /* Set a floating-point ABI if the user did not. */
20023 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20025 /* Perform consistency checks on the floating-point ABI. */
20026 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20027 Tag_GNU_MIPS_ABI_FP
);
20028 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20029 check_fpabi (fpabi
);
20033 /* Soft-float gets precedence over single-float, the two options should
20034 not be used together so this should not matter. */
20035 if (file_mips_opts
.soft_float
== 1)
20036 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20037 /* Single-float gets precedence over all double_float cases. */
20038 else if (file_mips_opts
.single_float
== 1)
20039 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20042 switch (file_mips_opts
.fp
)
20045 if (file_mips_opts
.gp
== 32)
20046 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20049 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20052 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20053 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20054 else if (file_mips_opts
.gp
== 32)
20055 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20057 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20062 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20063 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20067 /* Returns the relocation type required for a particular CFI encoding. */
20069 bfd_reloc_code_real_type
20070 mips_cfi_reloc_for_encoding (int encoding
)
20072 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20073 return BFD_RELOC_32_PCREL
;
20074 else return BFD_RELOC_NONE
;