1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend
;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend
;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode
;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p
: 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p
: 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p
: 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p
: 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi
= NO_ABI
;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls
= FALSE
;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared
= TRUE
;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
242 int warn_about_macros
;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
262 /* True if ".set sym32" is in effect. */
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float
;
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float
;
275 /* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
279 /* True if -mgp32 was passed. */
280 static int file_mips_gp32
= -1;
282 /* True if -mfp32 was passed. */
283 static int file_mips_fp32
= -1;
285 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286 static int file_mips_soft_float
= 0;
288 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289 static int file_mips_single_float
= 0;
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
295 /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG
,
296 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
298 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask
;
305 unsigned long mips_cprmask
[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa
= ISA_UNKNOWN
;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16
;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips
;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mips3d
;
337 /* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mdmx
;
341 /* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_smartmips
;
345 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
348 /* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350 static int file_ase_dsp
;
352 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2)
355 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
357 /* True if -mdspr2 was passed or implied by arguments passed on the
358 command line (e.g., by -march). */
359 static int file_ase_dspr2
;
361 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
362 || mips_opts.isa == ISA_MIPS64R2)
364 /* True if -mmt was passed or implied by arguments passed on the
365 command line (e.g., by -march). */
366 static int file_ase_mt
;
368 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
369 || mips_opts.isa == ISA_MIPS64R2)
371 /* The argument of the -march= flag. The architecture we are assembling. */
372 static int file_mips_arch
= CPU_UNKNOWN
;
373 static const char *mips_arch_string
;
375 /* The argument of the -mtune= flag. The architecture for which we
377 static int mips_tune
= CPU_UNKNOWN
;
378 static const char *mips_tune_string
;
380 /* True when generating 32-bit code for a 64-bit processor. */
381 static int mips_32bitmode
= 0;
383 /* True if the given ABI requires 32-bit registers. */
384 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
386 /* Likewise 64-bit registers. */
387 #define ABI_NEEDS_64BIT_REGS(ABI) \
389 || (ABI) == N64_ABI \
392 /* Return true if ISA supports 64 bit wide gp registers. */
393 #define ISA_HAS_64BIT_REGS(ISA) \
394 ((ISA) == ISA_MIPS3 \
395 || (ISA) == ISA_MIPS4 \
396 || (ISA) == ISA_MIPS5 \
397 || (ISA) == ISA_MIPS64 \
398 || (ISA) == ISA_MIPS64R2)
400 /* Return true if ISA supports 64 bit wide float registers. */
401 #define ISA_HAS_64BIT_FPRS(ISA) \
402 ((ISA) == ISA_MIPS3 \
403 || (ISA) == ISA_MIPS4 \
404 || (ISA) == ISA_MIPS5 \
405 || (ISA) == ISA_MIPS32R2 \
406 || (ISA) == ISA_MIPS64 \
407 || (ISA) == ISA_MIPS64R2)
409 /* Return true if ISA supports 64-bit right rotate (dror et al.)
411 #define ISA_HAS_DROR(ISA) \
412 ((ISA) == ISA_MIPS64R2 \
413 || (mips_opts.micromips \
414 && ISA_HAS_64BIT_REGS (ISA)) \
417 /* Return true if ISA supports 32-bit right rotate (ror et al.)
419 #define ISA_HAS_ROR(ISA) \
420 ((ISA) == ISA_MIPS32R2 \
421 || (ISA) == ISA_MIPS64R2 \
422 || mips_opts.ase_smartmips \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
428 ((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS64 \
431 || (ISA) == ISA_MIPS64R2)
433 /* Return true if ISA supports move to/from high part of a 64-bit
434 floating-point register. */
435 #define ISA_HAS_MXHC1(ISA) \
436 ((ISA) == ISA_MIPS32R2 \
437 || (ISA) == ISA_MIPS64R2)
439 #define HAVE_32BIT_GPRS \
440 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
442 #define HAVE_32BIT_FPRS \
443 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
445 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
446 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
448 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
450 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
452 /* True if relocations are stored in-place. */
453 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
455 /* The ABI-derived address size. */
456 #define HAVE_64BIT_ADDRESSES \
457 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
458 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
460 /* The size of symbolic constants (i.e., expressions of the form
461 "SYMBOL" or "SYMBOL + OFFSET"). */
462 #define HAVE_32BIT_SYMBOLS \
463 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
464 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
466 /* Addresses are loaded in different ways, depending on the address size
467 in use. The n32 ABI Documentation also mandates the use of additions
468 with overflow checking, but existing implementations don't follow it. */
469 #define ADDRESS_ADD_INSN \
470 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
472 #define ADDRESS_ADDI_INSN \
473 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
475 #define ADDRESS_LOAD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
478 #define ADDRESS_STORE_INSN \
479 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
481 /* Return true if the given CPU supports the MIPS16 ASE. */
482 #define CPU_HAS_MIPS16(cpu) \
483 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
484 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
486 /* Return true if the given CPU supports the microMIPS ASE. */
487 #define CPU_HAS_MICROMIPS(cpu) 0
489 /* True if CPU has a dror instruction. */
490 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
492 /* True if CPU has a ror instruction. */
493 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
495 /* True if CPU has seq/sne and seqi/snei instructions. */
496 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
498 /* True if CPU does not implement the all the coprocessor insns. For these
499 CPUs only those COP insns are accepted that are explicitly marked to be
500 available on the CPU. ISA membership for COP insns is ignored. */
501 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Returns true for a (non floating-point) coprocessor instruction. Reading
574 or writing the condition code is only possible on the coprocessors and
575 these insns are not marked with INSN_COP. Thus for these insns use the
576 condition-code flags. */
577 #define COP_INSN(PINFO) \
578 (PINFO != INSN_MACRO \
579 && ((PINFO) & (FP_S | FP_D)) == 0 \
580 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
582 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
583 has been selected. This implies, in particular, that addresses of text
584 labels have their LSB set. */
585 #define HAVE_CODE_COMPRESSION \
586 ((mips_opts.mips16 | mips_opts.micromips) != 0)
588 /* MIPS PIC level. */
590 enum mips_pic_level mips_pic
;
592 /* 1 if we should generate 32 bit offsets from the $gp register in
593 SVR4_PIC mode. Currently has no meaning in other modes. */
594 static int mips_big_got
= 0;
596 /* 1 if trap instructions should used for overflow rather than break
598 static int mips_trap
= 0;
600 /* 1 if double width floating point constants should not be constructed
601 by assembling two single width halves into two single width floating
602 point registers which just happen to alias the double width destination
603 register. On some architectures this aliasing can be disabled by a bit
604 in the status register, and the setting of this bit cannot be determined
605 automatically at assemble time. */
606 static int mips_disable_float_construction
;
608 /* Non-zero if any .set noreorder directives were used. */
610 static int mips_any_noreorder
;
612 /* Non-zero if nops should be inserted when the register referenced in
613 an mfhi/mflo instruction is read in the next two instructions. */
614 static int mips_7000_hilo_fix
;
616 /* The size of objects in the small data section. */
617 static unsigned int g_switch_value
= 8;
618 /* Whether the -G option was used. */
619 static int g_switch_seen
= 0;
624 /* If we can determine in advance that GP optimization won't be
625 possible, we can skip the relaxation stuff that tries to produce
626 GP-relative references. This makes delay slot optimization work
629 This function can only provide a guess, but it seems to work for
630 gcc output. It needs to guess right for gcc, otherwise gcc
631 will put what it thinks is a GP-relative instruction in a branch
634 I don't know if a fix is needed for the SVR4_PIC mode. I've only
635 fixed it for the non-PIC mode. KR 95/04/07 */
636 static int nopic_need_relax (symbolS
*, int);
638 /* handle of the OPCODE hash table */
639 static struct hash_control
*op_hash
= NULL
;
641 /* The opcode hash table we use for the mips16. */
642 static struct hash_control
*mips16_op_hash
= NULL
;
644 /* The opcode hash table we use for the microMIPS ASE. */
645 static struct hash_control
*micromips_op_hash
= NULL
;
647 /* This array holds the chars that always start a comment. If the
648 pre-processor is disabled, these aren't very useful */
649 const char comment_chars
[] = "#";
651 /* This array holds the chars that only start a comment at the beginning of
652 a line. If the line seems to have the form '# 123 filename'
653 .line and .file directives will appear in the pre-processed output */
654 /* Note that input_file.c hand checks for '#' at the beginning of the
655 first line of the input file. This is because the compiler outputs
656 #NO_APP at the beginning of its output. */
657 /* Also note that C style comments are always supported. */
658 const char line_comment_chars
[] = "#";
660 /* This array holds machine specific line separator characters. */
661 const char line_separator_chars
[] = ";";
663 /* Chars that can be used to separate mant from exp in floating point nums */
664 const char EXP_CHARS
[] = "eE";
666 /* Chars that mean this number is a floating point constant */
669 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
671 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
672 changed in read.c . Ideally it shouldn't have to know about it at all,
673 but nothing is ideal around here.
676 static char *insn_error
;
678 static int auto_align
= 1;
680 /* When outputting SVR4 PIC code, the assembler needs to know the
681 offset in the stack frame from which to restore the $gp register.
682 This is set by the .cprestore pseudo-op, and saved in this
684 static offsetT mips_cprestore_offset
= -1;
686 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
687 more optimizations, it can use a register value instead of a memory-saved
688 offset and even an other register than $gp as global pointer. */
689 static offsetT mips_cpreturn_offset
= -1;
690 static int mips_cpreturn_register
= -1;
691 static int mips_gp_register
= GP
;
692 static int mips_gprel_offset
= 0;
694 /* Whether mips_cprestore_offset has been set in the current function
695 (or whether it has already been warned about, if not). */
696 static int mips_cprestore_valid
= 0;
698 /* This is the register which holds the stack frame, as set by the
699 .frame pseudo-op. This is needed to implement .cprestore. */
700 static int mips_frame_reg
= SP
;
702 /* Whether mips_frame_reg has been set in the current function
703 (or whether it has already been warned about, if not). */
704 static int mips_frame_reg_valid
= 0;
706 /* To output NOP instructions correctly, we need to keep information
707 about the previous two instructions. */
709 /* Whether we are optimizing. The default value of 2 means to remove
710 unneeded NOPs and swap branch instructions when possible. A value
711 of 1 means to not swap branches. A value of 0 means to always
713 static int mips_optimize
= 2;
715 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
716 equivalent to seeing no -g option at all. */
717 static int mips_debug
= 0;
719 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
720 #define MAX_VR4130_NOPS 4
722 /* The maximum number of NOPs needed to fill delay slots. */
723 #define MAX_DELAY_NOPS 2
725 /* The maximum number of NOPs needed for any purpose. */
728 /* A list of previous instructions, with index 0 being the most recent.
729 We need to look back MAX_NOPS instructions when filling delay slots
730 or working around processor errata. We need to look back one
731 instruction further if we're thinking about using history[0] to
732 fill a branch delay slot. */
733 static struct mips_cl_insn history
[1 + MAX_NOPS
];
735 /* Nop instructions used by emit_nop. */
736 static struct mips_cl_insn nop_insn
;
737 static struct mips_cl_insn mips16_nop_insn
;
738 static struct mips_cl_insn micromips_nop16_insn
;
739 static struct mips_cl_insn micromips_nop32_insn
;
741 /* The appropriate nop for the current mode. */
742 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
743 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
745 /* The size of NOP_INSN in bytes. */
746 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
748 /* If this is set, it points to a frag holding nop instructions which
749 were inserted before the start of a noreorder section. If those
750 nops turn out to be unnecessary, the size of the frag can be
752 static fragS
*prev_nop_frag
;
754 /* The number of nop instructions we created in prev_nop_frag. */
755 static int prev_nop_frag_holds
;
757 /* The number of nop instructions that we know we need in
759 static int prev_nop_frag_required
;
761 /* The number of instructions we've seen since prev_nop_frag. */
762 static int prev_nop_frag_since
;
764 /* For ECOFF and ELF, relocations against symbols are done in two
765 parts, with a HI relocation and a LO relocation. Each relocation
766 has only 16 bits of space to store an addend. This means that in
767 order for the linker to handle carries correctly, it must be able
768 to locate both the HI and the LO relocation. This means that the
769 relocations must appear in order in the relocation table.
771 In order to implement this, we keep track of each unmatched HI
772 relocation. We then sort them so that they immediately precede the
773 corresponding LO relocation. */
778 struct mips_hi_fixup
*next
;
781 /* The section this fixup is in. */
785 /* The list of unmatched HI relocs. */
787 static struct mips_hi_fixup
*mips_hi_fixup_list
;
789 /* The frag containing the last explicit relocation operator.
790 Null if explicit relocations have not been used. */
792 static fragS
*prev_reloc_op_frag
;
794 /* Map normal MIPS register numbers to mips16 register numbers. */
796 #define X ILLEGAL_REG
797 static const int mips32_to_16_reg_map
[] =
799 X
, X
, 2, 3, 4, 5, 6, 7,
800 X
, X
, X
, X
, X
, X
, X
, X
,
801 0, 1, X
, X
, X
, X
, X
, X
,
802 X
, X
, X
, X
, X
, X
, X
, X
806 /* Map mips16 register numbers to normal MIPS register numbers. */
808 static const unsigned int mips16_to_32_reg_map
[] =
810 16, 17, 2, 3, 4, 5, 6, 7
813 /* Map normal MIPS register numbers to microMIPS register numbers. */
815 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
816 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
818 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
819 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
823 #define X ILLEGAL_REG
824 /* reg type h: 4, 5, 6. */
825 static const int mips32_to_micromips_reg_h_map
[] =
827 X
, X
, X
, X
, 4, 5, 6, X
,
828 X
, X
, X
, X
, X
, X
, X
, X
,
829 X
, X
, X
, X
, X
, X
, X
, X
,
830 X
, X
, X
, X
, X
, X
, X
, X
833 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
834 static const int mips32_to_micromips_reg_m_map
[] =
836 0, X
, 2, 3, X
, X
, X
, X
,
837 X
, X
, X
, X
, X
, X
, X
, X
,
838 4, 1, 5, 6, 7, X
, X
, X
,
839 X
, X
, X
, X
, X
, X
, X
, X
842 /* reg type q: 0, 2-7. 17. */
843 static const int mips32_to_micromips_reg_q_map
[] =
845 0, X
, 2, 3, 4, 5, 6, 7,
846 X
, X
, X
, X
, X
, X
, X
, X
,
847 X
, 1, X
, X
, X
, X
, X
, X
,
848 X
, X
, X
, X
, X
, X
, X
, X
851 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
854 /* Map microMIPS register numbers to normal MIPS register numbers. */
856 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
857 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
858 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
859 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
860 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
863 /* The microMIPS registers with type h. */
864 static const unsigned int micromips_to_32_reg_h_map
[] =
866 5, 5, 6, 4, 4, 4, 4, 4
869 /* The microMIPS registers with type i. */
870 static const unsigned int micromips_to_32_reg_i_map
[] =
872 6, 7, 7, 21, 22, 5, 6, 7
875 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
877 /* The microMIPS registers with type m. */
878 static const unsigned int micromips_to_32_reg_m_map
[] =
880 0, 17, 2, 3, 16, 18, 19, 20
883 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
885 /* The microMIPS registers with type q. */
886 static const unsigned int micromips_to_32_reg_q_map
[] =
888 0, 17, 2, 3, 4, 5, 6, 7
891 /* microMIPS imm type B. */
892 static const int micromips_imm_b_map
[] =
894 1, 4, 8, 12, 16, 20, 24, -1
897 /* microMIPS imm type C. */
898 static const int micromips_imm_c_map
[] =
900 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
903 /* Classifies the kind of instructions we're interested in when
904 implementing -mfix-vr4120. */
905 enum fix_vr4120_class
913 NUM_FIX_VR4120_CLASSES
916 /* ...likewise -mfix-loongson2f-jump. */
917 static bfd_boolean mips_fix_loongson2f_jump
;
919 /* ...likewise -mfix-loongson2f-nop. */
920 static bfd_boolean mips_fix_loongson2f_nop
;
922 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
923 static bfd_boolean mips_fix_loongson2f
;
925 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
926 there must be at least one other instruction between an instruction
927 of type X and an instruction of type Y. */
928 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
930 /* True if -mfix-vr4120 is in force. */
931 static int mips_fix_vr4120
;
933 /* ...likewise -mfix-vr4130. */
934 static int mips_fix_vr4130
;
936 /* ...likewise -mfix-24k. */
937 static int mips_fix_24k
;
939 /* ...likewise -mfix-cn63xxp1 */
940 static bfd_boolean mips_fix_cn63xxp1
;
942 /* We don't relax branches by default, since this causes us to expand
943 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
944 fail to compute the offset before expanding the macro to the most
945 efficient expansion. */
947 static int mips_relax_branch
;
949 /* The expansion of many macros depends on the type of symbol that
950 they refer to. For example, when generating position-dependent code,
951 a macro that refers to a symbol may have two different expansions,
952 one which uses GP-relative addresses and one which uses absolute
953 addresses. When generating SVR4-style PIC, a macro may have
954 different expansions for local and global symbols.
956 We handle these situations by generating both sequences and putting
957 them in variant frags. In position-dependent code, the first sequence
958 will be the GP-relative one and the second sequence will be the
959 absolute one. In SVR4 PIC, the first sequence will be for global
960 symbols and the second will be for local symbols.
962 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
963 SECOND are the lengths of the two sequences in bytes. These fields
964 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
965 the subtype has the following flags:
968 Set if it has been decided that we should use the second
969 sequence instead of the first.
972 Set in the first variant frag if the macro's second implementation
973 is longer than its first. This refers to the macro as a whole,
974 not an individual relaxation.
977 Set in the first variant frag if the macro appeared in a .set nomacro
978 block and if one alternative requires a warning but the other does not.
981 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
984 RELAX_DELAY_SLOT_16BIT
985 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
988 RELAX_DELAY_SLOT_SIZE_FIRST
989 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
990 the macro is of the wrong size for the branch delay slot.
992 RELAX_DELAY_SLOT_SIZE_SECOND
993 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
994 the macro is of the wrong size for the branch delay slot.
996 The frag's "opcode" points to the first fixup for relaxable code.
998 Relaxable macros are generated using a sequence such as:
1000 relax_start (SYMBOL);
1001 ... generate first expansion ...
1003 ... generate second expansion ...
1006 The code and fixups for the unwanted alternative are discarded
1007 by md_convert_frag. */
1008 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1010 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1011 #define RELAX_SECOND(X) ((X) & 0xff)
1012 #define RELAX_USE_SECOND 0x10000
1013 #define RELAX_SECOND_LONGER 0x20000
1014 #define RELAX_NOMACRO 0x40000
1015 #define RELAX_DELAY_SLOT 0x80000
1016 #define RELAX_DELAY_SLOT_16BIT 0x100000
1017 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1018 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1020 /* Branch without likely bit. If label is out of range, we turn:
1022 beq reg1, reg2, label
1032 with the following opcode replacements:
1039 bltzal <-> bgezal (with jal label instead of j label)
1041 Even though keeping the delay slot instruction in the delay slot of
1042 the branch would be more efficient, it would be very tricky to do
1043 correctly, because we'd have to introduce a variable frag *after*
1044 the delay slot instruction, and expand that instead. Let's do it
1045 the easy way for now, even if the branch-not-taken case now costs
1046 one additional instruction. Out-of-range branches are not supposed
1047 to be common, anyway.
1049 Branch likely. If label is out of range, we turn:
1051 beql reg1, reg2, label
1052 delay slot (annulled if branch not taken)
1061 delay slot (executed only if branch taken)
1064 It would be possible to generate a shorter sequence by losing the
1065 likely bit, generating something like:
1070 delay slot (executed only if branch taken)
1082 bltzall -> bgezal (with jal label instead of j label)
1083 bgezall -> bltzal (ditto)
1086 but it's not clear that it would actually improve performance. */
1087 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1088 ((relax_substateT) \
1091 | ((toofar) ? 0x20 : 0) \
1092 | ((link) ? 0x40 : 0) \
1093 | ((likely) ? 0x80 : 0) \
1094 | ((uncond) ? 0x100 : 0)))
1095 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1096 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1097 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1098 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1099 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1100 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1102 /* For mips16 code, we use an entirely different form of relaxation.
1103 mips16 supports two versions of most instructions which take
1104 immediate values: a small one which takes some small value, and a
1105 larger one which takes a 16 bit value. Since branches also follow
1106 this pattern, relaxing these values is required.
1108 We can assemble both mips16 and normal MIPS code in a single
1109 object. Therefore, we need to support this type of relaxation at
1110 the same time that we support the relaxation described above. We
1111 use the high bit of the subtype field to distinguish these cases.
1113 The information we store for this type of relaxation is the
1114 argument code found in the opcode file for this relocation, whether
1115 the user explicitly requested a small or extended form, and whether
1116 the relocation is in a jump or jal delay slot. That tells us the
1117 size of the value, and how it should be stored. We also store
1118 whether the fragment is considered to be extended or not. We also
1119 store whether this is known to be a branch to a different section,
1120 whether we have tried to relax this frag yet, and whether we have
1121 ever extended a PC relative fragment because of a shift count. */
1122 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1125 | ((small) ? 0x100 : 0) \
1126 | ((ext) ? 0x200 : 0) \
1127 | ((dslot) ? 0x400 : 0) \
1128 | ((jal_dslot) ? 0x800 : 0))
1129 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1130 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1131 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1132 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1133 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1134 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1135 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1136 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1137 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1138 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1139 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1140 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1142 /* For microMIPS code, we use relaxation similar to one we use for
1143 MIPS16 code. Some instructions that take immediate values support
1144 two encodings: a small one which takes some small value, and a
1145 larger one which takes a 16 bit value. As some branches also follow
1146 this pattern, relaxing these values is required.
1148 We can assemble both microMIPS and normal MIPS code in a single
1149 object. Therefore, we need to support this type of relaxation at
1150 the same time that we support the relaxation described above. We
1151 use one of the high bits of the subtype field to distinguish these
1154 The information we store for this type of relaxation is the argument
1155 code found in the opcode file for this relocation, the register
1156 selected as the assembler temporary, whether the branch is
1157 unconditional, whether it is compact, whether it stores the link
1158 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1159 branches to a sequence of instructions is enabled, and whether the
1160 displacement of a branch is too large to fit as an immediate argument
1161 of a 16-bit and a 32-bit branch, respectively. */
1162 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1163 relax32, toofar16, toofar32) \
1166 | (((at) & 0x1f) << 8) \
1167 | ((uncond) ? 0x2000 : 0) \
1168 | ((compact) ? 0x4000 : 0) \
1169 | ((link) ? 0x8000 : 0) \
1170 | ((relax32) ? 0x10000 : 0) \
1171 | ((toofar16) ? 0x20000 : 0) \
1172 | ((toofar32) ? 0x40000 : 0))
1173 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1174 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1175 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1176 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1177 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1178 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1179 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1181 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1182 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1183 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1184 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1185 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1186 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1188 /* Is the given value a sign-extended 32-bit value? */
1189 #define IS_SEXT_32BIT_NUM(x) \
1190 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1191 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1193 /* Is the given value a sign-extended 16-bit value? */
1194 #define IS_SEXT_16BIT_NUM(x) \
1195 (((x) &~ (offsetT) 0x7fff) == 0 \
1196 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1198 /* Is the given value a sign-extended 12-bit value? */
1199 #define IS_SEXT_12BIT_NUM(x) \
1200 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1202 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1203 #define IS_ZEXT_32BIT_NUM(x) \
1204 (((x) &~ (offsetT) 0xffffffff) == 0 \
1205 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1207 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1208 VALUE << SHIFT. VALUE is evaluated exactly once. */
1209 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1210 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1211 | (((VALUE) & (MASK)) << (SHIFT)))
1213 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1215 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1216 (((STRUCT) >> (SHIFT)) & (MASK))
1218 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1219 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1221 include/opcode/mips.h specifies operand fields using the macros
1222 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1223 with "MIPS16OP" instead of "OP". */
1224 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1227 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1228 OP_MASK_##FIELD, OP_SH_##FIELD); \
1230 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1231 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1233 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1237 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1238 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1240 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1241 : EXTRACT_BITS ((INSN).insn_opcode, \
1242 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1243 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1244 EXTRACT_BITS ((INSN).insn_opcode, \
1245 MIPS16OP_MASK_##FIELD, \
1246 MIPS16OP_SH_##FIELD)
1248 /* Whether or not we are emitting a branch-likely macro. */
1249 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1251 /* Global variables used when generating relaxable macros. See the
1252 comment above RELAX_ENCODE for more details about how relaxation
1255 /* 0 if we're not emitting a relaxable macro.
1256 1 if we're emitting the first of the two relaxation alternatives.
1257 2 if we're emitting the second alternative. */
1260 /* The first relaxable fixup in the current frag. (In other words,
1261 the first fixup that refers to relaxable code.) */
1264 /* sizes[0] says how many bytes of the first alternative are stored in
1265 the current frag. Likewise sizes[1] for the second alternative. */
1266 unsigned int sizes
[2];
1268 /* The symbol on which the choice of sequence depends. */
1272 /* Global variables used to decide whether a macro needs a warning. */
1274 /* True if the macro is in a branch delay slot. */
1275 bfd_boolean delay_slot_p
;
1277 /* Set to the length in bytes required if the macro is in a delay slot
1278 that requires a specific length of instruction, otherwise zero. */
1279 unsigned int delay_slot_length
;
1281 /* For relaxable macros, sizes[0] is the length of the first alternative
1282 in bytes and sizes[1] is the length of the second alternative.
1283 For non-relaxable macros, both elements give the length of the
1285 unsigned int sizes
[2];
1287 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1288 instruction of the first alternative in bytes and first_insn_sizes[1]
1289 is the length of the first instruction of the second alternative.
1290 For non-relaxable macros, both elements give the length of the first
1291 instruction in bytes.
1293 Set to zero if we haven't yet seen the first instruction. */
1294 unsigned int first_insn_sizes
[2];
1296 /* For relaxable macros, insns[0] is the number of instructions for the
1297 first alternative and insns[1] is the number of instructions for the
1300 For non-relaxable macros, both elements give the number of
1301 instructions for the macro. */
1302 unsigned int insns
[2];
1304 /* The first variant frag for this macro. */
1306 } mips_macro_warning
;
1308 /* Prototypes for static functions. */
1310 #define internalError() \
1311 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1313 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1315 static void append_insn
1316 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1317 bfd_boolean expansionp
);
1318 static void mips_no_prev_insn (void);
1319 static void macro_build (expressionS
*, const char *, const char *, ...);
1320 static void mips16_macro_build
1321 (expressionS
*, const char *, const char *, va_list *);
1322 static void load_register (int, expressionS
*, int);
1323 static void macro_start (void);
1324 static void macro_end (void);
1325 static void macro (struct mips_cl_insn
* ip
);
1326 static void mips16_macro (struct mips_cl_insn
* ip
);
1327 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1328 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1329 static void mips16_immed
1330 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1331 unsigned long *, bfd_boolean
*, unsigned short *);
1332 static size_t my_getSmallExpression
1333 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1334 static void my_getExpression (expressionS
*, char *);
1335 static void s_align (int);
1336 static void s_change_sec (int);
1337 static void s_change_section (int);
1338 static void s_cons (int);
1339 static void s_float_cons (int);
1340 static void s_mips_globl (int);
1341 static void s_option (int);
1342 static void s_mipsset (int);
1343 static void s_abicalls (int);
1344 static void s_cpload (int);
1345 static void s_cpsetup (int);
1346 static void s_cplocal (int);
1347 static void s_cprestore (int);
1348 static void s_cpreturn (int);
1349 static void s_dtprelword (int);
1350 static void s_dtpreldword (int);
1351 static void s_gpvalue (int);
1352 static void s_gpword (int);
1353 static void s_gpdword (int);
1354 static void s_cpadd (int);
1355 static void s_insn (int);
1356 static void md_obj_begin (void);
1357 static void md_obj_end (void);
1358 static void s_mips_ent (int);
1359 static void s_mips_end (int);
1360 static void s_mips_frame (int);
1361 static void s_mips_mask (int reg_type
);
1362 static void s_mips_stab (int);
1363 static void s_mips_weakext (int);
1364 static void s_mips_file (int);
1365 static void s_mips_loc (int);
1366 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1367 static int relaxed_branch_length (fragS
*, asection
*, int);
1368 static int validate_mips_insn (const struct mips_opcode
*);
1369 static int validate_micromips_insn (const struct mips_opcode
*);
1370 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1371 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1373 /* Table and functions used to map between CPU/ISA names, and
1374 ISA levels, and CPU numbers. */
1376 struct mips_cpu_info
1378 const char *name
; /* CPU or ISA name. */
1379 int flags
; /* ASEs available, or ISA flag. */
1380 int isa
; /* ISA level. */
1381 int cpu
; /* CPU number (default CPU if ISA). */
1384 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1385 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1386 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1387 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1388 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1389 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1390 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1392 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1393 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1394 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1398 The following pseudo-ops from the Kane and Heinrich MIPS book
1399 should be defined here, but are currently unsupported: .alias,
1400 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1402 The following pseudo-ops from the Kane and Heinrich MIPS book are
1403 specific to the type of debugging information being generated, and
1404 should be defined by the object format: .aent, .begin, .bend,
1405 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1408 The following pseudo-ops from the Kane and Heinrich MIPS book are
1409 not MIPS CPU specific, but are also not specific to the object file
1410 format. This file is probably the best place to define them, but
1411 they are not currently supported: .asm0, .endr, .lab, .struct. */
1413 static const pseudo_typeS mips_pseudo_table
[] =
1415 /* MIPS specific pseudo-ops. */
1416 {"option", s_option
, 0},
1417 {"set", s_mipsset
, 0},
1418 {"rdata", s_change_sec
, 'r'},
1419 {"sdata", s_change_sec
, 's'},
1420 {"livereg", s_ignore
, 0},
1421 {"abicalls", s_abicalls
, 0},
1422 {"cpload", s_cpload
, 0},
1423 {"cpsetup", s_cpsetup
, 0},
1424 {"cplocal", s_cplocal
, 0},
1425 {"cprestore", s_cprestore
, 0},
1426 {"cpreturn", s_cpreturn
, 0},
1427 {"dtprelword", s_dtprelword
, 0},
1428 {"dtpreldword", s_dtpreldword
, 0},
1429 {"gpvalue", s_gpvalue
, 0},
1430 {"gpword", s_gpword
, 0},
1431 {"gpdword", s_gpdword
, 0},
1432 {"cpadd", s_cpadd
, 0},
1433 {"insn", s_insn
, 0},
1435 /* Relatively generic pseudo-ops that happen to be used on MIPS
1437 {"asciiz", stringer
, 8 + 1},
1438 {"bss", s_change_sec
, 'b'},
1440 {"half", s_cons
, 1},
1441 {"dword", s_cons
, 3},
1442 {"weakext", s_mips_weakext
, 0},
1443 {"origin", s_org
, 0},
1444 {"repeat", s_rept
, 0},
1446 /* For MIPS this is non-standard, but we define it for consistency. */
1447 {"sbss", s_change_sec
, 'B'},
1449 /* These pseudo-ops are defined in read.c, but must be overridden
1450 here for one reason or another. */
1451 {"align", s_align
, 0},
1452 {"byte", s_cons
, 0},
1453 {"data", s_change_sec
, 'd'},
1454 {"double", s_float_cons
, 'd'},
1455 {"float", s_float_cons
, 'f'},
1456 {"globl", s_mips_globl
, 0},
1457 {"global", s_mips_globl
, 0},
1458 {"hword", s_cons
, 1},
1460 {"long", s_cons
, 2},
1461 {"octa", s_cons
, 4},
1462 {"quad", s_cons
, 3},
1463 {"section", s_change_section
, 0},
1464 {"short", s_cons
, 1},
1465 {"single", s_float_cons
, 'f'},
1466 {"stabn", s_mips_stab
, 'n'},
1467 {"text", s_change_sec
, 't'},
1468 {"word", s_cons
, 2},
1470 { "extern", ecoff_directive_extern
, 0},
1475 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1477 /* These pseudo-ops should be defined by the object file format.
1478 However, a.out doesn't support them, so we have versions here. */
1479 {"aent", s_mips_ent
, 1},
1480 {"bgnb", s_ignore
, 0},
1481 {"end", s_mips_end
, 0},
1482 {"endb", s_ignore
, 0},
1483 {"ent", s_mips_ent
, 0},
1484 {"file", s_mips_file
, 0},
1485 {"fmask", s_mips_mask
, 'F'},
1486 {"frame", s_mips_frame
, 0},
1487 {"loc", s_mips_loc
, 0},
1488 {"mask", s_mips_mask
, 'R'},
1489 {"verstamp", s_ignore
, 0},
1493 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1494 purpose of the `.dc.a' internal pseudo-op. */
1497 mips_address_bytes (void)
1499 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1502 extern void pop_insert (const pseudo_typeS
*);
1505 mips_pop_insert (void)
1507 pop_insert (mips_pseudo_table
);
1508 if (! ECOFF_DEBUGGING
)
1509 pop_insert (mips_nonecoff_pseudo_table
);
1512 /* Symbols labelling the current insn. */
1514 struct insn_label_list
1516 struct insn_label_list
*next
;
1520 static struct insn_label_list
*free_insn_labels
;
1521 #define label_list tc_segment_info_data.labels
1523 static void mips_clear_insn_labels (void);
1524 static void mips_mark_labels (void);
1525 static void mips_compressed_mark_labels (void);
1528 mips_clear_insn_labels (void)
1530 register struct insn_label_list
**pl
;
1531 segment_info_type
*si
;
1535 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1538 si
= seg_info (now_seg
);
1539 *pl
= si
->label_list
;
1540 si
->label_list
= NULL
;
1544 /* Mark instruction labels in MIPS16/microMIPS mode. */
1547 mips_mark_labels (void)
1549 if (HAVE_CODE_COMPRESSION
)
1550 mips_compressed_mark_labels ();
1553 static char *expr_end
;
1555 /* Expressions which appear in instructions. These are set by
1558 static expressionS imm_expr
;
1559 static expressionS imm2_expr
;
1560 static expressionS offset_expr
;
1562 /* Relocs associated with imm_expr and offset_expr. */
1564 static bfd_reloc_code_real_type imm_reloc
[3]
1565 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1566 static bfd_reloc_code_real_type offset_reloc
[3]
1567 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1569 /* This is set to the resulting size of the instruction to be produced
1570 by mips16_ip if an explicit extension is used or by mips_ip if an
1571 explicit size is supplied. */
1573 static unsigned int forced_insn_length
;
1576 /* The pdr segment for per procedure frame/regmask info. Not used for
1579 static segT pdr_seg
;
1582 /* The default target format to use. */
1584 #if defined (TE_FreeBSD)
1585 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1586 #elif defined (TE_TMIPS)
1587 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1589 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1593 mips_target_format (void)
1595 switch (OUTPUT_FLAVOR
)
1597 case bfd_target_ecoff_flavour
:
1598 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1599 case bfd_target_coff_flavour
:
1601 case bfd_target_elf_flavour
:
1603 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1604 return (target_big_endian
1605 ? "elf32-bigmips-vxworks"
1606 : "elf32-littlemips-vxworks");
1608 return (target_big_endian
1609 ? (HAVE_64BIT_OBJECTS
1610 ? ELF_TARGET ("elf64-", "big")
1612 ? ELF_TARGET ("elf32-n", "big")
1613 : ELF_TARGET ("elf32-", "big")))
1614 : (HAVE_64BIT_OBJECTS
1615 ? ELF_TARGET ("elf64-", "little")
1617 ? ELF_TARGET ("elf32-n", "little")
1618 : ELF_TARGET ("elf32-", "little"))));
1625 /* Return the length of a microMIPS instruction in bytes. If bits of
1626 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1627 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1628 major opcode) will require further modifications to the opcode
1631 static inline unsigned int
1632 micromips_insn_length (const struct mips_opcode
*mo
)
1634 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1637 /* Return the length of instruction INSN. */
1639 static inline unsigned int
1640 insn_length (const struct mips_cl_insn
*insn
)
1642 if (mips_opts
.micromips
)
1643 return micromips_insn_length (insn
->insn_mo
);
1644 else if (mips_opts
.mips16
)
1645 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1650 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1653 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1658 insn
->use_extend
= FALSE
;
1660 insn
->insn_opcode
= mo
->match
;
1663 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1664 insn
->fixp
[i
] = NULL
;
1665 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1666 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1667 insn
->mips16_absolute_jump_p
= 0;
1668 insn
->complete_p
= 0;
1671 /* Record the current MIPS16/microMIPS mode in now_seg. */
1674 mips_record_compressed_mode (void)
1676 segment_info_type
*si
;
1678 si
= seg_info (now_seg
);
1679 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1680 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1681 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1682 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1685 /* Install INSN at the location specified by its "frag" and "where" fields. */
1688 install_insn (const struct mips_cl_insn
*insn
)
1690 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1691 if (!HAVE_CODE_COMPRESSION
)
1692 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1693 else if (mips_opts
.micromips
)
1695 unsigned int length
= insn_length (insn
);
1697 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1698 else if (length
== 4)
1700 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1702 md_number_to_chars (f
, insn
->insn_opcode
& 0xffff, 2);
1705 as_bad (_("48-bit microMIPS instructions are not supported"));
1707 else if (insn
->mips16_absolute_jump_p
)
1709 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1710 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1714 if (insn
->use_extend
)
1716 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1719 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1721 mips_record_compressed_mode ();
1724 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1725 and install the opcode in the new location. */
1728 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1733 insn
->where
= where
;
1734 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1735 if (insn
->fixp
[i
] != NULL
)
1737 insn
->fixp
[i
]->fx_frag
= frag
;
1738 insn
->fixp
[i
]->fx_where
= where
;
1740 install_insn (insn
);
1743 /* Add INSN to the end of the output. */
1746 add_fixed_insn (struct mips_cl_insn
*insn
)
1748 char *f
= frag_more (insn_length (insn
));
1749 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1752 /* Start a variant frag and move INSN to the start of the variant part,
1753 marking it as fixed. The other arguments are as for frag_var. */
1756 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1757 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1759 frag_grow (max_chars
);
1760 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1762 frag_var (rs_machine_dependent
, max_chars
, var
,
1763 subtype
, symbol
, offset
, NULL
);
1766 /* Insert N copies of INSN into the history buffer, starting at
1767 position FIRST. Neither FIRST nor N need to be clipped. */
1770 insert_into_history (unsigned int first
, unsigned int n
,
1771 const struct mips_cl_insn
*insn
)
1773 if (mips_relax
.sequence
!= 2)
1777 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1779 history
[i
] = history
[i
- n
];
1785 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1786 the idea is to make it obvious at a glance that each errata is
1790 init_vr4120_conflicts (void)
1792 #define CONFLICT(FIRST, SECOND) \
1793 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1795 /* Errata 21 - [D]DIV[U] after [D]MACC */
1796 CONFLICT (MACC
, DIV
);
1797 CONFLICT (DMACC
, DIV
);
1799 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1800 CONFLICT (DMULT
, DMULT
);
1801 CONFLICT (DMULT
, DMACC
);
1802 CONFLICT (DMACC
, DMULT
);
1803 CONFLICT (DMACC
, DMACC
);
1805 /* Errata 24 - MT{LO,HI} after [D]MACC */
1806 CONFLICT (MACC
, MTHILO
);
1807 CONFLICT (DMACC
, MTHILO
);
1809 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1810 instruction is executed immediately after a MACC or DMACC
1811 instruction, the result of [either instruction] is incorrect." */
1812 CONFLICT (MACC
, MULT
);
1813 CONFLICT (MACC
, DMULT
);
1814 CONFLICT (DMACC
, MULT
);
1815 CONFLICT (DMACC
, DMULT
);
1817 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1818 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1819 DDIV or DDIVU instruction, the result of the MACC or
1820 DMACC instruction is incorrect.". */
1821 CONFLICT (DMULT
, MACC
);
1822 CONFLICT (DMULT
, DMACC
);
1823 CONFLICT (DIV
, MACC
);
1824 CONFLICT (DIV
, DMACC
);
1834 #define RTYPE_MASK 0x1ff00
1835 #define RTYPE_NUM 0x00100
1836 #define RTYPE_FPU 0x00200
1837 #define RTYPE_FCC 0x00400
1838 #define RTYPE_VEC 0x00800
1839 #define RTYPE_GP 0x01000
1840 #define RTYPE_CP0 0x02000
1841 #define RTYPE_PC 0x04000
1842 #define RTYPE_ACC 0x08000
1843 #define RTYPE_CCC 0x10000
1844 #define RNUM_MASK 0x000ff
1845 #define RWARN 0x80000
1847 #define GENERIC_REGISTER_NUMBERS \
1848 {"$0", RTYPE_NUM | 0}, \
1849 {"$1", RTYPE_NUM | 1}, \
1850 {"$2", RTYPE_NUM | 2}, \
1851 {"$3", RTYPE_NUM | 3}, \
1852 {"$4", RTYPE_NUM | 4}, \
1853 {"$5", RTYPE_NUM | 5}, \
1854 {"$6", RTYPE_NUM | 6}, \
1855 {"$7", RTYPE_NUM | 7}, \
1856 {"$8", RTYPE_NUM | 8}, \
1857 {"$9", RTYPE_NUM | 9}, \
1858 {"$10", RTYPE_NUM | 10}, \
1859 {"$11", RTYPE_NUM | 11}, \
1860 {"$12", RTYPE_NUM | 12}, \
1861 {"$13", RTYPE_NUM | 13}, \
1862 {"$14", RTYPE_NUM | 14}, \
1863 {"$15", RTYPE_NUM | 15}, \
1864 {"$16", RTYPE_NUM | 16}, \
1865 {"$17", RTYPE_NUM | 17}, \
1866 {"$18", RTYPE_NUM | 18}, \
1867 {"$19", RTYPE_NUM | 19}, \
1868 {"$20", RTYPE_NUM | 20}, \
1869 {"$21", RTYPE_NUM | 21}, \
1870 {"$22", RTYPE_NUM | 22}, \
1871 {"$23", RTYPE_NUM | 23}, \
1872 {"$24", RTYPE_NUM | 24}, \
1873 {"$25", RTYPE_NUM | 25}, \
1874 {"$26", RTYPE_NUM | 26}, \
1875 {"$27", RTYPE_NUM | 27}, \
1876 {"$28", RTYPE_NUM | 28}, \
1877 {"$29", RTYPE_NUM | 29}, \
1878 {"$30", RTYPE_NUM | 30}, \
1879 {"$31", RTYPE_NUM | 31}
1881 #define FPU_REGISTER_NAMES \
1882 {"$f0", RTYPE_FPU | 0}, \
1883 {"$f1", RTYPE_FPU | 1}, \
1884 {"$f2", RTYPE_FPU | 2}, \
1885 {"$f3", RTYPE_FPU | 3}, \
1886 {"$f4", RTYPE_FPU | 4}, \
1887 {"$f5", RTYPE_FPU | 5}, \
1888 {"$f6", RTYPE_FPU | 6}, \
1889 {"$f7", RTYPE_FPU | 7}, \
1890 {"$f8", RTYPE_FPU | 8}, \
1891 {"$f9", RTYPE_FPU | 9}, \
1892 {"$f10", RTYPE_FPU | 10}, \
1893 {"$f11", RTYPE_FPU | 11}, \
1894 {"$f12", RTYPE_FPU | 12}, \
1895 {"$f13", RTYPE_FPU | 13}, \
1896 {"$f14", RTYPE_FPU | 14}, \
1897 {"$f15", RTYPE_FPU | 15}, \
1898 {"$f16", RTYPE_FPU | 16}, \
1899 {"$f17", RTYPE_FPU | 17}, \
1900 {"$f18", RTYPE_FPU | 18}, \
1901 {"$f19", RTYPE_FPU | 19}, \
1902 {"$f20", RTYPE_FPU | 20}, \
1903 {"$f21", RTYPE_FPU | 21}, \
1904 {"$f22", RTYPE_FPU | 22}, \
1905 {"$f23", RTYPE_FPU | 23}, \
1906 {"$f24", RTYPE_FPU | 24}, \
1907 {"$f25", RTYPE_FPU | 25}, \
1908 {"$f26", RTYPE_FPU | 26}, \
1909 {"$f27", RTYPE_FPU | 27}, \
1910 {"$f28", RTYPE_FPU | 28}, \
1911 {"$f29", RTYPE_FPU | 29}, \
1912 {"$f30", RTYPE_FPU | 30}, \
1913 {"$f31", RTYPE_FPU | 31}
1915 #define FPU_CONDITION_CODE_NAMES \
1916 {"$fcc0", RTYPE_FCC | 0}, \
1917 {"$fcc1", RTYPE_FCC | 1}, \
1918 {"$fcc2", RTYPE_FCC | 2}, \
1919 {"$fcc3", RTYPE_FCC | 3}, \
1920 {"$fcc4", RTYPE_FCC | 4}, \
1921 {"$fcc5", RTYPE_FCC | 5}, \
1922 {"$fcc6", RTYPE_FCC | 6}, \
1923 {"$fcc7", RTYPE_FCC | 7}
1925 #define COPROC_CONDITION_CODE_NAMES \
1926 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1927 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1928 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1929 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1930 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1931 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1932 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1933 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1935 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1936 {"$a4", RTYPE_GP | 8}, \
1937 {"$a5", RTYPE_GP | 9}, \
1938 {"$a6", RTYPE_GP | 10}, \
1939 {"$a7", RTYPE_GP | 11}, \
1940 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1941 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1942 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1943 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1944 {"$t0", RTYPE_GP | 12}, \
1945 {"$t1", RTYPE_GP | 13}, \
1946 {"$t2", RTYPE_GP | 14}, \
1947 {"$t3", RTYPE_GP | 15}
1949 #define O32_SYMBOLIC_REGISTER_NAMES \
1950 {"$t0", RTYPE_GP | 8}, \
1951 {"$t1", RTYPE_GP | 9}, \
1952 {"$t2", RTYPE_GP | 10}, \
1953 {"$t3", RTYPE_GP | 11}, \
1954 {"$t4", RTYPE_GP | 12}, \
1955 {"$t5", RTYPE_GP | 13}, \
1956 {"$t6", RTYPE_GP | 14}, \
1957 {"$t7", RTYPE_GP | 15}, \
1958 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1959 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1960 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1961 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1963 /* Remaining symbolic register names */
1964 #define SYMBOLIC_REGISTER_NAMES \
1965 {"$zero", RTYPE_GP | 0}, \
1966 {"$at", RTYPE_GP | 1}, \
1967 {"$AT", RTYPE_GP | 1}, \
1968 {"$v0", RTYPE_GP | 2}, \
1969 {"$v1", RTYPE_GP | 3}, \
1970 {"$a0", RTYPE_GP | 4}, \
1971 {"$a1", RTYPE_GP | 5}, \
1972 {"$a2", RTYPE_GP | 6}, \
1973 {"$a3", RTYPE_GP | 7}, \
1974 {"$s0", RTYPE_GP | 16}, \
1975 {"$s1", RTYPE_GP | 17}, \
1976 {"$s2", RTYPE_GP | 18}, \
1977 {"$s3", RTYPE_GP | 19}, \
1978 {"$s4", RTYPE_GP | 20}, \
1979 {"$s5", RTYPE_GP | 21}, \
1980 {"$s6", RTYPE_GP | 22}, \
1981 {"$s7", RTYPE_GP | 23}, \
1982 {"$t8", RTYPE_GP | 24}, \
1983 {"$t9", RTYPE_GP | 25}, \
1984 {"$k0", RTYPE_GP | 26}, \
1985 {"$kt0", RTYPE_GP | 26}, \
1986 {"$k1", RTYPE_GP | 27}, \
1987 {"$kt1", RTYPE_GP | 27}, \
1988 {"$gp", RTYPE_GP | 28}, \
1989 {"$sp", RTYPE_GP | 29}, \
1990 {"$s8", RTYPE_GP | 30}, \
1991 {"$fp", RTYPE_GP | 30}, \
1992 {"$ra", RTYPE_GP | 31}
1994 #define MIPS16_SPECIAL_REGISTER_NAMES \
1995 {"$pc", RTYPE_PC | 0}
1997 #define MDMX_VECTOR_REGISTER_NAMES \
1998 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1999 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2000 {"$v2", RTYPE_VEC | 2}, \
2001 {"$v3", RTYPE_VEC | 3}, \
2002 {"$v4", RTYPE_VEC | 4}, \
2003 {"$v5", RTYPE_VEC | 5}, \
2004 {"$v6", RTYPE_VEC | 6}, \
2005 {"$v7", RTYPE_VEC | 7}, \
2006 {"$v8", RTYPE_VEC | 8}, \
2007 {"$v9", RTYPE_VEC | 9}, \
2008 {"$v10", RTYPE_VEC | 10}, \
2009 {"$v11", RTYPE_VEC | 11}, \
2010 {"$v12", RTYPE_VEC | 12}, \
2011 {"$v13", RTYPE_VEC | 13}, \
2012 {"$v14", RTYPE_VEC | 14}, \
2013 {"$v15", RTYPE_VEC | 15}, \
2014 {"$v16", RTYPE_VEC | 16}, \
2015 {"$v17", RTYPE_VEC | 17}, \
2016 {"$v18", RTYPE_VEC | 18}, \
2017 {"$v19", RTYPE_VEC | 19}, \
2018 {"$v20", RTYPE_VEC | 20}, \
2019 {"$v21", RTYPE_VEC | 21}, \
2020 {"$v22", RTYPE_VEC | 22}, \
2021 {"$v23", RTYPE_VEC | 23}, \
2022 {"$v24", RTYPE_VEC | 24}, \
2023 {"$v25", RTYPE_VEC | 25}, \
2024 {"$v26", RTYPE_VEC | 26}, \
2025 {"$v27", RTYPE_VEC | 27}, \
2026 {"$v28", RTYPE_VEC | 28}, \
2027 {"$v29", RTYPE_VEC | 29}, \
2028 {"$v30", RTYPE_VEC | 30}, \
2029 {"$v31", RTYPE_VEC | 31}
2031 #define MIPS_DSP_ACCUMULATOR_NAMES \
2032 {"$ac0", RTYPE_ACC | 0}, \
2033 {"$ac1", RTYPE_ACC | 1}, \
2034 {"$ac2", RTYPE_ACC | 2}, \
2035 {"$ac3", RTYPE_ACC | 3}
2037 static const struct regname reg_names
[] = {
2038 GENERIC_REGISTER_NUMBERS
,
2040 FPU_CONDITION_CODE_NAMES
,
2041 COPROC_CONDITION_CODE_NAMES
,
2043 /* The $txx registers depends on the abi,
2044 these will be added later into the symbol table from
2045 one of the tables below once mips_abi is set after
2046 parsing of arguments from the command line. */
2047 SYMBOLIC_REGISTER_NAMES
,
2049 MIPS16_SPECIAL_REGISTER_NAMES
,
2050 MDMX_VECTOR_REGISTER_NAMES
,
2051 MIPS_DSP_ACCUMULATOR_NAMES
,
2055 static const struct regname reg_names_o32
[] = {
2056 O32_SYMBOLIC_REGISTER_NAMES
,
2060 static const struct regname reg_names_n32n64
[] = {
2061 N32N64_SYMBOLIC_REGISTER_NAMES
,
2065 /* Check if S points at a valid register specifier according to TYPES.
2066 If so, then return 1, advance S to consume the specifier and store
2067 the register's number in REGNOP, otherwise return 0. */
2070 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2077 /* Find end of name. */
2079 if (is_name_beginner (*e
))
2081 while (is_part_of_name (*e
))
2084 /* Terminate name. */
2088 /* Look for a register symbol. */
2089 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2091 int r
= S_GET_VALUE (symbolP
);
2093 reg
= r
& RNUM_MASK
;
2094 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2095 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2096 reg
= (r
& RNUM_MASK
) - 2;
2098 /* Else see if this is a register defined in an itbl entry. */
2099 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2106 if (itbl_get_reg_val (n
, &r
))
2107 reg
= r
& RNUM_MASK
;
2110 /* Advance to next token if a register was recognised. */
2113 else if (types
& RWARN
)
2114 as_warn (_("Unrecognized register name `%s'"), *s
);
2122 /* Check if S points at a valid register list according to TYPES.
2123 If so, then return 1, advance S to consume the list and store
2124 the registers present on the list as a bitmask of ones in REGLISTP,
2125 otherwise return 0. A valid list comprises a comma-separated
2126 enumeration of valid single registers and/or dash-separated
2127 contiguous register ranges as determined by their numbers.
2129 As a special exception if one of s0-s7 registers is specified as
2130 the range's lower delimiter and s8 (fp) is its upper one, then no
2131 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2132 are selected; they have to be listed separately if needed. */
2135 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2137 unsigned int reglist
= 0;
2138 unsigned int lastregno
;
2139 bfd_boolean ok
= TRUE
;
2140 unsigned int regmask
;
2141 char *s_endlist
= *s
;
2145 while (reg_lookup (s
, types
, ®no
))
2151 ok
= reg_lookup (s
, types
, &lastregno
);
2152 if (ok
&& lastregno
< regno
)
2158 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2163 regmask
= 1 << lastregno
;
2164 regmask
= (regmask
<< 1) - 1;
2165 regmask
^= (1 << regno
) - 1;
2179 *reglistp
= reglist
;
2180 return ok
&& reglist
!= 0;
2183 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2184 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2187 is_opcode_valid (const struct mips_opcode
*mo
)
2189 int isa
= mips_opts
.isa
;
2192 if (mips_opts
.ase_mdmx
)
2194 if (mips_opts
.ase_dsp
)
2196 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2198 if (mips_opts
.ase_dspr2
)
2200 if (mips_opts
.ase_mt
)
2202 if (mips_opts
.ase_mips3d
)
2204 if (mips_opts
.ase_smartmips
)
2205 isa
|= INSN_SMARTMIPS
;
2207 /* Don't accept instructions based on the ISA if the CPU does not implement
2208 all the coprocessor insns. */
2209 if (NO_ISA_COP (mips_opts
.arch
)
2210 && COP_INSN (mo
->pinfo
))
2213 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
2216 /* Check whether the instruction or macro requires single-precision or
2217 double-precision floating-point support. Note that this information is
2218 stored differently in the opcode table for insns and macros. */
2219 if (mo
->pinfo
== INSN_MACRO
)
2221 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2222 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2226 fp_s
= mo
->pinfo
& FP_S
;
2227 fp_d
= mo
->pinfo
& FP_D
;
2230 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2233 if (fp_s
&& mips_opts
.soft_float
)
2239 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2240 selected ISA and architecture. */
2243 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2245 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
2248 /* Return TRUE if the size of the microMIPS opcode MO matches one
2249 explicitly requested. Always TRUE in the standard MIPS mode. */
2252 is_size_valid (const struct mips_opcode
*mo
)
2254 if (!mips_opts
.micromips
)
2257 if (!forced_insn_length
)
2259 if (mo
->pinfo
== INSN_MACRO
)
2261 return forced_insn_length
== micromips_insn_length (mo
);
2264 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2265 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2268 is_delay_slot_valid (const struct mips_opcode
*mo
)
2270 if (!mips_opts
.micromips
)
2273 if (mo
->pinfo
== INSN_MACRO
)
2275 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2276 && micromips_insn_length (mo
) != 4)
2278 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2279 && micromips_insn_length (mo
) != 2)
2285 /* This function is called once, at assembler startup time. It should set up
2286 all the tables, etc. that the MD part of the assembler will need. */
2291 const char *retval
= NULL
;
2295 if (mips_pic
!= NO_PIC
)
2297 if (g_switch_seen
&& g_switch_value
!= 0)
2298 as_bad (_("-G may not be used in position-independent code"));
2302 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2303 as_warn (_("Could not set architecture and machine"));
2305 op_hash
= hash_new ();
2307 for (i
= 0; i
< NUMOPCODES
;)
2309 const char *name
= mips_opcodes
[i
].name
;
2311 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2314 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2315 mips_opcodes
[i
].name
, retval
);
2316 /* Probably a memory allocation problem? Give up now. */
2317 as_fatal (_("Broken assembler. No assembly attempted."));
2321 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2323 if (!validate_mips_insn (&mips_opcodes
[i
]))
2325 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2327 create_insn (&nop_insn
, mips_opcodes
+ i
);
2328 if (mips_fix_loongson2f_nop
)
2329 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2330 nop_insn
.fixed_p
= 1;
2335 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2338 mips16_op_hash
= hash_new ();
2341 while (i
< bfd_mips16_num_opcodes
)
2343 const char *name
= mips16_opcodes
[i
].name
;
2345 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2347 as_fatal (_("internal: can't hash `%s': %s"),
2348 mips16_opcodes
[i
].name
, retval
);
2351 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2352 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2353 != mips16_opcodes
[i
].match
))
2355 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2356 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2359 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2361 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2362 mips16_nop_insn
.fixed_p
= 1;
2366 while (i
< bfd_mips16_num_opcodes
2367 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2370 micromips_op_hash
= hash_new ();
2373 while (i
< bfd_micromips_num_opcodes
)
2375 const char *name
= micromips_opcodes
[i
].name
;
2377 retval
= hash_insert (micromips_op_hash
, name
,
2378 (void *) µmips_opcodes
[i
]);
2380 as_fatal (_("internal: can't hash `%s': %s"),
2381 micromips_opcodes
[i
].name
, retval
);
2383 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2385 struct mips_cl_insn
*micromips_nop_insn
;
2387 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2390 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2391 micromips_nop_insn
= µmips_nop16_insn
;
2392 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2393 micromips_nop_insn
= µmips_nop32_insn
;
2397 if (micromips_nop_insn
->insn_mo
== NULL
2398 && strcmp (name
, "nop") == 0)
2400 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2401 micromips_nop_insn
->fixed_p
= 1;
2404 while (++i
< bfd_micromips_num_opcodes
2405 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2409 as_fatal (_("Broken assembler. No assembly attempted."));
2411 /* We add all the general register names to the symbol table. This
2412 helps us detect invalid uses of them. */
2413 for (i
= 0; reg_names
[i
].name
; i
++)
2414 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2415 reg_names
[i
].num
, /* & RNUM_MASK, */
2416 &zero_address_frag
));
2418 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2419 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2420 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2421 &zero_address_frag
));
2423 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2424 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2425 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2426 &zero_address_frag
));
2428 mips_no_prev_insn ();
2431 mips_cprmask
[0] = 0;
2432 mips_cprmask
[1] = 0;
2433 mips_cprmask
[2] = 0;
2434 mips_cprmask
[3] = 0;
2436 /* set the default alignment for the text section (2**2) */
2437 record_alignment (text_section
, 2);
2439 bfd_set_gp_size (stdoutput
, g_switch_value
);
2444 /* On a native system other than VxWorks, sections must be aligned
2445 to 16 byte boundaries. When configured for an embedded ELF
2446 target, we don't bother. */
2447 if (strncmp (TARGET_OS
, "elf", 3) != 0
2448 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2450 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2451 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2452 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2455 /* Create a .reginfo section for register masks and a .mdebug
2456 section for debugging information. */
2464 subseg
= now_subseg
;
2466 /* The ABI says this section should be loaded so that the
2467 running program can access it. However, we don't load it
2468 if we are configured for an embedded target */
2469 flags
= SEC_READONLY
| SEC_DATA
;
2470 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2471 flags
|= SEC_ALLOC
| SEC_LOAD
;
2473 if (mips_abi
!= N64_ABI
)
2475 sec
= subseg_new (".reginfo", (subsegT
) 0);
2477 bfd_set_section_flags (stdoutput
, sec
, flags
);
2478 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2480 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2484 /* The 64-bit ABI uses a .MIPS.options section rather than
2485 .reginfo section. */
2486 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2487 bfd_set_section_flags (stdoutput
, sec
, flags
);
2488 bfd_set_section_alignment (stdoutput
, sec
, 3);
2490 /* Set up the option header. */
2492 Elf_Internal_Options opthdr
;
2495 opthdr
.kind
= ODK_REGINFO
;
2496 opthdr
.size
= (sizeof (Elf_External_Options
)
2497 + sizeof (Elf64_External_RegInfo
));
2500 f
= frag_more (sizeof (Elf_External_Options
));
2501 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2502 (Elf_External_Options
*) f
);
2504 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2508 if (ECOFF_DEBUGGING
)
2510 sec
= subseg_new (".mdebug", (subsegT
) 0);
2511 (void) bfd_set_section_flags (stdoutput
, sec
,
2512 SEC_HAS_CONTENTS
| SEC_READONLY
);
2513 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2515 else if (mips_flag_pdr
)
2517 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2518 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2519 SEC_READONLY
| SEC_RELOC
2521 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2524 subseg_set (seg
, subseg
);
2527 #endif /* OBJ_ELF */
2529 if (! ECOFF_DEBUGGING
)
2532 if (mips_fix_vr4120
)
2533 init_vr4120_conflicts ();
2539 mips_emit_delays ();
2540 if (! ECOFF_DEBUGGING
)
2545 md_assemble (char *str
)
2547 struct mips_cl_insn insn
;
2548 bfd_reloc_code_real_type unused_reloc
[3]
2549 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2551 imm_expr
.X_op
= O_absent
;
2552 imm2_expr
.X_op
= O_absent
;
2553 offset_expr
.X_op
= O_absent
;
2554 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2555 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2556 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2557 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2558 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2559 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2561 if (mips_opts
.mips16
)
2562 mips16_ip (str
, &insn
);
2565 mips_ip (str
, &insn
);
2566 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2567 str
, insn
.insn_opcode
));
2572 as_bad ("%s `%s'", insn_error
, str
);
2576 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2579 if (mips_opts
.mips16
)
2580 mips16_macro (&insn
);
2587 if (imm_expr
.X_op
!= O_absent
)
2588 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2589 else if (offset_expr
.X_op
!= O_absent
)
2590 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2592 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2596 /* Convenience functions for abstracting away the differences between
2597 MIPS16 and non-MIPS16 relocations. */
2599 static inline bfd_boolean
2600 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2604 case BFD_RELOC_MIPS16_JMP
:
2605 case BFD_RELOC_MIPS16_GPREL
:
2606 case BFD_RELOC_MIPS16_GOT16
:
2607 case BFD_RELOC_MIPS16_CALL16
:
2608 case BFD_RELOC_MIPS16_HI16_S
:
2609 case BFD_RELOC_MIPS16_HI16
:
2610 case BFD_RELOC_MIPS16_LO16
:
2618 static inline bfd_boolean
2619 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2623 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2624 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2625 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2626 case BFD_RELOC_MICROMIPS_GPREL16
:
2627 case BFD_RELOC_MICROMIPS_JMP
:
2628 case BFD_RELOC_MICROMIPS_HI16
:
2629 case BFD_RELOC_MICROMIPS_HI16_S
:
2630 case BFD_RELOC_MICROMIPS_LO16
:
2631 case BFD_RELOC_MICROMIPS_LITERAL
:
2632 case BFD_RELOC_MICROMIPS_GOT16
:
2633 case BFD_RELOC_MICROMIPS_CALL16
:
2634 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2635 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2636 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2637 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2638 case BFD_RELOC_MICROMIPS_SUB
:
2639 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2640 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2641 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2642 case BFD_RELOC_MICROMIPS_HIGHEST
:
2643 case BFD_RELOC_MICROMIPS_HIGHER
:
2644 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2645 case BFD_RELOC_MICROMIPS_JALR
:
2653 static inline bfd_boolean
2654 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2656 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2659 static inline bfd_boolean
2660 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2662 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2663 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2666 static inline bfd_boolean
2667 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2669 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2670 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2673 static inline bfd_boolean
2674 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2676 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2677 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2680 static inline bfd_boolean
2681 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2683 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2686 /* Return true if the given relocation might need a matching %lo().
2687 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2688 need a matching %lo() when applied to local symbols. */
2690 static inline bfd_boolean
2691 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2693 return (HAVE_IN_PLACE_ADDENDS
2694 && (hi16_reloc_p (reloc
)
2695 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2696 all GOT16 relocations evaluate to "G". */
2697 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2700 /* Return the type of %lo() reloc needed by RELOC, given that
2701 reloc_needs_lo_p. */
2703 static inline bfd_reloc_code_real_type
2704 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2706 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2707 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2711 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2714 static inline bfd_boolean
2715 fixup_has_matching_lo_p (fixS
*fixp
)
2717 return (fixp
->fx_next
!= NULL
2718 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2719 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2720 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2723 /* This function returns true if modifying a register requires a
2727 reg_needs_delay (unsigned int reg
)
2729 unsigned long prev_pinfo
;
2731 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2732 if (! mips_opts
.noreorder
2733 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2734 && ! gpr_interlocks
)
2735 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2736 && ! cop_interlocks
)))
2738 /* A load from a coprocessor or from memory. All load delays
2739 delay the use of general register rt for one instruction. */
2740 /* Itbl support may require additional care here. */
2741 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2742 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2749 /* Move all labels in insn_labels to the current insertion point. */
2752 mips_move_labels (void)
2754 segment_info_type
*si
= seg_info (now_seg
);
2755 struct insn_label_list
*l
;
2758 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2760 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2761 symbol_set_frag (l
->label
, frag_now
);
2762 val
= (valueT
) frag_now_fix ();
2763 /* MIPS16/microMIPS text labels are stored as odd. */
2764 if (HAVE_CODE_COMPRESSION
)
2766 S_SET_VALUE (l
->label
, val
);
2771 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2773 bfd_boolean linkonce
= FALSE
;
2774 segT symseg
= S_GET_SEGMENT (sym
);
2776 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2778 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2781 /* The GNU toolchain uses an extension for ELF: a section
2782 beginning with the magic string .gnu.linkonce is a
2783 linkonce section. */
2784 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2785 sizeof ".gnu.linkonce" - 1) == 0)
2792 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2793 linker to handle them specially, such as generating jalx instructions
2794 when needed. We also make them odd for the duration of the assembly,
2795 in order to generate the right sort of code. We will make them even
2796 in the adjust_symtab routine, while leaving them marked. This is
2797 convenient for the debugger and the disassembler. The linker knows
2798 to make them odd again. */
2801 mips_compressed_mark_labels (void)
2803 segment_info_type
*si
= seg_info (now_seg
);
2804 struct insn_label_list
*l
;
2806 gas_assert (HAVE_CODE_COMPRESSION
);
2808 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2810 symbolS
*label
= l
->label
;
2812 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2815 if (mips_opts
.mips16
)
2816 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2818 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2821 if ((S_GET_VALUE (label
) & 1) == 0
2822 /* Don't adjust the address if the label is global or weak, or
2823 in a link-once section, since we'll be emitting symbol reloc
2824 references to it which will be patched up by the linker, and
2825 the final value of the symbol may or may not be MIPS16/microMIPS. */
2826 && ! S_IS_WEAK (label
)
2827 && ! S_IS_EXTERNAL (label
)
2828 && ! s_is_linkonce (label
, now_seg
))
2829 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2833 /* End the current frag. Make it a variant frag and record the
2837 relax_close_frag (void)
2839 mips_macro_warning
.first_frag
= frag_now
;
2840 frag_var (rs_machine_dependent
, 0, 0,
2841 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2842 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2844 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2845 mips_relax
.first_fixup
= 0;
2848 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2849 See the comment above RELAX_ENCODE for more details. */
2852 relax_start (symbolS
*symbol
)
2854 gas_assert (mips_relax
.sequence
== 0);
2855 mips_relax
.sequence
= 1;
2856 mips_relax
.symbol
= symbol
;
2859 /* Start generating the second version of a relaxable sequence.
2860 See the comment above RELAX_ENCODE for more details. */
2865 gas_assert (mips_relax
.sequence
== 1);
2866 mips_relax
.sequence
= 2;
2869 /* End the current relaxable sequence. */
2874 gas_assert (mips_relax
.sequence
== 2);
2875 relax_close_frag ();
2876 mips_relax
.sequence
= 0;
2879 /* Return true if IP is a delayed branch or jump. */
2881 static inline bfd_boolean
2882 delayed_branch_p (const struct mips_cl_insn
*ip
)
2884 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2885 | INSN_COND_BRANCH_DELAY
2886 | INSN_COND_BRANCH_LIKELY
)) != 0;
2889 /* Return true if IP is a compact branch or jump. */
2891 static inline bfd_boolean
2892 compact_branch_p (const struct mips_cl_insn
*ip
)
2894 if (mips_opts
.mips16
)
2895 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2896 | MIPS16_INSN_COND_BRANCH
)) != 0;
2898 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2899 | INSN2_COND_BRANCH
)) != 0;
2902 /* Return true if IP is an unconditional branch or jump. */
2904 static inline bfd_boolean
2905 uncond_branch_p (const struct mips_cl_insn
*ip
)
2907 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
2908 || (mips_opts
.mips16
2909 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
2910 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
2913 /* Return true if IP is a branch-likely instruction. */
2915 static inline bfd_boolean
2916 branch_likely_p (const struct mips_cl_insn
*ip
)
2918 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
2921 /* Return the type of nop that should be used to fill the delay slot
2922 of delayed branch IP. */
2924 static struct mips_cl_insn
*
2925 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
2927 if (mips_opts
.micromips
2928 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
2929 return µmips_nop32_insn
;
2933 /* Return the mask of core registers that IP reads or writes. */
2936 gpr_mod_mask (const struct mips_cl_insn
*ip
)
2938 unsigned long pinfo2
;
2942 pinfo2
= ip
->insn_mo
->pinfo2
;
2943 if (mips_opts
.micromips
)
2945 if (pinfo2
& INSN2_MOD_GPR_MD
)
2946 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
2947 if (pinfo2
& INSN2_MOD_GPR_MF
)
2948 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
2949 if (pinfo2
& INSN2_MOD_SP
)
2955 /* Return the mask of core registers that IP reads. */
2958 gpr_read_mask (const struct mips_cl_insn
*ip
)
2960 unsigned long pinfo
, pinfo2
;
2963 mask
= gpr_mod_mask (ip
);
2964 pinfo
= ip
->insn_mo
->pinfo
;
2965 pinfo2
= ip
->insn_mo
->pinfo2
;
2966 if (mips_opts
.mips16
)
2968 if (pinfo
& MIPS16_INSN_READ_X
)
2969 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
2970 if (pinfo
& MIPS16_INSN_READ_Y
)
2971 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
2972 if (pinfo
& MIPS16_INSN_READ_T
)
2974 if (pinfo
& MIPS16_INSN_READ_SP
)
2976 if (pinfo
& MIPS16_INSN_READ_31
)
2978 if (pinfo
& MIPS16_INSN_READ_Z
)
2979 mask
|= 1 << (mips16_to_32_reg_map
2980 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
2981 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2982 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2986 if (pinfo2
& INSN2_READ_GPR_D
)
2987 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
2988 if (pinfo
& INSN_READ_GPR_T
)
2989 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
2990 if (pinfo
& INSN_READ_GPR_S
)
2991 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
2992 if (pinfo2
& INSN2_READ_GP
)
2994 if (pinfo2
& INSN2_READ_GPR_31
)
2996 if (pinfo2
& INSN2_READ_GPR_Z
)
2997 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
2999 if (mips_opts
.micromips
)
3001 if (pinfo2
& INSN2_READ_GPR_MC
)
3002 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3003 if (pinfo2
& INSN2_READ_GPR_ME
)
3004 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3005 if (pinfo2
& INSN2_READ_GPR_MG
)
3006 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3007 if (pinfo2
& INSN2_READ_GPR_MJ
)
3008 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3009 if (pinfo2
& INSN2_READ_GPR_MMN
)
3011 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3012 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3014 if (pinfo2
& INSN2_READ_GPR_MP
)
3015 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3016 if (pinfo2
& INSN2_READ_GPR_MQ
)
3017 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3019 /* Don't include register 0. */
3023 /* Return the mask of core registers that IP writes. */
3026 gpr_write_mask (const struct mips_cl_insn
*ip
)
3028 unsigned long pinfo
, pinfo2
;
3031 mask
= gpr_mod_mask (ip
);
3032 pinfo
= ip
->insn_mo
->pinfo
;
3033 pinfo2
= ip
->insn_mo
->pinfo2
;
3034 if (mips_opts
.mips16
)
3036 if (pinfo
& MIPS16_INSN_WRITE_X
)
3037 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3038 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3039 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3040 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3041 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3042 if (pinfo
& MIPS16_INSN_WRITE_T
)
3044 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3046 if (pinfo
& MIPS16_INSN_WRITE_31
)
3048 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3049 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3053 if (pinfo
& INSN_WRITE_GPR_D
)
3054 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3055 if (pinfo
& INSN_WRITE_GPR_T
)
3056 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3057 if (pinfo
& INSN_WRITE_GPR_S
)
3058 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3059 if (pinfo
& INSN_WRITE_GPR_31
)
3061 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3062 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3064 if (mips_opts
.micromips
)
3066 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3067 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3068 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3070 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3071 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3073 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3074 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3075 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3076 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3078 /* Don't include register 0. */
3082 /* Return the mask of floating-point registers that IP reads. */
3085 fpr_read_mask (const struct mips_cl_insn
*ip
)
3087 unsigned long pinfo
, pinfo2
;
3091 pinfo
= ip
->insn_mo
->pinfo
;
3092 pinfo2
= ip
->insn_mo
->pinfo2
;
3093 if (!mips_opts
.mips16
)
3095 if (pinfo2
& INSN2_READ_FPR_D
)
3096 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3097 if (pinfo
& INSN_READ_FPR_S
)
3098 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3099 if (pinfo
& INSN_READ_FPR_T
)
3100 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3101 if (pinfo
& INSN_READ_FPR_R
)
3102 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3103 if (pinfo2
& INSN2_READ_FPR_Z
)
3104 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3106 /* Conservatively treat all operands to an FP_D instruction are doubles.
3107 (This is overly pessimistic for things like cvt.d.s.) */
3108 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3113 /* Return the mask of floating-point registers that IP writes. */
3116 fpr_write_mask (const struct mips_cl_insn
*ip
)
3118 unsigned long pinfo
, pinfo2
;
3122 pinfo
= ip
->insn_mo
->pinfo
;
3123 pinfo2
= ip
->insn_mo
->pinfo2
;
3124 if (!mips_opts
.mips16
)
3126 if (pinfo
& INSN_WRITE_FPR_D
)
3127 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3128 if (pinfo
& INSN_WRITE_FPR_S
)
3129 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3130 if (pinfo
& INSN_WRITE_FPR_T
)
3131 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3132 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3133 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3135 /* Conservatively treat all operands to an FP_D instruction are doubles.
3136 (This is overly pessimistic for things like cvt.s.d.) */
3137 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3142 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3143 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3144 by VR4120 errata. */
3147 classify_vr4120_insn (const char *name
)
3149 if (strncmp (name
, "macc", 4) == 0)
3150 return FIX_VR4120_MACC
;
3151 if (strncmp (name
, "dmacc", 5) == 0)
3152 return FIX_VR4120_DMACC
;
3153 if (strncmp (name
, "mult", 4) == 0)
3154 return FIX_VR4120_MULT
;
3155 if (strncmp (name
, "dmult", 5) == 0)
3156 return FIX_VR4120_DMULT
;
3157 if (strstr (name
, "div"))
3158 return FIX_VR4120_DIV
;
3159 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3160 return FIX_VR4120_MTHILO
;
3161 return NUM_FIX_VR4120_CLASSES
;
3164 #define INSN_ERET 0x42000018
3165 #define INSN_DERET 0x4200001f
3167 /* Return the number of instructions that must separate INSN1 and INSN2,
3168 where INSN1 is the earlier instruction. Return the worst-case value
3169 for any INSN2 if INSN2 is null. */
3172 insns_between (const struct mips_cl_insn
*insn1
,
3173 const struct mips_cl_insn
*insn2
)
3175 unsigned long pinfo1
, pinfo2
;
3178 /* This function needs to know which pinfo flags are set for INSN2
3179 and which registers INSN2 uses. The former is stored in PINFO2 and
3180 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3181 will have every flag set and INSN2_USES_GPR will always return true. */
3182 pinfo1
= insn1
->insn_mo
->pinfo
;
3183 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3185 #define INSN2_USES_GPR(REG) \
3186 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3188 /* For most targets, write-after-read dependencies on the HI and LO
3189 registers must be separated by at least two instructions. */
3190 if (!hilo_interlocks
)
3192 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3194 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3198 /* If we're working around r7000 errata, there must be two instructions
3199 between an mfhi or mflo and any instruction that uses the result. */
3200 if (mips_7000_hilo_fix
3201 && !mips_opts
.micromips
3202 && MF_HILO_INSN (pinfo1
)
3203 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3206 /* If we're working around 24K errata, one instruction is required
3207 if an ERET or DERET is followed by a branch instruction. */
3208 if (mips_fix_24k
&& !mips_opts
.micromips
)
3210 if (insn1
->insn_opcode
== INSN_ERET
3211 || insn1
->insn_opcode
== INSN_DERET
)
3214 || insn2
->insn_opcode
== INSN_ERET
3215 || insn2
->insn_opcode
== INSN_DERET
3216 || delayed_branch_p (insn2
))
3221 /* If working around VR4120 errata, check for combinations that need
3222 a single intervening instruction. */
3223 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3225 unsigned int class1
, class2
;
3227 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3228 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3232 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3233 if (vr4120_conflicts
[class1
] & (1 << class2
))
3238 if (!HAVE_CODE_COMPRESSION
)
3240 /* Check for GPR or coprocessor load delays. All such delays
3241 are on the RT register. */
3242 /* Itbl support may require additional care here. */
3243 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3244 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3246 know (pinfo1
& INSN_WRITE_GPR_T
);
3247 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3251 /* Check for generic coprocessor hazards.
3253 This case is not handled very well. There is no special
3254 knowledge of CP0 handling, and the coprocessors other than
3255 the floating point unit are not distinguished at all. */
3256 /* Itbl support may require additional care here. FIXME!
3257 Need to modify this to include knowledge about
3258 user specified delays! */
3259 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3260 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3262 /* Handle cases where INSN1 writes to a known general coprocessor
3263 register. There must be a one instruction delay before INSN2
3264 if INSN2 reads that register, otherwise no delay is needed. */
3265 mask
= fpr_write_mask (insn1
);
3268 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3273 /* Read-after-write dependencies on the control registers
3274 require a two-instruction gap. */
3275 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3276 && (pinfo2
& INSN_READ_COND_CODE
))
3279 /* We don't know exactly what INSN1 does. If INSN2 is
3280 also a coprocessor instruction, assume there must be
3281 a one instruction gap. */
3282 if (pinfo2
& INSN_COP
)
3287 /* Check for read-after-write dependencies on the coprocessor
3288 control registers in cases where INSN1 does not need a general
3289 coprocessor delay. This means that INSN1 is a floating point
3290 comparison instruction. */
3291 /* Itbl support may require additional care here. */
3292 else if (!cop_interlocks
3293 && (pinfo1
& INSN_WRITE_COND_CODE
)
3294 && (pinfo2
& INSN_READ_COND_CODE
))
3298 #undef INSN2_USES_GPR
3303 /* Return the number of nops that would be needed to work around the
3304 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3305 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3306 that are contained within the first IGNORE instructions of HIST. */
3309 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3310 const struct mips_cl_insn
*insn
)
3315 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3316 are not affected by the errata. */
3318 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3319 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3320 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3323 /* Search for the first MFLO or MFHI. */
3324 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3325 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3327 /* Extract the destination register. */
3328 mask
= gpr_write_mask (&hist
[i
]);
3330 /* No nops are needed if INSN reads that register. */
3331 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3334 /* ...or if any of the intervening instructions do. */
3335 for (j
= 0; j
< i
; j
++)
3336 if (gpr_read_mask (&hist
[j
]) & mask
)
3340 return MAX_VR4130_NOPS
- i
;
3345 #define BASE_REG_EQ(INSN1, INSN2) \
3346 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3347 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3349 /* Return the minimum alignment for this store instruction. */
3352 fix_24k_align_to (const struct mips_opcode
*mo
)
3354 if (strcmp (mo
->name
, "sh") == 0)
3357 if (strcmp (mo
->name
, "swc1") == 0
3358 || strcmp (mo
->name
, "swc2") == 0
3359 || strcmp (mo
->name
, "sw") == 0
3360 || strcmp (mo
->name
, "sc") == 0
3361 || strcmp (mo
->name
, "s.s") == 0)
3364 if (strcmp (mo
->name
, "sdc1") == 0
3365 || strcmp (mo
->name
, "sdc2") == 0
3366 || strcmp (mo
->name
, "s.d") == 0)
3373 struct fix_24k_store_info
3375 /* Immediate offset, if any, for this store instruction. */
3377 /* Alignment required by this store instruction. */
3379 /* True for register offsets. */
3380 int register_offset
;
3383 /* Comparison function used by qsort. */
3386 fix_24k_sort (const void *a
, const void *b
)
3388 const struct fix_24k_store_info
*pos1
= a
;
3389 const struct fix_24k_store_info
*pos2
= b
;
3391 return (pos1
->off
- pos2
->off
);
3394 /* INSN is a store instruction. Try to record the store information
3395 in STINFO. Return false if the information isn't known. */
3398 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3399 const struct mips_cl_insn
*insn
)
3401 /* The instruction must have a known offset. */
3402 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3405 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3406 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3410 /* Return the number of nops that would be needed to work around the 24k
3411 "lost data on stores during refill" errata if instruction INSN
3412 immediately followed the 2 instructions described by HIST.
3413 Ignore hazards that are contained within the first IGNORE
3414 instructions of HIST.
3416 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3417 for the data cache refills and store data. The following describes
3418 the scenario where the store data could be lost.
3420 * A data cache miss, due to either a load or a store, causing fill
3421 data to be supplied by the memory subsystem
3422 * The first three doublewords of fill data are returned and written
3424 * A sequence of four stores occurs in consecutive cycles around the
3425 final doubleword of the fill:
3429 * Zero, One or more instructions
3432 The four stores A-D must be to different doublewords of the line that
3433 is being filled. The fourth instruction in the sequence above permits
3434 the fill of the final doubleword to be transferred from the FSB into
3435 the cache. In the sequence above, the stores may be either integer
3436 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3437 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3438 different doublewords on the line. If the floating point unit is
3439 running in 1:2 mode, it is not possible to create the sequence above
3440 using only floating point store instructions.
3442 In this case, the cache line being filled is incorrectly marked
3443 invalid, thereby losing the data from any store to the line that
3444 occurs between the original miss and the completion of the five
3445 cycle sequence shown above.
3447 The workarounds are:
3449 * Run the data cache in write-through mode.
3450 * Insert a non-store instruction between
3451 Store A and Store B or Store B and Store C. */
3454 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3455 const struct mips_cl_insn
*insn
)
3457 struct fix_24k_store_info pos
[3];
3458 int align
, i
, base_offset
;
3463 /* If the previous instruction wasn't a store, there's nothing to
3465 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3468 /* If the instructions after the previous one are unknown, we have
3469 to assume the worst. */
3473 /* Check whether we are dealing with three consecutive stores. */
3474 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3475 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3478 /* If we don't know the relationship between the store addresses,
3479 assume the worst. */
3480 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3481 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3484 if (!fix_24k_record_store_info (&pos
[0], insn
)
3485 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3486 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3489 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3491 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3492 X bytes and such that the base register + X is known to be aligned
3495 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3499 align
= pos
[0].align_to
;
3500 base_offset
= pos
[0].off
;
3501 for (i
= 1; i
< 3; i
++)
3502 if (align
< pos
[i
].align_to
)
3504 align
= pos
[i
].align_to
;
3505 base_offset
= pos
[i
].off
;
3507 for (i
= 0; i
< 3; i
++)
3508 pos
[i
].off
-= base_offset
;
3511 pos
[0].off
&= ~align
+ 1;
3512 pos
[1].off
&= ~align
+ 1;
3513 pos
[2].off
&= ~align
+ 1;
3515 /* If any two stores write to the same chunk, they also write to the
3516 same doubleword. The offsets are still sorted at this point. */
3517 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3520 /* A range of at least 9 bytes is needed for the stores to be in
3521 non-overlapping doublewords. */
3522 if (pos
[2].off
- pos
[0].off
<= 8)
3525 if (pos
[2].off
- pos
[1].off
>= 24
3526 || pos
[1].off
- pos
[0].off
>= 24
3527 || pos
[2].off
- pos
[0].off
>= 32)
3533 /* Return the number of nops that would be needed if instruction INSN
3534 immediately followed the MAX_NOPS instructions given by HIST,
3535 where HIST[0] is the most recent instruction. Ignore hazards
3536 between INSN and the first IGNORE instructions in HIST.
3538 If INSN is null, return the worse-case number of nops for any
3542 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3543 const struct mips_cl_insn
*insn
)
3545 int i
, nops
, tmp_nops
;
3548 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3550 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3551 if (tmp_nops
> nops
)
3555 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3557 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3558 if (tmp_nops
> nops
)
3562 if (mips_fix_24k
&& !mips_opts
.micromips
)
3564 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3565 if (tmp_nops
> nops
)
3572 /* The variable arguments provide NUM_INSNS extra instructions that
3573 might be added to HIST. Return the largest number of nops that
3574 would be needed after the extended sequence, ignoring hazards
3575 in the first IGNORE instructions. */
3578 nops_for_sequence (int num_insns
, int ignore
,
3579 const struct mips_cl_insn
*hist
, ...)
3582 struct mips_cl_insn buffer
[MAX_NOPS
];
3583 struct mips_cl_insn
*cursor
;
3586 va_start (args
, hist
);
3587 cursor
= buffer
+ num_insns
;
3588 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3589 while (cursor
> buffer
)
3590 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3592 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3597 /* Like nops_for_insn, but if INSN is a branch, take into account the
3598 worst-case delay for the branch target. */
3601 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3602 const struct mips_cl_insn
*insn
)
3606 nops
= nops_for_insn (ignore
, hist
, insn
);
3607 if (delayed_branch_p (insn
))
3609 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3610 hist
, insn
, get_delay_slot_nop (insn
));
3611 if (tmp_nops
> nops
)
3614 else if (compact_branch_p (insn
))
3616 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3617 if (tmp_nops
> nops
)
3623 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3626 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3628 gas_assert (!HAVE_CODE_COMPRESSION
);
3629 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3630 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3633 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3634 jr target pc &= 'hffff_ffff_cfff_ffff. */
3637 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3639 gas_assert (!HAVE_CODE_COMPRESSION
);
3640 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3641 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3642 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3650 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3651 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3654 ep
.X_op
= O_constant
;
3655 ep
.X_add_number
= 0xcfff0000;
3656 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3657 ep
.X_add_number
= 0xffff;
3658 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3659 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3664 fix_loongson2f (struct mips_cl_insn
* ip
)
3666 if (mips_fix_loongson2f_nop
)
3667 fix_loongson2f_nop (ip
);
3669 if (mips_fix_loongson2f_jump
)
3670 fix_loongson2f_jump (ip
);
3673 /* IP is a branch that has a delay slot, and we need to fill it
3674 automatically. Return true if we can do that by swapping IP
3675 with the previous instruction. */
3678 can_swap_branch_p (struct mips_cl_insn
*ip
)
3680 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3681 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3684 /* -O2 and above is required for this optimization. */
3685 if (mips_optimize
< 2)
3688 /* If we have seen .set volatile or .set nomove, don't optimize. */
3689 if (mips_opts
.nomove
)
3692 /* We can't swap if the previous instruction's position is fixed. */
3693 if (history
[0].fixed_p
)
3696 /* If the previous previous insn was in a .set noreorder, we can't
3697 swap. Actually, the MIPS assembler will swap in this situation.
3698 However, gcc configured -with-gnu-as will generate code like
3706 in which we can not swap the bne and INSN. If gcc is not configured
3707 -with-gnu-as, it does not output the .set pseudo-ops. */
3708 if (history
[1].noreorder_p
)
3711 /* If the previous instruction had a fixup in mips16 mode, we can not
3712 swap. This normally means that the previous instruction was a 4
3713 byte branch anyhow. */
3714 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3717 /* If the branch is itself the target of a branch, we can not swap.
3718 We cheat on this; all we check for is whether there is a label on
3719 this instruction. If there are any branches to anything other than
3720 a label, users must use .set noreorder. */
3721 if (seg_info (now_seg
)->label_list
)
3724 /* If the previous instruction is in a variant frag other than this
3725 branch's one, we cannot do the swap. This does not apply to
3726 MIPS16/microMIPS code, which uses variant frags for different
3728 if (!HAVE_CODE_COMPRESSION
3730 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3733 /* We do not swap with instructions that cannot architecturally
3734 be placed in a branch delay slot, such as SYNC or ERET. We
3735 also refrain from swapping with a trap instruction, since it
3736 complicates trap handlers to have the trap instruction be in
3738 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3739 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3742 /* Check for conflicts between the branch and the instructions
3743 before the candidate delay slot. */
3744 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3747 /* Check for conflicts between the swapped sequence and the
3748 target of the branch. */
3749 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3752 /* If the branch reads a register that the previous
3753 instruction sets, we can not swap. */
3754 gpr_read
= gpr_read_mask (ip
);
3755 prev_gpr_write
= gpr_write_mask (&history
[0]);
3756 if (gpr_read
& prev_gpr_write
)
3759 /* If the branch writes a register that the previous
3760 instruction sets, we can not swap. */
3761 gpr_write
= gpr_write_mask (ip
);
3762 if (gpr_write
& prev_gpr_write
)
3765 /* If the branch writes a register that the previous
3766 instruction reads, we can not swap. */
3767 prev_gpr_read
= gpr_read_mask (&history
[0]);
3768 if (gpr_write
& prev_gpr_read
)
3771 /* If one instruction sets a condition code and the
3772 other one uses a condition code, we can not swap. */
3773 pinfo
= ip
->insn_mo
->pinfo
;
3774 if ((pinfo
& INSN_READ_COND_CODE
)
3775 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3777 if ((pinfo
& INSN_WRITE_COND_CODE
)
3778 && (prev_pinfo
& INSN_READ_COND_CODE
))
3781 /* If the previous instruction uses the PC, we can not swap. */
3782 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3783 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3785 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3788 /* If the previous instruction has an incorrect size for a fixed
3789 branch delay slot in microMIPS mode, we cannot swap. */
3790 pinfo2
= ip
->insn_mo
->pinfo2
;
3791 if (mips_opts
.micromips
3792 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3793 && insn_length (history
) != 2)
3795 if (mips_opts
.micromips
3796 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3797 && insn_length (history
) != 4)
3803 /* Decide how we should add IP to the instruction stream. */
3805 static enum append_method
3806 get_append_method (struct mips_cl_insn
*ip
)
3808 unsigned long pinfo
;
3810 /* The relaxed version of a macro sequence must be inherently
3812 if (mips_relax
.sequence
== 2)
3815 /* We must not dabble with instructions in a ".set norerorder" block. */
3816 if (mips_opts
.noreorder
)
3819 /* Otherwise, it's our responsibility to fill branch delay slots. */
3820 if (delayed_branch_p (ip
))
3822 if (!branch_likely_p (ip
) && can_swap_branch_p (ip
))
3825 pinfo
= ip
->insn_mo
->pinfo
;
3826 if (mips_opts
.mips16
3827 && ISA_SUPPORTS_MIPS16E
3828 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3829 return APPEND_ADD_COMPACT
;
3831 return APPEND_ADD_WITH_NOP
;
3837 /* IP is a MIPS16 instruction whose opcode we have just changed.
3838 Point IP->insn_mo to the new opcode's definition. */
3841 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3843 const struct mips_opcode
*mo
, *end
;
3845 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3846 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3847 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3855 /* For microMIPS macros, we need to generate a local number label
3856 as the target of branches. */
3857 #define MICROMIPS_LABEL_CHAR '\037'
3858 static unsigned long micromips_target_label
;
3859 static char micromips_target_name
[32];
3862 micromips_label_name (void)
3864 char *p
= micromips_target_name
;
3865 char symbol_name_temporary
[24];
3873 l
= micromips_target_label
;
3874 #ifdef LOCAL_LABEL_PREFIX
3875 *p
++ = LOCAL_LABEL_PREFIX
;
3878 *p
++ = MICROMIPS_LABEL_CHAR
;
3881 symbol_name_temporary
[i
++] = l
% 10 + '0';
3886 *p
++ = symbol_name_temporary
[--i
];
3889 return micromips_target_name
;
3893 micromips_label_expr (expressionS
*label_expr
)
3895 label_expr
->X_op
= O_symbol
;
3896 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
3897 label_expr
->X_add_number
= 0;
3901 micromips_label_inc (void)
3903 micromips_target_label
++;
3904 *micromips_target_name
= '\0';
3908 micromips_add_label (void)
3912 s
= colon (micromips_label_name ());
3913 micromips_label_inc ();
3914 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3916 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
3920 /* If assembling microMIPS code, then return the microMIPS reloc
3921 corresponding to the requested one if any. Otherwise return
3922 the reloc unchanged. */
3924 static bfd_reloc_code_real_type
3925 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
3927 static const bfd_reloc_code_real_type relocs
[][2] =
3929 /* Keep sorted incrementally by the left-hand key. */
3930 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
3931 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
3932 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
3933 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
3934 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
3935 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
3936 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
3937 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
3938 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
3939 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
3940 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
3941 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
3942 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
3943 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
3944 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
3945 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
3946 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
3947 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
3948 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
3949 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
3950 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
3951 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
3952 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
3953 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
3954 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
3955 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
3956 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
3958 bfd_reloc_code_real_type r
;
3961 if (!mips_opts
.micromips
)
3963 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
3969 return relocs
[i
][1];
3974 /* Output an instruction. IP is the instruction information.
3975 ADDRESS_EXPR is an operand of the instruction to be used with
3976 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3977 a macro expansion. */
3980 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3981 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
3983 unsigned long prev_pinfo2
, pinfo
;
3984 bfd_boolean relaxed_branch
= FALSE
;
3985 enum append_method method
;
3986 bfd_boolean relax32
;
3989 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
3990 fix_loongson2f (ip
);
3992 mips_mark_labels ();
3994 file_ase_mips16
|= mips_opts
.mips16
;
3995 file_ase_micromips
|= mips_opts
.micromips
;
3997 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3998 pinfo
= ip
->insn_mo
->pinfo
;
4000 if (mips_opts
.micromips
4002 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4003 && micromips_insn_length (ip
->insn_mo
) != 2)
4004 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4005 && micromips_insn_length (ip
->insn_mo
) != 4)))
4006 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4007 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4009 if (address_expr
== NULL
)
4011 else if (*reloc_type
<= BFD_RELOC_UNUSED
4012 && address_expr
->X_op
== O_constant
)
4017 switch (*reloc_type
)
4020 ip
->insn_opcode
|= address_expr
->X_add_number
;
4023 case BFD_RELOC_MIPS_HIGHEST
:
4024 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
4025 ip
->insn_opcode
|= tmp
& 0xffff;
4028 case BFD_RELOC_MIPS_HIGHER
:
4029 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
4030 ip
->insn_opcode
|= tmp
& 0xffff;
4033 case BFD_RELOC_HI16_S
:
4034 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
4035 ip
->insn_opcode
|= tmp
& 0xffff;
4038 case BFD_RELOC_HI16
:
4039 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
4042 case BFD_RELOC_UNUSED
:
4043 case BFD_RELOC_LO16
:
4044 case BFD_RELOC_MIPS_GOT_DISP
:
4045 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
4048 case BFD_RELOC_MIPS_JMP
:
4052 shift
= mips_opts
.micromips
? 1 : 2;
4053 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4054 as_bad (_("jump to misaligned address (0x%lx)"),
4055 (unsigned long) address_expr
->X_add_number
);
4056 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4062 case BFD_RELOC_MIPS16_JMP
:
4063 if ((address_expr
->X_add_number
& 3) != 0)
4064 as_bad (_("jump to misaligned address (0x%lx)"),
4065 (unsigned long) address_expr
->X_add_number
);
4067 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4068 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4069 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4073 case BFD_RELOC_16_PCREL_S2
:
4077 shift
= mips_opts
.micromips
? 1 : 2;
4078 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4079 as_bad (_("branch to misaligned address (0x%lx)"),
4080 (unsigned long) address_expr
->X_add_number
);
4081 if (!mips_relax_branch
)
4083 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4084 & ~((1 << (shift
+ 16)) - 1))
4085 as_bad (_("branch address range overflow (0x%lx)"),
4086 (unsigned long) address_expr
->X_add_number
);
4087 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4099 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4101 /* There are a lot of optimizations we could do that we don't.
4102 In particular, we do not, in general, reorder instructions.
4103 If you use gcc with optimization, it will reorder
4104 instructions and generally do much more optimization then we
4105 do here; repeating all that work in the assembler would only
4106 benefit hand written assembly code, and does not seem worth
4108 int nops
= (mips_optimize
== 0
4109 ? nops_for_insn (0, history
, NULL
)
4110 : nops_for_insn_or_target (0, history
, ip
));
4114 unsigned long old_frag_offset
;
4117 old_frag
= frag_now
;
4118 old_frag_offset
= frag_now_fix ();
4120 for (i
= 0; i
< nops
; i
++)
4121 add_fixed_insn (NOP_INSN
);
4122 insert_into_history (0, nops
, NOP_INSN
);
4126 listing_prev_line ();
4127 /* We may be at the start of a variant frag. In case we
4128 are, make sure there is enough space for the frag
4129 after the frags created by listing_prev_line. The
4130 argument to frag_grow here must be at least as large
4131 as the argument to all other calls to frag_grow in
4132 this file. We don't have to worry about being in the
4133 middle of a variant frag, because the variants insert
4134 all needed nop instructions themselves. */
4138 mips_move_labels ();
4140 #ifndef NO_ECOFF_DEBUGGING
4141 if (ECOFF_DEBUGGING
)
4142 ecoff_fix_loc (old_frag
, old_frag_offset
);
4146 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4150 /* Work out how many nops in prev_nop_frag are needed by IP,
4151 ignoring hazards generated by the first prev_nop_frag_since
4153 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4154 gas_assert (nops
<= prev_nop_frag_holds
);
4156 /* Enforce NOPS as a minimum. */
4157 if (nops
> prev_nop_frag_required
)
4158 prev_nop_frag_required
= nops
;
4160 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4162 /* Settle for the current number of nops. Update the history
4163 accordingly (for the benefit of any future .set reorder code). */
4164 prev_nop_frag
= NULL
;
4165 insert_into_history (prev_nop_frag_since
,
4166 prev_nop_frag_holds
, NOP_INSN
);
4170 /* Allow this instruction to replace one of the nops that was
4171 tentatively added to prev_nop_frag. */
4172 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4173 prev_nop_frag_holds
--;
4174 prev_nop_frag_since
++;
4178 method
= get_append_method (ip
);
4179 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4182 /* The value passed to dwarf2_emit_insn is the distance between
4183 the beginning of the current instruction and the address that
4184 should be recorded in the debug tables. This is normally the
4187 For MIPS16/microMIPS debug info we want to use ISA-encoded
4188 addresses, so we use -1 for an address higher by one than the
4191 If the instruction produced is a branch that we will swap with
4192 the preceding instruction, then we add the displacement by which
4193 the branch will be moved backwards. This is more appropriate
4194 and for MIPS16/microMIPS code also prevents a debugger from
4195 placing a breakpoint in the middle of the branch (and corrupting
4196 code if software breakpoints are used). */
4197 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4200 relax32
= (mips_relax_branch
4201 /* Don't try branch relaxation within .set nomacro, or within
4202 .set noat if we use $at for PIC computations. If it turns
4203 out that the branch was out-of-range, we'll get an error. */
4204 && !mips_opts
.warn_about_macros
4205 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4206 /* Don't relax BPOSGE32/64 as they have no complementing
4208 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4210 if (!HAVE_CODE_COMPRESSION
4213 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4214 && delayed_branch_p (ip
))
4216 relaxed_branch
= TRUE
;
4217 add_relaxed_insn (ip
, (relaxed_branch_length
4219 uncond_branch_p (ip
) ? -1
4220 : branch_likely_p (ip
) ? 1
4224 uncond_branch_p (ip
),
4225 branch_likely_p (ip
),
4226 pinfo
& INSN_WRITE_GPR_31
,
4228 address_expr
->X_add_symbol
,
4229 address_expr
->X_add_number
);
4230 *reloc_type
= BFD_RELOC_UNUSED
;
4232 else if (mips_opts
.micromips
4234 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4235 || *reloc_type
> BFD_RELOC_UNUSED
)
4236 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4237 /* Don't try branch relaxation when users specify
4238 16-bit/32-bit instructions. */
4239 && !forced_insn_length
)
4241 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4242 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4243 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4244 int compact
= compact_branch_p (ip
);
4245 int al
= pinfo
& INSN_WRITE_GPR_31
;
4248 gas_assert (address_expr
!= NULL
);
4249 gas_assert (!mips_relax
.sequence
);
4251 relaxed_branch
= TRUE
;
4252 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4253 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4254 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4256 address_expr
->X_add_symbol
,
4257 address_expr
->X_add_number
);
4258 *reloc_type
= BFD_RELOC_UNUSED
;
4260 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4262 /* We need to set up a variant frag. */
4263 gas_assert (address_expr
!= NULL
);
4264 add_relaxed_insn (ip
, 4, 0,
4266 (*reloc_type
- BFD_RELOC_UNUSED
,
4267 forced_insn_length
== 2, forced_insn_length
== 4,
4268 delayed_branch_p (&history
[0]),
4269 history
[0].mips16_absolute_jump_p
),
4270 make_expr_symbol (address_expr
), 0);
4272 else if (mips_opts
.mips16
4274 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
4276 if (!delayed_branch_p (ip
))
4277 /* Make sure there is enough room to swap this instruction with
4278 a following jump instruction. */
4280 add_fixed_insn (ip
);
4284 if (mips_opts
.mips16
4285 && mips_opts
.noreorder
4286 && delayed_branch_p (&history
[0]))
4287 as_warn (_("extended instruction in delay slot"));
4289 if (mips_relax
.sequence
)
4291 /* If we've reached the end of this frag, turn it into a variant
4292 frag and record the information for the instructions we've
4294 if (frag_room () < 4)
4295 relax_close_frag ();
4296 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4299 if (mips_relax
.sequence
!= 2)
4301 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4302 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4303 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4304 mips_macro_warning
.insns
[0]++;
4306 if (mips_relax
.sequence
!= 1)
4308 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4309 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4310 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4311 mips_macro_warning
.insns
[1]++;
4314 if (mips_opts
.mips16
)
4317 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4319 add_fixed_insn (ip
);
4322 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4324 bfd_reloc_code_real_type final_type
[3];
4325 reloc_howto_type
*howto0
;
4326 reloc_howto_type
*howto
;
4329 /* Perform any necessary conversion to microMIPS relocations
4330 and find out how many relocations there actually are. */
4331 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4332 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4334 /* In a compound relocation, it is the final (outermost)
4335 operator that determines the relocated field. */
4336 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4340 /* To reproduce this failure try assembling gas/testsuites/
4341 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4343 as_bad (_("Unsupported MIPS relocation number %d"),
4345 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4349 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4350 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4351 bfd_get_reloc_size (howto
),
4353 howto0
&& howto0
->pc_relative
,
4356 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4357 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4358 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4360 /* These relocations can have an addend that won't fit in
4361 4 octets for 64bit assembly. */
4363 && ! howto
->partial_inplace
4364 && (reloc_type
[0] == BFD_RELOC_16
4365 || reloc_type
[0] == BFD_RELOC_32
4366 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4367 || reloc_type
[0] == BFD_RELOC_GPREL16
4368 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4369 || reloc_type
[0] == BFD_RELOC_GPREL32
4370 || reloc_type
[0] == BFD_RELOC_64
4371 || reloc_type
[0] == BFD_RELOC_CTOR
4372 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4373 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4374 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4375 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4376 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4377 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4378 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4379 || hi16_reloc_p (reloc_type
[0])
4380 || lo16_reloc_p (reloc_type
[0])))
4381 ip
->fixp
[0]->fx_no_overflow
= 1;
4383 if (mips_relax
.sequence
)
4385 if (mips_relax
.first_fixup
== 0)
4386 mips_relax
.first_fixup
= ip
->fixp
[0];
4388 else if (reloc_needs_lo_p (*reloc_type
))
4390 struct mips_hi_fixup
*hi_fixup
;
4392 /* Reuse the last entry if it already has a matching %lo. */
4393 hi_fixup
= mips_hi_fixup_list
;
4395 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4397 hi_fixup
= ((struct mips_hi_fixup
*)
4398 xmalloc (sizeof (struct mips_hi_fixup
)));
4399 hi_fixup
->next
= mips_hi_fixup_list
;
4400 mips_hi_fixup_list
= hi_fixup
;
4402 hi_fixup
->fixp
= ip
->fixp
[0];
4403 hi_fixup
->seg
= now_seg
;
4406 /* Add fixups for the second and third relocations, if given.
4407 Note that the ABI allows the second relocation to be
4408 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4409 moment we only use RSS_UNDEF, but we could add support
4410 for the others if it ever becomes necessary. */
4411 for (i
= 1; i
< 3; i
++)
4412 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4414 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4415 ip
->fixp
[0]->fx_size
, NULL
, 0,
4416 FALSE
, final_type
[i
]);
4418 /* Use fx_tcbit to mark compound relocs. */
4419 ip
->fixp
[0]->fx_tcbit
= 1;
4420 ip
->fixp
[i
]->fx_tcbit
= 1;
4425 /* Update the register mask information. */
4426 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4427 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4432 insert_into_history (0, 1, ip
);
4435 case APPEND_ADD_WITH_NOP
:
4437 struct mips_cl_insn
*nop
;
4439 insert_into_history (0, 1, ip
);
4440 nop
= get_delay_slot_nop (ip
);
4441 add_fixed_insn (nop
);
4442 insert_into_history (0, 1, nop
);
4443 if (mips_relax
.sequence
)
4444 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4448 case APPEND_ADD_COMPACT
:
4449 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4450 gas_assert (mips_opts
.mips16
);
4451 ip
->insn_opcode
|= 0x0080;
4452 find_altered_mips16_opcode (ip
);
4454 insert_into_history (0, 1, ip
);
4459 struct mips_cl_insn delay
= history
[0];
4460 if (mips_opts
.mips16
)
4462 know (delay
.frag
== ip
->frag
);
4463 move_insn (ip
, delay
.frag
, delay
.where
);
4464 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4466 else if (relaxed_branch
)
4468 /* Add the delay slot instruction to the end of the
4469 current frag and shrink the fixed part of the
4470 original frag. If the branch occupies the tail of
4471 the latter, move it backwards to cover the gap. */
4472 delay
.frag
->fr_fix
-= branch_disp
;
4473 if (delay
.frag
== ip
->frag
)
4474 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4475 add_fixed_insn (&delay
);
4479 move_insn (&delay
, ip
->frag
,
4480 ip
->where
- branch_disp
+ insn_length (ip
));
4481 move_insn (ip
, history
[0].frag
, history
[0].where
);
4485 insert_into_history (0, 1, &delay
);
4490 /* If we have just completed an unconditional branch, clear the history. */
4491 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4492 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4493 mips_no_prev_insn ();
4495 /* We need to emit a label at the end of branch-likely macros. */
4496 if (emit_branch_likely_macro
)
4498 emit_branch_likely_macro
= FALSE
;
4499 micromips_add_label ();
4502 /* We just output an insn, so the next one doesn't have a label. */
4503 mips_clear_insn_labels ();
4506 /* Forget that there was any previous instruction or label. */
4509 mips_no_prev_insn (void)
4511 prev_nop_frag
= NULL
;
4512 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4513 mips_clear_insn_labels ();
4516 /* This function must be called before we emit something other than
4517 instructions. It is like mips_no_prev_insn except that it inserts
4518 any NOPS that might be needed by previous instructions. */
4521 mips_emit_delays (void)
4523 if (! mips_opts
.noreorder
)
4525 int nops
= nops_for_insn (0, history
, NULL
);
4529 add_fixed_insn (NOP_INSN
);
4530 mips_move_labels ();
4533 mips_no_prev_insn ();
4536 /* Start a (possibly nested) noreorder block. */
4539 start_noreorder (void)
4541 if (mips_opts
.noreorder
== 0)
4546 /* None of the instructions before the .set noreorder can be moved. */
4547 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4548 history
[i
].fixed_p
= 1;
4550 /* Insert any nops that might be needed between the .set noreorder
4551 block and the previous instructions. We will later remove any
4552 nops that turn out not to be needed. */
4553 nops
= nops_for_insn (0, history
, NULL
);
4556 if (mips_optimize
!= 0)
4558 /* Record the frag which holds the nop instructions, so
4559 that we can remove them if we don't need them. */
4560 frag_grow (nops
* NOP_INSN_SIZE
);
4561 prev_nop_frag
= frag_now
;
4562 prev_nop_frag_holds
= nops
;
4563 prev_nop_frag_required
= 0;
4564 prev_nop_frag_since
= 0;
4567 for (; nops
> 0; --nops
)
4568 add_fixed_insn (NOP_INSN
);
4570 /* Move on to a new frag, so that it is safe to simply
4571 decrease the size of prev_nop_frag. */
4572 frag_wane (frag_now
);
4574 mips_move_labels ();
4576 mips_mark_labels ();
4577 mips_clear_insn_labels ();
4579 mips_opts
.noreorder
++;
4580 mips_any_noreorder
= 1;
4583 /* End a nested noreorder block. */
4586 end_noreorder (void)
4589 mips_opts
.noreorder
--;
4590 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4592 /* Commit to inserting prev_nop_frag_required nops and go back to
4593 handling nop insertion the .set reorder way. */
4594 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4596 insert_into_history (prev_nop_frag_since
,
4597 prev_nop_frag_required
, NOP_INSN
);
4598 prev_nop_frag
= NULL
;
4602 /* Set up global variables for the start of a new macro. */
4607 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4608 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4609 sizeof (mips_macro_warning
.first_insn_sizes
));
4610 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4611 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4612 && delayed_branch_p (&history
[0]));
4613 switch (history
[0].insn_mo
->pinfo2
4614 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4616 case INSN2_BRANCH_DELAY_32BIT
:
4617 mips_macro_warning
.delay_slot_length
= 4;
4619 case INSN2_BRANCH_DELAY_16BIT
:
4620 mips_macro_warning
.delay_slot_length
= 2;
4623 mips_macro_warning
.delay_slot_length
= 0;
4626 mips_macro_warning
.first_frag
= NULL
;
4629 /* Given that a macro is longer than one instruction or of the wrong size,
4630 return the appropriate warning for it. Return null if no warning is
4631 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4632 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4633 and RELAX_NOMACRO. */
4636 macro_warning (relax_substateT subtype
)
4638 if (subtype
& RELAX_DELAY_SLOT
)
4639 return _("Macro instruction expanded into multiple instructions"
4640 " in a branch delay slot");
4641 else if (subtype
& RELAX_NOMACRO
)
4642 return _("Macro instruction expanded into multiple instructions");
4643 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4644 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4645 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4646 ? _("Macro instruction expanded into a wrong size instruction"
4647 " in a 16-bit branch delay slot")
4648 : _("Macro instruction expanded into a wrong size instruction"
4649 " in a 32-bit branch delay slot"));
4654 /* Finish up a macro. Emit warnings as appropriate. */
4659 /* Relaxation warning flags. */
4660 relax_substateT subtype
= 0;
4662 /* Check delay slot size requirements. */
4663 if (mips_macro_warning
.delay_slot_length
== 2)
4664 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4665 if (mips_macro_warning
.delay_slot_length
!= 0)
4667 if (mips_macro_warning
.delay_slot_length
4668 != mips_macro_warning
.first_insn_sizes
[0])
4669 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4670 if (mips_macro_warning
.delay_slot_length
4671 != mips_macro_warning
.first_insn_sizes
[1])
4672 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4675 /* Check instruction count requirements. */
4676 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4678 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4679 subtype
|= RELAX_SECOND_LONGER
;
4680 if (mips_opts
.warn_about_macros
)
4681 subtype
|= RELAX_NOMACRO
;
4682 if (mips_macro_warning
.delay_slot_p
)
4683 subtype
|= RELAX_DELAY_SLOT
;
4686 /* If both alternatives fail to fill a delay slot correctly,
4687 emit the warning now. */
4688 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4689 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4694 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4695 | RELAX_DELAY_SLOT_SIZE_FIRST
4696 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4697 msg
= macro_warning (s
);
4699 as_warn ("%s", msg
);
4703 /* If both implementations are longer than 1 instruction, then emit the
4705 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4710 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4711 msg
= macro_warning (s
);
4713 as_warn ("%s", msg
);
4717 /* If any flags still set, then one implementation might need a warning
4718 and the other either will need one of a different kind or none at all.
4719 Pass any remaining flags over to relaxation. */
4720 if (mips_macro_warning
.first_frag
!= NULL
)
4721 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4724 /* Instruction operand formats used in macros that vary between
4725 standard MIPS and microMIPS code. */
4727 static const char * const brk_fmt
[2] = { "c", "mF" };
4728 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4729 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4730 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4731 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4732 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4733 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4734 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4736 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4737 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4738 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4739 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4740 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4741 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4742 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4743 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4745 /* Read a macro's relocation codes from *ARGS and store them in *R.
4746 The first argument in *ARGS will be either the code for a single
4747 relocation or -1 followed by the three codes that make up a
4748 composite relocation. */
4751 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4755 next
= va_arg (*args
, int);
4757 r
[0] = (bfd_reloc_code_real_type
) next
;
4759 for (i
= 0; i
< 3; i
++)
4760 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4763 /* Build an instruction created by a macro expansion. This is passed
4764 a pointer to the count of instructions created so far, an
4765 expression, the name of the instruction to build, an operand format
4766 string, and corresponding arguments. */
4769 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4771 const struct mips_opcode
*mo
= NULL
;
4772 bfd_reloc_code_real_type r
[3];
4773 const struct mips_opcode
*amo
;
4774 struct hash_control
*hash
;
4775 struct mips_cl_insn insn
;
4778 va_start (args
, fmt
);
4780 if (mips_opts
.mips16
)
4782 mips16_macro_build (ep
, name
, fmt
, &args
);
4787 r
[0] = BFD_RELOC_UNUSED
;
4788 r
[1] = BFD_RELOC_UNUSED
;
4789 r
[2] = BFD_RELOC_UNUSED
;
4790 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4791 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4793 gas_assert (strcmp (name
, amo
->name
) == 0);
4797 /* Search until we get a match for NAME. It is assumed here that
4798 macros will never generate MDMX, MIPS-3D, or MT instructions.
4799 We try to match an instruction that fulfils the branch delay
4800 slot instruction length requirement (if any) of the previous
4801 instruction. While doing this we record the first instruction
4802 seen that matches all the other conditions and use it anyway
4803 if the requirement cannot be met; we will issue an appropriate
4804 warning later on. */
4805 if (strcmp (fmt
, amo
->args
) == 0
4806 && amo
->pinfo
!= INSN_MACRO
4807 && is_opcode_valid (amo
)
4808 && is_size_valid (amo
))
4810 if (is_delay_slot_valid (amo
))
4820 gas_assert (amo
->name
);
4822 while (strcmp (name
, amo
->name
) == 0);
4825 create_insn (&insn
, mo
);
4843 INSERT_OPERAND (mips_opts
.micromips
,
4844 EXTLSB
, insn
, va_arg (args
, int));
4849 /* Note that in the macro case, these arguments are already
4850 in MSB form. (When handling the instruction in the
4851 non-macro case, these arguments are sizes from which
4852 MSB values must be calculated.) */
4853 INSERT_OPERAND (mips_opts
.micromips
,
4854 INSMSB
, insn
, va_arg (args
, int));
4860 /* Note that in the macro case, these arguments are already
4861 in MSBD form. (When handling the instruction in the
4862 non-macro case, these arguments are sizes from which
4863 MSBD values must be calculated.) */
4864 INSERT_OPERAND (mips_opts
.micromips
,
4865 EXTMSBD
, insn
, va_arg (args
, int));
4869 gas_assert (!mips_opts
.micromips
);
4870 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
4879 gas_assert (!mips_opts
.micromips
);
4880 INSERT_OPERAND (0, BP
, insn
, va_arg (args
, int));
4884 gas_assert (mips_opts
.micromips
);
4888 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
4892 gas_assert (!mips_opts
.micromips
);
4893 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
4897 gas_assert (!mips_opts
.micromips
);
4899 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
4903 if (mips_opts
.micromips
)
4904 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
4906 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
4910 gas_assert (!mips_opts
.micromips
);
4912 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
4916 gas_assert (!mips_opts
.micromips
);
4918 int tmp
= va_arg (args
, int);
4920 INSERT_OPERAND (0, RT
, insn
, tmp
);
4921 INSERT_OPERAND (0, RD
, insn
, tmp
);
4927 gas_assert (!mips_opts
.micromips
);
4928 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
4935 INSERT_OPERAND (mips_opts
.micromips
,
4936 SHAMT
, insn
, va_arg (args
, int));
4940 gas_assert (!mips_opts
.micromips
);
4941 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
4945 gas_assert (!mips_opts
.micromips
);
4946 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
4950 gas_assert (!mips_opts
.micromips
);
4951 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
4955 gas_assert (!mips_opts
.micromips
);
4956 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
4963 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
4968 macro_read_relocs (&args
, r
);
4969 gas_assert (*r
== BFD_RELOC_GPREL16
4970 || *r
== BFD_RELOC_MIPS_HIGHER
4971 || *r
== BFD_RELOC_HI16_S
4972 || *r
== BFD_RELOC_LO16
4973 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
4977 macro_read_relocs (&args
, r
);
4981 macro_read_relocs (&args
, r
);
4982 gas_assert (ep
!= NULL
4983 && (ep
->X_op
== O_constant
4984 || (ep
->X_op
== O_symbol
4985 && (*r
== BFD_RELOC_MIPS_HIGHEST
4986 || *r
== BFD_RELOC_HI16_S
4987 || *r
== BFD_RELOC_HI16
4988 || *r
== BFD_RELOC_GPREL16
4989 || *r
== BFD_RELOC_MIPS_GOT_HI16
4990 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
4994 gas_assert (ep
!= NULL
);
4997 * This allows macro() to pass an immediate expression for
4998 * creating short branches without creating a symbol.
5000 * We don't allow branch relaxation for these branches, as
5001 * they should only appear in ".set nomacro" anyway.
5003 if (ep
->X_op
== O_constant
)
5005 /* For microMIPS we always use relocations for branches.
5006 So we should not resolve immediate values. */
5007 gas_assert (!mips_opts
.micromips
);
5009 if ((ep
->X_add_number
& 3) != 0)
5010 as_bad (_("branch to misaligned address (0x%lx)"),
5011 (unsigned long) ep
->X_add_number
);
5012 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5013 as_bad (_("branch address range overflow (0x%lx)"),
5014 (unsigned long) ep
->X_add_number
);
5015 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5019 *r
= BFD_RELOC_16_PCREL_S2
;
5023 gas_assert (ep
!= NULL
);
5024 *r
= BFD_RELOC_MIPS_JMP
;
5028 gas_assert (!mips_opts
.micromips
);
5029 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5033 INSERT_OPERAND (mips_opts
.micromips
,
5034 CACHE
, insn
, va_arg (args
, unsigned long));
5038 gas_assert (mips_opts
.micromips
);
5039 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5043 gas_assert (mips_opts
.micromips
);
5044 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5048 gas_assert (mips_opts
.micromips
);
5049 INSERT_OPERAND (1, OFFSET12
, insn
, va_arg (args
, unsigned long));
5053 gas_assert (mips_opts
.micromips
);
5054 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5057 case 'm': /* Opcode extension character. */
5058 gas_assert (mips_opts
.micromips
);
5062 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5066 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5070 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5084 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5086 append_insn (&insn
, ep
, r
, TRUE
);
5090 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5093 struct mips_opcode
*mo
;
5094 struct mips_cl_insn insn
;
5095 bfd_reloc_code_real_type r
[3]
5096 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5098 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5100 gas_assert (strcmp (name
, mo
->name
) == 0);
5102 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5105 gas_assert (mo
->name
);
5106 gas_assert (strcmp (name
, mo
->name
) == 0);
5109 create_insn (&insn
, mo
);
5127 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5132 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5136 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5140 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5150 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5157 regno
= va_arg (*args
, int);
5158 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5159 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5180 gas_assert (ep
!= NULL
);
5182 if (ep
->X_op
!= O_constant
)
5183 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5186 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
5187 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
5190 *r
= BFD_RELOC_UNUSED
;
5196 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5203 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5205 append_insn (&insn
, ep
, r
, TRUE
);
5209 * Sign-extend 32-bit mode constants that have bit 31 set and all
5210 * higher bits unset.
5213 normalize_constant_expr (expressionS
*ex
)
5215 if (ex
->X_op
== O_constant
5216 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5217 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5222 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5223 * all higher bits unset.
5226 normalize_address_expr (expressionS
*ex
)
5228 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5229 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5230 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5231 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5236 * Generate a "jalr" instruction with a relocation hint to the called
5237 * function. This occurs in NewABI PIC code.
5240 macro_build_jalr (expressionS
*ep
, int cprestore
)
5242 static const bfd_reloc_code_real_type jalr_relocs
[2]
5243 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5244 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5248 if (MIPS_JALR_HINT_P (ep
))
5253 if (!mips_opts
.micromips
)
5254 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5257 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5258 if (MIPS_JALR_HINT_P (ep
))
5259 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5261 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5263 if (MIPS_JALR_HINT_P (ep
))
5264 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5268 * Generate a "lui" instruction.
5271 macro_build_lui (expressionS
*ep
, int regnum
)
5273 gas_assert (! mips_opts
.mips16
);
5275 if (ep
->X_op
!= O_constant
)
5277 gas_assert (ep
->X_op
== O_symbol
);
5278 /* _gp_disp is a special case, used from s_cpload.
5279 __gnu_local_gp is used if mips_no_shared. */
5280 gas_assert (mips_pic
== NO_PIC
5282 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5283 || (! mips_in_shared
5284 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5285 "__gnu_local_gp") == 0));
5288 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5291 /* Generate a sequence of instructions to do a load or store from a constant
5292 offset off of a base register (breg) into/from a target register (treg),
5293 using AT if necessary. */
5295 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5296 int treg
, int breg
, int dbl
)
5298 gas_assert (ep
->X_op
== O_constant
);
5300 /* Sign-extending 32-bit constants makes their handling easier. */
5302 normalize_constant_expr (ep
);
5304 /* Right now, this routine can only handle signed 32-bit constants. */
5305 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5306 as_warn (_("operand overflow"));
5308 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5310 /* Signed 16-bit offset will fit in the op. Easy! */
5311 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5315 /* 32-bit offset, need multiple instructions and AT, like:
5316 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5317 addu $tempreg,$tempreg,$breg
5318 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5319 to handle the complete offset. */
5320 macro_build_lui (ep
, AT
);
5321 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5322 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5325 as_bad (_("Macro used $at after \".set noat\""));
5330 * Generates code to set the $at register to true (one)
5331 * if reg is less than the immediate expression.
5334 set_at (int reg
, int unsignedp
)
5336 if (imm_expr
.X_op
== O_constant
5337 && imm_expr
.X_add_number
>= -0x8000
5338 && imm_expr
.X_add_number
< 0x8000)
5339 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5340 AT
, reg
, BFD_RELOC_LO16
);
5343 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5344 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5348 /* Warn if an expression is not a constant. */
5351 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5353 if (ex
->X_op
== O_big
)
5354 as_bad (_("unsupported large constant"));
5355 else if (ex
->X_op
!= O_constant
)
5356 as_bad (_("Instruction %s requires absolute expression"),
5359 if (HAVE_32BIT_GPRS
)
5360 normalize_constant_expr (ex
);
5363 /* Count the leading zeroes by performing a binary chop. This is a
5364 bulky bit of source, but performance is a LOT better for the
5365 majority of values than a simple loop to count the bits:
5366 for (lcnt = 0; (lcnt < 32); lcnt++)
5367 if ((v) & (1 << (31 - lcnt)))
5369 However it is not code size friendly, and the gain will drop a bit
5370 on certain cached systems.
5372 #define COUNT_TOP_ZEROES(v) \
5373 (((v) & ~0xffff) == 0 \
5374 ? ((v) & ~0xff) == 0 \
5375 ? ((v) & ~0xf) == 0 \
5376 ? ((v) & ~0x3) == 0 \
5377 ? ((v) & ~0x1) == 0 \
5382 : ((v) & ~0x7) == 0 \
5385 : ((v) & ~0x3f) == 0 \
5386 ? ((v) & ~0x1f) == 0 \
5389 : ((v) & ~0x7f) == 0 \
5392 : ((v) & ~0xfff) == 0 \
5393 ? ((v) & ~0x3ff) == 0 \
5394 ? ((v) & ~0x1ff) == 0 \
5397 : ((v) & ~0x7ff) == 0 \
5400 : ((v) & ~0x3fff) == 0 \
5401 ? ((v) & ~0x1fff) == 0 \
5404 : ((v) & ~0x7fff) == 0 \
5407 : ((v) & ~0xffffff) == 0 \
5408 ? ((v) & ~0xfffff) == 0 \
5409 ? ((v) & ~0x3ffff) == 0 \
5410 ? ((v) & ~0x1ffff) == 0 \
5413 : ((v) & ~0x7ffff) == 0 \
5416 : ((v) & ~0x3fffff) == 0 \
5417 ? ((v) & ~0x1fffff) == 0 \
5420 : ((v) & ~0x7fffff) == 0 \
5423 : ((v) & ~0xfffffff) == 0 \
5424 ? ((v) & ~0x3ffffff) == 0 \
5425 ? ((v) & ~0x1ffffff) == 0 \
5428 : ((v) & ~0x7ffffff) == 0 \
5431 : ((v) & ~0x3fffffff) == 0 \
5432 ? ((v) & ~0x1fffffff) == 0 \
5435 : ((v) & ~0x7fffffff) == 0 \
5440 * This routine generates the least number of instructions necessary to load
5441 * an absolute expression value into a register.
5444 load_register (int reg
, expressionS
*ep
, int dbl
)
5447 expressionS hi32
, lo32
;
5449 if (ep
->X_op
!= O_big
)
5451 gas_assert (ep
->X_op
== O_constant
);
5453 /* Sign-extending 32-bit constants makes their handling easier. */
5455 normalize_constant_expr (ep
);
5457 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5459 /* We can handle 16 bit signed values with an addiu to
5460 $zero. No need to ever use daddiu here, since $zero and
5461 the result are always correct in 32 bit mode. */
5462 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5465 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5467 /* We can handle 16 bit unsigned values with an ori to
5469 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5472 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5474 /* 32 bit values require an lui. */
5475 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5476 if ((ep
->X_add_number
& 0xffff) != 0)
5477 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5482 /* The value is larger than 32 bits. */
5484 if (!dbl
|| HAVE_32BIT_GPRS
)
5488 sprintf_vma (value
, ep
->X_add_number
);
5489 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5490 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5494 if (ep
->X_op
!= O_big
)
5497 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5498 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5499 hi32
.X_add_number
&= 0xffffffff;
5501 lo32
.X_add_number
&= 0xffffffff;
5505 gas_assert (ep
->X_add_number
> 2);
5506 if (ep
->X_add_number
== 3)
5507 generic_bignum
[3] = 0;
5508 else if (ep
->X_add_number
> 4)
5509 as_bad (_("Number larger than 64 bits"));
5510 lo32
.X_op
= O_constant
;
5511 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5512 hi32
.X_op
= O_constant
;
5513 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5516 if (hi32
.X_add_number
== 0)
5521 unsigned long hi
, lo
;
5523 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5525 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5527 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5530 if (lo32
.X_add_number
& 0x80000000)
5532 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5533 if (lo32
.X_add_number
& 0xffff)
5534 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5539 /* Check for 16bit shifted constant. We know that hi32 is
5540 non-zero, so start the mask on the first bit of the hi32
5545 unsigned long himask
, lomask
;
5549 himask
= 0xffff >> (32 - shift
);
5550 lomask
= (0xffff << shift
) & 0xffffffff;
5554 himask
= 0xffff << (shift
- 32);
5557 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5558 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5562 tmp
.X_op
= O_constant
;
5564 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5565 | (lo32
.X_add_number
>> shift
));
5567 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5568 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5569 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5570 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5575 while (shift
<= (64 - 16));
5577 /* Find the bit number of the lowest one bit, and store the
5578 shifted value in hi/lo. */
5579 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5580 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5584 while ((lo
& 1) == 0)
5589 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5595 while ((hi
& 1) == 0)
5604 /* Optimize if the shifted value is a (power of 2) - 1. */
5605 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5606 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5608 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5613 /* This instruction will set the register to be all
5615 tmp
.X_op
= O_constant
;
5616 tmp
.X_add_number
= (offsetT
) -1;
5617 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5621 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5622 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5624 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5625 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5630 /* Sign extend hi32 before calling load_register, because we can
5631 generally get better code when we load a sign extended value. */
5632 if ((hi32
.X_add_number
& 0x80000000) != 0)
5633 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5634 load_register (reg
, &hi32
, 0);
5637 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5641 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5649 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5651 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5652 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5658 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5662 mid16
.X_add_number
>>= 16;
5663 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5664 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5667 if ((lo32
.X_add_number
& 0xffff) != 0)
5668 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5672 load_delay_nop (void)
5674 if (!gpr_interlocks
)
5675 macro_build (NULL
, "nop", "");
5678 /* Load an address into a register. */
5681 load_address (int reg
, expressionS
*ep
, int *used_at
)
5683 if (ep
->X_op
!= O_constant
5684 && ep
->X_op
!= O_symbol
)
5686 as_bad (_("expression too complex"));
5687 ep
->X_op
= O_constant
;
5690 if (ep
->X_op
== O_constant
)
5692 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5696 if (mips_pic
== NO_PIC
)
5698 /* If this is a reference to a GP relative symbol, we want
5699 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5701 lui $reg,<sym> (BFD_RELOC_HI16_S)
5702 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5703 If we have an addend, we always use the latter form.
5705 With 64bit address space and a usable $at we want
5706 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5707 lui $at,<sym> (BFD_RELOC_HI16_S)
5708 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5709 daddiu $at,<sym> (BFD_RELOC_LO16)
5713 If $at is already in use, we use a path which is suboptimal
5714 on superscalar processors.
5715 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5716 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5718 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5720 daddiu $reg,<sym> (BFD_RELOC_LO16)
5722 For GP relative symbols in 64bit address space we can use
5723 the same sequence as in 32bit address space. */
5724 if (HAVE_64BIT_SYMBOLS
)
5726 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5727 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5729 relax_start (ep
->X_add_symbol
);
5730 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5731 mips_gp_register
, BFD_RELOC_GPREL16
);
5735 if (*used_at
== 0 && mips_opts
.at
)
5737 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5738 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5739 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5740 BFD_RELOC_MIPS_HIGHER
);
5741 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5742 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5743 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5748 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5749 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5750 BFD_RELOC_MIPS_HIGHER
);
5751 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5752 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5753 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5754 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5757 if (mips_relax
.sequence
)
5762 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5763 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5765 relax_start (ep
->X_add_symbol
);
5766 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5767 mips_gp_register
, BFD_RELOC_GPREL16
);
5770 macro_build_lui (ep
, reg
);
5771 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5772 reg
, reg
, BFD_RELOC_LO16
);
5773 if (mips_relax
.sequence
)
5777 else if (!mips_big_got
)
5781 /* If this is a reference to an external symbol, we want
5782 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5784 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5786 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5787 If there is a constant, it must be added in after.
5789 If we have NewABI, we want
5790 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5791 unless we're referencing a global symbol with a non-zero
5792 offset, in which case cst must be added separately. */
5795 if (ep
->X_add_number
)
5797 ex
.X_add_number
= ep
->X_add_number
;
5798 ep
->X_add_number
= 0;
5799 relax_start (ep
->X_add_symbol
);
5800 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5801 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5802 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5803 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5804 ex
.X_op
= O_constant
;
5805 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5806 reg
, reg
, BFD_RELOC_LO16
);
5807 ep
->X_add_number
= ex
.X_add_number
;
5810 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5811 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5812 if (mips_relax
.sequence
)
5817 ex
.X_add_number
= ep
->X_add_number
;
5818 ep
->X_add_number
= 0;
5819 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5820 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5822 relax_start (ep
->X_add_symbol
);
5824 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5828 if (ex
.X_add_number
!= 0)
5830 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5831 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5832 ex
.X_op
= O_constant
;
5833 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5834 reg
, reg
, BFD_RELOC_LO16
);
5838 else if (mips_big_got
)
5842 /* This is the large GOT case. If this is a reference to an
5843 external symbol, we want
5844 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5846 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5848 Otherwise, for a reference to a local symbol in old ABI, we want
5849 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5851 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5852 If there is a constant, it must be added in after.
5854 In the NewABI, for local symbols, with or without offsets, we want:
5855 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5856 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5860 ex
.X_add_number
= ep
->X_add_number
;
5861 ep
->X_add_number
= 0;
5862 relax_start (ep
->X_add_symbol
);
5863 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5864 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5865 reg
, reg
, mips_gp_register
);
5866 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5867 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5868 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5869 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5870 else if (ex
.X_add_number
)
5872 ex
.X_op
= O_constant
;
5873 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5877 ep
->X_add_number
= ex
.X_add_number
;
5879 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5880 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5881 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5882 BFD_RELOC_MIPS_GOT_OFST
);
5887 ex
.X_add_number
= ep
->X_add_number
;
5888 ep
->X_add_number
= 0;
5889 relax_start (ep
->X_add_symbol
);
5890 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5891 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5892 reg
, reg
, mips_gp_register
);
5893 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5894 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5896 if (reg_needs_delay (mips_gp_register
))
5898 /* We need a nop before loading from $gp. This special
5899 check is required because the lui which starts the main
5900 instruction stream does not refer to $gp, and so will not
5901 insert the nop which may be required. */
5902 macro_build (NULL
, "nop", "");
5904 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5905 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5907 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5911 if (ex
.X_add_number
!= 0)
5913 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5914 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5915 ex
.X_op
= O_constant
;
5916 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5924 if (!mips_opts
.at
&& *used_at
== 1)
5925 as_bad (_("Macro used $at after \".set noat\""));
5928 /* Move the contents of register SOURCE into register DEST. */
5931 move_register (int dest
, int source
)
5933 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5934 instruction specifically requires a 32-bit one. */
5935 if (mips_opts
.micromips
5936 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5937 macro_build (NULL
, "move", "mp,mj", dest
, source
);
5939 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
5943 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5944 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5945 The two alternatives are:
5947 Global symbol Local sybmol
5948 ------------- ------------
5949 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5951 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5953 load_got_offset emits the first instruction and add_got_offset
5954 emits the second for a 16-bit offset or add_got_offset_hilo emits
5955 a sequence to add a 32-bit offset using a scratch register. */
5958 load_got_offset (int dest
, expressionS
*local
)
5963 global
.X_add_number
= 0;
5965 relax_start (local
->X_add_symbol
);
5966 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
5967 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5969 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
5970 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5975 add_got_offset (int dest
, expressionS
*local
)
5979 global
.X_op
= O_constant
;
5980 global
.X_op_symbol
= NULL
;
5981 global
.X_add_symbol
= NULL
;
5982 global
.X_add_number
= local
->X_add_number
;
5984 relax_start (local
->X_add_symbol
);
5985 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
5986 dest
, dest
, BFD_RELOC_LO16
);
5988 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
5993 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
5996 int hold_mips_optimize
;
5998 global
.X_op
= O_constant
;
5999 global
.X_op_symbol
= NULL
;
6000 global
.X_add_symbol
= NULL
;
6001 global
.X_add_number
= local
->X_add_number
;
6003 relax_start (local
->X_add_symbol
);
6004 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6006 /* Set mips_optimize around the lui instruction to avoid
6007 inserting an unnecessary nop after the lw. */
6008 hold_mips_optimize
= mips_optimize
;
6010 macro_build_lui (&global
, tmp
);
6011 mips_optimize
= hold_mips_optimize
;
6012 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6015 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6018 /* Emit a sequence of instructions to emulate a branch likely operation.
6019 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6020 is its complementing branch with the original condition negated.
6021 CALL is set if the original branch specified the link operation.
6022 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6024 Code like this is produced in the noreorder mode:
6029 delay slot (executed only if branch taken)
6037 delay slot (executed only if branch taken)
6040 In the reorder mode the delay slot would be filled with a nop anyway,
6041 so code produced is simply:
6046 This function is used when producing code for the microMIPS ASE that
6047 does not implement branch likely instructions in hardware. */
6050 macro_build_branch_likely (const char *br
, const char *brneg
,
6051 int call
, expressionS
*ep
, const char *fmt
,
6052 unsigned int sreg
, unsigned int treg
)
6054 int noreorder
= mips_opts
.noreorder
;
6057 gas_assert (mips_opts
.micromips
);
6061 micromips_label_expr (&expr1
);
6062 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6063 macro_build (NULL
, "nop", "");
6064 macro_build (ep
, call
? "bal" : "b", "p");
6066 /* Set to true so that append_insn adds a label. */
6067 emit_branch_likely_macro
= TRUE
;
6071 macro_build (ep
, br
, fmt
, sreg
, treg
);
6072 macro_build (NULL
, "nop", "");
6077 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6078 the condition code tested. EP specifies the branch target. */
6081 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6108 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6111 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6112 the register tested. EP specifies the branch target. */
6115 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6117 const char *brneg
= NULL
;
6127 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6131 gas_assert (mips_opts
.micromips
);
6140 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6147 br
= mips_opts
.micromips
? "blez" : "blezl";
6154 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6158 gas_assert (mips_opts
.micromips
);
6166 if (mips_opts
.micromips
&& brneg
)
6167 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6169 macro_build (ep
, br
, "s,p", sreg
);
6172 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6173 TREG as the registers tested. EP specifies the branch target. */
6176 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6177 unsigned int sreg
, unsigned int treg
)
6179 const char *brneg
= NULL
;
6191 br
= mips_opts
.micromips
? "beq" : "beql";
6200 br
= mips_opts
.micromips
? "bne" : "bnel";
6206 if (mips_opts
.micromips
&& brneg
)
6207 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6209 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6214 * This routine implements the seemingly endless macro or synthesized
6215 * instructions and addressing modes in the mips assembly language. Many
6216 * of these macros are simple and are similar to each other. These could
6217 * probably be handled by some kind of table or grammar approach instead of
6218 * this verbose method. Others are not simple macros but are more like
6219 * optimizing code generation.
6220 * One interesting optimization is when several store macros appear
6221 * consecutively that would load AT with the upper half of the same address.
6222 * The ensuing load upper instructions are ommited. This implies some kind
6223 * of global optimization. We currently only optimize within a single macro.
6224 * For many of the load and store macros if the address is specified as a
6225 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6226 * first load register 'at' with zero and use it as the base register. The
6227 * mips assembler simply uses register $zero. Just one tiny optimization
6231 macro (struct mips_cl_insn
*ip
)
6233 unsigned int treg
, sreg
, dreg
, breg
;
6234 unsigned int tempreg
;
6237 expressionS label_expr
;
6255 bfd_reloc_code_real_type r
;
6256 int hold_mips_optimize
;
6258 gas_assert (! mips_opts
.mips16
);
6260 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6261 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6262 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6263 mask
= ip
->insn_mo
->mask
;
6265 label_expr
.X_op
= O_constant
;
6266 label_expr
.X_op_symbol
= NULL
;
6267 label_expr
.X_add_symbol
= NULL
;
6268 label_expr
.X_add_number
= 0;
6270 expr1
.X_op
= O_constant
;
6271 expr1
.X_op_symbol
= NULL
;
6272 expr1
.X_add_symbol
= NULL
;
6273 expr1
.X_add_number
= 1;
6288 if (mips_opts
.micromips
)
6289 micromips_label_expr (&label_expr
);
6291 label_expr
.X_add_number
= 8;
6292 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6294 macro_build (NULL
, "nop", "");
6296 move_register (dreg
, sreg
);
6297 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6298 if (mips_opts
.micromips
)
6299 micromips_add_label ();
6316 if (!mips_opts
.micromips
)
6318 if (imm_expr
.X_op
== O_constant
6319 && imm_expr
.X_add_number
>= -0x200
6320 && imm_expr
.X_add_number
< 0x200)
6322 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6331 if (imm_expr
.X_op
== O_constant
6332 && imm_expr
.X_add_number
>= -0x8000
6333 && imm_expr
.X_add_number
< 0x8000)
6335 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6340 load_register (AT
, &imm_expr
, dbl
);
6341 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6360 if (imm_expr
.X_op
== O_constant
6361 && imm_expr
.X_add_number
>= 0
6362 && imm_expr
.X_add_number
< 0x10000)
6364 if (mask
!= M_NOR_I
)
6365 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6368 macro_build (&imm_expr
, "ori", "t,r,i",
6369 treg
, sreg
, BFD_RELOC_LO16
);
6370 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6376 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6377 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6381 switch (imm_expr
.X_add_number
)
6384 macro_build (NULL
, "nop", "");
6387 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6390 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6391 (int) imm_expr
.X_add_number
);
6400 gas_assert (mips_opts
.micromips
);
6401 macro_build_branch_ccl (mask
, &offset_expr
,
6402 EXTRACT_OPERAND (1, BCC
, *ip
));
6409 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6415 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6420 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6427 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6429 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6433 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6434 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6435 &offset_expr
, AT
, ZERO
);
6445 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6451 /* Check for > max integer. */
6452 maxnum
= 0x7fffffff;
6453 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6460 if (imm_expr
.X_op
== O_constant
6461 && imm_expr
.X_add_number
>= maxnum
6462 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6465 /* Result is always false. */
6467 macro_build (NULL
, "nop", "");
6469 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6472 if (imm_expr
.X_op
!= O_constant
)
6473 as_bad (_("Unsupported large constant"));
6474 ++imm_expr
.X_add_number
;
6478 if (mask
== M_BGEL_I
)
6480 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6482 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6483 &offset_expr
, sreg
);
6486 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6488 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6489 &offset_expr
, sreg
);
6492 maxnum
= 0x7fffffff;
6493 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6500 maxnum
= - maxnum
- 1;
6501 if (imm_expr
.X_op
== O_constant
6502 && imm_expr
.X_add_number
<= maxnum
6503 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6506 /* result is always true */
6507 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6508 macro_build (&offset_expr
, "b", "p");
6513 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6514 &offset_expr
, AT
, ZERO
);
6523 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6524 &offset_expr
, ZERO
, treg
);
6528 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6529 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6530 &offset_expr
, AT
, ZERO
);
6539 && imm_expr
.X_op
== O_constant
6540 && imm_expr
.X_add_number
== -1))
6542 if (imm_expr
.X_op
!= O_constant
)
6543 as_bad (_("Unsupported large constant"));
6544 ++imm_expr
.X_add_number
;
6548 if (mask
== M_BGEUL_I
)
6550 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6552 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6553 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6554 &offset_expr
, sreg
, ZERO
);
6559 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6560 &offset_expr
, AT
, ZERO
);
6568 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6570 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6574 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6575 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6576 &offset_expr
, AT
, ZERO
);
6584 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6585 &offset_expr
, sreg
, ZERO
);
6591 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6592 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6593 &offset_expr
, AT
, ZERO
);
6601 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6603 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6607 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6608 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6609 &offset_expr
, AT
, ZERO
);
6616 maxnum
= 0x7fffffff;
6617 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6624 if (imm_expr
.X_op
== O_constant
6625 && imm_expr
.X_add_number
>= maxnum
6626 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6628 if (imm_expr
.X_op
!= O_constant
)
6629 as_bad (_("Unsupported large constant"));
6630 ++imm_expr
.X_add_number
;
6634 if (mask
== M_BLTL_I
)
6636 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6637 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6638 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6639 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6644 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6645 &offset_expr
, AT
, ZERO
);
6653 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6654 &offset_expr
, sreg
, ZERO
);
6660 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6661 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6662 &offset_expr
, AT
, ZERO
);
6671 && imm_expr
.X_op
== O_constant
6672 && imm_expr
.X_add_number
== -1))
6674 if (imm_expr
.X_op
!= O_constant
)
6675 as_bad (_("Unsupported large constant"));
6676 ++imm_expr
.X_add_number
;
6680 if (mask
== M_BLTUL_I
)
6682 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6684 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6685 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6686 &offset_expr
, sreg
, ZERO
);
6691 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6692 &offset_expr
, AT
, ZERO
);
6700 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6702 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6706 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6707 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6708 &offset_expr
, AT
, ZERO
);
6718 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6719 &offset_expr
, ZERO
, treg
);
6723 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6724 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6725 &offset_expr
, AT
, ZERO
);
6731 /* Use unsigned arithmetic. */
6735 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6737 as_bad (_("Unsupported large constant"));
6742 pos
= imm_expr
.X_add_number
;
6743 size
= imm2_expr
.X_add_number
;
6748 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6751 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6753 as_bad (_("Improper extract size (%lu, position %lu)"),
6754 (unsigned long) size
, (unsigned long) pos
);
6758 if (size
<= 32 && pos
< 32)
6763 else if (size
<= 32)
6773 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6780 /* Use unsigned arithmetic. */
6784 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6786 as_bad (_("Unsupported large constant"));
6791 pos
= imm_expr
.X_add_number
;
6792 size
= imm2_expr
.X_add_number
;
6797 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6800 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6802 as_bad (_("Improper insert size (%lu, position %lu)"),
6803 (unsigned long) size
, (unsigned long) pos
);
6807 if (pos
< 32 && (pos
+ size
- 1) < 32)
6822 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6823 (int) (pos
+ size
- 1));
6839 as_warn (_("Divide by zero."));
6841 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6843 macro_build (NULL
, "break", BRK_FMT
, 7);
6850 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
6851 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6855 if (mips_opts
.micromips
)
6856 micromips_label_expr (&label_expr
);
6858 label_expr
.X_add_number
= 8;
6859 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
6860 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6861 macro_build (NULL
, "break", BRK_FMT
, 7);
6862 if (mips_opts
.micromips
)
6863 micromips_add_label ();
6865 expr1
.X_add_number
= -1;
6867 load_register (AT
, &expr1
, dbl
);
6868 if (mips_opts
.micromips
)
6869 micromips_label_expr (&label_expr
);
6871 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
6872 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
6875 expr1
.X_add_number
= 1;
6876 load_register (AT
, &expr1
, dbl
);
6877 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
6881 expr1
.X_add_number
= 0x80000000;
6882 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
6886 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
6887 /* We want to close the noreorder block as soon as possible, so
6888 that later insns are available for delay slot filling. */
6893 if (mips_opts
.micromips
)
6894 micromips_label_expr (&label_expr
);
6896 label_expr
.X_add_number
= 8;
6897 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
6898 macro_build (NULL
, "nop", "");
6900 /* We want to close the noreorder block as soon as possible, so
6901 that later insns are available for delay slot filling. */
6904 macro_build (NULL
, "break", BRK_FMT
, 6);
6906 if (mips_opts
.micromips
)
6907 micromips_add_label ();
6908 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
6947 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6949 as_warn (_("Divide by zero."));
6951 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6953 macro_build (NULL
, "break", BRK_FMT
, 7);
6956 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6958 if (strcmp (s2
, "mflo") == 0)
6959 move_register (dreg
, sreg
);
6961 move_register (dreg
, ZERO
);
6964 if (imm_expr
.X_op
== O_constant
6965 && imm_expr
.X_add_number
== -1
6966 && s
[strlen (s
) - 1] != 'u')
6968 if (strcmp (s2
, "mflo") == 0)
6970 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
6973 move_register (dreg
, ZERO
);
6978 load_register (AT
, &imm_expr
, dbl
);
6979 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
6980 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7002 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7003 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7004 /* We want to close the noreorder block as soon as possible, so
7005 that later insns are available for delay slot filling. */
7010 if (mips_opts
.micromips
)
7011 micromips_label_expr (&label_expr
);
7013 label_expr
.X_add_number
= 8;
7014 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7015 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7017 /* We want to close the noreorder block as soon as possible, so
7018 that later insns are available for delay slot filling. */
7020 macro_build (NULL
, "break", BRK_FMT
, 7);
7021 if (mips_opts
.micromips
)
7022 micromips_add_label ();
7024 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7036 /* Load the address of a symbol into a register. If breg is not
7037 zero, we then add a base register to it. */
7039 if (dbl
&& HAVE_32BIT_GPRS
)
7040 as_warn (_("dla used to load 32-bit register"));
7042 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7043 as_warn (_("la used to load 64-bit address"));
7045 if (offset_expr
.X_op
== O_constant
7046 && offset_expr
.X_add_number
>= -0x8000
7047 && offset_expr
.X_add_number
< 0x8000)
7049 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7050 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7054 if (mips_opts
.at
&& (treg
== breg
))
7064 if (offset_expr
.X_op
!= O_symbol
7065 && offset_expr
.X_op
!= O_constant
)
7067 as_bad (_("Expression too complex"));
7068 offset_expr
.X_op
= O_constant
;
7071 if (offset_expr
.X_op
== O_constant
)
7072 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7073 else if (mips_pic
== NO_PIC
)
7075 /* If this is a reference to a GP relative symbol, we want
7076 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7078 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7079 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7080 If we have a constant, we need two instructions anyhow,
7081 so we may as well always use the latter form.
7083 With 64bit address space and a usable $at we want
7084 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7085 lui $at,<sym> (BFD_RELOC_HI16_S)
7086 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7087 daddiu $at,<sym> (BFD_RELOC_LO16)
7089 daddu $tempreg,$tempreg,$at
7091 If $at is already in use, we use a path which is suboptimal
7092 on superscalar processors.
7093 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7094 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7096 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7098 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7100 For GP relative symbols in 64bit address space we can use
7101 the same sequence as in 32bit address space. */
7102 if (HAVE_64BIT_SYMBOLS
)
7104 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7105 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7107 relax_start (offset_expr
.X_add_symbol
);
7108 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7109 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7113 if (used_at
== 0 && mips_opts
.at
)
7115 macro_build (&offset_expr
, "lui", LUI_FMT
,
7116 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7117 macro_build (&offset_expr
, "lui", LUI_FMT
,
7118 AT
, BFD_RELOC_HI16_S
);
7119 macro_build (&offset_expr
, "daddiu", "t,r,j",
7120 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7121 macro_build (&offset_expr
, "daddiu", "t,r,j",
7122 AT
, AT
, BFD_RELOC_LO16
);
7123 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7124 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7129 macro_build (&offset_expr
, "lui", LUI_FMT
,
7130 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7131 macro_build (&offset_expr
, "daddiu", "t,r,j",
7132 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7133 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7134 macro_build (&offset_expr
, "daddiu", "t,r,j",
7135 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7136 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7137 macro_build (&offset_expr
, "daddiu", "t,r,j",
7138 tempreg
, tempreg
, BFD_RELOC_LO16
);
7141 if (mips_relax
.sequence
)
7146 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7147 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7149 relax_start (offset_expr
.X_add_symbol
);
7150 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7151 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7154 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7155 as_bad (_("Offset too large"));
7156 macro_build_lui (&offset_expr
, tempreg
);
7157 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7158 tempreg
, tempreg
, BFD_RELOC_LO16
);
7159 if (mips_relax
.sequence
)
7163 else if (!mips_big_got
&& !HAVE_NEWABI
)
7165 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7167 /* If this is a reference to an external symbol, and there
7168 is no constant, we want
7169 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7170 or for lca or if tempreg is PIC_CALL_REG
7171 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7172 For a local symbol, we want
7173 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7175 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7177 If we have a small constant, and this is a reference to
7178 an external symbol, we want
7179 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7181 addiu $tempreg,$tempreg,<constant>
7182 For a local symbol, we want the same instruction
7183 sequence, but we output a BFD_RELOC_LO16 reloc on the
7186 If we have a large constant, and this is a reference to
7187 an external symbol, we want
7188 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7189 lui $at,<hiconstant>
7190 addiu $at,$at,<loconstant>
7191 addu $tempreg,$tempreg,$at
7192 For a local symbol, we want the same instruction
7193 sequence, but we output a BFD_RELOC_LO16 reloc on the
7197 if (offset_expr
.X_add_number
== 0)
7199 if (mips_pic
== SVR4_PIC
7201 && (call
|| tempreg
== PIC_CALL_REG
))
7202 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7204 relax_start (offset_expr
.X_add_symbol
);
7205 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7206 lw_reloc_type
, mips_gp_register
);
7209 /* We're going to put in an addu instruction using
7210 tempreg, so we may as well insert the nop right
7215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7216 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7218 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7219 tempreg
, tempreg
, BFD_RELOC_LO16
);
7221 /* FIXME: If breg == 0, and the next instruction uses
7222 $tempreg, then if this variant case is used an extra
7223 nop will be generated. */
7225 else if (offset_expr
.X_add_number
>= -0x8000
7226 && offset_expr
.X_add_number
< 0x8000)
7228 load_got_offset (tempreg
, &offset_expr
);
7230 add_got_offset (tempreg
, &offset_expr
);
7234 expr1
.X_add_number
= offset_expr
.X_add_number
;
7235 offset_expr
.X_add_number
=
7236 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
7237 load_got_offset (tempreg
, &offset_expr
);
7238 offset_expr
.X_add_number
= expr1
.X_add_number
;
7239 /* If we are going to add in a base register, and the
7240 target register and the base register are the same,
7241 then we are using AT as a temporary register. Since
7242 we want to load the constant into AT, we add our
7243 current AT (from the global offset table) and the
7244 register into the register now, and pretend we were
7245 not using a base register. */
7249 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7254 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7258 else if (!mips_big_got
&& HAVE_NEWABI
)
7260 int add_breg_early
= 0;
7262 /* If this is a reference to an external, and there is no
7263 constant, or local symbol (*), with or without a
7265 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7266 or for lca or if tempreg is PIC_CALL_REG
7267 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7269 If we have a small constant, and this is a reference to
7270 an external symbol, we want
7271 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7272 addiu $tempreg,$tempreg,<constant>
7274 If we have a large constant, and this is a reference to
7275 an external symbol, we want
7276 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7277 lui $at,<hiconstant>
7278 addiu $at,$at,<loconstant>
7279 addu $tempreg,$tempreg,$at
7281 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7282 local symbols, even though it introduces an additional
7285 if (offset_expr
.X_add_number
)
7287 expr1
.X_add_number
= offset_expr
.X_add_number
;
7288 offset_expr
.X_add_number
= 0;
7290 relax_start (offset_expr
.X_add_symbol
);
7291 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7292 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7294 if (expr1
.X_add_number
>= -0x8000
7295 && expr1
.X_add_number
< 0x8000)
7297 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7298 tempreg
, tempreg
, BFD_RELOC_LO16
);
7300 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7302 /* If we are going to add in a base register, and the
7303 target register and the base register are the same,
7304 then we are using AT as a temporary register. Since
7305 we want to load the constant into AT, we add our
7306 current AT (from the global offset table) and the
7307 register into the register now, and pretend we were
7308 not using a base register. */
7313 gas_assert (tempreg
== AT
);
7314 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7320 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7321 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7327 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7330 offset_expr
.X_add_number
= expr1
.X_add_number
;
7332 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7333 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7336 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7337 treg
, tempreg
, breg
);
7343 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7345 relax_start (offset_expr
.X_add_symbol
);
7346 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7347 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7349 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7350 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7355 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7356 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7359 else if (mips_big_got
&& !HAVE_NEWABI
)
7362 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7363 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7364 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7366 /* This is the large GOT case. If this is a reference to an
7367 external symbol, and there is no constant, we want
7368 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7369 addu $tempreg,$tempreg,$gp
7370 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7371 or for lca or if tempreg is PIC_CALL_REG
7372 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7373 addu $tempreg,$tempreg,$gp
7374 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7375 For a local symbol, we want
7376 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7378 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7380 If we have a small constant, and this is a reference to
7381 an external symbol, we want
7382 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7383 addu $tempreg,$tempreg,$gp
7384 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7386 addiu $tempreg,$tempreg,<constant>
7387 For a local symbol, we want
7388 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7390 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7392 If we have a large constant, and this is a reference to
7393 an external symbol, we want
7394 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7395 addu $tempreg,$tempreg,$gp
7396 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7397 lui $at,<hiconstant>
7398 addiu $at,$at,<loconstant>
7399 addu $tempreg,$tempreg,$at
7400 For a local symbol, we want
7401 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7402 lui $at,<hiconstant>
7403 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7404 addu $tempreg,$tempreg,$at
7407 expr1
.X_add_number
= offset_expr
.X_add_number
;
7408 offset_expr
.X_add_number
= 0;
7409 relax_start (offset_expr
.X_add_symbol
);
7410 gpdelay
= reg_needs_delay (mips_gp_register
);
7411 if (expr1
.X_add_number
== 0 && breg
== 0
7412 && (call
|| tempreg
== PIC_CALL_REG
))
7414 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7415 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7417 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7418 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7419 tempreg
, tempreg
, mips_gp_register
);
7420 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7421 tempreg
, lw_reloc_type
, tempreg
);
7422 if (expr1
.X_add_number
== 0)
7426 /* We're going to put in an addu instruction using
7427 tempreg, so we may as well insert the nop right
7432 else if (expr1
.X_add_number
>= -0x8000
7433 && expr1
.X_add_number
< 0x8000)
7436 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7437 tempreg
, tempreg
, BFD_RELOC_LO16
);
7441 /* If we are going to add in a base register, and the
7442 target register and the base register are the same,
7443 then we are using AT as a temporary register. Since
7444 we want to load the constant into AT, we add our
7445 current AT (from the global offset table) and the
7446 register into the register now, and pretend we were
7447 not using a base register. */
7452 gas_assert (tempreg
== AT
);
7454 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7459 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7460 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7464 offset_expr
.X_add_number
=
7465 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
7470 /* This is needed because this instruction uses $gp, but
7471 the first instruction on the main stream does not. */
7472 macro_build (NULL
, "nop", "");
7475 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7476 local_reloc_type
, mips_gp_register
);
7477 if (expr1
.X_add_number
>= -0x8000
7478 && expr1
.X_add_number
< 0x8000)
7481 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7482 tempreg
, tempreg
, BFD_RELOC_LO16
);
7483 /* FIXME: If add_number is 0, and there was no base
7484 register, the external symbol case ended with a load,
7485 so if the symbol turns out to not be external, and
7486 the next instruction uses tempreg, an unnecessary nop
7487 will be inserted. */
7493 /* We must add in the base register now, as in the
7494 external symbol case. */
7495 gas_assert (tempreg
== AT
);
7497 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7500 /* We set breg to 0 because we have arranged to add
7501 it in in both cases. */
7505 macro_build_lui (&expr1
, AT
);
7506 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7507 AT
, AT
, BFD_RELOC_LO16
);
7508 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7509 tempreg
, tempreg
, AT
);
7514 else if (mips_big_got
&& HAVE_NEWABI
)
7516 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7517 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7518 int add_breg_early
= 0;
7520 /* This is the large GOT case. If this is a reference to an
7521 external symbol, and there is no constant, we want
7522 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7523 add $tempreg,$tempreg,$gp
7524 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7525 or for lca or if tempreg is PIC_CALL_REG
7526 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7527 add $tempreg,$tempreg,$gp
7528 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7530 If we have a small constant, and this is a reference to
7531 an external symbol, we want
7532 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7533 add $tempreg,$tempreg,$gp
7534 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7535 addi $tempreg,$tempreg,<constant>
7537 If we have a large constant, and this is a reference to
7538 an external symbol, we want
7539 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7540 addu $tempreg,$tempreg,$gp
7541 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7542 lui $at,<hiconstant>
7543 addi $at,$at,<loconstant>
7544 add $tempreg,$tempreg,$at
7546 If we have NewABI, and we know it's a local symbol, we want
7547 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7548 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7549 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7551 relax_start (offset_expr
.X_add_symbol
);
7553 expr1
.X_add_number
= offset_expr
.X_add_number
;
7554 offset_expr
.X_add_number
= 0;
7556 if (expr1
.X_add_number
== 0 && breg
== 0
7557 && (call
|| tempreg
== PIC_CALL_REG
))
7559 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7560 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7562 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7563 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7564 tempreg
, tempreg
, mips_gp_register
);
7565 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7566 tempreg
, lw_reloc_type
, tempreg
);
7568 if (expr1
.X_add_number
== 0)
7570 else if (expr1
.X_add_number
>= -0x8000
7571 && expr1
.X_add_number
< 0x8000)
7573 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7574 tempreg
, tempreg
, BFD_RELOC_LO16
);
7576 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7578 /* If we are going to add in a base register, and the
7579 target register and the base register are the same,
7580 then we are using AT as a temporary register. Since
7581 we want to load the constant into AT, we add our
7582 current AT (from the global offset table) and the
7583 register into the register now, and pretend we were
7584 not using a base register. */
7589 gas_assert (tempreg
== AT
);
7590 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7596 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7597 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7602 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7605 offset_expr
.X_add_number
= expr1
.X_add_number
;
7606 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7607 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7608 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7609 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7612 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7613 treg
, tempreg
, breg
);
7623 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7627 gas_assert (!mips_opts
.micromips
);
7629 unsigned long temp
= (treg
<< 16) | (0x01);
7630 macro_build (NULL
, "c2", "C", temp
);
7635 gas_assert (!mips_opts
.micromips
);
7637 unsigned long temp
= (0x02);
7638 macro_build (NULL
, "c2", "C", temp
);
7643 gas_assert (!mips_opts
.micromips
);
7645 unsigned long temp
= (treg
<< 16) | (0x02);
7646 macro_build (NULL
, "c2", "C", temp
);
7651 gas_assert (!mips_opts
.micromips
);
7652 macro_build (NULL
, "c2", "C", 3);
7656 gas_assert (!mips_opts
.micromips
);
7658 unsigned long temp
= (treg
<< 16) | 0x03;
7659 macro_build (NULL
, "c2", "C", temp
);
7664 /* The j instruction may not be used in PIC code, since it
7665 requires an absolute address. We convert it to a b
7667 if (mips_pic
== NO_PIC
)
7668 macro_build (&offset_expr
, "j", "a");
7670 macro_build (&offset_expr
, "b", "p");
7673 /* The jal instructions must be handled as macros because when
7674 generating PIC code they expand to multi-instruction
7675 sequences. Normally they are simple instructions. */
7680 gas_assert (mips_opts
.micromips
);
7688 if (mips_pic
== NO_PIC
)
7690 s
= jals
? "jalrs" : "jalr";
7691 if (mips_opts
.micromips
&& dreg
== RA
)
7692 macro_build (NULL
, s
, "mj", sreg
);
7694 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7698 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7699 && mips_cprestore_offset
>= 0);
7701 if (sreg
!= PIC_CALL_REG
)
7702 as_warn (_("MIPS PIC call to register other than $25"));
7704 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7705 ? "jalrs" : "jalr");
7706 if (mips_opts
.micromips
&& dreg
== RA
)
7707 macro_build (NULL
, s
, "mj", sreg
);
7709 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7710 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7712 if (mips_cprestore_offset
< 0)
7713 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7716 if (!mips_frame_reg_valid
)
7718 as_warn (_("No .frame pseudo-op used in PIC code"));
7719 /* Quiet this warning. */
7720 mips_frame_reg_valid
= 1;
7722 if (!mips_cprestore_valid
)
7724 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7725 /* Quiet this warning. */
7726 mips_cprestore_valid
= 1;
7728 if (mips_opts
.noreorder
)
7729 macro_build (NULL
, "nop", "");
7730 expr1
.X_add_number
= mips_cprestore_offset
;
7731 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7734 HAVE_64BIT_ADDRESSES
);
7742 gas_assert (mips_opts
.micromips
);
7746 if (mips_pic
== NO_PIC
)
7747 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7748 else if (mips_pic
== SVR4_PIC
)
7750 /* If this is a reference to an external symbol, and we are
7751 using a small GOT, we want
7752 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7756 lw $gp,cprestore($sp)
7757 The cprestore value is set using the .cprestore
7758 pseudo-op. If we are using a big GOT, we want
7759 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7761 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7765 lw $gp,cprestore($sp)
7766 If the symbol is not external, we want
7767 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7769 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7772 lw $gp,cprestore($sp)
7774 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7775 sequences above, minus nops, unless the symbol is local,
7776 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7782 relax_start (offset_expr
.X_add_symbol
);
7783 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7784 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7787 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7788 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7794 relax_start (offset_expr
.X_add_symbol
);
7795 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7796 BFD_RELOC_MIPS_CALL_HI16
);
7797 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7798 PIC_CALL_REG
, mips_gp_register
);
7799 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7800 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7803 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7804 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
7806 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7807 PIC_CALL_REG
, PIC_CALL_REG
,
7808 BFD_RELOC_MIPS_GOT_OFST
);
7812 macro_build_jalr (&offset_expr
, 0);
7816 relax_start (offset_expr
.X_add_symbol
);
7819 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7820 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7829 gpdelay
= reg_needs_delay (mips_gp_register
);
7830 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7831 BFD_RELOC_MIPS_CALL_HI16
);
7832 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7833 PIC_CALL_REG
, mips_gp_register
);
7834 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7835 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7840 macro_build (NULL
, "nop", "");
7842 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7843 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
7846 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7847 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
7849 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
7851 if (mips_cprestore_offset
< 0)
7852 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7855 if (!mips_frame_reg_valid
)
7857 as_warn (_("No .frame pseudo-op used in PIC code"));
7858 /* Quiet this warning. */
7859 mips_frame_reg_valid
= 1;
7861 if (!mips_cprestore_valid
)
7863 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7864 /* Quiet this warning. */
7865 mips_cprestore_valid
= 1;
7867 if (mips_opts
.noreorder
)
7868 macro_build (NULL
, "nop", "");
7869 expr1
.X_add_number
= mips_cprestore_offset
;
7870 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7873 HAVE_64BIT_ADDRESSES
);
7877 else if (mips_pic
== VXWORKS_PIC
)
7878 as_bad (_("Non-PIC jump used in PIC library"));
7911 gas_assert (!mips_opts
.micromips
);
7914 /* Itbl support may require additional care here. */
7921 /* Itbl support may require additional care here. */
7929 off12
= mips_opts
.micromips
;
7930 /* Itbl support may require additional care here. */
7935 gas_assert (!mips_opts
.micromips
);
7938 /* Itbl support may require additional care here. */
7946 off12
= mips_opts
.micromips
;
7953 off12
= mips_opts
.micromips
;
7959 /* Itbl support may require additional care here. */
7967 off12
= mips_opts
.micromips
;
7968 /* Itbl support may require additional care here. */
7975 /* Itbl support may require additional care here. */
7983 off12
= mips_opts
.micromips
;
7990 off12
= mips_opts
.micromips
;
7997 off12
= mips_opts
.micromips
;
8004 off12
= mips_opts
.micromips
;
8011 off12
= mips_opts
.micromips
;
8016 gas_assert (mips_opts
.micromips
);
8025 gas_assert (mips_opts
.micromips
);
8034 gas_assert (mips_opts
.micromips
);
8042 gas_assert (mips_opts
.micromips
);
8049 if (breg
== treg
+ lp
)
8052 tempreg
= treg
+ lp
;
8072 gas_assert (!mips_opts
.micromips
);
8075 /* Itbl support may require additional care here. */
8082 /* Itbl support may require additional care here. */
8090 off12
= mips_opts
.micromips
;
8091 /* Itbl support may require additional care here. */
8096 gas_assert (!mips_opts
.micromips
);
8099 /* Itbl support may require additional care here. */
8107 off12
= mips_opts
.micromips
;
8114 off12
= mips_opts
.micromips
;
8121 off12
= mips_opts
.micromips
;
8128 off12
= mips_opts
.micromips
;
8134 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8135 off12
= mips_opts
.micromips
;
8141 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8142 off12
= mips_opts
.micromips
;
8149 /* Itbl support may require additional care here. */
8156 off12
= mips_opts
.micromips
;
8157 /* Itbl support may require additional care here. */
8162 gas_assert (!mips_opts
.micromips
);
8165 /* Itbl support may require additional care here. */
8173 off12
= mips_opts
.micromips
;
8180 off12
= mips_opts
.micromips
;
8185 gas_assert (mips_opts
.micromips
);
8193 gas_assert (mips_opts
.micromips
);
8201 gas_assert (mips_opts
.micromips
);
8209 gas_assert (mips_opts
.micromips
);
8219 && NO_ISA_COP (mips_opts
.arch
)
8220 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
8222 as_bad (_("Opcode not supported on this processor: %s"),
8223 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
8227 if (offset_expr
.X_op
!= O_constant
8228 && offset_expr
.X_op
!= O_symbol
)
8230 as_bad (_("Expression too complex"));
8231 offset_expr
.X_op
= O_constant
;
8234 if (HAVE_32BIT_ADDRESSES
8235 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8239 sprintf_vma (value
, offset_expr
.X_add_number
);
8240 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8243 /* A constant expression in PIC code can be handled just as it
8244 is in non PIC code. */
8245 if (offset_expr
.X_op
== O_constant
)
8249 expr1
.X_add_number
= offset_expr
.X_add_number
;
8250 normalize_address_expr (&expr1
);
8251 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8253 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8254 & ~(bfd_vma
) 0xffff);
8257 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8259 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8260 & ~(bfd_vma
) 0xfff);
8265 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8267 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8268 tempreg
, tempreg
, breg
);
8272 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8274 macro_build (NULL
, s
, fmt
,
8275 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8279 /* A 12-bit offset field is too narrow to be used for a low-part
8280 relocation, so load the whole address into the auxillary
8281 register. In the case of "A(b)" addresses, we first load
8282 absolute address "A" into the register and then add base
8283 register "b". In the case of "o(b)" addresses, we simply
8284 need to add 16-bit offset "o" to base register "b", and
8285 offset_reloc already contains the relocations associated
8289 load_address (tempreg
, &offset_expr
, &used_at
);
8291 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8292 tempreg
, tempreg
, breg
);
8295 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8297 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8298 expr1
.X_add_number
= 0;
8299 macro_build (NULL
, s
, fmt
,
8300 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8302 else if (mips_pic
== NO_PIC
)
8304 /* If this is a reference to a GP relative symbol, and there
8305 is no base register, we want
8306 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8307 Otherwise, if there is no base register, we want
8308 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8309 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8310 If we have a constant, we need two instructions anyhow,
8311 so we always use the latter form.
8313 If we have a base register, and this is a reference to a
8314 GP relative symbol, we want
8315 addu $tempreg,$breg,$gp
8316 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8318 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8319 addu $tempreg,$tempreg,$breg
8320 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8321 With a constant we always use the latter case.
8323 With 64bit address space and no base register and $at usable,
8325 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8326 lui $at,<sym> (BFD_RELOC_HI16_S)
8327 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8330 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8331 If we have a base register, we want
8332 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8333 lui $at,<sym> (BFD_RELOC_HI16_S)
8334 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8338 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8340 Without $at we can't generate the optimal path for superscalar
8341 processors here since this would require two temporary registers.
8342 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8343 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8345 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8347 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8348 If we have a base register, we want
8349 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8350 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8352 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8354 daddu $tempreg,$tempreg,$breg
8355 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8357 For GP relative symbols in 64bit address space we can use
8358 the same sequence as in 32bit address space. */
8359 if (HAVE_64BIT_SYMBOLS
)
8361 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8362 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8364 relax_start (offset_expr
.X_add_symbol
);
8367 macro_build (&offset_expr
, s
, fmt
, treg
,
8368 BFD_RELOC_GPREL16
, mips_gp_register
);
8372 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8373 tempreg
, breg
, mips_gp_register
);
8374 macro_build (&offset_expr
, s
, fmt
, treg
,
8375 BFD_RELOC_GPREL16
, tempreg
);
8380 if (used_at
== 0 && mips_opts
.at
)
8382 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8383 BFD_RELOC_MIPS_HIGHEST
);
8384 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8386 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8387 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8389 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8390 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8391 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8392 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8398 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8399 BFD_RELOC_MIPS_HIGHEST
);
8400 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8401 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8402 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8403 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8404 tempreg
, BFD_RELOC_HI16_S
);
8405 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8407 macro_build (NULL
, "daddu", "d,v,t",
8408 tempreg
, tempreg
, breg
);
8409 macro_build (&offset_expr
, s
, fmt
, treg
,
8410 BFD_RELOC_LO16
, tempreg
);
8413 if (mips_relax
.sequence
)
8420 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8421 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8423 relax_start (offset_expr
.X_add_symbol
);
8424 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8428 macro_build_lui (&offset_expr
, tempreg
);
8429 macro_build (&offset_expr
, s
, fmt
, treg
,
8430 BFD_RELOC_LO16
, tempreg
);
8431 if (mips_relax
.sequence
)
8436 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8437 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8439 relax_start (offset_expr
.X_add_symbol
);
8440 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8441 tempreg
, breg
, mips_gp_register
);
8442 macro_build (&offset_expr
, s
, fmt
, treg
,
8443 BFD_RELOC_GPREL16
, tempreg
);
8446 macro_build_lui (&offset_expr
, tempreg
);
8447 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8448 tempreg
, tempreg
, breg
);
8449 macro_build (&offset_expr
, s
, fmt
, treg
,
8450 BFD_RELOC_LO16
, tempreg
);
8451 if (mips_relax
.sequence
)
8455 else if (!mips_big_got
)
8457 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8459 /* If this is a reference to an external symbol, we want
8460 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8462 <op> $treg,0($tempreg)
8464 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8466 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8467 <op> $treg,0($tempreg)
8470 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8471 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8473 If there is a base register, we add it to $tempreg before
8474 the <op>. If there is a constant, we stick it in the
8475 <op> instruction. We don't handle constants larger than
8476 16 bits, because we have no way to load the upper 16 bits
8477 (actually, we could handle them for the subset of cases
8478 in which we are not using $at). */
8479 gas_assert (offset_expr
.X_op
== O_symbol
);
8482 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8483 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8485 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8486 tempreg
, tempreg
, breg
);
8487 macro_build (&offset_expr
, s
, fmt
, treg
,
8488 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8491 expr1
.X_add_number
= offset_expr
.X_add_number
;
8492 offset_expr
.X_add_number
= 0;
8493 if (expr1
.X_add_number
< -0x8000
8494 || expr1
.X_add_number
>= 0x8000)
8495 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8496 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8497 lw_reloc_type
, mips_gp_register
);
8499 relax_start (offset_expr
.X_add_symbol
);
8501 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8502 tempreg
, BFD_RELOC_LO16
);
8505 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8506 tempreg
, tempreg
, breg
);
8507 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8509 else if (mips_big_got
&& !HAVE_NEWABI
)
8513 /* If this is a reference to an external symbol, we want
8514 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8515 addu $tempreg,$tempreg,$gp
8516 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8517 <op> $treg,0($tempreg)
8519 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8521 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8522 <op> $treg,0($tempreg)
8523 If there is a base register, we add it to $tempreg before
8524 the <op>. If there is a constant, we stick it in the
8525 <op> instruction. We don't handle constants larger than
8526 16 bits, because we have no way to load the upper 16 bits
8527 (actually, we could handle them for the subset of cases
8528 in which we are not using $at). */
8529 gas_assert (offset_expr
.X_op
== O_symbol
);
8530 expr1
.X_add_number
= offset_expr
.X_add_number
;
8531 offset_expr
.X_add_number
= 0;
8532 if (expr1
.X_add_number
< -0x8000
8533 || expr1
.X_add_number
>= 0x8000)
8534 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8535 gpdelay
= reg_needs_delay (mips_gp_register
);
8536 relax_start (offset_expr
.X_add_symbol
);
8537 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8538 BFD_RELOC_MIPS_GOT_HI16
);
8539 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8541 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8542 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8545 macro_build (NULL
, "nop", "");
8546 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8547 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8549 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8550 tempreg
, BFD_RELOC_LO16
);
8554 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8555 tempreg
, tempreg
, breg
);
8556 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8558 else if (mips_big_got
&& HAVE_NEWABI
)
8560 /* If this is a reference to an external symbol, we want
8561 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8562 add $tempreg,$tempreg,$gp
8563 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8564 <op> $treg,<ofst>($tempreg)
8565 Otherwise, for local symbols, we want:
8566 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8567 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8568 gas_assert (offset_expr
.X_op
== O_symbol
);
8569 expr1
.X_add_number
= offset_expr
.X_add_number
;
8570 offset_expr
.X_add_number
= 0;
8571 if (expr1
.X_add_number
< -0x8000
8572 || expr1
.X_add_number
>= 0x8000)
8573 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8574 relax_start (offset_expr
.X_add_symbol
);
8575 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8576 BFD_RELOC_MIPS_GOT_HI16
);
8577 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8579 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8580 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8582 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8583 tempreg
, tempreg
, breg
);
8584 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8587 offset_expr
.X_add_number
= expr1
.X_add_number
;
8588 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8589 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8591 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8592 tempreg
, tempreg
, breg
);
8593 macro_build (&offset_expr
, s
, fmt
, treg
,
8594 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8604 load_register (treg
, &imm_expr
, 0);
8608 load_register (treg
, &imm_expr
, 1);
8612 if (imm_expr
.X_op
== O_constant
)
8615 load_register (AT
, &imm_expr
, 0);
8616 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8621 gas_assert (offset_expr
.X_op
== O_symbol
8622 && strcmp (segment_name (S_GET_SEGMENT
8623 (offset_expr
.X_add_symbol
)),
8625 && offset_expr
.X_add_number
== 0);
8626 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8627 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8632 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8633 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8634 order 32 bits of the value and the low order 32 bits are either
8635 zero or in OFFSET_EXPR. */
8636 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8638 if (HAVE_64BIT_GPRS
)
8639 load_register (treg
, &imm_expr
, 1);
8644 if (target_big_endian
)
8656 load_register (hreg
, &imm_expr
, 0);
8659 if (offset_expr
.X_op
== O_absent
)
8660 move_register (lreg
, 0);
8663 gas_assert (offset_expr
.X_op
== O_constant
);
8664 load_register (lreg
, &offset_expr
, 0);
8671 /* We know that sym is in the .rdata section. First we get the
8672 upper 16 bits of the address. */
8673 if (mips_pic
== NO_PIC
)
8675 macro_build_lui (&offset_expr
, AT
);
8680 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8681 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8685 /* Now we load the register(s). */
8686 if (HAVE_64BIT_GPRS
)
8689 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8694 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8697 /* FIXME: How in the world do we deal with the possible
8699 offset_expr
.X_add_number
+= 4;
8700 macro_build (&offset_expr
, "lw", "t,o(b)",
8701 treg
+ 1, BFD_RELOC_LO16
, AT
);
8707 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8708 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8709 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8710 the value and the low order 32 bits are either zero or in
8712 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8715 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8716 if (HAVE_64BIT_FPRS
)
8718 gas_assert (HAVE_64BIT_GPRS
);
8719 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8723 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8724 if (offset_expr
.X_op
== O_absent
)
8725 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8728 gas_assert (offset_expr
.X_op
== O_constant
);
8729 load_register (AT
, &offset_expr
, 0);
8730 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8736 gas_assert (offset_expr
.X_op
== O_symbol
8737 && offset_expr
.X_add_number
== 0);
8738 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8739 if (strcmp (s
, ".lit8") == 0)
8741 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8743 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8744 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8747 breg
= mips_gp_register
;
8748 r
= BFD_RELOC_MIPS_LITERAL
;
8753 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8755 if (mips_pic
!= NO_PIC
)
8756 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8757 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8760 /* FIXME: This won't work for a 64 bit address. */
8761 macro_build_lui (&offset_expr
, AT
);
8764 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8766 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8767 treg
, BFD_RELOC_LO16
, AT
);
8776 /* Even on a big endian machine $fn comes before $fn+1. We have
8777 to adjust when loading from memory. */
8780 gas_assert (!mips_opts
.micromips
);
8781 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8782 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8783 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8784 /* FIXME: A possible overflow which I don't know how to deal
8786 offset_expr
.X_add_number
+= 4;
8787 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8788 target_big_endian
? treg
: treg
+ 1, r
, breg
);
8792 gas_assert (!mips_opts
.micromips
);
8793 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8794 /* Even on a big endian machine $fn comes before $fn+1. We have
8795 to adjust when storing to memory. */
8796 macro_build (&offset_expr
, "swc1", "T,o(b)",
8797 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
8798 offset_expr
.X_add_number
+= 4;
8799 macro_build (&offset_expr
, "swc1", "T,o(b)",
8800 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
8804 gas_assert (!mips_opts
.micromips
);
8806 * The MIPS assembler seems to check for X_add_number not
8807 * being double aligned and generating:
8810 * addiu at,at,%lo(foo+1)
8813 * But, the resulting address is the same after relocation so why
8814 * generate the extra instruction?
8816 /* Itbl support may require additional care here. */
8819 if (mips_opts
.isa
!= ISA_MIPS1
)
8828 gas_assert (!mips_opts
.micromips
);
8829 /* Itbl support may require additional care here. */
8832 if (mips_opts
.isa
!= ISA_MIPS1
)
8842 if (HAVE_64BIT_GPRS
)
8852 if (HAVE_64BIT_GPRS
)
8860 if (offset_expr
.X_op
!= O_symbol
8861 && offset_expr
.X_op
!= O_constant
)
8863 as_bad (_("Expression too complex"));
8864 offset_expr
.X_op
= O_constant
;
8867 if (HAVE_32BIT_ADDRESSES
8868 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8872 sprintf_vma (value
, offset_expr
.X_add_number
);
8873 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8876 /* Even on a big endian machine $fn comes before $fn+1. We have
8877 to adjust when loading from memory. We set coproc if we must
8878 load $fn+1 first. */
8879 /* Itbl support may require additional care here. */
8880 if (!target_big_endian
)
8883 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
8885 /* If this is a reference to a GP relative symbol, we want
8886 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8887 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8888 If we have a base register, we use this
8890 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8891 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8892 If this is not a GP relative symbol, we want
8893 lui $at,<sym> (BFD_RELOC_HI16_S)
8894 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8895 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8896 If there is a base register, we add it to $at after the
8897 lui instruction. If there is a constant, we always use
8899 if (offset_expr
.X_op
== O_symbol
8900 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8901 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8903 relax_start (offset_expr
.X_add_symbol
);
8906 tempreg
= mips_gp_register
;
8910 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8911 AT
, breg
, mips_gp_register
);
8916 /* Itbl support may require additional care here. */
8917 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8918 BFD_RELOC_GPREL16
, tempreg
);
8919 offset_expr
.X_add_number
+= 4;
8921 /* Set mips_optimize to 2 to avoid inserting an
8923 hold_mips_optimize
= mips_optimize
;
8925 /* Itbl support may require additional care here. */
8926 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
8927 BFD_RELOC_GPREL16
, tempreg
);
8928 mips_optimize
= hold_mips_optimize
;
8932 offset_expr
.X_add_number
-= 4;
8935 macro_build_lui (&offset_expr
, AT
);
8937 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
8938 /* Itbl support may require additional care here. */
8939 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8940 BFD_RELOC_LO16
, AT
);
8941 /* FIXME: How do we handle overflow here? */
8942 offset_expr
.X_add_number
+= 4;
8943 /* Itbl support may require additional care here. */
8944 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
8945 BFD_RELOC_LO16
, AT
);
8946 if (mips_relax
.sequence
)
8949 else if (!mips_big_got
)
8951 /* If this is a reference to an external symbol, we want
8952 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8957 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8959 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8960 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8961 If there is a base register we add it to $at before the
8962 lwc1 instructions. If there is a constant we include it
8963 in the lwc1 instructions. */
8965 expr1
.X_add_number
= offset_expr
.X_add_number
;
8966 if (expr1
.X_add_number
< -0x8000
8967 || expr1
.X_add_number
>= 0x8000 - 4)
8968 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8969 load_got_offset (AT
, &offset_expr
);
8972 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
8974 /* Set mips_optimize to 2 to avoid inserting an undesired
8976 hold_mips_optimize
= mips_optimize
;
8979 /* Itbl support may require additional care here. */
8980 relax_start (offset_expr
.X_add_symbol
);
8981 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8982 BFD_RELOC_LO16
, AT
);
8983 expr1
.X_add_number
+= 4;
8984 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
8985 BFD_RELOC_LO16
, AT
);
8987 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8988 BFD_RELOC_LO16
, AT
);
8989 offset_expr
.X_add_number
+= 4;
8990 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
8991 BFD_RELOC_LO16
, AT
);
8994 mips_optimize
= hold_mips_optimize
;
8996 else if (mips_big_got
)
9000 /* If this is a reference to an external symbol, we want
9001 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9003 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9008 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9010 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9011 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9012 If there is a base register we add it to $at before the
9013 lwc1 instructions. If there is a constant we include it
9014 in the lwc1 instructions. */
9016 expr1
.X_add_number
= offset_expr
.X_add_number
;
9017 offset_expr
.X_add_number
= 0;
9018 if (expr1
.X_add_number
< -0x8000
9019 || expr1
.X_add_number
>= 0x8000 - 4)
9020 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9021 gpdelay
= reg_needs_delay (mips_gp_register
);
9022 relax_start (offset_expr
.X_add_symbol
);
9023 macro_build (&offset_expr
, "lui", LUI_FMT
,
9024 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9025 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9026 AT
, AT
, mips_gp_register
);
9027 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9028 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9032 /* Itbl support may require additional care here. */
9033 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9034 BFD_RELOC_LO16
, AT
);
9035 expr1
.X_add_number
+= 4;
9037 /* Set mips_optimize to 2 to avoid inserting an undesired
9039 hold_mips_optimize
= mips_optimize
;
9041 /* Itbl support may require additional care here. */
9042 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9043 BFD_RELOC_LO16
, AT
);
9044 mips_optimize
= hold_mips_optimize
;
9045 expr1
.X_add_number
-= 4;
9048 offset_expr
.X_add_number
= expr1
.X_add_number
;
9050 macro_build (NULL
, "nop", "");
9051 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9052 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9056 /* Itbl support may require additional care here. */
9057 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9058 BFD_RELOC_LO16
, AT
);
9059 offset_expr
.X_add_number
+= 4;
9061 /* Set mips_optimize to 2 to avoid inserting an undesired
9063 hold_mips_optimize
= mips_optimize
;
9065 /* Itbl support may require additional care here. */
9066 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9067 BFD_RELOC_LO16
, AT
);
9068 mips_optimize
= hold_mips_optimize
;
9077 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9080 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9082 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9083 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9085 if (!HAVE_64BIT_GPRS
)
9087 offset_expr
.X_add_number
+= 4;
9088 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9089 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9094 /* New code added to support COPZ instructions.
9095 This code builds table entries out of the macros in mip_opcodes.
9096 R4000 uses interlocks to handle coproc delays.
9097 Other chips (like the R3000) require nops to be inserted for delays.
9099 FIXME: Currently, we require that the user handle delays.
9100 In order to fill delay slots for non-interlocked chips,
9101 we must have a way to specify delays based on the coprocessor.
9102 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9103 What are the side-effects of the cop instruction?
9104 What cache support might we have and what are its effects?
9105 Both coprocessor & memory require delays. how long???
9106 What registers are read/set/modified?
9108 If an itbl is provided to interpret cop instructions,
9109 this knowledge can be encoded in the itbl spec. */
9123 gas_assert (!mips_opts
.micromips
);
9124 if (NO_ISA_COP (mips_opts
.arch
)
9125 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
9127 as_bad (_("opcode not supported on this processor: %s"),
9128 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
9132 /* For now we just do C (same as Cz). The parameter will be
9133 stored in insn_opcode by mips_ip. */
9134 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9138 move_register (dreg
, sreg
);
9144 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9145 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9151 /* The MIPS assembler some times generates shifts and adds. I'm
9152 not trying to be that fancy. GCC should do this for us
9155 load_register (AT
, &imm_expr
, dbl
);
9156 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9157 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9173 load_register (AT
, &imm_expr
, dbl
);
9174 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9175 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9176 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9177 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9179 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9182 if (mips_opts
.micromips
)
9183 micromips_label_expr (&label_expr
);
9185 label_expr
.X_add_number
= 8;
9186 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9187 macro_build (NULL
, "nop", "");
9188 macro_build (NULL
, "break", BRK_FMT
, 6);
9189 if (mips_opts
.micromips
)
9190 micromips_add_label ();
9193 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9209 load_register (AT
, &imm_expr
, dbl
);
9210 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9211 sreg
, imm
? AT
: treg
);
9212 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9213 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9215 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9218 if (mips_opts
.micromips
)
9219 micromips_label_expr (&label_expr
);
9221 label_expr
.X_add_number
= 8;
9222 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9223 macro_build (NULL
, "nop", "");
9224 macro_build (NULL
, "break", BRK_FMT
, 6);
9225 if (mips_opts
.micromips
)
9226 micromips_add_label ();
9232 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9243 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9244 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9248 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9249 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9250 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9251 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9255 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9266 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9267 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9271 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9272 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9273 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9274 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9283 if (imm_expr
.X_op
!= O_constant
)
9284 as_bad (_("Improper rotate count"));
9285 rot
= imm_expr
.X_add_number
& 0x3f;
9286 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9288 rot
= (64 - rot
) & 0x3f;
9290 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9292 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9297 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9300 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9301 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9304 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9305 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9306 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9314 if (imm_expr
.X_op
!= O_constant
)
9315 as_bad (_("Improper rotate count"));
9316 rot
= imm_expr
.X_add_number
& 0x1f;
9317 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9319 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9324 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9328 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9329 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9330 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9335 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9337 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9341 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9342 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9343 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9344 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9348 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9350 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9354 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9355 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9356 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9357 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9366 if (imm_expr
.X_op
!= O_constant
)
9367 as_bad (_("Improper rotate count"));
9368 rot
= imm_expr
.X_add_number
& 0x3f;
9369 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9372 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9374 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9379 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9382 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9383 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9386 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9387 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9388 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9396 if (imm_expr
.X_op
!= O_constant
)
9397 as_bad (_("Improper rotate count"));
9398 rot
= imm_expr
.X_add_number
& 0x1f;
9399 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9401 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9406 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9410 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9411 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9412 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9418 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9420 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9423 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9424 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9429 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9431 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9436 as_warn (_("Instruction %s: result is always false"),
9438 move_register (dreg
, 0);
9441 if (CPU_HAS_SEQ (mips_opts
.arch
)
9442 && -512 <= imm_expr
.X_add_number
9443 && imm_expr
.X_add_number
< 512)
9445 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9446 (int) imm_expr
.X_add_number
);
9449 if (imm_expr
.X_op
== O_constant
9450 && imm_expr
.X_add_number
>= 0
9451 && imm_expr
.X_add_number
< 0x10000)
9453 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9455 else if (imm_expr
.X_op
== O_constant
9456 && imm_expr
.X_add_number
> -0x8000
9457 && imm_expr
.X_add_number
< 0)
9459 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9460 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9461 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9463 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9466 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9467 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9472 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9473 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9476 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9479 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9485 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9486 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9489 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9491 if (imm_expr
.X_op
== O_constant
9492 && imm_expr
.X_add_number
>= -0x8000
9493 && imm_expr
.X_add_number
< 0x8000)
9495 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9496 dreg
, sreg
, BFD_RELOC_LO16
);
9500 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9501 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9505 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9508 case M_SGT
: /* sreg > treg <==> treg < sreg */
9514 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9517 case M_SGT_I
: /* sreg > I <==> I < sreg */
9524 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9525 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9528 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9534 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9535 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9538 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9545 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9546 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9547 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9551 if (imm_expr
.X_op
== O_constant
9552 && imm_expr
.X_add_number
>= -0x8000
9553 && imm_expr
.X_add_number
< 0x8000)
9555 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9559 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9560 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9564 if (imm_expr
.X_op
== O_constant
9565 && imm_expr
.X_add_number
>= -0x8000
9566 && imm_expr
.X_add_number
< 0x8000)
9568 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9573 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9574 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9579 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9581 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9584 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9585 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9590 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9592 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9597 as_warn (_("Instruction %s: result is always true"),
9599 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9600 dreg
, 0, BFD_RELOC_LO16
);
9603 if (CPU_HAS_SEQ (mips_opts
.arch
)
9604 && -512 <= imm_expr
.X_add_number
9605 && imm_expr
.X_add_number
< 512)
9607 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9608 (int) imm_expr
.X_add_number
);
9611 if (imm_expr
.X_op
== O_constant
9612 && imm_expr
.X_add_number
>= 0
9613 && imm_expr
.X_add_number
< 0x10000)
9615 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9617 else if (imm_expr
.X_op
== O_constant
9618 && imm_expr
.X_add_number
> -0x8000
9619 && imm_expr
.X_add_number
< 0)
9621 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9622 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9623 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9625 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9628 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9629 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9634 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9635 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9638 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9653 if (!mips_opts
.micromips
)
9655 if (imm_expr
.X_op
== O_constant
9656 && imm_expr
.X_add_number
> -0x200
9657 && imm_expr
.X_add_number
<= 0x200)
9659 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9668 if (imm_expr
.X_op
== O_constant
9669 && imm_expr
.X_add_number
> -0x8000
9670 && imm_expr
.X_add_number
<= 0x8000)
9672 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9673 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9678 load_register (AT
, &imm_expr
, dbl
);
9679 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9701 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9702 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9707 gas_assert (!mips_opts
.micromips
);
9708 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9710 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9711 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9714 * Is the double cfc1 instruction a bug in the mips assembler;
9715 * or is there a reason for it?
9718 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9719 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9720 macro_build (NULL
, "nop", "");
9721 expr1
.X_add_number
= 3;
9722 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9723 expr1
.X_add_number
= 2;
9724 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9725 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9726 macro_build (NULL
, "nop", "");
9727 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9729 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9730 macro_build (NULL
, "nop", "");
9753 off12
= mips_opts
.micromips
;
9761 off12
= mips_opts
.micromips
;
9777 off12
= mips_opts
.micromips
;
9786 off12
= mips_opts
.micromips
;
9791 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
9792 as_bad (_("Operand overflow"));
9795 expr1
.X_add_number
= 0;
9800 load_address (tempreg
, ep
, &used_at
);
9802 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9803 tempreg
, tempreg
, breg
);
9809 && (offset_expr
.X_op
!= O_constant
9810 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
9811 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
9815 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
9816 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9821 else if (!ust
&& treg
== breg
)
9832 if (!target_big_endian
)
9833 ep
->X_add_number
+= off
;
9835 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9837 macro_build (NULL
, s
, "t,~(b)",
9838 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9840 if (!target_big_endian
)
9841 ep
->X_add_number
-= off
;
9843 ep
->X_add_number
+= off
;
9845 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9847 macro_build (NULL
, s2
, "t,~(b)",
9848 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9850 /* If necessary, move the result in tempreg to the final destination. */
9851 if (!ust
&& treg
!= tempreg
)
9853 /* Protect second load's delay slot. */
9855 move_register (treg
, tempreg
);
9861 if (target_big_endian
== ust
)
9862 ep
->X_add_number
+= off
;
9863 tempreg
= ust
|| ab
? treg
: AT
;
9864 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9866 /* For halfword transfers we need a temporary register to shuffle
9867 bytes. Unfortunately for M_USH_A we have none available before
9868 the next store as AT holds the base address. We deal with this
9869 case by clobbering TREG and then restoring it as with ULH. */
9870 tempreg
= ust
== ab
? treg
: AT
;
9872 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
9874 if (target_big_endian
== ust
)
9875 ep
->X_add_number
-= off
;
9877 ep
->X_add_number
+= off
;
9878 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9880 /* For M_USH_A re-retrieve the LSB. */
9883 if (target_big_endian
)
9884 ep
->X_add_number
+= off
;
9886 ep
->X_add_number
-= off
;
9887 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
9889 /* For ULH and M_USH_A OR the LSB in. */
9892 tempreg
= !ab
? AT
: treg
;
9893 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
9894 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
9899 /* FIXME: Check if this is one of the itbl macros, since they
9900 are added dynamically. */
9901 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
9904 if (!mips_opts
.at
&& used_at
)
9905 as_bad (_("Macro used $at after \".set noat\""));
9908 /* Implement macros in mips16 mode. */
9911 mips16_macro (struct mips_cl_insn
*ip
)
9914 int xreg
, yreg
, zreg
, tmp
;
9917 const char *s
, *s2
, *s3
;
9919 mask
= ip
->insn_mo
->mask
;
9921 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
9922 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
9923 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
9925 expr1
.X_op
= O_constant
;
9926 expr1
.X_op_symbol
= NULL
;
9927 expr1
.X_add_symbol
= NULL
;
9928 expr1
.X_add_number
= 1;
9948 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
9949 expr1
.X_add_number
= 2;
9950 macro_build (&expr1
, "bnez", "x,p", yreg
);
9951 macro_build (NULL
, "break", "6", 7);
9953 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9954 since that causes an overflow. We should do that as well,
9955 but I don't see how to do the comparisons without a temporary
9958 macro_build (NULL
, s
, "x", zreg
);
9978 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
9979 expr1
.X_add_number
= 2;
9980 macro_build (&expr1
, "bnez", "x,p", yreg
);
9981 macro_build (NULL
, "break", "6", 7);
9983 macro_build (NULL
, s2
, "x", zreg
);
9989 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
9990 macro_build (NULL
, "mflo", "x", zreg
);
9998 if (imm_expr
.X_op
!= O_constant
)
9999 as_bad (_("Unsupported large constant"));
10000 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10001 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10005 if (imm_expr
.X_op
!= O_constant
)
10006 as_bad (_("Unsupported large constant"));
10007 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10008 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10012 if (imm_expr
.X_op
!= O_constant
)
10013 as_bad (_("Unsupported large constant"));
10014 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10015 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10037 goto do_reverse_branch
;
10041 goto do_reverse_branch
;
10053 goto do_reverse_branch
;
10064 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10065 macro_build (&offset_expr
, s2
, "p");
10092 goto do_addone_branch_i
;
10097 goto do_addone_branch_i
;
10112 goto do_addone_branch_i
;
10118 do_addone_branch_i
:
10119 if (imm_expr
.X_op
!= O_constant
)
10120 as_bad (_("Unsupported large constant"));
10121 ++imm_expr
.X_add_number
;
10124 macro_build (&imm_expr
, s
, s3
, xreg
);
10125 macro_build (&offset_expr
, s2
, "p");
10129 expr1
.X_add_number
= 0;
10130 macro_build (&expr1
, "slti", "x,8", yreg
);
10132 move_register (xreg
, yreg
);
10133 expr1
.X_add_number
= 2;
10134 macro_build (&expr1
, "bteqz", "p");
10135 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10139 /* For consistency checking, verify that all bits are specified either
10140 by the match/mask part of the instruction definition, or by the
10143 validate_mips_insn (const struct mips_opcode
*opc
)
10145 const char *p
= opc
->args
;
10147 unsigned long used_bits
= opc
->mask
;
10149 if ((used_bits
& opc
->match
) != opc
->match
)
10151 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10152 opc
->name
, opc
->args
);
10155 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10165 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10166 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10167 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10168 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10169 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10170 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10171 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10172 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10173 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10174 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10175 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10176 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10177 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10179 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10180 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10181 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10182 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10183 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10184 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10185 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10186 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10187 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10188 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10189 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10190 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10191 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10192 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10193 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10196 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10197 c
, opc
->name
, opc
->args
);
10201 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10202 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10204 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10205 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10206 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10207 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10209 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10210 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10212 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10213 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10215 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10216 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10217 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10218 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10219 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10220 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10221 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10222 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10223 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10224 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10225 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10226 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10227 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10228 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10229 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10230 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10231 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10233 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10234 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10235 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10236 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10238 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10239 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10240 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10241 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10242 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10243 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10244 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10245 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10246 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10249 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10250 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10251 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10252 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10253 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10256 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10257 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10258 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10259 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10260 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10261 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10262 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10263 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10264 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10265 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10266 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10267 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10268 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10269 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10270 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10271 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10272 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10273 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10275 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10276 c
, opc
->name
, opc
->args
);
10280 if (used_bits
!= 0xffffffff)
10282 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10283 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10289 /* For consistency checking, verify that the length implied matches the
10290 major opcode and that all bits are specified either by the match/mask
10291 part of the instruction definition, or by the operand list. */
10294 validate_micromips_insn (const struct mips_opcode
*opc
)
10296 unsigned long match
= opc
->match
;
10297 unsigned long mask
= opc
->mask
;
10298 const char *p
= opc
->args
;
10299 unsigned long insn_bits
;
10300 unsigned long used_bits
;
10301 unsigned long major
;
10302 unsigned int length
;
10306 if ((mask
& match
) != match
)
10308 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10309 opc
->name
, opc
->args
);
10312 length
= micromips_insn_length (opc
);
10313 if (length
!= 2 && length
!= 4)
10315 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10316 "%s %s"), length
, opc
->name
, opc
->args
);
10319 major
= match
>> (10 + 8 * (length
- 2));
10320 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10321 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10323 as_bad (_("Internal error: bad microMIPS opcode "
10324 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10328 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10329 insn_bits
= 1 << 4 * length
;
10330 insn_bits
<<= 4 * length
;
10333 #define USE_BITS(field) \
10334 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10345 case 'A': USE_BITS (EXTLSB
); break;
10346 case 'B': USE_BITS (INSMSB
); break;
10347 case 'C': USE_BITS (EXTMSBD
); break;
10348 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10349 case 'E': USE_BITS (EXTLSB
); break;
10350 case 'F': USE_BITS (INSMSB
); break;
10351 case 'G': USE_BITS (EXTMSBD
); break;
10352 case 'H': USE_BITS (EXTMSBD
); break;
10354 as_bad (_("Internal error: bad mips opcode "
10355 "(unknown extension operand type `%c%c'): %s %s"),
10356 e
, c
, opc
->name
, opc
->args
);
10364 case 'A': USE_BITS (IMMA
); break;
10365 case 'B': USE_BITS (IMMB
); break;
10366 case 'C': USE_BITS (IMMC
); break;
10367 case 'D': USE_BITS (IMMD
); break;
10368 case 'E': USE_BITS (IMME
); break;
10369 case 'F': USE_BITS (IMMF
); break;
10370 case 'G': USE_BITS (IMMG
); break;
10371 case 'H': USE_BITS (IMMH
); break;
10372 case 'I': USE_BITS (IMMI
); break;
10373 case 'J': USE_BITS (IMMJ
); break;
10374 case 'L': USE_BITS (IMML
); break;
10375 case 'M': USE_BITS (IMMM
); break;
10376 case 'N': USE_BITS (IMMN
); break;
10377 case 'O': USE_BITS (IMMO
); break;
10378 case 'P': USE_BITS (IMMP
); break;
10379 case 'Q': USE_BITS (IMMQ
); break;
10380 case 'U': USE_BITS (IMMU
); break;
10381 case 'W': USE_BITS (IMMW
); break;
10382 case 'X': USE_BITS (IMMX
); break;
10383 case 'Y': USE_BITS (IMMY
); break;
10386 case 'b': USE_BITS (MB
); break;
10387 case 'c': USE_BITS (MC
); break;
10388 case 'd': USE_BITS (MD
); break;
10389 case 'e': USE_BITS (ME
); break;
10390 case 'f': USE_BITS (MF
); break;
10391 case 'g': USE_BITS (MG
); break;
10392 case 'h': USE_BITS (MH
); break;
10393 case 'i': USE_BITS (MI
); break;
10394 case 'j': USE_BITS (MJ
); break;
10395 case 'l': USE_BITS (ML
); break;
10396 case 'm': USE_BITS (MM
); break;
10397 case 'n': USE_BITS (MN
); break;
10398 case 'p': USE_BITS (MP
); break;
10399 case 'q': USE_BITS (MQ
); break;
10407 as_bad (_("Internal error: bad mips opcode "
10408 "(unknown extension operand type `%c%c'): %s %s"),
10409 e
, c
, opc
->name
, opc
->args
);
10413 case '.': USE_BITS (OFFSET10
); break;
10414 case '1': USE_BITS (STYPE
); break;
10415 case '<': USE_BITS (SHAMT
); break;
10416 case '>': USE_BITS (SHAMT
); break;
10417 case 'B': USE_BITS (CODE10
); break;
10418 case 'C': USE_BITS (COPZ
); break;
10419 case 'D': USE_BITS (FD
); break;
10420 case 'E': USE_BITS (RT
); break;
10421 case 'G': USE_BITS (RS
); break;
10422 case 'H': USE_BITS (SEL
); break;
10423 case 'K': USE_BITS (RS
); break;
10424 case 'M': USE_BITS (CCC
); break;
10425 case 'N': USE_BITS (BCC
); break;
10426 case 'R': USE_BITS (FR
); break;
10427 case 'S': USE_BITS (FS
); break;
10428 case 'T': USE_BITS (FT
); break;
10429 case 'V': USE_BITS (FS
); break;
10430 case 'a': USE_BITS (TARGET
); break;
10431 case 'b': USE_BITS (RS
); break;
10432 case 'c': USE_BITS (CODE
); break;
10433 case 'd': USE_BITS (RD
); break;
10434 case 'h': USE_BITS (PREFX
); break;
10435 case 'i': USE_BITS (IMMEDIATE
); break;
10436 case 'j': USE_BITS (DELTA
); break;
10437 case 'k': USE_BITS (CACHE
); break;
10438 case 'n': USE_BITS (RT
); break;
10439 case 'o': USE_BITS (DELTA
); break;
10440 case 'p': USE_BITS (DELTA
); break;
10441 case 'q': USE_BITS (CODE2
); break;
10442 case 'r': USE_BITS (RS
); break;
10443 case 's': USE_BITS (RS
); break;
10444 case 't': USE_BITS (RT
); break;
10445 case 'u': USE_BITS (IMMEDIATE
); break;
10446 case 'v': USE_BITS (RS
); break;
10447 case 'w': USE_BITS (RT
); break;
10448 case 'y': USE_BITS (RS3
); break;
10450 case '|': USE_BITS (TRAP
); break;
10451 case '~': USE_BITS (OFFSET12
); break;
10453 as_bad (_("Internal error: bad microMIPS opcode "
10454 "(unknown operand type `%c'): %s %s"),
10455 c
, opc
->name
, opc
->args
);
10459 if (used_bits
!= insn_bits
)
10461 if (~used_bits
& insn_bits
)
10462 as_bad (_("Internal error: bad microMIPS opcode "
10463 "(bits 0x%lx undefined): %s %s"),
10464 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10465 if (used_bits
& ~insn_bits
)
10466 as_bad (_("Internal error: bad microMIPS opcode "
10467 "(bits 0x%lx defined): %s %s"),
10468 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10474 /* UDI immediates. */
10475 struct mips_immed
{
10477 unsigned int shift
;
10478 unsigned long mask
;
10482 static const struct mips_immed mips_immed
[] = {
10483 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10484 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10485 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10486 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10490 /* Check whether an odd floating-point register is allowed. */
10492 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10494 const char *s
= insn
->name
;
10496 if (insn
->pinfo
== INSN_MACRO
)
10497 /* Let a macro pass, we'll catch it later when it is expanded. */
10500 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
10502 /* Allow odd registers for single-precision ops. */
10503 switch (insn
->pinfo
& (FP_S
| FP_D
))
10507 return 1; /* both single precision - ok */
10509 return 0; /* both double precision - fail */
10514 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10515 s
= strchr (insn
->name
, '.');
10517 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10518 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10521 /* Single-precision coprocessor loads and moves are OK too. */
10522 if ((insn
->pinfo
& FP_S
)
10523 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10524 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10530 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10531 taking bits from BIT up. */
10533 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10535 return (ep
->X_op
== O_constant
10536 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10537 && ep
->X_add_number
>= min
<< bit
10538 && ep
->X_add_number
< max
<< bit
);
10541 /* This routine assembles an instruction into its binary format. As a
10542 side effect, it sets one of the global variables imm_reloc or
10543 offset_reloc to the type of relocation to do if one of the operands
10544 is an address expression. */
10547 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10549 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10550 bfd_boolean need_delay_slot_ok
= TRUE
;
10551 struct mips_opcode
*firstinsn
= NULL
;
10552 const struct mips_opcode
*past
;
10553 struct hash_control
*hash
;
10557 struct mips_opcode
*insn
;
10559 unsigned int regno
;
10560 unsigned int lastregno
;
10561 unsigned int destregno
= 0;
10562 unsigned int lastpos
= 0;
10563 unsigned int limlo
, limhi
;
10565 offsetT min_range
, max_range
;
10569 unsigned int rtype
;
10575 if (mips_opts
.micromips
)
10577 hash
= micromips_op_hash
;
10578 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10583 past
= &mips_opcodes
[NUMOPCODES
];
10585 forced_insn_length
= 0;
10588 /* We first try to match an instruction up to a space or to the end. */
10589 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10592 /* Make a copy of the instruction so that we can fiddle with it. */
10593 name
= alloca (end
+ 1);
10594 memcpy (name
, str
, end
);
10599 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10601 if (insn
!= NULL
|| !mips_opts
.micromips
)
10603 if (forced_insn_length
)
10606 /* See if there's an instruction size override suffix,
10607 either `16' or `32', at the end of the mnemonic proper,
10608 that defines the operation, i.e. before the first `.'
10609 character if any. Strip it and retry. */
10610 dot
= strchr (name
, '.');
10611 opend
= dot
!= NULL
? dot
- name
: end
;
10614 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10615 forced_insn_length
= 2;
10616 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10617 forced_insn_length
= 4;
10620 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10624 insn_error
= _("Unrecognized opcode");
10628 /* For microMIPS instructions placed in a fixed-length branch delay slot
10629 we make up to two passes over the relevant fragment of the opcode
10630 table. First we try instructions that meet the delay slot's length
10631 requirement. If none matched, then we retry with the remaining ones
10632 and if one matches, then we use it and then issue an appropriate
10633 warning later on. */
10634 argsStart
= s
= str
+ end
;
10637 bfd_boolean delay_slot_ok
;
10638 bfd_boolean size_ok
;
10641 gas_assert (strcmp (insn
->name
, name
) == 0);
10643 ok
= is_opcode_valid (insn
);
10644 size_ok
= is_size_valid (insn
);
10645 delay_slot_ok
= is_delay_slot_valid (insn
);
10646 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10649 wrong_delay_slot_insns
= TRUE
;
10651 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10653 static char buf
[256];
10655 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10660 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10662 gas_assert (firstinsn
);
10663 need_delay_slot_ok
= FALSE
;
10673 sprintf (buf
, _("opcode not supported on this processor: %s (%s)"),
10674 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10675 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10677 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10678 8 * forced_insn_length
);
10684 create_insn (ip
, insn
);
10687 lastregno
= 0xffffffff;
10688 for (args
= insn
->args
;; ++args
)
10692 s
+= strspn (s
, " \t");
10696 case '\0': /* end of args */
10701 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
10702 gas_assert (!mips_opts
.micromips
);
10703 my_getExpression (&imm_expr
, s
);
10704 check_absolute_expr (ip
, &imm_expr
);
10705 if ((unsigned long) imm_expr
.X_add_number
!= 1
10706 && (unsigned long) imm_expr
.X_add_number
!= 3)
10708 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10709 (unsigned long) imm_expr
.X_add_number
);
10711 INSERT_OPERAND (0, BP
, *ip
, imm_expr
.X_add_number
);
10712 imm_expr
.X_op
= O_absent
;
10716 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
10717 gas_assert (!mips_opts
.micromips
);
10718 my_getExpression (&imm_expr
, s
);
10719 check_absolute_expr (ip
, &imm_expr
);
10720 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
10722 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10723 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
10725 INSERT_OPERAND (0, SA3
, *ip
, imm_expr
.X_add_number
);
10726 imm_expr
.X_op
= O_absent
;
10730 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
10731 gas_assert (!mips_opts
.micromips
);
10732 my_getExpression (&imm_expr
, s
);
10733 check_absolute_expr (ip
, &imm_expr
);
10734 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
10736 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10737 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
10739 INSERT_OPERAND (0, SA4
, *ip
, imm_expr
.X_add_number
);
10740 imm_expr
.X_op
= O_absent
;
10744 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
10745 gas_assert (!mips_opts
.micromips
);
10746 my_getExpression (&imm_expr
, s
);
10747 check_absolute_expr (ip
, &imm_expr
);
10748 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
10750 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10751 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
10753 INSERT_OPERAND (0, IMM8
, *ip
, imm_expr
.X_add_number
);
10754 imm_expr
.X_op
= O_absent
;
10758 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
10759 gas_assert (!mips_opts
.micromips
);
10760 my_getExpression (&imm_expr
, s
);
10761 check_absolute_expr (ip
, &imm_expr
);
10762 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
10764 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10765 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
10767 INSERT_OPERAND (0, RS
, *ip
, imm_expr
.X_add_number
);
10768 imm_expr
.X_op
= O_absent
;
10772 case '7': /* Four DSP accumulators in bits 11,12. */
10773 gas_assert (!mips_opts
.micromips
);
10774 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
10775 s
[3] >= '0' && s
[3] <= '3')
10777 regno
= s
[3] - '0';
10779 INSERT_OPERAND (0, DSPACC
, *ip
, regno
);
10783 as_bad (_("Invalid dsp acc register"));
10786 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
10787 gas_assert (!mips_opts
.micromips
);
10788 my_getExpression (&imm_expr
, s
);
10789 check_absolute_expr (ip
, &imm_expr
);
10790 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
10792 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10794 (unsigned long) imm_expr
.X_add_number
);
10796 INSERT_OPERAND (0, WRDSP
, *ip
, imm_expr
.X_add_number
);
10797 imm_expr
.X_op
= O_absent
;
10801 case '9': /* Four DSP accumulators in bits 21,22. */
10802 gas_assert (!mips_opts
.micromips
);
10803 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
10804 s
[3] >= '0' && s
[3] <= '3')
10806 regno
= s
[3] - '0';
10808 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
10812 as_bad (_("Invalid dsp acc register"));
10815 case '0': /* DSP 6-bit signed immediate in bit 20. */
10816 gas_assert (!mips_opts
.micromips
);
10817 my_getExpression (&imm_expr
, s
);
10818 check_absolute_expr (ip
, &imm_expr
);
10819 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
10820 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
10821 if (imm_expr
.X_add_number
< min_range
||
10822 imm_expr
.X_add_number
> max_range
)
10824 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10825 (long) min_range
, (long) max_range
,
10826 (long) imm_expr
.X_add_number
);
10828 INSERT_OPERAND (0, DSPSFT
, *ip
, imm_expr
.X_add_number
);
10829 imm_expr
.X_op
= O_absent
;
10833 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10834 gas_assert (!mips_opts
.micromips
);
10835 my_getExpression (&imm_expr
, s
);
10836 check_absolute_expr (ip
, &imm_expr
);
10837 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
10839 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10841 (unsigned long) imm_expr
.X_add_number
);
10843 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
10844 imm_expr
.X_op
= O_absent
;
10848 case ':': /* DSP 7-bit signed immediate in bit 19. */
10849 gas_assert (!mips_opts
.micromips
);
10850 my_getExpression (&imm_expr
, s
);
10851 check_absolute_expr (ip
, &imm_expr
);
10852 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
10853 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
10854 if (imm_expr
.X_add_number
< min_range
||
10855 imm_expr
.X_add_number
> max_range
)
10857 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10858 (long) min_range
, (long) max_range
,
10859 (long) imm_expr
.X_add_number
);
10861 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
10862 imm_expr
.X_op
= O_absent
;
10866 case '@': /* DSP 10-bit signed immediate in bit 16. */
10867 gas_assert (!mips_opts
.micromips
);
10868 my_getExpression (&imm_expr
, s
);
10869 check_absolute_expr (ip
, &imm_expr
);
10870 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
10871 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
10872 if (imm_expr
.X_add_number
< min_range
||
10873 imm_expr
.X_add_number
> max_range
)
10875 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10876 (long) min_range
, (long) max_range
,
10877 (long) imm_expr
.X_add_number
);
10879 INSERT_OPERAND (0, IMM10
, *ip
, imm_expr
.X_add_number
);
10880 imm_expr
.X_op
= O_absent
;
10884 case '!': /* MT usermode flag bit. */
10885 gas_assert (!mips_opts
.micromips
);
10886 my_getExpression (&imm_expr
, s
);
10887 check_absolute_expr (ip
, &imm_expr
);
10888 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
10889 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10890 (unsigned long) imm_expr
.X_add_number
);
10891 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
10892 imm_expr
.X_op
= O_absent
;
10896 case '$': /* MT load high flag bit. */
10897 gas_assert (!mips_opts
.micromips
);
10898 my_getExpression (&imm_expr
, s
);
10899 check_absolute_expr (ip
, &imm_expr
);
10900 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
10901 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10902 (unsigned long) imm_expr
.X_add_number
);
10903 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
10904 imm_expr
.X_op
= O_absent
;
10908 case '*': /* Four DSP accumulators in bits 18,19. */
10909 gas_assert (!mips_opts
.micromips
);
10910 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
10911 s
[3] >= '0' && s
[3] <= '3')
10913 regno
= s
[3] - '0';
10915 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
10919 as_bad (_("Invalid dsp/smartmips acc register"));
10922 case '&': /* Four DSP accumulators in bits 13,14. */
10923 gas_assert (!mips_opts
.micromips
);
10924 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
10925 s
[3] >= '0' && s
[3] <= '3')
10927 regno
= s
[3] - '0';
10929 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
10933 as_bad (_("Invalid dsp/smartmips acc register"));
10945 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
10949 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
10953 gas_assert (!mips_opts
.micromips
);
10954 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
10958 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
10964 /* Handle optional base register.
10965 Either the base register is omitted or
10966 we must have a left paren. */
10967 /* This is dependent on the next operand specifier
10968 is a base register specification. */
10969 gas_assert (args
[1] == 'b'
10970 || (mips_opts
.micromips
10972 && (args
[2] == 'l' || args
[2] == 'n'
10973 || args
[2] == 's' || args
[2] == 'a')));
10974 if (*s
== '\0' && args
[1] == 'b')
10976 /* Fall through. */
10978 case ')': /* These must match exactly. */
10983 case '[': /* These must match exactly. */
10985 gas_assert (!mips_opts
.micromips
);
10990 case '+': /* Opcode extension character. */
10993 case '1': /* UDI immediates. */
10997 gas_assert (!mips_opts
.micromips
);
10999 const struct mips_immed
*imm
= mips_immed
;
11001 while (imm
->type
&& imm
->type
!= *args
)
11005 my_getExpression (&imm_expr
, s
);
11006 check_absolute_expr (ip
, &imm_expr
);
11007 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11009 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11010 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11011 (unsigned long) imm_expr
.X_add_number
,
11012 (unsigned long) imm_expr
.X_add_number
);
11013 imm_expr
.X_add_number
&= imm
->mask
;
11015 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11017 imm_expr
.X_op
= O_absent
;
11022 case 'A': /* ins/ext position, becomes LSB. */
11031 my_getExpression (&imm_expr
, s
);
11032 check_absolute_expr (ip
, &imm_expr
);
11033 if ((unsigned long) imm_expr
.X_add_number
< limlo
11034 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11036 as_bad (_("Improper position (%lu)"),
11037 (unsigned long) imm_expr
.X_add_number
);
11038 imm_expr
.X_add_number
= limlo
;
11040 lastpos
= imm_expr
.X_add_number
;
11041 INSERT_OPERAND (mips_opts
.micromips
,
11042 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11043 imm_expr
.X_op
= O_absent
;
11047 case 'B': /* ins size, becomes MSB. */
11056 my_getExpression (&imm_expr
, s
);
11057 check_absolute_expr (ip
, &imm_expr
);
11058 /* Check for negative input so that small negative numbers
11059 will not succeed incorrectly. The checks against
11060 (pos+size) transitively check "size" itself,
11061 assuming that "pos" is reasonable. */
11062 if ((long) imm_expr
.X_add_number
< 0
11063 || ((unsigned long) imm_expr
.X_add_number
11065 || ((unsigned long) imm_expr
.X_add_number
11066 + lastpos
) > limhi
)
11068 as_bad (_("Improper insert size (%lu, position %lu)"),
11069 (unsigned long) imm_expr
.X_add_number
,
11070 (unsigned long) lastpos
);
11071 imm_expr
.X_add_number
= limlo
- lastpos
;
11073 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11074 lastpos
+ imm_expr
.X_add_number
- 1);
11075 imm_expr
.X_op
= O_absent
;
11079 case 'C': /* ext size, becomes MSBD. */
11092 my_getExpression (&imm_expr
, s
);
11093 check_absolute_expr (ip
, &imm_expr
);
11094 /* Check for negative input so that small negative numbers
11095 will not succeed incorrectly. The checks against
11096 (pos+size) transitively check "size" itself,
11097 assuming that "pos" is reasonable. */
11098 if ((long) imm_expr
.X_add_number
< 0
11099 || ((unsigned long) imm_expr
.X_add_number
11101 || ((unsigned long) imm_expr
.X_add_number
11102 + lastpos
) > limhi
)
11104 as_bad (_("Improper extract size (%lu, position %lu)"),
11105 (unsigned long) imm_expr
.X_add_number
,
11106 (unsigned long) lastpos
);
11107 imm_expr
.X_add_number
= limlo
- lastpos
;
11109 INSERT_OPERAND (mips_opts
.micromips
,
11110 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11111 imm_expr
.X_op
= O_absent
;
11116 /* +D is for disassembly only; never match. */
11120 /* "+I" is like "I", except that imm2_expr is used. */
11121 my_getExpression (&imm2_expr
, s
);
11122 if (imm2_expr
.X_op
!= O_big
11123 && imm2_expr
.X_op
!= O_constant
)
11124 insn_error
= _("absolute expression required");
11125 if (HAVE_32BIT_GPRS
)
11126 normalize_constant_expr (&imm2_expr
);
11130 case 'T': /* Coprocessor register. */
11131 gas_assert (!mips_opts
.micromips
);
11132 /* +T is for disassembly only; never match. */
11135 case 't': /* Coprocessor register number. */
11136 gas_assert (!mips_opts
.micromips
);
11137 if (s
[0] == '$' && ISDIGIT (s
[1]))
11147 while (ISDIGIT (*s
));
11149 as_bad (_("Invalid register number (%d)"), regno
);
11152 INSERT_OPERAND (0, RT
, *ip
, regno
);
11157 as_bad (_("Invalid coprocessor 0 register number"));
11161 /* bbit[01] and bbit[01]32 bit index. Give error if index
11162 is not in the valid range. */
11163 gas_assert (!mips_opts
.micromips
);
11164 my_getExpression (&imm_expr
, s
);
11165 check_absolute_expr (ip
, &imm_expr
);
11166 if ((unsigned) imm_expr
.X_add_number
> 31)
11168 as_bad (_("Improper bit index (%lu)"),
11169 (unsigned long) imm_expr
.X_add_number
);
11170 imm_expr
.X_add_number
= 0;
11172 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11173 imm_expr
.X_op
= O_absent
;
11178 /* bbit[01] bit index when bbit is used but we generate
11179 bbit[01]32 because the index is over 32. Move to the
11180 next candidate if index is not in the valid range. */
11181 gas_assert (!mips_opts
.micromips
);
11182 my_getExpression (&imm_expr
, s
);
11183 check_absolute_expr (ip
, &imm_expr
);
11184 if ((unsigned) imm_expr
.X_add_number
< 32
11185 || (unsigned) imm_expr
.X_add_number
> 63)
11187 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11188 imm_expr
.X_op
= O_absent
;
11193 /* cins, cins32, exts and exts32 position field. Give error
11194 if it's not in the valid range. */
11195 gas_assert (!mips_opts
.micromips
);
11196 my_getExpression (&imm_expr
, s
);
11197 check_absolute_expr (ip
, &imm_expr
);
11198 if ((unsigned) imm_expr
.X_add_number
> 31)
11200 as_bad (_("Improper position (%lu)"),
11201 (unsigned long) imm_expr
.X_add_number
);
11202 imm_expr
.X_add_number
= 0;
11204 /* Make the pos explicit to simplify +S. */
11205 lastpos
= imm_expr
.X_add_number
+ 32;
11206 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11207 imm_expr
.X_op
= O_absent
;
11212 /* cins, cins32, exts and exts32 position field. Move to
11213 the next candidate if it's not in the valid range. */
11214 gas_assert (!mips_opts
.micromips
);
11215 my_getExpression (&imm_expr
, s
);
11216 check_absolute_expr (ip
, &imm_expr
);
11217 if ((unsigned) imm_expr
.X_add_number
< 32
11218 || (unsigned) imm_expr
.X_add_number
> 63)
11220 lastpos
= imm_expr
.X_add_number
;
11221 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11222 imm_expr
.X_op
= O_absent
;
11227 /* cins and exts length-minus-one field. */
11228 gas_assert (!mips_opts
.micromips
);
11229 my_getExpression (&imm_expr
, s
);
11230 check_absolute_expr (ip
, &imm_expr
);
11231 if ((unsigned long) imm_expr
.X_add_number
> 31)
11233 as_bad (_("Improper size (%lu)"),
11234 (unsigned long) imm_expr
.X_add_number
);
11235 imm_expr
.X_add_number
= 0;
11237 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11238 imm_expr
.X_op
= O_absent
;
11243 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11244 length-minus-one field. */
11245 gas_assert (!mips_opts
.micromips
);
11246 my_getExpression (&imm_expr
, s
);
11247 check_absolute_expr (ip
, &imm_expr
);
11248 if ((long) imm_expr
.X_add_number
< 0
11249 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11251 as_bad (_("Improper size (%lu)"),
11252 (unsigned long) imm_expr
.X_add_number
);
11253 imm_expr
.X_add_number
= 0;
11255 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11256 imm_expr
.X_op
= O_absent
;
11261 /* seqi/snei immediate field. */
11262 gas_assert (!mips_opts
.micromips
);
11263 my_getExpression (&imm_expr
, s
);
11264 check_absolute_expr (ip
, &imm_expr
);
11265 if ((long) imm_expr
.X_add_number
< -512
11266 || (long) imm_expr
.X_add_number
>= 512)
11268 as_bad (_("Improper immediate (%ld)"),
11269 (long) imm_expr
.X_add_number
);
11270 imm_expr
.X_add_number
= 0;
11272 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11273 imm_expr
.X_op
= O_absent
;
11277 case 'a': /* 8-bit signed offset in bit 6 */
11278 gas_assert (!mips_opts
.micromips
);
11279 my_getExpression (&imm_expr
, s
);
11280 check_absolute_expr (ip
, &imm_expr
);
11281 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11282 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11283 if (imm_expr
.X_add_number
< min_range
11284 || imm_expr
.X_add_number
> max_range
)
11286 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11287 (long) min_range
, (long) max_range
,
11288 (long) imm_expr
.X_add_number
);
11290 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11291 imm_expr
.X_op
= O_absent
;
11295 case 'b': /* 8-bit signed offset in bit 3 */
11296 gas_assert (!mips_opts
.micromips
);
11297 my_getExpression (&imm_expr
, s
);
11298 check_absolute_expr (ip
, &imm_expr
);
11299 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11300 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11301 if (imm_expr
.X_add_number
< min_range
11302 || imm_expr
.X_add_number
> max_range
)
11304 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11305 (long) min_range
, (long) max_range
,
11306 (long) imm_expr
.X_add_number
);
11308 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11309 imm_expr
.X_op
= O_absent
;
11313 case 'c': /* 9-bit signed offset in bit 6 */
11314 gas_assert (!mips_opts
.micromips
);
11315 my_getExpression (&imm_expr
, s
);
11316 check_absolute_expr (ip
, &imm_expr
);
11317 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11318 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11319 /* We check the offset range before adjusted. */
11322 if (imm_expr
.X_add_number
< min_range
11323 || imm_expr
.X_add_number
> max_range
)
11325 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11326 (long) min_range
, (long) max_range
,
11327 (long) imm_expr
.X_add_number
);
11329 if (imm_expr
.X_add_number
& 0xf)
11331 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11332 (long) imm_expr
.X_add_number
);
11334 /* Right shift 4 bits to adjust the offset operand. */
11335 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11336 imm_expr
.X_add_number
>> 4);
11337 imm_expr
.X_op
= O_absent
;
11342 gas_assert (!mips_opts
.micromips
);
11343 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11345 if (regno
== AT
&& mips_opts
.at
)
11347 if (mips_opts
.at
== ATREG
)
11348 as_warn (_("used $at without \".set noat\""));
11350 as_warn (_("used $%u with \".set at=$%u\""),
11351 regno
, mips_opts
.at
);
11353 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11357 gas_assert (!mips_opts
.micromips
);
11358 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11360 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11364 as_bad (_("Internal error: bad %s opcode "
11365 "(unknown extension operand type `+%c'): %s %s"),
11366 mips_opts
.micromips
? "microMIPS" : "MIPS",
11367 *args
, insn
->name
, insn
->args
);
11368 /* Further processing is fruitless. */
11373 case '.': /* 10-bit offset. */
11374 case '~': /* 12-bit offset. */
11375 gas_assert (mips_opts
.micromips
);
11377 int shift
= *args
== '.' ? 9 : 11;
11380 /* Check whether there is only a single bracketed expression
11381 left. If so, it must be the base register and the
11382 constant must be zero. */
11383 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11386 /* If this value won't fit into the offset, then go find
11387 a macro that will generate a 16- or 32-bit offset code
11389 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11390 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11391 || imm_expr
.X_add_number
>= 1 << shift
11392 || imm_expr
.X_add_number
< -1 << shift
))
11395 imm_expr
.X_op
= O_absent
;
11399 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11401 INSERT_OPERAND (1, OFFSET12
, *ip
, imm_expr
.X_add_number
);
11402 imm_expr
.X_op
= O_absent
;
11407 case '<': /* must be at least one digit */
11409 * According to the manual, if the shift amount is greater
11410 * than 31 or less than 0, then the shift amount should be
11411 * mod 32. In reality the mips assembler issues an error.
11412 * We issue a warning and mask out all but the low 5 bits.
11414 my_getExpression (&imm_expr
, s
);
11415 check_absolute_expr (ip
, &imm_expr
);
11416 if ((unsigned long) imm_expr
.X_add_number
> 31)
11417 as_warn (_("Improper shift amount (%lu)"),
11418 (unsigned long) imm_expr
.X_add_number
);
11419 INSERT_OPERAND (mips_opts
.micromips
,
11420 SHAMT
, *ip
, imm_expr
.X_add_number
);
11421 imm_expr
.X_op
= O_absent
;
11425 case '>': /* shift amount minus 32 */
11426 my_getExpression (&imm_expr
, s
);
11427 check_absolute_expr (ip
, &imm_expr
);
11428 if ((unsigned long) imm_expr
.X_add_number
< 32
11429 || (unsigned long) imm_expr
.X_add_number
> 63)
11431 INSERT_OPERAND (mips_opts
.micromips
,
11432 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11433 imm_expr
.X_op
= O_absent
;
11437 case 'k': /* CACHE code. */
11438 case 'h': /* PREFX code. */
11439 case '1': /* SYNC type. */
11440 my_getExpression (&imm_expr
, s
);
11441 check_absolute_expr (ip
, &imm_expr
);
11442 if ((unsigned long) imm_expr
.X_add_number
> 31)
11443 as_warn (_("Invalid value for `%s' (%lu)"),
11445 (unsigned long) imm_expr
.X_add_number
);
11449 if (mips_fix_cn63xxp1
11450 && !mips_opts
.micromips
11451 && strcmp ("pref", insn
->name
) == 0)
11452 switch (imm_expr
.X_add_number
)
11461 case 31: /* These are ok. */
11464 default: /* The rest must be changed to 28. */
11465 imm_expr
.X_add_number
= 28;
11468 INSERT_OPERAND (mips_opts
.micromips
,
11469 CACHE
, *ip
, imm_expr
.X_add_number
);
11472 INSERT_OPERAND (mips_opts
.micromips
,
11473 PREFX
, *ip
, imm_expr
.X_add_number
);
11476 INSERT_OPERAND (mips_opts
.micromips
,
11477 STYPE
, *ip
, imm_expr
.X_add_number
);
11480 imm_expr
.X_op
= O_absent
;
11484 case 'c': /* BREAK code. */
11486 unsigned long mask
= (mips_opts
.micromips
11487 ? MICROMIPSOP_MASK_CODE
11490 my_getExpression (&imm_expr
, s
);
11491 check_absolute_expr (ip
, &imm_expr
);
11492 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11493 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11495 mask
, (unsigned long) imm_expr
.X_add_number
);
11496 INSERT_OPERAND (mips_opts
.micromips
,
11497 CODE
, *ip
, imm_expr
.X_add_number
);
11498 imm_expr
.X_op
= O_absent
;
11503 case 'q': /* Lower BREAK code. */
11505 unsigned long mask
= (mips_opts
.micromips
11506 ? MICROMIPSOP_MASK_CODE2
11509 my_getExpression (&imm_expr
, s
);
11510 check_absolute_expr (ip
, &imm_expr
);
11511 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11512 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11514 mask
, (unsigned long) imm_expr
.X_add_number
);
11515 INSERT_OPERAND (mips_opts
.micromips
,
11516 CODE2
, *ip
, imm_expr
.X_add_number
);
11517 imm_expr
.X_op
= O_absent
;
11522 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11524 unsigned long mask
= (mips_opts
.micromips
11525 ? MICROMIPSOP_MASK_CODE10
11528 my_getExpression (&imm_expr
, s
);
11529 check_absolute_expr (ip
, &imm_expr
);
11530 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11531 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11533 mask
, (unsigned long) imm_expr
.X_add_number
);
11534 if (mips_opts
.micromips
)
11535 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11537 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11538 imm_expr
.X_op
= O_absent
;
11543 case 'C': /* 25- or 23-bit coprocessor code. */
11545 unsigned long mask
= (mips_opts
.micromips
11546 ? MICROMIPSOP_MASK_COPZ
11549 my_getExpression (&imm_expr
, s
);
11550 check_absolute_expr (ip
, &imm_expr
);
11551 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11552 as_warn (_("Coproccesor code > %u bits (%lu)"),
11553 mips_opts
.micromips
? 23U : 25U,
11554 (unsigned long) imm_expr
.X_add_number
);
11555 INSERT_OPERAND (mips_opts
.micromips
,
11556 COPZ
, *ip
, imm_expr
.X_add_number
);
11557 imm_expr
.X_op
= O_absent
;
11562 case 'J': /* 19-bit WAIT code. */
11563 gas_assert (!mips_opts
.micromips
);
11564 my_getExpression (&imm_expr
, s
);
11565 check_absolute_expr (ip
, &imm_expr
);
11566 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11568 as_warn (_("Illegal 19-bit code (%lu)"),
11569 (unsigned long) imm_expr
.X_add_number
);
11570 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11572 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11573 imm_expr
.X_op
= O_absent
;
11577 case 'P': /* Performance register. */
11578 gas_assert (!mips_opts
.micromips
);
11579 my_getExpression (&imm_expr
, s
);
11580 check_absolute_expr (ip
, &imm_expr
);
11581 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11582 as_warn (_("Invalid performance register (%lu)"),
11583 (unsigned long) imm_expr
.X_add_number
);
11584 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11585 imm_expr
.X_op
= O_absent
;
11589 case 'G': /* Coprocessor destination register. */
11591 unsigned long opcode
= ip
->insn_opcode
;
11592 unsigned long mask
;
11593 unsigned int types
;
11596 if (mips_opts
.micromips
)
11598 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11599 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11600 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11604 case 0x000000fc: /* mfc0 */
11605 case 0x000002fc: /* mtc0 */
11606 case 0x580000fc: /* dmfc0 */
11607 case 0x580002fc: /* dmtc0 */
11617 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11618 cop0
= opcode
== OP_OP_COP0
;
11620 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11621 ok
= reg_lookup (&s
, types
, ®no
);
11622 if (mips_opts
.micromips
)
11623 INSERT_OPERAND (1, RS
, *ip
, regno
);
11625 INSERT_OPERAND (0, RD
, *ip
, regno
);
11634 case 'y': /* ALNV.PS source register. */
11635 gas_assert (mips_opts
.micromips
);
11637 case 'x': /* Ignore register name. */
11638 case 'U': /* Destination register (CLO/CLZ). */
11639 case 'g': /* Coprocessor destination register. */
11640 gas_assert (!mips_opts
.micromips
);
11641 case 'b': /* Base register. */
11642 case 'd': /* Destination register. */
11643 case 's': /* Source register. */
11644 case 't': /* Target register. */
11645 case 'r': /* Both target and source. */
11646 case 'v': /* Both dest and source. */
11647 case 'w': /* Both dest and target. */
11648 case 'E': /* Coprocessor target register. */
11649 case 'K': /* RDHWR destination register. */
11650 case 'z': /* Must be zero register. */
11653 if (*args
== 'E' || *args
== 'K')
11654 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11657 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11658 if (regno
== AT
&& mips_opts
.at
)
11660 if (mips_opts
.at
== ATREG
)
11661 as_warn (_("Used $at without \".set noat\""));
11663 as_warn (_("Used $%u with \".set at=$%u\""),
11664 regno
, mips_opts
.at
);
11674 if (c
== 'r' || c
== 'v' || c
== 'w')
11681 /* 'z' only matches $0. */
11682 if (c
== 'z' && regno
!= 0)
11685 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
11687 if (regno
== lastregno
)
11690 = _("Source and destination must be different");
11693 if (regno
== 31 && lastregno
== 0xffffffff)
11696 = _("A destination register must be supplied");
11700 /* Now that we have assembled one operand, we use the args
11701 string to figure out where it goes in the instruction. */
11708 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
11712 if (mips_opts
.micromips
)
11713 INSERT_OPERAND (1, RS
, *ip
, regno
);
11715 INSERT_OPERAND (0, RD
, *ip
, regno
);
11720 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
11724 gas_assert (!mips_opts
.micromips
);
11725 INSERT_OPERAND (0, RD
, *ip
, regno
);
11726 INSERT_OPERAND (0, RT
, *ip
, regno
);
11732 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
11736 gas_assert (mips_opts
.micromips
);
11737 INSERT_OPERAND (1, RS3
, *ip
, regno
);
11741 /* This case exists because on the r3000 trunc
11742 expands into a macro which requires a gp
11743 register. On the r6000 or r4000 it is
11744 assembled into a single instruction which
11745 ignores the register. Thus the insn version
11746 is MIPS_ISA2 and uses 'x', and the macro
11747 version is MIPS_ISA1 and uses 't'. */
11751 /* This case is for the div instruction, which
11752 acts differently if the destination argument
11753 is $0. This only matches $0, and is checked
11754 outside the switch. */
11764 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11768 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11773 case 'O': /* MDMX alignment immediate constant. */
11774 gas_assert (!mips_opts
.micromips
);
11775 my_getExpression (&imm_expr
, s
);
11776 check_absolute_expr (ip
, &imm_expr
);
11777 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
11778 as_warn (_("Improper align amount (%ld), using low bits"),
11779 (long) imm_expr
.X_add_number
);
11780 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
11781 imm_expr
.X_op
= O_absent
;
11785 case 'Q': /* MDMX vector, element sel, or const. */
11788 /* MDMX Immediate. */
11789 gas_assert (!mips_opts
.micromips
);
11790 my_getExpression (&imm_expr
, s
);
11791 check_absolute_expr (ip
, &imm_expr
);
11792 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
11793 as_warn (_("Invalid MDMX Immediate (%ld)"),
11794 (long) imm_expr
.X_add_number
);
11795 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
11796 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
11797 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
11799 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
11800 imm_expr
.X_op
= O_absent
;
11804 /* Not MDMX Immediate. Fall through. */
11805 case 'X': /* MDMX destination register. */
11806 case 'Y': /* MDMX source register. */
11807 case 'Z': /* MDMX target register. */
11810 gas_assert (!mips_opts
.micromips
);
11811 case 'D': /* Floating point destination register. */
11812 case 'S': /* Floating point source register. */
11813 case 'T': /* Floating point target register. */
11814 case 'R': /* Floating point source register. */
11818 || (mips_opts
.ase_mdmx
11819 && (ip
->insn_mo
->pinfo
& FP_D
)
11820 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
11821 | INSN_COPROC_MEMORY_DELAY
11822 | INSN_LOAD_COPROC_DELAY
11823 | INSN_LOAD_MEMORY_DELAY
11824 | INSN_STORE_MEMORY
))))
11825 rtype
|= RTYPE_VEC
;
11827 if (reg_lookup (&s
, rtype
, ®no
))
11829 if ((regno
& 1) != 0
11831 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
11832 as_warn (_("Float register should be even, was %d"),
11840 if (c
== 'V' || c
== 'W')
11851 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
11857 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
11861 /* This is like 'Z', but also needs to fix the MDMX
11862 vector/scalar select bits. Note that the
11863 scalar immediate case is handled above. */
11866 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
11867 int max_el
= (is_qh
? 3 : 7);
11869 my_getExpression(&imm_expr
, s
);
11870 check_absolute_expr (ip
, &imm_expr
);
11872 if (imm_expr
.X_add_number
> max_el
)
11873 as_bad (_("Bad element selector %ld"),
11874 (long) imm_expr
.X_add_number
);
11875 imm_expr
.X_add_number
&= max_el
;
11876 ip
->insn_opcode
|= (imm_expr
.X_add_number
11879 imm_expr
.X_op
= O_absent
;
11881 as_warn (_("Expecting ']' found '%s'"), s
);
11887 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
11888 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
11891 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
11894 /* Fall through. */
11898 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
11902 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
11912 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11916 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
11922 my_getExpression (&imm_expr
, s
);
11923 if (imm_expr
.X_op
!= O_big
11924 && imm_expr
.X_op
!= O_constant
)
11925 insn_error
= _("absolute expression required");
11926 if (HAVE_32BIT_GPRS
)
11927 normalize_constant_expr (&imm_expr
);
11932 my_getExpression (&offset_expr
, s
);
11933 normalize_address_expr (&offset_expr
);
11934 *imm_reloc
= BFD_RELOC_32
;
11947 unsigned char temp
[8];
11949 unsigned int length
;
11954 /* These only appear as the last operand in an
11955 instruction, and every instruction that accepts
11956 them in any variant accepts them in all variants.
11957 This means we don't have to worry about backing out
11958 any changes if the instruction does not match.
11960 The difference between them is the size of the
11961 floating point constant and where it goes. For 'F'
11962 and 'L' the constant is 64 bits; for 'f' and 'l' it
11963 is 32 bits. Where the constant is placed is based
11964 on how the MIPS assembler does things:
11967 f -- immediate value
11970 The .lit4 and .lit8 sections are only used if
11971 permitted by the -G argument.
11973 The code below needs to know whether the target register
11974 is 32 or 64 bits wide. It relies on the fact 'f' and
11975 'F' are used with GPR-based instructions and 'l' and
11976 'L' are used with FPR-based instructions. */
11978 f64
= *args
== 'F' || *args
== 'L';
11979 using_gprs
= *args
== 'F' || *args
== 'f';
11981 save_in
= input_line_pointer
;
11982 input_line_pointer
= s
;
11983 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
11985 s
= input_line_pointer
;
11986 input_line_pointer
= save_in
;
11987 if (err
!= NULL
&& *err
!= '\0')
11989 as_bad (_("Bad floating point constant: %s"), err
);
11990 memset (temp
, '\0', sizeof temp
);
11991 length
= f64
? 8 : 4;
11994 gas_assert (length
== (unsigned) (f64
? 8 : 4));
11998 && (g_switch_value
< 4
11999 || (temp
[0] == 0 && temp
[1] == 0)
12000 || (temp
[2] == 0 && temp
[3] == 0))))
12002 imm_expr
.X_op
= O_constant
;
12003 if (!target_big_endian
)
12004 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12006 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12008 else if (length
> 4
12009 && !mips_disable_float_construction
12010 /* Constants can only be constructed in GPRs and
12011 copied to FPRs if the GPRs are at least as wide
12012 as the FPRs. Force the constant into memory if
12013 we are using 64-bit FPRs but the GPRs are only
12016 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12017 && ((temp
[0] == 0 && temp
[1] == 0)
12018 || (temp
[2] == 0 && temp
[3] == 0))
12019 && ((temp
[4] == 0 && temp
[5] == 0)
12020 || (temp
[6] == 0 && temp
[7] == 0)))
12022 /* The value is simple enough to load with a couple of
12023 instructions. If using 32-bit registers, set
12024 imm_expr to the high order 32 bits and offset_expr to
12025 the low order 32 bits. Otherwise, set imm_expr to
12026 the entire 64 bit constant. */
12027 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12029 imm_expr
.X_op
= O_constant
;
12030 offset_expr
.X_op
= O_constant
;
12031 if (!target_big_endian
)
12033 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12034 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12038 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12039 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12041 if (offset_expr
.X_add_number
== 0)
12042 offset_expr
.X_op
= O_absent
;
12044 else if (sizeof (imm_expr
.X_add_number
) > 4)
12046 imm_expr
.X_op
= O_constant
;
12047 if (!target_big_endian
)
12048 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12050 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12054 imm_expr
.X_op
= O_big
;
12055 imm_expr
.X_add_number
= 4;
12056 if (!target_big_endian
)
12058 generic_bignum
[0] = bfd_getl16 (temp
);
12059 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12060 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12061 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12065 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12066 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12067 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12068 generic_bignum
[3] = bfd_getb16 (temp
);
12074 const char *newname
;
12077 /* Switch to the right section. */
12079 subseg
= now_subseg
;
12082 default: /* unused default case avoids warnings. */
12084 newname
= RDATA_SECTION_NAME
;
12085 if (g_switch_value
>= 8)
12089 newname
= RDATA_SECTION_NAME
;
12092 gas_assert (g_switch_value
>= 4);
12096 new_seg
= subseg_new (newname
, (subsegT
) 0);
12098 bfd_set_section_flags (stdoutput
, new_seg
,
12103 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12104 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12105 record_alignment (new_seg
, 4);
12107 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12108 if (seg
== now_seg
)
12109 as_bad (_("Can't use floating point insn in this section"));
12111 /* Set the argument to the current address in the
12113 offset_expr
.X_op
= O_symbol
;
12114 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12115 offset_expr
.X_add_number
= 0;
12117 /* Put the floating point number into the section. */
12118 p
= frag_more ((int) length
);
12119 memcpy (p
, temp
, length
);
12121 /* Switch back to the original section. */
12122 subseg_set (seg
, subseg
);
12127 case 'i': /* 16-bit unsigned immediate. */
12128 case 'j': /* 16-bit signed immediate. */
12129 *imm_reloc
= BFD_RELOC_LO16
;
12130 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12133 offsetT minval
, maxval
;
12135 more
= (insn
+ 1 < past
12136 && strcmp (insn
->name
, insn
[1].name
) == 0);
12138 /* If the expression was written as an unsigned number,
12139 only treat it as signed if there are no more
12143 && sizeof (imm_expr
.X_add_number
) <= 4
12144 && imm_expr
.X_op
== O_constant
12145 && imm_expr
.X_add_number
< 0
12146 && imm_expr
.X_unsigned
12147 && HAVE_64BIT_GPRS
)
12150 /* For compatibility with older assemblers, we accept
12151 0x8000-0xffff as signed 16-bit numbers when only
12152 signed numbers are allowed. */
12154 minval
= 0, maxval
= 0xffff;
12156 minval
= -0x8000, maxval
= 0x7fff;
12158 minval
= -0x8000, maxval
= 0xffff;
12160 if (imm_expr
.X_op
!= O_constant
12161 || imm_expr
.X_add_number
< minval
12162 || imm_expr
.X_add_number
> maxval
)
12166 if (imm_expr
.X_op
== O_constant
12167 || imm_expr
.X_op
== O_big
)
12168 as_bad (_("Expression out of range"));
12174 case 'o': /* 16-bit offset. */
12175 offset_reloc
[0] = BFD_RELOC_LO16
;
12176 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12177 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12179 /* Check whether there is only a single bracketed expression
12180 left. If so, it must be the base register and the
12181 constant must be zero. */
12182 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12184 offset_expr
.X_op
= O_constant
;
12185 offset_expr
.X_add_number
= 0;
12189 /* If this value won't fit into a 16 bit offset, then go
12190 find a macro that will generate the 32 bit offset
12192 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12193 && (offset_expr
.X_op
!= O_constant
12194 || offset_expr
.X_add_number
>= 0x8000
12195 || offset_expr
.X_add_number
< -0x8000))
12201 case 'p': /* PC-relative offset. */
12202 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12203 my_getExpression (&offset_expr
, s
);
12207 case 'u': /* Upper 16 bits. */
12208 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12209 && imm_expr
.X_op
== O_constant
12210 && (imm_expr
.X_add_number
< 0
12211 || imm_expr
.X_add_number
>= 0x10000))
12212 as_bad (_("lui expression (%lu) not in range 0..65535"),
12213 (unsigned long) imm_expr
.X_add_number
);
12217 case 'a': /* 26-bit address. */
12218 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12219 my_getExpression (&offset_expr
, s
);
12223 case 'N': /* 3-bit branch condition code. */
12224 case 'M': /* 3-bit compare condition code. */
12226 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12227 rtype
|= RTYPE_FCC
;
12228 if (!reg_lookup (&s
, rtype
, ®no
))
12230 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12231 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12232 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12233 && (regno
& 1) != 0)
12234 as_warn (_("Condition code register should be even for %s, "
12237 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12238 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12239 && (regno
& 3) != 0)
12240 as_warn (_("Condition code register should be 0 or 4 for %s, "
12244 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12246 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12250 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12261 while (ISDIGIT (*s
));
12264 c
= 8; /* Invalid sel value. */
12267 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12268 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12272 gas_assert (!mips_opts
.micromips
);
12273 /* Must be at least one digit. */
12274 my_getExpression (&imm_expr
, s
);
12275 check_absolute_expr (ip
, &imm_expr
);
12277 if ((unsigned long) imm_expr
.X_add_number
12278 > (unsigned long) OP_MASK_VECBYTE
)
12280 as_bad (_("bad byte vector index (%ld)"),
12281 (long) imm_expr
.X_add_number
);
12282 imm_expr
.X_add_number
= 0;
12285 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12286 imm_expr
.X_op
= O_absent
;
12291 gas_assert (!mips_opts
.micromips
);
12292 my_getExpression (&imm_expr
, s
);
12293 check_absolute_expr (ip
, &imm_expr
);
12295 if ((unsigned long) imm_expr
.X_add_number
12296 > (unsigned long) OP_MASK_VECALIGN
)
12298 as_bad (_("bad byte vector index (%ld)"),
12299 (long) imm_expr
.X_add_number
);
12300 imm_expr
.X_add_number
= 0;
12303 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12304 imm_expr
.X_op
= O_absent
;
12308 case 'm': /* Opcode extension character. */
12309 gas_assert (mips_opts
.micromips
);
12314 if (strncmp (s
, "$pc", 3) == 0)
12342 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12343 if (regno
== AT
&& mips_opts
.at
)
12345 if (mips_opts
.at
== ATREG
)
12346 as_warn (_("Used $at without \".set noat\""));
12348 as_warn (_("Used $%u with \".set at=$%u\""),
12349 regno
, mips_opts
.at
);
12355 gas_assert (args
[1] == ',');
12361 gas_assert (args
[1] == ',');
12363 continue; /* Nothing to do. */
12369 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12371 if (regno
== lastregno
)
12374 = _("Source and destination must be different");
12377 if (regno
== 31 && lastregno
== 0xffffffff)
12380 = _("A destination register must be supplied");
12391 gas_assert (args
[1] == ',');
12398 gas_assert (args
[1] == ',');
12401 continue; /* Nothing to do. */
12405 /* Make sure regno is the same as lastregno. */
12406 if (c
== 't' && regno
!= lastregno
)
12409 /* Make sure regno is the same as destregno. */
12410 if (c
== 'x' && regno
!= destregno
)
12413 /* We need to save regno, before regno maps to the
12414 microMIPS register encoding. */
12424 regno
= ILLEGAL_REG
;
12428 regno
= mips32_to_micromips_reg_b_map
[regno
];
12432 regno
= mips32_to_micromips_reg_c_map
[regno
];
12436 regno
= mips32_to_micromips_reg_d_map
[regno
];
12440 regno
= mips32_to_micromips_reg_e_map
[regno
];
12444 regno
= mips32_to_micromips_reg_f_map
[regno
];
12448 regno
= mips32_to_micromips_reg_g_map
[regno
];
12452 regno
= mips32_to_micromips_reg_h_map
[regno
];
12456 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12461 else if (regno
== 22)
12463 else if (regno
== 5)
12465 else if (regno
== 6)
12467 else if (regno
== 7)
12470 regno
= ILLEGAL_REG
;
12476 else if (regno
== 7)
12479 regno
= ILLEGAL_REG
;
12486 regno
= ILLEGAL_REG
;
12490 regno
= ILLEGAL_REG
;
12496 regno
= mips32_to_micromips_reg_l_map
[regno
];
12500 regno
= mips32_to_micromips_reg_m_map
[regno
];
12504 regno
= mips32_to_micromips_reg_n_map
[regno
];
12508 regno
= mips32_to_micromips_reg_q_map
[regno
];
12513 regno
= ILLEGAL_REG
;
12518 regno
= ILLEGAL_REG
;
12523 regno
= ILLEGAL_REG
;
12526 case 'j': /* Do nothing. */
12536 if (regno
== ILLEGAL_REG
)
12542 INSERT_OPERAND (1, MB
, *ip
, regno
);
12546 INSERT_OPERAND (1, MC
, *ip
, regno
);
12550 INSERT_OPERAND (1, MD
, *ip
, regno
);
12554 INSERT_OPERAND (1, ME
, *ip
, regno
);
12558 INSERT_OPERAND (1, MF
, *ip
, regno
);
12562 INSERT_OPERAND (1, MG
, *ip
, regno
);
12566 INSERT_OPERAND (1, MH
, *ip
, regno
);
12570 INSERT_OPERAND (1, MI
, *ip
, regno
);
12574 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12578 INSERT_OPERAND (1, ML
, *ip
, regno
);
12582 INSERT_OPERAND (1, MM
, *ip
, regno
);
12586 INSERT_OPERAND (1, MN
, *ip
, regno
);
12590 INSERT_OPERAND (1, MP
, *ip
, regno
);
12594 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12597 case 'a': /* Do nothing. */
12598 case 's': /* Do nothing. */
12599 case 't': /* Do nothing. */
12600 case 'x': /* Do nothing. */
12601 case 'y': /* Do nothing. */
12602 case 'z': /* Do nothing. */
12612 bfd_reloc_code_real_type r
[3];
12616 /* Check whether there is only a single bracketed
12617 expression left. If so, it must be the base register
12618 and the constant must be zero. */
12619 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12621 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12625 if (my_getSmallExpression (&ep
, r
, s
) > 0
12626 || !expr_const_in_range (&ep
, -64, 64, 2))
12629 imm
= ep
.X_add_number
>> 2;
12630 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12637 bfd_reloc_code_real_type r
[3];
12641 if (my_getSmallExpression (&ep
, r
, s
) > 0
12642 || ep
.X_op
!= O_constant
)
12645 for (imm
= 0; imm
< 8; imm
++)
12646 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12651 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12658 bfd_reloc_code_real_type r
[3];
12662 if (my_getSmallExpression (&ep
, r
, s
) > 0
12663 || ep
.X_op
!= O_constant
)
12666 for (imm
= 0; imm
< 16; imm
++)
12667 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
12672 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
12677 case 'D': /* pc relative offset */
12678 case 'E': /* pc relative offset */
12679 my_getExpression (&offset_expr
, s
);
12680 if (offset_expr
.X_op
== O_register
)
12683 if (!forced_insn_length
)
12684 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12686 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12688 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12694 bfd_reloc_code_real_type r
[3];
12698 if (my_getSmallExpression (&ep
, r
, s
) > 0
12699 || !expr_const_in_range (&ep
, 0, 16, 0))
12702 imm
= ep
.X_add_number
;
12703 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
12710 bfd_reloc_code_real_type r
[3];
12714 /* Check whether there is only a single bracketed
12715 expression left. If so, it must be the base register
12716 and the constant must be zero. */
12717 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12719 INSERT_OPERAND (1, IMMG
, *ip
, 0);
12723 if (my_getSmallExpression (&ep
, r
, s
) > 0
12724 || !expr_const_in_range (&ep
, -1, 15, 0))
12727 imm
= ep
.X_add_number
& 15;
12728 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
12735 bfd_reloc_code_real_type r
[3];
12739 /* Check whether there is only a single bracketed
12740 expression left. If so, it must be the base register
12741 and the constant must be zero. */
12742 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12744 INSERT_OPERAND (1, IMMH
, *ip
, 0);
12748 if (my_getSmallExpression (&ep
, r
, s
) > 0
12749 || !expr_const_in_range (&ep
, 0, 16, 1))
12752 imm
= ep
.X_add_number
>> 1;
12753 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
12760 bfd_reloc_code_real_type r
[3];
12764 if (my_getSmallExpression (&ep
, r
, s
) > 0
12765 || !expr_const_in_range (&ep
, -1, 127, 0))
12768 imm
= ep
.X_add_number
& 127;
12769 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
12776 bfd_reloc_code_real_type r
[3];
12780 /* Check whether there is only a single bracketed
12781 expression left. If so, it must be the base register
12782 and the constant must be zero. */
12783 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12785 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
12789 if (my_getSmallExpression (&ep
, r
, s
) > 0
12790 || !expr_const_in_range (&ep
, 0, 16, 2))
12793 imm
= ep
.X_add_number
>> 2;
12794 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
12801 bfd_reloc_code_real_type r
[3];
12805 /* Check whether there is only a single bracketed
12806 expression left. If so, it must be the base register
12807 and the constant must be zero. */
12808 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12810 INSERT_OPERAND (1, IMML
, *ip
, 0);
12814 if (my_getSmallExpression (&ep
, r
, s
) > 0
12815 || !expr_const_in_range (&ep
, 0, 16, 0))
12818 imm
= ep
.X_add_number
;
12819 INSERT_OPERAND (1, IMML
, *ip
, imm
);
12826 bfd_reloc_code_real_type r
[3];
12830 if (my_getSmallExpression (&ep
, r
, s
) > 0
12831 || !expr_const_in_range (&ep
, 1, 9, 0))
12834 imm
= ep
.X_add_number
& 7;
12835 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
12840 case 'N': /* Register list for lwm and swm. */
12842 /* A comma-separated list of registers and/or
12843 dash-separated contiguous ranges including
12844 both ra and a set of one or more registers
12845 starting at s0 up to s3 which have to be
12852 and any permutations of these. */
12853 unsigned int reglist
;
12856 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
12859 if ((reglist
& 0xfff1ffff) != 0x80010000)
12862 reglist
= (reglist
>> 17) & 7;
12864 if ((reglist
& -reglist
) != reglist
)
12867 imm
= ffs (reglist
) - 1;
12868 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
12872 case 'O': /* sdbbp 4-bit code. */
12874 bfd_reloc_code_real_type r
[3];
12878 if (my_getSmallExpression (&ep
, r
, s
) > 0
12879 || !expr_const_in_range (&ep
, 0, 16, 0))
12882 imm
= ep
.X_add_number
;
12883 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
12890 bfd_reloc_code_real_type r
[3];
12894 if (my_getSmallExpression (&ep
, r
, s
) > 0
12895 || !expr_const_in_range (&ep
, 0, 32, 2))
12898 imm
= ep
.X_add_number
>> 2;
12899 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
12906 bfd_reloc_code_real_type r
[3];
12910 if (my_getSmallExpression (&ep
, r
, s
) > 0
12911 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
12914 imm
= ep
.X_add_number
>> 2;
12915 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
12922 bfd_reloc_code_real_type r
[3];
12926 /* Check whether there is only a single bracketed
12927 expression left. If so, it must be the base register
12928 and the constant must be zero. */
12929 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12931 INSERT_OPERAND (1, IMMU
, *ip
, 0);
12935 if (my_getSmallExpression (&ep
, r
, s
) > 0
12936 || !expr_const_in_range (&ep
, 0, 32, 2))
12939 imm
= ep
.X_add_number
>> 2;
12940 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
12947 bfd_reloc_code_real_type r
[3];
12951 if (my_getSmallExpression (&ep
, r
, s
) > 0
12952 || !expr_const_in_range (&ep
, 0, 64, 2))
12955 imm
= ep
.X_add_number
>> 2;
12956 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
12963 bfd_reloc_code_real_type r
[3];
12967 if (my_getSmallExpression (&ep
, r
, s
) > 0
12968 || !expr_const_in_range (&ep
, -8, 8, 0))
12971 imm
= ep
.X_add_number
;
12972 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
12979 bfd_reloc_code_real_type r
[3];
12983 if (my_getSmallExpression (&ep
, r
, s
) > 0
12984 || expr_const_in_range (&ep
, -2, 2, 2)
12985 || !expr_const_in_range (&ep
, -258, 258, 2))
12988 imm
= ep
.X_add_number
>> 2;
12989 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
12990 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
12997 bfd_reloc_code_real_type r
[3];
13000 if (my_getSmallExpression (&ep
, r
, s
) > 0
13001 || !expr_const_in_range (&ep
, 0, 1, 0))
13008 as_bad (_("Internal error: bad microMIPS opcode "
13009 "(unknown extension operand type `m%c'): %s %s"),
13010 *args
, insn
->name
, insn
->args
);
13011 /* Further processing is fruitless. */
13016 case 'n': /* Register list for 32-bit lwm and swm. */
13017 gas_assert (mips_opts
.micromips
);
13019 /* A comma-separated list of registers and/or
13020 dash-separated contiguous ranges including
13021 at least one of ra and a set of one or more
13022 registers starting at s0 up to s7 and then
13023 s8 which have to be consecutive, e.g.:
13031 and any permutations of these. */
13032 unsigned int reglist
;
13036 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13039 if ((reglist
& 0x3f00ffff) != 0)
13042 ra
= (reglist
>> 27) & 0x10;
13043 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13045 if ((reglist
& -reglist
) != reglist
)
13048 imm
= (ffs (reglist
) - 1) | ra
;
13049 INSERT_OPERAND (1, RT
, *ip
, imm
);
13050 imm_expr
.X_op
= O_absent
;
13054 case '|': /* 4-bit trap code. */
13055 gas_assert (mips_opts
.micromips
);
13056 my_getExpression (&imm_expr
, s
);
13057 check_absolute_expr (ip
, &imm_expr
);
13058 if ((unsigned long) imm_expr
.X_add_number
13059 > MICROMIPSOP_MASK_TRAP
)
13060 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13061 (unsigned long) imm_expr
.X_add_number
,
13062 ip
->insn_mo
->name
);
13063 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13064 imm_expr
.X_op
= O_absent
;
13069 as_bad (_("Bad char = '%c'\n"), *args
);
13074 /* Args don't match. */
13076 insn_error
= _("Illegal operands");
13077 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13082 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13084 gas_assert (firstinsn
);
13085 need_delay_slot_ok
= FALSE
;
13094 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13096 /* This routine assembles an instruction into its binary format when
13097 assembling for the mips16. As a side effect, it sets one of the
13098 global variables imm_reloc or offset_reloc to the type of relocation
13099 to do if one of the operands is an address expression. It also sets
13100 forced_insn_length to the resulting instruction size in bytes if the
13101 user explicitly requested a small or extended instruction. */
13104 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13108 struct mips_opcode
*insn
;
13110 unsigned int regno
;
13111 unsigned int lastregno
= 0;
13117 forced_insn_length
= 0;
13119 for (s
= str
; ISLOWER (*s
); ++s
)
13131 if (s
[1] == 't' && s
[2] == ' ')
13134 forced_insn_length
= 2;
13138 else if (s
[1] == 'e' && s
[2] == ' ')
13141 forced_insn_length
= 4;
13145 /* Fall through. */
13147 insn_error
= _("unknown opcode");
13151 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13152 forced_insn_length
= 2;
13154 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13156 insn_error
= _("unrecognized opcode");
13165 gas_assert (strcmp (insn
->name
, str
) == 0);
13167 ok
= is_opcode_valid_16 (insn
);
13170 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13171 && strcmp (insn
->name
, insn
[1].name
) == 0)
13180 static char buf
[100];
13182 _("opcode not supported on this processor: %s (%s)"),
13183 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13184 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13191 create_insn (ip
, insn
);
13192 imm_expr
.X_op
= O_absent
;
13193 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13194 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13195 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13196 imm2_expr
.X_op
= O_absent
;
13197 offset_expr
.X_op
= O_absent
;
13198 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13199 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13200 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13201 for (args
= insn
->args
; 1; ++args
)
13208 /* In this switch statement we call break if we did not find
13209 a match, continue if we did find a match, or return if we
13218 /* Stuff the immediate value in now, if we can. */
13219 if (imm_expr
.X_op
== O_constant
13220 && *imm_reloc
> BFD_RELOC_UNUSED
13221 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
13222 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
13223 && insn
->pinfo
!= INSN_MACRO
)
13227 switch (*offset_reloc
)
13229 case BFD_RELOC_MIPS16_HI16_S
:
13230 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
13233 case BFD_RELOC_MIPS16_HI16
:
13234 tmp
= imm_expr
.X_add_number
>> 16;
13237 case BFD_RELOC_MIPS16_LO16
:
13238 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
13242 case BFD_RELOC_UNUSED
:
13243 tmp
= imm_expr
.X_add_number
;
13249 *offset_reloc
= BFD_RELOC_UNUSED
;
13251 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13252 tmp
, TRUE
, forced_insn_length
== 2,
13253 forced_insn_length
== 4, &ip
->insn_opcode
,
13254 &ip
->use_extend
, &ip
->extend
);
13255 imm_expr
.X_op
= O_absent
;
13256 *imm_reloc
= BFD_RELOC_UNUSED
;
13270 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13273 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13289 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13291 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13295 /* Fall through. */
13306 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13308 if (c
== 'v' || c
== 'w')
13311 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13313 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13324 if (c
== 'v' || c
== 'w')
13326 regno
= mips16_to_32_reg_map
[lastregno
];
13340 regno
= mips32_to_16_reg_map
[regno
];
13345 regno
= ILLEGAL_REG
;
13350 regno
= ILLEGAL_REG
;
13355 regno
= ILLEGAL_REG
;
13360 if (regno
== AT
&& mips_opts
.at
)
13362 if (mips_opts
.at
== ATREG
)
13363 as_warn (_("used $at without \".set noat\""));
13365 as_warn (_("used $%u with \".set at=$%u\""),
13366 regno
, mips_opts
.at
);
13374 if (regno
== ILLEGAL_REG
)
13381 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13385 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13388 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13391 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13397 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13400 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13401 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13411 if (strncmp (s
, "$pc", 3) == 0)
13428 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13431 if (imm_expr
.X_op
!= O_constant
)
13433 forced_insn_length
= 4;
13434 ip
->use_extend
= TRUE
;
13439 /* We need to relax this instruction. */
13440 *offset_reloc
= *imm_reloc
;
13441 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13446 *imm_reloc
= BFD_RELOC_UNUSED
;
13447 /* Fall through. */
13454 my_getExpression (&imm_expr
, s
);
13455 if (imm_expr
.X_op
== O_register
)
13457 /* What we thought was an expression turned out to
13460 if (s
[0] == '(' && args
[1] == '(')
13462 /* It looks like the expression was omitted
13463 before a register indirection, which means
13464 that the expression is implicitly zero. We
13465 still set up imm_expr, so that we handle
13466 explicit extensions correctly. */
13467 imm_expr
.X_op
= O_constant
;
13468 imm_expr
.X_add_number
= 0;
13469 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13476 /* We need to relax this instruction. */
13477 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13486 /* We use offset_reloc rather than imm_reloc for the PC
13487 relative operands. This lets macros with both
13488 immediate and address operands work correctly. */
13489 my_getExpression (&offset_expr
, s
);
13491 if (offset_expr
.X_op
== O_register
)
13494 /* We need to relax this instruction. */
13495 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13499 case '6': /* break code */
13500 my_getExpression (&imm_expr
, s
);
13501 check_absolute_expr (ip
, &imm_expr
);
13502 if ((unsigned long) imm_expr
.X_add_number
> 63)
13503 as_warn (_("Invalid value for `%s' (%lu)"),
13505 (unsigned long) imm_expr
.X_add_number
);
13506 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13507 imm_expr
.X_op
= O_absent
;
13511 case 'a': /* 26 bit address */
13512 my_getExpression (&offset_expr
, s
);
13514 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13515 ip
->insn_opcode
<<= 16;
13518 case 'l': /* register list for entry macro */
13519 case 'L': /* register list for exit macro */
13529 unsigned int freg
, reg1
, reg2
;
13531 while (*s
== ' ' || *s
== ',')
13533 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13535 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13539 as_bad (_("can't parse register list"));
13549 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13550 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13552 as_bad (_("invalid register list"));
13556 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13558 mask
&= ~ (7 << 3);
13561 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13563 mask
&= ~ (7 << 3);
13566 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13567 mask
|= (reg2
- 3) << 3;
13568 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13569 mask
|= (reg2
- 15) << 1;
13570 else if (reg1
== RA
&& reg2
== RA
)
13574 as_bad (_("invalid register list"));
13578 /* The mask is filled in in the opcode table for the
13579 benefit of the disassembler. We remove it before
13580 applying the actual mask. */
13581 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13582 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13586 case 'm': /* Register list for save insn. */
13587 case 'M': /* Register list for restore insn. */
13590 int framesz
= 0, seen_framesz
= 0;
13591 int nargs
= 0, statics
= 0, sregs
= 0;
13595 unsigned int reg1
, reg2
;
13597 SKIP_SPACE_TABS (s
);
13600 SKIP_SPACE_TABS (s
);
13602 my_getExpression (&imm_expr
, s
);
13603 if (imm_expr
.X_op
== O_constant
)
13605 /* Handle the frame size. */
13608 as_bad (_("more than one frame size in list"));
13612 framesz
= imm_expr
.X_add_number
;
13613 imm_expr
.X_op
= O_absent
;
13618 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13620 as_bad (_("can't parse register list"));
13632 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13635 as_bad (_("can't parse register list"));
13640 while (reg1
<= reg2
)
13642 if (reg1
>= 4 && reg1
<= 7)
13646 nargs
|= 1 << (reg1
- 4);
13648 /* statics $a0-$a3 */
13649 statics
|= 1 << (reg1
- 4);
13651 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13654 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13656 else if (reg1
== 31)
13658 /* Add $ra to insn. */
13663 as_bad (_("unexpected register in list"));
13671 /* Encode args/statics combination. */
13672 if (nargs
& statics
)
13673 as_bad (_("arg/static registers overlap"));
13674 else if (nargs
== 0xf)
13675 /* All $a0-$a3 are args. */
13676 opcode
|= MIPS16_ALL_ARGS
<< 16;
13677 else if (statics
== 0xf)
13678 /* All $a0-$a3 are statics. */
13679 opcode
|= MIPS16_ALL_STATICS
<< 16;
13682 int narg
= 0, nstat
= 0;
13684 /* Count arg registers. */
13685 while (nargs
& 0x1)
13691 as_bad (_("invalid arg register list"));
13693 /* Count static registers. */
13694 while (statics
& 0x8)
13696 statics
= (statics
<< 1) & 0xf;
13700 as_bad (_("invalid static register list"));
13702 /* Encode args/statics. */
13703 opcode
|= ((narg
<< 2) | nstat
) << 16;
13706 /* Encode $s0/$s1. */
13707 if (sregs
& (1 << 0)) /* $s0 */
13709 if (sregs
& (1 << 1)) /* $s1 */
13715 /* Count regs $s2-$s8. */
13723 as_bad (_("invalid static register list"));
13724 /* Encode $s2-$s8. */
13725 opcode
|= nsreg
<< 24;
13728 /* Encode frame size. */
13730 as_bad (_("missing frame size"));
13731 else if ((framesz
& 7) != 0 || framesz
< 0
13732 || framesz
> 0xff * 8)
13733 as_bad (_("invalid frame size"));
13734 else if (framesz
!= 128 || (opcode
>> 16) != 0)
13737 opcode
|= (((framesz
& 0xf0) << 16)
13738 | (framesz
& 0x0f));
13741 /* Finally build the instruction. */
13742 if ((opcode
>> 16) != 0 || framesz
== 0)
13744 ip
->use_extend
= TRUE
;
13745 ip
->extend
= opcode
>> 16;
13747 ip
->insn_opcode
|= opcode
& 0x7f;
13751 case 'e': /* extend code */
13752 my_getExpression (&imm_expr
, s
);
13753 check_absolute_expr (ip
, &imm_expr
);
13754 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
13756 as_warn (_("Invalid value for `%s' (%lu)"),
13758 (unsigned long) imm_expr
.X_add_number
);
13759 imm_expr
.X_add_number
&= 0x7ff;
13761 ip
->insn_opcode
|= imm_expr
.X_add_number
;
13762 imm_expr
.X_op
= O_absent
;
13772 /* Args don't match. */
13773 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
13774 strcmp (insn
->name
, insn
[1].name
) == 0)
13781 insn_error
= _("illegal operands");
13787 /* This structure holds information we know about a mips16 immediate
13790 struct mips16_immed_operand
13792 /* The type code used in the argument string in the opcode table. */
13794 /* The number of bits in the short form of the opcode. */
13796 /* The number of bits in the extended form of the opcode. */
13798 /* The amount by which the short form is shifted when it is used;
13799 for example, the sw instruction has a shift count of 2. */
13801 /* The amount by which the short form is shifted when it is stored
13802 into the instruction code. */
13804 /* Non-zero if the short form is unsigned. */
13806 /* Non-zero if the extended form is unsigned. */
13808 /* Non-zero if the value is PC relative. */
13812 /* The mips16 immediate operand types. */
13814 static const struct mips16_immed_operand mips16_immed_operands
[] =
13816 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13817 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13818 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13819 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13820 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
13821 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13822 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13823 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13824 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13825 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
13826 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13827 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13828 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13829 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
13830 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13831 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13832 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13833 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13834 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
13835 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
13836 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
13839 #define MIPS16_NUM_IMMED \
13840 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13842 /* Handle a mips16 instruction with an immediate value. This or's the
13843 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13844 whether an extended value is needed; if one is needed, it sets
13845 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13846 If SMALL is true, an unextended opcode was explicitly requested.
13847 If EXT is true, an extended opcode was explicitly requested. If
13848 WARN is true, warn if EXT does not match reality. */
13851 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
13852 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
13853 unsigned long *insn
, bfd_boolean
*use_extend
,
13854 unsigned short *extend
)
13856 const struct mips16_immed_operand
*op
;
13857 int mintiny
, maxtiny
;
13858 bfd_boolean needext
;
13860 op
= mips16_immed_operands
;
13861 while (op
->type
!= type
)
13864 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13869 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13872 maxtiny
= 1 << op
->nbits
;
13877 maxtiny
= (1 << op
->nbits
) - 1;
13882 mintiny
= - (1 << (op
->nbits
- 1));
13883 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13886 /* Branch offsets have an implicit 0 in the lowest bit. */
13887 if (type
== 'p' || type
== 'q')
13890 if ((val
& ((1 << op
->shift
) - 1)) != 0
13891 || val
< (mintiny
<< op
->shift
)
13892 || val
> (maxtiny
<< op
->shift
))
13897 if (warn
&& ext
&& ! needext
)
13898 as_warn_where (file
, line
,
13899 _("extended operand requested but not required"));
13900 if (small
&& needext
)
13901 as_bad_where (file
, line
, _("invalid unextended operand value"));
13903 if (small
|| (! ext
&& ! needext
))
13907 *use_extend
= FALSE
;
13908 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
13909 insnval
<<= op
->op_shift
;
13914 long minext
, maxext
;
13920 maxext
= (1 << op
->extbits
) - 1;
13924 minext
= - (1 << (op
->extbits
- 1));
13925 maxext
= (1 << (op
->extbits
- 1)) - 1;
13927 if (val
< minext
|| val
> maxext
)
13928 as_bad_where (file
, line
,
13929 _("operand value out of range for instruction"));
13931 *use_extend
= TRUE
;
13932 if (op
->extbits
== 16)
13934 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13937 else if (op
->extbits
== 15)
13939 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13944 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13948 *extend
= (unsigned short) extval
;
13953 struct percent_op_match
13956 bfd_reloc_code_real_type reloc
;
13959 static const struct percent_op_match mips_percent_op
[] =
13961 {"%lo", BFD_RELOC_LO16
},
13963 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13964 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13965 {"%call16", BFD_RELOC_MIPS_CALL16
},
13966 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13967 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13968 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13969 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13970 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13971 {"%got", BFD_RELOC_MIPS_GOT16
},
13972 {"%gp_rel", BFD_RELOC_GPREL16
},
13973 {"%half", BFD_RELOC_16
},
13974 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13975 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13976 {"%neg", BFD_RELOC_MIPS_SUB
},
13977 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13978 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13979 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13980 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13981 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13982 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13983 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13985 {"%hi", BFD_RELOC_HI16_S
}
13988 static const struct percent_op_match mips16_percent_op
[] =
13990 {"%lo", BFD_RELOC_MIPS16_LO16
},
13991 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13992 {"%got", BFD_RELOC_MIPS16_GOT16
},
13993 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13994 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
13998 /* Return true if *STR points to a relocation operator. When returning true,
13999 move *STR over the operator and store its relocation code in *RELOC.
14000 Leave both *STR and *RELOC alone when returning false. */
14003 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14005 const struct percent_op_match
*percent_op
;
14008 if (mips_opts
.mips16
)
14010 percent_op
= mips16_percent_op
;
14011 limit
= ARRAY_SIZE (mips16_percent_op
);
14015 percent_op
= mips_percent_op
;
14016 limit
= ARRAY_SIZE (mips_percent_op
);
14019 for (i
= 0; i
< limit
; i
++)
14020 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14022 int len
= strlen (percent_op
[i
].str
);
14024 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14027 *str
+= strlen (percent_op
[i
].str
);
14028 *reloc
= percent_op
[i
].reloc
;
14030 /* Check whether the output BFD supports this relocation.
14031 If not, issue an error and fall back on something safe. */
14032 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14034 as_bad (_("relocation %s isn't supported by the current ABI"),
14035 percent_op
[i
].str
);
14036 *reloc
= BFD_RELOC_UNUSED
;
14044 /* Parse string STR as a 16-bit relocatable operand. Store the
14045 expression in *EP and the relocations in the array starting
14046 at RELOC. Return the number of relocation operators used.
14048 On exit, EXPR_END points to the first character after the expression. */
14051 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14054 bfd_reloc_code_real_type reversed_reloc
[3];
14055 size_t reloc_index
, i
;
14056 int crux_depth
, str_depth
;
14059 /* Search for the start of the main expression, recoding relocations
14060 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14061 of the main expression and with CRUX_DEPTH containing the number
14062 of open brackets at that point. */
14069 crux_depth
= str_depth
;
14071 /* Skip over whitespace and brackets, keeping count of the number
14073 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14078 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14079 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14081 my_getExpression (ep
, crux
);
14084 /* Match every open bracket. */
14085 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14089 if (crux_depth
> 0)
14090 as_bad (_("unclosed '('"));
14094 if (reloc_index
!= 0)
14096 prev_reloc_op_frag
= frag_now
;
14097 for (i
= 0; i
< reloc_index
; i
++)
14098 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14101 return reloc_index
;
14105 my_getExpression (expressionS
*ep
, char *str
)
14109 save_in
= input_line_pointer
;
14110 input_line_pointer
= str
;
14112 expr_end
= input_line_pointer
;
14113 input_line_pointer
= save_in
;
14117 md_atof (int type
, char *litP
, int *sizeP
)
14119 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14123 md_number_to_chars (char *buf
, valueT val
, int n
)
14125 if (target_big_endian
)
14126 number_to_chars_bigendian (buf
, val
, n
);
14128 number_to_chars_littleendian (buf
, val
, n
);
14132 static int support_64bit_objects(void)
14134 const char **list
, **l
;
14137 list
= bfd_target_list ();
14138 for (l
= list
; *l
!= NULL
; l
++)
14139 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14140 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14142 yes
= (*l
!= NULL
);
14146 #endif /* OBJ_ELF */
14148 const char *md_shortopts
= "O::g::G:";
14152 OPTION_MARCH
= OPTION_MD_BASE
,
14174 OPTION_NO_SMARTMIPS
,
14178 OPTION_NO_MICROMIPS
,
14179 OPTION_COMPAT_ARCH_BASE
,
14188 OPTION_M7000_HILO_FIX
,
14189 OPTION_MNO_7000_HILO_FIX
,
14192 OPTION_FIX_LOONGSON2F_JUMP
,
14193 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14194 OPTION_FIX_LOONGSON2F_NOP
,
14195 OPTION_NO_FIX_LOONGSON2F_NOP
,
14197 OPTION_NO_FIX_VR4120
,
14199 OPTION_NO_FIX_VR4130
,
14200 OPTION_FIX_CN63XXP1
,
14201 OPTION_NO_FIX_CN63XXP1
,
14208 OPTION_CONSTRUCT_FLOATS
,
14209 OPTION_NO_CONSTRUCT_FLOATS
,
14212 OPTION_RELAX_BRANCH
,
14213 OPTION_NO_RELAX_BRANCH
,
14220 OPTION_SINGLE_FLOAT
,
14221 OPTION_DOUBLE_FLOAT
,
14224 OPTION_CALL_SHARED
,
14225 OPTION_CALL_NONPIC
,
14235 OPTION_MVXWORKS_PIC
,
14236 #endif /* OBJ_ELF */
14240 struct option md_longopts
[] =
14242 /* Options which specify architecture. */
14243 {"march", required_argument
, NULL
, OPTION_MARCH
},
14244 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14245 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14246 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14247 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14248 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14249 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14250 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14251 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14252 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14253 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14254 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14256 /* Options which specify Application Specific Extensions (ASEs). */
14257 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14258 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14259 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14260 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14261 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14262 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14263 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14264 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14265 {"mmt", no_argument
, NULL
, OPTION_MT
},
14266 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14267 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14268 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14269 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14270 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14271 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14272 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14274 /* Old-style architecture options. Don't add more of these. */
14275 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14276 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14277 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14278 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14279 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14280 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14281 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14282 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14284 /* Options which enable bug fixes. */
14285 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14286 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14287 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14288 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14289 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14290 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14291 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14292 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14293 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14294 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14295 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14296 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14297 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14298 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14299 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14301 /* Miscellaneous options. */
14302 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14303 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14304 {"break", no_argument
, NULL
, OPTION_BREAK
},
14305 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14306 {"EB", no_argument
, NULL
, OPTION_EB
},
14307 {"EL", no_argument
, NULL
, OPTION_EL
},
14308 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14309 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14310 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14311 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14312 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14313 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14314 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14315 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14316 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14317 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14318 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14319 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14320 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14321 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14322 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14323 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14325 /* Strictly speaking this next option is ELF specific,
14326 but we allow it for other ports as well in order to
14327 make testing easier. */
14328 {"32", no_argument
, NULL
, OPTION_32
},
14330 /* ELF-specific options. */
14332 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14333 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14334 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14335 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14336 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14337 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14338 {"n32", no_argument
, NULL
, OPTION_N32
},
14339 {"64", no_argument
, NULL
, OPTION_64
},
14340 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14341 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14342 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14343 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14344 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14345 #endif /* OBJ_ELF */
14347 {NULL
, no_argument
, NULL
, 0}
14349 size_t md_longopts_size
= sizeof (md_longopts
);
14351 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14352 NEW_VALUE. Warn if another value was already specified. Note:
14353 we have to defer parsing the -march and -mtune arguments in order
14354 to handle 'from-abi' correctly, since the ABI might be specified
14355 in a later argument. */
14358 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14360 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14361 as_warn (_("A different %s was already specified, is now %s"),
14362 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14365 *string_ptr
= new_value
;
14369 md_parse_option (int c
, char *arg
)
14373 case OPTION_CONSTRUCT_FLOATS
:
14374 mips_disable_float_construction
= 0;
14377 case OPTION_NO_CONSTRUCT_FLOATS
:
14378 mips_disable_float_construction
= 1;
14390 target_big_endian
= 1;
14394 target_big_endian
= 0;
14400 else if (arg
[0] == '0')
14402 else if (arg
[0] == '1')
14412 mips_debug
= atoi (arg
);
14416 file_mips_isa
= ISA_MIPS1
;
14420 file_mips_isa
= ISA_MIPS2
;
14424 file_mips_isa
= ISA_MIPS3
;
14428 file_mips_isa
= ISA_MIPS4
;
14432 file_mips_isa
= ISA_MIPS5
;
14435 case OPTION_MIPS32
:
14436 file_mips_isa
= ISA_MIPS32
;
14439 case OPTION_MIPS32R2
:
14440 file_mips_isa
= ISA_MIPS32R2
;
14443 case OPTION_MIPS64R2
:
14444 file_mips_isa
= ISA_MIPS64R2
;
14447 case OPTION_MIPS64
:
14448 file_mips_isa
= ISA_MIPS64
;
14452 mips_set_option_string (&mips_tune_string
, arg
);
14456 mips_set_option_string (&mips_arch_string
, arg
);
14460 mips_set_option_string (&mips_arch_string
, "4650");
14461 mips_set_option_string (&mips_tune_string
, "4650");
14464 case OPTION_NO_M4650
:
14468 mips_set_option_string (&mips_arch_string
, "4010");
14469 mips_set_option_string (&mips_tune_string
, "4010");
14472 case OPTION_NO_M4010
:
14476 mips_set_option_string (&mips_arch_string
, "4100");
14477 mips_set_option_string (&mips_tune_string
, "4100");
14480 case OPTION_NO_M4100
:
14484 mips_set_option_string (&mips_arch_string
, "3900");
14485 mips_set_option_string (&mips_tune_string
, "3900");
14488 case OPTION_NO_M3900
:
14492 mips_opts
.ase_mdmx
= 1;
14495 case OPTION_NO_MDMX
:
14496 mips_opts
.ase_mdmx
= 0;
14500 mips_opts
.ase_dsp
= 1;
14501 mips_opts
.ase_dspr2
= 0;
14504 case OPTION_NO_DSP
:
14505 mips_opts
.ase_dsp
= 0;
14506 mips_opts
.ase_dspr2
= 0;
14510 mips_opts
.ase_dspr2
= 1;
14511 mips_opts
.ase_dsp
= 1;
14514 case OPTION_NO_DSPR2
:
14515 mips_opts
.ase_dspr2
= 0;
14516 mips_opts
.ase_dsp
= 0;
14520 mips_opts
.ase_mt
= 1;
14524 mips_opts
.ase_mt
= 0;
14527 case OPTION_MICROMIPS
:
14528 if (mips_opts
.mips16
== 1)
14530 as_bad (_("-mmicromips cannot be used with -mips16"));
14533 mips_opts
.micromips
= 1;
14534 mips_no_prev_insn ();
14537 case OPTION_NO_MICROMIPS
:
14538 mips_opts
.micromips
= 0;
14539 mips_no_prev_insn ();
14542 case OPTION_MIPS16
:
14543 if (mips_opts
.micromips
== 1)
14545 as_bad (_("-mips16 cannot be used with -micromips"));
14548 mips_opts
.mips16
= 1;
14549 mips_no_prev_insn ();
14552 case OPTION_NO_MIPS16
:
14553 mips_opts
.mips16
= 0;
14554 mips_no_prev_insn ();
14557 case OPTION_MIPS3D
:
14558 mips_opts
.ase_mips3d
= 1;
14561 case OPTION_NO_MIPS3D
:
14562 mips_opts
.ase_mips3d
= 0;
14565 case OPTION_SMARTMIPS
:
14566 mips_opts
.ase_smartmips
= 1;
14569 case OPTION_NO_SMARTMIPS
:
14570 mips_opts
.ase_smartmips
= 0;
14573 case OPTION_FIX_24K
:
14577 case OPTION_NO_FIX_24K
:
14581 case OPTION_FIX_LOONGSON2F_JUMP
:
14582 mips_fix_loongson2f_jump
= TRUE
;
14585 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14586 mips_fix_loongson2f_jump
= FALSE
;
14589 case OPTION_FIX_LOONGSON2F_NOP
:
14590 mips_fix_loongson2f_nop
= TRUE
;
14593 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14594 mips_fix_loongson2f_nop
= FALSE
;
14597 case OPTION_FIX_VR4120
:
14598 mips_fix_vr4120
= 1;
14601 case OPTION_NO_FIX_VR4120
:
14602 mips_fix_vr4120
= 0;
14605 case OPTION_FIX_VR4130
:
14606 mips_fix_vr4130
= 1;
14609 case OPTION_NO_FIX_VR4130
:
14610 mips_fix_vr4130
= 0;
14613 case OPTION_FIX_CN63XXP1
:
14614 mips_fix_cn63xxp1
= TRUE
;
14617 case OPTION_NO_FIX_CN63XXP1
:
14618 mips_fix_cn63xxp1
= FALSE
;
14621 case OPTION_RELAX_BRANCH
:
14622 mips_relax_branch
= 1;
14625 case OPTION_NO_RELAX_BRANCH
:
14626 mips_relax_branch
= 0;
14629 case OPTION_MSHARED
:
14630 mips_in_shared
= TRUE
;
14633 case OPTION_MNO_SHARED
:
14634 mips_in_shared
= FALSE
;
14637 case OPTION_MSYM32
:
14638 mips_opts
.sym32
= TRUE
;
14641 case OPTION_MNO_SYM32
:
14642 mips_opts
.sym32
= FALSE
;
14646 /* When generating ELF code, we permit -KPIC and -call_shared to
14647 select SVR4_PIC, and -non_shared to select no PIC. This is
14648 intended to be compatible with Irix 5. */
14649 case OPTION_CALL_SHARED
:
14652 as_bad (_("-call_shared is supported only for ELF format"));
14655 mips_pic
= SVR4_PIC
;
14656 mips_abicalls
= TRUE
;
14659 case OPTION_CALL_NONPIC
:
14662 as_bad (_("-call_nonpic is supported only for ELF format"));
14666 mips_abicalls
= TRUE
;
14669 case OPTION_NON_SHARED
:
14672 as_bad (_("-non_shared is supported only for ELF format"));
14676 mips_abicalls
= FALSE
;
14679 /* The -xgot option tells the assembler to use 32 bit offsets
14680 when accessing the got in SVR4_PIC mode. It is for Irix
14685 #endif /* OBJ_ELF */
14688 g_switch_value
= atoi (arg
);
14692 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14696 mips_abi
= O32_ABI
;
14697 /* We silently ignore -32 for non-ELF targets. This greatly
14698 simplifies the construction of the MIPS GAS test cases. */
14705 as_bad (_("-n32 is supported for ELF format only"));
14708 mips_abi
= N32_ABI
;
14714 as_bad (_("-64 is supported for ELF format only"));
14717 mips_abi
= N64_ABI
;
14718 if (!support_64bit_objects())
14719 as_fatal (_("No compiled in support for 64 bit object file format"));
14721 #endif /* OBJ_ELF */
14724 file_mips_gp32
= 1;
14728 file_mips_gp32
= 0;
14732 file_mips_fp32
= 1;
14736 file_mips_fp32
= 0;
14739 case OPTION_SINGLE_FLOAT
:
14740 file_mips_single_float
= 1;
14743 case OPTION_DOUBLE_FLOAT
:
14744 file_mips_single_float
= 0;
14747 case OPTION_SOFT_FLOAT
:
14748 file_mips_soft_float
= 1;
14751 case OPTION_HARD_FLOAT
:
14752 file_mips_soft_float
= 0;
14759 as_bad (_("-mabi is supported for ELF format only"));
14762 if (strcmp (arg
, "32") == 0)
14763 mips_abi
= O32_ABI
;
14764 else if (strcmp (arg
, "o64") == 0)
14765 mips_abi
= O64_ABI
;
14766 else if (strcmp (arg
, "n32") == 0)
14767 mips_abi
= N32_ABI
;
14768 else if (strcmp (arg
, "64") == 0)
14770 mips_abi
= N64_ABI
;
14771 if (! support_64bit_objects())
14772 as_fatal (_("No compiled in support for 64 bit object file "
14775 else if (strcmp (arg
, "eabi") == 0)
14776 mips_abi
= EABI_ABI
;
14779 as_fatal (_("invalid abi -mabi=%s"), arg
);
14783 #endif /* OBJ_ELF */
14785 case OPTION_M7000_HILO_FIX
:
14786 mips_7000_hilo_fix
= TRUE
;
14789 case OPTION_MNO_7000_HILO_FIX
:
14790 mips_7000_hilo_fix
= FALSE
;
14794 case OPTION_MDEBUG
:
14795 mips_flag_mdebug
= TRUE
;
14798 case OPTION_NO_MDEBUG
:
14799 mips_flag_mdebug
= FALSE
;
14803 mips_flag_pdr
= TRUE
;
14806 case OPTION_NO_PDR
:
14807 mips_flag_pdr
= FALSE
;
14810 case OPTION_MVXWORKS_PIC
:
14811 mips_pic
= VXWORKS_PIC
;
14813 #endif /* OBJ_ELF */
14819 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14824 /* Set up globals to generate code for the ISA or processor
14825 described by INFO. */
14828 mips_set_architecture (const struct mips_cpu_info
*info
)
14832 file_mips_arch
= info
->cpu
;
14833 mips_opts
.arch
= info
->cpu
;
14834 mips_opts
.isa
= info
->isa
;
14839 /* Likewise for tuning. */
14842 mips_set_tune (const struct mips_cpu_info
*info
)
14845 mips_tune
= info
->cpu
;
14850 mips_after_parse_args (void)
14852 const struct mips_cpu_info
*arch_info
= 0;
14853 const struct mips_cpu_info
*tune_info
= 0;
14855 /* GP relative stuff not working for PE */
14856 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14858 if (g_switch_seen
&& g_switch_value
!= 0)
14859 as_bad (_("-G not supported in this configuration."));
14860 g_switch_value
= 0;
14863 if (mips_abi
== NO_ABI
)
14864 mips_abi
= MIPS_DEFAULT_ABI
;
14866 /* The following code determines the architecture and register size.
14867 Similar code was added to GCC 3.3 (see override_options() in
14868 config/mips/mips.c). The GAS and GCC code should be kept in sync
14869 as much as possible. */
14871 if (mips_arch_string
!= 0)
14872 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14874 if (file_mips_isa
!= ISA_UNKNOWN
)
14876 /* Handle -mipsN. At this point, file_mips_isa contains the
14877 ISA level specified by -mipsN, while arch_info->isa contains
14878 the -march selection (if any). */
14879 if (arch_info
!= 0)
14881 /* -march takes precedence over -mipsN, since it is more descriptive.
14882 There's no harm in specifying both as long as the ISA levels
14884 if (file_mips_isa
!= arch_info
->isa
)
14885 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
14886 mips_cpu_info_from_isa (file_mips_isa
)->name
,
14887 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14890 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
14893 if (arch_info
== 0)
14894 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14896 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14897 as_bad (_("-march=%s is not compatible with the selected ABI"),
14900 mips_set_architecture (arch_info
);
14902 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
14903 if (mips_tune_string
!= 0)
14904 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14906 if (tune_info
== 0)
14907 mips_set_tune (arch_info
);
14909 mips_set_tune (tune_info
);
14911 if (file_mips_gp32
>= 0)
14913 /* The user specified the size of the integer registers. Make sure
14914 it agrees with the ABI and ISA. */
14915 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14916 as_bad (_("-mgp64 used with a 32-bit processor"));
14917 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
14918 as_bad (_("-mgp32 used with a 64-bit ABI"));
14919 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
14920 as_bad (_("-mgp64 used with a 32-bit ABI"));
14924 /* Infer the integer register size from the ABI and processor.
14925 Restrict ourselves to 32-bit registers if that's all the
14926 processor has, or if the ABI cannot handle 64-bit registers. */
14927 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
14928 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
14931 switch (file_mips_fp32
)
14935 /* No user specified float register size.
14936 ??? GAS treats single-float processors as though they had 64-bit
14937 float registers (although it complains when double-precision
14938 instructions are used). As things stand, saying they have 32-bit
14939 registers would lead to spurious "register must be even" messages.
14940 So here we assume float registers are never smaller than the
14942 if (file_mips_gp32
== 0)
14943 /* 64-bit integer registers implies 64-bit float registers. */
14944 file_mips_fp32
= 0;
14945 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
14946 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14947 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14948 file_mips_fp32
= 0;
14950 /* 32-bit float registers. */
14951 file_mips_fp32
= 1;
14954 /* The user specified the size of the float registers. Check if it
14955 agrees with the ABI and ISA. */
14957 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14958 as_bad (_("-mfp64 used with a 32-bit fpu"));
14959 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
14960 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
14961 as_warn (_("-mfp64 used with a 32-bit ABI"));
14964 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14965 as_warn (_("-mfp32 used with a 64-bit ABI"));
14969 /* End of GCC-shared inference code. */
14971 /* This flag is set when we have a 64-bit capable CPU but use only
14972 32-bit wide registers. Note that EABI does not use it. */
14973 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
14974 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
14975 || mips_abi
== O32_ABI
))
14976 mips_32bitmode
= 1;
14978 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
14979 as_bad (_("trap exception not supported at ISA 1"));
14981 /* If the selected architecture includes support for ASEs, enable
14982 generation of code for them. */
14983 if (mips_opts
.mips16
== -1)
14984 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
14985 if (mips_opts
.micromips
== -1)
14986 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
14987 if (mips_opts
.ase_mips3d
== -1)
14988 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
14989 && file_mips_fp32
== 0) ? 1 : 0;
14990 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
14991 as_bad (_("-mfp32 used with -mips3d"));
14993 if (mips_opts
.ase_mdmx
== -1)
14994 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
14995 && file_mips_fp32
== 0) ? 1 : 0;
14996 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
14997 as_bad (_("-mfp32 used with -mdmx"));
14999 if (mips_opts
.ase_smartmips
== -1)
15000 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15001 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15002 as_warn (_("%s ISA does not support SmartMIPS"),
15003 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15005 if (mips_opts
.ase_dsp
== -1)
15006 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15007 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15008 as_warn (_("%s ISA does not support DSP ASE"),
15009 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15011 if (mips_opts
.ase_dspr2
== -1)
15013 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15014 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15016 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15017 as_warn (_("%s ISA does not support DSP R2 ASE"),
15018 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15020 if (mips_opts
.ase_mt
== -1)
15021 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15022 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15023 as_warn (_("%s ISA does not support MT ASE"),
15024 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15026 file_mips_isa
= mips_opts
.isa
;
15027 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15028 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15029 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15030 file_ase_dsp
= mips_opts
.ase_dsp
;
15031 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15032 file_ase_mt
= mips_opts
.ase_mt
;
15033 mips_opts
.gp32
= file_mips_gp32
;
15034 mips_opts
.fp32
= file_mips_fp32
;
15035 mips_opts
.soft_float
= file_mips_soft_float
;
15036 mips_opts
.single_float
= file_mips_single_float
;
15038 if (mips_flag_mdebug
< 0)
15040 #ifdef OBJ_MAYBE_ECOFF
15041 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15042 mips_flag_mdebug
= 1;
15044 #endif /* OBJ_MAYBE_ECOFF */
15045 mips_flag_mdebug
= 0;
15050 mips_init_after_args (void)
15052 /* initialize opcodes */
15053 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15054 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15058 md_pcrel_from (fixS
*fixP
)
15060 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15061 switch (fixP
->fx_r_type
)
15063 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15064 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15065 /* Return the address of the delay slot. */
15068 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15069 case BFD_RELOC_MICROMIPS_JMP
:
15070 case BFD_RELOC_16_PCREL_S2
:
15071 case BFD_RELOC_MIPS_JMP
:
15072 /* Return the address of the delay slot. */
15076 /* We have no relocation type for PC relative MIPS16 instructions. */
15077 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15079 _("PC relative MIPS16 instruction references a different section"));
15084 /* This is called before the symbol table is processed. In order to
15085 work with gcc when using mips-tfile, we must keep all local labels.
15086 However, in other cases, we want to discard them. If we were
15087 called with -g, but we didn't see any debugging information, it may
15088 mean that gcc is smuggling debugging information through to
15089 mips-tfile, in which case we must generate all local labels. */
15092 mips_frob_file_before_adjust (void)
15094 #ifndef NO_ECOFF_DEBUGGING
15095 if (ECOFF_DEBUGGING
15097 && ! ecoff_debugging_seen
)
15098 flag_keep_locals
= 1;
15102 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15103 the corresponding LO16 reloc. This is called before md_apply_fix and
15104 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15105 relocation operators.
15107 For our purposes, a %lo() expression matches a %got() or %hi()
15110 (a) it refers to the same symbol; and
15111 (b) the offset applied in the %lo() expression is no lower than
15112 the offset applied in the %got() or %hi().
15114 (b) allows us to cope with code like:
15117 lh $4,%lo(foo+2)($4)
15119 ...which is legal on RELA targets, and has a well-defined behaviour
15120 if the user knows that adding 2 to "foo" will not induce a carry to
15123 When several %lo()s match a particular %got() or %hi(), we use the
15124 following rules to distinguish them:
15126 (1) %lo()s with smaller offsets are a better match than %lo()s with
15129 (2) %lo()s with no matching %got() or %hi() are better than those
15130 that already have a matching %got() or %hi().
15132 (3) later %lo()s are better than earlier %lo()s.
15134 These rules are applied in order.
15136 (1) means, among other things, that %lo()s with identical offsets are
15137 chosen if they exist.
15139 (2) means that we won't associate several high-part relocations with
15140 the same low-part relocation unless there's no alternative. Having
15141 several high parts for the same low part is a GNU extension; this rule
15142 allows careful users to avoid it.
15144 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15145 with the last high-part relocation being at the front of the list.
15146 It therefore makes sense to choose the last matching low-part
15147 relocation, all other things being equal. It's also easier
15148 to code that way. */
15151 mips_frob_file (void)
15153 struct mips_hi_fixup
*l
;
15154 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15156 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15158 segment_info_type
*seginfo
;
15159 bfd_boolean matched_lo_p
;
15160 fixS
**hi_pos
, **lo_pos
, **pos
;
15162 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15164 /* If a GOT16 relocation turns out to be against a global symbol,
15165 there isn't supposed to be a matching LO. */
15166 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15167 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
15170 /* Check quickly whether the next fixup happens to be a matching %lo. */
15171 if (fixup_has_matching_lo_p (l
->fixp
))
15174 seginfo
= seg_info (l
->seg
);
15176 /* Set HI_POS to the position of this relocation in the chain.
15177 Set LO_POS to the position of the chosen low-part relocation.
15178 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15179 relocation that matches an immediately-preceding high-part
15183 matched_lo_p
= FALSE
;
15184 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15186 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15188 if (*pos
== l
->fixp
)
15191 if ((*pos
)->fx_r_type
== looking_for_rtype
15192 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15193 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15195 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15197 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15200 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15201 && fixup_has_matching_lo_p (*pos
));
15204 /* If we found a match, remove the high-part relocation from its
15205 current position and insert it before the low-part relocation.
15206 Make the offsets match so that fixup_has_matching_lo_p()
15209 We don't warn about unmatched high-part relocations since some
15210 versions of gcc have been known to emit dead "lui ...%hi(...)"
15212 if (lo_pos
!= NULL
)
15214 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15215 if (l
->fixp
->fx_next
!= *lo_pos
)
15217 *hi_pos
= l
->fixp
->fx_next
;
15218 l
->fixp
->fx_next
= *lo_pos
;
15225 /* We may have combined relocations without symbols in the N32/N64 ABI.
15226 We have to prevent gas from dropping them. */
15229 mips_force_relocation (fixS
*fixp
)
15231 if (generic_force_reloc (fixp
))
15234 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15235 so that the linker relaxation can update targets. */
15236 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15237 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15238 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15242 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
15243 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
15244 || hi16_reloc_p (fixp
->fx_r_type
)
15245 || lo16_reloc_p (fixp
->fx_r_type
)))
15251 /* Apply a fixup to the object file. */
15254 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15258 reloc_howto_type
*howto
;
15260 /* We ignore generic BFD relocations we don't know about. */
15261 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15265 gas_assert (fixP
->fx_size
== 2
15266 || fixP
->fx_size
== 4
15267 || fixP
->fx_r_type
== BFD_RELOC_16
15268 || fixP
->fx_r_type
== BFD_RELOC_64
15269 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15270 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15271 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15272 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15273 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15274 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15276 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
15278 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15279 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15280 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15281 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
15283 /* Don't treat parts of a composite relocation as done. There are two
15286 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15287 should nevertheless be emitted if the first part is.
15289 (2) In normal usage, composite relocations are never assembly-time
15290 constants. The easiest way of dealing with the pathological
15291 exceptions is to generate a relocation against STN_UNDEF and
15292 leave everything up to the linker. */
15293 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15296 switch (fixP
->fx_r_type
)
15298 case BFD_RELOC_MIPS_TLS_GD
:
15299 case BFD_RELOC_MIPS_TLS_LDM
:
15300 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15301 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15302 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15303 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15304 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15305 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15306 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15307 case BFD_RELOC_MICROMIPS_TLS_GD
:
15308 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15309 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15310 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15311 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15312 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15313 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15314 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15317 case BFD_RELOC_MIPS_JMP
:
15318 case BFD_RELOC_MIPS_SHIFT5
:
15319 case BFD_RELOC_MIPS_SHIFT6
:
15320 case BFD_RELOC_MIPS_GOT_DISP
:
15321 case BFD_RELOC_MIPS_GOT_PAGE
:
15322 case BFD_RELOC_MIPS_GOT_OFST
:
15323 case BFD_RELOC_MIPS_SUB
:
15324 case BFD_RELOC_MIPS_INSERT_A
:
15325 case BFD_RELOC_MIPS_INSERT_B
:
15326 case BFD_RELOC_MIPS_DELETE
:
15327 case BFD_RELOC_MIPS_HIGHEST
:
15328 case BFD_RELOC_MIPS_HIGHER
:
15329 case BFD_RELOC_MIPS_SCN_DISP
:
15330 case BFD_RELOC_MIPS_REL16
:
15331 case BFD_RELOC_MIPS_RELGOT
:
15332 case BFD_RELOC_MIPS_JALR
:
15333 case BFD_RELOC_HI16
:
15334 case BFD_RELOC_HI16_S
:
15335 case BFD_RELOC_GPREL16
:
15336 case BFD_RELOC_MIPS_LITERAL
:
15337 case BFD_RELOC_MIPS_CALL16
:
15338 case BFD_RELOC_MIPS_GOT16
:
15339 case BFD_RELOC_GPREL32
:
15340 case BFD_RELOC_MIPS_GOT_HI16
:
15341 case BFD_RELOC_MIPS_GOT_LO16
:
15342 case BFD_RELOC_MIPS_CALL_HI16
:
15343 case BFD_RELOC_MIPS_CALL_LO16
:
15344 case BFD_RELOC_MIPS16_GPREL
:
15345 case BFD_RELOC_MIPS16_GOT16
:
15346 case BFD_RELOC_MIPS16_CALL16
:
15347 case BFD_RELOC_MIPS16_HI16
:
15348 case BFD_RELOC_MIPS16_HI16_S
:
15349 case BFD_RELOC_MIPS16_JMP
:
15350 case BFD_RELOC_MICROMIPS_JMP
:
15351 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15352 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15353 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15354 case BFD_RELOC_MICROMIPS_SUB
:
15355 case BFD_RELOC_MICROMIPS_HIGHEST
:
15356 case BFD_RELOC_MICROMIPS_HIGHER
:
15357 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15358 case BFD_RELOC_MICROMIPS_JALR
:
15359 case BFD_RELOC_MICROMIPS_HI16
:
15360 case BFD_RELOC_MICROMIPS_HI16_S
:
15361 case BFD_RELOC_MICROMIPS_GPREL16
:
15362 case BFD_RELOC_MICROMIPS_LITERAL
:
15363 case BFD_RELOC_MICROMIPS_CALL16
:
15364 case BFD_RELOC_MICROMIPS_GOT16
:
15365 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15366 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15367 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15368 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15369 /* Nothing needed to do. The value comes from the reloc entry. */
15373 /* This is handled like BFD_RELOC_32, but we output a sign
15374 extended value if we are only 32 bits. */
15377 if (8 <= sizeof (valueT
))
15378 md_number_to_chars ((char *) buf
, *valP
, 8);
15383 if ((*valP
& 0x80000000) != 0)
15387 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
15389 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
15395 case BFD_RELOC_RVA
:
15398 /* If we are deleting this reloc entry, we must fill in the
15399 value now. This can happen if we have a .word which is not
15400 resolved when it appears but is later defined. */
15402 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
15405 case BFD_RELOC_LO16
:
15406 case BFD_RELOC_MIPS16_LO16
:
15407 case BFD_RELOC_MICROMIPS_LO16
:
15408 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15409 may be safe to remove, but if so it's not obvious. */
15410 /* When handling an embedded PIC switch statement, we can wind
15411 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15414 if (*valP
+ 0x8000 > 0xffff)
15415 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15416 _("relocation overflow"));
15417 /* 32-bit microMIPS instructions are divided into two halfwords.
15418 Relocations always refer to the second halfword, regardless
15420 if (target_big_endian
|| fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_LO16
)
15422 md_number_to_chars ((char *) buf
, *valP
, 2);
15426 case BFD_RELOC_16_PCREL_S2
:
15427 if ((*valP
& 0x3) != 0)
15428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15429 _("Branch to misaligned address (%lx)"), (long) *valP
);
15431 /* We need to save the bits in the instruction since fixup_segment()
15432 might be deleting the relocation entry (i.e., a branch within
15433 the current segment). */
15434 if (! fixP
->fx_done
)
15437 /* Update old instruction data. */
15438 if (target_big_endian
)
15439 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
15441 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
15443 if (*valP
+ 0x20000 <= 0x3ffff)
15445 insn
|= (*valP
>> 2) & 0xffff;
15446 md_number_to_chars ((char *) buf
, insn
, 4);
15448 else if (mips_pic
== NO_PIC
15450 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15451 && (fixP
->fx_frag
->fr_address
15452 < text_section
->vma
+ bfd_get_section_size (text_section
))
15453 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15454 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15455 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15457 /* The branch offset is too large. If this is an
15458 unconditional branch, and we are not generating PIC code,
15459 we can convert it to an absolute jump instruction. */
15460 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15461 insn
= 0x0c000000; /* jal */
15463 insn
= 0x08000000; /* j */
15464 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15466 fixP
->fx_addsy
= section_symbol (text_section
);
15467 *valP
+= md_pcrel_from (fixP
);
15468 md_number_to_chars ((char *) buf
, insn
, 4);
15472 /* If we got here, we have branch-relaxation disabled,
15473 and there's nothing we can do to fix this instruction
15474 without turning it into a longer sequence. */
15475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15476 _("Branch out of range"));
15480 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15481 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15482 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15483 /* We adjust the offset back to even. */
15484 if ((*valP
& 0x1) != 0)
15487 if (! fixP
->fx_done
)
15490 /* Should never visit here, because we keep the relocation. */
15494 case BFD_RELOC_VTABLE_INHERIT
:
15497 && !S_IS_DEFINED (fixP
->fx_addsy
)
15498 && !S_IS_WEAK (fixP
->fx_addsy
))
15499 S_SET_WEAK (fixP
->fx_addsy
);
15502 case BFD_RELOC_VTABLE_ENTRY
:
15510 /* Remember value for tc_gen_reloc. */
15511 fixP
->fx_addnumber
= *valP
;
15521 name
= input_line_pointer
;
15522 c
= get_symbol_end ();
15523 p
= (symbolS
*) symbol_find_or_make (name
);
15524 *input_line_pointer
= c
;
15528 /* Align the current frag to a given power of two. If a particular
15529 fill byte should be used, FILL points to an integer that contains
15530 that byte, otherwise FILL is null.
15532 The MIPS assembler also automatically adjusts any preceding
15536 mips_align (int to
, int *fill
, symbolS
*label
)
15538 mips_emit_delays ();
15539 mips_record_compressed_mode ();
15540 if (fill
== NULL
&& subseg_text_p (now_seg
))
15541 frag_align_code (to
, 0);
15543 frag_align (to
, fill
? *fill
: 0, 0);
15544 record_alignment (now_seg
, to
);
15547 gas_assert (S_GET_SEGMENT (label
) == now_seg
);
15548 symbol_set_frag (label
, frag_now
);
15549 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
15553 /* Align to a given power of two. .align 0 turns off the automatic
15554 alignment used by the data creating pseudo-ops. */
15557 s_align (int x ATTRIBUTE_UNUSED
)
15559 int temp
, fill_value
, *fill_ptr
;
15560 long max_alignment
= 28;
15562 /* o Note that the assembler pulls down any immediately preceding label
15563 to the aligned address.
15564 o It's not documented but auto alignment is reinstated by
15565 a .align pseudo instruction.
15566 o Note also that after auto alignment is turned off the mips assembler
15567 issues an error on attempt to assemble an improperly aligned data item.
15570 temp
= get_absolute_expression ();
15571 if (temp
> max_alignment
)
15572 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15575 as_warn (_("Alignment negative: 0 assumed."));
15578 if (*input_line_pointer
== ',')
15580 ++input_line_pointer
;
15581 fill_value
= get_absolute_expression ();
15582 fill_ptr
= &fill_value
;
15588 segment_info_type
*si
= seg_info (now_seg
);
15589 struct insn_label_list
*l
= si
->label_list
;
15590 /* Auto alignment should be switched on by next section change. */
15592 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
15599 demand_empty_rest_of_line ();
15603 s_change_sec (int sec
)
15608 /* The ELF backend needs to know that we are changing sections, so
15609 that .previous works correctly. We could do something like check
15610 for an obj_section_change_hook macro, but that might be confusing
15611 as it would not be appropriate to use it in the section changing
15612 functions in read.c, since obj-elf.c intercepts those. FIXME:
15613 This should be cleaner, somehow. */
15615 obj_elf_section_change_hook ();
15618 mips_emit_delays ();
15629 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15630 demand_empty_rest_of_line ();
15634 seg
= subseg_new (RDATA_SECTION_NAME
,
15635 (subsegT
) get_absolute_expression ());
15638 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15639 | SEC_READONLY
| SEC_RELOC
15641 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15642 record_alignment (seg
, 4);
15644 demand_empty_rest_of_line ();
15648 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15651 bfd_set_section_flags (stdoutput
, seg
,
15652 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15653 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15654 record_alignment (seg
, 4);
15656 demand_empty_rest_of_line ();
15660 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15663 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15664 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15665 record_alignment (seg
, 4);
15667 demand_empty_rest_of_line ();
15675 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15678 char *section_name
;
15683 int section_entry_size
;
15684 int section_alignment
;
15689 section_name
= input_line_pointer
;
15690 c
= get_symbol_end ();
15692 next_c
= *(input_line_pointer
+ 1);
15694 /* Do we have .section Name<,"flags">? */
15695 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15697 /* just after name is now '\0'. */
15698 *input_line_pointer
= c
;
15699 input_line_pointer
= section_name
;
15700 obj_elf_section (ignore
);
15703 input_line_pointer
++;
15705 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15707 section_type
= get_absolute_expression ();
15710 if (*input_line_pointer
++ == ',')
15711 section_flag
= get_absolute_expression ();
15714 if (*input_line_pointer
++ == ',')
15715 section_entry_size
= get_absolute_expression ();
15717 section_entry_size
= 0;
15718 if (*input_line_pointer
++ == ',')
15719 section_alignment
= get_absolute_expression ();
15721 section_alignment
= 0;
15722 /* FIXME: really ignore? */
15723 (void) section_alignment
;
15725 section_name
= xstrdup (section_name
);
15727 /* When using the generic form of .section (as implemented by obj-elf.c),
15728 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15729 traditionally had to fall back on the more common @progbits instead.
15731 There's nothing really harmful in this, since bfd will correct
15732 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15733 means that, for backwards compatibility, the special_section entries
15734 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15736 Even so, we shouldn't force users of the MIPS .section syntax to
15737 incorrectly label the sections as SHT_PROGBITS. The best compromise
15738 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15739 generic type-checking code. */
15740 if (section_type
== SHT_MIPS_DWARF
)
15741 section_type
= SHT_PROGBITS
;
15743 obj_elf_change_section (section_name
, section_type
, section_flag
,
15744 section_entry_size
, 0, 0, 0);
15746 if (now_seg
->name
!= section_name
)
15747 free (section_name
);
15748 #endif /* OBJ_ELF */
15752 mips_enable_auto_align (void)
15758 s_cons (int log_size
)
15760 segment_info_type
*si
= seg_info (now_seg
);
15761 struct insn_label_list
*l
= si
->label_list
;
15764 label
= l
!= NULL
? l
->label
: NULL
;
15765 mips_emit_delays ();
15766 if (log_size
> 0 && auto_align
)
15767 mips_align (log_size
, 0, label
);
15768 cons (1 << log_size
);
15769 mips_clear_insn_labels ();
15773 s_float_cons (int type
)
15775 segment_info_type
*si
= seg_info (now_seg
);
15776 struct insn_label_list
*l
= si
->label_list
;
15779 label
= l
!= NULL
? l
->label
: NULL
;
15781 mips_emit_delays ();
15786 mips_align (3, 0, label
);
15788 mips_align (2, 0, label
);
15792 mips_clear_insn_labels ();
15795 /* Handle .globl. We need to override it because on Irix 5 you are
15798 where foo is an undefined symbol, to mean that foo should be
15799 considered to be the address of a function. */
15802 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15811 name
= input_line_pointer
;
15812 c
= get_symbol_end ();
15813 symbolP
= symbol_find_or_make (name
);
15814 S_SET_EXTERNAL (symbolP
);
15816 *input_line_pointer
= c
;
15817 SKIP_WHITESPACE ();
15819 /* On Irix 5, every global symbol that is not explicitly labelled as
15820 being a function is apparently labelled as being an object. */
15823 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15824 && (*input_line_pointer
!= ','))
15829 secname
= input_line_pointer
;
15830 c
= get_symbol_end ();
15831 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15833 as_bad (_("%s: no such section"), secname
);
15834 *input_line_pointer
= c
;
15836 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15837 flag
= BSF_FUNCTION
;
15840 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15842 c
= *input_line_pointer
;
15845 input_line_pointer
++;
15846 SKIP_WHITESPACE ();
15847 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
15853 demand_empty_rest_of_line ();
15857 s_option (int x ATTRIBUTE_UNUSED
)
15862 opt
= input_line_pointer
;
15863 c
= get_symbol_end ();
15867 /* FIXME: What does this mean? */
15869 else if (strncmp (opt
, "pic", 3) == 0)
15873 i
= atoi (opt
+ 3);
15878 mips_pic
= SVR4_PIC
;
15879 mips_abicalls
= TRUE
;
15882 as_bad (_(".option pic%d not supported"), i
);
15884 if (mips_pic
== SVR4_PIC
)
15886 if (g_switch_seen
&& g_switch_value
!= 0)
15887 as_warn (_("-G may not be used with SVR4 PIC code"));
15888 g_switch_value
= 0;
15889 bfd_set_gp_size (stdoutput
, 0);
15893 as_warn (_("Unrecognized option \"%s\""), opt
);
15895 *input_line_pointer
= c
;
15896 demand_empty_rest_of_line ();
15899 /* This structure is used to hold a stack of .set values. */
15901 struct mips_option_stack
15903 struct mips_option_stack
*next
;
15904 struct mips_set_options options
;
15907 static struct mips_option_stack
*mips_opts_stack
;
15909 /* Handle the .set pseudo-op. */
15912 s_mipsset (int x ATTRIBUTE_UNUSED
)
15914 char *name
= input_line_pointer
, ch
;
15916 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15917 ++input_line_pointer
;
15918 ch
= *input_line_pointer
;
15919 *input_line_pointer
= '\0';
15921 if (strcmp (name
, "reorder") == 0)
15923 if (mips_opts
.noreorder
)
15926 else if (strcmp (name
, "noreorder") == 0)
15928 if (!mips_opts
.noreorder
)
15929 start_noreorder ();
15931 else if (strncmp (name
, "at=", 3) == 0)
15933 char *s
= name
+ 3;
15935 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15936 as_bad (_("Unrecognized register name `%s'"), s
);
15938 else if (strcmp (name
, "at") == 0)
15940 mips_opts
.at
= ATREG
;
15942 else if (strcmp (name
, "noat") == 0)
15944 mips_opts
.at
= ZERO
;
15946 else if (strcmp (name
, "macro") == 0)
15948 mips_opts
.warn_about_macros
= 0;
15950 else if (strcmp (name
, "nomacro") == 0)
15952 if (mips_opts
.noreorder
== 0)
15953 as_bad (_("`noreorder' must be set before `nomacro'"));
15954 mips_opts
.warn_about_macros
= 1;
15956 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15958 mips_opts
.nomove
= 0;
15960 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15962 mips_opts
.nomove
= 1;
15964 else if (strcmp (name
, "bopt") == 0)
15966 mips_opts
.nobopt
= 0;
15968 else if (strcmp (name
, "nobopt") == 0)
15970 mips_opts
.nobopt
= 1;
15972 else if (strcmp (name
, "gp=default") == 0)
15973 mips_opts
.gp32
= file_mips_gp32
;
15974 else if (strcmp (name
, "gp=32") == 0)
15975 mips_opts
.gp32
= 1;
15976 else if (strcmp (name
, "gp=64") == 0)
15978 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15979 as_warn (_("%s isa does not support 64-bit registers"),
15980 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15981 mips_opts
.gp32
= 0;
15983 else if (strcmp (name
, "fp=default") == 0)
15984 mips_opts
.fp32
= file_mips_fp32
;
15985 else if (strcmp (name
, "fp=32") == 0)
15986 mips_opts
.fp32
= 1;
15987 else if (strcmp (name
, "fp=64") == 0)
15989 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15990 as_warn (_("%s isa does not support 64-bit floating point registers"),
15991 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15992 mips_opts
.fp32
= 0;
15994 else if (strcmp (name
, "softfloat") == 0)
15995 mips_opts
.soft_float
= 1;
15996 else if (strcmp (name
, "hardfloat") == 0)
15997 mips_opts
.soft_float
= 0;
15998 else if (strcmp (name
, "singlefloat") == 0)
15999 mips_opts
.single_float
= 1;
16000 else if (strcmp (name
, "doublefloat") == 0)
16001 mips_opts
.single_float
= 0;
16002 else if (strcmp (name
, "mips16") == 0
16003 || strcmp (name
, "MIPS-16") == 0)
16005 if (mips_opts
.micromips
== 1)
16006 as_fatal (_("`mips16' cannot be used with `micromips'"));
16007 mips_opts
.mips16
= 1;
16009 else if (strcmp (name
, "nomips16") == 0
16010 || strcmp (name
, "noMIPS-16") == 0)
16011 mips_opts
.mips16
= 0;
16012 else if (strcmp (name
, "micromips") == 0)
16014 if (mips_opts
.mips16
== 1)
16015 as_fatal (_("`micromips' cannot be used with `mips16'"));
16016 mips_opts
.micromips
= 1;
16018 else if (strcmp (name
, "nomicromips") == 0)
16019 mips_opts
.micromips
= 0;
16020 else if (strcmp (name
, "smartmips") == 0)
16022 if (!ISA_SUPPORTS_SMARTMIPS
)
16023 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16024 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16025 mips_opts
.ase_smartmips
= 1;
16027 else if (strcmp (name
, "nosmartmips") == 0)
16028 mips_opts
.ase_smartmips
= 0;
16029 else if (strcmp (name
, "mips3d") == 0)
16030 mips_opts
.ase_mips3d
= 1;
16031 else if (strcmp (name
, "nomips3d") == 0)
16032 mips_opts
.ase_mips3d
= 0;
16033 else if (strcmp (name
, "mdmx") == 0)
16034 mips_opts
.ase_mdmx
= 1;
16035 else if (strcmp (name
, "nomdmx") == 0)
16036 mips_opts
.ase_mdmx
= 0;
16037 else if (strcmp (name
, "dsp") == 0)
16039 if (!ISA_SUPPORTS_DSP_ASE
)
16040 as_warn (_("%s ISA does not support DSP ASE"),
16041 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16042 mips_opts
.ase_dsp
= 1;
16043 mips_opts
.ase_dspr2
= 0;
16045 else if (strcmp (name
, "nodsp") == 0)
16047 mips_opts
.ase_dsp
= 0;
16048 mips_opts
.ase_dspr2
= 0;
16050 else if (strcmp (name
, "dspr2") == 0)
16052 if (!ISA_SUPPORTS_DSPR2_ASE
)
16053 as_warn (_("%s ISA does not support DSP R2 ASE"),
16054 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16055 mips_opts
.ase_dspr2
= 1;
16056 mips_opts
.ase_dsp
= 1;
16058 else if (strcmp (name
, "nodspr2") == 0)
16060 mips_opts
.ase_dspr2
= 0;
16061 mips_opts
.ase_dsp
= 0;
16063 else if (strcmp (name
, "mt") == 0)
16065 if (!ISA_SUPPORTS_MT_ASE
)
16066 as_warn (_("%s ISA does not support MT ASE"),
16067 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16068 mips_opts
.ase_mt
= 1;
16070 else if (strcmp (name
, "nomt") == 0)
16071 mips_opts
.ase_mt
= 0;
16072 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16076 /* Permit the user to change the ISA and architecture on the fly.
16077 Needless to say, misuse can cause serious problems. */
16078 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16081 mips_opts
.isa
= file_mips_isa
;
16082 mips_opts
.arch
= file_mips_arch
;
16084 else if (strncmp (name
, "arch=", 5) == 0)
16086 const struct mips_cpu_info
*p
;
16088 p
= mips_parse_cpu("internal use", name
+ 5);
16090 as_bad (_("unknown architecture %s"), name
+ 5);
16093 mips_opts
.arch
= p
->cpu
;
16094 mips_opts
.isa
= p
->isa
;
16097 else if (strncmp (name
, "mips", 4) == 0)
16099 const struct mips_cpu_info
*p
;
16101 p
= mips_parse_cpu("internal use", name
);
16103 as_bad (_("unknown ISA level %s"), name
+ 4);
16106 mips_opts
.arch
= p
->cpu
;
16107 mips_opts
.isa
= p
->isa
;
16111 as_bad (_("unknown ISA or architecture %s"), name
);
16113 switch (mips_opts
.isa
)
16121 mips_opts
.gp32
= 1;
16122 mips_opts
.fp32
= 1;
16129 mips_opts
.gp32
= 0;
16130 mips_opts
.fp32
= 0;
16133 as_bad (_("unknown ISA level %s"), name
+ 4);
16138 mips_opts
.gp32
= file_mips_gp32
;
16139 mips_opts
.fp32
= file_mips_fp32
;
16142 else if (strcmp (name
, "autoextend") == 0)
16143 mips_opts
.noautoextend
= 0;
16144 else if (strcmp (name
, "noautoextend") == 0)
16145 mips_opts
.noautoextend
= 1;
16146 else if (strcmp (name
, "push") == 0)
16148 struct mips_option_stack
*s
;
16150 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16151 s
->next
= mips_opts_stack
;
16152 s
->options
= mips_opts
;
16153 mips_opts_stack
= s
;
16155 else if (strcmp (name
, "pop") == 0)
16157 struct mips_option_stack
*s
;
16159 s
= mips_opts_stack
;
16161 as_bad (_(".set pop with no .set push"));
16164 /* If we're changing the reorder mode we need to handle
16165 delay slots correctly. */
16166 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16167 start_noreorder ();
16168 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16171 mips_opts
= s
->options
;
16172 mips_opts_stack
= s
->next
;
16176 else if (strcmp (name
, "sym32") == 0)
16177 mips_opts
.sym32
= TRUE
;
16178 else if (strcmp (name
, "nosym32") == 0)
16179 mips_opts
.sym32
= FALSE
;
16180 else if (strchr (name
, ','))
16182 /* Generic ".set" directive; use the generic handler. */
16183 *input_line_pointer
= ch
;
16184 input_line_pointer
= name
;
16190 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16192 *input_line_pointer
= ch
;
16193 demand_empty_rest_of_line ();
16196 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16197 .option pic2. It means to generate SVR4 PIC calls. */
16200 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16202 mips_pic
= SVR4_PIC
;
16203 mips_abicalls
= TRUE
;
16205 if (g_switch_seen
&& g_switch_value
!= 0)
16206 as_warn (_("-G may not be used with SVR4 PIC code"));
16207 g_switch_value
= 0;
16209 bfd_set_gp_size (stdoutput
, 0);
16210 demand_empty_rest_of_line ();
16213 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16214 PIC code. It sets the $gp register for the function based on the
16215 function address, which is in the register named in the argument.
16216 This uses a relocation against _gp_disp, which is handled specially
16217 by the linker. The result is:
16218 lui $gp,%hi(_gp_disp)
16219 addiu $gp,$gp,%lo(_gp_disp)
16220 addu $gp,$gp,.cpload argument
16221 The .cpload argument is normally $25 == $t9.
16223 The -mno-shared option changes this to:
16224 lui $gp,%hi(__gnu_local_gp)
16225 addiu $gp,$gp,%lo(__gnu_local_gp)
16226 and the argument is ignored. This saves an instruction, but the
16227 resulting code is not position independent; it uses an absolute
16228 address for __gnu_local_gp. Thus code assembled with -mno-shared
16229 can go into an ordinary executable, but not into a shared library. */
16232 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16238 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16239 .cpload is ignored. */
16240 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16246 /* .cpload should be in a .set noreorder section. */
16247 if (mips_opts
.noreorder
== 0)
16248 as_warn (_(".cpload not in noreorder section"));
16250 reg
= tc_get_register (0);
16252 /* If we need to produce a 64-bit address, we are better off using
16253 the default instruction sequence. */
16254 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16256 ex
.X_op
= O_symbol
;
16257 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16259 ex
.X_op_symbol
= NULL
;
16260 ex
.X_add_number
= 0;
16262 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16263 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16266 macro_build_lui (&ex
, mips_gp_register
);
16267 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16268 mips_gp_register
, BFD_RELOC_LO16
);
16270 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16271 mips_gp_register
, reg
);
16274 demand_empty_rest_of_line ();
16277 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16278 .cpsetup $reg1, offset|$reg2, label
16280 If offset is given, this results in:
16281 sd $gp, offset($sp)
16282 lui $gp, %hi(%neg(%gp_rel(label)))
16283 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16284 daddu $gp, $gp, $reg1
16286 If $reg2 is given, this results in:
16287 daddu $reg2, $gp, $0
16288 lui $gp, %hi(%neg(%gp_rel(label)))
16289 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16290 daddu $gp, $gp, $reg1
16291 $reg1 is normally $25 == $t9.
16293 The -mno-shared option replaces the last three instructions with
16295 addiu $gp,$gp,%lo(_gp) */
16298 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16300 expressionS ex_off
;
16301 expressionS ex_sym
;
16304 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16305 We also need NewABI support. */
16306 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16312 reg1
= tc_get_register (0);
16313 SKIP_WHITESPACE ();
16314 if (*input_line_pointer
!= ',')
16316 as_bad (_("missing argument separator ',' for .cpsetup"));
16320 ++input_line_pointer
;
16321 SKIP_WHITESPACE ();
16322 if (*input_line_pointer
== '$')
16324 mips_cpreturn_register
= tc_get_register (0);
16325 mips_cpreturn_offset
= -1;
16329 mips_cpreturn_offset
= get_absolute_expression ();
16330 mips_cpreturn_register
= -1;
16332 SKIP_WHITESPACE ();
16333 if (*input_line_pointer
!= ',')
16335 as_bad (_("missing argument separator ',' for .cpsetup"));
16339 ++input_line_pointer
;
16340 SKIP_WHITESPACE ();
16341 expression (&ex_sym
);
16344 if (mips_cpreturn_register
== -1)
16346 ex_off
.X_op
= O_constant
;
16347 ex_off
.X_add_symbol
= NULL
;
16348 ex_off
.X_op_symbol
= NULL
;
16349 ex_off
.X_add_number
= mips_cpreturn_offset
;
16351 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16352 BFD_RELOC_LO16
, SP
);
16355 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16356 mips_gp_register
, 0);
16358 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16360 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16361 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16364 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16365 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16366 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16369 mips_gp_register
, reg1
);
16375 ex
.X_op
= O_symbol
;
16376 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16377 ex
.X_op_symbol
= NULL
;
16378 ex
.X_add_number
= 0;
16380 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16381 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16383 macro_build_lui (&ex
, mips_gp_register
);
16384 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16385 mips_gp_register
, BFD_RELOC_LO16
);
16390 demand_empty_rest_of_line ();
16394 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16396 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16397 .cplocal is ignored. */
16398 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16404 mips_gp_register
= tc_get_register (0);
16405 demand_empty_rest_of_line ();
16408 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16409 offset from $sp. The offset is remembered, and after making a PIC
16410 call $gp is restored from that location. */
16413 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16417 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16418 .cprestore is ignored. */
16419 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16425 mips_cprestore_offset
= get_absolute_expression ();
16426 mips_cprestore_valid
= 1;
16428 ex
.X_op
= O_constant
;
16429 ex
.X_add_symbol
= NULL
;
16430 ex
.X_op_symbol
= NULL
;
16431 ex
.X_add_number
= mips_cprestore_offset
;
16434 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16435 SP
, HAVE_64BIT_ADDRESSES
);
16438 demand_empty_rest_of_line ();
16441 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16442 was given in the preceding .cpsetup, it results in:
16443 ld $gp, offset($sp)
16445 If a register $reg2 was given there, it results in:
16446 daddu $gp, $reg2, $0 */
16449 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16453 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16454 We also need NewABI support. */
16455 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16462 if (mips_cpreturn_register
== -1)
16464 ex
.X_op
= O_constant
;
16465 ex
.X_add_symbol
= NULL
;
16466 ex
.X_op_symbol
= NULL
;
16467 ex
.X_add_number
= mips_cpreturn_offset
;
16469 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16472 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16473 mips_cpreturn_register
, 0);
16476 demand_empty_rest_of_line ();
16479 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
16480 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
16481 use in DWARF debug information. */
16484 s_dtprel_internal (size_t bytes
)
16491 if (ex
.X_op
!= O_symbol
)
16493 as_bad (_("Unsupported use of %s"), (bytes
== 8
16496 ignore_rest_of_line ();
16499 p
= frag_more (bytes
);
16500 md_number_to_chars (p
, 0, bytes
);
16501 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
16503 ? BFD_RELOC_MIPS_TLS_DTPREL64
16504 : BFD_RELOC_MIPS_TLS_DTPREL32
));
16506 demand_empty_rest_of_line ();
16509 /* Handle .dtprelword. */
16512 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16514 s_dtprel_internal (4);
16517 /* Handle .dtpreldword. */
16520 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16522 s_dtprel_internal (8);
16525 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16526 code. It sets the offset to use in gp_rel relocations. */
16529 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16531 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16532 We also need NewABI support. */
16533 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16539 mips_gprel_offset
= get_absolute_expression ();
16541 demand_empty_rest_of_line ();
16544 /* Handle the .gpword pseudo-op. This is used when generating PIC
16545 code. It generates a 32 bit GP relative reloc. */
16548 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16550 segment_info_type
*si
;
16551 struct insn_label_list
*l
;
16556 /* When not generating PIC code, this is treated as .word. */
16557 if (mips_pic
!= SVR4_PIC
)
16563 si
= seg_info (now_seg
);
16564 l
= si
->label_list
;
16565 label
= l
!= NULL
? l
->label
: NULL
;
16566 mips_emit_delays ();
16568 mips_align (2, 0, label
);
16571 mips_clear_insn_labels ();
16573 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16575 as_bad (_("Unsupported use of .gpword"));
16576 ignore_rest_of_line ();
16580 md_number_to_chars (p
, 0, 4);
16581 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16582 BFD_RELOC_GPREL32
);
16584 demand_empty_rest_of_line ();
16588 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16590 segment_info_type
*si
;
16591 struct insn_label_list
*l
;
16596 /* When not generating PIC code, this is treated as .dword. */
16597 if (mips_pic
!= SVR4_PIC
)
16603 si
= seg_info (now_seg
);
16604 l
= si
->label_list
;
16605 label
= l
!= NULL
? l
->label
: NULL
;
16606 mips_emit_delays ();
16608 mips_align (3, 0, label
);
16611 mips_clear_insn_labels ();
16613 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16615 as_bad (_("Unsupported use of .gpdword"));
16616 ignore_rest_of_line ();
16620 md_number_to_chars (p
, 0, 8);
16621 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16622 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16624 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16625 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16626 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16628 demand_empty_rest_of_line ();
16631 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16632 tables in SVR4 PIC code. */
16635 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16639 /* This is ignored when not generating SVR4 PIC code. */
16640 if (mips_pic
!= SVR4_PIC
)
16646 /* Add $gp to the register named as an argument. */
16648 reg
= tc_get_register (0);
16649 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16652 demand_empty_rest_of_line ();
16655 /* Handle the .insn pseudo-op. This marks instruction labels in
16656 mips16/micromips mode. This permits the linker to handle them specially,
16657 such as generating jalx instructions when needed. We also make
16658 them odd for the duration of the assembly, in order to generate the
16659 right sort of code. We will make them even in the adjust_symtab
16660 routine, while leaving them marked. This is convenient for the
16661 debugger and the disassembler. The linker knows to make them odd
16665 s_insn (int ignore ATTRIBUTE_UNUSED
)
16667 mips_mark_labels ();
16669 demand_empty_rest_of_line ();
16672 /* Handle a .stabn directive. We need these in order to mark a label
16673 as being a mips16 text label correctly. Sometimes the compiler
16674 will emit a label, followed by a .stabn, and then switch sections.
16675 If the label and .stabn are in mips16 mode, then the label is
16676 really a mips16 text label. */
16679 s_mips_stab (int type
)
16682 mips_mark_labels ();
16687 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16690 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16697 name
= input_line_pointer
;
16698 c
= get_symbol_end ();
16699 symbolP
= symbol_find_or_make (name
);
16700 S_SET_WEAK (symbolP
);
16701 *input_line_pointer
= c
;
16703 SKIP_WHITESPACE ();
16705 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16707 if (S_IS_DEFINED (symbolP
))
16709 as_bad (_("ignoring attempt to redefine symbol %s"),
16710 S_GET_NAME (symbolP
));
16711 ignore_rest_of_line ();
16715 if (*input_line_pointer
== ',')
16717 ++input_line_pointer
;
16718 SKIP_WHITESPACE ();
16722 if (exp
.X_op
!= O_symbol
)
16724 as_bad (_("bad .weakext directive"));
16725 ignore_rest_of_line ();
16728 symbol_set_value_expression (symbolP
, &exp
);
16731 demand_empty_rest_of_line ();
16734 /* Parse a register string into a number. Called from the ECOFF code
16735 to parse .frame. The argument is non-zero if this is the frame
16736 register, so that we can record it in mips_frame_reg. */
16739 tc_get_register (int frame
)
16743 SKIP_WHITESPACE ();
16744 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16748 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16749 mips_frame_reg_valid
= 1;
16750 mips_cprestore_valid
= 0;
16756 md_section_align (asection
*seg
, valueT addr
)
16758 int align
= bfd_get_section_alignment (stdoutput
, seg
);
16762 /* We don't need to align ELF sections to the full alignment.
16763 However, Irix 5 may prefer that we align them at least to a 16
16764 byte boundary. We don't bother to align the sections if we
16765 are targeted for an embedded system. */
16766 if (strncmp (TARGET_OS
, "elf", 3) == 0)
16772 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
16775 /* Utility routine, called from above as well. If called while the
16776 input file is still being read, it's only an approximation. (For
16777 example, a symbol may later become defined which appeared to be
16778 undefined earlier.) */
16781 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
16786 if (g_switch_value
> 0)
16788 const char *symname
;
16791 /* Find out whether this symbol can be referenced off the $gp
16792 register. It can be if it is smaller than the -G size or if
16793 it is in the .sdata or .sbss section. Certain symbols can
16794 not be referenced off the $gp, although it appears as though
16796 symname
= S_GET_NAME (sym
);
16797 if (symname
!= (const char *) NULL
16798 && (strcmp (symname
, "eprol") == 0
16799 || strcmp (symname
, "etext") == 0
16800 || strcmp (symname
, "_gp") == 0
16801 || strcmp (symname
, "edata") == 0
16802 || strcmp (symname
, "_fbss") == 0
16803 || strcmp (symname
, "_fdata") == 0
16804 || strcmp (symname
, "_ftext") == 0
16805 || strcmp (symname
, "end") == 0
16806 || strcmp (symname
, "_gp_disp") == 0))
16808 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
16810 #ifndef NO_ECOFF_DEBUGGING
16811 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
16812 && (symbol_get_obj (sym
)->ecoff_extern_size
16813 <= g_switch_value
))
16815 /* We must defer this decision until after the whole
16816 file has been read, since there might be a .extern
16817 after the first use of this symbol. */
16818 || (before_relaxing
16819 #ifndef NO_ECOFF_DEBUGGING
16820 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
16822 && S_GET_VALUE (sym
) == 0)
16823 || (S_GET_VALUE (sym
) != 0
16824 && S_GET_VALUE (sym
) <= g_switch_value
)))
16828 const char *segname
;
16830 segname
= segment_name (S_GET_SEGMENT (sym
));
16831 gas_assert (strcmp (segname
, ".lit8") != 0
16832 && strcmp (segname
, ".lit4") != 0);
16833 change
= (strcmp (segname
, ".sdata") != 0
16834 && strcmp (segname
, ".sbss") != 0
16835 && strncmp (segname
, ".sdata.", 7) != 0
16836 && strncmp (segname
, ".sbss.", 6) != 0
16837 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16838 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16843 /* We are not optimizing for the $gp register. */
16848 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16851 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16855 /* Handle the case of a symbol equated to another symbol. */
16856 while (symbol_equated_reloc_p (sym
))
16860 /* It's possible to get a loop here in a badly written program. */
16861 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16867 if (symbol_section_p (sym
))
16870 symsec
= S_GET_SEGMENT (sym
);
16872 /* This must duplicate the test in adjust_reloc_syms. */
16873 return (symsec
!= &bfd_und_section
16874 && symsec
!= &bfd_abs_section
16875 && !bfd_is_com_section (symsec
)
16876 && !s_is_linkonce (sym
, segtype
)
16878 /* A global or weak symbol is treated as external. */
16879 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
16885 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16886 extended opcode. SEC is the section the frag is in. */
16889 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16892 const struct mips16_immed_operand
*op
;
16894 int mintiny
, maxtiny
;
16898 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16900 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16903 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16904 op
= mips16_immed_operands
;
16905 while (op
->type
!= type
)
16908 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
16913 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
16916 maxtiny
= 1 << op
->nbits
;
16921 maxtiny
= (1 << op
->nbits
) - 1;
16926 mintiny
= - (1 << (op
->nbits
- 1));
16927 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
16930 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16931 val
= S_GET_VALUE (fragp
->fr_symbol
);
16932 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16938 /* We won't have the section when we are called from
16939 mips_relax_frag. However, we will always have been called
16940 from md_estimate_size_before_relax first. If this is a
16941 branch to a different section, we mark it as such. If SEC is
16942 NULL, and the frag is not marked, then it must be a branch to
16943 the same section. */
16946 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16951 /* Must have been called from md_estimate_size_before_relax. */
16954 fragp
->fr_subtype
=
16955 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16957 /* FIXME: We should support this, and let the linker
16958 catch branches and loads that are out of range. */
16959 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16960 _("unsupported PC relative reference to different section"));
16964 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16965 /* Assume non-extended on the first relaxation pass.
16966 The address we have calculated will be bogus if this is
16967 a forward branch to another frag, as the forward frag
16968 will have fr_address == 0. */
16972 /* In this case, we know for sure that the symbol fragment is in
16973 the same section. If the relax_marker of the symbol fragment
16974 differs from the relax_marker of this fragment, we have not
16975 yet adjusted the symbol fragment fr_address. We want to add
16976 in STRETCH in order to get a better estimate of the address.
16977 This particularly matters because of the shift bits. */
16979 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16983 /* Adjust stretch for any alignment frag. Note that if have
16984 been expanding the earlier code, the symbol may be
16985 defined in what appears to be an earlier frag. FIXME:
16986 This doesn't handle the fr_subtype field, which specifies
16987 a maximum number of bytes to skip when doing an
16989 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16991 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16994 stretch
= - ((- stretch
)
16995 & ~ ((1 << (int) f
->fr_offset
) - 1));
16997 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17006 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17008 /* The base address rules are complicated. The base address of
17009 a branch is the following instruction. The base address of a
17010 PC relative load or add is the instruction itself, but if it
17011 is in a delay slot (in which case it can not be extended) use
17012 the address of the instruction whose delay slot it is in. */
17013 if (type
== 'p' || type
== 'q')
17017 /* If we are currently assuming that this frag should be
17018 extended, then, the current address is two bytes
17020 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17023 /* Ignore the low bit in the target, since it will be set
17024 for a text label. */
17025 if ((val
& 1) != 0)
17028 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17030 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17033 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17035 /* Branch offsets have an implicit 0 in the lowest bit. */
17036 if (type
== 'p' || type
== 'q')
17039 /* If any of the shifted bits are set, we must use an extended
17040 opcode. If the address depends on the size of this
17041 instruction, this can lead to a loop, so we arrange to always
17042 use an extended opcode. We only check this when we are in
17043 the main relaxation loop, when SEC is NULL. */
17044 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17046 fragp
->fr_subtype
=
17047 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17051 /* If we are about to mark a frag as extended because the value
17052 is precisely maxtiny + 1, then there is a chance of an
17053 infinite loop as in the following code:
17058 In this case when the la is extended, foo is 0x3fc bytes
17059 away, so the la can be shrunk, but then foo is 0x400 away, so
17060 the la must be extended. To avoid this loop, we mark the
17061 frag as extended if it was small, and is about to become
17062 extended with a value of maxtiny + 1. */
17063 if (val
== ((maxtiny
+ 1) << op
->shift
)
17064 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17067 fragp
->fr_subtype
=
17068 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17072 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17073 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17075 if ((val
& ((1 << op
->shift
) - 1)) != 0
17076 || val
< (mintiny
<< op
->shift
)
17077 || val
> (maxtiny
<< op
->shift
))
17083 /* Compute the length of a branch sequence, and adjust the
17084 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17085 worst-case length is computed, with UPDATE being used to indicate
17086 whether an unconditional (-1), branch-likely (+1) or regular (0)
17087 branch is to be computed. */
17089 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17091 bfd_boolean toofar
;
17095 && S_IS_DEFINED (fragp
->fr_symbol
)
17096 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17101 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17103 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17107 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17110 /* If the symbol is not defined or it's in a different segment,
17111 assume the user knows what's going on and emit a short
17117 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17119 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17120 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17121 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17122 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17128 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17131 if (mips_pic
!= NO_PIC
)
17133 /* Additional space for PIC loading of target address. */
17135 if (mips_opts
.isa
== ISA_MIPS1
)
17136 /* Additional space for $at-stabilizing nop. */
17140 /* If branch is conditional. */
17141 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17148 /* Compute the length of a branch sequence, and adjust the
17149 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17150 worst-case length is computed, with UPDATE being used to indicate
17151 whether an unconditional (-1), or regular (0) branch is to be
17155 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17157 bfd_boolean toofar
;
17161 && S_IS_DEFINED (fragp
->fr_symbol
)
17162 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17167 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17168 /* Ignore the low bit in the target, since it will be set
17169 for a text label. */
17170 if ((val
& 1) != 0)
17173 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17177 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17180 /* If the symbol is not defined or it's in a different segment,
17181 assume the user knows what's going on and emit a short
17187 if (fragp
&& update
17188 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17189 fragp
->fr_subtype
= (toofar
17190 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17191 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17196 bfd_boolean compact_known
= fragp
!= NULL
;
17197 bfd_boolean compact
= FALSE
;
17198 bfd_boolean uncond
;
17201 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17203 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17205 uncond
= update
< 0;
17207 /* If label is out of range, we turn branch <br>:
17209 <br> label # 4 bytes
17215 nop # 2 bytes if compact && !PIC
17218 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17221 /* If assembling PIC code, we further turn:
17227 lw/ld at, %got(label)(gp) # 4 bytes
17228 d/addiu at, %lo(label) # 4 bytes
17231 if (mips_pic
!= NO_PIC
)
17234 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17236 <brneg> 0f # 4 bytes
17237 nop # 2 bytes if !compact
17240 length
+= (compact_known
&& compact
) ? 4 : 6;
17246 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17247 bit accordingly. */
17250 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17252 bfd_boolean toofar
;
17255 && S_IS_DEFINED (fragp
->fr_symbol
)
17256 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17262 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17263 /* Ignore the low bit in the target, since it will be set
17264 for a text label. */
17265 if ((val
& 1) != 0)
17268 /* Assume this is a 2-byte branch. */
17269 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17271 /* We try to avoid the infinite loop by not adding 2 more bytes for
17276 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17278 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17279 else if (type
== 'E')
17280 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17285 /* If the symbol is not defined or it's in a different segment,
17286 we emit a normal 32-bit branch. */
17289 if (fragp
&& update
17290 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17292 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17293 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17301 /* Estimate the size of a frag before relaxing. Unless this is the
17302 mips16, we are not really relaxing here, and the final size is
17303 encoded in the subtype information. For the mips16, we have to
17304 decide whether we are using an extended opcode or not. */
17307 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17311 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17314 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17316 return fragp
->fr_var
;
17319 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17320 /* We don't want to modify the EXTENDED bit here; it might get us
17321 into infinite loops. We change it only in mips_relax_frag(). */
17322 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17324 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17328 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17329 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17330 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17331 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17332 fragp
->fr_var
= length
;
17337 if (mips_pic
== NO_PIC
)
17338 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17339 else if (mips_pic
== SVR4_PIC
)
17340 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17341 else if (mips_pic
== VXWORKS_PIC
)
17342 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17349 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17350 return -RELAX_FIRST (fragp
->fr_subtype
);
17353 return -RELAX_SECOND (fragp
->fr_subtype
);
17356 /* This is called to see whether a reloc against a defined symbol
17357 should be converted into a reloc against a section. */
17360 mips_fix_adjustable (fixS
*fixp
)
17362 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17363 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17366 if (fixp
->fx_addsy
== NULL
)
17369 /* If symbol SYM is in a mergeable section, relocations of the form
17370 SYM + 0 can usually be made section-relative. The mergeable data
17371 is then identified by the section offset rather than by the symbol.
17373 However, if we're generating REL LO16 relocations, the offset is split
17374 between the LO16 and parterning high part relocation. The linker will
17375 need to recalculate the complete offset in order to correctly identify
17378 The linker has traditionally not looked for the parterning high part
17379 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17380 placed anywhere. Rather than break backwards compatibility by changing
17381 this, it seems better not to force the issue, and instead keep the
17382 original symbol. This will work with either linker behavior. */
17383 if ((lo16_reloc_p (fixp
->fx_r_type
)
17384 || reloc_needs_lo_p (fixp
->fx_r_type
))
17385 && HAVE_IN_PLACE_ADDENDS
17386 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17389 /* There is no place to store an in-place offset for JALR relocations.
17390 Likewise an in-range offset of PC-relative relocations may overflow
17391 the in-place relocatable field if recalculated against the start
17392 address of the symbol's containing section. */
17393 if (HAVE_IN_PLACE_ADDENDS
17394 && (fixp
->fx_pcrel
|| jalr_reloc_p (fixp
->fx_r_type
)))
17398 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17399 to a floating-point stub. The same is true for non-R_MIPS16_26
17400 relocations against MIPS16 functions; in this case, the stub becomes
17401 the function's canonical address.
17403 Floating-point stubs are stored in unique .mips16.call.* or
17404 .mips16.fn.* sections. If a stub T for function F is in section S,
17405 the first relocation in section S must be against F; this is how the
17406 linker determines the target function. All relocations that might
17407 resolve to T must also be against F. We therefore have the following
17408 restrictions, which are given in an intentionally-redundant way:
17410 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17413 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17414 if that stub might be used.
17416 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17419 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17420 that stub might be used.
17422 There is a further restriction:
17424 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17425 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17426 targets with in-place addends; the relocation field cannot
17427 encode the low bit.
17429 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17430 against a MIPS16 symbol. We deal with (5) by by not reducing any
17431 such relocations on REL targets.
17433 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17434 relocation against some symbol R, no relocation against R may be
17435 reduced. (Note that this deals with (2) as well as (1) because
17436 relocations against global symbols will never be reduced on ELF
17437 targets.) This approach is a little simpler than trying to detect
17438 stub sections, and gives the "all or nothing" per-symbol consistency
17439 that we have for MIPS16 symbols. */
17441 && fixp
->fx_subsy
== NULL
17442 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17443 || *symbol_get_tc (fixp
->fx_addsy
)
17444 || (HAVE_IN_PLACE_ADDENDS
17445 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17446 && jmp_reloc_p (fixp
->fx_r_type
))))
17453 /* Translate internal representation of relocation info to BFD target
17457 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17459 static arelent
*retval
[4];
17461 bfd_reloc_code_real_type code
;
17463 memset (retval
, 0, sizeof(retval
));
17464 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17465 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17466 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17467 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17469 if (fixp
->fx_pcrel
)
17471 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17472 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17473 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17474 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17476 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17477 Relocations want only the symbol offset. */
17478 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17481 /* A gruesome hack which is a result of the gruesome gas
17482 reloc handling. What's worse, for COFF (as opposed to
17483 ECOFF), we might need yet another copy of reloc->address.
17484 See bfd_install_relocation. */
17485 reloc
->addend
+= reloc
->address
;
17489 reloc
->addend
= fixp
->fx_addnumber
;
17491 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17492 entry to be used in the relocation's section offset. */
17493 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17495 reloc
->address
= reloc
->addend
;
17499 code
= fixp
->fx_r_type
;
17501 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17502 if (reloc
->howto
== NULL
)
17504 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17505 _("Can not represent %s relocation in this object file format"),
17506 bfd_get_reloc_code_name (code
));
17513 /* Relax a machine dependent frag. This returns the amount by which
17514 the current size of the frag should change. */
17517 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17519 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17521 offsetT old_var
= fragp
->fr_var
;
17523 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17525 return fragp
->fr_var
- old_var
;
17528 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17530 offsetT old_var
= fragp
->fr_var
;
17531 offsetT new_var
= 4;
17533 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17534 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17535 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17536 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17537 fragp
->fr_var
= new_var
;
17539 return new_var
- old_var
;
17542 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17545 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17547 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17549 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17554 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17556 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17563 /* Convert a machine dependent frag. */
17566 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17568 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17571 unsigned long insn
;
17575 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
17577 if (target_big_endian
)
17578 insn
= bfd_getb32 (buf
);
17580 insn
= bfd_getl32 (buf
);
17582 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17584 /* We generate a fixup instead of applying it right now
17585 because, if there are linker relaxations, we're going to
17586 need the relocations. */
17587 exp
.X_op
= O_symbol
;
17588 exp
.X_add_symbol
= fragp
->fr_symbol
;
17589 exp
.X_add_number
= fragp
->fr_offset
;
17591 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17592 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
17593 fixp
->fx_file
= fragp
->fr_file
;
17594 fixp
->fx_line
= fragp
->fr_line
;
17596 md_number_to_chars ((char *) buf
, insn
, 4);
17603 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17604 _("Relaxed out-of-range branch into a jump"));
17606 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17609 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17611 /* Reverse the branch. */
17612 switch ((insn
>> 28) & 0xf)
17615 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17616 have the condition reversed by tweaking a single
17617 bit, and their opcodes all have 0x4???????. */
17618 gas_assert ((insn
& 0xf1000000) == 0x41000000);
17619 insn
^= 0x00010000;
17623 /* bltz 0x04000000 bgez 0x04010000
17624 bltzal 0x04100000 bgezal 0x04110000 */
17625 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17626 insn
^= 0x00010000;
17630 /* beq 0x10000000 bne 0x14000000
17631 blez 0x18000000 bgtz 0x1c000000 */
17632 insn
^= 0x04000000;
17640 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17642 /* Clear the and-link bit. */
17643 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17645 /* bltzal 0x04100000 bgezal 0x04110000
17646 bltzall 0x04120000 bgezall 0x04130000 */
17647 insn
&= ~0x00100000;
17650 /* Branch over the branch (if the branch was likely) or the
17651 full jump (not likely case). Compute the offset from the
17652 current instruction to branch to. */
17653 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17657 /* How many bytes in instructions we've already emitted? */
17658 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
17659 /* How many bytes in instructions from here to the end? */
17660 i
= fragp
->fr_var
- i
;
17662 /* Convert to instruction count. */
17664 /* Branch counts from the next instruction. */
17667 /* Branch over the jump. */
17668 md_number_to_chars ((char *) buf
, insn
, 4);
17672 md_number_to_chars ((char *) buf
, 0, 4);
17675 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17677 /* beql $0, $0, 2f */
17679 /* Compute the PC offset from the current instruction to
17680 the end of the variable frag. */
17681 /* How many bytes in instructions we've already emitted? */
17682 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
17683 /* How many bytes in instructions from here to the end? */
17684 i
= fragp
->fr_var
- i
;
17685 /* Convert to instruction count. */
17687 /* Don't decrement i, because we want to branch over the
17691 md_number_to_chars ((char *) buf
, insn
, 4);
17694 md_number_to_chars ((char *) buf
, 0, 4);
17699 if (mips_pic
== NO_PIC
)
17702 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17703 ? 0x0c000000 : 0x08000000);
17704 exp
.X_op
= O_symbol
;
17705 exp
.X_add_symbol
= fragp
->fr_symbol
;
17706 exp
.X_add_number
= fragp
->fr_offset
;
17708 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17709 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
17710 fixp
->fx_file
= fragp
->fr_file
;
17711 fixp
->fx_line
= fragp
->fr_line
;
17713 md_number_to_chars ((char *) buf
, insn
, 4);
17718 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17720 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17721 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17722 insn
|= at
<< OP_SH_RT
;
17723 exp
.X_op
= O_symbol
;
17724 exp
.X_add_symbol
= fragp
->fr_symbol
;
17725 exp
.X_add_number
= fragp
->fr_offset
;
17727 if (fragp
->fr_offset
)
17729 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17730 exp
.X_add_number
= 0;
17733 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17734 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
17735 fixp
->fx_file
= fragp
->fr_file
;
17736 fixp
->fx_line
= fragp
->fr_line
;
17738 md_number_to_chars ((char *) buf
, insn
, 4);
17741 if (mips_opts
.isa
== ISA_MIPS1
)
17744 md_number_to_chars ((char *) buf
, 0, 4);
17748 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17749 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17750 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17752 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
17753 4, &exp
, FALSE
, BFD_RELOC_LO16
);
17754 fixp
->fx_file
= fragp
->fr_file
;
17755 fixp
->fx_line
= fragp
->fr_line
;
17757 md_number_to_chars ((char *) buf
, insn
, 4);
17761 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17765 insn
|= at
<< OP_SH_RS
;
17767 md_number_to_chars ((char *) buf
, insn
, 4);
17772 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
17773 + fragp
->fr_fix
+ fragp
->fr_var
);
17775 fragp
->fr_fix
+= fragp
->fr_var
;
17780 /* Relax microMIPS branches. */
17781 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17783 bfd_byte
*buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
17784 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17785 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17786 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17787 bfd_boolean short_ds
;
17788 unsigned long insn
;
17792 exp
.X_op
= O_symbol
;
17793 exp
.X_add_symbol
= fragp
->fr_symbol
;
17794 exp
.X_add_number
= fragp
->fr_offset
;
17796 fragp
->fr_fix
+= fragp
->fr_var
;
17798 /* Handle 16-bit branches that fit or are forced to fit. */
17799 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17801 /* We generate a fixup instead of applying it right now,
17802 because if there is linker relaxation, we're going to
17803 need the relocations. */
17805 fixp
= fix_new_exp (fragp
,
17806 buf
- (bfd_byte
*) fragp
->fr_literal
,
17808 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
17809 else if (type
== 'E')
17810 fixp
= fix_new_exp (fragp
,
17811 buf
- (bfd_byte
*) fragp
->fr_literal
,
17813 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
17817 fixp
->fx_file
= fragp
->fr_file
;
17818 fixp
->fx_line
= fragp
->fr_line
;
17820 /* These relocations can have an addend that won't fit in
17822 fixp
->fx_no_overflow
= 1;
17827 /* Handle 32-bit branches that fit or are forced to fit. */
17828 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17829 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17831 /* We generate a fixup instead of applying it right now,
17832 because if there is linker relaxation, we're going to
17833 need the relocations. */
17834 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
17835 4, &exp
, TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17836 fixp
->fx_file
= fragp
->fr_file
;
17837 fixp
->fx_line
= fragp
->fr_line
;
17843 /* Relax 16-bit branches to 32-bit branches. */
17846 if (target_big_endian
)
17847 insn
= bfd_getb16 (buf
);
17849 insn
= bfd_getl16 (buf
);
17851 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
17852 insn
= 0x94000000; /* beq */
17853 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17855 unsigned long regno
;
17857 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
17858 regno
= micromips_to_32_reg_d_map
[regno
];
17859 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
17860 insn
|= regno
<< MICROMIPSOP_SH_RS
;
17865 /* Nothing else to do, just write it out. */
17866 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17867 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17869 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
17871 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
17874 gas_assert (buf
== ((bfd_byte
*) fragp
->fr_literal
17881 unsigned long next
;
17883 if (target_big_endian
)
17885 insn
= bfd_getb16 (buf
);
17886 next
= bfd_getb16 (buf
+ 2);
17890 insn
= bfd_getl16 (buf
);
17891 next
= bfd_getl16 (buf
+ 2);
17893 insn
= (insn
<< 16) | next
;
17896 /* Relax 32-bit branches to a sequence of instructions. */
17897 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17898 _("Relaxed out-of-range branch into a jump"));
17900 /* Set the short-delay-slot bit. */
17901 short_ds
= al
&& (insn
& 0x02000000) != 0;
17903 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
17907 /* Reverse the branch. */
17908 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
17909 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
17910 insn
^= 0x20000000;
17911 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
17912 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
17913 || (insn
& 0xffe00000) == 0x40800000 /* blez */
17914 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17915 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17916 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17917 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17918 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17919 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17920 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17921 insn
^= 0x00400000;
17922 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17923 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17924 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17925 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17926 insn
^= 0x00200000;
17932 /* Clear the and-link and short-delay-slot bits. */
17933 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17935 /* bltzal 0x40200000 bgezal 0x40600000 */
17936 /* bltzals 0x42200000 bgezals 0x42600000 */
17937 insn
&= ~0x02200000;
17940 /* Make a label at the end for use with the branch. */
17941 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17942 micromips_label_inc ();
17943 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
17945 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17949 fixp
= fix_new (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
17950 4, l
, 0, TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17951 fixp
->fx_file
= fragp
->fr_file
;
17952 fixp
->fx_line
= fragp
->fr_line
;
17954 /* Branch over the jump. */
17955 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
17957 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
17964 md_number_to_chars ((char *) buf
, insn
, 2);
17969 if (mips_pic
== NO_PIC
)
17971 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17973 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17974 insn
= al
? jal
: 0xd4000000;
17976 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
17977 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_JMP
);
17978 fixp
->fx_file
= fragp
->fr_file
;
17979 fixp
->fx_line
= fragp
->fr_line
;
17981 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
17983 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
17990 md_number_to_chars ((char *) buf
, insn
, 2);
17996 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17997 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17998 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18000 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18001 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18002 insn
|= at
<< MICROMIPSOP_SH_RT
;
18004 if (exp
.X_add_number
)
18006 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18007 exp
.X_add_number
= 0;
18010 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18011 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18012 fixp
->fx_file
= fragp
->fr_file
;
18013 fixp
->fx_line
= fragp
->fr_line
;
18015 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18017 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18020 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18021 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18022 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18024 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*) fragp
->fr_literal
,
18025 4, &exp
, FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18026 fixp
->fx_file
= fragp
->fr_file
;
18027 fixp
->fx_line
= fragp
->fr_line
;
18029 md_number_to_chars ((char *) buf
, insn
>> 16, 2);
18031 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18034 /* jr/jrc/jalr/jalrs $at */
18035 insn
= al
? jalr
: jr
;
18036 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18038 md_number_to_chars ((char *) buf
, insn
& 0xffff, 2);
18042 gas_assert (buf
== (bfd_byte
*) fragp
->fr_literal
+ fragp
->fr_fix
);
18046 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18049 const struct mips16_immed_operand
*op
;
18050 bfd_boolean small
, ext
;
18053 unsigned long insn
;
18054 bfd_boolean use_extend
;
18055 unsigned short extend
;
18057 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18058 op
= mips16_immed_operands
;
18059 while (op
->type
!= type
)
18062 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18073 val
= resolve_symbol_value (fragp
->fr_symbol
);
18078 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18080 /* The rules for the base address of a PC relative reloc are
18081 complicated; see mips16_extended_frag. */
18082 if (type
== 'p' || type
== 'q')
18087 /* Ignore the low bit in the target, since it will be
18088 set for a text label. */
18089 if ((val
& 1) != 0)
18092 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18094 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18097 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18100 /* Make sure the section winds up with the alignment we have
18103 record_alignment (asec
, op
->shift
);
18107 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18108 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18109 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18110 _("extended instruction in delay slot"));
18112 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
18114 if (target_big_endian
)
18115 insn
= bfd_getb16 (buf
);
18117 insn
= bfd_getl16 (buf
);
18119 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
18120 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
18121 small
, ext
, &insn
, &use_extend
, &extend
);
18125 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
18126 fragp
->fr_fix
+= 2;
18130 md_number_to_chars ((char *) buf
, insn
, 2);
18131 fragp
->fr_fix
+= 2;
18136 relax_substateT subtype
= fragp
->fr_subtype
;
18137 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18138 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18142 first
= RELAX_FIRST (subtype
);
18143 second
= RELAX_SECOND (subtype
);
18144 fixp
= (fixS
*) fragp
->fr_opcode
;
18146 /* If the delay slot chosen does not match the size of the instruction,
18147 then emit a warning. */
18148 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18149 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18154 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18155 | RELAX_DELAY_SLOT_SIZE_FIRST
18156 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18157 msg
= macro_warning (s
);
18159 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
18163 /* Possibly emit a warning if we've chosen the longer option. */
18164 if (use_second
== second_longer
)
18170 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18171 msg
= macro_warning (s
);
18173 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
18177 /* Go through all the fixups for the first sequence. Disable them
18178 (by marking them as done) if we're going to use the second
18179 sequence instead. */
18181 && fixp
->fx_frag
== fragp
18182 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18184 if (subtype
& RELAX_USE_SECOND
)
18186 fixp
= fixp
->fx_next
;
18189 /* Go through the fixups for the second sequence. Disable them if
18190 we're going to use the first sequence, otherwise adjust their
18191 addresses to account for the relaxation. */
18192 while (fixp
&& fixp
->fx_frag
== fragp
)
18194 if (subtype
& RELAX_USE_SECOND
)
18195 fixp
->fx_where
-= first
;
18198 fixp
= fixp
->fx_next
;
18201 /* Now modify the frag contents. */
18202 if (subtype
& RELAX_USE_SECOND
)
18206 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18207 memmove (start
, start
+ first
, second
);
18208 fragp
->fr_fix
-= first
;
18211 fragp
->fr_fix
-= second
;
18217 /* This function is called after the relocs have been generated.
18218 We've been storing mips16 text labels as odd. Here we convert them
18219 back to even for the convenience of the debugger. */
18222 mips_frob_file_after_relocs (void)
18225 unsigned int count
, i
;
18230 syms
= bfd_get_outsymbols (stdoutput
);
18231 count
= bfd_get_symcount (stdoutput
);
18232 for (i
= 0; i
< count
; i
++, syms
++)
18233 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18234 && ((*syms
)->value
& 1) != 0)
18236 (*syms
)->value
&= ~1;
18237 /* If the symbol has an odd size, it was probably computed
18238 incorrectly, so adjust that as well. */
18239 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18240 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18246 /* This function is called whenever a label is defined, including fake
18247 labels instantiated off the dot special symbol. It is used when
18248 handling branch delays; if a branch has a label, we assume we cannot
18249 move it. This also bumps the value of the symbol by 1 in compressed
18253 mips_record_label (symbolS
*sym
)
18255 segment_info_type
*si
= seg_info (now_seg
);
18256 struct insn_label_list
*l
;
18258 if (free_insn_labels
== NULL
)
18259 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18262 l
= free_insn_labels
;
18263 free_insn_labels
= l
->next
;
18267 l
->next
= si
->label_list
;
18268 si
->label_list
= l
;
18271 /* This function is called as tc_frob_label() whenever a label is defined
18272 and adds a DWARF-2 record we only want for true labels. */
18275 mips_define_label (symbolS
*sym
)
18277 mips_record_label (sym
);
18279 dwarf2_emit_label (sym
);
18283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18285 /* Some special processing for a MIPS ELF file. */
18288 mips_elf_final_processing (void)
18290 /* Write out the register information. */
18291 if (mips_abi
!= N64_ABI
)
18295 s
.ri_gprmask
= mips_gprmask
;
18296 s
.ri_cprmask
[0] = mips_cprmask
[0];
18297 s
.ri_cprmask
[1] = mips_cprmask
[1];
18298 s
.ri_cprmask
[2] = mips_cprmask
[2];
18299 s
.ri_cprmask
[3] = mips_cprmask
[3];
18300 /* The gp_value field is set by the MIPS ELF backend. */
18302 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18303 ((Elf32_External_RegInfo
*)
18304 mips_regmask_frag
));
18308 Elf64_Internal_RegInfo s
;
18310 s
.ri_gprmask
= mips_gprmask
;
18312 s
.ri_cprmask
[0] = mips_cprmask
[0];
18313 s
.ri_cprmask
[1] = mips_cprmask
[1];
18314 s
.ri_cprmask
[2] = mips_cprmask
[2];
18315 s
.ri_cprmask
[3] = mips_cprmask
[3];
18316 /* The gp_value field is set by the MIPS ELF backend. */
18318 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18319 ((Elf64_External_RegInfo
*)
18320 mips_regmask_frag
));
18323 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18324 sort of BFD interface for this. */
18325 if (mips_any_noreorder
)
18326 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18327 if (mips_pic
!= NO_PIC
)
18329 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18330 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18333 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18335 /* Set MIPS ELF flags for ASEs. */
18336 /* We may need to define a new flag for DSP ASE, and set this flag when
18337 file_ase_dsp is true. */
18338 /* Same for DSP R2. */
18339 /* We may need to define a new flag for MT ASE, and set this flag when
18340 file_ase_mt is true. */
18341 if (file_ase_mips16
)
18342 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18343 if (file_ase_micromips
)
18344 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18345 #if 0 /* XXX FIXME */
18346 if (file_ase_mips3d
)
18347 elf_elfheader (stdoutput
)->e_flags
|= ???;
18350 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18352 /* Set the MIPS ELF ABI flags. */
18353 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18354 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18355 else if (mips_abi
== O64_ABI
)
18356 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18357 else if (mips_abi
== EABI_ABI
)
18359 if (!file_mips_gp32
)
18360 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18362 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18364 else if (mips_abi
== N32_ABI
)
18365 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18367 /* Nothing to do for N64_ABI. */
18369 if (mips_32bitmode
)
18370 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18372 #if 0 /* XXX FIXME */
18373 /* 32 bit code with 64 bit FP registers. */
18374 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18375 elf_elfheader (stdoutput
)->e_flags
|= ???;
18379 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18381 typedef struct proc
{
18383 symbolS
*func_end_sym
;
18384 unsigned long reg_mask
;
18385 unsigned long reg_offset
;
18386 unsigned long fpreg_mask
;
18387 unsigned long fpreg_offset
;
18388 unsigned long frame_offset
;
18389 unsigned long frame_reg
;
18390 unsigned long pc_reg
;
18393 static procS cur_proc
;
18394 static procS
*cur_proc_ptr
;
18395 static int numprocs
;
18397 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18398 as "2", and a normal nop as "0". */
18400 #define NOP_OPCODE_MIPS 0
18401 #define NOP_OPCODE_MIPS16 1
18402 #define NOP_OPCODE_MICROMIPS 2
18405 mips_nop_opcode (void)
18407 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18408 return NOP_OPCODE_MICROMIPS
;
18409 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18410 return NOP_OPCODE_MIPS16
;
18412 return NOP_OPCODE_MIPS
;
18415 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18416 32-bit microMIPS NOPs here (if applicable). */
18419 mips_handle_align (fragS
*fragp
)
18423 int bytes
, size
, excess
;
18426 if (fragp
->fr_type
!= rs_align_code
)
18429 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18431 switch (nop_opcode
)
18433 case NOP_OPCODE_MICROMIPS
:
18434 opcode
= micromips_nop32_insn
.insn_opcode
;
18437 case NOP_OPCODE_MIPS16
:
18438 opcode
= mips16_nop_insn
.insn_opcode
;
18441 case NOP_OPCODE_MIPS
:
18443 opcode
= nop_insn
.insn_opcode
;
18448 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18449 excess
= bytes
% size
;
18451 /* Handle the leading part if we're not inserting a whole number of
18452 instructions, and make it the end of the fixed part of the frag.
18453 Try to fit in a short microMIPS NOP if applicable and possible,
18454 and use zeroes otherwise. */
18455 gas_assert (excess
< 4);
18456 fragp
->fr_fix
+= excess
;
18461 /* Fall through. */
18463 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18465 md_number_to_chars (p
, micromips_nop16_insn
.insn_opcode
, 2);
18470 /* Fall through. */
18473 /* Fall through. */
18478 md_number_to_chars (p
, opcode
, size
);
18479 fragp
->fr_var
= size
;
18483 md_obj_begin (void)
18490 /* Check for premature end, nesting errors, etc. */
18492 as_warn (_("missing .end at end of assembly"));
18501 if (*input_line_pointer
== '-')
18503 ++input_line_pointer
;
18506 if (!ISDIGIT (*input_line_pointer
))
18507 as_bad (_("expected simple number"));
18508 if (input_line_pointer
[0] == '0')
18510 if (input_line_pointer
[1] == 'x')
18512 input_line_pointer
+= 2;
18513 while (ISXDIGIT (*input_line_pointer
))
18516 val
|= hex_value (*input_line_pointer
++);
18518 return negative
? -val
: val
;
18522 ++input_line_pointer
;
18523 while (ISDIGIT (*input_line_pointer
))
18526 val
|= *input_line_pointer
++ - '0';
18528 return negative
? -val
: val
;
18531 if (!ISDIGIT (*input_line_pointer
))
18533 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18534 *input_line_pointer
, *input_line_pointer
);
18535 as_warn (_("invalid number"));
18538 while (ISDIGIT (*input_line_pointer
))
18541 val
+= *input_line_pointer
++ - '0';
18543 return negative
? -val
: val
;
18546 /* The .file directive; just like the usual .file directive, but there
18547 is an initial number which is the ECOFF file index. In the non-ECOFF
18548 case .file implies DWARF-2. */
18551 s_mips_file (int x ATTRIBUTE_UNUSED
)
18553 static int first_file_directive
= 0;
18555 if (ECOFF_DEBUGGING
)
18564 filename
= dwarf2_directive_file (0);
18566 /* Versions of GCC up to 3.1 start files with a ".file"
18567 directive even for stabs output. Make sure that this
18568 ".file" is handled. Note that you need a version of GCC
18569 after 3.1 in order to support DWARF-2 on MIPS. */
18570 if (filename
!= NULL
&& ! first_file_directive
)
18572 (void) new_logical_line (filename
, -1);
18573 s_app_file_string (filename
, 0);
18575 first_file_directive
= 1;
18579 /* The .loc directive, implying DWARF-2. */
18582 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18584 if (!ECOFF_DEBUGGING
)
18585 dwarf2_directive_loc (0);
18588 /* The .end directive. */
18591 s_mips_end (int x ATTRIBUTE_UNUSED
)
18595 /* Following functions need their own .frame and .cprestore directives. */
18596 mips_frame_reg_valid
= 0;
18597 mips_cprestore_valid
= 0;
18599 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18602 demand_empty_rest_of_line ();
18607 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18608 as_warn (_(".end not in text section"));
18612 as_warn (_(".end directive without a preceding .ent directive."));
18613 demand_empty_rest_of_line ();
18619 gas_assert (S_GET_NAME (p
));
18620 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18621 as_warn (_(".end symbol does not match .ent symbol."));
18623 if (debug_type
== DEBUG_STABS
)
18624 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18628 as_warn (_(".end directive missing or unknown symbol"));
18631 /* Create an expression to calculate the size of the function. */
18632 if (p
&& cur_proc_ptr
)
18634 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18635 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18638 exp
->X_op
= O_subtract
;
18639 exp
->X_add_symbol
= symbol_temp_new_now ();
18640 exp
->X_op_symbol
= p
;
18641 exp
->X_add_number
= 0;
18643 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18646 /* Generate a .pdr section. */
18647 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
18649 segT saved_seg
= now_seg
;
18650 subsegT saved_subseg
= now_subseg
;
18654 #ifdef md_flush_pending_output
18655 md_flush_pending_output ();
18658 gas_assert (pdr_seg
);
18659 subseg_set (pdr_seg
, 0);
18661 /* Write the symbol. */
18662 exp
.X_op
= O_symbol
;
18663 exp
.X_add_symbol
= p
;
18664 exp
.X_add_number
= 0;
18665 emit_expr (&exp
, 4);
18667 fragp
= frag_more (7 * 4);
18669 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18670 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18671 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18672 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18673 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18674 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18675 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18677 subseg_set (saved_seg
, saved_subseg
);
18679 #endif /* OBJ_ELF */
18681 cur_proc_ptr
= NULL
;
18684 /* The .aent and .ent directives. */
18687 s_mips_ent (int aent
)
18691 symbolP
= get_symbol ();
18692 if (*input_line_pointer
== ',')
18693 ++input_line_pointer
;
18694 SKIP_WHITESPACE ();
18695 if (ISDIGIT (*input_line_pointer
)
18696 || *input_line_pointer
== '-')
18699 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18700 as_warn (_(".ent or .aent not in text section."));
18702 if (!aent
&& cur_proc_ptr
)
18703 as_warn (_("missing .end"));
18707 /* This function needs its own .frame and .cprestore directives. */
18708 mips_frame_reg_valid
= 0;
18709 mips_cprestore_valid
= 0;
18711 cur_proc_ptr
= &cur_proc
;
18712 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18714 cur_proc_ptr
->func_sym
= symbolP
;
18718 if (debug_type
== DEBUG_STABS
)
18719 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18720 S_GET_NAME (symbolP
));
18723 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18725 demand_empty_rest_of_line ();
18728 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18729 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18730 s_mips_frame is used so that we can set the PDR information correctly.
18731 We can't use the ecoff routines because they make reference to the ecoff
18732 symbol table (in the mdebug section). */
18735 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18738 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18742 if (cur_proc_ptr
== (procS
*) NULL
)
18744 as_warn (_(".frame outside of .ent"));
18745 demand_empty_rest_of_line ();
18749 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18751 SKIP_WHITESPACE ();
18752 if (*input_line_pointer
++ != ','
18753 || get_absolute_expression_and_terminator (&val
) != ',')
18755 as_warn (_("Bad .frame directive"));
18756 --input_line_pointer
;
18757 demand_empty_rest_of_line ();
18761 cur_proc_ptr
->frame_offset
= val
;
18762 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18764 demand_empty_rest_of_line ();
18767 #endif /* OBJ_ELF */
18771 /* The .fmask and .mask directives. If the mdebug section is present
18772 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18773 embedded targets, s_mips_mask is used so that we can set the PDR
18774 information correctly. We can't use the ecoff routines because they
18775 make reference to the ecoff symbol table (in the mdebug section). */
18778 s_mips_mask (int reg_type
)
18781 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18785 if (cur_proc_ptr
== (procS
*) NULL
)
18787 as_warn (_(".mask/.fmask outside of .ent"));
18788 demand_empty_rest_of_line ();
18792 if (get_absolute_expression_and_terminator (&mask
) != ',')
18794 as_warn (_("Bad .mask/.fmask directive"));
18795 --input_line_pointer
;
18796 demand_empty_rest_of_line ();
18800 off
= get_absolute_expression ();
18802 if (reg_type
== 'F')
18804 cur_proc_ptr
->fpreg_mask
= mask
;
18805 cur_proc_ptr
->fpreg_offset
= off
;
18809 cur_proc_ptr
->reg_mask
= mask
;
18810 cur_proc_ptr
->reg_offset
= off
;
18813 demand_empty_rest_of_line ();
18816 #endif /* OBJ_ELF */
18817 s_ignore (reg_type
);
18820 /* A table describing all the processors gas knows about. Names are
18821 matched in the order listed.
18823 To ease comparison, please keep this table in the same order as
18824 gcc's mips_cpu_info_table[]. */
18825 static const struct mips_cpu_info mips_cpu_info_table
[] =
18827 /* Entries for generic ISAs */
18828 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
18829 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
18830 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
18831 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
18832 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
18833 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
18834 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18835 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
18836 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
18839 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
18840 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
18841 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
18844 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
18847 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
18848 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
18849 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
18850 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
18851 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
18852 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
18853 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
18854 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
18855 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
18856 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
18857 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
18858 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
18859 /* ST Microelectronics Loongson 2E and 2F cores */
18860 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
18861 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
18864 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
18865 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
18866 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
18867 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
18868 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
18869 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
18870 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
18871 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
18872 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
18873 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
18874 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
18875 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
18876 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
18877 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
18878 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
18881 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
18882 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
18883 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
18884 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
18886 /* MIPS 32 Release 2 */
18887 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18888 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18889 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18890 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18891 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18892 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18893 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18894 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18895 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18896 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18897 /* Deprecated forms of the above. */
18898 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18899 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18900 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18901 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18902 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18903 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18904 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18905 /* Deprecated forms of the above. */
18906 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18907 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18908 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18909 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18910 ISA_MIPS32R2
, CPU_MIPS32R2
},
18911 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18912 ISA_MIPS32R2
, CPU_MIPS32R2
},
18913 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18914 ISA_MIPS32R2
, CPU_MIPS32R2
},
18915 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18916 ISA_MIPS32R2
, CPU_MIPS32R2
},
18917 /* Deprecated forms of the above. */
18918 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18919 ISA_MIPS32R2
, CPU_MIPS32R2
},
18920 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18921 ISA_MIPS32R2
, CPU_MIPS32R2
},
18922 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18923 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
18924 ISA_MIPS32R2
, CPU_MIPS32R2
},
18925 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
18926 ISA_MIPS32R2
, CPU_MIPS32R2
},
18927 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
18928 ISA_MIPS32R2
, CPU_MIPS32R2
},
18929 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
18930 ISA_MIPS32R2
, CPU_MIPS32R2
},
18931 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
18932 ISA_MIPS32R2
, CPU_MIPS32R2
},
18933 /* Deprecated forms of the above. */
18934 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
18935 ISA_MIPS32R2
, CPU_MIPS32R2
},
18936 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
18937 ISA_MIPS32R2
, CPU_MIPS32R2
},
18938 /* 1004K cores are multiprocessor versions of the 34K. */
18939 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18940 ISA_MIPS32R2
, CPU_MIPS32R2
},
18941 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18942 ISA_MIPS32R2
, CPU_MIPS32R2
},
18943 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18944 ISA_MIPS32R2
, CPU_MIPS32R2
},
18945 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
18946 ISA_MIPS32R2
, CPU_MIPS32R2
},
18949 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
18950 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
18951 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18952 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18954 /* Broadcom SB-1 CPU core */
18955 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
18956 ISA_MIPS64
, CPU_SB1
},
18957 /* Broadcom SB-1A CPU core */
18958 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
18959 ISA_MIPS64
, CPU_SB1
},
18961 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
18963 /* MIPS 64 Release 2 */
18965 /* Cavium Networks Octeon CPU core */
18966 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
18969 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
18976 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18977 with a final "000" replaced by "k". Ignore case.
18979 Note: this function is shared between GCC and GAS. */
18982 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18984 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18985 given
++, canonical
++;
18987 return ((*given
== 0 && *canonical
== 0)
18988 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18992 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18993 CPU name. We've traditionally allowed a lot of variation here.
18995 Note: this function is shared between GCC and GAS. */
18998 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19000 /* First see if the name matches exactly, or with a final "000"
19001 turned into "k". */
19002 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19005 /* If not, try comparing based on numerical designation alone.
19006 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19007 if (TOLOWER (*given
) == 'r')
19009 if (!ISDIGIT (*given
))
19012 /* Skip over some well-known prefixes in the canonical name,
19013 hoping to find a number there too. */
19014 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19016 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19018 else if (TOLOWER (canonical
[0]) == 'r')
19021 return mips_strict_matching_cpu_name_p (canonical
, given
);
19025 /* Parse an option that takes the name of a processor as its argument.
19026 OPTION is the name of the option and CPU_STRING is the argument.
19027 Return the corresponding processor enumeration if the CPU_STRING is
19028 recognized, otherwise report an error and return null.
19030 A similar function exists in GCC. */
19032 static const struct mips_cpu_info
*
19033 mips_parse_cpu (const char *option
, const char *cpu_string
)
19035 const struct mips_cpu_info
*p
;
19037 /* 'from-abi' selects the most compatible architecture for the given
19038 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19039 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19040 version. Look first at the -mgp options, if given, otherwise base
19041 the choice on MIPS_DEFAULT_64BIT.
19043 Treat NO_ABI like the EABIs. One reason to do this is that the
19044 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19045 architecture. This code picks MIPS I for 'mips' and MIPS III for
19046 'mips64', just as we did in the days before 'from-abi'. */
19047 if (strcasecmp (cpu_string
, "from-abi") == 0)
19049 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19050 return mips_cpu_info_from_isa (ISA_MIPS1
);
19052 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19053 return mips_cpu_info_from_isa (ISA_MIPS3
);
19055 if (file_mips_gp32
>= 0)
19056 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19058 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19063 /* 'default' has traditionally been a no-op. Probably not very useful. */
19064 if (strcasecmp (cpu_string
, "default") == 0)
19067 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19068 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19071 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19075 /* Return the canonical processor information for ISA (a member of the
19076 ISA_MIPS* enumeration). */
19078 static const struct mips_cpu_info
*
19079 mips_cpu_info_from_isa (int isa
)
19083 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19084 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19085 && isa
== mips_cpu_info_table
[i
].isa
)
19086 return (&mips_cpu_info_table
[i
]);
19091 static const struct mips_cpu_info
*
19092 mips_cpu_info_from_arch (int arch
)
19096 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19097 if (arch
== mips_cpu_info_table
[i
].cpu
)
19098 return (&mips_cpu_info_table
[i
]);
19104 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19108 fprintf (stream
, "%24s", "");
19113 fprintf (stream
, ", ");
19117 if (*col_p
+ strlen (string
) > 72)
19119 fprintf (stream
, "\n%24s", "");
19123 fprintf (stream
, "%s", string
);
19124 *col_p
+= strlen (string
);
19130 md_show_usage (FILE *stream
)
19135 fprintf (stream
, _("\
19137 -EB generate big endian output\n\
19138 -EL generate little endian output\n\
19139 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19140 -G NUM allow referencing objects up to NUM bytes\n\
19141 implicitly with the gp register [default 8]\n"));
19142 fprintf (stream
, _("\
19143 -mips1 generate MIPS ISA I instructions\n\
19144 -mips2 generate MIPS ISA II instructions\n\
19145 -mips3 generate MIPS ISA III instructions\n\
19146 -mips4 generate MIPS ISA IV instructions\n\
19147 -mips5 generate MIPS ISA V instructions\n\
19148 -mips32 generate MIPS32 ISA instructions\n\
19149 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19150 -mips64 generate MIPS64 ISA instructions\n\
19151 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19152 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19156 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19157 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19158 show (stream
, "from-abi", &column
, &first
);
19159 fputc ('\n', stream
);
19161 fprintf (stream
, _("\
19162 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19163 -no-mCPU don't generate code specific to CPU.\n\
19164 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19168 show (stream
, "3900", &column
, &first
);
19169 show (stream
, "4010", &column
, &first
);
19170 show (stream
, "4100", &column
, &first
);
19171 show (stream
, "4650", &column
, &first
);
19172 fputc ('\n', stream
);
19174 fprintf (stream
, _("\
19175 -mips16 generate mips16 instructions\n\
19176 -no-mips16 do not generate mips16 instructions\n"));
19177 fprintf (stream
, _("\
19178 -mmicromips generate microMIPS instructions\n\
19179 -mno-micromips do not generate microMIPS instructions\n"));
19180 fprintf (stream
, _("\
19181 -msmartmips generate smartmips instructions\n\
19182 -mno-smartmips do not generate smartmips instructions\n"));
19183 fprintf (stream
, _("\
19184 -mdsp generate DSP instructions\n\
19185 -mno-dsp do not generate DSP instructions\n"));
19186 fprintf (stream
, _("\
19187 -mdspr2 generate DSP R2 instructions\n\
19188 -mno-dspr2 do not generate DSP R2 instructions\n"));
19189 fprintf (stream
, _("\
19190 -mmt generate MT instructions\n\
19191 -mno-mt do not generate MT instructions\n"));
19192 fprintf (stream
, _("\
19193 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19194 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19195 -mfix-vr4120 work around certain VR4120 errata\n\
19196 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19197 -mfix-24k insert a nop after ERET and DERET instructions\n\
19198 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19199 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19200 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19201 -msym32 assume all symbols have 32-bit values\n\
19202 -O0 remove unneeded NOPs, do not swap branches\n\
19203 -O remove unneeded NOPs and swap branches\n\
19204 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19205 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19206 fprintf (stream
, _("\
19207 -mhard-float allow floating-point instructions\n\
19208 -msoft-float do not allow floating-point instructions\n\
19209 -msingle-float only allow 32-bit floating-point operations\n\
19210 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19211 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19214 fprintf (stream
, _("\
19215 -KPIC, -call_shared generate SVR4 position independent code\n\
19216 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19217 -mvxworks-pic generate VxWorks position independent code\n\
19218 -non_shared do not generate code that can operate with DSOs\n\
19219 -xgot assume a 32 bit GOT\n\
19220 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19221 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19222 position dependent (non shared) code\n\
19223 -mabi=ABI create ABI conformant object file for:\n"));
19227 show (stream
, "32", &column
, &first
);
19228 show (stream
, "o64", &column
, &first
);
19229 show (stream
, "n32", &column
, &first
);
19230 show (stream
, "64", &column
, &first
);
19231 show (stream
, "eabi", &column
, &first
);
19233 fputc ('\n', stream
);
19235 fprintf (stream
, _("\
19236 -32 create o32 ABI object file (default)\n\
19237 -n32 create n32 ABI object file\n\
19238 -64 create 64 ABI object file\n"));
19244 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19246 if (HAVE_64BIT_SYMBOLS
)
19247 return dwarf2_format_64bit_irix
;
19249 return dwarf2_format_32bit
;
19254 mips_dwarf2_addr_size (void)
19256 if (HAVE_64BIT_OBJECTS
)
19262 /* Standard calling conventions leave the CFA at SP on entry. */
19264 mips_cfi_frame_initial_instructions (void)
19266 cfi_add_CFA_def_cfa_register (SP
);
19270 tc_mips_regname_to_dw2regnum (char *regname
)
19272 unsigned int regnum
= -1;
19275 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))