1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* Whether the 4650 instructions (mad/madu) are permitted. */
198 static int mips_4650
= -1;
200 /* Whether the 4010 instructions are permitted. */
201 static int mips_4010
= -1;
203 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
204 static int mips_4100
= -1;
206 /* start-sanitize-vr4320 */
207 /* Whether NEC vr4320 instructions are permitted. */
208 static int mips_4320
= -1;
210 /* end-sanitize-vr4320 */
211 /* start-sanitize-vr5400 */
212 /* Whether NEC vr5400 instructions are permitted. */
213 static int mips_5400
= -1;
215 /* end-sanitize-vr5400 */
216 /* start-sanitize-r5900 */
217 /* Whether Toshiba r5900 instructions are permitted. */
218 static int mips_5900
= -1;
220 /* end-sanitize-r5900 */
221 /* Whether Toshiba r3900 instructions are permitted. */
222 static int mips_3900
= -1;
224 /* start-sanitize-tx49 */
225 /* Whether Toshiba r4900 instructions are permitted. */
226 static int mips_4900
= -1;
228 /* end-sanitize-tx49 */
229 /* start-sanitize-tx19 */
230 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
231 The tx19 related options and configuration bits are handled by
233 /* end-sanitize-tx19 */
235 /* Whether the processor uses hardware interlocks to protect
236 reads from the HI and LO registers, and thus does not
237 require nops to be inserted. */
238 #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \
239 /* start-sanitize-tx49 */ \
240 || mips_cpu == 4900 || mips_4900 \
241 /* end-sanitize-tx49 */ \
242 /* start-sanitize-vr4320 */ \
243 || mips_cpu == 4320 \
244 /* end-sanitize-vr4320 */ \
245 /* start-sanitize-vr5400 */ \
246 || mips_cpu == 5400 \
247 /* end-sanitize-vr5400 */ \
250 /* Whether the processor uses hardware interlocks to protect reads
251 from the GPRs, and thus does not require nops to be inserted. */
252 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
253 /* start-sanitize-vr5400 */
254 #undef gpr_interlocks
255 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400)
256 /* end-sanitize-vr5400 */
259 /* As with other "interlocks" this is used by hardware that has FP
260 (co-processor) interlocks. */
261 /* Itbl support may require additional care here. */
262 #define cop_interlocks (mips_cpu == 4300 \
263 /* start-sanitize-vr4320 */ \
264 || mips_cpu == 4320 \
265 /* end-sanitize-vr4320 */ \
266 /* start-sanitize-vr5400 */ \
267 || mips_cpu == 5400 \
268 /* end-sanitize-vr5400 */ \
271 /* MIPS PIC level. */
275 /* Do not generate PIC code. */
278 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
279 not sure what it is supposed to do. */
282 /* Generate PIC code as in the SVR4 MIPS ABI. */
285 /* Generate PIC code without using a global offset table: the data
286 segment has a maximum size of 64K, all data references are off
287 the $gp register, and all text references are PC relative. This
288 is used on some embedded systems. */
292 static enum mips_pic_level mips_pic
;
294 /* 1 if we should generate 32 bit offsets from the GP register in
295 SVR4_PIC mode. Currently has no meaning in other modes. */
296 static int mips_big_got
;
298 /* 1 if trap instructions should used for overflow rather than break
300 static int mips_trap
;
302 /* Non-zero if any .set noreorder directives were used. */
304 static int mips_any_noreorder
;
306 /* The size of the small data section. */
307 static int g_switch_value
= 8;
308 /* Whether the -G option was used. */
309 static int g_switch_seen
= 0;
314 /* If we can determine in advance that GP optimization won't be
315 possible, we can skip the relaxation stuff that tries to produce
316 GP-relative references. This makes delay slot optimization work
319 This function can only provide a guess, but it seems to work for
320 gcc output. If it guesses wrong, the only loss should be in
321 efficiency; it shouldn't introduce any bugs.
323 I don't know if a fix is needed for the SVR4_PIC mode. I've only
324 fixed it for the non-PIC mode. KR 95/04/07 */
325 static int nopic_need_relax
PARAMS ((symbolS
*, int));
327 /* handle of the OPCODE hash table */
328 static struct hash_control
*op_hash
= NULL
;
330 /* The opcode hash table we use for the mips16. */
331 static struct hash_control
*mips16_op_hash
= NULL
;
333 /* This array holds the chars that always start a comment. If the
334 pre-processor is disabled, these aren't very useful */
335 const char comment_chars
[] = "#";
337 /* This array holds the chars that only start a comment at the beginning of
338 a line. If the line seems to have the form '# 123 filename'
339 .line and .file directives will appear in the pre-processed output */
340 /* Note that input_file.c hand checks for '#' at the beginning of the
341 first line of the input file. This is because the compiler outputs
342 #NO_APP at the beginning of its output. */
343 /* Also note that C style comments are always supported. */
344 const char line_comment_chars
[] = "#";
346 /* This array holds machine specific line separator characters. */
347 const char line_separator_chars
[] = "";
349 /* Chars that can be used to separate mant from exp in floating point nums */
350 const char EXP_CHARS
[] = "eE";
352 /* Chars that mean this number is a floating point constant */
355 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
357 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
358 changed in read.c . Ideally it shouldn't have to know about it at all,
359 but nothing is ideal around here.
362 static char *insn_error
;
364 static int auto_align
= 1;
366 /* When outputting SVR4 PIC code, the assembler needs to know the
367 offset in the stack frame from which to restore the $gp register.
368 This is set by the .cprestore pseudo-op, and saved in this
370 static offsetT mips_cprestore_offset
= -1;
372 /* This is the register which holds the stack frame, as set by the
373 .frame pseudo-op. This is needed to implement .cprestore. */
374 static int mips_frame_reg
= SP
;
376 /* To output NOP instructions correctly, we need to keep information
377 about the previous two instructions. */
379 /* Whether we are optimizing. The default value of 2 means to remove
380 unneeded NOPs and swap branch instructions when possible. A value
381 of 1 means to not swap branches. A value of 0 means to always
383 static int mips_optimize
= 2;
385 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
386 equivalent to seeing no -g option at all. */
387 static int mips_debug
= 0;
389 /* The previous instruction. */
390 static struct mips_cl_insn prev_insn
;
392 /* The instruction before prev_insn. */
393 static struct mips_cl_insn prev_prev_insn
;
395 /* If we don't want information for prev_insn or prev_prev_insn, we
396 point the insn_mo field at this dummy integer. */
397 static const struct mips_opcode dummy_opcode
= { 0 };
399 /* Non-zero if prev_insn is valid. */
400 static int prev_insn_valid
;
402 /* The frag for the previous instruction. */
403 static struct frag
*prev_insn_frag
;
405 /* The offset into prev_insn_frag for the previous instruction. */
406 static long prev_insn_where
;
408 /* The reloc type for the previous instruction, if any. */
409 static bfd_reloc_code_real_type prev_insn_reloc_type
;
411 /* The reloc for the previous instruction, if any. */
412 static fixS
*prev_insn_fixp
;
414 /* Non-zero if the previous instruction was in a delay slot. */
415 static int prev_insn_is_delay_slot
;
417 /* Non-zero if the previous instruction was in a .set noreorder. */
418 static int prev_insn_unreordered
;
420 /* Non-zero if the previous instruction uses an extend opcode (if
422 static int prev_insn_extended
;
424 /* Non-zero if the previous previous instruction was in a .set
426 static int prev_prev_insn_unreordered
;
428 /* If this is set, it points to a frag holding nop instructions which
429 were inserted before the start of a noreorder section. If those
430 nops turn out to be unnecessary, the size of the frag can be
432 static fragS
*prev_nop_frag
;
434 /* The number of nop instructions we created in prev_nop_frag. */
435 static int prev_nop_frag_holds
;
437 /* The number of nop instructions that we know we need in
439 static int prev_nop_frag_required
;
441 /* The number of instructions we've seen since prev_nop_frag. */
442 static int prev_nop_frag_since
;
444 /* For ECOFF and ELF, relocations against symbols are done in two
445 parts, with a HI relocation and a LO relocation. Each relocation
446 has only 16 bits of space to store an addend. This means that in
447 order for the linker to handle carries correctly, it must be able
448 to locate both the HI and the LO relocation. This means that the
449 relocations must appear in order in the relocation table.
451 In order to implement this, we keep track of each unmatched HI
452 relocation. We then sort them so that they immediately precede the
453 corresponding LO relocation. */
458 struct mips_hi_fixup
*next
;
461 /* The section this fixup is in. */
465 /* The list of unmatched HI relocs. */
467 static struct mips_hi_fixup
*mips_hi_fixup_list
;
469 /* Map normal MIPS register numbers to mips16 register numbers. */
471 #define X ILLEGAL_REG
472 static const int mips32_to_16_reg_map
[] =
474 X
, X
, 2, 3, 4, 5, 6, 7,
475 X
, X
, X
, X
, X
, X
, X
, X
,
476 0, 1, X
, X
, X
, X
, X
, X
,
477 X
, X
, X
, X
, X
, X
, X
, X
481 /* Map mips16 register numbers to normal MIPS register numbers. */
483 static const int mips16_to_32_reg_map
[] =
485 16, 17, 2, 3, 4, 5, 6, 7
488 /* Since the MIPS does not have multiple forms of PC relative
489 instructions, we do not have to do relaxing as is done on other
490 platforms. However, we do have to handle GP relative addressing
491 correctly, which turns out to be a similar problem.
493 Every macro that refers to a symbol can occur in (at least) two
494 forms, one with GP relative addressing and one without. For
495 example, loading a global variable into a register generally uses
496 a macro instruction like this:
498 If i can be addressed off the GP register (this is true if it is in
499 the .sbss or .sdata section, or if it is known to be smaller than
500 the -G argument) this will generate the following instruction:
502 This instruction will use a GPREL reloc. If i can not be addressed
503 off the GP register, the following instruction sequence will be used:
506 In this case the first instruction will have a HI16 reloc, and the
507 second reloc will have a LO16 reloc. Both relocs will be against
510 The issue here is that we may not know whether i is GP addressable
511 until after we see the instruction that uses it. Therefore, we
512 want to be able to choose the final instruction sequence only at
513 the end of the assembly. This is similar to the way other
514 platforms choose the size of a PC relative instruction only at the
517 When generating position independent code we do not use GP
518 addressing in quite the same way, but the issue still arises as
519 external symbols and local symbols must be handled differently.
521 We handle these issues by actually generating both possible
522 instruction sequences. The longer one is put in a frag_var with
523 type rs_machine_dependent. We encode what to do with the frag in
524 the subtype field. We encode (1) the number of existing bytes to
525 replace, (2) the number of new bytes to use, (3) the offset from
526 the start of the existing bytes to the first reloc we must generate
527 (that is, the offset is applied from the start of the existing
528 bytes after they are replaced by the new bytes, if any), (4) the
529 offset from the start of the existing bytes to the second reloc,
530 (5) whether a third reloc is needed (the third reloc is always four
531 bytes after the second reloc), and (6) whether to warn if this
532 variant is used (this is sometimes needed if .set nomacro or .set
533 noat is in effect). All these numbers are reasonably small.
535 Generating two instruction sequences must be handled carefully to
536 ensure that delay slots are handled correctly. Fortunately, there
537 are a limited number of cases. When the second instruction
538 sequence is generated, append_insn is directed to maintain the
539 existing delay slot information, so it continues to apply to any
540 code after the second instruction sequence. This means that the
541 second instruction sequence must not impose any requirements not
542 required by the first instruction sequence.
544 These variant frags are then handled in functions called by the
545 machine independent code. md_estimate_size_before_relax returns
546 the final size of the frag. md_convert_frag sets up the final form
547 of the frag. tc_gen_reloc adjust the first reloc and adds a second
549 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
553 | (((reloc1) + 64) << 9) \
554 | (((reloc2) + 64) << 2) \
555 | ((reloc3) ? (1 << 1) : 0) \
557 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
558 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
559 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
560 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
561 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
562 #define RELAX_WARN(i) ((i) & 1)
564 /* For mips16 code, we use an entirely different form of relaxation.
565 mips16 supports two versions of most instructions which take
566 immediate values: a small one which takes some small value, and a
567 larger one which takes a 16 bit value. Since branches also follow
568 this pattern, relaxing these values is required.
570 We can assemble both mips16 and normal MIPS code in a single
571 object. Therefore, we need to support this type of relaxation at
572 the same time that we support the relaxation described above. We
573 use the high bit of the subtype field to distinguish these cases.
575 The information we store for this type of relaxation is the
576 argument code found in the opcode file for this relocation, whether
577 the user explicitly requested a small or extended form, and whether
578 the relocation is in a jump or jal delay slot. That tells us the
579 size of the value, and how it should be stored. We also store
580 whether the fragment is considered to be extended or not. We also
581 store whether this is known to be a branch to a different section,
582 whether we have tried to relax this frag yet, and whether we have
583 ever extended a PC relative fragment because of a shift count. */
584 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
587 | ((small) ? 0x100 : 0) \
588 | ((ext) ? 0x200 : 0) \
589 | ((dslot) ? 0x400 : 0) \
590 | ((jal_dslot) ? 0x800 : 0))
591 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
592 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
593 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
594 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
595 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
596 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
597 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
598 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
599 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
600 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
601 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
602 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
604 /* Prototypes for static functions. */
607 #define internalError() \
608 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
610 #define internalError() as_fatal ("MIPS internal Error");
613 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
615 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
616 unsigned int reg
, enum mips_regclass
class));
617 static int reg_needs_delay
PARAMS ((int));
618 static void mips16_mark_labels
PARAMS ((void));
619 static void append_insn
PARAMS ((char *place
,
620 struct mips_cl_insn
* ip
,
622 bfd_reloc_code_real_type r
,
624 static void mips_no_prev_insn
PARAMS ((int));
625 static void mips_emit_delays
PARAMS ((boolean
));
627 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
628 const char *name
, const char *fmt
,
631 static void macro_build ();
633 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
634 const char *, const char *,
636 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
637 expressionS
* ep
, int regnum
));
638 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
639 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
641 static void load_register
PARAMS ((int *, int, expressionS
*, int));
642 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
643 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
644 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
645 #ifdef LOSING_COMPILER
646 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
648 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
649 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
650 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
651 boolean
, boolean
, unsigned long *,
652 boolean
*, unsigned short *));
653 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
654 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
655 static symbolS
*get_symbol
PARAMS ((void));
656 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
657 static void s_align
PARAMS ((int));
658 static void s_change_sec
PARAMS ((int));
659 static void s_cons
PARAMS ((int));
660 static void s_float_cons
PARAMS ((int));
661 static void s_mips_globl
PARAMS ((int));
662 static void s_option
PARAMS ((int));
663 static void s_mipsset
PARAMS ((int));
664 static void s_abicalls
PARAMS ((int));
665 static void s_cpload
PARAMS ((int));
666 static void s_cprestore
PARAMS ((int));
667 static void s_gpword
PARAMS ((int));
668 static void s_cpadd
PARAMS ((int));
669 static void s_insn
PARAMS ((int));
670 static void md_obj_begin
PARAMS ((void));
671 static void md_obj_end
PARAMS ((void));
672 static long get_number
PARAMS ((void));
673 static void s_ent
PARAMS ((int));
674 static void s_mipsend
PARAMS ((int));
675 static void s_file
PARAMS ((int));
676 static void s_mips_stab
PARAMS ((int));
677 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
679 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
683 The following pseudo-ops from the Kane and Heinrich MIPS book
684 should be defined here, but are currently unsupported: .alias,
685 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
687 The following pseudo-ops from the Kane and Heinrich MIPS book are
688 specific to the type of debugging information being generated, and
689 should be defined by the object format: .aent, .begin, .bend,
690 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
693 The following pseudo-ops from the Kane and Heinrich MIPS book are
694 not MIPS CPU specific, but are also not specific to the object file
695 format. This file is probably the best place to define them, but
696 they are not currently supported: .asm0, .endr, .lab, .repeat,
697 .struct, .weakext. */
699 static const pseudo_typeS mips_pseudo_table
[] =
701 /* MIPS specific pseudo-ops. */
702 {"option", s_option
, 0},
703 {"set", s_mipsset
, 0},
704 {"rdata", s_change_sec
, 'r'},
705 {"sdata", s_change_sec
, 's'},
706 {"livereg", s_ignore
, 0},
707 {"abicalls", s_abicalls
, 0},
708 {"cpload", s_cpload
, 0},
709 {"cprestore", s_cprestore
, 0},
710 {"gpword", s_gpword
, 0},
711 {"cpadd", s_cpadd
, 0},
714 /* Relatively generic pseudo-ops that happen to be used on MIPS
716 {"asciiz", stringer
, 1},
717 {"bss", s_change_sec
, 'b'},
720 {"dword", s_cons
, 3},
722 /* These pseudo-ops are defined in read.c, but must be overridden
723 here for one reason or another. */
724 {"align", s_align
, 0},
726 {"data", s_change_sec
, 'd'},
727 {"double", s_float_cons
, 'd'},
728 {"float", s_float_cons
, 'f'},
729 {"globl", s_mips_globl
, 0},
730 {"global", s_mips_globl
, 0},
731 {"hword", s_cons
, 1},
736 {"short", s_cons
, 1},
737 {"single", s_float_cons
, 'f'},
738 {"stabn", s_mips_stab
, 'n'},
739 {"text", s_change_sec
, 't'},
744 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
745 /* These pseudo-ops should be defined by the object file format.
746 However, a.out doesn't support them, so we have versions here. */
748 {"bgnb", s_ignore
, 0},
749 {"end", s_mipsend
, 0},
750 {"endb", s_ignore
, 0},
753 {"fmask", s_ignore
, 'F'},
754 {"frame", s_ignore
, 0},
755 {"loc", s_ignore
, 0},
756 {"mask", s_ignore
, 'R'},
757 {"verstamp", s_ignore
, 0},
761 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
766 pop_insert (mips_pseudo_table
);
767 if (! ECOFF_DEBUGGING
)
768 pop_insert (mips_nonecoff_pseudo_table
);
771 /* Symbols labelling the current insn. */
773 struct insn_label_list
775 struct insn_label_list
*next
;
779 static struct insn_label_list
*insn_labels
;
780 static struct insn_label_list
*free_insn_labels
;
782 static void mips_clear_insn_labels
PARAMS ((void));
785 mips_clear_insn_labels ()
787 register struct insn_label_list
**pl
;
789 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
795 static char *expr_end
;
797 /* Expressions which appear in instructions. These are set by
800 static expressionS imm_expr
;
801 static expressionS offset_expr
;
803 /* Relocs associated with imm_expr and offset_expr. */
805 static bfd_reloc_code_real_type imm_reloc
;
806 static bfd_reloc_code_real_type offset_reloc
;
808 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
810 static boolean imm_unmatched_hi
;
812 /* These are set by mips16_ip if an explicit extension is used. */
814 static boolean mips16_small
, mips16_ext
;
817 * This function is called once, at assembler startup time. It should
818 * set up all the tables, etc. that the MD part of the assembler will need.
824 register const char *retval
= NULL
;
825 register unsigned int i
= 0;
831 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
833 a
= xmalloc (sizeof TARGET_CPU
);
834 strcpy (a
, TARGET_CPU
);
835 a
[(sizeof TARGET_CPU
) - 3] = '\0';
841 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
842 just the generic 'mips', in which case set mips_cpu based
843 on the given ISA, if any. */
845 if (strcmp (cpu
, "mips") == 0)
847 if (mips_opts
.isa
< 0)
850 else if (mips_opts
.isa
== 2)
853 else if (mips_opts
.isa
== 3)
856 else if (mips_opts
.isa
== 4)
863 else if (strcmp (cpu
, "r3900") == 0
864 || strcmp (cpu
, "mipstx39") == 0
865 /* start-sanitize-tx19 */
866 || strcmp (cpu
, "r1900") == 0
867 || strcmp (cpu
, "mipstx19") == 0
868 /* end-sanitize-tx19 */
872 else if (strcmp (cpu
, "r6000") == 0
873 || strcmp (cpu
, "mips2") == 0)
876 else if (strcmp (cpu
, "mips64") == 0
877 || strcmp (cpu
, "r4000") == 0
878 || strcmp (cpu
, "mips3") == 0)
881 else if (strcmp (cpu
, "r4400") == 0)
884 else if (strcmp (cpu
, "mips64orion") == 0
885 || strcmp (cpu
, "r4600") == 0)
888 else if (strcmp (cpu
, "r4650") == 0)
891 else if (strcmp (cpu
, "mips64vr4300") == 0)
894 /* start-sanitize-vr4320 */
895 else if (strcmp (cpu
, "r4320") == 0
896 || strcmp (cpu
, "mips64vr4320") == 0)
899 /* end-sanitize-vr4320 */
900 else if (strcmp (cpu
, "mips64vr4100") == 0
901 /* start-sanitize-vr4111 */
902 || strcmp (cpu
, "mips64vr4111") == 0
903 /* end-sanitize-vr4111 */
907 else if (strcmp (cpu
, "r4010") == 0)
910 /* start-sanitize-tx49 */
911 else if (strcmp (cpu
, "mips64tx49") == 0)
913 /* end-sanitize-tx49 */
915 else if (strcmp (cpu
, "r5000") == 0
916 || strcmp (cpu
, "mips64vr5000") == 0)
919 /* start-sanitize-vr5400 */
920 else if (strcmp (cpu
, "r5400") == 0
921 || strcmp (cpu
, "mips64vr5400") == 0)
923 /* end-sanitize-vr5400 */
925 /* start-sanitize-r5900 */
926 else if (strcmp (cpu
, "r5900") == 0
927 || strcmp (cpu
, "mips64r5900") == 0)
929 /* end-sanitize-r5900 */
931 else if (strcmp (cpu
, "r8000") == 0
932 || strcmp (cpu
, "mips4") == 0)
935 else if (strcmp (cpu
, "r10000") == 0)
938 else if (strcmp (cpu
, "mips16") == 0)
939 mips_cpu
= 0; /* FIXME */
945 if (mips_opts
.isa
== -1)
951 else if (mips_cpu
== 6000
955 else if (mips_cpu
== 4000
959 /* start-sanitize-vr4320 */
961 /* end-sanitize-4320 */
963 /* start-sanitize-tx49 */
965 /* end-sanitize-tx49 */
966 /* start-sanitize-r5900 */
968 /* end-sanitize-r5900 */
972 else if (mips_cpu
== 5000
973 /* start-sanitize-vr5400 */
975 /* end-sanitize-vr5400 */
977 || mips_cpu
== 10000)
984 if (mips_opts
.mips16
< 0)
986 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
987 mips_opts
.mips16
= 1;
989 mips_opts
.mips16
= 0;
993 mips_4650
= (mips_cpu
== 4650);
996 mips_4010
= (mips_cpu
== 4010);
999 mips_4100
= (mips_cpu
== 4100);
1001 /* start-sanitize-vr4320 */
1003 mips_4320
= (mips_cpu
== 4320);
1005 /* end-sanitize-vr4320 */
1006 /* start-sanitize-vr5400 */
1008 mips_5400
= (mips_cpu
== 5400);
1009 /* end-sanitize-vr5400 */
1011 /* start-sanitize-r5900 */
1013 mips_5900
= (mips_cpu
== 5900);
1014 /* end-sanitize-r5900 */
1017 mips_3900
= (mips_cpu
== 3900);
1019 /* start-sanitize-tx49 */
1021 mips_4900
= (mips_cpu
== 4900);
1023 /* end-sanitize-tx49 */
1025 /* End of TARGET_CPU processing, get rid of malloced memory
1034 if (mips_opts
.isa
< 2 && mips_trap
)
1035 as_bad ("trap exception not supported at ISA 1");
1037 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1039 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1043 switch (mips_opts
.isa
)
1046 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1049 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1052 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1055 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1061 as_warn ("Could not set architecture and machine");
1063 file_mips_isa
= mips_opts
.isa
;
1065 op_hash
= hash_new ();
1067 for (i
= 0; i
< NUMOPCODES
;)
1069 const char *name
= mips_opcodes
[i
].name
;
1071 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1074 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
1075 mips_opcodes
[i
].name
, retval
);
1076 /* Probably a memory allocation problem? Give up now. */
1077 as_fatal ("Broken assembler. No assembly attempted.");
1081 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1083 if (!validate_mips_insn (&mips_opcodes
[i
]))
1088 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1091 mips16_op_hash
= hash_new ();
1094 while (i
< bfd_mips16_num_opcodes
)
1096 const char *name
= mips16_opcodes
[i
].name
;
1098 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1100 as_fatal ("internal: can't hash `%s': %s",
1101 mips16_opcodes
[i
].name
, retval
);
1104 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1105 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1106 != mips16_opcodes
[i
].match
))
1108 fprintf (stderr
, "internal error: bad mips16 opcode: %s %s\n",
1109 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1114 while (i
< bfd_mips16_num_opcodes
1115 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1119 as_fatal ("Broken assembler. No assembly attempted.");
1121 /* We add all the general register names to the symbol table. This
1122 helps us detect invalid uses of them. */
1123 for (i
= 0; i
< 32; i
++)
1127 sprintf (buf
, "$%d", i
);
1128 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1129 &zero_address_frag
));
1131 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1132 &zero_address_frag
));
1133 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1134 &zero_address_frag
));
1135 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1136 &zero_address_frag
));
1137 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1138 &zero_address_frag
));
1139 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1140 &zero_address_frag
));
1141 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1142 &zero_address_frag
));
1143 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1144 &zero_address_frag
));
1146 mips_no_prev_insn (false);
1149 mips_cprmask
[0] = 0;
1150 mips_cprmask
[1] = 0;
1151 mips_cprmask
[2] = 0;
1152 mips_cprmask
[3] = 0;
1154 /* set the default alignment for the text section (2**2) */
1155 record_alignment (text_section
, 2);
1157 if (USE_GLOBAL_POINTER_OPT
)
1158 bfd_set_gp_size (stdoutput
, g_switch_value
);
1160 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1162 /* On a native system, sections must be aligned to 16 byte
1163 boundaries. When configured for an embedded ELF target, we
1165 if (strcmp (TARGET_OS
, "elf") != 0)
1167 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1168 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1169 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1172 /* Create a .reginfo section for register masks and a .mdebug
1173 section for debugging information. */
1181 subseg
= now_subseg
;
1183 /* The ABI says this section should be loaded so that the
1184 running program can access it. However, we don't load it
1185 if we are configured for an embedded target */
1186 flags
= SEC_READONLY
| SEC_DATA
;
1187 if (strcmp (TARGET_OS
, "elf") != 0)
1188 flags
|= SEC_ALLOC
| SEC_LOAD
;
1192 sec
= subseg_new (".reginfo", (subsegT
) 0);
1195 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1196 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1199 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1204 /* The 64-bit ABI uses a .MIPS.options section rather than
1205 .reginfo section. */
1206 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1207 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1208 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1211 /* Set up the option header. */
1213 Elf_Internal_Options opthdr
;
1216 opthdr
.kind
= ODK_REGINFO
;
1217 opthdr
.size
= (sizeof (Elf_External_Options
)
1218 + sizeof (Elf64_External_RegInfo
));
1221 f
= frag_more (sizeof (Elf_External_Options
));
1222 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1223 (Elf_External_Options
*) f
);
1225 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1230 if (ECOFF_DEBUGGING
)
1232 sec
= subseg_new (".mdebug", (subsegT
) 0);
1233 (void) bfd_set_section_flags (stdoutput
, sec
,
1234 SEC_HAS_CONTENTS
| SEC_READONLY
);
1235 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1238 subseg_set (seg
, subseg
);
1242 if (! ECOFF_DEBUGGING
)
1249 if (! ECOFF_DEBUGGING
)
1257 struct mips_cl_insn insn
;
1259 imm_expr
.X_op
= O_absent
;
1260 imm_reloc
= BFD_RELOC_UNUSED
;
1261 imm_unmatched_hi
= false;
1262 offset_expr
.X_op
= O_absent
;
1263 offset_reloc
= BFD_RELOC_UNUSED
;
1265 if (mips_opts
.mips16
)
1266 mips16_ip (str
, &insn
);
1269 mips_ip (str
, &insn
);
1270 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1271 str
, insn
.insn_opcode
));
1276 as_bad ("%s `%s'", insn_error
, str
);
1280 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1282 if (mips_opts
.mips16
)
1283 mips16_macro (&insn
);
1289 if (imm_expr
.X_op
!= O_absent
)
1290 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1292 else if (offset_expr
.X_op
!= O_absent
)
1293 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1295 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1299 /* See whether instruction IP reads register REG. CLASS is the type
1303 insn_uses_reg (ip
, reg
, class)
1304 struct mips_cl_insn
*ip
;
1306 enum mips_regclass
class;
1308 if (class == MIPS16_REG
)
1310 assert (mips_opts
.mips16
);
1311 reg
= mips16_to_32_reg_map
[reg
];
1312 class = MIPS_GR_REG
;
1315 /* Don't report on general register 0, since it never changes. */
1316 if (class == MIPS_GR_REG
&& reg
== 0)
1319 if (class == MIPS_FP_REG
)
1321 assert (! mips_opts
.mips16
);
1322 /* If we are called with either $f0 or $f1, we must check $f0.
1323 This is not optimal, because it will introduce an unnecessary
1324 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1325 need to distinguish reading both $f0 and $f1 or just one of
1326 them. Note that we don't have to check the other way,
1327 because there is no instruction that sets both $f0 and $f1
1328 and requires a delay. */
1329 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1330 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1331 == (reg
&~ (unsigned) 1)))
1333 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1334 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1335 == (reg
&~ (unsigned) 1)))
1338 else if (! mips_opts
.mips16
)
1340 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1341 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1343 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1344 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1349 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1350 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1351 & MIPS16OP_MASK_RX
)]
1354 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1355 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1356 & MIPS16OP_MASK_RY
)]
1359 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1360 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1361 & MIPS16OP_MASK_MOVE32Z
)]
1364 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1366 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1368 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1370 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1371 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1372 & MIPS16OP_MASK_REGR32
) == reg
)
1379 /* This function returns true if modifying a register requires a
1383 reg_needs_delay (reg
)
1386 unsigned long prev_pinfo
;
1388 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1389 if (! mips_opts
.noreorder
1390 && mips_opts
.isa
< 4
1391 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1392 || (! gpr_interlocks
1393 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1395 /* A load from a coprocessor or from memory. All load
1396 delays delay the use of general register rt for one
1397 instruction on the r3000. The r6000 and r4000 use
1399 /* Itbl support may require additional care here. */
1400 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1401 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1408 /* Mark instruction labels in mips16 mode. This permits the linker to
1409 handle them specially, such as generating jalx instructions when
1410 needed. We also make them odd for the duration of the assembly, in
1411 order to generate the right sort of code. We will make them even
1412 in the adjust_symtab routine, while leaving them marked. This is
1413 convenient for the debugger and the disassembler. The linker knows
1414 to make them odd again. */
1417 mips16_mark_labels ()
1419 if (mips_opts
.mips16
)
1421 struct insn_label_list
*l
;
1423 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1426 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1427 S_SET_OTHER (l
->label
, STO_MIPS16
);
1429 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1430 ++l
->label
->sy_value
.X_add_number
;
1435 /* Output an instruction. PLACE is where to put the instruction; if
1436 it is NULL, this uses frag_more to get room. IP is the instruction
1437 information. ADDRESS_EXPR is an operand of the instruction to be
1438 used with RELOC_TYPE. */
1441 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1443 struct mips_cl_insn
*ip
;
1444 expressionS
*address_expr
;
1445 bfd_reloc_code_real_type reloc_type
;
1446 boolean unmatched_hi
;
1448 register unsigned long prev_pinfo
, pinfo
;
1453 /* Mark instruction labels in mips16 mode. */
1454 if (mips_opts
.mips16
)
1455 mips16_mark_labels ();
1457 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1458 pinfo
= ip
->insn_mo
->pinfo
;
1460 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1464 /* If the previous insn required any delay slots, see if we need
1465 to insert a NOP or two. There are eight kinds of possible
1466 hazards, of which an instruction can have at most one type.
1467 (1) a load from memory delay
1468 (2) a load from a coprocessor delay
1469 (3) an unconditional branch delay
1470 (4) a conditional branch delay
1471 (5) a move to coprocessor register delay
1472 (6) a load coprocessor register from memory delay
1473 (7) a coprocessor condition code delay
1474 (8) a HI/LO special register delay
1476 There are a lot of optimizations we could do that we don't.
1477 In particular, we do not, in general, reorder instructions.
1478 If you use gcc with optimization, it will reorder
1479 instructions and generally do much more optimization then we
1480 do here; repeating all that work in the assembler would only
1481 benefit hand written assembly code, and does not seem worth
1484 /* This is how a NOP is emitted. */
1485 #define emit_nop() \
1487 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1488 : md_number_to_chars (frag_more (4), 0, 4))
1490 /* The previous insn might require a delay slot, depending upon
1491 the contents of the current insn. */
1492 if (! mips_opts
.mips16
1493 && mips_opts
.isa
< 4
1494 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1495 && ! cop_interlocks
)
1496 || (! gpr_interlocks
1497 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1499 /* A load from a coprocessor or from memory. All load
1500 delays delay the use of general register rt for one
1501 instruction on the r3000. The r6000 and r4000 use
1503 /* Itbl support may require additional care here. */
1504 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1505 if (mips_optimize
== 0
1506 || insn_uses_reg (ip
,
1507 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1512 else if (! mips_opts
.mips16
1513 && mips_opts
.isa
< 4
1514 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1515 && ! cop_interlocks
)
1516 || (mips_opts
.isa
< 2
1517 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1519 /* A generic coprocessor delay. The previous instruction
1520 modified a coprocessor general or control register. If
1521 it modified a control register, we need to avoid any
1522 coprocessor instruction (this is probably not always
1523 required, but it sometimes is). If it modified a general
1524 register, we avoid using that register.
1526 On the r6000 and r4000 loading a coprocessor register
1527 from memory is interlocked, and does not require a delay.
1529 This case is not handled very well. There is no special
1530 knowledge of CP0 handling, and the coprocessors other
1531 than the floating point unit are not distinguished at
1533 /* Itbl support may require additional care here. FIXME!
1534 Need to modify this to include knowledge about
1535 user specified delays! */
1536 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1538 if (mips_optimize
== 0
1539 || insn_uses_reg (ip
,
1540 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1545 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1547 if (mips_optimize
== 0
1548 || insn_uses_reg (ip
,
1549 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1556 /* We don't know exactly what the previous instruction
1557 does. If the current instruction uses a coprocessor
1558 register, we must insert a NOP. If previous
1559 instruction may set the condition codes, and the
1560 current instruction uses them, we must insert two
1562 /* Itbl support may require additional care here. */
1563 if (mips_optimize
== 0
1564 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1565 && (pinfo
& INSN_READ_COND_CODE
)))
1567 else if (pinfo
& INSN_COP
)
1571 else if (! mips_opts
.mips16
1572 && mips_opts
.isa
< 4
1573 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1574 && ! cop_interlocks
)
1576 /* The previous instruction sets the coprocessor condition
1577 codes, but does not require a general coprocessor delay
1578 (this means it is a floating point comparison
1579 instruction). If this instruction uses the condition
1580 codes, we need to insert a single NOP. */
1581 /* Itbl support may require additional care here. */
1582 if (mips_optimize
== 0
1583 || (pinfo
& INSN_READ_COND_CODE
))
1586 else if (prev_pinfo
& INSN_READ_LO
)
1588 /* The previous instruction reads the LO register; if the
1589 current instruction writes to the LO register, we must
1590 insert two NOPS. Some newer processors have interlocks. */
1591 if (! hilo_interlocks
1592 && (mips_optimize
== 0
1593 || (pinfo
& INSN_WRITE_LO
)))
1596 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1598 /* The previous instruction reads the HI register; if the
1599 current instruction writes to the HI register, we must
1600 insert a NOP. Some newer processors have interlocks. */
1601 if (! hilo_interlocks
1602 && (mips_optimize
== 0
1603 || (pinfo
& INSN_WRITE_HI
)))
1607 /* If the previous instruction was in a noreorder section, then
1608 we don't want to insert the nop after all. */
1609 /* Itbl support may require additional care here. */
1610 if (prev_insn_unreordered
)
1613 /* There are two cases which require two intervening
1614 instructions: 1) setting the condition codes using a move to
1615 coprocessor instruction which requires a general coprocessor
1616 delay and then reading the condition codes 2) reading the HI
1617 or LO register and then writing to it (except on processors
1618 which have interlocks). If we are not already emitting a NOP
1619 instruction, we must check for these cases compared to the
1620 instruction previous to the previous instruction. */
1621 if ((! mips_opts
.mips16
1622 && mips_opts
.isa
< 4
1623 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1624 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1625 && (pinfo
& INSN_READ_COND_CODE
)
1626 && ! cop_interlocks
)
1627 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1628 && (pinfo
& INSN_WRITE_LO
)
1629 && ! hilo_interlocks
)
1630 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1631 && (pinfo
& INSN_WRITE_HI
)
1632 && ! hilo_interlocks
))
1637 if (prev_prev_insn_unreordered
)
1640 if (prev_prev_nop
&& nops
== 0)
1643 /* If we are being given a nop instruction, don't bother with
1644 one of the nops we would otherwise output. This will only
1645 happen when a nop instruction is used with mips_optimize set
1648 && ! mips_opts
.noreorder
1649 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1652 /* Now emit the right number of NOP instructions. */
1653 if (nops
> 0 && ! mips_opts
.noreorder
)
1656 unsigned long old_frag_offset
;
1658 struct insn_label_list
*l
;
1660 old_frag
= frag_now
;
1661 old_frag_offset
= frag_now_fix ();
1663 for (i
= 0; i
< nops
; i
++)
1668 listing_prev_line ();
1669 /* We may be at the start of a variant frag. In case we
1670 are, make sure there is enough space for the frag
1671 after the frags created by listing_prev_line. The
1672 argument to frag_grow here must be at least as large
1673 as the argument to all other calls to frag_grow in
1674 this file. We don't have to worry about being in the
1675 middle of a variant frag, because the variants insert
1676 all needed nop instructions themselves. */
1680 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1682 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1683 l
->label
->sy_frag
= frag_now
;
1684 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1685 /* mips16 text labels are stored as odd. */
1686 if (mips_opts
.mips16
)
1687 ++l
->label
->sy_value
.X_add_number
;
1690 #ifndef NO_ECOFF_DEBUGGING
1691 if (ECOFF_DEBUGGING
)
1692 ecoff_fix_loc (old_frag
, old_frag_offset
);
1695 else if (prev_nop_frag
!= NULL
)
1697 /* We have a frag holding nops we may be able to remove. If
1698 we don't need any nops, we can decrease the size of
1699 prev_nop_frag by the size of one instruction. If we do
1700 need some nops, we count them in prev_nops_required. */
1701 if (prev_nop_frag_since
== 0)
1705 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1706 --prev_nop_frag_holds
;
1709 prev_nop_frag_required
+= nops
;
1713 if (prev_prev_nop
== 0)
1715 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1716 --prev_nop_frag_holds
;
1719 ++prev_nop_frag_required
;
1722 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1723 prev_nop_frag
= NULL
;
1725 ++prev_nop_frag_since
;
1727 /* Sanity check: by the time we reach the second instruction
1728 after prev_nop_frag, we should have used up all the nops
1729 one way or another. */
1730 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1734 if (reloc_type
> BFD_RELOC_UNUSED
)
1736 /* We need to set up a variant frag. */
1737 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1738 f
= frag_var (rs_machine_dependent
, 4, 0,
1739 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1740 mips16_small
, mips16_ext
,
1742 & INSN_UNCOND_BRANCH_DELAY
),
1743 (prev_insn_reloc_type
1744 == BFD_RELOC_MIPS16_JMP
)),
1745 make_expr_symbol (address_expr
), (offsetT
) 0,
1748 else if (place
!= NULL
)
1750 else if (mips_opts
.mips16
1752 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1754 /* Make sure there is enough room to swap this instruction with
1755 a following jump instruction. */
1761 if (mips_opts
.mips16
1762 && mips_opts
.noreorder
1763 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1764 as_warn ("extended instruction in delay slot");
1770 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1772 if (address_expr
->X_op
== O_constant
)
1777 ip
->insn_opcode
|= address_expr
->X_add_number
;
1780 case BFD_RELOC_LO16
:
1781 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1784 case BFD_RELOC_MIPS_JMP
:
1785 if ((address_expr
->X_add_number
& 3) != 0)
1786 as_bad ("jump to misaligned address (0x%lx)",
1787 (unsigned long) address_expr
->X_add_number
);
1788 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1791 case BFD_RELOC_MIPS16_JMP
:
1792 if ((address_expr
->X_add_number
& 3) != 0)
1793 as_bad ("jump to misaligned address (0x%lx)",
1794 (unsigned long) address_expr
->X_add_number
);
1796 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1797 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1798 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1801 case BFD_RELOC_16_PCREL_S2
:
1811 /* Don't generate a reloc if we are writing into a variant
1815 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1817 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1821 struct mips_hi_fixup
*hi_fixup
;
1823 assert (reloc_type
== BFD_RELOC_HI16_S
);
1824 hi_fixup
= ((struct mips_hi_fixup
*)
1825 xmalloc (sizeof (struct mips_hi_fixup
)));
1826 hi_fixup
->fixp
= fixp
;
1827 hi_fixup
->seg
= now_seg
;
1828 hi_fixup
->next
= mips_hi_fixup_list
;
1829 mips_hi_fixup_list
= hi_fixup
;
1835 if (! mips_opts
.mips16
)
1836 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1837 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1839 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1840 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1846 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1849 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1852 /* Update the register mask information. */
1853 if (! mips_opts
.mips16
)
1855 if (pinfo
& INSN_WRITE_GPR_D
)
1856 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1857 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1858 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1859 if (pinfo
& INSN_READ_GPR_S
)
1860 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1861 if (pinfo
& INSN_WRITE_GPR_31
)
1862 mips_gprmask
|= 1 << 31;
1863 if (pinfo
& INSN_WRITE_FPR_D
)
1864 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1865 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1866 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1867 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1868 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1869 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1870 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1871 if (pinfo
& INSN_COP
)
1873 /* We don't keep enough information to sort these cases out.
1874 The itbl support does keep this information however, although
1875 we currently don't support itbl fprmats as part of the cop
1876 instruction. May want to add this support in the future. */
1878 /* Never set the bit for $0, which is always zero. */
1879 mips_gprmask
&=~ 1 << 0;
1883 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1884 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1885 & MIPS16OP_MASK_RX
);
1886 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1887 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1888 & MIPS16OP_MASK_RY
);
1889 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1890 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1891 & MIPS16OP_MASK_RZ
);
1892 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1893 mips_gprmask
|= 1 << TREG
;
1894 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1895 mips_gprmask
|= 1 << SP
;
1896 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1897 mips_gprmask
|= 1 << RA
;
1898 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1899 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1900 if (pinfo
& MIPS16_INSN_READ_Z
)
1901 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1902 & MIPS16OP_MASK_MOVE32Z
);
1903 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1904 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1905 & MIPS16OP_MASK_REGR32
);
1908 if (place
== NULL
&& ! mips_opts
.noreorder
)
1910 /* Filling the branch delay slot is more complex. We try to
1911 switch the branch with the previous instruction, which we can
1912 do if the previous instruction does not set up a condition
1913 that the branch tests and if the branch is not itself the
1914 target of any branch. */
1915 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1916 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1918 if (mips_optimize
< 2
1919 /* If we have seen .set volatile or .set nomove, don't
1921 || mips_opts
.nomove
!= 0
1922 /* If we had to emit any NOP instructions, then we
1923 already know we can not swap. */
1925 /* If we don't even know the previous insn, we can not
1927 || ! prev_insn_valid
1928 /* If the previous insn is already in a branch delay
1929 slot, then we can not swap. */
1930 || prev_insn_is_delay_slot
1931 /* If the previous previous insn was in a .set
1932 noreorder, we can't swap. Actually, the MIPS
1933 assembler will swap in this situation. However, gcc
1934 configured -with-gnu-as will generate code like
1940 in which we can not swap the bne and INSN. If gcc is
1941 not configured -with-gnu-as, it does not output the
1942 .set pseudo-ops. We don't have to check
1943 prev_insn_unreordered, because prev_insn_valid will
1944 be 0 in that case. We don't want to use
1945 prev_prev_insn_valid, because we do want to be able
1946 to swap at the start of a function. */
1947 || prev_prev_insn_unreordered
1948 /* If the branch is itself the target of a branch, we
1949 can not swap. We cheat on this; all we check for is
1950 whether there is a label on this instruction. If
1951 there are any branches to anything other than a
1952 label, users must use .set noreorder. */
1953 || insn_labels
!= NULL
1954 /* If the previous instruction is in a variant frag, we
1955 can not do the swap. This does not apply to the
1956 mips16, which uses variant frags for different
1958 || (! mips_opts
.mips16
1959 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1960 /* If the branch reads the condition codes, we don't
1961 even try to swap, because in the sequence
1966 we can not swap, and I don't feel like handling that
1968 || (! mips_opts
.mips16
1969 && mips_opts
.isa
< 4
1970 && (pinfo
& INSN_READ_COND_CODE
))
1971 /* We can not swap with an instruction that requires a
1972 delay slot, becase the target of the branch might
1973 interfere with that instruction. */
1974 || (! mips_opts
.mips16
1975 && mips_opts
.isa
< 4
1977 /* Itbl support may require additional care here. */
1978 & (INSN_LOAD_COPROC_DELAY
1979 | INSN_COPROC_MOVE_DELAY
1980 | INSN_WRITE_COND_CODE
)))
1981 || (! hilo_interlocks
1985 || (! mips_opts
.mips16
1987 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1988 || (! mips_opts
.mips16
1989 && mips_opts
.isa
< 2
1990 /* Itbl support may require additional care here. */
1991 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1992 /* We can not swap with a branch instruction. */
1994 & (INSN_UNCOND_BRANCH_DELAY
1995 | INSN_COND_BRANCH_DELAY
1996 | INSN_COND_BRANCH_LIKELY
))
1997 /* We do not swap with a trap instruction, since it
1998 complicates trap handlers to have the trap
1999 instruction be in a delay slot. */
2000 || (prev_pinfo
& INSN_TRAP
)
2001 /* If the branch reads a register that the previous
2002 instruction sets, we can not swap. */
2003 || (! mips_opts
.mips16
2004 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2005 && insn_uses_reg (ip
,
2006 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2009 || (! mips_opts
.mips16
2010 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2011 && insn_uses_reg (ip
,
2012 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2015 || (mips_opts
.mips16
2016 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2017 && insn_uses_reg (ip
,
2018 ((prev_insn
.insn_opcode
2020 & MIPS16OP_MASK_RX
),
2022 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2023 && insn_uses_reg (ip
,
2024 ((prev_insn
.insn_opcode
2026 & MIPS16OP_MASK_RY
),
2028 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2029 && insn_uses_reg (ip
,
2030 ((prev_insn
.insn_opcode
2032 & MIPS16OP_MASK_RZ
),
2034 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2035 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2036 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2037 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2038 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2039 && insn_uses_reg (ip
,
2040 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2043 /* If the branch writes a register that the previous
2044 instruction sets, we can not swap (we know that
2045 branches write only to RD or to $31). */
2046 || (! mips_opts
.mips16
2047 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2048 && (((pinfo
& INSN_WRITE_GPR_D
)
2049 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2050 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2051 || ((pinfo
& INSN_WRITE_GPR_31
)
2052 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2055 || (! mips_opts
.mips16
2056 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2057 && (((pinfo
& INSN_WRITE_GPR_D
)
2058 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2059 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2060 || ((pinfo
& INSN_WRITE_GPR_31
)
2061 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2064 || (mips_opts
.mips16
2065 && (pinfo
& MIPS16_INSN_WRITE_31
)
2066 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2067 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2068 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2070 /* If the branch writes a register that the previous
2071 instruction reads, we can not swap (we know that
2072 branches only write to RD or to $31). */
2073 || (! mips_opts
.mips16
2074 && (pinfo
& INSN_WRITE_GPR_D
)
2075 && insn_uses_reg (&prev_insn
,
2076 ((ip
->insn_opcode
>> OP_SH_RD
)
2079 || (! mips_opts
.mips16
2080 && (pinfo
& INSN_WRITE_GPR_31
)
2081 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2082 || (mips_opts
.mips16
2083 && (pinfo
& MIPS16_INSN_WRITE_31
)
2084 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2085 /* If we are generating embedded PIC code, the branch
2086 might be expanded into a sequence which uses $at, so
2087 we can't swap with an instruction which reads it. */
2088 || (mips_pic
== EMBEDDED_PIC
2089 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2090 /* If the previous previous instruction has a load
2091 delay, and sets a register that the branch reads, we
2093 || (! mips_opts
.mips16
2094 && mips_opts
.isa
< 4
2095 /* Itbl support may require additional care here. */
2096 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2097 || (! gpr_interlocks
2098 && (prev_prev_insn
.insn_mo
->pinfo
2099 & INSN_LOAD_MEMORY_DELAY
)))
2100 && insn_uses_reg (ip
,
2101 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2104 /* If one instruction sets a condition code and the
2105 other one uses a condition code, we can not swap. */
2106 || ((pinfo
& INSN_READ_COND_CODE
)
2107 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2108 || ((pinfo
& INSN_WRITE_COND_CODE
)
2109 && (prev_pinfo
& INSN_READ_COND_CODE
))
2110 /* If the previous instruction uses the PC, we can not
2112 || (mips_opts
.mips16
2113 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2114 /* If the previous instruction was extended, we can not
2116 || (mips_opts
.mips16
&& prev_insn_extended
)
2117 /* If the previous instruction had a fixup in mips16
2118 mode, we can not swap. This normally means that the
2119 previous instruction was a 4 byte branch anyhow. */
2120 || (mips_opts
.mips16
&& prev_insn_fixp
))
2122 /* We could do even better for unconditional branches to
2123 portions of this object file; we could pick up the
2124 instruction at the destination, put it in the delay
2125 slot, and bump the destination address. */
2127 /* Update the previous insn information. */
2128 prev_prev_insn
= *ip
;
2129 prev_insn
.insn_mo
= &dummy_opcode
;
2133 /* It looks like we can actually do the swap. */
2134 if (! mips_opts
.mips16
)
2139 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2140 memcpy (temp
, prev_f
, 4);
2141 memcpy (prev_f
, f
, 4);
2142 memcpy (f
, temp
, 4);
2145 prev_insn_fixp
->fx_frag
= frag_now
;
2146 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2150 fixp
->fx_frag
= prev_insn_frag
;
2151 fixp
->fx_where
= prev_insn_where
;
2159 assert (prev_insn_fixp
== NULL
);
2160 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2161 memcpy (temp
, prev_f
, 2);
2162 memcpy (prev_f
, f
, 2);
2163 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2165 assert (reloc_type
== BFD_RELOC_UNUSED
);
2166 memcpy (f
, temp
, 2);
2170 memcpy (f
, f
+ 2, 2);
2171 memcpy (f
+ 2, temp
, 2);
2175 fixp
->fx_frag
= prev_insn_frag
;
2176 fixp
->fx_where
= prev_insn_where
;
2180 /* Update the previous insn information; leave prev_insn
2182 prev_prev_insn
= *ip
;
2184 prev_insn_is_delay_slot
= 1;
2186 /* If that was an unconditional branch, forget the previous
2187 insn information. */
2188 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2190 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2191 prev_insn
.insn_mo
= &dummy_opcode
;
2194 prev_insn_fixp
= NULL
;
2195 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2196 prev_insn_extended
= 0;
2198 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2200 /* We don't yet optimize a branch likely. What we should do
2201 is look at the target, copy the instruction found there
2202 into the delay slot, and increment the branch to jump to
2203 the next instruction. */
2205 /* Update the previous insn information. */
2206 prev_prev_insn
= *ip
;
2207 prev_insn
.insn_mo
= &dummy_opcode
;
2208 prev_insn_fixp
= NULL
;
2209 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2210 prev_insn_extended
= 0;
2214 /* Update the previous insn information. */
2216 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2218 prev_prev_insn
= prev_insn
;
2221 /* Any time we see a branch, we always fill the delay slot
2222 immediately; since this insn is not a branch, we know it
2223 is not in a delay slot. */
2224 prev_insn_is_delay_slot
= 0;
2226 prev_insn_fixp
= fixp
;
2227 prev_insn_reloc_type
= reloc_type
;
2228 if (mips_opts
.mips16
)
2229 prev_insn_extended
= (ip
->use_extend
2230 || reloc_type
> BFD_RELOC_UNUSED
);
2233 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2234 prev_insn_unreordered
= 0;
2235 prev_insn_frag
= frag_now
;
2236 prev_insn_where
= f
- frag_now
->fr_literal
;
2237 prev_insn_valid
= 1;
2239 else if (place
== NULL
)
2241 /* We need to record a bit of information even when we are not
2242 reordering, in order to determine the base address for mips16
2243 PC relative relocs. */
2244 prev_prev_insn
= prev_insn
;
2246 prev_insn_reloc_type
= reloc_type
;
2247 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2248 prev_insn_unreordered
= 1;
2251 /* We just output an insn, so the next one doesn't have a label. */
2252 mips_clear_insn_labels ();
2254 /* We must ensure that a fixup associated with an unmatched %hi
2255 reloc does not become a variant frag. Otherwise, the
2256 rearrangement of %hi relocs in frob_file may confuse
2260 frag_wane (frag_now
);
2265 /* This function forgets that there was any previous instruction or
2266 label. If PRESERVE is non-zero, it remembers enough information to
2267 know whether nops are needed before a noreorder section. */
2270 mips_no_prev_insn (preserve
)
2275 prev_insn
.insn_mo
= &dummy_opcode
;
2276 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2277 prev_nop_frag
= NULL
;
2278 prev_nop_frag_holds
= 0;
2279 prev_nop_frag_required
= 0;
2280 prev_nop_frag_since
= 0;
2282 prev_insn_valid
= 0;
2283 prev_insn_is_delay_slot
= 0;
2284 prev_insn_unreordered
= 0;
2285 prev_insn_extended
= 0;
2286 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2287 prev_prev_insn_unreordered
= 0;
2288 mips_clear_insn_labels ();
2291 /* This function must be called whenever we turn on noreorder or emit
2292 something other than instructions. It inserts any NOPS which might
2293 be needed by the previous instruction, and clears the information
2294 kept for the previous instructions. The INSNS parameter is true if
2295 instructions are to follow. */
2298 mips_emit_delays (insns
)
2301 if (! mips_opts
.noreorder
)
2306 if ((! mips_opts
.mips16
2307 && mips_opts
.isa
< 4
2308 && (! cop_interlocks
2309 && (prev_insn
.insn_mo
->pinfo
2310 & (INSN_LOAD_COPROC_DELAY
2311 | INSN_COPROC_MOVE_DELAY
2312 | INSN_WRITE_COND_CODE
))))
2313 || (! hilo_interlocks
2314 && (prev_insn
.insn_mo
->pinfo
2317 || (! mips_opts
.mips16
2319 && (prev_insn
.insn_mo
->pinfo
2320 & INSN_LOAD_MEMORY_DELAY
))
2321 || (! mips_opts
.mips16
2322 && mips_opts
.isa
< 2
2323 && (prev_insn
.insn_mo
->pinfo
2324 & INSN_COPROC_MEMORY_DELAY
)))
2326 /* Itbl support may require additional care here. */
2328 if ((! mips_opts
.mips16
2329 && mips_opts
.isa
< 4
2330 && (! cop_interlocks
2331 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2332 || (! hilo_interlocks
2333 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2334 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2337 if (prev_insn_unreordered
)
2340 else if ((! mips_opts
.mips16
2341 && mips_opts
.isa
< 4
2342 && (! cop_interlocks
2343 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2344 || (! hilo_interlocks
2345 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2346 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2348 /* Itbl support may require additional care here. */
2349 if (! prev_prev_insn_unreordered
)
2355 struct insn_label_list
*l
;
2359 /* Record the frag which holds the nop instructions, so
2360 that we can remove them if we don't need them. */
2361 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2362 prev_nop_frag
= frag_now
;
2363 prev_nop_frag_holds
= nops
;
2364 prev_nop_frag_required
= 0;
2365 prev_nop_frag_since
= 0;
2368 for (; nops
> 0; --nops
)
2373 /* Move on to a new frag, so that it is safe to simply
2374 decrease the size of prev_nop_frag. */
2375 frag_wane (frag_now
);
2379 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2381 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2382 l
->label
->sy_frag
= frag_now
;
2383 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2384 /* mips16 text labels are stored as odd. */
2385 if (mips_opts
.mips16
)
2386 ++l
->label
->sy_value
.X_add_number
;
2391 /* Mark instruction labels in mips16 mode. */
2392 if (mips_opts
.mips16
&& insns
)
2393 mips16_mark_labels ();
2395 mips_no_prev_insn (insns
);
2398 /* Build an instruction created by a macro expansion. This is passed
2399 a pointer to the count of instructions created so far, an
2400 expression, the name of the instruction to build, an operand format
2401 string, and corresponding arguments. */
2405 macro_build (char *place
,
2413 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2422 struct mips_cl_insn insn
;
2423 bfd_reloc_code_real_type r
;
2428 va_start (args
, fmt
);
2434 * If the macro is about to expand into a second instruction,
2435 * print a warning if needed. We need to pass ip as a parameter
2436 * to generate a better warning message here...
2438 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2439 as_warn ("Macro instruction expanded into multiple instructions");
2442 *counter
+= 1; /* bump instruction counter */
2444 if (mips_opts
.mips16
)
2446 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2451 r
= BFD_RELOC_UNUSED
;
2452 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2453 assert (insn
.insn_mo
);
2454 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2456 /* Search until we get a match for NAME. */
2459 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2461 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2463 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2465 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2470 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2471 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2472 && (insn_isa
<= mips_opts
.isa
2474 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2476 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2478 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2479 /* start-sanitize-vr4320 */
2481 && (insn
.insn_mo
->membership
& INSN_4320
) != 0)
2482 /* end-sanitize-vr4320 */
2483 /* start-sanitize-tx49 */
2485 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2486 /* end-sanitize-tx49 */
2487 /* start-sanitize-r5900 */
2489 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2490 /* end-sanitize-r5900 */
2491 /* start-sanitize-vr5400 */
2493 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2494 /* end-sanitize-vr5400 */
2496 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2497 /* start-sanitize-r5900 */
2498 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2499 /* end-sanitize-r5900 */
2500 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2504 assert (insn
.insn_mo
->name
);
2505 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2508 insn
.insn_opcode
= insn
.insn_mo
->match
;
2524 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2530 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2535 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2540 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2547 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2551 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2555 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2562 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2568 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2569 assert (r
== BFD_RELOC_MIPS_GPREL
2570 || r
== BFD_RELOC_MIPS_LITERAL
2571 || r
== BFD_RELOC_LO16
2572 || r
== BFD_RELOC_MIPS_GOT16
2573 || r
== BFD_RELOC_MIPS_CALL16
2574 || r
== BFD_RELOC_MIPS_GOT_LO16
2575 || r
== BFD_RELOC_MIPS_CALL_LO16
2576 || (ep
->X_op
== O_subtract
2577 && now_seg
== text_section
2578 && r
== BFD_RELOC_PCREL_LO16
));
2582 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2584 && (ep
->X_op
== O_constant
2585 || (ep
->X_op
== O_symbol
2586 && (r
== BFD_RELOC_HI16_S
2587 || r
== BFD_RELOC_HI16
2588 || r
== BFD_RELOC_MIPS_GOT_HI16
2589 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2590 || (ep
->X_op
== O_subtract
2591 && now_seg
== text_section
2592 && r
== BFD_RELOC_PCREL_HI16_S
)));
2593 if (ep
->X_op
== O_constant
)
2595 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2597 r
= BFD_RELOC_UNUSED
;
2602 assert (ep
!= NULL
);
2604 * This allows macro() to pass an immediate expression for
2605 * creating short branches without creating a symbol.
2606 * Note that the expression still might come from the assembly
2607 * input, in which case the value is not checked for range nor
2608 * is a relocation entry generated (yuck).
2610 if (ep
->X_op
== O_constant
)
2612 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2616 r
= BFD_RELOC_16_PCREL_S2
;
2620 assert (ep
!= NULL
);
2621 r
= BFD_RELOC_MIPS_JMP
;
2625 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2634 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2636 append_insn (place
, &insn
, ep
, r
, false);
2640 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2648 struct mips_cl_insn insn
;
2649 bfd_reloc_code_real_type r
;
2651 r
= BFD_RELOC_UNUSED
;
2652 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2653 assert (insn
.insn_mo
);
2654 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2656 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2657 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2660 assert (insn
.insn_mo
->name
);
2661 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2664 insn
.insn_opcode
= insn
.insn_mo
->match
;
2665 insn
.use_extend
= false;
2684 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2689 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2693 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2697 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2707 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2714 regno
= va_arg (args
, int);
2715 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2716 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2737 assert (ep
!= NULL
);
2739 if (ep
->X_op
!= O_constant
)
2740 r
= BFD_RELOC_UNUSED
+ c
;
2743 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2744 false, false, &insn
.insn_opcode
,
2745 &insn
.use_extend
, &insn
.extend
);
2747 r
= BFD_RELOC_UNUSED
;
2753 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2760 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2762 append_insn (place
, &insn
, ep
, r
, false);
2766 * Generate a "lui" instruction.
2769 macro_build_lui (place
, counter
, ep
, regnum
)
2775 expressionS high_expr
;
2776 struct mips_cl_insn insn
;
2777 bfd_reloc_code_real_type r
;
2778 CONST
char *name
= "lui";
2779 CONST
char *fmt
= "t,u";
2781 assert (! mips_opts
.mips16
);
2787 high_expr
.X_op
= O_constant
;
2788 high_expr
.X_add_number
= ep
->X_add_number
;
2791 if (high_expr
.X_op
== O_constant
)
2793 /* we can compute the instruction now without a relocation entry */
2794 if (high_expr
.X_add_number
& 0x8000)
2795 high_expr
.X_add_number
+= 0x10000;
2796 high_expr
.X_add_number
=
2797 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2798 r
= BFD_RELOC_UNUSED
;
2802 assert (ep
->X_op
== O_symbol
);
2803 /* _gp_disp is a special case, used from s_cpload. */
2804 assert (mips_pic
== NO_PIC
2805 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2806 r
= BFD_RELOC_HI16_S
;
2810 * If the macro is about to expand into a second instruction,
2811 * print a warning if needed. We need to pass ip as a parameter
2812 * to generate a better warning message here...
2814 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2815 as_warn ("Macro instruction expanded into multiple instructions");
2818 *counter
+= 1; /* bump instruction counter */
2820 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2821 assert (insn
.insn_mo
);
2822 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2823 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2825 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2826 if (r
== BFD_RELOC_UNUSED
)
2828 insn
.insn_opcode
|= high_expr
.X_add_number
;
2829 append_insn (place
, &insn
, NULL
, r
, false);
2832 append_insn (place
, &insn
, &high_expr
, r
, false);
2836 * Generates code to set the $at register to true (one)
2837 * if reg is less than the immediate expression.
2840 set_at (counter
, reg
, unsignedp
)
2845 if (imm_expr
.X_op
== O_constant
2846 && imm_expr
.X_add_number
>= -0x8000
2847 && imm_expr
.X_add_number
< 0x8000)
2848 macro_build ((char *) NULL
, counter
, &imm_expr
,
2849 unsignedp
? "sltiu" : "slti",
2850 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2853 load_register (counter
, AT
, &imm_expr
, 0);
2854 macro_build ((char *) NULL
, counter
, NULL
,
2855 unsignedp
? "sltu" : "slt",
2856 "d,v,t", AT
, reg
, AT
);
2860 /* Warn if an expression is not a constant. */
2863 check_absolute_expr (ip
, ex
)
2864 struct mips_cl_insn
*ip
;
2867 if (ex
->X_op
== O_big
)
2868 as_bad ("unsupported large constant");
2869 else if (ex
->X_op
!= O_constant
)
2870 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2873 /* Count the leading zeroes by performing a binary chop. This is a
2874 bulky bit of source, but performance is a LOT better for the
2875 majority of values than a simple loop to count the bits:
2876 for (lcnt = 0; (lcnt < 32); lcnt++)
2877 if ((v) & (1 << (31 - lcnt)))
2879 However it is not code size friendly, and the gain will drop a bit
2880 on certain cached systems.
2882 #define COUNT_TOP_ZEROES(v) \
2883 (((v) & ~0xffff) == 0 \
2884 ? ((v) & ~0xff) == 0 \
2885 ? ((v) & ~0xf) == 0 \
2886 ? ((v) & ~0x3) == 0 \
2887 ? ((v) & ~0x1) == 0 \
2892 : ((v) & ~0x7) == 0 \
2895 : ((v) & ~0x3f) == 0 \
2896 ? ((v) & ~0x1f) == 0 \
2899 : ((v) & ~0x7f) == 0 \
2902 : ((v) & ~0xfff) == 0 \
2903 ? ((v) & ~0x3ff) == 0 \
2904 ? ((v) & ~0x1ff) == 0 \
2907 : ((v) & ~0x7ff) == 0 \
2910 : ((v) & ~0x3fff) == 0 \
2911 ? ((v) & ~0x1fff) == 0 \
2914 : ((v) & ~0x7fff) == 0 \
2917 : ((v) & ~0xffffff) == 0 \
2918 ? ((v) & ~0xfffff) == 0 \
2919 ? ((v) & ~0x3ffff) == 0 \
2920 ? ((v) & ~0x1ffff) == 0 \
2923 : ((v) & ~0x7ffff) == 0 \
2926 : ((v) & ~0x3fffff) == 0 \
2927 ? ((v) & ~0x1fffff) == 0 \
2930 : ((v) & ~0x7fffff) == 0 \
2933 : ((v) & ~0xfffffff) == 0 \
2934 ? ((v) & ~0x3ffffff) == 0 \
2935 ? ((v) & ~0x1ffffff) == 0 \
2938 : ((v) & ~0x7ffffff) == 0 \
2941 : ((v) & ~0x3fffffff) == 0 \
2942 ? ((v) & ~0x1fffffff) == 0 \
2945 : ((v) & ~0x7fffffff) == 0 \
2950 * This routine generates the least number of instructions neccessary to load
2951 * an absolute expression value into a register.
2954 load_register (counter
, reg
, ep
, dbl
)
2961 expressionS hi32
, lo32
;
2963 if (ep
->X_op
!= O_big
)
2965 assert (ep
->X_op
== O_constant
);
2966 if (ep
->X_add_number
< 0x8000
2967 && (ep
->X_add_number
>= 0
2968 || (ep
->X_add_number
>= -0x8000
2971 || sizeof (ep
->X_add_number
) > 4))))
2973 /* We can handle 16 bit signed values with an addiu to
2974 $zero. No need to ever use daddiu here, since $zero and
2975 the result are always correct in 32 bit mode. */
2976 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2977 (int) BFD_RELOC_LO16
);
2980 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2982 /* We can handle 16 bit unsigned values with an ori to
2984 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2985 (int) BFD_RELOC_LO16
);
2988 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2989 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2990 == ~ (offsetT
) 0x7fffffff))
2993 || sizeof (ep
->X_add_number
) > 4
2994 || (ep
->X_add_number
& 0x80000000) == 0))
2995 || ((mips_opts
.isa
< 3 || ! dbl
)
2996 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2997 || (mips_opts
.isa
< 3
2999 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3000 == ~ (offsetT
) 0xffffffff)))
3002 /* 32 bit values require an lui. */
3003 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3004 (int) BFD_RELOC_HI16
);
3005 if ((ep
->X_add_number
& 0xffff) != 0)
3006 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3007 (int) BFD_RELOC_LO16
);
3012 /* The value is larger than 32 bits. */
3014 if (mips_opts
.isa
< 3)
3016 as_bad ("Number larger than 32 bits");
3017 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3018 (int) BFD_RELOC_LO16
);
3022 if (ep
->X_op
!= O_big
)
3025 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3026 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3027 hi32
.X_add_number
&= 0xffffffff;
3029 lo32
.X_add_number
&= 0xffffffff;
3033 assert (ep
->X_add_number
> 2);
3034 if (ep
->X_add_number
== 3)
3035 generic_bignum
[3] = 0;
3036 else if (ep
->X_add_number
> 4)
3037 as_bad ("Number larger than 64 bits");
3038 lo32
.X_op
= O_constant
;
3039 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3040 hi32
.X_op
= O_constant
;
3041 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3044 if (hi32
.X_add_number
== 0)
3049 unsigned long hi
, lo
;
3051 if (hi32
.X_add_number
== 0xffffffff)
3053 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3055 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3056 reg
, 0, (int) BFD_RELOC_LO16
);
3059 if (lo32
.X_add_number
& 0x80000000)
3061 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3062 (int) BFD_RELOC_HI16
);
3063 if (lo32
.X_add_number
& 0xffff)
3064 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3065 reg
, reg
, (int) BFD_RELOC_LO16
);
3070 /* Check for 16bit shifted constant. We know that hi32 is
3071 non-zero, so start the mask on the first bit of the hi32
3076 unsigned long himask
, lomask
;
3080 himask
= 0xffff >> (32 - shift
);
3081 lomask
= (0xffff << shift
) & 0xffffffff;
3085 himask
= 0xffff << (shift
- 32);
3088 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3089 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3093 tmp
.X_op
= O_constant
;
3095 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3096 | (lo32
.X_add_number
>> shift
));
3098 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3099 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3100 (int) BFD_RELOC_LO16
);
3101 macro_build ((char *) NULL
, counter
, NULL
,
3102 (shift
>= 32) ? "dsll32" : "dsll",
3104 (shift
>= 32) ? shift
- 32 : shift
);
3108 } while (shift
<= (64 - 16));
3110 /* Find the bit number of the lowest one bit, and store the
3111 shifted value in hi/lo. */
3112 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3113 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3117 while ((lo
& 1) == 0)
3122 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3128 while ((hi
& 1) == 0)
3137 /* Optimize if the shifted value is a (power of 2) - 1. */
3138 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3139 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3141 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3146 /* This instruction will set the register to be all
3148 tmp
.X_op
= O_constant
;
3149 tmp
.X_add_number
= (offsetT
) -1;
3150 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3151 reg
, 0, (int) BFD_RELOC_LO16
);
3155 macro_build ((char *) NULL
, counter
, NULL
,
3156 (bit
>= 32) ? "dsll32" : "dsll",
3158 (bit
>= 32) ? bit
- 32 : bit
);
3160 macro_build ((char *) NULL
, counter
, NULL
,
3161 (shift
>= 32) ? "dsrl32" : "dsrl",
3163 (shift
>= 32) ? shift
- 32 : shift
);
3168 /* Sign extend hi32 before calling load_register, because we can
3169 generally get better code when we load a sign extended value. */
3170 if ((hi32
.X_add_number
& 0x80000000) != 0)
3171 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3172 load_register (counter
, reg
, &hi32
, 0);
3175 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3179 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3188 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3190 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3191 (int) BFD_RELOC_HI16
);
3192 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3199 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3204 mid16
.X_add_number
>>= 16;
3205 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3206 freg
, (int) BFD_RELOC_LO16
);
3207 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3211 if ((lo32
.X_add_number
& 0xffff) != 0)
3212 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3213 (int) BFD_RELOC_LO16
);
3216 /* Load an address into a register. */
3219 load_address (counter
, reg
, ep
)
3226 if (ep
->X_op
!= O_constant
3227 && ep
->X_op
!= O_symbol
)
3229 as_bad ("expression too complex");
3230 ep
->X_op
= O_constant
;
3233 if (ep
->X_op
== O_constant
)
3235 load_register (counter
, reg
, ep
, 0);
3239 if (mips_pic
== NO_PIC
)
3241 /* If this is a reference to a GP relative symbol, we want
3242 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3244 lui $reg,<sym> (BFD_RELOC_HI16_S)
3245 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3246 If we have an addend, we always use the latter form. */
3247 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3248 || nopic_need_relax (ep
->X_add_symbol
, 1))
3253 macro_build ((char *) NULL
, counter
, ep
,
3254 ((bfd_arch_bits_per_address (stdoutput
) == 32
3255 || mips_opts
.isa
< 3)
3256 ? "addiu" : "daddiu"),
3257 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3258 p
= frag_var (rs_machine_dependent
, 8, 0,
3259 RELAX_ENCODE (4, 8, 0, 4, 0,
3260 mips_opts
.warn_about_macros
),
3261 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3263 macro_build_lui (p
, counter
, ep
, reg
);
3266 macro_build (p
, counter
, ep
,
3267 ((bfd_arch_bits_per_address (stdoutput
) == 32
3268 || mips_opts
.isa
< 3)
3269 ? "addiu" : "daddiu"),
3270 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3272 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3276 /* If this is a reference to an external symbol, we want
3277 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3279 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3281 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3282 If there is a constant, it must be added in after. */
3283 ex
.X_add_number
= ep
->X_add_number
;
3284 ep
->X_add_number
= 0;
3286 macro_build ((char *) NULL
, counter
, ep
,
3287 ((bfd_arch_bits_per_address (stdoutput
) == 32
3288 || mips_opts
.isa
< 3)
3290 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3291 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3292 p
= frag_var (rs_machine_dependent
, 4, 0,
3293 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3294 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3295 macro_build (p
, counter
, ep
,
3296 ((bfd_arch_bits_per_address (stdoutput
) == 32
3297 || mips_opts
.isa
< 3)
3298 ? "addiu" : "daddiu"),
3299 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3300 if (ex
.X_add_number
!= 0)
3302 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3303 as_bad ("PIC code offset overflow (max 16 signed bits)");
3304 ex
.X_op
= O_constant
;
3305 macro_build ((char *) NULL
, counter
, &ex
,
3306 ((bfd_arch_bits_per_address (stdoutput
) == 32
3307 || mips_opts
.isa
< 3)
3308 ? "addiu" : "daddiu"),
3309 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3312 else if (mips_pic
== SVR4_PIC
)
3317 /* This is the large GOT case. If this is a reference to an
3318 external symbol, we want
3319 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3321 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3322 Otherwise, for a reference to a local symbol, we want
3323 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3325 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3326 If there is a constant, it must be added in after. */
3327 ex
.X_add_number
= ep
->X_add_number
;
3328 ep
->X_add_number
= 0;
3329 if (reg_needs_delay (GP
))
3334 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3335 (int) BFD_RELOC_MIPS_GOT_HI16
);
3336 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3337 ((bfd_arch_bits_per_address (stdoutput
) == 32
3338 || mips_opts
.isa
< 3)
3339 ? "addu" : "daddu"),
3340 "d,v,t", reg
, reg
, GP
);
3341 macro_build ((char *) NULL
, counter
, ep
,
3342 ((bfd_arch_bits_per_address (stdoutput
) == 32
3343 || mips_opts
.isa
< 3)
3345 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3346 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3347 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3348 mips_opts
.warn_about_macros
),
3349 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3352 /* We need a nop before loading from $gp. This special
3353 check is required because the lui which starts the main
3354 instruction stream does not refer to $gp, and so will not
3355 insert the nop which may be required. */
3356 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3359 macro_build (p
, counter
, ep
,
3360 ((bfd_arch_bits_per_address (stdoutput
) == 32
3361 || mips_opts
.isa
< 3)
3363 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3365 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3367 macro_build (p
, counter
, ep
,
3368 ((bfd_arch_bits_per_address (stdoutput
) == 32
3369 || mips_opts
.isa
< 3)
3370 ? "addiu" : "daddiu"),
3371 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3372 if (ex
.X_add_number
!= 0)
3374 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3375 as_bad ("PIC code offset overflow (max 16 signed bits)");
3376 ex
.X_op
= O_constant
;
3377 macro_build ((char *) NULL
, counter
, &ex
,
3378 ((bfd_arch_bits_per_address (stdoutput
) == 32
3379 || mips_opts
.isa
< 3)
3380 ? "addiu" : "daddiu"),
3381 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3384 else if (mips_pic
== EMBEDDED_PIC
)
3387 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3389 macro_build ((char *) NULL
, counter
, ep
,
3390 ((bfd_arch_bits_per_address (stdoutput
) == 32
3391 || mips_opts
.isa
< 3)
3392 ? "addiu" : "daddiu"),
3393 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3401 * This routine implements the seemingly endless macro or synthesized
3402 * instructions and addressing modes in the mips assembly language. Many
3403 * of these macros are simple and are similar to each other. These could
3404 * probably be handled by some kind of table or grammer aproach instead of
3405 * this verbose method. Others are not simple macros but are more like
3406 * optimizing code generation.
3407 * One interesting optimization is when several store macros appear
3408 * consecutivly that would load AT with the upper half of the same address.
3409 * The ensuing load upper instructions are ommited. This implies some kind
3410 * of global optimization. We currently only optimize within a single macro.
3411 * For many of the load and store macros if the address is specified as a
3412 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3413 * first load register 'at' with zero and use it as the base register. The
3414 * mips assembler simply uses register $zero. Just one tiny optimization
3419 struct mips_cl_insn
*ip
;
3421 register int treg
, sreg
, dreg
, breg
;
3436 bfd_reloc_code_real_type r
;
3438 int hold_mips_optimize
;
3440 assert (! mips_opts
.mips16
);
3442 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3443 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3444 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3445 mask
= ip
->insn_mo
->mask
;
3447 expr1
.X_op
= O_constant
;
3448 expr1
.X_op_symbol
= NULL
;
3449 expr1
.X_add_symbol
= NULL
;
3450 expr1
.X_add_number
= 1;
3462 mips_emit_delays (true);
3463 ++mips_opts
.noreorder
;
3464 mips_any_noreorder
= 1;
3466 expr1
.X_add_number
= 8;
3467 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3469 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3471 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3472 macro_build ((char *) NULL
, &icnt
, NULL
,
3473 dbl
? "dsub" : "sub",
3474 "d,v,t", dreg
, 0, sreg
);
3476 --mips_opts
.noreorder
;
3497 if (imm_expr
.X_op
== O_constant
3498 && imm_expr
.X_add_number
>= -0x8000
3499 && imm_expr
.X_add_number
< 0x8000)
3501 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3502 (int) BFD_RELOC_LO16
);
3505 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3506 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3525 if (imm_expr
.X_op
== O_constant
3526 && imm_expr
.X_add_number
>= 0
3527 && imm_expr
.X_add_number
< 0x10000)
3529 if (mask
!= M_NOR_I
)
3530 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3531 sreg
, (int) BFD_RELOC_LO16
);
3534 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3535 treg
, sreg
, (int) BFD_RELOC_LO16
);
3536 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3542 load_register (&icnt
, AT
, &imm_expr
, 0);
3543 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3560 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3562 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3566 load_register (&icnt
, AT
, &imm_expr
, 0);
3567 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3575 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3576 likely
? "bgezl" : "bgez",
3582 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3583 likely
? "blezl" : "blez",
3587 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3588 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3589 likely
? "beql" : "beq",
3596 /* check for > max integer */
3597 maxnum
= 0x7fffffff;
3598 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3605 if (imm_expr
.X_op
== O_constant
3606 && imm_expr
.X_add_number
>= maxnum
3607 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3610 /* result is always false */
3613 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3614 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3618 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3619 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3624 if (imm_expr
.X_op
!= O_constant
)
3625 as_bad ("Unsupported large constant");
3626 imm_expr
.X_add_number
++;
3630 if (mask
== M_BGEL_I
)
3632 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3634 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3635 likely
? "bgezl" : "bgez",
3639 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3641 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3642 likely
? "bgtzl" : "bgtz",
3646 maxnum
= 0x7fffffff;
3647 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3654 maxnum
= - maxnum
- 1;
3655 if (imm_expr
.X_op
== O_constant
3656 && imm_expr
.X_add_number
<= maxnum
3657 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3660 /* result is always true */
3661 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3662 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3665 set_at (&icnt
, sreg
, 0);
3666 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3667 likely
? "beql" : "beq",
3678 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3679 likely
? "beql" : "beq",
3683 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3685 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3686 likely
? "beql" : "beq",
3694 || (mips_opts
.isa
< 3
3695 && imm_expr
.X_op
== O_constant
3696 && imm_expr
.X_add_number
== 0xffffffff))
3698 if (imm_expr
.X_op
!= O_constant
)
3699 as_bad ("Unsupported large constant");
3700 imm_expr
.X_add_number
++;
3704 if (mask
== M_BGEUL_I
)
3706 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3708 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3710 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3711 likely
? "bnel" : "bne",
3715 set_at (&icnt
, sreg
, 1);
3716 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3717 likely
? "beql" : "beq",
3726 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3727 likely
? "bgtzl" : "bgtz",
3733 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3734 likely
? "bltzl" : "bltz",
3738 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3739 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3740 likely
? "bnel" : "bne",
3749 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3750 likely
? "bnel" : "bne",
3756 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3758 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3759 likely
? "bnel" : "bne",
3768 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3769 likely
? "blezl" : "blez",
3775 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3776 likely
? "bgezl" : "bgez",
3780 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3781 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3782 likely
? "beql" : "beq",
3789 maxnum
= 0x7fffffff;
3790 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3797 if (imm_expr
.X_op
== O_constant
3798 && imm_expr
.X_add_number
>= maxnum
3799 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3801 if (imm_expr
.X_op
!= O_constant
)
3802 as_bad ("Unsupported large constant");
3803 imm_expr
.X_add_number
++;
3807 if (mask
== M_BLTL_I
)
3809 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3812 likely
? "bltzl" : "bltz",
3816 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3818 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3819 likely
? "blezl" : "blez",
3823 set_at (&icnt
, sreg
, 0);
3824 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3825 likely
? "bnel" : "bne",
3834 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3835 likely
? "beql" : "beq",
3841 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3843 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3844 likely
? "beql" : "beq",
3852 || (mips_opts
.isa
< 3
3853 && imm_expr
.X_op
== O_constant
3854 && imm_expr
.X_add_number
== 0xffffffff))
3856 if (imm_expr
.X_op
!= O_constant
)
3857 as_bad ("Unsupported large constant");
3858 imm_expr
.X_add_number
++;
3862 if (mask
== M_BLTUL_I
)
3864 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3866 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3868 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3869 likely
? "beql" : "beq",
3873 set_at (&icnt
, sreg
, 1);
3874 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3875 likely
? "bnel" : "bne",
3884 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3885 likely
? "bltzl" : "bltz",
3891 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3892 likely
? "bgtzl" : "bgtz",
3896 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3897 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3898 likely
? "bnel" : "bne",
3909 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3910 likely
? "bnel" : "bne",
3914 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3916 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3917 likely
? "bnel" : "bne",
3933 as_warn ("Divide by zero.");
3935 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3937 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3941 mips_emit_delays (true);
3942 ++mips_opts
.noreorder
;
3943 mips_any_noreorder
= 1;
3946 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3947 macro_build ((char *) NULL
, &icnt
, NULL
,
3948 dbl
? "ddiv" : "div",
3949 "z,s,t", sreg
, treg
);
3953 expr1
.X_add_number
= 8;
3954 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3955 macro_build ((char *) NULL
, &icnt
, NULL
,
3956 dbl
? "ddiv" : "div",
3957 "z,s,t", sreg
, treg
);
3958 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3960 expr1
.X_add_number
= -1;
3961 macro_build ((char *) NULL
, &icnt
, &expr1
,
3962 dbl
? "daddiu" : "addiu",
3963 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3964 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3965 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3968 expr1
.X_add_number
= 1;
3969 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3970 (int) BFD_RELOC_LO16
);
3971 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3976 expr1
.X_add_number
= 0x80000000;
3977 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3978 (int) BFD_RELOC_HI16
);
3981 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3984 expr1
.X_add_number
= 8;
3985 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3986 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3987 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3989 --mips_opts
.noreorder
;
3990 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4029 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4031 as_warn ("Divide by zero.");
4033 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4035 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4038 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4040 if (strcmp (s2
, "mflo") == 0)
4041 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4044 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4047 if (imm_expr
.X_op
== O_constant
4048 && imm_expr
.X_add_number
== -1
4049 && s
[strlen (s
) - 1] != 'u')
4051 if (strcmp (s2
, "mflo") == 0)
4054 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4057 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4061 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4065 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4066 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4067 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4086 mips_emit_delays (true);
4087 ++mips_opts
.noreorder
;
4088 mips_any_noreorder
= 1;
4091 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4092 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4096 expr1
.X_add_number
= 8;
4097 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4098 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4099 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4101 --mips_opts
.noreorder
;
4102 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4108 /* Load the address of a symbol into a register. If breg is not
4109 zero, we then add a base register to it. */
4111 /* When generating embedded PIC code, we permit expressions of
4114 where bar is an address in the .text section. These are used
4115 when getting the addresses of functions. We don't permit
4116 X_add_number to be non-zero, because if the symbol is
4117 external the relaxing code needs to know that any addend is
4118 purely the offset to X_op_symbol. */
4119 if (mips_pic
== EMBEDDED_PIC
4120 && offset_expr
.X_op
== O_subtract
4121 && now_seg
== text_section
4122 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4123 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4124 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4125 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4126 ->sy_value
.X_add_symbol
)
4129 && offset_expr
.X_add_number
== 0)
4131 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4132 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4133 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4134 ((bfd_arch_bits_per_address (stdoutput
) == 32
4135 || mips_opts
.isa
< 3)
4136 ? "addiu" : "daddiu"),
4137 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4141 if (offset_expr
.X_op
!= O_symbol
4142 && offset_expr
.X_op
!= O_constant
)
4144 as_bad ("expression too complex");
4145 offset_expr
.X_op
= O_constant
;
4159 if (offset_expr
.X_op
== O_constant
)
4160 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4161 else if (mips_pic
== NO_PIC
)
4163 /* If this is a reference to an GP relative symbol, we want
4164 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4166 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4167 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4168 If we have a constant, we need two instructions anyhow,
4169 so we may as well always use the latter form. */
4170 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4171 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4176 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4177 ((bfd_arch_bits_per_address (stdoutput
) == 32
4178 || mips_opts
.isa
< 3)
4179 ? "addiu" : "daddiu"),
4180 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4181 p
= frag_var (rs_machine_dependent
, 8, 0,
4182 RELAX_ENCODE (4, 8, 0, 4, 0,
4183 mips_opts
.warn_about_macros
),
4184 offset_expr
.X_add_symbol
, (offsetT
) 0,
4187 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4190 macro_build (p
, &icnt
, &offset_expr
,
4191 ((bfd_arch_bits_per_address (stdoutput
) == 32
4192 || mips_opts
.isa
< 3)
4193 ? "addiu" : "daddiu"),
4194 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4196 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4198 /* If this is a reference to an external symbol, and there
4199 is no constant, we want
4200 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4201 For a local symbol, we want
4202 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4204 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4206 If we have a small constant, and this is a reference to
4207 an external symbol, we want
4208 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4210 addiu $tempreg,$tempreg,<constant>
4211 For a local symbol, we want the same instruction
4212 sequence, but we output a BFD_RELOC_LO16 reloc on the
4215 If we have a large constant, and this is a reference to
4216 an external symbol, we want
4217 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4218 lui $at,<hiconstant>
4219 addiu $at,$at,<loconstant>
4220 addu $tempreg,$tempreg,$at
4221 For a local symbol, we want the same instruction
4222 sequence, but we output a BFD_RELOC_LO16 reloc on the
4223 addiu instruction. */
4224 expr1
.X_add_number
= offset_expr
.X_add_number
;
4225 offset_expr
.X_add_number
= 0;
4227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4229 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4230 if (expr1
.X_add_number
== 0)
4238 /* We're going to put in an addu instruction using
4239 tempreg, so we may as well insert the nop right
4241 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4245 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4246 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4248 ? mips_opts
.warn_about_macros
4250 offset_expr
.X_add_symbol
, (offsetT
) 0,
4254 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4257 macro_build (p
, &icnt
, &expr1
,
4258 ((bfd_arch_bits_per_address (stdoutput
) == 32
4259 || mips_opts
.isa
< 3)
4260 ? "addiu" : "daddiu"),
4261 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4262 /* FIXME: If breg == 0, and the next instruction uses
4263 $tempreg, then if this variant case is used an extra
4264 nop will be generated. */
4266 else if (expr1
.X_add_number
>= -0x8000
4267 && expr1
.X_add_number
< 0x8000)
4269 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4271 macro_build ((char *) NULL
, &icnt
, &expr1
,
4272 ((bfd_arch_bits_per_address (stdoutput
) == 32
4273 || mips_opts
.isa
< 3)
4274 ? "addiu" : "daddiu"),
4275 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4276 (void) frag_var (rs_machine_dependent
, 0, 0,
4277 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4278 offset_expr
.X_add_symbol
, (offsetT
) 0,
4285 /* If we are going to add in a base register, and the
4286 target register and the base register are the same,
4287 then we are using AT as a temporary register. Since
4288 we want to load the constant into AT, we add our
4289 current AT (from the global offset table) and the
4290 register into the register now, and pretend we were
4291 not using a base register. */
4296 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4299 ((bfd_arch_bits_per_address (stdoutput
) == 32
4300 || mips_opts
.isa
< 3)
4301 ? "addu" : "daddu"),
4302 "d,v,t", treg
, AT
, breg
);
4308 /* Set mips_optimize around the lui instruction to avoid
4309 inserting an unnecessary nop after the lw. */
4310 hold_mips_optimize
= mips_optimize
;
4312 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4313 mips_optimize
= hold_mips_optimize
;
4315 macro_build ((char *) NULL
, &icnt
, &expr1
,
4316 ((bfd_arch_bits_per_address (stdoutput
) == 32
4317 || mips_opts
.isa
< 3)
4318 ? "addiu" : "daddiu"),
4319 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4321 ((bfd_arch_bits_per_address (stdoutput
) == 32
4322 || mips_opts
.isa
< 3)
4323 ? "addu" : "daddu"),
4324 "d,v,t", tempreg
, tempreg
, AT
);
4325 (void) frag_var (rs_machine_dependent
, 0, 0,
4326 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4327 offset_expr
.X_add_symbol
, (offsetT
) 0,
4332 else if (mips_pic
== SVR4_PIC
)
4336 /* This is the large GOT case. If this is a reference to an
4337 external symbol, and there is no constant, we want
4338 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4339 addu $tempreg,$tempreg,$gp
4340 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4341 For a local symbol, we want
4342 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4344 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4346 If we have a small constant, and this is a reference to
4347 an external symbol, we want
4348 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4349 addu $tempreg,$tempreg,$gp
4350 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4352 addiu $tempreg,$tempreg,<constant>
4353 For a local symbol, we want
4354 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4356 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4358 If we have a large constant, and this is a reference to
4359 an external symbol, we want
4360 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4361 addu $tempreg,$tempreg,$gp
4362 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4363 lui $at,<hiconstant>
4364 addiu $at,$at,<loconstant>
4365 addu $tempreg,$tempreg,$at
4366 For a local symbol, we want
4367 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4368 lui $at,<hiconstant>
4369 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4370 addu $tempreg,$tempreg,$at
4372 expr1
.X_add_number
= offset_expr
.X_add_number
;
4373 offset_expr
.X_add_number
= 0;
4375 if (reg_needs_delay (GP
))
4379 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4380 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4382 ((bfd_arch_bits_per_address (stdoutput
) == 32
4383 || mips_opts
.isa
< 3)
4384 ? "addu" : "daddu"),
4385 "d,v,t", tempreg
, tempreg
, GP
);
4386 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4388 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4390 if (expr1
.X_add_number
== 0)
4398 /* We're going to put in an addu instruction using
4399 tempreg, so we may as well insert the nop right
4401 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4406 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4407 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4410 ? mips_opts
.warn_about_macros
4412 offset_expr
.X_add_symbol
, (offsetT
) 0,
4415 else if (expr1
.X_add_number
>= -0x8000
4416 && expr1
.X_add_number
< 0x8000)
4418 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4420 macro_build ((char *) NULL
, &icnt
, &expr1
,
4421 ((bfd_arch_bits_per_address (stdoutput
) == 32
4422 || mips_opts
.isa
< 3)
4423 ? "addiu" : "daddiu"),
4424 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4426 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4427 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4429 ? mips_opts
.warn_about_macros
4431 offset_expr
.X_add_symbol
, (offsetT
) 0,
4438 /* If we are going to add in a base register, and the
4439 target register and the base register are the same,
4440 then we are using AT as a temporary register. Since
4441 we want to load the constant into AT, we add our
4442 current AT (from the global offset table) and the
4443 register into the register now, and pretend we were
4444 not using a base register. */
4452 assert (tempreg
== AT
);
4453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4455 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4456 ((bfd_arch_bits_per_address (stdoutput
) == 32
4457 || mips_opts
.isa
< 3)
4458 ? "addu" : "daddu"),
4459 "d,v,t", treg
, AT
, breg
);
4464 /* Set mips_optimize around the lui instruction to avoid
4465 inserting an unnecessary nop after the lw. */
4466 hold_mips_optimize
= mips_optimize
;
4468 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4469 mips_optimize
= hold_mips_optimize
;
4471 macro_build ((char *) NULL
, &icnt
, &expr1
,
4472 ((bfd_arch_bits_per_address (stdoutput
) == 32
4473 || mips_opts
.isa
< 3)
4474 ? "addiu" : "daddiu"),
4475 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4477 ((bfd_arch_bits_per_address (stdoutput
) == 32
4478 || mips_opts
.isa
< 3)
4479 ? "addu" : "daddu"),
4480 "d,v,t", dreg
, dreg
, AT
);
4482 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4483 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4486 ? mips_opts
.warn_about_macros
4488 offset_expr
.X_add_symbol
, (offsetT
) 0,
4496 /* This is needed because this instruction uses $gp, but
4497 the first instruction on the main stream does not. */
4498 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4501 macro_build (p
, &icnt
, &offset_expr
,
4503 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4505 if (expr1
.X_add_number
>= -0x8000
4506 && expr1
.X_add_number
< 0x8000)
4508 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4510 macro_build (p
, &icnt
, &expr1
,
4511 ((bfd_arch_bits_per_address (stdoutput
) == 32
4512 || mips_opts
.isa
< 3)
4513 ? "addiu" : "daddiu"),
4514 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4515 /* FIXME: If add_number is 0, and there was no base
4516 register, the external symbol case ended with a load,
4517 so if the symbol turns out to not be external, and
4518 the next instruction uses tempreg, an unnecessary nop
4519 will be inserted. */
4525 /* We must add in the base register now, as in the
4526 external symbol case. */
4527 assert (tempreg
== AT
);
4528 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4530 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4531 ((bfd_arch_bits_per_address (stdoutput
) == 32
4532 || mips_opts
.isa
< 3)
4533 ? "addu" : "daddu"),
4534 "d,v,t", treg
, AT
, breg
);
4537 /* We set breg to 0 because we have arranged to add
4538 it in in both cases. */
4542 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4544 macro_build (p
, &icnt
, &expr1
,
4545 ((bfd_arch_bits_per_address (stdoutput
) == 32
4546 || mips_opts
.isa
< 3)
4547 ? "addiu" : "daddiu"),
4548 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4550 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4551 ((bfd_arch_bits_per_address (stdoutput
) == 32
4552 || mips_opts
.isa
< 3)
4553 ? "addu" : "daddu"),
4554 "d,v,t", tempreg
, tempreg
, AT
);
4558 else if (mips_pic
== EMBEDDED_PIC
)
4561 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4563 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4564 ((bfd_arch_bits_per_address (stdoutput
) == 32
4565 || mips_opts
.isa
< 3)
4566 ? "addiu" : "daddiu"),
4567 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4573 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4574 ((bfd_arch_bits_per_address (stdoutput
) == 32
4575 || mips_opts
.isa
< 3)
4576 ? "addu" : "daddu"),
4577 "d,v,t", treg
, tempreg
, breg
);
4585 /* The j instruction may not be used in PIC code, since it
4586 requires an absolute address. We convert it to a b
4588 if (mips_pic
== NO_PIC
)
4589 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4591 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4594 /* The jal instructions must be handled as macros because when
4595 generating PIC code they expand to multi-instruction
4596 sequences. Normally they are simple instructions. */
4601 if (mips_pic
== NO_PIC
4602 || mips_pic
== EMBEDDED_PIC
)
4603 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4605 else if (mips_pic
== SVR4_PIC
)
4607 if (sreg
!= PIC_CALL_REG
)
4608 as_warn ("MIPS PIC call to register other than $25");
4610 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4612 if (mips_cprestore_offset
< 0)
4613 as_warn ("No .cprestore pseudo-op used in PIC code");
4616 expr1
.X_add_number
= mips_cprestore_offset
;
4617 macro_build ((char *) NULL
, &icnt
, &expr1
,
4618 ((bfd_arch_bits_per_address (stdoutput
) == 32
4619 || mips_opts
.isa
< 3)
4621 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4630 if (mips_pic
== NO_PIC
)
4631 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4632 else if (mips_pic
== SVR4_PIC
)
4634 /* If this is a reference to an external symbol, and we are
4635 using a small GOT, we want
4636 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4640 lw $gp,cprestore($sp)
4641 The cprestore value is set using the .cprestore
4642 pseudo-op. If we are using a big GOT, we want
4643 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4645 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4649 lw $gp,cprestore($sp)
4650 If the symbol is not external, we want
4651 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4653 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4656 lw $gp,cprestore($sp) */
4660 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4661 ((bfd_arch_bits_per_address (stdoutput
) == 32
4662 || mips_opts
.isa
< 3)
4664 "t,o(b)", PIC_CALL_REG
,
4665 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4666 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4668 p
= frag_var (rs_machine_dependent
, 4, 0,
4669 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4670 offset_expr
.X_add_symbol
, (offsetT
) 0,
4677 if (reg_needs_delay (GP
))
4681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4682 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4684 ((bfd_arch_bits_per_address (stdoutput
) == 32
4685 || mips_opts
.isa
< 3)
4686 ? "addu" : "daddu"),
4687 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4688 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4689 ((bfd_arch_bits_per_address (stdoutput
) == 32
4690 || mips_opts
.isa
< 3)
4692 "t,o(b)", PIC_CALL_REG
,
4693 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4694 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4696 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4697 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4699 offset_expr
.X_add_symbol
, (offsetT
) 0,
4703 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4706 macro_build (p
, &icnt
, &offset_expr
,
4707 ((bfd_arch_bits_per_address (stdoutput
) == 32
4708 || mips_opts
.isa
< 3)
4710 "t,o(b)", PIC_CALL_REG
,
4711 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4713 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4716 macro_build (p
, &icnt
, &offset_expr
,
4717 ((bfd_arch_bits_per_address (stdoutput
) == 32
4718 || mips_opts
.isa
< 3)
4719 ? "addiu" : "daddiu"),
4720 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4721 (int) BFD_RELOC_LO16
);
4722 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4723 "jalr", "s", PIC_CALL_REG
);
4724 if (mips_cprestore_offset
< 0)
4725 as_warn ("No .cprestore pseudo-op used in PIC code");
4728 if (mips_opts
.noreorder
)
4729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4731 expr1
.X_add_number
= mips_cprestore_offset
;
4732 macro_build ((char *) NULL
, &icnt
, &expr1
,
4733 ((bfd_arch_bits_per_address (stdoutput
) == 32
4734 || mips_opts
.isa
< 3)
4736 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4740 else if (mips_pic
== EMBEDDED_PIC
)
4742 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4743 /* The linker may expand the call to a longer sequence which
4744 uses $at, so we must break rather than return. */
4769 /* Itbl support may require additional care here. */
4774 /* Itbl support may require additional care here. */
4779 /* Itbl support may require additional care here. */
4784 /* Itbl support may require additional care here. */
4798 as_bad ("opcode not supported on this processor");
4802 /* Itbl support may require additional care here. */
4807 /* Itbl support may require additional care here. */
4812 /* Itbl support may require additional care here. */
4832 if (breg
== treg
|| coproc
|| lr
)
4854 /* Itbl support may require additional care here. */
4859 /* Itbl support may require additional care here. */
4864 /* Itbl support may require additional care here. */
4869 /* Itbl support may require additional care here. */
4887 as_bad ("opcode not supported on this processor");
4892 /* Itbl support may require additional care here. */
4896 /* Itbl support may require additional care here. */
4901 /* Itbl support may require additional care here. */
4913 /* Itbl support may require additional care here. */
4914 if (mask
== M_LWC1_AB
4915 || mask
== M_SWC1_AB
4916 || mask
== M_LDC1_AB
4917 || mask
== M_SDC1_AB
4926 if (offset_expr
.X_op
!= O_constant
4927 && offset_expr
.X_op
!= O_symbol
)
4929 as_bad ("expression too complex");
4930 offset_expr
.X_op
= O_constant
;
4933 /* A constant expression in PIC code can be handled just as it
4934 is in non PIC code. */
4935 if (mips_pic
== NO_PIC
4936 || offset_expr
.X_op
== O_constant
)
4938 /* If this is a reference to a GP relative symbol, and there
4939 is no base register, we want
4940 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4941 Otherwise, if there is no base register, we want
4942 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4943 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4944 If we have a constant, we need two instructions anyhow,
4945 so we always use the latter form.
4947 If we have a base register, and this is a reference to a
4948 GP relative symbol, we want
4949 addu $tempreg,$breg,$gp
4950 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4952 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4953 addu $tempreg,$tempreg,$breg
4954 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4955 With a constant we always use the latter case. */
4958 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4959 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4964 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4965 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4966 p
= frag_var (rs_machine_dependent
, 8, 0,
4967 RELAX_ENCODE (4, 8, 0, 4, 0,
4968 (mips_opts
.warn_about_macros
4970 && mips_opts
.noat
))),
4971 offset_expr
.X_add_symbol
, (offsetT
) 0,
4975 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4978 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4979 (int) BFD_RELOC_LO16
, tempreg
);
4983 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4984 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4990 ((bfd_arch_bits_per_address (stdoutput
) == 32
4991 || mips_opts
.isa
< 3)
4992 ? "addu" : "daddu"),
4993 "d,v,t", tempreg
, breg
, GP
);
4994 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4995 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4996 p
= frag_var (rs_machine_dependent
, 12, 0,
4997 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4998 offset_expr
.X_add_symbol
, (offsetT
) 0,
5001 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5004 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5005 ((bfd_arch_bits_per_address (stdoutput
) == 32
5006 || mips_opts
.isa
< 3)
5007 ? "addu" : "daddu"),
5008 "d,v,t", tempreg
, tempreg
, breg
);
5011 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5012 (int) BFD_RELOC_LO16
, tempreg
);
5015 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5017 /* If this is a reference to an external symbol, we want
5018 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5020 <op> $treg,0($tempreg)
5022 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5024 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5025 <op> $treg,0($tempreg)
5026 If there is a base register, we add it to $tempreg before
5027 the <op>. If there is a constant, we stick it in the
5028 <op> instruction. We don't handle constants larger than
5029 16 bits, because we have no way to load the upper 16 bits
5030 (actually, we could handle them for the subset of cases
5031 in which we are not using $at). */
5032 assert (offset_expr
.X_op
== O_symbol
);
5033 expr1
.X_add_number
= offset_expr
.X_add_number
;
5034 offset_expr
.X_add_number
= 0;
5035 if (expr1
.X_add_number
< -0x8000
5036 || expr1
.X_add_number
>= 0x8000)
5037 as_bad ("PIC code offset overflow (max 16 signed bits)");
5039 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5040 ((bfd_arch_bits_per_address (stdoutput
) == 32
5041 || mips_opts
.isa
< 3)
5043 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5045 p
= frag_var (rs_machine_dependent
, 4, 0,
5046 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5047 offset_expr
.X_add_symbol
, (offsetT
) 0,
5049 macro_build (p
, &icnt
, &offset_expr
,
5050 ((bfd_arch_bits_per_address (stdoutput
) == 32
5051 || mips_opts
.isa
< 3)
5052 ? "addiu" : "daddiu"),
5053 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5055 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5056 ((bfd_arch_bits_per_address (stdoutput
) == 32
5057 || mips_opts
.isa
< 3)
5058 ? "addu" : "daddu"),
5059 "d,v,t", tempreg
, tempreg
, breg
);
5060 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5061 (int) BFD_RELOC_LO16
, tempreg
);
5063 else if (mips_pic
== SVR4_PIC
)
5067 /* If this is a reference to an external symbol, we want
5068 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5069 addu $tempreg,$tempreg,$gp
5070 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5071 <op> $treg,0($tempreg)
5073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5075 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5076 <op> $treg,0($tempreg)
5077 If there is a base register, we add it to $tempreg before
5078 the <op>. If there is a constant, we stick it in the
5079 <op> instruction. We don't handle constants larger than
5080 16 bits, because we have no way to load the upper 16 bits
5081 (actually, we could handle them for the subset of cases
5082 in which we are not using $at). */
5083 assert (offset_expr
.X_op
== O_symbol
);
5084 expr1
.X_add_number
= offset_expr
.X_add_number
;
5085 offset_expr
.X_add_number
= 0;
5086 if (expr1
.X_add_number
< -0x8000
5087 || expr1
.X_add_number
>= 0x8000)
5088 as_bad ("PIC code offset overflow (max 16 signed bits)");
5089 if (reg_needs_delay (GP
))
5094 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5095 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5096 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5097 ((bfd_arch_bits_per_address (stdoutput
) == 32
5098 || mips_opts
.isa
< 3)
5099 ? "addu" : "daddu"),
5100 "d,v,t", tempreg
, tempreg
, GP
);
5101 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5102 ((bfd_arch_bits_per_address (stdoutput
) == 32
5103 || mips_opts
.isa
< 3)
5105 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5107 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5108 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5109 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5112 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5115 macro_build (p
, &icnt
, &offset_expr
,
5116 ((bfd_arch_bits_per_address (stdoutput
) == 32
5117 || mips_opts
.isa
< 3)
5119 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5121 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5123 macro_build (p
, &icnt
, &offset_expr
,
5124 ((bfd_arch_bits_per_address (stdoutput
) == 32
5125 || mips_opts
.isa
< 3)
5126 ? "addiu" : "daddiu"),
5127 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5129 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5130 ((bfd_arch_bits_per_address (stdoutput
) == 32
5131 || mips_opts
.isa
< 3)
5132 ? "addu" : "daddu"),
5133 "d,v,t", tempreg
, tempreg
, breg
);
5134 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5135 (int) BFD_RELOC_LO16
, tempreg
);
5137 else if (mips_pic
== EMBEDDED_PIC
)
5139 /* If there is no base register, we want
5140 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5141 If there is a base register, we want
5142 addu $tempreg,$breg,$gp
5143 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5145 assert (offset_expr
.X_op
== O_symbol
);
5148 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5149 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5155 ((bfd_arch_bits_per_address (stdoutput
) == 32
5156 || mips_opts
.isa
< 3)
5157 ? "addu" : "daddu"),
5158 "d,v,t", tempreg
, breg
, GP
);
5159 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5160 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5173 load_register (&icnt
, treg
, &imm_expr
, 0);
5177 load_register (&icnt
, treg
, &imm_expr
, 1);
5181 if (imm_expr
.X_op
== O_constant
)
5183 load_register (&icnt
, AT
, &imm_expr
, 0);
5184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5185 "mtc1", "t,G", AT
, treg
);
5190 assert (offset_expr
.X_op
== O_symbol
5191 && strcmp (segment_name (S_GET_SEGMENT
5192 (offset_expr
.X_add_symbol
)),
5194 && offset_expr
.X_add_number
== 0);
5195 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5196 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5201 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5202 the entire value, and in mips1 mode it is the high order 32
5203 bits of the value and the low order 32 bits are either zero
5204 or in offset_expr. */
5205 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5207 if (mips_opts
.isa
>= 3)
5208 load_register (&icnt
, treg
, &imm_expr
, 1);
5213 if (target_big_endian
)
5225 load_register (&icnt
, hreg
, &imm_expr
, 0);
5228 if (offset_expr
.X_op
== O_absent
)
5229 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5233 assert (offset_expr
.X_op
== O_constant
);
5234 load_register (&icnt
, lreg
, &offset_expr
, 0);
5241 /* We know that sym is in the .rdata section. First we get the
5242 upper 16 bits of the address. */
5243 if (mips_pic
== NO_PIC
)
5245 /* FIXME: This won't work for a 64 bit address. */
5246 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5248 else if (mips_pic
== SVR4_PIC
)
5250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5251 ((bfd_arch_bits_per_address (stdoutput
) == 32
5252 || mips_opts
.isa
< 3)
5254 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5256 else if (mips_pic
== EMBEDDED_PIC
)
5258 /* For embedded PIC we pick up the entire address off $gp in
5259 a single instruction. */
5260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5261 ((bfd_arch_bits_per_address (stdoutput
) == 32
5262 || mips_opts
.isa
< 3)
5263 ? "addiu" : "daddiu"),
5264 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5265 offset_expr
.X_op
= O_constant
;
5266 offset_expr
.X_add_number
= 0;
5271 /* Now we load the register(s). */
5272 if (mips_opts
.isa
>= 3)
5273 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5274 treg
, (int) BFD_RELOC_LO16
, AT
);
5277 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5278 treg
, (int) BFD_RELOC_LO16
, AT
);
5281 /* FIXME: How in the world do we deal with the possible
5283 offset_expr
.X_add_number
+= 4;
5284 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5285 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5289 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5290 does not become a variant frag. */
5291 frag_wane (frag_now
);
5297 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5298 the entire value, and in mips1 mode it is the high order 32
5299 bits of the value and the low order 32 bits are either zero
5300 or in offset_expr. */
5301 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5303 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5304 if (mips_opts
.isa
>= 3)
5305 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5306 "dmtc1", "t,S", AT
, treg
);
5309 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5310 "mtc1", "t,G", AT
, treg
+ 1);
5311 if (offset_expr
.X_op
== O_absent
)
5312 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5313 "mtc1", "t,G", 0, treg
);
5316 assert (offset_expr
.X_op
== O_constant
);
5317 load_register (&icnt
, AT
, &offset_expr
, 0);
5318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5319 "mtc1", "t,G", AT
, treg
);
5325 assert (offset_expr
.X_op
== O_symbol
5326 && offset_expr
.X_add_number
== 0);
5327 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5328 if (strcmp (s
, ".lit8") == 0)
5330 if (mips_opts
.isa
>= 2)
5332 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5333 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5337 r
= BFD_RELOC_MIPS_LITERAL
;
5342 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5343 if (mips_pic
== SVR4_PIC
)
5344 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5345 ((bfd_arch_bits_per_address (stdoutput
) == 32
5346 || mips_opts
.isa
< 3)
5348 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5351 /* FIXME: This won't work for a 64 bit address. */
5352 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5355 if (mips_opts
.isa
>= 2)
5357 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5358 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5360 /* To avoid confusion in tc_gen_reloc, we must ensure
5361 that this does not become a variant frag. */
5362 frag_wane (frag_now
);
5375 as_bad ("opcode not supported on this processor");
5378 /* Even on a big endian machine $fn comes before $fn+1. We have
5379 to adjust when loading from memory. */
5382 assert (mips_opts
.isa
< 2);
5383 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5384 target_big_endian
? treg
+ 1 : treg
,
5386 /* FIXME: A possible overflow which I don't know how to deal
5388 offset_expr
.X_add_number
+= 4;
5389 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5390 target_big_endian
? treg
: treg
+ 1,
5393 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5394 does not become a variant frag. */
5395 frag_wane (frag_now
);
5404 * The MIPS assembler seems to check for X_add_number not
5405 * being double aligned and generating:
5408 * addiu at,at,%lo(foo+1)
5411 * But, the resulting address is the same after relocation so why
5412 * generate the extra instruction?
5416 as_bad ("opcode not supported on this processor");
5419 /* Itbl support may require additional care here. */
5421 if (mips_opts
.isa
>= 2)
5434 as_bad ("opcode not supported on this processor");
5438 if (mips_opts
.isa
>= 2)
5446 /* Itbl support may require additional care here. */
5451 if (mips_opts
.isa
>= 3)
5462 if (mips_opts
.isa
>= 3)
5472 if (offset_expr
.X_op
!= O_symbol
5473 && offset_expr
.X_op
!= O_constant
)
5475 as_bad ("expression too complex");
5476 offset_expr
.X_op
= O_constant
;
5479 /* Even on a big endian machine $fn comes before $fn+1. We have
5480 to adjust when loading from memory. We set coproc if we must
5481 load $fn+1 first. */
5482 /* Itbl support may require additional care here. */
5483 if (! target_big_endian
)
5486 if (mips_pic
== NO_PIC
5487 || offset_expr
.X_op
== O_constant
)
5489 /* If this is a reference to a GP relative symbol, we want
5490 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5491 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5492 If we have a base register, we use this
5494 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5495 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5496 If this is not a GP relative symbol, we want
5497 lui $at,<sym> (BFD_RELOC_HI16_S)
5498 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5499 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5500 If there is a base register, we add it to $at after the
5501 lui instruction. If there is a constant, we always use
5503 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5504 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5523 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5524 ((bfd_arch_bits_per_address (stdoutput
) == 32
5525 || mips_opts
.isa
< 3)
5526 ? "addu" : "daddu"),
5527 "d,v,t", AT
, breg
, GP
);
5533 /* Itbl support may require additional care here. */
5534 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5535 coproc
? treg
+ 1 : treg
,
5536 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5537 offset_expr
.X_add_number
+= 4;
5539 /* Set mips_optimize to 2 to avoid inserting an
5541 hold_mips_optimize
= mips_optimize
;
5543 /* Itbl support may require additional care here. */
5544 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5545 coproc
? treg
: treg
+ 1,
5546 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5547 mips_optimize
= hold_mips_optimize
;
5549 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5550 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5551 used_at
&& mips_opts
.noat
),
5552 offset_expr
.X_add_symbol
, (offsetT
) 0,
5555 /* We just generated two relocs. When tc_gen_reloc
5556 handles this case, it will skip the first reloc and
5557 handle the second. The second reloc already has an
5558 extra addend of 4, which we added above. We must
5559 subtract it out, and then subtract another 4 to make
5560 the first reloc come out right. The second reloc
5561 will come out right because we are going to add 4 to
5562 offset_expr when we build its instruction below.
5564 If we have a symbol, then we don't want to include
5565 the offset, because it will wind up being included
5566 when we generate the reloc. */
5568 if (offset_expr
.X_op
== O_constant
)
5569 offset_expr
.X_add_number
-= 8;
5572 offset_expr
.X_add_number
= -4;
5573 offset_expr
.X_op
= O_constant
;
5576 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5581 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5582 ((bfd_arch_bits_per_address (stdoutput
) == 32
5583 || mips_opts
.isa
< 3)
5584 ? "addu" : "daddu"),
5585 "d,v,t", AT
, breg
, AT
);
5589 /* Itbl support may require additional care here. */
5590 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5591 coproc
? treg
+ 1 : treg
,
5592 (int) BFD_RELOC_LO16
, AT
);
5595 /* FIXME: How do we handle overflow here? */
5596 offset_expr
.X_add_number
+= 4;
5597 /* Itbl support may require additional care here. */
5598 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5599 coproc
? treg
: treg
+ 1,
5600 (int) BFD_RELOC_LO16
, AT
);
5602 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5606 /* If this is a reference to an external symbol, we want
5607 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5612 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5614 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5615 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5616 If there is a base register we add it to $at before the
5617 lwc1 instructions. If there is a constant we include it
5618 in the lwc1 instructions. */
5620 expr1
.X_add_number
= offset_expr
.X_add_number
;
5621 offset_expr
.X_add_number
= 0;
5622 if (expr1
.X_add_number
< -0x8000
5623 || expr1
.X_add_number
>= 0x8000 - 4)
5624 as_bad ("PIC code offset overflow (max 16 signed bits)");
5629 frag_grow (24 + off
);
5630 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5631 ((bfd_arch_bits_per_address (stdoutput
) == 32
5632 || mips_opts
.isa
< 3)
5634 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5635 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5638 ((bfd_arch_bits_per_address (stdoutput
) == 32
5639 || mips_opts
.isa
< 3)
5640 ? "addu" : "daddu"),
5641 "d,v,t", AT
, breg
, AT
);
5642 /* Itbl support may require additional care here. */
5643 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5644 coproc
? treg
+ 1 : treg
,
5645 (int) BFD_RELOC_LO16
, AT
);
5646 expr1
.X_add_number
+= 4;
5648 /* Set mips_optimize to 2 to avoid inserting an undesired
5650 hold_mips_optimize
= mips_optimize
;
5652 /* Itbl support may require additional care here. */
5653 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5654 coproc
? treg
: treg
+ 1,
5655 (int) BFD_RELOC_LO16
, AT
);
5656 mips_optimize
= hold_mips_optimize
;
5658 (void) frag_var (rs_machine_dependent
, 0, 0,
5659 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5660 offset_expr
.X_add_symbol
, (offsetT
) 0,
5663 else if (mips_pic
== SVR4_PIC
)
5667 /* If this is a reference to an external symbol, we want
5668 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5670 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5675 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5677 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5678 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5679 If there is a base register we add it to $at before the
5680 lwc1 instructions. If there is a constant we include it
5681 in the lwc1 instructions. */
5683 expr1
.X_add_number
= offset_expr
.X_add_number
;
5684 offset_expr
.X_add_number
= 0;
5685 if (expr1
.X_add_number
< -0x8000
5686 || expr1
.X_add_number
>= 0x8000 - 4)
5687 as_bad ("PIC code offset overflow (max 16 signed bits)");
5688 if (reg_needs_delay (GP
))
5697 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5698 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5700 ((bfd_arch_bits_per_address (stdoutput
) == 32
5701 || mips_opts
.isa
< 3)
5702 ? "addu" : "daddu"),
5703 "d,v,t", AT
, AT
, GP
);
5704 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5705 ((bfd_arch_bits_per_address (stdoutput
) == 32
5706 || mips_opts
.isa
< 3)
5708 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5709 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5711 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5712 ((bfd_arch_bits_per_address (stdoutput
) == 32
5713 || mips_opts
.isa
< 3)
5714 ? "addu" : "daddu"),
5715 "d,v,t", AT
, breg
, AT
);
5716 /* Itbl support may require additional care here. */
5717 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5718 coproc
? treg
+ 1 : treg
,
5719 (int) BFD_RELOC_LO16
, AT
);
5720 expr1
.X_add_number
+= 4;
5722 /* Set mips_optimize to 2 to avoid inserting an undesired
5724 hold_mips_optimize
= mips_optimize
;
5726 /* Itbl support may require additional care here. */
5727 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5728 coproc
? treg
: treg
+ 1,
5729 (int) BFD_RELOC_LO16
, AT
);
5730 mips_optimize
= hold_mips_optimize
;
5731 expr1
.X_add_number
-= 4;
5733 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5734 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5735 8 + gpdel
+ off
, 1, 0),
5736 offset_expr
.X_add_symbol
, (offsetT
) 0,
5740 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5743 macro_build (p
, &icnt
, &offset_expr
,
5744 ((bfd_arch_bits_per_address (stdoutput
) == 32
5745 || mips_opts
.isa
< 3)
5747 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5749 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5753 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5754 ((bfd_arch_bits_per_address (stdoutput
) == 32
5755 || mips_opts
.isa
< 3)
5756 ? "addu" : "daddu"),
5757 "d,v,t", AT
, breg
, AT
);
5760 /* Itbl support may require additional care here. */
5761 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5762 coproc
? treg
+ 1 : treg
,
5763 (int) BFD_RELOC_LO16
, AT
);
5765 expr1
.X_add_number
+= 4;
5767 /* Set mips_optimize to 2 to avoid inserting an undesired
5769 hold_mips_optimize
= mips_optimize
;
5771 /* Itbl support may require additional care here. */
5772 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5773 coproc
? treg
: treg
+ 1,
5774 (int) BFD_RELOC_LO16
, AT
);
5775 mips_optimize
= hold_mips_optimize
;
5777 else if (mips_pic
== EMBEDDED_PIC
)
5779 /* If there is no base register, we use
5780 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5781 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5782 If we have a base register, we use
5784 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5785 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5795 ((bfd_arch_bits_per_address (stdoutput
) == 32
5796 || mips_opts
.isa
< 3)
5797 ? "addu" : "daddu"),
5798 "d,v,t", AT
, breg
, GP
);
5803 /* Itbl support may require additional care here. */
5804 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5805 coproc
? treg
+ 1 : treg
,
5806 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5807 offset_expr
.X_add_number
+= 4;
5808 /* Itbl support may require additional care here. */
5809 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5810 coproc
? treg
: treg
+ 1,
5811 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5827 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
5828 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5829 (int) BFD_RELOC_LO16
, breg
);
5830 offset_expr
.X_add_number
+= 4;
5831 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5832 (int) BFD_RELOC_LO16
, breg
);
5835 /* New code added to support COPZ instructions.
5836 This code builds table entries out of the macros in mip_opcodes.
5837 R4000 uses interlocks to handle coproc delays.
5838 Other chips (like the R3000) require nops to be inserted for delays.
5840 FIXME: Currently, we require that the user handle delays.
5841 In order to fill delay slots for non-interlocked chips,
5842 we must have a way to specify delays based on the coprocessor.
5843 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5844 What are the side-effects of the cop instruction?
5845 What cache support might we have and what are its effects?
5846 Both coprocessor & memory require delays. how long???
5847 What registers are read/set/modified?
5849 If an itbl is provided to interpret cop instructions,
5850 this knowledge can be encoded in the itbl spec. */
5864 /* For now we just do C (same as Cz). The parameter will be
5865 stored in insn_opcode by mips_ip. */
5866 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5870 #ifdef LOSING_COMPILER
5872 /* Try and see if this is a new itbl instruction.
5873 This code builds table entries out of the macros in mip_opcodes.
5874 FIXME: For now we just assemble the expression and pass it's
5875 value along as a 32-bit immediate.
5876 We may want to have the assembler assemble this value,
5877 so that we gain the assembler's knowledge of delay slots,
5879 Would it be more efficient to use mask (id) here? */
5880 if (itbl_have_entries
5881 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5883 s
= ip
->insn_mo
->name
;
5885 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5886 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5893 as_warn ("Macro used $at after \".set noat\"");
5898 struct mips_cl_insn
*ip
;
5900 register int treg
, sreg
, dreg
, breg
;
5915 bfd_reloc_code_real_type r
;
5918 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5919 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5920 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5921 mask
= ip
->insn_mo
->mask
;
5923 expr1
.X_op
= O_constant
;
5924 expr1
.X_op_symbol
= NULL
;
5925 expr1
.X_add_symbol
= NULL
;
5926 expr1
.X_add_number
= 1;
5930 #endif /* LOSING_COMPILER */
5935 macro_build ((char *) NULL
, &icnt
, NULL
,
5936 dbl
? "dmultu" : "multu",
5938 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5944 /* The MIPS assembler some times generates shifts and adds. I'm
5945 not trying to be that fancy. GCC should do this for us
5947 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5948 macro_build ((char *) NULL
, &icnt
, NULL
,
5949 dbl
? "dmult" : "mult",
5951 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5957 mips_emit_delays (true);
5958 ++mips_opts
.noreorder
;
5959 mips_any_noreorder
= 1;
5960 macro_build ((char *) NULL
, &icnt
, NULL
,
5961 dbl
? "dmult" : "mult",
5963 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5964 macro_build ((char *) NULL
, &icnt
, NULL
,
5965 dbl
? "dsra32" : "sra",
5966 "d,w,<", dreg
, dreg
, 31);
5967 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5969 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5972 expr1
.X_add_number
= 8;
5973 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5974 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5975 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5977 --mips_opts
.noreorder
;
5978 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5984 mips_emit_delays (true);
5985 ++mips_opts
.noreorder
;
5986 mips_any_noreorder
= 1;
5987 macro_build ((char *) NULL
, &icnt
, NULL
,
5988 dbl
? "dmultu" : "multu",
5990 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5991 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5993 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5996 expr1
.X_add_number
= 8;
5997 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5998 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5999 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6001 --mips_opts
.noreorder
;
6005 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6006 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6007 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6013 if (imm_expr
.X_op
!= O_constant
)
6014 as_bad ("rotate count too large");
6015 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6016 (int) (imm_expr
.X_add_number
& 0x1f));
6017 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6018 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6019 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6023 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6024 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6025 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6031 if (imm_expr
.X_op
!= O_constant
)
6032 as_bad ("rotate count too large");
6033 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6034 (int) (imm_expr
.X_add_number
& 0x1f));
6035 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6036 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6037 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6043 as_bad ("opcode not supported on this processor");
6046 assert (mips_opts
.isa
< 2);
6047 /* Even on a big endian machine $fn comes before $fn+1. We have
6048 to adjust when storing to memory. */
6049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6050 target_big_endian
? treg
+ 1 : treg
,
6051 (int) BFD_RELOC_LO16
, breg
);
6052 offset_expr
.X_add_number
+= 4;
6053 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6054 target_big_endian
? treg
: treg
+ 1,
6055 (int) BFD_RELOC_LO16
, breg
);
6060 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6061 treg
, (int) BFD_RELOC_LO16
);
6063 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6064 sreg
, (int) BFD_RELOC_LO16
);
6067 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6069 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6070 dreg
, (int) BFD_RELOC_LO16
);
6075 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6077 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6078 sreg
, (int) BFD_RELOC_LO16
);
6083 as_warn ("Instruction %s: result is always false",
6085 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6088 if (imm_expr
.X_op
== O_constant
6089 && imm_expr
.X_add_number
>= 0
6090 && imm_expr
.X_add_number
< 0x10000)
6092 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6093 sreg
, (int) BFD_RELOC_LO16
);
6096 else if (imm_expr
.X_op
== O_constant
6097 && imm_expr
.X_add_number
> -0x8000
6098 && imm_expr
.X_add_number
< 0)
6100 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6101 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6102 ((bfd_arch_bits_per_address (stdoutput
) == 32
6103 || mips_opts
.isa
< 3)
6104 ? "addiu" : "daddiu"),
6105 "t,r,j", dreg
, sreg
,
6106 (int) BFD_RELOC_LO16
);
6111 load_register (&icnt
, AT
, &imm_expr
, 0);
6112 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6116 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6117 (int) BFD_RELOC_LO16
);
6122 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6128 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6129 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6130 (int) BFD_RELOC_LO16
);
6133 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6135 if (imm_expr
.X_op
== O_constant
6136 && imm_expr
.X_add_number
>= -0x8000
6137 && imm_expr
.X_add_number
< 0x8000)
6139 macro_build ((char *) NULL
, &icnt
, &expr1
,
6140 mask
== M_SGE_I
? "slti" : "sltiu",
6141 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6146 load_register (&icnt
, AT
, &imm_expr
, 0);
6147 macro_build ((char *) NULL
, &icnt
, NULL
,
6148 mask
== M_SGE_I
? "slt" : "sltu",
6149 "d,v,t", dreg
, sreg
, AT
);
6152 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6153 (int) BFD_RELOC_LO16
);
6158 case M_SGT
: /* sreg > treg <==> treg < sreg */
6164 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6167 case M_SGT_I
: /* sreg > I <==> I < sreg */
6173 load_register (&icnt
, AT
, &imm_expr
, 0);
6174 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6177 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6183 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6184 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6185 (int) BFD_RELOC_LO16
);
6188 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6194 load_register (&icnt
, AT
, &imm_expr
, 0);
6195 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6196 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6197 (int) BFD_RELOC_LO16
);
6201 if (imm_expr
.X_op
== O_constant
6202 && imm_expr
.X_add_number
>= -0x8000
6203 && imm_expr
.X_add_number
< 0x8000)
6205 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6206 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6209 load_register (&icnt
, AT
, &imm_expr
, 0);
6210 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6214 if (imm_expr
.X_op
== O_constant
6215 && imm_expr
.X_add_number
>= -0x8000
6216 && imm_expr
.X_add_number
< 0x8000)
6218 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6219 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6222 load_register (&icnt
, AT
, &imm_expr
, 0);
6223 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6229 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6232 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6236 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6238 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6244 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6246 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6252 as_warn ("Instruction %s: result is always true",
6254 macro_build ((char *) NULL
, &icnt
, &expr1
,
6255 ((bfd_arch_bits_per_address (stdoutput
) == 32
6256 || mips_opts
.isa
< 3)
6257 ? "addiu" : "daddiu"),
6258 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6261 if (imm_expr
.X_op
== O_constant
6262 && imm_expr
.X_add_number
>= 0
6263 && imm_expr
.X_add_number
< 0x10000)
6265 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6266 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6269 else if (imm_expr
.X_op
== O_constant
6270 && imm_expr
.X_add_number
> -0x8000
6271 && imm_expr
.X_add_number
< 0)
6273 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6274 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6275 ((bfd_arch_bits_per_address (stdoutput
) == 32
6276 || mips_opts
.isa
< 3)
6277 ? "addiu" : "daddiu"),
6278 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6283 load_register (&icnt
, AT
, &imm_expr
, 0);
6284 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6288 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6296 if (imm_expr
.X_op
== O_constant
6297 && imm_expr
.X_add_number
> -0x8000
6298 && imm_expr
.X_add_number
<= 0x8000)
6300 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6301 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6302 dbl
? "daddi" : "addi",
6303 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6306 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6307 macro_build ((char *) NULL
, &icnt
, NULL
,
6308 dbl
? "dsub" : "sub",
6309 "d,v,t", dreg
, sreg
, AT
);
6315 if (imm_expr
.X_op
== O_constant
6316 && imm_expr
.X_add_number
> -0x8000
6317 && imm_expr
.X_add_number
<= 0x8000)
6319 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6320 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6321 dbl
? "daddiu" : "addiu",
6322 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6325 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6326 macro_build ((char *) NULL
, &icnt
, NULL
,
6327 dbl
? "dsubu" : "subu",
6328 "d,v,t", dreg
, sreg
, AT
);
6349 load_register (&icnt
, AT
, &imm_expr
, 0);
6350 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6355 assert (mips_opts
.isa
< 2);
6356 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6357 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6360 * Is the double cfc1 instruction a bug in the mips assembler;
6361 * or is there a reason for it?
6363 mips_emit_delays (true);
6364 ++mips_opts
.noreorder
;
6365 mips_any_noreorder
= 1;
6366 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6367 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6368 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6369 expr1
.X_add_number
= 3;
6370 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6371 (int) BFD_RELOC_LO16
);
6372 expr1
.X_add_number
= 2;
6373 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6374 (int) BFD_RELOC_LO16
);
6375 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6376 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6377 macro_build ((char *) NULL
, &icnt
, NULL
,
6378 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6379 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6380 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6381 --mips_opts
.noreorder
;
6390 if (offset_expr
.X_add_number
>= 0x7fff)
6391 as_bad ("operand overflow");
6392 /* avoid load delay */
6393 if (! target_big_endian
)
6394 offset_expr
.X_add_number
+= 1;
6395 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6396 (int) BFD_RELOC_LO16
, breg
);
6397 if (! target_big_endian
)
6398 offset_expr
.X_add_number
-= 1;
6400 offset_expr
.X_add_number
+= 1;
6401 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6402 (int) BFD_RELOC_LO16
, breg
);
6403 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6404 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6417 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6418 as_bad ("operand overflow");
6419 if (! target_big_endian
)
6420 offset_expr
.X_add_number
+= off
;
6421 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6422 (int) BFD_RELOC_LO16
, breg
);
6423 if (! target_big_endian
)
6424 offset_expr
.X_add_number
-= off
;
6426 offset_expr
.X_add_number
+= off
;
6427 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6428 (int) BFD_RELOC_LO16
, breg
);
6441 load_address (&icnt
, AT
, &offset_expr
);
6443 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6444 ((bfd_arch_bits_per_address (stdoutput
) == 32
6445 || mips_opts
.isa
< 3)
6446 ? "addu" : "daddu"),
6447 "d,v,t", AT
, AT
, breg
);
6448 if (! target_big_endian
)
6449 expr1
.X_add_number
= off
;
6451 expr1
.X_add_number
= 0;
6452 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6453 (int) BFD_RELOC_LO16
, AT
);
6454 if (! target_big_endian
)
6455 expr1
.X_add_number
= 0;
6457 expr1
.X_add_number
= off
;
6458 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6459 (int) BFD_RELOC_LO16
, AT
);
6464 load_address (&icnt
, AT
, &offset_expr
);
6466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6467 ((bfd_arch_bits_per_address (stdoutput
) == 32
6468 || mips_opts
.isa
< 3)
6469 ? "addu" : "daddu"),
6470 "d,v,t", AT
, AT
, breg
);
6471 if (target_big_endian
)
6472 expr1
.X_add_number
= 0;
6473 macro_build ((char *) NULL
, &icnt
, &expr1
,
6474 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6475 (int) BFD_RELOC_LO16
, AT
);
6476 if (target_big_endian
)
6477 expr1
.X_add_number
= 1;
6479 expr1
.X_add_number
= 0;
6480 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6481 (int) BFD_RELOC_LO16
, AT
);
6482 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6484 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6489 if (offset_expr
.X_add_number
>= 0x7fff)
6490 as_bad ("operand overflow");
6491 if (target_big_endian
)
6492 offset_expr
.X_add_number
+= 1;
6493 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6494 (int) BFD_RELOC_LO16
, breg
);
6495 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6496 if (target_big_endian
)
6497 offset_expr
.X_add_number
-= 1;
6499 offset_expr
.X_add_number
+= 1;
6500 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6501 (int) BFD_RELOC_LO16
, breg
);
6514 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6515 as_bad ("operand overflow");
6516 if (! target_big_endian
)
6517 offset_expr
.X_add_number
+= off
;
6518 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6519 (int) BFD_RELOC_LO16
, breg
);
6520 if (! target_big_endian
)
6521 offset_expr
.X_add_number
-= off
;
6523 offset_expr
.X_add_number
+= off
;
6524 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6525 (int) BFD_RELOC_LO16
, breg
);
6538 load_address (&icnt
, AT
, &offset_expr
);
6540 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6541 ((bfd_arch_bits_per_address (stdoutput
) == 32
6542 || mips_opts
.isa
< 3)
6543 ? "addu" : "daddu"),
6544 "d,v,t", AT
, AT
, breg
);
6545 if (! target_big_endian
)
6546 expr1
.X_add_number
= off
;
6548 expr1
.X_add_number
= 0;
6549 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6550 (int) BFD_RELOC_LO16
, AT
);
6551 if (! target_big_endian
)
6552 expr1
.X_add_number
= 0;
6554 expr1
.X_add_number
= off
;
6555 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6556 (int) BFD_RELOC_LO16
, AT
);
6560 load_address (&icnt
, AT
, &offset_expr
);
6562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6563 ((bfd_arch_bits_per_address (stdoutput
) == 32
6564 || mips_opts
.isa
< 3)
6565 ? "addu" : "daddu"),
6566 "d,v,t", AT
, AT
, breg
);
6567 if (! target_big_endian
)
6568 expr1
.X_add_number
= 0;
6569 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6570 (int) BFD_RELOC_LO16
, AT
);
6571 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6573 if (! target_big_endian
)
6574 expr1
.X_add_number
= 1;
6576 expr1
.X_add_number
= 0;
6577 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6578 (int) BFD_RELOC_LO16
, AT
);
6579 if (! target_big_endian
)
6580 expr1
.X_add_number
= 0;
6582 expr1
.X_add_number
= 1;
6583 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6584 (int) BFD_RELOC_LO16
, AT
);
6585 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6587 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6592 /* FIXME: Check if this is one of the itbl macros, since they
6593 are added dynamically. */
6594 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6598 as_warn ("Macro used $at after \".set noat\"");
6601 /* Implement macros in mips16 mode. */
6605 struct mips_cl_insn
*ip
;
6608 int xreg
, yreg
, zreg
, tmp
;
6612 const char *s
, *s2
, *s3
;
6614 mask
= ip
->insn_mo
->mask
;
6616 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6617 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6618 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6622 expr1
.X_op
= O_constant
;
6623 expr1
.X_op_symbol
= NULL
;
6624 expr1
.X_add_symbol
= NULL
;
6625 expr1
.X_add_number
= 1;
6644 mips_emit_delays (true);
6645 ++mips_opts
.noreorder
;
6646 mips_any_noreorder
= 1;
6647 macro_build ((char *) NULL
, &icnt
, NULL
,
6648 dbl
? "ddiv" : "div",
6649 "0,x,y", xreg
, yreg
);
6650 expr1
.X_add_number
= 2;
6651 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6652 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6653 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6654 since that causes an overflow. We should do that as well,
6655 but I don't see how to do the comparisons without a temporary
6657 --mips_opts
.noreorder
;
6658 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6677 mips_emit_delays (true);
6678 ++mips_opts
.noreorder
;
6679 mips_any_noreorder
= 1;
6680 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6681 expr1
.X_add_number
= 2;
6682 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6683 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6684 --mips_opts
.noreorder
;
6685 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6691 macro_build ((char *) NULL
, &icnt
, NULL
,
6692 dbl
? "dmultu" : "multu",
6694 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6702 if (imm_expr
.X_op
!= O_constant
)
6703 as_bad ("Unsupported large constant");
6704 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6705 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6706 dbl
? "daddiu" : "addiu",
6707 "y,x,4", yreg
, xreg
);
6711 if (imm_expr
.X_op
!= O_constant
)
6712 as_bad ("Unsupported large constant");
6713 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6714 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6719 if (imm_expr
.X_op
!= O_constant
)
6720 as_bad ("Unsupported large constant");
6721 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6722 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6745 goto do_reverse_branch
;
6749 goto do_reverse_branch
;
6761 goto do_reverse_branch
;
6772 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6774 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6801 goto do_addone_branch_i
;
6806 goto do_addone_branch_i
;
6821 goto do_addone_branch_i
;
6828 if (imm_expr
.X_op
!= O_constant
)
6829 as_bad ("Unsupported large constant");
6830 ++imm_expr
.X_add_number
;
6833 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6834 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6838 expr1
.X_add_number
= 0;
6839 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6842 "move", "y,X", xreg
, yreg
);
6843 expr1
.X_add_number
= 2;
6844 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6845 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6846 "neg", "x,w", xreg
, xreg
);
6850 /* For consistency checking, verify that all bits are specified either
6851 by the match/mask part of the instruction definition, or by the
6854 validate_mips_insn (opc
)
6855 const struct mips_opcode
*opc
;
6857 const char *p
= opc
->args
;
6859 unsigned long used_bits
= opc
->mask
;
6861 if ((used_bits
& opc
->match
) != opc
->match
)
6863 as_bad ("internal: bad mips opcode (mask error): %s %s",
6864 opc
->name
, opc
->args
);
6867 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6874 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6875 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6877 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6878 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6879 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6880 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6882 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6885 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6886 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6887 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6888 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6889 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6890 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6891 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6892 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6893 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6894 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6895 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6897 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6898 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6899 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6900 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6902 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6903 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6904 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6905 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6906 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6907 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6908 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6909 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6912 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6913 /* start-sanitize-vr5400 */
6914 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
6915 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
6918 /* end-sanitize-vr5400 */
6920 as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s",
6921 c
, opc
->name
, opc
->args
);
6925 /* Some of the trapping instructions (break, t*, sdbbp) have "code"
6926 fields that cannot currently be set by assembly code. Ignore them
6928 if (opc
->pinfo
& INSN_TRAP
)
6930 static const char *const trap_insns
[] = {
6932 "teq", "tge", "tgeu", "tlt", "tltu", "tne",
6935 for (i
= sizeof(trap_insns
)/sizeof(trap_insns
[0]) - 1; i
>= 0; i
--)
6936 if (!strcmp (trap_insns
[i
], opc
->name
))
6938 used_bits
|= 0xffc0;
6942 if (used_bits
!= 0xffffffff)
6944 as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s",
6945 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6951 /* This routine assembles an instruction into its binary format. As a
6952 side effect, it sets one of the global variables imm_reloc or
6953 offset_reloc to the type of relocation to do if one of the operands
6954 is an address expression. */
6959 struct mips_cl_insn
*ip
;
6964 struct mips_opcode
*insn
;
6967 unsigned int lastregno
= 0;
6972 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6977 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6979 insn_error
= "unrecognized opcode";
6988 assert (strcmp (insn
->name
, str
) == 0);
6990 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
6992 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
6994 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
6996 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7001 if (insn_isa
<= mips_opts
.isa
)
7003 else if (insn
->pinfo
== INSN_MACRO
)
7005 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
7006 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
7007 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
7008 /* start-sanitize-vr4320 */
7009 || (mips_4320
&& (insn
->membership
& INSN_4320
) != 0)
7010 /* end-sanitize-vr4320 */
7011 /* start-sanitize-tx49 */
7012 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
7013 /* end-sanitize-tx49 */
7014 /* start-sanitize-r5900 */
7015 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
7016 /* end-sanitize-r5900 */
7017 /* start-sanitize-vr5400 */
7018 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
7019 /* end-sanitize-vr5400 */
7020 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
7025 if (insn
->pinfo
!= INSN_MACRO
)
7027 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
7029 /* start-sanitize-r5900 */
7030 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
7032 /* end-sanitize-r5900 */
7037 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7038 && strcmp (insn
->name
, insn
[1].name
) == 0)
7044 || insn_isa
<= mips_opts
.isa
)
7045 insn_error
= "opcode not supported on this processor";
7048 static char buf
[100];
7050 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
7057 ip
->insn_opcode
= insn
->match
;
7058 for (args
= insn
->args
;; ++args
)
7064 case '\0': /* end of args */
7077 ip
->insn_opcode
|= lastregno
<< 21;
7082 ip
->insn_opcode
|= lastregno
<< 16;
7086 ip
->insn_opcode
|= lastregno
<< 11;
7092 /* handle optional base register.
7093 Either the base register is omitted or
7094 we must have a left paren. */
7095 /* this is dependent on the next operand specifier
7096 is a 'b' for base register */
7097 assert (args
[1] == 'b');
7101 case ')': /* these must match exactly */
7102 /* start-sanitize-vr5400 */
7105 /* end-sanitize-vr5400 */
7110 case '<': /* must be at least one digit */
7112 * According to the manual, if the shift amount is greater
7113 * than 31 or less than 0 the the shift amount should be
7114 * mod 32. In reality the mips assembler issues an error.
7115 * We issue a warning and mask out all but the low 5 bits.
7117 my_getExpression (&imm_expr
, s
);
7118 check_absolute_expr (ip
, &imm_expr
);
7119 if ((unsigned long) imm_expr
.X_add_number
> 31)
7121 as_warn ("Improper shift amount (%ld)",
7122 (long) imm_expr
.X_add_number
);
7123 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7125 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7126 imm_expr
.X_op
= O_absent
;
7130 case '>': /* shift amount minus 32 */
7131 my_getExpression (&imm_expr
, s
);
7132 check_absolute_expr (ip
, &imm_expr
);
7133 if ((unsigned long) imm_expr
.X_add_number
< 32
7134 || (unsigned long) imm_expr
.X_add_number
> 63)
7136 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7137 imm_expr
.X_op
= O_absent
;
7141 case 'k': /* cache code */
7142 case 'h': /* prefx code */
7143 my_getExpression (&imm_expr
, s
);
7144 check_absolute_expr (ip
, &imm_expr
);
7145 if ((unsigned long) imm_expr
.X_add_number
> 31)
7147 as_warn ("Invalid value for `%s' (%lu)",
7149 (unsigned long) imm_expr
.X_add_number
);
7150 imm_expr
.X_add_number
&= 0x1f;
7153 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7155 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7156 imm_expr
.X_op
= O_absent
;
7160 case 'c': /* break code */
7161 my_getExpression (&imm_expr
, s
);
7162 check_absolute_expr (ip
, &imm_expr
);
7163 if ((unsigned) imm_expr
.X_add_number
> 1023)
7164 as_warn ("Illegal break code (%ld)",
7165 (long) imm_expr
.X_add_number
);
7166 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7167 imm_expr
.X_op
= O_absent
;
7171 case 'B': /* syscall code */
7172 my_getExpression (&imm_expr
, s
);
7173 check_absolute_expr (ip
, &imm_expr
);
7174 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7175 as_warn ("Illegal syscall code (%ld)",
7176 (long) imm_expr
.X_add_number
);
7177 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7178 imm_expr
.X_op
= O_absent
;
7182 case 'C': /* Coprocessor code */
7183 my_getExpression (&imm_expr
, s
);
7184 check_absolute_expr (ip
, &imm_expr
);
7185 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7187 as_warn ("Coproccesor code > 25 bits (%ld)",
7188 (long) imm_expr
.X_add_number
);
7189 imm_expr
.X_add_number
&= ((1<<25) - 1);
7191 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7192 imm_expr
.X_op
= O_absent
;
7196 case 'P': /* Performance register */
7197 my_getExpression (&imm_expr
, s
);
7198 check_absolute_expr (ip
, &imm_expr
);
7199 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7201 as_warn ("Invalidate performance regster (%ld)",
7202 (long) imm_expr
.X_add_number
);
7203 imm_expr
.X_add_number
&= 1;
7205 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7206 imm_expr
.X_op
= O_absent
;
7210 case 'b': /* base register */
7211 case 'd': /* destination register */
7212 case 's': /* source register */
7213 case 't': /* target register */
7214 case 'r': /* both target and source */
7215 case 'v': /* both dest and source */
7216 case 'w': /* both dest and target */
7217 case 'E': /* coprocessor target register */
7218 case 'G': /* coprocessor destination register */
7219 case 'x': /* ignore register name */
7220 case 'z': /* must be zero register */
7234 while (isdigit (*s
));
7236 as_bad ("Invalid register number (%d)", regno
);
7238 else if (*args
== 'E' || *args
== 'G')
7242 if (s
[1] == 'f' && s
[2] == 'p')
7247 else if (s
[1] == 's' && s
[2] == 'p')
7252 else if (s
[1] == 'g' && s
[2] == 'p')
7257 else if (s
[1] == 'a' && s
[2] == 't')
7262 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7267 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7272 else if (itbl_have_entries
)
7277 p
= s
+1; /* advance past '$' */
7278 n
= itbl_get_field (&p
); /* n is name */
7280 /* See if this is a register defined in an
7282 r
= itbl_get_reg_val (n
);
7285 /* Get_field advances to the start of
7286 the next field, so we need to back
7287 rack to the end of the last field. */
7291 s
= strchr (s
,'\0');
7304 as_warn ("Used $at without \".set noat\"");
7310 if (c
== 'r' || c
== 'v' || c
== 'w')
7317 /* 'z' only matches $0. */
7318 if (c
== 'z' && regno
!= 0)
7321 /* Now that we have assembled one operand, we use the args string
7322 * to figure out where it goes in the instruction. */
7329 ip
->insn_opcode
|= regno
<< 21;
7333 ip
->insn_opcode
|= regno
<< 11;
7338 ip
->insn_opcode
|= regno
<< 16;
7341 /* This case exists because on the r3000 trunc
7342 expands into a macro which requires a gp
7343 register. On the r6000 or r4000 it is
7344 assembled into a single instruction which
7345 ignores the register. Thus the insn version
7346 is MIPS_ISA2 and uses 'x', and the macro
7347 version is MIPS_ISA1 and uses 't'. */
7350 /* This case is for the div instruction, which
7351 acts differently if the destination argument
7352 is $0. This only matches $0, and is checked
7353 outside the switch. */
7356 /* Itbl operand; not yet implemented. FIXME ?? */
7358 /* What about all other operands like 'i', which
7359 can be specified in the opcode table? */
7369 ip
->insn_opcode
|= lastregno
<< 21;
7372 ip
->insn_opcode
|= lastregno
<< 16;
7377 case 'D': /* floating point destination register */
7378 case 'S': /* floating point source register */
7379 case 'T': /* floating point target register */
7380 case 'R': /* floating point source register */
7384 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7394 while (isdigit (*s
));
7397 as_bad ("Invalid float register number (%d)", regno
);
7399 if ((regno
& 1) != 0
7400 && mips_opts
.isa
< 3
7401 && ! (strcmp (str
, "mtc1") == 0
7402 || strcmp (str
, "mfc1") == 0
7403 || strcmp (str
, "lwc1") == 0
7404 || strcmp (str
, "swc1") == 0
7405 || strcmp (str
, "l.s") == 0
7406 || strcmp (str
, "s.s") == 0))
7407 as_warn ("Float register should be even, was %d",
7415 if (c
== 'V' || c
== 'W')
7425 ip
->insn_opcode
|= regno
<< 6;
7429 ip
->insn_opcode
|= regno
<< 11;
7433 ip
->insn_opcode
|= regno
<< 16;
7436 ip
->insn_opcode
|= regno
<< 21;
7445 ip
->insn_opcode
|= lastregno
<< 11;
7448 ip
->insn_opcode
|= lastregno
<< 16;
7454 my_getExpression (&imm_expr
, s
);
7455 if (imm_expr
.X_op
!= O_big
7456 && imm_expr
.X_op
!= O_constant
)
7457 insn_error
= "absolute expression required";
7462 my_getExpression (&offset_expr
, s
);
7463 imm_reloc
= BFD_RELOC_32
;
7475 unsigned char temp
[8];
7477 unsigned int length
;
7482 /* These only appear as the last operand in an
7483 instruction, and every instruction that accepts
7484 them in any variant accepts them in all variants.
7485 This means we don't have to worry about backing out
7486 any changes if the instruction does not match.
7488 The difference between them is the size of the
7489 floating point constant and where it goes. For 'F'
7490 and 'L' the constant is 64 bits; for 'f' and 'l' it
7491 is 32 bits. Where the constant is placed is based
7492 on how the MIPS assembler does things:
7495 f -- immediate value
7498 The .lit4 and .lit8 sections are only used if
7499 permitted by the -G argument.
7501 When generating embedded PIC code, we use the
7502 .lit8 section but not the .lit4 section (we can do
7503 .lit4 inline easily; we need to put .lit8
7504 somewhere in the data segment, and using .lit8
7505 permits the linker to eventually combine identical
7508 f64
= *args
== 'F' || *args
== 'L';
7510 save_in
= input_line_pointer
;
7511 input_line_pointer
= s
;
7512 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7514 s
= input_line_pointer
;
7515 input_line_pointer
= save_in
;
7516 if (err
!= NULL
&& *err
!= '\0')
7518 as_bad ("Bad floating point constant: %s", err
);
7519 memset (temp
, '\0', sizeof temp
);
7520 length
= f64
? 8 : 4;
7523 assert (length
== (f64
? 8 : 4));
7527 && (! USE_GLOBAL_POINTER_OPT
7528 || mips_pic
== EMBEDDED_PIC
7529 || g_switch_value
< 4
7530 || (temp
[0] == 0 && temp
[1] == 0)
7531 || (temp
[2] == 0 && temp
[3] == 0))))
7533 imm_expr
.X_op
= O_constant
;
7534 if (! target_big_endian
)
7535 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7537 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7540 && ((temp
[0] == 0 && temp
[1] == 0)
7541 || (temp
[2] == 0 && temp
[3] == 0))
7542 && ((temp
[4] == 0 && temp
[5] == 0)
7543 || (temp
[6] == 0 && temp
[7] == 0)))
7545 /* The value is simple enough to load with a
7546 couple of instructions. In mips1 mode, set
7547 imm_expr to the high order 32 bits and
7548 offset_expr to the low order 32 bits.
7549 Otherwise, set imm_expr to the entire 64 bit
7551 if (mips_opts
.isa
< 3)
7553 imm_expr
.X_op
= O_constant
;
7554 offset_expr
.X_op
= O_constant
;
7555 if (! target_big_endian
)
7557 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7558 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7562 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7563 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7565 if (offset_expr
.X_add_number
== 0)
7566 offset_expr
.X_op
= O_absent
;
7568 else if (sizeof (imm_expr
.X_add_number
) > 4)
7570 imm_expr
.X_op
= O_constant
;
7571 if (! target_big_endian
)
7572 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7574 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7578 imm_expr
.X_op
= O_big
;
7579 imm_expr
.X_add_number
= 4;
7580 if (! target_big_endian
)
7582 generic_bignum
[0] = bfd_getl16 (temp
);
7583 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7584 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7585 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7589 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7590 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7591 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7592 generic_bignum
[3] = bfd_getb16 (temp
);
7598 const char *newname
;
7601 /* Switch to the right section. */
7603 subseg
= now_subseg
;
7606 default: /* unused default case avoids warnings. */
7608 newname
= RDATA_SECTION_NAME
;
7609 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7613 newname
= RDATA_SECTION_NAME
;
7616 assert (!USE_GLOBAL_POINTER_OPT
7617 || g_switch_value
>= 4);
7621 new_seg
= subseg_new (newname
, (subsegT
) 0);
7622 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7623 bfd_set_section_flags (stdoutput
, new_seg
,
7628 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7629 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7630 && strcmp (TARGET_OS
, "elf") != 0)
7631 record_alignment (new_seg
, 4);
7633 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7635 as_bad ("Can't use floating point insn in this section");
7637 /* Set the argument to the current address in the
7639 offset_expr
.X_op
= O_symbol
;
7640 offset_expr
.X_add_symbol
=
7641 symbol_new ("L0\001", now_seg
,
7642 (valueT
) frag_now_fix (), frag_now
);
7643 offset_expr
.X_add_number
= 0;
7645 /* Put the floating point number into the section. */
7646 p
= frag_more ((int) length
);
7647 memcpy (p
, temp
, length
);
7649 /* Switch back to the original section. */
7650 subseg_set (seg
, subseg
);
7655 case 'i': /* 16 bit unsigned immediate */
7656 case 'j': /* 16 bit signed immediate */
7657 imm_reloc
= BFD_RELOC_LO16
;
7658 c
= my_getSmallExpression (&imm_expr
, s
);
7663 if (imm_expr
.X_op
== O_constant
)
7664 imm_expr
.X_add_number
=
7665 (imm_expr
.X_add_number
>> 16) & 0xffff;
7668 imm_reloc
= BFD_RELOC_HI16_S
;
7669 imm_unmatched_hi
= true;
7672 imm_reloc
= BFD_RELOC_HI16
;
7677 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7678 || ((imm_expr
.X_add_number
< 0
7679 || imm_expr
.X_add_number
>= 0x10000)
7680 && imm_expr
.X_op
== O_constant
))
7682 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7683 !strcmp (insn
->name
, insn
[1].name
))
7685 if (imm_expr
.X_op
!= O_constant
7686 && imm_expr
.X_op
!= O_big
)
7687 insn_error
= "absolute expression required";
7689 as_bad ("16 bit expression not in range 0..65535");
7697 /* The upper bound should be 0x8000, but
7698 unfortunately the MIPS assembler accepts numbers
7699 from 0x8000 to 0xffff and sign extends them, and
7700 we want to be compatible. We only permit this
7701 extended range for an instruction which does not
7702 provide any further alternates, since those
7703 alternates may handle other cases. People should
7704 use the numbers they mean, rather than relying on
7705 a mysterious sign extension. */
7706 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7707 strcmp (insn
->name
, insn
[1].name
) == 0);
7712 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7713 || ((imm_expr
.X_add_number
< -0x8000
7714 || imm_expr
.X_add_number
>= max
)
7715 && imm_expr
.X_op
== O_constant
)
7717 && imm_expr
.X_add_number
< 0
7718 && mips_opts
.isa
>= 3
7719 && imm_expr
.X_unsigned
7720 && sizeof (imm_expr
.X_add_number
) <= 4))
7724 if (imm_expr
.X_op
!= O_constant
7725 && imm_expr
.X_op
!= O_big
)
7726 insn_error
= "absolute expression required";
7728 as_bad ("16 bit expression not in range -32768..32767");
7734 case 'o': /* 16 bit offset */
7735 c
= my_getSmallExpression (&offset_expr
, s
);
7737 /* If this value won't fit into a 16 bit offset, then go
7738 find a macro that will generate the 32 bit offset
7739 code pattern. As a special hack, we accept the
7740 difference of two local symbols as a constant. This
7741 is required to suppose embedded PIC switches, which
7742 use an instruction which looks like
7743 lw $4,$L12-$LS12($4)
7744 The problem with handling this in a more general
7745 fashion is that the macro function doesn't expect to
7746 see anything which can be handled in a single
7747 constant instruction. */
7749 && (offset_expr
.X_op
!= O_constant
7750 || offset_expr
.X_add_number
>= 0x8000
7751 || offset_expr
.X_add_number
< -0x8000)
7752 && (mips_pic
!= EMBEDDED_PIC
7753 || offset_expr
.X_op
!= O_subtract
7754 || now_seg
!= text_section
7755 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7759 offset_reloc
= BFD_RELOC_LO16
;
7760 if (c
== 'h' || c
== 'H')
7762 assert (offset_expr
.X_op
== O_constant
);
7763 offset_expr
.X_add_number
=
7764 (offset_expr
.X_add_number
>> 16) & 0xffff;
7769 case 'p': /* pc relative offset */
7770 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7771 my_getExpression (&offset_expr
, s
);
7775 case 'u': /* upper 16 bits */
7776 c
= my_getSmallExpression (&imm_expr
, s
);
7777 if (imm_expr
.X_op
== O_constant
7778 && (imm_expr
.X_add_number
< 0
7779 || imm_expr
.X_add_number
>= 0x10000))
7780 as_bad ("lui expression not in range 0..65535");
7781 imm_reloc
= BFD_RELOC_LO16
;
7786 if (imm_expr
.X_op
== O_constant
)
7787 imm_expr
.X_add_number
=
7788 (imm_expr
.X_add_number
>> 16) & 0xffff;
7791 imm_reloc
= BFD_RELOC_HI16_S
;
7792 imm_unmatched_hi
= true;
7795 imm_reloc
= BFD_RELOC_HI16
;
7801 case 'a': /* 26 bit address */
7802 my_getExpression (&offset_expr
, s
);
7804 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7807 case 'N': /* 3 bit branch condition code */
7808 case 'M': /* 3 bit compare condition code */
7809 if (strncmp (s
, "$fcc", 4) != 0)
7819 while (isdigit (*s
));
7821 as_bad ("invalid condition code register $fcc%d", regno
);
7823 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7825 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7828 /* start-sanitize-vr5400 */
7829 case 'e': /* must be at least one digit */
7830 my_getExpression (&imm_expr
, s
);
7831 check_absolute_expr (ip
, &imm_expr
);
7832 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
7834 as_bad ("bad byte vector index (%ld)",
7835 (long) imm_expr
.X_add_number
);
7836 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
7838 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
7839 imm_expr
.X_op
= O_absent
;
7844 my_getExpression (&imm_expr
, s
);
7845 check_absolute_expr (ip
, &imm_expr
);
7846 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
7848 as_bad ("bad byte vector index (%ld)",
7849 (long) imm_expr
.X_add_number
);
7850 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
7852 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
7853 imm_expr
.X_op
= O_absent
;
7857 /* end-sanitize-vr5400 */
7859 as_bad ("bad char = '%c'\n", *args
);
7864 /* Args don't match. */
7865 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7866 !strcmp (insn
->name
, insn
[1].name
))
7872 insn_error
= "illegal operands";
7877 /* This routine assembles an instruction into its binary format when
7878 assembling for the mips16. As a side effect, it sets one of the
7879 global variables imm_reloc or offset_reloc to the type of
7880 relocation to do if one of the operands is an address expression.
7881 It also sets mips16_small and mips16_ext if the user explicitly
7882 requested a small or extended instruction. */
7887 struct mips_cl_insn
*ip
;
7891 struct mips_opcode
*insn
;
7894 unsigned int lastregno
= 0;
7899 mips16_small
= false;
7902 for (s
= str
; islower (*s
); ++s
)
7914 if (s
[1] == 't' && s
[2] == ' ')
7917 mips16_small
= true;
7921 else if (s
[1] == 'e' && s
[2] == ' ')
7930 insn_error
= "unknown opcode";
7934 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7935 mips16_small
= true;
7937 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7939 insn_error
= "unrecognized opcode";
7946 assert (strcmp (insn
->name
, str
) == 0);
7949 ip
->insn_opcode
= insn
->match
;
7950 ip
->use_extend
= false;
7951 imm_expr
.X_op
= O_absent
;
7952 imm_reloc
= BFD_RELOC_UNUSED
;
7953 offset_expr
.X_op
= O_absent
;
7954 offset_reloc
= BFD_RELOC_UNUSED
;
7955 for (args
= insn
->args
; 1; ++args
)
7962 /* In this switch statement we call break if we did not find
7963 a match, continue if we did find a match, or return if we
7972 /* Stuff the immediate value in now, if we can. */
7973 if (imm_expr
.X_op
== O_constant
7974 && imm_reloc
> BFD_RELOC_UNUSED
7975 && insn
->pinfo
!= INSN_MACRO
)
7977 mips16_immed ((char *) NULL
, 0,
7978 imm_reloc
- BFD_RELOC_UNUSED
,
7979 imm_expr
.X_add_number
, true, mips16_small
,
7980 mips16_ext
, &ip
->insn_opcode
,
7981 &ip
->use_extend
, &ip
->extend
);
7982 imm_expr
.X_op
= O_absent
;
7983 imm_reloc
= BFD_RELOC_UNUSED
;
7997 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8000 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8016 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8018 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8045 while (isdigit (*s
));
8048 as_bad ("invalid register number (%d)", regno
);
8054 if (s
[1] == 'f' && s
[2] == 'p')
8059 else if (s
[1] == 's' && s
[2] == 'p')
8064 else if (s
[1] == 'g' && s
[2] == 'p')
8069 else if (s
[1] == 'a' && s
[2] == 't')
8074 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8079 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8092 if (c
== 'v' || c
== 'w')
8094 regno
= mips16_to_32_reg_map
[lastregno
];
8108 regno
= mips32_to_16_reg_map
[regno
];
8113 regno
= ILLEGAL_REG
;
8118 regno
= ILLEGAL_REG
;
8123 regno
= ILLEGAL_REG
;
8128 if (regno
== AT
&& ! mips_opts
.noat
)
8129 as_warn ("used $at without \".set noat\"");
8136 if (regno
== ILLEGAL_REG
)
8143 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8147 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8150 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8153 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8159 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8162 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8163 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8173 if (strncmp (s
, "$pc", 3) == 0)
8197 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8199 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8200 and generate the appropriate reloc. If the text
8201 inside %gprel is not a symbol name with an
8202 optional offset, then we generate a normal reloc
8203 and will probably fail later. */
8204 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8205 if (imm_expr
.X_op
== O_symbol
)
8208 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8210 ip
->use_extend
= true;
8217 /* Just pick up a normal expression. */
8218 my_getExpression (&imm_expr
, s
);
8221 if (imm_expr
.X_op
== O_register
)
8223 /* What we thought was an expression turned out to
8226 if (s
[0] == '(' && args
[1] == '(')
8228 /* It looks like the expression was omitted
8229 before a register indirection, which means
8230 that the expression is implicitly zero. We
8231 still set up imm_expr, so that we handle
8232 explicit extensions correctly. */
8233 imm_expr
.X_op
= O_constant
;
8234 imm_expr
.X_add_number
= 0;
8235 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8242 /* We need to relax this instruction. */
8243 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8252 /* We use offset_reloc rather than imm_reloc for the PC
8253 relative operands. This lets macros with both
8254 immediate and address operands work correctly. */
8255 my_getExpression (&offset_expr
, s
);
8257 if (offset_expr
.X_op
== O_register
)
8260 /* We need to relax this instruction. */
8261 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8265 case '6': /* break code */
8266 my_getExpression (&imm_expr
, s
);
8267 check_absolute_expr (ip
, &imm_expr
);
8268 if ((unsigned long) imm_expr
.X_add_number
> 63)
8270 as_warn ("Invalid value for `%s' (%lu)",
8272 (unsigned long) imm_expr
.X_add_number
);
8273 imm_expr
.X_add_number
&= 0x3f;
8275 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8276 imm_expr
.X_op
= O_absent
;
8280 case 'a': /* 26 bit address */
8281 my_getExpression (&offset_expr
, s
);
8283 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8284 ip
->insn_opcode
<<= 16;
8287 case 'l': /* register list for entry macro */
8288 case 'L': /* register list for exit macro */
8298 int freg
, reg1
, reg2
;
8300 while (*s
== ' ' || *s
== ',')
8304 as_bad ("can't parse register list");
8316 while (isdigit (*s
))
8338 as_bad ("invalid register list");
8343 while (isdigit (*s
))
8350 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8355 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8360 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8361 mask
|= (reg2
- 3) << 3;
8362 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8363 mask
|= (reg2
- 15) << 1;
8364 else if (reg1
== 31 && reg2
== 31)
8368 as_bad ("invalid register list");
8372 /* The mask is filled in in the opcode table for the
8373 benefit of the disassembler. We remove it before
8374 applying the actual mask. */
8375 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8376 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8380 case 'e': /* extend code */
8381 my_getExpression (&imm_expr
, s
);
8382 check_absolute_expr (ip
, &imm_expr
);
8383 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8385 as_warn ("Invalid value for `%s' (%lu)",
8387 (unsigned long) imm_expr
.X_add_number
);
8388 imm_expr
.X_add_number
&= 0x7ff;
8390 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8391 imm_expr
.X_op
= O_absent
;
8401 /* Args don't match. */
8402 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8403 strcmp (insn
->name
, insn
[1].name
) == 0)
8410 insn_error
= "illegal operands";
8416 /* This structure holds information we know about a mips16 immediate
8419 struct mips16_immed_operand
8421 /* The type code used in the argument string in the opcode table. */
8423 /* The number of bits in the short form of the opcode. */
8425 /* The number of bits in the extended form of the opcode. */
8427 /* The amount by which the short form is shifted when it is used;
8428 for example, the sw instruction has a shift count of 2. */
8430 /* The amount by which the short form is shifted when it is stored
8431 into the instruction code. */
8433 /* Non-zero if the short form is unsigned. */
8435 /* Non-zero if the extended form is unsigned. */
8437 /* Non-zero if the value is PC relative. */
8441 /* The mips16 immediate operand types. */
8443 static const struct mips16_immed_operand mips16_immed_operands
[] =
8445 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8446 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8447 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8448 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8449 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8450 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8451 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8452 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8453 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8454 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8455 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8456 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8457 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8458 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8459 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8460 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8461 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8462 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8463 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8464 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8465 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8468 #define MIPS16_NUM_IMMED \
8469 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8471 /* Handle a mips16 instruction with an immediate value. This or's the
8472 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8473 whether an extended value is needed; if one is needed, it sets
8474 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8475 If SMALL is true, an unextended opcode was explicitly requested.
8476 If EXT is true, an extended opcode was explicitly requested. If
8477 WARN is true, warn if EXT does not match reality. */
8480 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8489 unsigned long *insn
;
8490 boolean
*use_extend
;
8491 unsigned short *extend
;
8493 register const struct mips16_immed_operand
*op
;
8494 int mintiny
, maxtiny
;
8497 op
= mips16_immed_operands
;
8498 while (op
->type
!= type
)
8501 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8506 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8509 maxtiny
= 1 << op
->nbits
;
8514 maxtiny
= (1 << op
->nbits
) - 1;
8519 mintiny
= - (1 << (op
->nbits
- 1));
8520 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8523 /* Branch offsets have an implicit 0 in the lowest bit. */
8524 if (type
== 'p' || type
== 'q')
8527 if ((val
& ((1 << op
->shift
) - 1)) != 0
8528 || val
< (mintiny
<< op
->shift
)
8529 || val
> (maxtiny
<< op
->shift
))
8534 if (warn
&& ext
&& ! needext
)
8535 as_warn_where (file
, line
, "extended operand requested but not required");
8536 if (small
&& needext
)
8537 as_bad_where (file
, line
, "invalid unextended operand value");
8539 if (small
|| (! ext
&& ! needext
))
8543 *use_extend
= false;
8544 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8545 insnval
<<= op
->op_shift
;
8550 long minext
, maxext
;
8556 maxext
= (1 << op
->extbits
) - 1;
8560 minext
= - (1 << (op
->extbits
- 1));
8561 maxext
= (1 << (op
->extbits
- 1)) - 1;
8563 if (val
< minext
|| val
> maxext
)
8564 as_bad_where (file
, line
,
8565 "operand value out of range for instruction");
8568 if (op
->extbits
== 16)
8570 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8573 else if (op
->extbits
== 15)
8575 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8580 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8584 *extend
= (unsigned short) extval
;
8593 my_getSmallExpression (ep
, str
)
8604 ((str
[1] == 'h' && str
[2] == 'i')
8605 || (str
[1] == 'H' && str
[2] == 'I')
8606 || (str
[1] == 'l' && str
[2] == 'o'))
8618 * A small expression may be followed by a base register.
8619 * Scan to the end of this operand, and then back over a possible
8620 * base register. Then scan the small expression up to that
8621 * point. (Based on code in sparc.c...)
8623 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8625 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8627 if (isdigit (sp
[-2]))
8629 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8631 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8637 else if (sp
- 5 >= str
8640 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8641 || (sp
[-3] == 's' && sp
[-2] == 'p')
8642 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8643 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8649 /* no expression means zero offset */
8652 /* %xx(reg) is an error */
8653 ep
->X_op
= O_absent
;
8658 ep
->X_op
= O_constant
;
8661 ep
->X_add_symbol
= NULL
;
8662 ep
->X_op_symbol
= NULL
;
8663 ep
->X_add_number
= 0;
8668 my_getExpression (ep
, str
);
8675 my_getExpression (ep
, str
);
8676 return c
; /* => %hi or %lo encountered */
8680 my_getExpression (ep
, str
)
8686 save_in
= input_line_pointer
;
8687 input_line_pointer
= str
;
8689 expr_end
= input_line_pointer
;
8690 input_line_pointer
= save_in
;
8692 /* If we are in mips16 mode, and this is an expression based on `.',
8693 then we bump the value of the symbol by 1 since that is how other
8694 text symbols are handled. We don't bother to handle complex
8695 expressions, just `.' plus or minus a constant. */
8696 if (mips_opts
.mips16
8697 && ep
->X_op
== O_symbol
8698 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8699 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8700 && ep
->X_add_symbol
->sy_frag
== frag_now
8701 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8702 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8703 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8706 /* Turn a string in input_line_pointer into a floating point constant
8707 of type type, and store the appropriate bytes in *litP. The number
8708 of LITTLENUMS emitted is stored in *sizeP . An error message is
8709 returned, or NULL on OK. */
8712 md_atof (type
, litP
, sizeP
)
8718 LITTLENUM_TYPE words
[4];
8734 return "bad call to md_atof";
8737 t
= atof_ieee (input_line_pointer
, type
, words
);
8739 input_line_pointer
= t
;
8743 if (! target_big_endian
)
8745 for (i
= prec
- 1; i
>= 0; i
--)
8747 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8753 for (i
= 0; i
< prec
; i
++)
8755 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8764 md_number_to_chars (buf
, val
, n
)
8769 if (target_big_endian
)
8770 number_to_chars_bigendian (buf
, val
, n
);
8772 number_to_chars_littleendian (buf
, val
, n
);
8775 CONST
char *md_shortopts
= "O::g::G:";
8777 struct option md_longopts
[] = {
8778 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8779 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8780 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8781 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8782 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8783 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8784 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8785 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8786 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8787 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8788 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8789 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8790 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8791 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8792 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8793 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8794 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8795 {"break", no_argument
, NULL
, OPTION_BREAK
},
8796 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8797 #define OPTION_EB (OPTION_MD_BASE + 11)
8798 {"EB", no_argument
, NULL
, OPTION_EB
},
8799 #define OPTION_EL (OPTION_MD_BASE + 12)
8800 {"EL", no_argument
, NULL
, OPTION_EL
},
8801 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8802 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8803 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8804 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8805 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8806 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8807 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8808 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8809 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8810 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8811 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8812 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8813 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8814 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8815 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8816 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8817 /* start-sanitize-r5900 */
8818 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8819 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8820 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8821 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8822 /* end-sanitize-r5900 */
8823 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8824 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8825 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8826 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8828 /* start-sanitize-tx19 */
8829 {"m1900", no_argument
, NULL
, OPTION_M3900
},
8830 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
8831 /* end-sanitize-tx19 */
8833 /* start-sanitize-vr5400 */
8834 #define OPTION_M5400 (OPTION_MD_BASE + 28)
8835 {"m5400", no_argument
, NULL
, OPTION_M5400
},
8836 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
8837 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
8839 /* end-sanitize-vr5400 */
8840 /* start-sanitize-tx49 */
8841 #define OPTION_M4900 (OPTION_MD_BASE + 30)
8842 {"m4900", no_argument
, NULL
, OPTION_M4900
},
8843 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
8844 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
8846 /* end-sanitize-tx49 */
8847 /* start-sanitize-vr4320 */
8848 #define OPTION_M4320 (OPTION_MD_BASE + 32)
8849 {"m4320", no_argument
, NULL
, OPTION_M4320
},
8850 #define OPTION_NO_M4320 (OPTION_MD_BASE + 33)
8851 {"no-m4320", no_argument
, NULL
, OPTION_NO_M4320
},
8853 /* end-sanitize-vr4320 */
8854 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8855 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8856 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8857 #define OPTION_32 (OPTION_MD_BASE + 20)
8858 #define OPTION_64 (OPTION_MD_BASE + 21)
8860 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8861 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8862 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8863 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8864 {"32", no_argument
, NULL
, OPTION_32
},
8865 {"64", no_argument
, NULL
, OPTION_64
},
8868 {NULL
, no_argument
, NULL
, 0}
8870 size_t md_longopts_size
= sizeof(md_longopts
);
8873 md_parse_option (c
, arg
)
8888 target_big_endian
= 1;
8892 target_big_endian
= 0;
8896 if (arg
&& arg
[1] == '0')
8906 mips_debug
= atoi (arg
);
8907 /* When the MIPS assembler sees -g or -g2, it does not do
8908 optimizations which limit full symbolic debugging. We take
8909 that to be equivalent to -O0. */
8910 if (mips_debug
== 2)
8934 /* Identify the processor type */
8936 if (strcmp (p
, "default") == 0
8937 || strcmp (p
, "DEFAULT") == 0)
8943 /* We need to cope with the various "vr" prefixes for the 4300
8945 if (*p
== 'v' || *p
== 'V')
8951 if (*p
== 'r' || *p
== 'R')
8958 if (strcmp (p
, "10000") == 0
8959 || strcmp (p
, "10k") == 0
8960 || strcmp (p
, "10K") == 0)
8962 /* start-sanitize-tx19 */
8963 else if (strcmp (p
, "1900") == 0)
8965 /* end-sanitize-tx19 */
8969 if (strcmp (p
, "2000") == 0
8970 || strcmp (p
, "2k") == 0
8971 || strcmp (p
, "2K") == 0)
8976 if (strcmp (p
, "3000") == 0
8977 || strcmp (p
, "3k") == 0
8978 || strcmp (p
, "3K") == 0)
8980 else if (strcmp (p
, "3900") == 0)
8985 if (strcmp (p
, "4000") == 0
8986 || strcmp (p
, "4k") == 0
8987 || strcmp (p
, "4K") == 0)
8989 else if (strcmp (p
, "4100") == 0)
8991 else if (strcmp (p
, "4300") == 0)
8993 /* start-sanitize-vr4320 */
8994 else if (strcmp (p
, "4320") == 0)
8996 /* end-sanitize-vr4320 */
8997 else if (strcmp (p
, "4400") == 0)
8999 else if (strcmp (p
, "4600") == 0)
9001 else if (strcmp (p
, "4650") == 0)
9003 /* start-sanitize-tx49 */
9004 else if (strcmp (p
, "4900") == 0)
9006 /* end-sanitize-tx49 */
9007 else if (strcmp (p
, "4010") == 0)
9012 if (strcmp (p
, "5000") == 0
9013 || strcmp (p
, "5k") == 0
9014 || strcmp (p
, "5K") == 0)
9016 /* start-sanitize-vr5400 */
9017 else if (strcmp (p
, "5400") == 0)
9019 /* end-sanitize-vr5400 */
9020 /* start-sanitize-r5900 */
9021 else if (strcmp (p
, "5900") == 0)
9023 /* end-sanitize-r5900 */
9027 if (strcmp (p
, "6000") == 0
9028 || strcmp (p
, "6k") == 0
9029 || strcmp (p
, "6K") == 0)
9034 if (strcmp (p
, "8000") == 0
9035 || strcmp (p
, "8k") == 0
9036 || strcmp (p
, "8K") == 0)
9041 if (strcmp (p
, "orion") == 0)
9047 && (mips_cpu
!= 4300
9049 /* start-sanitize-vr4320 */
9051 /* end-sanitize-vr4320 */
9052 /* start-sanitize-vr5400 */
9054 /* end-sanitize-vr5400 */
9055 && mips_cpu
!= 5000))
9057 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
9063 as_bad ("invalid architecture -mcpu=%s", arg
);
9074 case OPTION_NO_M4650
:
9082 case OPTION_NO_M4010
:
9090 case OPTION_NO_M4100
:
9094 /* start-sanitize-r5900 */
9099 case OPTION_NO_M5900
:
9102 /* end-sanitize-r5900 */
9104 /* start-sanitize-vr4320 */
9109 case OPTION_NO_M4320
:
9113 /* end-sanitize-vr4320 */
9114 /* start-sanitize-vr5400 */
9119 case OPTION_NO_M5400
:
9123 /* end-sanitize-vr5400 */
9128 case OPTION_NO_M3900
:
9132 /* start-sanitize-tx49 */
9137 case OPTION_NO_M4900
:
9141 /* end-sanitize-tx49 */
9143 mips_opts
.mips16
= 1;
9144 mips_no_prev_insn (false);
9147 case OPTION_NO_MIPS16
:
9148 mips_opts
.mips16
= 0;
9149 mips_no_prev_insn (false);
9152 case OPTION_MEMBEDDED_PIC
:
9153 mips_pic
= EMBEDDED_PIC
;
9154 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9156 as_bad ("-G may not be used with embedded PIC code");
9159 g_switch_value
= 0x7fffffff;
9162 /* When generating ELF code, we permit -KPIC and -call_shared to
9163 select SVR4_PIC, and -non_shared to select no PIC. This is
9164 intended to be compatible with Irix 5. */
9165 case OPTION_CALL_SHARED
:
9166 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9168 as_bad ("-call_shared is supported only for ELF format");
9171 mips_pic
= SVR4_PIC
;
9172 if (g_switch_seen
&& g_switch_value
!= 0)
9174 as_bad ("-G may not be used with SVR4 PIC code");
9180 case OPTION_NON_SHARED
:
9181 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9183 as_bad ("-non_shared is supported only for ELF format");
9189 /* The -xgot option tells the assembler to use 32 offsets when
9190 accessing the got in SVR4_PIC mode. It is for Irix
9197 if (! USE_GLOBAL_POINTER_OPT
)
9199 as_bad ("-G is not supported for this configuration");
9202 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9204 as_bad ("-G may not be used with SVR4 or embedded PIC code");
9208 g_switch_value
= atoi (arg
);
9212 /* The -32 and -64 options tell the assembler to output the 32
9213 bit or the 64 bit MIPS ELF format. */
9220 const char **list
, **l
;
9222 list
= bfd_target_list ();
9223 for (l
= list
; *l
!= NULL
; l
++)
9224 if (strcmp (*l
, "elf64-bigmips") == 0
9225 || strcmp (*l
, "elf64-littlemips") == 0)
9228 as_fatal ("No compiled in support for 64 bit object file format");
9242 md_show_usage (stream
)
9247 -membedded-pic generate embedded position independent code\n\
9248 -EB generate big endian output\n\
9249 -EL generate little endian output\n\
9250 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9251 -G NUM allow referencing objects up to NUM bytes\n\
9252 implicitly with the gp register [default 8]\n");
9254 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
9255 -mips2, -mcpu=r6000 generate code for r6000\n\
9256 -mips3, -mcpu=r4000 generate code for r4000\n\
9257 -mips4, -mcpu=r8000 generate code for r8000\n\
9258 -mcpu=vr4300 generate code for vr4300\n\
9259 -mcpu=vr4100 generate code for vr4100\n\
9260 -m4650 permit R4650 instructions\n\
9261 -no-m4650 do not permit R4650 instructions\n\
9262 -m4010 permit R4010 instructions\n\
9263 -no-m4010 do not permit R4010 instructions\n\
9264 -m4100 permit VR4100 instructions\n\
9265 -no-m4100 do not permit VR4100 instructions\n");
9267 -mips16 generate mips16 instructions\n\
9268 -no-mips16 do not generate mips16 instructions\n");
9270 -O0 remove unneeded NOPs, do not swap branches\n\
9271 -O remove unneeded NOPs and swap branches\n\
9272 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9273 --break, --no-trap break exception on div by 0 and mult overflow\n");
9276 -KPIC, -call_shared generate SVR4 position independent code\n\
9277 -non_shared do not generate position independent code\n\
9278 -xgot assume a 32 bit GOT\n\
9279 -32 create 32 bit object file (default)\n\
9280 -64 create 64 bit object file\n");
9285 mips_init_after_args ()
9287 /* initialize opcodes */
9288 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9289 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9293 md_pcrel_from (fixP
)
9296 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9297 && fixP
->fx_addsy
!= (symbolS
*) NULL
9298 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9300 /* This makes a branch to an undefined symbol be a branch to the
9301 current location. */
9305 /* return the address of the delay slot */
9306 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9309 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9310 reloc for a cons. We could use the definition there, except that
9311 we want to handle 64 bit relocs specially. */
9314 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9317 unsigned int nbytes
;
9321 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9323 if (nbytes
== 8 && ! mips_64
)
9325 if (target_big_endian
)
9331 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9332 as_bad ("Unsupported reloc size %d", nbytes
);
9334 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9337 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9340 /* This is called before the symbol table is processed. In order to
9341 work with gcc when using mips-tfile, we must keep all local labels.
9342 However, in other cases, we want to discard them. If we were
9343 called with -g, but we didn't see any debugging information, it may
9344 mean that gcc is smuggling debugging information through to
9345 mips-tfile, in which case we must generate all local labels. */
9348 mips_frob_file_before_adjust ()
9350 #ifndef NO_ECOFF_DEBUGGING
9353 && ! ecoff_debugging_seen
)
9354 flag_keep_locals
= 1;
9358 /* Sort any unmatched HI16_S relocs so that they immediately precede
9359 the corresponding LO reloc. This is called before md_apply_fix and
9360 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9361 explicit use of the %hi modifier. */
9366 struct mips_hi_fixup
*l
;
9368 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9370 segment_info_type
*seginfo
;
9373 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9375 /* Check quickly whether the next fixup happens to be a matching
9377 if (l
->fixp
->fx_next
!= NULL
9378 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9379 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9380 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9383 /* Look through the fixups for this segment for a matching %lo.
9384 When we find one, move the %hi just in front of it. We do
9385 this in two passes. In the first pass, we try to find a
9386 unique %lo. In the second pass, we permit multiple %hi
9387 relocs for a single %lo (this is a GNU extension). */
9388 seginfo
= seg_info (l
->seg
);
9389 for (pass
= 0; pass
< 2; pass
++)
9394 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9396 /* Check whether this is a %lo fixup which matches l->fixp. */
9397 if (f
->fx_r_type
== BFD_RELOC_LO16
9398 && f
->fx_addsy
== l
->fixp
->fx_addsy
9399 && f
->fx_offset
== l
->fixp
->fx_offset
9402 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9403 || prev
->fx_addsy
!= f
->fx_addsy
9404 || prev
->fx_offset
!= f
->fx_offset
))
9408 /* Move l->fixp before f. */
9409 for (pf
= &seginfo
->fix_root
;
9411 pf
= &(*pf
)->fx_next
)
9412 assert (*pf
!= NULL
);
9414 *pf
= l
->fixp
->fx_next
;
9416 l
->fixp
->fx_next
= f
;
9418 seginfo
->fix_root
= l
->fixp
;
9420 prev
->fx_next
= l
->fixp
;
9432 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9433 "Unmatched %%hi reloc");
9438 /* When generating embedded PIC code we need to use a special
9439 relocation to represent the difference of two symbols in the .text
9440 section (switch tables use a difference of this sort). See
9441 include/coff/mips.h for details. This macro checks whether this
9442 fixup requires the special reloc. */
9443 #define SWITCH_TABLE(fixp) \
9444 ((fixp)->fx_r_type == BFD_RELOC_32 \
9445 && (fixp)->fx_addsy != NULL \
9446 && (fixp)->fx_subsy != NULL \
9447 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9448 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9450 /* When generating embedded PIC code we must keep all PC relative
9451 relocations, in case the linker has to relax a call. We also need
9452 to keep relocations for switch table entries. */
9456 mips_force_relocation (fixp
)
9459 return (mips_pic
== EMBEDDED_PIC
9461 || SWITCH_TABLE (fixp
)
9462 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9463 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9466 /* Apply a fixup to the object file. */
9469 md_apply_fix (fixP
, valueP
)
9476 assert (fixP
->fx_size
== 4
9477 || fixP
->fx_r_type
== BFD_RELOC_16
9478 || fixP
->fx_r_type
== BFD_RELOC_64
);
9482 /* If we aren't adjusting this fixup to be against the section
9483 symbol, we need to adjust the value. */
9485 if (fixP
->fx_addsy
!= NULL
9486 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
9487 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
9489 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9490 if (value
!= 0 && ! fixP
->fx_pcrel
)
9492 /* In this case, the bfd_install_relocation routine will
9493 incorrectly add the symbol value back in. We just want
9494 the addend to appear in the object file. */
9495 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9500 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9502 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9505 switch (fixP
->fx_r_type
)
9507 case BFD_RELOC_MIPS_JMP
:
9508 case BFD_RELOC_HI16
:
9509 case BFD_RELOC_HI16_S
:
9510 case BFD_RELOC_MIPS_GPREL
:
9511 case BFD_RELOC_MIPS_LITERAL
:
9512 case BFD_RELOC_MIPS_CALL16
:
9513 case BFD_RELOC_MIPS_GOT16
:
9514 case BFD_RELOC_MIPS_GPREL32
:
9515 case BFD_RELOC_MIPS_GOT_HI16
:
9516 case BFD_RELOC_MIPS_GOT_LO16
:
9517 case BFD_RELOC_MIPS_CALL_HI16
:
9518 case BFD_RELOC_MIPS_CALL_LO16
:
9519 case BFD_RELOC_MIPS16_GPREL
:
9521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9522 "Invalid PC relative reloc");
9523 /* Nothing needed to do. The value comes from the reloc entry */
9526 case BFD_RELOC_MIPS16_JMP
:
9527 /* We currently always generate a reloc against a symbol, which
9528 means that we don't want an addend even if the symbol is
9530 fixP
->fx_addnumber
= 0;
9533 case BFD_RELOC_PCREL_HI16_S
:
9534 /* The addend for this is tricky if it is internal, so we just
9535 do everything here rather than in bfd_install_relocation. */
9536 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9538 /* For an external symbol adjust by the address to make it
9539 pcrel_offset. We use the address of the RELLO reloc
9540 which follows this one. */
9541 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9542 + fixP
->fx_next
->fx_where
);
9547 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9548 if (target_big_endian
)
9550 md_number_to_chars (buf
, value
, 2);
9553 case BFD_RELOC_PCREL_LO16
:
9554 /* The addend for this is tricky if it is internal, so we just
9555 do everything here rather than in bfd_install_relocation. */
9556 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9557 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9558 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9559 if (target_big_endian
)
9561 md_number_to_chars (buf
, value
, 2);
9565 /* This is handled like BFD_RELOC_32, but we output a sign
9566 extended value if we are only 32 bits. */
9568 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9570 if (8 <= sizeof (valueT
))
9571 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9578 w1
= w2
= fixP
->fx_where
;
9579 if (target_big_endian
)
9583 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9584 if ((value
& 0x80000000) != 0)
9588 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9594 /* If we are deleting this reloc entry, we must fill in the
9595 value now. This can happen if we have a .word which is not
9596 resolved when it appears but is later defined. We also need
9597 to fill in the value if this is an embedded PIC switch table
9600 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9601 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9606 /* If we are deleting this reloc entry, we must fill in the
9608 assert (fixP
->fx_size
== 2);
9610 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9614 case BFD_RELOC_LO16
:
9615 /* When handling an embedded PIC switch statement, we can wind
9616 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9619 if (value
< -0x8000 || value
> 0x7fff)
9620 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9621 "relocation overflow");
9622 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9623 if (target_big_endian
)
9625 md_number_to_chars (buf
, value
, 2);
9629 case BFD_RELOC_16_PCREL_S2
:
9631 * We need to save the bits in the instruction since fixup_segment()
9632 * might be deleting the relocation entry (i.e., a branch within
9633 * the current segment).
9635 if ((value
& 0x3) != 0)
9636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9637 "Branch to odd address (%lx)", value
);
9640 /* update old instruction data */
9641 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9642 if (target_big_endian
)
9643 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9645 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9647 if (value
>= -0x8000 && value
< 0x8000)
9648 insn
|= value
& 0xffff;
9651 /* The branch offset is too large. If this is an
9652 unconditional branch, and we are not generating PIC code,
9653 we can convert it to an absolute jump instruction. */
9654 if (mips_pic
== NO_PIC
9656 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9657 && (fixP
->fx_frag
->fr_address
9658 < text_section
->vma
+ text_section
->_raw_size
)
9659 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9660 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9661 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9663 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9664 insn
= 0x0c000000; /* jal */
9666 insn
= 0x08000000; /* j */
9667 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9669 fixP
->fx_addsy
= section_symbol (text_section
);
9670 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9674 /* FIXME. It would be possible in principle to handle
9675 conditional branches which overflow. They could be
9676 transformed into a branch around a jump. This would
9677 require setting up variant frags for each different
9678 branch type. The native MIPS assembler attempts to
9679 handle these cases, but it appears to do it
9681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9682 "Branch out of range");
9686 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9701 const struct mips_opcode
*p
;
9702 int treg
, sreg
, dreg
, shamt
;
9707 for (i
= 0; i
< NUMOPCODES
; ++i
)
9709 p
= &mips_opcodes
[i
];
9710 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9712 printf ("%08lx %s\t", oc
, p
->name
);
9713 treg
= (oc
>> 16) & 0x1f;
9714 sreg
= (oc
>> 21) & 0x1f;
9715 dreg
= (oc
>> 11) & 0x1f;
9716 shamt
= (oc
>> 6) & 0x1f;
9718 for (args
= p
->args
;; ++args
)
9729 printf ("%c", *args
);
9733 assert (treg
== sreg
);
9734 printf ("$%d,$%d", treg
, sreg
);
9739 printf ("$%d", dreg
);
9744 printf ("$%d", treg
);
9748 printf ("0x%x", treg
);
9753 printf ("$%d", sreg
);
9757 printf ("0x%08lx", oc
& 0x1ffffff);
9769 printf ("$%d", shamt
);
9780 printf ("%08lx UNDEFINED\n", oc
);
9791 name
= input_line_pointer
;
9792 c
= get_symbol_end ();
9793 p
= (symbolS
*) symbol_find_or_make (name
);
9794 *input_line_pointer
= c
;
9798 /* Align the current frag to a given power of two. The MIPS assembler
9799 also automatically adjusts any preceding label. */
9802 mips_align (to
, fill
, label
)
9807 mips_emit_delays (false);
9808 frag_align (to
, fill
, 0);
9809 record_alignment (now_seg
, to
);
9812 assert (S_GET_SEGMENT (label
) == now_seg
);
9813 label
->sy_frag
= frag_now
;
9814 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9818 /* Align to a given power of two. .align 0 turns off the automatic
9819 alignment used by the data creating pseudo-ops. */
9826 register long temp_fill
;
9827 long max_alignment
= 15;
9831 o Note that the assembler pulls down any immediately preceeding label
9832 to the aligned address.
9833 o It's not documented but auto alignment is reinstated by
9834 a .align pseudo instruction.
9835 o Note also that after auto alignment is turned off the mips assembler
9836 issues an error on attempt to assemble an improperly aligned data item.
9841 temp
= get_absolute_expression ();
9842 if (temp
> max_alignment
)
9843 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9846 as_warn ("Alignment negative: 0 assumed.");
9849 if (*input_line_pointer
== ',')
9851 input_line_pointer
++;
9852 temp_fill
= get_absolute_expression ();
9859 mips_align (temp
, (int) temp_fill
,
9860 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9867 demand_empty_rest_of_line ();
9871 mips_flush_pending_output ()
9873 mips_emit_delays (false);
9874 mips_clear_insn_labels ();
9883 /* When generating embedded PIC code, we only use the .text, .lit8,
9884 .sdata and .sbss sections. We change the .data and .rdata
9885 pseudo-ops to use .sdata. */
9886 if (mips_pic
== EMBEDDED_PIC
9887 && (sec
== 'd' || sec
== 'r'))
9891 /* The ELF backend needs to know that we are changing sections, so
9892 that .previous works correctly. We could do something like check
9893 for a obj_section_change_hook macro, but that might be confusing
9894 as it would not be appropriate to use it in the section changing
9895 functions in read.c, since obj-elf.c intercepts those. FIXME:
9896 This should be cleaner, somehow. */
9897 obj_elf_section_change_hook ();
9900 mips_emit_delays (false);
9910 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9911 demand_empty_rest_of_line ();
9915 if (USE_GLOBAL_POINTER_OPT
)
9917 seg
= subseg_new (RDATA_SECTION_NAME
,
9918 (subsegT
) get_absolute_expression ());
9919 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9921 bfd_set_section_flags (stdoutput
, seg
,
9927 if (strcmp (TARGET_OS
, "elf") != 0)
9928 bfd_set_section_alignment (stdoutput
, seg
, 4);
9930 demand_empty_rest_of_line ();
9934 as_bad ("No read only data section in this object file format");
9935 demand_empty_rest_of_line ();
9941 if (USE_GLOBAL_POINTER_OPT
)
9943 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9944 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9946 bfd_set_section_flags (stdoutput
, seg
,
9947 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9949 if (strcmp (TARGET_OS
, "elf") != 0)
9950 bfd_set_section_alignment (stdoutput
, seg
, 4);
9952 demand_empty_rest_of_line ();
9957 as_bad ("Global pointers not supported; recompile -G 0");
9958 demand_empty_rest_of_line ();
9967 mips_enable_auto_align ()
9978 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9979 mips_emit_delays (false);
9980 if (log_size
> 0 && auto_align
)
9981 mips_align (log_size
, 0, label
);
9982 mips_clear_insn_labels ();
9983 cons (1 << log_size
);
9992 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9994 mips_emit_delays (false);
9998 mips_align (3, 0, label
);
10000 mips_align (2, 0, label
);
10002 mips_clear_insn_labels ();
10007 /* Handle .globl. We need to override it because on Irix 5 you are
10010 where foo is an undefined symbol, to mean that foo should be
10011 considered to be the address of a function. */
10022 name
= input_line_pointer
;
10023 c
= get_symbol_end ();
10024 symbolP
= symbol_find_or_make (name
);
10025 *input_line_pointer
= c
;
10026 SKIP_WHITESPACE ();
10028 /* On Irix 5, every global symbol that is not explicitly labelled as
10029 being a function is apparently labelled as being an object. */
10032 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10037 secname
= input_line_pointer
;
10038 c
= get_symbol_end ();
10039 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10041 as_bad ("%s: no such section", secname
);
10042 *input_line_pointer
= c
;
10044 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10045 flag
= BSF_FUNCTION
;
10048 symbolP
->bsym
->flags
|= flag
;
10050 S_SET_EXTERNAL (symbolP
);
10051 demand_empty_rest_of_line ();
10061 opt
= input_line_pointer
;
10062 c
= get_symbol_end ();
10066 /* FIXME: What does this mean? */
10068 else if (strncmp (opt
, "pic", 3) == 0)
10072 i
= atoi (opt
+ 3);
10076 mips_pic
= SVR4_PIC
;
10078 as_bad (".option pic%d not supported", i
);
10080 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10082 if (g_switch_seen
&& g_switch_value
!= 0)
10083 as_warn ("-G may not be used with SVR4 PIC code");
10084 g_switch_value
= 0;
10085 bfd_set_gp_size (stdoutput
, 0);
10089 as_warn ("Unrecognized option \"%s\"", opt
);
10091 *input_line_pointer
= c
;
10092 demand_empty_rest_of_line ();
10095 /* This structure is used to hold a stack of .set values. */
10097 struct mips_option_stack
10099 struct mips_option_stack
*next
;
10100 struct mips_set_options options
;
10103 static struct mips_option_stack
*mips_opts_stack
;
10105 /* Handle the .set pseudo-op. */
10111 char *name
= input_line_pointer
, ch
;
10113 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10114 input_line_pointer
++;
10115 ch
= *input_line_pointer
;
10116 *input_line_pointer
= '\0';
10118 if (strcmp (name
, "reorder") == 0)
10120 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10122 /* If we still have pending nops, we can discard them. The
10123 usual nop handling will insert any that are still
10125 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10126 * (mips_opts
.mips16
? 2 : 4));
10127 prev_nop_frag
= NULL
;
10129 mips_opts
.noreorder
= 0;
10131 else if (strcmp (name
, "noreorder") == 0)
10133 mips_emit_delays (true);
10134 mips_opts
.noreorder
= 1;
10135 mips_any_noreorder
= 1;
10137 else if (strcmp (name
, "at") == 0)
10139 mips_opts
.noat
= 0;
10141 else if (strcmp (name
, "noat") == 0)
10143 mips_opts
.noat
= 1;
10145 else if (strcmp (name
, "macro") == 0)
10147 mips_opts
.warn_about_macros
= 0;
10149 else if (strcmp (name
, "nomacro") == 0)
10151 if (mips_opts
.noreorder
== 0)
10152 as_bad ("`noreorder' must be set before `nomacro'");
10153 mips_opts
.warn_about_macros
= 1;
10155 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10157 mips_opts
.nomove
= 0;
10159 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10161 mips_opts
.nomove
= 1;
10163 else if (strcmp (name
, "bopt") == 0)
10165 mips_opts
.nobopt
= 0;
10167 else if (strcmp (name
, "nobopt") == 0)
10169 mips_opts
.nobopt
= 1;
10171 else if (strcmp (name
, "mips16") == 0
10172 || strcmp (name
, "MIPS-16") == 0)
10173 mips_opts
.mips16
= 1;
10174 else if (strcmp (name
, "nomips16") == 0
10175 || strcmp (name
, "noMIPS-16") == 0)
10176 mips_opts
.mips16
= 0;
10177 else if (strncmp (name
, "mips", 4) == 0)
10181 /* Permit the user to change the ISA on the fly. Needless to
10182 say, misuse can cause serious problems. */
10183 isa
= atoi (name
+ 4);
10185 mips_opts
.isa
= file_mips_isa
;
10186 else if (isa
< 1 || isa
> 4)
10187 as_bad ("unknown ISA level");
10189 mips_opts
.isa
= isa
;
10191 else if (strcmp (name
, "autoextend") == 0)
10192 mips_opts
.noautoextend
= 0;
10193 else if (strcmp (name
, "noautoextend") == 0)
10194 mips_opts
.noautoextend
= 1;
10195 else if (strcmp (name
, "push") == 0)
10197 struct mips_option_stack
*s
;
10199 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10200 s
->next
= mips_opts_stack
;
10201 s
->options
= mips_opts
;
10202 mips_opts_stack
= s
;
10204 else if (strcmp (name
, "pop") == 0)
10206 struct mips_option_stack
*s
;
10208 s
= mips_opts_stack
;
10210 as_bad (".set pop with no .set push");
10213 /* If we're changing the reorder mode we need to handle
10214 delay slots correctly. */
10215 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10216 mips_emit_delays (true);
10217 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10219 if (prev_nop_frag
!= NULL
)
10221 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10222 * (mips_opts
.mips16
? 2 : 4));
10223 prev_nop_frag
= NULL
;
10227 mips_opts
= s
->options
;
10228 mips_opts_stack
= s
->next
;
10234 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
10236 *input_line_pointer
= ch
;
10237 demand_empty_rest_of_line ();
10240 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10241 .option pic2. It means to generate SVR4 PIC calls. */
10244 s_abicalls (ignore
)
10247 mips_pic
= SVR4_PIC
;
10248 if (USE_GLOBAL_POINTER_OPT
)
10250 if (g_switch_seen
&& g_switch_value
!= 0)
10251 as_warn ("-G may not be used with SVR4 PIC code");
10252 g_switch_value
= 0;
10254 bfd_set_gp_size (stdoutput
, 0);
10255 demand_empty_rest_of_line ();
10258 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10259 PIC code. It sets the $gp register for the function based on the
10260 function address, which is in the register named in the argument.
10261 This uses a relocation against _gp_disp, which is handled specially
10262 by the linker. The result is:
10263 lui $gp,%hi(_gp_disp)
10264 addiu $gp,$gp,%lo(_gp_disp)
10265 addu $gp,$gp,.cpload argument
10266 The .cpload argument is normally $25 == $t9. */
10275 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10276 if (mips_pic
!= SVR4_PIC
)
10282 /* .cpload should be a in .set noreorder section. */
10283 if (mips_opts
.noreorder
== 0)
10284 as_warn (".cpload not in noreorder section");
10286 ex
.X_op
= O_symbol
;
10287 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10288 ex
.X_op_symbol
= NULL
;
10289 ex
.X_add_number
= 0;
10291 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10292 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10294 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10295 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10296 (int) BFD_RELOC_LO16
);
10298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10299 GP
, GP
, tc_get_register (0));
10301 demand_empty_rest_of_line ();
10304 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10305 offset from $sp. The offset is remembered, and after making a PIC
10306 call $gp is restored from that location. */
10309 s_cprestore (ignore
)
10315 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10316 if (mips_pic
!= SVR4_PIC
)
10322 mips_cprestore_offset
= get_absolute_expression ();
10324 ex
.X_op
= O_constant
;
10325 ex
.X_add_symbol
= NULL
;
10326 ex
.X_op_symbol
= NULL
;
10327 ex
.X_add_number
= mips_cprestore_offset
;
10329 macro_build ((char *) NULL
, &icnt
, &ex
,
10330 ((bfd_arch_bits_per_address (stdoutput
) == 32
10331 || mips_opts
.isa
< 3)
10333 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10335 demand_empty_rest_of_line ();
10338 /* Handle the .gpword pseudo-op. This is used when generating PIC
10339 code. It generates a 32 bit GP relative reloc. */
10349 /* When not generating PIC code, this is treated as .word. */
10350 if (mips_pic
!= SVR4_PIC
)
10356 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10357 mips_emit_delays (true);
10359 mips_align (2, 0, label
);
10360 mips_clear_insn_labels ();
10364 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10366 as_bad ("Unsupported use of .gpword");
10367 ignore_rest_of_line ();
10371 md_number_to_chars (p
, (valueT
) 0, 4);
10372 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10373 BFD_RELOC_MIPS_GPREL32
);
10375 demand_empty_rest_of_line ();
10378 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10379 tables in SVR4 PIC code. */
10388 /* This is ignored when not generating SVR4 PIC code. */
10389 if (mips_pic
!= SVR4_PIC
)
10395 /* Add $gp to the register named as an argument. */
10396 reg
= tc_get_register (0);
10397 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10398 ((bfd_arch_bits_per_address (stdoutput
) == 32
10399 || mips_opts
.isa
< 3)
10400 ? "addu" : "daddu"),
10401 "d,v,t", reg
, reg
, GP
);
10403 demand_empty_rest_of_line ();
10406 /* Handle the .insn pseudo-op. This marks instruction labels in
10407 mips16 mode. This permits the linker to handle them specially,
10408 such as generating jalx instructions when needed. We also make
10409 them odd for the duration of the assembly, in order to generate the
10410 right sort of code. We will make them even in the adjust_symtab
10411 routine, while leaving them marked. This is convenient for the
10412 debugger and the disassembler. The linker knows to make them odd
10419 if (mips_opts
.mips16
)
10420 mips16_mark_labels ();
10422 demand_empty_rest_of_line ();
10425 /* Handle a .stabn directive. We need these in order to mark a label
10426 as being a mips16 text label correctly. Sometimes the compiler
10427 will emit a label, followed by a .stabn, and then switch sections.
10428 If the label and .stabn are in mips16 mode, then the label is
10429 really a mips16 text label. */
10435 if (type
== 'n' && mips_opts
.mips16
)
10436 mips16_mark_labels ();
10441 /* Parse a register string into a number. Called from the ECOFF code
10442 to parse .frame. The argument is non-zero if this is the frame
10443 register, so that we can record it in mips_frame_reg. */
10446 tc_get_register (frame
)
10451 SKIP_WHITESPACE ();
10452 if (*input_line_pointer
++ != '$')
10454 as_warn ("expected `$'");
10457 else if (isdigit ((unsigned char) *input_line_pointer
))
10459 reg
= get_absolute_expression ();
10460 if (reg
< 0 || reg
>= 32)
10462 as_warn ("Bad register number");
10468 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10470 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10472 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10474 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10478 as_warn ("Unrecognized register name");
10481 input_line_pointer
+= 2;
10484 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10489 md_section_align (seg
, addr
)
10493 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10496 /* We don't need to align ELF sections to the full alignment.
10497 However, Irix 5 may prefer that we align them at least to a 16
10498 byte boundary. We don't bother to align the sections if we are
10499 targeted for an embedded system. */
10500 if (strcmp (TARGET_OS
, "elf") == 0)
10506 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10509 /* Utility routine, called from above as well. If called while the
10510 input file is still being read, it's only an approximation. (For
10511 example, a symbol may later become defined which appeared to be
10512 undefined earlier.) */
10515 nopic_need_relax (sym
, before_relaxing
)
10517 int before_relaxing
;
10522 if (USE_GLOBAL_POINTER_OPT
)
10524 const char *symname
;
10527 /* Find out whether this symbol can be referenced off the GP
10528 register. It can be if it is smaller than the -G size or if
10529 it is in the .sdata or .sbss section. Certain symbols can
10530 not be referenced off the GP, although it appears as though
10532 symname
= S_GET_NAME (sym
);
10533 if (symname
!= (const char *) NULL
10534 && (strcmp (symname
, "eprol") == 0
10535 || strcmp (symname
, "etext") == 0
10536 || strcmp (symname
, "_gp") == 0
10537 || strcmp (symname
, "edata") == 0
10538 || strcmp (symname
, "_fbss") == 0
10539 || strcmp (symname
, "_fdata") == 0
10540 || strcmp (symname
, "_ftext") == 0
10541 || strcmp (symname
, "end") == 0
10542 || strcmp (symname
, "_gp_disp") == 0))
10544 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10546 #ifndef NO_ECOFF_DEBUGGING
10547 || (sym
->ecoff_extern_size
!= 0
10548 && sym
->ecoff_extern_size
<= g_switch_value
)
10550 /* We must defer this decision until after the whole
10551 file has been read, since there might be a .extern
10552 after the first use of this symbol. */
10553 || (before_relaxing
10554 #ifndef NO_ECOFF_DEBUGGING
10555 && sym
->ecoff_extern_size
== 0
10557 && S_GET_VALUE (sym
) == 0)
10558 || (S_GET_VALUE (sym
) != 0
10559 && S_GET_VALUE (sym
) <= g_switch_value
)))
10563 const char *segname
;
10565 segname
= segment_name (S_GET_SEGMENT (sym
));
10566 assert (strcmp (segname
, ".lit8") != 0
10567 && strcmp (segname
, ".lit4") != 0);
10568 change
= (strcmp (segname
, ".sdata") != 0
10569 && strcmp (segname
, ".sbss") != 0);
10574 /* We are not optimizing for the GP register. */
10578 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10579 extended opcode. SEC is the section the frag is in. */
10582 mips16_extended_frag (fragp
, sec
, stretch
)
10588 register const struct mips16_immed_operand
*op
;
10590 int mintiny
, maxtiny
;
10593 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10595 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10598 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10599 op
= mips16_immed_operands
;
10600 while (op
->type
!= type
)
10603 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10608 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10611 maxtiny
= 1 << op
->nbits
;
10616 maxtiny
= (1 << op
->nbits
) - 1;
10621 mintiny
= - (1 << (op
->nbits
- 1));
10622 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10625 /* We can't call S_GET_VALUE here, because we don't want to lock in
10626 a particular frag address. */
10627 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10629 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10630 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10631 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10633 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10634 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10637 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10638 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10639 + fragp
->fr_symbol
->sy_value
.X_add_number
10640 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10641 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10650 /* We won't have the section when we are called from
10651 mips_relax_frag. However, we will always have been called
10652 from md_estimate_size_before_relax first. If this is a
10653 branch to a different section, we mark it as such. If SEC is
10654 NULL, and the frag is not marked, then it must be a branch to
10655 the same section. */
10658 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10665 fragp
->fr_subtype
=
10666 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10668 /* FIXME: We should support this, and let the linker
10669 catch branches and loads that are out of range. */
10670 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10671 "unsupported PC relative reference to different section");
10677 /* In this case, we know for sure that the symbol fragment is in
10678 the same section. If the fr_address of the symbol fragment
10679 is greater then the address of this fragment we want to add
10680 in STRETCH in order to get a better estimate of the address.
10681 This particularly matters because of the shift bits. */
10683 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10687 /* Adjust stretch for any alignment frag. Note that if have
10688 been expanding the earlier code, the symbol may be
10689 defined in what appears to be an earlier frag. FIXME:
10690 This doesn't handle the fr_subtype field, which specifies
10691 a maximum number of bytes to skip when doing an
10694 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10697 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10700 stretch
= - ((- stretch
)
10701 & ~ ((1 << (int) f
->fr_offset
) - 1));
10703 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10712 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10714 /* The base address rules are complicated. The base address of
10715 a branch is the following instruction. The base address of a
10716 PC relative load or add is the instruction itself, but if it
10717 is in a delay slot (in which case it can not be extended) use
10718 the address of the instruction whose delay slot it is in. */
10719 if (type
== 'p' || type
== 'q')
10723 /* If we are currently assuming that this frag should be
10724 extended, then, the current address is two bytes
10726 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10729 /* Ignore the low bit in the target, since it will be set
10730 for a text label. */
10731 if ((val
& 1) != 0)
10734 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10736 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10739 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10741 /* Branch offsets have an implicit 0 in the lowest bit. */
10742 if (type
== 'p' || type
== 'q')
10745 /* If any of the shifted bits are set, we must use an extended
10746 opcode. If the address depends on the size of this
10747 instruction, this can lead to a loop, so we arrange to always
10748 use an extended opcode. We only check this when we are in
10749 the main relaxation loop, when SEC is NULL. */
10750 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10752 fragp
->fr_subtype
=
10753 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10757 /* If we are about to mark a frag as extended because the value
10758 is precisely maxtiny + 1, then there is a chance of an
10759 infinite loop as in the following code:
10764 In this case when the la is extended, foo is 0x3fc bytes
10765 away, so the la can be shrunk, but then foo is 0x400 away, so
10766 the la must be extended. To avoid this loop, we mark the
10767 frag as extended if it was small, and is about to become
10768 extended with a value of maxtiny + 1. */
10769 if (val
== ((maxtiny
+ 1) << op
->shift
)
10770 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10773 fragp
->fr_subtype
=
10774 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10778 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10779 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
10781 if ((val
& ((1 << op
->shift
) - 1)) != 0
10782 || val
< (mintiny
<< op
->shift
)
10783 || val
> (maxtiny
<< op
->shift
))
10789 /* Estimate the size of a frag before relaxing. Unless this is the
10790 mips16, we are not really relaxing here, and the final size is
10791 encoded in the subtype information. For the mips16, we have to
10792 decide whether we are using an extended opcode or not. */
10796 md_estimate_size_before_relax (fragp
, segtype
)
10802 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10804 if (mips16_extended_frag (fragp
, segtype
, 0))
10806 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10811 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10816 if (mips_pic
== NO_PIC
)
10818 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10820 else if (mips_pic
== SVR4_PIC
)
10825 sym
= fragp
->fr_symbol
;
10827 /* Handle the case of a symbol equated to another symbol. */
10828 while (sym
->sy_value
.X_op
== O_symbol
10829 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10833 /* It's possible to get a loop here in a badly written
10835 n
= sym
->sy_value
.X_add_symbol
;
10841 symsec
= S_GET_SEGMENT (sym
);
10843 /* This must duplicate the test in adjust_reloc_syms. */
10844 change
= (symsec
!= &bfd_und_section
10845 && symsec
!= &bfd_abs_section
10846 && ! bfd_is_com_section (symsec
));
10853 /* Record the offset to the first reloc in the fr_opcode field.
10854 This lets md_convert_frag and tc_gen_reloc know that the code
10855 must be expanded. */
10856 fragp
->fr_opcode
= (fragp
->fr_literal
10858 - RELAX_OLD (fragp
->fr_subtype
)
10859 + RELAX_RELOC1 (fragp
->fr_subtype
));
10860 /* FIXME: This really needs as_warn_where. */
10861 if (RELAX_WARN (fragp
->fr_subtype
))
10862 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
10868 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10871 /* This is called to see whether a reloc against a defined symbol
10872 should be converted into a reloc against a section. Don't adjust
10873 MIPS16 jump relocations, so we don't have to worry about the format
10874 of the offset in the .o file. Don't adjust relocations against
10875 mips16 symbols, so that the linker can find them if it needs to set
10879 mips_fix_adjustable (fixp
)
10882 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10884 if (fixp
->fx_addsy
== NULL
)
10887 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10888 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10889 && fixp
->fx_subsy
== NULL
)
10895 /* Translate internal representation of relocation info to BFD target
10899 tc_gen_reloc (section
, fixp
)
10903 static arelent
*retval
[4];
10905 bfd_reloc_code_real_type code
;
10907 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10910 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10911 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10913 if (mips_pic
== EMBEDDED_PIC
10914 && SWITCH_TABLE (fixp
))
10916 /* For a switch table entry we use a special reloc. The addend
10917 is actually the difference between the reloc address and the
10919 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10920 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10921 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10922 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10924 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10926 /* We use a special addend for an internal RELLO reloc. */
10927 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10928 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10930 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10932 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10934 assert (fixp
->fx_next
!= NULL
10935 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10936 /* We use a special addend for an internal RELHI reloc. The
10937 reloc is relative to the RELLO; adjust the addend
10939 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10940 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10941 + fixp
->fx_next
->fx_where
10942 - S_GET_VALUE (fixp
->fx_subsy
));
10944 reloc
->addend
= (fixp
->fx_addnumber
10945 + fixp
->fx_next
->fx_frag
->fr_address
10946 + fixp
->fx_next
->fx_where
);
10948 else if (fixp
->fx_pcrel
== 0)
10949 reloc
->addend
= fixp
->fx_addnumber
;
10952 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10953 /* A gruesome hack which is a result of the gruesome gas reloc
10955 reloc
->addend
= reloc
->address
;
10957 reloc
->addend
= -reloc
->address
;
10960 /* If this is a variant frag, we may need to adjust the existing
10961 reloc and generate a new one. */
10962 if (fixp
->fx_frag
->fr_opcode
!= NULL
10963 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10964 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10965 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10966 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10967 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10968 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10969 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10973 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10975 /* If this is not the last reloc in this frag, then we have two
10976 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10977 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10978 the second one handle all of them. */
10979 if (fixp
->fx_next
!= NULL
10980 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10982 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10983 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10984 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10985 && (fixp
->fx_next
->fx_r_type
10986 == BFD_RELOC_MIPS_GOT_LO16
))
10987 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10988 && (fixp
->fx_next
->fx_r_type
10989 == BFD_RELOC_MIPS_CALL_LO16
)));
10994 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10995 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10996 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10998 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10999 reloc2
->address
= (reloc
->address
11000 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11001 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11002 reloc2
->addend
= fixp
->fx_addnumber
;
11003 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11004 assert (reloc2
->howto
!= NULL
);
11006 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11010 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11013 reloc3
->address
+= 4;
11016 if (mips_pic
== NO_PIC
)
11018 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11019 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11021 else if (mips_pic
== SVR4_PIC
)
11023 switch (fixp
->fx_r_type
)
11027 case BFD_RELOC_MIPS_GOT16
:
11029 case BFD_RELOC_MIPS_CALL16
:
11030 case BFD_RELOC_MIPS_GOT_LO16
:
11031 case BFD_RELOC_MIPS_CALL_LO16
:
11032 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11040 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11041 fixup_segment converted a non-PC relative reloc into a PC
11042 relative reloc. In such a case, we need to convert the reloc
11044 code
= fixp
->fx_r_type
;
11045 if (fixp
->fx_pcrel
)
11050 code
= BFD_RELOC_8_PCREL
;
11053 code
= BFD_RELOC_16_PCREL
;
11056 code
= BFD_RELOC_32_PCREL
;
11059 code
= BFD_RELOC_64_PCREL
;
11061 case BFD_RELOC_8_PCREL
:
11062 case BFD_RELOC_16_PCREL
:
11063 case BFD_RELOC_32_PCREL
:
11064 case BFD_RELOC_64_PCREL
:
11065 case BFD_RELOC_16_PCREL_S2
:
11066 case BFD_RELOC_PCREL_HI16_S
:
11067 case BFD_RELOC_PCREL_LO16
:
11070 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11071 "Cannot make %s relocation PC relative",
11072 bfd_get_reloc_code_name (code
));
11076 /* To support a PC relative reloc when generating embedded PIC code
11077 for ECOFF, we use a Cygnus extension. We check for that here to
11078 make sure that we don't let such a reloc escape normally. */
11079 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11080 && code
== BFD_RELOC_16_PCREL_S2
11081 && mips_pic
!= EMBEDDED_PIC
)
11082 reloc
->howto
= NULL
;
11084 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11086 if (reloc
->howto
== NULL
)
11088 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11089 "Can not represent %s relocation in this object file format",
11090 bfd_get_reloc_code_name (code
));
11097 /* Relax a machine dependent frag. This returns the amount by which
11098 the current size of the frag should change. */
11101 mips_relax_frag (fragp
, stretch
)
11105 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11108 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11110 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11112 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11117 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11119 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11126 /* Convert a machine dependent frag. */
11129 md_convert_frag (abfd
, asec
, fragp
)
11137 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11140 register const struct mips16_immed_operand
*op
;
11141 boolean small
, ext
;
11144 unsigned long insn
;
11145 boolean use_extend
;
11146 unsigned short extend
;
11148 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11149 op
= mips16_immed_operands
;
11150 while (op
->type
!= type
)
11153 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11164 resolve_symbol_value (fragp
->fr_symbol
, 1);
11165 val
= S_GET_VALUE (fragp
->fr_symbol
);
11170 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11172 /* The rules for the base address of a PC relative reloc are
11173 complicated; see mips16_extended_frag. */
11174 if (type
== 'p' || type
== 'q')
11179 /* Ignore the low bit in the target, since it will be
11180 set for a text label. */
11181 if ((val
& 1) != 0)
11184 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11186 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11189 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11192 /* Make sure the section winds up with the alignment we have
11195 record_alignment (asec
, op
->shift
);
11199 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11200 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11201 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11202 "extended instruction in delay slot");
11204 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11206 if (target_big_endian
)
11207 insn
= bfd_getb16 (buf
);
11209 insn
= bfd_getl16 (buf
);
11211 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11212 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11213 small
, ext
, &insn
, &use_extend
, &extend
);
11217 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11218 fragp
->fr_fix
+= 2;
11222 md_number_to_chars (buf
, insn
, 2);
11223 fragp
->fr_fix
+= 2;
11228 if (fragp
->fr_opcode
== NULL
)
11231 old
= RELAX_OLD (fragp
->fr_subtype
);
11232 new = RELAX_NEW (fragp
->fr_subtype
);
11233 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11236 memcpy (fixptr
- old
, fixptr
, new);
11238 fragp
->fr_fix
+= new - old
;
11244 /* This function is called after the relocs have been generated.
11245 We've been storing mips16 text labels as odd. Here we convert them
11246 back to even for the convenience of the debugger. */
11249 mips_frob_file_after_relocs ()
11252 unsigned int count
, i
;
11254 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11257 syms
= bfd_get_outsymbols (stdoutput
);
11258 count
= bfd_get_symcount (stdoutput
);
11259 for (i
= 0; i
< count
; i
++, syms
++)
11261 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11262 && ((*syms
)->value
& 1) != 0)
11264 (*syms
)->value
&= ~1;
11265 /* If the symbol has an odd size, it was probably computed
11266 incorrectly, so adjust that as well. */
11267 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11268 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11275 /* This function is called whenever a label is defined. It is used
11276 when handling branch delays; if a branch has a label, we assume we
11277 can not move it. */
11280 mips_define_label (sym
)
11283 struct insn_label_list
*l
;
11285 if (free_insn_labels
== NULL
)
11286 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11289 l
= free_insn_labels
;
11290 free_insn_labels
= l
->next
;
11294 l
->next
= insn_labels
;
11298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11300 /* Some special processing for a MIPS ELF file. */
11303 mips_elf_final_processing ()
11305 /* Write out the register information. */
11310 s
.ri_gprmask
= mips_gprmask
;
11311 s
.ri_cprmask
[0] = mips_cprmask
[0];
11312 s
.ri_cprmask
[1] = mips_cprmask
[1];
11313 s
.ri_cprmask
[2] = mips_cprmask
[2];
11314 s
.ri_cprmask
[3] = mips_cprmask
[3];
11315 /* The gp_value field is set by the MIPS ELF backend. */
11317 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11318 ((Elf32_External_RegInfo
*)
11319 mips_regmask_frag
));
11323 Elf64_Internal_RegInfo s
;
11325 s
.ri_gprmask
= mips_gprmask
;
11327 s
.ri_cprmask
[0] = mips_cprmask
[0];
11328 s
.ri_cprmask
[1] = mips_cprmask
[1];
11329 s
.ri_cprmask
[2] = mips_cprmask
[2];
11330 s
.ri_cprmask
[3] = mips_cprmask
[3];
11331 /* The gp_value field is set by the MIPS ELF backend. */
11333 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11334 ((Elf64_External_RegInfo
*)
11335 mips_regmask_frag
));
11338 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11339 sort of BFD interface for this. */
11340 if (mips_any_noreorder
)
11341 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11342 if (mips_pic
!= NO_PIC
)
11343 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11346 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11348 /* These functions should really be defined by the object file format,
11349 since they are related to debugging information. However, this
11350 code has to work for the a.out format, which does not define them,
11351 so we provide simple versions here. These don't actually generate
11352 any debugging information, but they do simple checking and someday
11353 somebody may make them useful. */
11357 struct loc
*loc_next
;
11358 unsigned long loc_fileno
;
11359 unsigned long loc_lineno
;
11360 unsigned long loc_offset
;
11361 unsigned short loc_delta
;
11362 unsigned short loc_count
;
11369 typedef struct proc
11371 struct proc
*proc_next
;
11372 struct symbol
*proc_isym
;
11373 struct symbol
*proc_end
;
11374 unsigned long proc_reg_mask
;
11375 unsigned long proc_reg_offset
;
11376 unsigned long proc_fpreg_mask
;
11377 unsigned long proc_fpreg_offset
;
11378 unsigned long proc_frameoffset
;
11379 unsigned long proc_framereg
;
11380 unsigned long proc_pcreg
;
11382 struct file
*proc_file
;
11387 typedef struct file
11389 struct file
*file_next
;
11390 unsigned long file_fileno
;
11391 struct symbol
*file_symbol
;
11392 struct symbol
*file_end
;
11393 struct proc
*file_proc
;
11398 static struct obstack proc_frags
;
11399 static procS
*proc_lastP
;
11400 static procS
*proc_rootP
;
11401 static int numprocs
;
11406 obstack_begin (&proc_frags
, 0x2000);
11412 /* check for premature end, nesting errors, etc */
11413 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11414 as_warn ("missing `.end' at end of assembly");
11423 if (*input_line_pointer
== '-')
11425 ++input_line_pointer
;
11428 if (!isdigit (*input_line_pointer
))
11429 as_bad ("Expected simple number.");
11430 if (input_line_pointer
[0] == '0')
11432 if (input_line_pointer
[1] == 'x')
11434 input_line_pointer
+= 2;
11435 while (isxdigit (*input_line_pointer
))
11438 val
|= hex_value (*input_line_pointer
++);
11440 return negative
? -val
: val
;
11444 ++input_line_pointer
;
11445 while (isdigit (*input_line_pointer
))
11448 val
|= *input_line_pointer
++ - '0';
11450 return negative
? -val
: val
;
11453 if (!isdigit (*input_line_pointer
))
11455 printf (" *input_line_pointer == '%c' 0x%02x\n",
11456 *input_line_pointer
, *input_line_pointer
);
11457 as_warn ("Invalid number");
11460 while (isdigit (*input_line_pointer
))
11463 val
+= *input_line_pointer
++ - '0';
11465 return negative
? -val
: val
;
11468 /* The .file directive; just like the usual .file directive, but there
11469 is an initial number which is the ECOFF file index. */
11477 line
= get_number ();
11482 /* The .end directive. */
11490 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11493 demand_empty_rest_of_line ();
11497 if (now_seg
!= text_section
)
11498 as_warn (".end not in text section");
11501 as_warn (".end and no .ent seen yet.");
11507 assert (S_GET_NAME (p
));
11508 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
11509 as_warn (".end symbol does not match .ent symbol.");
11512 proc_lastP
->proc_end
= (symbolS
*) 1;
11515 /* The .aent and .ent directives. */
11525 symbolP
= get_symbol ();
11526 if (*input_line_pointer
== ',')
11527 input_line_pointer
++;
11528 SKIP_WHITESPACE ();
11529 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11530 number
= get_number ();
11531 if (now_seg
!= text_section
)
11532 as_warn (".ent or .aent not in text section.");
11534 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11535 as_warn ("missing `.end'");
11539 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11540 procP
->proc_isym
= symbolP
;
11541 procP
->proc_reg_mask
= 0;
11542 procP
->proc_reg_offset
= 0;
11543 procP
->proc_fpreg_mask
= 0;
11544 procP
->proc_fpreg_offset
= 0;
11545 procP
->proc_frameoffset
= 0;
11546 procP
->proc_framereg
= 0;
11547 procP
->proc_pcreg
= 0;
11548 procP
->proc_end
= NULL
;
11549 procP
->proc_next
= NULL
;
11551 proc_lastP
->proc_next
= procP
;
11553 proc_rootP
= procP
;
11554 proc_lastP
= procP
;
11557 demand_empty_rest_of_line ();
11560 /* The .frame directive. */
11573 frame_reg
= tc_get_register (1);
11574 if (*input_line_pointer
== ',')
11575 input_line_pointer
++;
11576 frame_off
= get_absolute_expression ();
11577 if (*input_line_pointer
== ',')
11578 input_line_pointer
++;
11579 pcreg
= tc_get_register (0);
11581 /* bob third eye */
11582 assert (proc_rootP
);
11583 proc_rootP
->proc_framereg
= frame_reg
;
11584 proc_rootP
->proc_frameoffset
= frame_off
;
11585 proc_rootP
->proc_pcreg
= pcreg
;
11586 /* bob macho .frame */
11588 /* We don't have to write out a frame stab for unoptimized code. */
11589 if (!(frame_reg
== FP
&& frame_off
== 0))
11592 as_warn ("No .ent for .frame to use.");
11593 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11594 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11595 S_SET_TYPE (symP
, N_RMASK
);
11596 S_SET_OTHER (symP
, 0);
11597 S_SET_DESC (symP
, 0);
11598 symP
->sy_forward
= proc_lastP
->proc_isym
;
11599 /* bob perhaps I should have used pseudo set */
11601 demand_empty_rest_of_line ();
11605 /* The .fmask and .mask directives. */
11612 char str
[100], *strP
;
11618 mask
= get_number ();
11619 if (*input_line_pointer
== ',')
11620 input_line_pointer
++;
11621 off
= get_absolute_expression ();
11623 /* bob only for coff */
11624 assert (proc_rootP
);
11625 if (reg_type
== 'F')
11627 proc_rootP
->proc_fpreg_mask
= mask
;
11628 proc_rootP
->proc_fpreg_offset
= off
;
11632 proc_rootP
->proc_reg_mask
= mask
;
11633 proc_rootP
->proc_reg_offset
= off
;
11636 /* bob macho .mask + .fmask */
11638 /* We don't have to write out a mask stab if no saved regs. */
11642 as_warn ("No .ent for .mask to use.");
11644 for (i
= 0; i
< 32; i
++)
11648 sprintf (strP
, "%c%d,", reg_type
, i
);
11649 strP
+= strlen (strP
);
11653 sprintf (strP
, ";%d,", off
);
11654 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11655 S_SET_TYPE (symP
, N_RMASK
);
11656 S_SET_OTHER (symP
, 0);
11657 S_SET_DESC (symP
, 0);
11658 symP
->sy_forward
= proc_lastP
->proc_isym
;
11659 /* bob perhaps I should have used pseudo set */
11664 /* The .loc directive. */
11675 assert (now_seg
== text_section
);
11677 lineno
= get_number ();
11678 addroff
= frag_now_fix ();
11680 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11681 S_SET_TYPE (symbolP
, N_SLINE
);
11682 S_SET_OTHER (symbolP
, 0);
11683 S_SET_DESC (symbolP
, lineno
);
11684 symbolP
->sy_segment
= now_seg
;