1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 FIXME: The CPU specific variables (mips_4010, et. al.) should
146 probably be in here as well, and there should probably be some way
149 struct mips_set_options
151 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
152 if it has not been initialized. Changed by `.set mipsN', and the
153 -mipsN command line option, and the default CPU. */
155 /* Whether we are assembling for the mips16 processor. 0 if we are
156 not, 1 if we are, and -1 if the value has not been initialized.
157 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
158 -nomips16 command line options, and the default CPU. */
160 /* Non-zero if we should not reorder instructions. Changed by `.set
161 reorder' and `.set noreorder'. */
163 /* Non-zero if we should not permit the $at ($1) register to be used
164 in instructions. Changed by `.set at' and `.set noat'. */
166 /* Non-zero if we should warn when a macro instruction expands into
167 more than one machine instruction. Changed by `.set nomacro' and
169 int warn_about_macros
;
170 /* Non-zero if we should not move instructions. Changed by `.set
171 move', `.set volatile', `.set nomove', and `.set novolatile'. */
173 /* Non-zero if we should not optimize branches by moving the target
174 of the branch into the delay slot. Actually, we don't perform
175 this optimization anyhow. Changed by `.set bopt' and `.set
178 /* Non-zero if we should not autoextend mips16 instructions.
179 Changed by `.set autoextend' and `.set noautoextend'. */
183 /* This is the struct we use to hold the current set of options. Note
184 that we must set the isa and mips16 fields to -1 to indicate that
185 they have not been initialized. */
187 static struct mips_set_options mips_opts
= { -1, -1 };
189 /* These variables are filled in with the masks of registers used.
190 The object format code reads them and puts them in the appropriate
192 unsigned long mips_gprmask
;
193 unsigned long mips_cprmask
[4];
195 /* MIPS ISA we are using for this output file. */
196 static int file_mips_isa
;
198 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
199 static int mips_cpu
= -1;
201 /* Whether the 4650 instructions (mad/madu) are permitted. */
202 static int mips_4650
= -1;
204 /* Whether the 4010 instructions are permitted. */
205 static int mips_4010
= -1;
207 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
208 static int mips_4100
= -1;
210 /* start-sanitize-vr4320 */
211 /* Whether NEC vr4320 instructions are permitted. */
212 static int mips_4320
= -1;
214 /* end-sanitize-vr4320 */
215 /* start-sanitize-cygnus */
216 /* Whether NEC vr5400 instructions are permitted. */
217 static int mips_5400
= -1;
219 /* end-sanitize-cygnus */
220 /* start-sanitize-r5900 */
221 /* Whether Toshiba r5900 instructions are permitted. */
222 static int mips_5900
= -1;
224 /* end-sanitize-r5900 */
225 /* Whether Toshiba r3900 instructions are permitted. */
226 static int mips_3900
= -1;
228 /* start-sanitize-tx49 */
229 /* Whether Toshiba r4900 instructions are permitted. */
230 static int mips_4900
= -1;
232 /* end-sanitize-tx49 */
233 /* start-sanitize-tx19 */
234 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
235 The tx19 related options and configuration bits are handled by
237 /* end-sanitize-tx19 */
239 /* Whether the processor uses hardware interlocks to protect
240 reads from the HI and LO registers, and thus does not
241 require nops to be inserted.
243 FIXME: We really should not be checking mips_cpu here. The -mcpu=
244 option is documented to not do anything special. In gcc, the
245 -mcpu= option only affects scheduling, and does not affect code
246 generation. Each test of -mcpu= here should actually be testing a
247 specific variable, such as mips_4010, and each such variable should
248 have a command line option to set it. The -mcpu= option may be
249 used to set the default value of these options, as is the case for
252 #define hilo_interlocks (mips_4010 \
253 /* start-sanitize-tx49 */ \
254 || mips_cpu == 4900 || mips_4900 \
255 /* end-sanitize-tx49 */ \
256 /* start-sanitize-vr4320 */ \
257 || mips_cpu == 4320 \
258 /* end-sanitize-vr4320 */ \
259 /* start-sanitize-r5900 */ \
261 /* end-sanitize-r5900 */ \
264 /* Whether the processor uses hardware interlocks to protect reads
265 from the GPRs, and thus does not require nops to be inserted. */
266 #define gpr_interlocks \
267 (mips_opts.isa >= 2 \
268 /* start-sanitize-cygnus */ \
270 /* end-sanitize-cygnus */ \
271 /* start-sanitize-r5900 */ \
273 /* end-sanitize-r5900 */ \
276 /* As with other "interlocks" this is used by hardware that has FP
277 (co-processor) interlocks. */
278 /* Itbl support may require additional care here. */
279 #define cop_interlocks (mips_cpu == 4300 \
280 /* start-sanitize-vr4320 */ \
281 || mips_cpu == 4320 \
282 /* end-sanitize-vr4320 */ \
283 /* start-sanitize-cygnus */ \
284 || mips_cpu == 5400 \
285 /* end-sanitize-cygnus */ \
288 /* MIPS PIC level. */
292 /* Do not generate PIC code. */
295 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
296 not sure what it is supposed to do. */
299 /* Generate PIC code as in the SVR4 MIPS ABI. */
302 /* Generate PIC code without using a global offset table: the data
303 segment has a maximum size of 64K, all data references are off
304 the $gp register, and all text references are PC relative. This
305 is used on some embedded systems. */
309 static enum mips_pic_level mips_pic
;
311 /* 1 if we should generate 32 bit offsets from the GP register in
312 SVR4_PIC mode. Currently has no meaning in other modes. */
313 static int mips_big_got
;
315 /* 1 if trap instructions should used for overflow rather than break
317 static int mips_trap
;
319 /* Non-zero if any .set noreorder directives were used. */
321 static int mips_any_noreorder
;
323 /* The size of the small data section. */
324 static int g_switch_value
= 8;
325 /* Whether the -G option was used. */
326 static int g_switch_seen
= 0;
331 /* If we can determine in advance that GP optimization won't be
332 possible, we can skip the relaxation stuff that tries to produce
333 GP-relative references. This makes delay slot optimization work
336 This function can only provide a guess, but it seems to work for
337 gcc output. If it guesses wrong, the only loss should be in
338 efficiency; it shouldn't introduce any bugs.
340 I don't know if a fix is needed for the SVR4_PIC mode. I've only
341 fixed it for the non-PIC mode. KR 95/04/07 */
342 static int nopic_need_relax
PARAMS ((symbolS
*, int));
344 /* handle of the OPCODE hash table */
345 static struct hash_control
*op_hash
= NULL
;
347 /* The opcode hash table we use for the mips16. */
348 static struct hash_control
*mips16_op_hash
= NULL
;
350 /* This array holds the chars that always start a comment. If the
351 pre-processor is disabled, these aren't very useful */
352 const char comment_chars
[] = "#";
354 /* This array holds the chars that only start a comment at the beginning of
355 a line. If the line seems to have the form '# 123 filename'
356 .line and .file directives will appear in the pre-processed output */
357 /* Note that input_file.c hand checks for '#' at the beginning of the
358 first line of the input file. This is because the compiler outputs
359 #NO_APP at the beginning of its output. */
360 /* Also note that C style comments are always supported. */
361 const char line_comment_chars
[] = "#";
363 /* This array holds machine specific line separator characters. */
364 const char line_separator_chars
[] = "";
366 /* Chars that can be used to separate mant from exp in floating point nums */
367 const char EXP_CHARS
[] = "eE";
369 /* Chars that mean this number is a floating point constant */
372 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
374 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
375 changed in read.c . Ideally it shouldn't have to know about it at all,
376 but nothing is ideal around here.
379 static char *insn_error
;
381 static int auto_align
= 1;
383 /* When outputting SVR4 PIC code, the assembler needs to know the
384 offset in the stack frame from which to restore the $gp register.
385 This is set by the .cprestore pseudo-op, and saved in this
387 static offsetT mips_cprestore_offset
= -1;
389 /* This is the register which holds the stack frame, as set by the
390 .frame pseudo-op. This is needed to implement .cprestore. */
391 static int mips_frame_reg
= SP
;
393 /* To output NOP instructions correctly, we need to keep information
394 about the previous two instructions. */
396 /* Whether we are optimizing. The default value of 2 means to remove
397 unneeded NOPs and swap branch instructions when possible. A value
398 of 1 means to not swap branches. A value of 0 means to always
400 static int mips_optimize
= 2;
402 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
403 equivalent to seeing no -g option at all. */
404 static int mips_debug
= 0;
406 /* The previous instruction. */
407 static struct mips_cl_insn prev_insn
;
409 /* The instruction before prev_insn. */
410 static struct mips_cl_insn prev_prev_insn
;
412 /* If we don't want information for prev_insn or prev_prev_insn, we
413 point the insn_mo field at this dummy integer. */
414 static const struct mips_opcode dummy_opcode
= { 0 };
416 /* Non-zero if prev_insn is valid. */
417 static int prev_insn_valid
;
419 /* The frag for the previous instruction. */
420 static struct frag
*prev_insn_frag
;
422 /* The offset into prev_insn_frag for the previous instruction. */
423 static long prev_insn_where
;
425 /* The reloc type for the previous instruction, if any. */
426 static bfd_reloc_code_real_type prev_insn_reloc_type
;
428 /* The reloc for the previous instruction, if any. */
429 static fixS
*prev_insn_fixp
;
431 /* Non-zero if the previous instruction was in a delay slot. */
432 static int prev_insn_is_delay_slot
;
434 /* Non-zero if the previous instruction was in a .set noreorder. */
435 static int prev_insn_unreordered
;
437 /* Non-zero if the previous instruction uses an extend opcode (if
439 static int prev_insn_extended
;
441 /* Non-zero if the previous previous instruction was in a .set
443 static int prev_prev_insn_unreordered
;
445 /* start-sanitize-branchbug4011 */
446 /* Non-zero if the previous insn had one or more labels */
447 static int prev_insn_labels
;
449 /* end-sanitize-branchbug4011 */
450 /* If this is set, it points to a frag holding nop instructions which
451 were inserted before the start of a noreorder section. If those
452 nops turn out to be unnecessary, the size of the frag can be
454 static fragS
*prev_nop_frag
;
456 /* The number of nop instructions we created in prev_nop_frag. */
457 static int prev_nop_frag_holds
;
459 /* The number of nop instructions that we know we need in
461 static int prev_nop_frag_required
;
463 /* The number of instructions we've seen since prev_nop_frag. */
464 static int prev_nop_frag_since
;
466 /* For ECOFF and ELF, relocations against symbols are done in two
467 parts, with a HI relocation and a LO relocation. Each relocation
468 has only 16 bits of space to store an addend. This means that in
469 order for the linker to handle carries correctly, it must be able
470 to locate both the HI and the LO relocation. This means that the
471 relocations must appear in order in the relocation table.
473 In order to implement this, we keep track of each unmatched HI
474 relocation. We then sort them so that they immediately precede the
475 corresponding LO relocation. */
480 struct mips_hi_fixup
*next
;
483 /* The section this fixup is in. */
487 /* The list of unmatched HI relocs. */
489 static struct mips_hi_fixup
*mips_hi_fixup_list
;
491 /* Map normal MIPS register numbers to mips16 register numbers. */
493 #define X ILLEGAL_REG
494 static const int mips32_to_16_reg_map
[] =
496 X
, X
, 2, 3, 4, 5, 6, 7,
497 X
, X
, X
, X
, X
, X
, X
, X
,
498 0, 1, X
, X
, X
, X
, X
, X
,
499 X
, X
, X
, X
, X
, X
, X
, X
503 /* Map mips16 register numbers to normal MIPS register numbers. */
505 static const int mips16_to_32_reg_map
[] =
507 16, 17, 2, 3, 4, 5, 6, 7
510 /* Since the MIPS does not have multiple forms of PC relative
511 instructions, we do not have to do relaxing as is done on other
512 platforms. However, we do have to handle GP relative addressing
513 correctly, which turns out to be a similar problem.
515 Every macro that refers to a symbol can occur in (at least) two
516 forms, one with GP relative addressing and one without. For
517 example, loading a global variable into a register generally uses
518 a macro instruction like this:
520 If i can be addressed off the GP register (this is true if it is in
521 the .sbss or .sdata section, or if it is known to be smaller than
522 the -G argument) this will generate the following instruction:
524 This instruction will use a GPREL reloc. If i can not be addressed
525 off the GP register, the following instruction sequence will be used:
528 In this case the first instruction will have a HI16 reloc, and the
529 second reloc will have a LO16 reloc. Both relocs will be against
532 The issue here is that we may not know whether i is GP addressable
533 until after we see the instruction that uses it. Therefore, we
534 want to be able to choose the final instruction sequence only at
535 the end of the assembly. This is similar to the way other
536 platforms choose the size of a PC relative instruction only at the
539 When generating position independent code we do not use GP
540 addressing in quite the same way, but the issue still arises as
541 external symbols and local symbols must be handled differently.
543 We handle these issues by actually generating both possible
544 instruction sequences. The longer one is put in a frag_var with
545 type rs_machine_dependent. We encode what to do with the frag in
546 the subtype field. We encode (1) the number of existing bytes to
547 replace, (2) the number of new bytes to use, (3) the offset from
548 the start of the existing bytes to the first reloc we must generate
549 (that is, the offset is applied from the start of the existing
550 bytes after they are replaced by the new bytes, if any), (4) the
551 offset from the start of the existing bytes to the second reloc,
552 (5) whether a third reloc is needed (the third reloc is always four
553 bytes after the second reloc), and (6) whether to warn if this
554 variant is used (this is sometimes needed if .set nomacro or .set
555 noat is in effect). All these numbers are reasonably small.
557 Generating two instruction sequences must be handled carefully to
558 ensure that delay slots are handled correctly. Fortunately, there
559 are a limited number of cases. When the second instruction
560 sequence is generated, append_insn is directed to maintain the
561 existing delay slot information, so it continues to apply to any
562 code after the second instruction sequence. This means that the
563 second instruction sequence must not impose any requirements not
564 required by the first instruction sequence.
566 These variant frags are then handled in functions called by the
567 machine independent code. md_estimate_size_before_relax returns
568 the final size of the frag. md_convert_frag sets up the final form
569 of the frag. tc_gen_reloc adjust the first reloc and adds a second
571 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
575 | (((reloc1) + 64) << 9) \
576 | (((reloc2) + 64) << 2) \
577 | ((reloc3) ? (1 << 1) : 0) \
579 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
580 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
581 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
582 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
583 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
584 #define RELAX_WARN(i) ((i) & 1)
586 /* For mips16 code, we use an entirely different form of relaxation.
587 mips16 supports two versions of most instructions which take
588 immediate values: a small one which takes some small value, and a
589 larger one which takes a 16 bit value. Since branches also follow
590 this pattern, relaxing these values is required.
592 We can assemble both mips16 and normal MIPS code in a single
593 object. Therefore, we need to support this type of relaxation at
594 the same time that we support the relaxation described above. We
595 use the high bit of the subtype field to distinguish these cases.
597 The information we store for this type of relaxation is the
598 argument code found in the opcode file for this relocation, whether
599 the user explicitly requested a small or extended form, and whether
600 the relocation is in a jump or jal delay slot. That tells us the
601 size of the value, and how it should be stored. We also store
602 whether the fragment is considered to be extended or not. We also
603 store whether this is known to be a branch to a different section,
604 whether we have tried to relax this frag yet, and whether we have
605 ever extended a PC relative fragment because of a shift count. */
606 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
609 | ((small) ? 0x100 : 0) \
610 | ((ext) ? 0x200 : 0) \
611 | ((dslot) ? 0x400 : 0) \
612 | ((jal_dslot) ? 0x800 : 0))
613 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
614 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
615 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
616 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
617 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
618 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
619 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
620 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
621 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
622 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
623 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
624 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
625 /* start-sanitize-branchbug4011 */
626 /* The 4011 core has a bug in it's branch processing that
627 an be avoided if branches never branches (where branches
628 are defined as those starting with 'b'). We do this here
629 by insuring that labels are not directly on branch instructions,
630 and if they are inserting a no-op between the label and the
632 static int mips_fix_4011_branch_bug
= 0;
633 /* end-sanitize-branchbug4011 */
635 /* Prototypes for static functions. */
638 #define internalError() \
639 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
641 #define internalError() as_fatal (_("MIPS internal Error"));
644 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
646 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
647 unsigned int reg
, enum mips_regclass
class));
648 static int reg_needs_delay
PARAMS ((int));
649 static void mips16_mark_labels
PARAMS ((void));
650 static void append_insn
PARAMS ((char *place
,
651 struct mips_cl_insn
* ip
,
653 bfd_reloc_code_real_type r
,
655 static void mips_no_prev_insn
PARAMS ((int));
656 static void mips_emit_delays
PARAMS ((boolean
));
658 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
659 const char *name
, const char *fmt
,
662 static void macro_build ();
664 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
665 const char *, const char *,
667 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
668 expressionS
* ep
, int regnum
));
669 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
670 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
672 static void load_register
PARAMS ((int *, int, expressionS
*, int));
673 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
674 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
675 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
676 #ifdef LOSING_COMPILER
677 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
679 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
680 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
681 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
682 boolean
, boolean
, unsigned long *,
683 boolean
*, unsigned short *));
684 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
685 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
686 static symbolS
*get_symbol
PARAMS ((void));
687 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
688 static void s_align
PARAMS ((int));
689 static void s_change_sec
PARAMS ((int));
690 static void s_cons
PARAMS ((int));
691 static void s_float_cons
PARAMS ((int));
692 static void s_mips_globl
PARAMS ((int));
693 static void s_option
PARAMS ((int));
694 static void s_mipsset
PARAMS ((int));
695 static void s_abicalls
PARAMS ((int));
696 static void s_cpload
PARAMS ((int));
697 static void s_cprestore
PARAMS ((int));
698 static void s_gpword
PARAMS ((int));
699 static void s_cpadd
PARAMS ((int));
700 static void s_insn
PARAMS ((int));
701 static void md_obj_begin
PARAMS ((void));
702 static void md_obj_end
PARAMS ((void));
703 static long get_number
PARAMS ((void));
704 static void s_mips_ent
PARAMS ((int));
705 static void s_mips_end
PARAMS ((int));
706 static void s_mips_frame
PARAMS ((int));
707 static void s_mips_mask
PARAMS ((int));
708 static void s_mips_stab
PARAMS ((int));
709 static void s_mips_weakext
PARAMS ((int));
710 static void s_file
PARAMS ((int));
711 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
714 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
718 The following pseudo-ops from the Kane and Heinrich MIPS book
719 should be defined here, but are currently unsupported: .alias,
720 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
722 The following pseudo-ops from the Kane and Heinrich MIPS book are
723 specific to the type of debugging information being generated, and
724 should be defined by the object format: .aent, .begin, .bend,
725 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
728 The following pseudo-ops from the Kane and Heinrich MIPS book are
729 not MIPS CPU specific, but are also not specific to the object file
730 format. This file is probably the best place to define them, but
731 they are not currently supported: .asm0, .endr, .lab, .repeat,
734 static const pseudo_typeS mips_pseudo_table
[] =
736 /* MIPS specific pseudo-ops. */
737 {"option", s_option
, 0},
738 {"set", s_mipsset
, 0},
739 {"rdata", s_change_sec
, 'r'},
740 {"sdata", s_change_sec
, 's'},
741 {"livereg", s_ignore
, 0},
742 {"abicalls", s_abicalls
, 0},
743 {"cpload", s_cpload
, 0},
744 {"cprestore", s_cprestore
, 0},
745 {"gpword", s_gpword
, 0},
746 {"cpadd", s_cpadd
, 0},
749 /* Relatively generic pseudo-ops that happen to be used on MIPS
751 {"asciiz", stringer
, 1},
752 {"bss", s_change_sec
, 'b'},
755 {"dword", s_cons
, 3},
756 {"weakext", s_mips_weakext
, 0},
758 /* These pseudo-ops are defined in read.c, but must be overridden
759 here for one reason or another. */
760 {"align", s_align
, 0},
762 {"data", s_change_sec
, 'd'},
763 {"double", s_float_cons
, 'd'},
764 {"float", s_float_cons
, 'f'},
765 {"globl", s_mips_globl
, 0},
766 {"global", s_mips_globl
, 0},
767 {"hword", s_cons
, 1},
772 {"short", s_cons
, 1},
773 {"single", s_float_cons
, 'f'},
774 {"stabn", s_mips_stab
, 'n'},
775 {"text", s_change_sec
, 't'},
780 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
781 /* These pseudo-ops should be defined by the object file format.
782 However, a.out doesn't support them, so we have versions here. */
783 {"aent", s_mips_ent
, 1},
784 {"bgnb", s_ignore
, 0},
785 {"end", s_mips_end
, 0},
786 {"endb", s_ignore
, 0},
787 {"ent", s_mips_ent
, 0},
789 {"fmask", s_mips_mask
, 'F'},
790 {"frame", s_mips_frame
, 0},
791 {"loc", s_ignore
, 0},
792 {"mask", s_mips_mask
, 'R'},
793 {"verstamp", s_ignore
, 0},
797 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
802 pop_insert (mips_pseudo_table
);
803 if (! ECOFF_DEBUGGING
)
804 pop_insert (mips_nonecoff_pseudo_table
);
807 /* Symbols labelling the current insn. */
809 struct insn_label_list
811 struct insn_label_list
*next
;
815 static struct insn_label_list
*insn_labels
;
816 static struct insn_label_list
*free_insn_labels
;
818 static void mips_clear_insn_labels
PARAMS ((void));
821 mips_clear_insn_labels ()
823 register struct insn_label_list
**pl
;
825 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
831 static char *expr_end
;
833 /* Expressions which appear in instructions. These are set by
836 static expressionS imm_expr
;
837 static expressionS offset_expr
;
839 /* Relocs associated with imm_expr and offset_expr. */
841 static bfd_reloc_code_real_type imm_reloc
;
842 static bfd_reloc_code_real_type offset_reloc
;
844 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
846 static boolean imm_unmatched_hi
;
848 /* These are set by mips16_ip if an explicit extension is used. */
850 static boolean mips16_small
, mips16_ext
;
852 #ifdef MIPS_STABS_ELF
853 /* The pdr segment for per procedure frame/regmask info */
859 * This function is called once, at assembler startup time. It should
860 * set up all the tables, etc. that the MD part of the assembler will need.
866 register const char *retval
= NULL
;
867 register unsigned int i
= 0;
873 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
875 a
= xmalloc (sizeof TARGET_CPU
);
876 strcpy (a
, TARGET_CPU
);
877 a
[(sizeof TARGET_CPU
) - 3] = '\0';
883 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
884 just the generic 'mips', in which case set mips_cpu based
885 on the given ISA, if any. */
887 if (strcmp (cpu
, "mips") == 0)
889 if (mips_opts
.isa
< 0)
892 else if (mips_opts
.isa
== 2)
895 else if (mips_opts
.isa
== 3)
898 else if (mips_opts
.isa
== 4)
905 else if (strcmp (cpu
, "r3900") == 0
906 || strcmp (cpu
, "mipstx39") == 0
907 /* start-sanitize-tx19 */
908 || strcmp (cpu
, "r1900") == 0
909 || strcmp (cpu
, "mipstx19") == 0
910 /* end-sanitize-tx19 */
914 else if (strcmp (cpu
, "r6000") == 0
915 || strcmp (cpu
, "mips2") == 0)
918 else if (strcmp (cpu
, "mips64") == 0
919 || strcmp (cpu
, "r4000") == 0
920 || strcmp (cpu
, "mips3") == 0)
923 else if (strcmp (cpu
, "r4400") == 0)
926 else if (strcmp (cpu
, "mips64orion") == 0
927 || strcmp (cpu
, "r4600") == 0)
930 else if (strcmp (cpu
, "r4650") == 0)
933 else if (strcmp (cpu
, "mips64vr4300") == 0)
936 /* start-sanitize-vr4xxx */
937 else if (strcmp (cpu
, "mips64vr4xxx") == 0)
940 /* end-sanitize-vr4xxx */
941 /* start-sanitize-vr4320 */
942 else if (strcmp (cpu
, "r4320") == 0
943 || strcmp (cpu
, "mips64vr4320") == 0)
946 /* end-sanitize-vr4320 */
947 else if (strcmp (cpu
, "mips64vr4100") == 0)
950 else if (strcmp (cpu
, "r4010") == 0)
953 /* start-sanitize-tx49 */
954 else if (strcmp (cpu
, "mips64tx49") == 0)
956 /* end-sanitize-tx49 */
958 else if (strcmp (cpu
, "r5000") == 0
959 || strcmp (cpu
, "mips64vr5000") == 0)
962 /* start-sanitize-cygnus */
963 else if (strcmp (cpu
, "r5400") == 0
964 || strcmp (cpu
, "mips64vr5400") == 0)
966 /* end-sanitize-cygnus */
968 /* start-sanitize-r5900 */
969 else if (strcmp (cpu
, "r5900") == 0
970 || strcmp (cpu
, "mips64r5900") == 0)
972 /* end-sanitize-r5900 */
974 else if (strcmp (cpu
, "r8000") == 0
975 || strcmp (cpu
, "mips4") == 0)
978 else if (strcmp (cpu
, "r10000") == 0)
981 else if (strcmp (cpu
, "mips16") == 0)
982 mips_cpu
= 0; /* FIXME */
988 if (mips_opts
.isa
== -1)
994 else if (mips_cpu
== 6000
998 else if (mips_cpu
== 4000
1002 /* start-sanitize-vr4320 */
1004 /* end-sanitize-vr4320 */
1006 /* start-sanitize-tx49 */
1008 /* end-sanitize-tx49 */
1009 /* start-sanitize-r5900 */
1011 /* end-sanitize-r5900 */
1012 || mips_cpu
== 4650)
1015 else if (mips_cpu
== 5000
1016 /* start-sanitize-cygnus */
1018 /* end-sanitize-cygnus */
1020 || mips_cpu
== 10000)
1027 if (mips_opts
.mips16
< 0)
1029 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
1030 mips_opts
.mips16
= 1;
1032 mips_opts
.mips16
= 0;
1036 mips_4650
= (mips_cpu
== 4650);
1039 mips_4010
= (mips_cpu
== 4010);
1042 mips_4100
= (mips_cpu
== 4100);
1044 /* start-sanitize-vr4320 */
1046 mips_4320
= (mips_cpu
== 4320);
1048 /* end-sanitize-vr4320 */
1049 /* start-sanitize-cygnus */
1051 mips_5400
= (mips_cpu
== 5400);
1052 /* end-sanitize-cygnus */
1054 /* start-sanitize-r5900 */
1056 mips_5900
= (mips_cpu
== 5900);
1057 /* end-sanitize-r5900 */
1060 mips_3900
= (mips_cpu
== 3900);
1062 /* start-sanitize-tx49 */
1064 mips_4900
= (mips_cpu
== 4900);
1066 /* end-sanitize-tx49 */
1068 /* End of TARGET_CPU processing, get rid of malloced memory
1077 if (mips_opts
.isa
< 2 && mips_trap
)
1078 as_bad (_("trap exception not supported at ISA 1"));
1080 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1082 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1086 switch (mips_opts
.isa
)
1089 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1092 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1095 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1098 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1104 as_warn (_("Could not set architecture and machine"));
1106 file_mips_isa
= mips_opts
.isa
;
1108 op_hash
= hash_new ();
1110 for (i
= 0; i
< NUMOPCODES
;)
1112 const char *name
= mips_opcodes
[i
].name
;
1114 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1117 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1118 mips_opcodes
[i
].name
, retval
);
1119 /* Probably a memory allocation problem? Give up now. */
1120 as_fatal (_("Broken assembler. No assembly attempted."));
1124 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1126 if (!validate_mips_insn (&mips_opcodes
[i
]))
1131 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1134 mips16_op_hash
= hash_new ();
1137 while (i
< bfd_mips16_num_opcodes
)
1139 const char *name
= mips16_opcodes
[i
].name
;
1141 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1143 as_fatal (_("internal: can't hash `%s': %s"),
1144 mips16_opcodes
[i
].name
, retval
);
1147 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1148 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1149 != mips16_opcodes
[i
].match
))
1151 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1152 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1157 while (i
< bfd_mips16_num_opcodes
1158 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1162 as_fatal (_("Broken assembler. No assembly attempted."));
1164 /* We add all the general register names to the symbol table. This
1165 helps us detect invalid uses of them. */
1166 for (i
= 0; i
< 32; i
++)
1170 sprintf (buf
, "$%d", i
);
1171 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1172 &zero_address_frag
));
1174 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1175 &zero_address_frag
));
1176 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1177 &zero_address_frag
));
1178 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1179 &zero_address_frag
));
1180 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1181 &zero_address_frag
));
1182 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1183 &zero_address_frag
));
1184 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1185 &zero_address_frag
));
1186 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1187 &zero_address_frag
));
1189 mips_no_prev_insn (false);
1192 mips_cprmask
[0] = 0;
1193 mips_cprmask
[1] = 0;
1194 mips_cprmask
[2] = 0;
1195 mips_cprmask
[3] = 0;
1197 /* set the default alignment for the text section (2**2) */
1198 record_alignment (text_section
, 2);
1200 if (USE_GLOBAL_POINTER_OPT
)
1201 bfd_set_gp_size (stdoutput
, g_switch_value
);
1203 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1205 /* On a native system, sections must be aligned to 16 byte
1206 boundaries. When configured for an embedded ELF target, we
1208 if (strcmp (TARGET_OS
, "elf") != 0)
1210 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1211 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1212 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1215 /* Create a .reginfo section for register masks and a .mdebug
1216 section for debugging information. */
1224 subseg
= now_subseg
;
1226 /* The ABI says this section should be loaded so that the
1227 running program can access it. However, we don't load it
1228 if we are configured for an embedded target */
1229 flags
= SEC_READONLY
| SEC_DATA
;
1230 if (strcmp (TARGET_OS
, "elf") != 0)
1231 flags
|= SEC_ALLOC
| SEC_LOAD
;
1235 sec
= subseg_new (".reginfo", (subsegT
) 0);
1238 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1239 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1242 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1247 /* The 64-bit ABI uses a .MIPS.options section rather than
1248 .reginfo section. */
1249 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1250 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1251 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1254 /* Set up the option header. */
1256 Elf_Internal_Options opthdr
;
1259 opthdr
.kind
= ODK_REGINFO
;
1260 opthdr
.size
= (sizeof (Elf_External_Options
)
1261 + sizeof (Elf64_External_RegInfo
));
1264 f
= frag_more (sizeof (Elf_External_Options
));
1265 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1266 (Elf_External_Options
*) f
);
1268 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1273 if (ECOFF_DEBUGGING
)
1275 sec
= subseg_new (".mdebug", (subsegT
) 0);
1276 (void) bfd_set_section_flags (stdoutput
, sec
,
1277 SEC_HAS_CONTENTS
| SEC_READONLY
);
1278 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1281 #ifdef MIPS_STABS_ELF
1282 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1283 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1284 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1285 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1288 subseg_set (seg
, subseg
);
1292 if (! ECOFF_DEBUGGING
)
1299 if (! ECOFF_DEBUGGING
)
1307 struct mips_cl_insn insn
;
1309 imm_expr
.X_op
= O_absent
;
1310 imm_reloc
= BFD_RELOC_UNUSED
;
1311 imm_unmatched_hi
= false;
1312 offset_expr
.X_op
= O_absent
;
1313 offset_reloc
= BFD_RELOC_UNUSED
;
1315 if (mips_opts
.mips16
)
1316 mips16_ip (str
, &insn
);
1319 mips_ip (str
, &insn
);
1320 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1321 str
, insn
.insn_opcode
));
1326 as_bad ("%s `%s'", insn_error
, str
);
1330 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1332 if (mips_opts
.mips16
)
1333 mips16_macro (&insn
);
1339 if (imm_expr
.X_op
!= O_absent
)
1340 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1342 else if (offset_expr
.X_op
!= O_absent
)
1343 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1345 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1349 /* See whether instruction IP reads register REG. CLASS is the type
1353 insn_uses_reg (ip
, reg
, class)
1354 struct mips_cl_insn
*ip
;
1356 enum mips_regclass
class;
1358 if (class == MIPS16_REG
)
1360 assert (mips_opts
.mips16
);
1361 reg
= mips16_to_32_reg_map
[reg
];
1362 class = MIPS_GR_REG
;
1365 /* Don't report on general register 0, since it never changes. */
1366 if (class == MIPS_GR_REG
&& reg
== 0)
1369 if (class == MIPS_FP_REG
)
1371 assert (! mips_opts
.mips16
);
1372 /* If we are called with either $f0 or $f1, we must check $f0.
1373 This is not optimal, because it will introduce an unnecessary
1374 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1375 need to distinguish reading both $f0 and $f1 or just one of
1376 them. Note that we don't have to check the other way,
1377 because there is no instruction that sets both $f0 and $f1
1378 and requires a delay. */
1379 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1380 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1381 == (reg
&~ (unsigned) 1)))
1383 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1384 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1385 == (reg
&~ (unsigned) 1)))
1388 else if (! mips_opts
.mips16
)
1390 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1391 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1393 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1394 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1399 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1400 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1401 & MIPS16OP_MASK_RX
)]
1404 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1405 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1406 & MIPS16OP_MASK_RY
)]
1409 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1410 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1411 & MIPS16OP_MASK_MOVE32Z
)]
1414 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1416 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1418 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1420 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1421 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1422 & MIPS16OP_MASK_REGR32
) == reg
)
1429 /* This function returns true if modifying a register requires a
1433 reg_needs_delay (reg
)
1436 unsigned long prev_pinfo
;
1438 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1439 if (! mips_opts
.noreorder
1440 && mips_opts
.isa
< 4
1441 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1442 || (! gpr_interlocks
1443 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1445 /* A load from a coprocessor or from memory. All load
1446 delays delay the use of general register rt for one
1447 instruction on the r3000. The r6000 and r4000 use
1449 /* Itbl support may require additional care here. */
1450 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1451 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1458 /* Mark instruction labels in mips16 mode. This permits the linker to
1459 handle them specially, such as generating jalx instructions when
1460 needed. We also make them odd for the duration of the assembly, in
1461 order to generate the right sort of code. We will make them even
1462 in the adjust_symtab routine, while leaving them marked. This is
1463 convenient for the debugger and the disassembler. The linker knows
1464 to make them odd again. */
1467 mips16_mark_labels ()
1469 if (mips_opts
.mips16
)
1471 struct insn_label_list
*l
;
1473 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1476 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1477 S_SET_OTHER (l
->label
, STO_MIPS16
);
1479 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1480 ++l
->label
->sy_value
.X_add_number
;
1485 /* Output an instruction. PLACE is where to put the instruction; if
1486 it is NULL, this uses frag_more to get room. IP is the instruction
1487 information. ADDRESS_EXPR is an operand of the instruction to be
1488 used with RELOC_TYPE. */
1491 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1493 struct mips_cl_insn
*ip
;
1494 expressionS
*address_expr
;
1495 bfd_reloc_code_real_type reloc_type
;
1496 boolean unmatched_hi
;
1498 register unsigned long prev_pinfo
, pinfo
;
1502 /* start-sanitize-branchbug4011 */
1503 int label_nop
= 0; /* True if a no-op needs to appear between
1504 the current insn and the current labels */
1505 /* end-sanitize-branchbug4011 */
1507 /* Mark instruction labels in mips16 mode. */
1508 if (mips_opts
.mips16
)
1509 mips16_mark_labels ();
1511 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1512 pinfo
= ip
->insn_mo
->pinfo
;
1514 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1518 /* If the previous insn required any delay slots, see if we need
1519 to insert a NOP or two. There are eight kinds of possible
1520 hazards, of which an instruction can have at most one type.
1521 (1) a load from memory delay
1522 (2) a load from a coprocessor delay
1523 (3) an unconditional branch delay
1524 (4) a conditional branch delay
1525 (5) a move to coprocessor register delay
1526 (6) a load coprocessor register from memory delay
1527 (7) a coprocessor condition code delay
1528 (8) a HI/LO special register delay
1530 There are a lot of optimizations we could do that we don't.
1531 In particular, we do not, in general, reorder instructions.
1532 If you use gcc with optimization, it will reorder
1533 instructions and generally do much more optimization then we
1534 do here; repeating all that work in the assembler would only
1535 benefit hand written assembly code, and does not seem worth
1538 /* This is how a NOP is emitted. */
1539 #define emit_nop() \
1541 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1542 : md_number_to_chars (frag_more (4), 0, 4))
1544 /* The previous insn might require a delay slot, depending upon
1545 the contents of the current insn. */
1546 if (! mips_opts
.mips16
1547 && mips_opts
.isa
< 4
1548 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1549 && ! cop_interlocks
)
1550 || (! gpr_interlocks
1551 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1553 /* A load from a coprocessor or from memory. All load
1554 delays delay the use of general register rt for one
1555 instruction on the r3000. The r6000 and r4000 use
1557 /* Itbl support may require additional care here. */
1558 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1559 if (mips_optimize
== 0
1560 || insn_uses_reg (ip
,
1561 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1566 else if (! mips_opts
.mips16
1567 && mips_opts
.isa
< 4
1568 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1569 && ! cop_interlocks
)
1570 || (mips_opts
.isa
< 2
1571 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1573 /* A generic coprocessor delay. The previous instruction
1574 modified a coprocessor general or control register. If
1575 it modified a control register, we need to avoid any
1576 coprocessor instruction (this is probably not always
1577 required, but it sometimes is). If it modified a general
1578 register, we avoid using that register.
1580 On the r6000 and r4000 loading a coprocessor register
1581 from memory is interlocked, and does not require a delay.
1583 This case is not handled very well. There is no special
1584 knowledge of CP0 handling, and the coprocessors other
1585 than the floating point unit are not distinguished at
1587 /* Itbl support may require additional care here. FIXME!
1588 Need to modify this to include knowledge about
1589 user specified delays! */
1590 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1592 if (mips_optimize
== 0
1593 || insn_uses_reg (ip
,
1594 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1599 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1601 if (mips_optimize
== 0
1602 || insn_uses_reg (ip
,
1603 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1610 /* We don't know exactly what the previous instruction
1611 does. If the current instruction uses a coprocessor
1612 register, we must insert a NOP. If previous
1613 instruction may set the condition codes, and the
1614 current instruction uses them, we must insert two
1616 /* Itbl support may require additional care here. */
1617 if (mips_optimize
== 0
1618 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1619 && (pinfo
& INSN_READ_COND_CODE
)))
1621 else if (pinfo
& INSN_COP
)
1625 else if (! mips_opts
.mips16
1626 && mips_opts
.isa
< 4
1627 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1628 && ! cop_interlocks
)
1630 /* The previous instruction sets the coprocessor condition
1631 codes, but does not require a general coprocessor delay
1632 (this means it is a floating point comparison
1633 instruction). If this instruction uses the condition
1634 codes, we need to insert a single NOP. */
1635 /* Itbl support may require additional care here. */
1636 if (mips_optimize
== 0
1637 || (pinfo
& INSN_READ_COND_CODE
))
1640 else if (prev_pinfo
& INSN_READ_LO
)
1642 /* The previous instruction reads the LO register; if the
1643 current instruction writes to the LO register, we must
1644 insert two NOPS. Some newer processors have interlocks.
1645 Also the tx39's multiply instructions can be exectuted
1646 immediatly after a read from HI/LO (without the delay),
1647 though the tx39's divide insns still do require the
1649 if (! (hilo_interlocks
1650 || (mips_3900
&& (pinfo
& INSN_MULT
)))
1651 && (mips_optimize
== 0
1652 || (pinfo
& INSN_WRITE_LO
)))
1655 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1657 /* The previous instruction reads the HI register; if the
1658 current instruction writes to the HI register, we must
1659 insert a NOP. Some newer processors have interlocks.
1660 Also the note tx39's multiply above. */
1661 if (! (hilo_interlocks
1662 || (mips_3900
&& (pinfo
& INSN_MULT
)))
1663 && (mips_optimize
== 0
1664 || (pinfo
& INSN_WRITE_HI
)))
1668 /* If the previous instruction was in a noreorder section, then
1669 we don't want to insert the nop after all. */
1670 /* Itbl support may require additional care here. */
1671 if (prev_insn_unreordered
)
1674 /* There are two cases which require two intervening
1675 instructions: 1) setting the condition codes using a move to
1676 coprocessor instruction which requires a general coprocessor
1677 delay and then reading the condition codes 2) reading the HI
1678 or LO register and then writing to it (except on processors
1679 which have interlocks). If we are not already emitting a NOP
1680 instruction, we must check for these cases compared to the
1681 instruction previous to the previous instruction. */
1682 if ((! mips_opts
.mips16
1683 && mips_opts
.isa
< 4
1684 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1685 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1686 && (pinfo
& INSN_READ_COND_CODE
)
1687 && ! cop_interlocks
)
1688 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1689 && (pinfo
& INSN_WRITE_LO
)
1690 && ! (hilo_interlocks
1691 || (mips_3900
&& (pinfo
& INSN_MULT
))))
1692 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1693 && (pinfo
& INSN_WRITE_HI
)
1694 && ! (hilo_interlocks
1695 || (mips_3900
&& (pinfo
& INSN_MULT
)))))
1700 if (prev_prev_insn_unreordered
)
1703 if (prev_prev_nop
&& nops
== 0)
1706 /* If we are being given a nop instruction, don't bother with
1707 one of the nops we would otherwise output. This will only
1708 happen when a nop instruction is used with mips_optimize set
1711 && ! mips_opts
.noreorder
1712 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1715 /* start-sanitize-branchbug4011 */
1716 /* If we have a label on a branch insn, we need at least one no-op
1717 between the label and the branch. The pinfo flags in this test
1718 must cover all the kinds of branches. */
1719 if (mips_fix_4011_branch_bug
1720 && insn_labels
!= NULL
1721 && (ip
->insn_mo
->pinfo
1722 & (INSN_UNCOND_BRANCH_DELAY
1723 |INSN_COND_BRANCH_DELAY
1724 |INSN_COND_BRANCH_LIKELY
)))
1728 /* Make sure we've got at least one nop. */
1733 /* end-sanitize-branchbug4011 */
1734 /* Now emit the right number of NOP instructions. */
1735 if (nops
> 0 && ! mips_opts
.noreorder
)
1738 unsigned long old_frag_offset
;
1740 struct insn_label_list
*l
;
1742 old_frag
= frag_now
;
1743 old_frag_offset
= frag_now_fix ();
1745 /* start-sanitize-branchbug4011 */
1746 /* Emit the nops that should be before the label. */
1750 /* end-sanitize-branchbug4011 */
1751 for (i
= 0; i
< nops
; i
++)
1756 listing_prev_line ();
1757 /* We may be at the start of a variant frag. In case we
1758 are, make sure there is enough space for the frag
1759 after the frags created by listing_prev_line. The
1760 argument to frag_grow here must be at least as large
1761 as the argument to all other calls to frag_grow in
1762 this file. We don't have to worry about being in the
1763 middle of a variant frag, because the variants insert
1764 all needed nop instructions themselves. */
1768 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1770 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1771 l
->label
->sy_frag
= frag_now
;
1772 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1773 /* mips16 text labels are stored as odd. */
1774 if (mips_opts
.mips16
)
1775 ++l
->label
->sy_value
.X_add_number
;
1778 #ifndef NO_ECOFF_DEBUGGING
1779 if (ECOFF_DEBUGGING
)
1780 ecoff_fix_loc (old_frag
, old_frag_offset
);
1782 /* start-sanitize-branchbug4011 */
1785 /* Emit the nop after the label, and return the
1786 nop count to it's proper value. */
1790 /* end-sanitize-branchbug4011 */
1792 else if (prev_nop_frag
!= NULL
)
1794 /* We have a frag holding nops we may be able to remove. If
1795 we don't need any nops, we can decrease the size of
1796 prev_nop_frag by the size of one instruction. If we do
1797 need some nops, we count them in prev_nops_required. */
1798 if (prev_nop_frag_since
== 0)
1802 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1803 --prev_nop_frag_holds
;
1806 prev_nop_frag_required
+= nops
;
1810 if (prev_prev_nop
== 0)
1812 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1813 --prev_nop_frag_holds
;
1816 ++prev_nop_frag_required
;
1819 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1820 prev_nop_frag
= NULL
;
1822 ++prev_nop_frag_since
;
1824 /* Sanity check: by the time we reach the second instruction
1825 after prev_nop_frag, we should have used up all the nops
1826 one way or another. */
1827 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1831 if (reloc_type
> BFD_RELOC_UNUSED
)
1833 /* We need to set up a variant frag. */
1834 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1835 f
= frag_var (rs_machine_dependent
, 4, 0,
1836 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1837 mips16_small
, mips16_ext
,
1839 & INSN_UNCOND_BRANCH_DELAY
),
1840 (prev_insn_reloc_type
1841 == BFD_RELOC_MIPS16_JMP
)),
1842 make_expr_symbol (address_expr
), (offsetT
) 0,
1845 else if (place
!= NULL
)
1847 else if (mips_opts
.mips16
1849 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1851 /* Make sure there is enough room to swap this instruction with
1852 a following jump instruction. */
1858 if (mips_opts
.mips16
1859 && mips_opts
.noreorder
1860 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1861 as_warn (_("extended instruction in delay slot"));
1867 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1869 if (address_expr
->X_op
== O_constant
)
1874 ip
->insn_opcode
|= address_expr
->X_add_number
;
1877 case BFD_RELOC_LO16
:
1878 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1881 case BFD_RELOC_MIPS_JMP
:
1882 if ((address_expr
->X_add_number
& 3) != 0)
1883 as_bad (_("jump to misaligned address (0x%lx)"),
1884 (unsigned long) address_expr
->X_add_number
);
1885 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1888 case BFD_RELOC_MIPS16_JMP
:
1889 if ((address_expr
->X_add_number
& 3) != 0)
1890 as_bad (_("jump to misaligned address (0x%lx)"),
1891 (unsigned long) address_expr
->X_add_number
);
1893 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1894 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1895 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1898 /* start-sanitize-r5900 */
1899 case BFD_RELOC_MIPS15_S3
:
1900 ip
->insn_opcode
|= ((imm_expr
.X_add_number
& 0x7fff) >> 3) << 6;
1902 /* end-sanitize-r5900 */
1904 case BFD_RELOC_16_PCREL_S2
:
1914 /* Don't generate a reloc if we are writing into a variant
1918 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1920 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1924 struct mips_hi_fixup
*hi_fixup
;
1926 assert (reloc_type
== BFD_RELOC_HI16_S
);
1927 hi_fixup
= ((struct mips_hi_fixup
*)
1928 xmalloc (sizeof (struct mips_hi_fixup
)));
1929 hi_fixup
->fixp
= fixp
;
1930 hi_fixup
->seg
= now_seg
;
1931 hi_fixup
->next
= mips_hi_fixup_list
;
1932 mips_hi_fixup_list
= hi_fixup
;
1938 if (! mips_opts
.mips16
)
1939 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1940 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1942 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1943 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1949 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1952 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1955 /* Update the register mask information. */
1956 if (! mips_opts
.mips16
)
1958 if (pinfo
& INSN_WRITE_GPR_D
)
1959 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1960 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1961 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1962 if (pinfo
& INSN_READ_GPR_S
)
1963 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1964 if (pinfo
& INSN_WRITE_GPR_31
)
1965 mips_gprmask
|= 1 << 31;
1966 if (pinfo
& INSN_WRITE_FPR_D
)
1967 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1968 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1969 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1970 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1971 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1972 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1973 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1974 if (pinfo
& INSN_COP
)
1976 /* We don't keep enough information to sort these cases out.
1977 The itbl support does keep this information however, although
1978 we currently don't support itbl fprmats as part of the cop
1979 instruction. May want to add this support in the future. */
1981 /* Never set the bit for $0, which is always zero. */
1982 mips_gprmask
&=~ 1 << 0;
1986 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1987 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1988 & MIPS16OP_MASK_RX
);
1989 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1990 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1991 & MIPS16OP_MASK_RY
);
1992 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1993 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1994 & MIPS16OP_MASK_RZ
);
1995 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1996 mips_gprmask
|= 1 << TREG
;
1997 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1998 mips_gprmask
|= 1 << SP
;
1999 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2000 mips_gprmask
|= 1 << RA
;
2001 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2002 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2003 if (pinfo
& MIPS16_INSN_READ_Z
)
2004 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2005 & MIPS16OP_MASK_MOVE32Z
);
2006 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2007 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2008 & MIPS16OP_MASK_REGR32
);
2011 if (place
== NULL
&& ! mips_opts
.noreorder
)
2013 /* Filling the branch delay slot is more complex. We try to
2014 switch the branch with the previous instruction, which we can
2015 do if the previous instruction does not set up a condition
2016 that the branch tests and if the branch is not itself the
2017 target of any branch. */
2018 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2019 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2021 if (mips_optimize
< 2
2022 /* If we have seen .set volatile or .set nomove, don't
2024 || mips_opts
.nomove
!= 0
2025 /* If we had to emit any NOP instructions, then we
2026 already know we can not swap. */
2028 /* If we don't even know the previous insn, we can not
2030 || ! prev_insn_valid
2031 /* If the previous insn is already in a branch delay
2032 slot, then we can not swap. */
2033 || prev_insn_is_delay_slot
2034 /* start-sanitize-branchbug4011 */
2035 /* We can't swap the branch back to a previous label */
2036 || (mips_fix_4011_branch_bug
&& prev_insn_labels
)
2037 /* end-sanitize-branchbug4011 */
2038 /* If the previous previous insn was in a .set
2039 noreorder, we can't swap. Actually, the MIPS
2040 assembler will swap in this situation. However, gcc
2041 configured -with-gnu-as will generate code like
2047 in which we can not swap the bne and INSN. If gcc is
2048 not configured -with-gnu-as, it does not output the
2049 .set pseudo-ops. We don't have to check
2050 prev_insn_unreordered, because prev_insn_valid will
2051 be 0 in that case. We don't want to use
2052 prev_prev_insn_valid, because we do want to be able
2053 to swap at the start of a function. */
2054 || prev_prev_insn_unreordered
2055 /* If the branch is itself the target of a branch, we
2056 can not swap. We cheat on this; all we check for is
2057 whether there is a label on this instruction. If
2058 there are any branches to anything other than a
2059 label, users must use .set noreorder. */
2060 || insn_labels
!= NULL
2061 /* If the previous instruction is in a variant frag, we
2062 can not do the swap. This does not apply to the
2063 mips16, which uses variant frags for different
2065 || (! mips_opts
.mips16
2066 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2067 /* If the branch reads the condition codes, we don't
2068 even try to swap, because in the sequence
2073 we can not swap, and I don't feel like handling that
2075 || (! mips_opts
.mips16
2076 && mips_opts
.isa
< 4
2077 && (pinfo
& INSN_READ_COND_CODE
))
2078 /* We can not swap with an instruction that requires a
2079 delay slot, becase the target of the branch might
2080 interfere with that instruction. */
2081 || (! mips_opts
.mips16
2082 && mips_opts
.isa
< 4
2084 /* Itbl support may require additional care here. */
2085 & (INSN_LOAD_COPROC_DELAY
2086 | INSN_COPROC_MOVE_DELAY
2087 | INSN_WRITE_COND_CODE
)))
2088 || (! (hilo_interlocks
|| (mips_3900
&& (pinfo
& INSN_MULT
)))
2092 || (! mips_opts
.mips16
2094 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2095 || (! mips_opts
.mips16
2096 && mips_opts
.isa
< 2
2097 /* Itbl support may require additional care here. */
2098 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2099 /* We can not swap with a branch instruction. */
2101 & (INSN_UNCOND_BRANCH_DELAY
2102 | INSN_COND_BRANCH_DELAY
2103 | INSN_COND_BRANCH_LIKELY
))
2104 /* We do not swap with a trap instruction, since it
2105 complicates trap handlers to have the trap
2106 instruction be in a delay slot. */
2107 || (prev_pinfo
& INSN_TRAP
)
2108 /* If the branch reads a register that the previous
2109 instruction sets, we can not swap. */
2110 || (! mips_opts
.mips16
2111 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2112 && insn_uses_reg (ip
,
2113 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2116 || (! mips_opts
.mips16
2117 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2118 && insn_uses_reg (ip
,
2119 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2122 || (mips_opts
.mips16
2123 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2124 && insn_uses_reg (ip
,
2125 ((prev_insn
.insn_opcode
2127 & MIPS16OP_MASK_RX
),
2129 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2130 && insn_uses_reg (ip
,
2131 ((prev_insn
.insn_opcode
2133 & MIPS16OP_MASK_RY
),
2135 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2136 && insn_uses_reg (ip
,
2137 ((prev_insn
.insn_opcode
2139 & MIPS16OP_MASK_RZ
),
2141 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2142 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2143 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2144 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2145 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2146 && insn_uses_reg (ip
,
2147 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2150 /* If the branch writes a register that the previous
2151 instruction sets, we can not swap (we know that
2152 branches write only to RD or to $31). */
2153 || (! mips_opts
.mips16
2154 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2155 && (((pinfo
& INSN_WRITE_GPR_D
)
2156 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2157 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2158 || ((pinfo
& INSN_WRITE_GPR_31
)
2159 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2162 || (! mips_opts
.mips16
2163 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2164 && (((pinfo
& INSN_WRITE_GPR_D
)
2165 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2166 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2167 || ((pinfo
& INSN_WRITE_GPR_31
)
2168 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2171 || (mips_opts
.mips16
2172 && (pinfo
& MIPS16_INSN_WRITE_31
)
2173 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2174 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2175 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2177 /* If the branch writes a register that the previous
2178 instruction reads, we can not swap (we know that
2179 branches only write to RD or to $31). */
2180 || (! mips_opts
.mips16
2181 && (pinfo
& INSN_WRITE_GPR_D
)
2182 && insn_uses_reg (&prev_insn
,
2183 ((ip
->insn_opcode
>> OP_SH_RD
)
2186 || (! mips_opts
.mips16
2187 && (pinfo
& INSN_WRITE_GPR_31
)
2188 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2189 || (mips_opts
.mips16
2190 && (pinfo
& MIPS16_INSN_WRITE_31
)
2191 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2192 /* If we are generating embedded PIC code, the branch
2193 might be expanded into a sequence which uses $at, so
2194 we can't swap with an instruction which reads it. */
2195 || (mips_pic
== EMBEDDED_PIC
2196 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2197 /* If the previous previous instruction has a load
2198 delay, and sets a register that the branch reads, we
2200 || (! mips_opts
.mips16
2201 && mips_opts
.isa
< 4
2202 /* Itbl support may require additional care here. */
2203 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2204 || (! gpr_interlocks
2205 && (prev_prev_insn
.insn_mo
->pinfo
2206 & INSN_LOAD_MEMORY_DELAY
)))
2207 && insn_uses_reg (ip
,
2208 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2211 /* If one instruction sets a condition code and the
2212 other one uses a condition code, we can not swap. */
2213 || ((pinfo
& INSN_READ_COND_CODE
)
2214 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2215 || ((pinfo
& INSN_WRITE_COND_CODE
)
2216 && (prev_pinfo
& INSN_READ_COND_CODE
))
2217 /* If the previous instruction uses the PC, we can not
2219 || (mips_opts
.mips16
2220 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2221 /* If the previous instruction was extended, we can not
2223 || (mips_opts
.mips16
&& prev_insn_extended
)
2224 /* If the previous instruction had a fixup in mips16
2225 mode, we can not swap. This normally means that the
2226 previous instruction was a 4 byte branch anyhow. */
2227 || (mips_opts
.mips16
&& prev_insn_fixp
))
2229 /* We could do even better for unconditional branches to
2230 portions of this object file; we could pick up the
2231 instruction at the destination, put it in the delay
2232 slot, and bump the destination address. */
2234 /* Update the previous insn information. */
2235 prev_prev_insn
= *ip
;
2236 prev_insn
.insn_mo
= &dummy_opcode
;
2240 /* It looks like we can actually do the swap. */
2241 if (! mips_opts
.mips16
)
2246 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2247 memcpy (temp
, prev_f
, 4);
2248 memcpy (prev_f
, f
, 4);
2249 memcpy (f
, temp
, 4);
2252 prev_insn_fixp
->fx_frag
= frag_now
;
2253 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2257 fixp
->fx_frag
= prev_insn_frag
;
2258 fixp
->fx_where
= prev_insn_where
;
2266 assert (prev_insn_fixp
== NULL
);
2267 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2268 memcpy (temp
, prev_f
, 2);
2269 memcpy (prev_f
, f
, 2);
2270 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2272 assert (reloc_type
== BFD_RELOC_UNUSED
);
2273 memcpy (f
, temp
, 2);
2277 memcpy (f
, f
+ 2, 2);
2278 memcpy (f
+ 2, temp
, 2);
2282 fixp
->fx_frag
= prev_insn_frag
;
2283 fixp
->fx_where
= prev_insn_where
;
2287 /* Update the previous insn information; leave prev_insn
2289 prev_prev_insn
= *ip
;
2291 prev_insn_is_delay_slot
= 1;
2293 /* If that was an unconditional branch, forget the previous
2294 insn information. */
2295 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2297 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2298 prev_insn
.insn_mo
= &dummy_opcode
;
2301 prev_insn_fixp
= NULL
;
2302 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2303 prev_insn_extended
= 0;
2305 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2307 /* We don't yet optimize a branch likely. What we should do
2308 is look at the target, copy the instruction found there
2309 into the delay slot, and increment the branch to jump to
2310 the next instruction. */
2312 /* Update the previous insn information. */
2313 prev_prev_insn
= *ip
;
2314 prev_insn
.insn_mo
= &dummy_opcode
;
2315 prev_insn_fixp
= NULL
;
2316 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2317 prev_insn_extended
= 0;
2321 /* Update the previous insn information. */
2323 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2325 prev_prev_insn
= prev_insn
;
2328 /* Any time we see a branch, we always fill the delay slot
2329 immediately; since this insn is not a branch, we know it
2330 is not in a delay slot. */
2331 prev_insn_is_delay_slot
= 0;
2333 prev_insn_fixp
= fixp
;
2334 prev_insn_reloc_type
= reloc_type
;
2335 if (mips_opts
.mips16
)
2336 prev_insn_extended
= (ip
->use_extend
2337 || reloc_type
> BFD_RELOC_UNUSED
);
2340 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2341 prev_insn_unreordered
= 0;
2342 prev_insn_frag
= frag_now
;
2343 prev_insn_where
= f
- frag_now
->fr_literal
;
2344 prev_insn_valid
= 1;
2345 /* start-sanitize-branchbug4011 */
2346 prev_insn_labels
= !! insn_labels
;
2347 /* end-sanitize-branchbug4011 */
2349 else if (place
== NULL
)
2351 /* We need to record a bit of information even when we are not
2352 reordering, in order to determine the base address for mips16
2353 PC relative relocs. */
2354 prev_prev_insn
= prev_insn
;
2356 prev_insn_reloc_type
= reloc_type
;
2357 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2358 prev_insn_unreordered
= 1;
2359 /* start-sanitize-branchbug4011 */
2360 prev_insn_labels
= !! insn_labels
;
2361 /* end-sanitize-branchbug4011 */
2364 /* We just output an insn, so the next one doesn't have a label. */
2365 mips_clear_insn_labels ();
2367 /* We must ensure that a fixup associated with an unmatched %hi
2368 reloc does not become a variant frag. Otherwise, the
2369 rearrangement of %hi relocs in frob_file may confuse
2373 frag_wane (frag_now
);
2378 /* This function forgets that there was any previous instruction or
2379 label. If PRESERVE is non-zero, it remembers enough information to
2380 know whether nops are needed before a noreorder section. */
2383 mips_no_prev_insn (preserve
)
2388 prev_insn
.insn_mo
= &dummy_opcode
;
2389 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2390 prev_nop_frag
= NULL
;
2391 prev_nop_frag_holds
= 0;
2392 prev_nop_frag_required
= 0;
2393 prev_nop_frag_since
= 0;
2395 prev_insn_valid
= 0;
2396 prev_insn_is_delay_slot
= 0;
2397 prev_insn_unreordered
= 0;
2398 prev_insn_extended
= 0;
2399 /* start-sanitize-branchbug4011 */
2400 prev_insn_labels
= 0;
2401 /* end-sanitize-branchbug4011 */
2402 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2403 prev_prev_insn_unreordered
= 0;
2404 mips_clear_insn_labels ();
2407 /* This function must be called whenever we turn on noreorder or emit
2408 something other than instructions. It inserts any NOPS which might
2409 be needed by the previous instruction, and clears the information
2410 kept for the previous instructions. The INSNS parameter is true if
2411 instructions are to follow. */
2414 mips_emit_delays (insns
)
2417 if (! mips_opts
.noreorder
)
2422 if ((! mips_opts
.mips16
2423 && mips_opts
.isa
< 4
2424 && (! cop_interlocks
2425 && (prev_insn
.insn_mo
->pinfo
2426 & (INSN_LOAD_COPROC_DELAY
2427 | INSN_COPROC_MOVE_DELAY
2428 | INSN_WRITE_COND_CODE
))))
2429 || (! hilo_interlocks
2430 && (prev_insn
.insn_mo
->pinfo
2433 || (! mips_opts
.mips16
2435 && (prev_insn
.insn_mo
->pinfo
2436 & INSN_LOAD_MEMORY_DELAY
))
2437 || (! mips_opts
.mips16
2438 && mips_opts
.isa
< 2
2439 && (prev_insn
.insn_mo
->pinfo
2440 & INSN_COPROC_MEMORY_DELAY
)))
2442 /* Itbl support may require additional care here. */
2444 if ((! mips_opts
.mips16
2445 && mips_opts
.isa
< 4
2446 && (! cop_interlocks
2447 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2448 || (! hilo_interlocks
2449 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2450 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2453 if (prev_insn_unreordered
)
2456 else if ((! mips_opts
.mips16
2457 && mips_opts
.isa
< 4
2458 && (! cop_interlocks
2459 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2460 || (! hilo_interlocks
2461 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2462 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2464 /* Itbl support may require additional care here. */
2465 if (! prev_prev_insn_unreordered
)
2471 struct insn_label_list
*l
;
2475 /* Record the frag which holds the nop instructions, so
2476 that we can remove them if we don't need them. */
2477 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2478 prev_nop_frag
= frag_now
;
2479 prev_nop_frag_holds
= nops
;
2480 prev_nop_frag_required
= 0;
2481 prev_nop_frag_since
= 0;
2484 for (; nops
> 0; --nops
)
2489 /* Move on to a new frag, so that it is safe to simply
2490 decrease the size of prev_nop_frag. */
2491 frag_wane (frag_now
);
2495 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2497 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2498 l
->label
->sy_frag
= frag_now
;
2499 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2500 /* mips16 text labels are stored as odd. */
2501 if (mips_opts
.mips16
)
2502 ++l
->label
->sy_value
.X_add_number
;
2507 /* Mark instruction labels in mips16 mode. */
2508 if (mips_opts
.mips16
&& insns
)
2509 mips16_mark_labels ();
2511 mips_no_prev_insn (insns
);
2514 /* Build an instruction created by a macro expansion. This is passed
2515 a pointer to the count of instructions created so far, an
2516 expression, the name of the instruction to build, an operand format
2517 string, and corresponding arguments. */
2521 macro_build (char *place
,
2529 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2538 struct mips_cl_insn insn
;
2539 bfd_reloc_code_real_type r
;
2544 va_start (args
, fmt
);
2550 * If the macro is about to expand into a second instruction,
2551 * print a warning if needed. We need to pass ip as a parameter
2552 * to generate a better warning message here...
2554 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2555 as_warn (_("Macro instruction expanded into multiple instructions"));
2558 *counter
+= 1; /* bump instruction counter */
2560 if (mips_opts
.mips16
)
2562 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2567 r
= BFD_RELOC_UNUSED
;
2568 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2569 assert (insn
.insn_mo
);
2570 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2572 /* Search until we get a match for NAME. */
2575 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2577 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2579 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2581 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2586 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2587 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2588 && (insn_isa
<= mips_opts
.isa
2590 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2592 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2594 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2595 /* start-sanitize-vr4320 */
2597 && (insn
.insn_mo
->membership
& INSN_4320
) != 0)
2598 /* end-sanitize-vr4320 */
2599 /* start-sanitize-tx49 */
2601 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2602 /* end-sanitize-tx49 */
2603 /* start-sanitize-r5900 */
2605 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2606 /* end-sanitize-r5900 */
2607 /* start-sanitize-cygnus */
2609 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2610 /* end-sanitize-cygnus */
2612 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2613 /* start-sanitize-r5900 */
2614 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2615 /* end-sanitize-r5900 */
2616 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2620 assert (insn
.insn_mo
->name
);
2621 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2624 insn
.insn_opcode
= insn
.insn_mo
->match
;
2640 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2646 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2651 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2656 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2663 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2667 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2671 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2675 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2682 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2688 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2689 assert (r
== BFD_RELOC_MIPS_GPREL
2690 || r
== BFD_RELOC_MIPS_LITERAL
2691 || r
== BFD_RELOC_LO16
2692 || r
== BFD_RELOC_MIPS_GOT16
2693 || r
== BFD_RELOC_MIPS_CALL16
2694 || r
== BFD_RELOC_MIPS_GOT_LO16
2695 || r
== BFD_RELOC_MIPS_CALL_LO16
2696 || (ep
->X_op
== O_subtract
2697 && now_seg
== text_section
2698 && r
== BFD_RELOC_PCREL_LO16
));
2702 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2704 && (ep
->X_op
== O_constant
2705 || (ep
->X_op
== O_symbol
2706 && (r
== BFD_RELOC_HI16_S
2707 || r
== BFD_RELOC_HI16
2708 || r
== BFD_RELOC_MIPS_GOT_HI16
2709 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2710 || (ep
->X_op
== O_subtract
2711 && now_seg
== text_section
2712 && r
== BFD_RELOC_PCREL_HI16_S
)));
2713 if (ep
->X_op
== O_constant
)
2715 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2717 r
= BFD_RELOC_UNUSED
;
2722 assert (ep
!= NULL
);
2724 * This allows macro() to pass an immediate expression for
2725 * creating short branches without creating a symbol.
2726 * Note that the expression still might come from the assembly
2727 * input, in which case the value is not checked for range nor
2728 * is a relocation entry generated (yuck).
2730 if (ep
->X_op
== O_constant
)
2732 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2736 r
= BFD_RELOC_16_PCREL_S2
;
2740 assert (ep
!= NULL
);
2741 r
= BFD_RELOC_MIPS_JMP
;
2745 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2754 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2756 append_insn (place
, &insn
, ep
, r
, false);
2760 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2768 struct mips_cl_insn insn
;
2769 bfd_reloc_code_real_type r
;
2771 r
= BFD_RELOC_UNUSED
;
2772 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2773 assert (insn
.insn_mo
);
2774 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2776 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2777 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2780 assert (insn
.insn_mo
->name
);
2781 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2784 insn
.insn_opcode
= insn
.insn_mo
->match
;
2785 insn
.use_extend
= false;
2804 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2809 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2813 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2817 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2827 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2834 regno
= va_arg (args
, int);
2835 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2836 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2857 assert (ep
!= NULL
);
2859 if (ep
->X_op
!= O_constant
)
2860 r
= BFD_RELOC_UNUSED
+ c
;
2863 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2864 false, false, &insn
.insn_opcode
,
2865 &insn
.use_extend
, &insn
.extend
);
2867 r
= BFD_RELOC_UNUSED
;
2873 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2880 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2882 append_insn (place
, &insn
, ep
, r
, false);
2886 * Generate a "lui" instruction.
2889 macro_build_lui (place
, counter
, ep
, regnum
)
2895 expressionS high_expr
;
2896 struct mips_cl_insn insn
;
2897 bfd_reloc_code_real_type r
;
2898 CONST
char *name
= "lui";
2899 CONST
char *fmt
= "t,u";
2901 assert (! mips_opts
.mips16
);
2907 high_expr
.X_op
= O_constant
;
2908 high_expr
.X_add_number
= ep
->X_add_number
;
2911 if (high_expr
.X_op
== O_constant
)
2913 /* we can compute the instruction now without a relocation entry */
2914 if (high_expr
.X_add_number
& 0x8000)
2915 high_expr
.X_add_number
+= 0x10000;
2916 high_expr
.X_add_number
=
2917 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2918 r
= BFD_RELOC_UNUSED
;
2922 assert (ep
->X_op
== O_symbol
);
2923 /* _gp_disp is a special case, used from s_cpload. */
2924 assert (mips_pic
== NO_PIC
2925 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2926 r
= BFD_RELOC_HI16_S
;
2930 * If the macro is about to expand into a second instruction,
2931 * print a warning if needed. We need to pass ip as a parameter
2932 * to generate a better warning message here...
2934 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2935 as_warn (_("Macro instruction expanded into multiple instructions"));
2938 *counter
+= 1; /* bump instruction counter */
2940 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2941 assert (insn
.insn_mo
);
2942 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2943 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2945 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2946 if (r
== BFD_RELOC_UNUSED
)
2948 insn
.insn_opcode
|= high_expr
.X_add_number
;
2949 append_insn (place
, &insn
, NULL
, r
, false);
2952 append_insn (place
, &insn
, &high_expr
, r
, false);
2956 * Generates code to set the $at register to true (one)
2957 * if reg is less than the immediate expression.
2960 set_at (counter
, reg
, unsignedp
)
2965 if (imm_expr
.X_op
== O_constant
2966 && imm_expr
.X_add_number
>= -0x8000
2967 && imm_expr
.X_add_number
< 0x8000)
2968 macro_build ((char *) NULL
, counter
, &imm_expr
,
2969 unsignedp
? "sltiu" : "slti",
2970 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2973 load_register (counter
, AT
, &imm_expr
, 0);
2974 macro_build ((char *) NULL
, counter
, NULL
,
2975 unsignedp
? "sltu" : "slt",
2976 "d,v,t", AT
, reg
, AT
);
2980 /* Warn if an expression is not a constant. */
2983 check_absolute_expr (ip
, ex
)
2984 struct mips_cl_insn
*ip
;
2987 if (ex
->X_op
== O_big
)
2988 as_bad (_("unsupported large constant"));
2989 else if (ex
->X_op
!= O_constant
)
2990 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2993 /* Count the leading zeroes by performing a binary chop. This is a
2994 bulky bit of source, but performance is a LOT better for the
2995 majority of values than a simple loop to count the bits:
2996 for (lcnt = 0; (lcnt < 32); lcnt++)
2997 if ((v) & (1 << (31 - lcnt)))
2999 However it is not code size friendly, and the gain will drop a bit
3000 on certain cached systems.
3002 #define COUNT_TOP_ZEROES(v) \
3003 (((v) & ~0xffff) == 0 \
3004 ? ((v) & ~0xff) == 0 \
3005 ? ((v) & ~0xf) == 0 \
3006 ? ((v) & ~0x3) == 0 \
3007 ? ((v) & ~0x1) == 0 \
3012 : ((v) & ~0x7) == 0 \
3015 : ((v) & ~0x3f) == 0 \
3016 ? ((v) & ~0x1f) == 0 \
3019 : ((v) & ~0x7f) == 0 \
3022 : ((v) & ~0xfff) == 0 \
3023 ? ((v) & ~0x3ff) == 0 \
3024 ? ((v) & ~0x1ff) == 0 \
3027 : ((v) & ~0x7ff) == 0 \
3030 : ((v) & ~0x3fff) == 0 \
3031 ? ((v) & ~0x1fff) == 0 \
3034 : ((v) & ~0x7fff) == 0 \
3037 : ((v) & ~0xffffff) == 0 \
3038 ? ((v) & ~0xfffff) == 0 \
3039 ? ((v) & ~0x3ffff) == 0 \
3040 ? ((v) & ~0x1ffff) == 0 \
3043 : ((v) & ~0x7ffff) == 0 \
3046 : ((v) & ~0x3fffff) == 0 \
3047 ? ((v) & ~0x1fffff) == 0 \
3050 : ((v) & ~0x7fffff) == 0 \
3053 : ((v) & ~0xfffffff) == 0 \
3054 ? ((v) & ~0x3ffffff) == 0 \
3055 ? ((v) & ~0x1ffffff) == 0 \
3058 : ((v) & ~0x7ffffff) == 0 \
3061 : ((v) & ~0x3fffffff) == 0 \
3062 ? ((v) & ~0x1fffffff) == 0 \
3065 : ((v) & ~0x7fffffff) == 0 \
3070 * This routine generates the least number of instructions neccessary to load
3071 * an absolute expression value into a register.
3074 load_register (counter
, reg
, ep
, dbl
)
3081 expressionS hi32
, lo32
;
3083 if (ep
->X_op
!= O_big
)
3085 assert (ep
->X_op
== O_constant
);
3086 if (ep
->X_add_number
< 0x8000
3087 && (ep
->X_add_number
>= 0
3088 || (ep
->X_add_number
>= -0x8000
3091 || sizeof (ep
->X_add_number
) > 4))))
3093 /* We can handle 16 bit signed values with an addiu to
3094 $zero. No need to ever use daddiu here, since $zero and
3095 the result are always correct in 32 bit mode. */
3096 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3097 (int) BFD_RELOC_LO16
);
3100 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3102 /* We can handle 16 bit unsigned values with an ori to
3104 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3105 (int) BFD_RELOC_LO16
);
3108 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3109 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3110 == ~ (offsetT
) 0x7fffffff))
3113 || sizeof (ep
->X_add_number
) > 4
3114 || (ep
->X_add_number
& 0x80000000) == 0))
3115 || ((mips_opts
.isa
< 3 || ! dbl
)
3116 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3117 || (mips_opts
.isa
< 3
3119 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3120 == ~ (offsetT
) 0xffffffff)))
3122 /* 32 bit values require an lui. */
3123 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3124 (int) BFD_RELOC_HI16
);
3125 if ((ep
->X_add_number
& 0xffff) != 0)
3126 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3127 (int) BFD_RELOC_LO16
);
3132 /* The value is larger than 32 bits. */
3134 if (mips_opts
.isa
< 3)
3136 as_bad (_("Number larger than 32 bits"));
3137 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3138 (int) BFD_RELOC_LO16
);
3142 if (ep
->X_op
!= O_big
)
3145 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3146 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3147 hi32
.X_add_number
&= 0xffffffff;
3149 lo32
.X_add_number
&= 0xffffffff;
3153 assert (ep
->X_add_number
> 2);
3154 if (ep
->X_add_number
== 3)
3155 generic_bignum
[3] = 0;
3156 else if (ep
->X_add_number
> 4)
3157 as_bad (_("Number larger than 64 bits"));
3158 lo32
.X_op
= O_constant
;
3159 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3160 hi32
.X_op
= O_constant
;
3161 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3164 if (hi32
.X_add_number
== 0)
3169 unsigned long hi
, lo
;
3171 if (hi32
.X_add_number
== 0xffffffff)
3173 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3175 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3176 reg
, 0, (int) BFD_RELOC_LO16
);
3179 if (lo32
.X_add_number
& 0x80000000)
3181 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3182 (int) BFD_RELOC_HI16
);
3183 if (lo32
.X_add_number
& 0xffff)
3184 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3185 reg
, reg
, (int) BFD_RELOC_LO16
);
3190 /* Check for 16bit shifted constant. We know that hi32 is
3191 non-zero, so start the mask on the first bit of the hi32
3196 unsigned long himask
, lomask
;
3200 himask
= 0xffff >> (32 - shift
);
3201 lomask
= (0xffff << shift
) & 0xffffffff;
3205 himask
= 0xffff << (shift
- 32);
3208 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3209 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3213 tmp
.X_op
= O_constant
;
3215 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3216 | (lo32
.X_add_number
>> shift
));
3218 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3219 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3220 (int) BFD_RELOC_LO16
);
3221 macro_build ((char *) NULL
, counter
, NULL
,
3222 (shift
>= 32) ? "dsll32" : "dsll",
3224 (shift
>= 32) ? shift
- 32 : shift
);
3228 } while (shift
<= (64 - 16));
3230 /* Find the bit number of the lowest one bit, and store the
3231 shifted value in hi/lo. */
3232 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3233 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3237 while ((lo
& 1) == 0)
3242 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3248 while ((hi
& 1) == 0)
3257 /* Optimize if the shifted value is a (power of 2) - 1. */
3258 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3259 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3261 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3266 /* This instruction will set the register to be all
3268 tmp
.X_op
= O_constant
;
3269 tmp
.X_add_number
= (offsetT
) -1;
3270 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3271 reg
, 0, (int) BFD_RELOC_LO16
);
3275 macro_build ((char *) NULL
, counter
, NULL
,
3276 (bit
>= 32) ? "dsll32" : "dsll",
3278 (bit
>= 32) ? bit
- 32 : bit
);
3280 macro_build ((char *) NULL
, counter
, NULL
,
3281 (shift
>= 32) ? "dsrl32" : "dsrl",
3283 (shift
>= 32) ? shift
- 32 : shift
);
3288 /* Sign extend hi32 before calling load_register, because we can
3289 generally get better code when we load a sign extended value. */
3290 if ((hi32
.X_add_number
& 0x80000000) != 0)
3291 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3292 load_register (counter
, reg
, &hi32
, 0);
3295 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3299 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3308 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3310 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3311 (int) BFD_RELOC_HI16
);
3312 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3319 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3324 mid16
.X_add_number
>>= 16;
3325 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3326 freg
, (int) BFD_RELOC_LO16
);
3327 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3331 if ((lo32
.X_add_number
& 0xffff) != 0)
3332 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3333 (int) BFD_RELOC_LO16
);
3336 /* Load an address into a register. */
3339 load_address (counter
, reg
, ep
)
3346 if (ep
->X_op
!= O_constant
3347 && ep
->X_op
!= O_symbol
)
3349 as_bad (_("expression too complex"));
3350 ep
->X_op
= O_constant
;
3353 if (ep
->X_op
== O_constant
)
3355 load_register (counter
, reg
, ep
, 0);
3359 if (mips_pic
== NO_PIC
)
3361 /* If this is a reference to a GP relative symbol, we want
3362 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3364 lui $reg,<sym> (BFD_RELOC_HI16_S)
3365 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3366 If we have an addend, we always use the latter form. */
3367 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3368 || nopic_need_relax (ep
->X_add_symbol
, 1))
3373 macro_build ((char *) NULL
, counter
, ep
,
3374 ((bfd_arch_bits_per_address (stdoutput
) == 32
3375 || mips_opts
.isa
< 3)
3376 ? "addiu" : "daddiu"),
3377 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3378 p
= frag_var (rs_machine_dependent
, 8, 0,
3379 RELAX_ENCODE (4, 8, 0, 4, 0,
3380 mips_opts
.warn_about_macros
),
3381 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3383 macro_build_lui (p
, counter
, ep
, reg
);
3386 macro_build (p
, counter
, ep
,
3387 ((bfd_arch_bits_per_address (stdoutput
) == 32
3388 || mips_opts
.isa
< 3)
3389 ? "addiu" : "daddiu"),
3390 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3392 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3396 /* If this is a reference to an external symbol, we want
3397 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3399 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3401 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3402 If there is a constant, it must be added in after. */
3403 ex
.X_add_number
= ep
->X_add_number
;
3404 ep
->X_add_number
= 0;
3406 macro_build ((char *) NULL
, counter
, ep
,
3407 ((bfd_arch_bits_per_address (stdoutput
) == 32
3408 || mips_opts
.isa
< 3)
3410 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3411 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3412 p
= frag_var (rs_machine_dependent
, 4, 0,
3413 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3414 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3415 macro_build (p
, counter
, ep
,
3416 ((bfd_arch_bits_per_address (stdoutput
) == 32
3417 || mips_opts
.isa
< 3)
3418 ? "addiu" : "daddiu"),
3419 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3420 if (ex
.X_add_number
!= 0)
3422 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3423 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3424 ex
.X_op
= O_constant
;
3425 macro_build ((char *) NULL
, counter
, &ex
,
3426 ((bfd_arch_bits_per_address (stdoutput
) == 32
3427 || mips_opts
.isa
< 3)
3428 ? "addiu" : "daddiu"),
3429 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3432 else if (mips_pic
== SVR4_PIC
)
3437 /* This is the large GOT case. If this is a reference to an
3438 external symbol, we want
3439 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3441 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3442 Otherwise, for a reference to a local symbol, we want
3443 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3445 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3446 If there is a constant, it must be added in after. */
3447 ex
.X_add_number
= ep
->X_add_number
;
3448 ep
->X_add_number
= 0;
3449 if (reg_needs_delay (GP
))
3454 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3455 (int) BFD_RELOC_MIPS_GOT_HI16
);
3456 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3457 ((bfd_arch_bits_per_address (stdoutput
) == 32
3458 || mips_opts
.isa
< 3)
3459 ? "addu" : "daddu"),
3460 "d,v,t", reg
, reg
, GP
);
3461 macro_build ((char *) NULL
, counter
, ep
,
3462 ((bfd_arch_bits_per_address (stdoutput
) == 32
3463 || mips_opts
.isa
< 3)
3465 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3466 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3467 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3468 mips_opts
.warn_about_macros
),
3469 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3472 /* We need a nop before loading from $gp. This special
3473 check is required because the lui which starts the main
3474 instruction stream does not refer to $gp, and so will not
3475 insert the nop which may be required. */
3476 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3479 macro_build (p
, counter
, ep
,
3480 ((bfd_arch_bits_per_address (stdoutput
) == 32
3481 || mips_opts
.isa
< 3)
3483 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3485 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3487 macro_build (p
, counter
, ep
,
3488 ((bfd_arch_bits_per_address (stdoutput
) == 32
3489 || mips_opts
.isa
< 3)
3490 ? "addiu" : "daddiu"),
3491 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3492 if (ex
.X_add_number
!= 0)
3494 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3495 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3496 ex
.X_op
= O_constant
;
3497 macro_build ((char *) NULL
, counter
, &ex
,
3498 ((bfd_arch_bits_per_address (stdoutput
) == 32
3499 || mips_opts
.isa
< 3)
3500 ? "addiu" : "daddiu"),
3501 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3504 else if (mips_pic
== EMBEDDED_PIC
)
3507 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3509 macro_build ((char *) NULL
, counter
, ep
,
3510 ((bfd_arch_bits_per_address (stdoutput
) == 32
3511 || mips_opts
.isa
< 3)
3512 ? "addiu" : "daddiu"),
3513 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3521 * This routine implements the seemingly endless macro or synthesized
3522 * instructions and addressing modes in the mips assembly language. Many
3523 * of these macros are simple and are similar to each other. These could
3524 * probably be handled by some kind of table or grammer aproach instead of
3525 * this verbose method. Others are not simple macros but are more like
3526 * optimizing code generation.
3527 * One interesting optimization is when several store macros appear
3528 * consecutivly that would load AT with the upper half of the same address.
3529 * The ensuing load upper instructions are ommited. This implies some kind
3530 * of global optimization. We currently only optimize within a single macro.
3531 * For many of the load and store macros if the address is specified as a
3532 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3533 * first load register 'at' with zero and use it as the base register. The
3534 * mips assembler simply uses register $zero. Just one tiny optimization
3539 struct mips_cl_insn
*ip
;
3541 register int treg
, sreg
, dreg
, breg
;
3557 bfd_reloc_code_real_type r
;
3559 int hold_mips_optimize
;
3561 assert (! mips_opts
.mips16
);
3563 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3564 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3565 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3566 mask
= ip
->insn_mo
->mask
;
3568 expr1
.X_op
= O_constant
;
3569 expr1
.X_op_symbol
= NULL
;
3570 expr1
.X_add_symbol
= NULL
;
3571 expr1
.X_add_number
= 1;
3583 mips_emit_delays (true);
3584 ++mips_opts
.noreorder
;
3585 mips_any_noreorder
= 1;
3587 expr1
.X_add_number
= 8;
3588 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3590 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3592 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3593 macro_build ((char *) NULL
, &icnt
, NULL
,
3594 dbl
? "dsub" : "sub",
3595 "d,v,t", dreg
, 0, sreg
);
3597 --mips_opts
.noreorder
;
3618 if (imm_expr
.X_op
== O_constant
3619 && imm_expr
.X_add_number
>= -0x8000
3620 && imm_expr
.X_add_number
< 0x8000)
3622 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3623 (int) BFD_RELOC_LO16
);
3626 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3627 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3646 if (imm_expr
.X_op
== O_constant
3647 && imm_expr
.X_add_number
>= 0
3648 && imm_expr
.X_add_number
< 0x10000)
3650 if (mask
!= M_NOR_I
)
3651 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3652 sreg
, (int) BFD_RELOC_LO16
);
3655 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3656 treg
, sreg
, (int) BFD_RELOC_LO16
);
3657 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3663 load_register (&icnt
, AT
, &imm_expr
, 0);
3664 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3681 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3683 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3687 load_register (&icnt
, AT
, &imm_expr
, 0);
3688 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3696 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3697 likely
? "bgezl" : "bgez",
3703 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3704 likely
? "blezl" : "blez",
3708 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3709 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3710 likely
? "beql" : "beq",
3717 /* check for > max integer */
3718 maxnum
= 0x7fffffff;
3719 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3726 if (imm_expr
.X_op
== O_constant
3727 && imm_expr
.X_add_number
>= maxnum
3728 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3731 /* result is always false */
3734 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3735 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3739 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3740 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3745 if (imm_expr
.X_op
!= O_constant
)
3746 as_bad (_("Unsupported large constant"));
3747 imm_expr
.X_add_number
++;
3751 if (mask
== M_BGEL_I
)
3753 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3755 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3756 likely
? "bgezl" : "bgez",
3760 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3762 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3763 likely
? "bgtzl" : "bgtz",
3767 maxnum
= 0x7fffffff;
3768 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3775 maxnum
= - maxnum
- 1;
3776 if (imm_expr
.X_op
== O_constant
3777 && imm_expr
.X_add_number
<= maxnum
3778 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3781 /* result is always true */
3782 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3783 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3786 set_at (&icnt
, sreg
, 0);
3787 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3788 likely
? "beql" : "beq",
3799 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3800 likely
? "beql" : "beq",
3804 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3806 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3807 likely
? "beql" : "beq",
3815 || (mips_opts
.isa
< 3
3816 && imm_expr
.X_op
== O_constant
3817 && imm_expr
.X_add_number
== 0xffffffff))
3819 if (imm_expr
.X_op
!= O_constant
)
3820 as_bad (_("Unsupported large constant"));
3821 imm_expr
.X_add_number
++;
3825 if (mask
== M_BGEUL_I
)
3827 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3829 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3831 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3832 likely
? "bnel" : "bne",
3836 set_at (&icnt
, sreg
, 1);
3837 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3838 likely
? "beql" : "beq",
3847 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3848 likely
? "bgtzl" : "bgtz",
3854 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3855 likely
? "bltzl" : "bltz",
3859 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3860 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3861 likely
? "bnel" : "bne",
3870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3871 likely
? "bnel" : "bne",
3877 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3879 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3880 likely
? "bnel" : "bne",
3889 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3890 likely
? "blezl" : "blez",
3896 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3897 likely
? "bgezl" : "bgez",
3901 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3903 likely
? "beql" : "beq",
3910 maxnum
= 0x7fffffff;
3911 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3918 if (imm_expr
.X_op
== O_constant
3919 && imm_expr
.X_add_number
>= maxnum
3920 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3922 if (imm_expr
.X_op
!= O_constant
)
3923 as_bad (_("Unsupported large constant"));
3924 imm_expr
.X_add_number
++;
3928 if (mask
== M_BLTL_I
)
3930 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3933 likely
? "bltzl" : "bltz",
3937 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3939 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3940 likely
? "blezl" : "blez",
3944 set_at (&icnt
, sreg
, 0);
3945 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3946 likely
? "bnel" : "bne",
3955 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3956 likely
? "beql" : "beq",
3962 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3964 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3965 likely
? "beql" : "beq",
3973 || (mips_opts
.isa
< 3
3974 && imm_expr
.X_op
== O_constant
3975 && imm_expr
.X_add_number
== 0xffffffff))
3977 if (imm_expr
.X_op
!= O_constant
)
3978 as_bad (_("Unsupported large constant"));
3979 imm_expr
.X_add_number
++;
3983 if (mask
== M_BLTUL_I
)
3985 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3987 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3989 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3990 likely
? "beql" : "beq",
3994 set_at (&icnt
, sreg
, 1);
3995 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3996 likely
? "bnel" : "bne",
4005 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4006 likely
? "bltzl" : "bltz",
4012 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4013 likely
? "bgtzl" : "bgtz",
4017 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4018 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4019 likely
? "bnel" : "bne",
4030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4031 likely
? "bnel" : "bne",
4035 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4037 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4038 likely
? "bnel" : "bne",
4054 as_warn (_("Divide by zero."));
4056 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4058 /* start-sanitize-r5900 */
4060 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4062 /* end-sanitize-r5900 */
4063 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4067 mips_emit_delays (true);
4068 ++mips_opts
.noreorder
;
4069 mips_any_noreorder
= 1;
4072 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4073 macro_build ((char *) NULL
, &icnt
, NULL
,
4074 dbl
? "ddiv" : "div",
4075 "z,s,t", sreg
, treg
);
4079 expr1
.X_add_number
= 8;
4080 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4081 macro_build ((char *) NULL
, &icnt
, NULL
,
4082 dbl
? "ddiv" : "div",
4083 "z,s,t", sreg
, treg
);
4084 /* start-sanitize-r5900 */
4086 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4088 /* end-sanitize-r5900 */
4089 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4091 expr1
.X_add_number
= -1;
4092 macro_build ((char *) NULL
, &icnt
, &expr1
,
4093 dbl
? "daddiu" : "addiu",
4094 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4095 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4096 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4099 expr1
.X_add_number
= 1;
4100 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4101 (int) BFD_RELOC_LO16
);
4102 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4107 expr1
.X_add_number
= 0x80000000;
4108 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4109 (int) BFD_RELOC_HI16
);
4113 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4114 /* We want to close the noreorder block as soon as possible, so
4115 that later insns are available for delay slot filling. */
4116 --mips_opts
.noreorder
;
4120 expr1
.X_add_number
= 8;
4121 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4122 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4124 /* We want to close the noreorder block as soon as possible, so
4125 that later insns are available for delay slot filling. */
4126 --mips_opts
.noreorder
;
4128 /* start-sanitize-r5900 */
4130 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
4132 /* end-sanitize-r5900 */
4133 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4135 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4174 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4176 as_warn (_("Divide by zero."));
4178 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4180 /* start-sanitize-r5900 */
4182 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4184 /* end-sanitize-r5900 */
4185 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4188 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4190 if (strcmp (s2
, "mflo") == 0)
4191 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4194 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4197 if (imm_expr
.X_op
== O_constant
4198 && imm_expr
.X_add_number
== -1
4199 && s
[strlen (s
) - 1] != 'u')
4201 if (strcmp (s2
, "mflo") == 0)
4204 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4207 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4211 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4215 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4216 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4217 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4236 mips_emit_delays (true);
4237 ++mips_opts
.noreorder
;
4238 mips_any_noreorder
= 1;
4241 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4242 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4243 /* We want to close the noreorder block as soon as possible, so
4244 that later insns are available for delay slot filling. */
4245 --mips_opts
.noreorder
;
4249 expr1
.X_add_number
= 8;
4250 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4251 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4253 /* We want to close the noreorder block as soon as possible, so
4254 that later insns are available for delay slot filling. */
4255 --mips_opts
.noreorder
;
4256 /* start-sanitize-r5900 */
4258 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4260 /* end-sanitize-r5900 */
4261 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4263 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4269 /* Load the address of a symbol into a register. If breg is not
4270 zero, we then add a base register to it. */
4272 /* When generating embedded PIC code, we permit expressions of
4275 where bar is an address in the .text section. These are used
4276 when getting the addresses of functions. We don't permit
4277 X_add_number to be non-zero, because if the symbol is
4278 external the relaxing code needs to know that any addend is
4279 purely the offset to X_op_symbol. */
4280 if (mips_pic
== EMBEDDED_PIC
4281 && offset_expr
.X_op
== O_subtract
4282 && now_seg
== text_section
4283 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4284 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4285 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4286 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4287 ->sy_value
.X_add_symbol
)
4290 && offset_expr
.X_add_number
== 0)
4292 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4293 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4294 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4295 ((bfd_arch_bits_per_address (stdoutput
) == 32
4296 || mips_opts
.isa
< 3)
4297 ? "addiu" : "daddiu"),
4298 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4302 if (offset_expr
.X_op
!= O_symbol
4303 && offset_expr
.X_op
!= O_constant
)
4305 as_bad (_("expression too complex"));
4306 offset_expr
.X_op
= O_constant
;
4320 if (offset_expr
.X_op
== O_constant
)
4321 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4322 else if (mips_pic
== NO_PIC
)
4324 /* If this is a reference to an GP relative symbol, we want
4325 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4327 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4328 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4329 If we have a constant, we need two instructions anyhow,
4330 so we may as well always use the latter form. */
4331 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4332 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4337 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4338 ((bfd_arch_bits_per_address (stdoutput
) == 32
4339 || mips_opts
.isa
< 3)
4340 ? "addiu" : "daddiu"),
4341 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4342 p
= frag_var (rs_machine_dependent
, 8, 0,
4343 RELAX_ENCODE (4, 8, 0, 4, 0,
4344 mips_opts
.warn_about_macros
),
4345 offset_expr
.X_add_symbol
, (offsetT
) 0,
4348 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4351 macro_build (p
, &icnt
, &offset_expr
,
4352 ((bfd_arch_bits_per_address (stdoutput
) == 32
4353 || mips_opts
.isa
< 3)
4354 ? "addiu" : "daddiu"),
4355 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4357 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4359 /* If this is a reference to an external symbol, and there
4360 is no constant, we want
4361 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4362 For a local symbol, we want
4363 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4365 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4367 If we have a small constant, and this is a reference to
4368 an external symbol, we want
4369 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4371 addiu $tempreg,$tempreg,<constant>
4372 For a local symbol, we want the same instruction
4373 sequence, but we output a BFD_RELOC_LO16 reloc on the
4376 If we have a large constant, and this is a reference to
4377 an external symbol, we want
4378 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4379 lui $at,<hiconstant>
4380 addiu $at,$at,<loconstant>
4381 addu $tempreg,$tempreg,$at
4382 For a local symbol, we want the same instruction
4383 sequence, but we output a BFD_RELOC_LO16 reloc on the
4384 addiu instruction. */
4385 expr1
.X_add_number
= offset_expr
.X_add_number
;
4386 offset_expr
.X_add_number
= 0;
4388 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4390 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4391 if (expr1
.X_add_number
== 0)
4399 /* We're going to put in an addu instruction using
4400 tempreg, so we may as well insert the nop right
4402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4406 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4407 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4409 ? mips_opts
.warn_about_macros
4411 offset_expr
.X_add_symbol
, (offsetT
) 0,
4415 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4418 macro_build (p
, &icnt
, &expr1
,
4419 ((bfd_arch_bits_per_address (stdoutput
) == 32
4420 || mips_opts
.isa
< 3)
4421 ? "addiu" : "daddiu"),
4422 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4423 /* FIXME: If breg == 0, and the next instruction uses
4424 $tempreg, then if this variant case is used an extra
4425 nop will be generated. */
4427 else if (expr1
.X_add_number
>= -0x8000
4428 && expr1
.X_add_number
< 0x8000)
4430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4432 macro_build ((char *) NULL
, &icnt
, &expr1
,
4433 ((bfd_arch_bits_per_address (stdoutput
) == 32
4434 || mips_opts
.isa
< 3)
4435 ? "addiu" : "daddiu"),
4436 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4437 (void) frag_var (rs_machine_dependent
, 0, 0,
4438 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4439 offset_expr
.X_add_symbol
, (offsetT
) 0,
4446 /* If we are going to add in a base register, and the
4447 target register and the base register are the same,
4448 then we are using AT as a temporary register. Since
4449 we want to load the constant into AT, we add our
4450 current AT (from the global offset table) and the
4451 register into the register now, and pretend we were
4452 not using a base register. */
4457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4459 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4460 ((bfd_arch_bits_per_address (stdoutput
) == 32
4461 || mips_opts
.isa
< 3)
4462 ? "addu" : "daddu"),
4463 "d,v,t", treg
, AT
, breg
);
4469 /* Set mips_optimize around the lui instruction to avoid
4470 inserting an unnecessary nop after the lw. */
4471 hold_mips_optimize
= mips_optimize
;
4473 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4474 mips_optimize
= hold_mips_optimize
;
4476 macro_build ((char *) NULL
, &icnt
, &expr1
,
4477 ((bfd_arch_bits_per_address (stdoutput
) == 32
4478 || mips_opts
.isa
< 3)
4479 ? "addiu" : "daddiu"),
4480 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4482 ((bfd_arch_bits_per_address (stdoutput
) == 32
4483 || mips_opts
.isa
< 3)
4484 ? "addu" : "daddu"),
4485 "d,v,t", tempreg
, tempreg
, AT
);
4486 (void) frag_var (rs_machine_dependent
, 0, 0,
4487 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4488 offset_expr
.X_add_symbol
, (offsetT
) 0,
4493 else if (mips_pic
== SVR4_PIC
)
4497 /* This is the large GOT case. If this is a reference to an
4498 external symbol, and there is no constant, we want
4499 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4500 addu $tempreg,$tempreg,$gp
4501 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4502 For a local symbol, we want
4503 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4505 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4507 If we have a small constant, and this is a reference to
4508 an external symbol, we want
4509 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4510 addu $tempreg,$tempreg,$gp
4511 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4513 addiu $tempreg,$tempreg,<constant>
4514 For a local symbol, we want
4515 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4517 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4519 If we have a large constant, and this is a reference to
4520 an external symbol, we want
4521 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4522 addu $tempreg,$tempreg,$gp
4523 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4524 lui $at,<hiconstant>
4525 addiu $at,$at,<loconstant>
4526 addu $tempreg,$tempreg,$at
4527 For a local symbol, we want
4528 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4529 lui $at,<hiconstant>
4530 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4531 addu $tempreg,$tempreg,$at
4533 expr1
.X_add_number
= offset_expr
.X_add_number
;
4534 offset_expr
.X_add_number
= 0;
4536 if (reg_needs_delay (GP
))
4540 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4541 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4543 ((bfd_arch_bits_per_address (stdoutput
) == 32
4544 || mips_opts
.isa
< 3)
4545 ? "addu" : "daddu"),
4546 "d,v,t", tempreg
, tempreg
, GP
);
4547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4549 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4551 if (expr1
.X_add_number
== 0)
4559 /* We're going to put in an addu instruction using
4560 tempreg, so we may as well insert the nop right
4562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4567 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4568 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4571 ? mips_opts
.warn_about_macros
4573 offset_expr
.X_add_symbol
, (offsetT
) 0,
4576 else if (expr1
.X_add_number
>= -0x8000
4577 && expr1
.X_add_number
< 0x8000)
4579 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4581 macro_build ((char *) NULL
, &icnt
, &expr1
,
4582 ((bfd_arch_bits_per_address (stdoutput
) == 32
4583 || mips_opts
.isa
< 3)
4584 ? "addiu" : "daddiu"),
4585 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4587 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4588 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4590 ? mips_opts
.warn_about_macros
4592 offset_expr
.X_add_symbol
, (offsetT
) 0,
4599 /* If we are going to add in a base register, and the
4600 target register and the base register are the same,
4601 then we are using AT as a temporary register. Since
4602 we want to load the constant into AT, we add our
4603 current AT (from the global offset table) and the
4604 register into the register now, and pretend we were
4605 not using a base register. */
4613 assert (tempreg
== AT
);
4614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4616 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4617 ((bfd_arch_bits_per_address (stdoutput
) == 32
4618 || mips_opts
.isa
< 3)
4619 ? "addu" : "daddu"),
4620 "d,v,t", treg
, AT
, breg
);
4625 /* Set mips_optimize around the lui instruction to avoid
4626 inserting an unnecessary nop after the lw. */
4627 hold_mips_optimize
= mips_optimize
;
4629 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4630 mips_optimize
= hold_mips_optimize
;
4632 macro_build ((char *) NULL
, &icnt
, &expr1
,
4633 ((bfd_arch_bits_per_address (stdoutput
) == 32
4634 || mips_opts
.isa
< 3)
4635 ? "addiu" : "daddiu"),
4636 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4638 ((bfd_arch_bits_per_address (stdoutput
) == 32
4639 || mips_opts
.isa
< 3)
4640 ? "addu" : "daddu"),
4641 "d,v,t", dreg
, dreg
, AT
);
4643 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4644 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4647 ? mips_opts
.warn_about_macros
4649 offset_expr
.X_add_symbol
, (offsetT
) 0,
4657 /* This is needed because this instruction uses $gp, but
4658 the first instruction on the main stream does not. */
4659 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4662 macro_build (p
, &icnt
, &offset_expr
,
4664 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4666 if (expr1
.X_add_number
>= -0x8000
4667 && expr1
.X_add_number
< 0x8000)
4669 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4671 macro_build (p
, &icnt
, &expr1
,
4672 ((bfd_arch_bits_per_address (stdoutput
) == 32
4673 || mips_opts
.isa
< 3)
4674 ? "addiu" : "daddiu"),
4675 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4676 /* FIXME: If add_number is 0, and there was no base
4677 register, the external symbol case ended with a load,
4678 so if the symbol turns out to not be external, and
4679 the next instruction uses tempreg, an unnecessary nop
4680 will be inserted. */
4686 /* We must add in the base register now, as in the
4687 external symbol case. */
4688 assert (tempreg
== AT
);
4689 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4691 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4692 ((bfd_arch_bits_per_address (stdoutput
) == 32
4693 || mips_opts
.isa
< 3)
4694 ? "addu" : "daddu"),
4695 "d,v,t", treg
, AT
, breg
);
4698 /* We set breg to 0 because we have arranged to add
4699 it in in both cases. */
4703 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4705 macro_build (p
, &icnt
, &expr1
,
4706 ((bfd_arch_bits_per_address (stdoutput
) == 32
4707 || mips_opts
.isa
< 3)
4708 ? "addiu" : "daddiu"),
4709 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4711 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4712 ((bfd_arch_bits_per_address (stdoutput
) == 32
4713 || mips_opts
.isa
< 3)
4714 ? "addu" : "daddu"),
4715 "d,v,t", tempreg
, tempreg
, AT
);
4719 else if (mips_pic
== EMBEDDED_PIC
)
4722 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4724 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4725 ((bfd_arch_bits_per_address (stdoutput
) == 32
4726 || mips_opts
.isa
< 3)
4727 ? "addiu" : "daddiu"),
4728 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4734 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4735 ((bfd_arch_bits_per_address (stdoutput
) == 32
4736 || mips_opts
.isa
< 3)
4737 ? "addu" : "daddu"),
4738 "d,v,t", treg
, tempreg
, breg
);
4746 /* The j instruction may not be used in PIC code, since it
4747 requires an absolute address. We convert it to a b
4749 if (mips_pic
== NO_PIC
)
4750 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4752 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4755 /* The jal instructions must be handled as macros because when
4756 generating PIC code they expand to multi-instruction
4757 sequences. Normally they are simple instructions. */
4762 if (mips_pic
== NO_PIC
4763 || mips_pic
== EMBEDDED_PIC
)
4764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4766 else if (mips_pic
== SVR4_PIC
)
4768 if (sreg
!= PIC_CALL_REG
)
4769 as_warn (_("MIPS PIC call to register other than $25"));
4771 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4773 if (mips_cprestore_offset
< 0)
4774 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4777 expr1
.X_add_number
= mips_cprestore_offset
;
4778 macro_build ((char *) NULL
, &icnt
, &expr1
,
4779 ((bfd_arch_bits_per_address (stdoutput
) == 32
4780 || mips_opts
.isa
< 3)
4782 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4791 if (mips_pic
== NO_PIC
)
4792 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4793 else if (mips_pic
== SVR4_PIC
)
4795 /* If this is a reference to an external symbol, and we are
4796 using a small GOT, we want
4797 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4801 lw $gp,cprestore($sp)
4802 The cprestore value is set using the .cprestore
4803 pseudo-op. If we are using a big GOT, we want
4804 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4806 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4810 lw $gp,cprestore($sp)
4811 If the symbol is not external, we want
4812 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4814 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4817 lw $gp,cprestore($sp) */
4821 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4822 ((bfd_arch_bits_per_address (stdoutput
) == 32
4823 || mips_opts
.isa
< 3)
4825 "t,o(b)", PIC_CALL_REG
,
4826 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4829 p
= frag_var (rs_machine_dependent
, 4, 0,
4830 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4831 offset_expr
.X_add_symbol
, (offsetT
) 0,
4838 if (reg_needs_delay (GP
))
4842 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4843 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4844 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4845 ((bfd_arch_bits_per_address (stdoutput
) == 32
4846 || mips_opts
.isa
< 3)
4847 ? "addu" : "daddu"),
4848 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4849 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4850 ((bfd_arch_bits_per_address (stdoutput
) == 32
4851 || mips_opts
.isa
< 3)
4853 "t,o(b)", PIC_CALL_REG
,
4854 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4857 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4858 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4860 offset_expr
.X_add_symbol
, (offsetT
) 0,
4864 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4867 macro_build (p
, &icnt
, &offset_expr
,
4868 ((bfd_arch_bits_per_address (stdoutput
) == 32
4869 || mips_opts
.isa
< 3)
4871 "t,o(b)", PIC_CALL_REG
,
4872 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4874 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4877 macro_build (p
, &icnt
, &offset_expr
,
4878 ((bfd_arch_bits_per_address (stdoutput
) == 32
4879 || mips_opts
.isa
< 3)
4880 ? "addiu" : "daddiu"),
4881 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4882 (int) BFD_RELOC_LO16
);
4883 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4884 "jalr", "s", PIC_CALL_REG
);
4885 if (mips_cprestore_offset
< 0)
4886 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4889 if (mips_opts
.noreorder
)
4890 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4892 expr1
.X_add_number
= mips_cprestore_offset
;
4893 macro_build ((char *) NULL
, &icnt
, &expr1
,
4894 ((bfd_arch_bits_per_address (stdoutput
) == 32
4895 || mips_opts
.isa
< 3)
4897 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4901 else if (mips_pic
== EMBEDDED_PIC
)
4903 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4904 /* The linker may expand the call to a longer sequence which
4905 uses $at, so we must break rather than return. */
4930 /* Itbl support may require additional care here. */
4935 /* Itbl support may require additional care here. */
4940 /* Itbl support may require additional care here. */
4945 /* Itbl support may require additional care here. */
4959 as_bad (_("opcode not supported on this processor"));
4963 /* Itbl support may require additional care here. */
4968 /* Itbl support may require additional care here. */
4973 /* Itbl support may require additional care here. */
4993 if (breg
== treg
|| coproc
|| lr
)
5015 /* Itbl support may require additional care here. */
5020 /* Itbl support may require additional care here. */
5025 /* Itbl support may require additional care here. */
5030 /* Itbl support may require additional care here. */
5048 as_bad (_("opcode not supported on this processor"));
5053 /* Itbl support may require additional care here. */
5057 /* Itbl support may require additional care here. */
5062 /* Itbl support may require additional care here. */
5074 /* Itbl support may require additional care here. */
5075 if (mask
== M_LWC1_AB
5076 || mask
== M_SWC1_AB
5077 || mask
== M_LDC1_AB
5078 || mask
== M_SDC1_AB
5087 if (offset_expr
.X_op
!= O_constant
5088 && offset_expr
.X_op
!= O_symbol
)
5090 as_bad (_("expression too complex"));
5091 offset_expr
.X_op
= O_constant
;
5094 /* A constant expression in PIC code can be handled just as it
5095 is in non PIC code. */
5096 if (mips_pic
== NO_PIC
5097 || offset_expr
.X_op
== O_constant
)
5099 /* If this is a reference to a GP relative symbol, and there
5100 is no base register, we want
5101 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5102 Otherwise, if there is no base register, we want
5103 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5104 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5105 If we have a constant, we need two instructions anyhow,
5106 so we always use the latter form.
5108 If we have a base register, and this is a reference to a
5109 GP relative symbol, we want
5110 addu $tempreg,$breg,$gp
5111 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5113 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5114 addu $tempreg,$tempreg,$breg
5115 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5116 With a constant we always use the latter case. */
5119 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5120 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5125 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5126 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5127 p
= frag_var (rs_machine_dependent
, 8, 0,
5128 RELAX_ENCODE (4, 8, 0, 4, 0,
5129 (mips_opts
.warn_about_macros
5131 && mips_opts
.noat
))),
5132 offset_expr
.X_add_symbol
, (offsetT
) 0,
5136 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5139 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5140 (int) BFD_RELOC_LO16
, tempreg
);
5144 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5145 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5150 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5151 ((bfd_arch_bits_per_address (stdoutput
) == 32
5152 || mips_opts
.isa
< 3)
5153 ? "addu" : "daddu"),
5154 "d,v,t", tempreg
, breg
, GP
);
5155 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5156 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5157 p
= frag_var (rs_machine_dependent
, 12, 0,
5158 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5159 offset_expr
.X_add_symbol
, (offsetT
) 0,
5162 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5165 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5166 ((bfd_arch_bits_per_address (stdoutput
) == 32
5167 || mips_opts
.isa
< 3)
5168 ? "addu" : "daddu"),
5169 "d,v,t", tempreg
, tempreg
, breg
);
5172 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5173 (int) BFD_RELOC_LO16
, tempreg
);
5176 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5178 /* If this is a reference to an external symbol, we want
5179 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5181 <op> $treg,0($tempreg)
5183 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5185 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5186 <op> $treg,0($tempreg)
5187 If there is a base register, we add it to $tempreg before
5188 the <op>. If there is a constant, we stick it in the
5189 <op> instruction. We don't handle constants larger than
5190 16 bits, because we have no way to load the upper 16 bits
5191 (actually, we could handle them for the subset of cases
5192 in which we are not using $at). */
5193 assert (offset_expr
.X_op
== O_symbol
);
5194 expr1
.X_add_number
= offset_expr
.X_add_number
;
5195 offset_expr
.X_add_number
= 0;
5196 if (expr1
.X_add_number
< -0x8000
5197 || expr1
.X_add_number
>= 0x8000)
5198 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5200 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5201 ((bfd_arch_bits_per_address (stdoutput
) == 32
5202 || mips_opts
.isa
< 3)
5204 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5205 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5206 p
= frag_var (rs_machine_dependent
, 4, 0,
5207 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5208 offset_expr
.X_add_symbol
, (offsetT
) 0,
5210 macro_build (p
, &icnt
, &offset_expr
,
5211 ((bfd_arch_bits_per_address (stdoutput
) == 32
5212 || mips_opts
.isa
< 3)
5213 ? "addiu" : "daddiu"),
5214 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5216 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5217 ((bfd_arch_bits_per_address (stdoutput
) == 32
5218 || mips_opts
.isa
< 3)
5219 ? "addu" : "daddu"),
5220 "d,v,t", tempreg
, tempreg
, breg
);
5221 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5222 (int) BFD_RELOC_LO16
, tempreg
);
5224 else if (mips_pic
== SVR4_PIC
)
5228 /* If this is a reference to an external symbol, we want
5229 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5230 addu $tempreg,$tempreg,$gp
5231 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5232 <op> $treg,0($tempreg)
5234 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5236 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5237 <op> $treg,0($tempreg)
5238 If there is a base register, we add it to $tempreg before
5239 the <op>. If there is a constant, we stick it in the
5240 <op> instruction. We don't handle constants larger than
5241 16 bits, because we have no way to load the upper 16 bits
5242 (actually, we could handle them for the subset of cases
5243 in which we are not using $at). */
5244 assert (offset_expr
.X_op
== O_symbol
);
5245 expr1
.X_add_number
= offset_expr
.X_add_number
;
5246 offset_expr
.X_add_number
= 0;
5247 if (expr1
.X_add_number
< -0x8000
5248 || expr1
.X_add_number
>= 0x8000)
5249 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5250 if (reg_needs_delay (GP
))
5255 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5256 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5257 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5258 ((bfd_arch_bits_per_address (stdoutput
) == 32
5259 || mips_opts
.isa
< 3)
5260 ? "addu" : "daddu"),
5261 "d,v,t", tempreg
, tempreg
, GP
);
5262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5263 ((bfd_arch_bits_per_address (stdoutput
) == 32
5264 || mips_opts
.isa
< 3)
5266 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5268 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5269 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5270 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5273 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5276 macro_build (p
, &icnt
, &offset_expr
,
5277 ((bfd_arch_bits_per_address (stdoutput
) == 32
5278 || mips_opts
.isa
< 3)
5280 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5282 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5284 macro_build (p
, &icnt
, &offset_expr
,
5285 ((bfd_arch_bits_per_address (stdoutput
) == 32
5286 || mips_opts
.isa
< 3)
5287 ? "addiu" : "daddiu"),
5288 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5290 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5291 ((bfd_arch_bits_per_address (stdoutput
) == 32
5292 || mips_opts
.isa
< 3)
5293 ? "addu" : "daddu"),
5294 "d,v,t", tempreg
, tempreg
, breg
);
5295 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5296 (int) BFD_RELOC_LO16
, tempreg
);
5298 else if (mips_pic
== EMBEDDED_PIC
)
5300 /* If there is no base register, we want
5301 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5302 If there is a base register, we want
5303 addu $tempreg,$breg,$gp
5304 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5306 assert (offset_expr
.X_op
== O_symbol
);
5309 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5310 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5315 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5316 ((bfd_arch_bits_per_address (stdoutput
) == 32
5317 || mips_opts
.isa
< 3)
5318 ? "addu" : "daddu"),
5319 "d,v,t", tempreg
, breg
, GP
);
5320 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5321 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5334 load_register (&icnt
, treg
, &imm_expr
, 0);
5338 load_register (&icnt
, treg
, &imm_expr
, 1);
5342 if (imm_expr
.X_op
== O_constant
)
5344 load_register (&icnt
, AT
, &imm_expr
, 0);
5345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5346 "mtc1", "t,G", AT
, treg
);
5351 assert (offset_expr
.X_op
== O_symbol
5352 && strcmp (segment_name (S_GET_SEGMENT
5353 (offset_expr
.X_add_symbol
)),
5355 && offset_expr
.X_add_number
== 0);
5356 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5357 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5362 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5363 the entire value, and in mips1 mode it is the high order 32
5364 bits of the value and the low order 32 bits are either zero
5365 or in offset_expr. */
5366 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5368 if (mips_opts
.isa
>= 3)
5369 load_register (&icnt
, treg
, &imm_expr
, 1);
5374 if (target_big_endian
)
5386 load_register (&icnt
, hreg
, &imm_expr
, 0);
5389 if (offset_expr
.X_op
== O_absent
)
5390 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5394 assert (offset_expr
.X_op
== O_constant
);
5395 load_register (&icnt
, lreg
, &offset_expr
, 0);
5402 /* We know that sym is in the .rdata section. First we get the
5403 upper 16 bits of the address. */
5404 if (mips_pic
== NO_PIC
)
5406 /* FIXME: This won't work for a 64 bit address. */
5407 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5409 else if (mips_pic
== SVR4_PIC
)
5411 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5412 ((bfd_arch_bits_per_address (stdoutput
) == 32
5413 || mips_opts
.isa
< 3)
5415 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5417 else if (mips_pic
== EMBEDDED_PIC
)
5419 /* For embedded PIC we pick up the entire address off $gp in
5420 a single instruction. */
5421 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5422 ((bfd_arch_bits_per_address (stdoutput
) == 32
5423 || mips_opts
.isa
< 3)
5424 ? "addiu" : "daddiu"),
5425 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5426 offset_expr
.X_op
= O_constant
;
5427 offset_expr
.X_add_number
= 0;
5432 /* Now we load the register(s). */
5433 if (mips_opts
.isa
>= 3)
5434 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5435 treg
, (int) BFD_RELOC_LO16
, AT
);
5438 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5439 treg
, (int) BFD_RELOC_LO16
, AT
);
5442 /* FIXME: How in the world do we deal with the possible
5444 offset_expr
.X_add_number
+= 4;
5445 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5446 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5450 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5451 does not become a variant frag. */
5452 frag_wane (frag_now
);
5458 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5459 the entire value, and in mips1 mode it is the high order 32
5460 bits of the value and the low order 32 bits are either zero
5461 or in offset_expr. */
5462 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5464 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5465 if (mips_opts
.isa
>= 3)
5466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5467 "dmtc1", "t,S", AT
, treg
);
5470 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5471 "mtc1", "t,G", AT
, treg
+ 1);
5472 if (offset_expr
.X_op
== O_absent
)
5473 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5474 "mtc1", "t,G", 0, treg
);
5477 assert (offset_expr
.X_op
== O_constant
);
5478 load_register (&icnt
, AT
, &offset_expr
, 0);
5479 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5480 "mtc1", "t,G", AT
, treg
);
5486 assert (offset_expr
.X_op
== O_symbol
5487 && offset_expr
.X_add_number
== 0);
5488 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5489 if (strcmp (s
, ".lit8") == 0)
5491 if (mips_opts
.isa
>= 2)
5493 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5494 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5498 r
= BFD_RELOC_MIPS_LITERAL
;
5503 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5504 if (mips_pic
== SVR4_PIC
)
5505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5506 ((bfd_arch_bits_per_address (stdoutput
) == 32
5507 || mips_opts
.isa
< 3)
5509 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5512 /* FIXME: This won't work for a 64 bit address. */
5513 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5516 if (mips_opts
.isa
>= 2)
5518 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5519 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5521 /* To avoid confusion in tc_gen_reloc, we must ensure
5522 that this does not become a variant frag. */
5523 frag_wane (frag_now
);
5536 as_bad (_("opcode not supported on this processor"));
5539 /* Even on a big endian machine $fn comes before $fn+1. We have
5540 to adjust when loading from memory. */
5543 assert (mips_opts
.isa
< 2);
5544 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5545 target_big_endian
? treg
+ 1 : treg
,
5547 /* FIXME: A possible overflow which I don't know how to deal
5549 offset_expr
.X_add_number
+= 4;
5550 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5551 target_big_endian
? treg
: treg
+ 1,
5554 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5555 does not become a variant frag. */
5556 frag_wane (frag_now
);
5565 * The MIPS assembler seems to check for X_add_number not
5566 * being double aligned and generating:
5569 * addiu at,at,%lo(foo+1)
5572 * But, the resulting address is the same after relocation so why
5573 * generate the extra instruction?
5577 as_bad (_("opcode not supported on this processor"));
5580 /* Itbl support may require additional care here. */
5582 if (mips_opts
.isa
>= 2)
5595 as_bad (_("opcode not supported on this processor"));
5599 if (mips_opts
.isa
>= 2)
5607 /* Itbl support may require additional care here. */
5612 if (mips_opts
.isa
>= 3)
5623 if (mips_opts
.isa
>= 3)
5633 if (offset_expr
.X_op
!= O_symbol
5634 && offset_expr
.X_op
!= O_constant
)
5636 as_bad (_("expression too complex"));
5637 offset_expr
.X_op
= O_constant
;
5640 /* Even on a big endian machine $fn comes before $fn+1. We have
5641 to adjust when loading from memory. We set coproc if we must
5642 load $fn+1 first. */
5643 /* Itbl support may require additional care here. */
5644 if (! target_big_endian
)
5647 if (mips_pic
== NO_PIC
5648 || offset_expr
.X_op
== O_constant
)
5650 /* If this is a reference to a GP relative symbol, we want
5651 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5652 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5653 If we have a base register, we use this
5655 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5656 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5657 If this is not a GP relative symbol, we want
5658 lui $at,<sym> (BFD_RELOC_HI16_S)
5659 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5660 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5661 If there is a base register, we add it to $at after the
5662 lui instruction. If there is a constant, we always use
5664 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5665 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5684 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5685 ((bfd_arch_bits_per_address (stdoutput
) == 32
5686 || mips_opts
.isa
< 3)
5687 ? "addu" : "daddu"),
5688 "d,v,t", AT
, breg
, GP
);
5694 /* Itbl support may require additional care here. */
5695 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5696 coproc
? treg
+ 1 : treg
,
5697 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5698 offset_expr
.X_add_number
+= 4;
5700 /* Set mips_optimize to 2 to avoid inserting an
5702 hold_mips_optimize
= mips_optimize
;
5704 /* Itbl support may require additional care here. */
5705 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5706 coproc
? treg
: treg
+ 1,
5707 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5708 mips_optimize
= hold_mips_optimize
;
5710 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5711 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5712 used_at
&& mips_opts
.noat
),
5713 offset_expr
.X_add_symbol
, (offsetT
) 0,
5716 /* We just generated two relocs. When tc_gen_reloc
5717 handles this case, it will skip the first reloc and
5718 handle the second. The second reloc already has an
5719 extra addend of 4, which we added above. We must
5720 subtract it out, and then subtract another 4 to make
5721 the first reloc come out right. The second reloc
5722 will come out right because we are going to add 4 to
5723 offset_expr when we build its instruction below.
5725 If we have a symbol, then we don't want to include
5726 the offset, because it will wind up being included
5727 when we generate the reloc. */
5729 if (offset_expr
.X_op
== O_constant
)
5730 offset_expr
.X_add_number
-= 8;
5733 offset_expr
.X_add_number
= -4;
5734 offset_expr
.X_op
= O_constant
;
5737 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5742 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5743 ((bfd_arch_bits_per_address (stdoutput
) == 32
5744 || mips_opts
.isa
< 3)
5745 ? "addu" : "daddu"),
5746 "d,v,t", AT
, breg
, AT
);
5750 /* Itbl support may require additional care here. */
5751 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5752 coproc
? treg
+ 1 : treg
,
5753 (int) BFD_RELOC_LO16
, AT
);
5756 /* FIXME: How do we handle overflow here? */
5757 offset_expr
.X_add_number
+= 4;
5758 /* Itbl support may require additional care here. */
5759 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5760 coproc
? treg
: treg
+ 1,
5761 (int) BFD_RELOC_LO16
, AT
);
5763 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5767 /* If this is a reference to an external symbol, we want
5768 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5773 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5775 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5776 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5777 If there is a base register we add it to $at before the
5778 lwc1 instructions. If there is a constant we include it
5779 in the lwc1 instructions. */
5781 expr1
.X_add_number
= offset_expr
.X_add_number
;
5782 offset_expr
.X_add_number
= 0;
5783 if (expr1
.X_add_number
< -0x8000
5784 || expr1
.X_add_number
>= 0x8000 - 4)
5785 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5790 frag_grow (24 + off
);
5791 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5792 ((bfd_arch_bits_per_address (stdoutput
) == 32
5793 || mips_opts
.isa
< 3)
5795 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5796 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5798 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5799 ((bfd_arch_bits_per_address (stdoutput
) == 32
5800 || mips_opts
.isa
< 3)
5801 ? "addu" : "daddu"),
5802 "d,v,t", AT
, breg
, AT
);
5803 /* Itbl support may require additional care here. */
5804 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5805 coproc
? treg
+ 1 : treg
,
5806 (int) BFD_RELOC_LO16
, AT
);
5807 expr1
.X_add_number
+= 4;
5809 /* Set mips_optimize to 2 to avoid inserting an undesired
5811 hold_mips_optimize
= mips_optimize
;
5813 /* Itbl support may require additional care here. */
5814 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5815 coproc
? treg
: treg
+ 1,
5816 (int) BFD_RELOC_LO16
, AT
);
5817 mips_optimize
= hold_mips_optimize
;
5819 (void) frag_var (rs_machine_dependent
, 0, 0,
5820 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5821 offset_expr
.X_add_symbol
, (offsetT
) 0,
5824 else if (mips_pic
== SVR4_PIC
)
5828 /* If this is a reference to an external symbol, we want
5829 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5831 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5836 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5838 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5839 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5840 If there is a base register we add it to $at before the
5841 lwc1 instructions. If there is a constant we include it
5842 in the lwc1 instructions. */
5844 expr1
.X_add_number
= offset_expr
.X_add_number
;
5845 offset_expr
.X_add_number
= 0;
5846 if (expr1
.X_add_number
< -0x8000
5847 || expr1
.X_add_number
>= 0x8000 - 4)
5848 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5849 if (reg_needs_delay (GP
))
5858 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5859 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5860 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5861 ((bfd_arch_bits_per_address (stdoutput
) == 32
5862 || mips_opts
.isa
< 3)
5863 ? "addu" : "daddu"),
5864 "d,v,t", AT
, AT
, GP
);
5865 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5866 ((bfd_arch_bits_per_address (stdoutput
) == 32
5867 || mips_opts
.isa
< 3)
5869 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5870 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5872 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5873 ((bfd_arch_bits_per_address (stdoutput
) == 32
5874 || mips_opts
.isa
< 3)
5875 ? "addu" : "daddu"),
5876 "d,v,t", AT
, breg
, AT
);
5877 /* Itbl support may require additional care here. */
5878 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5879 coproc
? treg
+ 1 : treg
,
5880 (int) BFD_RELOC_LO16
, AT
);
5881 expr1
.X_add_number
+= 4;
5883 /* Set mips_optimize to 2 to avoid inserting an undesired
5885 hold_mips_optimize
= mips_optimize
;
5887 /* Itbl support may require additional care here. */
5888 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5889 coproc
? treg
: treg
+ 1,
5890 (int) BFD_RELOC_LO16
, AT
);
5891 mips_optimize
= hold_mips_optimize
;
5892 expr1
.X_add_number
-= 4;
5894 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5895 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5896 8 + gpdel
+ off
, 1, 0),
5897 offset_expr
.X_add_symbol
, (offsetT
) 0,
5901 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5904 macro_build (p
, &icnt
, &offset_expr
,
5905 ((bfd_arch_bits_per_address (stdoutput
) == 32
5906 || mips_opts
.isa
< 3)
5908 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5910 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5914 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5915 ((bfd_arch_bits_per_address (stdoutput
) == 32
5916 || mips_opts
.isa
< 3)
5917 ? "addu" : "daddu"),
5918 "d,v,t", AT
, breg
, AT
);
5921 /* Itbl support may require additional care here. */
5922 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5923 coproc
? treg
+ 1 : treg
,
5924 (int) BFD_RELOC_LO16
, AT
);
5926 expr1
.X_add_number
+= 4;
5928 /* Set mips_optimize to 2 to avoid inserting an undesired
5930 hold_mips_optimize
= mips_optimize
;
5932 /* Itbl support may require additional care here. */
5933 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5934 coproc
? treg
: treg
+ 1,
5935 (int) BFD_RELOC_LO16
, AT
);
5936 mips_optimize
= hold_mips_optimize
;
5938 else if (mips_pic
== EMBEDDED_PIC
)
5940 /* If there is no base register, we use
5941 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5942 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5943 If we have a base register, we use
5945 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5946 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5955 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5956 ((bfd_arch_bits_per_address (stdoutput
) == 32
5957 || mips_opts
.isa
< 3)
5958 ? "addu" : "daddu"),
5959 "d,v,t", AT
, breg
, GP
);
5964 /* Itbl support may require additional care here. */
5965 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5966 coproc
? treg
+ 1 : treg
,
5967 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5968 offset_expr
.X_add_number
+= 4;
5969 /* Itbl support may require additional care here. */
5970 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5971 coproc
? treg
: treg
+ 1,
5972 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5988 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
5989 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5990 (int) BFD_RELOC_LO16
, breg
);
5991 offset_expr
.X_add_number
+= 4;
5992 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5993 (int) BFD_RELOC_LO16
, breg
);
5996 /* New code added to support COPZ instructions.
5997 This code builds table entries out of the macros in mip_opcodes.
5998 R4000 uses interlocks to handle coproc delays.
5999 Other chips (like the R3000) require nops to be inserted for delays.
6001 FIXME: Currently, we require that the user handle delays.
6002 In order to fill delay slots for non-interlocked chips,
6003 we must have a way to specify delays based on the coprocessor.
6004 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6005 What are the side-effects of the cop instruction?
6006 What cache support might we have and what are its effects?
6007 Both coprocessor & memory require delays. how long???
6008 What registers are read/set/modified?
6010 If an itbl is provided to interpret cop instructions,
6011 this knowledge can be encoded in the itbl spec. */
6025 /* For now we just do C (same as Cz). The parameter will be
6026 stored in insn_opcode by mips_ip. */
6027 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6031 #ifdef LOSING_COMPILER
6033 /* Try and see if this is a new itbl instruction.
6034 This code builds table entries out of the macros in mip_opcodes.
6035 FIXME: For now we just assemble the expression and pass it's
6036 value along as a 32-bit immediate.
6037 We may want to have the assembler assemble this value,
6038 so that we gain the assembler's knowledge of delay slots,
6040 Would it be more efficient to use mask (id) here? */
6041 if (itbl_have_entries
6042 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6044 s
= ip
->insn_mo
->name
;
6046 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6047 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6054 as_warn (_("Macro used $at after \".set noat\""));
6059 struct mips_cl_insn
*ip
;
6061 register int treg
, sreg
, dreg
, breg
;
6077 bfd_reloc_code_real_type r
;
6080 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6081 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6082 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6083 mask
= ip
->insn_mo
->mask
;
6085 expr1
.X_op
= O_constant
;
6086 expr1
.X_op_symbol
= NULL
;
6087 expr1
.X_add_symbol
= NULL
;
6088 expr1
.X_add_number
= 1;
6092 #endif /* LOSING_COMPILER */
6097 macro_build ((char *) NULL
, &icnt
, NULL
,
6098 dbl
? "dmultu" : "multu",
6100 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6106 /* The MIPS assembler some times generates shifts and adds. I'm
6107 not trying to be that fancy. GCC should do this for us
6109 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6110 macro_build ((char *) NULL
, &icnt
, NULL
,
6111 dbl
? "dmult" : "mult",
6113 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6126 mips_emit_delays (true);
6127 ++mips_opts
.noreorder
;
6128 mips_any_noreorder
= 1;
6130 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6131 macro_build ((char *) NULL
, &icnt
, NULL
,
6132 dbl
? "dmult" : "mult",
6133 "s,t", sreg
, imm
? AT
: treg
);
6134 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6135 macro_build ((char *) NULL
, &icnt
, NULL
,
6136 dbl
? "dsra32" : "sra",
6137 "d,w,<", dreg
, dreg
, 31);
6138 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6140 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6143 expr1
.X_add_number
= 8;
6144 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6145 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6146 /* start-sanitize-r5900 */
6148 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
6150 /* end-sanitize-r5900 */
6151 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6153 --mips_opts
.noreorder
;
6154 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6167 mips_emit_delays (true);
6168 ++mips_opts
.noreorder
;
6169 mips_any_noreorder
= 1;
6171 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6172 macro_build ((char *) NULL
, &icnt
, NULL
,
6173 dbl
? "dmultu" : "multu",
6174 "s,t", sreg
, imm
? AT
: treg
);
6175 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6176 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6178 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6181 expr1
.X_add_number
= 8;
6182 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6183 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6184 /* start-sanitize-r5900 */
6186 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
6188 /* end-sanitize-r5900 */
6189 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6191 --mips_opts
.noreorder
;
6195 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6196 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6197 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6199 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6203 if (imm_expr
.X_op
!= O_constant
)
6204 as_bad (_("rotate count too large"));
6205 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6206 (int) (imm_expr
.X_add_number
& 0x1f));
6207 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6208 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6209 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6213 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6214 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6215 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6217 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6221 if (imm_expr
.X_op
!= O_constant
)
6222 as_bad (_("rotate count too large"));
6223 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6224 (int) (imm_expr
.X_add_number
& 0x1f));
6225 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6226 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6227 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6233 as_bad (_("opcode not supported on this processor"));
6236 assert (mips_opts
.isa
< 2);
6237 /* Even on a big endian machine $fn comes before $fn+1. We have
6238 to adjust when storing to memory. */
6239 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6240 target_big_endian
? treg
+ 1 : treg
,
6241 (int) BFD_RELOC_LO16
, breg
);
6242 offset_expr
.X_add_number
+= 4;
6243 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6244 target_big_endian
? treg
: treg
+ 1,
6245 (int) BFD_RELOC_LO16
, breg
);
6250 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6251 treg
, (int) BFD_RELOC_LO16
);
6253 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6254 sreg
, (int) BFD_RELOC_LO16
);
6257 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6259 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6260 dreg
, (int) BFD_RELOC_LO16
);
6265 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6267 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6268 sreg
, (int) BFD_RELOC_LO16
);
6273 as_warn (_("Instruction %s: result is always false"),
6275 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6278 if (imm_expr
.X_op
== O_constant
6279 && imm_expr
.X_add_number
>= 0
6280 && imm_expr
.X_add_number
< 0x10000)
6282 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6283 sreg
, (int) BFD_RELOC_LO16
);
6286 else if (imm_expr
.X_op
== O_constant
6287 && imm_expr
.X_add_number
> -0x8000
6288 && imm_expr
.X_add_number
< 0)
6290 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6291 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6292 ((bfd_arch_bits_per_address (stdoutput
) == 32
6293 || mips_opts
.isa
< 3)
6294 ? "addiu" : "daddiu"),
6295 "t,r,j", dreg
, sreg
,
6296 (int) BFD_RELOC_LO16
);
6301 load_register (&icnt
, AT
, &imm_expr
, 0);
6302 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6306 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6307 (int) BFD_RELOC_LO16
);
6312 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6318 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6319 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6320 (int) BFD_RELOC_LO16
);
6323 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6325 if (imm_expr
.X_op
== O_constant
6326 && imm_expr
.X_add_number
>= -0x8000
6327 && imm_expr
.X_add_number
< 0x8000)
6329 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6330 mask
== M_SGE_I
? "slti" : "sltiu",
6331 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6336 load_register (&icnt
, AT
, &imm_expr
, 0);
6337 macro_build ((char *) NULL
, &icnt
, NULL
,
6338 mask
== M_SGE_I
? "slt" : "sltu",
6339 "d,v,t", dreg
, sreg
, AT
);
6342 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6343 (int) BFD_RELOC_LO16
);
6348 case M_SGT
: /* sreg > treg <==> treg < sreg */
6354 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6357 case M_SGT_I
: /* sreg > I <==> I < sreg */
6363 load_register (&icnt
, AT
, &imm_expr
, 0);
6364 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6367 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6373 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6374 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6375 (int) BFD_RELOC_LO16
);
6378 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6384 load_register (&icnt
, AT
, &imm_expr
, 0);
6385 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6386 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6387 (int) BFD_RELOC_LO16
);
6391 if (imm_expr
.X_op
== O_constant
6392 && imm_expr
.X_add_number
>= -0x8000
6393 && imm_expr
.X_add_number
< 0x8000)
6395 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6396 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6399 load_register (&icnt
, AT
, &imm_expr
, 0);
6400 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6404 if (imm_expr
.X_op
== O_constant
6405 && imm_expr
.X_add_number
>= -0x8000
6406 && imm_expr
.X_add_number
< 0x8000)
6408 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6409 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6412 load_register (&icnt
, AT
, &imm_expr
, 0);
6413 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6419 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6422 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6426 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6428 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6434 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6436 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6442 as_warn (_("Instruction %s: result is always true"),
6444 macro_build ((char *) NULL
, &icnt
, &expr1
,
6445 ((bfd_arch_bits_per_address (stdoutput
) == 32
6446 || mips_opts
.isa
< 3)
6447 ? "addiu" : "daddiu"),
6448 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6451 if (imm_expr
.X_op
== O_constant
6452 && imm_expr
.X_add_number
>= 0
6453 && imm_expr
.X_add_number
< 0x10000)
6455 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6456 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6459 else if (imm_expr
.X_op
== O_constant
6460 && imm_expr
.X_add_number
> -0x8000
6461 && imm_expr
.X_add_number
< 0)
6463 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6464 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6465 ((bfd_arch_bits_per_address (stdoutput
) == 32
6466 || mips_opts
.isa
< 3)
6467 ? "addiu" : "daddiu"),
6468 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6473 load_register (&icnt
, AT
, &imm_expr
, 0);
6474 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6478 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6486 if (imm_expr
.X_op
== O_constant
6487 && imm_expr
.X_add_number
> -0x8000
6488 && imm_expr
.X_add_number
<= 0x8000)
6490 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6491 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6492 dbl
? "daddi" : "addi",
6493 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6496 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6497 macro_build ((char *) NULL
, &icnt
, NULL
,
6498 dbl
? "dsub" : "sub",
6499 "d,v,t", dreg
, sreg
, AT
);
6505 if (imm_expr
.X_op
== O_constant
6506 && imm_expr
.X_add_number
> -0x8000
6507 && imm_expr
.X_add_number
<= 0x8000)
6509 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6510 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6511 dbl
? "daddiu" : "addiu",
6512 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6515 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6516 macro_build ((char *) NULL
, &icnt
, NULL
,
6517 dbl
? "dsubu" : "subu",
6518 "d,v,t", dreg
, sreg
, AT
);
6539 load_register (&icnt
, AT
, &imm_expr
, 0);
6540 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6545 assert (mips_opts
.isa
< 2);
6546 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6547 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6550 * Is the double cfc1 instruction a bug in the mips assembler;
6551 * or is there a reason for it?
6553 mips_emit_delays (true);
6554 ++mips_opts
.noreorder
;
6555 mips_any_noreorder
= 1;
6556 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6557 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6558 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6559 expr1
.X_add_number
= 3;
6560 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6561 (int) BFD_RELOC_LO16
);
6562 expr1
.X_add_number
= 2;
6563 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6564 (int) BFD_RELOC_LO16
);
6565 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6566 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6567 macro_build ((char *) NULL
, &icnt
, NULL
,
6568 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6569 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6570 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6571 --mips_opts
.noreorder
;
6580 if (offset_expr
.X_add_number
>= 0x7fff)
6581 as_bad (_("operand overflow"));
6582 /* avoid load delay */
6583 if (! target_big_endian
)
6584 offset_expr
.X_add_number
+= 1;
6585 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6586 (int) BFD_RELOC_LO16
, breg
);
6587 if (! target_big_endian
)
6588 offset_expr
.X_add_number
-= 1;
6590 offset_expr
.X_add_number
+= 1;
6591 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6592 (int) BFD_RELOC_LO16
, breg
);
6593 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6594 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6607 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6608 as_bad (_("operand overflow"));
6609 if (! target_big_endian
)
6610 offset_expr
.X_add_number
+= off
;
6611 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6612 (int) BFD_RELOC_LO16
, breg
);
6613 if (! target_big_endian
)
6614 offset_expr
.X_add_number
-= off
;
6616 offset_expr
.X_add_number
+= off
;
6617 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6618 (int) BFD_RELOC_LO16
, breg
);
6631 load_address (&icnt
, AT
, &offset_expr
);
6633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6634 ((bfd_arch_bits_per_address (stdoutput
) == 32
6635 || mips_opts
.isa
< 3)
6636 ? "addu" : "daddu"),
6637 "d,v,t", AT
, AT
, breg
);
6638 if (! target_big_endian
)
6639 expr1
.X_add_number
= off
;
6641 expr1
.X_add_number
= 0;
6642 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6643 (int) BFD_RELOC_LO16
, AT
);
6644 if (! target_big_endian
)
6645 expr1
.X_add_number
= 0;
6647 expr1
.X_add_number
= off
;
6648 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6649 (int) BFD_RELOC_LO16
, AT
);
6654 load_address (&icnt
, AT
, &offset_expr
);
6656 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6657 ((bfd_arch_bits_per_address (stdoutput
) == 32
6658 || mips_opts
.isa
< 3)
6659 ? "addu" : "daddu"),
6660 "d,v,t", AT
, AT
, breg
);
6661 if (target_big_endian
)
6662 expr1
.X_add_number
= 0;
6663 macro_build ((char *) NULL
, &icnt
, &expr1
,
6664 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6665 (int) BFD_RELOC_LO16
, AT
);
6666 if (target_big_endian
)
6667 expr1
.X_add_number
= 1;
6669 expr1
.X_add_number
= 0;
6670 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6671 (int) BFD_RELOC_LO16
, AT
);
6672 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6674 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6679 if (offset_expr
.X_add_number
>= 0x7fff)
6680 as_bad (_("operand overflow"));
6681 if (target_big_endian
)
6682 offset_expr
.X_add_number
+= 1;
6683 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6684 (int) BFD_RELOC_LO16
, breg
);
6685 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6686 if (target_big_endian
)
6687 offset_expr
.X_add_number
-= 1;
6689 offset_expr
.X_add_number
+= 1;
6690 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6691 (int) BFD_RELOC_LO16
, breg
);
6704 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6705 as_bad (_("operand overflow"));
6706 if (! target_big_endian
)
6707 offset_expr
.X_add_number
+= off
;
6708 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6709 (int) BFD_RELOC_LO16
, breg
);
6710 if (! target_big_endian
)
6711 offset_expr
.X_add_number
-= off
;
6713 offset_expr
.X_add_number
+= off
;
6714 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6715 (int) BFD_RELOC_LO16
, breg
);
6728 load_address (&icnt
, AT
, &offset_expr
);
6730 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6731 ((bfd_arch_bits_per_address (stdoutput
) == 32
6732 || mips_opts
.isa
< 3)
6733 ? "addu" : "daddu"),
6734 "d,v,t", AT
, AT
, breg
);
6735 if (! target_big_endian
)
6736 expr1
.X_add_number
= off
;
6738 expr1
.X_add_number
= 0;
6739 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6740 (int) BFD_RELOC_LO16
, AT
);
6741 if (! target_big_endian
)
6742 expr1
.X_add_number
= 0;
6744 expr1
.X_add_number
= off
;
6745 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6746 (int) BFD_RELOC_LO16
, AT
);
6750 load_address (&icnt
, AT
, &offset_expr
);
6752 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6753 ((bfd_arch_bits_per_address (stdoutput
) == 32
6754 || mips_opts
.isa
< 3)
6755 ? "addu" : "daddu"),
6756 "d,v,t", AT
, AT
, breg
);
6757 if (! target_big_endian
)
6758 expr1
.X_add_number
= 0;
6759 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6760 (int) BFD_RELOC_LO16
, AT
);
6761 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6763 if (! target_big_endian
)
6764 expr1
.X_add_number
= 1;
6766 expr1
.X_add_number
= 0;
6767 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6768 (int) BFD_RELOC_LO16
, AT
);
6769 if (! target_big_endian
)
6770 expr1
.X_add_number
= 0;
6772 expr1
.X_add_number
= 1;
6773 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6774 (int) BFD_RELOC_LO16
, AT
);
6775 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6777 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6782 /* FIXME: Check if this is one of the itbl macros, since they
6783 are added dynamically. */
6784 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6788 as_warn (_("Macro used $at after \".set noat\""));
6791 /* Implement macros in mips16 mode. */
6795 struct mips_cl_insn
*ip
;
6798 int xreg
, yreg
, zreg
, tmp
;
6802 const char *s
, *s2
, *s3
;
6804 mask
= ip
->insn_mo
->mask
;
6806 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6807 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6808 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6812 expr1
.X_op
= O_constant
;
6813 expr1
.X_op_symbol
= NULL
;
6814 expr1
.X_add_symbol
= NULL
;
6815 expr1
.X_add_number
= 1;
6834 mips_emit_delays (true);
6835 ++mips_opts
.noreorder
;
6836 mips_any_noreorder
= 1;
6837 macro_build ((char *) NULL
, &icnt
, NULL
,
6838 dbl
? "ddiv" : "div",
6839 "0,x,y", xreg
, yreg
);
6840 expr1
.X_add_number
= 2;
6841 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6842 /* start-sanitize-r5900 */
6844 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
6846 /* end-sanitize-r5900 */
6847 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6849 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6850 since that causes an overflow. We should do that as well,
6851 but I don't see how to do the comparisons without a temporary
6853 --mips_opts
.noreorder
;
6854 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6873 mips_emit_delays (true);
6874 ++mips_opts
.noreorder
;
6875 mips_any_noreorder
= 1;
6876 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6877 expr1
.X_add_number
= 2;
6878 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6879 /* start-sanitize-r5900 */
6881 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
6883 /* end-sanitize-r5900 */
6884 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6885 --mips_opts
.noreorder
;
6886 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6892 macro_build ((char *) NULL
, &icnt
, NULL
,
6893 dbl
? "dmultu" : "multu",
6895 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6903 if (imm_expr
.X_op
!= O_constant
)
6904 as_bad (_("Unsupported large constant"));
6905 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6906 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6907 dbl
? "daddiu" : "addiu",
6908 "y,x,4", yreg
, xreg
);
6912 if (imm_expr
.X_op
!= O_constant
)
6913 as_bad (_("Unsupported large constant"));
6914 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6915 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6920 if (imm_expr
.X_op
!= O_constant
)
6921 as_bad (_("Unsupported large constant"));
6922 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6923 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6946 goto do_reverse_branch
;
6950 goto do_reverse_branch
;
6962 goto do_reverse_branch
;
6973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6975 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7002 goto do_addone_branch_i
;
7007 goto do_addone_branch_i
;
7022 goto do_addone_branch_i
;
7029 if (imm_expr
.X_op
!= O_constant
)
7030 as_bad (_("Unsupported large constant"));
7031 ++imm_expr
.X_add_number
;
7034 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7039 expr1
.X_add_number
= 0;
7040 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7042 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7043 "move", "y,X", xreg
, yreg
);
7044 expr1
.X_add_number
= 2;
7045 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7046 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7047 "neg", "x,w", xreg
, xreg
);
7051 /* For consistency checking, verify that all bits are specified either
7052 by the match/mask part of the instruction definition, or by the
7055 validate_mips_insn (opc
)
7056 const struct mips_opcode
*opc
;
7058 const char *p
= opc
->args
;
7060 unsigned long used_bits
= opc
->mask
;
7062 if ((used_bits
& opc
->match
) != opc
->match
)
7064 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7065 opc
->name
, opc
->args
);
7068 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7075 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7076 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7078 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
7079 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7080 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7081 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7083 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7086 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7087 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7088 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7089 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7090 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7091 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7092 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7093 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7094 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7095 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7096 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7098 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7099 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7100 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7101 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7103 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7104 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7105 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7106 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7107 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7108 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7109 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7110 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7111 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7114 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7115 /* start-sanitize-r5900 */
7116 case '0': USE_BITS (OP_MASK_VADDI
, OP_SH_VADDI
); break;
7117 case '1': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
7118 case '2': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
7119 case '3': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
7120 case '4': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
7121 case '5': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
7122 case '6': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
7124 USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
);
7125 USE_BITS (OP_MASK_VUFTF
, OP_SH_VUFTF
);
7128 USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
);
7129 USE_BITS (OP_MASK_VUFSF
, OP_SH_VUFSF
);
7137 case 'O': USE_BITS (OP_MASK_VUCALLMS
, OP_SH_VUCALLMS
);break;
7138 case '&': USE_BITS (OP_MASK_VUDEST
, OP_SH_VUDEST
); break;
7145 /* end-sanitize-r5900 */
7146 /* start-sanitize-cygnus */
7147 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7148 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7151 /* end-sanitize-cygnus */
7153 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7154 c
, opc
->name
, opc
->args
);
7158 if (used_bits
!= 0xffffffff)
7160 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7161 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7167 /* This routine assembles an instruction into its binary format. As a
7168 side effect, it sets one of the global variables imm_reloc or
7169 offset_reloc to the type of relocation to do if one of the operands
7170 is an address expression. */
7175 struct mips_cl_insn
*ip
;
7180 struct mips_opcode
*insn
;
7183 unsigned int lastregno
= 0;
7186 int full_opcode_match
= 1;
7190 /* If the instruction contains a '.', we first try to match an instruction
7191 including the '.'. Then we try again without the '.'. */
7193 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
7196 /* If we stopped on whitespace, then replace the whitespace with null for
7197 the call to hash_find. Save the character we replaced just in case we
7198 have to re-parse the instruction. */
7205 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7207 /* If we didn't find the instruction in the opcode table, try again, but
7208 this time with just the instruction up to, but not including the
7212 /* Restore the character we overwrite above (if any). */
7216 /* Scan up to the first '.' or whitespace. */
7217 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace (*s
); ++s
)
7220 /* If we did not find a '.', then we can quit now. */
7223 insn_error
= "unrecognized opcode";
7227 /* Lookup the instruction in the hash table. */
7229 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7231 insn_error
= "unrecognized opcode";
7235 full_opcode_match
= 0;
7244 assert (strcmp (insn
->name
, str
) == 0);
7246 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7248 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7250 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7252 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7257 if (insn_isa
<= mips_opts
.isa
)
7259 else if (insn
->pinfo
== INSN_MACRO
)
7261 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
7262 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
7263 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
7264 /* start-sanitize-vr4320 */
7265 || (mips_4320
&& (insn
->membership
& INSN_4320
) != 0)
7266 /* end-sanitize-vr4320 */
7267 /* start-sanitize-tx49 */
7268 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
7269 /* end-sanitize-tx49 */
7270 /* start-sanitize-r5900 */
7271 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
7272 /* end-sanitize-r5900 */
7273 /* start-sanitize-cygnus */
7274 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
7275 /* end-sanitize-cygnus */
7276 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
7281 if (insn
->pinfo
!= INSN_MACRO
)
7283 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
7285 /* start-sanitize-r5900 */
7286 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
7288 /* end-sanitize-r5900 */
7293 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7294 && strcmp (insn
->name
, insn
[1].name
) == 0)
7300 || insn_isa
<= mips_opts
.isa
)
7301 insn_error
= _("opcode not supported on this processor");
7304 static char buf
[100];
7306 sprintf (buf
, _("opcode requires -mips%d or greater"), insn_isa
);
7313 ip
->insn_opcode
= insn
->match
;
7314 for (args
= insn
->args
;; ++args
)
7320 case '\0': /* end of args */
7333 ip
->insn_opcode
|= lastregno
<< 21;
7338 ip
->insn_opcode
|= lastregno
<< 16;
7342 ip
->insn_opcode
|= lastregno
<< 11;
7348 /* Handle optional base register.
7349 Either the base register is omitted or
7350 we must have a left paren. */
7351 /* This is dependent on the next operand specifier
7352 is a base register specification. */
7353 assert (args
[1] == 'b' || args
[1] == '5'
7354 || args
[1] == '-' || args
[1] == '4');
7358 case ')': /* these must match exactly */
7359 /* start-sanitize-cygnus */
7362 /* end-sanitize-cygnus */
7363 /* start-sanitize-r5900 */
7366 /* end-sanitize-r5900 */
7371 case '<': /* must be at least one digit */
7373 * According to the manual, if the shift amount is greater
7374 * than 31 or less than 0 the the shift amount should be
7375 * mod 32. In reality the mips assembler issues an error.
7376 * We issue a warning and mask out all but the low 5 bits.
7378 my_getExpression (&imm_expr
, s
);
7379 check_absolute_expr (ip
, &imm_expr
);
7380 if ((unsigned long) imm_expr
.X_add_number
> 31)
7382 as_warn (_("Improper shift amount (%ld)"),
7383 (long) imm_expr
.X_add_number
);
7384 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7386 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7387 imm_expr
.X_op
= O_absent
;
7391 case '>': /* shift amount minus 32 */
7392 my_getExpression (&imm_expr
, s
);
7393 check_absolute_expr (ip
, &imm_expr
);
7394 if ((unsigned long) imm_expr
.X_add_number
< 32
7395 || (unsigned long) imm_expr
.X_add_number
> 63)
7397 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7398 imm_expr
.X_op
= O_absent
;
7402 /* start-sanitize-r5900 */
7403 case '0': /* 5 bit signed immediate at 6 */
7404 my_getExpression (&imm_expr
, s
);
7405 check_absolute_expr (ip
, &imm_expr
);
7406 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7407 || ((imm_expr
.X_add_number
< -16
7408 || imm_expr
.X_add_number
>= 16)
7409 && imm_expr
.X_op
== O_constant
))
7411 if (imm_expr
.X_op
!= O_constant
7412 && imm_expr
.X_op
!= O_big
)
7413 insn_error
= "absolute expression required";
7415 as_bad (_("5 bit expression not in range -16..15"));
7417 ip
->insn_opcode
|= (imm_expr
.X_add_number
) << 6;
7418 imm_expr
.X_op
= O_absent
;
7422 case '9': /* vi27 for vcallmsr */
7423 if (strncmp (s
, "$vi27", 5) == 0)
7425 else if (strncmp (s
, "vi27", 4) == 0)
7428 as_bad (_("expected vi27"));
7431 case '#': /* escape character */
7432 /* '#' specifies that we've got an optional suffix to this
7433 operand that must match exactly (if it exists). */
7434 if (*s
!= '\0' && *s
!= ','
7435 && *s
!= ' ' && *s
!= '\t' && *s
!= '\n')
7437 if (*s
== *(args
+ 1))
7448 case 'K': /* DEST operand completer (optional), must
7449 match previous dest if specified. */
7450 case '&': /* DEST instruction completer */
7451 case ';': /* DEST instruction completer, must be xyz */
7458 /* Parse the completer. */
7460 while ((!full_opcode_match
|| *args
== 'K')
7461 && *s
!= '\0' && *s
!= ' ' && *s
!= ',')
7473 insn_error
= "Invalid dest specification";
7482 /* Each completer can only appear once. */
7483 if (w
> 1 || x
> 1 || y
> 1 || z
> 1)
7485 insn_error
= "Invalid dest specification";
7489 /* If this is the opcode completer, then we must insert
7490 the appropriate value into the insn. */
7493 /* Not strictly in the specs, but requested by users. */
7494 if (w
== 0 && x
== 0 && y
== 0 && z
== 0)
7497 ip
->insn_opcode
|= ((w
<< 21) | (x
<< 24)
7498 | (y
<< 23) | (z
<< 22));
7499 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7501 else if (*args
== ';')
7503 /* This implicitly has the .xyz completer. */
7504 if (w
== 0 && x
== 0 && y
== 0 && z
== 0)
7507 if (w
!= 0 || x
!= 1 || y
!= 1 || z
!= 1)
7509 insn_error
= "Invalid dest specification";
7513 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7519 /* This is the operand completer, make sure it matches
7520 the previous opcode completer. */
7521 temp
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7522 if (temp
&& temp
!= last_h
)
7524 insn_error
= "DEST field in operand does not match DEST field in instruction";
7533 case 'J': /* vu0 I register */
7537 insn_error
= "operand `I' expected";
7540 case 'Q': /* vu0 Q register */
7544 insn_error
= "operand `Q' expected";
7547 case 'X': /* vu0 R register */
7551 insn_error
= "operand `R' expected";
7554 case 'U': /* vu0 ACC register */
7555 if (s
[0] == 'A' && s
[1] == 'C' && s
[2] == 'C')
7558 insn_error
= "operand `ACC' expected";
7562 my_getSmallExpression (&imm_expr
, s
);
7563 imm_reloc
= BFD_RELOC_MIPS15_S3
;
7566 /* end-sanitize-r5900 */
7568 case 'k': /* cache code */
7569 case 'h': /* prefx code */
7570 my_getExpression (&imm_expr
, s
);
7571 check_absolute_expr (ip
, &imm_expr
);
7572 if ((unsigned long) imm_expr
.X_add_number
> 31)
7574 as_warn (_("Invalid value for `%s' (%lu)"),
7576 (unsigned long) imm_expr
.X_add_number
);
7577 imm_expr
.X_add_number
&= 0x1f;
7580 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7582 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7583 imm_expr
.X_op
= O_absent
;
7587 case 'c': /* break code */
7588 my_getExpression (&imm_expr
, s
);
7589 check_absolute_expr (ip
, &imm_expr
);
7590 if ((unsigned) imm_expr
.X_add_number
> 1023)
7592 as_warn (_("Illegal break code (%ld)"),
7593 (long) imm_expr
.X_add_number
);
7594 imm_expr
.X_add_number
&= 0x3ff;
7596 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7597 imm_expr
.X_op
= O_absent
;
7601 case 'q': /* lower break code */
7602 my_getExpression (&imm_expr
, s
);
7603 check_absolute_expr (ip
, &imm_expr
);
7604 if ((unsigned) imm_expr
.X_add_number
> 1023)
7606 as_warn (_("Illegal lower break code (%ld)"),
7607 (long) imm_expr
.X_add_number
);
7608 imm_expr
.X_add_number
&= 0x3ff;
7610 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7611 imm_expr
.X_op
= O_absent
;
7615 case 'B': /* syscall code */
7616 my_getExpression (&imm_expr
, s
);
7617 check_absolute_expr (ip
, &imm_expr
);
7618 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7619 as_warn (_("Illegal syscall code (%ld)"),
7620 (long) imm_expr
.X_add_number
);
7621 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7622 imm_expr
.X_op
= O_absent
;
7626 case 'C': /* Coprocessor code */
7627 my_getExpression (&imm_expr
, s
);
7628 check_absolute_expr (ip
, &imm_expr
);
7629 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7631 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7632 (long) imm_expr
.X_add_number
);
7633 imm_expr
.X_add_number
&= ((1<<25) - 1);
7635 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7636 imm_expr
.X_op
= O_absent
;
7640 case 'P': /* Performance register */
7641 my_getExpression (&imm_expr
, s
);
7642 check_absolute_expr (ip
, &imm_expr
);
7643 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7645 as_warn (_("Invalidate performance regster (%ld)"),
7646 (long) imm_expr
.X_add_number
);
7647 imm_expr
.X_add_number
&= 1;
7649 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7650 imm_expr
.X_op
= O_absent
;
7654 case 'b': /* base register */
7655 case 'd': /* destination register */
7656 case 's': /* source register */
7657 case 't': /* target register */
7658 case 'r': /* both target and source */
7659 case 'v': /* both dest and source */
7660 case 'w': /* both dest and target */
7661 case 'E': /* coprocessor target register */
7662 case 'G': /* coprocessor destination register */
7663 case 'x': /* ignore register name */
7664 case 'z': /* must be zero register */
7668 /* start-sanitize-r5900 */
7669 /* Allow "$viNN" as coprocessor register name */
7677 /* end-sanitize-r5900 */
7689 while (isdigit (*s
));
7691 as_bad (_("Invalid register number (%d)"), regno
);
7693 else if (*args
== 'E' || *args
== 'G')
7697 if (s
[1] == 'f' && s
[2] == 'p')
7702 else if (s
[1] == 's' && s
[2] == 'p')
7707 else if (s
[1] == 'g' && s
[2] == 'p')
7712 else if (s
[1] == 'a' && s
[2] == 't')
7717 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7722 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7727 else if (itbl_have_entries
)
7732 p
= s
+1; /* advance past '$' */
7733 n
= itbl_get_field (&p
); /* n is name */
7735 /* See if this is a register defined in an
7737 r
= itbl_get_reg_val (n
);
7740 /* Get_field advances to the start of
7741 the next field, so we need to back
7742 rack to the end of the last field. */
7746 s
= strchr (s
,'\0');
7759 as_warn (_("Used $at without \".set noat\""));
7765 if (c
== 'r' || c
== 'v' || c
== 'w')
7772 /* 'z' only matches $0. */
7773 if (c
== 'z' && regno
!= 0)
7776 /* Now that we have assembled one operand, we use the args string
7777 * to figure out where it goes in the instruction. */
7784 ip
->insn_opcode
|= regno
<< 21;
7788 ip
->insn_opcode
|= regno
<< 11;
7793 ip
->insn_opcode
|= regno
<< 16;
7796 /* This case exists because on the r3000 trunc
7797 expands into a macro which requires a gp
7798 register. On the r6000 or r4000 it is
7799 assembled into a single instruction which
7800 ignores the register. Thus the insn version
7801 is MIPS_ISA2 and uses 'x', and the macro
7802 version is MIPS_ISA1 and uses 't'. */
7805 /* This case is for the div instruction, which
7806 acts differently if the destination argument
7807 is $0. This only matches $0, and is checked
7808 outside the switch. */
7811 /* Itbl operand; not yet implemented. FIXME ?? */
7813 /* What about all other operands like 'i', which
7814 can be specified in the opcode table? */
7824 ip
->insn_opcode
|= lastregno
<< 21;
7827 ip
->insn_opcode
|= lastregno
<< 16;
7832 case 'D': /* floating point destination register */
7833 case 'S': /* floating point source register */
7834 case 'T': /* floating point target register */
7835 case 'R': /* floating point source register */
7838 /* start-sanitize-r5900 */
7839 case '1': /* vu0 fp reg position 1 */
7840 case '2': /* vu0 fp reg position 2 */
7841 case '3': /* vu0 fp reg position 3 */
7842 case '4': /* vu0 int reg position 1 */
7843 case '5': /* vu0 int reg position 2 */
7844 case '6': /* vu0 int reg position 3 */
7845 case '7': /* vu0 fp reg with ftf modifier */
7846 case '8': /* vu0 fp reg with fsf modifier */
7847 /* end-sanitize-r5900 */
7849 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7859 while (isdigit (*s
));
7862 as_bad (_("Invalid float register number (%d)"), regno
);
7864 if ((regno
& 1) != 0
7865 && mips_opts
.isa
< 3
7866 && ! (strcmp (str
, "mtc1") == 0
7867 || strcmp (str
, "mfc1") == 0
7868 || strcmp (str
, "lwc1") == 0
7869 || strcmp (str
, "swc1") == 0
7870 || strcmp (str
, "l.s") == 0
7871 || strcmp (str
, "s.s") == 0))
7872 as_warn (_("Float register should be even, was %d"),
7880 if (c
== 'V' || c
== 'W')
7890 ip
->insn_opcode
|= regno
<< 6;
7894 ip
->insn_opcode
|= regno
<< 11;
7898 ip
->insn_opcode
|= regno
<< 16;
7901 ip
->insn_opcode
|= regno
<< 21;
7908 /* start-sanitize-r5900 */
7909 /* Handle vf and vi regsiters for vu0. Handle optional
7913 && (s
[1] == 'f' || s
[1] == 'i')
7918 && (s
[2] == 'f' || s
[2] == 'i')
7931 while (isdigit (*s
));
7934 as_bad (_("Invalid vu0 register number (%d)"), regno
);
7938 if (c
== '7' || c
== '8')
7947 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7952 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7957 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7962 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7965 as_bad (_("Invalid FSF/FTF specification"));
7973 if (c
== 'V' || c
== 'W')
7985 ip
->insn_opcode
|= regno
<< 16;
7990 ip
->insn_opcode
|= regno
<< 11;
7994 ip
->insn_opcode
|= regno
<< 6;
8000 /* end-sanitize-r5900 */
8005 ip
->insn_opcode
|= lastregno
<< 11;
8008 ip
->insn_opcode
|= lastregno
<< 16;
8014 my_getExpression (&imm_expr
, s
);
8015 if (imm_expr
.X_op
!= O_big
8016 && imm_expr
.X_op
!= O_constant
)
8017 insn_error
= _("absolute expression required");
8022 my_getExpression (&offset_expr
, s
);
8023 imm_reloc
= BFD_RELOC_32
;
8035 unsigned char temp
[8];
8037 unsigned int length
;
8042 /* These only appear as the last operand in an
8043 instruction, and every instruction that accepts
8044 them in any variant accepts them in all variants.
8045 This means we don't have to worry about backing out
8046 any changes if the instruction does not match.
8048 The difference between them is the size of the
8049 floating point constant and where it goes. For 'F'
8050 and 'L' the constant is 64 bits; for 'f' and 'l' it
8051 is 32 bits. Where the constant is placed is based
8052 on how the MIPS assembler does things:
8055 f -- immediate value
8058 The .lit4 and .lit8 sections are only used if
8059 permitted by the -G argument.
8061 When generating embedded PIC code, we use the
8062 .lit8 section but not the .lit4 section (we can do
8063 .lit4 inline easily; we need to put .lit8
8064 somewhere in the data segment, and using .lit8
8065 permits the linker to eventually combine identical
8068 f64
= *args
== 'F' || *args
== 'L';
8070 save_in
= input_line_pointer
;
8071 input_line_pointer
= s
;
8072 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8074 s
= input_line_pointer
;
8075 input_line_pointer
= save_in
;
8076 if (err
!= NULL
&& *err
!= '\0')
8078 as_bad (_("Bad floating point constant: %s"), err
);
8079 memset (temp
, '\0', sizeof temp
);
8080 length
= f64
? 8 : 4;
8083 assert (length
== (f64
? 8 : 4));
8087 && (! USE_GLOBAL_POINTER_OPT
8088 || mips_pic
== EMBEDDED_PIC
8089 || g_switch_value
< 4
8090 || (temp
[0] == 0 && temp
[1] == 0)
8091 || (temp
[2] == 0 && temp
[3] == 0))))
8093 imm_expr
.X_op
= O_constant
;
8094 if (! target_big_endian
)
8095 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8097 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8100 && ((temp
[0] == 0 && temp
[1] == 0)
8101 || (temp
[2] == 0 && temp
[3] == 0))
8102 && ((temp
[4] == 0 && temp
[5] == 0)
8103 || (temp
[6] == 0 && temp
[7] == 0)))
8105 /* The value is simple enough to load with a
8106 couple of instructions. In mips1 mode, set
8107 imm_expr to the high order 32 bits and
8108 offset_expr to the low order 32 bits.
8109 Otherwise, set imm_expr to the entire 64 bit
8111 if (mips_opts
.isa
< 3)
8113 imm_expr
.X_op
= O_constant
;
8114 offset_expr
.X_op
= O_constant
;
8115 if (! target_big_endian
)
8117 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8118 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8122 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8123 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8125 if (offset_expr
.X_add_number
== 0)
8126 offset_expr
.X_op
= O_absent
;
8128 else if (sizeof (imm_expr
.X_add_number
) > 4)
8130 imm_expr
.X_op
= O_constant
;
8131 if (! target_big_endian
)
8132 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8134 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8138 imm_expr
.X_op
= O_big
;
8139 imm_expr
.X_add_number
= 4;
8140 if (! target_big_endian
)
8142 generic_bignum
[0] = bfd_getl16 (temp
);
8143 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8144 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8145 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8149 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8150 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8151 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8152 generic_bignum
[3] = bfd_getb16 (temp
);
8158 const char *newname
;
8161 /* Switch to the right section. */
8163 subseg
= now_subseg
;
8166 default: /* unused default case avoids warnings. */
8168 newname
= RDATA_SECTION_NAME
;
8169 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8173 newname
= RDATA_SECTION_NAME
;
8176 assert (!USE_GLOBAL_POINTER_OPT
8177 || g_switch_value
>= 4);
8181 new_seg
= subseg_new (newname
, (subsegT
) 0);
8182 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8183 bfd_set_section_flags (stdoutput
, new_seg
,
8188 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8189 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8190 && strcmp (TARGET_OS
, "elf") != 0)
8191 record_alignment (new_seg
, 4);
8193 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8195 as_bad (_("Can't use floating point insn in this section"));
8197 /* Set the argument to the current address in the
8199 offset_expr
.X_op
= O_symbol
;
8200 offset_expr
.X_add_symbol
=
8201 symbol_new ("L0\001", now_seg
,
8202 (valueT
) frag_now_fix (), frag_now
);
8203 offset_expr
.X_add_number
= 0;
8205 /* Put the floating point number into the section. */
8206 p
= frag_more ((int) length
);
8207 memcpy (p
, temp
, length
);
8209 /* Switch back to the original section. */
8210 subseg_set (seg
, subseg
);
8215 case 'i': /* 16 bit unsigned immediate */
8216 case 'j': /* 16 bit signed immediate */
8217 imm_reloc
= BFD_RELOC_LO16
;
8218 c
= my_getSmallExpression (&imm_expr
, s
);
8223 if (imm_expr
.X_op
== O_constant
)
8224 imm_expr
.X_add_number
=
8225 (imm_expr
.X_add_number
>> 16) & 0xffff;
8228 imm_reloc
= BFD_RELOC_HI16_S
;
8229 imm_unmatched_hi
= true;
8232 imm_reloc
= BFD_RELOC_HI16
;
8234 else if (imm_expr
.X_op
== O_constant
)
8235 imm_expr
.X_add_number
&= 0xffff;
8239 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8240 || ((imm_expr
.X_add_number
< 0
8241 || imm_expr
.X_add_number
>= 0x10000)
8242 && imm_expr
.X_op
== O_constant
))
8244 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8245 !strcmp (insn
->name
, insn
[1].name
))
8247 if (imm_expr
.X_op
!= O_constant
8248 && imm_expr
.X_op
!= O_big
)
8249 insn_error
= _("absolute expression required");
8251 as_bad (_("16 bit expression not in range 0..65535"));
8259 /* The upper bound should be 0x8000, but
8260 unfortunately the MIPS assembler accepts numbers
8261 from 0x8000 to 0xffff and sign extends them, and
8262 we want to be compatible. We only permit this
8263 extended range for an instruction which does not
8264 provide any further alternates, since those
8265 alternates may handle other cases. People should
8266 use the numbers they mean, rather than relying on
8267 a mysterious sign extension. */
8268 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8269 strcmp (insn
->name
, insn
[1].name
) == 0);
8274 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8275 || ((imm_expr
.X_add_number
< -0x8000
8276 || imm_expr
.X_add_number
>= max
)
8277 && imm_expr
.X_op
== O_constant
)
8279 && imm_expr
.X_add_number
< 0
8280 && mips_opts
.isa
>= 3
8281 && imm_expr
.X_unsigned
8282 && sizeof (imm_expr
.X_add_number
) <= 4))
8286 if (imm_expr
.X_op
!= O_constant
8287 && imm_expr
.X_op
!= O_big
)
8288 insn_error
= _("absolute expression required");
8290 as_bad (_("16 bit expression not in range -32768..32767"));
8296 case 'o': /* 16 bit offset */
8297 c
= my_getSmallExpression (&offset_expr
, s
);
8299 /* If this value won't fit into a 16 bit offset, then go
8300 find a macro that will generate the 32 bit offset
8301 code pattern. As a special hack, we accept the
8302 difference of two local symbols as a constant. This
8303 is required to suppose embedded PIC switches, which
8304 use an instruction which looks like
8305 lw $4,$L12-$LS12($4)
8306 The problem with handling this in a more general
8307 fashion is that the macro function doesn't expect to
8308 see anything which can be handled in a single
8309 constant instruction. */
8311 && (offset_expr
.X_op
!= O_constant
8312 || offset_expr
.X_add_number
>= 0x8000
8313 || offset_expr
.X_add_number
< -0x8000)
8314 && (mips_pic
!= EMBEDDED_PIC
8315 || offset_expr
.X_op
!= O_subtract
8316 || now_seg
!= text_section
8317 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
8321 offset_reloc
= BFD_RELOC_LO16
;
8322 if (c
== 'h' || c
== 'H')
8324 assert (offset_expr
.X_op
== O_constant
);
8325 offset_expr
.X_add_number
=
8326 (offset_expr
.X_add_number
>> 16) & 0xffff;
8331 case 'p': /* pc relative offset */
8332 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8333 my_getExpression (&offset_expr
, s
);
8337 case 'u': /* upper 16 bits */
8338 c
= my_getSmallExpression (&imm_expr
, s
);
8339 imm_reloc
= BFD_RELOC_LO16
;
8344 if (imm_expr
.X_op
== O_constant
)
8345 imm_expr
.X_add_number
=
8346 (imm_expr
.X_add_number
>> 16) & 0xffff;
8349 imm_reloc
= BFD_RELOC_HI16_S
;
8350 imm_unmatched_hi
= true;
8353 imm_reloc
= BFD_RELOC_HI16
;
8355 else if (imm_expr
.X_op
== O_constant
)
8356 imm_expr
.X_add_number
&= 0xffff;
8358 if (imm_expr
.X_op
== O_constant
8359 && (imm_expr
.X_add_number
< 0
8360 || imm_expr
.X_add_number
>= 0x10000))
8361 as_bad (_("lui expression not in range 0..65535"));
8365 case 'a': /* 26 bit address */
8366 my_getExpression (&offset_expr
, s
);
8368 offset_reloc
= BFD_RELOC_MIPS_JMP
;
8371 case 'N': /* 3 bit branch condition code */
8372 case 'M': /* 3 bit compare condition code */
8373 if (strncmp (s
, "$fcc", 4) != 0)
8383 while (isdigit (*s
));
8385 as_bad (_("invalid condition code register $fcc%d"), regno
);
8387 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8389 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8392 /* start-sanitize-cygnus */
8393 case 'e': /* must be at least one digit */
8394 my_getExpression (&imm_expr
, s
);
8395 check_absolute_expr (ip
, &imm_expr
);
8396 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
8398 as_bad (_("bad byte vector index (%ld)"),
8399 (long) imm_expr
.X_add_number
);
8400 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8402 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8403 imm_expr
.X_op
= O_absent
;
8408 my_getExpression (&imm_expr
, s
);
8409 check_absolute_expr (ip
, &imm_expr
);
8410 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
8412 as_bad (_("bad byte vector index (%ld)"),
8413 (long) imm_expr
.X_add_number
);
8414 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8416 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
8417 imm_expr
.X_op
= O_absent
;
8421 /* end-sanitize-cygnus */
8423 as_bad (_("bad char = '%c'\n"), *args
);
8428 /* Args don't match. */
8429 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8430 !strcmp (insn
->name
, insn
[1].name
))
8436 insn_error
= _("illegal operands");
8441 /* This routine assembles an instruction into its binary format when
8442 assembling for the mips16. As a side effect, it sets one of the
8443 global variables imm_reloc or offset_reloc to the type of
8444 relocation to do if one of the operands is an address expression.
8445 It also sets mips16_small and mips16_ext if the user explicitly
8446 requested a small or extended instruction. */
8451 struct mips_cl_insn
*ip
;
8455 struct mips_opcode
*insn
;
8458 unsigned int lastregno
= 0;
8463 mips16_small
= false;
8466 for (s
= str
; islower (*s
); ++s
)
8478 if (s
[1] == 't' && s
[2] == ' ')
8481 mips16_small
= true;
8485 else if (s
[1] == 'e' && s
[2] == ' ')
8494 insn_error
= _("unknown opcode");
8498 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8499 mips16_small
= true;
8501 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8503 insn_error
= _("unrecognized opcode");
8510 assert (strcmp (insn
->name
, str
) == 0);
8513 ip
->insn_opcode
= insn
->match
;
8514 ip
->use_extend
= false;
8515 imm_expr
.X_op
= O_absent
;
8516 imm_reloc
= BFD_RELOC_UNUSED
;
8517 offset_expr
.X_op
= O_absent
;
8518 offset_reloc
= BFD_RELOC_UNUSED
;
8519 for (args
= insn
->args
; 1; ++args
)
8526 /* In this switch statement we call break if we did not find
8527 a match, continue if we did find a match, or return if we
8536 /* Stuff the immediate value in now, if we can. */
8537 if (imm_expr
.X_op
== O_constant
8538 && imm_reloc
> BFD_RELOC_UNUSED
8539 && insn
->pinfo
!= INSN_MACRO
)
8541 mips16_immed ((char *) NULL
, 0,
8542 imm_reloc
- BFD_RELOC_UNUSED
,
8543 imm_expr
.X_add_number
, true, mips16_small
,
8544 mips16_ext
, &ip
->insn_opcode
,
8545 &ip
->use_extend
, &ip
->extend
);
8546 imm_expr
.X_op
= O_absent
;
8547 imm_reloc
= BFD_RELOC_UNUSED
;
8561 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8564 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8580 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8582 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8609 while (isdigit (*s
));
8612 as_bad (_("invalid register number (%d)"), regno
);
8618 if (s
[1] == 'f' && s
[2] == 'p')
8623 else if (s
[1] == 's' && s
[2] == 'p')
8628 else if (s
[1] == 'g' && s
[2] == 'p')
8633 else if (s
[1] == 'a' && s
[2] == 't')
8638 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8643 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8656 if (c
== 'v' || c
== 'w')
8658 regno
= mips16_to_32_reg_map
[lastregno
];
8672 regno
= mips32_to_16_reg_map
[regno
];
8677 regno
= ILLEGAL_REG
;
8682 regno
= ILLEGAL_REG
;
8687 regno
= ILLEGAL_REG
;
8692 if (regno
== AT
&& ! mips_opts
.noat
)
8693 as_warn (_("used $at without \".set noat\""));
8700 if (regno
== ILLEGAL_REG
)
8707 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8711 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8714 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8717 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8723 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8726 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8727 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8737 if (strncmp (s
, "$pc", 3) == 0)
8761 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8763 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8764 and generate the appropriate reloc. If the text
8765 inside %gprel is not a symbol name with an
8766 optional offset, then we generate a normal reloc
8767 and will probably fail later. */
8768 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8769 if (imm_expr
.X_op
== O_symbol
)
8772 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8774 ip
->use_extend
= true;
8781 /* Just pick up a normal expression. */
8782 my_getExpression (&imm_expr
, s
);
8785 if (imm_expr
.X_op
== O_register
)
8787 /* What we thought was an expression turned out to
8790 if (s
[0] == '(' && args
[1] == '(')
8792 /* It looks like the expression was omitted
8793 before a register indirection, which means
8794 that the expression is implicitly zero. We
8795 still set up imm_expr, so that we handle
8796 explicit extensions correctly. */
8797 imm_expr
.X_op
= O_constant
;
8798 imm_expr
.X_add_number
= 0;
8799 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8806 /* We need to relax this instruction. */
8807 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8816 /* We use offset_reloc rather than imm_reloc for the PC
8817 relative operands. This lets macros with both
8818 immediate and address operands work correctly. */
8819 my_getExpression (&offset_expr
, s
);
8821 if (offset_expr
.X_op
== O_register
)
8824 /* We need to relax this instruction. */
8825 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8829 case '6': /* break code */
8830 my_getExpression (&imm_expr
, s
);
8831 check_absolute_expr (ip
, &imm_expr
);
8832 if ((unsigned long) imm_expr
.X_add_number
> 63)
8834 as_warn (_("Invalid value for `%s' (%lu)"),
8836 (unsigned long) imm_expr
.X_add_number
);
8837 imm_expr
.X_add_number
&= 0x3f;
8839 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8840 imm_expr
.X_op
= O_absent
;
8844 case 'a': /* 26 bit address */
8845 my_getExpression (&offset_expr
, s
);
8847 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8848 ip
->insn_opcode
<<= 16;
8851 case 'l': /* register list for entry macro */
8852 case 'L': /* register list for exit macro */
8862 int freg
, reg1
, reg2
;
8864 while (*s
== ' ' || *s
== ',')
8868 as_bad (_("can't parse register list"));
8880 while (isdigit (*s
))
8902 as_bad (_("invalid register list"));
8907 while (isdigit (*s
))
8914 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8919 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8924 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8925 mask
|= (reg2
- 3) << 3;
8926 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8927 mask
|= (reg2
- 15) << 1;
8928 else if (reg1
== 31 && reg2
== 31)
8932 as_bad (_("invalid register list"));
8936 /* The mask is filled in in the opcode table for the
8937 benefit of the disassembler. We remove it before
8938 applying the actual mask. */
8939 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8940 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8944 case 'e': /* extend code */
8945 my_getExpression (&imm_expr
, s
);
8946 check_absolute_expr (ip
, &imm_expr
);
8947 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8949 as_warn (_("Invalid value for `%s' (%lu)"),
8951 (unsigned long) imm_expr
.X_add_number
);
8952 imm_expr
.X_add_number
&= 0x7ff;
8954 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8955 imm_expr
.X_op
= O_absent
;
8965 /* Args don't match. */
8966 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8967 strcmp (insn
->name
, insn
[1].name
) == 0)
8974 insn_error
= _("illegal operands");
8980 /* This structure holds information we know about a mips16 immediate
8983 struct mips16_immed_operand
8985 /* The type code used in the argument string in the opcode table. */
8987 /* The number of bits in the short form of the opcode. */
8989 /* The number of bits in the extended form of the opcode. */
8991 /* The amount by which the short form is shifted when it is used;
8992 for example, the sw instruction has a shift count of 2. */
8994 /* The amount by which the short form is shifted when it is stored
8995 into the instruction code. */
8997 /* Non-zero if the short form is unsigned. */
8999 /* Non-zero if the extended form is unsigned. */
9001 /* Non-zero if the value is PC relative. */
9005 /* The mips16 immediate operand types. */
9007 static const struct mips16_immed_operand mips16_immed_operands
[] =
9009 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9010 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9011 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9012 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9013 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9014 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9015 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9016 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9017 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9018 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9019 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9020 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9021 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9022 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9023 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9024 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9025 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9026 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9027 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9028 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9029 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9032 #define MIPS16_NUM_IMMED \
9033 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9035 /* Handle a mips16 instruction with an immediate value. This or's the
9036 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9037 whether an extended value is needed; if one is needed, it sets
9038 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9039 If SMALL is true, an unextended opcode was explicitly requested.
9040 If EXT is true, an extended opcode was explicitly requested. If
9041 WARN is true, warn if EXT does not match reality. */
9044 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9053 unsigned long *insn
;
9054 boolean
*use_extend
;
9055 unsigned short *extend
;
9057 register const struct mips16_immed_operand
*op
;
9058 int mintiny
, maxtiny
;
9061 op
= mips16_immed_operands
;
9062 while (op
->type
!= type
)
9065 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9070 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9073 maxtiny
= 1 << op
->nbits
;
9078 maxtiny
= (1 << op
->nbits
) - 1;
9083 mintiny
= - (1 << (op
->nbits
- 1));
9084 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9087 /* Branch offsets have an implicit 0 in the lowest bit. */
9088 if (type
== 'p' || type
== 'q')
9091 if ((val
& ((1 << op
->shift
) - 1)) != 0
9092 || val
< (mintiny
<< op
->shift
)
9093 || val
> (maxtiny
<< op
->shift
))
9098 if (warn
&& ext
&& ! needext
)
9099 as_warn_where (file
, line
, _("extended operand requested but not required"));
9100 if (small
&& needext
)
9101 as_bad_where (file
, line
, _("invalid unextended operand value"));
9103 if (small
|| (! ext
&& ! needext
))
9107 *use_extend
= false;
9108 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9109 insnval
<<= op
->op_shift
;
9114 long minext
, maxext
;
9120 maxext
= (1 << op
->extbits
) - 1;
9124 minext
= - (1 << (op
->extbits
- 1));
9125 maxext
= (1 << (op
->extbits
- 1)) - 1;
9127 if (val
< minext
|| val
> maxext
)
9128 as_bad_where (file
, line
,
9129 _("operand value out of range for instruction"));
9132 if (op
->extbits
== 16)
9134 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9137 else if (op
->extbits
== 15)
9139 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9144 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9148 *extend
= (unsigned short) extval
;
9157 my_getSmallExpression (ep
, str
)
9168 ((str
[1] == 'h' && str
[2] == 'i')
9169 || (str
[1] == 'H' && str
[2] == 'I')
9170 || (str
[1] == 'l' && str
[2] == 'o'))
9182 * A small expression may be followed by a base register.
9183 * Scan to the end of this operand, and then back over a possible
9184 * base register. Then scan the small expression up to that
9185 * point. (Based on code in sparc.c...)
9187 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
9189 if (sp
- 4 >= str
&& sp
[-1] == RP
)
9191 if (isdigit (sp
[-2]))
9193 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
9195 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
9201 else if (sp
- 5 >= str
9204 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
9205 || (sp
[-3] == 's' && sp
[-2] == 'p')
9206 || (sp
[-3] == 'g' && sp
[-2] == 'p')
9207 || (sp
[-3] == 'a' && sp
[-2] == 't')))
9213 /* no expression means zero offset */
9216 /* %xx(reg) is an error */
9217 ep
->X_op
= O_absent
;
9222 ep
->X_op
= O_constant
;
9225 ep
->X_add_symbol
= NULL
;
9226 ep
->X_op_symbol
= NULL
;
9227 ep
->X_add_number
= 0;
9232 my_getExpression (ep
, str
);
9239 my_getExpression (ep
, str
);
9240 return c
; /* => %hi or %lo encountered */
9244 my_getExpression (ep
, str
)
9250 save_in
= input_line_pointer
;
9251 input_line_pointer
= str
;
9253 expr_end
= input_line_pointer
;
9254 input_line_pointer
= save_in
;
9256 /* If we are in mips16 mode, and this is an expression based on `.',
9257 then we bump the value of the symbol by 1 since that is how other
9258 text symbols are handled. We don't bother to handle complex
9259 expressions, just `.' plus or minus a constant. */
9260 if (mips_opts
.mips16
9261 && ep
->X_op
== O_symbol
9262 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9263 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9264 && ep
->X_add_symbol
->sy_frag
== frag_now
9265 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
9266 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
9267 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
9270 /* Turn a string in input_line_pointer into a floating point constant
9271 of type type, and store the appropriate bytes in *litP. The number
9272 of LITTLENUMS emitted is stored in *sizeP . An error message is
9273 returned, or NULL on OK. */
9276 md_atof (type
, litP
, sizeP
)
9282 LITTLENUM_TYPE words
[4];
9298 return _("bad call to md_atof");
9301 t
= atof_ieee (input_line_pointer
, type
, words
);
9303 input_line_pointer
= t
;
9307 if (! target_big_endian
)
9309 for (i
= prec
- 1; i
>= 0; i
--)
9311 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9317 for (i
= 0; i
< prec
; i
++)
9319 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9328 md_number_to_chars (buf
, val
, n
)
9333 if (target_big_endian
)
9334 number_to_chars_bigendian (buf
, val
, n
);
9336 number_to_chars_littleendian (buf
, val
, n
);
9339 CONST
char *md_shortopts
= "O::g::G:";
9341 struct option md_longopts
[] = {
9342 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9343 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9344 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9345 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9346 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9347 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9348 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9349 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9350 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9351 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9352 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9353 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9354 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9355 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9356 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9357 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9358 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9359 {"break", no_argument
, NULL
, OPTION_BREAK
},
9360 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9361 #define OPTION_EB (OPTION_MD_BASE + 11)
9362 {"EB", no_argument
, NULL
, OPTION_EB
},
9363 #define OPTION_EL (OPTION_MD_BASE + 12)
9364 {"EL", no_argument
, NULL
, OPTION_EL
},
9365 #define OPTION_M4650 (OPTION_MD_BASE + 13)
9366 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9367 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
9368 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9369 #define OPTION_M4010 (OPTION_MD_BASE + 15)
9370 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9371 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
9372 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9373 #define OPTION_M4100 (OPTION_MD_BASE + 17)
9374 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9375 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
9376 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9377 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
9378 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9379 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
9380 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9381 /* start-sanitize-r5900 */
9382 #define OPTION_M5900 (OPTION_MD_BASE + 24)
9383 {"m5900", no_argument
, NULL
, OPTION_M5900
},
9384 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
9385 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
9386 /* end-sanitize-r5900 */
9387 #define OPTION_M3900 (OPTION_MD_BASE + 26)
9388 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9389 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
9390 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9392 /* start-sanitize-tx19 */
9393 {"m1900", no_argument
, NULL
, OPTION_M3900
},
9394 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
9395 /* end-sanitize-tx19 */
9397 /* start-sanitize-cygnus */
9398 #define OPTION_M5400 (OPTION_MD_BASE + 28)
9399 {"m5400", no_argument
, NULL
, OPTION_M5400
},
9400 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
9401 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
9403 /* end-sanitize-cygnus */
9404 /* start-sanitize-tx49 */
9405 #define OPTION_M4900 (OPTION_MD_BASE + 30)
9406 {"m4900", no_argument
, NULL
, OPTION_M4900
},
9407 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
9408 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
9410 /* end-sanitize-tx49 */
9411 /* start-sanitize-vr4320 */
9412 #define OPTION_M4320 (OPTION_MD_BASE + 32)
9413 {"m4320", no_argument
, NULL
, OPTION_M4320
},
9414 #define OPTION_NO_M4320 (OPTION_MD_BASE + 33)
9415 {"no-m4320", no_argument
, NULL
, OPTION_NO_M4320
},
9417 /* end-sanitize-vr4320 */
9418 /* start-sanitize-branchbug4011 */
9419 #define OPTION_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 34)
9420 {"fix-4011-branch-bug", no_argument
, NULL
, OPTION_FIX_4011_BRANCH_BUG
},
9421 #define OPTION_NO_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 35)
9422 {"no-fix-4011-branch-bug", no_argument
, NULL
, OPTION_NO_FIX_4011_BRANCH_BUG
},
9423 /* end-sanitize-branchbug4011 */
9424 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
9425 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
9426 #define OPTION_XGOT (OPTION_MD_BASE + 19)
9427 #define OPTION_32 (OPTION_MD_BASE + 20)
9428 #define OPTION_64 (OPTION_MD_BASE + 21)
9430 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9431 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9432 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9433 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9434 {"32", no_argument
, NULL
, OPTION_32
},
9435 {"64", no_argument
, NULL
, OPTION_64
},
9438 {NULL
, no_argument
, NULL
, 0}
9440 size_t md_longopts_size
= sizeof(md_longopts
);
9443 md_parse_option (c
, arg
)
9458 target_big_endian
= 1;
9462 target_big_endian
= 0;
9466 if (arg
&& arg
[1] == '0')
9476 mips_debug
= atoi (arg
);
9477 /* When the MIPS assembler sees -g or -g2, it does not do
9478 optimizations which limit full symbolic debugging. We take
9479 that to be equivalent to -O0. */
9480 if (mips_debug
== 2)
9504 /* Identify the processor type */
9506 if (strcmp (p
, "default") == 0
9507 || strcmp (p
, "DEFAULT") == 0)
9513 /* We need to cope with the various "vr" prefixes for the 4300
9515 if (*p
== 'v' || *p
== 'V')
9521 if (*p
== 'r' || *p
== 'R')
9528 if (strcmp (p
, "10000") == 0
9529 || strcmp (p
, "10k") == 0
9530 || strcmp (p
, "10K") == 0)
9532 /* start-sanitize-tx19 */
9533 else if (strcmp (p
, "1900") == 0)
9535 /* end-sanitize-tx19 */
9539 if (strcmp (p
, "2000") == 0
9540 || strcmp (p
, "2k") == 0
9541 || strcmp (p
, "2K") == 0)
9546 if (strcmp (p
, "3000") == 0
9547 || strcmp (p
, "3k") == 0
9548 || strcmp (p
, "3K") == 0)
9550 else if (strcmp (p
, "3900") == 0)
9555 if (strcmp (p
, "4000") == 0
9556 || strcmp (p
, "4k") == 0
9557 || strcmp (p
, "4K") == 0)
9559 else if (strcmp (p
, "4100") == 0)
9561 else if (strcmp (p
, "4300") == 0)
9563 /* start-sanitize-vr4320 */
9564 else if (strcmp (p
, "4320") == 0)
9566 /* end-sanitize-vr4320 */
9567 else if (strcmp (p
, "4400") == 0)
9569 else if (strcmp (p
, "4600") == 0)
9571 else if (strcmp (p
, "4650") == 0)
9573 /* start-sanitize-tx49 */
9574 else if (strcmp (p
, "4900") == 0)
9576 /* end-sanitize-tx49 */
9577 else if (strcmp (p
, "4010") == 0)
9582 if (strcmp (p
, "5000") == 0
9583 || strcmp (p
, "5k") == 0
9584 || strcmp (p
, "5K") == 0)
9586 /* start-sanitize-cygnus */
9587 else if (strcmp (p
, "5400") == 0)
9589 /* end-sanitize-cygnus */
9590 /* start-sanitize-r5900 */
9591 else if (strcmp (p
, "5900") == 0)
9593 /* end-sanitize-r5900 */
9597 if (strcmp (p
, "6000") == 0
9598 || strcmp (p
, "6k") == 0
9599 || strcmp (p
, "6K") == 0)
9604 if (strcmp (p
, "8000") == 0
9605 || strcmp (p
, "8k") == 0
9606 || strcmp (p
, "8K") == 0)
9611 if (strcmp (p
, "orion") == 0)
9617 && (mips_cpu
!= 4300
9619 /* start-sanitize-vr4320 */
9621 /* end-sanitize-vr4320 */
9622 /* start-sanitize-cygnus */
9624 /* end-sanitize-cygnus */
9625 && mips_cpu
!= 5000))
9627 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9633 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9644 case OPTION_NO_M4650
:
9652 case OPTION_NO_M4010
:
9660 case OPTION_NO_M4100
:
9664 /* start-sanitize-r5900 */
9669 case OPTION_NO_M5900
:
9672 /* end-sanitize-r5900 */
9674 /* start-sanitize-vr4320 */
9679 case OPTION_NO_M4320
:
9683 /* end-sanitize-vr4320 */
9684 /* start-sanitize-cygnus */
9689 case OPTION_NO_M5400
:
9693 /* end-sanitize-cygnus */
9698 case OPTION_NO_M3900
:
9702 /* start-sanitize-tx49 */
9707 case OPTION_NO_M4900
:
9711 /* end-sanitize-tx49 */
9713 mips_opts
.mips16
= 1;
9714 mips_no_prev_insn (false);
9717 case OPTION_NO_MIPS16
:
9718 mips_opts
.mips16
= 0;
9719 mips_no_prev_insn (false);
9722 case OPTION_MEMBEDDED_PIC
:
9723 mips_pic
= EMBEDDED_PIC
;
9724 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9726 as_bad (_("-G may not be used with embedded PIC code"));
9729 g_switch_value
= 0x7fffffff;
9732 /* When generating ELF code, we permit -KPIC and -call_shared to
9733 select SVR4_PIC, and -non_shared to select no PIC. This is
9734 intended to be compatible with Irix 5. */
9735 case OPTION_CALL_SHARED
:
9736 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9738 as_bad (_("-call_shared is supported only for ELF format"));
9741 mips_pic
= SVR4_PIC
;
9742 if (g_switch_seen
&& g_switch_value
!= 0)
9744 as_bad (_("-G may not be used with SVR4 PIC code"));
9750 case OPTION_NON_SHARED
:
9751 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9753 as_bad (_("-non_shared is supported only for ELF format"));
9759 /* The -xgot option tells the assembler to use 32 offsets when
9760 accessing the got in SVR4_PIC mode. It is for Irix
9767 if (! USE_GLOBAL_POINTER_OPT
)
9769 as_bad (_("-G is not supported for this configuration"));
9772 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9774 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9778 g_switch_value
= atoi (arg
);
9782 /* The -32 and -64 options tell the assembler to output the 32
9783 bit or the 64 bit MIPS ELF format. */
9790 const char **list
, **l
;
9792 list
= bfd_target_list ();
9793 for (l
= list
; *l
!= NULL
; l
++)
9794 if (strcmp (*l
, "elf64-bigmips") == 0
9795 || strcmp (*l
, "elf64-littlemips") == 0)
9798 as_fatal (_("No compiled in support for 64 bit object file format"));
9804 /* start-sanitize-branchbug4011 */
9805 case OPTION_FIX_4011_BRANCH_BUG
:
9806 mips_fix_4011_branch_bug
= 1;
9809 case OPTION_NO_FIX_4011_BRANCH_BUG
:
9810 mips_fix_4011_branch_bug
= 0;
9813 /* end-sanitize-branchbug4011 */
9822 md_show_usage (stream
)
9825 fprintf(stream
, _("\
9827 -membedded-pic generate embedded position independent code\n\
9828 -EB generate big endian output\n\
9829 -EL generate little endian output\n\
9830 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9831 -G NUM allow referencing objects up to NUM bytes\n\
9832 implicitly with the gp register [default 8]\n"));
9833 fprintf(stream
, _("\
9834 -mips1 generate MIPS ISA I instructions\n\
9835 -mips2 generate MIPS ISA II instructions\n\
9836 -mips3 generate MIPS ISA III instructions\n\
9837 -mips4 generate MIPS ISA IV instructions\n\
9838 -mcpu=vr4300 generate code for vr4300\n\
9839 -mcpu=vr4100 generate code for vr4100\n\
9840 -m4650 permit R4650 instructions\n\
9841 -no-m4650 do not permit R4650 instructions\n\
9842 -m4010 permit R4010 instructions\n\
9843 -no-m4010 do not permit R4010 instructions\n\
9844 -m4100 permit VR4100 instructions\n\
9845 -no-m4100 do not permit VR4100 instructions\n"));
9846 fprintf(stream
, _("\
9847 -mips16 generate mips16 instructions\n\
9848 -no-mips16 do not generate mips16 instructions\n"));
9849 fprintf(stream
, _("\
9850 -O0 remove unneeded NOPs, do not swap branches\n\
9851 -O remove unneeded NOPs and swap branches\n\
9852 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9853 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9855 fprintf(stream
, _("\
9856 -KPIC, -call_shared generate SVR4 position independent code\n\
9857 -non_shared do not generate position independent code\n\
9858 -xgot assume a 32 bit GOT\n\
9859 -32 create 32 bit object file (default)\n\
9860 -64 create 64 bit object file\n"));
9865 mips_init_after_args ()
9867 /* initialize opcodes */
9868 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9869 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9873 md_pcrel_from (fixP
)
9876 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9877 && fixP
->fx_addsy
!= (symbolS
*) NULL
9878 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9880 /* This makes a branch to an undefined symbol be a branch to the
9881 current location. */
9885 /* return the address of the delay slot */
9886 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9889 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9890 reloc for a cons. We could use the definition there, except that
9891 we want to handle 64 bit relocs specially. */
9894 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9897 unsigned int nbytes
;
9901 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9903 if (nbytes
== 8 && ! mips_64
)
9905 if (target_big_endian
)
9911 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9912 as_bad (_("Unsupported reloc size %d"), nbytes
);
9914 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9917 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9920 /* This is called before the symbol table is processed. In order to
9921 work with gcc when using mips-tfile, we must keep all local labels.
9922 However, in other cases, we want to discard them. If we were
9923 called with -g, but we didn't see any debugging information, it may
9924 mean that gcc is smuggling debugging information through to
9925 mips-tfile, in which case we must generate all local labels. */
9928 mips_frob_file_before_adjust ()
9930 #ifndef NO_ECOFF_DEBUGGING
9933 && ! ecoff_debugging_seen
)
9934 flag_keep_locals
= 1;
9938 /* Sort any unmatched HI16_S relocs so that they immediately precede
9939 the corresponding LO reloc. This is called before md_apply_fix and
9940 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9941 explicit use of the %hi modifier. */
9946 struct mips_hi_fixup
*l
;
9948 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9950 segment_info_type
*seginfo
;
9953 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9955 /* Check quickly whether the next fixup happens to be a matching
9957 if (l
->fixp
->fx_next
!= NULL
9958 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9959 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9960 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9963 /* Look through the fixups for this segment for a matching %lo.
9964 When we find one, move the %hi just in front of it. We do
9965 this in two passes. In the first pass, we try to find a
9966 unique %lo. In the second pass, we permit multiple %hi
9967 relocs for a single %lo (this is a GNU extension). */
9968 seginfo
= seg_info (l
->seg
);
9969 for (pass
= 0; pass
< 2; pass
++)
9974 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9976 /* Check whether this is a %lo fixup which matches l->fixp. */
9977 if (f
->fx_r_type
== BFD_RELOC_LO16
9978 && f
->fx_addsy
== l
->fixp
->fx_addsy
9979 && f
->fx_offset
== l
->fixp
->fx_offset
9982 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9983 || prev
->fx_addsy
!= f
->fx_addsy
9984 || prev
->fx_offset
!= f
->fx_offset
))
9988 /* Move l->fixp before f. */
9989 for (pf
= &seginfo
->fix_root
;
9991 pf
= &(*pf
)->fx_next
)
9992 assert (*pf
!= NULL
);
9994 *pf
= l
->fixp
->fx_next
;
9996 l
->fixp
->fx_next
= f
;
9998 seginfo
->fix_root
= l
->fixp
;
10000 prev
->fx_next
= l
->fixp
;
10012 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10013 _("Unmatched %%hi reloc"));
10018 /* When generating embedded PIC code we need to use a special
10019 relocation to represent the difference of two symbols in the .text
10020 section (switch tables use a difference of this sort). See
10021 include/coff/mips.h for details. This macro checks whether this
10022 fixup requires the special reloc. */
10023 #define SWITCH_TABLE(fixp) \
10024 ((fixp)->fx_r_type == BFD_RELOC_32 \
10025 && (fixp)->fx_addsy != NULL \
10026 && (fixp)->fx_subsy != NULL \
10027 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10028 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10030 /* When generating embedded PIC code we must keep all PC relative
10031 relocations, in case the linker has to relax a call. We also need
10032 to keep relocations for switch table entries. */
10036 mips_force_relocation (fixp
)
10039 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10040 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10043 return (mips_pic
== EMBEDDED_PIC
10045 || SWITCH_TABLE (fixp
)
10046 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10047 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10050 /* Apply a fixup to the object file. */
10053 md_apply_fix (fixP
, valueP
)
10057 unsigned char *buf
;
10060 assert (fixP
->fx_size
== 4
10061 || fixP
->fx_r_type
== BFD_RELOC_16
10062 || fixP
->fx_r_type
== BFD_RELOC_64
10063 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10064 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10068 /* If we aren't adjusting this fixup to be against the section
10069 symbol, we need to adjust the value. */
10071 if (fixP
->fx_addsy
!= NULL
10072 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
10073 && (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10074 || S_IS_WEAK (fixP
->fx_addsy
)))
10076 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10077 if (value
!= 0 && ! fixP
->fx_pcrel
)
10079 /* In this case, the bfd_install_relocation routine will
10080 incorrectly add the symbol value back in. We just want
10081 the addend to appear in the object file. */
10082 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10087 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
10089 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10092 switch (fixP
->fx_r_type
)
10094 case BFD_RELOC_MIPS_JMP
:
10095 case BFD_RELOC_HI16
:
10096 case BFD_RELOC_HI16_S
:
10097 case BFD_RELOC_MIPS_GPREL
:
10098 case BFD_RELOC_MIPS_LITERAL
:
10099 case BFD_RELOC_MIPS_CALL16
:
10100 case BFD_RELOC_MIPS_GOT16
:
10101 case BFD_RELOC_MIPS_GPREL32
:
10102 case BFD_RELOC_MIPS_GOT_HI16
:
10103 case BFD_RELOC_MIPS_GOT_LO16
:
10104 case BFD_RELOC_MIPS_CALL_HI16
:
10105 case BFD_RELOC_MIPS_CALL_LO16
:
10106 case BFD_RELOC_MIPS16_GPREL
:
10107 /* start-sanitize-r5900 */
10108 case BFD_RELOC_MIPS15_S3
:
10109 /* end-sanitize-r5900 */
10110 if (fixP
->fx_pcrel
)
10111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10112 _("Invalid PC relative reloc"));
10113 /* Nothing needed to do. The value comes from the reloc entry */
10116 case BFD_RELOC_MIPS16_JMP
:
10117 /* We currently always generate a reloc against a symbol, which
10118 means that we don't want an addend even if the symbol is
10120 fixP
->fx_addnumber
= 0;
10123 case BFD_RELOC_PCREL_HI16_S
:
10124 /* The addend for this is tricky if it is internal, so we just
10125 do everything here rather than in bfd_install_relocation. */
10126 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
10128 /* For an external symbol adjust by the address to make it
10129 pcrel_offset. We use the address of the RELLO reloc
10130 which follows this one. */
10131 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10132 + fixP
->fx_next
->fx_where
);
10134 if (value
& 0x8000)
10137 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10138 if (target_big_endian
)
10140 md_number_to_chars (buf
, value
, 2);
10143 case BFD_RELOC_PCREL_LO16
:
10144 /* The addend for this is tricky if it is internal, so we just
10145 do everything here rather than in bfd_install_relocation. */
10146 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
10147 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10148 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10149 if (target_big_endian
)
10151 md_number_to_chars (buf
, value
, 2);
10155 /* This is handled like BFD_RELOC_32, but we output a sign
10156 extended value if we are only 32 bits. */
10158 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10160 if (8 <= sizeof (valueT
))
10161 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10168 w1
= w2
= fixP
->fx_where
;
10169 if (target_big_endian
)
10173 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10174 if ((value
& 0x80000000) != 0)
10178 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10184 /* If we are deleting this reloc entry, we must fill in the
10185 value now. This can happen if we have a .word which is not
10186 resolved when it appears but is later defined. We also need
10187 to fill in the value if this is an embedded PIC switch table
10190 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10191 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10196 /* If we are deleting this reloc entry, we must fill in the
10198 assert (fixP
->fx_size
== 2);
10200 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10204 case BFD_RELOC_LO16
:
10205 /* When handling an embedded PIC switch statement, we can wind
10206 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10209 if (value
< -0x8000 || value
> 0x7fff)
10210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10211 _("relocation overflow"));
10212 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10213 if (target_big_endian
)
10215 md_number_to_chars (buf
, value
, 2);
10219 case BFD_RELOC_16_PCREL_S2
:
10221 * We need to save the bits in the instruction since fixup_segment()
10222 * might be deleting the relocation entry (i.e., a branch within
10223 * the current segment).
10225 if ((value
& 0x3) != 0)
10226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10227 _("Branch to odd address (%lx)"), value
);
10230 /* update old instruction data */
10231 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10232 if (target_big_endian
)
10233 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10235 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10237 if (value
>= -0x8000 && value
< 0x8000)
10238 insn
|= value
& 0xffff;
10241 /* The branch offset is too large. If this is an
10242 unconditional branch, and we are not generating PIC code,
10243 we can convert it to an absolute jump instruction. */
10244 if (mips_pic
== NO_PIC
10246 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10247 && (fixP
->fx_frag
->fr_address
10248 < text_section
->vma
+ text_section
->_raw_size
)
10249 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10250 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10251 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10253 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10254 insn
= 0x0c000000; /* jal */
10256 insn
= 0x08000000; /* j */
10257 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10259 fixP
->fx_addsy
= section_symbol (text_section
);
10260 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10264 /* FIXME. It would be possible in principle to handle
10265 conditional branches which overflow. They could be
10266 transformed into a branch around a jump. This would
10267 require setting up variant frags for each different
10268 branch type. The native MIPS assembler attempts to
10269 handle these cases, but it appears to do it
10271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10272 _("Branch out of range"));
10276 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10279 case BFD_RELOC_VTABLE_INHERIT
:
10282 && !S_IS_DEFINED (fixP
->fx_addsy
)
10283 && !S_IS_WEAK (fixP
->fx_addsy
))
10284 S_SET_WEAK (fixP
->fx_addsy
);
10287 case BFD_RELOC_VTABLE_ENTRY
:
10303 const struct mips_opcode
*p
;
10304 int treg
, sreg
, dreg
, shamt
;
10309 for (i
= 0; i
< NUMOPCODES
; ++i
)
10311 p
= &mips_opcodes
[i
];
10312 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10314 printf ("%08lx %s\t", oc
, p
->name
);
10315 treg
= (oc
>> 16) & 0x1f;
10316 sreg
= (oc
>> 21) & 0x1f;
10317 dreg
= (oc
>> 11) & 0x1f;
10318 shamt
= (oc
>> 6) & 0x1f;
10320 for (args
= p
->args
;; ++args
)
10331 printf ("%c", *args
);
10335 assert (treg
== sreg
);
10336 printf ("$%d,$%d", treg
, sreg
);
10341 printf ("$%d", dreg
);
10346 printf ("$%d", treg
);
10350 printf ("0x%x", treg
);
10355 printf ("$%d", sreg
);
10359 printf ("0x%08lx", oc
& 0x1ffffff);
10366 printf ("%d", imm
);
10371 printf ("$%d", shamt
);
10382 printf (_("%08lx UNDEFINED\n"), oc
);
10393 name
= input_line_pointer
;
10394 c
= get_symbol_end ();
10395 p
= (symbolS
*) symbol_find_or_make (name
);
10396 *input_line_pointer
= c
;
10400 /* Align the current frag to a given power of two. The MIPS assembler
10401 also automatically adjusts any preceding label. */
10404 mips_align (to
, fill
, label
)
10409 mips_emit_delays (false);
10410 frag_align (to
, fill
, 0);
10411 record_alignment (now_seg
, to
);
10414 assert (S_GET_SEGMENT (label
) == now_seg
);
10415 label
->sy_frag
= frag_now
;
10416 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10420 /* Align to a given power of two. .align 0 turns off the automatic
10421 alignment used by the data creating pseudo-ops. */
10428 register long temp_fill
;
10429 long max_alignment
= 15;
10433 o Note that the assembler pulls down any immediately preceeding label
10434 to the aligned address.
10435 o It's not documented but auto alignment is reinstated by
10436 a .align pseudo instruction.
10437 o Note also that after auto alignment is turned off the mips assembler
10438 issues an error on attempt to assemble an improperly aligned data item.
10443 temp
= get_absolute_expression ();
10444 if (temp
> max_alignment
)
10445 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10448 as_warn (_("Alignment negative: 0 assumed."));
10451 if (*input_line_pointer
== ',')
10453 input_line_pointer
++;
10454 temp_fill
= get_absolute_expression ();
10461 mips_align (temp
, (int) temp_fill
,
10462 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10469 demand_empty_rest_of_line ();
10473 mips_flush_pending_output ()
10475 mips_emit_delays (false);
10476 mips_clear_insn_labels ();
10485 /* When generating embedded PIC code, we only use the .text, .lit8,
10486 .sdata and .sbss sections. We change the .data and .rdata
10487 pseudo-ops to use .sdata. */
10488 if (mips_pic
== EMBEDDED_PIC
10489 && (sec
== 'd' || sec
== 'r'))
10493 /* The ELF backend needs to know that we are changing sections, so
10494 that .previous works correctly. We could do something like check
10495 for a obj_section_change_hook macro, but that might be confusing
10496 as it would not be appropriate to use it in the section changing
10497 functions in read.c, since obj-elf.c intercepts those. FIXME:
10498 This should be cleaner, somehow. */
10499 obj_elf_section_change_hook ();
10502 mips_emit_delays (false);
10512 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10513 demand_empty_rest_of_line ();
10517 if (USE_GLOBAL_POINTER_OPT
)
10519 seg
= subseg_new (RDATA_SECTION_NAME
,
10520 (subsegT
) get_absolute_expression ());
10521 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10523 bfd_set_section_flags (stdoutput
, seg
,
10529 if (strcmp (TARGET_OS
, "elf") != 0)
10530 bfd_set_section_alignment (stdoutput
, seg
, 4);
10532 demand_empty_rest_of_line ();
10536 as_bad (_("No read only data section in this object file format"));
10537 demand_empty_rest_of_line ();
10543 if (USE_GLOBAL_POINTER_OPT
)
10545 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10546 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10548 bfd_set_section_flags (stdoutput
, seg
,
10549 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10551 if (strcmp (TARGET_OS
, "elf") != 0)
10552 bfd_set_section_alignment (stdoutput
, seg
, 4);
10554 demand_empty_rest_of_line ();
10559 as_bad (_("Global pointers not supported; recompile -G 0"));
10560 demand_empty_rest_of_line ();
10569 mips_enable_auto_align ()
10580 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10581 mips_emit_delays (false);
10582 if (log_size
> 0 && auto_align
)
10583 mips_align (log_size
, 0, label
);
10584 mips_clear_insn_labels ();
10585 cons (1 << log_size
);
10589 s_float_cons (type
)
10594 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10596 mips_emit_delays (false);
10600 mips_align (3, 0, label
);
10602 mips_align (2, 0, label
);
10604 mips_clear_insn_labels ();
10609 /* Handle .globl. We need to override it because on Irix 5 you are
10612 where foo is an undefined symbol, to mean that foo should be
10613 considered to be the address of a function. */
10624 name
= input_line_pointer
;
10625 c
= get_symbol_end ();
10626 symbolP
= symbol_find_or_make (name
);
10627 *input_line_pointer
= c
;
10628 SKIP_WHITESPACE ();
10630 /* On Irix 5, every global symbol that is not explicitly labelled as
10631 being a function is apparently labelled as being an object. */
10634 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10639 secname
= input_line_pointer
;
10640 c
= get_symbol_end ();
10641 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10643 as_bad (_("%s: no such section"), secname
);
10644 *input_line_pointer
= c
;
10646 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10647 flag
= BSF_FUNCTION
;
10650 symbolP
->bsym
->flags
|= flag
;
10652 S_SET_EXTERNAL (symbolP
);
10653 demand_empty_rest_of_line ();
10663 opt
= input_line_pointer
;
10664 c
= get_symbol_end ();
10668 /* FIXME: What does this mean? */
10670 else if (strncmp (opt
, "pic", 3) == 0)
10674 i
= atoi (opt
+ 3);
10678 mips_pic
= SVR4_PIC
;
10680 as_bad (_(".option pic%d not supported"), i
);
10682 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10684 if (g_switch_seen
&& g_switch_value
!= 0)
10685 as_warn (_("-G may not be used with SVR4 PIC code"));
10686 g_switch_value
= 0;
10687 bfd_set_gp_size (stdoutput
, 0);
10691 as_warn (_("Unrecognized option \"%s\""), opt
);
10693 *input_line_pointer
= c
;
10694 demand_empty_rest_of_line ();
10697 /* This structure is used to hold a stack of .set values. */
10699 struct mips_option_stack
10701 struct mips_option_stack
*next
;
10702 struct mips_set_options options
;
10705 static struct mips_option_stack
*mips_opts_stack
;
10707 /* Handle the .set pseudo-op. */
10713 char *name
= input_line_pointer
, ch
;
10715 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10716 input_line_pointer
++;
10717 ch
= *input_line_pointer
;
10718 *input_line_pointer
= '\0';
10720 if (strcmp (name
, "reorder") == 0)
10722 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10724 /* If we still have pending nops, we can discard them. The
10725 usual nop handling will insert any that are still
10727 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10728 * (mips_opts
.mips16
? 2 : 4));
10729 prev_nop_frag
= NULL
;
10731 mips_opts
.noreorder
= 0;
10733 else if (strcmp (name
, "noreorder") == 0)
10735 mips_emit_delays (true);
10736 mips_opts
.noreorder
= 1;
10737 mips_any_noreorder
= 1;
10739 else if (strcmp (name
, "at") == 0)
10741 mips_opts
.noat
= 0;
10743 else if (strcmp (name
, "noat") == 0)
10745 mips_opts
.noat
= 1;
10747 else if (strcmp (name
, "macro") == 0)
10749 mips_opts
.warn_about_macros
= 0;
10751 else if (strcmp (name
, "nomacro") == 0)
10753 if (mips_opts
.noreorder
== 0)
10754 as_bad (_("`noreorder' must be set before `nomacro'"));
10755 mips_opts
.warn_about_macros
= 1;
10757 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10759 mips_opts
.nomove
= 0;
10761 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10763 mips_opts
.nomove
= 1;
10765 else if (strcmp (name
, "bopt") == 0)
10767 mips_opts
.nobopt
= 0;
10769 else if (strcmp (name
, "nobopt") == 0)
10771 mips_opts
.nobopt
= 1;
10773 else if (strcmp (name
, "mips16") == 0
10774 || strcmp (name
, "MIPS-16") == 0)
10775 mips_opts
.mips16
= 1;
10776 else if (strcmp (name
, "nomips16") == 0
10777 || strcmp (name
, "noMIPS-16") == 0)
10778 mips_opts
.mips16
= 0;
10779 else if (strncmp (name
, "mips", 4) == 0)
10783 /* Permit the user to change the ISA on the fly. Needless to
10784 say, misuse can cause serious problems. */
10785 isa
= atoi (name
+ 4);
10787 mips_opts
.isa
= file_mips_isa
;
10788 else if (isa
< 1 || isa
> 4)
10789 as_bad (_("unknown ISA level"));
10791 mips_opts
.isa
= isa
;
10793 else if (strcmp (name
, "autoextend") == 0)
10794 mips_opts
.noautoextend
= 0;
10795 else if (strcmp (name
, "noautoextend") == 0)
10796 mips_opts
.noautoextend
= 1;
10797 else if (strcmp (name
, "push") == 0)
10799 struct mips_option_stack
*s
;
10801 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10802 s
->next
= mips_opts_stack
;
10803 s
->options
= mips_opts
;
10804 mips_opts_stack
= s
;
10806 else if (strcmp (name
, "pop") == 0)
10808 struct mips_option_stack
*s
;
10810 s
= mips_opts_stack
;
10812 as_bad (_(".set pop with no .set push"));
10815 /* If we're changing the reorder mode we need to handle
10816 delay slots correctly. */
10817 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10818 mips_emit_delays (true);
10819 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10821 if (prev_nop_frag
!= NULL
)
10823 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10824 * (mips_opts
.mips16
? 2 : 4));
10825 prev_nop_frag
= NULL
;
10829 mips_opts
= s
->options
;
10830 mips_opts_stack
= s
->next
;
10836 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10838 *input_line_pointer
= ch
;
10839 demand_empty_rest_of_line ();
10842 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10843 .option pic2. It means to generate SVR4 PIC calls. */
10846 s_abicalls (ignore
)
10849 mips_pic
= SVR4_PIC
;
10850 if (USE_GLOBAL_POINTER_OPT
)
10852 if (g_switch_seen
&& g_switch_value
!= 0)
10853 as_warn (_("-G may not be used with SVR4 PIC code"));
10854 g_switch_value
= 0;
10856 bfd_set_gp_size (stdoutput
, 0);
10857 demand_empty_rest_of_line ();
10860 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10861 PIC code. It sets the $gp register for the function based on the
10862 function address, which is in the register named in the argument.
10863 This uses a relocation against _gp_disp, which is handled specially
10864 by the linker. The result is:
10865 lui $gp,%hi(_gp_disp)
10866 addiu $gp,$gp,%lo(_gp_disp)
10867 addu $gp,$gp,.cpload argument
10868 The .cpload argument is normally $25 == $t9. */
10877 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10878 if (mips_pic
!= SVR4_PIC
)
10884 /* .cpload should be a in .set noreorder section. */
10885 if (mips_opts
.noreorder
== 0)
10886 as_warn (_(".cpload not in noreorder section"));
10888 ex
.X_op
= O_symbol
;
10889 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10890 ex
.X_op_symbol
= NULL
;
10891 ex
.X_add_number
= 0;
10893 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10894 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10896 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10897 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10898 (int) BFD_RELOC_LO16
);
10900 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10901 GP
, GP
, tc_get_register (0));
10903 demand_empty_rest_of_line ();
10906 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10907 offset from $sp. The offset is remembered, and after making a PIC
10908 call $gp is restored from that location. */
10911 s_cprestore (ignore
)
10917 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10918 if (mips_pic
!= SVR4_PIC
)
10924 mips_cprestore_offset
= get_absolute_expression ();
10926 ex
.X_op
= O_constant
;
10927 ex
.X_add_symbol
= NULL
;
10928 ex
.X_op_symbol
= NULL
;
10929 ex
.X_add_number
= mips_cprestore_offset
;
10931 macro_build ((char *) NULL
, &icnt
, &ex
,
10932 ((bfd_arch_bits_per_address (stdoutput
) == 32
10933 || mips_opts
.isa
< 3)
10935 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10937 demand_empty_rest_of_line ();
10940 /* Handle the .gpword pseudo-op. This is used when generating PIC
10941 code. It generates a 32 bit GP relative reloc. */
10951 /* When not generating PIC code, this is treated as .word. */
10952 if (mips_pic
!= SVR4_PIC
)
10958 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10959 mips_emit_delays (true);
10961 mips_align (2, 0, label
);
10962 mips_clear_insn_labels ();
10966 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10968 as_bad (_("Unsupported use of .gpword"));
10969 ignore_rest_of_line ();
10973 md_number_to_chars (p
, (valueT
) 0, 4);
10974 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10975 BFD_RELOC_MIPS_GPREL32
);
10977 demand_empty_rest_of_line ();
10980 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10981 tables in SVR4 PIC code. */
10990 /* This is ignored when not generating SVR4 PIC code. */
10991 if (mips_pic
!= SVR4_PIC
)
10997 /* Add $gp to the register named as an argument. */
10998 reg
= tc_get_register (0);
10999 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11000 ((bfd_arch_bits_per_address (stdoutput
) == 32
11001 || mips_opts
.isa
< 3)
11002 ? "addu" : "daddu"),
11003 "d,v,t", reg
, reg
, GP
);
11005 demand_empty_rest_of_line ();
11008 /* Handle the .insn pseudo-op. This marks instruction labels in
11009 mips16 mode. This permits the linker to handle them specially,
11010 such as generating jalx instructions when needed. We also make
11011 them odd for the duration of the assembly, in order to generate the
11012 right sort of code. We will make them even in the adjust_symtab
11013 routine, while leaving them marked. This is convenient for the
11014 debugger and the disassembler. The linker knows to make them odd
11021 if (mips_opts
.mips16
)
11022 mips16_mark_labels ();
11024 demand_empty_rest_of_line ();
11027 /* Handle a .stabn directive. We need these in order to mark a label
11028 as being a mips16 text label correctly. Sometimes the compiler
11029 will emit a label, followed by a .stabn, and then switch sections.
11030 If the label and .stabn are in mips16 mode, then the label is
11031 really a mips16 text label. */
11037 if (type
== 'n' && mips_opts
.mips16
)
11038 mips16_mark_labels ();
11043 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11047 s_mips_weakext (ignore
)
11055 name
= input_line_pointer
;
11056 c
= get_symbol_end ();
11057 symbolP
= symbol_find_or_make (name
);
11058 S_SET_WEAK (symbolP
);
11059 *input_line_pointer
= c
;
11061 SKIP_WHITESPACE ();
11063 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11065 if (S_IS_DEFINED (symbolP
))
11067 as_bad ("Ignoring attempt to redefine symbol `%s'.",
11068 S_GET_NAME (symbolP
));
11069 ignore_rest_of_line ();
11073 if (*input_line_pointer
== ',')
11075 ++input_line_pointer
;
11076 SKIP_WHITESPACE ();
11080 if (exp
.X_op
!= O_symbol
)
11082 as_bad ("bad .weakext directive");
11083 ignore_rest_of_line();
11086 symbolP
->sy_value
= exp
;
11089 demand_empty_rest_of_line ();
11092 /* Parse a register string into a number. Called from the ECOFF code
11093 to parse .frame. The argument is non-zero if this is the frame
11094 register, so that we can record it in mips_frame_reg. */
11097 tc_get_register (frame
)
11102 SKIP_WHITESPACE ();
11103 if (*input_line_pointer
++ != '$')
11105 as_warn (_("expected `$'"));
11108 else if (isdigit ((unsigned char) *input_line_pointer
))
11110 reg
= get_absolute_expression ();
11111 if (reg
< 0 || reg
>= 32)
11113 as_warn (_("Bad register number"));
11119 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11121 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11123 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11125 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11129 as_warn (_("Unrecognized register name"));
11132 input_line_pointer
+= 2;
11135 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11140 md_section_align (seg
, addr
)
11144 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11147 /* We don't need to align ELF sections to the full alignment.
11148 However, Irix 5 may prefer that we align them at least to a 16
11149 byte boundary. We don't bother to align the sections if we are
11150 targeted for an embedded system. */
11151 if (strcmp (TARGET_OS
, "elf") == 0)
11157 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11160 /* Utility routine, called from above as well. If called while the
11161 input file is still being read, it's only an approximation. (For
11162 example, a symbol may later become defined which appeared to be
11163 undefined earlier.) */
11166 nopic_need_relax (sym
, before_relaxing
)
11168 int before_relaxing
;
11173 if (USE_GLOBAL_POINTER_OPT
)
11175 const char *symname
;
11178 /* Find out whether this symbol can be referenced off the GP
11179 register. It can be if it is smaller than the -G size or if
11180 it is in the .sdata or .sbss section. Certain symbols can
11181 not be referenced off the GP, although it appears as though
11183 symname
= S_GET_NAME (sym
);
11184 if (symname
!= (const char *) NULL
11185 && (strcmp (symname
, "eprol") == 0
11186 || strcmp (symname
, "etext") == 0
11187 || strcmp (symname
, "_gp") == 0
11188 || strcmp (symname
, "edata") == 0
11189 || strcmp (symname
, "_fbss") == 0
11190 || strcmp (symname
, "_fdata") == 0
11191 || strcmp (symname
, "_ftext") == 0
11192 || strcmp (symname
, "end") == 0
11193 || strcmp (symname
, "_gp_disp") == 0))
11195 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11197 #ifndef NO_ECOFF_DEBUGGING
11198 || (sym
->ecoff_extern_size
!= 0
11199 && sym
->ecoff_extern_size
<= g_switch_value
)
11201 /* We must defer this decision until after the whole
11202 file has been read, since there might be a .extern
11203 after the first use of this symbol. */
11204 || (before_relaxing
11205 #ifndef NO_ECOFF_DEBUGGING
11206 && sym
->ecoff_extern_size
== 0
11208 && S_GET_VALUE (sym
) == 0)
11209 || (S_GET_VALUE (sym
) != 0
11210 && S_GET_VALUE (sym
) <= g_switch_value
)))
11214 const char *segname
;
11216 segname
= segment_name (S_GET_SEGMENT (sym
));
11217 assert (strcmp (segname
, ".lit8") != 0
11218 && strcmp (segname
, ".lit4") != 0);
11219 change
= (strcmp (segname
, ".sdata") != 0
11220 && strcmp (segname
, ".sbss") != 0);
11225 /* We are not optimizing for the GP register. */
11229 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11230 extended opcode. SEC is the section the frag is in. */
11233 mips16_extended_frag (fragp
, sec
, stretch
)
11239 register const struct mips16_immed_operand
*op
;
11241 int mintiny
, maxtiny
;
11244 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11246 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11249 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11250 op
= mips16_immed_operands
;
11251 while (op
->type
!= type
)
11254 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11259 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11262 maxtiny
= 1 << op
->nbits
;
11267 maxtiny
= (1 << op
->nbits
) - 1;
11272 mintiny
= - (1 << (op
->nbits
- 1));
11273 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11276 /* We can't call S_GET_VALUE here, because we don't want to lock in
11277 a particular frag address. */
11278 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
11280 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
11281 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11282 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11284 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
11285 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
11288 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
11289 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
11290 + fragp
->fr_symbol
->sy_value
.X_add_number
11291 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11292 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
11301 /* We won't have the section when we are called from
11302 mips_relax_frag. However, we will always have been called
11303 from md_estimate_size_before_relax first. If this is a
11304 branch to a different section, we mark it as such. If SEC is
11305 NULL, and the frag is not marked, then it must be a branch to
11306 the same section. */
11309 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11316 fragp
->fr_subtype
=
11317 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11319 /* FIXME: We should support this, and let the linker
11320 catch branches and loads that are out of range. */
11321 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11322 _("unsupported PC relative reference to different section"));
11328 /* In this case, we know for sure that the symbol fragment is in
11329 the same section. If the fr_address of the symbol fragment
11330 is greater then the address of this fragment we want to add
11331 in STRETCH in order to get a better estimate of the address.
11332 This particularly matters because of the shift bits. */
11334 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
11338 /* Adjust stretch for any alignment frag. Note that if have
11339 been expanding the earlier code, the symbol may be
11340 defined in what appears to be an earlier frag. FIXME:
11341 This doesn't handle the fr_subtype field, which specifies
11342 a maximum number of bytes to skip when doing an
11345 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
11348 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11351 stretch
= - ((- stretch
)
11352 & ~ ((1 << (int) f
->fr_offset
) - 1));
11354 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11363 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11365 /* The base address rules are complicated. The base address of
11366 a branch is the following instruction. The base address of a
11367 PC relative load or add is the instruction itself, but if it
11368 is in a delay slot (in which case it can not be extended) use
11369 the address of the instruction whose delay slot it is in. */
11370 if (type
== 'p' || type
== 'q')
11374 /* If we are currently assuming that this frag should be
11375 extended, then, the current address is two bytes
11377 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11380 /* Ignore the low bit in the target, since it will be set
11381 for a text label. */
11382 if ((val
& 1) != 0)
11385 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11387 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11390 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11392 /* Branch offsets have an implicit 0 in the lowest bit. */
11393 if (type
== 'p' || type
== 'q')
11396 /* If any of the shifted bits are set, we must use an extended
11397 opcode. If the address depends on the size of this
11398 instruction, this can lead to a loop, so we arrange to always
11399 use an extended opcode. We only check this when we are in
11400 the main relaxation loop, when SEC is NULL. */
11401 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11403 fragp
->fr_subtype
=
11404 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11408 /* If we are about to mark a frag as extended because the value
11409 is precisely maxtiny + 1, then there is a chance of an
11410 infinite loop as in the following code:
11415 In this case when the la is extended, foo is 0x3fc bytes
11416 away, so the la can be shrunk, but then foo is 0x400 away, so
11417 the la must be extended. To avoid this loop, we mark the
11418 frag as extended if it was small, and is about to become
11419 extended with a value of maxtiny + 1. */
11420 if (val
== ((maxtiny
+ 1) << op
->shift
)
11421 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11424 fragp
->fr_subtype
=
11425 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11429 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11430 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11432 if ((val
& ((1 << op
->shift
) - 1)) != 0
11433 || val
< (mintiny
<< op
->shift
)
11434 || val
> (maxtiny
<< op
->shift
))
11440 /* Estimate the size of a frag before relaxing. Unless this is the
11441 mips16, we are not really relaxing here, and the final size is
11442 encoded in the subtype information. For the mips16, we have to
11443 decide whether we are using an extended opcode or not. */
11447 md_estimate_size_before_relax (fragp
, segtype
)
11453 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11455 if (mips16_extended_frag (fragp
, segtype
, 0))
11457 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11462 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11467 if (mips_pic
== NO_PIC
)
11469 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11471 else if (mips_pic
== SVR4_PIC
)
11476 sym
= fragp
->fr_symbol
;
11478 /* Handle the case of a symbol equated to another symbol. */
11479 while (sym
->sy_value
.X_op
== O_symbol
11480 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11484 /* It's possible to get a loop here in a badly written
11486 n
= sym
->sy_value
.X_add_symbol
;
11492 symsec
= S_GET_SEGMENT (sym
);
11494 /* This must duplicate the test in adjust_reloc_syms. */
11495 change
= (symsec
!= &bfd_und_section
11496 && symsec
!= &bfd_abs_section
11497 && ! bfd_is_com_section (symsec
));
11504 /* Record the offset to the first reloc in the fr_opcode field.
11505 This lets md_convert_frag and tc_gen_reloc know that the code
11506 must be expanded. */
11507 fragp
->fr_opcode
= (fragp
->fr_literal
11509 - RELAX_OLD (fragp
->fr_subtype
)
11510 + RELAX_RELOC1 (fragp
->fr_subtype
));
11511 /* FIXME: This really needs as_warn_where. */
11512 if (RELAX_WARN (fragp
->fr_subtype
))
11513 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11519 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11522 /* This is called to see whether a reloc against a defined symbol
11523 should be converted into a reloc against a section. Don't adjust
11524 MIPS16 jump relocations, so we don't have to worry about the format
11525 of the offset in the .o file. Don't adjust relocations against
11526 mips16 symbols, so that the linker can find them if it needs to set
11530 mips_fix_adjustable (fixp
)
11533 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11535 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11536 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11538 if (fixp
->fx_addsy
== NULL
)
11541 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11542 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11543 && fixp
->fx_subsy
== NULL
)
11549 /* Translate internal representation of relocation info to BFD target
11553 tc_gen_reloc (section
, fixp
)
11557 static arelent
*retval
[4];
11559 bfd_reloc_code_real_type code
;
11561 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11564 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11565 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11567 if (mips_pic
== EMBEDDED_PIC
11568 && SWITCH_TABLE (fixp
))
11570 /* For a switch table entry we use a special reloc. The addend
11571 is actually the difference between the reloc address and the
11573 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11574 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11575 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11576 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11578 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11580 /* We use a special addend for an internal RELLO reloc. */
11581 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11582 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11584 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11586 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11588 assert (fixp
->fx_next
!= NULL
11589 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11590 /* We use a special addend for an internal RELHI reloc. The
11591 reloc is relative to the RELLO; adjust the addend
11593 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11594 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11595 + fixp
->fx_next
->fx_where
11596 - S_GET_VALUE (fixp
->fx_subsy
));
11598 reloc
->addend
= (fixp
->fx_addnumber
11599 + fixp
->fx_next
->fx_frag
->fr_address
11600 + fixp
->fx_next
->fx_where
);
11602 else if (fixp
->fx_pcrel
== 0)
11603 reloc
->addend
= fixp
->fx_addnumber
;
11606 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11607 /* A gruesome hack which is a result of the gruesome gas reloc
11609 reloc
->addend
= reloc
->address
;
11611 reloc
->addend
= -reloc
->address
;
11614 /* If this is a variant frag, we may need to adjust the existing
11615 reloc and generate a new one. */
11616 if (fixp
->fx_frag
->fr_opcode
!= NULL
11617 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11618 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11619 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11620 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11621 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11622 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11623 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11627 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11629 /* If this is not the last reloc in this frag, then we have two
11630 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11631 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11632 the second one handle all of them. */
11633 if (fixp
->fx_next
!= NULL
11634 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11636 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11637 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11638 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11639 && (fixp
->fx_next
->fx_r_type
11640 == BFD_RELOC_MIPS_GOT_LO16
))
11641 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11642 && (fixp
->fx_next
->fx_r_type
11643 == BFD_RELOC_MIPS_CALL_LO16
)));
11648 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11649 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11650 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11652 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11653 reloc2
->address
= (reloc
->address
11654 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11655 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11656 reloc2
->addend
= fixp
->fx_addnumber
;
11657 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11658 assert (reloc2
->howto
!= NULL
);
11660 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11664 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11667 reloc3
->address
+= 4;
11670 if (mips_pic
== NO_PIC
)
11672 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11673 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11675 else if (mips_pic
== SVR4_PIC
)
11677 switch (fixp
->fx_r_type
)
11681 case BFD_RELOC_MIPS_GOT16
:
11683 case BFD_RELOC_MIPS_CALL16
:
11684 case BFD_RELOC_MIPS_GOT_LO16
:
11685 case BFD_RELOC_MIPS_CALL_LO16
:
11686 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11694 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11695 to be used in the relocation's section offset. */
11696 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11698 reloc
->address
= reloc
->addend
;
11702 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11703 fixup_segment converted a non-PC relative reloc into a PC
11704 relative reloc. In such a case, we need to convert the reloc
11706 code
= fixp
->fx_r_type
;
11707 if (fixp
->fx_pcrel
)
11712 code
= BFD_RELOC_8_PCREL
;
11715 code
= BFD_RELOC_16_PCREL
;
11718 code
= BFD_RELOC_32_PCREL
;
11721 code
= BFD_RELOC_64_PCREL
;
11723 case BFD_RELOC_8_PCREL
:
11724 case BFD_RELOC_16_PCREL
:
11725 case BFD_RELOC_32_PCREL
:
11726 case BFD_RELOC_64_PCREL
:
11727 case BFD_RELOC_16_PCREL_S2
:
11728 case BFD_RELOC_PCREL_HI16_S
:
11729 case BFD_RELOC_PCREL_LO16
:
11732 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11733 _("Cannot make %s relocation PC relative"),
11734 bfd_get_reloc_code_name (code
));
11738 /* To support a PC relative reloc when generating embedded PIC code
11739 for ECOFF, we use a Cygnus extension. We check for that here to
11740 make sure that we don't let such a reloc escape normally. */
11741 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11742 && code
== BFD_RELOC_16_PCREL_S2
11743 && mips_pic
!= EMBEDDED_PIC
)
11744 reloc
->howto
= NULL
;
11746 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11748 if (reloc
->howto
== NULL
)
11750 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11751 _("Can not represent %s relocation in this object file format"),
11752 bfd_get_reloc_code_name (code
));
11759 /* Relax a machine dependent frag. This returns the amount by which
11760 the current size of the frag should change. */
11763 mips_relax_frag (fragp
, stretch
)
11767 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11770 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11772 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11774 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11779 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11781 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11788 /* Convert a machine dependent frag. */
11791 md_convert_frag (abfd
, asec
, fragp
)
11799 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11802 register const struct mips16_immed_operand
*op
;
11803 boolean small
, ext
;
11806 unsigned long insn
;
11807 boolean use_extend
;
11808 unsigned short extend
;
11810 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11811 op
= mips16_immed_operands
;
11812 while (op
->type
!= type
)
11815 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11826 resolve_symbol_value (fragp
->fr_symbol
, 1);
11827 val
= S_GET_VALUE (fragp
->fr_symbol
);
11832 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11834 /* The rules for the base address of a PC relative reloc are
11835 complicated; see mips16_extended_frag. */
11836 if (type
== 'p' || type
== 'q')
11841 /* Ignore the low bit in the target, since it will be
11842 set for a text label. */
11843 if ((val
& 1) != 0)
11846 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11848 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11851 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11854 /* Make sure the section winds up with the alignment we have
11857 record_alignment (asec
, op
->shift
);
11861 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11862 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11863 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11864 _("extended instruction in delay slot"));
11866 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11868 if (target_big_endian
)
11869 insn
= bfd_getb16 (buf
);
11871 insn
= bfd_getl16 (buf
);
11873 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11874 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11875 small
, ext
, &insn
, &use_extend
, &extend
);
11879 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11880 fragp
->fr_fix
+= 2;
11884 md_number_to_chars (buf
, insn
, 2);
11885 fragp
->fr_fix
+= 2;
11890 if (fragp
->fr_opcode
== NULL
)
11893 old
= RELAX_OLD (fragp
->fr_subtype
);
11894 new = RELAX_NEW (fragp
->fr_subtype
);
11895 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11898 memcpy (fixptr
- old
, fixptr
, new);
11900 fragp
->fr_fix
+= new - old
;
11906 /* This function is called after the relocs have been generated.
11907 We've been storing mips16 text labels as odd. Here we convert them
11908 back to even for the convenience of the debugger. */
11911 mips_frob_file_after_relocs ()
11914 unsigned int count
, i
;
11916 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11919 syms
= bfd_get_outsymbols (stdoutput
);
11920 count
= bfd_get_symcount (stdoutput
);
11921 for (i
= 0; i
< count
; i
++, syms
++)
11923 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11924 && ((*syms
)->value
& 1) != 0)
11926 (*syms
)->value
&= ~1;
11927 /* If the symbol has an odd size, it was probably computed
11928 incorrectly, so adjust that as well. */
11929 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11930 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11937 /* This function is called whenever a label is defined. It is used
11938 when handling branch delays; if a branch has a label, we assume we
11939 can not move it. */
11942 mips_define_label (sym
)
11945 struct insn_label_list
*l
;
11947 if (free_insn_labels
== NULL
)
11948 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11951 l
= free_insn_labels
;
11952 free_insn_labels
= l
->next
;
11956 l
->next
= insn_labels
;
11960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11962 /* Some special processing for a MIPS ELF file. */
11965 mips_elf_final_processing ()
11967 /* Write out the register information. */
11972 s
.ri_gprmask
= mips_gprmask
;
11973 s
.ri_cprmask
[0] = mips_cprmask
[0];
11974 s
.ri_cprmask
[1] = mips_cprmask
[1];
11975 s
.ri_cprmask
[2] = mips_cprmask
[2];
11976 s
.ri_cprmask
[3] = mips_cprmask
[3];
11977 /* The gp_value field is set by the MIPS ELF backend. */
11979 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11980 ((Elf32_External_RegInfo
*)
11981 mips_regmask_frag
));
11985 Elf64_Internal_RegInfo s
;
11987 s
.ri_gprmask
= mips_gprmask
;
11989 s
.ri_cprmask
[0] = mips_cprmask
[0];
11990 s
.ri_cprmask
[1] = mips_cprmask
[1];
11991 s
.ri_cprmask
[2] = mips_cprmask
[2];
11992 s
.ri_cprmask
[3] = mips_cprmask
[3];
11993 /* The gp_value field is set by the MIPS ELF backend. */
11995 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11996 ((Elf64_External_RegInfo
*)
11997 mips_regmask_frag
));
12000 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12001 sort of BFD interface for this. */
12002 if (mips_any_noreorder
)
12003 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12004 if (mips_pic
!= NO_PIC
)
12005 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12008 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12010 typedef struct proc
12012 struct symbol
*isym
;
12013 unsigned long reg_mask
;
12014 unsigned long reg_offset
;
12015 unsigned long fpreg_mask
;
12016 unsigned long fpreg_offset
;
12017 unsigned long frame_offset
;
12018 unsigned long frame_reg
;
12019 unsigned long pc_reg
;
12023 static procS cur_proc
;
12024 static procS
*cur_proc_ptr
;
12025 static int numprocs
;
12035 /* check for premature end, nesting errors, etc */
12037 as_warn (_("missing `.end' at end of assembly"));
12046 if (*input_line_pointer
== '-')
12048 ++input_line_pointer
;
12051 if (!isdigit (*input_line_pointer
))
12052 as_bad (_("Expected simple number."));
12053 if (input_line_pointer
[0] == '0')
12055 if (input_line_pointer
[1] == 'x')
12057 input_line_pointer
+= 2;
12058 while (isxdigit (*input_line_pointer
))
12061 val
|= hex_value (*input_line_pointer
++);
12063 return negative
? -val
: val
;
12067 ++input_line_pointer
;
12068 while (isdigit (*input_line_pointer
))
12071 val
|= *input_line_pointer
++ - '0';
12073 return negative
? -val
: val
;
12076 if (!isdigit (*input_line_pointer
))
12078 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12079 *input_line_pointer
, *input_line_pointer
);
12080 as_warn (_("Invalid number"));
12083 while (isdigit (*input_line_pointer
))
12086 val
+= *input_line_pointer
++ - '0';
12088 return negative
? -val
: val
;
12091 /* The .file directive; just like the usual .file directive, but there
12092 is an initial number which is the ECOFF file index. */
12100 line
= get_number ();
12105 /* The .end directive. */
12114 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12117 demand_empty_rest_of_line ();
12122 #ifdef BFD_ASSEMBLER
12123 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12128 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12135 as_warn (_(".end not in text section"));
12139 as_warn (_(".end directive without a preceding .ent directive."));
12140 demand_empty_rest_of_line ();
12146 assert (S_GET_NAME (p
));
12147 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12148 as_warn (_(".end symbol does not match .ent symbol."));
12151 as_warn (_(".end directive missing or unknown symbol"));
12153 #ifdef MIPS_STABS_ELF
12155 segT saved_seg
= now_seg
;
12156 subsegT saved_subseg
= now_subseg
;
12157 fragS
*saved_frag
= frag_now
;
12163 dot
= frag_now_fix ();
12165 #ifdef md_flush_pending_output
12166 md_flush_pending_output ();
12170 subseg_set (pdr_seg
, 0);
12172 /* Write the symbol */
12173 exp
.X_op
= O_symbol
;
12174 exp
.X_add_symbol
= p
;
12175 exp
.X_add_number
= 0;
12176 emit_expr (&exp
, 4);
12178 fragp
= frag_more (7*4);
12180 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12181 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12182 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12183 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12184 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12185 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12186 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12188 subseg_set (saved_seg
, saved_subseg
);
12192 cur_proc_ptr
= NULL
;
12195 /* The .aent and .ent directives. */
12205 symbolP
= get_symbol ();
12206 if (*input_line_pointer
== ',')
12207 input_line_pointer
++;
12208 SKIP_WHITESPACE ();
12209 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
12210 number
= get_number ();
12212 #ifdef BFD_ASSEMBLER
12213 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12218 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12225 as_warn (_(".ent or .aent not in text section."));
12227 if (!aent
&& cur_proc_ptr
)
12228 as_warn (_("missing `.end'"));
12232 cur_proc_ptr
= &cur_proc
;
12233 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12235 cur_proc_ptr
->isym
= symbolP
;
12237 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
12242 demand_empty_rest_of_line ();
12245 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12246 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12247 s_mips_frame is used so that we can set the PDR information correctly.
12248 We can't use the ecoff routines because they make reference to the ecoff
12249 symbol table (in the mdebug section). */
12252 s_mips_frame (ignore
)
12255 #ifdef MIPS_STABS_ELF
12259 if (cur_proc_ptr
== (procS
*) NULL
)
12261 as_warn (_(".frame outside of .ent"));
12262 demand_empty_rest_of_line ();
12266 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12268 SKIP_WHITESPACE ();
12269 if (*input_line_pointer
++ != ','
12270 || get_absolute_expression_and_terminator (&val
) != ',')
12272 as_warn (_("Bad .frame directive"));
12273 --input_line_pointer
;
12274 demand_empty_rest_of_line ();
12278 cur_proc_ptr
->frame_offset
= val
;
12279 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12281 demand_empty_rest_of_line ();
12284 #endif /* MIPS_STABS_ELF */
12287 /* The .fmask and .mask directives. If the mdebug section is present
12288 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12289 embedded targets, s_mips_mask is used so that we can set the PDR
12290 information correctly. We can't use the ecoff routines because they
12291 make reference to the ecoff symbol table (in the mdebug section). */
12294 s_mips_mask (reg_type
)
12297 #ifdef MIPS_STABS_ELF
12300 if (cur_proc_ptr
== (procS
*) NULL
)
12302 as_warn (_(".mask/.fmask outside of .ent"));
12303 demand_empty_rest_of_line ();
12307 if (get_absolute_expression_and_terminator (&mask
) != ',')
12309 as_warn (_("Bad .mask/.fmask directive"));
12310 --input_line_pointer
;
12311 demand_empty_rest_of_line ();
12315 off
= get_absolute_expression ();
12317 if (reg_type
== 'F')
12319 cur_proc_ptr
->fpreg_mask
= mask
;
12320 cur_proc_ptr
->fpreg_offset
= off
;
12324 cur_proc_ptr
->reg_mask
= mask
;
12325 cur_proc_ptr
->reg_offset
= off
;
12328 demand_empty_rest_of_line ();
12330 s_ignore (reg_type
);
12331 #endif /* MIPS_STABS_ELF */
12334 /* The .loc directive. */
12345 assert (now_seg
== text_section
);
12347 lineno
= get_number ();
12348 addroff
= frag_now_fix ();
12350 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12351 S_SET_TYPE (symbolP
, N_SLINE
);
12352 S_SET_OTHER (symbolP
, 0);
12353 S_SET_DESC (symbolP
, lineno
);
12354 symbolP
->sy_segment
= now_seg
;