1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* Whether the 4650 instructions (mad/madu) are permitted. */
198 static int mips_4650
= -1;
200 /* Whether the 4010 instructions are permitted. */
201 static int mips_4010
= -1;
203 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
204 static int mips_4100
= -1;
206 /* start-sanitize-vr4320 */
207 /* Whether NEC vr4320 instructions are permitted. */
208 static int mips_4320
= -1;
210 /* end-sanitize-vr4320 */
211 /* start-sanitize-vr5400 */
212 /* Whether NEC vr5400 instructions are permitted. */
213 static int mips_5400
= -1;
215 /* end-sanitize-vr5400 */
216 /* start-sanitize-r5900 */
217 /* Whether Toshiba r5900 instructions are permitted. */
218 static int mips_5900
= -1;
220 /* end-sanitize-r5900 */
221 /* Whether Toshiba r3900 instructions are permitted. */
222 static int mips_3900
= -1;
224 /* start-sanitize-tx49 */
225 /* Whether Toshiba r4900 instructions are permitted. */
226 static int mips_4900
= -1;
228 /* end-sanitize-tx49 */
229 /* start-sanitize-tx19 */
230 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
231 The tx19 related options and configuration bits are handled by
233 /* end-sanitize-tx19 */
235 /* Whether the processor uses hardware interlocks to protect
236 reads from the HI and LO registers, and thus does not
237 require nops to be inserted. */
238 #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \
239 /* start-sanitize-tx49 */ \
240 || mips_cpu == 4900 || mips_4900 \
241 /* end-sanitize-tx49 */ \
242 /* start-sanitize-vr4320 */ \
243 || mips_cpu == 4320 \
244 /* end-sanitize-vr4320 */ \
245 /* start-sanitize-vr5400 */ \
246 || mips_cpu == 5400 \
247 /* end-sanitize-vr5400 */ \
250 /* Whether the processor uses hardware interlocks to protect reads
251 from the GPRs, and thus does not require nops to be inserted. */
252 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
253 /* start-sanitize-vr5400 */
254 #undef gpr_interlocks
255 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400)
256 /* end-sanitize-vr5400 */
259 /* As with other "interlocks" this is used by hardware that has FP
260 (co-processor) interlocks. */
261 /* Itbl support may require additional care here. */
262 #define cop_interlocks (mips_cpu == 4300 \
263 /* start-sanitize-vr4320 */ \
264 || mips_cpu == 4320 \
265 /* end-sanitize-vr4320 */ \
266 /* start-sanitize-vr5400 */ \
267 || mips_cpu == 5400 \
268 /* end-sanitize-vr5400 */ \
271 /* MIPS PIC level. */
275 /* Do not generate PIC code. */
278 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
279 not sure what it is supposed to do. */
282 /* Generate PIC code as in the SVR4 MIPS ABI. */
285 /* Generate PIC code without using a global offset table: the data
286 segment has a maximum size of 64K, all data references are off
287 the $gp register, and all text references are PC relative. This
288 is used on some embedded systems. */
292 static enum mips_pic_level mips_pic
;
294 /* 1 if we should generate 32 bit offsets from the GP register in
295 SVR4_PIC mode. Currently has no meaning in other modes. */
296 static int mips_big_got
;
298 /* 1 if trap instructions should used for overflow rather than break
300 static int mips_trap
;
302 /* Non-zero if any .set noreorder directives were used. */
304 static int mips_any_noreorder
;
306 /* The size of the small data section. */
307 static int g_switch_value
= 8;
308 /* Whether the -G option was used. */
309 static int g_switch_seen
= 0;
314 /* If we can determine in advance that GP optimization won't be
315 possible, we can skip the relaxation stuff that tries to produce
316 GP-relative references. This makes delay slot optimization work
319 This function can only provide a guess, but it seems to work for
320 gcc output. If it guesses wrong, the only loss should be in
321 efficiency; it shouldn't introduce any bugs.
323 I don't know if a fix is needed for the SVR4_PIC mode. I've only
324 fixed it for the non-PIC mode. KR 95/04/07 */
325 static int nopic_need_relax
PARAMS ((symbolS
*, int));
327 /* handle of the OPCODE hash table */
328 static struct hash_control
*op_hash
= NULL
;
330 /* The opcode hash table we use for the mips16. */
331 static struct hash_control
*mips16_op_hash
= NULL
;
333 /* This array holds the chars that always start a comment. If the
334 pre-processor is disabled, these aren't very useful */
335 const char comment_chars
[] = "#";
337 /* This array holds the chars that only start a comment at the beginning of
338 a line. If the line seems to have the form '# 123 filename'
339 .line and .file directives will appear in the pre-processed output */
340 /* Note that input_file.c hand checks for '#' at the beginning of the
341 first line of the input file. This is because the compiler outputs
342 #NO_APP at the beginning of its output. */
343 /* Also note that C style comments are always supported. */
344 const char line_comment_chars
[] = "#";
346 /* This array holds machine specific line separator characters. */
347 const char line_separator_chars
[] = "";
349 /* Chars that can be used to separate mant from exp in floating point nums */
350 const char EXP_CHARS
[] = "eE";
352 /* Chars that mean this number is a floating point constant */
355 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
357 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
358 changed in read.c . Ideally it shouldn't have to know about it at all,
359 but nothing is ideal around here.
362 static char *insn_error
;
364 static int auto_align
= 1;
366 /* When outputting SVR4 PIC code, the assembler needs to know the
367 offset in the stack frame from which to restore the $gp register.
368 This is set by the .cprestore pseudo-op, and saved in this
370 static offsetT mips_cprestore_offset
= -1;
372 /* This is the register which holds the stack frame, as set by the
373 .frame pseudo-op. This is needed to implement .cprestore. */
374 static int mips_frame_reg
= SP
;
376 /* To output NOP instructions correctly, we need to keep information
377 about the previous two instructions. */
379 /* Whether we are optimizing. The default value of 2 means to remove
380 unneeded NOPs and swap branch instructions when possible. A value
381 of 1 means to not swap branches. A value of 0 means to always
383 static int mips_optimize
= 2;
385 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
386 equivalent to seeing no -g option at all. */
387 static int mips_debug
= 0;
389 /* The previous instruction. */
390 static struct mips_cl_insn prev_insn
;
392 /* The instruction before prev_insn. */
393 static struct mips_cl_insn prev_prev_insn
;
395 /* If we don't want information for prev_insn or prev_prev_insn, we
396 point the insn_mo field at this dummy integer. */
397 static const struct mips_opcode dummy_opcode
= { 0 };
399 /* Non-zero if prev_insn is valid. */
400 static int prev_insn_valid
;
402 /* The frag for the previous instruction. */
403 static struct frag
*prev_insn_frag
;
405 /* The offset into prev_insn_frag for the previous instruction. */
406 static long prev_insn_where
;
408 /* The reloc type for the previous instruction, if any. */
409 static bfd_reloc_code_real_type prev_insn_reloc_type
;
411 /* The reloc for the previous instruction, if any. */
412 static fixS
*prev_insn_fixp
;
414 /* Non-zero if the previous instruction was in a delay slot. */
415 static int prev_insn_is_delay_slot
;
417 /* Non-zero if the previous instruction was in a .set noreorder. */
418 static int prev_insn_unreordered
;
420 /* Non-zero if the previous instruction uses an extend opcode (if
422 static int prev_insn_extended
;
424 /* Non-zero if the previous previous instruction was in a .set
426 static int prev_prev_insn_unreordered
;
428 /* If this is set, it points to a frag holding nop instructions which
429 were inserted before the start of a noreorder section. If those
430 nops turn out to be unnecessary, the size of the frag can be
432 static fragS
*prev_nop_frag
;
434 /* The number of nop instructions we created in prev_nop_frag. */
435 static int prev_nop_frag_holds
;
437 /* The number of nop instructions that we know we need in
439 static int prev_nop_frag_required
;
441 /* The number of instructions we've seen since prev_nop_frag. */
442 static int prev_nop_frag_since
;
444 /* For ECOFF and ELF, relocations against symbols are done in two
445 parts, with a HI relocation and a LO relocation. Each relocation
446 has only 16 bits of space to store an addend. This means that in
447 order for the linker to handle carries correctly, it must be able
448 to locate both the HI and the LO relocation. This means that the
449 relocations must appear in order in the relocation table.
451 In order to implement this, we keep track of each unmatched HI
452 relocation. We then sort them so that they immediately precede the
453 corresponding LO relocation. */
458 struct mips_hi_fixup
*next
;
461 /* The section this fixup is in. */
465 /* The list of unmatched HI relocs. */
467 static struct mips_hi_fixup
*mips_hi_fixup_list
;
469 /* Map normal MIPS register numbers to mips16 register numbers. */
471 #define X ILLEGAL_REG
472 static const int mips32_to_16_reg_map
[] =
474 X
, X
, 2, 3, 4, 5, 6, 7,
475 X
, X
, X
, X
, X
, X
, X
, X
,
476 0, 1, X
, X
, X
, X
, X
, X
,
477 X
, X
, X
, X
, X
, X
, X
, X
481 /* Map mips16 register numbers to normal MIPS register numbers. */
483 static const int mips16_to_32_reg_map
[] =
485 16, 17, 2, 3, 4, 5, 6, 7
488 /* Since the MIPS does not have multiple forms of PC relative
489 instructions, we do not have to do relaxing as is done on other
490 platforms. However, we do have to handle GP relative addressing
491 correctly, which turns out to be a similar problem.
493 Every macro that refers to a symbol can occur in (at least) two
494 forms, one with GP relative addressing and one without. For
495 example, loading a global variable into a register generally uses
496 a macro instruction like this:
498 If i can be addressed off the GP register (this is true if it is in
499 the .sbss or .sdata section, or if it is known to be smaller than
500 the -G argument) this will generate the following instruction:
502 This instruction will use a GPREL reloc. If i can not be addressed
503 off the GP register, the following instruction sequence will be used:
506 In this case the first instruction will have a HI16 reloc, and the
507 second reloc will have a LO16 reloc. Both relocs will be against
510 The issue here is that we may not know whether i is GP addressable
511 until after we see the instruction that uses it. Therefore, we
512 want to be able to choose the final instruction sequence only at
513 the end of the assembly. This is similar to the way other
514 platforms choose the size of a PC relative instruction only at the
517 When generating position independent code we do not use GP
518 addressing in quite the same way, but the issue still arises as
519 external symbols and local symbols must be handled differently.
521 We handle these issues by actually generating both possible
522 instruction sequences. The longer one is put in a frag_var with
523 type rs_machine_dependent. We encode what to do with the frag in
524 the subtype field. We encode (1) the number of existing bytes to
525 replace, (2) the number of new bytes to use, (3) the offset from
526 the start of the existing bytes to the first reloc we must generate
527 (that is, the offset is applied from the start of the existing
528 bytes after they are replaced by the new bytes, if any), (4) the
529 offset from the start of the existing bytes to the second reloc,
530 (5) whether a third reloc is needed (the third reloc is always four
531 bytes after the second reloc), and (6) whether to warn if this
532 variant is used (this is sometimes needed if .set nomacro or .set
533 noat is in effect). All these numbers are reasonably small.
535 Generating two instruction sequences must be handled carefully to
536 ensure that delay slots are handled correctly. Fortunately, there
537 are a limited number of cases. When the second instruction
538 sequence is generated, append_insn is directed to maintain the
539 existing delay slot information, so it continues to apply to any
540 code after the second instruction sequence. This means that the
541 second instruction sequence must not impose any requirements not
542 required by the first instruction sequence.
544 These variant frags are then handled in functions called by the
545 machine independent code. md_estimate_size_before_relax returns
546 the final size of the frag. md_convert_frag sets up the final form
547 of the frag. tc_gen_reloc adjust the first reloc and adds a second
549 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
553 | (((reloc1) + 64) << 9) \
554 | (((reloc2) + 64) << 2) \
555 | ((reloc3) ? (1 << 1) : 0) \
557 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
558 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
559 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
560 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
561 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
562 #define RELAX_WARN(i) ((i) & 1)
564 /* For mips16 code, we use an entirely different form of relaxation.
565 mips16 supports two versions of most instructions which take
566 immediate values: a small one which takes some small value, and a
567 larger one which takes a 16 bit value. Since branches also follow
568 this pattern, relaxing these values is required.
570 We can assemble both mips16 and normal MIPS code in a single
571 object. Therefore, we need to support this type of relaxation at
572 the same time that we support the relaxation described above. We
573 use the high bit of the subtype field to distinguish these cases.
575 The information we store for this type of relaxation is the
576 argument code found in the opcode file for this relocation, whether
577 the user explicitly requested a small or extended form, and whether
578 the relocation is in a jump or jal delay slot. That tells us the
579 size of the value, and how it should be stored. We also store
580 whether the fragment is considered to be extended or not. We also
581 store whether this is known to be a branch to a different section,
582 whether we have tried to relax this frag yet, and whether we have
583 ever extended a PC relative fragment because of a shift count. */
584 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
587 | ((small) ? 0x100 : 0) \
588 | ((ext) ? 0x200 : 0) \
589 | ((dslot) ? 0x400 : 0) \
590 | ((jal_dslot) ? 0x800 : 0))
591 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
592 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
593 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
594 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
595 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
596 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
597 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
598 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
599 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
600 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
601 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
602 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
604 /* Prototypes for static functions. */
607 #define internalError() \
608 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
610 #define internalError() as_fatal ("MIPS internal Error");
613 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
615 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
616 unsigned int reg
, enum mips_regclass
class));
617 static int reg_needs_delay
PARAMS ((int));
618 static void mips16_mark_labels
PARAMS ((void));
619 static void append_insn
PARAMS ((char *place
,
620 struct mips_cl_insn
* ip
,
622 bfd_reloc_code_real_type r
,
624 static void mips_no_prev_insn
PARAMS ((int));
625 static void mips_emit_delays
PARAMS ((boolean
));
627 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
628 const char *name
, const char *fmt
,
631 static void macro_build ();
633 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
634 const char *, const char *,
636 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
637 expressionS
* ep
, int regnum
));
638 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
639 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
641 static void load_register
PARAMS ((int *, int, expressionS
*, int));
642 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
643 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
644 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
645 #ifdef LOSING_COMPILER
646 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
648 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
649 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
650 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
651 boolean
, boolean
, unsigned long *,
652 boolean
*, unsigned short *));
653 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
654 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
655 static symbolS
*get_symbol
PARAMS ((void));
656 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
657 static void s_align
PARAMS ((int));
658 static void s_change_sec
PARAMS ((int));
659 static void s_cons
PARAMS ((int));
660 static void s_float_cons
PARAMS ((int));
661 static void s_mips_globl
PARAMS ((int));
662 static void s_option
PARAMS ((int));
663 static void s_mipsset
PARAMS ((int));
664 static void s_abicalls
PARAMS ((int));
665 static void s_cpload
PARAMS ((int));
666 static void s_cprestore
PARAMS ((int));
667 static void s_gpword
PARAMS ((int));
668 static void s_cpadd
PARAMS ((int));
669 static void s_insn
PARAMS ((int));
670 static void md_obj_begin
PARAMS ((void));
671 static void md_obj_end
PARAMS ((void));
672 static long get_number
PARAMS ((void));
673 static void s_ent
PARAMS ((int));
674 static void s_mipsend
PARAMS ((int));
675 static void s_file
PARAMS ((int));
676 static void s_mips_stab
PARAMS ((int));
677 static void s_mips_weakext
PARAMS ((int));
678 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
681 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
685 The following pseudo-ops from the Kane and Heinrich MIPS book
686 should be defined here, but are currently unsupported: .alias,
687 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
689 The following pseudo-ops from the Kane and Heinrich MIPS book are
690 specific to the type of debugging information being generated, and
691 should be defined by the object format: .aent, .begin, .bend,
692 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
695 The following pseudo-ops from the Kane and Heinrich MIPS book are
696 not MIPS CPU specific, but are also not specific to the object file
697 format. This file is probably the best place to define them, but
698 they are not currently supported: .asm0, .endr, .lab, .repeat,
701 static const pseudo_typeS mips_pseudo_table
[] =
703 /* MIPS specific pseudo-ops. */
704 {"option", s_option
, 0},
705 {"set", s_mipsset
, 0},
706 {"rdata", s_change_sec
, 'r'},
707 {"sdata", s_change_sec
, 's'},
708 {"livereg", s_ignore
, 0},
709 {"abicalls", s_abicalls
, 0},
710 {"cpload", s_cpload
, 0},
711 {"cprestore", s_cprestore
, 0},
712 {"gpword", s_gpword
, 0},
713 {"cpadd", s_cpadd
, 0},
716 /* Relatively generic pseudo-ops that happen to be used on MIPS
718 {"asciiz", stringer
, 1},
719 {"bss", s_change_sec
, 'b'},
722 {"dword", s_cons
, 3},
723 {"weakext", s_mips_weakext
, 0},
725 /* These pseudo-ops are defined in read.c, but must be overridden
726 here for one reason or another. */
727 {"align", s_align
, 0},
729 {"data", s_change_sec
, 'd'},
730 {"double", s_float_cons
, 'd'},
731 {"float", s_float_cons
, 'f'},
732 {"globl", s_mips_globl
, 0},
733 {"global", s_mips_globl
, 0},
734 {"hword", s_cons
, 1},
739 {"short", s_cons
, 1},
740 {"single", s_float_cons
, 'f'},
741 {"stabn", s_mips_stab
, 'n'},
742 {"text", s_change_sec
, 't'},
747 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
748 /* These pseudo-ops should be defined by the object file format.
749 However, a.out doesn't support them, so we have versions here. */
751 {"bgnb", s_ignore
, 0},
752 {"end", s_mipsend
, 0},
753 {"endb", s_ignore
, 0},
756 {"fmask", s_ignore
, 'F'},
757 {"frame", s_ignore
, 0},
758 {"loc", s_ignore
, 0},
759 {"mask", s_ignore
, 'R'},
760 {"verstamp", s_ignore
, 0},
764 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
769 pop_insert (mips_pseudo_table
);
770 if (! ECOFF_DEBUGGING
)
771 pop_insert (mips_nonecoff_pseudo_table
);
774 /* Symbols labelling the current insn. */
776 struct insn_label_list
778 struct insn_label_list
*next
;
782 static struct insn_label_list
*insn_labels
;
783 static struct insn_label_list
*free_insn_labels
;
785 static void mips_clear_insn_labels
PARAMS ((void));
788 mips_clear_insn_labels ()
790 register struct insn_label_list
**pl
;
792 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
798 static char *expr_end
;
800 /* Expressions which appear in instructions. These are set by
803 static expressionS imm_expr
;
804 static expressionS offset_expr
;
806 /* Relocs associated with imm_expr and offset_expr. */
808 static bfd_reloc_code_real_type imm_reloc
;
809 static bfd_reloc_code_real_type offset_reloc
;
811 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
813 static boolean imm_unmatched_hi
;
815 /* These are set by mips16_ip if an explicit extension is used. */
817 static boolean mips16_small
, mips16_ext
;
820 * This function is called once, at assembler startup time. It should
821 * set up all the tables, etc. that the MD part of the assembler will need.
827 register const char *retval
= NULL
;
828 register unsigned int i
= 0;
834 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
836 a
= xmalloc (sizeof TARGET_CPU
);
837 strcpy (a
, TARGET_CPU
);
838 a
[(sizeof TARGET_CPU
) - 3] = '\0';
844 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
845 just the generic 'mips', in which case set mips_cpu based
846 on the given ISA, if any. */
848 if (strcmp (cpu
, "mips") == 0)
850 if (mips_opts
.isa
< 0)
853 else if (mips_opts
.isa
== 2)
856 else if (mips_opts
.isa
== 3)
859 else if (mips_opts
.isa
== 4)
866 else if (strcmp (cpu
, "r3900") == 0
867 || strcmp (cpu
, "mipstx39") == 0
868 /* start-sanitize-tx19 */
869 || strcmp (cpu
, "r1900") == 0
870 || strcmp (cpu
, "mipstx19") == 0
871 /* end-sanitize-tx19 */
875 else if (strcmp (cpu
, "r6000") == 0
876 || strcmp (cpu
, "mips2") == 0)
879 else if (strcmp (cpu
, "mips64") == 0
880 || strcmp (cpu
, "r4000") == 0
881 || strcmp (cpu
, "mips3") == 0)
884 else if (strcmp (cpu
, "r4400") == 0)
887 else if (strcmp (cpu
, "mips64orion") == 0
888 || strcmp (cpu
, "r4600") == 0)
891 else if (strcmp (cpu
, "r4650") == 0)
894 else if (strcmp (cpu
, "mips64vr4300") == 0)
897 /* start-sanitize-vr4320 */
898 else if (strcmp (cpu
, "r4320") == 0
899 || strcmp (cpu
, "mips64vr4320") == 0)
902 /* end-sanitize-vr4320 */
903 else if (strcmp (cpu
, "mips64vr4100") == 0)
906 else if (strcmp (cpu
, "r4010") == 0)
909 /* start-sanitize-tx49 */
910 else if (strcmp (cpu
, "mips64tx49") == 0)
912 /* end-sanitize-tx49 */
914 else if (strcmp (cpu
, "r5000") == 0
915 || strcmp (cpu
, "mips64vr5000") == 0)
918 /* start-sanitize-vr5400 */
919 else if (strcmp (cpu
, "r5400") == 0
920 || strcmp (cpu
, "mips64vr5400") == 0)
922 /* end-sanitize-vr5400 */
924 /* start-sanitize-r5900 */
925 else if (strcmp (cpu
, "r5900") == 0
926 || strcmp (cpu
, "mips64r5900") == 0)
928 /* end-sanitize-r5900 */
930 else if (strcmp (cpu
, "r8000") == 0
931 || strcmp (cpu
, "mips4") == 0)
934 else if (strcmp (cpu
, "r10000") == 0)
937 else if (strcmp (cpu
, "mips16") == 0)
938 mips_cpu
= 0; /* FIXME */
944 if (mips_opts
.isa
== -1)
950 else if (mips_cpu
== 6000
954 else if (mips_cpu
== 4000
958 /* start-sanitize-vr4320 */
960 /* end-sanitize-vr4320 */
962 /* start-sanitize-tx49 */
964 /* end-sanitize-tx49 */
965 /* start-sanitize-r5900 */
967 /* end-sanitize-r5900 */
971 else if (mips_cpu
== 5000
972 /* start-sanitize-vr5400 */
974 /* end-sanitize-vr5400 */
976 || mips_cpu
== 10000)
983 if (mips_opts
.mips16
< 0)
985 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
986 mips_opts
.mips16
= 1;
988 mips_opts
.mips16
= 0;
992 mips_4650
= (mips_cpu
== 4650);
995 mips_4010
= (mips_cpu
== 4010);
998 mips_4100
= (mips_cpu
== 4100);
1000 /* start-sanitize-vr4320 */
1002 mips_4320
= (mips_cpu
== 4320);
1004 /* end-sanitize-vr4320 */
1005 /* start-sanitize-vr5400 */
1007 mips_5400
= (mips_cpu
== 5400);
1008 /* end-sanitize-vr5400 */
1010 /* start-sanitize-r5900 */
1012 mips_5900
= (mips_cpu
== 5900);
1013 /* end-sanitize-r5900 */
1016 mips_3900
= (mips_cpu
== 3900);
1018 /* start-sanitize-tx49 */
1020 mips_4900
= (mips_cpu
== 4900);
1022 /* end-sanitize-tx49 */
1024 /* End of TARGET_CPU processing, get rid of malloced memory
1033 if (mips_opts
.isa
< 2 && mips_trap
)
1034 as_bad ("trap exception not supported at ISA 1");
1036 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1038 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1042 switch (mips_opts
.isa
)
1045 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1048 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1051 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1054 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1060 as_warn ("Could not set architecture and machine");
1062 file_mips_isa
= mips_opts
.isa
;
1064 op_hash
= hash_new ();
1066 for (i
= 0; i
< NUMOPCODES
;)
1068 const char *name
= mips_opcodes
[i
].name
;
1070 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1073 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
1074 mips_opcodes
[i
].name
, retval
);
1075 /* Probably a memory allocation problem? Give up now. */
1076 as_fatal ("Broken assembler. No assembly attempted.");
1080 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1082 if (!validate_mips_insn (&mips_opcodes
[i
]))
1087 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1090 mips16_op_hash
= hash_new ();
1093 while (i
< bfd_mips16_num_opcodes
)
1095 const char *name
= mips16_opcodes
[i
].name
;
1097 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1099 as_fatal ("internal: can't hash `%s': %s",
1100 mips16_opcodes
[i
].name
, retval
);
1103 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1104 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1105 != mips16_opcodes
[i
].match
))
1107 fprintf (stderr
, "internal error: bad mips16 opcode: %s %s\n",
1108 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1113 while (i
< bfd_mips16_num_opcodes
1114 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1118 as_fatal ("Broken assembler. No assembly attempted.");
1120 /* We add all the general register names to the symbol table. This
1121 helps us detect invalid uses of them. */
1122 for (i
= 0; i
< 32; i
++)
1126 sprintf (buf
, "$%d", i
);
1127 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1128 &zero_address_frag
));
1130 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1131 &zero_address_frag
));
1132 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1133 &zero_address_frag
));
1134 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1135 &zero_address_frag
));
1136 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1137 &zero_address_frag
));
1138 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1139 &zero_address_frag
));
1140 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1141 &zero_address_frag
));
1142 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1143 &zero_address_frag
));
1145 mips_no_prev_insn (false);
1148 mips_cprmask
[0] = 0;
1149 mips_cprmask
[1] = 0;
1150 mips_cprmask
[2] = 0;
1151 mips_cprmask
[3] = 0;
1153 /* set the default alignment for the text section (2**2) */
1154 record_alignment (text_section
, 2);
1156 if (USE_GLOBAL_POINTER_OPT
)
1157 bfd_set_gp_size (stdoutput
, g_switch_value
);
1159 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1161 /* On a native system, sections must be aligned to 16 byte
1162 boundaries. When configured for an embedded ELF target, we
1164 if (strcmp (TARGET_OS
, "elf") != 0)
1166 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1167 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1168 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1171 /* Create a .reginfo section for register masks and a .mdebug
1172 section for debugging information. */
1180 subseg
= now_subseg
;
1182 /* The ABI says this section should be loaded so that the
1183 running program can access it. However, we don't load it
1184 if we are configured for an embedded target */
1185 flags
= SEC_READONLY
| SEC_DATA
;
1186 if (strcmp (TARGET_OS
, "elf") != 0)
1187 flags
|= SEC_ALLOC
| SEC_LOAD
;
1191 sec
= subseg_new (".reginfo", (subsegT
) 0);
1194 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1195 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1198 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1203 /* The 64-bit ABI uses a .MIPS.options section rather than
1204 .reginfo section. */
1205 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1206 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1207 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1210 /* Set up the option header. */
1212 Elf_Internal_Options opthdr
;
1215 opthdr
.kind
= ODK_REGINFO
;
1216 opthdr
.size
= (sizeof (Elf_External_Options
)
1217 + sizeof (Elf64_External_RegInfo
));
1220 f
= frag_more (sizeof (Elf_External_Options
));
1221 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1222 (Elf_External_Options
*) f
);
1224 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1229 if (ECOFF_DEBUGGING
)
1231 sec
= subseg_new (".mdebug", (subsegT
) 0);
1232 (void) bfd_set_section_flags (stdoutput
, sec
,
1233 SEC_HAS_CONTENTS
| SEC_READONLY
);
1234 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1237 subseg_set (seg
, subseg
);
1241 if (! ECOFF_DEBUGGING
)
1248 if (! ECOFF_DEBUGGING
)
1256 struct mips_cl_insn insn
;
1258 imm_expr
.X_op
= O_absent
;
1259 imm_reloc
= BFD_RELOC_UNUSED
;
1260 imm_unmatched_hi
= false;
1261 offset_expr
.X_op
= O_absent
;
1262 offset_reloc
= BFD_RELOC_UNUSED
;
1264 if (mips_opts
.mips16
)
1265 mips16_ip (str
, &insn
);
1268 mips_ip (str
, &insn
);
1269 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1270 str
, insn
.insn_opcode
));
1275 as_bad ("%s `%s'", insn_error
, str
);
1279 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1281 if (mips_opts
.mips16
)
1282 mips16_macro (&insn
);
1288 if (imm_expr
.X_op
!= O_absent
)
1289 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1291 else if (offset_expr
.X_op
!= O_absent
)
1292 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1294 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1298 /* See whether instruction IP reads register REG. CLASS is the type
1302 insn_uses_reg (ip
, reg
, class)
1303 struct mips_cl_insn
*ip
;
1305 enum mips_regclass
class;
1307 if (class == MIPS16_REG
)
1309 assert (mips_opts
.mips16
);
1310 reg
= mips16_to_32_reg_map
[reg
];
1311 class = MIPS_GR_REG
;
1314 /* Don't report on general register 0, since it never changes. */
1315 if (class == MIPS_GR_REG
&& reg
== 0)
1318 if (class == MIPS_FP_REG
)
1320 assert (! mips_opts
.mips16
);
1321 /* If we are called with either $f0 or $f1, we must check $f0.
1322 This is not optimal, because it will introduce an unnecessary
1323 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1324 need to distinguish reading both $f0 and $f1 or just one of
1325 them. Note that we don't have to check the other way,
1326 because there is no instruction that sets both $f0 and $f1
1327 and requires a delay. */
1328 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1329 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1330 == (reg
&~ (unsigned) 1)))
1332 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1333 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1334 == (reg
&~ (unsigned) 1)))
1337 else if (! mips_opts
.mips16
)
1339 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1340 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1342 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1343 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1348 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1349 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1350 & MIPS16OP_MASK_RX
)]
1353 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1354 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1355 & MIPS16OP_MASK_RY
)]
1358 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1359 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1360 & MIPS16OP_MASK_MOVE32Z
)]
1363 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1365 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1367 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1369 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1370 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1371 & MIPS16OP_MASK_REGR32
) == reg
)
1378 /* This function returns true if modifying a register requires a
1382 reg_needs_delay (reg
)
1385 unsigned long prev_pinfo
;
1387 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1388 if (! mips_opts
.noreorder
1389 && mips_opts
.isa
< 4
1390 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1391 || (! gpr_interlocks
1392 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1394 /* A load from a coprocessor or from memory. All load
1395 delays delay the use of general register rt for one
1396 instruction on the r3000. The r6000 and r4000 use
1398 /* Itbl support may require additional care here. */
1399 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1400 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1407 /* Mark instruction labels in mips16 mode. This permits the linker to
1408 handle them specially, such as generating jalx instructions when
1409 needed. We also make them odd for the duration of the assembly, in
1410 order to generate the right sort of code. We will make them even
1411 in the adjust_symtab routine, while leaving them marked. This is
1412 convenient for the debugger and the disassembler. The linker knows
1413 to make them odd again. */
1416 mips16_mark_labels ()
1418 if (mips_opts
.mips16
)
1420 struct insn_label_list
*l
;
1422 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1425 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1426 S_SET_OTHER (l
->label
, STO_MIPS16
);
1428 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1429 ++l
->label
->sy_value
.X_add_number
;
1434 /* Output an instruction. PLACE is where to put the instruction; if
1435 it is NULL, this uses frag_more to get room. IP is the instruction
1436 information. ADDRESS_EXPR is an operand of the instruction to be
1437 used with RELOC_TYPE. */
1440 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1442 struct mips_cl_insn
*ip
;
1443 expressionS
*address_expr
;
1444 bfd_reloc_code_real_type reloc_type
;
1445 boolean unmatched_hi
;
1447 register unsigned long prev_pinfo
, pinfo
;
1452 /* Mark instruction labels in mips16 mode. */
1453 if (mips_opts
.mips16
)
1454 mips16_mark_labels ();
1456 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1457 pinfo
= ip
->insn_mo
->pinfo
;
1459 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1463 /* If the previous insn required any delay slots, see if we need
1464 to insert a NOP or two. There are eight kinds of possible
1465 hazards, of which an instruction can have at most one type.
1466 (1) a load from memory delay
1467 (2) a load from a coprocessor delay
1468 (3) an unconditional branch delay
1469 (4) a conditional branch delay
1470 (5) a move to coprocessor register delay
1471 (6) a load coprocessor register from memory delay
1472 (7) a coprocessor condition code delay
1473 (8) a HI/LO special register delay
1475 There are a lot of optimizations we could do that we don't.
1476 In particular, we do not, in general, reorder instructions.
1477 If you use gcc with optimization, it will reorder
1478 instructions and generally do much more optimization then we
1479 do here; repeating all that work in the assembler would only
1480 benefit hand written assembly code, and does not seem worth
1483 /* This is how a NOP is emitted. */
1484 #define emit_nop() \
1486 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1487 : md_number_to_chars (frag_more (4), 0, 4))
1489 /* The previous insn might require a delay slot, depending upon
1490 the contents of the current insn. */
1491 if (! mips_opts
.mips16
1492 && mips_opts
.isa
< 4
1493 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1494 && ! cop_interlocks
)
1495 || (! gpr_interlocks
1496 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1498 /* A load from a coprocessor or from memory. All load
1499 delays delay the use of general register rt for one
1500 instruction on the r3000. The r6000 and r4000 use
1502 /* Itbl support may require additional care here. */
1503 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1504 if (mips_optimize
== 0
1505 || insn_uses_reg (ip
,
1506 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1511 else if (! mips_opts
.mips16
1512 && mips_opts
.isa
< 4
1513 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1514 && ! cop_interlocks
)
1515 || (mips_opts
.isa
< 2
1516 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1518 /* A generic coprocessor delay. The previous instruction
1519 modified a coprocessor general or control register. If
1520 it modified a control register, we need to avoid any
1521 coprocessor instruction (this is probably not always
1522 required, but it sometimes is). If it modified a general
1523 register, we avoid using that register.
1525 On the r6000 and r4000 loading a coprocessor register
1526 from memory is interlocked, and does not require a delay.
1528 This case is not handled very well. There is no special
1529 knowledge of CP0 handling, and the coprocessors other
1530 than the floating point unit are not distinguished at
1532 /* Itbl support may require additional care here. FIXME!
1533 Need to modify this to include knowledge about
1534 user specified delays! */
1535 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1537 if (mips_optimize
== 0
1538 || insn_uses_reg (ip
,
1539 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1544 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1546 if (mips_optimize
== 0
1547 || insn_uses_reg (ip
,
1548 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1555 /* We don't know exactly what the previous instruction
1556 does. If the current instruction uses a coprocessor
1557 register, we must insert a NOP. If previous
1558 instruction may set the condition codes, and the
1559 current instruction uses them, we must insert two
1561 /* Itbl support may require additional care here. */
1562 if (mips_optimize
== 0
1563 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1564 && (pinfo
& INSN_READ_COND_CODE
)))
1566 else if (pinfo
& INSN_COP
)
1570 else if (! mips_opts
.mips16
1571 && mips_opts
.isa
< 4
1572 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1573 && ! cop_interlocks
)
1575 /* The previous instruction sets the coprocessor condition
1576 codes, but does not require a general coprocessor delay
1577 (this means it is a floating point comparison
1578 instruction). If this instruction uses the condition
1579 codes, we need to insert a single NOP. */
1580 /* Itbl support may require additional care here. */
1581 if (mips_optimize
== 0
1582 || (pinfo
& INSN_READ_COND_CODE
))
1585 else if (prev_pinfo
& INSN_READ_LO
)
1587 /* The previous instruction reads the LO register; if the
1588 current instruction writes to the LO register, we must
1589 insert two NOPS. Some newer processors have interlocks. */
1590 if (! hilo_interlocks
1591 && (mips_optimize
== 0
1592 || (pinfo
& INSN_WRITE_LO
)))
1595 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1597 /* The previous instruction reads the HI register; if the
1598 current instruction writes to the HI register, we must
1599 insert a NOP. Some newer processors have interlocks. */
1600 if (! hilo_interlocks
1601 && (mips_optimize
== 0
1602 || (pinfo
& INSN_WRITE_HI
)))
1606 /* If the previous instruction was in a noreorder section, then
1607 we don't want to insert the nop after all. */
1608 /* Itbl support may require additional care here. */
1609 if (prev_insn_unreordered
)
1612 /* There are two cases which require two intervening
1613 instructions: 1) setting the condition codes using a move to
1614 coprocessor instruction which requires a general coprocessor
1615 delay and then reading the condition codes 2) reading the HI
1616 or LO register and then writing to it (except on processors
1617 which have interlocks). If we are not already emitting a NOP
1618 instruction, we must check for these cases compared to the
1619 instruction previous to the previous instruction. */
1620 if ((! mips_opts
.mips16
1621 && mips_opts
.isa
< 4
1622 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1623 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1624 && (pinfo
& INSN_READ_COND_CODE
)
1625 && ! cop_interlocks
)
1626 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1627 && (pinfo
& INSN_WRITE_LO
)
1628 && ! hilo_interlocks
)
1629 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1630 && (pinfo
& INSN_WRITE_HI
)
1631 && ! hilo_interlocks
))
1636 if (prev_prev_insn_unreordered
)
1639 if (prev_prev_nop
&& nops
== 0)
1642 /* If we are being given a nop instruction, don't bother with
1643 one of the nops we would otherwise output. This will only
1644 happen when a nop instruction is used with mips_optimize set
1647 && ! mips_opts
.noreorder
1648 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1651 /* Now emit the right number of NOP instructions. */
1652 if (nops
> 0 && ! mips_opts
.noreorder
)
1655 unsigned long old_frag_offset
;
1657 struct insn_label_list
*l
;
1659 old_frag
= frag_now
;
1660 old_frag_offset
= frag_now_fix ();
1662 for (i
= 0; i
< nops
; i
++)
1667 listing_prev_line ();
1668 /* We may be at the start of a variant frag. In case we
1669 are, make sure there is enough space for the frag
1670 after the frags created by listing_prev_line. The
1671 argument to frag_grow here must be at least as large
1672 as the argument to all other calls to frag_grow in
1673 this file. We don't have to worry about being in the
1674 middle of a variant frag, because the variants insert
1675 all needed nop instructions themselves. */
1679 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1681 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1682 l
->label
->sy_frag
= frag_now
;
1683 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1684 /* mips16 text labels are stored as odd. */
1685 if (mips_opts
.mips16
)
1686 ++l
->label
->sy_value
.X_add_number
;
1689 #ifndef NO_ECOFF_DEBUGGING
1690 if (ECOFF_DEBUGGING
)
1691 ecoff_fix_loc (old_frag
, old_frag_offset
);
1694 else if (prev_nop_frag
!= NULL
)
1696 /* We have a frag holding nops we may be able to remove. If
1697 we don't need any nops, we can decrease the size of
1698 prev_nop_frag by the size of one instruction. If we do
1699 need some nops, we count them in prev_nops_required. */
1700 if (prev_nop_frag_since
== 0)
1704 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1705 --prev_nop_frag_holds
;
1708 prev_nop_frag_required
+= nops
;
1712 if (prev_prev_nop
== 0)
1714 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1715 --prev_nop_frag_holds
;
1718 ++prev_nop_frag_required
;
1721 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1722 prev_nop_frag
= NULL
;
1724 ++prev_nop_frag_since
;
1726 /* Sanity check: by the time we reach the second instruction
1727 after prev_nop_frag, we should have used up all the nops
1728 one way or another. */
1729 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1733 if (reloc_type
> BFD_RELOC_UNUSED
)
1735 /* We need to set up a variant frag. */
1736 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1737 f
= frag_var (rs_machine_dependent
, 4, 0,
1738 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1739 mips16_small
, mips16_ext
,
1741 & INSN_UNCOND_BRANCH_DELAY
),
1742 (prev_insn_reloc_type
1743 == BFD_RELOC_MIPS16_JMP
)),
1744 make_expr_symbol (address_expr
), (offsetT
) 0,
1747 else if (place
!= NULL
)
1749 else if (mips_opts
.mips16
1751 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1753 /* Make sure there is enough room to swap this instruction with
1754 a following jump instruction. */
1760 if (mips_opts
.mips16
1761 && mips_opts
.noreorder
1762 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1763 as_warn ("extended instruction in delay slot");
1769 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1771 if (address_expr
->X_op
== O_constant
)
1776 ip
->insn_opcode
|= address_expr
->X_add_number
;
1779 case BFD_RELOC_LO16
:
1780 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1783 case BFD_RELOC_MIPS_JMP
:
1784 if ((address_expr
->X_add_number
& 3) != 0)
1785 as_bad ("jump to misaligned address (0x%lx)",
1786 (unsigned long) address_expr
->X_add_number
);
1787 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1790 case BFD_RELOC_MIPS16_JMP
:
1791 if ((address_expr
->X_add_number
& 3) != 0)
1792 as_bad ("jump to misaligned address (0x%lx)",
1793 (unsigned long) address_expr
->X_add_number
);
1795 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1796 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1797 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1800 /* start-sanitize-r5900 */
1801 case BFD_RELOC_MIPS15_S3
:
1802 ip
->insn_opcode
|= ((imm_expr
.X_add_number
& 0x7fff) >> 3) << 6;
1804 /* end-sanitize-r5900 */
1806 case BFD_RELOC_16_PCREL_S2
:
1816 /* Don't generate a reloc if we are writing into a variant
1820 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1822 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1826 struct mips_hi_fixup
*hi_fixup
;
1828 assert (reloc_type
== BFD_RELOC_HI16_S
);
1829 hi_fixup
= ((struct mips_hi_fixup
*)
1830 xmalloc (sizeof (struct mips_hi_fixup
)));
1831 hi_fixup
->fixp
= fixp
;
1832 hi_fixup
->seg
= now_seg
;
1833 hi_fixup
->next
= mips_hi_fixup_list
;
1834 mips_hi_fixup_list
= hi_fixup
;
1840 if (! mips_opts
.mips16
)
1841 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1842 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1844 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1845 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1851 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1854 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1857 /* Update the register mask information. */
1858 if (! mips_opts
.mips16
)
1860 if (pinfo
& INSN_WRITE_GPR_D
)
1861 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1862 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1863 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1864 if (pinfo
& INSN_READ_GPR_S
)
1865 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1866 if (pinfo
& INSN_WRITE_GPR_31
)
1867 mips_gprmask
|= 1 << 31;
1868 if (pinfo
& INSN_WRITE_FPR_D
)
1869 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1870 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1871 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1872 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1873 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1874 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1875 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1876 if (pinfo
& INSN_COP
)
1878 /* We don't keep enough information to sort these cases out.
1879 The itbl support does keep this information however, although
1880 we currently don't support itbl fprmats as part of the cop
1881 instruction. May want to add this support in the future. */
1883 /* Never set the bit for $0, which is always zero. */
1884 mips_gprmask
&=~ 1 << 0;
1888 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1889 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1890 & MIPS16OP_MASK_RX
);
1891 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1892 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1893 & MIPS16OP_MASK_RY
);
1894 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1895 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1896 & MIPS16OP_MASK_RZ
);
1897 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1898 mips_gprmask
|= 1 << TREG
;
1899 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1900 mips_gprmask
|= 1 << SP
;
1901 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1902 mips_gprmask
|= 1 << RA
;
1903 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1904 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1905 if (pinfo
& MIPS16_INSN_READ_Z
)
1906 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1907 & MIPS16OP_MASK_MOVE32Z
);
1908 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1909 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1910 & MIPS16OP_MASK_REGR32
);
1913 if (place
== NULL
&& ! mips_opts
.noreorder
)
1915 /* Filling the branch delay slot is more complex. We try to
1916 switch the branch with the previous instruction, which we can
1917 do if the previous instruction does not set up a condition
1918 that the branch tests and if the branch is not itself the
1919 target of any branch. */
1920 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1921 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1923 if (mips_optimize
< 2
1924 /* If we have seen .set volatile or .set nomove, don't
1926 || mips_opts
.nomove
!= 0
1927 /* If we had to emit any NOP instructions, then we
1928 already know we can not swap. */
1930 /* If we don't even know the previous insn, we can not
1932 || ! prev_insn_valid
1933 /* If the previous insn is already in a branch delay
1934 slot, then we can not swap. */
1935 || prev_insn_is_delay_slot
1936 /* If the previous previous insn was in a .set
1937 noreorder, we can't swap. Actually, the MIPS
1938 assembler will swap in this situation. However, gcc
1939 configured -with-gnu-as will generate code like
1945 in which we can not swap the bne and INSN. If gcc is
1946 not configured -with-gnu-as, it does not output the
1947 .set pseudo-ops. We don't have to check
1948 prev_insn_unreordered, because prev_insn_valid will
1949 be 0 in that case. We don't want to use
1950 prev_prev_insn_valid, because we do want to be able
1951 to swap at the start of a function. */
1952 || prev_prev_insn_unreordered
1953 /* If the branch is itself the target of a branch, we
1954 can not swap. We cheat on this; all we check for is
1955 whether there is a label on this instruction. If
1956 there are any branches to anything other than a
1957 label, users must use .set noreorder. */
1958 || insn_labels
!= NULL
1959 /* If the previous instruction is in a variant frag, we
1960 can not do the swap. This does not apply to the
1961 mips16, which uses variant frags for different
1963 || (! mips_opts
.mips16
1964 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1965 /* If the branch reads the condition codes, we don't
1966 even try to swap, because in the sequence
1971 we can not swap, and I don't feel like handling that
1973 || (! mips_opts
.mips16
1974 && mips_opts
.isa
< 4
1975 && (pinfo
& INSN_READ_COND_CODE
))
1976 /* We can not swap with an instruction that requires a
1977 delay slot, becase the target of the branch might
1978 interfere with that instruction. */
1979 || (! mips_opts
.mips16
1980 && mips_opts
.isa
< 4
1982 /* Itbl support may require additional care here. */
1983 & (INSN_LOAD_COPROC_DELAY
1984 | INSN_COPROC_MOVE_DELAY
1985 | INSN_WRITE_COND_CODE
)))
1986 || (! hilo_interlocks
1990 || (! mips_opts
.mips16
1992 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1993 || (! mips_opts
.mips16
1994 && mips_opts
.isa
< 2
1995 /* Itbl support may require additional care here. */
1996 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1997 /* We can not swap with a branch instruction. */
1999 & (INSN_UNCOND_BRANCH_DELAY
2000 | INSN_COND_BRANCH_DELAY
2001 | INSN_COND_BRANCH_LIKELY
))
2002 /* We do not swap with a trap instruction, since it
2003 complicates trap handlers to have the trap
2004 instruction be in a delay slot. */
2005 || (prev_pinfo
& INSN_TRAP
)
2006 /* If the branch reads a register that the previous
2007 instruction sets, we can not swap. */
2008 || (! mips_opts
.mips16
2009 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2010 && insn_uses_reg (ip
,
2011 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2014 || (! mips_opts
.mips16
2015 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2016 && insn_uses_reg (ip
,
2017 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2020 || (mips_opts
.mips16
2021 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2022 && insn_uses_reg (ip
,
2023 ((prev_insn
.insn_opcode
2025 & MIPS16OP_MASK_RX
),
2027 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2028 && insn_uses_reg (ip
,
2029 ((prev_insn
.insn_opcode
2031 & MIPS16OP_MASK_RY
),
2033 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2034 && insn_uses_reg (ip
,
2035 ((prev_insn
.insn_opcode
2037 & MIPS16OP_MASK_RZ
),
2039 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2040 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2041 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2042 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2043 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2044 && insn_uses_reg (ip
,
2045 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2048 /* If the branch writes a register that the previous
2049 instruction sets, we can not swap (we know that
2050 branches write only to RD or to $31). */
2051 || (! mips_opts
.mips16
2052 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2053 && (((pinfo
& INSN_WRITE_GPR_D
)
2054 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2055 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2056 || ((pinfo
& INSN_WRITE_GPR_31
)
2057 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2060 || (! mips_opts
.mips16
2061 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2062 && (((pinfo
& INSN_WRITE_GPR_D
)
2063 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2064 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2065 || ((pinfo
& INSN_WRITE_GPR_31
)
2066 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2069 || (mips_opts
.mips16
2070 && (pinfo
& MIPS16_INSN_WRITE_31
)
2071 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2072 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2073 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2075 /* If the branch writes a register that the previous
2076 instruction reads, we can not swap (we know that
2077 branches only write to RD or to $31). */
2078 || (! mips_opts
.mips16
2079 && (pinfo
& INSN_WRITE_GPR_D
)
2080 && insn_uses_reg (&prev_insn
,
2081 ((ip
->insn_opcode
>> OP_SH_RD
)
2084 || (! mips_opts
.mips16
2085 && (pinfo
& INSN_WRITE_GPR_31
)
2086 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2087 || (mips_opts
.mips16
2088 && (pinfo
& MIPS16_INSN_WRITE_31
)
2089 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2090 /* If we are generating embedded PIC code, the branch
2091 might be expanded into a sequence which uses $at, so
2092 we can't swap with an instruction which reads it. */
2093 || (mips_pic
== EMBEDDED_PIC
2094 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2095 /* If the previous previous instruction has a load
2096 delay, and sets a register that the branch reads, we
2098 || (! mips_opts
.mips16
2099 && mips_opts
.isa
< 4
2100 /* Itbl support may require additional care here. */
2101 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2102 || (! gpr_interlocks
2103 && (prev_prev_insn
.insn_mo
->pinfo
2104 & INSN_LOAD_MEMORY_DELAY
)))
2105 && insn_uses_reg (ip
,
2106 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2109 /* If one instruction sets a condition code and the
2110 other one uses a condition code, we can not swap. */
2111 || ((pinfo
& INSN_READ_COND_CODE
)
2112 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2113 || ((pinfo
& INSN_WRITE_COND_CODE
)
2114 && (prev_pinfo
& INSN_READ_COND_CODE
))
2115 /* If the previous instruction uses the PC, we can not
2117 || (mips_opts
.mips16
2118 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2119 /* If the previous instruction was extended, we can not
2121 || (mips_opts
.mips16
&& prev_insn_extended
)
2122 /* If the previous instruction had a fixup in mips16
2123 mode, we can not swap. This normally means that the
2124 previous instruction was a 4 byte branch anyhow. */
2125 || (mips_opts
.mips16
&& prev_insn_fixp
))
2127 /* We could do even better for unconditional branches to
2128 portions of this object file; we could pick up the
2129 instruction at the destination, put it in the delay
2130 slot, and bump the destination address. */
2132 /* Update the previous insn information. */
2133 prev_prev_insn
= *ip
;
2134 prev_insn
.insn_mo
= &dummy_opcode
;
2138 /* It looks like we can actually do the swap. */
2139 if (! mips_opts
.mips16
)
2144 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2145 memcpy (temp
, prev_f
, 4);
2146 memcpy (prev_f
, f
, 4);
2147 memcpy (f
, temp
, 4);
2150 prev_insn_fixp
->fx_frag
= frag_now
;
2151 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2155 fixp
->fx_frag
= prev_insn_frag
;
2156 fixp
->fx_where
= prev_insn_where
;
2164 assert (prev_insn_fixp
== NULL
);
2165 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2166 memcpy (temp
, prev_f
, 2);
2167 memcpy (prev_f
, f
, 2);
2168 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2170 assert (reloc_type
== BFD_RELOC_UNUSED
);
2171 memcpy (f
, temp
, 2);
2175 memcpy (f
, f
+ 2, 2);
2176 memcpy (f
+ 2, temp
, 2);
2180 fixp
->fx_frag
= prev_insn_frag
;
2181 fixp
->fx_where
= prev_insn_where
;
2185 /* Update the previous insn information; leave prev_insn
2187 prev_prev_insn
= *ip
;
2189 prev_insn_is_delay_slot
= 1;
2191 /* If that was an unconditional branch, forget the previous
2192 insn information. */
2193 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2195 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2196 prev_insn
.insn_mo
= &dummy_opcode
;
2199 prev_insn_fixp
= NULL
;
2200 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2201 prev_insn_extended
= 0;
2203 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2205 /* We don't yet optimize a branch likely. What we should do
2206 is look at the target, copy the instruction found there
2207 into the delay slot, and increment the branch to jump to
2208 the next instruction. */
2210 /* Update the previous insn information. */
2211 prev_prev_insn
= *ip
;
2212 prev_insn
.insn_mo
= &dummy_opcode
;
2213 prev_insn_fixp
= NULL
;
2214 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2215 prev_insn_extended
= 0;
2219 /* Update the previous insn information. */
2221 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2223 prev_prev_insn
= prev_insn
;
2226 /* Any time we see a branch, we always fill the delay slot
2227 immediately; since this insn is not a branch, we know it
2228 is not in a delay slot. */
2229 prev_insn_is_delay_slot
= 0;
2231 prev_insn_fixp
= fixp
;
2232 prev_insn_reloc_type
= reloc_type
;
2233 if (mips_opts
.mips16
)
2234 prev_insn_extended
= (ip
->use_extend
2235 || reloc_type
> BFD_RELOC_UNUSED
);
2238 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2239 prev_insn_unreordered
= 0;
2240 prev_insn_frag
= frag_now
;
2241 prev_insn_where
= f
- frag_now
->fr_literal
;
2242 prev_insn_valid
= 1;
2244 else if (place
== NULL
)
2246 /* We need to record a bit of information even when we are not
2247 reordering, in order to determine the base address for mips16
2248 PC relative relocs. */
2249 prev_prev_insn
= prev_insn
;
2251 prev_insn_reloc_type
= reloc_type
;
2252 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2253 prev_insn_unreordered
= 1;
2256 /* We just output an insn, so the next one doesn't have a label. */
2257 mips_clear_insn_labels ();
2259 /* We must ensure that a fixup associated with an unmatched %hi
2260 reloc does not become a variant frag. Otherwise, the
2261 rearrangement of %hi relocs in frob_file may confuse
2265 frag_wane (frag_now
);
2270 /* This function forgets that there was any previous instruction or
2271 label. If PRESERVE is non-zero, it remembers enough information to
2272 know whether nops are needed before a noreorder section. */
2275 mips_no_prev_insn (preserve
)
2280 prev_insn
.insn_mo
= &dummy_opcode
;
2281 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2282 prev_nop_frag
= NULL
;
2283 prev_nop_frag_holds
= 0;
2284 prev_nop_frag_required
= 0;
2285 prev_nop_frag_since
= 0;
2287 prev_insn_valid
= 0;
2288 prev_insn_is_delay_slot
= 0;
2289 prev_insn_unreordered
= 0;
2290 prev_insn_extended
= 0;
2291 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2292 prev_prev_insn_unreordered
= 0;
2293 mips_clear_insn_labels ();
2296 /* This function must be called whenever we turn on noreorder or emit
2297 something other than instructions. It inserts any NOPS which might
2298 be needed by the previous instruction, and clears the information
2299 kept for the previous instructions. The INSNS parameter is true if
2300 instructions are to follow. */
2303 mips_emit_delays (insns
)
2306 if (! mips_opts
.noreorder
)
2311 if ((! mips_opts
.mips16
2312 && mips_opts
.isa
< 4
2313 && (! cop_interlocks
2314 && (prev_insn
.insn_mo
->pinfo
2315 & (INSN_LOAD_COPROC_DELAY
2316 | INSN_COPROC_MOVE_DELAY
2317 | INSN_WRITE_COND_CODE
))))
2318 || (! hilo_interlocks
2319 && (prev_insn
.insn_mo
->pinfo
2322 || (! mips_opts
.mips16
2324 && (prev_insn
.insn_mo
->pinfo
2325 & INSN_LOAD_MEMORY_DELAY
))
2326 || (! mips_opts
.mips16
2327 && mips_opts
.isa
< 2
2328 && (prev_insn
.insn_mo
->pinfo
2329 & INSN_COPROC_MEMORY_DELAY
)))
2331 /* Itbl support may require additional care here. */
2333 if ((! mips_opts
.mips16
2334 && mips_opts
.isa
< 4
2335 && (! cop_interlocks
2336 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2337 || (! hilo_interlocks
2338 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2339 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2342 if (prev_insn_unreordered
)
2345 else if ((! mips_opts
.mips16
2346 && mips_opts
.isa
< 4
2347 && (! cop_interlocks
2348 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2349 || (! hilo_interlocks
2350 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2351 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2353 /* Itbl support may require additional care here. */
2354 if (! prev_prev_insn_unreordered
)
2360 struct insn_label_list
*l
;
2364 /* Record the frag which holds the nop instructions, so
2365 that we can remove them if we don't need them. */
2366 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2367 prev_nop_frag
= frag_now
;
2368 prev_nop_frag_holds
= nops
;
2369 prev_nop_frag_required
= 0;
2370 prev_nop_frag_since
= 0;
2373 for (; nops
> 0; --nops
)
2378 /* Move on to a new frag, so that it is safe to simply
2379 decrease the size of prev_nop_frag. */
2380 frag_wane (frag_now
);
2384 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2386 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2387 l
->label
->sy_frag
= frag_now
;
2388 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2389 /* mips16 text labels are stored as odd. */
2390 if (mips_opts
.mips16
)
2391 ++l
->label
->sy_value
.X_add_number
;
2396 /* Mark instruction labels in mips16 mode. */
2397 if (mips_opts
.mips16
&& insns
)
2398 mips16_mark_labels ();
2400 mips_no_prev_insn (insns
);
2403 /* Build an instruction created by a macro expansion. This is passed
2404 a pointer to the count of instructions created so far, an
2405 expression, the name of the instruction to build, an operand format
2406 string, and corresponding arguments. */
2410 macro_build (char *place
,
2418 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2427 struct mips_cl_insn insn
;
2428 bfd_reloc_code_real_type r
;
2433 va_start (args
, fmt
);
2439 * If the macro is about to expand into a second instruction,
2440 * print a warning if needed. We need to pass ip as a parameter
2441 * to generate a better warning message here...
2443 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2444 as_warn ("Macro instruction expanded into multiple instructions");
2447 *counter
+= 1; /* bump instruction counter */
2449 if (mips_opts
.mips16
)
2451 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2456 r
= BFD_RELOC_UNUSED
;
2457 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2458 assert (insn
.insn_mo
);
2459 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2461 /* Search until we get a match for NAME. */
2464 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2466 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2468 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2470 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2475 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2476 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2477 && (insn_isa
<= mips_opts
.isa
2479 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2481 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2483 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2484 /* start-sanitize-vr4320 */
2486 && (insn
.insn_mo
->membership
& INSN_4320
) != 0)
2487 /* end-sanitize-vr4320 */
2488 /* start-sanitize-tx49 */
2490 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2491 /* end-sanitize-tx49 */
2492 /* start-sanitize-r5900 */
2494 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2495 /* end-sanitize-r5900 */
2496 /* start-sanitize-vr5400 */
2498 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2499 /* end-sanitize-vr5400 */
2501 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2502 /* start-sanitize-r5900 */
2503 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2504 /* end-sanitize-r5900 */
2505 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2509 assert (insn
.insn_mo
->name
);
2510 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2513 insn
.insn_opcode
= insn
.insn_mo
->match
;
2529 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2535 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2540 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2545 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2552 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2556 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2560 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2567 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2573 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2574 assert (r
== BFD_RELOC_MIPS_GPREL
2575 || r
== BFD_RELOC_MIPS_LITERAL
2576 || r
== BFD_RELOC_LO16
2577 || r
== BFD_RELOC_MIPS_GOT16
2578 || r
== BFD_RELOC_MIPS_CALL16
2579 || r
== BFD_RELOC_MIPS_GOT_LO16
2580 || r
== BFD_RELOC_MIPS_CALL_LO16
2581 || (ep
->X_op
== O_subtract
2582 && now_seg
== text_section
2583 && r
== BFD_RELOC_PCREL_LO16
));
2587 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2589 && (ep
->X_op
== O_constant
2590 || (ep
->X_op
== O_symbol
2591 && (r
== BFD_RELOC_HI16_S
2592 || r
== BFD_RELOC_HI16
2593 || r
== BFD_RELOC_MIPS_GOT_HI16
2594 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2595 || (ep
->X_op
== O_subtract
2596 && now_seg
== text_section
2597 && r
== BFD_RELOC_PCREL_HI16_S
)));
2598 if (ep
->X_op
== O_constant
)
2600 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2602 r
= BFD_RELOC_UNUSED
;
2607 assert (ep
!= NULL
);
2609 * This allows macro() to pass an immediate expression for
2610 * creating short branches without creating a symbol.
2611 * Note that the expression still might come from the assembly
2612 * input, in which case the value is not checked for range nor
2613 * is a relocation entry generated (yuck).
2615 if (ep
->X_op
== O_constant
)
2617 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2621 r
= BFD_RELOC_16_PCREL_S2
;
2625 assert (ep
!= NULL
);
2626 r
= BFD_RELOC_MIPS_JMP
;
2630 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2639 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2641 append_insn (place
, &insn
, ep
, r
, false);
2645 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2653 struct mips_cl_insn insn
;
2654 bfd_reloc_code_real_type r
;
2656 r
= BFD_RELOC_UNUSED
;
2657 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2658 assert (insn
.insn_mo
);
2659 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2661 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2662 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2665 assert (insn
.insn_mo
->name
);
2666 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2669 insn
.insn_opcode
= insn
.insn_mo
->match
;
2670 insn
.use_extend
= false;
2689 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2694 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2698 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2702 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2712 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2719 regno
= va_arg (args
, int);
2720 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2721 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2742 assert (ep
!= NULL
);
2744 if (ep
->X_op
!= O_constant
)
2745 r
= BFD_RELOC_UNUSED
+ c
;
2748 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2749 false, false, &insn
.insn_opcode
,
2750 &insn
.use_extend
, &insn
.extend
);
2752 r
= BFD_RELOC_UNUSED
;
2758 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2765 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2767 append_insn (place
, &insn
, ep
, r
, false);
2771 * Generate a "lui" instruction.
2774 macro_build_lui (place
, counter
, ep
, regnum
)
2780 expressionS high_expr
;
2781 struct mips_cl_insn insn
;
2782 bfd_reloc_code_real_type r
;
2783 CONST
char *name
= "lui";
2784 CONST
char *fmt
= "t,u";
2786 assert (! mips_opts
.mips16
);
2792 high_expr
.X_op
= O_constant
;
2793 high_expr
.X_add_number
= ep
->X_add_number
;
2796 if (high_expr
.X_op
== O_constant
)
2798 /* we can compute the instruction now without a relocation entry */
2799 if (high_expr
.X_add_number
& 0x8000)
2800 high_expr
.X_add_number
+= 0x10000;
2801 high_expr
.X_add_number
=
2802 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2803 r
= BFD_RELOC_UNUSED
;
2807 assert (ep
->X_op
== O_symbol
);
2808 /* _gp_disp is a special case, used from s_cpload. */
2809 assert (mips_pic
== NO_PIC
2810 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2811 r
= BFD_RELOC_HI16_S
;
2815 * If the macro is about to expand into a second instruction,
2816 * print a warning if needed. We need to pass ip as a parameter
2817 * to generate a better warning message here...
2819 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2820 as_warn ("Macro instruction expanded into multiple instructions");
2823 *counter
+= 1; /* bump instruction counter */
2825 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2826 assert (insn
.insn_mo
);
2827 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2828 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2830 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2831 if (r
== BFD_RELOC_UNUSED
)
2833 insn
.insn_opcode
|= high_expr
.X_add_number
;
2834 append_insn (place
, &insn
, NULL
, r
, false);
2837 append_insn (place
, &insn
, &high_expr
, r
, false);
2841 * Generates code to set the $at register to true (one)
2842 * if reg is less than the immediate expression.
2845 set_at (counter
, reg
, unsignedp
)
2850 if (imm_expr
.X_op
== O_constant
2851 && imm_expr
.X_add_number
>= -0x8000
2852 && imm_expr
.X_add_number
< 0x8000)
2853 macro_build ((char *) NULL
, counter
, &imm_expr
,
2854 unsignedp
? "sltiu" : "slti",
2855 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2858 load_register (counter
, AT
, &imm_expr
, 0);
2859 macro_build ((char *) NULL
, counter
, NULL
,
2860 unsignedp
? "sltu" : "slt",
2861 "d,v,t", AT
, reg
, AT
);
2865 /* Warn if an expression is not a constant. */
2868 check_absolute_expr (ip
, ex
)
2869 struct mips_cl_insn
*ip
;
2872 if (ex
->X_op
== O_big
)
2873 as_bad ("unsupported large constant");
2874 else if (ex
->X_op
!= O_constant
)
2875 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2878 /* Count the leading zeroes by performing a binary chop. This is a
2879 bulky bit of source, but performance is a LOT better for the
2880 majority of values than a simple loop to count the bits:
2881 for (lcnt = 0; (lcnt < 32); lcnt++)
2882 if ((v) & (1 << (31 - lcnt)))
2884 However it is not code size friendly, and the gain will drop a bit
2885 on certain cached systems.
2887 #define COUNT_TOP_ZEROES(v) \
2888 (((v) & ~0xffff) == 0 \
2889 ? ((v) & ~0xff) == 0 \
2890 ? ((v) & ~0xf) == 0 \
2891 ? ((v) & ~0x3) == 0 \
2892 ? ((v) & ~0x1) == 0 \
2897 : ((v) & ~0x7) == 0 \
2900 : ((v) & ~0x3f) == 0 \
2901 ? ((v) & ~0x1f) == 0 \
2904 : ((v) & ~0x7f) == 0 \
2907 : ((v) & ~0xfff) == 0 \
2908 ? ((v) & ~0x3ff) == 0 \
2909 ? ((v) & ~0x1ff) == 0 \
2912 : ((v) & ~0x7ff) == 0 \
2915 : ((v) & ~0x3fff) == 0 \
2916 ? ((v) & ~0x1fff) == 0 \
2919 : ((v) & ~0x7fff) == 0 \
2922 : ((v) & ~0xffffff) == 0 \
2923 ? ((v) & ~0xfffff) == 0 \
2924 ? ((v) & ~0x3ffff) == 0 \
2925 ? ((v) & ~0x1ffff) == 0 \
2928 : ((v) & ~0x7ffff) == 0 \
2931 : ((v) & ~0x3fffff) == 0 \
2932 ? ((v) & ~0x1fffff) == 0 \
2935 : ((v) & ~0x7fffff) == 0 \
2938 : ((v) & ~0xfffffff) == 0 \
2939 ? ((v) & ~0x3ffffff) == 0 \
2940 ? ((v) & ~0x1ffffff) == 0 \
2943 : ((v) & ~0x7ffffff) == 0 \
2946 : ((v) & ~0x3fffffff) == 0 \
2947 ? ((v) & ~0x1fffffff) == 0 \
2950 : ((v) & ~0x7fffffff) == 0 \
2955 * This routine generates the least number of instructions neccessary to load
2956 * an absolute expression value into a register.
2959 load_register (counter
, reg
, ep
, dbl
)
2966 expressionS hi32
, lo32
;
2968 if (ep
->X_op
!= O_big
)
2970 assert (ep
->X_op
== O_constant
);
2971 if (ep
->X_add_number
< 0x8000
2972 && (ep
->X_add_number
>= 0
2973 || (ep
->X_add_number
>= -0x8000
2976 || sizeof (ep
->X_add_number
) > 4))))
2978 /* We can handle 16 bit signed values with an addiu to
2979 $zero. No need to ever use daddiu here, since $zero and
2980 the result are always correct in 32 bit mode. */
2981 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2982 (int) BFD_RELOC_LO16
);
2985 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2987 /* We can handle 16 bit unsigned values with an ori to
2989 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2990 (int) BFD_RELOC_LO16
);
2993 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2994 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2995 == ~ (offsetT
) 0x7fffffff))
2998 || sizeof (ep
->X_add_number
) > 4
2999 || (ep
->X_add_number
& 0x80000000) == 0))
3000 || ((mips_opts
.isa
< 3 || ! dbl
)
3001 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3002 || (mips_opts
.isa
< 3
3004 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3005 == ~ (offsetT
) 0xffffffff)))
3007 /* 32 bit values require an lui. */
3008 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3009 (int) BFD_RELOC_HI16
);
3010 if ((ep
->X_add_number
& 0xffff) != 0)
3011 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3012 (int) BFD_RELOC_LO16
);
3017 /* The value is larger than 32 bits. */
3019 if (mips_opts
.isa
< 3)
3021 as_bad ("Number larger than 32 bits");
3022 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3023 (int) BFD_RELOC_LO16
);
3027 if (ep
->X_op
!= O_big
)
3030 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3031 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3032 hi32
.X_add_number
&= 0xffffffff;
3034 lo32
.X_add_number
&= 0xffffffff;
3038 assert (ep
->X_add_number
> 2);
3039 if (ep
->X_add_number
== 3)
3040 generic_bignum
[3] = 0;
3041 else if (ep
->X_add_number
> 4)
3042 as_bad ("Number larger than 64 bits");
3043 lo32
.X_op
= O_constant
;
3044 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3045 hi32
.X_op
= O_constant
;
3046 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3049 if (hi32
.X_add_number
== 0)
3054 unsigned long hi
, lo
;
3056 if (hi32
.X_add_number
== 0xffffffff)
3058 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3060 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3061 reg
, 0, (int) BFD_RELOC_LO16
);
3064 if (lo32
.X_add_number
& 0x80000000)
3066 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3067 (int) BFD_RELOC_HI16
);
3068 if (lo32
.X_add_number
& 0xffff)
3069 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3070 reg
, reg
, (int) BFD_RELOC_LO16
);
3075 /* Check for 16bit shifted constant. We know that hi32 is
3076 non-zero, so start the mask on the first bit of the hi32
3081 unsigned long himask
, lomask
;
3085 himask
= 0xffff >> (32 - shift
);
3086 lomask
= (0xffff << shift
) & 0xffffffff;
3090 himask
= 0xffff << (shift
- 32);
3093 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3094 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3098 tmp
.X_op
= O_constant
;
3100 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3101 | (lo32
.X_add_number
>> shift
));
3103 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3104 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3105 (int) BFD_RELOC_LO16
);
3106 macro_build ((char *) NULL
, counter
, NULL
,
3107 (shift
>= 32) ? "dsll32" : "dsll",
3109 (shift
>= 32) ? shift
- 32 : shift
);
3113 } while (shift
<= (64 - 16));
3115 /* Find the bit number of the lowest one bit, and store the
3116 shifted value in hi/lo. */
3117 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3118 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3122 while ((lo
& 1) == 0)
3127 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3133 while ((hi
& 1) == 0)
3142 /* Optimize if the shifted value is a (power of 2) - 1. */
3143 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3144 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3146 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3151 /* This instruction will set the register to be all
3153 tmp
.X_op
= O_constant
;
3154 tmp
.X_add_number
= (offsetT
) -1;
3155 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3156 reg
, 0, (int) BFD_RELOC_LO16
);
3160 macro_build ((char *) NULL
, counter
, NULL
,
3161 (bit
>= 32) ? "dsll32" : "dsll",
3163 (bit
>= 32) ? bit
- 32 : bit
);
3165 macro_build ((char *) NULL
, counter
, NULL
,
3166 (shift
>= 32) ? "dsrl32" : "dsrl",
3168 (shift
>= 32) ? shift
- 32 : shift
);
3173 /* Sign extend hi32 before calling load_register, because we can
3174 generally get better code when we load a sign extended value. */
3175 if ((hi32
.X_add_number
& 0x80000000) != 0)
3176 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3177 load_register (counter
, reg
, &hi32
, 0);
3180 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3184 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3193 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3195 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3196 (int) BFD_RELOC_HI16
);
3197 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3204 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3209 mid16
.X_add_number
>>= 16;
3210 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3211 freg
, (int) BFD_RELOC_LO16
);
3212 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3216 if ((lo32
.X_add_number
& 0xffff) != 0)
3217 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3218 (int) BFD_RELOC_LO16
);
3221 /* Load an address into a register. */
3224 load_address (counter
, reg
, ep
)
3231 if (ep
->X_op
!= O_constant
3232 && ep
->X_op
!= O_symbol
)
3234 as_bad ("expression too complex");
3235 ep
->X_op
= O_constant
;
3238 if (ep
->X_op
== O_constant
)
3240 load_register (counter
, reg
, ep
, 0);
3244 if (mips_pic
== NO_PIC
)
3246 /* If this is a reference to a GP relative symbol, we want
3247 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3249 lui $reg,<sym> (BFD_RELOC_HI16_S)
3250 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3251 If we have an addend, we always use the latter form. */
3252 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3253 || nopic_need_relax (ep
->X_add_symbol
, 1))
3258 macro_build ((char *) NULL
, counter
, ep
,
3259 ((bfd_arch_bits_per_address (stdoutput
) == 32
3260 || mips_opts
.isa
< 3)
3261 ? "addiu" : "daddiu"),
3262 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3263 p
= frag_var (rs_machine_dependent
, 8, 0,
3264 RELAX_ENCODE (4, 8, 0, 4, 0,
3265 mips_opts
.warn_about_macros
),
3266 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3268 macro_build_lui (p
, counter
, ep
, reg
);
3271 macro_build (p
, counter
, ep
,
3272 ((bfd_arch_bits_per_address (stdoutput
) == 32
3273 || mips_opts
.isa
< 3)
3274 ? "addiu" : "daddiu"),
3275 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3277 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3281 /* If this is a reference to an external symbol, we want
3282 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3284 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3286 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3287 If there is a constant, it must be added in after. */
3288 ex
.X_add_number
= ep
->X_add_number
;
3289 ep
->X_add_number
= 0;
3291 macro_build ((char *) NULL
, counter
, ep
,
3292 ((bfd_arch_bits_per_address (stdoutput
) == 32
3293 || mips_opts
.isa
< 3)
3295 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3296 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3297 p
= frag_var (rs_machine_dependent
, 4, 0,
3298 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3299 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3300 macro_build (p
, counter
, ep
,
3301 ((bfd_arch_bits_per_address (stdoutput
) == 32
3302 || mips_opts
.isa
< 3)
3303 ? "addiu" : "daddiu"),
3304 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3305 if (ex
.X_add_number
!= 0)
3307 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3308 as_bad ("PIC code offset overflow (max 16 signed bits)");
3309 ex
.X_op
= O_constant
;
3310 macro_build ((char *) NULL
, counter
, &ex
,
3311 ((bfd_arch_bits_per_address (stdoutput
) == 32
3312 || mips_opts
.isa
< 3)
3313 ? "addiu" : "daddiu"),
3314 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3317 else if (mips_pic
== SVR4_PIC
)
3322 /* This is the large GOT case. If this is a reference to an
3323 external symbol, we want
3324 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3326 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3327 Otherwise, for a reference to a local symbol, we want
3328 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3330 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3331 If there is a constant, it must be added in after. */
3332 ex
.X_add_number
= ep
->X_add_number
;
3333 ep
->X_add_number
= 0;
3334 if (reg_needs_delay (GP
))
3339 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3340 (int) BFD_RELOC_MIPS_GOT_HI16
);
3341 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3342 ((bfd_arch_bits_per_address (stdoutput
) == 32
3343 || mips_opts
.isa
< 3)
3344 ? "addu" : "daddu"),
3345 "d,v,t", reg
, reg
, GP
);
3346 macro_build ((char *) NULL
, counter
, ep
,
3347 ((bfd_arch_bits_per_address (stdoutput
) == 32
3348 || mips_opts
.isa
< 3)
3350 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3351 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3352 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3353 mips_opts
.warn_about_macros
),
3354 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3357 /* We need a nop before loading from $gp. This special
3358 check is required because the lui which starts the main
3359 instruction stream does not refer to $gp, and so will not
3360 insert the nop which may be required. */
3361 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3364 macro_build (p
, counter
, ep
,
3365 ((bfd_arch_bits_per_address (stdoutput
) == 32
3366 || mips_opts
.isa
< 3)
3368 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3370 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3372 macro_build (p
, counter
, ep
,
3373 ((bfd_arch_bits_per_address (stdoutput
) == 32
3374 || mips_opts
.isa
< 3)
3375 ? "addiu" : "daddiu"),
3376 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3377 if (ex
.X_add_number
!= 0)
3379 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3380 as_bad ("PIC code offset overflow (max 16 signed bits)");
3381 ex
.X_op
= O_constant
;
3382 macro_build ((char *) NULL
, counter
, &ex
,
3383 ((bfd_arch_bits_per_address (stdoutput
) == 32
3384 || mips_opts
.isa
< 3)
3385 ? "addiu" : "daddiu"),
3386 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3389 else if (mips_pic
== EMBEDDED_PIC
)
3392 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3394 macro_build ((char *) NULL
, counter
, ep
,
3395 ((bfd_arch_bits_per_address (stdoutput
) == 32
3396 || mips_opts
.isa
< 3)
3397 ? "addiu" : "daddiu"),
3398 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3406 * This routine implements the seemingly endless macro or synthesized
3407 * instructions and addressing modes in the mips assembly language. Many
3408 * of these macros are simple and are similar to each other. These could
3409 * probably be handled by some kind of table or grammer aproach instead of
3410 * this verbose method. Others are not simple macros but are more like
3411 * optimizing code generation.
3412 * One interesting optimization is when several store macros appear
3413 * consecutivly that would load AT with the upper half of the same address.
3414 * The ensuing load upper instructions are ommited. This implies some kind
3415 * of global optimization. We currently only optimize within a single macro.
3416 * For many of the load and store macros if the address is specified as a
3417 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3418 * first load register 'at' with zero and use it as the base register. The
3419 * mips assembler simply uses register $zero. Just one tiny optimization
3424 struct mips_cl_insn
*ip
;
3426 register int treg
, sreg
, dreg
, breg
;
3441 bfd_reloc_code_real_type r
;
3443 int hold_mips_optimize
;
3445 assert (! mips_opts
.mips16
);
3447 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3448 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3449 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3450 mask
= ip
->insn_mo
->mask
;
3452 expr1
.X_op
= O_constant
;
3453 expr1
.X_op_symbol
= NULL
;
3454 expr1
.X_add_symbol
= NULL
;
3455 expr1
.X_add_number
= 1;
3467 mips_emit_delays (true);
3468 ++mips_opts
.noreorder
;
3469 mips_any_noreorder
= 1;
3471 expr1
.X_add_number
= 8;
3472 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3474 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3476 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3477 macro_build ((char *) NULL
, &icnt
, NULL
,
3478 dbl
? "dsub" : "sub",
3479 "d,v,t", dreg
, 0, sreg
);
3481 --mips_opts
.noreorder
;
3502 if (imm_expr
.X_op
== O_constant
3503 && imm_expr
.X_add_number
>= -0x8000
3504 && imm_expr
.X_add_number
< 0x8000)
3506 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3507 (int) BFD_RELOC_LO16
);
3510 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3511 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3530 if (imm_expr
.X_op
== O_constant
3531 && imm_expr
.X_add_number
>= 0
3532 && imm_expr
.X_add_number
< 0x10000)
3534 if (mask
!= M_NOR_I
)
3535 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3536 sreg
, (int) BFD_RELOC_LO16
);
3539 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3540 treg
, sreg
, (int) BFD_RELOC_LO16
);
3541 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3547 load_register (&icnt
, AT
, &imm_expr
, 0);
3548 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3565 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3567 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3571 load_register (&icnt
, AT
, &imm_expr
, 0);
3572 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3580 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3581 likely
? "bgezl" : "bgez",
3587 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3588 likely
? "blezl" : "blez",
3592 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3593 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3594 likely
? "beql" : "beq",
3601 /* check for > max integer */
3602 maxnum
= 0x7fffffff;
3603 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3610 if (imm_expr
.X_op
== O_constant
3611 && imm_expr
.X_add_number
>= maxnum
3612 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3615 /* result is always false */
3618 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3619 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3623 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3624 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3629 if (imm_expr
.X_op
!= O_constant
)
3630 as_bad ("Unsupported large constant");
3631 imm_expr
.X_add_number
++;
3635 if (mask
== M_BGEL_I
)
3637 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3639 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3640 likely
? "bgezl" : "bgez",
3644 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3646 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3647 likely
? "bgtzl" : "bgtz",
3651 maxnum
= 0x7fffffff;
3652 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3659 maxnum
= - maxnum
- 1;
3660 if (imm_expr
.X_op
== O_constant
3661 && imm_expr
.X_add_number
<= maxnum
3662 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3665 /* result is always true */
3666 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3667 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3670 set_at (&icnt
, sreg
, 0);
3671 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3672 likely
? "beql" : "beq",
3683 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3684 likely
? "beql" : "beq",
3688 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3690 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3691 likely
? "beql" : "beq",
3699 || (mips_opts
.isa
< 3
3700 && imm_expr
.X_op
== O_constant
3701 && imm_expr
.X_add_number
== 0xffffffff))
3703 if (imm_expr
.X_op
!= O_constant
)
3704 as_bad ("Unsupported large constant");
3705 imm_expr
.X_add_number
++;
3709 if (mask
== M_BGEUL_I
)
3711 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3713 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3715 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3716 likely
? "bnel" : "bne",
3720 set_at (&icnt
, sreg
, 1);
3721 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3722 likely
? "beql" : "beq",
3731 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3732 likely
? "bgtzl" : "bgtz",
3738 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3739 likely
? "bltzl" : "bltz",
3743 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3744 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3745 likely
? "bnel" : "bne",
3754 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3755 likely
? "bnel" : "bne",
3761 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3763 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3764 likely
? "bnel" : "bne",
3773 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3774 likely
? "blezl" : "blez",
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3781 likely
? "bgezl" : "bgez",
3785 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3786 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3787 likely
? "beql" : "beq",
3794 maxnum
= 0x7fffffff;
3795 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3802 if (imm_expr
.X_op
== O_constant
3803 && imm_expr
.X_add_number
>= maxnum
3804 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3806 if (imm_expr
.X_op
!= O_constant
)
3807 as_bad ("Unsupported large constant");
3808 imm_expr
.X_add_number
++;
3812 if (mask
== M_BLTL_I
)
3814 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3816 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3817 likely
? "bltzl" : "bltz",
3821 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3823 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3824 likely
? "blezl" : "blez",
3828 set_at (&icnt
, sreg
, 0);
3829 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3830 likely
? "bnel" : "bne",
3839 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3840 likely
? "beql" : "beq",
3846 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3848 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3849 likely
? "beql" : "beq",
3857 || (mips_opts
.isa
< 3
3858 && imm_expr
.X_op
== O_constant
3859 && imm_expr
.X_add_number
== 0xffffffff))
3861 if (imm_expr
.X_op
!= O_constant
)
3862 as_bad ("Unsupported large constant");
3863 imm_expr
.X_add_number
++;
3867 if (mask
== M_BLTUL_I
)
3869 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3871 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3873 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3874 likely
? "beql" : "beq",
3878 set_at (&icnt
, sreg
, 1);
3879 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3880 likely
? "bnel" : "bne",
3889 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3890 likely
? "bltzl" : "bltz",
3896 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3897 likely
? "bgtzl" : "bgtz",
3901 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3903 likely
? "bnel" : "bne",
3914 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3915 likely
? "bnel" : "bne",
3919 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3921 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3922 likely
? "bnel" : "bne",
3938 as_warn ("Divide by zero.");
3940 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3942 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3946 mips_emit_delays (true);
3947 ++mips_opts
.noreorder
;
3948 mips_any_noreorder
= 1;
3951 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3952 macro_build ((char *) NULL
, &icnt
, NULL
,
3953 dbl
? "ddiv" : "div",
3954 "z,s,t", sreg
, treg
);
3958 expr1
.X_add_number
= 8;
3959 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3960 macro_build ((char *) NULL
, &icnt
, NULL
,
3961 dbl
? "ddiv" : "div",
3962 "z,s,t", sreg
, treg
);
3963 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3965 expr1
.X_add_number
= -1;
3966 macro_build ((char *) NULL
, &icnt
, &expr1
,
3967 dbl
? "daddiu" : "addiu",
3968 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3969 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3970 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3973 expr1
.X_add_number
= 1;
3974 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3975 (int) BFD_RELOC_LO16
);
3976 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3981 expr1
.X_add_number
= 0x80000000;
3982 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3983 (int) BFD_RELOC_HI16
);
3986 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3989 expr1
.X_add_number
= 8;
3990 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3991 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3992 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3994 --mips_opts
.noreorder
;
3995 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4034 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4036 as_warn ("Divide by zero.");
4038 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4040 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4043 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4045 if (strcmp (s2
, "mflo") == 0)
4046 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4049 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4052 if (imm_expr
.X_op
== O_constant
4053 && imm_expr
.X_add_number
== -1
4054 && s
[strlen (s
) - 1] != 'u')
4056 if (strcmp (s2
, "mflo") == 0)
4059 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4062 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4066 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4070 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4071 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4072 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4091 mips_emit_delays (true);
4092 ++mips_opts
.noreorder
;
4093 mips_any_noreorder
= 1;
4096 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4097 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4101 expr1
.X_add_number
= 8;
4102 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4104 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4106 --mips_opts
.noreorder
;
4107 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4113 /* Load the address of a symbol into a register. If breg is not
4114 zero, we then add a base register to it. */
4116 /* When generating embedded PIC code, we permit expressions of
4119 where bar is an address in the .text section. These are used
4120 when getting the addresses of functions. We don't permit
4121 X_add_number to be non-zero, because if the symbol is
4122 external the relaxing code needs to know that any addend is
4123 purely the offset to X_op_symbol. */
4124 if (mips_pic
== EMBEDDED_PIC
4125 && offset_expr
.X_op
== O_subtract
4126 && now_seg
== text_section
4127 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4128 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4129 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4130 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4131 ->sy_value
.X_add_symbol
)
4134 && offset_expr
.X_add_number
== 0)
4136 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4137 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4138 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4139 ((bfd_arch_bits_per_address (stdoutput
) == 32
4140 || mips_opts
.isa
< 3)
4141 ? "addiu" : "daddiu"),
4142 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4146 if (offset_expr
.X_op
!= O_symbol
4147 && offset_expr
.X_op
!= O_constant
)
4149 as_bad ("expression too complex");
4150 offset_expr
.X_op
= O_constant
;
4164 if (offset_expr
.X_op
== O_constant
)
4165 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4166 else if (mips_pic
== NO_PIC
)
4168 /* If this is a reference to an GP relative symbol, we want
4169 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4171 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4172 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4173 If we have a constant, we need two instructions anyhow,
4174 so we may as well always use the latter form. */
4175 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4176 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4181 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4182 ((bfd_arch_bits_per_address (stdoutput
) == 32
4183 || mips_opts
.isa
< 3)
4184 ? "addiu" : "daddiu"),
4185 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4186 p
= frag_var (rs_machine_dependent
, 8, 0,
4187 RELAX_ENCODE (4, 8, 0, 4, 0,
4188 mips_opts
.warn_about_macros
),
4189 offset_expr
.X_add_symbol
, (offsetT
) 0,
4192 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4195 macro_build (p
, &icnt
, &offset_expr
,
4196 ((bfd_arch_bits_per_address (stdoutput
) == 32
4197 || mips_opts
.isa
< 3)
4198 ? "addiu" : "daddiu"),
4199 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4201 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4203 /* If this is a reference to an external symbol, and there
4204 is no constant, we want
4205 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4206 For a local symbol, we want
4207 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4209 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4211 If we have a small constant, and this is a reference to
4212 an external symbol, we want
4213 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4215 addiu $tempreg,$tempreg,<constant>
4216 For a local symbol, we want the same instruction
4217 sequence, but we output a BFD_RELOC_LO16 reloc on the
4220 If we have a large constant, and this is a reference to
4221 an external symbol, we want
4222 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4223 lui $at,<hiconstant>
4224 addiu $at,$at,<loconstant>
4225 addu $tempreg,$tempreg,$at
4226 For a local symbol, we want the same instruction
4227 sequence, but we output a BFD_RELOC_LO16 reloc on the
4228 addiu instruction. */
4229 expr1
.X_add_number
= offset_expr
.X_add_number
;
4230 offset_expr
.X_add_number
= 0;
4232 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4234 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4235 if (expr1
.X_add_number
== 0)
4243 /* We're going to put in an addu instruction using
4244 tempreg, so we may as well insert the nop right
4246 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4250 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4251 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4253 ? mips_opts
.warn_about_macros
4255 offset_expr
.X_add_symbol
, (offsetT
) 0,
4259 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4262 macro_build (p
, &icnt
, &expr1
,
4263 ((bfd_arch_bits_per_address (stdoutput
) == 32
4264 || mips_opts
.isa
< 3)
4265 ? "addiu" : "daddiu"),
4266 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4267 /* FIXME: If breg == 0, and the next instruction uses
4268 $tempreg, then if this variant case is used an extra
4269 nop will be generated. */
4271 else if (expr1
.X_add_number
>= -0x8000
4272 && expr1
.X_add_number
< 0x8000)
4274 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4276 macro_build ((char *) NULL
, &icnt
, &expr1
,
4277 ((bfd_arch_bits_per_address (stdoutput
) == 32
4278 || mips_opts
.isa
< 3)
4279 ? "addiu" : "daddiu"),
4280 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4281 (void) frag_var (rs_machine_dependent
, 0, 0,
4282 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4283 offset_expr
.X_add_symbol
, (offsetT
) 0,
4290 /* If we are going to add in a base register, and the
4291 target register and the base register are the same,
4292 then we are using AT as a temporary register. Since
4293 we want to load the constant into AT, we add our
4294 current AT (from the global offset table) and the
4295 register into the register now, and pretend we were
4296 not using a base register. */
4301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4303 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4304 ((bfd_arch_bits_per_address (stdoutput
) == 32
4305 || mips_opts
.isa
< 3)
4306 ? "addu" : "daddu"),
4307 "d,v,t", treg
, AT
, breg
);
4313 /* Set mips_optimize around the lui instruction to avoid
4314 inserting an unnecessary nop after the lw. */
4315 hold_mips_optimize
= mips_optimize
;
4317 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4318 mips_optimize
= hold_mips_optimize
;
4320 macro_build ((char *) NULL
, &icnt
, &expr1
,
4321 ((bfd_arch_bits_per_address (stdoutput
) == 32
4322 || mips_opts
.isa
< 3)
4323 ? "addiu" : "daddiu"),
4324 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4325 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4326 ((bfd_arch_bits_per_address (stdoutput
) == 32
4327 || mips_opts
.isa
< 3)
4328 ? "addu" : "daddu"),
4329 "d,v,t", tempreg
, tempreg
, AT
);
4330 (void) frag_var (rs_machine_dependent
, 0, 0,
4331 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4332 offset_expr
.X_add_symbol
, (offsetT
) 0,
4337 else if (mips_pic
== SVR4_PIC
)
4341 /* This is the large GOT case. If this is a reference to an
4342 external symbol, and there is no constant, we want
4343 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4344 addu $tempreg,$tempreg,$gp
4345 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4346 For a local symbol, we want
4347 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4349 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4351 If we have a small constant, and this is a reference to
4352 an external symbol, we want
4353 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4354 addu $tempreg,$tempreg,$gp
4355 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4357 addiu $tempreg,$tempreg,<constant>
4358 For a local symbol, we want
4359 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4361 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4363 If we have a large constant, and this is a reference to
4364 an external symbol, we want
4365 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4366 addu $tempreg,$tempreg,$gp
4367 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4368 lui $at,<hiconstant>
4369 addiu $at,$at,<loconstant>
4370 addu $tempreg,$tempreg,$at
4371 For a local symbol, we want
4372 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4373 lui $at,<hiconstant>
4374 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4375 addu $tempreg,$tempreg,$at
4377 expr1
.X_add_number
= offset_expr
.X_add_number
;
4378 offset_expr
.X_add_number
= 0;
4380 if (reg_needs_delay (GP
))
4384 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4385 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4386 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4387 ((bfd_arch_bits_per_address (stdoutput
) == 32
4388 || mips_opts
.isa
< 3)
4389 ? "addu" : "daddu"),
4390 "d,v,t", tempreg
, tempreg
, GP
);
4391 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4393 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4395 if (expr1
.X_add_number
== 0)
4403 /* We're going to put in an addu instruction using
4404 tempreg, so we may as well insert the nop right
4406 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4411 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4412 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4415 ? mips_opts
.warn_about_macros
4417 offset_expr
.X_add_symbol
, (offsetT
) 0,
4420 else if (expr1
.X_add_number
>= -0x8000
4421 && expr1
.X_add_number
< 0x8000)
4423 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4425 macro_build ((char *) NULL
, &icnt
, &expr1
,
4426 ((bfd_arch_bits_per_address (stdoutput
) == 32
4427 || mips_opts
.isa
< 3)
4428 ? "addiu" : "daddiu"),
4429 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4431 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4432 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4434 ? mips_opts
.warn_about_macros
4436 offset_expr
.X_add_symbol
, (offsetT
) 0,
4443 /* If we are going to add in a base register, and the
4444 target register and the base register are the same,
4445 then we are using AT as a temporary register. Since
4446 we want to load the constant into AT, we add our
4447 current AT (from the global offset table) and the
4448 register into the register now, and pretend we were
4449 not using a base register. */
4457 assert (tempreg
== AT
);
4458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4461 ((bfd_arch_bits_per_address (stdoutput
) == 32
4462 || mips_opts
.isa
< 3)
4463 ? "addu" : "daddu"),
4464 "d,v,t", treg
, AT
, breg
);
4469 /* Set mips_optimize around the lui instruction to avoid
4470 inserting an unnecessary nop after the lw. */
4471 hold_mips_optimize
= mips_optimize
;
4473 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4474 mips_optimize
= hold_mips_optimize
;
4476 macro_build ((char *) NULL
, &icnt
, &expr1
,
4477 ((bfd_arch_bits_per_address (stdoutput
) == 32
4478 || mips_opts
.isa
< 3)
4479 ? "addiu" : "daddiu"),
4480 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4482 ((bfd_arch_bits_per_address (stdoutput
) == 32
4483 || mips_opts
.isa
< 3)
4484 ? "addu" : "daddu"),
4485 "d,v,t", dreg
, dreg
, AT
);
4487 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4488 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4491 ? mips_opts
.warn_about_macros
4493 offset_expr
.X_add_symbol
, (offsetT
) 0,
4501 /* This is needed because this instruction uses $gp, but
4502 the first instruction on the main stream does not. */
4503 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4506 macro_build (p
, &icnt
, &offset_expr
,
4508 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4510 if (expr1
.X_add_number
>= -0x8000
4511 && expr1
.X_add_number
< 0x8000)
4513 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4515 macro_build (p
, &icnt
, &expr1
,
4516 ((bfd_arch_bits_per_address (stdoutput
) == 32
4517 || mips_opts
.isa
< 3)
4518 ? "addiu" : "daddiu"),
4519 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4520 /* FIXME: If add_number is 0, and there was no base
4521 register, the external symbol case ended with a load,
4522 so if the symbol turns out to not be external, and
4523 the next instruction uses tempreg, an unnecessary nop
4524 will be inserted. */
4530 /* We must add in the base register now, as in the
4531 external symbol case. */
4532 assert (tempreg
== AT
);
4533 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4535 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4536 ((bfd_arch_bits_per_address (stdoutput
) == 32
4537 || mips_opts
.isa
< 3)
4538 ? "addu" : "daddu"),
4539 "d,v,t", treg
, AT
, breg
);
4542 /* We set breg to 0 because we have arranged to add
4543 it in in both cases. */
4547 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4549 macro_build (p
, &icnt
, &expr1
,
4550 ((bfd_arch_bits_per_address (stdoutput
) == 32
4551 || mips_opts
.isa
< 3)
4552 ? "addiu" : "daddiu"),
4553 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4555 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4556 ((bfd_arch_bits_per_address (stdoutput
) == 32
4557 || mips_opts
.isa
< 3)
4558 ? "addu" : "daddu"),
4559 "d,v,t", tempreg
, tempreg
, AT
);
4563 else if (mips_pic
== EMBEDDED_PIC
)
4566 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4568 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4569 ((bfd_arch_bits_per_address (stdoutput
) == 32
4570 || mips_opts
.isa
< 3)
4571 ? "addiu" : "daddiu"),
4572 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4578 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4579 ((bfd_arch_bits_per_address (stdoutput
) == 32
4580 || mips_opts
.isa
< 3)
4581 ? "addu" : "daddu"),
4582 "d,v,t", treg
, tempreg
, breg
);
4590 /* The j instruction may not be used in PIC code, since it
4591 requires an absolute address. We convert it to a b
4593 if (mips_pic
== NO_PIC
)
4594 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4596 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4599 /* The jal instructions must be handled as macros because when
4600 generating PIC code they expand to multi-instruction
4601 sequences. Normally they are simple instructions. */
4606 if (mips_pic
== NO_PIC
4607 || mips_pic
== EMBEDDED_PIC
)
4608 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4610 else if (mips_pic
== SVR4_PIC
)
4612 if (sreg
!= PIC_CALL_REG
)
4613 as_warn ("MIPS PIC call to register other than $25");
4615 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4617 if (mips_cprestore_offset
< 0)
4618 as_warn ("No .cprestore pseudo-op used in PIC code");
4621 expr1
.X_add_number
= mips_cprestore_offset
;
4622 macro_build ((char *) NULL
, &icnt
, &expr1
,
4623 ((bfd_arch_bits_per_address (stdoutput
) == 32
4624 || mips_opts
.isa
< 3)
4626 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4635 if (mips_pic
== NO_PIC
)
4636 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4637 else if (mips_pic
== SVR4_PIC
)
4639 /* If this is a reference to an external symbol, and we are
4640 using a small GOT, we want
4641 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4645 lw $gp,cprestore($sp)
4646 The cprestore value is set using the .cprestore
4647 pseudo-op. If we are using a big GOT, we want
4648 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4650 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4654 lw $gp,cprestore($sp)
4655 If the symbol is not external, we want
4656 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4658 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4661 lw $gp,cprestore($sp) */
4665 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4666 ((bfd_arch_bits_per_address (stdoutput
) == 32
4667 || mips_opts
.isa
< 3)
4669 "t,o(b)", PIC_CALL_REG
,
4670 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4673 p
= frag_var (rs_machine_dependent
, 4, 0,
4674 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4675 offset_expr
.X_add_symbol
, (offsetT
) 0,
4682 if (reg_needs_delay (GP
))
4686 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4687 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4688 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4689 ((bfd_arch_bits_per_address (stdoutput
) == 32
4690 || mips_opts
.isa
< 3)
4691 ? "addu" : "daddu"),
4692 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4693 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4694 ((bfd_arch_bits_per_address (stdoutput
) == 32
4695 || mips_opts
.isa
< 3)
4697 "t,o(b)", PIC_CALL_REG
,
4698 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4701 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4702 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4704 offset_expr
.X_add_symbol
, (offsetT
) 0,
4708 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4711 macro_build (p
, &icnt
, &offset_expr
,
4712 ((bfd_arch_bits_per_address (stdoutput
) == 32
4713 || mips_opts
.isa
< 3)
4715 "t,o(b)", PIC_CALL_REG
,
4716 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4718 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4721 macro_build (p
, &icnt
, &offset_expr
,
4722 ((bfd_arch_bits_per_address (stdoutput
) == 32
4723 || mips_opts
.isa
< 3)
4724 ? "addiu" : "daddiu"),
4725 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4726 (int) BFD_RELOC_LO16
);
4727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4728 "jalr", "s", PIC_CALL_REG
);
4729 if (mips_cprestore_offset
< 0)
4730 as_warn ("No .cprestore pseudo-op used in PIC code");
4733 if (mips_opts
.noreorder
)
4734 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4736 expr1
.X_add_number
= mips_cprestore_offset
;
4737 macro_build ((char *) NULL
, &icnt
, &expr1
,
4738 ((bfd_arch_bits_per_address (stdoutput
) == 32
4739 || mips_opts
.isa
< 3)
4741 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4745 else if (mips_pic
== EMBEDDED_PIC
)
4747 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4748 /* The linker may expand the call to a longer sequence which
4749 uses $at, so we must break rather than return. */
4774 /* Itbl support may require additional care here. */
4779 /* Itbl support may require additional care here. */
4784 /* Itbl support may require additional care here. */
4789 /* Itbl support may require additional care here. */
4803 as_bad ("opcode not supported on this processor");
4807 /* Itbl support may require additional care here. */
4812 /* Itbl support may require additional care here. */
4817 /* Itbl support may require additional care here. */
4837 if (breg
== treg
|| coproc
|| lr
)
4859 /* Itbl support may require additional care here. */
4864 /* Itbl support may require additional care here. */
4869 /* Itbl support may require additional care here. */
4874 /* Itbl support may require additional care here. */
4892 as_bad ("opcode not supported on this processor");
4897 /* Itbl support may require additional care here. */
4901 /* Itbl support may require additional care here. */
4906 /* Itbl support may require additional care here. */
4918 /* Itbl support may require additional care here. */
4919 if (mask
== M_LWC1_AB
4920 || mask
== M_SWC1_AB
4921 || mask
== M_LDC1_AB
4922 || mask
== M_SDC1_AB
4931 if (offset_expr
.X_op
!= O_constant
4932 && offset_expr
.X_op
!= O_symbol
)
4934 as_bad ("expression too complex");
4935 offset_expr
.X_op
= O_constant
;
4938 /* A constant expression in PIC code can be handled just as it
4939 is in non PIC code. */
4940 if (mips_pic
== NO_PIC
4941 || offset_expr
.X_op
== O_constant
)
4943 /* If this is a reference to a GP relative symbol, and there
4944 is no base register, we want
4945 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4946 Otherwise, if there is no base register, we want
4947 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4948 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4949 If we have a constant, we need two instructions anyhow,
4950 so we always use the latter form.
4952 If we have a base register, and this is a reference to a
4953 GP relative symbol, we want
4954 addu $tempreg,$breg,$gp
4955 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4957 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4958 addu $tempreg,$tempreg,$breg
4959 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4960 With a constant we always use the latter case. */
4963 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4964 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4969 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4970 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4971 p
= frag_var (rs_machine_dependent
, 8, 0,
4972 RELAX_ENCODE (4, 8, 0, 4, 0,
4973 (mips_opts
.warn_about_macros
4975 && mips_opts
.noat
))),
4976 offset_expr
.X_add_symbol
, (offsetT
) 0,
4980 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4983 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4984 (int) BFD_RELOC_LO16
, tempreg
);
4988 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4989 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4995 ((bfd_arch_bits_per_address (stdoutput
) == 32
4996 || mips_opts
.isa
< 3)
4997 ? "addu" : "daddu"),
4998 "d,v,t", tempreg
, breg
, GP
);
4999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5000 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5001 p
= frag_var (rs_machine_dependent
, 12, 0,
5002 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5003 offset_expr
.X_add_symbol
, (offsetT
) 0,
5006 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5009 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5010 ((bfd_arch_bits_per_address (stdoutput
) == 32
5011 || mips_opts
.isa
< 3)
5012 ? "addu" : "daddu"),
5013 "d,v,t", tempreg
, tempreg
, breg
);
5016 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5017 (int) BFD_RELOC_LO16
, tempreg
);
5020 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5022 /* If this is a reference to an external symbol, we want
5023 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5025 <op> $treg,0($tempreg)
5027 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5029 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5030 <op> $treg,0($tempreg)
5031 If there is a base register, we add it to $tempreg before
5032 the <op>. If there is a constant, we stick it in the
5033 <op> instruction. We don't handle constants larger than
5034 16 bits, because we have no way to load the upper 16 bits
5035 (actually, we could handle them for the subset of cases
5036 in which we are not using $at). */
5037 assert (offset_expr
.X_op
== O_symbol
);
5038 expr1
.X_add_number
= offset_expr
.X_add_number
;
5039 offset_expr
.X_add_number
= 0;
5040 if (expr1
.X_add_number
< -0x8000
5041 || expr1
.X_add_number
>= 0x8000)
5042 as_bad ("PIC code offset overflow (max 16 signed bits)");
5044 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5045 ((bfd_arch_bits_per_address (stdoutput
) == 32
5046 || mips_opts
.isa
< 3)
5048 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5049 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5050 p
= frag_var (rs_machine_dependent
, 4, 0,
5051 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5052 offset_expr
.X_add_symbol
, (offsetT
) 0,
5054 macro_build (p
, &icnt
, &offset_expr
,
5055 ((bfd_arch_bits_per_address (stdoutput
) == 32
5056 || mips_opts
.isa
< 3)
5057 ? "addiu" : "daddiu"),
5058 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5060 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5061 ((bfd_arch_bits_per_address (stdoutput
) == 32
5062 || mips_opts
.isa
< 3)
5063 ? "addu" : "daddu"),
5064 "d,v,t", tempreg
, tempreg
, breg
);
5065 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5066 (int) BFD_RELOC_LO16
, tempreg
);
5068 else if (mips_pic
== SVR4_PIC
)
5072 /* If this is a reference to an external symbol, we want
5073 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5074 addu $tempreg,$tempreg,$gp
5075 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5076 <op> $treg,0($tempreg)
5078 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5080 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5081 <op> $treg,0($tempreg)
5082 If there is a base register, we add it to $tempreg before
5083 the <op>. If there is a constant, we stick it in the
5084 <op> instruction. We don't handle constants larger than
5085 16 bits, because we have no way to load the upper 16 bits
5086 (actually, we could handle them for the subset of cases
5087 in which we are not using $at). */
5088 assert (offset_expr
.X_op
== O_symbol
);
5089 expr1
.X_add_number
= offset_expr
.X_add_number
;
5090 offset_expr
.X_add_number
= 0;
5091 if (expr1
.X_add_number
< -0x8000
5092 || expr1
.X_add_number
>= 0x8000)
5093 as_bad ("PIC code offset overflow (max 16 signed bits)");
5094 if (reg_needs_delay (GP
))
5099 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5100 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5101 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5102 ((bfd_arch_bits_per_address (stdoutput
) == 32
5103 || mips_opts
.isa
< 3)
5104 ? "addu" : "daddu"),
5105 "d,v,t", tempreg
, tempreg
, GP
);
5106 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5107 ((bfd_arch_bits_per_address (stdoutput
) == 32
5108 || mips_opts
.isa
< 3)
5110 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5112 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5113 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5114 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5117 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5120 macro_build (p
, &icnt
, &offset_expr
,
5121 ((bfd_arch_bits_per_address (stdoutput
) == 32
5122 || mips_opts
.isa
< 3)
5124 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5126 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5128 macro_build (p
, &icnt
, &offset_expr
,
5129 ((bfd_arch_bits_per_address (stdoutput
) == 32
5130 || mips_opts
.isa
< 3)
5131 ? "addiu" : "daddiu"),
5132 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5134 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5135 ((bfd_arch_bits_per_address (stdoutput
) == 32
5136 || mips_opts
.isa
< 3)
5137 ? "addu" : "daddu"),
5138 "d,v,t", tempreg
, tempreg
, breg
);
5139 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5140 (int) BFD_RELOC_LO16
, tempreg
);
5142 else if (mips_pic
== EMBEDDED_PIC
)
5144 /* If there is no base register, we want
5145 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5146 If there is a base register, we want
5147 addu $tempreg,$breg,$gp
5148 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5150 assert (offset_expr
.X_op
== O_symbol
);
5153 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5154 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5160 ((bfd_arch_bits_per_address (stdoutput
) == 32
5161 || mips_opts
.isa
< 3)
5162 ? "addu" : "daddu"),
5163 "d,v,t", tempreg
, breg
, GP
);
5164 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5165 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5178 load_register (&icnt
, treg
, &imm_expr
, 0);
5182 load_register (&icnt
, treg
, &imm_expr
, 1);
5186 if (imm_expr
.X_op
== O_constant
)
5188 load_register (&icnt
, AT
, &imm_expr
, 0);
5189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5190 "mtc1", "t,G", AT
, treg
);
5195 assert (offset_expr
.X_op
== O_symbol
5196 && strcmp (segment_name (S_GET_SEGMENT
5197 (offset_expr
.X_add_symbol
)),
5199 && offset_expr
.X_add_number
== 0);
5200 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5201 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5206 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5207 the entire value, and in mips1 mode it is the high order 32
5208 bits of the value and the low order 32 bits are either zero
5209 or in offset_expr. */
5210 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5212 if (mips_opts
.isa
>= 3)
5213 load_register (&icnt
, treg
, &imm_expr
, 1);
5218 if (target_big_endian
)
5230 load_register (&icnt
, hreg
, &imm_expr
, 0);
5233 if (offset_expr
.X_op
== O_absent
)
5234 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5238 assert (offset_expr
.X_op
== O_constant
);
5239 load_register (&icnt
, lreg
, &offset_expr
, 0);
5246 /* We know that sym is in the .rdata section. First we get the
5247 upper 16 bits of the address. */
5248 if (mips_pic
== NO_PIC
)
5250 /* FIXME: This won't work for a 64 bit address. */
5251 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5253 else if (mips_pic
== SVR4_PIC
)
5255 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5256 ((bfd_arch_bits_per_address (stdoutput
) == 32
5257 || mips_opts
.isa
< 3)
5259 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5261 else if (mips_pic
== EMBEDDED_PIC
)
5263 /* For embedded PIC we pick up the entire address off $gp in
5264 a single instruction. */
5265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5266 ((bfd_arch_bits_per_address (stdoutput
) == 32
5267 || mips_opts
.isa
< 3)
5268 ? "addiu" : "daddiu"),
5269 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5270 offset_expr
.X_op
= O_constant
;
5271 offset_expr
.X_add_number
= 0;
5276 /* Now we load the register(s). */
5277 if (mips_opts
.isa
>= 3)
5278 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5279 treg
, (int) BFD_RELOC_LO16
, AT
);
5282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5283 treg
, (int) BFD_RELOC_LO16
, AT
);
5286 /* FIXME: How in the world do we deal with the possible
5288 offset_expr
.X_add_number
+= 4;
5289 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5290 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5294 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5295 does not become a variant frag. */
5296 frag_wane (frag_now
);
5302 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5303 the entire value, and in mips1 mode it is the high order 32
5304 bits of the value and the low order 32 bits are either zero
5305 or in offset_expr. */
5306 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5308 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5309 if (mips_opts
.isa
>= 3)
5310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5311 "dmtc1", "t,S", AT
, treg
);
5314 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5315 "mtc1", "t,G", AT
, treg
+ 1);
5316 if (offset_expr
.X_op
== O_absent
)
5317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5318 "mtc1", "t,G", 0, treg
);
5321 assert (offset_expr
.X_op
== O_constant
);
5322 load_register (&icnt
, AT
, &offset_expr
, 0);
5323 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5324 "mtc1", "t,G", AT
, treg
);
5330 assert (offset_expr
.X_op
== O_symbol
5331 && offset_expr
.X_add_number
== 0);
5332 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5333 if (strcmp (s
, ".lit8") == 0)
5335 if (mips_opts
.isa
>= 2)
5337 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5338 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5342 r
= BFD_RELOC_MIPS_LITERAL
;
5347 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5348 if (mips_pic
== SVR4_PIC
)
5349 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5350 ((bfd_arch_bits_per_address (stdoutput
) == 32
5351 || mips_opts
.isa
< 3)
5353 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5356 /* FIXME: This won't work for a 64 bit address. */
5357 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5360 if (mips_opts
.isa
>= 2)
5362 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5363 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5365 /* To avoid confusion in tc_gen_reloc, we must ensure
5366 that this does not become a variant frag. */
5367 frag_wane (frag_now
);
5380 as_bad ("opcode not supported on this processor");
5383 /* Even on a big endian machine $fn comes before $fn+1. We have
5384 to adjust when loading from memory. */
5387 assert (mips_opts
.isa
< 2);
5388 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5389 target_big_endian
? treg
+ 1 : treg
,
5391 /* FIXME: A possible overflow which I don't know how to deal
5393 offset_expr
.X_add_number
+= 4;
5394 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5395 target_big_endian
? treg
: treg
+ 1,
5398 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5399 does not become a variant frag. */
5400 frag_wane (frag_now
);
5409 * The MIPS assembler seems to check for X_add_number not
5410 * being double aligned and generating:
5413 * addiu at,at,%lo(foo+1)
5416 * But, the resulting address is the same after relocation so why
5417 * generate the extra instruction?
5421 as_bad ("opcode not supported on this processor");
5424 /* Itbl support may require additional care here. */
5426 if (mips_opts
.isa
>= 2)
5439 as_bad ("opcode not supported on this processor");
5443 if (mips_opts
.isa
>= 2)
5451 /* Itbl support may require additional care here. */
5456 if (mips_opts
.isa
>= 3)
5467 if (mips_opts
.isa
>= 3)
5477 if (offset_expr
.X_op
!= O_symbol
5478 && offset_expr
.X_op
!= O_constant
)
5480 as_bad ("expression too complex");
5481 offset_expr
.X_op
= O_constant
;
5484 /* Even on a big endian machine $fn comes before $fn+1. We have
5485 to adjust when loading from memory. We set coproc if we must
5486 load $fn+1 first. */
5487 /* Itbl support may require additional care here. */
5488 if (! target_big_endian
)
5491 if (mips_pic
== NO_PIC
5492 || offset_expr
.X_op
== O_constant
)
5494 /* If this is a reference to a GP relative symbol, we want
5495 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5496 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5497 If we have a base register, we use this
5499 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5500 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5501 If this is not a GP relative symbol, we want
5502 lui $at,<sym> (BFD_RELOC_HI16_S)
5503 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5504 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5505 If there is a base register, we add it to $at after the
5506 lui instruction. If there is a constant, we always use
5508 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5509 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5529 ((bfd_arch_bits_per_address (stdoutput
) == 32
5530 || mips_opts
.isa
< 3)
5531 ? "addu" : "daddu"),
5532 "d,v,t", AT
, breg
, GP
);
5538 /* Itbl support may require additional care here. */
5539 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5540 coproc
? treg
+ 1 : treg
,
5541 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5542 offset_expr
.X_add_number
+= 4;
5544 /* Set mips_optimize to 2 to avoid inserting an
5546 hold_mips_optimize
= mips_optimize
;
5548 /* Itbl support may require additional care here. */
5549 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5550 coproc
? treg
: treg
+ 1,
5551 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5552 mips_optimize
= hold_mips_optimize
;
5554 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5555 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5556 used_at
&& mips_opts
.noat
),
5557 offset_expr
.X_add_symbol
, (offsetT
) 0,
5560 /* We just generated two relocs. When tc_gen_reloc
5561 handles this case, it will skip the first reloc and
5562 handle the second. The second reloc already has an
5563 extra addend of 4, which we added above. We must
5564 subtract it out, and then subtract another 4 to make
5565 the first reloc come out right. The second reloc
5566 will come out right because we are going to add 4 to
5567 offset_expr when we build its instruction below.
5569 If we have a symbol, then we don't want to include
5570 the offset, because it will wind up being included
5571 when we generate the reloc. */
5573 if (offset_expr
.X_op
== O_constant
)
5574 offset_expr
.X_add_number
-= 8;
5577 offset_expr
.X_add_number
= -4;
5578 offset_expr
.X_op
= O_constant
;
5581 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5586 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5587 ((bfd_arch_bits_per_address (stdoutput
) == 32
5588 || mips_opts
.isa
< 3)
5589 ? "addu" : "daddu"),
5590 "d,v,t", AT
, breg
, AT
);
5594 /* Itbl support may require additional care here. */
5595 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5596 coproc
? treg
+ 1 : treg
,
5597 (int) BFD_RELOC_LO16
, AT
);
5600 /* FIXME: How do we handle overflow here? */
5601 offset_expr
.X_add_number
+= 4;
5602 /* Itbl support may require additional care here. */
5603 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5604 coproc
? treg
: treg
+ 1,
5605 (int) BFD_RELOC_LO16
, AT
);
5607 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5611 /* If this is a reference to an external symbol, we want
5612 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5617 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5619 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5620 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5621 If there is a base register we add it to $at before the
5622 lwc1 instructions. If there is a constant we include it
5623 in the lwc1 instructions. */
5625 expr1
.X_add_number
= offset_expr
.X_add_number
;
5626 offset_expr
.X_add_number
= 0;
5627 if (expr1
.X_add_number
< -0x8000
5628 || expr1
.X_add_number
>= 0x8000 - 4)
5629 as_bad ("PIC code offset overflow (max 16 signed bits)");
5634 frag_grow (24 + off
);
5635 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5636 ((bfd_arch_bits_per_address (stdoutput
) == 32
5637 || mips_opts
.isa
< 3)
5639 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5640 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5642 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5643 ((bfd_arch_bits_per_address (stdoutput
) == 32
5644 || mips_opts
.isa
< 3)
5645 ? "addu" : "daddu"),
5646 "d,v,t", AT
, breg
, AT
);
5647 /* Itbl support may require additional care here. */
5648 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5649 coproc
? treg
+ 1 : treg
,
5650 (int) BFD_RELOC_LO16
, AT
);
5651 expr1
.X_add_number
+= 4;
5653 /* Set mips_optimize to 2 to avoid inserting an undesired
5655 hold_mips_optimize
= mips_optimize
;
5657 /* Itbl support may require additional care here. */
5658 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5659 coproc
? treg
: treg
+ 1,
5660 (int) BFD_RELOC_LO16
, AT
);
5661 mips_optimize
= hold_mips_optimize
;
5663 (void) frag_var (rs_machine_dependent
, 0, 0,
5664 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5665 offset_expr
.X_add_symbol
, (offsetT
) 0,
5668 else if (mips_pic
== SVR4_PIC
)
5672 /* If this is a reference to an external symbol, we want
5673 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5675 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5680 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5682 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5683 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5684 If there is a base register we add it to $at before the
5685 lwc1 instructions. If there is a constant we include it
5686 in the lwc1 instructions. */
5688 expr1
.X_add_number
= offset_expr
.X_add_number
;
5689 offset_expr
.X_add_number
= 0;
5690 if (expr1
.X_add_number
< -0x8000
5691 || expr1
.X_add_number
>= 0x8000 - 4)
5692 as_bad ("PIC code offset overflow (max 16 signed bits)");
5693 if (reg_needs_delay (GP
))
5702 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5703 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5704 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5705 ((bfd_arch_bits_per_address (stdoutput
) == 32
5706 || mips_opts
.isa
< 3)
5707 ? "addu" : "daddu"),
5708 "d,v,t", AT
, AT
, GP
);
5709 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5710 ((bfd_arch_bits_per_address (stdoutput
) == 32
5711 || mips_opts
.isa
< 3)
5713 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5714 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5716 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5717 ((bfd_arch_bits_per_address (stdoutput
) == 32
5718 || mips_opts
.isa
< 3)
5719 ? "addu" : "daddu"),
5720 "d,v,t", AT
, breg
, AT
);
5721 /* Itbl support may require additional care here. */
5722 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5723 coproc
? treg
+ 1 : treg
,
5724 (int) BFD_RELOC_LO16
, AT
);
5725 expr1
.X_add_number
+= 4;
5727 /* Set mips_optimize to 2 to avoid inserting an undesired
5729 hold_mips_optimize
= mips_optimize
;
5731 /* Itbl support may require additional care here. */
5732 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5733 coproc
? treg
: treg
+ 1,
5734 (int) BFD_RELOC_LO16
, AT
);
5735 mips_optimize
= hold_mips_optimize
;
5736 expr1
.X_add_number
-= 4;
5738 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5739 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5740 8 + gpdel
+ off
, 1, 0),
5741 offset_expr
.X_add_symbol
, (offsetT
) 0,
5745 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5748 macro_build (p
, &icnt
, &offset_expr
,
5749 ((bfd_arch_bits_per_address (stdoutput
) == 32
5750 || mips_opts
.isa
< 3)
5752 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5754 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5758 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5759 ((bfd_arch_bits_per_address (stdoutput
) == 32
5760 || mips_opts
.isa
< 3)
5761 ? "addu" : "daddu"),
5762 "d,v,t", AT
, breg
, AT
);
5765 /* Itbl support may require additional care here. */
5766 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5767 coproc
? treg
+ 1 : treg
,
5768 (int) BFD_RELOC_LO16
, AT
);
5770 expr1
.X_add_number
+= 4;
5772 /* Set mips_optimize to 2 to avoid inserting an undesired
5774 hold_mips_optimize
= mips_optimize
;
5776 /* Itbl support may require additional care here. */
5777 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5778 coproc
? treg
: treg
+ 1,
5779 (int) BFD_RELOC_LO16
, AT
);
5780 mips_optimize
= hold_mips_optimize
;
5782 else if (mips_pic
== EMBEDDED_PIC
)
5784 /* If there is no base register, we use
5785 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5786 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5787 If we have a base register, we use
5789 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5790 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5799 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5800 ((bfd_arch_bits_per_address (stdoutput
) == 32
5801 || mips_opts
.isa
< 3)
5802 ? "addu" : "daddu"),
5803 "d,v,t", AT
, breg
, GP
);
5808 /* Itbl support may require additional care here. */
5809 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5810 coproc
? treg
+ 1 : treg
,
5811 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5812 offset_expr
.X_add_number
+= 4;
5813 /* Itbl support may require additional care here. */
5814 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5815 coproc
? treg
: treg
+ 1,
5816 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5832 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
5833 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5834 (int) BFD_RELOC_LO16
, breg
);
5835 offset_expr
.X_add_number
+= 4;
5836 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5837 (int) BFD_RELOC_LO16
, breg
);
5840 /* New code added to support COPZ instructions.
5841 This code builds table entries out of the macros in mip_opcodes.
5842 R4000 uses interlocks to handle coproc delays.
5843 Other chips (like the R3000) require nops to be inserted for delays.
5845 FIXME: Currently, we require that the user handle delays.
5846 In order to fill delay slots for non-interlocked chips,
5847 we must have a way to specify delays based on the coprocessor.
5848 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5849 What are the side-effects of the cop instruction?
5850 What cache support might we have and what are its effects?
5851 Both coprocessor & memory require delays. how long???
5852 What registers are read/set/modified?
5854 If an itbl is provided to interpret cop instructions,
5855 this knowledge can be encoded in the itbl spec. */
5869 /* For now we just do C (same as Cz). The parameter will be
5870 stored in insn_opcode by mips_ip. */
5871 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5875 #ifdef LOSING_COMPILER
5877 /* Try and see if this is a new itbl instruction.
5878 This code builds table entries out of the macros in mip_opcodes.
5879 FIXME: For now we just assemble the expression and pass it's
5880 value along as a 32-bit immediate.
5881 We may want to have the assembler assemble this value,
5882 so that we gain the assembler's knowledge of delay slots,
5884 Would it be more efficient to use mask (id) here? */
5885 if (itbl_have_entries
5886 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5888 s
= ip
->insn_mo
->name
;
5890 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5891 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5898 as_warn ("Macro used $at after \".set noat\"");
5903 struct mips_cl_insn
*ip
;
5905 register int treg
, sreg
, dreg
, breg
;
5920 bfd_reloc_code_real_type r
;
5923 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5924 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5925 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5926 mask
= ip
->insn_mo
->mask
;
5928 expr1
.X_op
= O_constant
;
5929 expr1
.X_op_symbol
= NULL
;
5930 expr1
.X_add_symbol
= NULL
;
5931 expr1
.X_add_number
= 1;
5935 #endif /* LOSING_COMPILER */
5940 macro_build ((char *) NULL
, &icnt
, NULL
,
5941 dbl
? "dmultu" : "multu",
5943 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5949 /* The MIPS assembler some times generates shifts and adds. I'm
5950 not trying to be that fancy. GCC should do this for us
5952 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5953 macro_build ((char *) NULL
, &icnt
, NULL
,
5954 dbl
? "dmult" : "mult",
5956 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5962 mips_emit_delays (true);
5963 ++mips_opts
.noreorder
;
5964 mips_any_noreorder
= 1;
5965 macro_build ((char *) NULL
, &icnt
, NULL
,
5966 dbl
? "dmult" : "mult",
5968 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5969 macro_build ((char *) NULL
, &icnt
, NULL
,
5970 dbl
? "dsra32" : "sra",
5971 "d,w,<", dreg
, dreg
, 31);
5972 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5974 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5977 expr1
.X_add_number
= 8;
5978 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5979 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5980 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5982 --mips_opts
.noreorder
;
5983 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5989 mips_emit_delays (true);
5990 ++mips_opts
.noreorder
;
5991 mips_any_noreorder
= 1;
5992 macro_build ((char *) NULL
, &icnt
, NULL
,
5993 dbl
? "dmultu" : "multu",
5995 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5996 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5998 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6001 expr1
.X_add_number
= 8;
6002 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6003 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6004 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6006 --mips_opts
.noreorder
;
6010 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6011 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6012 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6014 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6018 if (imm_expr
.X_op
!= O_constant
)
6019 as_bad ("rotate count too large");
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6021 (int) (imm_expr
.X_add_number
& 0x1f));
6022 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6023 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6024 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6028 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6029 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6030 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6032 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6036 if (imm_expr
.X_op
!= O_constant
)
6037 as_bad ("rotate count too large");
6038 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6039 (int) (imm_expr
.X_add_number
& 0x1f));
6040 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6041 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6042 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6048 as_bad ("opcode not supported on this processor");
6051 assert (mips_opts
.isa
< 2);
6052 /* Even on a big endian machine $fn comes before $fn+1. We have
6053 to adjust when storing to memory. */
6054 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6055 target_big_endian
? treg
+ 1 : treg
,
6056 (int) BFD_RELOC_LO16
, breg
);
6057 offset_expr
.X_add_number
+= 4;
6058 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6059 target_big_endian
? treg
: treg
+ 1,
6060 (int) BFD_RELOC_LO16
, breg
);
6065 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6066 treg
, (int) BFD_RELOC_LO16
);
6068 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6069 sreg
, (int) BFD_RELOC_LO16
);
6072 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6074 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6075 dreg
, (int) BFD_RELOC_LO16
);
6080 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6082 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6083 sreg
, (int) BFD_RELOC_LO16
);
6088 as_warn ("Instruction %s: result is always false",
6090 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6093 if (imm_expr
.X_op
== O_constant
6094 && imm_expr
.X_add_number
>= 0
6095 && imm_expr
.X_add_number
< 0x10000)
6097 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6098 sreg
, (int) BFD_RELOC_LO16
);
6101 else if (imm_expr
.X_op
== O_constant
6102 && imm_expr
.X_add_number
> -0x8000
6103 && imm_expr
.X_add_number
< 0)
6105 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6106 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6107 ((bfd_arch_bits_per_address (stdoutput
) == 32
6108 || mips_opts
.isa
< 3)
6109 ? "addiu" : "daddiu"),
6110 "t,r,j", dreg
, sreg
,
6111 (int) BFD_RELOC_LO16
);
6116 load_register (&icnt
, AT
, &imm_expr
, 0);
6117 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6121 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6122 (int) BFD_RELOC_LO16
);
6127 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6133 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6134 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6135 (int) BFD_RELOC_LO16
);
6138 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6140 if (imm_expr
.X_op
== O_constant
6141 && imm_expr
.X_add_number
>= -0x8000
6142 && imm_expr
.X_add_number
< 0x8000)
6144 macro_build ((char *) NULL
, &icnt
, &expr1
,
6145 mask
== M_SGE_I
? "slti" : "sltiu",
6146 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6151 load_register (&icnt
, AT
, &imm_expr
, 0);
6152 macro_build ((char *) NULL
, &icnt
, NULL
,
6153 mask
== M_SGE_I
? "slt" : "sltu",
6154 "d,v,t", dreg
, sreg
, AT
);
6157 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6158 (int) BFD_RELOC_LO16
);
6163 case M_SGT
: /* sreg > treg <==> treg < sreg */
6169 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6172 case M_SGT_I
: /* sreg > I <==> I < sreg */
6178 load_register (&icnt
, AT
, &imm_expr
, 0);
6179 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6182 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6188 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6189 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6190 (int) BFD_RELOC_LO16
);
6193 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6199 load_register (&icnt
, AT
, &imm_expr
, 0);
6200 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6201 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6202 (int) BFD_RELOC_LO16
);
6206 if (imm_expr
.X_op
== O_constant
6207 && imm_expr
.X_add_number
>= -0x8000
6208 && imm_expr
.X_add_number
< 0x8000)
6210 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6211 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6214 load_register (&icnt
, AT
, &imm_expr
, 0);
6215 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6219 if (imm_expr
.X_op
== O_constant
6220 && imm_expr
.X_add_number
>= -0x8000
6221 && imm_expr
.X_add_number
< 0x8000)
6223 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6224 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6227 load_register (&icnt
, AT
, &imm_expr
, 0);
6228 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6234 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6237 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6241 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6243 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6249 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6251 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6257 as_warn ("Instruction %s: result is always true",
6259 macro_build ((char *) NULL
, &icnt
, &expr1
,
6260 ((bfd_arch_bits_per_address (stdoutput
) == 32
6261 || mips_opts
.isa
< 3)
6262 ? "addiu" : "daddiu"),
6263 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6266 if (imm_expr
.X_op
== O_constant
6267 && imm_expr
.X_add_number
>= 0
6268 && imm_expr
.X_add_number
< 0x10000)
6270 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6271 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6274 else if (imm_expr
.X_op
== O_constant
6275 && imm_expr
.X_add_number
> -0x8000
6276 && imm_expr
.X_add_number
< 0)
6278 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6279 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6280 ((bfd_arch_bits_per_address (stdoutput
) == 32
6281 || mips_opts
.isa
< 3)
6282 ? "addiu" : "daddiu"),
6283 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6288 load_register (&icnt
, AT
, &imm_expr
, 0);
6289 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6293 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6301 if (imm_expr
.X_op
== O_constant
6302 && imm_expr
.X_add_number
> -0x8000
6303 && imm_expr
.X_add_number
<= 0x8000)
6305 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6306 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6307 dbl
? "daddi" : "addi",
6308 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6311 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6312 macro_build ((char *) NULL
, &icnt
, NULL
,
6313 dbl
? "dsub" : "sub",
6314 "d,v,t", dreg
, sreg
, AT
);
6320 if (imm_expr
.X_op
== O_constant
6321 && imm_expr
.X_add_number
> -0x8000
6322 && imm_expr
.X_add_number
<= 0x8000)
6324 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6325 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6326 dbl
? "daddiu" : "addiu",
6327 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6330 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6331 macro_build ((char *) NULL
, &icnt
, NULL
,
6332 dbl
? "dsubu" : "subu",
6333 "d,v,t", dreg
, sreg
, AT
);
6354 load_register (&icnt
, AT
, &imm_expr
, 0);
6355 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6360 assert (mips_opts
.isa
< 2);
6361 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6362 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6365 * Is the double cfc1 instruction a bug in the mips assembler;
6366 * or is there a reason for it?
6368 mips_emit_delays (true);
6369 ++mips_opts
.noreorder
;
6370 mips_any_noreorder
= 1;
6371 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6372 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6373 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6374 expr1
.X_add_number
= 3;
6375 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6376 (int) BFD_RELOC_LO16
);
6377 expr1
.X_add_number
= 2;
6378 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6379 (int) BFD_RELOC_LO16
);
6380 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6381 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6382 macro_build ((char *) NULL
, &icnt
, NULL
,
6383 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6384 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6385 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6386 --mips_opts
.noreorder
;
6395 if (offset_expr
.X_add_number
>= 0x7fff)
6396 as_bad ("operand overflow");
6397 /* avoid load delay */
6398 if (! target_big_endian
)
6399 offset_expr
.X_add_number
+= 1;
6400 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6401 (int) BFD_RELOC_LO16
, breg
);
6402 if (! target_big_endian
)
6403 offset_expr
.X_add_number
-= 1;
6405 offset_expr
.X_add_number
+= 1;
6406 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6407 (int) BFD_RELOC_LO16
, breg
);
6408 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6409 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6422 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6423 as_bad ("operand overflow");
6424 if (! target_big_endian
)
6425 offset_expr
.X_add_number
+= off
;
6426 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6427 (int) BFD_RELOC_LO16
, breg
);
6428 if (! target_big_endian
)
6429 offset_expr
.X_add_number
-= off
;
6431 offset_expr
.X_add_number
+= off
;
6432 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6433 (int) BFD_RELOC_LO16
, breg
);
6446 load_address (&icnt
, AT
, &offset_expr
);
6448 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6449 ((bfd_arch_bits_per_address (stdoutput
) == 32
6450 || mips_opts
.isa
< 3)
6451 ? "addu" : "daddu"),
6452 "d,v,t", AT
, AT
, breg
);
6453 if (! target_big_endian
)
6454 expr1
.X_add_number
= off
;
6456 expr1
.X_add_number
= 0;
6457 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6458 (int) BFD_RELOC_LO16
, AT
);
6459 if (! target_big_endian
)
6460 expr1
.X_add_number
= 0;
6462 expr1
.X_add_number
= off
;
6463 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6464 (int) BFD_RELOC_LO16
, AT
);
6469 load_address (&icnt
, AT
, &offset_expr
);
6471 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6472 ((bfd_arch_bits_per_address (stdoutput
) == 32
6473 || mips_opts
.isa
< 3)
6474 ? "addu" : "daddu"),
6475 "d,v,t", AT
, AT
, breg
);
6476 if (target_big_endian
)
6477 expr1
.X_add_number
= 0;
6478 macro_build ((char *) NULL
, &icnt
, &expr1
,
6479 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6480 (int) BFD_RELOC_LO16
, AT
);
6481 if (target_big_endian
)
6482 expr1
.X_add_number
= 1;
6484 expr1
.X_add_number
= 0;
6485 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6486 (int) BFD_RELOC_LO16
, AT
);
6487 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6489 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6494 if (offset_expr
.X_add_number
>= 0x7fff)
6495 as_bad ("operand overflow");
6496 if (target_big_endian
)
6497 offset_expr
.X_add_number
+= 1;
6498 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6499 (int) BFD_RELOC_LO16
, breg
);
6500 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6501 if (target_big_endian
)
6502 offset_expr
.X_add_number
-= 1;
6504 offset_expr
.X_add_number
+= 1;
6505 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6506 (int) BFD_RELOC_LO16
, breg
);
6519 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6520 as_bad ("operand overflow");
6521 if (! target_big_endian
)
6522 offset_expr
.X_add_number
+= off
;
6523 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6524 (int) BFD_RELOC_LO16
, breg
);
6525 if (! target_big_endian
)
6526 offset_expr
.X_add_number
-= off
;
6528 offset_expr
.X_add_number
+= off
;
6529 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6530 (int) BFD_RELOC_LO16
, breg
);
6543 load_address (&icnt
, AT
, &offset_expr
);
6545 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6546 ((bfd_arch_bits_per_address (stdoutput
) == 32
6547 || mips_opts
.isa
< 3)
6548 ? "addu" : "daddu"),
6549 "d,v,t", AT
, AT
, breg
);
6550 if (! target_big_endian
)
6551 expr1
.X_add_number
= off
;
6553 expr1
.X_add_number
= 0;
6554 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6555 (int) BFD_RELOC_LO16
, AT
);
6556 if (! target_big_endian
)
6557 expr1
.X_add_number
= 0;
6559 expr1
.X_add_number
= off
;
6560 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6561 (int) BFD_RELOC_LO16
, AT
);
6565 load_address (&icnt
, AT
, &offset_expr
);
6567 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6568 ((bfd_arch_bits_per_address (stdoutput
) == 32
6569 || mips_opts
.isa
< 3)
6570 ? "addu" : "daddu"),
6571 "d,v,t", AT
, AT
, breg
);
6572 if (! target_big_endian
)
6573 expr1
.X_add_number
= 0;
6574 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6575 (int) BFD_RELOC_LO16
, AT
);
6576 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6578 if (! target_big_endian
)
6579 expr1
.X_add_number
= 1;
6581 expr1
.X_add_number
= 0;
6582 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6583 (int) BFD_RELOC_LO16
, AT
);
6584 if (! target_big_endian
)
6585 expr1
.X_add_number
= 0;
6587 expr1
.X_add_number
= 1;
6588 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6589 (int) BFD_RELOC_LO16
, AT
);
6590 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6592 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6597 /* FIXME: Check if this is one of the itbl macros, since they
6598 are added dynamically. */
6599 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6603 as_warn ("Macro used $at after \".set noat\"");
6606 /* Implement macros in mips16 mode. */
6610 struct mips_cl_insn
*ip
;
6613 int xreg
, yreg
, zreg
, tmp
;
6617 const char *s
, *s2
, *s3
;
6619 mask
= ip
->insn_mo
->mask
;
6621 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6622 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6623 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6627 expr1
.X_op
= O_constant
;
6628 expr1
.X_op_symbol
= NULL
;
6629 expr1
.X_add_symbol
= NULL
;
6630 expr1
.X_add_number
= 1;
6649 mips_emit_delays (true);
6650 ++mips_opts
.noreorder
;
6651 mips_any_noreorder
= 1;
6652 macro_build ((char *) NULL
, &icnt
, NULL
,
6653 dbl
? "ddiv" : "div",
6654 "0,x,y", xreg
, yreg
);
6655 expr1
.X_add_number
= 2;
6656 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6657 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6658 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6659 since that causes an overflow. We should do that as well,
6660 but I don't see how to do the comparisons without a temporary
6662 --mips_opts
.noreorder
;
6663 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6682 mips_emit_delays (true);
6683 ++mips_opts
.noreorder
;
6684 mips_any_noreorder
= 1;
6685 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6686 expr1
.X_add_number
= 2;
6687 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6688 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6689 --mips_opts
.noreorder
;
6690 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6696 macro_build ((char *) NULL
, &icnt
, NULL
,
6697 dbl
? "dmultu" : "multu",
6699 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6707 if (imm_expr
.X_op
!= O_constant
)
6708 as_bad ("Unsupported large constant");
6709 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6710 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6711 dbl
? "daddiu" : "addiu",
6712 "y,x,4", yreg
, xreg
);
6716 if (imm_expr
.X_op
!= O_constant
)
6717 as_bad ("Unsupported large constant");
6718 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6719 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6724 if (imm_expr
.X_op
!= O_constant
)
6725 as_bad ("Unsupported large constant");
6726 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6727 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6750 goto do_reverse_branch
;
6754 goto do_reverse_branch
;
6766 goto do_reverse_branch
;
6777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6779 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6806 goto do_addone_branch_i
;
6811 goto do_addone_branch_i
;
6826 goto do_addone_branch_i
;
6833 if (imm_expr
.X_op
!= O_constant
)
6834 as_bad ("Unsupported large constant");
6835 ++imm_expr
.X_add_number
;
6838 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6843 expr1
.X_add_number
= 0;
6844 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6846 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6847 "move", "y,X", xreg
, yreg
);
6848 expr1
.X_add_number
= 2;
6849 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6851 "neg", "x,w", xreg
, xreg
);
6855 /* For consistency checking, verify that all bits are specified either
6856 by the match/mask part of the instruction definition, or by the
6859 validate_mips_insn (opc
)
6860 const struct mips_opcode
*opc
;
6862 const char *p
= opc
->args
;
6864 unsigned long used_bits
= opc
->mask
;
6866 if ((used_bits
& opc
->match
) != opc
->match
)
6868 as_bad ("internal: bad mips opcode (mask error): %s %s",
6869 opc
->name
, opc
->args
);
6872 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6879 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6880 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6882 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6883 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6884 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6885 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6887 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6890 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6891 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6892 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6893 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6894 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6895 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6896 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6897 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6898 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6899 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6900 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6902 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6903 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6904 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6905 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6907 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6908 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6909 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6910 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6911 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6912 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6913 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6914 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6917 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6918 /* start-sanitize-r5900 */
6919 case '0': USE_BITS (OP_MASK_VADDI
, OP_SH_VADDI
); break;
6920 case '1': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
6921 case '2': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
6922 case '3': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
6923 case '4': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
6924 case '5': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
6925 case '6': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
6927 USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
);
6928 USE_BITS (OP_MASK_VUFTF
, OP_SH_VUFTF
);
6931 USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
);
6932 USE_BITS (OP_MASK_VUFSF
, OP_SH_VUFSF
);
6940 case 'O': USE_BITS (OP_MASK_VUCALLMS
, OP_SH_VUCALLMS
);break;
6941 case '&': USE_BITS (OP_MASK_VUDEST
, OP_SH_VUDEST
); break;
6947 /* end-sanitize-r5900 */
6948 /* start-sanitize-vr5400 */
6949 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
6950 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
6953 /* end-sanitize-vr5400 */
6955 as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s",
6956 c
, opc
->name
, opc
->args
);
6960 /* Some of the trapping instructions (break, t*, sdbbp) have "code"
6961 fields that cannot currently be set by assembly code. Ignore them
6963 if (opc
->pinfo
& INSN_TRAP
)
6965 static const char *const trap_insns
[] = {
6967 "teq", "tge", "tgeu", "tlt", "tltu", "tne",
6970 for (i
= sizeof(trap_insns
)/sizeof(trap_insns
[0]) - 1; i
>= 0; i
--)
6971 if (!strcmp (trap_insns
[i
], opc
->name
))
6973 used_bits
|= 0xffc0;
6977 if (used_bits
!= 0xffffffff)
6979 as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s",
6980 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6986 /* This routine assembles an instruction into its binary format. As a
6987 side effect, it sets one of the global variables imm_reloc or
6988 offset_reloc to the type of relocation to do if one of the operands
6989 is an address expression. */
6994 struct mips_cl_insn
*ip
;
6999 struct mips_opcode
*insn
;
7002 unsigned int lastregno
= 0;
7008 /* If the instruction contains a '.', we first try to match an instruction
7009 including the '.'. Then we try again without the '.'. */
7011 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
7014 /* If we stopped on whitespace, then replace the whitespace with null for
7015 the call to hash_find. Save the character we replaced just in case we
7016 have to re-parse the instruction. */
7023 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7025 /* If we didn't find the instruction in the opcode table, try again, but
7026 this time with just the instruction up to, but not including the
7030 /* Restore the character we overwrite above (if any). */
7034 /* Scan up to the first '.' or whitespace. */
7035 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace (*s
); ++s
)
7038 /* If we did not find a '.', then we can quit now. */
7041 insn_error
= "unrecognized opcode";
7045 /* Lookup the instruction in the hash table. */
7047 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7049 insn_error
= "unrecognized opcode";
7060 assert (strcmp (insn
->name
, str
) == 0);
7062 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7064 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7066 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7068 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7073 if (insn_isa
<= mips_opts
.isa
)
7075 else if (insn
->pinfo
== INSN_MACRO
)
7077 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
7078 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
7079 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
7080 /* start-sanitize-vr4320 */
7081 || (mips_4320
&& (insn
->membership
& INSN_4320
) != 0)
7082 /* end-sanitize-vr4320 */
7083 /* start-sanitize-tx49 */
7084 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
7085 /* end-sanitize-tx49 */
7086 /* start-sanitize-r5900 */
7087 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
7088 /* end-sanitize-r5900 */
7089 /* start-sanitize-vr5400 */
7090 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
7091 /* end-sanitize-vr5400 */
7092 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
7097 if (insn
->pinfo
!= INSN_MACRO
)
7099 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
7101 /* start-sanitize-r5900 */
7102 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
7104 /* end-sanitize-r5900 */
7109 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7110 && strcmp (insn
->name
, insn
[1].name
) == 0)
7116 || insn_isa
<= mips_opts
.isa
)
7117 insn_error
= "opcode not supported on this processor";
7120 static char buf
[100];
7122 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
7129 ip
->insn_opcode
= insn
->match
;
7130 for (args
= insn
->args
;; ++args
)
7136 case '\0': /* end of args */
7149 ip
->insn_opcode
|= lastregno
<< 21;
7154 ip
->insn_opcode
|= lastregno
<< 16;
7158 ip
->insn_opcode
|= lastregno
<< 11;
7164 /* Handle optional base register.
7165 Either the base register is omitted or
7166 we must have a left paren. */
7167 /* This is dependent on the next operand specifier
7168 is a base register specification. */
7169 assert (args
[1] == 'b' || args
[1] == '5'
7170 || args
[1] == '-' || args
[1] == '4');
7174 case ')': /* these must match exactly */
7175 /* start-sanitize-vr5400 */
7178 /* end-sanitize-vr5400 */
7179 /* start-sanitize-r5900 */
7182 /* end-sanitize-r5900 */
7187 case '<': /* must be at least one digit */
7189 * According to the manual, if the shift amount is greater
7190 * than 31 or less than 0 the the shift amount should be
7191 * mod 32. In reality the mips assembler issues an error.
7192 * We issue a warning and mask out all but the low 5 bits.
7194 my_getExpression (&imm_expr
, s
);
7195 check_absolute_expr (ip
, &imm_expr
);
7196 if ((unsigned long) imm_expr
.X_add_number
> 31)
7198 as_warn ("Improper shift amount (%ld)",
7199 (long) imm_expr
.X_add_number
);
7200 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7202 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7203 imm_expr
.X_op
= O_absent
;
7207 case '>': /* shift amount minus 32 */
7208 my_getExpression (&imm_expr
, s
);
7209 check_absolute_expr (ip
, &imm_expr
);
7210 if ((unsigned long) imm_expr
.X_add_number
< 32
7211 || (unsigned long) imm_expr
.X_add_number
> 63)
7213 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7214 imm_expr
.X_op
= O_absent
;
7218 /* start-sanitize-r5900 */
7219 case '0': /* 5 bit signed immediate at 6 */
7220 my_getExpression (&imm_expr
, s
);
7221 check_absolute_expr (ip
, &imm_expr
);
7222 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7223 || ((imm_expr
.X_add_number
< -16
7224 || imm_expr
.X_add_number
>= 16)
7225 && imm_expr
.X_op
== O_constant
))
7227 if (imm_expr
.X_op
!= O_constant
7228 && imm_expr
.X_op
!= O_big
)
7229 insn_error
= "absolute expression required";
7231 as_bad ("5 bit expression not in range -16..15");
7233 ip
->insn_opcode
|= (imm_expr
.X_add_number
) << 6;
7234 imm_expr
.X_op
= O_absent
;
7238 case '9': /* vi19 for vcallmsr */
7239 if (strncmp (s
, "vi19", 4) == 0)
7242 as_bad ("expected vi19");
7245 case '#': /* escape character */
7246 /* '#' specifies that we've got an optional suffix to this
7247 operand that must match exactly (if it exists). */
7248 if (*s
!= '\0' && *s
!= ','
7249 && *s
!= ' ' && *s
!= '\t' && *s
!= '\n')
7251 if (*s
== *(args
+ 1))
7262 case 'K': /* DEST operand completer (optional), must
7263 match previous dest if specified. */
7264 case '&': /* DEST instruction completer */
7271 /* Parse the completer. */
7273 while (*s
!= '\0' && *s
!= ' ' && *s
!= ',')
7285 insn_error
= "Invalid dest specification";
7291 /* Each completer can only appear once. */
7292 if (w
> 1 || x
> 1 || y
> 1 || z
> 1)
7294 insn_error
= "Invalid dest specification";
7298 /* If this is the opcode completer, then we must insert
7299 the appropriate value into the insn. */
7302 ip
->insn_opcode
|= ((w
<< 21) | (x
<< 24)
7303 | (y
<< 23) | (z
<< 22));
7304 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7310 /* This is the operand completer, make sure it matches
7311 the previous opcode completer. */
7312 temp
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7313 if (temp
&& temp
!= last_h
)
7315 insn_error
= "DEST field in operand does not match DEST field in instruction";
7324 case 'J': /* vu0 I register */
7328 insn_error
= "operand `I' expected";
7331 case 'Q': /* vu0 Q register */
7335 insn_error
= "operand `Q' expected";
7338 case 'X': /* vu0 R register */
7342 insn_error
= "operand `R' expected";
7345 case 'U': /* vu0 ACC register */
7346 if (s
[0] == 'A' && s
[1] == 'C' && s
[2] == 'C')
7349 insn_error
= "operand `ACC' expected";
7353 my_getSmallExpression (&imm_expr
, s
);
7354 imm_reloc
= BFD_RELOC_MIPS15_S3
;
7357 /* end-sanitize-r5900 */
7359 case 'k': /* cache code */
7360 case 'h': /* prefx code */
7361 my_getExpression (&imm_expr
, s
);
7362 check_absolute_expr (ip
, &imm_expr
);
7363 if ((unsigned long) imm_expr
.X_add_number
> 31)
7365 as_warn ("Invalid value for `%s' (%lu)",
7367 (unsigned long) imm_expr
.X_add_number
);
7368 imm_expr
.X_add_number
&= 0x1f;
7371 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7373 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7374 imm_expr
.X_op
= O_absent
;
7378 case 'c': /* break code */
7379 my_getExpression (&imm_expr
, s
);
7380 check_absolute_expr (ip
, &imm_expr
);
7381 if ((unsigned) imm_expr
.X_add_number
> 1023)
7382 as_warn ("Illegal break code (%ld)",
7383 (long) imm_expr
.X_add_number
);
7384 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7385 imm_expr
.X_op
= O_absent
;
7389 case 'B': /* syscall code */
7390 my_getExpression (&imm_expr
, s
);
7391 check_absolute_expr (ip
, &imm_expr
);
7392 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7393 as_warn ("Illegal syscall code (%ld)",
7394 (long) imm_expr
.X_add_number
);
7395 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7396 imm_expr
.X_op
= O_absent
;
7400 case 'C': /* Coprocessor code */
7401 my_getExpression (&imm_expr
, s
);
7402 check_absolute_expr (ip
, &imm_expr
);
7403 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7405 as_warn ("Coproccesor code > 25 bits (%ld)",
7406 (long) imm_expr
.X_add_number
);
7407 imm_expr
.X_add_number
&= ((1<<25) - 1);
7409 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7410 imm_expr
.X_op
= O_absent
;
7414 case 'P': /* Performance register */
7415 my_getExpression (&imm_expr
, s
);
7416 check_absolute_expr (ip
, &imm_expr
);
7417 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7419 as_warn ("Invalidate performance regster (%ld)",
7420 (long) imm_expr
.X_add_number
);
7421 imm_expr
.X_add_number
&= 1;
7423 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7424 imm_expr
.X_op
= O_absent
;
7428 case 'b': /* base register */
7429 case 'd': /* destination register */
7430 case 's': /* source register */
7431 case 't': /* target register */
7432 case 'r': /* both target and source */
7433 case 'v': /* both dest and source */
7434 case 'w': /* both dest and target */
7435 case 'E': /* coprocessor target register */
7436 case 'G': /* coprocessor destination register */
7437 case 'x': /* ignore register name */
7438 case 'z': /* must be zero register */
7452 while (isdigit (*s
));
7454 as_bad ("Invalid register number (%d)", regno
);
7456 else if (*args
== 'E' || *args
== 'G')
7460 if (s
[1] == 'f' && s
[2] == 'p')
7465 else if (s
[1] == 's' && s
[2] == 'p')
7470 else if (s
[1] == 'g' && s
[2] == 'p')
7475 else if (s
[1] == 'a' && s
[2] == 't')
7480 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7485 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7490 else if (itbl_have_entries
)
7495 p
= s
+1; /* advance past '$' */
7496 n
= itbl_get_field (&p
); /* n is name */
7498 /* See if this is a register defined in an
7500 r
= itbl_get_reg_val (n
);
7503 /* Get_field advances to the start of
7504 the next field, so we need to back
7505 rack to the end of the last field. */
7509 s
= strchr (s
,'\0');
7522 as_warn ("Used $at without \".set noat\"");
7528 if (c
== 'r' || c
== 'v' || c
== 'w')
7535 /* 'z' only matches $0. */
7536 if (c
== 'z' && regno
!= 0)
7539 /* Now that we have assembled one operand, we use the args string
7540 * to figure out where it goes in the instruction. */
7547 ip
->insn_opcode
|= regno
<< 21;
7551 ip
->insn_opcode
|= regno
<< 11;
7556 ip
->insn_opcode
|= regno
<< 16;
7559 /* This case exists because on the r3000 trunc
7560 expands into a macro which requires a gp
7561 register. On the r6000 or r4000 it is
7562 assembled into a single instruction which
7563 ignores the register. Thus the insn version
7564 is MIPS_ISA2 and uses 'x', and the macro
7565 version is MIPS_ISA1 and uses 't'. */
7568 /* This case is for the div instruction, which
7569 acts differently if the destination argument
7570 is $0. This only matches $0, and is checked
7571 outside the switch. */
7574 /* Itbl operand; not yet implemented. FIXME ?? */
7576 /* What about all other operands like 'i', which
7577 can be specified in the opcode table? */
7587 ip
->insn_opcode
|= lastregno
<< 21;
7590 ip
->insn_opcode
|= lastregno
<< 16;
7595 case 'D': /* floating point destination register */
7596 case 'S': /* floating point source register */
7597 case 'T': /* floating point target register */
7598 case 'R': /* floating point source register */
7601 /* start-sanitize-r5900 */
7602 case '1': /* vu0 fp reg position 1 */
7603 case '2': /* vu0 fp reg position 2 */
7604 case '3': /* vu0 fp reg position 3 */
7605 case '4': /* vu0 int reg position 1 */
7606 case '5': /* vu0 int reg position 2 */
7607 case '6': /* vu0 int reg position 3 */
7608 case '7': /* vu0 fp reg with ftf modifier */
7609 case '8': /* vu0 fp reg with fsf modifier */
7610 /* end-sanitize-r5900 */
7612 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7622 while (isdigit (*s
));
7625 as_bad ("Invalid float register number (%d)", regno
);
7627 if ((regno
& 1) != 0
7628 && mips_opts
.isa
< 3
7629 && ! (strcmp (str
, "mtc1") == 0
7630 || strcmp (str
, "mfc1") == 0
7631 || strcmp (str
, "lwc1") == 0
7632 || strcmp (str
, "swc1") == 0
7633 || strcmp (str
, "l.s") == 0
7634 || strcmp (str
, "s.s") == 0))
7635 as_warn ("Float register should be even, was %d",
7643 if (c
== 'V' || c
== 'W')
7653 ip
->insn_opcode
|= regno
<< 6;
7657 ip
->insn_opcode
|= regno
<< 11;
7661 ip
->insn_opcode
|= regno
<< 16;
7664 ip
->insn_opcode
|= regno
<< 21;
7671 /* start-sanitize-r5900 */
7672 /* Handle vf and vi regsiters for vu0. */
7674 && (s
[1] == 'f' || s
[1] == 'i')
7685 while (isdigit (*s
));
7688 as_bad ("Invalid vu0 register number (%d)", regno
);
7692 if (c
== '7' || c
== '8')
7701 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7706 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7711 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7716 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7719 as_bad ("Invalid FSF/FTF specification");
7727 if (c
== 'V' || c
== 'W')
7739 ip
->insn_opcode
|= regno
<< 16;
7744 ip
->insn_opcode
|= regno
<< 11;
7748 ip
->insn_opcode
|= regno
<< 6;
7754 /* end-sanitize-r5900 */
7759 ip
->insn_opcode
|= lastregno
<< 11;
7762 ip
->insn_opcode
|= lastregno
<< 16;
7768 my_getExpression (&imm_expr
, s
);
7769 if (imm_expr
.X_op
!= O_big
7770 && imm_expr
.X_op
!= O_constant
)
7771 insn_error
= "absolute expression required";
7776 my_getExpression (&offset_expr
, s
);
7777 imm_reloc
= BFD_RELOC_32
;
7789 unsigned char temp
[8];
7791 unsigned int length
;
7796 /* These only appear as the last operand in an
7797 instruction, and every instruction that accepts
7798 them in any variant accepts them in all variants.
7799 This means we don't have to worry about backing out
7800 any changes if the instruction does not match.
7802 The difference between them is the size of the
7803 floating point constant and where it goes. For 'F'
7804 and 'L' the constant is 64 bits; for 'f' and 'l' it
7805 is 32 bits. Where the constant is placed is based
7806 on how the MIPS assembler does things:
7809 f -- immediate value
7812 The .lit4 and .lit8 sections are only used if
7813 permitted by the -G argument.
7815 When generating embedded PIC code, we use the
7816 .lit8 section but not the .lit4 section (we can do
7817 .lit4 inline easily; we need to put .lit8
7818 somewhere in the data segment, and using .lit8
7819 permits the linker to eventually combine identical
7822 f64
= *args
== 'F' || *args
== 'L';
7824 save_in
= input_line_pointer
;
7825 input_line_pointer
= s
;
7826 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7828 s
= input_line_pointer
;
7829 input_line_pointer
= save_in
;
7830 if (err
!= NULL
&& *err
!= '\0')
7832 as_bad ("Bad floating point constant: %s", err
);
7833 memset (temp
, '\0', sizeof temp
);
7834 length
= f64
? 8 : 4;
7837 assert (length
== (f64
? 8 : 4));
7841 && (! USE_GLOBAL_POINTER_OPT
7842 || mips_pic
== EMBEDDED_PIC
7843 || g_switch_value
< 4
7844 || (temp
[0] == 0 && temp
[1] == 0)
7845 || (temp
[2] == 0 && temp
[3] == 0))))
7847 imm_expr
.X_op
= O_constant
;
7848 if (! target_big_endian
)
7849 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7851 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7854 && ((temp
[0] == 0 && temp
[1] == 0)
7855 || (temp
[2] == 0 && temp
[3] == 0))
7856 && ((temp
[4] == 0 && temp
[5] == 0)
7857 || (temp
[6] == 0 && temp
[7] == 0)))
7859 /* The value is simple enough to load with a
7860 couple of instructions. In mips1 mode, set
7861 imm_expr to the high order 32 bits and
7862 offset_expr to the low order 32 bits.
7863 Otherwise, set imm_expr to the entire 64 bit
7865 if (mips_opts
.isa
< 3)
7867 imm_expr
.X_op
= O_constant
;
7868 offset_expr
.X_op
= O_constant
;
7869 if (! target_big_endian
)
7871 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7872 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7876 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7877 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7879 if (offset_expr
.X_add_number
== 0)
7880 offset_expr
.X_op
= O_absent
;
7882 else if (sizeof (imm_expr
.X_add_number
) > 4)
7884 imm_expr
.X_op
= O_constant
;
7885 if (! target_big_endian
)
7886 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7888 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7892 imm_expr
.X_op
= O_big
;
7893 imm_expr
.X_add_number
= 4;
7894 if (! target_big_endian
)
7896 generic_bignum
[0] = bfd_getl16 (temp
);
7897 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7898 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7899 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7903 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7904 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7905 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7906 generic_bignum
[3] = bfd_getb16 (temp
);
7912 const char *newname
;
7915 /* Switch to the right section. */
7917 subseg
= now_subseg
;
7920 default: /* unused default case avoids warnings. */
7922 newname
= RDATA_SECTION_NAME
;
7923 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7927 newname
= RDATA_SECTION_NAME
;
7930 assert (!USE_GLOBAL_POINTER_OPT
7931 || g_switch_value
>= 4);
7935 new_seg
= subseg_new (newname
, (subsegT
) 0);
7936 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7937 bfd_set_section_flags (stdoutput
, new_seg
,
7942 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7943 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7944 && strcmp (TARGET_OS
, "elf") != 0)
7945 record_alignment (new_seg
, 4);
7947 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7949 as_bad ("Can't use floating point insn in this section");
7951 /* Set the argument to the current address in the
7953 offset_expr
.X_op
= O_symbol
;
7954 offset_expr
.X_add_symbol
=
7955 symbol_new ("L0\001", now_seg
,
7956 (valueT
) frag_now_fix (), frag_now
);
7957 offset_expr
.X_add_number
= 0;
7959 /* Put the floating point number into the section. */
7960 p
= frag_more ((int) length
);
7961 memcpy (p
, temp
, length
);
7963 /* Switch back to the original section. */
7964 subseg_set (seg
, subseg
);
7969 case 'i': /* 16 bit unsigned immediate */
7970 case 'j': /* 16 bit signed immediate */
7971 imm_reloc
= BFD_RELOC_LO16
;
7972 c
= my_getSmallExpression (&imm_expr
, s
);
7977 if (imm_expr
.X_op
== O_constant
)
7978 imm_expr
.X_add_number
=
7979 (imm_expr
.X_add_number
>> 16) & 0xffff;
7982 imm_reloc
= BFD_RELOC_HI16_S
;
7983 imm_unmatched_hi
= true;
7986 imm_reloc
= BFD_RELOC_HI16
;
7991 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7992 || ((imm_expr
.X_add_number
< 0
7993 || imm_expr
.X_add_number
>= 0x10000)
7994 && imm_expr
.X_op
== O_constant
))
7996 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7997 !strcmp (insn
->name
, insn
[1].name
))
7999 if (imm_expr
.X_op
!= O_constant
8000 && imm_expr
.X_op
!= O_big
)
8001 insn_error
= "absolute expression required";
8003 as_bad ("16 bit expression not in range 0..65535");
8011 /* The upper bound should be 0x8000, but
8012 unfortunately the MIPS assembler accepts numbers
8013 from 0x8000 to 0xffff and sign extends them, and
8014 we want to be compatible. We only permit this
8015 extended range for an instruction which does not
8016 provide any further alternates, since those
8017 alternates may handle other cases. People should
8018 use the numbers they mean, rather than relying on
8019 a mysterious sign extension. */
8020 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8021 strcmp (insn
->name
, insn
[1].name
) == 0);
8026 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8027 || ((imm_expr
.X_add_number
< -0x8000
8028 || imm_expr
.X_add_number
>= max
)
8029 && imm_expr
.X_op
== O_constant
)
8031 && imm_expr
.X_add_number
< 0
8032 && mips_opts
.isa
>= 3
8033 && imm_expr
.X_unsigned
8034 && sizeof (imm_expr
.X_add_number
) <= 4))
8038 if (imm_expr
.X_op
!= O_constant
8039 && imm_expr
.X_op
!= O_big
)
8040 insn_error
= "absolute expression required";
8042 as_bad ("16 bit expression not in range -32768..32767");
8048 case 'o': /* 16 bit offset */
8049 c
= my_getSmallExpression (&offset_expr
, s
);
8051 /* If this value won't fit into a 16 bit offset, then go
8052 find a macro that will generate the 32 bit offset
8053 code pattern. As a special hack, we accept the
8054 difference of two local symbols as a constant. This
8055 is required to suppose embedded PIC switches, which
8056 use an instruction which looks like
8057 lw $4,$L12-$LS12($4)
8058 The problem with handling this in a more general
8059 fashion is that the macro function doesn't expect to
8060 see anything which can be handled in a single
8061 constant instruction. */
8063 && (offset_expr
.X_op
!= O_constant
8064 || offset_expr
.X_add_number
>= 0x8000
8065 || offset_expr
.X_add_number
< -0x8000)
8066 && (mips_pic
!= EMBEDDED_PIC
8067 || offset_expr
.X_op
!= O_subtract
8068 || now_seg
!= text_section
8069 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
8073 offset_reloc
= BFD_RELOC_LO16
;
8074 if (c
== 'h' || c
== 'H')
8076 assert (offset_expr
.X_op
== O_constant
);
8077 offset_expr
.X_add_number
=
8078 (offset_expr
.X_add_number
>> 16) & 0xffff;
8083 case 'p': /* pc relative offset */
8084 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8085 my_getExpression (&offset_expr
, s
);
8089 case 'u': /* upper 16 bits */
8090 c
= my_getSmallExpression (&imm_expr
, s
);
8091 if (imm_expr
.X_op
== O_constant
8092 && (imm_expr
.X_add_number
< 0
8093 || imm_expr
.X_add_number
>= 0x10000))
8094 as_bad ("lui expression not in range 0..65535");
8095 imm_reloc
= BFD_RELOC_LO16
;
8100 if (imm_expr
.X_op
== O_constant
)
8101 imm_expr
.X_add_number
=
8102 (imm_expr
.X_add_number
>> 16) & 0xffff;
8105 imm_reloc
= BFD_RELOC_HI16_S
;
8106 imm_unmatched_hi
= true;
8109 imm_reloc
= BFD_RELOC_HI16
;
8115 case 'a': /* 26 bit address */
8116 my_getExpression (&offset_expr
, s
);
8118 offset_reloc
= BFD_RELOC_MIPS_JMP
;
8121 case 'N': /* 3 bit branch condition code */
8122 case 'M': /* 3 bit compare condition code */
8123 if (strncmp (s
, "$fcc", 4) != 0)
8133 while (isdigit (*s
));
8135 as_bad ("invalid condition code register $fcc%d", regno
);
8137 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8139 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8142 /* start-sanitize-vr5400 */
8143 case 'e': /* must be at least one digit */
8144 my_getExpression (&imm_expr
, s
);
8145 check_absolute_expr (ip
, &imm_expr
);
8146 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
8148 as_bad ("bad byte vector index (%ld)",
8149 (long) imm_expr
.X_add_number
);
8150 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8152 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8153 imm_expr
.X_op
= O_absent
;
8158 my_getExpression (&imm_expr
, s
);
8159 check_absolute_expr (ip
, &imm_expr
);
8160 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
8162 as_bad ("bad byte vector index (%ld)",
8163 (long) imm_expr
.X_add_number
);
8164 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8166 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
8167 imm_expr
.X_op
= O_absent
;
8171 /* end-sanitize-vr5400 */
8173 as_bad ("bad char = '%c'\n", *args
);
8178 /* Args don't match. */
8179 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8180 !strcmp (insn
->name
, insn
[1].name
))
8186 insn_error
= "illegal operands";
8191 /* This routine assembles an instruction into its binary format when
8192 assembling for the mips16. As a side effect, it sets one of the
8193 global variables imm_reloc or offset_reloc to the type of
8194 relocation to do if one of the operands is an address expression.
8195 It also sets mips16_small and mips16_ext if the user explicitly
8196 requested a small or extended instruction. */
8201 struct mips_cl_insn
*ip
;
8205 struct mips_opcode
*insn
;
8208 unsigned int lastregno
= 0;
8213 mips16_small
= false;
8216 for (s
= str
; islower (*s
); ++s
)
8228 if (s
[1] == 't' && s
[2] == ' ')
8231 mips16_small
= true;
8235 else if (s
[1] == 'e' && s
[2] == ' ')
8244 insn_error
= "unknown opcode";
8248 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8249 mips16_small
= true;
8251 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8253 insn_error
= "unrecognized opcode";
8260 assert (strcmp (insn
->name
, str
) == 0);
8263 ip
->insn_opcode
= insn
->match
;
8264 ip
->use_extend
= false;
8265 imm_expr
.X_op
= O_absent
;
8266 imm_reloc
= BFD_RELOC_UNUSED
;
8267 offset_expr
.X_op
= O_absent
;
8268 offset_reloc
= BFD_RELOC_UNUSED
;
8269 for (args
= insn
->args
; 1; ++args
)
8276 /* In this switch statement we call break if we did not find
8277 a match, continue if we did find a match, or return if we
8286 /* Stuff the immediate value in now, if we can. */
8287 if (imm_expr
.X_op
== O_constant
8288 && imm_reloc
> BFD_RELOC_UNUSED
8289 && insn
->pinfo
!= INSN_MACRO
)
8291 mips16_immed ((char *) NULL
, 0,
8292 imm_reloc
- BFD_RELOC_UNUSED
,
8293 imm_expr
.X_add_number
, true, mips16_small
,
8294 mips16_ext
, &ip
->insn_opcode
,
8295 &ip
->use_extend
, &ip
->extend
);
8296 imm_expr
.X_op
= O_absent
;
8297 imm_reloc
= BFD_RELOC_UNUSED
;
8311 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8314 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8330 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8332 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8359 while (isdigit (*s
));
8362 as_bad ("invalid register number (%d)", regno
);
8368 if (s
[1] == 'f' && s
[2] == 'p')
8373 else if (s
[1] == 's' && s
[2] == 'p')
8378 else if (s
[1] == 'g' && s
[2] == 'p')
8383 else if (s
[1] == 'a' && s
[2] == 't')
8388 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8393 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8406 if (c
== 'v' || c
== 'w')
8408 regno
= mips16_to_32_reg_map
[lastregno
];
8422 regno
= mips32_to_16_reg_map
[regno
];
8427 regno
= ILLEGAL_REG
;
8432 regno
= ILLEGAL_REG
;
8437 regno
= ILLEGAL_REG
;
8442 if (regno
== AT
&& ! mips_opts
.noat
)
8443 as_warn ("used $at without \".set noat\"");
8450 if (regno
== ILLEGAL_REG
)
8457 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8461 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8464 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8467 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8473 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8476 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8477 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8487 if (strncmp (s
, "$pc", 3) == 0)
8511 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8513 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8514 and generate the appropriate reloc. If the text
8515 inside %gprel is not a symbol name with an
8516 optional offset, then we generate a normal reloc
8517 and will probably fail later. */
8518 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8519 if (imm_expr
.X_op
== O_symbol
)
8522 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8524 ip
->use_extend
= true;
8531 /* Just pick up a normal expression. */
8532 my_getExpression (&imm_expr
, s
);
8535 if (imm_expr
.X_op
== O_register
)
8537 /* What we thought was an expression turned out to
8540 if (s
[0] == '(' && args
[1] == '(')
8542 /* It looks like the expression was omitted
8543 before a register indirection, which means
8544 that the expression is implicitly zero. We
8545 still set up imm_expr, so that we handle
8546 explicit extensions correctly. */
8547 imm_expr
.X_op
= O_constant
;
8548 imm_expr
.X_add_number
= 0;
8549 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8556 /* We need to relax this instruction. */
8557 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8566 /* We use offset_reloc rather than imm_reloc for the PC
8567 relative operands. This lets macros with both
8568 immediate and address operands work correctly. */
8569 my_getExpression (&offset_expr
, s
);
8571 if (offset_expr
.X_op
== O_register
)
8574 /* We need to relax this instruction. */
8575 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8579 case '6': /* break code */
8580 my_getExpression (&imm_expr
, s
);
8581 check_absolute_expr (ip
, &imm_expr
);
8582 if ((unsigned long) imm_expr
.X_add_number
> 63)
8584 as_warn ("Invalid value for `%s' (%lu)",
8586 (unsigned long) imm_expr
.X_add_number
);
8587 imm_expr
.X_add_number
&= 0x3f;
8589 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8590 imm_expr
.X_op
= O_absent
;
8594 case 'a': /* 26 bit address */
8595 my_getExpression (&offset_expr
, s
);
8597 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8598 ip
->insn_opcode
<<= 16;
8601 case 'l': /* register list for entry macro */
8602 case 'L': /* register list for exit macro */
8612 int freg
, reg1
, reg2
;
8614 while (*s
== ' ' || *s
== ',')
8618 as_bad ("can't parse register list");
8630 while (isdigit (*s
))
8652 as_bad ("invalid register list");
8657 while (isdigit (*s
))
8664 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8669 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8674 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8675 mask
|= (reg2
- 3) << 3;
8676 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8677 mask
|= (reg2
- 15) << 1;
8678 else if (reg1
== 31 && reg2
== 31)
8682 as_bad ("invalid register list");
8686 /* The mask is filled in in the opcode table for the
8687 benefit of the disassembler. We remove it before
8688 applying the actual mask. */
8689 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8690 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8694 case 'e': /* extend code */
8695 my_getExpression (&imm_expr
, s
);
8696 check_absolute_expr (ip
, &imm_expr
);
8697 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8699 as_warn ("Invalid value for `%s' (%lu)",
8701 (unsigned long) imm_expr
.X_add_number
);
8702 imm_expr
.X_add_number
&= 0x7ff;
8704 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8705 imm_expr
.X_op
= O_absent
;
8715 /* Args don't match. */
8716 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8717 strcmp (insn
->name
, insn
[1].name
) == 0)
8724 insn_error
= "illegal operands";
8730 /* This structure holds information we know about a mips16 immediate
8733 struct mips16_immed_operand
8735 /* The type code used in the argument string in the opcode table. */
8737 /* The number of bits in the short form of the opcode. */
8739 /* The number of bits in the extended form of the opcode. */
8741 /* The amount by which the short form is shifted when it is used;
8742 for example, the sw instruction has a shift count of 2. */
8744 /* The amount by which the short form is shifted when it is stored
8745 into the instruction code. */
8747 /* Non-zero if the short form is unsigned. */
8749 /* Non-zero if the extended form is unsigned. */
8751 /* Non-zero if the value is PC relative. */
8755 /* The mips16 immediate operand types. */
8757 static const struct mips16_immed_operand mips16_immed_operands
[] =
8759 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8760 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8761 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8762 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8763 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8764 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8765 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8766 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8767 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8768 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8769 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8770 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8771 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8772 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8773 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8774 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8775 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8776 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8777 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8778 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8779 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8782 #define MIPS16_NUM_IMMED \
8783 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8785 /* Handle a mips16 instruction with an immediate value. This or's the
8786 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8787 whether an extended value is needed; if one is needed, it sets
8788 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8789 If SMALL is true, an unextended opcode was explicitly requested.
8790 If EXT is true, an extended opcode was explicitly requested. If
8791 WARN is true, warn if EXT does not match reality. */
8794 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8803 unsigned long *insn
;
8804 boolean
*use_extend
;
8805 unsigned short *extend
;
8807 register const struct mips16_immed_operand
*op
;
8808 int mintiny
, maxtiny
;
8811 op
= mips16_immed_operands
;
8812 while (op
->type
!= type
)
8815 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8820 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8823 maxtiny
= 1 << op
->nbits
;
8828 maxtiny
= (1 << op
->nbits
) - 1;
8833 mintiny
= - (1 << (op
->nbits
- 1));
8834 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8837 /* Branch offsets have an implicit 0 in the lowest bit. */
8838 if (type
== 'p' || type
== 'q')
8841 if ((val
& ((1 << op
->shift
) - 1)) != 0
8842 || val
< (mintiny
<< op
->shift
)
8843 || val
> (maxtiny
<< op
->shift
))
8848 if (warn
&& ext
&& ! needext
)
8849 as_warn_where (file
, line
, "extended operand requested but not required");
8850 if (small
&& needext
)
8851 as_bad_where (file
, line
, "invalid unextended operand value");
8853 if (small
|| (! ext
&& ! needext
))
8857 *use_extend
= false;
8858 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8859 insnval
<<= op
->op_shift
;
8864 long minext
, maxext
;
8870 maxext
= (1 << op
->extbits
) - 1;
8874 minext
= - (1 << (op
->extbits
- 1));
8875 maxext
= (1 << (op
->extbits
- 1)) - 1;
8877 if (val
< minext
|| val
> maxext
)
8878 as_bad_where (file
, line
,
8879 "operand value out of range for instruction");
8882 if (op
->extbits
== 16)
8884 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8887 else if (op
->extbits
== 15)
8889 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8894 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8898 *extend
= (unsigned short) extval
;
8907 my_getSmallExpression (ep
, str
)
8918 ((str
[1] == 'h' && str
[2] == 'i')
8919 || (str
[1] == 'H' && str
[2] == 'I')
8920 || (str
[1] == 'l' && str
[2] == 'o'))
8932 * A small expression may be followed by a base register.
8933 * Scan to the end of this operand, and then back over a possible
8934 * base register. Then scan the small expression up to that
8935 * point. (Based on code in sparc.c...)
8937 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8939 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8941 if (isdigit (sp
[-2]))
8943 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8945 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8951 else if (sp
- 5 >= str
8954 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8955 || (sp
[-3] == 's' && sp
[-2] == 'p')
8956 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8957 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8963 /* no expression means zero offset */
8966 /* %xx(reg) is an error */
8967 ep
->X_op
= O_absent
;
8972 ep
->X_op
= O_constant
;
8975 ep
->X_add_symbol
= NULL
;
8976 ep
->X_op_symbol
= NULL
;
8977 ep
->X_add_number
= 0;
8982 my_getExpression (ep
, str
);
8989 my_getExpression (ep
, str
);
8990 return c
; /* => %hi or %lo encountered */
8994 my_getExpression (ep
, str
)
9000 save_in
= input_line_pointer
;
9001 input_line_pointer
= str
;
9003 expr_end
= input_line_pointer
;
9004 input_line_pointer
= save_in
;
9006 /* If we are in mips16 mode, and this is an expression based on `.',
9007 then we bump the value of the symbol by 1 since that is how other
9008 text symbols are handled. We don't bother to handle complex
9009 expressions, just `.' plus or minus a constant. */
9010 if (mips_opts
.mips16
9011 && ep
->X_op
== O_symbol
9012 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9013 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9014 && ep
->X_add_symbol
->sy_frag
== frag_now
9015 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
9016 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
9017 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
9020 /* Turn a string in input_line_pointer into a floating point constant
9021 of type type, and store the appropriate bytes in *litP. The number
9022 of LITTLENUMS emitted is stored in *sizeP . An error message is
9023 returned, or NULL on OK. */
9026 md_atof (type
, litP
, sizeP
)
9032 LITTLENUM_TYPE words
[4];
9048 return "bad call to md_atof";
9051 t
= atof_ieee (input_line_pointer
, type
, words
);
9053 input_line_pointer
= t
;
9057 if (! target_big_endian
)
9059 for (i
= prec
- 1; i
>= 0; i
--)
9061 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9067 for (i
= 0; i
< prec
; i
++)
9069 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9078 md_number_to_chars (buf
, val
, n
)
9083 if (target_big_endian
)
9084 number_to_chars_bigendian (buf
, val
, n
);
9086 number_to_chars_littleendian (buf
, val
, n
);
9089 CONST
char *md_shortopts
= "O::g::G:";
9091 struct option md_longopts
[] = {
9092 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9093 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9094 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9095 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9096 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9097 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9098 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9099 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9100 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9101 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9102 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9103 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9104 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9105 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9106 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9107 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9108 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9109 {"break", no_argument
, NULL
, OPTION_BREAK
},
9110 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9111 #define OPTION_EB (OPTION_MD_BASE + 11)
9112 {"EB", no_argument
, NULL
, OPTION_EB
},
9113 #define OPTION_EL (OPTION_MD_BASE + 12)
9114 {"EL", no_argument
, NULL
, OPTION_EL
},
9115 #define OPTION_M4650 (OPTION_MD_BASE + 13)
9116 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9117 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
9118 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9119 #define OPTION_M4010 (OPTION_MD_BASE + 15)
9120 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9121 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
9122 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9123 #define OPTION_M4100 (OPTION_MD_BASE + 17)
9124 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9125 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
9126 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9127 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
9128 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9129 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
9130 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9131 /* start-sanitize-r5900 */
9132 #define OPTION_M5900 (OPTION_MD_BASE + 24)
9133 {"m5900", no_argument
, NULL
, OPTION_M5900
},
9134 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
9135 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
9136 /* end-sanitize-r5900 */
9137 #define OPTION_M3900 (OPTION_MD_BASE + 26)
9138 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9139 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
9140 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9142 /* start-sanitize-tx19 */
9143 {"m1900", no_argument
, NULL
, OPTION_M3900
},
9144 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
9145 /* end-sanitize-tx19 */
9147 /* start-sanitize-vr5400 */
9148 #define OPTION_M5400 (OPTION_MD_BASE + 28)
9149 {"m5400", no_argument
, NULL
, OPTION_M5400
},
9150 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
9151 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
9153 /* end-sanitize-vr5400 */
9154 /* start-sanitize-tx49 */
9155 #define OPTION_M4900 (OPTION_MD_BASE + 30)
9156 {"m4900", no_argument
, NULL
, OPTION_M4900
},
9157 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
9158 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
9160 /* end-sanitize-tx49 */
9161 /* start-sanitize-vr4320 */
9162 #define OPTION_M4320 (OPTION_MD_BASE + 32)
9163 {"m4320", no_argument
, NULL
, OPTION_M4320
},
9164 #define OPTION_NO_M4320 (OPTION_MD_BASE + 33)
9165 {"no-m4320", no_argument
, NULL
, OPTION_NO_M4320
},
9167 /* end-sanitize-vr4320 */
9168 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
9169 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
9170 #define OPTION_XGOT (OPTION_MD_BASE + 19)
9171 #define OPTION_32 (OPTION_MD_BASE + 20)
9172 #define OPTION_64 (OPTION_MD_BASE + 21)
9174 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9175 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9176 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9177 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9178 {"32", no_argument
, NULL
, OPTION_32
},
9179 {"64", no_argument
, NULL
, OPTION_64
},
9182 {NULL
, no_argument
, NULL
, 0}
9184 size_t md_longopts_size
= sizeof(md_longopts
);
9187 md_parse_option (c
, arg
)
9202 target_big_endian
= 1;
9206 target_big_endian
= 0;
9210 if (arg
&& arg
[1] == '0')
9220 mips_debug
= atoi (arg
);
9221 /* When the MIPS assembler sees -g or -g2, it does not do
9222 optimizations which limit full symbolic debugging. We take
9223 that to be equivalent to -O0. */
9224 if (mips_debug
== 2)
9248 /* Identify the processor type */
9250 if (strcmp (p
, "default") == 0
9251 || strcmp (p
, "DEFAULT") == 0)
9257 /* We need to cope with the various "vr" prefixes for the 4300
9259 if (*p
== 'v' || *p
== 'V')
9265 if (*p
== 'r' || *p
== 'R')
9272 if (strcmp (p
, "10000") == 0
9273 || strcmp (p
, "10k") == 0
9274 || strcmp (p
, "10K") == 0)
9276 /* start-sanitize-tx19 */
9277 else if (strcmp (p
, "1900") == 0)
9279 /* end-sanitize-tx19 */
9283 if (strcmp (p
, "2000") == 0
9284 || strcmp (p
, "2k") == 0
9285 || strcmp (p
, "2K") == 0)
9290 if (strcmp (p
, "3000") == 0
9291 || strcmp (p
, "3k") == 0
9292 || strcmp (p
, "3K") == 0)
9294 else if (strcmp (p
, "3900") == 0)
9299 if (strcmp (p
, "4000") == 0
9300 || strcmp (p
, "4k") == 0
9301 || strcmp (p
, "4K") == 0)
9303 else if (strcmp (p
, "4100") == 0)
9305 else if (strcmp (p
, "4300") == 0)
9307 /* start-sanitize-vr4320 */
9308 else if (strcmp (p
, "4320") == 0)
9310 /* end-sanitize-vr4320 */
9311 else if (strcmp (p
, "4400") == 0)
9313 else if (strcmp (p
, "4600") == 0)
9315 else if (strcmp (p
, "4650") == 0)
9317 /* start-sanitize-tx49 */
9318 else if (strcmp (p
, "4900") == 0)
9320 /* end-sanitize-tx49 */
9321 else if (strcmp (p
, "4010") == 0)
9326 if (strcmp (p
, "5000") == 0
9327 || strcmp (p
, "5k") == 0
9328 || strcmp (p
, "5K") == 0)
9330 /* start-sanitize-vr5400 */
9331 else if (strcmp (p
, "5400") == 0)
9333 /* end-sanitize-vr5400 */
9334 /* start-sanitize-r5900 */
9335 else if (strcmp (p
, "5900") == 0)
9337 /* end-sanitize-r5900 */
9341 if (strcmp (p
, "6000") == 0
9342 || strcmp (p
, "6k") == 0
9343 || strcmp (p
, "6K") == 0)
9348 if (strcmp (p
, "8000") == 0
9349 || strcmp (p
, "8k") == 0
9350 || strcmp (p
, "8K") == 0)
9355 if (strcmp (p
, "orion") == 0)
9361 && (mips_cpu
!= 4300
9363 /* start-sanitize-vr4320 */
9365 /* end-sanitize-vr4320 */
9366 /* start-sanitize-vr5400 */
9368 /* end-sanitize-vr5400 */
9369 && mips_cpu
!= 5000))
9371 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
9377 as_bad ("invalid architecture -mcpu=%s", arg
);
9388 case OPTION_NO_M4650
:
9396 case OPTION_NO_M4010
:
9404 case OPTION_NO_M4100
:
9408 /* start-sanitize-r5900 */
9413 case OPTION_NO_M5900
:
9416 /* end-sanitize-r5900 */
9418 /* start-sanitize-vr4320 */
9423 case OPTION_NO_M4320
:
9427 /* end-sanitize-vr4320 */
9428 /* start-sanitize-vr5400 */
9433 case OPTION_NO_M5400
:
9437 /* end-sanitize-vr5400 */
9442 case OPTION_NO_M3900
:
9446 /* start-sanitize-tx49 */
9451 case OPTION_NO_M4900
:
9455 /* end-sanitize-tx49 */
9457 mips_opts
.mips16
= 1;
9458 mips_no_prev_insn (false);
9461 case OPTION_NO_MIPS16
:
9462 mips_opts
.mips16
= 0;
9463 mips_no_prev_insn (false);
9466 case OPTION_MEMBEDDED_PIC
:
9467 mips_pic
= EMBEDDED_PIC
;
9468 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9470 as_bad ("-G may not be used with embedded PIC code");
9473 g_switch_value
= 0x7fffffff;
9476 /* When generating ELF code, we permit -KPIC and -call_shared to
9477 select SVR4_PIC, and -non_shared to select no PIC. This is
9478 intended to be compatible with Irix 5. */
9479 case OPTION_CALL_SHARED
:
9480 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9482 as_bad ("-call_shared is supported only for ELF format");
9485 mips_pic
= SVR4_PIC
;
9486 if (g_switch_seen
&& g_switch_value
!= 0)
9488 as_bad ("-G may not be used with SVR4 PIC code");
9494 case OPTION_NON_SHARED
:
9495 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9497 as_bad ("-non_shared is supported only for ELF format");
9503 /* The -xgot option tells the assembler to use 32 offsets when
9504 accessing the got in SVR4_PIC mode. It is for Irix
9511 if (! USE_GLOBAL_POINTER_OPT
)
9513 as_bad ("-G is not supported for this configuration");
9516 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9518 as_bad ("-G may not be used with SVR4 or embedded PIC code");
9522 g_switch_value
= atoi (arg
);
9526 /* The -32 and -64 options tell the assembler to output the 32
9527 bit or the 64 bit MIPS ELF format. */
9534 const char **list
, **l
;
9536 list
= bfd_target_list ();
9537 for (l
= list
; *l
!= NULL
; l
++)
9538 if (strcmp (*l
, "elf64-bigmips") == 0
9539 || strcmp (*l
, "elf64-littlemips") == 0)
9542 as_fatal ("No compiled in support for 64 bit object file format");
9556 md_show_usage (stream
)
9561 -membedded-pic generate embedded position independent code\n\
9562 -EB generate big endian output\n\
9563 -EL generate little endian output\n\
9564 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9565 -G NUM allow referencing objects up to NUM bytes\n\
9566 implicitly with the gp register [default 8]\n");
9568 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
9569 -mips2, -mcpu=r6000 generate code for r6000\n\
9570 -mips3, -mcpu=r4000 generate code for r4000\n\
9571 -mips4, -mcpu=r8000 generate code for r8000\n\
9572 -mcpu=vr4300 generate code for vr4300\n\
9573 -mcpu=vr4100 generate code for vr4100\n\
9574 -m4650 permit R4650 instructions\n\
9575 -no-m4650 do not permit R4650 instructions\n\
9576 -m4010 permit R4010 instructions\n\
9577 -no-m4010 do not permit R4010 instructions\n\
9578 -m4100 permit VR4100 instructions\n\
9579 -no-m4100 do not permit VR4100 instructions\n");
9581 -mips16 generate mips16 instructions\n\
9582 -no-mips16 do not generate mips16 instructions\n");
9584 -O0 remove unneeded NOPs, do not swap branches\n\
9585 -O remove unneeded NOPs and swap branches\n\
9586 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9587 --break, --no-trap break exception on div by 0 and mult overflow\n");
9590 -KPIC, -call_shared generate SVR4 position independent code\n\
9591 -non_shared do not generate position independent code\n\
9592 -xgot assume a 32 bit GOT\n\
9593 -32 create 32 bit object file (default)\n\
9594 -64 create 64 bit object file\n");
9599 mips_init_after_args ()
9601 /* initialize opcodes */
9602 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9603 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9607 md_pcrel_from (fixP
)
9610 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9611 && fixP
->fx_addsy
!= (symbolS
*) NULL
9612 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9614 /* This makes a branch to an undefined symbol be a branch to the
9615 current location. */
9619 /* return the address of the delay slot */
9620 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9623 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9624 reloc for a cons. We could use the definition there, except that
9625 we want to handle 64 bit relocs specially. */
9628 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9631 unsigned int nbytes
;
9635 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9637 if (nbytes
== 8 && ! mips_64
)
9639 if (target_big_endian
)
9645 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9646 as_bad ("Unsupported reloc size %d", nbytes
);
9648 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9651 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9654 /* This is called before the symbol table is processed. In order to
9655 work with gcc when using mips-tfile, we must keep all local labels.
9656 However, in other cases, we want to discard them. If we were
9657 called with -g, but we didn't see any debugging information, it may
9658 mean that gcc is smuggling debugging information through to
9659 mips-tfile, in which case we must generate all local labels. */
9662 mips_frob_file_before_adjust ()
9664 #ifndef NO_ECOFF_DEBUGGING
9667 && ! ecoff_debugging_seen
)
9668 flag_keep_locals
= 1;
9672 /* Sort any unmatched HI16_S relocs so that they immediately precede
9673 the corresponding LO reloc. This is called before md_apply_fix and
9674 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9675 explicit use of the %hi modifier. */
9680 struct mips_hi_fixup
*l
;
9682 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9684 segment_info_type
*seginfo
;
9687 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9689 /* Check quickly whether the next fixup happens to be a matching
9691 if (l
->fixp
->fx_next
!= NULL
9692 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9693 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9694 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9697 /* Look through the fixups for this segment for a matching %lo.
9698 When we find one, move the %hi just in front of it. We do
9699 this in two passes. In the first pass, we try to find a
9700 unique %lo. In the second pass, we permit multiple %hi
9701 relocs for a single %lo (this is a GNU extension). */
9702 seginfo
= seg_info (l
->seg
);
9703 for (pass
= 0; pass
< 2; pass
++)
9708 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9710 /* Check whether this is a %lo fixup which matches l->fixp. */
9711 if (f
->fx_r_type
== BFD_RELOC_LO16
9712 && f
->fx_addsy
== l
->fixp
->fx_addsy
9713 && f
->fx_offset
== l
->fixp
->fx_offset
9716 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9717 || prev
->fx_addsy
!= f
->fx_addsy
9718 || prev
->fx_offset
!= f
->fx_offset
))
9722 /* Move l->fixp before f. */
9723 for (pf
= &seginfo
->fix_root
;
9725 pf
= &(*pf
)->fx_next
)
9726 assert (*pf
!= NULL
);
9728 *pf
= l
->fixp
->fx_next
;
9730 l
->fixp
->fx_next
= f
;
9732 seginfo
->fix_root
= l
->fixp
;
9734 prev
->fx_next
= l
->fixp
;
9746 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9747 "Unmatched %%hi reloc");
9752 /* When generating embedded PIC code we need to use a special
9753 relocation to represent the difference of two symbols in the .text
9754 section (switch tables use a difference of this sort). See
9755 include/coff/mips.h for details. This macro checks whether this
9756 fixup requires the special reloc. */
9757 #define SWITCH_TABLE(fixp) \
9758 ((fixp)->fx_r_type == BFD_RELOC_32 \
9759 && (fixp)->fx_addsy != NULL \
9760 && (fixp)->fx_subsy != NULL \
9761 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9762 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9764 /* When generating embedded PIC code we must keep all PC relative
9765 relocations, in case the linker has to relax a call. We also need
9766 to keep relocations for switch table entries. */
9770 mips_force_relocation (fixp
)
9773 return (mips_pic
== EMBEDDED_PIC
9775 || SWITCH_TABLE (fixp
)
9776 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9777 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9780 /* Apply a fixup to the object file. */
9783 md_apply_fix (fixP
, valueP
)
9790 assert (fixP
->fx_size
== 4
9791 || fixP
->fx_r_type
== BFD_RELOC_16
9792 || fixP
->fx_r_type
== BFD_RELOC_64
);
9796 /* If we aren't adjusting this fixup to be against the section
9797 symbol, we need to adjust the value. */
9799 if (fixP
->fx_addsy
!= NULL
9800 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
9801 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
9803 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9804 if (value
!= 0 && ! fixP
->fx_pcrel
)
9806 /* In this case, the bfd_install_relocation routine will
9807 incorrectly add the symbol value back in. We just want
9808 the addend to appear in the object file. */
9809 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9814 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9816 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9819 switch (fixP
->fx_r_type
)
9821 case BFD_RELOC_MIPS_JMP
:
9822 case BFD_RELOC_HI16
:
9823 case BFD_RELOC_HI16_S
:
9824 case BFD_RELOC_MIPS_GPREL
:
9825 case BFD_RELOC_MIPS_LITERAL
:
9826 case BFD_RELOC_MIPS_CALL16
:
9827 case BFD_RELOC_MIPS_GOT16
:
9828 case BFD_RELOC_MIPS_GPREL32
:
9829 case BFD_RELOC_MIPS_GOT_HI16
:
9830 case BFD_RELOC_MIPS_GOT_LO16
:
9831 case BFD_RELOC_MIPS_CALL_HI16
:
9832 case BFD_RELOC_MIPS_CALL_LO16
:
9833 case BFD_RELOC_MIPS16_GPREL
:
9834 /* start-sanitize-r5900 */
9835 case BFD_RELOC_MIPS15_S3
:
9836 /* end-sanitize-r5900 */
9838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9839 "Invalid PC relative reloc");
9840 /* Nothing needed to do. The value comes from the reloc entry */
9843 case BFD_RELOC_MIPS16_JMP
:
9844 /* We currently always generate a reloc against a symbol, which
9845 means that we don't want an addend even if the symbol is
9847 fixP
->fx_addnumber
= 0;
9850 case BFD_RELOC_PCREL_HI16_S
:
9851 /* The addend for this is tricky if it is internal, so we just
9852 do everything here rather than in bfd_install_relocation. */
9853 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9855 /* For an external symbol adjust by the address to make it
9856 pcrel_offset. We use the address of the RELLO reloc
9857 which follows this one. */
9858 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9859 + fixP
->fx_next
->fx_where
);
9864 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9865 if (target_big_endian
)
9867 md_number_to_chars (buf
, value
, 2);
9870 case BFD_RELOC_PCREL_LO16
:
9871 /* The addend for this is tricky if it is internal, so we just
9872 do everything here rather than in bfd_install_relocation. */
9873 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9874 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9875 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9876 if (target_big_endian
)
9878 md_number_to_chars (buf
, value
, 2);
9882 /* This is handled like BFD_RELOC_32, but we output a sign
9883 extended value if we are only 32 bits. */
9885 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9887 if (8 <= sizeof (valueT
))
9888 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9895 w1
= w2
= fixP
->fx_where
;
9896 if (target_big_endian
)
9900 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9901 if ((value
& 0x80000000) != 0)
9905 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9911 /* If we are deleting this reloc entry, we must fill in the
9912 value now. This can happen if we have a .word which is not
9913 resolved when it appears but is later defined. We also need
9914 to fill in the value if this is an embedded PIC switch table
9917 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9918 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9923 /* If we are deleting this reloc entry, we must fill in the
9925 assert (fixP
->fx_size
== 2);
9927 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9931 case BFD_RELOC_LO16
:
9932 /* When handling an embedded PIC switch statement, we can wind
9933 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9936 if (value
< -0x8000 || value
> 0x7fff)
9937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9938 "relocation overflow");
9939 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9940 if (target_big_endian
)
9942 md_number_to_chars (buf
, value
, 2);
9946 case BFD_RELOC_16_PCREL_S2
:
9948 * We need to save the bits in the instruction since fixup_segment()
9949 * might be deleting the relocation entry (i.e., a branch within
9950 * the current segment).
9952 if ((value
& 0x3) != 0)
9953 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9954 "Branch to odd address (%lx)", value
);
9957 /* update old instruction data */
9958 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9959 if (target_big_endian
)
9960 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9962 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9964 if (value
>= -0x8000 && value
< 0x8000)
9965 insn
|= value
& 0xffff;
9968 /* The branch offset is too large. If this is an
9969 unconditional branch, and we are not generating PIC code,
9970 we can convert it to an absolute jump instruction. */
9971 if (mips_pic
== NO_PIC
9973 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9974 && (fixP
->fx_frag
->fr_address
9975 < text_section
->vma
+ text_section
->_raw_size
)
9976 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9977 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9978 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9980 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9981 insn
= 0x0c000000; /* jal */
9983 insn
= 0x08000000; /* j */
9984 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9986 fixP
->fx_addsy
= section_symbol (text_section
);
9987 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9991 /* FIXME. It would be possible in principle to handle
9992 conditional branches which overflow. They could be
9993 transformed into a branch around a jump. This would
9994 require setting up variant frags for each different
9995 branch type. The native MIPS assembler attempts to
9996 handle these cases, but it appears to do it
9998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9999 "Branch out of range");
10003 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10018 const struct mips_opcode
*p
;
10019 int treg
, sreg
, dreg
, shamt
;
10024 for (i
= 0; i
< NUMOPCODES
; ++i
)
10026 p
= &mips_opcodes
[i
];
10027 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10029 printf ("%08lx %s\t", oc
, p
->name
);
10030 treg
= (oc
>> 16) & 0x1f;
10031 sreg
= (oc
>> 21) & 0x1f;
10032 dreg
= (oc
>> 11) & 0x1f;
10033 shamt
= (oc
>> 6) & 0x1f;
10035 for (args
= p
->args
;; ++args
)
10046 printf ("%c", *args
);
10050 assert (treg
== sreg
);
10051 printf ("$%d,$%d", treg
, sreg
);
10056 printf ("$%d", dreg
);
10061 printf ("$%d", treg
);
10065 printf ("0x%x", treg
);
10070 printf ("$%d", sreg
);
10074 printf ("0x%08lx", oc
& 0x1ffffff);
10081 printf ("%d", imm
);
10086 printf ("$%d", shamt
);
10097 printf ("%08lx UNDEFINED\n", oc
);
10108 name
= input_line_pointer
;
10109 c
= get_symbol_end ();
10110 p
= (symbolS
*) symbol_find_or_make (name
);
10111 *input_line_pointer
= c
;
10115 /* Align the current frag to a given power of two. The MIPS assembler
10116 also automatically adjusts any preceding label. */
10119 mips_align (to
, fill
, label
)
10124 mips_emit_delays (false);
10125 frag_align (to
, fill
, 0);
10126 record_alignment (now_seg
, to
);
10129 assert (S_GET_SEGMENT (label
) == now_seg
);
10130 label
->sy_frag
= frag_now
;
10131 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10135 /* Align to a given power of two. .align 0 turns off the automatic
10136 alignment used by the data creating pseudo-ops. */
10143 register long temp_fill
;
10144 long max_alignment
= 15;
10148 o Note that the assembler pulls down any immediately preceeding label
10149 to the aligned address.
10150 o It's not documented but auto alignment is reinstated by
10151 a .align pseudo instruction.
10152 o Note also that after auto alignment is turned off the mips assembler
10153 issues an error on attempt to assemble an improperly aligned data item.
10158 temp
= get_absolute_expression ();
10159 if (temp
> max_alignment
)
10160 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
10163 as_warn ("Alignment negative: 0 assumed.");
10166 if (*input_line_pointer
== ',')
10168 input_line_pointer
++;
10169 temp_fill
= get_absolute_expression ();
10176 mips_align (temp
, (int) temp_fill
,
10177 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10184 demand_empty_rest_of_line ();
10188 mips_flush_pending_output ()
10190 mips_emit_delays (false);
10191 mips_clear_insn_labels ();
10200 /* When generating embedded PIC code, we only use the .text, .lit8,
10201 .sdata and .sbss sections. We change the .data and .rdata
10202 pseudo-ops to use .sdata. */
10203 if (mips_pic
== EMBEDDED_PIC
10204 && (sec
== 'd' || sec
== 'r'))
10208 /* The ELF backend needs to know that we are changing sections, so
10209 that .previous works correctly. We could do something like check
10210 for a obj_section_change_hook macro, but that might be confusing
10211 as it would not be appropriate to use it in the section changing
10212 functions in read.c, since obj-elf.c intercepts those. FIXME:
10213 This should be cleaner, somehow. */
10214 obj_elf_section_change_hook ();
10217 mips_emit_delays (false);
10227 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10228 demand_empty_rest_of_line ();
10232 if (USE_GLOBAL_POINTER_OPT
)
10234 seg
= subseg_new (RDATA_SECTION_NAME
,
10235 (subsegT
) get_absolute_expression ());
10236 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10238 bfd_set_section_flags (stdoutput
, seg
,
10244 if (strcmp (TARGET_OS
, "elf") != 0)
10245 bfd_set_section_alignment (stdoutput
, seg
, 4);
10247 demand_empty_rest_of_line ();
10251 as_bad ("No read only data section in this object file format");
10252 demand_empty_rest_of_line ();
10258 if (USE_GLOBAL_POINTER_OPT
)
10260 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10261 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10263 bfd_set_section_flags (stdoutput
, seg
,
10264 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10266 if (strcmp (TARGET_OS
, "elf") != 0)
10267 bfd_set_section_alignment (stdoutput
, seg
, 4);
10269 demand_empty_rest_of_line ();
10274 as_bad ("Global pointers not supported; recompile -G 0");
10275 demand_empty_rest_of_line ();
10284 mips_enable_auto_align ()
10295 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10296 mips_emit_delays (false);
10297 if (log_size
> 0 && auto_align
)
10298 mips_align (log_size
, 0, label
);
10299 mips_clear_insn_labels ();
10300 cons (1 << log_size
);
10304 s_float_cons (type
)
10309 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10311 mips_emit_delays (false);
10315 mips_align (3, 0, label
);
10317 mips_align (2, 0, label
);
10319 mips_clear_insn_labels ();
10324 /* Handle .globl. We need to override it because on Irix 5 you are
10327 where foo is an undefined symbol, to mean that foo should be
10328 considered to be the address of a function. */
10339 name
= input_line_pointer
;
10340 c
= get_symbol_end ();
10341 symbolP
= symbol_find_or_make (name
);
10342 *input_line_pointer
= c
;
10343 SKIP_WHITESPACE ();
10345 /* On Irix 5, every global symbol that is not explicitly labelled as
10346 being a function is apparently labelled as being an object. */
10349 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10354 secname
= input_line_pointer
;
10355 c
= get_symbol_end ();
10356 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10358 as_bad ("%s: no such section", secname
);
10359 *input_line_pointer
= c
;
10361 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10362 flag
= BSF_FUNCTION
;
10365 symbolP
->bsym
->flags
|= flag
;
10367 S_SET_EXTERNAL (symbolP
);
10368 demand_empty_rest_of_line ();
10378 opt
= input_line_pointer
;
10379 c
= get_symbol_end ();
10383 /* FIXME: What does this mean? */
10385 else if (strncmp (opt
, "pic", 3) == 0)
10389 i
= atoi (opt
+ 3);
10393 mips_pic
= SVR4_PIC
;
10395 as_bad (".option pic%d not supported", i
);
10397 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10399 if (g_switch_seen
&& g_switch_value
!= 0)
10400 as_warn ("-G may not be used with SVR4 PIC code");
10401 g_switch_value
= 0;
10402 bfd_set_gp_size (stdoutput
, 0);
10406 as_warn ("Unrecognized option \"%s\"", opt
);
10408 *input_line_pointer
= c
;
10409 demand_empty_rest_of_line ();
10412 /* This structure is used to hold a stack of .set values. */
10414 struct mips_option_stack
10416 struct mips_option_stack
*next
;
10417 struct mips_set_options options
;
10420 static struct mips_option_stack
*mips_opts_stack
;
10422 /* Handle the .set pseudo-op. */
10428 char *name
= input_line_pointer
, ch
;
10430 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10431 input_line_pointer
++;
10432 ch
= *input_line_pointer
;
10433 *input_line_pointer
= '\0';
10435 if (strcmp (name
, "reorder") == 0)
10437 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10439 /* If we still have pending nops, we can discard them. The
10440 usual nop handling will insert any that are still
10442 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10443 * (mips_opts
.mips16
? 2 : 4));
10444 prev_nop_frag
= NULL
;
10446 mips_opts
.noreorder
= 0;
10448 else if (strcmp (name
, "noreorder") == 0)
10450 mips_emit_delays (true);
10451 mips_opts
.noreorder
= 1;
10452 mips_any_noreorder
= 1;
10454 else if (strcmp (name
, "at") == 0)
10456 mips_opts
.noat
= 0;
10458 else if (strcmp (name
, "noat") == 0)
10460 mips_opts
.noat
= 1;
10462 else if (strcmp (name
, "macro") == 0)
10464 mips_opts
.warn_about_macros
= 0;
10466 else if (strcmp (name
, "nomacro") == 0)
10468 if (mips_opts
.noreorder
== 0)
10469 as_bad ("`noreorder' must be set before `nomacro'");
10470 mips_opts
.warn_about_macros
= 1;
10472 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10474 mips_opts
.nomove
= 0;
10476 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10478 mips_opts
.nomove
= 1;
10480 else if (strcmp (name
, "bopt") == 0)
10482 mips_opts
.nobopt
= 0;
10484 else if (strcmp (name
, "nobopt") == 0)
10486 mips_opts
.nobopt
= 1;
10488 else if (strcmp (name
, "mips16") == 0
10489 || strcmp (name
, "MIPS-16") == 0)
10490 mips_opts
.mips16
= 1;
10491 else if (strcmp (name
, "nomips16") == 0
10492 || strcmp (name
, "noMIPS-16") == 0)
10493 mips_opts
.mips16
= 0;
10494 else if (strncmp (name
, "mips", 4) == 0)
10498 /* Permit the user to change the ISA on the fly. Needless to
10499 say, misuse can cause serious problems. */
10500 isa
= atoi (name
+ 4);
10502 mips_opts
.isa
= file_mips_isa
;
10503 else if (isa
< 1 || isa
> 4)
10504 as_bad ("unknown ISA level");
10506 mips_opts
.isa
= isa
;
10508 else if (strcmp (name
, "autoextend") == 0)
10509 mips_opts
.noautoextend
= 0;
10510 else if (strcmp (name
, "noautoextend") == 0)
10511 mips_opts
.noautoextend
= 1;
10512 else if (strcmp (name
, "push") == 0)
10514 struct mips_option_stack
*s
;
10516 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10517 s
->next
= mips_opts_stack
;
10518 s
->options
= mips_opts
;
10519 mips_opts_stack
= s
;
10521 else if (strcmp (name
, "pop") == 0)
10523 struct mips_option_stack
*s
;
10525 s
= mips_opts_stack
;
10527 as_bad (".set pop with no .set push");
10530 /* If we're changing the reorder mode we need to handle
10531 delay slots correctly. */
10532 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10533 mips_emit_delays (true);
10534 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10536 if (prev_nop_frag
!= NULL
)
10538 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10539 * (mips_opts
.mips16
? 2 : 4));
10540 prev_nop_frag
= NULL
;
10544 mips_opts
= s
->options
;
10545 mips_opts_stack
= s
->next
;
10551 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
10553 *input_line_pointer
= ch
;
10554 demand_empty_rest_of_line ();
10557 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10558 .option pic2. It means to generate SVR4 PIC calls. */
10561 s_abicalls (ignore
)
10564 mips_pic
= SVR4_PIC
;
10565 if (USE_GLOBAL_POINTER_OPT
)
10567 if (g_switch_seen
&& g_switch_value
!= 0)
10568 as_warn ("-G may not be used with SVR4 PIC code");
10569 g_switch_value
= 0;
10571 bfd_set_gp_size (stdoutput
, 0);
10572 demand_empty_rest_of_line ();
10575 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10576 PIC code. It sets the $gp register for the function based on the
10577 function address, which is in the register named in the argument.
10578 This uses a relocation against _gp_disp, which is handled specially
10579 by the linker. The result is:
10580 lui $gp,%hi(_gp_disp)
10581 addiu $gp,$gp,%lo(_gp_disp)
10582 addu $gp,$gp,.cpload argument
10583 The .cpload argument is normally $25 == $t9. */
10592 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10593 if (mips_pic
!= SVR4_PIC
)
10599 /* .cpload should be a in .set noreorder section. */
10600 if (mips_opts
.noreorder
== 0)
10601 as_warn (".cpload not in noreorder section");
10603 ex
.X_op
= O_symbol
;
10604 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10605 ex
.X_op_symbol
= NULL
;
10606 ex
.X_add_number
= 0;
10608 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10609 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10611 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10612 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10613 (int) BFD_RELOC_LO16
);
10615 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10616 GP
, GP
, tc_get_register (0));
10618 demand_empty_rest_of_line ();
10621 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10622 offset from $sp. The offset is remembered, and after making a PIC
10623 call $gp is restored from that location. */
10626 s_cprestore (ignore
)
10632 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10633 if (mips_pic
!= SVR4_PIC
)
10639 mips_cprestore_offset
= get_absolute_expression ();
10641 ex
.X_op
= O_constant
;
10642 ex
.X_add_symbol
= NULL
;
10643 ex
.X_op_symbol
= NULL
;
10644 ex
.X_add_number
= mips_cprestore_offset
;
10646 macro_build ((char *) NULL
, &icnt
, &ex
,
10647 ((bfd_arch_bits_per_address (stdoutput
) == 32
10648 || mips_opts
.isa
< 3)
10650 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10652 demand_empty_rest_of_line ();
10655 /* Handle the .gpword pseudo-op. This is used when generating PIC
10656 code. It generates a 32 bit GP relative reloc. */
10666 /* When not generating PIC code, this is treated as .word. */
10667 if (mips_pic
!= SVR4_PIC
)
10673 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10674 mips_emit_delays (true);
10676 mips_align (2, 0, label
);
10677 mips_clear_insn_labels ();
10681 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10683 as_bad ("Unsupported use of .gpword");
10684 ignore_rest_of_line ();
10688 md_number_to_chars (p
, (valueT
) 0, 4);
10689 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10690 BFD_RELOC_MIPS_GPREL32
);
10692 demand_empty_rest_of_line ();
10695 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10696 tables in SVR4 PIC code. */
10705 /* This is ignored when not generating SVR4 PIC code. */
10706 if (mips_pic
!= SVR4_PIC
)
10712 /* Add $gp to the register named as an argument. */
10713 reg
= tc_get_register (0);
10714 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10715 ((bfd_arch_bits_per_address (stdoutput
) == 32
10716 || mips_opts
.isa
< 3)
10717 ? "addu" : "daddu"),
10718 "d,v,t", reg
, reg
, GP
);
10720 demand_empty_rest_of_line ();
10723 /* Handle the .insn pseudo-op. This marks instruction labels in
10724 mips16 mode. This permits the linker to handle them specially,
10725 such as generating jalx instructions when needed. We also make
10726 them odd for the duration of the assembly, in order to generate the
10727 right sort of code. We will make them even in the adjust_symtab
10728 routine, while leaving them marked. This is convenient for the
10729 debugger and the disassembler. The linker knows to make them odd
10736 if (mips_opts
.mips16
)
10737 mips16_mark_labels ();
10739 demand_empty_rest_of_line ();
10742 /* Handle a .stabn directive. We need these in order to mark a label
10743 as being a mips16 text label correctly. Sometimes the compiler
10744 will emit a label, followed by a .stabn, and then switch sections.
10745 If the label and .stabn are in mips16 mode, then the label is
10746 really a mips16 text label. */
10752 if (type
== 'n' && mips_opts
.mips16
)
10753 mips16_mark_labels ();
10758 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10762 s_mips_weakext (ignore
)
10770 name
= input_line_pointer
;
10771 c
= get_symbol_end ();
10772 symbolP
= symbol_find_or_make (name
);
10773 S_SET_WEAK (symbolP
);
10774 *input_line_pointer
= c
;
10776 SKIP_WHITESPACE ();
10778 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10780 if (S_IS_DEFINED (symbolP
))
10782 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10783 S_GET_NAME (symbolP
));
10784 ignore_rest_of_line ();
10788 if (*input_line_pointer
== ',')
10790 ++input_line_pointer
;
10791 SKIP_WHITESPACE ();
10795 if (exp
.X_op
!= O_symbol
)
10797 as_bad ("bad .weakext directive");
10798 ignore_rest_of_line();
10801 symbolP
->sy_value
= exp
;
10804 demand_empty_rest_of_line ();
10807 /* Parse a register string into a number. Called from the ECOFF code
10808 to parse .frame. The argument is non-zero if this is the frame
10809 register, so that we can record it in mips_frame_reg. */
10812 tc_get_register (frame
)
10817 SKIP_WHITESPACE ();
10818 if (*input_line_pointer
++ != '$')
10820 as_warn ("expected `$'");
10823 else if (isdigit ((unsigned char) *input_line_pointer
))
10825 reg
= get_absolute_expression ();
10826 if (reg
< 0 || reg
>= 32)
10828 as_warn ("Bad register number");
10834 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10836 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10838 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10840 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10844 as_warn ("Unrecognized register name");
10847 input_line_pointer
+= 2;
10850 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10855 md_section_align (seg
, addr
)
10859 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10862 /* We don't need to align ELF sections to the full alignment.
10863 However, Irix 5 may prefer that we align them at least to a 16
10864 byte boundary. We don't bother to align the sections if we are
10865 targeted for an embedded system. */
10866 if (strcmp (TARGET_OS
, "elf") == 0)
10872 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10875 /* Utility routine, called from above as well. If called while the
10876 input file is still being read, it's only an approximation. (For
10877 example, a symbol may later become defined which appeared to be
10878 undefined earlier.) */
10881 nopic_need_relax (sym
, before_relaxing
)
10883 int before_relaxing
;
10888 if (USE_GLOBAL_POINTER_OPT
)
10890 const char *symname
;
10893 /* Find out whether this symbol can be referenced off the GP
10894 register. It can be if it is smaller than the -G size or if
10895 it is in the .sdata or .sbss section. Certain symbols can
10896 not be referenced off the GP, although it appears as though
10898 symname
= S_GET_NAME (sym
);
10899 if (symname
!= (const char *) NULL
10900 && (strcmp (symname
, "eprol") == 0
10901 || strcmp (symname
, "etext") == 0
10902 || strcmp (symname
, "_gp") == 0
10903 || strcmp (symname
, "edata") == 0
10904 || strcmp (symname
, "_fbss") == 0
10905 || strcmp (symname
, "_fdata") == 0
10906 || strcmp (symname
, "_ftext") == 0
10907 || strcmp (symname
, "end") == 0
10908 || strcmp (symname
, "_gp_disp") == 0))
10910 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10912 #ifndef NO_ECOFF_DEBUGGING
10913 || (sym
->ecoff_extern_size
!= 0
10914 && sym
->ecoff_extern_size
<= g_switch_value
)
10916 /* We must defer this decision until after the whole
10917 file has been read, since there might be a .extern
10918 after the first use of this symbol. */
10919 || (before_relaxing
10920 #ifndef NO_ECOFF_DEBUGGING
10921 && sym
->ecoff_extern_size
== 0
10923 && S_GET_VALUE (sym
) == 0)
10924 || (S_GET_VALUE (sym
) != 0
10925 && S_GET_VALUE (sym
) <= g_switch_value
)))
10929 const char *segname
;
10931 segname
= segment_name (S_GET_SEGMENT (sym
));
10932 assert (strcmp (segname
, ".lit8") != 0
10933 && strcmp (segname
, ".lit4") != 0);
10934 change
= (strcmp (segname
, ".sdata") != 0
10935 && strcmp (segname
, ".sbss") != 0);
10940 /* We are not optimizing for the GP register. */
10944 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10945 extended opcode. SEC is the section the frag is in. */
10948 mips16_extended_frag (fragp
, sec
, stretch
)
10954 register const struct mips16_immed_operand
*op
;
10956 int mintiny
, maxtiny
;
10959 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10961 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10964 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10965 op
= mips16_immed_operands
;
10966 while (op
->type
!= type
)
10969 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10974 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10977 maxtiny
= 1 << op
->nbits
;
10982 maxtiny
= (1 << op
->nbits
) - 1;
10987 mintiny
= - (1 << (op
->nbits
- 1));
10988 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10991 /* We can't call S_GET_VALUE here, because we don't want to lock in
10992 a particular frag address. */
10993 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10995 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10996 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10997 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10999 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
11000 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
11003 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
11004 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
11005 + fragp
->fr_symbol
->sy_value
.X_add_number
11006 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11007 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
11016 /* We won't have the section when we are called from
11017 mips_relax_frag. However, we will always have been called
11018 from md_estimate_size_before_relax first. If this is a
11019 branch to a different section, we mark it as such. If SEC is
11020 NULL, and the frag is not marked, then it must be a branch to
11021 the same section. */
11024 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11031 fragp
->fr_subtype
=
11032 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11034 /* FIXME: We should support this, and let the linker
11035 catch branches and loads that are out of range. */
11036 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11037 "unsupported PC relative reference to different section");
11043 /* In this case, we know for sure that the symbol fragment is in
11044 the same section. If the fr_address of the symbol fragment
11045 is greater then the address of this fragment we want to add
11046 in STRETCH in order to get a better estimate of the address.
11047 This particularly matters because of the shift bits. */
11049 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
11053 /* Adjust stretch for any alignment frag. Note that if have
11054 been expanding the earlier code, the symbol may be
11055 defined in what appears to be an earlier frag. FIXME:
11056 This doesn't handle the fr_subtype field, which specifies
11057 a maximum number of bytes to skip when doing an
11060 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
11063 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11066 stretch
= - ((- stretch
)
11067 & ~ ((1 << (int) f
->fr_offset
) - 1));
11069 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11078 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11080 /* The base address rules are complicated. The base address of
11081 a branch is the following instruction. The base address of a
11082 PC relative load or add is the instruction itself, but if it
11083 is in a delay slot (in which case it can not be extended) use
11084 the address of the instruction whose delay slot it is in. */
11085 if (type
== 'p' || type
== 'q')
11089 /* If we are currently assuming that this frag should be
11090 extended, then, the current address is two bytes
11092 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11095 /* Ignore the low bit in the target, since it will be set
11096 for a text label. */
11097 if ((val
& 1) != 0)
11100 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11102 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11105 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11107 /* Branch offsets have an implicit 0 in the lowest bit. */
11108 if (type
== 'p' || type
== 'q')
11111 /* If any of the shifted bits are set, we must use an extended
11112 opcode. If the address depends on the size of this
11113 instruction, this can lead to a loop, so we arrange to always
11114 use an extended opcode. We only check this when we are in
11115 the main relaxation loop, when SEC is NULL. */
11116 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11118 fragp
->fr_subtype
=
11119 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11123 /* If we are about to mark a frag as extended because the value
11124 is precisely maxtiny + 1, then there is a chance of an
11125 infinite loop as in the following code:
11130 In this case when the la is extended, foo is 0x3fc bytes
11131 away, so the la can be shrunk, but then foo is 0x400 away, so
11132 the la must be extended. To avoid this loop, we mark the
11133 frag as extended if it was small, and is about to become
11134 extended with a value of maxtiny + 1. */
11135 if (val
== ((maxtiny
+ 1) << op
->shift
)
11136 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11139 fragp
->fr_subtype
=
11140 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11144 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11145 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
11147 if ((val
& ((1 << op
->shift
) - 1)) != 0
11148 || val
< (mintiny
<< op
->shift
)
11149 || val
> (maxtiny
<< op
->shift
))
11155 /* Estimate the size of a frag before relaxing. Unless this is the
11156 mips16, we are not really relaxing here, and the final size is
11157 encoded in the subtype information. For the mips16, we have to
11158 decide whether we are using an extended opcode or not. */
11162 md_estimate_size_before_relax (fragp
, segtype
)
11168 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11170 if (mips16_extended_frag (fragp
, segtype
, 0))
11172 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11177 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11182 if (mips_pic
== NO_PIC
)
11184 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11186 else if (mips_pic
== SVR4_PIC
)
11191 sym
= fragp
->fr_symbol
;
11193 /* Handle the case of a symbol equated to another symbol. */
11194 while (sym
->sy_value
.X_op
== O_symbol
11195 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11199 /* It's possible to get a loop here in a badly written
11201 n
= sym
->sy_value
.X_add_symbol
;
11207 symsec
= S_GET_SEGMENT (sym
);
11209 /* This must duplicate the test in adjust_reloc_syms. */
11210 change
= (symsec
!= &bfd_und_section
11211 && symsec
!= &bfd_abs_section
11212 && ! bfd_is_com_section (symsec
));
11219 /* Record the offset to the first reloc in the fr_opcode field.
11220 This lets md_convert_frag and tc_gen_reloc know that the code
11221 must be expanded. */
11222 fragp
->fr_opcode
= (fragp
->fr_literal
11224 - RELAX_OLD (fragp
->fr_subtype
)
11225 + RELAX_RELOC1 (fragp
->fr_subtype
));
11226 /* FIXME: This really needs as_warn_where. */
11227 if (RELAX_WARN (fragp
->fr_subtype
))
11228 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
11234 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11237 /* This is called to see whether a reloc against a defined symbol
11238 should be converted into a reloc against a section. Don't adjust
11239 MIPS16 jump relocations, so we don't have to worry about the format
11240 of the offset in the .o file. Don't adjust relocations against
11241 mips16 symbols, so that the linker can find them if it needs to set
11245 mips_fix_adjustable (fixp
)
11248 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11250 if (fixp
->fx_addsy
== NULL
)
11253 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11254 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11255 && fixp
->fx_subsy
== NULL
)
11261 /* Translate internal representation of relocation info to BFD target
11265 tc_gen_reloc (section
, fixp
)
11269 static arelent
*retval
[4];
11271 bfd_reloc_code_real_type code
;
11273 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11276 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11277 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11279 if (mips_pic
== EMBEDDED_PIC
11280 && SWITCH_TABLE (fixp
))
11282 /* For a switch table entry we use a special reloc. The addend
11283 is actually the difference between the reloc address and the
11285 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11286 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11287 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
11288 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11290 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11292 /* We use a special addend for an internal RELLO reloc. */
11293 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11294 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11296 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11298 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11300 assert (fixp
->fx_next
!= NULL
11301 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11302 /* We use a special addend for an internal RELHI reloc. The
11303 reloc is relative to the RELLO; adjust the addend
11305 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11306 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11307 + fixp
->fx_next
->fx_where
11308 - S_GET_VALUE (fixp
->fx_subsy
));
11310 reloc
->addend
= (fixp
->fx_addnumber
11311 + fixp
->fx_next
->fx_frag
->fr_address
11312 + fixp
->fx_next
->fx_where
);
11314 else if (fixp
->fx_pcrel
== 0)
11315 reloc
->addend
= fixp
->fx_addnumber
;
11318 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11319 /* A gruesome hack which is a result of the gruesome gas reloc
11321 reloc
->addend
= reloc
->address
;
11323 reloc
->addend
= -reloc
->address
;
11326 /* If this is a variant frag, we may need to adjust the existing
11327 reloc and generate a new one. */
11328 if (fixp
->fx_frag
->fr_opcode
!= NULL
11329 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11330 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11331 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11332 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11333 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11334 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11335 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11339 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11341 /* If this is not the last reloc in this frag, then we have two
11342 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11343 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11344 the second one handle all of them. */
11345 if (fixp
->fx_next
!= NULL
11346 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11348 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11349 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11350 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11351 && (fixp
->fx_next
->fx_r_type
11352 == BFD_RELOC_MIPS_GOT_LO16
))
11353 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11354 && (fixp
->fx_next
->fx_r_type
11355 == BFD_RELOC_MIPS_CALL_LO16
)));
11360 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11361 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11362 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11364 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11365 reloc2
->address
= (reloc
->address
11366 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11367 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11368 reloc2
->addend
= fixp
->fx_addnumber
;
11369 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11370 assert (reloc2
->howto
!= NULL
);
11372 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11376 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11379 reloc3
->address
+= 4;
11382 if (mips_pic
== NO_PIC
)
11384 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11385 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11387 else if (mips_pic
== SVR4_PIC
)
11389 switch (fixp
->fx_r_type
)
11393 case BFD_RELOC_MIPS_GOT16
:
11395 case BFD_RELOC_MIPS_CALL16
:
11396 case BFD_RELOC_MIPS_GOT_LO16
:
11397 case BFD_RELOC_MIPS_CALL_LO16
:
11398 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11406 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11407 fixup_segment converted a non-PC relative reloc into a PC
11408 relative reloc. In such a case, we need to convert the reloc
11410 code
= fixp
->fx_r_type
;
11411 if (fixp
->fx_pcrel
)
11416 code
= BFD_RELOC_8_PCREL
;
11419 code
= BFD_RELOC_16_PCREL
;
11422 code
= BFD_RELOC_32_PCREL
;
11425 code
= BFD_RELOC_64_PCREL
;
11427 case BFD_RELOC_8_PCREL
:
11428 case BFD_RELOC_16_PCREL
:
11429 case BFD_RELOC_32_PCREL
:
11430 case BFD_RELOC_64_PCREL
:
11431 case BFD_RELOC_16_PCREL_S2
:
11432 case BFD_RELOC_PCREL_HI16_S
:
11433 case BFD_RELOC_PCREL_LO16
:
11436 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11437 "Cannot make %s relocation PC relative",
11438 bfd_get_reloc_code_name (code
));
11442 /* To support a PC relative reloc when generating embedded PIC code
11443 for ECOFF, we use a Cygnus extension. We check for that here to
11444 make sure that we don't let such a reloc escape normally. */
11445 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11446 && code
== BFD_RELOC_16_PCREL_S2
11447 && mips_pic
!= EMBEDDED_PIC
)
11448 reloc
->howto
= NULL
;
11450 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11452 if (reloc
->howto
== NULL
)
11454 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11455 "Can not represent %s relocation in this object file format",
11456 bfd_get_reloc_code_name (code
));
11463 /* Relax a machine dependent frag. This returns the amount by which
11464 the current size of the frag should change. */
11467 mips_relax_frag (fragp
, stretch
)
11471 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11474 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11476 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11478 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11483 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11485 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11492 /* Convert a machine dependent frag. */
11495 md_convert_frag (abfd
, asec
, fragp
)
11503 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11506 register const struct mips16_immed_operand
*op
;
11507 boolean small
, ext
;
11510 unsigned long insn
;
11511 boolean use_extend
;
11512 unsigned short extend
;
11514 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11515 op
= mips16_immed_operands
;
11516 while (op
->type
!= type
)
11519 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11530 resolve_symbol_value (fragp
->fr_symbol
, 1);
11531 val
= S_GET_VALUE (fragp
->fr_symbol
);
11536 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11538 /* The rules for the base address of a PC relative reloc are
11539 complicated; see mips16_extended_frag. */
11540 if (type
== 'p' || type
== 'q')
11545 /* Ignore the low bit in the target, since it will be
11546 set for a text label. */
11547 if ((val
& 1) != 0)
11550 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11552 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11555 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11558 /* Make sure the section winds up with the alignment we have
11561 record_alignment (asec
, op
->shift
);
11565 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11566 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11567 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11568 "extended instruction in delay slot");
11570 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11572 if (target_big_endian
)
11573 insn
= bfd_getb16 (buf
);
11575 insn
= bfd_getl16 (buf
);
11577 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11578 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11579 small
, ext
, &insn
, &use_extend
, &extend
);
11583 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11584 fragp
->fr_fix
+= 2;
11588 md_number_to_chars (buf
, insn
, 2);
11589 fragp
->fr_fix
+= 2;
11594 if (fragp
->fr_opcode
== NULL
)
11597 old
= RELAX_OLD (fragp
->fr_subtype
);
11598 new = RELAX_NEW (fragp
->fr_subtype
);
11599 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11602 memcpy (fixptr
- old
, fixptr
, new);
11604 fragp
->fr_fix
+= new - old
;
11610 /* This function is called after the relocs have been generated.
11611 We've been storing mips16 text labels as odd. Here we convert them
11612 back to even for the convenience of the debugger. */
11615 mips_frob_file_after_relocs ()
11618 unsigned int count
, i
;
11620 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11623 syms
= bfd_get_outsymbols (stdoutput
);
11624 count
= bfd_get_symcount (stdoutput
);
11625 for (i
= 0; i
< count
; i
++, syms
++)
11627 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11628 && ((*syms
)->value
& 1) != 0)
11630 (*syms
)->value
&= ~1;
11631 /* If the symbol has an odd size, it was probably computed
11632 incorrectly, so adjust that as well. */
11633 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11634 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11641 /* This function is called whenever a label is defined. It is used
11642 when handling branch delays; if a branch has a label, we assume we
11643 can not move it. */
11646 mips_define_label (sym
)
11649 struct insn_label_list
*l
;
11651 if (free_insn_labels
== NULL
)
11652 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11655 l
= free_insn_labels
;
11656 free_insn_labels
= l
->next
;
11660 l
->next
= insn_labels
;
11664 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11666 /* Some special processing for a MIPS ELF file. */
11669 mips_elf_final_processing ()
11671 /* Write out the register information. */
11676 s
.ri_gprmask
= mips_gprmask
;
11677 s
.ri_cprmask
[0] = mips_cprmask
[0];
11678 s
.ri_cprmask
[1] = mips_cprmask
[1];
11679 s
.ri_cprmask
[2] = mips_cprmask
[2];
11680 s
.ri_cprmask
[3] = mips_cprmask
[3];
11681 /* The gp_value field is set by the MIPS ELF backend. */
11683 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11684 ((Elf32_External_RegInfo
*)
11685 mips_regmask_frag
));
11689 Elf64_Internal_RegInfo s
;
11691 s
.ri_gprmask
= mips_gprmask
;
11693 s
.ri_cprmask
[0] = mips_cprmask
[0];
11694 s
.ri_cprmask
[1] = mips_cprmask
[1];
11695 s
.ri_cprmask
[2] = mips_cprmask
[2];
11696 s
.ri_cprmask
[3] = mips_cprmask
[3];
11697 /* The gp_value field is set by the MIPS ELF backend. */
11699 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11700 ((Elf64_External_RegInfo
*)
11701 mips_regmask_frag
));
11704 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11705 sort of BFD interface for this. */
11706 if (mips_any_noreorder
)
11707 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11708 if (mips_pic
!= NO_PIC
)
11709 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11712 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11714 /* These functions should really be defined by the object file format,
11715 since they are related to debugging information. However, this
11716 code has to work for the a.out format, which does not define them,
11717 so we provide simple versions here. These don't actually generate
11718 any debugging information, but they do simple checking and someday
11719 somebody may make them useful. */
11723 struct loc
*loc_next
;
11724 unsigned long loc_fileno
;
11725 unsigned long loc_lineno
;
11726 unsigned long loc_offset
;
11727 unsigned short loc_delta
;
11728 unsigned short loc_count
;
11735 typedef struct proc
11737 struct proc
*proc_next
;
11738 struct symbol
*proc_isym
;
11739 struct symbol
*proc_end
;
11740 unsigned long proc_reg_mask
;
11741 unsigned long proc_reg_offset
;
11742 unsigned long proc_fpreg_mask
;
11743 unsigned long proc_fpreg_offset
;
11744 unsigned long proc_frameoffset
;
11745 unsigned long proc_framereg
;
11746 unsigned long proc_pcreg
;
11748 struct file
*proc_file
;
11753 typedef struct file
11755 struct file
*file_next
;
11756 unsigned long file_fileno
;
11757 struct symbol
*file_symbol
;
11758 struct symbol
*file_end
;
11759 struct proc
*file_proc
;
11764 static struct obstack proc_frags
;
11765 static procS
*proc_lastP
;
11766 static procS
*proc_rootP
;
11767 static int numprocs
;
11772 obstack_begin (&proc_frags
, 0x2000);
11778 /* check for premature end, nesting errors, etc */
11779 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11780 as_warn ("missing `.end' at end of assembly");
11789 if (*input_line_pointer
== '-')
11791 ++input_line_pointer
;
11794 if (!isdigit (*input_line_pointer
))
11795 as_bad ("Expected simple number.");
11796 if (input_line_pointer
[0] == '0')
11798 if (input_line_pointer
[1] == 'x')
11800 input_line_pointer
+= 2;
11801 while (isxdigit (*input_line_pointer
))
11804 val
|= hex_value (*input_line_pointer
++);
11806 return negative
? -val
: val
;
11810 ++input_line_pointer
;
11811 while (isdigit (*input_line_pointer
))
11814 val
|= *input_line_pointer
++ - '0';
11816 return negative
? -val
: val
;
11819 if (!isdigit (*input_line_pointer
))
11821 printf (" *input_line_pointer == '%c' 0x%02x\n",
11822 *input_line_pointer
, *input_line_pointer
);
11823 as_warn ("Invalid number");
11826 while (isdigit (*input_line_pointer
))
11829 val
+= *input_line_pointer
++ - '0';
11831 return negative
? -val
: val
;
11834 /* The .file directive; just like the usual .file directive, but there
11835 is an initial number which is the ECOFF file index. */
11843 line
= get_number ();
11848 /* The .end directive. */
11856 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11859 demand_empty_rest_of_line ();
11863 if (now_seg
!= text_section
)
11864 as_warn (".end not in text section");
11867 as_warn (".end and no .ent seen yet.");
11873 assert (S_GET_NAME (p
));
11874 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
11875 as_warn (".end symbol does not match .ent symbol.");
11878 proc_lastP
->proc_end
= (symbolS
*) 1;
11881 /* The .aent and .ent directives. */
11891 symbolP
= get_symbol ();
11892 if (*input_line_pointer
== ',')
11893 input_line_pointer
++;
11894 SKIP_WHITESPACE ();
11895 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11896 number
= get_number ();
11897 if (now_seg
!= text_section
)
11898 as_warn (".ent or .aent not in text section.");
11900 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11901 as_warn ("missing `.end'");
11905 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11906 procP
->proc_isym
= symbolP
;
11907 procP
->proc_reg_mask
= 0;
11908 procP
->proc_reg_offset
= 0;
11909 procP
->proc_fpreg_mask
= 0;
11910 procP
->proc_fpreg_offset
= 0;
11911 procP
->proc_frameoffset
= 0;
11912 procP
->proc_framereg
= 0;
11913 procP
->proc_pcreg
= 0;
11914 procP
->proc_end
= NULL
;
11915 procP
->proc_next
= NULL
;
11917 proc_lastP
->proc_next
= procP
;
11919 proc_rootP
= procP
;
11920 proc_lastP
= procP
;
11923 demand_empty_rest_of_line ();
11926 /* The .frame directive. */
11939 frame_reg
= tc_get_register (1);
11940 if (*input_line_pointer
== ',')
11941 input_line_pointer
++;
11942 frame_off
= get_absolute_expression ();
11943 if (*input_line_pointer
== ',')
11944 input_line_pointer
++;
11945 pcreg
= tc_get_register (0);
11947 /* bob third eye */
11948 assert (proc_rootP
);
11949 proc_rootP
->proc_framereg
= frame_reg
;
11950 proc_rootP
->proc_frameoffset
= frame_off
;
11951 proc_rootP
->proc_pcreg
= pcreg
;
11952 /* bob macho .frame */
11954 /* We don't have to write out a frame stab for unoptimized code. */
11955 if (!(frame_reg
== FP
&& frame_off
== 0))
11958 as_warn ("No .ent for .frame to use.");
11959 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11960 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11961 S_SET_TYPE (symP
, N_RMASK
);
11962 S_SET_OTHER (symP
, 0);
11963 S_SET_DESC (symP
, 0);
11964 symP
->sy_forward
= proc_lastP
->proc_isym
;
11965 /* bob perhaps I should have used pseudo set */
11967 demand_empty_rest_of_line ();
11971 /* The .fmask and .mask directives. */
11978 char str
[100], *strP
;
11984 mask
= get_number ();
11985 if (*input_line_pointer
== ',')
11986 input_line_pointer
++;
11987 off
= get_absolute_expression ();
11989 /* bob only for coff */
11990 assert (proc_rootP
);
11991 if (reg_type
== 'F')
11993 proc_rootP
->proc_fpreg_mask
= mask
;
11994 proc_rootP
->proc_fpreg_offset
= off
;
11998 proc_rootP
->proc_reg_mask
= mask
;
11999 proc_rootP
->proc_reg_offset
= off
;
12002 /* bob macho .mask + .fmask */
12004 /* We don't have to write out a mask stab if no saved regs. */
12008 as_warn ("No .ent for .mask to use.");
12010 for (i
= 0; i
< 32; i
++)
12014 sprintf (strP
, "%c%d,", reg_type
, i
);
12015 strP
+= strlen (strP
);
12019 sprintf (strP
, ";%d,", off
);
12020 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
12021 S_SET_TYPE (symP
, N_RMASK
);
12022 S_SET_OTHER (symP
, 0);
12023 S_SET_DESC (symP
, 0);
12024 symP
->sy_forward
= proc_lastP
->proc_isym
;
12025 /* bob perhaps I should have used pseudo set */
12030 /* The .loc directive. */
12041 assert (now_seg
== text_section
);
12043 lineno
= get_number ();
12044 addroff
= frag_now_fix ();
12046 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12047 S_SET_TYPE (symbolP
, N_SLINE
);
12048 S_SET_OTHER (symbolP
, 0);
12049 S_SET_DESC (symbolP
, lineno
);
12050 symbolP
->sy_segment
= now_seg
;