1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* This is the set of options which may be modified by the .set
140 pseudo-op. We use a struct so that .set push and .set pop are more
143 struct mips_set_options
145 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
146 if it has not been initialized. Changed by `.set mipsN', and the
147 -mipsN command line option, and the default CPU. */
149 /* Enabled Application Specific Extensions (ASEs). These are set to -1
150 if they have not been initialized. Changed by `.set <asename>', by
151 command line options, and based on the default architecture. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros
;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
180 /* Restrict general purpose registers and floating point registers
181 to 32 bit. This is initially determined when -mgp32 or -mfp32
182 is passed but can changed if the assembler code uses .set mipsN. */
185 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
186 command line option, and the default CPU. */
190 /* True if -mgp32 was passed. */
191 static int file_mips_gp32
= -1;
193 /* True if -mfp32 was passed. */
194 static int file_mips_fp32
= -1;
196 /* This is the struct we use to hold the current set of options. Note
197 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
198 -1 to indicate that they have not been initialized. */
200 static struct mips_set_options mips_opts
=
202 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
205 /* These variables are filled in with the masks of registers used.
206 The object format code reads them and puts them in the appropriate
208 unsigned long mips_gprmask
;
209 unsigned long mips_cprmask
[4];
211 /* MIPS ISA we are using for this output file. */
212 static int file_mips_isa
= ISA_UNKNOWN
;
214 /* True if -mips16 was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mips16
;
218 /* True if -mips3d was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips3d
;
222 /* True if -mdmx was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mdmx
;
226 /* The argument of the -march= flag. The architecture we are assembling. */
227 static int file_mips_arch
= CPU_UNKNOWN
;
228 static const char *mips_arch_string
;
230 /* The argument of the -mtune= flag. The architecture for which we
232 static int mips_tune
= CPU_UNKNOWN
;
233 static const char *mips_tune_string
;
235 /* True when generating 32-bit code for a 64-bit processor. */
236 static int mips_32bitmode
= 0;
238 /* True if the given ABI requires 32-bit registers. */
239 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
241 /* Likewise 64-bit registers. */
242 #define ABI_NEEDS_64BIT_REGS(ABI) \
244 || (ABI) == N64_ABI \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
253 || (ISA) == ISA_MIPS64R2 \
256 /* Return true if ISA supports 64-bit right rotate (dror et al.)
258 #define ISA_HAS_DROR(ISA) ( \
259 (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 32-bit right rotate (ror et al.)
264 #define ISA_HAS_ROR(ISA) ( \
265 (ISA) == ISA_MIPS32R2 \
266 || (ISA) == ISA_MIPS64R2 \
269 #define HAVE_32BIT_GPRS \
270 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
272 #define HAVE_32BIT_FPRS \
273 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
275 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
276 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
278 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
280 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
282 /* We can only have 64bit addresses if the object file format supports it. */
283 #define HAVE_32BIT_ADDRESSES \
285 || (bfd_arch_bits_per_address (stdoutput) == 32 \
286 || ! HAVE_64BIT_OBJECTS)) \
288 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
290 /* Addresses are loaded in different ways, depending on the address size
291 in use. The n32 ABI Documentation also mandates the use of additions
292 with overflow checking, but existing implementations don't follow it. */
293 #define ADDRESS_ADD_INSN \
294 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
296 #define ADDRESS_ADDI_INSN \
297 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
299 #define ADDRESS_LOAD_INSN \
300 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
302 #define ADDRESS_STORE_INSN \
303 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
305 /* Return true if the given CPU supports the MIPS16 ASE. */
306 #define CPU_HAS_MIPS16(cpu) \
307 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
308 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
310 /* Return true if the given CPU supports the MIPS3D ASE. */
311 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
314 /* Return true if the given CPU supports the MDMX ASE. */
315 #define CPU_HAS_MDMX(cpu) (FALSE \
318 /* True if CPU has a dror instruction. */
319 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
321 /* True if CPU has a ror instruction. */
322 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
324 /* True if mflo and mfhi can be immediately followed by instructions
325 which write to the HI and LO registers.
327 According to MIPS specifications, MIPS ISAs I, II, and III need
328 (at least) two instructions between the reads of HI/LO and
329 instructions which write them, and later ISAs do not. Contradicting
330 the MIPS specifications, some MIPS IV processor user manuals (e.g.
331 the UM for the NEC Vr5000) document needing the instructions between
332 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
333 MIPS64 and later ISAs to have the interlocks, plus any specific
334 earlier-ISA CPUs for which CPU documentation declares that the
335 instructions are really interlocked. */
336 #define hilo_interlocks \
337 (mips_opts.isa == ISA_MIPS32 \
338 || mips_opts.isa == ISA_MIPS32R2 \
339 || mips_opts.isa == ISA_MIPS64 \
340 || mips_opts.isa == ISA_MIPS64R2 \
341 || mips_opts.arch == CPU_R4010 \
342 || mips_opts.arch == CPU_R10000 \
343 || mips_opts.arch == CPU_R12000 \
344 || mips_opts.arch == CPU_RM7000 \
345 || mips_opts.arch == CPU_VR5500 \
348 /* Whether the processor uses hardware interlocks to protect reads
349 from the GPRs after they are loaded from memory, and thus does not
350 require nops to be inserted. This applies to instructions marked
351 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
353 #define gpr_interlocks \
354 (mips_opts.isa != ISA_MIPS1 \
355 || mips_opts.arch == CPU_R3900)
357 /* Whether the processor uses hardware interlocks to avoid delays
358 required by coprocessor instructions, and thus does not require
359 nops to be inserted. This applies to instructions marked
360 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
361 between instructions marked INSN_WRITE_COND_CODE and ones marked
362 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
363 levels I, II, and III. */
364 /* Itbl support may require additional care here. */
365 #define cop_interlocks \
366 ((mips_opts.isa != ISA_MIPS1 \
367 && mips_opts.isa != ISA_MIPS2 \
368 && mips_opts.isa != ISA_MIPS3) \
369 || mips_opts.arch == CPU_R4300 \
372 /* Whether the processor uses hardware interlocks to protect reads
373 from coprocessor registers after they are loaded from memory, and
374 thus does not require nops to be inserted. This applies to
375 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
376 requires at MIPS ISA level I. */
377 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
379 /* Is this a mfhi or mflo instruction? */
380 #define MF_HILO_INSN(PINFO) \
381 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
383 /* MIPS PIC level. */
385 enum mips_pic_level mips_pic
;
387 /* 1 if we should generate 32 bit offsets from the $gp register in
388 SVR4_PIC mode. Currently has no meaning in other modes. */
389 static int mips_big_got
= 0;
391 /* 1 if trap instructions should used for overflow rather than break
393 static int mips_trap
= 0;
395 /* 1 if double width floating point constants should not be constructed
396 by assembling two single width halves into two single width floating
397 point registers which just happen to alias the double width destination
398 register. On some architectures this aliasing can be disabled by a bit
399 in the status register, and the setting of this bit cannot be determined
400 automatically at assemble time. */
401 static int mips_disable_float_construction
;
403 /* Non-zero if any .set noreorder directives were used. */
405 static int mips_any_noreorder
;
407 /* Non-zero if nops should be inserted when the register referenced in
408 an mfhi/mflo instruction is read in the next two instructions. */
409 static int mips_7000_hilo_fix
;
411 /* The size of the small data section. */
412 static unsigned int g_switch_value
= 8;
413 /* Whether the -G option was used. */
414 static int g_switch_seen
= 0;
419 /* If we can determine in advance that GP optimization won't be
420 possible, we can skip the relaxation stuff that tries to produce
421 GP-relative references. This makes delay slot optimization work
424 This function can only provide a guess, but it seems to work for
425 gcc output. It needs to guess right for gcc, otherwise gcc
426 will put what it thinks is a GP-relative instruction in a branch
429 I don't know if a fix is needed for the SVR4_PIC mode. I've only
430 fixed it for the non-PIC mode. KR 95/04/07 */
431 static int nopic_need_relax (symbolS
*, int);
433 /* handle of the OPCODE hash table */
434 static struct hash_control
*op_hash
= NULL
;
436 /* The opcode hash table we use for the mips16. */
437 static struct hash_control
*mips16_op_hash
= NULL
;
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful */
441 const char comment_chars
[] = "#";
443 /* This array holds the chars that only start a comment at the beginning of
444 a line. If the line seems to have the form '# 123 filename'
445 .line and .file directives will appear in the pre-processed output */
446 /* Note that input_file.c hand checks for '#' at the beginning of the
447 first line of the input file. This is because the compiler outputs
448 #NO_APP at the beginning of its output. */
449 /* Also note that C style comments are always supported. */
450 const char line_comment_chars
[] = "#";
452 /* This array holds machine specific line separator characters. */
453 const char line_separator_chars
[] = ";";
455 /* Chars that can be used to separate mant from exp in floating point nums */
456 const char EXP_CHARS
[] = "eE";
458 /* Chars that mean this number is a floating point constant */
461 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
463 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
464 changed in read.c . Ideally it shouldn't have to know about it at all,
465 but nothing is ideal around here.
468 static char *insn_error
;
470 static int auto_align
= 1;
472 /* When outputting SVR4 PIC code, the assembler needs to know the
473 offset in the stack frame from which to restore the $gp register.
474 This is set by the .cprestore pseudo-op, and saved in this
476 static offsetT mips_cprestore_offset
= -1;
478 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
479 more optimizations, it can use a register value instead of a memory-saved
480 offset and even an other register than $gp as global pointer. */
481 static offsetT mips_cpreturn_offset
= -1;
482 static int mips_cpreturn_register
= -1;
483 static int mips_gp_register
= GP
;
484 static int mips_gprel_offset
= 0;
486 /* Whether mips_cprestore_offset has been set in the current function
487 (or whether it has already been warned about, if not). */
488 static int mips_cprestore_valid
= 0;
490 /* This is the register which holds the stack frame, as set by the
491 .frame pseudo-op. This is needed to implement .cprestore. */
492 static int mips_frame_reg
= SP
;
494 /* Whether mips_frame_reg has been set in the current function
495 (or whether it has already been warned about, if not). */
496 static int mips_frame_reg_valid
= 0;
498 /* To output NOP instructions correctly, we need to keep information
499 about the previous two instructions. */
501 /* Whether we are optimizing. The default value of 2 means to remove
502 unneeded NOPs and swap branch instructions when possible. A value
503 of 1 means to not swap branches. A value of 0 means to always
505 static int mips_optimize
= 2;
507 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
508 equivalent to seeing no -g option at all. */
509 static int mips_debug
= 0;
511 /* The previous instruction. */
512 static struct mips_cl_insn prev_insn
;
514 /* The instruction before prev_insn. */
515 static struct mips_cl_insn prev_prev_insn
;
517 /* If we don't want information for prev_insn or prev_prev_insn, we
518 point the insn_mo field at this dummy integer. */
519 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
521 /* Non-zero if prev_insn is valid. */
522 static int prev_insn_valid
;
524 /* The frag for the previous instruction. */
525 static struct frag
*prev_insn_frag
;
527 /* The offset into prev_insn_frag for the previous instruction. */
528 static long prev_insn_where
;
530 /* The reloc type for the previous instruction, if any. */
531 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
533 /* The reloc for the previous instruction, if any. */
534 static fixS
*prev_insn_fixp
[3];
536 /* Non-zero if the previous instruction was in a delay slot. */
537 static int prev_insn_is_delay_slot
;
539 /* Non-zero if the previous instruction was in a .set noreorder. */
540 static int prev_insn_unreordered
;
542 /* Non-zero if the previous instruction uses an extend opcode (if
544 static int prev_insn_extended
;
546 /* Non-zero if the previous previous instruction was in a .set
548 static int prev_prev_insn_unreordered
;
550 /* If this is set, it points to a frag holding nop instructions which
551 were inserted before the start of a noreorder section. If those
552 nops turn out to be unnecessary, the size of the frag can be
554 static fragS
*prev_nop_frag
;
556 /* The number of nop instructions we created in prev_nop_frag. */
557 static int prev_nop_frag_holds
;
559 /* The number of nop instructions that we know we need in
561 static int prev_nop_frag_required
;
563 /* The number of instructions we've seen since prev_nop_frag. */
564 static int prev_nop_frag_since
;
566 /* For ECOFF and ELF, relocations against symbols are done in two
567 parts, with a HI relocation and a LO relocation. Each relocation
568 has only 16 bits of space to store an addend. This means that in
569 order for the linker to handle carries correctly, it must be able
570 to locate both the HI and the LO relocation. This means that the
571 relocations must appear in order in the relocation table.
573 In order to implement this, we keep track of each unmatched HI
574 relocation. We then sort them so that they immediately precede the
575 corresponding LO relocation. */
580 struct mips_hi_fixup
*next
;
583 /* The section this fixup is in. */
587 /* The list of unmatched HI relocs. */
589 static struct mips_hi_fixup
*mips_hi_fixup_list
;
591 /* The frag containing the last explicit relocation operator.
592 Null if explicit relocations have not been used. */
594 static fragS
*prev_reloc_op_frag
;
596 /* Map normal MIPS register numbers to mips16 register numbers. */
598 #define X ILLEGAL_REG
599 static const int mips32_to_16_reg_map
[] =
601 X
, X
, 2, 3, 4, 5, 6, 7,
602 X
, X
, X
, X
, X
, X
, X
, X
,
603 0, 1, X
, X
, X
, X
, X
, X
,
604 X
, X
, X
, X
, X
, X
, X
, X
608 /* Map mips16 register numbers to normal MIPS register numbers. */
610 static const unsigned int mips16_to_32_reg_map
[] =
612 16, 17, 2, 3, 4, 5, 6, 7
615 static int mips_fix_vr4120
;
617 /* We don't relax branches by default, since this causes us to expand
618 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
619 fail to compute the offset before expanding the macro to the most
620 efficient expansion. */
622 static int mips_relax_branch
;
624 /* The expansion of many macros depends on the type of symbol that
625 they refer to. For example, when generating position-dependent code,
626 a macro that refers to a symbol may have two different expansions,
627 one which uses GP-relative addresses and one which uses absolute
628 addresses. When generating SVR4-style PIC, a macro may have
629 different expansions for local and global symbols.
631 We handle these situations by generating both sequences and putting
632 them in variant frags. In position-dependent code, the first sequence
633 will be the GP-relative one and the second sequence will be the
634 absolute one. In SVR4 PIC, the first sequence will be for global
635 symbols and the second will be for local symbols.
637 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
638 SECOND are the lengths of the two sequences in bytes. These fields
639 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
640 the subtype has the following flags:
643 Set if it has been decided that we should use the second
644 sequence instead of the first.
647 Set in the first variant frag if the macro's second implementation
648 is longer than its first. This refers to the macro as a whole,
649 not an individual relaxation.
652 Set in the first variant frag if the macro appeared in a .set nomacro
653 block and if one alternative requires a warning but the other does not.
656 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
659 The frag's "opcode" points to the first fixup for relaxable code.
661 Relaxable macros are generated using a sequence such as:
663 relax_start (SYMBOL);
664 ... generate first expansion ...
666 ... generate second expansion ...
669 The code and fixups for the unwanted alternative are discarded
670 by md_convert_frag. */
671 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
673 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
674 #define RELAX_SECOND(X) ((X) & 0xff)
675 #define RELAX_USE_SECOND 0x10000
676 #define RELAX_SECOND_LONGER 0x20000
677 #define RELAX_NOMACRO 0x40000
678 #define RELAX_DELAY_SLOT 0x80000
680 /* Branch without likely bit. If label is out of range, we turn:
682 beq reg1, reg2, label
692 with the following opcode replacements:
699 bltzal <-> bgezal (with jal label instead of j label)
701 Even though keeping the delay slot instruction in the delay slot of
702 the branch would be more efficient, it would be very tricky to do
703 correctly, because we'd have to introduce a variable frag *after*
704 the delay slot instruction, and expand that instead. Let's do it
705 the easy way for now, even if the branch-not-taken case now costs
706 one additional instruction. Out-of-range branches are not supposed
707 to be common, anyway.
709 Branch likely. If label is out of range, we turn:
711 beql reg1, reg2, label
712 delay slot (annulled if branch not taken)
721 delay slot (executed only if branch taken)
724 It would be possible to generate a shorter sequence by losing the
725 likely bit, generating something like:
730 delay slot (executed only if branch taken)
742 bltzall -> bgezal (with jal label instead of j label)
743 bgezall -> bltzal (ditto)
746 but it's not clear that it would actually improve performance. */
747 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
750 | ((toofar) ? 1 : 0) \
752 | ((likely) ? 4 : 0) \
753 | ((uncond) ? 8 : 0)))
754 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
755 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
756 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
757 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
758 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
760 /* For mips16 code, we use an entirely different form of relaxation.
761 mips16 supports two versions of most instructions which take
762 immediate values: a small one which takes some small value, and a
763 larger one which takes a 16 bit value. Since branches also follow
764 this pattern, relaxing these values is required.
766 We can assemble both mips16 and normal MIPS code in a single
767 object. Therefore, we need to support this type of relaxation at
768 the same time that we support the relaxation described above. We
769 use the high bit of the subtype field to distinguish these cases.
771 The information we store for this type of relaxation is the
772 argument code found in the opcode file for this relocation, whether
773 the user explicitly requested a small or extended form, and whether
774 the relocation is in a jump or jal delay slot. That tells us the
775 size of the value, and how it should be stored. We also store
776 whether the fragment is considered to be extended or not. We also
777 store whether this is known to be a branch to a different section,
778 whether we have tried to relax this frag yet, and whether we have
779 ever extended a PC relative fragment because of a shift count. */
780 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
783 | ((small) ? 0x100 : 0) \
784 | ((ext) ? 0x200 : 0) \
785 | ((dslot) ? 0x400 : 0) \
786 | ((jal_dslot) ? 0x800 : 0))
787 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
788 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
789 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
790 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
791 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
792 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
793 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
794 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
795 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
796 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
797 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
798 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
800 /* Is the given value a sign-extended 32-bit value? */
801 #define IS_SEXT_32BIT_NUM(x) \
802 (((x) &~ (offsetT) 0x7fffffff) == 0 \
803 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
805 /* Is the given value a sign-extended 16-bit value? */
806 #define IS_SEXT_16BIT_NUM(x) \
807 (((x) &~ (offsetT) 0x7fff) == 0 \
808 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
811 /* Global variables used when generating relaxable macros. See the
812 comment above RELAX_ENCODE for more details about how relaxation
815 /* 0 if we're not emitting a relaxable macro.
816 1 if we're emitting the first of the two relaxation alternatives.
817 2 if we're emitting the second alternative. */
820 /* The first relaxable fixup in the current frag. (In other words,
821 the first fixup that refers to relaxable code.) */
824 /* sizes[0] says how many bytes of the first alternative are stored in
825 the current frag. Likewise sizes[1] for the second alternative. */
826 unsigned int sizes
[2];
828 /* The symbol on which the choice of sequence depends. */
832 /* Global variables used to decide whether a macro needs a warning. */
834 /* True if the macro is in a branch delay slot. */
835 bfd_boolean delay_slot_p
;
837 /* For relaxable macros, sizes[0] is the length of the first alternative
838 in bytes and sizes[1] is the length of the second alternative.
839 For non-relaxable macros, both elements give the length of the
841 unsigned int sizes
[2];
843 /* The first variant frag for this macro. */
845 } mips_macro_warning
;
847 /* Prototypes for static functions. */
849 #define internalError() \
850 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
852 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
854 static void append_insn
855 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
856 static void mips_no_prev_insn (int);
857 static void mips16_macro_build
858 (expressionS
*, const char *, const char *, va_list);
859 static void load_register (int, expressionS
*, int);
860 static void macro_start (void);
861 static void macro_end (void);
862 static void macro (struct mips_cl_insn
* ip
);
863 static void mips16_macro (struct mips_cl_insn
* ip
);
864 #ifdef LOSING_COMPILER
865 static void macro2 (struct mips_cl_insn
* ip
);
867 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
868 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
869 static void mips16_immed
870 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
871 unsigned long *, bfd_boolean
*, unsigned short *);
872 static size_t my_getSmallExpression
873 (expressionS
*, bfd_reloc_code_real_type
*, char *);
874 static void my_getExpression (expressionS
*, char *);
875 static void s_align (int);
876 static void s_change_sec (int);
877 static void s_change_section (int);
878 static void s_cons (int);
879 static void s_float_cons (int);
880 static void s_mips_globl (int);
881 static void s_option (int);
882 static void s_mipsset (int);
883 static void s_abicalls (int);
884 static void s_cpload (int);
885 static void s_cpsetup (int);
886 static void s_cplocal (int);
887 static void s_cprestore (int);
888 static void s_cpreturn (int);
889 static void s_gpvalue (int);
890 static void s_gpword (int);
891 static void s_gpdword (int);
892 static void s_cpadd (int);
893 static void s_insn (int);
894 static void md_obj_begin (void);
895 static void md_obj_end (void);
896 static void s_mips_ent (int);
897 static void s_mips_end (int);
898 static void s_mips_frame (int);
899 static void s_mips_mask (int reg_type
);
900 static void s_mips_stab (int);
901 static void s_mips_weakext (int);
902 static void s_mips_file (int);
903 static void s_mips_loc (int);
904 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
905 static int relaxed_branch_length (fragS
*, asection
*, int);
906 static int validate_mips_insn (const struct mips_opcode
*);
908 /* Table and functions used to map between CPU/ISA names, and
909 ISA levels, and CPU numbers. */
913 const char *name
; /* CPU or ISA name. */
914 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
915 int isa
; /* ISA level. */
916 int cpu
; /* CPU number (default CPU if ISA). */
919 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
920 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
921 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
925 The following pseudo-ops from the Kane and Heinrich MIPS book
926 should be defined here, but are currently unsupported: .alias,
927 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
929 The following pseudo-ops from the Kane and Heinrich MIPS book are
930 specific to the type of debugging information being generated, and
931 should be defined by the object format: .aent, .begin, .bend,
932 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
935 The following pseudo-ops from the Kane and Heinrich MIPS book are
936 not MIPS CPU specific, but are also not specific to the object file
937 format. This file is probably the best place to define them, but
938 they are not currently supported: .asm0, .endr, .lab, .repeat,
941 static const pseudo_typeS mips_pseudo_table
[] =
943 /* MIPS specific pseudo-ops. */
944 {"option", s_option
, 0},
945 {"set", s_mipsset
, 0},
946 {"rdata", s_change_sec
, 'r'},
947 {"sdata", s_change_sec
, 's'},
948 {"livereg", s_ignore
, 0},
949 {"abicalls", s_abicalls
, 0},
950 {"cpload", s_cpload
, 0},
951 {"cpsetup", s_cpsetup
, 0},
952 {"cplocal", s_cplocal
, 0},
953 {"cprestore", s_cprestore
, 0},
954 {"cpreturn", s_cpreturn
, 0},
955 {"gpvalue", s_gpvalue
, 0},
956 {"gpword", s_gpword
, 0},
957 {"gpdword", s_gpdword
, 0},
958 {"cpadd", s_cpadd
, 0},
961 /* Relatively generic pseudo-ops that happen to be used on MIPS
963 {"asciiz", stringer
, 1},
964 {"bss", s_change_sec
, 'b'},
967 {"dword", s_cons
, 3},
968 {"weakext", s_mips_weakext
, 0},
970 /* These pseudo-ops are defined in read.c, but must be overridden
971 here for one reason or another. */
972 {"align", s_align
, 0},
974 {"data", s_change_sec
, 'd'},
975 {"double", s_float_cons
, 'd'},
976 {"float", s_float_cons
, 'f'},
977 {"globl", s_mips_globl
, 0},
978 {"global", s_mips_globl
, 0},
979 {"hword", s_cons
, 1},
984 {"section", s_change_section
, 0},
985 {"short", s_cons
, 1},
986 {"single", s_float_cons
, 'f'},
987 {"stabn", s_mips_stab
, 'n'},
988 {"text", s_change_sec
, 't'},
991 { "extern", ecoff_directive_extern
, 0},
996 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
998 /* These pseudo-ops should be defined by the object file format.
999 However, a.out doesn't support them, so we have versions here. */
1000 {"aent", s_mips_ent
, 1},
1001 {"bgnb", s_ignore
, 0},
1002 {"end", s_mips_end
, 0},
1003 {"endb", s_ignore
, 0},
1004 {"ent", s_mips_ent
, 0},
1005 {"file", s_mips_file
, 0},
1006 {"fmask", s_mips_mask
, 'F'},
1007 {"frame", s_mips_frame
, 0},
1008 {"loc", s_mips_loc
, 0},
1009 {"mask", s_mips_mask
, 'R'},
1010 {"verstamp", s_ignore
, 0},
1014 extern void pop_insert (const pseudo_typeS
*);
1017 mips_pop_insert (void)
1019 pop_insert (mips_pseudo_table
);
1020 if (! ECOFF_DEBUGGING
)
1021 pop_insert (mips_nonecoff_pseudo_table
);
1024 /* Symbols labelling the current insn. */
1026 struct insn_label_list
1028 struct insn_label_list
*next
;
1032 static struct insn_label_list
*insn_labels
;
1033 static struct insn_label_list
*free_insn_labels
;
1035 static void mips_clear_insn_labels (void);
1038 mips_clear_insn_labels (void)
1040 register struct insn_label_list
**pl
;
1042 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1048 static char *expr_end
;
1050 /* Expressions which appear in instructions. These are set by
1053 static expressionS imm_expr
;
1054 static expressionS imm2_expr
;
1055 static expressionS offset_expr
;
1057 /* Relocs associated with imm_expr and offset_expr. */
1059 static bfd_reloc_code_real_type imm_reloc
[3]
1060 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1061 static bfd_reloc_code_real_type offset_reloc
[3]
1062 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1064 /* These are set by mips16_ip if an explicit extension is used. */
1066 static bfd_boolean mips16_small
, mips16_ext
;
1069 /* The pdr segment for per procedure frame/regmask info. Not used for
1072 static segT pdr_seg
;
1075 /* The default target format to use. */
1078 mips_target_format (void)
1080 switch (OUTPUT_FLAVOR
)
1082 case bfd_target_ecoff_flavour
:
1083 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1084 case bfd_target_coff_flavour
:
1086 case bfd_target_elf_flavour
:
1088 /* This is traditional mips. */
1089 return (target_big_endian
1090 ? (HAVE_64BIT_OBJECTS
1091 ? "elf64-tradbigmips"
1093 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1094 : (HAVE_64BIT_OBJECTS
1095 ? "elf64-tradlittlemips"
1097 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1099 return (target_big_endian
1100 ? (HAVE_64BIT_OBJECTS
1103 ? "elf32-nbigmips" : "elf32-bigmips"))
1104 : (HAVE_64BIT_OBJECTS
1105 ? "elf64-littlemips"
1107 ? "elf32-nlittlemips" : "elf32-littlemips")));
1115 /* This function is called once, at assembler startup time. It should
1116 set up all the tables, etc. that the MD part of the assembler will need. */
1121 register const char *retval
= NULL
;
1125 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1126 as_warn (_("Could not set architecture and machine"));
1128 op_hash
= hash_new ();
1130 for (i
= 0; i
< NUMOPCODES
;)
1132 const char *name
= mips_opcodes
[i
].name
;
1134 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1137 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1138 mips_opcodes
[i
].name
, retval
);
1139 /* Probably a memory allocation problem? Give up now. */
1140 as_fatal (_("Broken assembler. No assembly attempted."));
1144 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1146 if (!validate_mips_insn (&mips_opcodes
[i
]))
1151 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1154 mips16_op_hash
= hash_new ();
1157 while (i
< bfd_mips16_num_opcodes
)
1159 const char *name
= mips16_opcodes
[i
].name
;
1161 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1163 as_fatal (_("internal: can't hash `%s': %s"),
1164 mips16_opcodes
[i
].name
, retval
);
1167 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1168 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1169 != mips16_opcodes
[i
].match
))
1171 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1172 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1177 while (i
< bfd_mips16_num_opcodes
1178 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1182 as_fatal (_("Broken assembler. No assembly attempted."));
1184 /* We add all the general register names to the symbol table. This
1185 helps us detect invalid uses of them. */
1186 for (i
= 0; i
< 32; i
++)
1190 sprintf (buf
, "$%d", i
);
1191 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1192 &zero_address_frag
));
1194 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1195 &zero_address_frag
));
1196 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1197 &zero_address_frag
));
1198 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1199 &zero_address_frag
));
1200 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1201 &zero_address_frag
));
1202 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1203 &zero_address_frag
));
1204 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1205 &zero_address_frag
));
1206 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1207 &zero_address_frag
));
1208 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1209 &zero_address_frag
));
1210 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1211 &zero_address_frag
));
1213 /* If we don't add these register names to the symbol table, they
1214 may end up being added as regular symbols by operand(), and then
1215 make it to the object file as undefined in case they're not
1216 regarded as local symbols. They're local in o32, since `$' is a
1217 local symbol prefix, but not in n32 or n64. */
1218 for (i
= 0; i
< 8; i
++)
1222 sprintf (buf
, "$fcc%i", i
);
1223 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1224 &zero_address_frag
));
1227 mips_no_prev_insn (FALSE
);
1230 mips_cprmask
[0] = 0;
1231 mips_cprmask
[1] = 0;
1232 mips_cprmask
[2] = 0;
1233 mips_cprmask
[3] = 0;
1235 /* set the default alignment for the text section (2**2) */
1236 record_alignment (text_section
, 2);
1238 bfd_set_gp_size (stdoutput
, g_switch_value
);
1240 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1242 /* On a native system, sections must be aligned to 16 byte
1243 boundaries. When configured for an embedded ELF target, we
1245 if (strcmp (TARGET_OS
, "elf") != 0)
1247 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1248 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1249 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1252 /* Create a .reginfo section for register masks and a .mdebug
1253 section for debugging information. */
1261 subseg
= now_subseg
;
1263 /* The ABI says this section should be loaded so that the
1264 running program can access it. However, we don't load it
1265 if we are configured for an embedded target */
1266 flags
= SEC_READONLY
| SEC_DATA
;
1267 if (strcmp (TARGET_OS
, "elf") != 0)
1268 flags
|= SEC_ALLOC
| SEC_LOAD
;
1270 if (mips_abi
!= N64_ABI
)
1272 sec
= subseg_new (".reginfo", (subsegT
) 0);
1274 bfd_set_section_flags (stdoutput
, sec
, flags
);
1275 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1278 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1283 /* The 64-bit ABI uses a .MIPS.options section rather than
1284 .reginfo section. */
1285 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1286 bfd_set_section_flags (stdoutput
, sec
, flags
);
1287 bfd_set_section_alignment (stdoutput
, sec
, 3);
1290 /* Set up the option header. */
1292 Elf_Internal_Options opthdr
;
1295 opthdr
.kind
= ODK_REGINFO
;
1296 opthdr
.size
= (sizeof (Elf_External_Options
)
1297 + sizeof (Elf64_External_RegInfo
));
1300 f
= frag_more (sizeof (Elf_External_Options
));
1301 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1302 (Elf_External_Options
*) f
);
1304 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1309 if (ECOFF_DEBUGGING
)
1311 sec
= subseg_new (".mdebug", (subsegT
) 0);
1312 (void) bfd_set_section_flags (stdoutput
, sec
,
1313 SEC_HAS_CONTENTS
| SEC_READONLY
);
1314 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1317 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1319 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1320 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1321 SEC_READONLY
| SEC_RELOC
1323 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1327 subseg_set (seg
, subseg
);
1331 if (! ECOFF_DEBUGGING
)
1338 if (! ECOFF_DEBUGGING
)
1343 md_assemble (char *str
)
1345 struct mips_cl_insn insn
;
1346 bfd_reloc_code_real_type unused_reloc
[3]
1347 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1349 imm_expr
.X_op
= O_absent
;
1350 imm2_expr
.X_op
= O_absent
;
1351 offset_expr
.X_op
= O_absent
;
1352 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1353 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1354 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1355 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1356 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1357 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1359 if (mips_opts
.mips16
)
1360 mips16_ip (str
, &insn
);
1363 mips_ip (str
, &insn
);
1364 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1365 str
, insn
.insn_opcode
));
1370 as_bad ("%s `%s'", insn_error
, str
);
1374 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1377 if (mips_opts
.mips16
)
1378 mips16_macro (&insn
);
1385 if (imm_expr
.X_op
!= O_absent
)
1386 append_insn (&insn
, &imm_expr
, imm_reloc
);
1387 else if (offset_expr
.X_op
!= O_absent
)
1388 append_insn (&insn
, &offset_expr
, offset_reloc
);
1390 append_insn (&insn
, NULL
, unused_reloc
);
1394 /* Return true if the given relocation might need a matching %lo().
1395 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1396 applied to local symbols. */
1398 static inline bfd_boolean
1399 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1401 return (reloc
== BFD_RELOC_HI16_S
1402 || reloc
== BFD_RELOC_MIPS_GOT16
);
1405 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1408 static inline bfd_boolean
1409 fixup_has_matching_lo_p (fixS
*fixp
)
1411 return (fixp
->fx_next
!= NULL
1412 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1413 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1414 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1417 /* See whether instruction IP reads register REG. CLASS is the type
1421 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1422 enum mips_regclass
class)
1424 if (class == MIPS16_REG
)
1426 assert (mips_opts
.mips16
);
1427 reg
= mips16_to_32_reg_map
[reg
];
1428 class = MIPS_GR_REG
;
1431 /* Don't report on general register ZERO, since it never changes. */
1432 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1435 if (class == MIPS_FP_REG
)
1437 assert (! mips_opts
.mips16
);
1438 /* If we are called with either $f0 or $f1, we must check $f0.
1439 This is not optimal, because it will introduce an unnecessary
1440 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1441 need to distinguish reading both $f0 and $f1 or just one of
1442 them. Note that we don't have to check the other way,
1443 because there is no instruction that sets both $f0 and $f1
1444 and requires a delay. */
1445 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1446 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1447 == (reg
&~ (unsigned) 1)))
1449 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1450 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1451 == (reg
&~ (unsigned) 1)))
1454 else if (! mips_opts
.mips16
)
1456 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1457 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1459 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1460 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1465 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1466 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1467 & MIPS16OP_MASK_RX
)]
1470 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1471 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1472 & MIPS16OP_MASK_RY
)]
1475 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1476 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1477 & MIPS16OP_MASK_MOVE32Z
)]
1480 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1482 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1484 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1486 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1487 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1488 & MIPS16OP_MASK_REGR32
) == reg
)
1495 /* This function returns true if modifying a register requires a
1499 reg_needs_delay (unsigned int reg
)
1501 unsigned long prev_pinfo
;
1503 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1504 if (! mips_opts
.noreorder
1505 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1506 && ! gpr_interlocks
)
1507 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1508 && ! cop_interlocks
)))
1510 /* A load from a coprocessor or from memory. All load delays
1511 delay the use of general register rt for one instruction. */
1512 /* Itbl support may require additional care here. */
1513 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1514 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1521 /* Mark instruction labels in mips16 mode. This permits the linker to
1522 handle them specially, such as generating jalx instructions when
1523 needed. We also make them odd for the duration of the assembly, in
1524 order to generate the right sort of code. We will make them even
1525 in the adjust_symtab routine, while leaving them marked. This is
1526 convenient for the debugger and the disassembler. The linker knows
1527 to make them odd again. */
1530 mips16_mark_labels (void)
1532 if (mips_opts
.mips16
)
1534 struct insn_label_list
*l
;
1537 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1540 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1541 S_SET_OTHER (l
->label
, STO_MIPS16
);
1543 val
= S_GET_VALUE (l
->label
);
1545 S_SET_VALUE (l
->label
, val
+ 1);
1550 /* End the current frag. Make it a variant frag and record the
1554 relax_close_frag (void)
1556 mips_macro_warning
.first_frag
= frag_now
;
1557 frag_var (rs_machine_dependent
, 0, 0,
1558 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1559 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1561 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1562 mips_relax
.first_fixup
= 0;
1565 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1566 See the comment above RELAX_ENCODE for more details. */
1569 relax_start (symbolS
*symbol
)
1571 assert (mips_relax
.sequence
== 0);
1572 mips_relax
.sequence
= 1;
1573 mips_relax
.symbol
= symbol
;
1576 /* Start generating the second version of a relaxable sequence.
1577 See the comment above RELAX_ENCODE for more details. */
1582 assert (mips_relax
.sequence
== 1);
1583 mips_relax
.sequence
= 2;
1586 /* End the current relaxable sequence. */
1591 assert (mips_relax
.sequence
== 2);
1592 relax_close_frag ();
1593 mips_relax
.sequence
= 0;
1596 /* Output an instruction. IP is the instruction information.
1597 ADDRESS_EXPR is an operand of the instruction to be used with
1601 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1602 bfd_reloc_code_real_type
*reloc_type
)
1604 register unsigned long prev_pinfo
, pinfo
;
1608 relax_stateT prev_insn_frag_type
= 0;
1609 bfd_boolean relaxed_branch
= FALSE
;
1610 bfd_boolean force_new_frag
= FALSE
;
1612 /* Mark instruction labels in mips16 mode. */
1613 mips16_mark_labels ();
1615 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1616 pinfo
= ip
->insn_mo
->pinfo
;
1618 if (mips_relax
.sequence
!= 2
1619 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1623 /* If the previous insn required any delay slots, see if we need
1624 to insert a NOP or two. There are eight kinds of possible
1625 hazards, of which an instruction can have at most one type.
1626 (1) a load from memory delay
1627 (2) a load from a coprocessor delay
1628 (3) an unconditional branch delay
1629 (4) a conditional branch delay
1630 (5) a move to coprocessor register delay
1631 (6) a load coprocessor register from memory delay
1632 (7) a coprocessor condition code delay
1633 (8) a HI/LO special register delay
1635 There are a lot of optimizations we could do that we don't.
1636 In particular, we do not, in general, reorder instructions.
1637 If you use gcc with optimization, it will reorder
1638 instructions and generally do much more optimization then we
1639 do here; repeating all that work in the assembler would only
1640 benefit hand written assembly code, and does not seem worth
1643 /* This is how a NOP is emitted. */
1644 #define emit_nop() \
1646 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1647 : md_number_to_chars (frag_more (4), 0, 4))
1649 /* The previous insn might require a delay slot, depending upon
1650 the contents of the current insn. */
1651 if (! mips_opts
.mips16
1652 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1653 && ! gpr_interlocks
)
1654 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1655 && ! cop_interlocks
)))
1657 /* A load from a coprocessor or from memory. All load
1658 delays delay the use of general register rt for one
1660 /* Itbl support may require additional care here. */
1661 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1662 if (mips_optimize
== 0
1663 || insn_uses_reg (ip
,
1664 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1669 else if (! mips_opts
.mips16
1670 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1671 && ! cop_interlocks
)
1672 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1673 && ! cop_mem_interlocks
)))
1675 /* A generic coprocessor delay. The previous instruction
1676 modified a coprocessor general or control register. If
1677 it modified a control register, we need to avoid any
1678 coprocessor instruction (this is probably not always
1679 required, but it sometimes is). If it modified a general
1680 register, we avoid using that register.
1682 This case is not handled very well. There is no special
1683 knowledge of CP0 handling, and the coprocessors other
1684 than the floating point unit are not distinguished at
1686 /* Itbl support may require additional care here. FIXME!
1687 Need to modify this to include knowledge about
1688 user specified delays! */
1689 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1691 if (mips_optimize
== 0
1692 || insn_uses_reg (ip
,
1693 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1698 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1700 if (mips_optimize
== 0
1701 || insn_uses_reg (ip
,
1702 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1709 /* We don't know exactly what the previous instruction
1710 does. If the current instruction uses a coprocessor
1711 register, we must insert a NOP. If previous
1712 instruction may set the condition codes, and the
1713 current instruction uses them, we must insert two
1715 /* Itbl support may require additional care here. */
1716 if (mips_optimize
== 0
1717 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1718 && (pinfo
& INSN_READ_COND_CODE
)))
1720 else if (pinfo
& INSN_COP
)
1724 else if (! mips_opts
.mips16
1725 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1726 && ! cop_interlocks
)
1728 /* The previous instruction sets the coprocessor condition
1729 codes, but does not require a general coprocessor delay
1730 (this means it is a floating point comparison
1731 instruction). If this instruction uses the condition
1732 codes, we need to insert a single NOP. */
1733 /* Itbl support may require additional care here. */
1734 if (mips_optimize
== 0
1735 || (pinfo
& INSN_READ_COND_CODE
))
1739 /* If we're fixing up mfhi/mflo for the r7000 and the
1740 previous insn was an mfhi/mflo and the current insn
1741 reads the register that the mfhi/mflo wrote to, then
1744 else if (mips_7000_hilo_fix
1745 && MF_HILO_INSN (prev_pinfo
)
1746 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1753 /* If we're fixing up mfhi/mflo for the r7000 and the
1754 2nd previous insn was an mfhi/mflo and the current insn
1755 reads the register that the mfhi/mflo wrote to, then
1758 else if (mips_7000_hilo_fix
1759 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1760 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1768 else if (prev_pinfo
& INSN_READ_LO
)
1770 /* The previous instruction reads the LO register; if the
1771 current instruction writes to the LO register, we must
1772 insert two NOPS. Some newer processors have interlocks.
1773 Also the tx39's multiply instructions can be executed
1774 immediately after a read from HI/LO (without the delay),
1775 though the tx39's divide insns still do require the
1777 if (! (hilo_interlocks
1778 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1779 && (mips_optimize
== 0
1780 || (pinfo
& INSN_WRITE_LO
)))
1782 /* Most mips16 branch insns don't have a delay slot.
1783 If a read from LO is immediately followed by a branch
1784 to a write to LO we have a read followed by a write
1785 less than 2 insns away. We assume the target of
1786 a branch might be a write to LO, and insert a nop
1787 between a read and an immediately following branch. */
1788 else if (mips_opts
.mips16
1789 && (mips_optimize
== 0
1790 || (pinfo
& MIPS16_INSN_BRANCH
)))
1793 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1795 /* The previous instruction reads the HI register; if the
1796 current instruction writes to the HI register, we must
1797 insert a NOP. Some newer processors have interlocks.
1798 Also the note tx39's multiply above. */
1799 if (! (hilo_interlocks
1800 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1801 && (mips_optimize
== 0
1802 || (pinfo
& INSN_WRITE_HI
)))
1804 /* Most mips16 branch insns don't have a delay slot.
1805 If a read from HI is immediately followed by a branch
1806 to a write to HI we have a read followed by a write
1807 less than 2 insns away. We assume the target of
1808 a branch might be a write to HI, and insert a nop
1809 between a read and an immediately following branch. */
1810 else if (mips_opts
.mips16
1811 && (mips_optimize
== 0
1812 || (pinfo
& MIPS16_INSN_BRANCH
)))
1816 /* If the previous instruction was in a noreorder section, then
1817 we don't want to insert the nop after all. */
1818 /* Itbl support may require additional care here. */
1819 if (prev_insn_unreordered
)
1822 /* There are two cases which require two intervening
1823 instructions: 1) setting the condition codes using a move to
1824 coprocessor instruction which requires a general coprocessor
1825 delay and then reading the condition codes 2) reading the HI
1826 or LO register and then writing to it (except on processors
1827 which have interlocks). If we are not already emitting a NOP
1828 instruction, we must check for these cases compared to the
1829 instruction previous to the previous instruction. */
1830 if ((! mips_opts
.mips16
1831 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1832 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1833 && (pinfo
& INSN_READ_COND_CODE
)
1834 && ! cop_interlocks
)
1835 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1836 && (pinfo
& INSN_WRITE_LO
)
1837 && ! (hilo_interlocks
1838 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1839 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1840 && (pinfo
& INSN_WRITE_HI
)
1841 && ! (hilo_interlocks
1842 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1847 if (prev_prev_insn_unreordered
)
1850 if (prev_prev_nop
&& nops
== 0)
1853 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1855 /* We're out of bits in pinfo, so we must resort to string
1856 ops here. Shortcuts are selected based on opcodes being
1857 limited to the VR4120 instruction set. */
1859 const char *pn
= prev_insn
.insn_mo
->name
;
1860 const char *tn
= ip
->insn_mo
->name
;
1861 if (strncmp(pn
, "macc", 4) == 0
1862 || strncmp(pn
, "dmacc", 5) == 0)
1864 /* Errata 21 - [D]DIV[U] after [D]MACC */
1865 if (strstr (tn
, "div"))
1870 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1871 if (pn
[0] == 'd' /* dmacc */
1872 && (strncmp(tn
, "dmult", 5) == 0
1873 || strncmp(tn
, "dmacc", 5) == 0))
1878 /* Errata 24 - MT{LO,HI} after [D]MACC */
1879 if (strcmp (tn
, "mtlo") == 0
1880 || strcmp (tn
, "mthi") == 0)
1886 else if (strncmp(pn
, "dmult", 5) == 0
1887 && (strncmp(tn
, "dmult", 5) == 0
1888 || strncmp(tn
, "dmacc", 5) == 0))
1890 /* Here is the rest of errata 23. */
1893 if (nops
< min_nops
)
1897 /* If we are being given a nop instruction, don't bother with
1898 one of the nops we would otherwise output. This will only
1899 happen when a nop instruction is used with mips_optimize set
1902 && ! mips_opts
.noreorder
1903 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1906 /* Now emit the right number of NOP instructions. */
1907 if (nops
> 0 && ! mips_opts
.noreorder
)
1910 unsigned long old_frag_offset
;
1912 struct insn_label_list
*l
;
1914 old_frag
= frag_now
;
1915 old_frag_offset
= frag_now_fix ();
1917 for (i
= 0; i
< nops
; i
++)
1922 listing_prev_line ();
1923 /* We may be at the start of a variant frag. In case we
1924 are, make sure there is enough space for the frag
1925 after the frags created by listing_prev_line. The
1926 argument to frag_grow here must be at least as large
1927 as the argument to all other calls to frag_grow in
1928 this file. We don't have to worry about being in the
1929 middle of a variant frag, because the variants insert
1930 all needed nop instructions themselves. */
1934 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1938 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1939 symbol_set_frag (l
->label
, frag_now
);
1940 val
= (valueT
) frag_now_fix ();
1941 /* mips16 text labels are stored as odd. */
1942 if (mips_opts
.mips16
)
1944 S_SET_VALUE (l
->label
, val
);
1947 #ifndef NO_ECOFF_DEBUGGING
1948 if (ECOFF_DEBUGGING
)
1949 ecoff_fix_loc (old_frag
, old_frag_offset
);
1952 else if (prev_nop_frag
!= NULL
)
1954 /* We have a frag holding nops we may be able to remove. If
1955 we don't need any nops, we can decrease the size of
1956 prev_nop_frag by the size of one instruction. If we do
1957 need some nops, we count them in prev_nops_required. */
1958 if (prev_nop_frag_since
== 0)
1962 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1963 --prev_nop_frag_holds
;
1966 prev_nop_frag_required
+= nops
;
1970 if (prev_prev_nop
== 0)
1972 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1973 --prev_nop_frag_holds
;
1976 ++prev_nop_frag_required
;
1979 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1980 prev_nop_frag
= NULL
;
1982 ++prev_nop_frag_since
;
1984 /* Sanity check: by the time we reach the second instruction
1985 after prev_nop_frag, we should have used up all the nops
1986 one way or another. */
1987 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1991 /* Record the frag type before frag_var. */
1993 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
1996 && *reloc_type
== BFD_RELOC_16_PCREL_S2
1997 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
1998 || pinfo
& INSN_COND_BRANCH_LIKELY
)
1999 && mips_relax_branch
2000 /* Don't try branch relaxation within .set nomacro, or within
2001 .set noat if we use $at for PIC computations. If it turns
2002 out that the branch was out-of-range, we'll get an error. */
2003 && !mips_opts
.warn_about_macros
2004 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2005 && !mips_opts
.mips16
)
2007 relaxed_branch
= TRUE
;
2008 f
= frag_var (rs_machine_dependent
,
2009 relaxed_branch_length
2011 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2012 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2014 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2015 pinfo
& INSN_COND_BRANCH_LIKELY
,
2016 pinfo
& INSN_WRITE_GPR_31
,
2018 address_expr
->X_add_symbol
,
2019 address_expr
->X_add_number
,
2021 *reloc_type
= BFD_RELOC_UNUSED
;
2023 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2025 /* We need to set up a variant frag. */
2026 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2027 f
= frag_var (rs_machine_dependent
, 4, 0,
2028 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2029 mips16_small
, mips16_ext
,
2031 & INSN_UNCOND_BRANCH_DELAY
),
2032 (*prev_insn_reloc_type
2033 == BFD_RELOC_MIPS16_JMP
)),
2034 make_expr_symbol (address_expr
), 0, NULL
);
2036 else if (mips_opts
.mips16
2038 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2040 /* Make sure there is enough room to swap this instruction with
2041 a following jump instruction. */
2047 if (mips_opts
.mips16
2048 && mips_opts
.noreorder
2049 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2050 as_warn (_("extended instruction in delay slot"));
2052 if (mips_relax
.sequence
)
2054 /* If we've reached the end of this frag, turn it into a variant
2055 frag and record the information for the instructions we've
2057 if (frag_room () < 4)
2058 relax_close_frag ();
2059 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2062 if (mips_relax
.sequence
!= 2)
2063 mips_macro_warning
.sizes
[0] += 4;
2064 if (mips_relax
.sequence
!= 1)
2065 mips_macro_warning
.sizes
[1] += 4;
2070 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2071 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2073 if (address_expr
->X_op
== O_constant
)
2077 switch (*reloc_type
)
2080 ip
->insn_opcode
|= address_expr
->X_add_number
;
2083 case BFD_RELOC_MIPS_HIGHEST
:
2084 tmp
= (address_expr
->X_add_number
2085 + ((valueT
) 0x8000 << 32) + 0x80008000) >> 16;
2087 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2090 case BFD_RELOC_MIPS_HIGHER
:
2091 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2092 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2095 case BFD_RELOC_HI16_S
:
2096 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2100 case BFD_RELOC_HI16
:
2101 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2104 case BFD_RELOC_LO16
:
2105 case BFD_RELOC_MIPS_GOT_DISP
:
2106 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2109 case BFD_RELOC_MIPS_JMP
:
2110 if ((address_expr
->X_add_number
& 3) != 0)
2111 as_bad (_("jump to misaligned address (0x%lx)"),
2112 (unsigned long) address_expr
->X_add_number
);
2113 if (address_expr
->X_add_number
& ~0xfffffff)
2114 as_bad (_("jump address range overflow (0x%lx)"),
2115 (unsigned long) address_expr
->X_add_number
);
2116 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2119 case BFD_RELOC_MIPS16_JMP
:
2120 if ((address_expr
->X_add_number
& 3) != 0)
2121 as_bad (_("jump to misaligned address (0x%lx)"),
2122 (unsigned long) address_expr
->X_add_number
);
2123 if (address_expr
->X_add_number
& ~0xfffffff)
2124 as_bad (_("jump address range overflow (0x%lx)"),
2125 (unsigned long) address_expr
->X_add_number
);
2127 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2128 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2129 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2132 case BFD_RELOC_16_PCREL_S2
:
2142 reloc_howto_type
*howto
;
2145 /* In a compound relocation, it is the final (outermost)
2146 operator that determines the relocated field. */
2147 for (i
= 1; i
< 3; i
++)
2148 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2151 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2152 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2153 bfd_get_reloc_size(howto
),
2155 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2158 /* These relocations can have an addend that won't fit in
2159 4 octets for 64bit assembly. */
2161 && ! howto
->partial_inplace
2162 && (reloc_type
[0] == BFD_RELOC_16
2163 || reloc_type
[0] == BFD_RELOC_32
2164 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2165 || reloc_type
[0] == BFD_RELOC_HI16_S
2166 || reloc_type
[0] == BFD_RELOC_LO16
2167 || reloc_type
[0] == BFD_RELOC_GPREL16
2168 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2169 || reloc_type
[0] == BFD_RELOC_GPREL32
2170 || reloc_type
[0] == BFD_RELOC_64
2171 || reloc_type
[0] == BFD_RELOC_CTOR
2172 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2173 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2174 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2175 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2176 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2177 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2178 fixp
[0]->fx_no_overflow
= 1;
2180 if (mips_relax
.sequence
)
2182 if (mips_relax
.first_fixup
== 0)
2183 mips_relax
.first_fixup
= fixp
[0];
2185 else if (reloc_needs_lo_p (*reloc_type
))
2187 struct mips_hi_fixup
*hi_fixup
;
2189 /* Reuse the last entry if it already has a matching %lo. */
2190 hi_fixup
= mips_hi_fixup_list
;
2192 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2194 hi_fixup
= ((struct mips_hi_fixup
*)
2195 xmalloc (sizeof (struct mips_hi_fixup
)));
2196 hi_fixup
->next
= mips_hi_fixup_list
;
2197 mips_hi_fixup_list
= hi_fixup
;
2199 hi_fixup
->fixp
= fixp
[0];
2200 hi_fixup
->seg
= now_seg
;
2203 /* Add fixups for the second and third relocations, if given.
2204 Note that the ABI allows the second relocation to be
2205 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2206 moment we only use RSS_UNDEF, but we could add support
2207 for the others if it ever becomes necessary. */
2208 for (i
= 1; i
< 3; i
++)
2209 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2211 address_expr
->X_op
= O_absent
;
2212 address_expr
->X_add_symbol
= 0;
2213 address_expr
->X_add_number
= 0;
2215 fixp
[i
] = fix_new_exp (frag_now
, fixp
[0]->fx_where
,
2216 fixp
[0]->fx_size
, address_expr
,
2217 FALSE
, reloc_type
[i
]);
2222 if (! mips_opts
.mips16
)
2224 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2226 dwarf2_emit_insn (4);
2229 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2231 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2232 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2234 dwarf2_emit_insn (4);
2241 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2244 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2246 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2250 /* Update the register mask information. */
2251 if (! mips_opts
.mips16
)
2253 if (pinfo
& INSN_WRITE_GPR_D
)
2254 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2255 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2256 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2257 if (pinfo
& INSN_READ_GPR_S
)
2258 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2259 if (pinfo
& INSN_WRITE_GPR_31
)
2260 mips_gprmask
|= 1 << RA
;
2261 if (pinfo
& INSN_WRITE_FPR_D
)
2262 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2263 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2264 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2265 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2266 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2267 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2268 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2269 if (pinfo
& INSN_COP
)
2271 /* We don't keep enough information to sort these cases out.
2272 The itbl support does keep this information however, although
2273 we currently don't support itbl fprmats as part of the cop
2274 instruction. May want to add this support in the future. */
2276 /* Never set the bit for $0, which is always zero. */
2277 mips_gprmask
&= ~1 << 0;
2281 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2282 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2283 & MIPS16OP_MASK_RX
);
2284 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2285 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2286 & MIPS16OP_MASK_RY
);
2287 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2288 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2289 & MIPS16OP_MASK_RZ
);
2290 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2291 mips_gprmask
|= 1 << TREG
;
2292 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2293 mips_gprmask
|= 1 << SP
;
2294 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2295 mips_gprmask
|= 1 << RA
;
2296 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2297 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2298 if (pinfo
& MIPS16_INSN_READ_Z
)
2299 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2300 & MIPS16OP_MASK_MOVE32Z
);
2301 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2302 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2303 & MIPS16OP_MASK_REGR32
);
2306 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2308 /* Filling the branch delay slot is more complex. We try to
2309 switch the branch with the previous instruction, which we can
2310 do if the previous instruction does not set up a condition
2311 that the branch tests and if the branch is not itself the
2312 target of any branch. */
2313 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2314 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2316 if (mips_optimize
< 2
2317 /* If we have seen .set volatile or .set nomove, don't
2319 || mips_opts
.nomove
!= 0
2320 /* If we had to emit any NOP instructions, then we
2321 already know we can not swap. */
2323 /* If we don't even know the previous insn, we can not
2325 || ! prev_insn_valid
2326 /* If the previous insn is already in a branch delay
2327 slot, then we can not swap. */
2328 || prev_insn_is_delay_slot
2329 /* If the previous previous insn was in a .set
2330 noreorder, we can't swap. Actually, the MIPS
2331 assembler will swap in this situation. However, gcc
2332 configured -with-gnu-as will generate code like
2338 in which we can not swap the bne and INSN. If gcc is
2339 not configured -with-gnu-as, it does not output the
2340 .set pseudo-ops. We don't have to check
2341 prev_insn_unreordered, because prev_insn_valid will
2342 be 0 in that case. We don't want to use
2343 prev_prev_insn_valid, because we do want to be able
2344 to swap at the start of a function. */
2345 || prev_prev_insn_unreordered
2346 /* If the branch is itself the target of a branch, we
2347 can not swap. We cheat on this; all we check for is
2348 whether there is a label on this instruction. If
2349 there are any branches to anything other than a
2350 label, users must use .set noreorder. */
2351 || insn_labels
!= NULL
2352 /* If the previous instruction is in a variant frag
2353 other than this branch's one, we cannot do the swap.
2354 This does not apply to the mips16, which uses variant
2355 frags for different purposes. */
2356 || (! mips_opts
.mips16
2357 && prev_insn_frag_type
== rs_machine_dependent
)
2358 /* If the branch reads the condition codes, we don't
2359 even try to swap, because in the sequence
2364 we can not swap, and I don't feel like handling that
2366 || (! mips_opts
.mips16
2367 && (pinfo
& INSN_READ_COND_CODE
)
2368 && ! cop_interlocks
)
2369 /* We can not swap with an instruction that requires a
2370 delay slot, because the target of the branch might
2371 interfere with that instruction. */
2372 || (! mips_opts
.mips16
2374 /* Itbl support may require additional care here. */
2375 & (INSN_LOAD_COPROC_DELAY
2376 | INSN_COPROC_MOVE_DELAY
2377 | INSN_WRITE_COND_CODE
))
2378 && ! cop_interlocks
)
2379 || (! (hilo_interlocks
2380 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2384 || (! mips_opts
.mips16
2385 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2386 && ! gpr_interlocks
)
2387 || (! mips_opts
.mips16
2388 /* Itbl support may require additional care here. */
2389 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2390 && ! cop_mem_interlocks
)
2391 /* We can not swap with a branch instruction. */
2393 & (INSN_UNCOND_BRANCH_DELAY
2394 | INSN_COND_BRANCH_DELAY
2395 | INSN_COND_BRANCH_LIKELY
))
2396 /* We do not swap with a trap instruction, since it
2397 complicates trap handlers to have the trap
2398 instruction be in a delay slot. */
2399 || (prev_pinfo
& INSN_TRAP
)
2400 /* If the branch reads a register that the previous
2401 instruction sets, we can not swap. */
2402 || (! mips_opts
.mips16
2403 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2404 && insn_uses_reg (ip
,
2405 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2408 || (! mips_opts
.mips16
2409 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2410 && insn_uses_reg (ip
,
2411 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2414 || (mips_opts
.mips16
2415 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2416 && insn_uses_reg (ip
,
2417 ((prev_insn
.insn_opcode
2419 & MIPS16OP_MASK_RX
),
2421 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2422 && insn_uses_reg (ip
,
2423 ((prev_insn
.insn_opcode
2425 & MIPS16OP_MASK_RY
),
2427 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2428 && insn_uses_reg (ip
,
2429 ((prev_insn
.insn_opcode
2431 & MIPS16OP_MASK_RZ
),
2433 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2434 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2435 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2436 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2437 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2438 && insn_uses_reg (ip
,
2439 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2442 /* If the branch writes a register that the previous
2443 instruction sets, we can not swap (we know that
2444 branches write only to RD or to $31). */
2445 || (! mips_opts
.mips16
2446 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2447 && (((pinfo
& INSN_WRITE_GPR_D
)
2448 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2449 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2450 || ((pinfo
& INSN_WRITE_GPR_31
)
2451 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2454 || (! mips_opts
.mips16
2455 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2456 && (((pinfo
& INSN_WRITE_GPR_D
)
2457 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2458 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2459 || ((pinfo
& INSN_WRITE_GPR_31
)
2460 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2463 || (mips_opts
.mips16
2464 && (pinfo
& MIPS16_INSN_WRITE_31
)
2465 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2466 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2467 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2469 /* If the branch writes a register that the previous
2470 instruction reads, we can not swap (we know that
2471 branches only write to RD or to $31). */
2472 || (! mips_opts
.mips16
2473 && (pinfo
& INSN_WRITE_GPR_D
)
2474 && insn_uses_reg (&prev_insn
,
2475 ((ip
->insn_opcode
>> OP_SH_RD
)
2478 || (! mips_opts
.mips16
2479 && (pinfo
& INSN_WRITE_GPR_31
)
2480 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2481 || (mips_opts
.mips16
2482 && (pinfo
& MIPS16_INSN_WRITE_31
)
2483 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2484 /* If the previous previous instruction has a load
2485 delay, and sets a register that the branch reads, we
2487 || (! mips_opts
.mips16
2488 /* Itbl support may require additional care here. */
2489 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2490 && ! cop_interlocks
)
2491 || ((prev_prev_insn
.insn_mo
->pinfo
2492 & INSN_LOAD_MEMORY_DELAY
)
2493 && ! gpr_interlocks
))
2494 && insn_uses_reg (ip
,
2495 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2498 /* If one instruction sets a condition code and the
2499 other one uses a condition code, we can not swap. */
2500 || ((pinfo
& INSN_READ_COND_CODE
)
2501 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2502 || ((pinfo
& INSN_WRITE_COND_CODE
)
2503 && (prev_pinfo
& INSN_READ_COND_CODE
))
2504 /* If the previous instruction uses the PC, we can not
2506 || (mips_opts
.mips16
2507 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2508 /* If the previous instruction was extended, we can not
2510 || (mips_opts
.mips16
&& prev_insn_extended
)
2511 /* If the previous instruction had a fixup in mips16
2512 mode, we can not swap. This normally means that the
2513 previous instruction was a 4 byte branch anyhow. */
2514 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2515 /* If the previous instruction is a sync, sync.l, or
2516 sync.p, we can not swap. */
2517 || (prev_pinfo
& INSN_SYNC
))
2519 /* We could do even better for unconditional branches to
2520 portions of this object file; we could pick up the
2521 instruction at the destination, put it in the delay
2522 slot, and bump the destination address. */
2524 /* Update the previous insn information. */
2525 prev_prev_insn
= *ip
;
2526 prev_insn
.insn_mo
= &dummy_opcode
;
2530 /* It looks like we can actually do the swap. */
2531 if (! mips_opts
.mips16
)
2536 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2537 if (!relaxed_branch
)
2539 /* If this is not a relaxed branch, then just
2540 swap the instructions. */
2541 memcpy (temp
, prev_f
, 4);
2542 memcpy (prev_f
, f
, 4);
2543 memcpy (f
, temp
, 4);
2547 /* If this is a relaxed branch, then we move the
2548 instruction to be placed in the delay slot to
2549 the current frag, shrinking the fixed part of
2550 the originating frag. If the branch occupies
2551 the tail of the latter, we move it backwards,
2552 into the space freed by the moved instruction. */
2554 memcpy (f
, prev_f
, 4);
2555 prev_insn_frag
->fr_fix
-= 4;
2556 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2557 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2560 if (prev_insn_fixp
[0])
2562 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2563 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2565 if (prev_insn_fixp
[1])
2567 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2568 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2570 if (prev_insn_fixp
[2])
2572 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2573 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2575 if (prev_insn_fixp
[0] && HAVE_NEWABI
2576 && prev_insn_frag
!= frag_now
2577 && (prev_insn_fixp
[0]->fx_r_type
2578 == BFD_RELOC_MIPS_GOT_DISP
2579 || (prev_insn_fixp
[0]->fx_r_type
2580 == BFD_RELOC_MIPS_CALL16
)))
2582 /* To avoid confusion in tc_gen_reloc, we must
2583 ensure that this does not become a variant
2585 force_new_frag
= TRUE
;
2588 if (!relaxed_branch
)
2592 fixp
[0]->fx_frag
= prev_insn_frag
;
2593 fixp
[0]->fx_where
= prev_insn_where
;
2597 fixp
[1]->fx_frag
= prev_insn_frag
;
2598 fixp
[1]->fx_where
= prev_insn_where
;
2602 fixp
[2]->fx_frag
= prev_insn_frag
;
2603 fixp
[2]->fx_where
= prev_insn_where
;
2606 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2609 fixp
[0]->fx_where
-= 4;
2611 fixp
[1]->fx_where
-= 4;
2613 fixp
[2]->fx_where
-= 4;
2621 assert (prev_insn_fixp
[0] == NULL
);
2622 assert (prev_insn_fixp
[1] == NULL
);
2623 assert (prev_insn_fixp
[2] == NULL
);
2624 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2625 memcpy (temp
, prev_f
, 2);
2626 memcpy (prev_f
, f
, 2);
2627 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2629 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2630 memcpy (f
, temp
, 2);
2634 memcpy (f
, f
+ 2, 2);
2635 memcpy (f
+ 2, temp
, 2);
2639 fixp
[0]->fx_frag
= prev_insn_frag
;
2640 fixp
[0]->fx_where
= prev_insn_where
;
2644 fixp
[1]->fx_frag
= prev_insn_frag
;
2645 fixp
[1]->fx_where
= prev_insn_where
;
2649 fixp
[2]->fx_frag
= prev_insn_frag
;
2650 fixp
[2]->fx_where
= prev_insn_where
;
2654 /* Update the previous insn information; leave prev_insn
2656 prev_prev_insn
= *ip
;
2658 prev_insn_is_delay_slot
= 1;
2660 /* If that was an unconditional branch, forget the previous
2661 insn information. */
2662 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2664 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2665 prev_insn
.insn_mo
= &dummy_opcode
;
2668 prev_insn_fixp
[0] = NULL
;
2669 prev_insn_fixp
[1] = NULL
;
2670 prev_insn_fixp
[2] = NULL
;
2671 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2672 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2673 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2674 prev_insn_extended
= 0;
2676 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2678 /* We don't yet optimize a branch likely. What we should do
2679 is look at the target, copy the instruction found there
2680 into the delay slot, and increment the branch to jump to
2681 the next instruction. */
2683 /* Update the previous insn information. */
2684 prev_prev_insn
= *ip
;
2685 prev_insn
.insn_mo
= &dummy_opcode
;
2686 prev_insn_fixp
[0] = NULL
;
2687 prev_insn_fixp
[1] = NULL
;
2688 prev_insn_fixp
[2] = NULL
;
2689 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2690 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2691 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2692 prev_insn_extended
= 0;
2696 /* Update the previous insn information. */
2698 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2700 prev_prev_insn
= prev_insn
;
2703 /* Any time we see a branch, we always fill the delay slot
2704 immediately; since this insn is not a branch, we know it
2705 is not in a delay slot. */
2706 prev_insn_is_delay_slot
= 0;
2708 prev_insn_fixp
[0] = fixp
[0];
2709 prev_insn_fixp
[1] = fixp
[1];
2710 prev_insn_fixp
[2] = fixp
[2];
2711 prev_insn_reloc_type
[0] = reloc_type
[0];
2712 prev_insn_reloc_type
[1] = reloc_type
[1];
2713 prev_insn_reloc_type
[2] = reloc_type
[2];
2714 if (mips_opts
.mips16
)
2715 prev_insn_extended
= (ip
->use_extend
2716 || *reloc_type
> BFD_RELOC_UNUSED
);
2719 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2720 prev_insn_unreordered
= 0;
2721 prev_insn_frag
= frag_now
;
2722 prev_insn_where
= f
- frag_now
->fr_literal
;
2723 prev_insn_valid
= 1;
2725 else if (mips_relax
.sequence
!= 2)
2727 /* We need to record a bit of information even when we are not
2728 reordering, in order to determine the base address for mips16
2729 PC relative relocs. */
2730 prev_prev_insn
= prev_insn
;
2732 prev_insn_reloc_type
[0] = reloc_type
[0];
2733 prev_insn_reloc_type
[1] = reloc_type
[1];
2734 prev_insn_reloc_type
[2] = reloc_type
[2];
2735 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2736 prev_insn_unreordered
= 1;
2739 /* We just output an insn, so the next one doesn't have a label. */
2740 mips_clear_insn_labels ();
2743 /* This function forgets that there was any previous instruction or
2744 label. If PRESERVE is non-zero, it remembers enough information to
2745 know whether nops are needed before a noreorder section. */
2748 mips_no_prev_insn (int preserve
)
2752 prev_insn
.insn_mo
= &dummy_opcode
;
2753 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2754 prev_nop_frag
= NULL
;
2755 prev_nop_frag_holds
= 0;
2756 prev_nop_frag_required
= 0;
2757 prev_nop_frag_since
= 0;
2759 prev_insn_valid
= 0;
2760 prev_insn_is_delay_slot
= 0;
2761 prev_insn_unreordered
= 0;
2762 prev_insn_extended
= 0;
2763 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2764 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2765 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2766 prev_prev_insn_unreordered
= 0;
2767 mips_clear_insn_labels ();
2770 /* This function must be called whenever we turn on noreorder or emit
2771 something other than instructions. It inserts any NOPS which might
2772 be needed by the previous instruction, and clears the information
2773 kept for the previous instructions. The INSNS parameter is true if
2774 instructions are to follow. */
2777 mips_emit_delays (bfd_boolean insns
)
2779 if (! mips_opts
.noreorder
)
2784 if ((! mips_opts
.mips16
2785 && ((prev_insn
.insn_mo
->pinfo
2786 & (INSN_LOAD_COPROC_DELAY
2787 | INSN_COPROC_MOVE_DELAY
2788 | INSN_WRITE_COND_CODE
))
2789 && ! cop_interlocks
))
2790 || (! hilo_interlocks
2791 && (prev_insn
.insn_mo
->pinfo
2794 || (! mips_opts
.mips16
2795 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2796 && ! gpr_interlocks
)
2797 || (! mips_opts
.mips16
2798 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2799 && ! cop_mem_interlocks
))
2801 /* Itbl support may require additional care here. */
2803 if ((! mips_opts
.mips16
2804 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2805 && ! cop_interlocks
))
2806 || (! hilo_interlocks
2807 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2808 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2811 if (prev_insn_unreordered
)
2814 else if ((! mips_opts
.mips16
2815 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2816 && ! cop_interlocks
))
2817 || (! hilo_interlocks
2818 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2819 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2821 /* Itbl support may require additional care here. */
2822 if (! prev_prev_insn_unreordered
)
2826 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2829 const char *pn
= prev_insn
.insn_mo
->name
;
2830 if (strncmp(pn
, "macc", 4) == 0
2831 || strncmp(pn
, "dmacc", 5) == 0
2832 || strncmp(pn
, "dmult", 5) == 0)
2836 if (nops
< min_nops
)
2842 struct insn_label_list
*l
;
2846 /* Record the frag which holds the nop instructions, so
2847 that we can remove them if we don't need them. */
2848 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2849 prev_nop_frag
= frag_now
;
2850 prev_nop_frag_holds
= nops
;
2851 prev_nop_frag_required
= 0;
2852 prev_nop_frag_since
= 0;
2855 for (; nops
> 0; --nops
)
2860 /* Move on to a new frag, so that it is safe to simply
2861 decrease the size of prev_nop_frag. */
2862 frag_wane (frag_now
);
2866 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2870 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2871 symbol_set_frag (l
->label
, frag_now
);
2872 val
= (valueT
) frag_now_fix ();
2873 /* mips16 text labels are stored as odd. */
2874 if (mips_opts
.mips16
)
2876 S_SET_VALUE (l
->label
, val
);
2881 /* Mark instruction labels in mips16 mode. */
2883 mips16_mark_labels ();
2885 mips_no_prev_insn (insns
);
2888 /* Set up global variables for the start of a new macro. */
2893 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2894 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2895 && (prev_insn
.insn_mo
->pinfo
2896 & (INSN_UNCOND_BRANCH_DELAY
2897 | INSN_COND_BRANCH_DELAY
2898 | INSN_COND_BRANCH_LIKELY
)) != 0);
2901 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2902 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2903 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2906 macro_warning (relax_substateT subtype
)
2908 if (subtype
& RELAX_DELAY_SLOT
)
2909 return _("Macro instruction expanded into multiple instructions"
2910 " in a branch delay slot");
2911 else if (subtype
& RELAX_NOMACRO
)
2912 return _("Macro instruction expanded into multiple instructions");
2917 /* Finish up a macro. Emit warnings as appropriate. */
2922 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2924 relax_substateT subtype
;
2926 /* Set up the relaxation warning flags. */
2928 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2929 subtype
|= RELAX_SECOND_LONGER
;
2930 if (mips_opts
.warn_about_macros
)
2931 subtype
|= RELAX_NOMACRO
;
2932 if (mips_macro_warning
.delay_slot_p
)
2933 subtype
|= RELAX_DELAY_SLOT
;
2935 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2937 /* Either the macro has a single implementation or both
2938 implementations are longer than 4 bytes. Emit the
2940 const char *msg
= macro_warning (subtype
);
2946 /* One implementation might need a warning but the other
2947 definitely doesn't. */
2948 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2953 /* Build an instruction created by a macro expansion. This is passed
2954 a pointer to the count of instructions created so far, an
2955 expression, the name of the instruction to build, an operand format
2956 string, and corresponding arguments. */
2959 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2961 struct mips_cl_insn insn
;
2962 bfd_reloc_code_real_type r
[3];
2965 va_start (args
, fmt
);
2967 if (mips_opts
.mips16
)
2969 mips16_macro_build (ep
, name
, fmt
, args
);
2974 r
[0] = BFD_RELOC_UNUSED
;
2975 r
[1] = BFD_RELOC_UNUSED
;
2976 r
[2] = BFD_RELOC_UNUSED
;
2977 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2978 assert (insn
.insn_mo
);
2979 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2981 /* Search until we get a match for NAME. */
2984 /* It is assumed here that macros will never generate
2985 MDMX or MIPS-3D instructions. */
2986 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2987 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2988 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2990 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2992 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2996 assert (insn
.insn_mo
->name
);
2997 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3000 insn
.insn_opcode
= insn
.insn_mo
->match
;
3018 insn
.insn_opcode
|= (va_arg (args
, int)
3019 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3024 /* Note that in the macro case, these arguments are already
3025 in MSB form. (When handling the instruction in the
3026 non-macro case, these arguments are sizes from which
3027 MSB values must be calculated.) */
3028 insn
.insn_opcode
|= (va_arg (args
, int)
3029 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3035 /* Note that in the macro case, these arguments are already
3036 in MSBD form. (When handling the instruction in the
3037 non-macro case, these arguments are sizes from which
3038 MSBD values must be calculated.) */
3039 insn
.insn_opcode
|= (va_arg (args
, int)
3040 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3051 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3055 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3060 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3066 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3071 int tmp
= va_arg (args
, int);
3073 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3074 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3080 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3087 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3091 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3095 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3099 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3103 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3110 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3116 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3117 assert (*r
== BFD_RELOC_GPREL16
3118 || *r
== BFD_RELOC_MIPS_LITERAL
3119 || *r
== BFD_RELOC_MIPS_HIGHER
3120 || *r
== BFD_RELOC_HI16_S
3121 || *r
== BFD_RELOC_LO16
3122 || *r
== BFD_RELOC_MIPS_GOT16
3123 || *r
== BFD_RELOC_MIPS_CALL16
3124 || *r
== BFD_RELOC_MIPS_GOT_DISP
3125 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3126 || *r
== BFD_RELOC_MIPS_GOT_OFST
3127 || *r
== BFD_RELOC_MIPS_GOT_LO16
3128 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3132 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3134 && (ep
->X_op
== O_constant
3135 || (ep
->X_op
== O_symbol
3136 && (*r
== BFD_RELOC_MIPS_HIGHEST
3137 || *r
== BFD_RELOC_HI16_S
3138 || *r
== BFD_RELOC_HI16
3139 || *r
== BFD_RELOC_GPREL16
3140 || *r
== BFD_RELOC_MIPS_GOT_HI16
3141 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3145 assert (ep
!= NULL
);
3147 * This allows macro() to pass an immediate expression for
3148 * creating short branches without creating a symbol.
3149 * Note that the expression still might come from the assembly
3150 * input, in which case the value is not checked for range nor
3151 * is a relocation entry generated (yuck).
3153 if (ep
->X_op
== O_constant
)
3155 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3159 *r
= BFD_RELOC_16_PCREL_S2
;
3163 assert (ep
!= NULL
);
3164 *r
= BFD_RELOC_MIPS_JMP
;
3168 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3177 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3179 append_insn (&insn
, ep
, r
);
3183 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3186 struct mips_cl_insn insn
;
3187 bfd_reloc_code_real_type r
[3]
3188 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3190 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3191 assert (insn
.insn_mo
);
3192 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3194 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3195 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3198 assert (insn
.insn_mo
->name
);
3199 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3202 insn
.insn_opcode
= insn
.insn_mo
->match
;
3203 insn
.use_extend
= FALSE
;
3222 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3227 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3231 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3235 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3245 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3252 regno
= va_arg (args
, int);
3253 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3254 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3275 assert (ep
!= NULL
);
3277 if (ep
->X_op
!= O_constant
)
3278 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3281 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3282 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3285 *r
= BFD_RELOC_UNUSED
;
3291 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3298 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3300 append_insn (&insn
, ep
, r
);
3304 * Generate a "jalr" instruction with a relocation hint to the called
3305 * function. This occurs in NewABI PIC code.
3308 macro_build_jalr (expressionS
*ep
)
3317 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3319 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3320 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3324 * Generate a "lui" instruction.
3327 macro_build_lui (expressionS
*ep
, int regnum
)
3329 expressionS high_expr
;
3330 struct mips_cl_insn insn
;
3331 bfd_reloc_code_real_type r
[3]
3332 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3333 const char *name
= "lui";
3334 const char *fmt
= "t,u";
3336 assert (! mips_opts
.mips16
);
3340 if (high_expr
.X_op
== O_constant
)
3342 /* we can compute the instruction now without a relocation entry */
3343 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3345 *r
= BFD_RELOC_UNUSED
;
3349 assert (ep
->X_op
== O_symbol
);
3350 /* _gp_disp is a special case, used from s_cpload. */
3351 assert (mips_pic
== NO_PIC
3353 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3354 *r
= BFD_RELOC_HI16_S
;
3357 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3358 assert (insn
.insn_mo
);
3359 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3360 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3362 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3363 if (*r
== BFD_RELOC_UNUSED
)
3365 insn
.insn_opcode
|= high_expr
.X_add_number
;
3366 append_insn (&insn
, NULL
, r
);
3369 append_insn (&insn
, &high_expr
, r
);
3372 /* Generate a sequence of instructions to do a load or store from a constant
3373 offset off of a base register (breg) into/from a target register (treg),
3374 using AT if necessary. */
3376 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3377 int treg
, int breg
, int dbl
)
3379 assert (ep
->X_op
== O_constant
);
3381 /* Sign-extending 32-bit constants makes their handling easier. */
3382 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3383 == ~((bfd_vma
) 0x7fffffff)))
3385 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3386 as_bad (_("constant too large"));
3388 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3392 /* Right now, this routine can only handle signed 32-bit constants. */
3393 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3394 as_warn (_("operand overflow"));
3396 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3398 /* Signed 16-bit offset will fit in the op. Easy! */
3399 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3403 /* 32-bit offset, need multiple instructions and AT, like:
3404 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3405 addu $tempreg,$tempreg,$breg
3406 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3407 to handle the complete offset. */
3408 macro_build_lui (ep
, AT
);
3409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3410 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3413 as_warn (_("Macro used $at after \".set noat\""));
3418 * Generates code to set the $at register to true (one)
3419 * if reg is less than the immediate expression.
3422 set_at (int reg
, int unsignedp
)
3424 if (imm_expr
.X_op
== O_constant
3425 && imm_expr
.X_add_number
>= -0x8000
3426 && imm_expr
.X_add_number
< 0x8000)
3427 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3428 AT
, reg
, BFD_RELOC_LO16
);
3431 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3432 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3437 normalize_constant_expr (expressionS
*ex
)
3439 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3440 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3444 /* Warn if an expression is not a constant. */
3447 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3449 if (ex
->X_op
== O_big
)
3450 as_bad (_("unsupported large constant"));
3451 else if (ex
->X_op
!= O_constant
)
3452 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3454 normalize_constant_expr (ex
);
3457 /* Count the leading zeroes by performing a binary chop. This is a
3458 bulky bit of source, but performance is a LOT better for the
3459 majority of values than a simple loop to count the bits:
3460 for (lcnt = 0; (lcnt < 32); lcnt++)
3461 if ((v) & (1 << (31 - lcnt)))
3463 However it is not code size friendly, and the gain will drop a bit
3464 on certain cached systems.
3466 #define COUNT_TOP_ZEROES(v) \
3467 (((v) & ~0xffff) == 0 \
3468 ? ((v) & ~0xff) == 0 \
3469 ? ((v) & ~0xf) == 0 \
3470 ? ((v) & ~0x3) == 0 \
3471 ? ((v) & ~0x1) == 0 \
3476 : ((v) & ~0x7) == 0 \
3479 : ((v) & ~0x3f) == 0 \
3480 ? ((v) & ~0x1f) == 0 \
3483 : ((v) & ~0x7f) == 0 \
3486 : ((v) & ~0xfff) == 0 \
3487 ? ((v) & ~0x3ff) == 0 \
3488 ? ((v) & ~0x1ff) == 0 \
3491 : ((v) & ~0x7ff) == 0 \
3494 : ((v) & ~0x3fff) == 0 \
3495 ? ((v) & ~0x1fff) == 0 \
3498 : ((v) & ~0x7fff) == 0 \
3501 : ((v) & ~0xffffff) == 0 \
3502 ? ((v) & ~0xfffff) == 0 \
3503 ? ((v) & ~0x3ffff) == 0 \
3504 ? ((v) & ~0x1ffff) == 0 \
3507 : ((v) & ~0x7ffff) == 0 \
3510 : ((v) & ~0x3fffff) == 0 \
3511 ? ((v) & ~0x1fffff) == 0 \
3514 : ((v) & ~0x7fffff) == 0 \
3517 : ((v) & ~0xfffffff) == 0 \
3518 ? ((v) & ~0x3ffffff) == 0 \
3519 ? ((v) & ~0x1ffffff) == 0 \
3522 : ((v) & ~0x7ffffff) == 0 \
3525 : ((v) & ~0x3fffffff) == 0 \
3526 ? ((v) & ~0x1fffffff) == 0 \
3529 : ((v) & ~0x7fffffff) == 0 \
3534 * This routine generates the least number of instructions necessary to load
3535 * an absolute expression value into a register.
3538 load_register (int reg
, expressionS
*ep
, int dbl
)
3541 expressionS hi32
, lo32
;
3543 if (ep
->X_op
!= O_big
)
3545 assert (ep
->X_op
== O_constant
);
3547 /* Sign-extending 32-bit constants makes their handling easier. */
3548 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3549 == ~((bfd_vma
) 0x7fffffff)))
3551 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3552 as_bad (_("constant too large"));
3554 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3558 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3560 /* We can handle 16 bit signed values with an addiu to
3561 $zero. No need to ever use daddiu here, since $zero and
3562 the result are always correct in 32 bit mode. */
3563 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3566 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3568 /* We can handle 16 bit unsigned values with an ori to
3570 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3573 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3575 /* 32 bit values require an lui. */
3576 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3577 if ((ep
->X_add_number
& 0xffff) != 0)
3578 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3583 /* The value is larger than 32 bits. */
3585 if (HAVE_32BIT_GPRS
)
3587 as_bad (_("Number (0x%lx) larger than 32 bits"),
3588 (unsigned long) ep
->X_add_number
);
3589 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3593 if (ep
->X_op
!= O_big
)
3596 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3597 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3598 hi32
.X_add_number
&= 0xffffffff;
3600 lo32
.X_add_number
&= 0xffffffff;
3604 assert (ep
->X_add_number
> 2);
3605 if (ep
->X_add_number
== 3)
3606 generic_bignum
[3] = 0;
3607 else if (ep
->X_add_number
> 4)
3608 as_bad (_("Number larger than 64 bits"));
3609 lo32
.X_op
= O_constant
;
3610 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3611 hi32
.X_op
= O_constant
;
3612 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3615 if (hi32
.X_add_number
== 0)
3620 unsigned long hi
, lo
;
3622 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3624 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3626 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3629 if (lo32
.X_add_number
& 0x80000000)
3631 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3632 if (lo32
.X_add_number
& 0xffff)
3633 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3638 /* Check for 16bit shifted constant. We know that hi32 is
3639 non-zero, so start the mask on the first bit of the hi32
3644 unsigned long himask
, lomask
;
3648 himask
= 0xffff >> (32 - shift
);
3649 lomask
= (0xffff << shift
) & 0xffffffff;
3653 himask
= 0xffff << (shift
- 32);
3656 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3657 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3661 tmp
.X_op
= O_constant
;
3663 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3664 | (lo32
.X_add_number
>> shift
));
3666 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3667 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3668 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3669 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3674 while (shift
<= (64 - 16));
3676 /* Find the bit number of the lowest one bit, and store the
3677 shifted value in hi/lo. */
3678 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3679 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3683 while ((lo
& 1) == 0)
3688 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3694 while ((hi
& 1) == 0)
3703 /* Optimize if the shifted value is a (power of 2) - 1. */
3704 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3705 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3707 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3712 /* This instruction will set the register to be all
3714 tmp
.X_op
= O_constant
;
3715 tmp
.X_add_number
= (offsetT
) -1;
3716 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3720 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3721 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3723 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3724 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3729 /* Sign extend hi32 before calling load_register, because we can
3730 generally get better code when we load a sign extended value. */
3731 if ((hi32
.X_add_number
& 0x80000000) != 0)
3732 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3733 load_register (reg
, &hi32
, 0);
3736 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3740 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3748 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3750 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3751 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3757 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3761 mid16
.X_add_number
>>= 16;
3762 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3763 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3766 if ((lo32
.X_add_number
& 0xffff) != 0)
3767 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3771 load_delay_nop (void)
3773 if (!gpr_interlocks
)
3774 macro_build (NULL
, "nop", "");
3777 /* Load an address into a register. */
3780 load_address (int reg
, expressionS
*ep
, int *used_at
)
3782 if (ep
->X_op
!= O_constant
3783 && ep
->X_op
!= O_symbol
)
3785 as_bad (_("expression too complex"));
3786 ep
->X_op
= O_constant
;
3789 if (ep
->X_op
== O_constant
)
3791 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3795 if (mips_pic
== NO_PIC
)
3797 /* If this is a reference to a GP relative symbol, we want
3798 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3800 lui $reg,<sym> (BFD_RELOC_HI16_S)
3801 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3802 If we have an addend, we always use the latter form.
3804 With 64bit address space and a usable $at we want
3805 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3806 lui $at,<sym> (BFD_RELOC_HI16_S)
3807 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3808 daddiu $at,<sym> (BFD_RELOC_LO16)
3812 If $at is already in use, we use a path which is suboptimal
3813 on superscalar processors.
3814 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3815 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3817 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3819 daddiu $reg,<sym> (BFD_RELOC_LO16)
3821 if (HAVE_64BIT_ADDRESSES
)
3823 /* ??? We don't provide a GP-relative alternative for these macros.
3824 It used not to be possible with the original relaxation code,
3825 but it could be done now. */
3827 if (*used_at
== 0 && ! mips_opts
.noat
)
3829 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3830 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3831 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3832 BFD_RELOC_MIPS_HIGHER
);
3833 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3834 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3835 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3840 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3841 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3842 BFD_RELOC_MIPS_HIGHER
);
3843 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3844 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3845 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3846 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3851 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3852 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3854 relax_start (ep
->X_add_symbol
);
3855 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3856 mips_gp_register
, BFD_RELOC_GPREL16
);
3859 macro_build_lui (ep
, reg
);
3860 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3861 reg
, reg
, BFD_RELOC_LO16
);
3862 if (mips_relax
.sequence
)
3866 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3870 /* If this is a reference to an external symbol, we want
3871 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3873 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3875 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3876 If there is a constant, it must be added in after.
3878 If we have NewABI, we want
3879 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3880 unless we're referencing a global symbol with a non-zero
3881 offset, in which case cst must be added separately. */
3884 if (ep
->X_add_number
)
3886 ex
.X_add_number
= ep
->X_add_number
;
3887 ep
->X_add_number
= 0;
3888 relax_start (ep
->X_add_symbol
);
3889 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3890 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3891 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3892 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3893 ex
.X_op
= O_constant
;
3894 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3895 reg
, reg
, BFD_RELOC_LO16
);
3896 ep
->X_add_number
= ex
.X_add_number
;
3899 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3900 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3901 if (mips_relax
.sequence
)
3906 ex
.X_add_number
= ep
->X_add_number
;
3907 ep
->X_add_number
= 0;
3908 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3909 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3911 relax_start (ep
->X_add_symbol
);
3913 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3917 if (ex
.X_add_number
!= 0)
3919 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3920 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3921 ex
.X_op
= O_constant
;
3922 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3923 reg
, reg
, BFD_RELOC_LO16
);
3927 else if (mips_pic
== SVR4_PIC
)
3931 /* This is the large GOT case. If this is a reference to an
3932 external symbol, we want
3933 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3935 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3937 Otherwise, for a reference to a local symbol in old ABI, we want
3938 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3940 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3941 If there is a constant, it must be added in after.
3943 In the NewABI, for local symbols, with or without offsets, we want:
3944 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3945 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3949 ex
.X_add_number
= ep
->X_add_number
;
3950 ep
->X_add_number
= 0;
3951 relax_start (ep
->X_add_symbol
);
3952 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3953 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3954 reg
, reg
, mips_gp_register
);
3955 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3956 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3957 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3958 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3959 else if (ex
.X_add_number
)
3961 ex
.X_op
= O_constant
;
3962 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3966 ep
->X_add_number
= ex
.X_add_number
;
3968 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3969 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3970 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3971 BFD_RELOC_MIPS_GOT_OFST
);
3976 ex
.X_add_number
= ep
->X_add_number
;
3977 ep
->X_add_number
= 0;
3978 relax_start (ep
->X_add_symbol
);
3979 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3980 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3981 reg
, reg
, mips_gp_register
);
3982 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3983 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3985 if (reg_needs_delay (mips_gp_register
))
3987 /* We need a nop before loading from $gp. This special
3988 check is required because the lui which starts the main
3989 instruction stream does not refer to $gp, and so will not
3990 insert the nop which may be required. */
3991 macro_build (NULL
, "nop", "");
3993 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3994 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3996 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4000 if (ex
.X_add_number
!= 0)
4002 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4003 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4004 ex
.X_op
= O_constant
;
4005 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4014 /* Move the contents of register SOURCE into register DEST. */
4017 move_register (int dest
, int source
)
4019 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4023 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4024 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4025 The two alternatives are:
4027 Global symbol Local sybmol
4028 ------------- ------------
4029 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4031 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4033 load_got_offset emits the first instruction and add_got_offset
4034 emits the second for a 16-bit offset or add_got_offset_hilo emits
4035 a sequence to add a 32-bit offset using a scratch register. */
4038 load_got_offset (int dest
, expressionS
*local
)
4043 global
.X_add_number
= 0;
4045 relax_start (local
->X_add_symbol
);
4046 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4047 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4049 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4050 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4055 add_got_offset (int dest
, expressionS
*local
)
4059 global
.X_op
= O_constant
;
4060 global
.X_op_symbol
= NULL
;
4061 global
.X_add_symbol
= NULL
;
4062 global
.X_add_number
= local
->X_add_number
;
4064 relax_start (local
->X_add_symbol
);
4065 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4066 dest
, dest
, BFD_RELOC_LO16
);
4068 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4073 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4076 int hold_mips_optimize
;
4078 global
.X_op
= O_constant
;
4079 global
.X_op_symbol
= NULL
;
4080 global
.X_add_symbol
= NULL
;
4081 global
.X_add_number
= local
->X_add_number
;
4083 relax_start (local
->X_add_symbol
);
4084 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4086 /* Set mips_optimize around the lui instruction to avoid
4087 inserting an unnecessary nop after the lw. */
4088 hold_mips_optimize
= mips_optimize
;
4090 macro_build_lui (&global
, tmp
);
4091 mips_optimize
= hold_mips_optimize
;
4092 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4095 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4100 * This routine implements the seemingly endless macro or synthesized
4101 * instructions and addressing modes in the mips assembly language. Many
4102 * of these macros are simple and are similar to each other. These could
4103 * probably be handled by some kind of table or grammar approach instead of
4104 * this verbose method. Others are not simple macros but are more like
4105 * optimizing code generation.
4106 * One interesting optimization is when several store macros appear
4107 * consecutively that would load AT with the upper half of the same address.
4108 * The ensuing load upper instructions are ommited. This implies some kind
4109 * of global optimization. We currently only optimize within a single macro.
4110 * For many of the load and store macros if the address is specified as a
4111 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4112 * first load register 'at' with zero and use it as the base register. The
4113 * mips assembler simply uses register $zero. Just one tiny optimization
4117 macro (struct mips_cl_insn
*ip
)
4119 register int treg
, sreg
, dreg
, breg
;
4135 bfd_reloc_code_real_type r
;
4136 int hold_mips_optimize
;
4138 assert (! mips_opts
.mips16
);
4140 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4141 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4142 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4143 mask
= ip
->insn_mo
->mask
;
4145 expr1
.X_op
= O_constant
;
4146 expr1
.X_op_symbol
= NULL
;
4147 expr1
.X_add_symbol
= NULL
;
4148 expr1
.X_add_number
= 1;
4160 mips_emit_delays (TRUE
);
4161 ++mips_opts
.noreorder
;
4162 mips_any_noreorder
= 1;
4164 expr1
.X_add_number
= 8;
4165 macro_build (&expr1
, "bgez", "s,p", sreg
);
4167 macro_build (NULL
, "nop", "", 0);
4169 move_register (dreg
, sreg
);
4170 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4172 --mips_opts
.noreorder
;
4193 if (imm_expr
.X_op
== O_constant
4194 && imm_expr
.X_add_number
>= -0x8000
4195 && imm_expr
.X_add_number
< 0x8000)
4197 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4200 load_register (AT
, &imm_expr
, dbl
);
4201 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4220 if (imm_expr
.X_op
== O_constant
4221 && imm_expr
.X_add_number
>= 0
4222 && imm_expr
.X_add_number
< 0x10000)
4224 if (mask
!= M_NOR_I
)
4225 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4228 macro_build (&imm_expr
, "ori", "t,r,i",
4229 treg
, sreg
, BFD_RELOC_LO16
);
4230 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4235 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4236 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4253 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4255 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4258 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4259 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4267 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4272 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4275 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4276 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4282 /* check for > max integer */
4283 maxnum
= 0x7fffffff;
4284 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4291 if (imm_expr
.X_op
== O_constant
4292 && imm_expr
.X_add_number
>= maxnum
4293 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4296 /* result is always false */
4298 macro_build (NULL
, "nop", "", 0);
4300 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4303 if (imm_expr
.X_op
!= O_constant
)
4304 as_bad (_("Unsupported large constant"));
4305 ++imm_expr
.X_add_number
;
4309 if (mask
== M_BGEL_I
)
4311 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4313 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4316 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4318 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4321 maxnum
= 0x7fffffff;
4322 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4329 maxnum
= - maxnum
- 1;
4330 if (imm_expr
.X_op
== O_constant
4331 && imm_expr
.X_add_number
<= maxnum
4332 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4335 /* result is always true */
4336 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4337 macro_build (&offset_expr
, "b", "p");
4341 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4351 macro_build (&offset_expr
, likely
? "beql" : "beq",
4355 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4356 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4364 && imm_expr
.X_op
== O_constant
4365 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4367 if (imm_expr
.X_op
!= O_constant
)
4368 as_bad (_("Unsupported large constant"));
4369 ++imm_expr
.X_add_number
;
4373 if (mask
== M_BGEUL_I
)
4375 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4377 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4379 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4384 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4392 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4397 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4400 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4401 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4409 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4415 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4416 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4424 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4429 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4432 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4433 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4439 maxnum
= 0x7fffffff;
4440 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4447 if (imm_expr
.X_op
== O_constant
4448 && imm_expr
.X_add_number
>= maxnum
4449 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4451 if (imm_expr
.X_op
!= O_constant
)
4452 as_bad (_("Unsupported large constant"));
4453 ++imm_expr
.X_add_number
;
4457 if (mask
== M_BLTL_I
)
4459 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4461 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4464 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4466 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4470 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4478 macro_build (&offset_expr
, likely
? "beql" : "beq",
4484 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4485 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4493 && imm_expr
.X_op
== O_constant
4494 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4496 if (imm_expr
.X_op
!= O_constant
)
4497 as_bad (_("Unsupported large constant"));
4498 ++imm_expr
.X_add_number
;
4502 if (mask
== M_BLTUL_I
)
4504 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4506 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4508 macro_build (&offset_expr
, likely
? "beql" : "beq",
4513 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4521 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4526 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4529 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4530 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4540 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4544 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4545 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4553 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4555 as_bad (_("Unsupported large constant"));
4560 pos
= (unsigned long) imm_expr
.X_add_number
;
4561 size
= (unsigned long) imm2_expr
.X_add_number
;
4566 as_bad (_("Improper position (%lu)"), pos
);
4569 if (size
== 0 || size
> 64
4570 || (pos
+ size
- 1) > 63)
4572 as_bad (_("Improper extract size (%lu, position %lu)"),
4577 if (size
<= 32 && pos
< 32)
4582 else if (size
<= 32)
4592 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4601 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4603 as_bad (_("Unsupported large constant"));
4608 pos
= (unsigned long) imm_expr
.X_add_number
;
4609 size
= (unsigned long) imm2_expr
.X_add_number
;
4614 as_bad (_("Improper position (%lu)"), pos
);
4617 if (size
== 0 || size
> 64
4618 || (pos
+ size
- 1) > 63)
4620 as_bad (_("Improper insert size (%lu, position %lu)"),
4625 if (pos
< 32 && (pos
+ size
- 1) < 32)
4640 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4657 as_warn (_("Divide by zero."));
4659 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4661 macro_build (NULL
, "break", "c", 7);
4665 mips_emit_delays (TRUE
);
4666 ++mips_opts
.noreorder
;
4667 mips_any_noreorder
= 1;
4670 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4671 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4675 expr1
.X_add_number
= 8;
4676 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4677 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4678 macro_build (NULL
, "break", "c", 7);
4680 expr1
.X_add_number
= -1;
4681 load_register (AT
, &expr1
, dbl
);
4682 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4683 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4686 expr1
.X_add_number
= 1;
4687 load_register (AT
, &expr1
, dbl
);
4688 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4692 expr1
.X_add_number
= 0x80000000;
4693 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4697 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4698 /* We want to close the noreorder block as soon as possible, so
4699 that later insns are available for delay slot filling. */
4700 --mips_opts
.noreorder
;
4704 expr1
.X_add_number
= 8;
4705 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4706 macro_build (NULL
, "nop", "", 0);
4708 /* We want to close the noreorder block as soon as possible, so
4709 that later insns are available for delay slot filling. */
4710 --mips_opts
.noreorder
;
4712 macro_build (NULL
, "break", "c", 6);
4714 macro_build (NULL
, s
, "d", dreg
);
4753 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4755 as_warn (_("Divide by zero."));
4757 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4759 macro_build (NULL
, "break", "c", 7);
4762 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4764 if (strcmp (s2
, "mflo") == 0)
4765 move_register (dreg
, sreg
);
4767 move_register (dreg
, 0);
4770 if (imm_expr
.X_op
== O_constant
4771 && imm_expr
.X_add_number
== -1
4772 && s
[strlen (s
) - 1] != 'u')
4774 if (strcmp (s2
, "mflo") == 0)
4776 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4779 move_register (dreg
, 0);
4783 load_register (AT
, &imm_expr
, dbl
);
4784 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4785 macro_build (NULL
, s2
, "d", dreg
);
4804 mips_emit_delays (TRUE
);
4805 ++mips_opts
.noreorder
;
4806 mips_any_noreorder
= 1;
4809 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4810 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4811 /* We want to close the noreorder block as soon as possible, so
4812 that later insns are available for delay slot filling. */
4813 --mips_opts
.noreorder
;
4817 expr1
.X_add_number
= 8;
4818 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4819 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4821 /* We want to close the noreorder block as soon as possible, so
4822 that later insns are available for delay slot filling. */
4823 --mips_opts
.noreorder
;
4824 macro_build (NULL
, "break", "c", 7);
4826 macro_build (NULL
, s2
, "d", dreg
);
4838 /* Load the address of a symbol into a register. If breg is not
4839 zero, we then add a base register to it. */
4841 if (dbl
&& HAVE_32BIT_GPRS
)
4842 as_warn (_("dla used to load 32-bit register"));
4844 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4845 as_warn (_("la used to load 64-bit address"));
4847 if (offset_expr
.X_op
== O_constant
4848 && offset_expr
.X_add_number
>= -0x8000
4849 && offset_expr
.X_add_number
< 0x8000)
4851 macro_build (&offset_expr
,
4852 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4853 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4868 if (offset_expr
.X_op
!= O_symbol
4869 && offset_expr
.X_op
!= O_constant
)
4871 as_bad (_("expression too complex"));
4872 offset_expr
.X_op
= O_constant
;
4875 if (offset_expr
.X_op
== O_constant
)
4876 load_register (tempreg
, &offset_expr
,
4878 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4879 : HAVE_64BIT_ADDRESSES
));
4880 else if (mips_pic
== NO_PIC
)
4882 /* If this is a reference to a GP relative symbol, we want
4883 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4885 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4886 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4887 If we have a constant, we need two instructions anyhow,
4888 so we may as well always use the latter form.
4890 With 64bit address space and a usable $at we want
4891 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4892 lui $at,<sym> (BFD_RELOC_HI16_S)
4893 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4894 daddiu $at,<sym> (BFD_RELOC_LO16)
4896 daddu $tempreg,$tempreg,$at
4898 If $at is already in use, we use a path which is suboptimal
4899 on superscalar processors.
4900 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4901 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4903 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4905 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4907 if (HAVE_64BIT_ADDRESSES
)
4909 /* ??? We don't provide a GP-relative alternative for
4910 these macros. It used not to be possible with the
4911 original relaxation code, but it could be done now. */
4913 if (used_at
== 0 && ! mips_opts
.noat
)
4915 macro_build (&offset_expr
, "lui", "t,u",
4916 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4917 macro_build (&offset_expr
, "lui", "t,u",
4918 AT
, BFD_RELOC_HI16_S
);
4919 macro_build (&offset_expr
, "daddiu", "t,r,j",
4920 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4921 macro_build (&offset_expr
, "daddiu", "t,r,j",
4922 AT
, AT
, BFD_RELOC_LO16
);
4923 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4924 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4929 macro_build (&offset_expr
, "lui", "t,u",
4930 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4931 macro_build (&offset_expr
, "daddiu", "t,r,j",
4932 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4933 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4934 macro_build (&offset_expr
, "daddiu", "t,r,j",
4935 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4936 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4937 macro_build (&offset_expr
, "daddiu", "t,r,j",
4938 tempreg
, tempreg
, BFD_RELOC_LO16
);
4943 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4944 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4946 relax_start (offset_expr
.X_add_symbol
);
4947 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4948 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4951 macro_build_lui (&offset_expr
, tempreg
);
4952 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4953 tempreg
, tempreg
, BFD_RELOC_LO16
);
4954 if (mips_relax
.sequence
)
4958 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4960 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4962 /* If this is a reference to an external symbol, and there
4963 is no constant, we want
4964 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4965 or for lca or if tempreg is PIC_CALL_REG
4966 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4967 For a local symbol, we want
4968 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4970 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4972 If we have a small constant, and this is a reference to
4973 an external symbol, we want
4974 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4976 addiu $tempreg,$tempreg,<constant>
4977 For a local symbol, we want the same instruction
4978 sequence, but we output a BFD_RELOC_LO16 reloc on the
4981 If we have a large constant, and this is a reference to
4982 an external symbol, we want
4983 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4984 lui $at,<hiconstant>
4985 addiu $at,$at,<loconstant>
4986 addu $tempreg,$tempreg,$at
4987 For a local symbol, we want the same instruction
4988 sequence, but we output a BFD_RELOC_LO16 reloc on the
4992 if (offset_expr
.X_add_number
== 0)
4994 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
4995 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4997 relax_start (offset_expr
.X_add_symbol
);
4998 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
4999 lw_reloc_type
, mips_gp_register
);
5002 /* We're going to put in an addu instruction using
5003 tempreg, so we may as well insert the nop right
5008 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5009 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5011 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5012 tempreg
, tempreg
, BFD_RELOC_LO16
);
5014 /* FIXME: If breg == 0, and the next instruction uses
5015 $tempreg, then if this variant case is used an extra
5016 nop will be generated. */
5018 else if (offset_expr
.X_add_number
>= -0x8000
5019 && offset_expr
.X_add_number
< 0x8000)
5021 load_got_offset (tempreg
, &offset_expr
);
5023 add_got_offset (tempreg
, &offset_expr
);
5027 expr1
.X_add_number
= offset_expr
.X_add_number
;
5028 offset_expr
.X_add_number
=
5029 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5030 load_got_offset (tempreg
, &offset_expr
);
5031 offset_expr
.X_add_number
= expr1
.X_add_number
;
5032 /* If we are going to add in a base register, and the
5033 target register and the base register are the same,
5034 then we are using AT as a temporary register. Since
5035 we want to load the constant into AT, we add our
5036 current AT (from the global offset table) and the
5037 register into the register now, and pretend we were
5038 not using a base register. */
5042 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5047 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5051 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5053 int add_breg_early
= 0;
5055 /* If this is a reference to an external, and there is no
5056 constant, or local symbol (*), with or without a
5058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5059 or for lca or if tempreg is PIC_CALL_REG
5060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5062 If we have a small constant, and this is a reference to
5063 an external symbol, we want
5064 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5065 addiu $tempreg,$tempreg,<constant>
5067 If we have a large constant, and this is a reference to
5068 an external symbol, we want
5069 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5070 lui $at,<hiconstant>
5071 addiu $at,$at,<loconstant>
5072 addu $tempreg,$tempreg,$at
5074 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5075 local symbols, even though it introduces an additional
5078 if (offset_expr
.X_add_number
)
5080 expr1
.X_add_number
= offset_expr
.X_add_number
;
5081 offset_expr
.X_add_number
= 0;
5083 relax_start (offset_expr
.X_add_symbol
);
5084 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5085 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5087 if (expr1
.X_add_number
>= -0x8000
5088 && expr1
.X_add_number
< 0x8000)
5090 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5091 tempreg
, tempreg
, BFD_RELOC_LO16
);
5093 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5097 /* If we are going to add in a base register, and the
5098 target register and the base register are the same,
5099 then we are using AT as a temporary register. Since
5100 we want to load the constant into AT, we add our
5101 current AT (from the global offset table) and the
5102 register into the register now, and pretend we were
5103 not using a base register. */
5108 assert (tempreg
== AT
);
5109 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5115 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5116 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5122 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5125 offset_expr
.X_add_number
= expr1
.X_add_number
;
5127 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5128 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5131 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5132 treg
, tempreg
, breg
);
5138 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5140 relax_start (offset_expr
.X_add_symbol
);
5141 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5142 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5144 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5145 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5150 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5151 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5154 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5157 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5158 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5159 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5161 /* This is the large GOT case. If this is a reference to an
5162 external symbol, and there is no constant, we want
5163 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5164 addu $tempreg,$tempreg,$gp
5165 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5166 or for lca or if tempreg is PIC_CALL_REG
5167 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5168 addu $tempreg,$tempreg,$gp
5169 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5170 For a local symbol, we want
5171 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5173 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5175 If we have a small constant, and this is a reference to
5176 an external symbol, we want
5177 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5178 addu $tempreg,$tempreg,$gp
5179 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5181 addiu $tempreg,$tempreg,<constant>
5182 For a local symbol, we want
5183 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5185 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5187 If we have a large constant, and this is a reference to
5188 an external symbol, we want
5189 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5190 addu $tempreg,$tempreg,$gp
5191 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5192 lui $at,<hiconstant>
5193 addiu $at,$at,<loconstant>
5194 addu $tempreg,$tempreg,$at
5195 For a local symbol, we want
5196 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5197 lui $at,<hiconstant>
5198 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5199 addu $tempreg,$tempreg,$at
5202 expr1
.X_add_number
= offset_expr
.X_add_number
;
5203 offset_expr
.X_add_number
= 0;
5204 relax_start (offset_expr
.X_add_symbol
);
5205 gpdelay
= reg_needs_delay (mips_gp_register
);
5206 if (expr1
.X_add_number
== 0 && breg
== 0
5207 && (call
|| tempreg
== PIC_CALL_REG
))
5209 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5210 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5212 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5213 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5214 tempreg
, tempreg
, mips_gp_register
);
5215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5216 tempreg
, lw_reloc_type
, tempreg
);
5217 if (expr1
.X_add_number
== 0)
5221 /* We're going to put in an addu instruction using
5222 tempreg, so we may as well insert the nop right
5227 else if (expr1
.X_add_number
>= -0x8000
5228 && expr1
.X_add_number
< 0x8000)
5231 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5232 tempreg
, tempreg
, BFD_RELOC_LO16
);
5238 /* If we are going to add in a base register, and the
5239 target register and the base register are the same,
5240 then we are using AT as a temporary register. Since
5241 we want to load the constant into AT, we add our
5242 current AT (from the global offset table) and the
5243 register into the register now, and pretend we were
5244 not using a base register. */
5249 assert (tempreg
== AT
);
5251 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5256 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5257 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5261 offset_expr
.X_add_number
=
5262 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5267 /* This is needed because this instruction uses $gp, but
5268 the first instruction on the main stream does not. */
5269 macro_build (NULL
, "nop", "");
5272 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5273 local_reloc_type
, mips_gp_register
);
5274 if (expr1
.X_add_number
>= -0x8000
5275 && expr1
.X_add_number
< 0x8000)
5278 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5279 tempreg
, tempreg
, BFD_RELOC_LO16
);
5280 /* FIXME: If add_number is 0, and there was no base
5281 register, the external symbol case ended with a load,
5282 so if the symbol turns out to not be external, and
5283 the next instruction uses tempreg, an unnecessary nop
5284 will be inserted. */
5290 /* We must add in the base register now, as in the
5291 external symbol case. */
5292 assert (tempreg
== AT
);
5294 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5297 /* We set breg to 0 because we have arranged to add
5298 it in in both cases. */
5302 macro_build_lui (&expr1
, AT
);
5303 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5304 AT
, AT
, BFD_RELOC_LO16
);
5305 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5306 tempreg
, tempreg
, AT
);
5310 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5312 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5313 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5314 int add_breg_early
= 0;
5316 /* This is the large GOT case. If this is a reference to an
5317 external symbol, and there is no constant, we want
5318 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5319 add $tempreg,$tempreg,$gp
5320 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5321 or for lca or if tempreg is PIC_CALL_REG
5322 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5323 add $tempreg,$tempreg,$gp
5324 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5326 If we have a small constant, and this is a reference to
5327 an external symbol, we want
5328 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5329 add $tempreg,$tempreg,$gp
5330 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5331 addi $tempreg,$tempreg,<constant>
5333 If we have a large constant, and this is a reference to
5334 an external symbol, we want
5335 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5336 addu $tempreg,$tempreg,$gp
5337 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5338 lui $at,<hiconstant>
5339 addi $at,$at,<loconstant>
5340 add $tempreg,$tempreg,$at
5342 If we have NewABI, and we know it's a local symbol, we want
5343 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5344 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5345 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5347 relax_start (offset_expr
.X_add_symbol
);
5349 expr1
.X_add_number
= offset_expr
.X_add_number
;
5350 offset_expr
.X_add_number
= 0;
5352 if (expr1
.X_add_number
== 0 && breg
== 0
5353 && (call
|| tempreg
== PIC_CALL_REG
))
5355 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5356 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5358 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5359 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5360 tempreg
, tempreg
, mips_gp_register
);
5361 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5362 tempreg
, lw_reloc_type
, tempreg
);
5364 if (expr1
.X_add_number
== 0)
5366 else if (expr1
.X_add_number
>= -0x8000
5367 && expr1
.X_add_number
< 0x8000)
5369 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5370 tempreg
, tempreg
, BFD_RELOC_LO16
);
5372 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5376 /* If we are going to add in a base register, and the
5377 target register and the base register are the same,
5378 then we are using AT as a temporary register. Since
5379 we want to load the constant into AT, we add our
5380 current AT (from the global offset table) and the
5381 register into the register now, and pretend we were
5382 not using a base register. */
5387 assert (tempreg
== AT
);
5388 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5394 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5395 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5400 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5403 offset_expr
.X_add_number
= expr1
.X_add_number
;
5404 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5405 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5406 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5407 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5410 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5411 treg
, tempreg
, breg
);
5424 if (mips_pic
== NO_PIC
)
5425 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5427 s
= ADDRESS_ADD_INSN
;
5429 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5438 /* The j instruction may not be used in PIC code, since it
5439 requires an absolute address. We convert it to a b
5441 if (mips_pic
== NO_PIC
)
5442 macro_build (&offset_expr
, "j", "a");
5444 macro_build (&offset_expr
, "b", "p");
5447 /* The jal instructions must be handled as macros because when
5448 generating PIC code they expand to multi-instruction
5449 sequences. Normally they are simple instructions. */
5454 if (mips_pic
== NO_PIC
)
5455 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5456 else if (mips_pic
== SVR4_PIC
)
5458 if (sreg
!= PIC_CALL_REG
)
5459 as_warn (_("MIPS PIC call to register other than $25"));
5461 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5464 if (mips_cprestore_offset
< 0)
5465 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5468 if (! mips_frame_reg_valid
)
5470 as_warn (_("No .frame pseudo-op used in PIC code"));
5471 /* Quiet this warning. */
5472 mips_frame_reg_valid
= 1;
5474 if (! mips_cprestore_valid
)
5476 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5477 /* Quiet this warning. */
5478 mips_cprestore_valid
= 1;
5480 expr1
.X_add_number
= mips_cprestore_offset
;
5481 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5484 HAVE_64BIT_ADDRESSES
);
5494 if (mips_pic
== NO_PIC
)
5495 macro_build (&offset_expr
, "jal", "a");
5496 else if (mips_pic
== SVR4_PIC
)
5498 /* If this is a reference to an external symbol, and we are
5499 using a small GOT, we want
5500 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5504 lw $gp,cprestore($sp)
5505 The cprestore value is set using the .cprestore
5506 pseudo-op. If we are using a big GOT, we want
5507 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5509 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5513 lw $gp,cprestore($sp)
5514 If the symbol is not external, we want
5515 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5517 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5520 lw $gp,cprestore($sp)
5522 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5523 sequences above, minus nops, unless the symbol is local,
5524 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5530 relax_start (offset_expr
.X_add_symbol
);
5531 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5532 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5535 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5536 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5542 relax_start (offset_expr
.X_add_symbol
);
5543 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5544 BFD_RELOC_MIPS_CALL_HI16
);
5545 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5546 PIC_CALL_REG
, mips_gp_register
);
5547 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5548 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5551 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5552 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5554 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5555 PIC_CALL_REG
, PIC_CALL_REG
,
5556 BFD_RELOC_MIPS_GOT_OFST
);
5560 macro_build_jalr (&offset_expr
);
5564 relax_start (offset_expr
.X_add_symbol
);
5567 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5568 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5577 gpdelay
= reg_needs_delay (mips_gp_register
);
5578 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5579 BFD_RELOC_MIPS_CALL_HI16
);
5580 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5581 PIC_CALL_REG
, mips_gp_register
);
5582 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5583 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5588 macro_build (NULL
, "nop", "");
5590 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5591 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5594 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5595 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5597 macro_build_jalr (&offset_expr
);
5599 if (mips_cprestore_offset
< 0)
5600 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5603 if (! mips_frame_reg_valid
)
5605 as_warn (_("No .frame pseudo-op used in PIC code"));
5606 /* Quiet this warning. */
5607 mips_frame_reg_valid
= 1;
5609 if (! mips_cprestore_valid
)
5611 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5612 /* Quiet this warning. */
5613 mips_cprestore_valid
= 1;
5615 if (mips_opts
.noreorder
)
5616 macro_build (NULL
, "nop", "");
5617 expr1
.X_add_number
= mips_cprestore_offset
;
5618 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5621 HAVE_64BIT_ADDRESSES
);
5647 /* Itbl support may require additional care here. */
5652 /* Itbl support may require additional care here. */
5657 /* Itbl support may require additional care here. */
5662 /* Itbl support may require additional care here. */
5674 if (mips_opts
.arch
== CPU_R4650
)
5676 as_bad (_("opcode not supported on this processor"));
5680 /* Itbl support may require additional care here. */
5685 /* Itbl support may require additional care here. */
5690 /* Itbl support may require additional care here. */
5710 if (breg
== treg
|| coproc
|| lr
)
5732 /* Itbl support may require additional care here. */
5737 /* Itbl support may require additional care here. */
5742 /* Itbl support may require additional care here. */
5747 /* Itbl support may require additional care here. */
5763 if (mips_opts
.arch
== CPU_R4650
)
5765 as_bad (_("opcode not supported on this processor"));
5770 /* Itbl support may require additional care here. */
5774 /* Itbl support may require additional care here. */
5779 /* Itbl support may require additional care here. */
5791 /* Itbl support may require additional care here. */
5792 if (mask
== M_LWC1_AB
5793 || mask
== M_SWC1_AB
5794 || mask
== M_LDC1_AB
5795 || mask
== M_SDC1_AB
5804 /* Sign-extending 32-bit constants makes their handling easier.
5805 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5807 if ((! HAVE_64BIT_ADDRESSES
5808 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5809 && (offset_expr
.X_op
== O_constant
)
5810 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5811 == ~((bfd_vma
) 0x7fffffff)))
5813 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5814 as_bad (_("constant too large"));
5816 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5817 ^ 0x80000000) - 0x80000000);
5820 if (offset_expr
.X_op
!= O_constant
5821 && offset_expr
.X_op
!= O_symbol
)
5823 as_bad (_("expression too complex"));
5824 offset_expr
.X_op
= O_constant
;
5827 /* A constant expression in PIC code can be handled just as it
5828 is in non PIC code. */
5829 if (mips_pic
== NO_PIC
5830 || offset_expr
.X_op
== O_constant
)
5832 /* If this is a reference to a GP relative symbol, and there
5833 is no base register, we want
5834 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5835 Otherwise, if there is no base register, we want
5836 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5837 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5838 If we have a constant, we need two instructions anyhow,
5839 so we always use the latter form.
5841 If we have a base register, and this is a reference to a
5842 GP relative symbol, we want
5843 addu $tempreg,$breg,$gp
5844 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5846 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5847 addu $tempreg,$tempreg,$breg
5848 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5849 With a constant we always use the latter case.
5851 With 64bit address space and no base register and $at usable,
5853 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5854 lui $at,<sym> (BFD_RELOC_HI16_S)
5855 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5858 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5859 If we have a base register, we want
5860 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5861 lui $at,<sym> (BFD_RELOC_HI16_S)
5862 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5866 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5868 Without $at we can't generate the optimal path for superscalar
5869 processors here since this would require two temporary registers.
5870 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5871 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5873 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5875 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5876 If we have a base register, we want
5877 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5878 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5880 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5882 daddu $tempreg,$tempreg,$breg
5883 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5885 If we have 64-bit addresses, as an optimization, for
5886 addresses which are 32-bit constants (e.g. kseg0/kseg1
5887 addresses) we fall back to the 32-bit address generation
5888 mechanism since it is more efficient. Note that due to
5889 the signed offset used by memory operations, the 32-bit
5890 range is shifted down by 32768 here. This code should
5891 probably attempt to generate 64-bit constants more
5892 efficiently in general.
5894 As an extension for architectures with 64-bit registers,
5895 we don't truncate 64-bit addresses given as literal
5896 constants down to 32 bits, to support existing practice
5897 in the mips64 Linux (the kernel), that compiles source
5898 files with -mabi=64, assembling them as o32 or n32 (with
5899 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5900 the whole kernel is loaded into a memory region that is
5901 addressable with sign-extended 32-bit addresses, it is
5902 wasteful to compute the upper 32 bits of every
5903 non-literal address, that takes more space and time.
5904 Some day this should probably be implemented as an
5905 assembler option, such that the kernel doesn't have to
5906 use such ugly hacks, even though it will still have to
5907 end up converting the binary to ELF32 for a number of
5908 platforms whose boot loaders don't support ELF64
5910 if ((HAVE_64BIT_ADDRESSES
5911 && ! (offset_expr
.X_op
== O_constant
5912 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5914 && offset_expr
.X_op
== O_constant
5915 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5917 /* ??? We don't provide a GP-relative alternative for
5918 these macros. It used not to be possible with the
5919 original relaxation code, but it could be done now. */
5921 if (used_at
== 0 && ! mips_opts
.noat
)
5923 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5924 BFD_RELOC_MIPS_HIGHEST
);
5925 macro_build (&offset_expr
, "lui", "t,u", AT
,
5927 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5928 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5930 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5931 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5932 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5933 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5939 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5940 BFD_RELOC_MIPS_HIGHEST
);
5941 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5942 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5943 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5944 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5945 tempreg
, BFD_RELOC_HI16_S
);
5946 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5948 macro_build (NULL
, "daddu", "d,v,t",
5949 tempreg
, tempreg
, breg
);
5950 macro_build (&offset_expr
, s
, fmt
, treg
,
5951 BFD_RELOC_LO16
, tempreg
);
5957 if (offset_expr
.X_op
== O_constant
5958 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
5959 as_bad (_("load/store address overflow (max 32 bits)"));
5963 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5964 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5966 relax_start (offset_expr
.X_add_symbol
);
5967 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5972 macro_build_lui (&offset_expr
, tempreg
);
5973 macro_build (&offset_expr
, s
, fmt
, treg
,
5974 BFD_RELOC_LO16
, tempreg
);
5975 if (mips_relax
.sequence
)
5980 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5981 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5983 relax_start (offset_expr
.X_add_symbol
);
5984 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5985 tempreg
, breg
, mips_gp_register
);
5986 macro_build (&offset_expr
, s
, fmt
, treg
,
5987 BFD_RELOC_GPREL16
, tempreg
);
5990 macro_build_lui (&offset_expr
, tempreg
);
5991 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5992 tempreg
, tempreg
, breg
);
5993 macro_build (&offset_expr
, s
, fmt
, treg
,
5994 BFD_RELOC_LO16
, tempreg
);
5995 if (mips_relax
.sequence
)
5999 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6001 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6003 /* If this is a reference to an external symbol, we want
6004 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6006 <op> $treg,0($tempreg)
6008 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6010 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6011 <op> $treg,0($tempreg)
6014 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6015 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6017 If there is a base register, we add it to $tempreg before
6018 the <op>. If there is a constant, we stick it in the
6019 <op> instruction. We don't handle constants larger than
6020 16 bits, because we have no way to load the upper 16 bits
6021 (actually, we could handle them for the subset of cases
6022 in which we are not using $at). */
6023 assert (offset_expr
.X_op
== O_symbol
);
6026 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6027 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6029 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6030 tempreg
, tempreg
, breg
);
6031 macro_build (&offset_expr
, s
, fmt
, treg
,
6032 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6039 expr1
.X_add_number
= offset_expr
.X_add_number
;
6040 offset_expr
.X_add_number
= 0;
6041 if (expr1
.X_add_number
< -0x8000
6042 || expr1
.X_add_number
>= 0x8000)
6043 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6044 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6045 lw_reloc_type
, mips_gp_register
);
6047 relax_start (offset_expr
.X_add_symbol
);
6049 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6050 tempreg
, BFD_RELOC_LO16
);
6053 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6054 tempreg
, tempreg
, breg
);
6055 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6057 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6061 /* If this is a reference to an external symbol, we want
6062 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6063 addu $tempreg,$tempreg,$gp
6064 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6065 <op> $treg,0($tempreg)
6067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6069 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6070 <op> $treg,0($tempreg)
6071 If there is a base register, we add it to $tempreg before
6072 the <op>. If there is a constant, we stick it in the
6073 <op> instruction. We don't handle constants larger than
6074 16 bits, because we have no way to load the upper 16 bits
6075 (actually, we could handle them for the subset of cases
6076 in which we are not using $at). */
6077 assert (offset_expr
.X_op
== O_symbol
);
6078 expr1
.X_add_number
= offset_expr
.X_add_number
;
6079 offset_expr
.X_add_number
= 0;
6080 if (expr1
.X_add_number
< -0x8000
6081 || expr1
.X_add_number
>= 0x8000)
6082 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6083 gpdelay
= reg_needs_delay (mips_gp_register
);
6084 relax_start (offset_expr
.X_add_symbol
);
6085 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6086 BFD_RELOC_MIPS_GOT_HI16
);
6087 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6089 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6090 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6093 macro_build (NULL
, "nop", "");
6094 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6095 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6097 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6098 tempreg
, BFD_RELOC_LO16
);
6102 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6103 tempreg
, tempreg
, breg
);
6104 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6106 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6108 /* If this is a reference to an external symbol, we want
6109 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6110 add $tempreg,$tempreg,$gp
6111 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6112 <op> $treg,<ofst>($tempreg)
6113 Otherwise, for local symbols, we want:
6114 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6115 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6116 assert (offset_expr
.X_op
== O_symbol
);
6117 expr1
.X_add_number
= offset_expr
.X_add_number
;
6118 offset_expr
.X_add_number
= 0;
6119 if (expr1
.X_add_number
< -0x8000
6120 || expr1
.X_add_number
>= 0x8000)
6121 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6122 relax_start (offset_expr
.X_add_symbol
);
6123 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6124 BFD_RELOC_MIPS_GOT_HI16
);
6125 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6127 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6128 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6131 tempreg
, tempreg
, breg
);
6132 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6135 offset_expr
.X_add_number
= expr1
.X_add_number
;
6136 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6137 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6140 tempreg
, tempreg
, breg
);
6141 macro_build (&offset_expr
, s
, fmt
, treg
,
6142 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6155 load_register (treg
, &imm_expr
, 0);
6159 load_register (treg
, &imm_expr
, 1);
6163 if (imm_expr
.X_op
== O_constant
)
6165 load_register (AT
, &imm_expr
, 0);
6166 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6171 assert (offset_expr
.X_op
== O_symbol
6172 && strcmp (segment_name (S_GET_SEGMENT
6173 (offset_expr
.X_add_symbol
)),
6175 && offset_expr
.X_add_number
== 0);
6176 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6177 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6182 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6183 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6184 order 32 bits of the value and the low order 32 bits are either
6185 zero or in OFFSET_EXPR. */
6186 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6188 if (HAVE_64BIT_GPRS
)
6189 load_register (treg
, &imm_expr
, 1);
6194 if (target_big_endian
)
6206 load_register (hreg
, &imm_expr
, 0);
6209 if (offset_expr
.X_op
== O_absent
)
6210 move_register (lreg
, 0);
6213 assert (offset_expr
.X_op
== O_constant
);
6214 load_register (lreg
, &offset_expr
, 0);
6221 /* We know that sym is in the .rdata section. First we get the
6222 upper 16 bits of the address. */
6223 if (mips_pic
== NO_PIC
)
6225 macro_build_lui (&offset_expr
, AT
);
6227 else if (mips_pic
== SVR4_PIC
)
6229 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6230 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6235 /* Now we load the register(s). */
6236 if (HAVE_64BIT_GPRS
)
6237 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6240 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6243 /* FIXME: How in the world do we deal with the possible
6245 offset_expr
.X_add_number
+= 4;
6246 macro_build (&offset_expr
, "lw", "t,o(b)",
6247 treg
+ 1, BFD_RELOC_LO16
, AT
);
6253 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6254 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6255 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6256 the value and the low order 32 bits are either zero or in
6258 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6260 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6261 if (HAVE_64BIT_FPRS
)
6263 assert (HAVE_64BIT_GPRS
);
6264 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6268 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6269 if (offset_expr
.X_op
== O_absent
)
6270 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6273 assert (offset_expr
.X_op
== O_constant
);
6274 load_register (AT
, &offset_expr
, 0);
6275 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6281 assert (offset_expr
.X_op
== O_symbol
6282 && offset_expr
.X_add_number
== 0);
6283 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6284 if (strcmp (s
, ".lit8") == 0)
6286 if (mips_opts
.isa
!= ISA_MIPS1
)
6288 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6289 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6292 breg
= mips_gp_register
;
6293 r
= BFD_RELOC_MIPS_LITERAL
;
6298 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6299 if (mips_pic
== SVR4_PIC
)
6300 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6301 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6304 /* FIXME: This won't work for a 64 bit address. */
6305 macro_build_lui (&offset_expr
, AT
);
6308 if (mips_opts
.isa
!= ISA_MIPS1
)
6310 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6311 treg
, BFD_RELOC_LO16
, AT
);
6320 if (mips_opts
.arch
== CPU_R4650
)
6322 as_bad (_("opcode not supported on this processor"));
6325 /* Even on a big endian machine $fn comes before $fn+1. We have
6326 to adjust when loading from memory. */
6329 assert (mips_opts
.isa
== ISA_MIPS1
);
6330 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6331 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6332 /* FIXME: A possible overflow which I don't know how to deal
6334 offset_expr
.X_add_number
+= 4;
6335 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6336 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6344 * The MIPS assembler seems to check for X_add_number not
6345 * being double aligned and generating:
6348 * addiu at,at,%lo(foo+1)
6351 * But, the resulting address is the same after relocation so why
6352 * generate the extra instruction?
6354 if (mips_opts
.arch
== CPU_R4650
)
6356 as_bad (_("opcode not supported on this processor"));
6359 /* Itbl support may require additional care here. */
6361 if (mips_opts
.isa
!= ISA_MIPS1
)
6372 if (mips_opts
.arch
== CPU_R4650
)
6374 as_bad (_("opcode not supported on this processor"));
6378 if (mips_opts
.isa
!= ISA_MIPS1
)
6386 /* Itbl support may require additional care here. */
6391 if (HAVE_64BIT_GPRS
)
6402 if (HAVE_64BIT_GPRS
)
6412 if (offset_expr
.X_op
!= O_symbol
6413 && offset_expr
.X_op
!= O_constant
)
6415 as_bad (_("expression too complex"));
6416 offset_expr
.X_op
= O_constant
;
6419 /* Even on a big endian machine $fn comes before $fn+1. We have
6420 to adjust when loading from memory. We set coproc if we must
6421 load $fn+1 first. */
6422 /* Itbl support may require additional care here. */
6423 if (! target_big_endian
)
6426 if (mips_pic
== NO_PIC
6427 || offset_expr
.X_op
== O_constant
)
6429 /* If this is a reference to a GP relative symbol, we want
6430 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6431 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6432 If we have a base register, we use this
6434 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6435 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6436 If this is not a GP relative symbol, we want
6437 lui $at,<sym> (BFD_RELOC_HI16_S)
6438 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6439 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6440 If there is a base register, we add it to $at after the
6441 lui instruction. If there is a constant, we always use
6443 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6444 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6448 relax_start (offset_expr
.X_add_symbol
);
6451 tempreg
= mips_gp_register
;
6456 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6457 AT
, breg
, mips_gp_register
);
6462 /* Itbl support may require additional care here. */
6463 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6464 BFD_RELOC_GPREL16
, tempreg
);
6465 offset_expr
.X_add_number
+= 4;
6467 /* Set mips_optimize to 2 to avoid inserting an
6469 hold_mips_optimize
= mips_optimize
;
6471 /* Itbl support may require additional care here. */
6472 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6473 BFD_RELOC_GPREL16
, tempreg
);
6474 mips_optimize
= hold_mips_optimize
;
6478 /* We just generated two relocs. When tc_gen_reloc
6479 handles this case, it will skip the first reloc and
6480 handle the second. The second reloc already has an
6481 extra addend of 4, which we added above. We must
6482 subtract it out, and then subtract another 4 to make
6483 the first reloc come out right. The second reloc
6484 will come out right because we are going to add 4 to
6485 offset_expr when we build its instruction below.
6487 If we have a symbol, then we don't want to include
6488 the offset, because it will wind up being included
6489 when we generate the reloc. */
6491 if (offset_expr
.X_op
== O_constant
)
6492 offset_expr
.X_add_number
-= 8;
6495 offset_expr
.X_add_number
= -4;
6496 offset_expr
.X_op
= O_constant
;
6499 macro_build_lui (&offset_expr
, AT
);
6501 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6502 /* Itbl support may require additional care here. */
6503 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6504 BFD_RELOC_LO16
, AT
);
6505 /* FIXME: How do we handle overflow here? */
6506 offset_expr
.X_add_number
+= 4;
6507 /* Itbl support may require additional care here. */
6508 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6509 BFD_RELOC_LO16
, AT
);
6510 if (mips_relax
.sequence
)
6513 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6515 /* If this is a reference to an external symbol, we want
6516 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6521 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6523 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6524 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6525 If there is a base register we add it to $at before the
6526 lwc1 instructions. If there is a constant we include it
6527 in the lwc1 instructions. */
6529 expr1
.X_add_number
= offset_expr
.X_add_number
;
6530 if (expr1
.X_add_number
< -0x8000
6531 || expr1
.X_add_number
>= 0x8000 - 4)
6532 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6533 load_got_offset (AT
, &offset_expr
);
6536 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6538 /* Set mips_optimize to 2 to avoid inserting an undesired
6540 hold_mips_optimize
= mips_optimize
;
6543 /* Itbl support may require additional care here. */
6544 relax_start (offset_expr
.X_add_symbol
);
6545 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6546 BFD_RELOC_LO16
, AT
);
6547 expr1
.X_add_number
+= 4;
6548 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6549 BFD_RELOC_LO16
, AT
);
6551 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6552 BFD_RELOC_LO16
, AT
);
6553 offset_expr
.X_add_number
+= 4;
6554 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6555 BFD_RELOC_LO16
, AT
);
6558 mips_optimize
= hold_mips_optimize
;
6560 else if (mips_pic
== SVR4_PIC
)
6564 /* If this is a reference to an external symbol, we want
6565 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6567 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6572 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6574 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6575 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6576 If there is a base register we add it to $at before the
6577 lwc1 instructions. If there is a constant we include it
6578 in the lwc1 instructions. */
6580 expr1
.X_add_number
= offset_expr
.X_add_number
;
6581 offset_expr
.X_add_number
= 0;
6582 if (expr1
.X_add_number
< -0x8000
6583 || expr1
.X_add_number
>= 0x8000 - 4)
6584 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6585 gpdelay
= reg_needs_delay (mips_gp_register
);
6586 relax_start (offset_expr
.X_add_symbol
);
6587 macro_build (&offset_expr
, "lui", "t,u",
6588 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6589 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6590 AT
, AT
, mips_gp_register
);
6591 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6592 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6595 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6596 /* Itbl support may require additional care here. */
6597 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6598 BFD_RELOC_LO16
, AT
);
6599 expr1
.X_add_number
+= 4;
6601 /* Set mips_optimize to 2 to avoid inserting an undesired
6603 hold_mips_optimize
= mips_optimize
;
6605 /* Itbl support may require additional care here. */
6606 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6607 BFD_RELOC_LO16
, AT
);
6608 mips_optimize
= hold_mips_optimize
;
6609 expr1
.X_add_number
-= 4;
6612 offset_expr
.X_add_number
= expr1
.X_add_number
;
6614 macro_build (NULL
, "nop", "");
6615 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6616 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6619 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6620 /* Itbl support may require additional care here. */
6621 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6622 BFD_RELOC_LO16
, AT
);
6623 offset_expr
.X_add_number
+= 4;
6625 /* Set mips_optimize to 2 to avoid inserting an undesired
6627 hold_mips_optimize
= mips_optimize
;
6629 /* Itbl support may require additional care here. */
6630 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6631 BFD_RELOC_LO16
, AT
);
6632 mips_optimize
= hold_mips_optimize
;
6649 assert (HAVE_32BIT_ADDRESSES
);
6650 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6651 offset_expr
.X_add_number
+= 4;
6652 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6655 /* New code added to support COPZ instructions.
6656 This code builds table entries out of the macros in mip_opcodes.
6657 R4000 uses interlocks to handle coproc delays.
6658 Other chips (like the R3000) require nops to be inserted for delays.
6660 FIXME: Currently, we require that the user handle delays.
6661 In order to fill delay slots for non-interlocked chips,
6662 we must have a way to specify delays based on the coprocessor.
6663 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6664 What are the side-effects of the cop instruction?
6665 What cache support might we have and what are its effects?
6666 Both coprocessor & memory require delays. how long???
6667 What registers are read/set/modified?
6669 If an itbl is provided to interpret cop instructions,
6670 this knowledge can be encoded in the itbl spec. */
6684 /* For now we just do C (same as Cz). The parameter will be
6685 stored in insn_opcode by mips_ip. */
6686 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6690 move_register (dreg
, sreg
);
6693 #ifdef LOSING_COMPILER
6695 /* Try and see if this is a new itbl instruction.
6696 This code builds table entries out of the macros in mip_opcodes.
6697 FIXME: For now we just assemble the expression and pass it's
6698 value along as a 32-bit immediate.
6699 We may want to have the assembler assemble this value,
6700 so that we gain the assembler's knowledge of delay slots,
6702 Would it be more efficient to use mask (id) here? */
6703 if (itbl_have_entries
6704 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6706 s
= ip
->insn_mo
->name
;
6708 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6709 macro_build (&immed_expr
, s
, "C");
6716 as_warn (_("Macro used $at after \".set noat\""));
6720 macro2 (struct mips_cl_insn
*ip
)
6722 register int treg
, sreg
, dreg
, breg
;
6737 bfd_reloc_code_real_type r
;
6739 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6740 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6741 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6742 mask
= ip
->insn_mo
->mask
;
6744 expr1
.X_op
= O_constant
;
6745 expr1
.X_op_symbol
= NULL
;
6746 expr1
.X_add_symbol
= NULL
;
6747 expr1
.X_add_number
= 1;
6751 #endif /* LOSING_COMPILER */
6756 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6757 macro_build (NULL
, "mflo", "d", dreg
);
6763 /* The MIPS assembler some times generates shifts and adds. I'm
6764 not trying to be that fancy. GCC should do this for us
6766 load_register (AT
, &imm_expr
, dbl
);
6767 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6768 macro_build (NULL
, "mflo", "d", dreg
);
6781 mips_emit_delays (TRUE
);
6782 ++mips_opts
.noreorder
;
6783 mips_any_noreorder
= 1;
6785 load_register (AT
, &imm_expr
, dbl
);
6786 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6787 macro_build (NULL
, "mflo", "d", dreg
);
6788 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6789 macro_build (NULL
, "mfhi", "d", AT
);
6791 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6794 expr1
.X_add_number
= 8;
6795 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6796 macro_build (NULL
, "nop", "", 0);
6797 macro_build (NULL
, "break", "c", 6);
6799 --mips_opts
.noreorder
;
6800 macro_build (NULL
, "mflo", "d", dreg
);
6813 mips_emit_delays (TRUE
);
6814 ++mips_opts
.noreorder
;
6815 mips_any_noreorder
= 1;
6817 load_register (AT
, &imm_expr
, dbl
);
6818 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6819 sreg
, imm
? AT
: treg
);
6820 macro_build (NULL
, "mfhi", "d", AT
);
6821 macro_build (NULL
, "mflo", "d", dreg
);
6823 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6826 expr1
.X_add_number
= 8;
6827 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6828 macro_build (NULL
, "nop", "", 0);
6829 macro_build (NULL
, "break", "c", 6);
6831 --mips_opts
.noreorder
;
6835 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6847 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6848 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6853 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6854 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6855 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6856 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6860 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6872 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6873 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6878 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6879 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6880 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6881 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6889 if (imm_expr
.X_op
!= O_constant
)
6890 as_bad (_("Improper rotate count"));
6891 rot
= imm_expr
.X_add_number
& 0x3f;
6892 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6894 rot
= (64 - rot
) & 0x3f;
6896 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6898 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6903 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6906 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6907 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6909 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6910 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6911 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6919 if (imm_expr
.X_op
!= O_constant
)
6920 as_bad (_("Improper rotate count"));
6921 rot
= imm_expr
.X_add_number
& 0x1f;
6922 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6924 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6929 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6932 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6933 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6934 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6939 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6941 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6944 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6945 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6946 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6947 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6951 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6953 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6956 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6957 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6958 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6959 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6967 if (imm_expr
.X_op
!= O_constant
)
6968 as_bad (_("Improper rotate count"));
6969 rot
= imm_expr
.X_add_number
& 0x3f;
6970 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6973 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6975 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6980 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6983 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6984 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6986 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6987 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6988 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6996 if (imm_expr
.X_op
!= O_constant
)
6997 as_bad (_("Improper rotate count"));
6998 rot
= imm_expr
.X_add_number
& 0x1f;
6999 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7001 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7006 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7009 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7010 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7011 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7016 if (mips_opts
.arch
== CPU_R4650
)
7018 as_bad (_("opcode not supported on this processor"));
7021 assert (mips_opts
.isa
== ISA_MIPS1
);
7022 /* Even on a big endian machine $fn comes before $fn+1. We have
7023 to adjust when storing to memory. */
7024 macro_build (&offset_expr
, "swc1", "T,o(b)",
7025 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7026 offset_expr
.X_add_number
+= 4;
7027 macro_build (&offset_expr
, "swc1", "T,o(b)",
7028 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7033 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7035 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7038 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7039 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7044 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7046 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7051 as_warn (_("Instruction %s: result is always false"),
7053 move_register (dreg
, 0);
7056 if (imm_expr
.X_op
== O_constant
7057 && imm_expr
.X_add_number
>= 0
7058 && imm_expr
.X_add_number
< 0x10000)
7060 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7063 else if (imm_expr
.X_op
== O_constant
7064 && imm_expr
.X_add_number
> -0x8000
7065 && imm_expr
.X_add_number
< 0)
7067 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7068 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7069 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7074 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7075 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7078 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7083 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7089 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7090 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7093 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7095 if (imm_expr
.X_op
== O_constant
7096 && imm_expr
.X_add_number
>= -0x8000
7097 && imm_expr
.X_add_number
< 0x8000)
7099 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7100 dreg
, sreg
, BFD_RELOC_LO16
);
7105 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7106 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7110 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7115 case M_SGT
: /* sreg > treg <==> treg < sreg */
7121 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7124 case M_SGT_I
: /* sreg > I <==> I < sreg */
7130 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7131 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7134 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7140 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7141 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7144 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7150 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7151 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7152 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7156 if (imm_expr
.X_op
== O_constant
7157 && imm_expr
.X_add_number
>= -0x8000
7158 && imm_expr
.X_add_number
< 0x8000)
7160 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7163 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7164 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7168 if (imm_expr
.X_op
== O_constant
7169 && imm_expr
.X_add_number
>= -0x8000
7170 && imm_expr
.X_add_number
< 0x8000)
7172 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7176 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7177 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7182 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7184 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7187 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7188 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7193 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7195 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7200 as_warn (_("Instruction %s: result is always true"),
7202 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7203 dreg
, 0, BFD_RELOC_LO16
);
7206 if (imm_expr
.X_op
== O_constant
7207 && imm_expr
.X_add_number
>= 0
7208 && imm_expr
.X_add_number
< 0x10000)
7210 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7213 else if (imm_expr
.X_op
== O_constant
7214 && imm_expr
.X_add_number
> -0x8000
7215 && imm_expr
.X_add_number
< 0)
7217 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7218 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7219 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7224 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7225 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7228 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7236 if (imm_expr
.X_op
== O_constant
7237 && imm_expr
.X_add_number
> -0x8000
7238 && imm_expr
.X_add_number
<= 0x8000)
7240 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7241 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7242 dreg
, sreg
, BFD_RELOC_LO16
);
7245 load_register (AT
, &imm_expr
, dbl
);
7246 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7252 if (imm_expr
.X_op
== O_constant
7253 && imm_expr
.X_add_number
> -0x8000
7254 && imm_expr
.X_add_number
<= 0x8000)
7256 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7257 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7258 dreg
, sreg
, BFD_RELOC_LO16
);
7261 load_register (AT
, &imm_expr
, dbl
);
7262 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7283 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7284 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7289 assert (mips_opts
.isa
== ISA_MIPS1
);
7290 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7291 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7294 * Is the double cfc1 instruction a bug in the mips assembler;
7295 * or is there a reason for it?
7297 mips_emit_delays (TRUE
);
7298 ++mips_opts
.noreorder
;
7299 mips_any_noreorder
= 1;
7300 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7301 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7302 macro_build (NULL
, "nop", "");
7303 expr1
.X_add_number
= 3;
7304 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7305 expr1
.X_add_number
= 2;
7306 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7307 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7308 macro_build (NULL
, "nop", "");
7309 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7311 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7312 macro_build (NULL
, "nop", "");
7313 --mips_opts
.noreorder
;
7322 if (offset_expr
.X_add_number
>= 0x7fff)
7323 as_bad (_("operand overflow"));
7324 if (! target_big_endian
)
7325 ++offset_expr
.X_add_number
;
7326 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7327 if (! target_big_endian
)
7328 --offset_expr
.X_add_number
;
7330 ++offset_expr
.X_add_number
;
7331 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7332 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7333 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7346 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7347 as_bad (_("operand overflow"));
7352 if (! target_big_endian
)
7353 offset_expr
.X_add_number
+= off
;
7354 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7355 if (! target_big_endian
)
7356 offset_expr
.X_add_number
-= off
;
7358 offset_expr
.X_add_number
+= off
;
7359 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7361 /* If necessary, move the result in tempreg the final destination. */
7362 if (treg
== tempreg
)
7364 /* Protect second load's delay slot. */
7366 move_register (treg
, tempreg
);
7380 load_address (AT
, &offset_expr
, &used_at
);
7382 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7383 if (! target_big_endian
)
7384 expr1
.X_add_number
= off
;
7386 expr1
.X_add_number
= 0;
7387 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7388 if (! target_big_endian
)
7389 expr1
.X_add_number
= 0;
7391 expr1
.X_add_number
= off
;
7392 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7398 load_address (AT
, &offset_expr
, &used_at
);
7400 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7401 if (target_big_endian
)
7402 expr1
.X_add_number
= 0;
7403 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7404 treg
, BFD_RELOC_LO16
, AT
);
7405 if (target_big_endian
)
7406 expr1
.X_add_number
= 1;
7408 expr1
.X_add_number
= 0;
7409 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7410 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7411 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7415 if (offset_expr
.X_add_number
>= 0x7fff)
7416 as_bad (_("operand overflow"));
7417 if (target_big_endian
)
7418 ++offset_expr
.X_add_number
;
7419 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7420 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7421 if (target_big_endian
)
7422 --offset_expr
.X_add_number
;
7424 ++offset_expr
.X_add_number
;
7425 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7438 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7439 as_bad (_("operand overflow"));
7440 if (! target_big_endian
)
7441 offset_expr
.X_add_number
+= off
;
7442 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7443 if (! target_big_endian
)
7444 offset_expr
.X_add_number
-= off
;
7446 offset_expr
.X_add_number
+= off
;
7447 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7461 load_address (AT
, &offset_expr
, &used_at
);
7463 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7464 if (! target_big_endian
)
7465 expr1
.X_add_number
= off
;
7467 expr1
.X_add_number
= 0;
7468 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7469 if (! target_big_endian
)
7470 expr1
.X_add_number
= 0;
7472 expr1
.X_add_number
= off
;
7473 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7478 load_address (AT
, &offset_expr
, &used_at
);
7480 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7481 if (! target_big_endian
)
7482 expr1
.X_add_number
= 0;
7483 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7484 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7485 if (! target_big_endian
)
7486 expr1
.X_add_number
= 1;
7488 expr1
.X_add_number
= 0;
7489 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7490 if (! target_big_endian
)
7491 expr1
.X_add_number
= 0;
7493 expr1
.X_add_number
= 1;
7494 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7495 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7496 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7500 /* FIXME: Check if this is one of the itbl macros, since they
7501 are added dynamically. */
7502 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7506 as_warn (_("Macro used $at after \".set noat\""));
7509 /* Implement macros in mips16 mode. */
7512 mips16_macro (struct mips_cl_insn
*ip
)
7515 int xreg
, yreg
, zreg
, tmp
;
7518 const char *s
, *s2
, *s3
;
7520 mask
= ip
->insn_mo
->mask
;
7522 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7523 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7524 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7526 expr1
.X_op
= O_constant
;
7527 expr1
.X_op_symbol
= NULL
;
7528 expr1
.X_add_symbol
= NULL
;
7529 expr1
.X_add_number
= 1;
7548 mips_emit_delays (TRUE
);
7549 ++mips_opts
.noreorder
;
7550 mips_any_noreorder
= 1;
7551 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7552 expr1
.X_add_number
= 2;
7553 macro_build (&expr1
, "bnez", "x,p", yreg
);
7554 macro_build (NULL
, "break", "6", 7);
7556 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7557 since that causes an overflow. We should do that as well,
7558 but I don't see how to do the comparisons without a temporary
7560 --mips_opts
.noreorder
;
7561 macro_build (NULL
, s
, "x", zreg
);
7580 mips_emit_delays (TRUE
);
7581 ++mips_opts
.noreorder
;
7582 mips_any_noreorder
= 1;
7583 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7584 expr1
.X_add_number
= 2;
7585 macro_build (&expr1
, "bnez", "x,p", yreg
);
7586 macro_build (NULL
, "break", "6", 7);
7587 --mips_opts
.noreorder
;
7588 macro_build (NULL
, s2
, "x", zreg
);
7594 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7595 macro_build (NULL
, "mflo", "x", zreg
);
7603 if (imm_expr
.X_op
!= O_constant
)
7604 as_bad (_("Unsupported large constant"));
7605 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7606 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7610 if (imm_expr
.X_op
!= O_constant
)
7611 as_bad (_("Unsupported large constant"));
7612 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7613 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7617 if (imm_expr
.X_op
!= O_constant
)
7618 as_bad (_("Unsupported large constant"));
7619 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7620 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7642 goto do_reverse_branch
;
7646 goto do_reverse_branch
;
7658 goto do_reverse_branch
;
7669 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7670 macro_build (&offset_expr
, s2
, "p");
7697 goto do_addone_branch_i
;
7702 goto do_addone_branch_i
;
7717 goto do_addone_branch_i
;
7724 if (imm_expr
.X_op
!= O_constant
)
7725 as_bad (_("Unsupported large constant"));
7726 ++imm_expr
.X_add_number
;
7729 macro_build (&imm_expr
, s
, s3
, xreg
);
7730 macro_build (&offset_expr
, s2
, "p");
7734 expr1
.X_add_number
= 0;
7735 macro_build (&expr1
, "slti", "x,8", yreg
);
7737 move_register (xreg
, yreg
);
7738 expr1
.X_add_number
= 2;
7739 macro_build (&expr1
, "bteqz", "p");
7740 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7744 /* For consistency checking, verify that all bits are specified either
7745 by the match/mask part of the instruction definition, or by the
7748 validate_mips_insn (const struct mips_opcode
*opc
)
7750 const char *p
= opc
->args
;
7752 unsigned long used_bits
= opc
->mask
;
7754 if ((used_bits
& opc
->match
) != opc
->match
)
7756 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7757 opc
->name
, opc
->args
);
7760 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7770 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7771 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7772 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7773 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7774 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7775 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7776 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7777 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7778 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7781 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7782 c
, opc
->name
, opc
->args
);
7786 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7787 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7789 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7790 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7791 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7792 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7794 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7795 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7797 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7798 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7800 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7801 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7802 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7803 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7804 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7805 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7806 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7807 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7808 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7809 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7810 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7811 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7812 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7813 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7814 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7815 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7816 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7818 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7819 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7820 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7821 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7823 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7824 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7825 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7826 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7827 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7828 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7829 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7830 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7831 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7834 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7835 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7836 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7837 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7838 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7842 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7843 c
, opc
->name
, opc
->args
);
7847 if (used_bits
!= 0xffffffff)
7849 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7850 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7856 /* This routine assembles an instruction into its binary format. As a
7857 side effect, it sets one of the global variables imm_reloc or
7858 offset_reloc to the type of relocation to do if one of the operands
7859 is an address expression. */
7862 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7867 struct mips_opcode
*insn
;
7870 unsigned int lastregno
= 0;
7871 unsigned int lastpos
= 0;
7872 unsigned int limlo
, limhi
;
7878 /* If the instruction contains a '.', we first try to match an instruction
7879 including the '.'. Then we try again without the '.'. */
7881 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7884 /* If we stopped on whitespace, then replace the whitespace with null for
7885 the call to hash_find. Save the character we replaced just in case we
7886 have to re-parse the instruction. */
7893 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7895 /* If we didn't find the instruction in the opcode table, try again, but
7896 this time with just the instruction up to, but not including the
7900 /* Restore the character we overwrite above (if any). */
7904 /* Scan up to the first '.' or whitespace. */
7906 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7910 /* If we did not find a '.', then we can quit now. */
7913 insn_error
= "unrecognized opcode";
7917 /* Lookup the instruction in the hash table. */
7919 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7921 insn_error
= "unrecognized opcode";
7931 assert (strcmp (insn
->name
, str
) == 0);
7933 if (OPCODE_IS_MEMBER (insn
,
7935 | (file_ase_mips16
? INSN_MIPS16
: 0)
7936 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7937 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7943 if (insn
->pinfo
!= INSN_MACRO
)
7945 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7951 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7952 && strcmp (insn
->name
, insn
[1].name
) == 0)
7961 static char buf
[100];
7963 _("opcode not supported on this processor: %s (%s)"),
7964 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7965 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7975 ip
->insn_opcode
= insn
->match
;
7977 for (args
= insn
->args
;; ++args
)
7981 s
+= strspn (s
, " \t");
7985 case '\0': /* end of args */
7998 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8002 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8006 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8010 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8016 /* Handle optional base register.
8017 Either the base register is omitted or
8018 we must have a left paren. */
8019 /* This is dependent on the next operand specifier
8020 is a base register specification. */
8021 assert (args
[1] == 'b' || args
[1] == '5'
8022 || args
[1] == '-' || args
[1] == '4');
8026 case ')': /* these must match exactly */
8033 case '+': /* Opcode extension character. */
8036 case 'A': /* ins/ext position, becomes LSB. */
8045 my_getExpression (&imm_expr
, s
);
8046 check_absolute_expr (ip
, &imm_expr
);
8047 if ((unsigned long) imm_expr
.X_add_number
< limlo
8048 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8050 as_bad (_("Improper position (%lu)"),
8051 (unsigned long) imm_expr
.X_add_number
);
8052 imm_expr
.X_add_number
= limlo
;
8054 lastpos
= imm_expr
.X_add_number
;
8055 ip
->insn_opcode
|= (imm_expr
.X_add_number
8056 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8057 imm_expr
.X_op
= O_absent
;
8061 case 'B': /* ins size, becomes MSB. */
8070 my_getExpression (&imm_expr
, s
);
8071 check_absolute_expr (ip
, &imm_expr
);
8072 /* Check for negative input so that small negative numbers
8073 will not succeed incorrectly. The checks against
8074 (pos+size) transitively check "size" itself,
8075 assuming that "pos" is reasonable. */
8076 if ((long) imm_expr
.X_add_number
< 0
8077 || ((unsigned long) imm_expr
.X_add_number
8079 || ((unsigned long) imm_expr
.X_add_number
8082 as_bad (_("Improper insert size (%lu, position %lu)"),
8083 (unsigned long) imm_expr
.X_add_number
,
8084 (unsigned long) lastpos
);
8085 imm_expr
.X_add_number
= limlo
- lastpos
;
8087 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8088 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8089 imm_expr
.X_op
= O_absent
;
8093 case 'C': /* ext size, becomes MSBD. */
8106 my_getExpression (&imm_expr
, s
);
8107 check_absolute_expr (ip
, &imm_expr
);
8108 /* Check for negative input so that small negative numbers
8109 will not succeed incorrectly. The checks against
8110 (pos+size) transitively check "size" itself,
8111 assuming that "pos" is reasonable. */
8112 if ((long) imm_expr
.X_add_number
< 0
8113 || ((unsigned long) imm_expr
.X_add_number
8115 || ((unsigned long) imm_expr
.X_add_number
8118 as_bad (_("Improper extract size (%lu, position %lu)"),
8119 (unsigned long) imm_expr
.X_add_number
,
8120 (unsigned long) lastpos
);
8121 imm_expr
.X_add_number
= limlo
- lastpos
;
8123 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8124 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8125 imm_expr
.X_op
= O_absent
;
8130 /* +D is for disassembly only; never match. */
8134 /* "+I" is like "I", except that imm2_expr is used. */
8135 my_getExpression (&imm2_expr
, s
);
8136 if (imm2_expr
.X_op
!= O_big
8137 && imm2_expr
.X_op
!= O_constant
)
8138 insn_error
= _("absolute expression required");
8139 normalize_constant_expr (&imm2_expr
);
8144 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8145 *args
, insn
->name
, insn
->args
);
8146 /* Further processing is fruitless. */
8151 case '<': /* must be at least one digit */
8153 * According to the manual, if the shift amount is greater
8154 * than 31 or less than 0, then the shift amount should be
8155 * mod 32. In reality the mips assembler issues an error.
8156 * We issue a warning and mask out all but the low 5 bits.
8158 my_getExpression (&imm_expr
, s
);
8159 check_absolute_expr (ip
, &imm_expr
);
8160 if ((unsigned long) imm_expr
.X_add_number
> 31)
8162 as_warn (_("Improper shift amount (%lu)"),
8163 (unsigned long) imm_expr
.X_add_number
);
8164 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8166 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8167 imm_expr
.X_op
= O_absent
;
8171 case '>': /* shift amount minus 32 */
8172 my_getExpression (&imm_expr
, s
);
8173 check_absolute_expr (ip
, &imm_expr
);
8174 if ((unsigned long) imm_expr
.X_add_number
< 32
8175 || (unsigned long) imm_expr
.X_add_number
> 63)
8177 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8178 imm_expr
.X_op
= O_absent
;
8182 case 'k': /* cache code */
8183 case 'h': /* prefx code */
8184 my_getExpression (&imm_expr
, s
);
8185 check_absolute_expr (ip
, &imm_expr
);
8186 if ((unsigned long) imm_expr
.X_add_number
> 31)
8188 as_warn (_("Invalid value for `%s' (%lu)"),
8190 (unsigned long) imm_expr
.X_add_number
);
8191 imm_expr
.X_add_number
&= 0x1f;
8194 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8196 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8197 imm_expr
.X_op
= O_absent
;
8201 case 'c': /* break code */
8202 my_getExpression (&imm_expr
, s
);
8203 check_absolute_expr (ip
, &imm_expr
);
8204 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8206 as_warn (_("Illegal break code (%lu)"),
8207 (unsigned long) imm_expr
.X_add_number
);
8208 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8210 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8211 imm_expr
.X_op
= O_absent
;
8215 case 'q': /* lower break code */
8216 my_getExpression (&imm_expr
, s
);
8217 check_absolute_expr (ip
, &imm_expr
);
8218 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8220 as_warn (_("Illegal lower break code (%lu)"),
8221 (unsigned long) imm_expr
.X_add_number
);
8222 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8224 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8225 imm_expr
.X_op
= O_absent
;
8229 case 'B': /* 20-bit syscall/break code. */
8230 my_getExpression (&imm_expr
, s
);
8231 check_absolute_expr (ip
, &imm_expr
);
8232 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8233 as_warn (_("Illegal 20-bit code (%lu)"),
8234 (unsigned long) imm_expr
.X_add_number
);
8235 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8236 imm_expr
.X_op
= O_absent
;
8240 case 'C': /* Coprocessor code */
8241 my_getExpression (&imm_expr
, s
);
8242 check_absolute_expr (ip
, &imm_expr
);
8243 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8245 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8246 (unsigned long) imm_expr
.X_add_number
);
8247 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8249 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8250 imm_expr
.X_op
= O_absent
;
8254 case 'J': /* 19-bit wait code. */
8255 my_getExpression (&imm_expr
, s
);
8256 check_absolute_expr (ip
, &imm_expr
);
8257 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8258 as_warn (_("Illegal 19-bit code (%lu)"),
8259 (unsigned long) imm_expr
.X_add_number
);
8260 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8261 imm_expr
.X_op
= O_absent
;
8265 case 'P': /* Performance register */
8266 my_getExpression (&imm_expr
, s
);
8267 check_absolute_expr (ip
, &imm_expr
);
8268 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8270 as_warn (_("Invalid performance register (%lu)"),
8271 (unsigned long) imm_expr
.X_add_number
);
8272 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8274 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8275 imm_expr
.X_op
= O_absent
;
8279 case 'b': /* base register */
8280 case 'd': /* destination register */
8281 case 's': /* source register */
8282 case 't': /* target register */
8283 case 'r': /* both target and source */
8284 case 'v': /* both dest and source */
8285 case 'w': /* both dest and target */
8286 case 'E': /* coprocessor target register */
8287 case 'G': /* coprocessor destination register */
8288 case 'K': /* 'rdhwr' destination register */
8289 case 'x': /* ignore register name */
8290 case 'z': /* must be zero register */
8291 case 'U': /* destination register (clo/clz). */
8306 while (ISDIGIT (*s
));
8308 as_bad (_("Invalid register number (%d)"), regno
);
8310 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8314 if (s
[1] == 'r' && s
[2] == 'a')
8319 else if (s
[1] == 'f' && s
[2] == 'p')
8324 else if (s
[1] == 's' && s
[2] == 'p')
8329 else if (s
[1] == 'g' && s
[2] == 'p')
8334 else if (s
[1] == 'a' && s
[2] == 't')
8339 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8344 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8349 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8354 else if (itbl_have_entries
)
8359 p
= s
+ 1; /* advance past '$' */
8360 n
= itbl_get_field (&p
); /* n is name */
8362 /* See if this is a register defined in an
8364 if (itbl_get_reg_val (n
, &r
))
8366 /* Get_field advances to the start of
8367 the next field, so we need to back
8368 rack to the end of the last field. */
8372 s
= strchr (s
, '\0');
8386 as_warn (_("Used $at without \".set noat\""));
8392 if (c
== 'r' || c
== 'v' || c
== 'w')
8399 /* 'z' only matches $0. */
8400 if (c
== 'z' && regno
!= 0)
8403 /* Now that we have assembled one operand, we use the args string
8404 * to figure out where it goes in the instruction. */
8411 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8416 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8419 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8420 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8425 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8428 /* This case exists because on the r3000 trunc
8429 expands into a macro which requires a gp
8430 register. On the r6000 or r4000 it is
8431 assembled into a single instruction which
8432 ignores the register. Thus the insn version
8433 is MIPS_ISA2 and uses 'x', and the macro
8434 version is MIPS_ISA1 and uses 't'. */
8437 /* This case is for the div instruction, which
8438 acts differently if the destination argument
8439 is $0. This only matches $0, and is checked
8440 outside the switch. */
8443 /* Itbl operand; not yet implemented. FIXME ?? */
8445 /* What about all other operands like 'i', which
8446 can be specified in the opcode table? */
8456 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8459 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8464 case 'O': /* MDMX alignment immediate constant. */
8465 my_getExpression (&imm_expr
, s
);
8466 check_absolute_expr (ip
, &imm_expr
);
8467 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8469 as_warn ("Improper align amount (%ld), using low bits",
8470 (long) imm_expr
.X_add_number
);
8471 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8473 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8474 imm_expr
.X_op
= O_absent
;
8478 case 'Q': /* MDMX vector, element sel, or const. */
8481 /* MDMX Immediate. */
8482 my_getExpression (&imm_expr
, s
);
8483 check_absolute_expr (ip
, &imm_expr
);
8484 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8486 as_warn (_("Invalid MDMX Immediate (%ld)"),
8487 (long) imm_expr
.X_add_number
);
8488 imm_expr
.X_add_number
&= OP_MASK_FT
;
8490 imm_expr
.X_add_number
&= OP_MASK_FT
;
8491 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8492 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8494 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8495 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8496 imm_expr
.X_op
= O_absent
;
8500 /* Not MDMX Immediate. Fall through. */
8501 case 'X': /* MDMX destination register. */
8502 case 'Y': /* MDMX source register. */
8503 case 'Z': /* MDMX target register. */
8505 case 'D': /* floating point destination register */
8506 case 'S': /* floating point source register */
8507 case 'T': /* floating point target register */
8508 case 'R': /* floating point source register */
8512 /* Accept $fN for FP and MDMX register numbers, and in
8513 addition accept $vN for MDMX register numbers. */
8514 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8515 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8526 while (ISDIGIT (*s
));
8529 as_bad (_("Invalid float register number (%d)"), regno
);
8531 if ((regno
& 1) != 0
8533 && ! (strcmp (str
, "mtc1") == 0
8534 || strcmp (str
, "mfc1") == 0
8535 || strcmp (str
, "lwc1") == 0
8536 || strcmp (str
, "swc1") == 0
8537 || strcmp (str
, "l.s") == 0
8538 || strcmp (str
, "s.s") == 0))
8539 as_warn (_("Float register should be even, was %d"),
8547 if (c
== 'V' || c
== 'W')
8558 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8563 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8566 /* This is like 'Z', but also needs to fix the MDMX
8567 vector/scalar select bits. Note that the
8568 scalar immediate case is handled above. */
8571 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8572 int max_el
= (is_qh
? 3 : 7);
8574 my_getExpression(&imm_expr
, s
);
8575 check_absolute_expr (ip
, &imm_expr
);
8577 if (imm_expr
.X_add_number
> max_el
)
8578 as_bad(_("Bad element selector %ld"),
8579 (long) imm_expr
.X_add_number
);
8580 imm_expr
.X_add_number
&= max_el
;
8581 ip
->insn_opcode
|= (imm_expr
.X_add_number
8585 as_warn(_("Expecting ']' found '%s'"), s
);
8591 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8592 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8595 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8602 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8605 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8615 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8618 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8624 my_getExpression (&imm_expr
, s
);
8625 if (imm_expr
.X_op
!= O_big
8626 && imm_expr
.X_op
!= O_constant
)
8627 insn_error
= _("absolute expression required");
8628 normalize_constant_expr (&imm_expr
);
8633 my_getExpression (&offset_expr
, s
);
8634 *imm_reloc
= BFD_RELOC_32
;
8647 unsigned char temp
[8];
8649 unsigned int length
;
8654 /* These only appear as the last operand in an
8655 instruction, and every instruction that accepts
8656 them in any variant accepts them in all variants.
8657 This means we don't have to worry about backing out
8658 any changes if the instruction does not match.
8660 The difference between them is the size of the
8661 floating point constant and where it goes. For 'F'
8662 and 'L' the constant is 64 bits; for 'f' and 'l' it
8663 is 32 bits. Where the constant is placed is based
8664 on how the MIPS assembler does things:
8667 f -- immediate value
8670 The .lit4 and .lit8 sections are only used if
8671 permitted by the -G argument.
8673 The code below needs to know whether the target register
8674 is 32 or 64 bits wide. It relies on the fact 'f' and
8675 'F' are used with GPR-based instructions and 'l' and
8676 'L' are used with FPR-based instructions. */
8678 f64
= *args
== 'F' || *args
== 'L';
8679 using_gprs
= *args
== 'F' || *args
== 'f';
8681 save_in
= input_line_pointer
;
8682 input_line_pointer
= s
;
8683 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8685 s
= input_line_pointer
;
8686 input_line_pointer
= save_in
;
8687 if (err
!= NULL
&& *err
!= '\0')
8689 as_bad (_("Bad floating point constant: %s"), err
);
8690 memset (temp
, '\0', sizeof temp
);
8691 length
= f64
? 8 : 4;
8694 assert (length
== (unsigned) (f64
? 8 : 4));
8698 && (g_switch_value
< 4
8699 || (temp
[0] == 0 && temp
[1] == 0)
8700 || (temp
[2] == 0 && temp
[3] == 0))))
8702 imm_expr
.X_op
= O_constant
;
8703 if (! target_big_endian
)
8704 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8706 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8709 && ! mips_disable_float_construction
8710 /* Constants can only be constructed in GPRs and
8711 copied to FPRs if the GPRs are at least as wide
8712 as the FPRs. Force the constant into memory if
8713 we are using 64-bit FPRs but the GPRs are only
8716 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8717 && ((temp
[0] == 0 && temp
[1] == 0)
8718 || (temp
[2] == 0 && temp
[3] == 0))
8719 && ((temp
[4] == 0 && temp
[5] == 0)
8720 || (temp
[6] == 0 && temp
[7] == 0)))
8722 /* The value is simple enough to load with a couple of
8723 instructions. If using 32-bit registers, set
8724 imm_expr to the high order 32 bits and offset_expr to
8725 the low order 32 bits. Otherwise, set imm_expr to
8726 the entire 64 bit constant. */
8727 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8729 imm_expr
.X_op
= O_constant
;
8730 offset_expr
.X_op
= O_constant
;
8731 if (! target_big_endian
)
8733 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8734 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8738 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8739 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8741 if (offset_expr
.X_add_number
== 0)
8742 offset_expr
.X_op
= O_absent
;
8744 else if (sizeof (imm_expr
.X_add_number
) > 4)
8746 imm_expr
.X_op
= O_constant
;
8747 if (! target_big_endian
)
8748 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8750 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8754 imm_expr
.X_op
= O_big
;
8755 imm_expr
.X_add_number
= 4;
8756 if (! target_big_endian
)
8758 generic_bignum
[0] = bfd_getl16 (temp
);
8759 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8760 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8761 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8765 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8766 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8767 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8768 generic_bignum
[3] = bfd_getb16 (temp
);
8774 const char *newname
;
8777 /* Switch to the right section. */
8779 subseg
= now_subseg
;
8782 default: /* unused default case avoids warnings. */
8784 newname
= RDATA_SECTION_NAME
;
8785 if (g_switch_value
>= 8)
8789 newname
= RDATA_SECTION_NAME
;
8792 assert (g_switch_value
>= 4);
8796 new_seg
= subseg_new (newname
, (subsegT
) 0);
8797 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8798 bfd_set_section_flags (stdoutput
, new_seg
,
8803 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8804 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8805 && strcmp (TARGET_OS
, "elf") != 0)
8806 record_alignment (new_seg
, 4);
8808 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8810 as_bad (_("Can't use floating point insn in this section"));
8812 /* Set the argument to the current address in the
8814 offset_expr
.X_op
= O_symbol
;
8815 offset_expr
.X_add_symbol
=
8816 symbol_new ("L0\001", now_seg
,
8817 (valueT
) frag_now_fix (), frag_now
);
8818 offset_expr
.X_add_number
= 0;
8820 /* Put the floating point number into the section. */
8821 p
= frag_more ((int) length
);
8822 memcpy (p
, temp
, length
);
8824 /* Switch back to the original section. */
8825 subseg_set (seg
, subseg
);
8830 case 'i': /* 16 bit unsigned immediate */
8831 case 'j': /* 16 bit signed immediate */
8832 *imm_reloc
= BFD_RELOC_LO16
;
8833 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8836 offsetT minval
, maxval
;
8838 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8839 && strcmp (insn
->name
, insn
[1].name
) == 0);
8841 /* If the expression was written as an unsigned number,
8842 only treat it as signed if there are no more
8846 && sizeof (imm_expr
.X_add_number
) <= 4
8847 && imm_expr
.X_op
== O_constant
8848 && imm_expr
.X_add_number
< 0
8849 && imm_expr
.X_unsigned
8853 /* For compatibility with older assemblers, we accept
8854 0x8000-0xffff as signed 16-bit numbers when only
8855 signed numbers are allowed. */
8857 minval
= 0, maxval
= 0xffff;
8859 minval
= -0x8000, maxval
= 0x7fff;
8861 minval
= -0x8000, maxval
= 0xffff;
8863 if (imm_expr
.X_op
!= O_constant
8864 || imm_expr
.X_add_number
< minval
8865 || imm_expr
.X_add_number
> maxval
)
8869 if (imm_expr
.X_op
== O_constant
8870 || imm_expr
.X_op
== O_big
)
8871 as_bad (_("expression out of range"));
8877 case 'o': /* 16 bit offset */
8878 /* Check whether there is only a single bracketed expression
8879 left. If so, it must be the base register and the
8880 constant must be zero. */
8881 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8883 offset_expr
.X_op
= O_constant
;
8884 offset_expr
.X_add_number
= 0;
8888 /* If this value won't fit into a 16 bit offset, then go
8889 find a macro that will generate the 32 bit offset
8891 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8892 && (offset_expr
.X_op
!= O_constant
8893 || offset_expr
.X_add_number
>= 0x8000
8894 || offset_expr
.X_add_number
< -0x8000))
8900 case 'p': /* pc relative offset */
8901 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8902 my_getExpression (&offset_expr
, s
);
8906 case 'u': /* upper 16 bits */
8907 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8908 && imm_expr
.X_op
== O_constant
8909 && (imm_expr
.X_add_number
< 0
8910 || imm_expr
.X_add_number
>= 0x10000))
8911 as_bad (_("lui expression not in range 0..65535"));
8915 case 'a': /* 26 bit address */
8916 my_getExpression (&offset_expr
, s
);
8918 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8921 case 'N': /* 3 bit branch condition code */
8922 case 'M': /* 3 bit compare condition code */
8923 if (strncmp (s
, "$fcc", 4) != 0)
8933 while (ISDIGIT (*s
));
8935 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8936 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8937 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8938 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8939 && (regno
& 1) != 0)
8940 as_warn(_("Condition code register should be even for %s, was %d"),
8942 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8943 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8944 && (regno
& 3) != 0)
8945 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8948 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8950 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8954 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8965 while (ISDIGIT (*s
));
8968 c
= 8; /* Invalid sel value. */
8971 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8972 ip
->insn_opcode
|= c
;
8976 /* Must be at least one digit. */
8977 my_getExpression (&imm_expr
, s
);
8978 check_absolute_expr (ip
, &imm_expr
);
8980 if ((unsigned long) imm_expr
.X_add_number
8981 > (unsigned long) OP_MASK_VECBYTE
)
8983 as_bad (_("bad byte vector index (%ld)"),
8984 (long) imm_expr
.X_add_number
);
8985 imm_expr
.X_add_number
= 0;
8988 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8989 imm_expr
.X_op
= O_absent
;
8994 my_getExpression (&imm_expr
, s
);
8995 check_absolute_expr (ip
, &imm_expr
);
8997 if ((unsigned long) imm_expr
.X_add_number
8998 > (unsigned long) OP_MASK_VECALIGN
)
9000 as_bad (_("bad byte vector index (%ld)"),
9001 (long) imm_expr
.X_add_number
);
9002 imm_expr
.X_add_number
= 0;
9005 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9006 imm_expr
.X_op
= O_absent
;
9011 as_bad (_("bad char = '%c'\n"), *args
);
9016 /* Args don't match. */
9017 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9018 !strcmp (insn
->name
, insn
[1].name
))
9022 insn_error
= _("illegal operands");
9027 insn_error
= _("illegal operands");
9032 /* This routine assembles an instruction into its binary format when
9033 assembling for the mips16. As a side effect, it sets one of the
9034 global variables imm_reloc or offset_reloc to the type of
9035 relocation to do if one of the operands is an address expression.
9036 It also sets mips16_small and mips16_ext if the user explicitly
9037 requested a small or extended instruction. */
9040 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9044 struct mips_opcode
*insn
;
9047 unsigned int lastregno
= 0;
9052 mips16_small
= FALSE
;
9055 for (s
= str
; ISLOWER (*s
); ++s
)
9067 if (s
[1] == 't' && s
[2] == ' ')
9070 mips16_small
= TRUE
;
9074 else if (s
[1] == 'e' && s
[2] == ' ')
9083 insn_error
= _("unknown opcode");
9087 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9088 mips16_small
= TRUE
;
9090 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9092 insn_error
= _("unrecognized opcode");
9099 assert (strcmp (insn
->name
, str
) == 0);
9102 ip
->insn_opcode
= insn
->match
;
9103 ip
->use_extend
= FALSE
;
9104 imm_expr
.X_op
= O_absent
;
9105 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9106 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9107 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9108 imm2_expr
.X_op
= O_absent
;
9109 offset_expr
.X_op
= O_absent
;
9110 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9111 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9112 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9113 for (args
= insn
->args
; 1; ++args
)
9120 /* In this switch statement we call break if we did not find
9121 a match, continue if we did find a match, or return if we
9130 /* Stuff the immediate value in now, if we can. */
9131 if (imm_expr
.X_op
== O_constant
9132 && *imm_reloc
> BFD_RELOC_UNUSED
9133 && insn
->pinfo
!= INSN_MACRO
)
9135 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9136 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9137 mips16_ext
, &ip
->insn_opcode
,
9138 &ip
->use_extend
, &ip
->extend
);
9139 imm_expr
.X_op
= O_absent
;
9140 *imm_reloc
= BFD_RELOC_UNUSED
;
9154 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9157 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9173 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9175 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9202 while (ISDIGIT (*s
));
9205 as_bad (_("invalid register number (%d)"), regno
);
9211 if (s
[1] == 'r' && s
[2] == 'a')
9216 else if (s
[1] == 'f' && s
[2] == 'p')
9221 else if (s
[1] == 's' && s
[2] == 'p')
9226 else if (s
[1] == 'g' && s
[2] == 'p')
9231 else if (s
[1] == 'a' && s
[2] == 't')
9236 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9241 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9246 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9259 if (c
== 'v' || c
== 'w')
9261 regno
= mips16_to_32_reg_map
[lastregno
];
9275 regno
= mips32_to_16_reg_map
[regno
];
9280 regno
= ILLEGAL_REG
;
9285 regno
= ILLEGAL_REG
;
9290 regno
= ILLEGAL_REG
;
9295 if (regno
== AT
&& ! mips_opts
.noat
)
9296 as_warn (_("used $at without \".set noat\""));
9303 if (regno
== ILLEGAL_REG
)
9310 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9314 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9317 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9320 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9326 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9329 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9330 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9340 if (strncmp (s
, "$pc", 3) == 0)
9364 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9366 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9367 and generate the appropriate reloc. If the text
9368 inside %gprel is not a symbol name with an
9369 optional offset, then we generate a normal reloc
9370 and will probably fail later. */
9371 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9372 if (imm_expr
.X_op
== O_symbol
)
9375 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9377 ip
->use_extend
= TRUE
;
9384 /* Just pick up a normal expression. */
9385 my_getExpression (&imm_expr
, s
);
9388 if (imm_expr
.X_op
== O_register
)
9390 /* What we thought was an expression turned out to
9393 if (s
[0] == '(' && args
[1] == '(')
9395 /* It looks like the expression was omitted
9396 before a register indirection, which means
9397 that the expression is implicitly zero. We
9398 still set up imm_expr, so that we handle
9399 explicit extensions correctly. */
9400 imm_expr
.X_op
= O_constant
;
9401 imm_expr
.X_add_number
= 0;
9402 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9409 /* We need to relax this instruction. */
9410 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9419 /* We use offset_reloc rather than imm_reloc for the PC
9420 relative operands. This lets macros with both
9421 immediate and address operands work correctly. */
9422 my_getExpression (&offset_expr
, s
);
9424 if (offset_expr
.X_op
== O_register
)
9427 /* We need to relax this instruction. */
9428 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9432 case '6': /* break code */
9433 my_getExpression (&imm_expr
, s
);
9434 check_absolute_expr (ip
, &imm_expr
);
9435 if ((unsigned long) imm_expr
.X_add_number
> 63)
9437 as_warn (_("Invalid value for `%s' (%lu)"),
9439 (unsigned long) imm_expr
.X_add_number
);
9440 imm_expr
.X_add_number
&= 0x3f;
9442 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9443 imm_expr
.X_op
= O_absent
;
9447 case 'a': /* 26 bit address */
9448 my_getExpression (&offset_expr
, s
);
9450 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9451 ip
->insn_opcode
<<= 16;
9454 case 'l': /* register list for entry macro */
9455 case 'L': /* register list for exit macro */
9465 int freg
, reg1
, reg2
;
9467 while (*s
== ' ' || *s
== ',')
9471 as_bad (_("can't parse register list"));
9483 while (ISDIGIT (*s
))
9505 as_bad (_("invalid register list"));
9510 while (ISDIGIT (*s
))
9517 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9522 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9527 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9528 mask
|= (reg2
- 3) << 3;
9529 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9530 mask
|= (reg2
- 15) << 1;
9531 else if (reg1
== RA
&& reg2
== RA
)
9535 as_bad (_("invalid register list"));
9539 /* The mask is filled in in the opcode table for the
9540 benefit of the disassembler. We remove it before
9541 applying the actual mask. */
9542 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9543 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9547 case 'e': /* extend code */
9548 my_getExpression (&imm_expr
, s
);
9549 check_absolute_expr (ip
, &imm_expr
);
9550 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9552 as_warn (_("Invalid value for `%s' (%lu)"),
9554 (unsigned long) imm_expr
.X_add_number
);
9555 imm_expr
.X_add_number
&= 0x7ff;
9557 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9558 imm_expr
.X_op
= O_absent
;
9568 /* Args don't match. */
9569 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9570 strcmp (insn
->name
, insn
[1].name
) == 0)
9577 insn_error
= _("illegal operands");
9583 /* This structure holds information we know about a mips16 immediate
9586 struct mips16_immed_operand
9588 /* The type code used in the argument string in the opcode table. */
9590 /* The number of bits in the short form of the opcode. */
9592 /* The number of bits in the extended form of the opcode. */
9594 /* The amount by which the short form is shifted when it is used;
9595 for example, the sw instruction has a shift count of 2. */
9597 /* The amount by which the short form is shifted when it is stored
9598 into the instruction code. */
9600 /* Non-zero if the short form is unsigned. */
9602 /* Non-zero if the extended form is unsigned. */
9604 /* Non-zero if the value is PC relative. */
9608 /* The mips16 immediate operand types. */
9610 static const struct mips16_immed_operand mips16_immed_operands
[] =
9612 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9613 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9614 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9615 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9616 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9617 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9618 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9619 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9620 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9621 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9622 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9623 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9624 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9625 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9626 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9627 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9628 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9629 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9630 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9631 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9632 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9635 #define MIPS16_NUM_IMMED \
9636 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9638 /* Handle a mips16 instruction with an immediate value. This or's the
9639 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9640 whether an extended value is needed; if one is needed, it sets
9641 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9642 If SMALL is true, an unextended opcode was explicitly requested.
9643 If EXT is true, an extended opcode was explicitly requested. If
9644 WARN is true, warn if EXT does not match reality. */
9647 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9648 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9649 unsigned long *insn
, bfd_boolean
*use_extend
,
9650 unsigned short *extend
)
9652 register const struct mips16_immed_operand
*op
;
9653 int mintiny
, maxtiny
;
9654 bfd_boolean needext
;
9656 op
= mips16_immed_operands
;
9657 while (op
->type
!= type
)
9660 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9665 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9668 maxtiny
= 1 << op
->nbits
;
9673 maxtiny
= (1 << op
->nbits
) - 1;
9678 mintiny
= - (1 << (op
->nbits
- 1));
9679 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9682 /* Branch offsets have an implicit 0 in the lowest bit. */
9683 if (type
== 'p' || type
== 'q')
9686 if ((val
& ((1 << op
->shift
) - 1)) != 0
9687 || val
< (mintiny
<< op
->shift
)
9688 || val
> (maxtiny
<< op
->shift
))
9693 if (warn
&& ext
&& ! needext
)
9694 as_warn_where (file
, line
,
9695 _("extended operand requested but not required"));
9696 if (small
&& needext
)
9697 as_bad_where (file
, line
, _("invalid unextended operand value"));
9699 if (small
|| (! ext
&& ! needext
))
9703 *use_extend
= FALSE
;
9704 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9705 insnval
<<= op
->op_shift
;
9710 long minext
, maxext
;
9716 maxext
= (1 << op
->extbits
) - 1;
9720 minext
= - (1 << (op
->extbits
- 1));
9721 maxext
= (1 << (op
->extbits
- 1)) - 1;
9723 if (val
< minext
|| val
> maxext
)
9724 as_bad_where (file
, line
,
9725 _("operand value out of range for instruction"));
9728 if (op
->extbits
== 16)
9730 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9733 else if (op
->extbits
== 15)
9735 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9740 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9744 *extend
= (unsigned short) extval
;
9749 static const struct percent_op_match
9752 bfd_reloc_code_real_type reloc
;
9755 {"%lo", BFD_RELOC_LO16
},
9757 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9758 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9759 {"%call16", BFD_RELOC_MIPS_CALL16
},
9760 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9761 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9762 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9763 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9764 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9765 {"%got", BFD_RELOC_MIPS_GOT16
},
9766 {"%gp_rel", BFD_RELOC_GPREL16
},
9767 {"%half", BFD_RELOC_16
},
9768 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9769 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9770 {"%neg", BFD_RELOC_MIPS_SUB
},
9772 {"%hi", BFD_RELOC_HI16_S
}
9776 /* Return true if *STR points to a relocation operator. When returning true,
9777 move *STR over the operator and store its relocation code in *RELOC.
9778 Leave both *STR and *RELOC alone when returning false. */
9781 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9785 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
9786 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9788 *str
+= strlen (percent_op
[i
].str
);
9789 *reloc
= percent_op
[i
].reloc
;
9791 /* Check whether the output BFD supports this relocation.
9792 If not, issue an error and fall back on something safe. */
9793 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9795 as_bad ("relocation %s isn't supported by the current ABI",
9797 *reloc
= BFD_RELOC_LO16
;
9805 /* Parse string STR as a 16-bit relocatable operand. Store the
9806 expression in *EP and the relocations in the array starting
9807 at RELOC. Return the number of relocation operators used.
9809 On exit, EXPR_END points to the first character after the expression.
9810 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
9813 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9816 bfd_reloc_code_real_type reversed_reloc
[3];
9817 size_t reloc_index
, i
;
9818 int crux_depth
, str_depth
;
9821 /* Search for the start of the main expression, recoding relocations
9822 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9823 of the main expression and with CRUX_DEPTH containing the number
9824 of open brackets at that point. */
9831 crux_depth
= str_depth
;
9833 /* Skip over whitespace and brackets, keeping count of the number
9835 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9840 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9841 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9843 my_getExpression (ep
, crux
);
9846 /* Match every open bracket. */
9847 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9852 as_bad ("unclosed '('");
9856 if (reloc_index
== 0)
9857 reloc
[0] = BFD_RELOC_LO16
;
9860 prev_reloc_op_frag
= frag_now
;
9861 for (i
= 0; i
< reloc_index
; i
++)
9862 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9869 my_getExpression (expressionS
*ep
, char *str
)
9874 save_in
= input_line_pointer
;
9875 input_line_pointer
= str
;
9877 expr_end
= input_line_pointer
;
9878 input_line_pointer
= save_in
;
9880 /* If we are in mips16 mode, and this is an expression based on `.',
9881 then we bump the value of the symbol by 1 since that is how other
9882 text symbols are handled. We don't bother to handle complex
9883 expressions, just `.' plus or minus a constant. */
9884 if (mips_opts
.mips16
9885 && ep
->X_op
== O_symbol
9886 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9887 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9888 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9889 && symbol_constant_p (ep
->X_add_symbol
)
9890 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9891 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9894 /* Turn a string in input_line_pointer into a floating point constant
9895 of type TYPE, and store the appropriate bytes in *LITP. The number
9896 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9897 returned, or NULL on OK. */
9900 md_atof (int type
, char *litP
, int *sizeP
)
9903 LITTLENUM_TYPE words
[4];
9919 return _("bad call to md_atof");
9922 t
= atof_ieee (input_line_pointer
, type
, words
);
9924 input_line_pointer
= t
;
9928 if (! target_big_endian
)
9930 for (i
= prec
- 1; i
>= 0; i
--)
9932 md_number_to_chars (litP
, words
[i
], 2);
9938 for (i
= 0; i
< prec
; i
++)
9940 md_number_to_chars (litP
, words
[i
], 2);
9949 md_number_to_chars (char *buf
, valueT val
, int n
)
9951 if (target_big_endian
)
9952 number_to_chars_bigendian (buf
, val
, n
);
9954 number_to_chars_littleendian (buf
, val
, n
);
9958 static int support_64bit_objects(void)
9960 const char **list
, **l
;
9963 list
= bfd_target_list ();
9964 for (l
= list
; *l
!= NULL
; l
++)
9966 /* This is traditional mips */
9967 if (strcmp (*l
, "elf64-tradbigmips") == 0
9968 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9970 if (strcmp (*l
, "elf64-bigmips") == 0
9971 || strcmp (*l
, "elf64-littlemips") == 0)
9978 #endif /* OBJ_ELF */
9980 const char *md_shortopts
= "O::g::G:";
9982 struct option md_longopts
[] =
9984 /* Options which specify architecture. */
9985 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9986 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9987 {"march", required_argument
, NULL
, OPTION_MARCH
},
9988 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9989 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9990 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9991 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9992 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9993 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
9994 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9995 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
9996 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9997 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
9998 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9999 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10000 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10001 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10002 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10003 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10004 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10005 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10006 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10007 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10008 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10010 /* Options which specify Application Specific Extensions (ASEs). */
10011 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10012 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10013 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10014 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10015 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10016 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10017 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10018 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10019 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10020 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10021 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10022 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10023 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10025 /* Old-style architecture options. Don't add more of these. */
10026 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10027 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10028 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10029 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10030 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10031 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10032 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10033 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10034 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10035 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10036 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10037 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10038 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10039 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10040 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10041 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10042 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10044 /* Options which enable bug fixes. */
10045 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10046 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10047 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10048 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10049 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10050 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10051 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10052 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10053 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10054 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10056 /* Miscellaneous options. */
10057 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10058 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10059 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10060 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10061 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10062 {"break", no_argument
, NULL
, OPTION_BREAK
},
10063 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10064 #define OPTION_EB (OPTION_MISC_BASE + 2)
10065 {"EB", no_argument
, NULL
, OPTION_EB
},
10066 #define OPTION_EL (OPTION_MISC_BASE + 3)
10067 {"EL", no_argument
, NULL
, OPTION_EL
},
10068 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10069 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10070 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10071 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10072 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10073 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10074 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10075 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10076 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10077 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10078 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10079 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10080 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10081 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10082 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10083 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10085 /* ELF-specific options. */
10087 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
10088 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10089 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10090 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10091 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10092 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10093 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10094 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10095 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10096 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10097 #define OPTION_32 (OPTION_ELF_BASE + 4)
10098 {"32", no_argument
, NULL
, OPTION_32
},
10099 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10100 {"n32", no_argument
, NULL
, OPTION_N32
},
10101 #define OPTION_64 (OPTION_ELF_BASE + 6)
10102 {"64", no_argument
, NULL
, OPTION_64
},
10103 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10104 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10105 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10106 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10107 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10108 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10109 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10110 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10111 #endif /* OBJ_ELF */
10113 {NULL
, no_argument
, NULL
, 0}
10115 size_t md_longopts_size
= sizeof (md_longopts
);
10117 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10118 NEW_VALUE. Warn if another value was already specified. Note:
10119 we have to defer parsing the -march and -mtune arguments in order
10120 to handle 'from-abi' correctly, since the ABI might be specified
10121 in a later argument. */
10124 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10126 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10127 as_warn (_("A different %s was already specified, is now %s"),
10128 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10131 *string_ptr
= new_value
;
10135 md_parse_option (int c
, char *arg
)
10139 case OPTION_CONSTRUCT_FLOATS
:
10140 mips_disable_float_construction
= 0;
10143 case OPTION_NO_CONSTRUCT_FLOATS
:
10144 mips_disable_float_construction
= 1;
10156 target_big_endian
= 1;
10160 target_big_endian
= 0;
10164 if (arg
&& arg
[1] == '0')
10174 mips_debug
= atoi (arg
);
10175 /* When the MIPS assembler sees -g or -g2, it does not do
10176 optimizations which limit full symbolic debugging. We take
10177 that to be equivalent to -O0. */
10178 if (mips_debug
== 2)
10183 file_mips_isa
= ISA_MIPS1
;
10187 file_mips_isa
= ISA_MIPS2
;
10191 file_mips_isa
= ISA_MIPS3
;
10195 file_mips_isa
= ISA_MIPS4
;
10199 file_mips_isa
= ISA_MIPS5
;
10202 case OPTION_MIPS32
:
10203 file_mips_isa
= ISA_MIPS32
;
10206 case OPTION_MIPS32R2
:
10207 file_mips_isa
= ISA_MIPS32R2
;
10210 case OPTION_MIPS64R2
:
10211 file_mips_isa
= ISA_MIPS64R2
;
10214 case OPTION_MIPS64
:
10215 file_mips_isa
= ISA_MIPS64
;
10219 mips_set_option_string (&mips_tune_string
, arg
);
10223 mips_set_option_string (&mips_arch_string
, arg
);
10227 mips_set_option_string (&mips_arch_string
, "4650");
10228 mips_set_option_string (&mips_tune_string
, "4650");
10231 case OPTION_NO_M4650
:
10235 mips_set_option_string (&mips_arch_string
, "4010");
10236 mips_set_option_string (&mips_tune_string
, "4010");
10239 case OPTION_NO_M4010
:
10243 mips_set_option_string (&mips_arch_string
, "4100");
10244 mips_set_option_string (&mips_tune_string
, "4100");
10247 case OPTION_NO_M4100
:
10251 mips_set_option_string (&mips_arch_string
, "3900");
10252 mips_set_option_string (&mips_tune_string
, "3900");
10255 case OPTION_NO_M3900
:
10259 mips_opts
.ase_mdmx
= 1;
10262 case OPTION_NO_MDMX
:
10263 mips_opts
.ase_mdmx
= 0;
10266 case OPTION_MIPS16
:
10267 mips_opts
.mips16
= 1;
10268 mips_no_prev_insn (FALSE
);
10271 case OPTION_NO_MIPS16
:
10272 mips_opts
.mips16
= 0;
10273 mips_no_prev_insn (FALSE
);
10276 case OPTION_MIPS3D
:
10277 mips_opts
.ase_mips3d
= 1;
10280 case OPTION_NO_MIPS3D
:
10281 mips_opts
.ase_mips3d
= 0;
10284 case OPTION_FIX_VR4120
:
10285 mips_fix_vr4120
= 1;
10288 case OPTION_NO_FIX_VR4120
:
10289 mips_fix_vr4120
= 0;
10292 case OPTION_RELAX_BRANCH
:
10293 mips_relax_branch
= 1;
10296 case OPTION_NO_RELAX_BRANCH
:
10297 mips_relax_branch
= 0;
10301 /* When generating ELF code, we permit -KPIC and -call_shared to
10302 select SVR4_PIC, and -non_shared to select no PIC. This is
10303 intended to be compatible with Irix 5. */
10304 case OPTION_CALL_SHARED
:
10305 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10307 as_bad (_("-call_shared is supported only for ELF format"));
10310 mips_pic
= SVR4_PIC
;
10311 mips_abicalls
= TRUE
;
10312 if (g_switch_seen
&& g_switch_value
!= 0)
10314 as_bad (_("-G may not be used with SVR4 PIC code"));
10317 g_switch_value
= 0;
10320 case OPTION_NON_SHARED
:
10321 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10323 as_bad (_("-non_shared is supported only for ELF format"));
10327 mips_abicalls
= FALSE
;
10330 /* The -xgot option tells the assembler to use 32 offsets when
10331 accessing the got in SVR4_PIC mode. It is for Irix
10336 #endif /* OBJ_ELF */
10339 if (mips_pic
== SVR4_PIC
)
10341 as_bad (_("-G may not be used with SVR4 PIC code"));
10345 g_switch_value
= atoi (arg
);
10350 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10353 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10355 as_bad (_("-32 is supported for ELF format only"));
10358 mips_abi
= O32_ABI
;
10362 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10364 as_bad (_("-n32 is supported for ELF format only"));
10367 mips_abi
= N32_ABI
;
10371 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10373 as_bad (_("-64 is supported for ELF format only"));
10376 mips_abi
= N64_ABI
;
10377 if (! support_64bit_objects())
10378 as_fatal (_("No compiled in support for 64 bit object file format"));
10380 #endif /* OBJ_ELF */
10383 file_mips_gp32
= 1;
10387 file_mips_gp32
= 0;
10391 file_mips_fp32
= 1;
10395 file_mips_fp32
= 0;
10400 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10402 as_bad (_("-mabi is supported for ELF format only"));
10405 if (strcmp (arg
, "32") == 0)
10406 mips_abi
= O32_ABI
;
10407 else if (strcmp (arg
, "o64") == 0)
10408 mips_abi
= O64_ABI
;
10409 else if (strcmp (arg
, "n32") == 0)
10410 mips_abi
= N32_ABI
;
10411 else if (strcmp (arg
, "64") == 0)
10413 mips_abi
= N64_ABI
;
10414 if (! support_64bit_objects())
10415 as_fatal (_("No compiled in support for 64 bit object file "
10418 else if (strcmp (arg
, "eabi") == 0)
10419 mips_abi
= EABI_ABI
;
10422 as_fatal (_("invalid abi -mabi=%s"), arg
);
10426 #endif /* OBJ_ELF */
10428 case OPTION_M7000_HILO_FIX
:
10429 mips_7000_hilo_fix
= TRUE
;
10432 case OPTION_MNO_7000_HILO_FIX
:
10433 mips_7000_hilo_fix
= FALSE
;
10437 case OPTION_MDEBUG
:
10438 mips_flag_mdebug
= TRUE
;
10441 case OPTION_NO_MDEBUG
:
10442 mips_flag_mdebug
= FALSE
;
10446 mips_flag_pdr
= TRUE
;
10449 case OPTION_NO_PDR
:
10450 mips_flag_pdr
= FALSE
;
10452 #endif /* OBJ_ELF */
10461 /* Set up globals to generate code for the ISA or processor
10462 described by INFO. */
10465 mips_set_architecture (const struct mips_cpu_info
*info
)
10469 file_mips_arch
= info
->cpu
;
10470 mips_opts
.arch
= info
->cpu
;
10471 mips_opts
.isa
= info
->isa
;
10476 /* Likewise for tuning. */
10479 mips_set_tune (const struct mips_cpu_info
*info
)
10482 mips_tune
= info
->cpu
;
10487 mips_after_parse_args (void)
10489 const struct mips_cpu_info
*arch_info
= 0;
10490 const struct mips_cpu_info
*tune_info
= 0;
10492 /* GP relative stuff not working for PE */
10493 if (strncmp (TARGET_OS
, "pe", 2) == 0
10494 && g_switch_value
!= 0)
10497 as_bad (_("-G not supported in this configuration."));
10498 g_switch_value
= 0;
10501 if (mips_abi
== NO_ABI
)
10502 mips_abi
= MIPS_DEFAULT_ABI
;
10504 /* The following code determines the architecture and register size.
10505 Similar code was added to GCC 3.3 (see override_options() in
10506 config/mips/mips.c). The GAS and GCC code should be kept in sync
10507 as much as possible. */
10509 if (mips_arch_string
!= 0)
10510 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10512 if (file_mips_isa
!= ISA_UNKNOWN
)
10514 /* Handle -mipsN. At this point, file_mips_isa contains the
10515 ISA level specified by -mipsN, while arch_info->isa contains
10516 the -march selection (if any). */
10517 if (arch_info
!= 0)
10519 /* -march takes precedence over -mipsN, since it is more descriptive.
10520 There's no harm in specifying both as long as the ISA levels
10522 if (file_mips_isa
!= arch_info
->isa
)
10523 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10524 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10525 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10528 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10531 if (arch_info
== 0)
10532 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10534 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10535 as_bad ("-march=%s is not compatible with the selected ABI",
10538 mips_set_architecture (arch_info
);
10540 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10541 if (mips_tune_string
!= 0)
10542 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10544 if (tune_info
== 0)
10545 mips_set_tune (arch_info
);
10547 mips_set_tune (tune_info
);
10549 if (file_mips_gp32
>= 0)
10551 /* The user specified the size of the integer registers. Make sure
10552 it agrees with the ABI and ISA. */
10553 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10554 as_bad (_("-mgp64 used with a 32-bit processor"));
10555 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10556 as_bad (_("-mgp32 used with a 64-bit ABI"));
10557 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10558 as_bad (_("-mgp64 used with a 32-bit ABI"));
10562 /* Infer the integer register size from the ABI and processor.
10563 Restrict ourselves to 32-bit registers if that's all the
10564 processor has, or if the ABI cannot handle 64-bit registers. */
10565 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10566 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10569 /* ??? GAS treats single-float processors as though they had 64-bit
10570 float registers (although it complains when double-precision
10571 instructions are used). As things stand, saying they have 32-bit
10572 registers would lead to spurious "register must be even" messages.
10573 So here we assume float registers are always the same size as
10574 integer ones, unless the user says otherwise. */
10575 if (file_mips_fp32
< 0)
10576 file_mips_fp32
= file_mips_gp32
;
10578 /* End of GCC-shared inference code. */
10580 /* This flag is set when we have a 64-bit capable CPU but use only
10581 32-bit wide registers. Note that EABI does not use it. */
10582 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10583 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10584 || mips_abi
== O32_ABI
))
10585 mips_32bitmode
= 1;
10587 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10588 as_bad (_("trap exception not supported at ISA 1"));
10590 /* If the selected architecture includes support for ASEs, enable
10591 generation of code for them. */
10592 if (mips_opts
.mips16
== -1)
10593 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10594 if (mips_opts
.ase_mips3d
== -1)
10595 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10596 if (mips_opts
.ase_mdmx
== -1)
10597 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10599 file_mips_isa
= mips_opts
.isa
;
10600 file_ase_mips16
= mips_opts
.mips16
;
10601 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10602 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10603 mips_opts
.gp32
= file_mips_gp32
;
10604 mips_opts
.fp32
= file_mips_fp32
;
10606 if (mips_flag_mdebug
< 0)
10608 #ifdef OBJ_MAYBE_ECOFF
10609 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10610 mips_flag_mdebug
= 1;
10612 #endif /* OBJ_MAYBE_ECOFF */
10613 mips_flag_mdebug
= 0;
10618 mips_init_after_args (void)
10620 /* initialize opcodes */
10621 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10622 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10626 md_pcrel_from (fixS
*fixP
)
10628 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10629 switch (fixP
->fx_r_type
)
10631 case BFD_RELOC_16_PCREL_S2
:
10632 case BFD_RELOC_MIPS_JMP
:
10633 /* Return the address of the delay slot. */
10640 /* This is called before the symbol table is processed. In order to
10641 work with gcc when using mips-tfile, we must keep all local labels.
10642 However, in other cases, we want to discard them. If we were
10643 called with -g, but we didn't see any debugging information, it may
10644 mean that gcc is smuggling debugging information through to
10645 mips-tfile, in which case we must generate all local labels. */
10648 mips_frob_file_before_adjust (void)
10650 #ifndef NO_ECOFF_DEBUGGING
10651 if (ECOFF_DEBUGGING
10653 && ! ecoff_debugging_seen
)
10654 flag_keep_locals
= 1;
10658 /* Sort any unmatched HI16_S relocs so that they immediately precede
10659 the corresponding LO reloc. This is called before md_apply_fix3 and
10660 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10661 explicit use of the %hi modifier. */
10664 mips_frob_file (void)
10666 struct mips_hi_fixup
*l
;
10668 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10670 segment_info_type
*seginfo
;
10673 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10675 /* If a GOT16 relocation turns out to be against a global symbol,
10676 there isn't supposed to be a matching LO. */
10677 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10678 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10681 /* Check quickly whether the next fixup happens to be a matching %lo. */
10682 if (fixup_has_matching_lo_p (l
->fixp
))
10685 /* Look through the fixups for this segment for a matching %lo.
10686 When we find one, move the %hi just in front of it. We do
10687 this in two passes. In the first pass, we try to find a
10688 unique %lo. In the second pass, we permit multiple %hi
10689 relocs for a single %lo (this is a GNU extension). */
10690 seginfo
= seg_info (l
->seg
);
10691 for (pass
= 0; pass
< 2; pass
++)
10696 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10698 /* Check whether this is a %lo fixup which matches l->fixp. */
10699 if (f
->fx_r_type
== BFD_RELOC_LO16
10700 && f
->fx_addsy
== l
->fixp
->fx_addsy
10701 && f
->fx_offset
== l
->fixp
->fx_offset
10704 || !reloc_needs_lo_p (prev
->fx_r_type
)
10705 || !fixup_has_matching_lo_p (prev
)))
10709 /* Move l->fixp before f. */
10710 for (pf
= &seginfo
->fix_root
;
10712 pf
= &(*pf
)->fx_next
)
10713 assert (*pf
!= NULL
);
10715 *pf
= l
->fixp
->fx_next
;
10717 l
->fixp
->fx_next
= f
;
10719 seginfo
->fix_root
= l
->fixp
;
10721 prev
->fx_next
= l
->fixp
;
10732 #if 0 /* GCC code motion plus incomplete dead code elimination
10733 can leave a %hi without a %lo. */
10735 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10736 _("Unmatched %%hi reloc"));
10742 /* We may have combined relocations without symbols in the N32/N64 ABI.
10743 We have to prevent gas from dropping them. */
10746 mips_force_relocation (fixS
*fixp
)
10748 if (generic_force_reloc (fixp
))
10752 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10753 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10754 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10755 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10761 /* This hook is called before a fix is simplified. We don't really
10762 decide whether to skip a fix here. Rather, we turn global symbols
10763 used as branch targets into local symbols, such that they undergo
10764 simplification. We can only do this if the symbol is defined and
10765 it is in the same section as the branch. If this doesn't hold, we
10766 emit a better error message than just saying the relocation is not
10767 valid for the selected object format.
10769 FIXP is the fix-up we're going to try to simplify, SEG is the
10770 segment in which the fix up occurs. The return value should be
10771 non-zero to indicate the fix-up is valid for further
10772 simplifications. */
10775 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10777 /* There's a lot of discussion on whether it should be possible to
10778 use R_MIPS_PC16 to represent branch relocations. The outcome
10779 seems to be that it can, but gas/bfd are very broken in creating
10780 RELA relocations for this, so for now we only accept branches to
10781 symbols in the same section. Anything else is of dubious value,
10782 since there's no guarantee that at link time the symbol would be
10783 in range. Even for branches to local symbols this is arguably
10784 wrong, since it we assume the symbol is not going to be
10785 overridden, which should be possible per ELF library semantics,
10786 but then, there isn't a dynamic relocation that could be used to
10787 this effect, and the target would likely be out of range as well.
10789 Unfortunately, it seems that there is too much code out there
10790 that relies on branches to symbols that are global to be resolved
10791 as if they were local, like the IRIX tools do, so we do it as
10792 well, but with a warning so that people are reminded to fix their
10793 code. If we ever get back to using R_MIPS_PC16 for branch
10794 targets, this entire block should go away (and probably the
10795 whole function). */
10797 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10798 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10799 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10800 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10803 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10806 _("Cannot branch to undefined symbol."));
10807 /* Avoid any further errors about this fixup. */
10810 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10813 _("Cannot branch to symbol in another section."));
10816 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10818 symbolS
*sym
= fixP
->fx_addsy
;
10820 if (mips_pic
== SVR4_PIC
)
10821 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10822 _("Pretending global symbol used as branch target is local."));
10824 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10825 S_GET_SEGMENT (sym
),
10827 symbol_get_frag (sym
));
10828 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10829 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10830 assert (symbol_resolved_p (sym
));
10831 symbol_mark_resolved (fixP
->fx_addsy
);
10838 /* Apply a fixup to the object file. */
10841 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10845 static int previous_fx_r_type
= 0;
10846 reloc_howto_type
*howto
;
10848 /* We ignore generic BFD relocations we don't know about. */
10849 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10853 assert (fixP
->fx_size
== 4
10854 || fixP
->fx_r_type
== BFD_RELOC_16
10855 || fixP
->fx_r_type
== BFD_RELOC_64
10856 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10857 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10858 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10859 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10861 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10863 /* We are not done if this is a composite relocation to set up gp. */
10864 assert (! fixP
->fx_pcrel
);
10865 if (fixP
->fx_addsy
== NULL
10866 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10867 || (fixP
->fx_r_type
== BFD_RELOC_64
10868 && (previous_fx_r_type
== BFD_RELOC_GPREL32
10869 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
10870 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
10871 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
10872 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
10874 previous_fx_r_type
= fixP
->fx_r_type
;
10876 switch (fixP
->fx_r_type
)
10878 case BFD_RELOC_MIPS_JMP
:
10879 case BFD_RELOC_MIPS_SHIFT5
:
10880 case BFD_RELOC_MIPS_SHIFT6
:
10881 case BFD_RELOC_MIPS_GOT_DISP
:
10882 case BFD_RELOC_MIPS_GOT_PAGE
:
10883 case BFD_RELOC_MIPS_GOT_OFST
:
10884 case BFD_RELOC_MIPS_SUB
:
10885 case BFD_RELOC_MIPS_INSERT_A
:
10886 case BFD_RELOC_MIPS_INSERT_B
:
10887 case BFD_RELOC_MIPS_DELETE
:
10888 case BFD_RELOC_MIPS_HIGHEST
:
10889 case BFD_RELOC_MIPS_HIGHER
:
10890 case BFD_RELOC_MIPS_SCN_DISP
:
10891 case BFD_RELOC_MIPS_REL16
:
10892 case BFD_RELOC_MIPS_RELGOT
:
10893 case BFD_RELOC_MIPS_JALR
:
10894 case BFD_RELOC_HI16
:
10895 case BFD_RELOC_HI16_S
:
10896 case BFD_RELOC_GPREL16
:
10897 case BFD_RELOC_MIPS_LITERAL
:
10898 case BFD_RELOC_MIPS_CALL16
:
10899 case BFD_RELOC_MIPS_GOT16
:
10900 case BFD_RELOC_GPREL32
:
10901 case BFD_RELOC_MIPS_GOT_HI16
:
10902 case BFD_RELOC_MIPS_GOT_LO16
:
10903 case BFD_RELOC_MIPS_CALL_HI16
:
10904 case BFD_RELOC_MIPS_CALL_LO16
:
10905 case BFD_RELOC_MIPS16_GPREL
:
10906 assert (! fixP
->fx_pcrel
);
10907 /* Nothing needed to do. The value comes from the reloc entry */
10910 case BFD_RELOC_MIPS16_JMP
:
10911 /* We currently always generate a reloc against a symbol, which
10912 means that we don't want an addend even if the symbol is
10918 /* This is handled like BFD_RELOC_32, but we output a sign
10919 extended value if we are only 32 bits. */
10922 if (8 <= sizeof (valueT
))
10923 md_number_to_chars (buf
, *valP
, 8);
10928 if ((*valP
& 0x80000000) != 0)
10932 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
10934 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
10940 case BFD_RELOC_RVA
:
10942 /* If we are deleting this reloc entry, we must fill in the
10943 value now. This can happen if we have a .word which is not
10944 resolved when it appears but is later defined. */
10946 md_number_to_chars (buf
, *valP
, 4);
10950 /* If we are deleting this reloc entry, we must fill in the
10952 assert (fixP
->fx_size
== 2);
10954 md_number_to_chars (buf
, *valP
, 2);
10957 case BFD_RELOC_LO16
:
10958 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
10959 may be safe to remove, but if so it's not obvious. */
10960 /* When handling an embedded PIC switch statement, we can wind
10961 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10964 if (*valP
+ 0x8000 > 0xffff)
10965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10966 _("relocation overflow"));
10967 if (target_big_endian
)
10969 md_number_to_chars (buf
, *valP
, 2);
10973 case BFD_RELOC_16_PCREL_S2
:
10974 if ((*valP
& 0x3) != 0)
10975 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10976 _("Branch to odd address (%lx)"), (long) *valP
);
10979 * We need to save the bits in the instruction since fixup_segment()
10980 * might be deleting the relocation entry (i.e., a branch within
10981 * the current segment).
10983 if (! fixP
->fx_done
)
10986 /* update old instruction data */
10987 if (target_big_endian
)
10988 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10990 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10992 if (*valP
+ 0x20000 <= 0x3ffff)
10994 insn
|= (*valP
>> 2) & 0xffff;
10995 md_number_to_chars (buf
, insn
, 4);
10997 else if (mips_pic
== NO_PIC
10999 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11000 && (fixP
->fx_frag
->fr_address
11001 < text_section
->vma
+ text_section
->_raw_size
)
11002 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11003 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11004 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11006 /* The branch offset is too large. If this is an
11007 unconditional branch, and we are not generating PIC code,
11008 we can convert it to an absolute jump instruction. */
11009 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11010 insn
= 0x0c000000; /* jal */
11012 insn
= 0x08000000; /* j */
11013 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11015 fixP
->fx_addsy
= section_symbol (text_section
);
11016 *valP
+= md_pcrel_from (fixP
);
11017 md_number_to_chars (buf
, insn
, 4);
11021 /* If we got here, we have branch-relaxation disabled,
11022 and there's nothing we can do to fix this instruction
11023 without turning it into a longer sequence. */
11024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11025 _("Branch out of range"));
11029 case BFD_RELOC_VTABLE_INHERIT
:
11032 && !S_IS_DEFINED (fixP
->fx_addsy
)
11033 && !S_IS_WEAK (fixP
->fx_addsy
))
11034 S_SET_WEAK (fixP
->fx_addsy
);
11037 case BFD_RELOC_VTABLE_ENTRY
:
11045 /* Remember value for tc_gen_reloc. */
11046 fixP
->fx_addnumber
= *valP
;
11051 printInsn (unsigned long oc
)
11053 const struct mips_opcode
*p
;
11054 int treg
, sreg
, dreg
, shamt
;
11059 for (i
= 0; i
< NUMOPCODES
; ++i
)
11061 p
= &mips_opcodes
[i
];
11062 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11064 printf ("%08lx %s\t", oc
, p
->name
);
11065 treg
= (oc
>> 16) & 0x1f;
11066 sreg
= (oc
>> 21) & 0x1f;
11067 dreg
= (oc
>> 11) & 0x1f;
11068 shamt
= (oc
>> 6) & 0x1f;
11070 for (args
= p
->args
;; ++args
)
11081 printf ("%c", *args
);
11085 assert (treg
== sreg
);
11086 printf ("$%d,$%d", treg
, sreg
);
11091 printf ("$%d", dreg
);
11096 printf ("$%d", treg
);
11100 printf ("0x%x", treg
);
11105 printf ("$%d", sreg
);
11109 printf ("0x%08lx", oc
& 0x1ffffff);
11116 printf ("%d", imm
);
11121 printf ("$%d", shamt
);
11132 printf (_("%08lx UNDEFINED\n"), oc
);
11143 name
= input_line_pointer
;
11144 c
= get_symbol_end ();
11145 p
= (symbolS
*) symbol_find_or_make (name
);
11146 *input_line_pointer
= c
;
11150 /* Align the current frag to a given power of two. The MIPS assembler
11151 also automatically adjusts any preceding label. */
11154 mips_align (int to
, int fill
, symbolS
*label
)
11156 mips_emit_delays (FALSE
);
11157 frag_align (to
, fill
, 0);
11158 record_alignment (now_seg
, to
);
11161 assert (S_GET_SEGMENT (label
) == now_seg
);
11162 symbol_set_frag (label
, frag_now
);
11163 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11167 /* Align to a given power of two. .align 0 turns off the automatic
11168 alignment used by the data creating pseudo-ops. */
11171 s_align (int x ATTRIBUTE_UNUSED
)
11174 register long temp_fill
;
11175 long max_alignment
= 15;
11179 o Note that the assembler pulls down any immediately preceding label
11180 to the aligned address.
11181 o It's not documented but auto alignment is reinstated by
11182 a .align pseudo instruction.
11183 o Note also that after auto alignment is turned off the mips assembler
11184 issues an error on attempt to assemble an improperly aligned data item.
11189 temp
= get_absolute_expression ();
11190 if (temp
> max_alignment
)
11191 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11194 as_warn (_("Alignment negative: 0 assumed."));
11197 if (*input_line_pointer
== ',')
11199 ++input_line_pointer
;
11200 temp_fill
= get_absolute_expression ();
11207 mips_align (temp
, (int) temp_fill
,
11208 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11215 demand_empty_rest_of_line ();
11219 mips_flush_pending_output (void)
11221 mips_emit_delays (FALSE
);
11222 mips_clear_insn_labels ();
11226 s_change_sec (int sec
)
11231 /* The ELF backend needs to know that we are changing sections, so
11232 that .previous works correctly. We could do something like check
11233 for an obj_section_change_hook macro, but that might be confusing
11234 as it would not be appropriate to use it in the section changing
11235 functions in read.c, since obj-elf.c intercepts those. FIXME:
11236 This should be cleaner, somehow. */
11237 obj_elf_section_change_hook ();
11240 mips_emit_delays (FALSE
);
11250 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11251 demand_empty_rest_of_line ();
11255 seg
= subseg_new (RDATA_SECTION_NAME
,
11256 (subsegT
) get_absolute_expression ());
11257 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11259 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11260 | SEC_READONLY
| SEC_RELOC
11262 if (strcmp (TARGET_OS
, "elf") != 0)
11263 record_alignment (seg
, 4);
11265 demand_empty_rest_of_line ();
11269 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11270 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11272 bfd_set_section_flags (stdoutput
, seg
,
11273 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11274 if (strcmp (TARGET_OS
, "elf") != 0)
11275 record_alignment (seg
, 4);
11277 demand_empty_rest_of_line ();
11285 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11288 char *section_name
;
11293 int section_entry_size
;
11294 int section_alignment
;
11296 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11299 section_name
= input_line_pointer
;
11300 c
= get_symbol_end ();
11302 next_c
= *(input_line_pointer
+ 1);
11304 /* Do we have .section Name<,"flags">? */
11305 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11307 /* just after name is now '\0'. */
11308 *input_line_pointer
= c
;
11309 input_line_pointer
= section_name
;
11310 obj_elf_section (ignore
);
11313 input_line_pointer
++;
11315 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11317 section_type
= get_absolute_expression ();
11320 if (*input_line_pointer
++ == ',')
11321 section_flag
= get_absolute_expression ();
11324 if (*input_line_pointer
++ == ',')
11325 section_entry_size
= get_absolute_expression ();
11327 section_entry_size
= 0;
11328 if (*input_line_pointer
++ == ',')
11329 section_alignment
= get_absolute_expression ();
11331 section_alignment
= 0;
11333 section_name
= xstrdup (section_name
);
11335 /* When using the generic form of .section (as implemented by obj-elf.c),
11336 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11337 traditionally had to fall back on the more common @progbits instead.
11339 There's nothing really harmful in this, since bfd will correct
11340 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11341 means that, for backwards compatibiltiy, the special_section entries
11342 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11344 Even so, we shouldn't force users of the MIPS .section syntax to
11345 incorrectly label the sections as SHT_PROGBITS. The best compromise
11346 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11347 generic type-checking code. */
11348 if (section_type
== SHT_MIPS_DWARF
)
11349 section_type
= SHT_PROGBITS
;
11351 obj_elf_change_section (section_name
, section_type
, section_flag
,
11352 section_entry_size
, 0, 0, 0);
11354 if (now_seg
->name
!= section_name
)
11355 free (section_name
);
11356 #endif /* OBJ_ELF */
11360 mips_enable_auto_align (void)
11366 s_cons (int log_size
)
11370 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11371 mips_emit_delays (FALSE
);
11372 if (log_size
> 0 && auto_align
)
11373 mips_align (log_size
, 0, label
);
11374 mips_clear_insn_labels ();
11375 cons (1 << log_size
);
11379 s_float_cons (int type
)
11383 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11385 mips_emit_delays (FALSE
);
11390 mips_align (3, 0, label
);
11392 mips_align (2, 0, label
);
11395 mips_clear_insn_labels ();
11400 /* Handle .globl. We need to override it because on Irix 5 you are
11403 where foo is an undefined symbol, to mean that foo should be
11404 considered to be the address of a function. */
11407 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11414 name
= input_line_pointer
;
11415 c
= get_symbol_end ();
11416 symbolP
= symbol_find_or_make (name
);
11417 *input_line_pointer
= c
;
11418 SKIP_WHITESPACE ();
11420 /* On Irix 5, every global symbol that is not explicitly labelled as
11421 being a function is apparently labelled as being an object. */
11424 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11429 secname
= input_line_pointer
;
11430 c
= get_symbol_end ();
11431 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11433 as_bad (_("%s: no such section"), secname
);
11434 *input_line_pointer
= c
;
11436 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11437 flag
= BSF_FUNCTION
;
11440 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11442 S_SET_EXTERNAL (symbolP
);
11443 demand_empty_rest_of_line ();
11447 s_option (int x ATTRIBUTE_UNUSED
)
11452 opt
= input_line_pointer
;
11453 c
= get_symbol_end ();
11457 /* FIXME: What does this mean? */
11459 else if (strncmp (opt
, "pic", 3) == 0)
11463 i
= atoi (opt
+ 3);
11468 mips_pic
= SVR4_PIC
;
11469 mips_abicalls
= TRUE
;
11472 as_bad (_(".option pic%d not supported"), i
);
11474 if (mips_pic
== SVR4_PIC
)
11476 if (g_switch_seen
&& g_switch_value
!= 0)
11477 as_warn (_("-G may not be used with SVR4 PIC code"));
11478 g_switch_value
= 0;
11479 bfd_set_gp_size (stdoutput
, 0);
11483 as_warn (_("Unrecognized option \"%s\""), opt
);
11485 *input_line_pointer
= c
;
11486 demand_empty_rest_of_line ();
11489 /* This structure is used to hold a stack of .set values. */
11491 struct mips_option_stack
11493 struct mips_option_stack
*next
;
11494 struct mips_set_options options
;
11497 static struct mips_option_stack
*mips_opts_stack
;
11499 /* Handle the .set pseudo-op. */
11502 s_mipsset (int x ATTRIBUTE_UNUSED
)
11504 char *name
= input_line_pointer
, ch
;
11506 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11507 ++input_line_pointer
;
11508 ch
= *input_line_pointer
;
11509 *input_line_pointer
= '\0';
11511 if (strcmp (name
, "reorder") == 0)
11513 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11515 /* If we still have pending nops, we can discard them. The
11516 usual nop handling will insert any that are still
11518 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11519 * (mips_opts
.mips16
? 2 : 4));
11520 prev_nop_frag
= NULL
;
11522 mips_opts
.noreorder
= 0;
11524 else if (strcmp (name
, "noreorder") == 0)
11526 mips_emit_delays (TRUE
);
11527 mips_opts
.noreorder
= 1;
11528 mips_any_noreorder
= 1;
11530 else if (strcmp (name
, "at") == 0)
11532 mips_opts
.noat
= 0;
11534 else if (strcmp (name
, "noat") == 0)
11536 mips_opts
.noat
= 1;
11538 else if (strcmp (name
, "macro") == 0)
11540 mips_opts
.warn_about_macros
= 0;
11542 else if (strcmp (name
, "nomacro") == 0)
11544 if (mips_opts
.noreorder
== 0)
11545 as_bad (_("`noreorder' must be set before `nomacro'"));
11546 mips_opts
.warn_about_macros
= 1;
11548 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11550 mips_opts
.nomove
= 0;
11552 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11554 mips_opts
.nomove
= 1;
11556 else if (strcmp (name
, "bopt") == 0)
11558 mips_opts
.nobopt
= 0;
11560 else if (strcmp (name
, "nobopt") == 0)
11562 mips_opts
.nobopt
= 1;
11564 else if (strcmp (name
, "mips16") == 0
11565 || strcmp (name
, "MIPS-16") == 0)
11566 mips_opts
.mips16
= 1;
11567 else if (strcmp (name
, "nomips16") == 0
11568 || strcmp (name
, "noMIPS-16") == 0)
11569 mips_opts
.mips16
= 0;
11570 else if (strcmp (name
, "mips3d") == 0)
11571 mips_opts
.ase_mips3d
= 1;
11572 else if (strcmp (name
, "nomips3d") == 0)
11573 mips_opts
.ase_mips3d
= 0;
11574 else if (strcmp (name
, "mdmx") == 0)
11575 mips_opts
.ase_mdmx
= 1;
11576 else if (strcmp (name
, "nomdmx") == 0)
11577 mips_opts
.ase_mdmx
= 0;
11578 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11582 /* Permit the user to change the ISA and architecture on the fly.
11583 Needless to say, misuse can cause serious problems. */
11584 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11587 mips_opts
.isa
= file_mips_isa
;
11588 mips_opts
.arch
= file_mips_arch
;
11590 else if (strncmp (name
, "arch=", 5) == 0)
11592 const struct mips_cpu_info
*p
;
11594 p
= mips_parse_cpu("internal use", name
+ 5);
11596 as_bad (_("unknown architecture %s"), name
+ 5);
11599 mips_opts
.arch
= p
->cpu
;
11600 mips_opts
.isa
= p
->isa
;
11603 else if (strncmp (name
, "mips", 4) == 0)
11605 const struct mips_cpu_info
*p
;
11607 p
= mips_parse_cpu("internal use", name
);
11609 as_bad (_("unknown ISA level %s"), name
+ 4);
11612 mips_opts
.arch
= p
->cpu
;
11613 mips_opts
.isa
= p
->isa
;
11617 as_bad (_("unknown ISA or architecture %s"), name
);
11619 switch (mips_opts
.isa
)
11627 mips_opts
.gp32
= 1;
11628 mips_opts
.fp32
= 1;
11635 mips_opts
.gp32
= 0;
11636 mips_opts
.fp32
= 0;
11639 as_bad (_("unknown ISA level %s"), name
+ 4);
11644 mips_opts
.gp32
= file_mips_gp32
;
11645 mips_opts
.fp32
= file_mips_fp32
;
11648 else if (strcmp (name
, "autoextend") == 0)
11649 mips_opts
.noautoextend
= 0;
11650 else if (strcmp (name
, "noautoextend") == 0)
11651 mips_opts
.noautoextend
= 1;
11652 else if (strcmp (name
, "push") == 0)
11654 struct mips_option_stack
*s
;
11656 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11657 s
->next
= mips_opts_stack
;
11658 s
->options
= mips_opts
;
11659 mips_opts_stack
= s
;
11661 else if (strcmp (name
, "pop") == 0)
11663 struct mips_option_stack
*s
;
11665 s
= mips_opts_stack
;
11667 as_bad (_(".set pop with no .set push"));
11670 /* If we're changing the reorder mode we need to handle
11671 delay slots correctly. */
11672 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11673 mips_emit_delays (TRUE
);
11674 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11676 if (prev_nop_frag
!= NULL
)
11678 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11679 * (mips_opts
.mips16
? 2 : 4));
11680 prev_nop_frag
= NULL
;
11684 mips_opts
= s
->options
;
11685 mips_opts_stack
= s
->next
;
11691 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11693 *input_line_pointer
= ch
;
11694 demand_empty_rest_of_line ();
11697 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11698 .option pic2. It means to generate SVR4 PIC calls. */
11701 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11703 mips_pic
= SVR4_PIC
;
11704 mips_abicalls
= TRUE
;
11706 if (g_switch_seen
&& g_switch_value
!= 0)
11707 as_warn (_("-G may not be used with SVR4 PIC code"));
11708 g_switch_value
= 0;
11710 bfd_set_gp_size (stdoutput
, 0);
11711 demand_empty_rest_of_line ();
11714 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11715 PIC code. It sets the $gp register for the function based on the
11716 function address, which is in the register named in the argument.
11717 This uses a relocation against _gp_disp, which is handled specially
11718 by the linker. The result is:
11719 lui $gp,%hi(_gp_disp)
11720 addiu $gp,$gp,%lo(_gp_disp)
11721 addu $gp,$gp,.cpload argument
11722 The .cpload argument is normally $25 == $t9. */
11725 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11729 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11730 .cpload is ignored. */
11731 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11737 /* .cpload should be in a .set noreorder section. */
11738 if (mips_opts
.noreorder
== 0)
11739 as_warn (_(".cpload not in noreorder section"));
11741 ex
.X_op
= O_symbol
;
11742 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11743 ex
.X_op_symbol
= NULL
;
11744 ex
.X_add_number
= 0;
11746 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11747 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11750 macro_build_lui (&ex
, mips_gp_register
);
11751 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11752 mips_gp_register
, BFD_RELOC_LO16
);
11753 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11754 mips_gp_register
, tc_get_register (0));
11757 demand_empty_rest_of_line ();
11760 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11761 .cpsetup $reg1, offset|$reg2, label
11763 If offset is given, this results in:
11764 sd $gp, offset($sp)
11765 lui $gp, %hi(%neg(%gp_rel(label)))
11766 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11767 daddu $gp, $gp, $reg1
11769 If $reg2 is given, this results in:
11770 daddu $reg2, $gp, $0
11771 lui $gp, %hi(%neg(%gp_rel(label)))
11772 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11773 daddu $gp, $gp, $reg1
11774 $reg1 is normally $25 == $t9. */
11776 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11778 expressionS ex_off
;
11779 expressionS ex_sym
;
11783 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11784 We also need NewABI support. */
11785 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11791 reg1
= tc_get_register (0);
11792 SKIP_WHITESPACE ();
11793 if (*input_line_pointer
!= ',')
11795 as_bad (_("missing argument separator ',' for .cpsetup"));
11799 ++input_line_pointer
;
11800 SKIP_WHITESPACE ();
11801 if (*input_line_pointer
== '$')
11803 mips_cpreturn_register
= tc_get_register (0);
11804 mips_cpreturn_offset
= -1;
11808 mips_cpreturn_offset
= get_absolute_expression ();
11809 mips_cpreturn_register
= -1;
11811 SKIP_WHITESPACE ();
11812 if (*input_line_pointer
!= ',')
11814 as_bad (_("missing argument separator ',' for .cpsetup"));
11818 ++input_line_pointer
;
11819 SKIP_WHITESPACE ();
11820 expression (&ex_sym
);
11823 if (mips_cpreturn_register
== -1)
11825 ex_off
.X_op
= O_constant
;
11826 ex_off
.X_add_symbol
= NULL
;
11827 ex_off
.X_op_symbol
= NULL
;
11828 ex_off
.X_add_number
= mips_cpreturn_offset
;
11830 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11831 BFD_RELOC_LO16
, SP
);
11834 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11835 mips_gp_register
, 0);
11837 /* Ensure there's room for the next two instructions, so that `f'
11838 doesn't end up with an address in the wrong frag. */
11841 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
, BFD_RELOC_GPREL16
);
11842 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11843 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11844 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11845 4, NULL
, 0, 0, BFD_RELOC_HI16_S
);
11848 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11849 mips_gp_register
, BFD_RELOC_GPREL16
);
11850 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11851 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11852 fix_new (frag_now
, f
- frag_now
->fr_literal
,
11853 4, NULL
, 0, 0, BFD_RELOC_LO16
);
11855 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11856 mips_gp_register
, reg1
);
11859 demand_empty_rest_of_line ();
11863 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11865 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11866 .cplocal is ignored. */
11867 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11873 mips_gp_register
= tc_get_register (0);
11874 demand_empty_rest_of_line ();
11877 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11878 offset from $sp. The offset is remembered, and after making a PIC
11879 call $gp is restored from that location. */
11882 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11886 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11887 .cprestore is ignored. */
11888 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11894 mips_cprestore_offset
= get_absolute_expression ();
11895 mips_cprestore_valid
= 1;
11897 ex
.X_op
= O_constant
;
11898 ex
.X_add_symbol
= NULL
;
11899 ex
.X_op_symbol
= NULL
;
11900 ex
.X_add_number
= mips_cprestore_offset
;
11903 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11904 SP
, HAVE_64BIT_ADDRESSES
);
11907 demand_empty_rest_of_line ();
11910 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11911 was given in the preceding .cpsetup, it results in:
11912 ld $gp, offset($sp)
11914 If a register $reg2 was given there, it results in:
11915 daddu $gp, $reg2, $0
11918 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11922 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11923 We also need NewABI support. */
11924 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11931 if (mips_cpreturn_register
== -1)
11933 ex
.X_op
= O_constant
;
11934 ex
.X_add_symbol
= NULL
;
11935 ex
.X_op_symbol
= NULL
;
11936 ex
.X_add_number
= mips_cpreturn_offset
;
11938 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11941 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11942 mips_cpreturn_register
, 0);
11945 demand_empty_rest_of_line ();
11948 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11949 code. It sets the offset to use in gp_rel relocations. */
11952 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11954 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11955 We also need NewABI support. */
11956 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11962 mips_gprel_offset
= get_absolute_expression ();
11964 demand_empty_rest_of_line ();
11967 /* Handle the .gpword pseudo-op. This is used when generating PIC
11968 code. It generates a 32 bit GP relative reloc. */
11971 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11977 /* When not generating PIC code, this is treated as .word. */
11978 if (mips_pic
!= SVR4_PIC
)
11984 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11985 mips_emit_delays (TRUE
);
11987 mips_align (2, 0, label
);
11988 mips_clear_insn_labels ();
11992 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11994 as_bad (_("Unsupported use of .gpword"));
11995 ignore_rest_of_line ();
11999 md_number_to_chars (p
, 0, 4);
12000 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12001 BFD_RELOC_GPREL32
);
12003 demand_empty_rest_of_line ();
12007 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12013 /* When not generating PIC code, this is treated as .dword. */
12014 if (mips_pic
!= SVR4_PIC
)
12020 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12021 mips_emit_delays (TRUE
);
12023 mips_align (3, 0, label
);
12024 mips_clear_insn_labels ();
12028 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12030 as_bad (_("Unsupported use of .gpdword"));
12031 ignore_rest_of_line ();
12035 md_number_to_chars (p
, 0, 8);
12036 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12037 BFD_RELOC_GPREL32
);
12039 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12040 ex
.X_op
= O_absent
;
12041 ex
.X_add_symbol
= 0;
12042 ex
.X_add_number
= 0;
12043 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12046 demand_empty_rest_of_line ();
12049 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12050 tables in SVR4 PIC code. */
12053 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12057 /* This is ignored when not generating SVR4 PIC code. */
12058 if (mips_pic
!= SVR4_PIC
)
12064 /* Add $gp to the register named as an argument. */
12066 reg
= tc_get_register (0);
12067 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12070 demand_empty_rest_of_line ();
12073 /* Handle the .insn pseudo-op. This marks instruction labels in
12074 mips16 mode. This permits the linker to handle them specially,
12075 such as generating jalx instructions when needed. We also make
12076 them odd for the duration of the assembly, in order to generate the
12077 right sort of code. We will make them even in the adjust_symtab
12078 routine, while leaving them marked. This is convenient for the
12079 debugger and the disassembler. The linker knows to make them odd
12083 s_insn (int ignore ATTRIBUTE_UNUSED
)
12085 mips16_mark_labels ();
12087 demand_empty_rest_of_line ();
12090 /* Handle a .stabn directive. We need these in order to mark a label
12091 as being a mips16 text label correctly. Sometimes the compiler
12092 will emit a label, followed by a .stabn, and then switch sections.
12093 If the label and .stabn are in mips16 mode, then the label is
12094 really a mips16 text label. */
12097 s_mips_stab (int type
)
12100 mips16_mark_labels ();
12105 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12109 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12116 name
= input_line_pointer
;
12117 c
= get_symbol_end ();
12118 symbolP
= symbol_find_or_make (name
);
12119 S_SET_WEAK (symbolP
);
12120 *input_line_pointer
= c
;
12122 SKIP_WHITESPACE ();
12124 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12126 if (S_IS_DEFINED (symbolP
))
12128 as_bad ("ignoring attempt to redefine symbol %s",
12129 S_GET_NAME (symbolP
));
12130 ignore_rest_of_line ();
12134 if (*input_line_pointer
== ',')
12136 ++input_line_pointer
;
12137 SKIP_WHITESPACE ();
12141 if (exp
.X_op
!= O_symbol
)
12143 as_bad ("bad .weakext directive");
12144 ignore_rest_of_line ();
12147 symbol_set_value_expression (symbolP
, &exp
);
12150 demand_empty_rest_of_line ();
12153 /* Parse a register string into a number. Called from the ECOFF code
12154 to parse .frame. The argument is non-zero if this is the frame
12155 register, so that we can record it in mips_frame_reg. */
12158 tc_get_register (int frame
)
12162 SKIP_WHITESPACE ();
12163 if (*input_line_pointer
++ != '$')
12165 as_warn (_("expected `$'"));
12168 else if (ISDIGIT (*input_line_pointer
))
12170 reg
= get_absolute_expression ();
12171 if (reg
< 0 || reg
>= 32)
12173 as_warn (_("Bad register number"));
12179 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12182 input_line_pointer
+= 2;
12184 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12187 input_line_pointer
+= 2;
12189 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12192 input_line_pointer
+= 2;
12194 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12197 input_line_pointer
+= 2;
12199 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12202 input_line_pointer
+= 2;
12204 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12207 input_line_pointer
+= 3;
12209 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12212 input_line_pointer
+= 3;
12214 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12217 input_line_pointer
+= 4;
12221 as_warn (_("Unrecognized register name"));
12223 while (ISALNUM(*input_line_pointer
))
12224 input_line_pointer
++;
12229 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12230 mips_frame_reg_valid
= 1;
12231 mips_cprestore_valid
= 0;
12237 md_section_align (asection
*seg
, valueT addr
)
12239 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12242 /* We don't need to align ELF sections to the full alignment.
12243 However, Irix 5 may prefer that we align them at least to a 16
12244 byte boundary. We don't bother to align the sections if we are
12245 targeted for an embedded system. */
12246 if (strcmp (TARGET_OS
, "elf") == 0)
12252 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12255 /* Utility routine, called from above as well. If called while the
12256 input file is still being read, it's only an approximation. (For
12257 example, a symbol may later become defined which appeared to be
12258 undefined earlier.) */
12261 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12266 if (g_switch_value
> 0)
12268 const char *symname
;
12271 /* Find out whether this symbol can be referenced off the $gp
12272 register. It can be if it is smaller than the -G size or if
12273 it is in the .sdata or .sbss section. Certain symbols can
12274 not be referenced off the $gp, although it appears as though
12276 symname
= S_GET_NAME (sym
);
12277 if (symname
!= (const char *) NULL
12278 && (strcmp (symname
, "eprol") == 0
12279 || strcmp (symname
, "etext") == 0
12280 || strcmp (symname
, "_gp") == 0
12281 || strcmp (symname
, "edata") == 0
12282 || strcmp (symname
, "_fbss") == 0
12283 || strcmp (symname
, "_fdata") == 0
12284 || strcmp (symname
, "_ftext") == 0
12285 || strcmp (symname
, "end") == 0
12286 || strcmp (symname
, "_gp_disp") == 0))
12288 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12290 #ifndef NO_ECOFF_DEBUGGING
12291 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12292 && (symbol_get_obj (sym
)->ecoff_extern_size
12293 <= g_switch_value
))
12295 /* We must defer this decision until after the whole
12296 file has been read, since there might be a .extern
12297 after the first use of this symbol. */
12298 || (before_relaxing
12299 #ifndef NO_ECOFF_DEBUGGING
12300 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12302 && S_GET_VALUE (sym
) == 0)
12303 || (S_GET_VALUE (sym
) != 0
12304 && S_GET_VALUE (sym
) <= g_switch_value
)))
12308 const char *segname
;
12310 segname
= segment_name (S_GET_SEGMENT (sym
));
12311 assert (strcmp (segname
, ".lit8") != 0
12312 && strcmp (segname
, ".lit4") != 0);
12313 change
= (strcmp (segname
, ".sdata") != 0
12314 && strcmp (segname
, ".sbss") != 0
12315 && strncmp (segname
, ".sdata.", 7) != 0
12316 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12321 /* We are not optimizing for the $gp register. */
12326 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12329 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12332 bfd_boolean linkonce
;
12334 /* Handle the case of a symbol equated to another symbol. */
12335 while (symbol_equated_reloc_p (sym
))
12339 /* It's possible to get a loop here in a badly written
12341 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12347 symsec
= S_GET_SEGMENT (sym
);
12349 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12351 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12353 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12357 /* The GNU toolchain uses an extension for ELF: a section
12358 beginning with the magic string .gnu.linkonce is a linkonce
12360 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12361 sizeof ".gnu.linkonce" - 1) == 0)
12365 /* This must duplicate the test in adjust_reloc_syms. */
12366 return (symsec
!= &bfd_und_section
12367 && symsec
!= &bfd_abs_section
12368 && ! bfd_is_com_section (symsec
)
12371 /* A global or weak symbol is treated as external. */
12372 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12373 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12379 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12380 extended opcode. SEC is the section the frag is in. */
12383 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12386 register const struct mips16_immed_operand
*op
;
12388 int mintiny
, maxtiny
;
12392 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12394 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12397 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12398 op
= mips16_immed_operands
;
12399 while (op
->type
!= type
)
12402 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12407 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12410 maxtiny
= 1 << op
->nbits
;
12415 maxtiny
= (1 << op
->nbits
) - 1;
12420 mintiny
= - (1 << (op
->nbits
- 1));
12421 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12424 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12425 val
= S_GET_VALUE (fragp
->fr_symbol
);
12426 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12432 /* We won't have the section when we are called from
12433 mips_relax_frag. However, we will always have been called
12434 from md_estimate_size_before_relax first. If this is a
12435 branch to a different section, we mark it as such. If SEC is
12436 NULL, and the frag is not marked, then it must be a branch to
12437 the same section. */
12440 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12445 /* Must have been called from md_estimate_size_before_relax. */
12448 fragp
->fr_subtype
=
12449 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12451 /* FIXME: We should support this, and let the linker
12452 catch branches and loads that are out of range. */
12453 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12454 _("unsupported PC relative reference to different section"));
12458 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12459 /* Assume non-extended on the first relaxation pass.
12460 The address we have calculated will be bogus if this is
12461 a forward branch to another frag, as the forward frag
12462 will have fr_address == 0. */
12466 /* In this case, we know for sure that the symbol fragment is in
12467 the same section. If the relax_marker of the symbol fragment
12468 differs from the relax_marker of this fragment, we have not
12469 yet adjusted the symbol fragment fr_address. We want to add
12470 in STRETCH in order to get a better estimate of the address.
12471 This particularly matters because of the shift bits. */
12473 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12477 /* Adjust stretch for any alignment frag. Note that if have
12478 been expanding the earlier code, the symbol may be
12479 defined in what appears to be an earlier frag. FIXME:
12480 This doesn't handle the fr_subtype field, which specifies
12481 a maximum number of bytes to skip when doing an
12483 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12485 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12488 stretch
= - ((- stretch
)
12489 & ~ ((1 << (int) f
->fr_offset
) - 1));
12491 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12500 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12502 /* The base address rules are complicated. The base address of
12503 a branch is the following instruction. The base address of a
12504 PC relative load or add is the instruction itself, but if it
12505 is in a delay slot (in which case it can not be extended) use
12506 the address of the instruction whose delay slot it is in. */
12507 if (type
== 'p' || type
== 'q')
12511 /* If we are currently assuming that this frag should be
12512 extended, then, the current address is two bytes
12514 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12517 /* Ignore the low bit in the target, since it will be set
12518 for a text label. */
12519 if ((val
& 1) != 0)
12522 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12524 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12527 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12529 /* Branch offsets have an implicit 0 in the lowest bit. */
12530 if (type
== 'p' || type
== 'q')
12533 /* If any of the shifted bits are set, we must use an extended
12534 opcode. If the address depends on the size of this
12535 instruction, this can lead to a loop, so we arrange to always
12536 use an extended opcode. We only check this when we are in
12537 the main relaxation loop, when SEC is NULL. */
12538 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12540 fragp
->fr_subtype
=
12541 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12545 /* If we are about to mark a frag as extended because the value
12546 is precisely maxtiny + 1, then there is a chance of an
12547 infinite loop as in the following code:
12552 In this case when the la is extended, foo is 0x3fc bytes
12553 away, so the la can be shrunk, but then foo is 0x400 away, so
12554 the la must be extended. To avoid this loop, we mark the
12555 frag as extended if it was small, and is about to become
12556 extended with a value of maxtiny + 1. */
12557 if (val
== ((maxtiny
+ 1) << op
->shift
)
12558 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12561 fragp
->fr_subtype
=
12562 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12566 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12567 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12569 if ((val
& ((1 << op
->shift
) - 1)) != 0
12570 || val
< (mintiny
<< op
->shift
)
12571 || val
> (maxtiny
<< op
->shift
))
12577 /* Compute the length of a branch sequence, and adjust the
12578 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12579 worst-case length is computed, with UPDATE being used to indicate
12580 whether an unconditional (-1), branch-likely (+1) or regular (0)
12581 branch is to be computed. */
12583 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12585 bfd_boolean toofar
;
12589 && S_IS_DEFINED (fragp
->fr_symbol
)
12590 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12595 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12597 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12601 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12604 /* If the symbol is not defined or it's in a different segment,
12605 assume the user knows what's going on and emit a short
12611 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12613 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12614 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12615 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12621 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12624 if (mips_pic
!= NO_PIC
)
12626 /* Additional space for PIC loading of target address. */
12628 if (mips_opts
.isa
== ISA_MIPS1
)
12629 /* Additional space for $at-stabilizing nop. */
12633 /* If branch is conditional. */
12634 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12641 /* Estimate the size of a frag before relaxing. Unless this is the
12642 mips16, we are not really relaxing here, and the final size is
12643 encoded in the subtype information. For the mips16, we have to
12644 decide whether we are using an extended opcode or not. */
12647 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12651 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12654 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12656 return fragp
->fr_var
;
12659 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12660 /* We don't want to modify the EXTENDED bit here; it might get us
12661 into infinite loops. We change it only in mips_relax_frag(). */
12662 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12664 if (mips_pic
== NO_PIC
)
12665 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12666 else if (mips_pic
== SVR4_PIC
)
12667 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12673 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12674 return -RELAX_FIRST (fragp
->fr_subtype
);
12677 return -RELAX_SECOND (fragp
->fr_subtype
);
12680 /* This is called to see whether a reloc against a defined symbol
12681 should be converted into a reloc against a section. Don't adjust
12682 MIPS16 jump relocations, so we don't have to worry about the format
12683 of the offset in the .o file. Don't adjust relocations against
12684 mips16 symbols, so that the linker can find them if it needs to set
12688 mips_fix_adjustable (fixS
*fixp
)
12690 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12693 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12694 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12697 if (fixp
->fx_addsy
== NULL
)
12701 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12702 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12703 && fixp
->fx_subsy
== NULL
)
12710 /* Translate internal representation of relocation info to BFD target
12714 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12716 static arelent
*retval
[4];
12718 bfd_reloc_code_real_type code
;
12720 memset (retval
, 0, sizeof(retval
));
12721 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12722 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12723 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12724 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12726 assert (! fixp
->fx_pcrel
);
12727 reloc
->addend
= fixp
->fx_addnumber
;
12729 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12730 entry to be used in the relocation's section offset. */
12731 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12733 reloc
->address
= reloc
->addend
;
12737 code
= fixp
->fx_r_type
;
12739 /* To support a PC relative reloc, we used a Cygnus extension.
12740 We check for that here to make sure that we don't let such a
12741 reloc escape normally. (FIXME: This was formerly used by
12742 embedded-PIC support, but is now used by branch handling in
12743 general. That probably should be fixed.) */
12744 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12745 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12746 && code
== BFD_RELOC_16_PCREL_S2
)
12747 reloc
->howto
= NULL
;
12749 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12751 if (reloc
->howto
== NULL
)
12753 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12754 _("Can not represent %s relocation in this object file format"),
12755 bfd_get_reloc_code_name (code
));
12762 /* Relax a machine dependent frag. This returns the amount by which
12763 the current size of the frag should change. */
12766 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12768 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12770 offsetT old_var
= fragp
->fr_var
;
12772 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12774 return fragp
->fr_var
- old_var
;
12777 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12780 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12782 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12784 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12789 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12791 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12798 /* Convert a machine dependent frag. */
12801 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12803 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12806 unsigned long insn
;
12810 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12812 if (target_big_endian
)
12813 insn
= bfd_getb32 (buf
);
12815 insn
= bfd_getl32 (buf
);
12817 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12819 /* We generate a fixup instead of applying it right now
12820 because, if there are linker relaxations, we're going to
12821 need the relocations. */
12822 exp
.X_op
= O_symbol
;
12823 exp
.X_add_symbol
= fragp
->fr_symbol
;
12824 exp
.X_add_number
= fragp
->fr_offset
;
12826 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12828 BFD_RELOC_16_PCREL_S2
);
12829 fixp
->fx_file
= fragp
->fr_file
;
12830 fixp
->fx_line
= fragp
->fr_line
;
12832 md_number_to_chars (buf
, insn
, 4);
12839 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12840 _("relaxed out-of-range branch into a jump"));
12842 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12845 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12847 /* Reverse the branch. */
12848 switch ((insn
>> 28) & 0xf)
12851 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12852 have the condition reversed by tweaking a single
12853 bit, and their opcodes all have 0x4???????. */
12854 assert ((insn
& 0xf1000000) == 0x41000000);
12855 insn
^= 0x00010000;
12859 /* bltz 0x04000000 bgez 0x04010000
12860 bltzal 0x04100000 bgezal 0x04110000 */
12861 assert ((insn
& 0xfc0e0000) == 0x04000000);
12862 insn
^= 0x00010000;
12866 /* beq 0x10000000 bne 0x14000000
12867 blez 0x18000000 bgtz 0x1c000000 */
12868 insn
^= 0x04000000;
12876 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12878 /* Clear the and-link bit. */
12879 assert ((insn
& 0xfc1c0000) == 0x04100000);
12881 /* bltzal 0x04100000 bgezal 0x04110000
12882 bltzall 0x04120000 bgezall 0x04130000 */
12883 insn
&= ~0x00100000;
12886 /* Branch over the branch (if the branch was likely) or the
12887 full jump (not likely case). Compute the offset from the
12888 current instruction to branch to. */
12889 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12893 /* How many bytes in instructions we've already emitted? */
12894 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12895 /* How many bytes in instructions from here to the end? */
12896 i
= fragp
->fr_var
- i
;
12898 /* Convert to instruction count. */
12900 /* Branch counts from the next instruction. */
12903 /* Branch over the jump. */
12904 md_number_to_chars (buf
, insn
, 4);
12908 md_number_to_chars (buf
, 0, 4);
12911 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12913 /* beql $0, $0, 2f */
12915 /* Compute the PC offset from the current instruction to
12916 the end of the variable frag. */
12917 /* How many bytes in instructions we've already emitted? */
12918 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12919 /* How many bytes in instructions from here to the end? */
12920 i
= fragp
->fr_var
- i
;
12921 /* Convert to instruction count. */
12923 /* Don't decrement i, because we want to branch over the
12927 md_number_to_chars (buf
, insn
, 4);
12930 md_number_to_chars (buf
, 0, 4);
12935 if (mips_pic
== NO_PIC
)
12938 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12939 ? 0x0c000000 : 0x08000000);
12940 exp
.X_op
= O_symbol
;
12941 exp
.X_add_symbol
= fragp
->fr_symbol
;
12942 exp
.X_add_number
= fragp
->fr_offset
;
12944 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12945 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12946 fixp
->fx_file
= fragp
->fr_file
;
12947 fixp
->fx_line
= fragp
->fr_line
;
12949 md_number_to_chars (buf
, insn
, 4);
12954 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12955 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12956 exp
.X_op
= O_symbol
;
12957 exp
.X_add_symbol
= fragp
->fr_symbol
;
12958 exp
.X_add_number
= fragp
->fr_offset
;
12960 if (fragp
->fr_offset
)
12962 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12963 exp
.X_add_number
= 0;
12966 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12967 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12968 fixp
->fx_file
= fragp
->fr_file
;
12969 fixp
->fx_line
= fragp
->fr_line
;
12971 md_number_to_chars (buf
, insn
, 4);
12974 if (mips_opts
.isa
== ISA_MIPS1
)
12977 md_number_to_chars (buf
, 0, 4);
12981 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
12982 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
12984 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12985 4, &exp
, 0, BFD_RELOC_LO16
);
12986 fixp
->fx_file
= fragp
->fr_file
;
12987 fixp
->fx_line
= fragp
->fr_line
;
12989 md_number_to_chars (buf
, insn
, 4);
12993 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12998 md_number_to_chars (buf
, insn
, 4);
13003 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13004 + fragp
->fr_fix
+ fragp
->fr_var
);
13006 fragp
->fr_fix
+= fragp
->fr_var
;
13011 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13014 register const struct mips16_immed_operand
*op
;
13015 bfd_boolean small
, ext
;
13018 unsigned long insn
;
13019 bfd_boolean use_extend
;
13020 unsigned short extend
;
13022 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13023 op
= mips16_immed_operands
;
13024 while (op
->type
!= type
)
13027 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13038 resolve_symbol_value (fragp
->fr_symbol
);
13039 val
= S_GET_VALUE (fragp
->fr_symbol
);
13044 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13046 /* The rules for the base address of a PC relative reloc are
13047 complicated; see mips16_extended_frag. */
13048 if (type
== 'p' || type
== 'q')
13053 /* Ignore the low bit in the target, since it will be
13054 set for a text label. */
13055 if ((val
& 1) != 0)
13058 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13060 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13063 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13066 /* Make sure the section winds up with the alignment we have
13069 record_alignment (asec
, op
->shift
);
13073 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13074 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13075 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13076 _("extended instruction in delay slot"));
13078 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13080 if (target_big_endian
)
13081 insn
= bfd_getb16 (buf
);
13083 insn
= bfd_getl16 (buf
);
13085 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13086 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13087 small
, ext
, &insn
, &use_extend
, &extend
);
13091 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13092 fragp
->fr_fix
+= 2;
13096 md_number_to_chars (buf
, insn
, 2);
13097 fragp
->fr_fix
+= 2;
13105 first
= RELAX_FIRST (fragp
->fr_subtype
);
13106 second
= RELAX_SECOND (fragp
->fr_subtype
);
13107 fixp
= (fixS
*) fragp
->fr_opcode
;
13109 /* Possibly emit a warning if we've chosen the longer option. */
13110 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13111 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13113 const char *msg
= macro_warning (fragp
->fr_subtype
);
13115 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13118 /* Go through all the fixups for the first sequence. Disable them
13119 (by marking them as done) if we're going to use the second
13120 sequence instead. */
13122 && fixp
->fx_frag
== fragp
13123 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13125 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13127 fixp
= fixp
->fx_next
;
13130 /* Go through the fixups for the second sequence. Disable them if
13131 we're going to use the first sequence, otherwise adjust their
13132 addresses to account for the relaxation. */
13133 while (fixp
&& fixp
->fx_frag
== fragp
)
13135 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13136 fixp
->fx_where
-= first
;
13139 fixp
= fixp
->fx_next
;
13142 /* Now modify the frag contents. */
13143 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13147 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13148 memmove (start
, start
+ first
, second
);
13149 fragp
->fr_fix
-= first
;
13152 fragp
->fr_fix
-= second
;
13158 /* This function is called after the relocs have been generated.
13159 We've been storing mips16 text labels as odd. Here we convert them
13160 back to even for the convenience of the debugger. */
13163 mips_frob_file_after_relocs (void)
13166 unsigned int count
, i
;
13168 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13171 syms
= bfd_get_outsymbols (stdoutput
);
13172 count
= bfd_get_symcount (stdoutput
);
13173 for (i
= 0; i
< count
; i
++, syms
++)
13175 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13176 && ((*syms
)->value
& 1) != 0)
13178 (*syms
)->value
&= ~1;
13179 /* If the symbol has an odd size, it was probably computed
13180 incorrectly, so adjust that as well. */
13181 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13182 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13189 /* This function is called whenever a label is defined. It is used
13190 when handling branch delays; if a branch has a label, we assume we
13191 can not move it. */
13194 mips_define_label (symbolS
*sym
)
13196 struct insn_label_list
*l
;
13198 if (free_insn_labels
== NULL
)
13199 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13202 l
= free_insn_labels
;
13203 free_insn_labels
= l
->next
;
13207 l
->next
= insn_labels
;
13211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13213 /* Some special processing for a MIPS ELF file. */
13216 mips_elf_final_processing (void)
13218 /* Write out the register information. */
13219 if (mips_abi
!= N64_ABI
)
13223 s
.ri_gprmask
= mips_gprmask
;
13224 s
.ri_cprmask
[0] = mips_cprmask
[0];
13225 s
.ri_cprmask
[1] = mips_cprmask
[1];
13226 s
.ri_cprmask
[2] = mips_cprmask
[2];
13227 s
.ri_cprmask
[3] = mips_cprmask
[3];
13228 /* The gp_value field is set by the MIPS ELF backend. */
13230 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13231 ((Elf32_External_RegInfo
*)
13232 mips_regmask_frag
));
13236 Elf64_Internal_RegInfo s
;
13238 s
.ri_gprmask
= mips_gprmask
;
13240 s
.ri_cprmask
[0] = mips_cprmask
[0];
13241 s
.ri_cprmask
[1] = mips_cprmask
[1];
13242 s
.ri_cprmask
[2] = mips_cprmask
[2];
13243 s
.ri_cprmask
[3] = mips_cprmask
[3];
13244 /* The gp_value field is set by the MIPS ELF backend. */
13246 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13247 ((Elf64_External_RegInfo
*)
13248 mips_regmask_frag
));
13251 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13252 sort of BFD interface for this. */
13253 if (mips_any_noreorder
)
13254 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13255 if (mips_pic
!= NO_PIC
)
13257 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13258 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13261 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13263 /* Set MIPS ELF flags for ASEs. */
13264 if (file_ase_mips16
)
13265 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13266 #if 0 /* XXX FIXME */
13267 if (file_ase_mips3d
)
13268 elf_elfheader (stdoutput
)->e_flags
|= ???;
13271 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13273 /* Set the MIPS ELF ABI flags. */
13274 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13275 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13276 else if (mips_abi
== O64_ABI
)
13277 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13278 else if (mips_abi
== EABI_ABI
)
13280 if (!file_mips_gp32
)
13281 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13283 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13285 else if (mips_abi
== N32_ABI
)
13286 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13288 /* Nothing to do for N64_ABI. */
13290 if (mips_32bitmode
)
13291 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13294 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13296 typedef struct proc
{
13298 unsigned long reg_mask
;
13299 unsigned long reg_offset
;
13300 unsigned long fpreg_mask
;
13301 unsigned long fpreg_offset
;
13302 unsigned long frame_offset
;
13303 unsigned long frame_reg
;
13304 unsigned long pc_reg
;
13307 static procS cur_proc
;
13308 static procS
*cur_proc_ptr
;
13309 static int numprocs
;
13311 /* Fill in an rs_align_code fragment. */
13314 mips_handle_align (fragS
*fragp
)
13316 if (fragp
->fr_type
!= rs_align_code
)
13319 if (mips_opts
.mips16
)
13321 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13322 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13327 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13328 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13336 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13340 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13344 md_obj_begin (void)
13351 /* check for premature end, nesting errors, etc */
13353 as_warn (_("missing .end at end of assembly"));
13362 if (*input_line_pointer
== '-')
13364 ++input_line_pointer
;
13367 if (!ISDIGIT (*input_line_pointer
))
13368 as_bad (_("expected simple number"));
13369 if (input_line_pointer
[0] == '0')
13371 if (input_line_pointer
[1] == 'x')
13373 input_line_pointer
+= 2;
13374 while (ISXDIGIT (*input_line_pointer
))
13377 val
|= hex_value (*input_line_pointer
++);
13379 return negative
? -val
: val
;
13383 ++input_line_pointer
;
13384 while (ISDIGIT (*input_line_pointer
))
13387 val
|= *input_line_pointer
++ - '0';
13389 return negative
? -val
: val
;
13392 if (!ISDIGIT (*input_line_pointer
))
13394 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13395 *input_line_pointer
, *input_line_pointer
);
13396 as_warn (_("invalid number"));
13399 while (ISDIGIT (*input_line_pointer
))
13402 val
+= *input_line_pointer
++ - '0';
13404 return negative
? -val
: val
;
13407 /* The .file directive; just like the usual .file directive, but there
13408 is an initial number which is the ECOFF file index. In the non-ECOFF
13409 case .file implies DWARF-2. */
13412 s_mips_file (int x ATTRIBUTE_UNUSED
)
13414 static int first_file_directive
= 0;
13416 if (ECOFF_DEBUGGING
)
13425 filename
= dwarf2_directive_file (0);
13427 /* Versions of GCC up to 3.1 start files with a ".file"
13428 directive even for stabs output. Make sure that this
13429 ".file" is handled. Note that you need a version of GCC
13430 after 3.1 in order to support DWARF-2 on MIPS. */
13431 if (filename
!= NULL
&& ! first_file_directive
)
13433 (void) new_logical_line (filename
, -1);
13434 s_app_file_string (filename
);
13436 first_file_directive
= 1;
13440 /* The .loc directive, implying DWARF-2. */
13443 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13445 if (!ECOFF_DEBUGGING
)
13446 dwarf2_directive_loc (0);
13449 /* The .end directive. */
13452 s_mips_end (int x ATTRIBUTE_UNUSED
)
13456 /* Following functions need their own .frame and .cprestore directives. */
13457 mips_frame_reg_valid
= 0;
13458 mips_cprestore_valid
= 0;
13460 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13463 demand_empty_rest_of_line ();
13468 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13469 as_warn (_(".end not in text section"));
13473 as_warn (_(".end directive without a preceding .ent directive."));
13474 demand_empty_rest_of_line ();
13480 assert (S_GET_NAME (p
));
13481 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13482 as_warn (_(".end symbol does not match .ent symbol."));
13484 if (debug_type
== DEBUG_STABS
)
13485 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13489 as_warn (_(".end directive missing or unknown symbol"));
13492 /* Generate a .pdr section. */
13493 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13496 segT saved_seg
= now_seg
;
13497 subsegT saved_subseg
= now_subseg
;
13502 dot
= frag_now_fix ();
13504 #ifdef md_flush_pending_output
13505 md_flush_pending_output ();
13509 subseg_set (pdr_seg
, 0);
13511 /* Write the symbol. */
13512 exp
.X_op
= O_symbol
;
13513 exp
.X_add_symbol
= p
;
13514 exp
.X_add_number
= 0;
13515 emit_expr (&exp
, 4);
13517 fragp
= frag_more (7 * 4);
13519 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13520 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13521 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13522 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13523 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13524 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13525 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13527 subseg_set (saved_seg
, saved_subseg
);
13529 #endif /* OBJ_ELF */
13531 cur_proc_ptr
= NULL
;
13534 /* The .aent and .ent directives. */
13537 s_mips_ent (int aent
)
13541 symbolP
= get_symbol ();
13542 if (*input_line_pointer
== ',')
13543 ++input_line_pointer
;
13544 SKIP_WHITESPACE ();
13545 if (ISDIGIT (*input_line_pointer
)
13546 || *input_line_pointer
== '-')
13549 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13550 as_warn (_(".ent or .aent not in text section."));
13552 if (!aent
&& cur_proc_ptr
)
13553 as_warn (_("missing .end"));
13557 /* This function needs its own .frame and .cprestore directives. */
13558 mips_frame_reg_valid
= 0;
13559 mips_cprestore_valid
= 0;
13561 cur_proc_ptr
= &cur_proc
;
13562 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13564 cur_proc_ptr
->isym
= symbolP
;
13566 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13570 if (debug_type
== DEBUG_STABS
)
13571 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13572 S_GET_NAME (symbolP
));
13575 demand_empty_rest_of_line ();
13578 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13579 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13580 s_mips_frame is used so that we can set the PDR information correctly.
13581 We can't use the ecoff routines because they make reference to the ecoff
13582 symbol table (in the mdebug section). */
13585 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13588 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13592 if (cur_proc_ptr
== (procS
*) NULL
)
13594 as_warn (_(".frame outside of .ent"));
13595 demand_empty_rest_of_line ();
13599 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13601 SKIP_WHITESPACE ();
13602 if (*input_line_pointer
++ != ','
13603 || get_absolute_expression_and_terminator (&val
) != ',')
13605 as_warn (_("Bad .frame directive"));
13606 --input_line_pointer
;
13607 demand_empty_rest_of_line ();
13611 cur_proc_ptr
->frame_offset
= val
;
13612 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13614 demand_empty_rest_of_line ();
13617 #endif /* OBJ_ELF */
13621 /* The .fmask and .mask directives. If the mdebug section is present
13622 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13623 embedded targets, s_mips_mask is used so that we can set the PDR
13624 information correctly. We can't use the ecoff routines because they
13625 make reference to the ecoff symbol table (in the mdebug section). */
13628 s_mips_mask (int reg_type
)
13631 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13635 if (cur_proc_ptr
== (procS
*) NULL
)
13637 as_warn (_(".mask/.fmask outside of .ent"));
13638 demand_empty_rest_of_line ();
13642 if (get_absolute_expression_and_terminator (&mask
) != ',')
13644 as_warn (_("Bad .mask/.fmask directive"));
13645 --input_line_pointer
;
13646 demand_empty_rest_of_line ();
13650 off
= get_absolute_expression ();
13652 if (reg_type
== 'F')
13654 cur_proc_ptr
->fpreg_mask
= mask
;
13655 cur_proc_ptr
->fpreg_offset
= off
;
13659 cur_proc_ptr
->reg_mask
= mask
;
13660 cur_proc_ptr
->reg_offset
= off
;
13663 demand_empty_rest_of_line ();
13666 #endif /* OBJ_ELF */
13667 s_ignore (reg_type
);
13670 /* The .loc directive. */
13680 assert (now_seg
== text_section
);
13682 lineno
= get_number ();
13683 addroff
= frag_now_fix ();
13685 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13686 S_SET_TYPE (symbolP
, N_SLINE
);
13687 S_SET_OTHER (symbolP
, 0);
13688 S_SET_DESC (symbolP
, lineno
);
13689 symbolP
->sy_segment
= now_seg
;
13693 /* A table describing all the processors gas knows about. Names are
13694 matched in the order listed.
13696 To ease comparison, please keep this table in the same order as
13697 gcc's mips_cpu_info_table[]. */
13698 static const struct mips_cpu_info mips_cpu_info_table
[] =
13700 /* Entries for generic ISAs */
13701 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13702 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13703 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13704 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13705 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13706 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13707 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13708 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13709 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13712 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13713 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13714 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13717 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13720 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13721 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13722 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13723 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13724 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13725 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13726 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13727 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13728 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13729 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13730 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13731 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13734 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13735 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13736 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13737 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13738 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13739 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13740 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13741 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13742 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13743 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13744 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13745 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13746 { "rm9000", 0, ISA_MIPS4
, CPU_RM7000
},
13749 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13750 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13751 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13754 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13755 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13757 /* Broadcom SB-1 CPU core */
13758 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13765 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13766 with a final "000" replaced by "k". Ignore case.
13768 Note: this function is shared between GCC and GAS. */
13771 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13773 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13774 given
++, canonical
++;
13776 return ((*given
== 0 && *canonical
== 0)
13777 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13781 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13782 CPU name. We've traditionally allowed a lot of variation here.
13784 Note: this function is shared between GCC and GAS. */
13787 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13789 /* First see if the name matches exactly, or with a final "000"
13790 turned into "k". */
13791 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13794 /* If not, try comparing based on numerical designation alone.
13795 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13796 if (TOLOWER (*given
) == 'r')
13798 if (!ISDIGIT (*given
))
13801 /* Skip over some well-known prefixes in the canonical name,
13802 hoping to find a number there too. */
13803 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13805 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13807 else if (TOLOWER (canonical
[0]) == 'r')
13810 return mips_strict_matching_cpu_name_p (canonical
, given
);
13814 /* Parse an option that takes the name of a processor as its argument.
13815 OPTION is the name of the option and CPU_STRING is the argument.
13816 Return the corresponding processor enumeration if the CPU_STRING is
13817 recognized, otherwise report an error and return null.
13819 A similar function exists in GCC. */
13821 static const struct mips_cpu_info
*
13822 mips_parse_cpu (const char *option
, const char *cpu_string
)
13824 const struct mips_cpu_info
*p
;
13826 /* 'from-abi' selects the most compatible architecture for the given
13827 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13828 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13829 version. Look first at the -mgp options, if given, otherwise base
13830 the choice on MIPS_DEFAULT_64BIT.
13832 Treat NO_ABI like the EABIs. One reason to do this is that the
13833 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13834 architecture. This code picks MIPS I for 'mips' and MIPS III for
13835 'mips64', just as we did in the days before 'from-abi'. */
13836 if (strcasecmp (cpu_string
, "from-abi") == 0)
13838 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13839 return mips_cpu_info_from_isa (ISA_MIPS1
);
13841 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13842 return mips_cpu_info_from_isa (ISA_MIPS3
);
13844 if (file_mips_gp32
>= 0)
13845 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13847 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13852 /* 'default' has traditionally been a no-op. Probably not very useful. */
13853 if (strcasecmp (cpu_string
, "default") == 0)
13856 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13857 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13860 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13864 /* Return the canonical processor information for ISA (a member of the
13865 ISA_MIPS* enumeration). */
13867 static const struct mips_cpu_info
*
13868 mips_cpu_info_from_isa (int isa
)
13872 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13873 if (mips_cpu_info_table
[i
].is_isa
13874 && isa
== mips_cpu_info_table
[i
].isa
)
13875 return (&mips_cpu_info_table
[i
]);
13880 static const struct mips_cpu_info
*
13881 mips_cpu_info_from_arch (int arch
)
13885 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13886 if (arch
== mips_cpu_info_table
[i
].cpu
)
13887 return (&mips_cpu_info_table
[i
]);
13893 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13897 fprintf (stream
, "%24s", "");
13902 fprintf (stream
, ", ");
13906 if (*col_p
+ strlen (string
) > 72)
13908 fprintf (stream
, "\n%24s", "");
13912 fprintf (stream
, "%s", string
);
13913 *col_p
+= strlen (string
);
13919 md_show_usage (FILE *stream
)
13924 fprintf (stream
, _("\
13926 -EB generate big endian output\n\
13927 -EL generate little endian output\n\
13928 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13929 -G NUM allow referencing objects up to NUM bytes\n\
13930 implicitly with the gp register [default 8]\n"));
13931 fprintf (stream
, _("\
13932 -mips1 generate MIPS ISA I instructions\n\
13933 -mips2 generate MIPS ISA II instructions\n\
13934 -mips3 generate MIPS ISA III instructions\n\
13935 -mips4 generate MIPS ISA IV instructions\n\
13936 -mips5 generate MIPS ISA V instructions\n\
13937 -mips32 generate MIPS32 ISA instructions\n\
13938 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13939 -mips64 generate MIPS64 ISA instructions\n\
13940 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13941 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13945 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13946 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13947 show (stream
, "from-abi", &column
, &first
);
13948 fputc ('\n', stream
);
13950 fprintf (stream
, _("\
13951 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13952 -no-mCPU don't generate code specific to CPU.\n\
13953 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13957 show (stream
, "3900", &column
, &first
);
13958 show (stream
, "4010", &column
, &first
);
13959 show (stream
, "4100", &column
, &first
);
13960 show (stream
, "4650", &column
, &first
);
13961 fputc ('\n', stream
);
13963 fprintf (stream
, _("\
13964 -mips16 generate mips16 instructions\n\
13965 -no-mips16 do not generate mips16 instructions\n"));
13966 fprintf (stream
, _("\
13967 -mfix-vr4120 work around certain VR4120 errata\n\
13968 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13969 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13970 -O0 remove unneeded NOPs, do not swap branches\n\
13971 -O remove unneeded NOPs and swap branches\n\
13972 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13973 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13974 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13976 fprintf (stream
, _("\
13977 -KPIC, -call_shared generate SVR4 position independent code\n\
13978 -non_shared do not generate position independent code\n\
13979 -xgot assume a 32 bit GOT\n\
13980 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
13981 -mabi=ABI create ABI conformant object file for:\n"));
13985 show (stream
, "32", &column
, &first
);
13986 show (stream
, "o64", &column
, &first
);
13987 show (stream
, "n32", &column
, &first
);
13988 show (stream
, "64", &column
, &first
);
13989 show (stream
, "eabi", &column
, &first
);
13991 fputc ('\n', stream
);
13993 fprintf (stream
, _("\
13994 -32 create o32 ABI object file (default)\n\
13995 -n32 create n32 ABI object file\n\
13996 -64 create 64 ABI object file\n"));
14001 mips_dwarf2_format (void)
14003 if (mips_abi
== N64_ABI
)
14006 return dwarf2_format_64bit_irix
;
14008 return dwarf2_format_64bit
;
14012 return dwarf2_format_32bit
;
14016 mips_dwarf2_addr_size (void)
14018 if (mips_abi
== N64_ABI
)