1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* These variables are filled in with the masks of registers used.
69 The object format code reads them and puts them in the appropriate
71 unsigned long mips_gprmask
;
72 unsigned long mips_cprmask
[4];
74 /* MIPS ISA (Instruction Set Architecture) level. */
75 static int mips_isa
= -1;
77 /* MIPS PIC level. 0 is normal, non-PIC code. 2 means to generate
78 SVR4 ABI PIC calls. 1 doesn't mean anything. */
81 static int mips_warn_about_macros
;
82 static int mips_noreorder
;
83 static int mips_any_noreorder
;
84 static int mips_nomove
;
86 static int mips_nobopt
;
89 /* The size of the small data section. */
90 static int g_switch_value
= 8;
96 /* handle of the OPCODE hash table */
97 static struct hash_control
*op_hash
= NULL
;
99 /* This array holds the chars that always start a comment. If the
100 pre-processor is disabled, these aren't very useful */
101 const char comment_chars
[] = "#";
103 /* This array holds the chars that only start a comment at the beginning of
104 a line. If the line seems to have the form '# 123 filename'
105 .line and .file directives will appear in the pre-processed output */
106 /* Note that input_file.c hand checks for '#' at the beginning of the
107 first line of the input file. This is because the compiler outputs
108 #NO_APP at the beginning of its output. */
109 /* Also note that C style comments are always supported. */
110 const char line_comment_chars
[] = "#";
112 /* This array holds machine specific line separator characters. */
113 const char line_separator_chars
[] = "";
115 /* Chars that can be used to separate mant from exp in floating point nums */
116 const char EXP_CHARS
[] = "eE";
118 /* Chars that mean this number is a floating point constant */
121 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
123 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
124 changed in read.c . Ideally it shouldn't have to know about it at all,
125 but nothing is ideal around here.
128 static char *insn_error
;
130 static int byte_order
= BYTE_ORDER
;
132 static int auto_align
= 1;
134 /* Symbol labelling the current insn. */
135 static symbolS
*insn_label
;
137 /* When outputting SVR4 PIC code, the assembler needs to know the
138 offset in the stack frame from which to restore the $gp register.
139 This is set by the .cprestore pseudo-op, and saved in this
141 static offsetT mips_cprestore_offset
= -1;
143 /* This is the register which holds the stack frame, as set by the
144 .frame pseudo-op. This is needed to implement .cprestore. */
145 static int mips_frame_reg
= SP
;
147 /* To output NOP instructions correctly, we need to keep information
148 about the previous two instructions. */
150 /* Whether we are optimizing. The default value of 2 means to remove
151 unneeded NOPs and swap branch instructions when possible. A value
152 of 1 means to not swap branches. A value of 0 means to always
154 static int mips_optimize
= 2;
156 /* The previous instruction. */
157 static struct mips_cl_insn prev_insn
;
159 /* The instruction before prev_insn. */
160 static struct mips_cl_insn prev_prev_insn
;
162 /* If we don't want information for prev_insn or prev_prev_insn, we
163 point the insn_mo field at this dummy integer. */
164 static const struct mips_opcode dummy_opcode
= { 0 };
166 /* Non-zero if prev_insn is valid. */
167 static int prev_insn_valid
;
169 /* The frag for the previous instruction. */
170 static struct frag
*prev_insn_frag
;
172 /* The offset into prev_insn_frag for the previous instruction. */
173 static long prev_insn_where
;
175 /* The reloc for the previous instruction, if any. */
176 static fixS
*prev_insn_fixp
;
178 /* Non-zero if the previous instruction was in a delay slot. */
179 static int prev_insn_is_delay_slot
;
181 /* Non-zero if the previous instruction was in a .set noreorder. */
182 static int prev_insn_unreordered
;
184 /* Non-zero if the previous previous instruction was in a .set
186 static int prev_prev_insn_unreordered
;
188 /* Since the MIPS does not have multiple forms of PC relative
189 instructions, we do not have to do relaxing as is done on other
190 platforms. However, we do have to handle GP relative addressing
191 correctly, which turns out to be a similar problem.
193 Every macro that refers to a symbol can occur in (at least) two
194 forms, one with GP relative addressing and one without. For
195 example, loading a global variable into a register generally uses
196 an macroinstruction like this:
198 If i can be addressed off the GP register (this is true if it is in
199 the .sbss or .sdata section, or if it is known to be smaller than
200 the -G argument) this will generate the following instruction:
202 This instruction will use a GPREL reloc. If i can not be addressed
203 off the GP register, the following instruction sequence will be used:
206 In this case the first instruction will have a HI16 reloc, and the
207 second reloc will have a LO16 reloc. Both relocs will be against
210 The issue here is that we may not know whether i is GP addressable
211 until after we see the instruction that uses it. Therefore, we
212 want to be able to choose the final instruction sequence only at
213 the end of the assembly. This is similar to the way other
214 platforms choose the form of a PC relative instruction only at the
217 When generating position independent code we do not use GP
218 addressing in the same way, but the issue still arises as external
219 symbols and local symbols must be handled differently.
221 We handle these issues by actually generating both possible
222 instruction sequences. The longer one is put in a frag_var with
223 type rs_machine_dependent. We encode what to do with the frag in
224 the subtype field. We encode (1) the number of existing bytes to
225 replace, (2) the number of new bytes to use, (3) the offset from
226 the start of the existing bytes to the first reloc we must generate
227 (that is, the offset is applied from the start of the existing
228 bytes after they are replaced by the new bytes, if any), (4) the
229 offset from the start of the existing bytes to the second reloc,
230 (5) whether a third reloc is needed (the third reloc is always four
231 bytes after the second reloc), and (6) whether to warn if this
232 variant is used (this is sometimes needed if .set nomacro or .set
233 noat is in effect). All these numbers are reasonably small.
235 Generating two instruction sequences must be handled carefully to
236 ensure that delay slots are handled correctly. Fortunately, the
237 issue only arises in a restricted number of cases. When the second
238 instruction sequence is generated, append_insn is directed to
239 maintain the existing delay slot information, so it continues to
240 apply to any code after the second instruction sequence. This
241 means that the second instruction sequence must not impose any
242 requirements not required by the first instruction sequence.
244 These variant frags are then handled in functions called by the
245 machine independent code. md_estimate_size_before_relax returns
246 the final size of the frag. md_convert_frag sets up the final form
247 of the frag. tc_gen_reloc adjust the first reloc and adds a second
249 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
253 | (((reloc1) + 64) << 9) \
254 | (((reloc2) + 64) << 2) \
255 | ((reloc3) ? (1 << 1) : 0) \
257 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
258 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
259 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
260 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
261 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
262 #define RELAX_WARN(i) ((i) & 1)
264 /* Prototypes for static functions. */
267 #define internalError() \
268 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
270 #define internalError() as_fatal ("MIPS internal Error");
273 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
274 unsigned int reg
, int fpr
));
275 static void append_insn
PARAMS ((char *place
,
276 struct mips_cl_insn
* ip
,
278 bfd_reloc_code_real_type r
));
279 static void mips_no_prev_insn
PARAMS ((void));
280 static void mips_emit_delays
PARAMS ((void));
281 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
282 const char *name
, const char *fmt
,
284 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
285 expressionS
* ep
, int regnum
));
286 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
287 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
289 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
290 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
291 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
292 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
293 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
294 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
295 static symbolS
*get_symbol
PARAMS ((void));
296 static void mips_align
PARAMS ((int to
, int fill
));
297 static void s_align
PARAMS ((int));
298 static void s_stringer
PARAMS ((int));
299 static void s_change_sec
PARAMS ((int));
300 static void s_cons
PARAMS ((int));
301 static void s_err
PARAMS ((int));
302 static void s_extern
PARAMS ((int));
303 static void s_float_cons
PARAMS ((int));
304 static void s_option
PARAMS ((int));
305 static void s_mipsset
PARAMS ((int));
306 static void s_mips_space
PARAMS ((int));
307 static void s_abicalls
PARAMS ((int));
308 static void s_cpload
PARAMS ((int));
309 static void s_cprestore
PARAMS ((int));
310 static void s_gpword
PARAMS ((int));
311 static void s_cpadd
PARAMS ((int));
312 #ifndef ECOFF_DEBUGGING
313 static void md_obj_begin
PARAMS ((void));
314 static void md_obj_end
PARAMS ((void));
315 static long get_number
PARAMS ((void));
316 static void s_ent
PARAMS ((int));
317 static void s_mipsend
PARAMS ((int));
318 static void s_file
PARAMS ((int));
320 static void s_frame
PARAMS ((int));
321 static void s_loc
PARAMS ((int));
322 static void s_mask
PARAMS ((char));
328 The following pseudo-ops from the Kane and Heinrich MIPS book
329 should be defined here, but are currently unsupported: .alias,
330 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
332 The following pseudo-ops from the Kane and Heinrich MIPS book are
333 specific to the type of debugging information being generated, and
334 should be defined by the object format: .aent, .begin, .bend,
335 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
338 The following pseudo-ops from the Kane and Heinrich MIPS book are
339 not MIPS CPU specific, but are also not specific to the object file
340 format. This file is probably the best place to define them, but
341 they are not currently supported: .asm0, .endr, .lab, .repeat,
342 .struct, .weakext. */
344 const pseudo_typeS md_pseudo_table
[] =
346 /* MIPS specific pseudo-ops. */
347 {"option", s_option
, 0},
348 {"set", s_mipsset
, 0},
349 {"rdata", s_change_sec
, 'r'},
350 {"sdata", s_change_sec
, 's'},
351 {"livereg", s_ignore
, 0},
352 { "abicalls", s_abicalls
, 0},
353 { "cpload", s_cpload
, 0},
354 { "cprestore", s_cprestore
, 0},
355 { "gpword", s_gpword
, 0},
356 { "cpadd", s_cpadd
, 0},
358 /* Relatively generic pseudo-ops that happen to be used on MIPS
360 {"asciiz", s_stringer
, 1},
361 {"bss", s_change_sec
, 'b'},
364 {"dword", s_cons
, 3},
366 /* These pseudo-ops are defined in read.c, but must be overridden
367 here for one reason or another. */
368 {"align", s_align
, 0},
369 {"ascii", s_stringer
, 0},
370 {"asciz", s_stringer
, 1},
372 {"data", s_change_sec
, 'd'},
373 {"double", s_float_cons
, 'd'},
374 {"extern", s_extern
, 0},
375 {"float", s_float_cons
, 'f'},
376 {"space", s_mips_space
, 0},
377 {"text", s_change_sec
, 't'},
380 #ifndef ECOFF_DEBUGGING
381 /* These pseudo-ops should be defined by the object file format.
382 However, a.out doesn't support them, so we have versions here. */
384 {"bgnb", s_ignore
, 0},
385 {"end", s_mipsend
, 0},
386 {"endb", s_ignore
, 0},
389 {"fmask", s_ignore
, 'F'},
390 {"frame", s_ignore
, 0},
391 {"loc", s_ignore
, 0},
392 {"mask", s_ignore
, 'R'},
393 {"verstamp", s_ignore
, 0},
400 const relax_typeS md_relax_table
[] =
406 static char *expr_end
;
408 static expressionS imm_expr
;
409 static expressionS offset_expr
;
410 static bfd_reloc_code_real_type imm_reloc
;
411 static bfd_reloc_code_real_type offset_reloc
;
413 /* FIXME: This should be handled in a different way. */
414 extern int target_big_endian
;
417 * This function is called once, at assembler startup time. It should
418 * set up all the tables, etc. that the MD part of the assembler will need.
424 register const char *retval
= NULL
;
425 register unsigned int i
= 0;
429 if (strcmp (TARGET_CPU
, "mips") == 0)
431 else if (strcmp (TARGET_CPU
, "r6000") == 0
432 || strcmp (TARGET_CPU
, "mips2") == 0)
434 else if (strcmp (TARGET_CPU
, "mips64") == 0
435 || strcmp (TARGET_CPU
, "r4000") == 0
436 || strcmp (TARGET_CPU
, "mips3") == 0)
445 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
448 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
451 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
455 as_warn ("Could not set architecture and machine");
457 if ((op_hash
= hash_new ()) == NULL
)
459 as_fatal ("Virtual memory exhausted");
461 for (i
= 0; i
< NUMOPCODES
;)
463 const char *name
= mips_opcodes
[i
].name
;
465 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
468 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
469 mips_opcodes
[i
].name
, retval
);
470 as_fatal ("Broken assembler. No assembly attempted.");
474 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
475 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
476 != mips_opcodes
[i
].match
))
478 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
479 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
480 as_fatal ("Broken assembler. No assembly attempted.");
484 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
487 mips_no_prev_insn ();
495 /* set the default alignment for the text section (2**2) */
496 record_alignment (text_section
, 2);
498 /* FIXME: This should be handled in a different way. */
499 target_big_endian
= byte_order
== BIG_ENDIAN
;
502 bfd_set_gp_size (stdoutput
, g_switch_value
);
506 /* Sections must be aligned to 16 byte boundaries. */
507 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
508 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
509 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
511 /* Create a .reginfo section for register masks and a .mdebug
512 section for debugging information. */
520 sec
= subseg_new (".reginfo", (subsegT
) 0);
522 /* I don't know why this section should be loaded, but the ABI
523 says that SHF_ALLOC should be set. */
524 (void) bfd_set_section_flags (stdoutput
, sec
,
525 (SEC_ALLOC
| SEC_LOAD
526 | SEC_READONLY
| SEC_DATA
));
527 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
529 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
531 #ifdef ECOFF_DEBUGGING
532 sec
= subseg_new (".mdebug", (subsegT
) 0);
533 (void) bfd_set_section_flags (stdoutput
, sec
,
534 SEC_HAS_CONTENTS
| SEC_READONLY
);
535 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
538 subseg_set (seg
, subseg
);
542 #ifndef ECOFF_DEBUGGING
550 #ifndef ECOFF_DEBUGGING
559 struct mips_cl_insn insn
;
561 imm_expr
.X_op
= O_absent
;
562 offset_expr
.X_op
= O_absent
;
564 mips_ip (str
, &insn
);
567 as_bad ("%s `%s'", insn_error
, str
);
570 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
576 if (imm_expr
.X_op
!= O_absent
)
577 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
578 else if (offset_expr
.X_op
!= O_absent
)
579 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
581 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
585 /* See whether instruction IP reads register REG. If FPR is non-zero,
586 REG is a floating point register. */
589 insn_uses_reg (ip
, reg
, fpr
)
590 struct mips_cl_insn
*ip
;
594 /* Don't report on general register 0, since it never changes. */
595 if (! fpr
&& reg
== 0)
600 /* If we are called with either $f0 or $f1, we must check $f0.
601 This is not optimal, because it will introduce an unnecessary
602 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
603 need to distinguish reading both $f0 and $f1 or just one of
604 them. Note that we don't have to check the other way,
605 because there is no instruction that sets both $f0 and $f1
606 and requires a delay. */
607 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
608 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
609 == (reg
&~ (unsigned) 1)))
611 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
612 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
613 == (reg
&~ (unsigned) 1)))
618 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
619 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
621 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
622 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
629 /* Output an instruction. PLACE is where to put the instruction; if
630 it is NULL, this uses frag_more to get room. IP is the instruction
631 information. ADDRESS_EXPR is an operand of the instruction to be
632 used with RELOC_TYPE. */
635 append_insn (place
, ip
, address_expr
, reloc_type
)
637 struct mips_cl_insn
*ip
;
638 expressionS
*address_expr
;
639 bfd_reloc_code_real_type reloc_type
;
641 register unsigned long prev_pinfo
, pinfo
;
646 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
647 pinfo
= ip
->insn_mo
->pinfo
;
649 if (place
== NULL
&& ! mips_noreorder
)
651 /* If the previous insn required any delay slots, see if we need
652 to insert a NOP or two. There are eight kinds of possible
653 hazards, of which an instruction can have at most one type.
654 (1) a load from memory delay
655 (2) a load from a coprocessor delay
656 (3) an unconditional branch delay
657 (4) a conditional branch delay
658 (5) a move to coprocessor register delay
659 (6) a load coprocessor register from memory delay
660 (7) a coprocessor condition code delay
661 (8) a HI/LO special register delay
663 There are a lot of optimizations we could do that we don't.
664 In particular, we do not, in general, reorder instructions.
665 If you use gcc with optimization, it will reorder
666 instructions and generally do much more optimization then we
667 do here; repeating all that work in the assembler would only
668 benefit hand written assembly code, and does not seem worth
671 /* This is how a NOP is emitted. */
672 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
674 /* The previous insn might require a delay slot, depending upon
675 the contents of the current insn. */
676 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
678 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
680 /* A load from a coprocessor or from memory. All load
681 delays delay the use of general register rt for one
682 instruction on the r3000. The r6000 and r4000 use
684 know (prev_pinfo
& INSN_WRITE_GPR_T
);
685 if (mips_optimize
== 0
686 || insn_uses_reg (ip
,
687 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
692 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
694 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
696 /* A generic coprocessor delay. The previous instruction
697 modified a coprocessor general or control register. If
698 it modified a control register, we need to avoid any
699 coprocessor instruction (this is probably not always
700 required, but it sometimes is). If it modified a general
701 register, we avoid using that register.
703 On the r6000 and r4000 loading a coprocessor register
704 from memory is interlocked, and does not require a delay.
706 This case is not handled very well. There is no special
707 knowledge of CP0 handling, and the coprocessors other
708 than the floating point unit are not distinguished at
710 if (prev_pinfo
& INSN_WRITE_FPR_T
)
712 if (mips_optimize
== 0
713 || insn_uses_reg (ip
,
714 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
719 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
721 if (mips_optimize
== 0
722 || insn_uses_reg (ip
,
723 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
730 /* We don't know exactly what the previous instruction
731 does. If the current instruction uses a coprocessor
732 register, we must insert a NOP. If previous
733 instruction may set the condition codes, and the
734 current instruction uses them, we must insert two
736 if (mips_optimize
== 0
737 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
738 && (pinfo
& INSN_READ_COND_CODE
)))
740 else if (pinfo
& INSN_COP
)
744 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
746 /* The previous instruction sets the coprocessor condition
747 codes, but does not require a general coprocessor delay
748 (this means it is a floating point comparison
749 instruction). If this instruction uses the condition
750 codes, we need to insert a single NOP. */
751 if (mips_optimize
== 0
752 || (pinfo
& INSN_READ_COND_CODE
))
755 else if (prev_pinfo
& INSN_READ_LO
)
757 /* The previous instruction reads the LO register; if the
758 current instruction writes to the LO register, we must
760 if (mips_optimize
== 0
761 || (pinfo
& INSN_WRITE_LO
))
764 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
766 /* The previous instruction reads the HI register; if the
767 current instruction writes to the HI register, we must
769 if (mips_optimize
== 0
770 || (pinfo
& INSN_WRITE_HI
))
774 /* There are two cases which require two intervening
775 instructions: 1) setting the condition codes using a move to
776 coprocessor instruction which requires a general coprocessor
777 delay and then reading the condition codes 2) reading the HI
778 or LO register and then writing to it. If we are not already
779 emitting a NOP instruction, we must check for these cases
780 compared to the instruction previous to the previous
783 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
784 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
785 && (pinfo
& INSN_READ_COND_CODE
))
786 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
787 && (pinfo
& INSN_WRITE_LO
))
788 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
789 && (pinfo
& INSN_WRITE_HI
))))
792 /* If we are being given a nop instruction, don't bother with
793 one of the nops we would otherwise output. This will only
794 happen when a nop instruction is used with mips_optimize set
796 if (nops
> 0 && ip
->insn_opcode
== 0)
799 /* Now emit the right number of NOP instructions. */
805 if (insn_label
!= NULL
)
807 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
808 insn_label
->sy_frag
= frag_now
;
809 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
819 if (address_expr
!= NULL
)
821 if (address_expr
->X_op
== O_constant
)
826 ip
->insn_opcode
|= address_expr
->X_add_number
;
830 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
833 case BFD_RELOC_MIPS_JMP
:
834 case BFD_RELOC_16_PCREL_S2
:
843 assert (reloc_type
!= BFD_RELOC_UNUSED
);
845 /* Don't generate a reloc if we are writing into a variant
848 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
850 reloc_type
== BFD_RELOC_16_PCREL_S2
,
855 md_number_to_chars (f
, ip
->insn_opcode
, 4);
857 /* Update the register mask information. */
858 if (pinfo
& INSN_WRITE_GPR_D
)
859 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
860 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
861 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
862 if (pinfo
& INSN_READ_GPR_S
)
863 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
864 if (pinfo
& INSN_WRITE_GPR_31
)
865 mips_gprmask
|= 1 << 31;
866 if (pinfo
& INSN_WRITE_FPR_D
)
867 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
868 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
869 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
870 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
871 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
872 if (pinfo
& INSN_COP
)
874 /* We don't keep enough information to sort these cases out. */
876 /* Never set the bit for $0, which is always zero. */
877 mips_gprmask
&=~ 1 << 0;
879 if (place
== NULL
&& ! mips_noreorder
)
881 /* Filling the branch delay slot is more complex. We try to
882 switch the branch with the previous instruction, which we can
883 do if the previous instruction does not set up a condition
884 that the branch tests and if the branch is not itself the
885 target of any branch. */
886 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
887 || (pinfo
& INSN_COND_BRANCH_DELAY
))
889 if (mips_optimize
< 2
890 /* If we have seen .set nobopt, don't optimize. */
892 /* If we have seen .set volatile or .set nomove, don't
895 /* If we had to emit any NOP instructions, then we
896 already know we can not swap. */
898 /* If we don't even know the previous insn, we can not
901 /* If the previous insn is already in a branch delay
902 slot, then we can not swap. */
903 || prev_insn_is_delay_slot
904 /* If the previous previous insn was in a .set
905 noreorder, we can't swap. Actually, the MIPS
906 assembler will swap in this situation. However, gcc
907 configured -with-gnu-as will generate code like
913 in which we can not swap the bne and INSN. If gcc is
914 not configured -with-gnu-as, it does not output the
915 .set pseudo-ops. We don't have to check
916 prev_insn_unreordered, because prev_insn_valid will
917 be 0 in that case. We don't want to use
918 prev_prev_insn_valid, because we do want to be able
919 to swap at the start of a function. */
920 || prev_prev_insn_unreordered
921 /* If the branch is itself the target of a branch, we
922 can not swap. We cheat on this; all we check for is
923 whether there is a label on this instruction. If
924 there are any branches to anything other than a
925 label, users must use .set noreorder. */
926 || insn_label
!= NULL
927 /* If the previous instruction is in a variant frag, we
928 can not do the swap. */
929 || prev_insn_frag
->fr_type
== rs_machine_dependent
930 /* If the branch reads the condition codes, we don't
931 even try to swap, because in the sequence
936 we can not swap, and I don't feel like handling that
938 || (pinfo
& INSN_READ_COND_CODE
)
939 /* We can not swap with an instruction that requires a
940 delay slot, becase the target of the branch might
941 interfere with that instruction. */
943 & (INSN_LOAD_COPROC_DELAY
944 | INSN_COPROC_MOVE_DELAY
945 | INSN_WRITE_COND_CODE
950 & (INSN_LOAD_MEMORY_DELAY
951 | INSN_COPROC_MEMORY_DELAY
)))
952 /* We can not swap with a branch instruction. */
954 & (INSN_UNCOND_BRANCH_DELAY
955 | INSN_COND_BRANCH_DELAY
956 | INSN_COND_BRANCH_LIKELY
))
957 /* We do not swap with a trap instruction, since it
958 complicates trap handlers to have the trap
959 instruction be in a delay slot. */
960 || (prev_pinfo
& INSN_TRAP
)
961 /* If the branch reads a register that the previous
962 instruction sets, we can not swap. */
963 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
964 && insn_uses_reg (ip
,
965 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
968 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
969 && insn_uses_reg (ip
,
970 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
973 /* If the branch writes a register that the previous
974 instruction sets, we can not swap (we know that
975 branches write only to RD or to $31). */
976 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
977 && (((pinfo
& INSN_WRITE_GPR_D
)
978 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
979 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
980 || ((pinfo
& INSN_WRITE_GPR_31
)
981 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
984 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
985 && (((pinfo
& INSN_WRITE_GPR_D
)
986 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
987 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
988 || ((pinfo
& INSN_WRITE_GPR_31
)
989 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
992 /* If the branch writes a register that the previous
993 instruction reads, we can not swap (we know that
994 branches only write to RD or to $31). */
995 || ((pinfo
& INSN_WRITE_GPR_D
)
996 && insn_uses_reg (&prev_insn
,
997 ((ip
->insn_opcode
>> OP_SH_RD
)
1000 || ((pinfo
& INSN_WRITE_GPR_31
)
1001 && insn_uses_reg (&prev_insn
, 31, 0))
1002 /* If the previous previous instruction has a load
1003 delay, and sets a register that the branch reads, we
1005 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1007 && (prev_prev_insn
.insn_mo
->pinfo
1008 & INSN_LOAD_MEMORY_DELAY
)))
1009 && insn_uses_reg (ip
,
1010 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1014 /* We could do even better for unconditional branches to
1015 portions of this object file; we could pick up the
1016 instruction at the destination, put it in the delay
1017 slot, and bump the destination address. */
1019 /* Update the previous insn information. */
1020 prev_prev_insn
= *ip
;
1021 prev_insn
.insn_mo
= &dummy_opcode
;
1028 /* It looks like we can actually do the swap. */
1029 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1030 memcpy (temp
, prev_f
, 4);
1031 memcpy (prev_f
, f
, 4);
1032 memcpy (f
, temp
, 4);
1035 prev_insn_fixp
->fx_frag
= frag_now
;
1036 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1040 fixp
->fx_frag
= prev_insn_frag
;
1041 fixp
->fx_where
= prev_insn_where
;
1043 /* Update the previous insn information; leave prev_insn
1045 prev_prev_insn
= *ip
;
1047 prev_insn_is_delay_slot
= 1;
1049 /* If that was an unconditional branch, forget the previous
1050 insn information. */
1051 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1053 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1054 prev_insn
.insn_mo
= &dummy_opcode
;
1057 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1059 /* We don't yet optimize a branch likely. What we should do
1060 is look at the target, copy the instruction found there
1061 into the delay slot, and increment the branch to jump to
1062 the next instruction. */
1064 /* Update the previous insn information. */
1065 prev_prev_insn
= *ip
;
1066 prev_insn
.insn_mo
= &dummy_opcode
;
1070 /* Update the previous insn information. */
1072 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1074 prev_prev_insn
= prev_insn
;
1077 /* Any time we see a branch, we always fill the delay slot
1078 immediately; since this insn is not a branch, we know it
1079 is not in a delay slot. */
1080 prev_insn_is_delay_slot
= 0;
1083 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1084 prev_insn_unreordered
= 0;
1085 prev_insn_frag
= frag_now
;
1086 prev_insn_where
= f
- frag_now
->fr_literal
;
1087 prev_insn_fixp
= fixp
;
1088 prev_insn_valid
= 1;
1091 /* We just output an insn, so the next one doesn't have a label. */
1095 /* This function forgets that there was any previous instruction or
1099 mips_no_prev_insn ()
1101 prev_insn
.insn_mo
= &dummy_opcode
;
1102 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1103 prev_insn_valid
= 0;
1104 prev_insn_is_delay_slot
= 0;
1105 prev_insn_unreordered
= 0;
1106 prev_prev_insn_unreordered
= 0;
1110 /* This function must be called whenever we turn on noreorder or emit
1111 something other than instructions. It inserts any NOPS which might
1112 be needed by the previous instruction, and clears the information
1113 kept for the previous instructions. */
1118 if (! mips_noreorder
)
1123 if ((prev_insn
.insn_mo
->pinfo
1124 & (INSN_LOAD_COPROC_DELAY
1125 | INSN_COPROC_MOVE_DELAY
1126 | INSN_WRITE_COND_CODE
1130 && (prev_insn
.insn_mo
->pinfo
1131 & (INSN_LOAD_MEMORY_DELAY
1132 | INSN_COPROC_MEMORY_DELAY
))))
1135 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1136 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1137 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1140 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1141 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1142 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1147 if (insn_label
!= NULL
)
1149 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1150 insn_label
->sy_frag
= frag_now
;
1151 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1154 mips_no_prev_insn ();
1158 /* Build an instruction created by a macro expansion. This is passed
1159 a pointer to the count of instructions created so far, an
1160 expression, the name of the instruction to build, an operand format
1161 string, and corresponding arguments. */
1165 macro_build (char *place
,
1171 #else /* ! defined (NO_STDARG) */
1173 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1180 #endif /* ! defined (NO_STDARG) */
1182 struct mips_cl_insn insn
;
1183 bfd_reloc_code_real_type r
;
1187 va_start (args
, fmt
);
1193 * If the macro is about to expand into a second instruction,
1194 * print a warning if needed. We need to pass ip as a parameter
1195 * to generate a better warning message here...
1197 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1198 as_warn ("Macro instruction expanded into multiple instructions");
1201 *counter
+= 1; /* bump instruction counter */
1203 r
= BFD_RELOC_UNUSED
;
1204 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1205 assert (insn
.insn_mo
);
1206 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1208 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1209 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1212 assert (insn
.insn_mo
->name
);
1213 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1215 insn
.insn_opcode
= insn
.insn_mo
->match
;
1231 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1237 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1242 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1247 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1254 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1258 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1262 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1269 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1275 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1276 assert (r
== BFD_RELOC_MIPS_GPREL
1277 || r
== BFD_RELOC_MIPS_LITERAL
1278 || r
== BFD_RELOC_LO16
1279 || r
== BFD_RELOC_MIPS_GOT16
1280 || r
== BFD_RELOC_MIPS_CALL16
);
1284 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1285 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1290 assert (ep
!= NULL
);
1292 * This allows macro() to pass an immediate expression for
1293 * creating short branches without creating a symbol.
1294 * Note that the expression still might come from the assembly
1295 * input, in which case the value is not checked for range nor
1296 * is a relocation entry generated (yuck).
1298 if (ep
->X_op
== O_constant
)
1300 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1304 r
= BFD_RELOC_16_PCREL_S2
;
1308 assert (ep
!= NULL
);
1309 r
= BFD_RELOC_MIPS_JMP
;
1318 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1320 append_insn (place
, &insn
, ep
, r
);
1324 * Generate a "lui" instruction.
1327 macro_build_lui (place
, counter
, ep
, regnum
)
1333 expressionS high_expr
;
1334 struct mips_cl_insn insn
;
1335 bfd_reloc_code_real_type r
;
1336 CONST
char *name
= "lui";
1337 CONST
char *fmt
= "t,u";
1343 high_expr
.X_op
= O_constant
;
1344 high_expr
.X_add_number
= 0;
1347 if (high_expr
.X_op
== O_constant
)
1349 /* we can compute the instruction now without a relocation entry */
1350 if (high_expr
.X_add_number
& 0x8000)
1351 high_expr
.X_add_number
+= 0x10000;
1352 high_expr
.X_add_number
=
1353 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1354 r
= BFD_RELOC_UNUSED
;
1358 assert (ep
->X_op
== O_symbol
);
1359 /* _gp_disp is a special case, used from s_cpload. */
1360 assert (mips_pic
== 0
1361 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1362 r
= BFD_RELOC_HI16_S
;
1366 * If the macro is about to expand into a second instruction,
1367 * print a warning if needed. We need to pass ip as a parameter
1368 * to generate a better warning message here...
1370 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1371 as_warn ("Macro instruction expanded into multiple instructions");
1374 *counter
+= 1; /* bump instruction counter */
1376 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1377 assert (insn
.insn_mo
);
1378 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1379 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1381 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1382 if (r
== BFD_RELOC_UNUSED
)
1384 insn
.insn_opcode
|= high_expr
.X_add_number
;
1385 append_insn (place
, &insn
, NULL
, r
);
1388 append_insn (place
, &insn
, &high_expr
, r
);
1392 * Generates code to set the $at register to true (one)
1393 * if reg is less than the immediate expression.
1396 set_at (counter
, reg
, unsignedp
)
1401 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1402 macro_build ((char *) NULL
, counter
, &imm_expr
,
1403 unsignedp
? "sltiu" : "slti",
1404 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1407 load_register (counter
, AT
, &imm_expr
);
1408 macro_build ((char *) NULL
, counter
, NULL
,
1409 unsignedp
? "sltu" : "slt",
1410 "d,v,t", AT
, reg
, AT
);
1414 /* Warn if an expression is not a constant. */
1417 check_absolute_expr (ip
, ex
)
1418 struct mips_cl_insn
*ip
;
1421 if (ex
->X_op
!= O_constant
)
1422 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1426 * This routine generates the least number of instructions neccessary to load
1427 * an absolute expression value into a register.
1430 load_register (counter
, reg
, ep
)
1435 assert (ep
->X_op
== O_constant
);
1436 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1437 macro_build ((char *) NULL
, counter
, ep
,
1438 mips_isa
< 3 ? "addiu" : "daddiu",
1439 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1440 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1441 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1442 (int) BFD_RELOC_LO16
);
1443 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1444 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1445 == ~ (offsetT
) 0x7fffffff))
1447 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
);
1448 if ((ep
->X_add_number
& 0xffff) != 0)
1449 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1450 (int) BFD_RELOC_LO16
);
1452 else if (mips_isa
< 3)
1454 as_bad ("Number larger than 32 bits");
1455 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1456 (int) BFD_RELOC_LO16
);
1461 expressionS hi32
, lo32
;
1465 hi32
.X_add_number
>>= shift
;
1466 hi32
.X_add_number
&= 0xffffffff;
1467 if ((hi32
.X_add_number
& 0x80000000) != 0)
1468 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1469 load_register (counter
, reg
, &hi32
);
1471 lo32
.X_add_number
&= 0xffffffff;
1472 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1473 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1479 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1482 mid16
.X_add_number
>>= 16;
1483 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1484 reg
, (int) BFD_RELOC_LO16
);
1485 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1488 if ((lo32
.X_add_number
& 0xffff) != 0)
1489 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1490 (int) BFD_RELOC_LO16
);
1494 /* Load an address into a register. */
1497 load_address (counter
, reg
, ep
)
1504 if (ep
->X_op
!= O_constant
1505 && ep
->X_op
!= O_symbol
)
1507 as_bad ("expression too complex");
1508 ep
->X_op
= O_constant
;
1511 if (ep
->X_op
== O_constant
)
1512 load_register (counter
, reg
, ep
);
1513 else if (mips_pic
== 0)
1515 /* If this is a reference to a GP relative symbol, we want
1516 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1518 lui $reg,$gp,<sym> (BFD_RELOC_HI16_S)
1519 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1520 If we have an addend, we always use the latter form. */
1521 if (ep
->X_add_number
!= 0)
1526 macro_build ((char *) NULL
, counter
, ep
,
1527 mips_isa
< 3 ? "addiu" : "daddiu",
1528 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1529 p
= frag_var (rs_machine_dependent
, 8, 0,
1530 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1531 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1533 macro_build_lui (p
, counter
, ep
, reg
);
1536 macro_build (p
, counter
, ep
,
1537 mips_isa
< 3 ? "addiu" : "daddiu",
1538 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1544 /* If this is a reference to an external symbol, we want
1545 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1547 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1549 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1550 If there is a constant, it must be added in afterward. */
1551 ex
.X_add_number
= ep
->X_add_number
;
1552 ep
->X_add_number
= 0;
1554 macro_build ((char *) NULL
, counter
, ep
,
1555 mips_isa
< 3 ? "lw" : "ld",
1556 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1557 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1558 p
= frag_var (rs_machine_dependent
, 4, 0,
1559 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1560 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1561 macro_build (p
, counter
, ep
,
1562 mips_isa
< 3 ? "addiu" : "daddiu",
1563 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1564 if (ex
.X_add_number
!= 0)
1566 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1567 as_bad ("PIC code offset overflow (max 16 signed bits)");
1568 ex
.X_op
= O_constant
;
1569 macro_build (p
, counter
, &ex
,
1570 mips_isa
< 3 ? "addiu" : "daddiu",
1571 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1578 * This routine implements the seemingly endless macro or synthesized
1579 * instructions and addressing modes in the mips assembly language. Many
1580 * of these macros are simple and are similar to each other. These could
1581 * probably be handled by some kind of table or grammer aproach instead of
1582 * this verbose method. Others are not simple macros but are more like
1583 * optimizing code generation.
1584 * One interesting optimization is when several store macros appear
1585 * consecutivly that would load AT with the upper half of the same address.
1586 * The ensuing load upper instructions are ommited. This implies some kind
1587 * of global optimization. We currently only optimize within a single macro.
1588 * For many of the load and store macros if the address is specified as a
1589 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1590 * first load register 'at' with zero and use it as the base register. The
1591 * mips assembler simply uses register $zero. Just one tiny optimization
1596 struct mips_cl_insn
*ip
;
1598 register int treg
, sreg
, dreg
, breg
;
1611 bfd_reloc_code_real_type r
;
1614 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1615 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1616 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1617 mask
= ip
->insn_mo
->mask
;
1619 expr1
.X_op
= O_constant
;
1620 expr1
.X_op_symbol
= NULL
;
1621 expr1
.X_add_symbol
= NULL
;
1622 expr1
.X_add_number
= 1;
1634 mips_emit_delays ();
1636 mips_any_noreorder
= 1;
1638 expr1
.X_add_number
= 8;
1639 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1641 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1643 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1644 macro_build ((char *) NULL
, &icnt
, NULL
,
1645 dbl
? "dsub" : "sub",
1646 "d,v,t", dreg
, 0, sreg
);
1669 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1671 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1672 (int) BFD_RELOC_LO16
);
1675 load_register (&icnt
, AT
, &imm_expr
);
1676 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1695 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1697 if (mask
!= M_NOR_I
)
1698 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1699 sreg
, (int) BFD_RELOC_LO16
);
1702 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1703 treg
, sreg
, (int) BFD_RELOC_LO16
);
1704 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "nor", "d,v,t",
1710 load_register (&icnt
, AT
, &imm_expr
);
1711 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1728 if (imm_expr
.X_add_number
== 0)
1730 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1734 load_register (&icnt
, AT
, &imm_expr
);
1735 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1743 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1744 likely
? "bgezl" : "bgez",
1750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1751 likely
? "blezl" : "blez",
1755 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1756 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1757 likely
? "beql" : "beq",
1764 /* check for > max integer */
1765 maxnum
= 0x7fffffff;
1773 if (imm_expr
.X_add_number
>= maxnum
)
1776 /* result is always false */
1779 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1780 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1784 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1785 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1790 imm_expr
.X_add_number
++;
1794 if (mask
== M_BGEL_I
)
1796 if (imm_expr
.X_add_number
== 0)
1798 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1799 likely
? "bgezl" : "bgez",
1803 if (imm_expr
.X_add_number
== 1)
1805 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1806 likely
? "bgtzl" : "bgtz",
1810 maxnum
= 0x7fffffff;
1818 maxnum
= - maxnum
- 1;
1819 if (imm_expr
.X_add_number
<= maxnum
)
1822 /* result is always true */
1823 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1824 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1827 set_at (&icnt
, sreg
, 0);
1828 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1829 likely
? "beql" : "beq",
1840 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1841 likely
? "beql" : "beq",
1845 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1847 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1848 likely
? "beql" : "beq",
1855 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1857 imm_expr
.X_add_number
++;
1861 if (mask
== M_BGEUL_I
)
1863 if (imm_expr
.X_add_number
== 0)
1865 if (imm_expr
.X_add_number
== 1)
1867 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1868 likely
? "bnel" : "bne",
1872 set_at (&icnt
, sreg
, 1);
1873 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1874 likely
? "beql" : "beq",
1883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1884 likely
? "bgtzl" : "bgtz",
1890 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1891 likely
? "bltzl" : "bltz",
1895 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1896 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1897 likely
? "bnel" : "bne",
1906 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1907 likely
? "bnel" : "bne",
1913 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1915 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1916 likely
? "bnel" : "bne",
1925 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1926 likely
? "blezl" : "blez",
1932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1933 likely
? "bgezl" : "bgez",
1937 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1938 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1939 likely
? "beql" : "beq",
1946 maxnum
= 0x7fffffff;
1954 if (imm_expr
.X_add_number
>= maxnum
)
1956 imm_expr
.X_add_number
++;
1960 if (mask
== M_BLTL_I
)
1962 if (imm_expr
.X_add_number
== 0)
1964 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1965 likely
? "bltzl" : "bltz",
1969 if (imm_expr
.X_add_number
== 1)
1971 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1972 likely
? "blezl" : "blez",
1976 set_at (&icnt
, sreg
, 0);
1977 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1978 likely
? "bnel" : "bne",
1987 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1988 likely
? "beql" : "beq",
1994 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1996 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1997 likely
? "beql" : "beq",
2004 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2006 imm_expr
.X_add_number
++;
2010 if (mask
== M_BLTUL_I
)
2012 if (imm_expr
.X_add_number
== 0)
2014 if (imm_expr
.X_add_number
== 1)
2016 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2017 likely
? "beql" : "beq",
2021 set_at (&icnt
, sreg
, 1);
2022 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2023 likely
? "bnel" : "bne",
2032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2033 likely
? "bltzl" : "bltz",
2039 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2040 likely
? "bgtzl" : "bgtz",
2044 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2045 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2046 likely
? "bnel" : "bne",
2057 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2058 likely
? "bnel" : "bne",
2062 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2064 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2065 likely
? "bnel" : "bne",
2081 as_warn ("Divide by zero.");
2082 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2086 mips_emit_delays ();
2088 mips_any_noreorder
= 1;
2089 macro_build ((char *) NULL
, &icnt
, NULL
,
2090 dbl
? "ddiv" : "div",
2091 "z,s,t", sreg
, treg
);
2092 expr1
.X_add_number
= 8;
2093 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2094 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2095 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2096 expr1
.X_add_number
= -1;
2097 macro_build ((char *) NULL
, &icnt
, &expr1
,
2098 dbl
? "daddiu" : "addiu",
2099 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2100 expr1
.X_add_number
= dbl
? 20 : 16;
2101 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2104 expr1
.X_add_number
= 1;
2105 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2106 (int) BFD_RELOC_LO16
);
2107 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2112 expr1
.X_add_number
= 0x80000000;
2113 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
);
2115 expr1
.X_add_number
= 8;
2116 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2117 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2118 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2120 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2159 if (imm_expr
.X_add_number
== 0)
2161 as_warn ("Divide by zero.");
2162 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2165 if (imm_expr
.X_add_number
== 1)
2167 if (strcmp (s2
, "mflo") == 0)
2168 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2171 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2174 if (imm_expr
.X_add_number
== -1
2175 && s
[strlen (s
) - 1] != 'u')
2177 if (strcmp (s2
, "mflo") == 0)
2180 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2183 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2187 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2191 load_register (&icnt
, AT
, &imm_expr
);
2192 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2193 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2212 mips_emit_delays ();
2214 mips_any_noreorder
= 1;
2215 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2216 expr1
.X_add_number
= 8;
2217 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2218 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2219 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2221 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2225 /* Load the address of a symbol into a register. If M_LA_AB, we
2226 then add a base register to it. */
2227 if (offset_expr
.X_op
!= O_symbol
2228 && offset_expr
.X_op
!= O_constant
)
2230 as_bad ("expression too complex");
2231 offset_expr
.X_op
= O_constant
;
2245 if (offset_expr
.X_op
== O_constant
)
2246 load_register (&icnt
, tempreg
, &offset_expr
);
2247 else if (mips_pic
== 0)
2249 /* If this is a reference to an GP relative symbol, we want
2250 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2252 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2253 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2254 If we have a constant, we need two instructions anyhow,
2255 so we may as well always use the latter form. */
2256 if (offset_expr
.X_add_number
!= 0)
2261 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2262 mips_isa
< 3 ? "addiu" : "daddiu",
2263 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2264 p
= frag_var (rs_machine_dependent
, 8, 0,
2265 RELAX_ENCODE (4, 8, 0, 4, 0,
2266 mips_warn_about_macros
),
2267 offset_expr
.X_add_symbol
, (long) 0,
2270 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2273 macro_build (p
, &icnt
, &offset_expr
,
2274 mips_isa
< 3 ? "addiu" : "daddiu",
2275 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2279 /* If this is a reference to an external symbol, and there
2280 is no constant, we want
2281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2282 For a local symbol, we want
2283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2285 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2287 If we have a small constant, and this is a reference to
2288 an external symbol, we want
2289 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2291 addiu $tempreg,$tempreg,<constant>
2292 For a local symbol, we want the same instruction
2293 sequence, but we output a BFD_RELOC_LO16 reloc on the
2296 If we have a large constant, and this is a reference to
2297 an external symbol, we want
2298 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2299 lui $at,<hiconstant>
2300 addiu $at,$at,<loconstant>
2301 addu $tempreg,$tempreg,$at
2302 For a local symbol, we want the same instruction
2303 sequence, but we output a BFD_RELOC_LO16 reloc on the
2304 addiu instruction. */
2305 expr1
.X_add_number
= offset_expr
.X_add_number
;
2306 offset_expr
.X_add_number
= 0;
2308 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2309 mips_isa
< 3 ? "lw" : "ld",
2310 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2311 if (expr1
.X_add_number
== 0)
2319 /* We're going to put in an addu instruction using
2320 tempreg, so we may as well insert the nop right
2322 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2326 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2327 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2329 ? mips_warn_about_macros
2331 offset_expr
.X_add_symbol
, (long) 0,
2335 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2338 macro_build (p
, &icnt
, &expr1
,
2339 mips_isa
< 3 ? "addiu" : "daddiu",
2340 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2341 /* FIXME: If breg == 0, and the next instruction uses
2342 $tempreg, then if this variant case is used an extra
2343 nop will be generated. */
2345 else if (expr1
.X_add_number
>= -0x8000
2346 && expr1
.X_add_number
< 0x8000)
2348 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2350 macro_build ((char *) NULL
, &icnt
, &expr1
,
2351 mips_isa
< 3 ? "addiu" : "daddiu",
2352 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2353 (void) frag_var (rs_machine_dependent
, 0, 0,
2354 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2355 offset_expr
.X_add_symbol
, (long) 0,
2362 /* If we are going to add in a base register, and the
2363 target register and the base register are the same,
2364 then we are using AT as a temporary register. Since
2365 we want to load the constant into AT, we add our
2366 current AT (from the global offset table) and the
2367 register into the register now, and pretend we were
2368 not using a base register. */
2373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2375 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2376 mips_isa
< 3 ? "addu" : "daddu",
2377 "d,v,t", treg
, AT
, breg
);
2383 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2384 macro_build ((char *) NULL
, &icnt
, &expr1
,
2385 mips_isa
< 3 ? "addiu" : "daddiu",
2386 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2387 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2388 mips_isa
< 3 ? "addu" : "daddu",
2389 "d,v,t", tempreg
, tempreg
, AT
);
2390 (void) frag_var (rs_machine_dependent
, 0, 0,
2391 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2392 offset_expr
.X_add_symbol
, (long) 0,
2399 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2400 mips_isa
< 3 ? "addu" : "daddu",
2401 "d,v,t", treg
, tempreg
, breg
);
2409 /* The j instruction may not be used in PIC code, since it
2410 requires an absolute address. We convert it to a b
2413 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2415 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2418 /* The jal instructions must be handled as macros because when
2419 generating PIC code they expand to multi-instruction
2420 sequences. Normally they are simple instructions. */
2427 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2432 /* I only know how to handle pic2. */
2433 assert (mips_pic
== 2);
2435 if (sreg
!= PIC_CALL_REG
)
2436 as_warn ("MIPS PIC call to register other than $25");
2438 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
2440 if (mips_cprestore_offset
< 0)
2441 as_warn ("No .cprestore pseudo-op used in PIC code");
2444 expr1
.X_add_number
= mips_cprestore_offset
;
2445 macro_build ((char *) NULL
, &icnt
, &expr1
,
2446 mips_isa
< 3 ? "lw" : "ld",
2447 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2454 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2458 /* I only know how to handle pic2. */
2459 assert (mips_pic
== 2);
2461 /* If this is a reference to an external symbol, we want
2462 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2466 lw $gp,cprestore($sp)
2467 The cprestore value is set using the .cprestore pseudo-op.
2468 If the symbol is not external, we want
2469 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2471 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2474 lw $gp,cprestore($sp)
2477 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2478 mips_isa
< 3 ? "lw" : "ld",
2479 "t,o(b)", PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL16
, GP
);
2480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2481 p
= frag_var (rs_machine_dependent
, 4, 0,
2482 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2483 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2484 macro_build (p
, &icnt
, &offset_expr
,
2485 mips_isa
< 3 ? "addiu" : "daddiu",
2486 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2487 (int) BFD_RELOC_LO16
);
2488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "s",
2490 if (mips_cprestore_offset
< 0)
2491 as_warn ("No .cprestore pseudo-op used in PIC code");
2495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2497 expr1
.X_add_number
= mips_cprestore_offset
;
2498 macro_build ((char *) NULL
, &icnt
, &expr1
,
2499 mips_isa
< 3 ? "lw" : "ld",
2500 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2568 if (breg
== treg
|| coproc
)
2637 if (mask
== M_LWC1_AB
2638 || mask
== M_SWC1_AB
2639 || mask
== M_LDC1_AB
2640 || mask
== M_SDC1_AB
2649 if (offset_expr
.X_op
!= O_constant
2650 && offset_expr
.X_op
!= O_symbol
)
2652 as_bad ("expression too complex");
2653 offset_expr
.X_op
= O_constant
;
2656 /* A constant expression in PIC code can be handled just as it
2657 is in non PIC code. */
2659 || offset_expr
.X_op
== O_constant
)
2661 /* If this is a reference to a GP relative symbol, and there
2662 is no base register, we want
2663 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2665 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2666 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2667 If we have a constant, we need two instructions anyhow,
2668 so we always use the latter form.
2670 If we have a base register, and this is a reference to a
2671 GP relative symbol, we want
2672 addu $tempreg,$breg,$gp
2673 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2675 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2676 addu $tempreg,$tempreg,$breg
2677 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2678 With a constant we always use the latter case. */
2681 if (offset_expr
.X_add_number
!= 0)
2686 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2687 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2688 p
= frag_var (rs_machine_dependent
, 8, 0,
2689 RELAX_ENCODE (4, 8, 0, 4, 0,
2690 mips_warn_about_macros
),
2691 offset_expr
.X_add_symbol
, (long) 0,
2694 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2697 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2698 (int) BFD_RELOC_LO16
, tempreg
);
2702 if (offset_expr
.X_add_number
!= 0)
2707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2708 mips_isa
< 3 ? "addu" : "daddu",
2709 "d,v,t", tempreg
, breg
, GP
);
2710 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2711 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2712 p
= frag_var (rs_machine_dependent
, 12, 0,
2713 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2714 offset_expr
.X_add_symbol
, (long) 0,
2717 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2720 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2721 mips_isa
< 3 ? "addu" : "daddu",
2722 "d,v,t", tempreg
, tempreg
, breg
);
2725 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2726 (int) BFD_RELOC_LO16
, tempreg
);
2731 /* If this is a reference to an external symbol, we want
2732 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2734 <op> $treg,0($tempreg)
2736 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2738 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2739 <op> $treg,0($tempreg)
2740 If there is a base register, we add it to $tempreg before
2741 the <op>. If there is a constant, we stick it in the
2742 <op> instruction. We don't handle constants larger than
2743 16 bits, because we have no way to load the upper 16 bits
2744 (actually, we could handle them for the subset of cases
2745 in which we are not using $at). */
2746 assert (offset_expr
.X_op
== O_symbol
);
2747 expr1
.X_add_number
= offset_expr
.X_add_number
;
2748 offset_expr
.X_add_number
= 0;
2749 if (expr1
.X_add_number
< -0x8000
2750 || expr1
.X_add_number
>= 0x8000)
2751 as_bad ("PIC code offset overflow (max 16 signed bits)");
2753 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2754 mips_isa
< 3 ? "lw" : "ld",
2755 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2757 p
= frag_var (rs_machine_dependent
, 4, 0,
2758 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2759 offset_expr
.X_add_symbol
, (long) 0,
2761 macro_build (p
, &icnt
, &offset_expr
,
2762 mips_isa
< 3 ? "addiu" : "daddiu",
2763 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2765 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2766 mips_isa
< 3 ? "addu" : "daddu",
2767 "d,v,t", tempreg
, tempreg
, breg
);
2768 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2769 (int) BFD_RELOC_LO16
, tempreg
);
2779 load_register (&icnt
, treg
, &imm_expr
);
2785 assert (offset_expr
.X_op
== O_symbol
2786 && strcmp (segment_name (S_GET_SEGMENT
2787 (offset_expr
.X_add_symbol
)),
2789 && offset_expr
.X_add_number
== 0);
2790 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2791 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2795 assert (imm_expr
.X_op
== O_constant
);
2796 load_register (&icnt
, treg
, &imm_expr
);
2801 /* We know that sym is in the .rdata instruction. First we get
2802 the upper 16 bits of the address. */
2805 /* FIXME: This won't work for a 64 bit address. */
2806 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
2810 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2811 mips_isa
< 3 ? "lw" : "ld",
2812 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2814 /* Now we load the register(s). */
2816 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
2817 treg
, (int) BFD_RELOC_LO16
, AT
);
2820 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2821 treg
, (int) BFD_RELOC_LO16
, AT
);
2824 /* FIXME: How in the world do we deal with the possible
2826 offset_expr
.X_add_number
+= 4;
2827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2828 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
2837 /* Load a floating point number from the .lit8 section. */
2838 assert (offset_expr
.X_op
== O_symbol
2839 && strcmp (segment_name (S_GET_SEGMENT
2840 (offset_expr
.X_add_symbol
)),
2842 && offset_expr
.X_add_number
== 0);
2845 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2846 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2850 r
= BFD_RELOC_MIPS_LITERAL
;
2855 /* Load the double from the .rdata section. */
2856 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2857 mips_isa
< 3 ? "lw" : "ld",
2858 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2861 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2862 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
2871 /* Even on a big endian machine $fn comes before $fn+1. We have
2872 to adjust when loading from memory. */
2875 assert (mips_isa
< 2);
2876 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2877 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2879 /* FIXME: A possible overflow which I don't know how to deal
2881 offset_expr
.X_add_number
+= 4;
2882 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2883 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2891 * The MIPS assembler seems to check for X_add_number not
2892 * being double aligned and generating:
2895 * addiu at,at,%lo(foo+1)
2898 * But, the resulting address is the same after relocation so why
2899 * generate the extra instruction?
2946 if (offset_expr
.X_op
!= O_symbol
2947 && offset_expr
.X_op
!= O_constant
)
2949 as_bad ("expression too complex");
2950 offset_expr
.X_op
= O_constant
;
2953 /* Even on a big endian machine $fn comes before $fn+1. We have
2954 to adjust when loading from memory. We set coproc if we must
2955 load $fn+1 first. */
2956 if (byte_order
== LITTLE_ENDIAN
)
2960 || offset_expr
.X_op
== O_constant
)
2962 /* If this is a reference to a GP relative symbol, we want
2963 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2964 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
2965 If we have a base register, we use this
2967 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
2968 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
2969 If this is not a GP relative symbol, we want
2970 lui $at,<sym> (BFD_RELOC_HI16_S)
2971 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
2972 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
2973 If there is a base register, we add it to $at after the
2974 lui instruction. If there is a constant, we always use
2976 if (offset_expr
.X_add_number
!= 0)
2995 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2996 mips_isa
< 3 ? "addu" : "daddu",
2997 "d,v,t", AT
, breg
, GP
);
3003 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3004 coproc
? treg
+ 1 : treg
,
3005 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3006 offset_expr
.X_add_number
+= 4;
3007 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3008 coproc
? treg
: treg
+ 1,
3009 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3010 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3011 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3012 ! used_at
&& mips_noat
),
3013 offset_expr
.X_add_symbol
, (long) 0,
3016 /* We just generated two relocs. When tc_gen_reloc
3017 handles this case, it will skip the first reloc and
3018 handle the second. The second reloc already has an
3019 extra addend of 4, which we added above. We must
3020 subtract it out, and then subtract another 4 to make
3021 the first reloc come out right. The second reloc
3022 will come out right because we are going to add 4 to
3023 offset_expr when we build its instruction below. */
3024 offset_expr
.X_add_number
-= 8;
3025 offset_expr
.X_op
= O_constant
;
3027 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3032 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3033 mips_isa
< 3 ? "addu" : "daddu",
3034 "d,v,t", AT
, breg
, AT
);
3038 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3039 coproc
? treg
+ 1 : treg
,
3040 (int) BFD_RELOC_LO16
, AT
);
3043 /* FIXME: How do we handle overflow here? */
3044 offset_expr
.X_add_number
+= 4;
3045 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3046 coproc
? treg
: treg
+ 1,
3047 (int) BFD_RELOC_LO16
, AT
);
3053 /* If this is a reference to an external symbol, we want
3054 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3059 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3061 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3062 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3063 If there is a base register we add it to $at before the
3064 lwc1 instructions. If there is a constant we include it
3065 in the lwc1 instructions. */
3067 expr1
.X_add_number
= offset_expr
.X_add_number
;
3068 offset_expr
.X_add_number
= 0;
3069 if (expr1
.X_add_number
< -0x8000
3070 || expr1
.X_add_number
>= 0x8000 - 4)
3071 as_bad ("PIC code offset overflow (max 16 signed bits)");
3076 frag_grow (16 + off
);
3077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3078 mips_isa
< 3 ? "lw" : "ld",
3079 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3083 mips_isa
< 3 ? "addu" : "daddu",
3084 "d,v,t", AT
, breg
, AT
);
3085 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3086 coproc
? treg
+ 1 : treg
,
3087 (int) BFD_RELOC_LO16
, AT
);
3088 expr1
.X_add_number
+= 4;
3089 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3090 coproc
? treg
: treg
+ 1,
3091 (int) BFD_RELOC_LO16
, AT
);
3092 (void) frag_var (rs_machine_dependent
, 0, 0,
3093 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3094 offset_expr
.X_add_symbol
, (long) 0,
3109 assert (mips_isa
< 3);
3110 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3111 (int) BFD_RELOC_LO16
, breg
);
3112 offset_expr
.X_add_number
+= 4;
3113 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3114 (int) BFD_RELOC_LO16
, breg
);
3120 macro_build ((char *) NULL
, &icnt
, NULL
,
3121 dbl
? "dmultu" : "multu",
3123 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3129 /* The MIPS assembler some times generates shifts and adds. I'm
3130 not trying to be that fancy. GCC should do this for us
3132 load_register (&icnt
, AT
, &imm_expr
);
3133 macro_build ((char *) NULL
, &icnt
, NULL
,
3134 dbl
? "dmult" : "mult",
3136 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3142 mips_emit_delays ();
3144 mips_any_noreorder
= 1;
3145 macro_build ((char *) NULL
, &icnt
, NULL
,
3146 dbl
? "dmult" : "mult",
3148 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3149 macro_build ((char *) NULL
, &icnt
, NULL
,
3150 dbl
? "dsra32" : "sra",
3151 "d,w,<", dreg
, dreg
, 31);
3152 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3153 expr1
.X_add_number
= 8;
3154 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3155 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3156 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3158 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3164 mips_emit_delays ();
3166 mips_any_noreorder
= 1;
3167 macro_build ((char *) NULL
, &icnt
, NULL
,
3168 dbl
? "dmultu" : "multu",
3170 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3171 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3172 expr1
.X_add_number
= 8;
3173 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3174 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3175 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3180 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3181 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3182 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3184 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3188 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3189 imm_expr
.X_add_number
& 0x1f);
3190 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3191 (0 - imm_expr
.X_add_number
) & 0x1f);
3192 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3196 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3197 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3198 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3200 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3204 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3205 imm_expr
.X_add_number
& 0x1f);
3206 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3207 (0 - imm_expr
.X_add_number
) & 0x1f);
3208 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3212 assert (mips_isa
< 2);
3213 /* Even on a big endian machine $fn comes before $fn+1. We have
3214 to adjust when storing to memory. */
3215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3216 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3217 (int) BFD_RELOC_LO16
, breg
);
3218 offset_expr
.X_add_number
+= 4;
3219 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3220 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3221 (int) BFD_RELOC_LO16
, breg
);
3226 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3227 treg
, (int) BFD_RELOC_LO16
);
3229 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3230 sreg
, (int) BFD_RELOC_LO16
);
3233 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3235 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3236 dreg
, (int) BFD_RELOC_LO16
);
3241 if (imm_expr
.X_add_number
== 0)
3243 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3244 sreg
, (int) BFD_RELOC_LO16
);
3249 as_warn ("Instruction %s: result is always false",
3251 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3254 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3256 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3257 sreg
, (int) BFD_RELOC_LO16
);
3260 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3262 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3263 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3264 mips_isa
< 3 ? "addiu" : "daddiu",
3265 "t,r,j", dreg
, sreg
,
3266 (int) BFD_RELOC_LO16
);
3271 load_register (&icnt
, AT
, &imm_expr
);
3272 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3276 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3277 (int) BFD_RELOC_LO16
);
3282 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3288 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3289 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3290 (int) BFD_RELOC_LO16
);
3293 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3295 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3297 macro_build ((char *) NULL
, &icnt
, &expr1
,
3298 mask
== M_SGE_I
? "slti" : "sltiu",
3299 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3304 load_register (&icnt
, AT
, &imm_expr
);
3305 macro_build ((char *) NULL
, &icnt
, NULL
,
3306 mask
== M_SGE_I
? "slt" : "sltu",
3307 "d,v,t", dreg
, sreg
, AT
);
3310 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3311 (int) BFD_RELOC_LO16
);
3316 case M_SGT
: /* sreg > treg <==> treg < sreg */
3322 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3325 case M_SGT_I
: /* sreg > I <==> I < sreg */
3331 load_register (&icnt
, AT
, &imm_expr
);
3332 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3335 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3341 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3342 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3343 (int) BFD_RELOC_LO16
);
3346 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3352 load_register (&icnt
, AT
, &imm_expr
);
3353 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3354 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3355 (int) BFD_RELOC_LO16
);
3359 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3361 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3362 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3365 load_register (&icnt
, AT
, &imm_expr
);
3366 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3370 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3372 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3373 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3376 load_register (&icnt
, AT
, &imm_expr
);
3377 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3383 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3386 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3390 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3392 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3398 if (imm_expr
.X_add_number
== 0)
3400 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3406 as_warn ("Instruction %s: result is always true",
3408 macro_build ((char *) NULL
, &icnt
, &expr1
,
3409 mips_isa
< 3 ? "addiu" : "daddiu",
3410 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3413 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3415 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3416 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3419 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3421 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3422 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3423 mips_isa
< 3 ? "addiu" : "daddiu",
3424 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3429 load_register (&icnt
, AT
, &imm_expr
);
3430 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3434 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3442 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3444 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3445 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3446 dbl
? "daddi" : "addi",
3447 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3450 load_register (&icnt
, AT
, &imm_expr
);
3451 macro_build ((char *) NULL
, &icnt
, NULL
,
3452 dbl
? "dsub" : "sub",
3453 "d,v,t", dreg
, sreg
, AT
);
3459 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3461 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3462 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3463 dbl
? "daddiu" : "addiu",
3464 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3467 load_register (&icnt
, AT
, &imm_expr
);
3468 macro_build ((char *) NULL
, &icnt
, NULL
,
3469 dbl
? "dsubu" : "subu",
3470 "d,v,t", dreg
, sreg
, AT
);
3491 load_register (&icnt
, AT
, &imm_expr
);
3492 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3497 assert (mips_isa
< 2);
3498 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3499 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3502 * Is the double cfc1 instruction a bug in the mips assembler;
3503 * or is there a reason for it?
3505 mips_emit_delays ();
3507 mips_any_noreorder
= 1;
3508 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3509 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3510 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3511 expr1
.X_add_number
= 3;
3512 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3513 (int) BFD_RELOC_LO16
);
3514 expr1
.X_add_number
= 2;
3515 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3516 (int) BFD_RELOC_LO16
);
3517 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3518 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3519 macro_build ((char *) NULL
, &icnt
, NULL
,
3520 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3521 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3522 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3532 /* avoid load delay */
3533 offset_expr
.X_add_number
+= 1;
3534 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3535 (int) BFD_RELOC_LO16
, breg
);
3536 offset_expr
.X_add_number
-= 1;
3537 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3538 (int) BFD_RELOC_LO16
, breg
);
3539 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3540 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3544 /* does this work on a big endian machine? */
3545 offset_expr
.X_add_number
+= 3;
3546 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3547 (int) BFD_RELOC_LO16
, breg
);
3548 offset_expr
.X_add_number
-= 3;
3549 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3550 (int) BFD_RELOC_LO16
, breg
);
3556 load_address (&icnt
, AT
, &offset_expr
);
3557 if (mask
== M_ULW_A
)
3559 expr1
.X_add_number
= 3;
3560 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3561 (int) BFD_RELOC_LO16
, AT
);
3562 expr1
.X_add_number
= 0;
3563 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3564 (int) BFD_RELOC_LO16
, AT
);
3568 macro_build ((char *) NULL
, &icnt
, &expr1
,
3569 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3570 (int) BFD_RELOC_LO16
, AT
);
3571 expr1
.X_add_number
= 0;
3572 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3573 (int) BFD_RELOC_LO16
, AT
);
3574 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3576 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3582 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3583 (int) BFD_RELOC_LO16
, breg
);
3584 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3585 offset_expr
.X_add_number
+= 1;
3586 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3587 (int) BFD_RELOC_LO16
, breg
);
3591 offset_expr
.X_add_number
+= 3;
3592 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3593 (int) BFD_RELOC_LO16
, breg
);
3594 offset_expr
.X_add_number
-= 3;
3595 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3596 (int) BFD_RELOC_LO16
, breg
);
3601 load_address (&icnt
, AT
, &offset_expr
);
3602 if (mask
== M_USW_A
)
3604 expr1
.X_add_number
= 3;
3605 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3606 (int) BFD_RELOC_LO16
, AT
);
3607 expr1
.X_add_number
= 0;
3608 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3609 (int) BFD_RELOC_LO16
, AT
);
3613 expr1
.X_add_number
= 0;
3614 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3615 (int) BFD_RELOC_LO16
, AT
);
3616 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3618 expr1
.X_add_number
= 1;
3619 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3620 (int) BFD_RELOC_LO16
, AT
);
3621 expr1
.X_add_number
= 0;
3622 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3623 (int) BFD_RELOC_LO16
, AT
);
3624 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3626 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3632 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3636 as_warn ("Macro used $at after \".set noat\"");
3641 This routine assembles an instruction into its binary format. As a side
3642 effect it sets one of the global variables imm_reloc or offset_reloc to the
3643 type of relocation to do if one of the operands is an address expression.
3648 struct mips_cl_insn
*ip
;
3653 struct mips_opcode
*insn
;
3656 unsigned int lastregno
= 0;
3661 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
3673 as_warn ("Unknown opcode: `%s'", str
);
3676 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
3678 as_warn ("`%s' not in hash table.", str
);
3679 insn_error
= "ERROR: Unrecognized opcode";
3687 assert (strcmp (insn
->name
, str
) == 0);
3689 if (insn
->pinfo
== INSN_MACRO
)
3690 insn_isa
= insn
->match
;
3691 else if (insn
->pinfo
& INSN_ISA2
)
3693 else if (insn
->pinfo
& INSN_ISA3
)
3698 if (insn_isa
> mips_isa
)
3700 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
3701 && strcmp (insn
->name
, insn
[1].name
) == 0)
3706 insn_error
= "ERROR: instruction not supported on this processor";
3711 ip
->insn_opcode
= insn
->match
;
3712 for (args
= insn
->args
;; ++args
)
3718 case '\0': /* end of args */
3731 ip
->insn_opcode
|= lastregno
<< 21;
3736 ip
->insn_opcode
|= lastregno
<< 16;
3740 ip
->insn_opcode
|= lastregno
<< 11;
3746 /* handle optional base register.
3747 Either the base register is omitted or
3748 we must have a left paren. */
3749 /* this is dependent on the next operand specifier
3750 is a 'b' for base register */
3751 assert (args
[1] == 'b');
3755 case ')': /* these must match exactly */
3760 case '<': /* must be at least one digit */
3762 * According to the manual, if the shift amount is greater
3763 * than 31 or less than 0 the the shift amount should be
3764 * mod 32. In reality the mips assembler issues an error.
3765 * We issue a warning and mask out all but the low 5 bits.
3767 my_getExpression (&imm_expr
, s
);
3768 check_absolute_expr (ip
, &imm_expr
);
3769 if ((unsigned long) imm_expr
.X_add_number
> 31)
3771 as_warn ("Improper shift amount (%ld)",
3772 (long) imm_expr
.X_add_number
);
3773 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
3775 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3776 imm_expr
.X_op
= O_absent
;
3780 case '>': /* shift amount minus 32 */
3781 my_getExpression (&imm_expr
, s
);
3782 check_absolute_expr (ip
, &imm_expr
);
3783 if ((unsigned long) imm_expr
.X_add_number
< 32
3784 || (unsigned long) imm_expr
.X_add_number
> 63)
3786 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
3787 imm_expr
.X_op
= O_absent
;
3791 case 'k': /* cache code */
3792 my_getExpression (&imm_expr
, s
);
3793 check_absolute_expr (ip
, &imm_expr
);
3794 if ((unsigned long) imm_expr
.X_add_number
> 31)
3796 as_warn ("Invalid cahce opcode (%lu)",
3797 (unsigned long) imm_expr
.X_add_number
);
3798 imm_expr
.X_add_number
&= 0x1f;
3800 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
3801 imm_expr
.X_op
= O_absent
;
3805 case 'c': /* break code */
3806 my_getExpression (&imm_expr
, s
);
3807 check_absolute_expr (ip
, &imm_expr
);
3808 if ((unsigned) imm_expr
.X_add_number
> 1023)
3809 as_warn ("Illegal break code (%ld)",
3810 (long) imm_expr
.X_add_number
);
3811 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3812 imm_expr
.X_op
= O_absent
;
3816 case 'B': /* syscall code */
3817 my_getExpression (&imm_expr
, s
);
3818 check_absolute_expr (ip
, &imm_expr
);
3819 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3820 as_warn ("Illegal syscall code (%ld)",
3821 (long) imm_expr
.X_add_number
);
3822 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3823 imm_expr
.X_op
= O_absent
;
3827 case 'C': /* Coprocessor code */
3828 my_getExpression (&imm_expr
, s
);
3829 check_absolute_expr (ip
, &imm_expr
);
3830 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3832 as_warn ("Coproccesor code > 25 bits (%ld)",
3833 (long) imm_expr
.X_add_number
);
3834 imm_expr
.X_add_number
&= ((1<<25) - 1);
3836 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3837 imm_expr
.X_op
= O_absent
;
3841 case 'b': /* base register */
3842 case 'd': /* destination register */
3843 case 's': /* source register */
3844 case 't': /* target register */
3845 case 'r': /* both target and source */
3846 case 'v': /* both dest and source */
3847 case 'w': /* both dest and target */
3848 case 'E': /* coprocessor target register */
3849 case 'G': /* coprocessor destination register */
3850 case 'x': /* ignore register name */
3851 case 'z': /* must be zero register */
3865 while (isdigit (*s
));
3867 as_bad ("Invalid register number (%d)", regno
);
3869 else if (*args
== 'E' || *args
== 'G')
3873 if (s
[1] == 'f' && s
[2] == 'p')
3878 else if (s
[1] == 's' && s
[2] == 'p')
3883 else if (s
[1] == 'g' && s
[2] == 'p')
3888 else if (s
[1] == 'a' && s
[2] == 't')
3895 if (regno
== AT
&& ! mips_noat
)
3896 as_warn ("Used $at without \".set noat\"");
3903 if (c
== 'r' || c
== 'v' || c
== 'w')
3910 /* 'z' only matches $0. */
3911 if (c
== 'z' && regno
!= 0)
3919 ip
->insn_opcode
|= regno
<< 21;
3923 ip
->insn_opcode
|= regno
<< 11;
3928 ip
->insn_opcode
|= regno
<< 16;
3931 /* This case exists because on the r3000 trunc
3932 expands into a macro which requires a gp
3933 register. On the r6000 or r4000 it is
3934 assembled into a single instruction which
3935 ignores the register. Thus the insn version
3936 is MIPS_ISA2 and uses 'x', and the macro
3937 version is MIPS_ISA1 and uses 't'. */
3940 /* This case is for the div instruction, which
3941 acts differently if the destination argument
3942 is $0. This only matches $0, and is checked
3943 outside the switch. */
3954 ip
->insn_opcode
|= lastregno
<< 21;
3957 ip
->insn_opcode
|= lastregno
<< 16;
3962 case 'D': /* floating point destination register */
3963 case 'S': /* floating point source register */
3964 case 'T': /* floating point target register */
3968 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3978 while (isdigit (*s
));
3981 as_bad ("Invalid float register number (%d)", regno
);
3983 if ((regno
& 1) != 0
3985 && ! (strcmp (str
, "mtc1") == 0 ||
3986 strcmp (str
, "mfc1") == 0 ||
3987 strcmp (str
, "lwc1") == 0 ||
3988 strcmp (str
, "swc1") == 0))
3989 as_warn ("Float register should be even, was %d",
3997 if (c
== 'V' || c
== 'W')
4007 ip
->insn_opcode
|= regno
<< 6;
4011 ip
->insn_opcode
|= regno
<< 11;
4015 ip
->insn_opcode
|= regno
<< 16;
4023 ip
->insn_opcode
|= lastregno
<< 11;
4026 ip
->insn_opcode
|= lastregno
<< 16;
4032 my_getExpression (&imm_expr
, s
);
4033 check_absolute_expr (ip
, &imm_expr
);
4038 my_getExpression (&offset_expr
, s
);
4039 imm_reloc
= BFD_RELOC_32
;
4051 unsigned char temp
[8];
4053 unsigned int length
;
4058 /* These only appear as the last operand in an
4059 instruction, and every instruction that accepts
4060 them in any variant accepts them in all variants.
4061 This means we don't have to worry about backing out
4062 any changes if the instruction does not match.
4064 The difference between them is the size of the
4065 floating point constant and where it goes. For 'F'
4066 and 'L' the constant is 64 bits; for 'f' and 'l' it
4067 is 32 bits. Where the constant is placed is based
4068 on how the MIPS assembler does things:
4071 f -- immediate value
4074 When generating PIC code, we do not use the .lit8
4075 or .lit4 sections at all, in order to reserve the
4076 entire global offset table. */
4078 f64
= *args
== 'F' || *args
== 'L';
4080 save_in
= input_line_pointer
;
4081 input_line_pointer
= s
;
4082 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4084 s
= input_line_pointer
;
4085 input_line_pointer
= save_in
;
4086 if (err
!= NULL
&& *err
!= '\0')
4088 as_bad ("Bad floating point constant: %s", err
);
4089 memset (temp
, '\0', sizeof temp
);
4090 length
= f64
? 8 : 4;
4093 assert (length
== (f64
? 8 : 4));
4096 || (mips_pic
!= 0 && *args
== 'l'))
4098 imm_expr
.X_op
= O_constant
;
4099 if (byte_order
== LITTLE_ENDIAN
)
4100 imm_expr
.X_add_number
=
4101 (((((((int) temp
[3] << 8)
4106 imm_expr
.X_add_number
=
4107 (((((((int) temp
[0] << 8)
4114 const char *newname
;
4117 /* Switch to the right section. */
4119 subseg
= now_subseg
;
4122 default: /* unused default case avoids warnings. */
4124 newname
= (mips_pic
== 0 ? ".lit8" : ".rdata");
4130 assert (mips_pic
== 0);
4134 new_seg
= subseg_new (newname
, (subsegT
) 0);
4136 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4139 as_bad ("Can't use floating point insn in this section");
4141 /* Set the argument to the current address in the
4143 offset_expr
.X_op
= O_symbol
;
4144 offset_expr
.X_add_symbol
=
4145 symbol_new ("L0\001", now_seg
,
4146 (valueT
) frag_now_fix (), frag_now
);
4147 offset_expr
.X_add_number
= 0;
4149 /* Put the floating point number into the section. */
4150 p
= frag_more ((int) length
);
4151 memcpy (p
, temp
, length
);
4153 /* Switch back to the original section. */
4154 subseg_set (seg
, subseg
);
4159 case 'i': /* 16 bit unsigned immediate */
4160 case 'j': /* 16 bit signed immediate */
4161 imm_reloc
= BFD_RELOC_LO16
;
4162 c
= my_getSmallExpression (&imm_expr
, s
);
4167 if (imm_expr
.X_op
== O_constant
)
4168 imm_expr
.X_add_number
=
4169 (imm_expr
.X_add_number
>> 16) & 0xffff;
4171 imm_reloc
= BFD_RELOC_HI16_S
;
4173 imm_reloc
= BFD_RELOC_HI16
;
4177 check_absolute_expr (ip
, &imm_expr
);
4180 if (imm_expr
.X_add_number
< 0
4181 || imm_expr
.X_add_number
>= 0x10000)
4183 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4184 !strcmp (insn
->name
, insn
[1].name
))
4186 as_bad ("16 bit expression not in range 0..65535");
4191 if (imm_expr
.X_add_number
< -0x8000 ||
4192 imm_expr
.X_add_number
>= 0x8000)
4194 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4195 !strcmp (insn
->name
, insn
[1].name
))
4197 as_bad ("16 bit expression not in range -32768..32767");
4203 case 'o': /* 16 bit offset */
4204 c
= my_getSmallExpression (&offset_expr
, s
);
4206 * If this value won't fit into a 16 bit offset, then
4207 * go find a macro that will generate the 32 bit offset
4210 if (offset_expr
.X_op
!= O_constant
4211 || offset_expr
.X_add_number
>= 0x8000
4212 || offset_expr
.X_add_number
< -0x8000)
4215 offset_reloc
= BFD_RELOC_LO16
;
4216 if (c
== 'h' || c
== 'H')
4218 assert (offset_expr
.X_op
== O_constant
);
4219 offset_expr
.X_add_number
=
4220 (offset_expr
.X_add_number
>> 16) & 0xffff;
4225 case 'p': /* pc relative offset */
4226 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4227 my_getExpression (&offset_expr
, s
);
4231 case 'u': /* upper 16 bits */
4232 c
= my_getSmallExpression (&imm_expr
, s
);
4233 if (imm_expr
.X_op
!= O_constant
4234 || imm_expr
.X_add_number
< 0
4235 || imm_expr
.X_add_number
>= 0x10000)
4236 as_bad ("lui expression not in range 0..65535");
4237 imm_reloc
= BFD_RELOC_LO16
;
4242 if (imm_expr
.X_op
== O_constant
)
4243 imm_expr
.X_add_number
=
4244 (imm_expr
.X_add_number
>> 16) & 0xffff;
4246 imm_reloc
= BFD_RELOC_HI16_S
;
4248 imm_reloc
= BFD_RELOC_HI16
;
4254 case 'a': /* 26 bit address */
4255 my_getExpression (&offset_expr
, s
);
4257 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4261 fprintf (stderr
, "bad char = '%c'\n", *args
);
4266 /* Args don't match. */
4267 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4268 !strcmp (insn
->name
, insn
[1].name
))
4274 insn_error
= "ERROR: Illegal operands";
4283 my_getSmallExpression (ep
, str
)
4294 ((str
[1] == 'h' && str
[2] == 'i')
4295 || (str
[1] == 'H' && str
[2] == 'I')
4296 || (str
[1] == 'l' && str
[2] == 'o'))
4308 * A small expression may be followed by a base register.
4309 * Scan to the end of this operand, and then back over a possible
4310 * base register. Then scan the small expression up to that
4311 * point. (Based on code in sparc.c...)
4313 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4315 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4317 if (isdigit (sp
[-2]))
4319 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4321 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4327 else if (sp
- 5 >= str
4330 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4331 || (sp
[-3] == 's' && sp
[-2] == 'p')
4332 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4333 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4339 /* no expression means zero offset */
4342 /* %xx(reg) is an error */
4343 ep
->X_op
= O_absent
;
4348 ep
->X_op
= O_constant
;
4351 ep
->X_add_symbol
= NULL
;
4352 ep
->X_op_symbol
= NULL
;
4353 ep
->X_add_number
= 0;
4358 my_getExpression (ep
, str
);
4365 my_getExpression (ep
, str
);
4366 return c
; /* => %hi or %lo encountered */
4370 my_getExpression (ep
, str
)
4376 save_in
= input_line_pointer
;
4377 input_line_pointer
= str
;
4379 expr_end
= input_line_pointer
;
4380 input_line_pointer
= save_in
;
4383 /* Turn a string in input_line_pointer into a floating point constant
4384 of type type, and store the appropriate bytes in *litP. The number
4385 of LITTLENUMS emitted is stored in *sizeP . An error message is
4386 returned, or NULL on OK. */
4389 md_atof (type
, litP
, sizeP
)
4395 LITTLENUM_TYPE words
[4];
4411 return "bad call to md_atof";
4414 t
= atof_ieee (input_line_pointer
, type
, words
);
4416 input_line_pointer
= t
;
4420 if (byte_order
== LITTLE_ENDIAN
)
4422 for (i
= prec
- 1; i
>= 0; i
--)
4424 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4430 for (i
= 0; i
< prec
; i
++)
4432 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4441 md_number_to_chars (buf
, val
, n
)
4489 md_number_to_chars (buf
, hi
, 4);
4514 md_parse_option (argP
, cntP
, vecP
)
4519 /* Accept -nocpp but ignore it. */
4520 if (strcmp (*argP
, "nocpp") == 0)
4526 if (strcmp (*argP
, "EL") == 0
4527 || strcmp (*argP
, "EB") == 0)
4529 /* FIXME: This breaks -L -EL. */
4537 if ((*argP
)[1] == '0')
4546 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4551 if (strncmp (*argP
, "mips", 4) == 0)
4553 mips_isa
= atol (*argP
+ 4);
4556 else if (mips_isa
< 1 || mips_isa
> 3)
4558 as_bad ("-mips%d not supported", mips_isa
);
4565 if (strncmp (*argP
, "mcpu=", 5) == 0)
4569 /* Identify the processor type */
4571 if (strcmp (p
, "default") == 0
4572 || strcmp (p
, "DEFAULT") == 0)
4576 if (*p
== 'r' || *p
== 'R')
4583 if (strcmp (p
, "2000") == 0
4584 || strcmp (p
, "2k") == 0
4585 || strcmp (p
, "2K") == 0)
4590 if (strcmp (p
, "3000") == 0
4591 || strcmp (p
, "3k") == 0
4592 || strcmp (p
, "3K") == 0)
4597 if (strcmp (p
, "4000") == 0
4598 || strcmp (p
, "4k") == 0
4599 || strcmp (p
, "4K") == 0)
4604 if (strcmp (p
, "6000") == 0
4605 || strcmp (p
, "6k") == 0
4606 || strcmp (p
, "6K") == 0)
4613 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4626 if ((*argP
)[1] != '\0')
4627 g_switch_value
= atoi (*argP
+ 1);
4630 **vecP
= (char *) NULL
;
4633 g_switch_value
= atoi (**vecP
);
4636 as_warn ("Number expected after -G");
4642 return 1; /* pretend you parsed the character */
4646 md_pcrel_from (fixP
)
4649 /* return the address of the delay slot */
4650 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4653 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4654 reloc for a cons. We could use the definition there, except that
4655 we want to handle 64 bit relocs specially. */
4658 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
4661 unsigned int nbytes
;
4664 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
4666 FIXME: There is no way to select anything but 32 bit mode right
4670 if (byte_order
== BIG_ENDIAN
)
4675 if (nbytes
!= 2 && nbytes
!= 4)
4676 as_bad ("Unsupported reloc size %d", nbytes
);
4678 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
4679 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
4683 md_apply_fix (fixP
, valueP
)
4690 assert (fixP
->fx_size
== 4);
4693 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
4695 switch (fixP
->fx_r_type
)
4698 case BFD_RELOC_MIPS_JMP
:
4699 case BFD_RELOC_HI16
:
4700 case BFD_RELOC_HI16_S
:
4701 case BFD_RELOC_LO16
:
4702 case BFD_RELOC_MIPS_GPREL
:
4703 case BFD_RELOC_MIPS_LITERAL
:
4704 case BFD_RELOC_MIPS_CALL16
:
4705 case BFD_RELOC_MIPS_GOT16
:
4706 case BFD_RELOC_MIPS_GPREL32
:
4707 /* Nothing needed to do. The value comes from the reloc entry */
4710 case BFD_RELOC_16_PCREL_S2
:
4712 * We need to save the bits in the instruction since fixup_segment()
4713 * might be deleting the relocation entry (i.e., a branch within
4714 * the current segment).
4717 as_warn ("Branch to odd address (%lx)", value
);
4719 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
4720 as_bad ("Relocation overflow");
4722 /* update old instruction data */
4723 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
4727 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
4731 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
4738 insn
|= value
& 0xFFFF;
4739 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
4753 const struct mips_opcode
*p
;
4754 int treg
, sreg
, dreg
, shamt
;
4759 for (i
= 0; i
< NUMOPCODES
; ++i
)
4761 p
= &mips_opcodes
[i
];
4762 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
4764 printf ("%08lx %s\t", oc
, p
->name
);
4765 treg
= (oc
>> 16) & 0x1f;
4766 sreg
= (oc
>> 21) & 0x1f;
4767 dreg
= (oc
>> 11) & 0x1f;
4768 shamt
= (oc
>> 6) & 0x1f;
4770 for (args
= p
->args
;; ++args
)
4781 printf ("%c", *args
);
4785 assert (treg
== sreg
);
4786 printf ("$%d,$%d", treg
, sreg
);
4791 printf ("$%d", dreg
);
4796 printf ("$%d", treg
);
4800 printf ("0x%x", treg
);
4805 printf ("$%d", sreg
);
4809 printf ("0x%08lx", oc
& 0x1ffffff);
4821 printf ("$%d", shamt
);
4832 printf ("%08lx UNDEFINED\n", oc
);
4843 name
= input_line_pointer
;
4844 c
= get_symbol_end ();
4845 p
= (symbolS
*) symbol_find_or_make (name
);
4846 *input_line_pointer
= c
;
4850 /* Align the current frag to a given power of two. The MIPS assembler
4851 also automatically adjusts any preceding label. */
4854 mips_align (to
, fill
)
4858 mips_emit_delays ();
4859 frag_align (to
, fill
);
4860 record_alignment (now_seg
, to
);
4861 if (insn_label
!= NULL
)
4863 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4864 insn_label
->sy_frag
= frag_now
;
4865 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4870 /* Align to a given power of two. .align 0 turns off the automatic
4871 alignment used by the data creating pseudo-ops. */
4878 register long temp_fill
;
4879 long max_alignment
= 15;
4883 o Note that the assembler pulls down any immediately preceeding label
4884 to the aligned address.
4885 o It's not documented but auto alignment is reinstated by
4886 a .align pseudo instruction.
4887 o Note also that after auto alignment is turned off the mips assembler
4888 issues an error on attempt to assemble an improperly aligned data item.
4893 temp
= get_absolute_expression ();
4894 if (temp
> max_alignment
)
4895 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4898 as_warn ("Alignment negative: 0 assumed.");
4901 if (*input_line_pointer
== ',')
4903 input_line_pointer
++;
4904 temp_fill
= get_absolute_expression ();
4911 mips_align (temp
, (int) temp_fill
);
4918 demand_empty_rest_of_line ();
4921 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4922 that there was a previous instruction. */
4925 s_stringer (append_zero
)
4928 mips_emit_delays ();
4930 stringer (append_zero
);
4941 mips_emit_delays ();
4951 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4952 demand_empty_rest_of_line ();
4957 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4958 demand_empty_rest_of_line ();
4960 #else /* ! defined (OBJ_ECOFF) */
4962 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
4963 bfd_set_section_flags (stdoutput
, seg
,
4969 bfd_set_section_alignment (stdoutput
, seg
, 4);
4970 demand_empty_rest_of_line ();
4972 #else /* ! defined (OBJ_ELF) */
4975 #endif /* ! defined (OBJ_ELF) */
4976 #endif /* ! defined (OBJ_ECOFF) */
4980 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4982 bfd_set_section_flags (stdoutput
, seg
,
4983 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
4984 bfd_set_section_alignment (stdoutput
, seg
, 4);
4986 demand_empty_rest_of_line ();
4988 #else /* ! defined (GPOPT) */
4989 as_bad ("Global pointers not supported; recompile -G 0");
4990 demand_empty_rest_of_line ();
4992 #endif /* ! defined (GPOPT) */
5002 mips_emit_delays ();
5003 if (log_size
> 0 && auto_align
)
5004 mips_align (log_size
, 0);
5006 cons (1 << log_size
);
5013 as_fatal ("Encountered `.err', aborting assembly");
5023 symbolP
= get_symbol ();
5024 if (*input_line_pointer
== ',')
5025 input_line_pointer
++;
5026 size
= get_absolute_expression ();
5027 S_SET_VALUE (symbolP
, size
);
5028 S_SET_EXTERNAL (symbolP
);
5030 #ifdef ECOFF_DEBUGGING
5031 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
5032 so we use an additional ECOFF specific field. */
5033 symbolP
->ecoff_undefined
= 1;
5041 mips_emit_delays ();
5061 opt
= input_line_pointer
;
5062 c
= get_symbol_end ();
5066 /* FIXME: What does this mean? */
5068 else if (strncmp (opt
, "pic", 3) == 0)
5070 mips_pic
= atoi (opt
+ 3);
5071 /* Supposedly no other values are used. */
5072 assert (mips_pic
== 0 || mips_pic
== 2);
5075 as_warn ("Unrecognized option \"%s\"", opt
);
5077 *input_line_pointer
= c
;
5078 demand_empty_rest_of_line ();
5085 char *name
= input_line_pointer
, ch
;
5087 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5088 input_line_pointer
++;
5089 ch
= *input_line_pointer
;
5090 *input_line_pointer
= '\0';
5092 if (strcmp (name
, "reorder") == 0)
5096 prev_insn_unreordered
= 1;
5097 prev_prev_insn_unreordered
= 1;
5101 else if (strcmp (name
, "noreorder") == 0)
5103 mips_emit_delays ();
5105 mips_any_noreorder
= 1;
5107 else if (strcmp (name
, "at") == 0)
5111 else if (strcmp (name
, "noat") == 0)
5115 else if (strcmp (name
, "macro") == 0)
5117 mips_warn_about_macros
= 0;
5119 else if (strcmp (name
, "nomacro") == 0)
5121 if (mips_noreorder
== 0)
5122 as_bad ("`noreorder' must be set before `nomacro'");
5123 mips_warn_about_macros
= 1;
5125 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5129 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5133 else if (strcmp (name
, "bopt") == 0)
5137 else if (strcmp (name
, "nobopt") == 0)
5143 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5145 *input_line_pointer
= ch
;
5146 demand_empty_rest_of_line ();
5149 /* The same as the usual .space directive, except that we have to
5150 forget about any previous instruction. */
5153 s_mips_space (param
)
5156 mips_emit_delays ();
5161 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5162 .option pic2. It means to generate SVR4 PIC calls. */
5169 demand_empty_rest_of_line ();
5172 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5173 PIC code. It sets the $gp register for the function based on the
5174 function address, which is in the register named in the argument.
5175 This uses a relocation against _gp_disp, which is handled specially
5176 by the linker. The result is:
5177 lui $gp,%hi(_gp_disp)
5178 addiu $gp,$gp,%lo(_gp_disp)
5179 addu $gp,$gp,.cpload argument
5180 The .cpload argument is normally $25 == $t9. */
5189 /* If we are not generating PIC code, .cpload is ignored. */
5196 /* .cpload should be a in .set noreorder section. */
5197 if (mips_noreorder
== 0)
5198 as_warn (".cpload not in noreorder section");
5201 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5202 ex
.X_op_symbol
= NULL
;
5203 ex
.X_add_number
= 0;
5205 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5206 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5207 (int) BFD_RELOC_LO16
);
5209 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5210 GP
, GP
, tc_get_register (0));
5212 demand_empty_rest_of_line ();
5215 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5216 offset from $sp. The offset is remembered, and after making a PIC
5217 call $gp is restored from that location. */
5220 s_cprestore (ignore
)
5226 /* If we are not generating PIC code, .cprestore is ignored. */
5233 mips_cprestore_offset
= get_absolute_expression ();
5235 ex
.X_op
= O_constant
;
5236 ex
.X_add_symbol
= NULL
;
5237 ex
.X_op_symbol
= NULL
;
5238 ex
.X_add_number
= mips_cprestore_offset
;
5240 macro_build ((char *) NULL
, &icnt
, &ex
,
5241 mips_isa
< 3 ? "sw" : "sd",
5242 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5244 demand_empty_rest_of_line ();
5247 /* Handle the .gpword pseudo-op. This is used when generating PIC
5248 code. It generates a 32 bit GP relative reloc. */
5257 /* When not generating PIC code, this is treated as .word. */
5264 mips_emit_delays ();
5271 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5273 as_bad ("Unsupported use of .gpword");
5274 ignore_rest_of_line ();
5278 md_number_to_chars (p
, (valueT
) 0, 4);
5279 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5280 BFD_RELOC_MIPS_GPREL32
);
5282 demand_empty_rest_of_line ();
5285 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5286 tables in SVR4 PIC code. */
5295 /* This is ignored when not generating SVR4 PIC code. */
5302 /* Add $gp to the register named as an argument. */
5303 reg
= tc_get_register (0);
5304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5305 mips_isa
< 3 ? "addu" : "daddu",
5306 "d,v,t", reg
, reg
, GP
);
5308 demand_empty_rest_of_line ();
5311 /* Parse a register string into a number. Called from the ECOFF code
5312 to parse .frame. The argument is non-zero if this is the frame
5313 register, so that we can record it in mips_frame_reg. */
5316 tc_get_register (frame
)
5322 if (*input_line_pointer
++ != '$')
5324 as_warn ("expected `$'");
5327 else if (isdigit ((unsigned char) *input_line_pointer
))
5329 reg
= get_absolute_expression ();
5330 if (reg
< 0 || reg
>= 32)
5332 as_warn ("Bad register number");
5338 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5340 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5342 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5344 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5348 as_warn ("Unrecognized register name");
5351 input_line_pointer
+= 2;
5354 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5359 md_section_align (seg
, addr
)
5363 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5365 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5368 /* Estimate the size of a frag before relaxing. We are not really
5369 relaxing here, and the final size is encoded in the subtype
5374 md_estimate_size_before_relax (fragp
, segtype
)
5383 const char *symname
;
5385 /* Find out whether this symbol can be referenced off the GP
5386 register. It can be if it is smaller than the -G size or if
5387 it is in the .sdata or .sbss section. Certain symbols can
5388 not be referenced off the GP, although it appears as though
5390 symname
= S_GET_NAME (fragp
->fr_symbol
);
5391 if (symname
!= (const char *) NULL
5392 && (strcmp (symname
, "eprol") == 0
5393 || strcmp (symname
, "etext") == 0
5394 || strcmp (symname
, "_gp") == 0
5395 || strcmp (symname
, "edata") == 0
5396 || strcmp (symname
, "_fbss") == 0
5397 || strcmp (symname
, "_fdata") == 0
5398 || strcmp (symname
, "_ftext") == 0
5399 || strcmp (symname
, "end") == 0
5400 || strcmp (symname
, "_gp_disp") == 0))
5402 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5403 && S_GET_VALUE (fragp
->fr_symbol
) != 0
5404 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)
5408 const char *segname
;
5410 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5411 assert (strcmp (segname
, ".lit8") != 0
5412 && strcmp (segname
, ".lit4") != 0);
5413 change
= (strcmp (segname
, ".sdata") != 0
5414 && strcmp (segname
, ".sbss") != 0);
5416 #else /* ! defined (GPOPT) */
5417 /* We are not optimizing for the GP register. */
5419 #endif /* ! defined (GPOPT) */
5423 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5425 /* This must duplicate the test in adjust_reloc_syms. */
5426 change
= (symsec
!= &bfd_und_section
5427 && symsec
!= &bfd_abs_section
5428 && ! bfd_is_com_section (symsec
));
5433 /* Record the offset to the first reloc in the fr_opcode field.
5434 This lets md_convert_frag and tc_gen_reloc know that the code
5435 must be expanded. */
5436 fragp
->fr_opcode
= (fragp
->fr_literal
5438 - RELAX_OLD (fragp
->fr_subtype
)
5439 + RELAX_RELOC1 (fragp
->fr_subtype
));
5440 /* FIXME: This really needs as_warn_where. */
5441 if (RELAX_WARN (fragp
->fr_subtype
))
5442 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
5448 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
5451 /* Translate internal representation of relocation info to BFD target
5455 tc_gen_reloc (section
, fixp
)
5459 static arelent
*retval
[4];
5462 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
5465 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5466 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5467 if (fixp
->fx_pcrel
== 0)
5468 reloc
->addend
= fixp
->fx_addnumber
;
5473 reloc
->addend
= -reloc
->address
;
5476 /* If this is a variant frag, we may need to adjust the existing
5477 reloc and generate a new one. */
5478 if (fixp
->fx_frag
->fr_opcode
!= NULL
5479 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5480 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
5481 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
5485 /* If this is not the last reloc in this frag, then we have two
5486 GPREL relocs, both of which are being replaced. Let the
5487 second one handle all of them. */
5488 if (fixp
->fx_next
!= NULL
5489 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
5491 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5492 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5497 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
5498 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5499 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
5501 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5502 reloc2
->address
= (reloc
->address
5503 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
5504 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
5505 reloc2
->addend
= fixp
->fx_addnumber
;
5506 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
5507 assert (reloc2
->howto
!= NULL
);
5509 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
5513 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
5516 reloc3
->address
+= 4;
5521 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5522 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
5526 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
5528 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
5529 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
5534 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5536 if (reloc
->howto
== NULL
)
5538 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5539 "Can not represent relocation in this object file format");
5546 /* Convert a machine dependent frag. */
5549 md_convert_frag (abfd
, asec
, fragp
)
5557 if (fragp
->fr_opcode
== NULL
)
5560 old
= RELAX_OLD (fragp
->fr_subtype
);
5561 new = RELAX_NEW (fragp
->fr_subtype
);
5562 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
5565 memcpy (fixptr
- old
, fixptr
, new);
5567 fragp
->fr_fix
+= new - old
;
5570 /* This function is called whenever a label is defined. It is used
5571 when handling branch delays; if a branch has a label, we assume we
5575 mips_define_label (sym
)
5583 /* Some special processing for a MIPS ELF file. */
5586 mips_elf_final_processing ()
5590 /* Write out the .reginfo section. */
5591 s
.ri_gprmask
= mips_gprmask
;
5592 s
.ri_cprmask
[0] = mips_cprmask
[0];
5593 s
.ri_cprmask
[1] = mips_cprmask
[1];
5594 s
.ri_cprmask
[2] = mips_cprmask
[2];
5595 s
.ri_cprmask
[3] = mips_cprmask
[3];
5596 /* The gp_value field is set by the MIPS ELF backend. */
5598 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
5599 ((Elf32_External_RegInfo
*)
5600 mips_regmask_frag
));
5602 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
5603 sort of BFD interface for this. */
5604 if (mips_any_noreorder
)
5605 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
5607 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
5610 #endif /* OBJ_ELF */
5612 #ifndef ECOFF_DEBUGGING
5614 /* These functions should really be defined by the object file format,
5615 since they are related to debugging information. However, this
5616 code has to work for the a.out format, which does not define them,
5617 so we provide simple versions here. These don't actually generate
5618 any debugging information, but they do simple checking and someday
5619 somebody may make them useful. */
5623 struct loc
*loc_next
;
5624 unsigned long loc_fileno
;
5625 unsigned long loc_lineno
;
5626 unsigned long loc_offset
;
5627 unsigned short loc_delta
;
5628 unsigned short loc_count
;
5637 struct proc
*proc_next
;
5638 struct symbol
*proc_isym
;
5639 struct symbol
*proc_end
;
5640 unsigned long proc_reg_mask
;
5641 unsigned long proc_reg_offset
;
5642 unsigned long proc_fpreg_mask
;
5643 unsigned long proc_fpreg_offset
;
5644 unsigned long proc_frameoffset
;
5645 unsigned long proc_framereg
;
5646 unsigned long proc_pcreg
;
5648 struct file
*proc_file
;
5655 struct file
*file_next
;
5656 unsigned long file_fileno
;
5657 struct symbol
*file_symbol
;
5658 struct symbol
*file_end
;
5659 struct proc
*file_proc
;
5664 static struct obstack proc_frags
;
5665 static procS
*proc_lastP
;
5666 static procS
*proc_rootP
;
5667 static int numprocs
;
5672 obstack_begin (&proc_frags
, 0x2000);
5678 /* check for premature end, nesting errors, etc */
5679 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5680 as_warn ("missing `.end' at end of assembly");
5683 extern char hex_value
[];
5691 if (*input_line_pointer
== '-')
5693 ++input_line_pointer
;
5696 if (!isdigit (*input_line_pointer
))
5697 as_bad ("Expected simple number.");
5698 if (input_line_pointer
[0] == '0')
5700 if (input_line_pointer
[1] == 'x')
5702 input_line_pointer
+= 2;
5703 while (isxdigit (*input_line_pointer
))
5706 val
|= hex_value
[(int) *input_line_pointer
++];
5708 return negative
? -val
: val
;
5712 ++input_line_pointer
;
5713 while (isdigit (*input_line_pointer
))
5716 val
|= *input_line_pointer
++ - '0';
5718 return negative
? -val
: val
;
5721 if (!isdigit (*input_line_pointer
))
5723 printf (" *input_line_pointer == '%c' 0x%02x\n",
5724 *input_line_pointer
, *input_line_pointer
);
5725 as_warn ("Invalid number");
5728 while (isdigit (*input_line_pointer
))
5731 val
+= *input_line_pointer
++ - '0';
5733 return negative
? -val
: val
;
5736 /* The .file directive; just like the usual .file directive, but there
5737 is an initial number which is the ECOFF file index. */
5745 line
= get_number ();
5750 /* The .end directive. */
5758 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5761 demand_empty_rest_of_line ();
5765 if (now_seg
!= text_section
)
5766 as_warn (".end not in text section");
5769 as_warn (".end and no .ent seen yet.");
5775 assert (S_GET_NAME (p
));
5776 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
5777 as_warn (".end symbol does not match .ent symbol.");
5780 proc_lastP
->proc_end
= (symbolS
*) 1;
5783 /* The .aent and .ent directives. */
5793 symbolP
= get_symbol ();
5794 if (*input_line_pointer
== ',')
5795 input_line_pointer
++;
5797 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
5798 number
= get_number ();
5799 if (now_seg
!= text_section
)
5800 as_warn (".ent or .aent not in text section.");
5802 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5803 as_warn ("missing `.end'");
5807 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
5808 procP
->proc_isym
= symbolP
;
5809 procP
->proc_reg_mask
= 0;
5810 procP
->proc_reg_offset
= 0;
5811 procP
->proc_fpreg_mask
= 0;
5812 procP
->proc_fpreg_offset
= 0;
5813 procP
->proc_frameoffset
= 0;
5814 procP
->proc_framereg
= 0;
5815 procP
->proc_pcreg
= 0;
5816 procP
->proc_end
= NULL
;
5817 procP
->proc_next
= NULL
;
5819 proc_lastP
->proc_next
= procP
;
5825 demand_empty_rest_of_line ();
5828 /* The .frame directive. */
5841 frame_reg
= tc_get_register (1);
5842 if (*input_line_pointer
== ',')
5843 input_line_pointer
++;
5844 frame_off
= get_absolute_expression ();
5845 if (*input_line_pointer
== ',')
5846 input_line_pointer
++;
5847 pcreg
= tc_get_register (0);
5850 assert (proc_rootP
);
5851 proc_rootP
->proc_framereg
= frame_reg
;
5852 proc_rootP
->proc_frameoffset
= frame_off
;
5853 proc_rootP
->proc_pcreg
= pcreg
;
5854 /* bob macho .frame */
5856 /* We don't have to write out a frame stab for unoptimized code. */
5857 if (!(frame_reg
== FP
&& frame_off
== 0))
5860 as_warn ("No .ent for .frame to use.");
5861 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
5862 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
5863 S_SET_TYPE (symP
, N_RMASK
);
5864 S_SET_OTHER (symP
, 0);
5865 S_SET_DESC (symP
, 0);
5866 symP
->sy_forward
= proc_lastP
->proc_isym
;
5867 /* bob perhaps I should have used pseudo set */
5869 demand_empty_rest_of_line ();
5873 /* The .fmask and .mask directives. */
5880 char str
[100], *strP
;
5886 mask
= get_number ();
5887 if (*input_line_pointer
== ',')
5888 input_line_pointer
++;
5889 off
= get_absolute_expression ();
5891 /* bob only for coff */
5892 assert (proc_rootP
);
5893 if (reg_type
== 'F')
5895 proc_rootP
->proc_fpreg_mask
= mask
;
5896 proc_rootP
->proc_fpreg_offset
= off
;
5900 proc_rootP
->proc_reg_mask
= mask
;
5901 proc_rootP
->proc_reg_offset
= off
;
5904 /* bob macho .mask + .fmask */
5906 /* We don't have to write out a mask stab if no saved regs. */
5910 as_warn ("No .ent for .mask to use.");
5912 for (i
= 0; i
< 32; i
++)
5916 sprintf (strP
, "%c%d,", reg_type
, i
);
5917 strP
+= strlen (strP
);
5921 sprintf (strP
, ";%d,", off
);
5922 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
5923 S_SET_TYPE (symP
, N_RMASK
);
5924 S_SET_OTHER (symP
, 0);
5925 S_SET_DESC (symP
, 0);
5926 symP
->sy_forward
= proc_lastP
->proc_isym
;
5927 /* bob perhaps I should have used pseudo set */
5932 /* The .loc directive. */
5943 assert (now_seg
== text_section
);
5945 lineno
= get_number ();
5946 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
5948 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
5949 S_SET_TYPE (symbolP
, N_SLINE
);
5950 S_SET_OTHER (symbolP
, 0);
5951 S_SET_DESC (symbolP
, lineno
);
5952 symbolP
->sy_segment
= now_seg
;
5956 #endif /* ! defined (ECOFF_DEBUGGING) */