1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
36 #include "dw2gencfi.h"
39 #define DBG(x) printf x
45 /* Clean up namespace so we can include obj-elf.h too. */
46 static int mips_output_flavor (void);
47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
48 #undef OBJ_PROCESS_STAB
55 #undef obj_frob_file_after_relocs
56 #undef obj_frob_symbol
58 #undef obj_sec_sym_ok_for_reloc
59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
62 /* Fix any of them that we actually care about. */
64 #define OUTPUT_FLAVOR mips_output_flavor()
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
76 int mips_flag_mdebug
= -1;
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
82 int mips_flag_pdr
= FALSE
;
84 int mips_flag_pdr
= TRUE
;
89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
90 static char *mips_regmask_frag
;
96 #define PIC_CALL_REG 25
104 #define ILLEGAL_REG (32)
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
199 /* Whether we are assembling for the mips16 processor. 0 if we are
200 not, 1 if we are, and -1 if the value has not been initialized.
201 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
202 -nomips16 command line options, and the default CPU. */
204 /* Non-zero if we should not reorder instructions. Changed by `.set
205 reorder' and `.set noreorder'. */
207 /* Non-zero if we should not permit the $at ($1) register to be used
208 in instructions. Changed by `.set at' and `.set noat'. */
210 /* Non-zero if we should warn when a macro instruction expands into
211 more than one machine instruction. Changed by `.set nomacro' and
213 int warn_about_macros
;
214 /* Non-zero if we should not move instructions. Changed by `.set
215 move', `.set volatile', `.set nomove', and `.set novolatile'. */
217 /* Non-zero if we should not optimize branches by moving the target
218 of the branch into the delay slot. Actually, we don't perform
219 this optimization anyhow. Changed by `.set bopt' and `.set
222 /* Non-zero if we should not autoextend mips16 instructions.
223 Changed by `.set autoextend' and `.set noautoextend'. */
225 /* Restrict general purpose registers and floating point registers
226 to 32 bit. This is initially determined when -mgp32 or -mfp32
227 is passed but can changed if the assembler code uses .set mipsN. */
230 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
231 command line option, and the default CPU. */
233 /* True if ".set sym32" is in effect. */
237 /* True if -mgp32 was passed. */
238 static int file_mips_gp32
= -1;
240 /* True if -mfp32 was passed. */
241 static int file_mips_fp32
= -1;
243 /* This is the struct we use to hold the current set of options. Note
244 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
245 -1 to indicate that they have not been initialized. */
247 static struct mips_set_options mips_opts
=
249 ISA_UNKNOWN
, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
252 /* These variables are filled in with the masks of registers used.
253 The object format code reads them and puts them in the appropriate
255 unsigned long mips_gprmask
;
256 unsigned long mips_cprmask
[4];
258 /* MIPS ISA we are using for this output file. */
259 static int file_mips_isa
= ISA_UNKNOWN
;
261 /* True if -mips16 was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips16
;
265 /* True if -mips3d was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mips3d
;
269 /* True if -mdmx was passed or implied by arguments passed on the
270 command line (e.g., by -march). */
271 static int file_ase_mdmx
;
273 /* True if -msmartmips was passed or implied by arguments passed on the
274 command line (e.g., by -march). */
275 static int file_ase_smartmips
;
277 #define ISA_SUPPORT_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
278 || mips_opts.isa == ISA_MIPS32R2)
280 /* True if -mdsp was passed or implied by arguments passed on the
281 command line (e.g., by -march). */
282 static int file_ase_dsp
;
284 /* True if -mmt was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mt
;
288 /* The argument of the -march= flag. The architecture we are assembling. */
289 static int file_mips_arch
= CPU_UNKNOWN
;
290 static const char *mips_arch_string
;
292 /* The argument of the -mtune= flag. The architecture for which we
294 static int mips_tune
= CPU_UNKNOWN
;
295 static const char *mips_tune_string
;
297 /* True when generating 32-bit code for a 64-bit processor. */
298 static int mips_32bitmode
= 0;
300 /* True if the given ABI requires 32-bit registers. */
301 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
303 /* Likewise 64-bit registers. */
304 #define ABI_NEEDS_64BIT_REGS(ABI) \
306 || (ABI) == N64_ABI \
309 /* Return true if ISA supports 64 bit gp register instructions. */
310 #define ISA_HAS_64BIT_REGS(ISA) ( \
312 || (ISA) == ISA_MIPS4 \
313 || (ISA) == ISA_MIPS5 \
314 || (ISA) == ISA_MIPS64 \
315 || (ISA) == ISA_MIPS64R2 \
318 /* Return true if ISA supports 64-bit right rotate (dror et al.)
320 #define ISA_HAS_DROR(ISA) ( \
321 (ISA) == ISA_MIPS64R2 \
324 /* Return true if ISA supports 32-bit right rotate (ror et al.)
326 #define ISA_HAS_ROR(ISA) ( \
327 (ISA) == ISA_MIPS32R2 \
328 || (ISA) == ISA_MIPS64R2 \
329 || mips_opts.ase_smartmips \
332 #define HAVE_32BIT_GPRS \
333 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
335 #define HAVE_32BIT_FPRS \
336 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
338 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
339 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
341 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
343 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
345 /* True if relocations are stored in-place. */
346 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
348 /* The ABI-derived address size. */
349 #define HAVE_64BIT_ADDRESSES \
350 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
351 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
353 /* The size of symbolic constants (i.e., expressions of the form
354 "SYMBOL" or "SYMBOL + OFFSET"). */
355 #define HAVE_32BIT_SYMBOLS \
356 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
357 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
359 /* Addresses are loaded in different ways, depending on the address size
360 in use. The n32 ABI Documentation also mandates the use of additions
361 with overflow checking, but existing implementations don't follow it. */
362 #define ADDRESS_ADD_INSN \
363 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
365 #define ADDRESS_ADDI_INSN \
366 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
368 #define ADDRESS_LOAD_INSN \
369 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
371 #define ADDRESS_STORE_INSN \
372 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
374 /* Return true if the given CPU supports the MIPS16 ASE. */
375 #define CPU_HAS_MIPS16(cpu) \
376 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
377 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
379 /* Return true if the given CPU supports the MIPS3D ASE. */
380 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
383 /* Return true if the given CPU supports the MDMX ASE. */
384 #define CPU_HAS_MDMX(cpu) (FALSE \
387 /* Return true if the given CPU supports the DSP ASE. */
388 #define CPU_HAS_DSP(cpu) (FALSE \
391 /* Return true if the given CPU supports the MT ASE. */
392 #define CPU_HAS_MT(cpu) (FALSE \
395 /* True if CPU has a dror instruction. */
396 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
398 /* True if CPU has a ror instruction. */
399 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
401 /* True if mflo and mfhi can be immediately followed by instructions
402 which write to the HI and LO registers.
404 According to MIPS specifications, MIPS ISAs I, II, and III need
405 (at least) two instructions between the reads of HI/LO and
406 instructions which write them, and later ISAs do not. Contradicting
407 the MIPS specifications, some MIPS IV processor user manuals (e.g.
408 the UM for the NEC Vr5000) document needing the instructions between
409 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
410 MIPS64 and later ISAs to have the interlocks, plus any specific
411 earlier-ISA CPUs for which CPU documentation declares that the
412 instructions are really interlocked. */
413 #define hilo_interlocks \
414 (mips_opts.isa == ISA_MIPS32 \
415 || mips_opts.isa == ISA_MIPS32R2 \
416 || mips_opts.isa == ISA_MIPS64 \
417 || mips_opts.isa == ISA_MIPS64R2 \
418 || mips_opts.arch == CPU_R4010 \
419 || mips_opts.arch == CPU_R10000 \
420 || mips_opts.arch == CPU_R12000 \
421 || mips_opts.arch == CPU_RM7000 \
422 || mips_opts.arch == CPU_VR5500 \
425 /* Whether the processor uses hardware interlocks to protect reads
426 from the GPRs after they are loaded from memory, and thus does not
427 require nops to be inserted. This applies to instructions marked
428 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
430 #define gpr_interlocks \
431 (mips_opts.isa != ISA_MIPS1 \
432 || mips_opts.arch == CPU_R3900)
434 /* Whether the processor uses hardware interlocks to avoid delays
435 required by coprocessor instructions, and thus does not require
436 nops to be inserted. This applies to instructions marked
437 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
438 between instructions marked INSN_WRITE_COND_CODE and ones marked
439 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
440 levels I, II, and III. */
441 /* Itbl support may require additional care here. */
442 #define cop_interlocks \
443 ((mips_opts.isa != ISA_MIPS1 \
444 && mips_opts.isa != ISA_MIPS2 \
445 && mips_opts.isa != ISA_MIPS3) \
446 || mips_opts.arch == CPU_R4300 \
449 /* Whether the processor uses hardware interlocks to protect reads
450 from coprocessor registers after they are loaded from memory, and
451 thus does not require nops to be inserted. This applies to
452 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
453 requires at MIPS ISA level I. */
454 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
456 /* Is this a mfhi or mflo instruction? */
457 #define MF_HILO_INSN(PINFO) \
458 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
460 /* MIPS PIC level. */
462 enum mips_pic_level mips_pic
;
464 /* 1 if we should generate 32 bit offsets from the $gp register in
465 SVR4_PIC mode. Currently has no meaning in other modes. */
466 static int mips_big_got
= 0;
468 /* 1 if trap instructions should used for overflow rather than break
470 static int mips_trap
= 0;
472 /* 1 if double width floating point constants should not be constructed
473 by assembling two single width halves into two single width floating
474 point registers which just happen to alias the double width destination
475 register. On some architectures this aliasing can be disabled by a bit
476 in the status register, and the setting of this bit cannot be determined
477 automatically at assemble time. */
478 static int mips_disable_float_construction
;
480 /* Non-zero if any .set noreorder directives were used. */
482 static int mips_any_noreorder
;
484 /* Non-zero if nops should be inserted when the register referenced in
485 an mfhi/mflo instruction is read in the next two instructions. */
486 static int mips_7000_hilo_fix
;
488 /* The size of the small data section. */
489 static unsigned int g_switch_value
= 8;
490 /* Whether the -G option was used. */
491 static int g_switch_seen
= 0;
496 /* If we can determine in advance that GP optimization won't be
497 possible, we can skip the relaxation stuff that tries to produce
498 GP-relative references. This makes delay slot optimization work
501 This function can only provide a guess, but it seems to work for
502 gcc output. It needs to guess right for gcc, otherwise gcc
503 will put what it thinks is a GP-relative instruction in a branch
506 I don't know if a fix is needed for the SVR4_PIC mode. I've only
507 fixed it for the non-PIC mode. KR 95/04/07 */
508 static int nopic_need_relax (symbolS
*, int);
510 /* handle of the OPCODE hash table */
511 static struct hash_control
*op_hash
= NULL
;
513 /* The opcode hash table we use for the mips16. */
514 static struct hash_control
*mips16_op_hash
= NULL
;
516 /* This array holds the chars that always start a comment. If the
517 pre-processor is disabled, these aren't very useful */
518 const char comment_chars
[] = "#";
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output */
523 /* Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output. */
526 /* Also note that C style comments are always supported. */
527 const char line_comment_chars
[] = "#";
529 /* This array holds machine specific line separator characters. */
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point nums */
533 const char EXP_CHARS
[] = "eE";
535 /* Chars that mean this number is a floating point constant */
538 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
540 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
541 changed in read.c . Ideally it shouldn't have to know about it at all,
542 but nothing is ideal around here.
545 static char *insn_error
;
547 static int auto_align
= 1;
549 /* When outputting SVR4 PIC code, the assembler needs to know the
550 offset in the stack frame from which to restore the $gp register.
551 This is set by the .cprestore pseudo-op, and saved in this
553 static offsetT mips_cprestore_offset
= -1;
555 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
556 more optimizations, it can use a register value instead of a memory-saved
557 offset and even an other register than $gp as global pointer. */
558 static offsetT mips_cpreturn_offset
= -1;
559 static int mips_cpreturn_register
= -1;
560 static int mips_gp_register
= GP
;
561 static int mips_gprel_offset
= 0;
563 /* Whether mips_cprestore_offset has been set in the current function
564 (or whether it has already been warned about, if not). */
565 static int mips_cprestore_valid
= 0;
567 /* This is the register which holds the stack frame, as set by the
568 .frame pseudo-op. This is needed to implement .cprestore. */
569 static int mips_frame_reg
= SP
;
571 /* Whether mips_frame_reg has been set in the current function
572 (or whether it has already been warned about, if not). */
573 static int mips_frame_reg_valid
= 0;
575 /* To output NOP instructions correctly, we need to keep information
576 about the previous two instructions. */
578 /* Whether we are optimizing. The default value of 2 means to remove
579 unneeded NOPs and swap branch instructions when possible. A value
580 of 1 means to not swap branches. A value of 0 means to always
582 static int mips_optimize
= 2;
584 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
585 equivalent to seeing no -g option at all. */
586 static int mips_debug
= 0;
588 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
589 #define MAX_VR4130_NOPS 4
591 /* The maximum number of NOPs needed to fill delay slots. */
592 #define MAX_DELAY_NOPS 2
594 /* The maximum number of NOPs needed for any purpose. */
597 /* A list of previous instructions, with index 0 being the most recent.
598 We need to look back MAX_NOPS instructions when filling delay slots
599 or working around processor errata. We need to look back one
600 instruction further if we're thinking about using history[0] to
601 fill a branch delay slot. */
602 static struct mips_cl_insn history
[1 + MAX_NOPS
];
604 /* Nop instructions used by emit_nop. */
605 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
607 /* The appropriate nop for the current mode. */
608 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
610 /* If this is set, it points to a frag holding nop instructions which
611 were inserted before the start of a noreorder section. If those
612 nops turn out to be unnecessary, the size of the frag can be
614 static fragS
*prev_nop_frag
;
616 /* The number of nop instructions we created in prev_nop_frag. */
617 static int prev_nop_frag_holds
;
619 /* The number of nop instructions that we know we need in
621 static int prev_nop_frag_required
;
623 /* The number of instructions we've seen since prev_nop_frag. */
624 static int prev_nop_frag_since
;
626 /* For ECOFF and ELF, relocations against symbols are done in two
627 parts, with a HI relocation and a LO relocation. Each relocation
628 has only 16 bits of space to store an addend. This means that in
629 order for the linker to handle carries correctly, it must be able
630 to locate both the HI and the LO relocation. This means that the
631 relocations must appear in order in the relocation table.
633 In order to implement this, we keep track of each unmatched HI
634 relocation. We then sort them so that they immediately precede the
635 corresponding LO relocation. */
640 struct mips_hi_fixup
*next
;
643 /* The section this fixup is in. */
647 /* The list of unmatched HI relocs. */
649 static struct mips_hi_fixup
*mips_hi_fixup_list
;
651 /* The frag containing the last explicit relocation operator.
652 Null if explicit relocations have not been used. */
654 static fragS
*prev_reloc_op_frag
;
656 /* Map normal MIPS register numbers to mips16 register numbers. */
658 #define X ILLEGAL_REG
659 static const int mips32_to_16_reg_map
[] =
661 X
, X
, 2, 3, 4, 5, 6, 7,
662 X
, X
, X
, X
, X
, X
, X
, X
,
663 0, 1, X
, X
, X
, X
, X
, X
,
664 X
, X
, X
, X
, X
, X
, X
, X
668 /* Map mips16 register numbers to normal MIPS register numbers. */
670 static const unsigned int mips16_to_32_reg_map
[] =
672 16, 17, 2, 3, 4, 5, 6, 7
675 /* Classifies the kind of instructions we're interested in when
676 implementing -mfix-vr4120. */
677 enum fix_vr4120_class
{
684 NUM_FIX_VR4120_CLASSES
687 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
688 there must be at least one other instruction between an instruction
689 of type X and an instruction of type Y. */
690 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
692 /* True if -mfix-vr4120 is in force. */
693 static int mips_fix_vr4120
;
695 /* ...likewise -mfix-vr4130. */
696 static int mips_fix_vr4130
;
698 /* We don't relax branches by default, since this causes us to expand
699 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
700 fail to compute the offset before expanding the macro to the most
701 efficient expansion. */
703 static int mips_relax_branch
;
705 /* The expansion of many macros depends on the type of symbol that
706 they refer to. For example, when generating position-dependent code,
707 a macro that refers to a symbol may have two different expansions,
708 one which uses GP-relative addresses and one which uses absolute
709 addresses. When generating SVR4-style PIC, a macro may have
710 different expansions for local and global symbols.
712 We handle these situations by generating both sequences and putting
713 them in variant frags. In position-dependent code, the first sequence
714 will be the GP-relative one and the second sequence will be the
715 absolute one. In SVR4 PIC, the first sequence will be for global
716 symbols and the second will be for local symbols.
718 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
719 SECOND are the lengths of the two sequences in bytes. These fields
720 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
721 the subtype has the following flags:
724 Set if it has been decided that we should use the second
725 sequence instead of the first.
728 Set in the first variant frag if the macro's second implementation
729 is longer than its first. This refers to the macro as a whole,
730 not an individual relaxation.
733 Set in the first variant frag if the macro appeared in a .set nomacro
734 block and if one alternative requires a warning but the other does not.
737 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
740 The frag's "opcode" points to the first fixup for relaxable code.
742 Relaxable macros are generated using a sequence such as:
744 relax_start (SYMBOL);
745 ... generate first expansion ...
747 ... generate second expansion ...
750 The code and fixups for the unwanted alternative are discarded
751 by md_convert_frag. */
752 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
754 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
755 #define RELAX_SECOND(X) ((X) & 0xff)
756 #define RELAX_USE_SECOND 0x10000
757 #define RELAX_SECOND_LONGER 0x20000
758 #define RELAX_NOMACRO 0x40000
759 #define RELAX_DELAY_SLOT 0x80000
761 /* Branch without likely bit. If label is out of range, we turn:
763 beq reg1, reg2, label
773 with the following opcode replacements:
780 bltzal <-> bgezal (with jal label instead of j label)
782 Even though keeping the delay slot instruction in the delay slot of
783 the branch would be more efficient, it would be very tricky to do
784 correctly, because we'd have to introduce a variable frag *after*
785 the delay slot instruction, and expand that instead. Let's do it
786 the easy way for now, even if the branch-not-taken case now costs
787 one additional instruction. Out-of-range branches are not supposed
788 to be common, anyway.
790 Branch likely. If label is out of range, we turn:
792 beql reg1, reg2, label
793 delay slot (annulled if branch not taken)
802 delay slot (executed only if branch taken)
805 It would be possible to generate a shorter sequence by losing the
806 likely bit, generating something like:
811 delay slot (executed only if branch taken)
823 bltzall -> bgezal (with jal label instead of j label)
824 bgezall -> bltzal (ditto)
827 but it's not clear that it would actually improve performance. */
828 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
831 | ((toofar) ? 1 : 0) \
833 | ((likely) ? 4 : 0) \
834 | ((uncond) ? 8 : 0)))
835 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
836 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
837 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
838 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
839 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
841 /* For mips16 code, we use an entirely different form of relaxation.
842 mips16 supports two versions of most instructions which take
843 immediate values: a small one which takes some small value, and a
844 larger one which takes a 16 bit value. Since branches also follow
845 this pattern, relaxing these values is required.
847 We can assemble both mips16 and normal MIPS code in a single
848 object. Therefore, we need to support this type of relaxation at
849 the same time that we support the relaxation described above. We
850 use the high bit of the subtype field to distinguish these cases.
852 The information we store for this type of relaxation is the
853 argument code found in the opcode file for this relocation, whether
854 the user explicitly requested a small or extended form, and whether
855 the relocation is in a jump or jal delay slot. That tells us the
856 size of the value, and how it should be stored. We also store
857 whether the fragment is considered to be extended or not. We also
858 store whether this is known to be a branch to a different section,
859 whether we have tried to relax this frag yet, and whether we have
860 ever extended a PC relative fragment because of a shift count. */
861 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
864 | ((small) ? 0x100 : 0) \
865 | ((ext) ? 0x200 : 0) \
866 | ((dslot) ? 0x400 : 0) \
867 | ((jal_dslot) ? 0x800 : 0))
868 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
869 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
870 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
871 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
872 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
873 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
874 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
875 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
876 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
877 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
878 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
879 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
881 /* Is the given value a sign-extended 32-bit value? */
882 #define IS_SEXT_32BIT_NUM(x) \
883 (((x) &~ (offsetT) 0x7fffffff) == 0 \
884 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
886 /* Is the given value a sign-extended 16-bit value? */
887 #define IS_SEXT_16BIT_NUM(x) \
888 (((x) &~ (offsetT) 0x7fff) == 0 \
889 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
891 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
892 #define IS_ZEXT_32BIT_NUM(x) \
893 (((x) &~ (offsetT) 0xffffffff) == 0 \
894 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
896 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
897 VALUE << SHIFT. VALUE is evaluated exactly once. */
898 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
899 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
900 | (((VALUE) & (MASK)) << (SHIFT)))
902 /* Extract bits MASK << SHIFT from STRUCT and shift them right
904 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
905 (((STRUCT) >> (SHIFT)) & (MASK))
907 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
908 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
910 include/opcode/mips.h specifies operand fields using the macros
911 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
912 with "MIPS16OP" instead of "OP". */
913 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
914 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
915 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
916 INSERT_BITS ((INSN).insn_opcode, VALUE, \
917 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
919 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
920 #define EXTRACT_OPERAND(FIELD, INSN) \
921 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
922 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
923 EXTRACT_BITS ((INSN).insn_opcode, \
924 MIPS16OP_MASK_##FIELD, \
927 /* Global variables used when generating relaxable macros. See the
928 comment above RELAX_ENCODE for more details about how relaxation
931 /* 0 if we're not emitting a relaxable macro.
932 1 if we're emitting the first of the two relaxation alternatives.
933 2 if we're emitting the second alternative. */
936 /* The first relaxable fixup in the current frag. (In other words,
937 the first fixup that refers to relaxable code.) */
940 /* sizes[0] says how many bytes of the first alternative are stored in
941 the current frag. Likewise sizes[1] for the second alternative. */
942 unsigned int sizes
[2];
944 /* The symbol on which the choice of sequence depends. */
948 /* Global variables used to decide whether a macro needs a warning. */
950 /* True if the macro is in a branch delay slot. */
951 bfd_boolean delay_slot_p
;
953 /* For relaxable macros, sizes[0] is the length of the first alternative
954 in bytes and sizes[1] is the length of the second alternative.
955 For non-relaxable macros, both elements give the length of the
957 unsigned int sizes
[2];
959 /* The first variant frag for this macro. */
961 } mips_macro_warning
;
963 /* Prototypes for static functions. */
965 #define internalError() \
966 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
968 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
970 static void append_insn
971 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
972 static void mips_no_prev_insn (void);
973 static void mips16_macro_build
974 (expressionS
*, const char *, const char *, va_list);
975 static void load_register (int, expressionS
*, int);
976 static void macro_start (void);
977 static void macro_end (void);
978 static void macro (struct mips_cl_insn
* ip
);
979 static void mips16_macro (struct mips_cl_insn
* ip
);
980 #ifdef LOSING_COMPILER
981 static void macro2 (struct mips_cl_insn
* ip
);
983 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
984 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
985 static void mips16_immed
986 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
987 unsigned long *, bfd_boolean
*, unsigned short *);
988 static size_t my_getSmallExpression
989 (expressionS
*, bfd_reloc_code_real_type
*, char *);
990 static void my_getExpression (expressionS
*, char *);
991 static void s_align (int);
992 static void s_change_sec (int);
993 static void s_change_section (int);
994 static void s_cons (int);
995 static void s_float_cons (int);
996 static void s_mips_globl (int);
997 static void s_option (int);
998 static void s_mipsset (int);
999 static void s_abicalls (int);
1000 static void s_cpload (int);
1001 static void s_cpsetup (int);
1002 static void s_cplocal (int);
1003 static void s_cprestore (int);
1004 static void s_cpreturn (int);
1005 static void s_gpvalue (int);
1006 static void s_gpword (int);
1007 static void s_gpdword (int);
1008 static void s_cpadd (int);
1009 static void s_insn (int);
1010 static void md_obj_begin (void);
1011 static void md_obj_end (void);
1012 static void s_mips_ent (int);
1013 static void s_mips_end (int);
1014 static void s_mips_frame (int);
1015 static void s_mips_mask (int reg_type
);
1016 static void s_mips_stab (int);
1017 static void s_mips_weakext (int);
1018 static void s_mips_file (int);
1019 static void s_mips_loc (int);
1020 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1021 static int relaxed_branch_length (fragS
*, asection
*, int);
1022 static int validate_mips_insn (const struct mips_opcode
*);
1024 /* Table and functions used to map between CPU/ISA names, and
1025 ISA levels, and CPU numbers. */
1027 struct mips_cpu_info
1029 const char *name
; /* CPU or ISA name. */
1030 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
1031 int isa
; /* ISA level. */
1032 int cpu
; /* CPU number (default CPU if ISA). */
1035 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1036 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1037 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1041 The following pseudo-ops from the Kane and Heinrich MIPS book
1042 should be defined here, but are currently unsupported: .alias,
1043 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1045 The following pseudo-ops from the Kane and Heinrich MIPS book are
1046 specific to the type of debugging information being generated, and
1047 should be defined by the object format: .aent, .begin, .bend,
1048 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1051 The following pseudo-ops from the Kane and Heinrich MIPS book are
1052 not MIPS CPU specific, but are also not specific to the object file
1053 format. This file is probably the best place to define them, but
1054 they are not currently supported: .asm0, .endr, .lab, .repeat,
1057 static const pseudo_typeS mips_pseudo_table
[] =
1059 /* MIPS specific pseudo-ops. */
1060 {"option", s_option
, 0},
1061 {"set", s_mipsset
, 0},
1062 {"rdata", s_change_sec
, 'r'},
1063 {"sdata", s_change_sec
, 's'},
1064 {"livereg", s_ignore
, 0},
1065 {"abicalls", s_abicalls
, 0},
1066 {"cpload", s_cpload
, 0},
1067 {"cpsetup", s_cpsetup
, 0},
1068 {"cplocal", s_cplocal
, 0},
1069 {"cprestore", s_cprestore
, 0},
1070 {"cpreturn", s_cpreturn
, 0},
1071 {"gpvalue", s_gpvalue
, 0},
1072 {"gpword", s_gpword
, 0},
1073 {"gpdword", s_gpdword
, 0},
1074 {"cpadd", s_cpadd
, 0},
1075 {"insn", s_insn
, 0},
1077 /* Relatively generic pseudo-ops that happen to be used on MIPS
1079 {"asciiz", stringer
, 1},
1080 {"bss", s_change_sec
, 'b'},
1082 {"half", s_cons
, 1},
1083 {"dword", s_cons
, 3},
1084 {"weakext", s_mips_weakext
, 0},
1086 /* These pseudo-ops are defined in read.c, but must be overridden
1087 here for one reason or another. */
1088 {"align", s_align
, 0},
1089 {"byte", s_cons
, 0},
1090 {"data", s_change_sec
, 'd'},
1091 {"double", s_float_cons
, 'd'},
1092 {"float", s_float_cons
, 'f'},
1093 {"globl", s_mips_globl
, 0},
1094 {"global", s_mips_globl
, 0},
1095 {"hword", s_cons
, 1},
1097 {"long", s_cons
, 2},
1098 {"octa", s_cons
, 4},
1099 {"quad", s_cons
, 3},
1100 {"section", s_change_section
, 0},
1101 {"short", s_cons
, 1},
1102 {"single", s_float_cons
, 'f'},
1103 {"stabn", s_mips_stab
, 'n'},
1104 {"text", s_change_sec
, 't'},
1105 {"word", s_cons
, 2},
1107 { "extern", ecoff_directive_extern
, 0},
1112 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1114 /* These pseudo-ops should be defined by the object file format.
1115 However, a.out doesn't support them, so we have versions here. */
1116 {"aent", s_mips_ent
, 1},
1117 {"bgnb", s_ignore
, 0},
1118 {"end", s_mips_end
, 0},
1119 {"endb", s_ignore
, 0},
1120 {"ent", s_mips_ent
, 0},
1121 {"file", s_mips_file
, 0},
1122 {"fmask", s_mips_mask
, 'F'},
1123 {"frame", s_mips_frame
, 0},
1124 {"loc", s_mips_loc
, 0},
1125 {"mask", s_mips_mask
, 'R'},
1126 {"verstamp", s_ignore
, 0},
1130 extern void pop_insert (const pseudo_typeS
*);
1133 mips_pop_insert (void)
1135 pop_insert (mips_pseudo_table
);
1136 if (! ECOFF_DEBUGGING
)
1137 pop_insert (mips_nonecoff_pseudo_table
);
1140 /* Symbols labelling the current insn. */
1142 struct insn_label_list
1144 struct insn_label_list
*next
;
1148 static struct insn_label_list
*insn_labels
;
1149 static struct insn_label_list
*free_insn_labels
;
1151 static void mips_clear_insn_labels (void);
1154 mips_clear_insn_labels (void)
1156 register struct insn_label_list
**pl
;
1158 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1164 static char *expr_end
;
1166 /* Expressions which appear in instructions. These are set by
1169 static expressionS imm_expr
;
1170 static expressionS imm2_expr
;
1171 static expressionS offset_expr
;
1173 /* Relocs associated with imm_expr and offset_expr. */
1175 static bfd_reloc_code_real_type imm_reloc
[3]
1176 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1177 static bfd_reloc_code_real_type offset_reloc
[3]
1178 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1180 /* These are set by mips16_ip if an explicit extension is used. */
1182 static bfd_boolean mips16_small
, mips16_ext
;
1185 /* The pdr segment for per procedure frame/regmask info. Not used for
1188 static segT pdr_seg
;
1191 /* The default target format to use. */
1194 mips_target_format (void)
1196 switch (OUTPUT_FLAVOR
)
1198 case bfd_target_ecoff_flavour
:
1199 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1200 case bfd_target_coff_flavour
:
1202 case bfd_target_elf_flavour
:
1204 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1205 return (target_big_endian
1206 ? "elf32-bigmips-vxworks"
1207 : "elf32-littlemips-vxworks");
1210 /* This is traditional mips. */
1211 return (target_big_endian
1212 ? (HAVE_64BIT_OBJECTS
1213 ? "elf64-tradbigmips"
1215 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1216 : (HAVE_64BIT_OBJECTS
1217 ? "elf64-tradlittlemips"
1219 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1221 return (target_big_endian
1222 ? (HAVE_64BIT_OBJECTS
1225 ? "elf32-nbigmips" : "elf32-bigmips"))
1226 : (HAVE_64BIT_OBJECTS
1227 ? "elf64-littlemips"
1229 ? "elf32-nlittlemips" : "elf32-littlemips")));
1237 /* Return the length of instruction INSN. */
1239 static inline unsigned int
1240 insn_length (const struct mips_cl_insn
*insn
)
1242 if (!mips_opts
.mips16
)
1244 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1247 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1250 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1255 insn
->use_extend
= FALSE
;
1257 insn
->insn_opcode
= mo
->match
;
1260 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1261 insn
->fixp
[i
] = NULL
;
1262 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1263 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1264 insn
->mips16_absolute_jump_p
= 0;
1267 /* Install INSN at the location specified by its "frag" and "where" fields. */
1270 install_insn (const struct mips_cl_insn
*insn
)
1272 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1273 if (!mips_opts
.mips16
)
1274 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1275 else if (insn
->mips16_absolute_jump_p
)
1277 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1278 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1282 if (insn
->use_extend
)
1284 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1287 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1291 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1292 and install the opcode in the new location. */
1295 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1300 insn
->where
= where
;
1301 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1302 if (insn
->fixp
[i
] != NULL
)
1304 insn
->fixp
[i
]->fx_frag
= frag
;
1305 insn
->fixp
[i
]->fx_where
= where
;
1307 install_insn (insn
);
1310 /* Add INSN to the end of the output. */
1313 add_fixed_insn (struct mips_cl_insn
*insn
)
1315 char *f
= frag_more (insn_length (insn
));
1316 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1319 /* Start a variant frag and move INSN to the start of the variant part,
1320 marking it as fixed. The other arguments are as for frag_var. */
1323 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1324 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1326 frag_grow (max_chars
);
1327 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1329 frag_var (rs_machine_dependent
, max_chars
, var
,
1330 subtype
, symbol
, offset
, NULL
);
1333 /* Insert N copies of INSN into the history buffer, starting at
1334 position FIRST. Neither FIRST nor N need to be clipped. */
1337 insert_into_history (unsigned int first
, unsigned int n
,
1338 const struct mips_cl_insn
*insn
)
1340 if (mips_relax
.sequence
!= 2)
1344 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1346 history
[i
] = history
[i
- n
];
1352 /* Emit a nop instruction, recording it in the history buffer. */
1357 add_fixed_insn (NOP_INSN
);
1358 insert_into_history (0, 1, NOP_INSN
);
1361 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1362 the idea is to make it obvious at a glance that each errata is
1366 init_vr4120_conflicts (void)
1368 #define CONFLICT(FIRST, SECOND) \
1369 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1371 /* Errata 21 - [D]DIV[U] after [D]MACC */
1372 CONFLICT (MACC
, DIV
);
1373 CONFLICT (DMACC
, DIV
);
1375 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1376 CONFLICT (DMULT
, DMULT
);
1377 CONFLICT (DMULT
, DMACC
);
1378 CONFLICT (DMACC
, DMULT
);
1379 CONFLICT (DMACC
, DMACC
);
1381 /* Errata 24 - MT{LO,HI} after [D]MACC */
1382 CONFLICT (MACC
, MTHILO
);
1383 CONFLICT (DMACC
, MTHILO
);
1385 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1386 instruction is executed immediately after a MACC or DMACC
1387 instruction, the result of [either instruction] is incorrect." */
1388 CONFLICT (MACC
, MULT
);
1389 CONFLICT (MACC
, DMULT
);
1390 CONFLICT (DMACC
, MULT
);
1391 CONFLICT (DMACC
, DMULT
);
1393 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1394 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1395 DDIV or DDIVU instruction, the result of the MACC or
1396 DMACC instruction is incorrect.". */
1397 CONFLICT (DMULT
, MACC
);
1398 CONFLICT (DMULT
, DMACC
);
1399 CONFLICT (DIV
, MACC
);
1400 CONFLICT (DIV
, DMACC
);
1405 /* This function is called once, at assembler startup time. It should
1406 set up all the tables, etc. that the MD part of the assembler will need. */
1411 register const char *retval
= NULL
;
1415 if (mips_pic
!= NO_PIC
)
1417 if (g_switch_seen
&& g_switch_value
!= 0)
1418 as_bad (_("-G may not be used in position-independent code"));
1422 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1423 as_warn (_("Could not set architecture and machine"));
1425 op_hash
= hash_new ();
1427 for (i
= 0; i
< NUMOPCODES
;)
1429 const char *name
= mips_opcodes
[i
].name
;
1431 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1434 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1435 mips_opcodes
[i
].name
, retval
);
1436 /* Probably a memory allocation problem? Give up now. */
1437 as_fatal (_("Broken assembler. No assembly attempted."));
1441 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1443 if (!validate_mips_insn (&mips_opcodes
[i
]))
1445 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1447 create_insn (&nop_insn
, mips_opcodes
+ i
);
1448 nop_insn
.fixed_p
= 1;
1453 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1456 mips16_op_hash
= hash_new ();
1459 while (i
< bfd_mips16_num_opcodes
)
1461 const char *name
= mips16_opcodes
[i
].name
;
1463 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1465 as_fatal (_("internal: can't hash `%s': %s"),
1466 mips16_opcodes
[i
].name
, retval
);
1469 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1470 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1471 != mips16_opcodes
[i
].match
))
1473 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1474 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1477 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1479 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1480 mips16_nop_insn
.fixed_p
= 1;
1484 while (i
< bfd_mips16_num_opcodes
1485 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1489 as_fatal (_("Broken assembler. No assembly attempted."));
1491 /* We add all the general register names to the symbol table. This
1492 helps us detect invalid uses of them. */
1493 for (i
= 0; i
< 32; i
++)
1497 sprintf (buf
, "$%d", i
);
1498 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1499 &zero_address_frag
));
1501 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1502 &zero_address_frag
));
1503 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1504 &zero_address_frag
));
1505 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1506 &zero_address_frag
));
1507 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1508 &zero_address_frag
));
1509 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1510 &zero_address_frag
));
1511 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1512 &zero_address_frag
));
1513 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1514 &zero_address_frag
));
1515 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1516 &zero_address_frag
));
1517 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1518 &zero_address_frag
));
1520 /* If we don't add these register names to the symbol table, they
1521 may end up being added as regular symbols by operand(), and then
1522 make it to the object file as undefined in case they're not
1523 regarded as local symbols. They're local in o32, since `$' is a
1524 local symbol prefix, but not in n32 or n64. */
1525 for (i
= 0; i
< 8; i
++)
1529 sprintf (buf
, "$fcc%i", i
);
1530 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1531 &zero_address_frag
));
1534 mips_no_prev_insn ();
1537 mips_cprmask
[0] = 0;
1538 mips_cprmask
[1] = 0;
1539 mips_cprmask
[2] = 0;
1540 mips_cprmask
[3] = 0;
1542 /* set the default alignment for the text section (2**2) */
1543 record_alignment (text_section
, 2);
1545 bfd_set_gp_size (stdoutput
, g_switch_value
);
1547 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1549 /* On a native system other than VxWorks, sections must be aligned
1550 to 16 byte boundaries. When configured for an embedded ELF
1551 target, we don't bother. */
1552 if (strcmp (TARGET_OS
, "elf") != 0
1553 && strcmp (TARGET_OS
, "vxworks") != 0)
1555 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1556 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1557 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1560 /* Create a .reginfo section for register masks and a .mdebug
1561 section for debugging information. */
1569 subseg
= now_subseg
;
1571 /* The ABI says this section should be loaded so that the
1572 running program can access it. However, we don't load it
1573 if we are configured for an embedded target */
1574 flags
= SEC_READONLY
| SEC_DATA
;
1575 if (strcmp (TARGET_OS
, "elf") != 0)
1576 flags
|= SEC_ALLOC
| SEC_LOAD
;
1578 if (mips_abi
!= N64_ABI
)
1580 sec
= subseg_new (".reginfo", (subsegT
) 0);
1582 bfd_set_section_flags (stdoutput
, sec
, flags
);
1583 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1586 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1591 /* The 64-bit ABI uses a .MIPS.options section rather than
1592 .reginfo section. */
1593 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1594 bfd_set_section_flags (stdoutput
, sec
, flags
);
1595 bfd_set_section_alignment (stdoutput
, sec
, 3);
1598 /* Set up the option header. */
1600 Elf_Internal_Options opthdr
;
1603 opthdr
.kind
= ODK_REGINFO
;
1604 opthdr
.size
= (sizeof (Elf_External_Options
)
1605 + sizeof (Elf64_External_RegInfo
));
1608 f
= frag_more (sizeof (Elf_External_Options
));
1609 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1610 (Elf_External_Options
*) f
);
1612 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1617 if (ECOFF_DEBUGGING
)
1619 sec
= subseg_new (".mdebug", (subsegT
) 0);
1620 (void) bfd_set_section_flags (stdoutput
, sec
,
1621 SEC_HAS_CONTENTS
| SEC_READONLY
);
1622 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1625 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1627 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1628 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1629 SEC_READONLY
| SEC_RELOC
1631 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1635 subseg_set (seg
, subseg
);
1639 if (! ECOFF_DEBUGGING
)
1642 if (mips_fix_vr4120
)
1643 init_vr4120_conflicts ();
1649 if (! ECOFF_DEBUGGING
)
1654 md_assemble (char *str
)
1656 struct mips_cl_insn insn
;
1657 bfd_reloc_code_real_type unused_reloc
[3]
1658 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1660 imm_expr
.X_op
= O_absent
;
1661 imm2_expr
.X_op
= O_absent
;
1662 offset_expr
.X_op
= O_absent
;
1663 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1664 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1665 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1666 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1667 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1668 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1670 if (mips_opts
.mips16
)
1671 mips16_ip (str
, &insn
);
1674 mips_ip (str
, &insn
);
1675 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1676 str
, insn
.insn_opcode
));
1681 as_bad ("%s `%s'", insn_error
, str
);
1685 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1688 if (mips_opts
.mips16
)
1689 mips16_macro (&insn
);
1696 if (imm_expr
.X_op
!= O_absent
)
1697 append_insn (&insn
, &imm_expr
, imm_reloc
);
1698 else if (offset_expr
.X_op
!= O_absent
)
1699 append_insn (&insn
, &offset_expr
, offset_reloc
);
1701 append_insn (&insn
, NULL
, unused_reloc
);
1705 /* Return true if the given relocation might need a matching %lo().
1706 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1707 need a matching %lo() when applied to local symbols. */
1709 static inline bfd_boolean
1710 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1712 return (HAVE_IN_PLACE_ADDENDS
1713 && (reloc
== BFD_RELOC_HI16_S
1714 || reloc
== BFD_RELOC_MIPS16_HI16_S
1715 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
1716 all GOT16 relocations evaluate to "G". */
1717 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
1720 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1723 static inline bfd_boolean
1724 fixup_has_matching_lo_p (fixS
*fixp
)
1726 return (fixp
->fx_next
!= NULL
1727 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1728 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1729 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1730 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1733 /* See whether instruction IP reads register REG. CLASS is the type
1737 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1738 enum mips_regclass
class)
1740 if (class == MIPS16_REG
)
1742 assert (mips_opts
.mips16
);
1743 reg
= mips16_to_32_reg_map
[reg
];
1744 class = MIPS_GR_REG
;
1747 /* Don't report on general register ZERO, since it never changes. */
1748 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1751 if (class == MIPS_FP_REG
)
1753 assert (! mips_opts
.mips16
);
1754 /* If we are called with either $f0 or $f1, we must check $f0.
1755 This is not optimal, because it will introduce an unnecessary
1756 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1757 need to distinguish reading both $f0 and $f1 or just one of
1758 them. Note that we don't have to check the other way,
1759 because there is no instruction that sets both $f0 and $f1
1760 and requires a delay. */
1761 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1762 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1763 == (reg
&~ (unsigned) 1)))
1765 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1766 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1767 == (reg
&~ (unsigned) 1)))
1770 else if (! mips_opts
.mips16
)
1772 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1773 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1775 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1776 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1781 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1782 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1784 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1785 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1787 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1788 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1791 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1793 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1795 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1797 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1798 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1805 /* This function returns true if modifying a register requires a
1809 reg_needs_delay (unsigned int reg
)
1811 unsigned long prev_pinfo
;
1813 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1814 if (! mips_opts
.noreorder
1815 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1816 && ! gpr_interlocks
)
1817 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1818 && ! cop_interlocks
)))
1820 /* A load from a coprocessor or from memory. All load delays
1821 delay the use of general register rt for one instruction. */
1822 /* Itbl support may require additional care here. */
1823 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1824 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1831 /* Move all labels in insn_labels to the current insertion point. */
1834 mips_move_labels (void)
1836 struct insn_label_list
*l
;
1839 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1841 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1842 symbol_set_frag (l
->label
, frag_now
);
1843 val
= (valueT
) frag_now_fix ();
1844 /* mips16 text labels are stored as odd. */
1845 if (mips_opts
.mips16
)
1847 S_SET_VALUE (l
->label
, val
);
1851 /* Mark instruction labels in mips16 mode. This permits the linker to
1852 handle them specially, such as generating jalx instructions when
1853 needed. We also make them odd for the duration of the assembly, in
1854 order to generate the right sort of code. We will make them even
1855 in the adjust_symtab routine, while leaving them marked. This is
1856 convenient for the debugger and the disassembler. The linker knows
1857 to make them odd again. */
1860 mips16_mark_labels (void)
1862 if (mips_opts
.mips16
)
1864 struct insn_label_list
*l
;
1867 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1870 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1871 S_SET_OTHER (l
->label
, STO_MIPS16
);
1873 val
= S_GET_VALUE (l
->label
);
1875 S_SET_VALUE (l
->label
, val
+ 1);
1880 /* End the current frag. Make it a variant frag and record the
1884 relax_close_frag (void)
1886 mips_macro_warning
.first_frag
= frag_now
;
1887 frag_var (rs_machine_dependent
, 0, 0,
1888 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1889 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1891 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1892 mips_relax
.first_fixup
= 0;
1895 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1896 See the comment above RELAX_ENCODE for more details. */
1899 relax_start (symbolS
*symbol
)
1901 assert (mips_relax
.sequence
== 0);
1902 mips_relax
.sequence
= 1;
1903 mips_relax
.symbol
= symbol
;
1906 /* Start generating the second version of a relaxable sequence.
1907 See the comment above RELAX_ENCODE for more details. */
1912 assert (mips_relax
.sequence
== 1);
1913 mips_relax
.sequence
= 2;
1916 /* End the current relaxable sequence. */
1921 assert (mips_relax
.sequence
== 2);
1922 relax_close_frag ();
1923 mips_relax
.sequence
= 0;
1926 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1927 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1928 by VR4120 errata. */
1931 classify_vr4120_insn (const char *name
)
1933 if (strncmp (name
, "macc", 4) == 0)
1934 return FIX_VR4120_MACC
;
1935 if (strncmp (name
, "dmacc", 5) == 0)
1936 return FIX_VR4120_DMACC
;
1937 if (strncmp (name
, "mult", 4) == 0)
1938 return FIX_VR4120_MULT
;
1939 if (strncmp (name
, "dmult", 5) == 0)
1940 return FIX_VR4120_DMULT
;
1941 if (strstr (name
, "div"))
1942 return FIX_VR4120_DIV
;
1943 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1944 return FIX_VR4120_MTHILO
;
1945 return NUM_FIX_VR4120_CLASSES
;
1948 /* Return the number of instructions that must separate INSN1 and INSN2,
1949 where INSN1 is the earlier instruction. Return the worst-case value
1950 for any INSN2 if INSN2 is null. */
1953 insns_between (const struct mips_cl_insn
*insn1
,
1954 const struct mips_cl_insn
*insn2
)
1956 unsigned long pinfo1
, pinfo2
;
1958 /* This function needs to know which pinfo flags are set for INSN2
1959 and which registers INSN2 uses. The former is stored in PINFO2 and
1960 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1961 will have every flag set and INSN2_USES_REG will always return true. */
1962 pinfo1
= insn1
->insn_mo
->pinfo
;
1963 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1965 #define INSN2_USES_REG(REG, CLASS) \
1966 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1968 /* For most targets, write-after-read dependencies on the HI and LO
1969 registers must be separated by at least two instructions. */
1970 if (!hilo_interlocks
)
1972 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1974 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1978 /* If we're working around r7000 errata, there must be two instructions
1979 between an mfhi or mflo and any instruction that uses the result. */
1980 if (mips_7000_hilo_fix
1981 && MF_HILO_INSN (pinfo1
)
1982 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1985 /* If working around VR4120 errata, check for combinations that need
1986 a single intervening instruction. */
1987 if (mips_fix_vr4120
)
1989 unsigned int class1
, class2
;
1991 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1992 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1996 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1997 if (vr4120_conflicts
[class1
] & (1 << class2
))
2002 if (!mips_opts
.mips16
)
2004 /* Check for GPR or coprocessor load delays. All such delays
2005 are on the RT register. */
2006 /* Itbl support may require additional care here. */
2007 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2008 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2010 know (pinfo1
& INSN_WRITE_GPR_T
);
2011 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2015 /* Check for generic coprocessor hazards.
2017 This case is not handled very well. There is no special
2018 knowledge of CP0 handling, and the coprocessors other than
2019 the floating point unit are not distinguished at all. */
2020 /* Itbl support may require additional care here. FIXME!
2021 Need to modify this to include knowledge about
2022 user specified delays! */
2023 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2024 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2026 /* Handle cases where INSN1 writes to a known general coprocessor
2027 register. There must be a one instruction delay before INSN2
2028 if INSN2 reads that register, otherwise no delay is needed. */
2029 if (pinfo1
& INSN_WRITE_FPR_T
)
2031 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2034 else if (pinfo1
& INSN_WRITE_FPR_S
)
2036 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2041 /* Read-after-write dependencies on the control registers
2042 require a two-instruction gap. */
2043 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2044 && (pinfo2
& INSN_READ_COND_CODE
))
2047 /* We don't know exactly what INSN1 does. If INSN2 is
2048 also a coprocessor instruction, assume there must be
2049 a one instruction gap. */
2050 if (pinfo2
& INSN_COP
)
2055 /* Check for read-after-write dependencies on the coprocessor
2056 control registers in cases where INSN1 does not need a general
2057 coprocessor delay. This means that INSN1 is a floating point
2058 comparison instruction. */
2059 /* Itbl support may require additional care here. */
2060 else if (!cop_interlocks
2061 && (pinfo1
& INSN_WRITE_COND_CODE
)
2062 && (pinfo2
& INSN_READ_COND_CODE
))
2066 #undef INSN2_USES_REG
2071 /* Return the number of nops that would be needed to work around the
2072 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2073 the MAX_VR4130_NOPS instructions described by HISTORY. */
2076 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2077 const struct mips_cl_insn
*insn
)
2081 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2082 are not affected by the errata. */
2084 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2085 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2086 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2089 /* Search for the first MFLO or MFHI. */
2090 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2091 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2093 /* Extract the destination register. */
2094 if (mips_opts
.mips16
)
2095 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2097 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2099 /* No nops are needed if INSN reads that register. */
2100 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2103 /* ...or if any of the intervening instructions do. */
2104 for (j
= 0; j
< i
; j
++)
2105 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2108 return MAX_VR4130_NOPS
- i
;
2113 /* Return the number of nops that would be needed if instruction INSN
2114 immediately followed the MAX_NOPS instructions given by HISTORY,
2115 where HISTORY[0] is the most recent instruction. If INSN is null,
2116 return the worse-case number of nops for any instruction. */
2119 nops_for_insn (const struct mips_cl_insn
*history
,
2120 const struct mips_cl_insn
*insn
)
2122 int i
, nops
, tmp_nops
;
2125 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2126 if (!history
[i
].noreorder_p
)
2128 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2129 if (tmp_nops
> nops
)
2133 if (mips_fix_vr4130
)
2135 tmp_nops
= nops_for_vr4130 (history
, insn
);
2136 if (tmp_nops
> nops
)
2143 /* The variable arguments provide NUM_INSNS extra instructions that
2144 might be added to HISTORY. Return the largest number of nops that
2145 would be needed after the extended sequence. */
2148 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2151 struct mips_cl_insn buffer
[MAX_NOPS
];
2152 struct mips_cl_insn
*cursor
;
2155 va_start (args
, history
);
2156 cursor
= buffer
+ num_insns
;
2157 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2158 while (cursor
> buffer
)
2159 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2161 nops
= nops_for_insn (buffer
, NULL
);
2166 /* Like nops_for_insn, but if INSN is a branch, take into account the
2167 worst-case delay for the branch target. */
2170 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2171 const struct mips_cl_insn
*insn
)
2175 nops
= nops_for_insn (history
, insn
);
2176 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2177 | INSN_COND_BRANCH_DELAY
2178 | INSN_COND_BRANCH_LIKELY
))
2180 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2181 if (tmp_nops
> nops
)
2184 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2186 tmp_nops
= nops_for_sequence (1, history
, insn
);
2187 if (tmp_nops
> nops
)
2193 /* Output an instruction. IP is the instruction information.
2194 ADDRESS_EXPR is an operand of the instruction to be used with
2198 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2199 bfd_reloc_code_real_type
*reloc_type
)
2201 register unsigned long prev_pinfo
, pinfo
;
2202 relax_stateT prev_insn_frag_type
= 0;
2203 bfd_boolean relaxed_branch
= FALSE
;
2205 /* Mark instruction labels in mips16 mode. */
2206 mips16_mark_labels ();
2208 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2209 pinfo
= ip
->insn_mo
->pinfo
;
2211 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2213 /* There are a lot of optimizations we could do that we don't.
2214 In particular, we do not, in general, reorder instructions.
2215 If you use gcc with optimization, it will reorder
2216 instructions and generally do much more optimization then we
2217 do here; repeating all that work in the assembler would only
2218 benefit hand written assembly code, and does not seem worth
2220 int nops
= (mips_optimize
== 0
2221 ? nops_for_insn (history
, NULL
)
2222 : nops_for_insn_or_target (history
, ip
));
2226 unsigned long old_frag_offset
;
2229 old_frag
= frag_now
;
2230 old_frag_offset
= frag_now_fix ();
2232 for (i
= 0; i
< nops
; i
++)
2237 listing_prev_line ();
2238 /* We may be at the start of a variant frag. In case we
2239 are, make sure there is enough space for the frag
2240 after the frags created by listing_prev_line. The
2241 argument to frag_grow here must be at least as large
2242 as the argument to all other calls to frag_grow in
2243 this file. We don't have to worry about being in the
2244 middle of a variant frag, because the variants insert
2245 all needed nop instructions themselves. */
2249 mips_move_labels ();
2251 #ifndef NO_ECOFF_DEBUGGING
2252 if (ECOFF_DEBUGGING
)
2253 ecoff_fix_loc (old_frag
, old_frag_offset
);
2257 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2259 /* Work out how many nops in prev_nop_frag are needed by IP. */
2260 int nops
= nops_for_insn_or_target (history
, ip
);
2261 assert (nops
<= prev_nop_frag_holds
);
2263 /* Enforce NOPS as a minimum. */
2264 if (nops
> prev_nop_frag_required
)
2265 prev_nop_frag_required
= nops
;
2267 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2269 /* Settle for the current number of nops. Update the history
2270 accordingly (for the benefit of any future .set reorder code). */
2271 prev_nop_frag
= NULL
;
2272 insert_into_history (prev_nop_frag_since
,
2273 prev_nop_frag_holds
, NOP_INSN
);
2277 /* Allow this instruction to replace one of the nops that was
2278 tentatively added to prev_nop_frag. */
2279 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2280 prev_nop_frag_holds
--;
2281 prev_nop_frag_since
++;
2286 /* The value passed to dwarf2_emit_insn is the distance between
2287 the beginning of the current instruction and the address that
2288 should be recorded in the debug tables. For MIPS16 debug info
2289 we want to use ISA-encoded addresses, so we pass -1 for an
2290 address higher by one than the current. */
2291 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2294 /* Record the frag type before frag_var. */
2295 if (history
[0].frag
)
2296 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2299 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2300 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2301 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2302 && mips_relax_branch
2303 /* Don't try branch relaxation within .set nomacro, or within
2304 .set noat if we use $at for PIC computations. If it turns
2305 out that the branch was out-of-range, we'll get an error. */
2306 && !mips_opts
.warn_about_macros
2307 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2308 && !mips_opts
.mips16
)
2310 relaxed_branch
= TRUE
;
2311 add_relaxed_insn (ip
, (relaxed_branch_length
2313 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2314 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2317 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2318 pinfo
& INSN_COND_BRANCH_LIKELY
,
2319 pinfo
& INSN_WRITE_GPR_31
,
2321 address_expr
->X_add_symbol
,
2322 address_expr
->X_add_number
);
2323 *reloc_type
= BFD_RELOC_UNUSED
;
2325 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2327 /* We need to set up a variant frag. */
2328 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2329 add_relaxed_insn (ip
, 4, 0,
2331 (*reloc_type
- BFD_RELOC_UNUSED
,
2332 mips16_small
, mips16_ext
,
2333 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2334 history
[0].mips16_absolute_jump_p
),
2335 make_expr_symbol (address_expr
), 0);
2337 else if (mips_opts
.mips16
2339 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2341 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2342 /* Make sure there is enough room to swap this instruction with
2343 a following jump instruction. */
2345 add_fixed_insn (ip
);
2349 if (mips_opts
.mips16
2350 && mips_opts
.noreorder
2351 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2352 as_warn (_("extended instruction in delay slot"));
2354 if (mips_relax
.sequence
)
2356 /* If we've reached the end of this frag, turn it into a variant
2357 frag and record the information for the instructions we've
2359 if (frag_room () < 4)
2360 relax_close_frag ();
2361 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2364 if (mips_relax
.sequence
!= 2)
2365 mips_macro_warning
.sizes
[0] += 4;
2366 if (mips_relax
.sequence
!= 1)
2367 mips_macro_warning
.sizes
[1] += 4;
2369 if (mips_opts
.mips16
)
2372 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2374 add_fixed_insn (ip
);
2377 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2379 if (address_expr
->X_op
== O_constant
)
2383 switch (*reloc_type
)
2386 ip
->insn_opcode
|= address_expr
->X_add_number
;
2389 case BFD_RELOC_MIPS_HIGHEST
:
2390 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2391 ip
->insn_opcode
|= tmp
& 0xffff;
2394 case BFD_RELOC_MIPS_HIGHER
:
2395 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2396 ip
->insn_opcode
|= tmp
& 0xffff;
2399 case BFD_RELOC_HI16_S
:
2400 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2401 ip
->insn_opcode
|= tmp
& 0xffff;
2404 case BFD_RELOC_HI16
:
2405 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2408 case BFD_RELOC_UNUSED
:
2409 case BFD_RELOC_LO16
:
2410 case BFD_RELOC_MIPS_GOT_DISP
:
2411 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2414 case BFD_RELOC_MIPS_JMP
:
2415 if ((address_expr
->X_add_number
& 3) != 0)
2416 as_bad (_("jump to misaligned address (0x%lx)"),
2417 (unsigned long) address_expr
->X_add_number
);
2418 if (address_expr
->X_add_number
& ~0xfffffff)
2419 as_warn (_("jump address range overflow (0x%lx)"),
2420 (unsigned long) address_expr
->X_add_number
);
2421 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2424 case BFD_RELOC_MIPS16_JMP
:
2425 if ((address_expr
->X_add_number
& 3) != 0)
2426 as_bad (_("jump to misaligned address (0x%lx)"),
2427 (unsigned long) address_expr
->X_add_number
);
2428 if (address_expr
->X_add_number
& ~0xfffffff)
2429 as_warn (_("jump address range overflow (0x%lx)"),
2430 (unsigned long) address_expr
->X_add_number
);
2432 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2433 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2434 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2437 case BFD_RELOC_16_PCREL_S2
:
2438 if ((address_expr
->X_add_number
& 3) != 0)
2439 as_bad (_("branch to misaligned address (0x%lx)"),
2440 (unsigned long) address_expr
->X_add_number
);
2441 if (mips_relax_branch
)
2443 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2444 as_bad (_("branch address range overflow (0x%lx)"),
2445 (unsigned long) address_expr
->X_add_number
);
2446 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2453 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2456 reloc_howto_type
*howto
;
2459 /* In a compound relocation, it is the final (outermost)
2460 operator that determines the relocated field. */
2461 for (i
= 1; i
< 3; i
++)
2462 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2465 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2466 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2467 bfd_get_reloc_size (howto
),
2469 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2472 /* These relocations can have an addend that won't fit in
2473 4 octets for 64bit assembly. */
2475 && ! howto
->partial_inplace
2476 && (reloc_type
[0] == BFD_RELOC_16
2477 || reloc_type
[0] == BFD_RELOC_32
2478 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2479 || reloc_type
[0] == BFD_RELOC_HI16_S
2480 || reloc_type
[0] == BFD_RELOC_LO16
2481 || reloc_type
[0] == BFD_RELOC_GPREL16
2482 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2483 || reloc_type
[0] == BFD_RELOC_GPREL32
2484 || reloc_type
[0] == BFD_RELOC_64
2485 || reloc_type
[0] == BFD_RELOC_CTOR
2486 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2487 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2488 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2489 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2490 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2491 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2492 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2493 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2494 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2495 ip
->fixp
[0]->fx_no_overflow
= 1;
2497 if (mips_relax
.sequence
)
2499 if (mips_relax
.first_fixup
== 0)
2500 mips_relax
.first_fixup
= ip
->fixp
[0];
2502 else if (reloc_needs_lo_p (*reloc_type
))
2504 struct mips_hi_fixup
*hi_fixup
;
2506 /* Reuse the last entry if it already has a matching %lo. */
2507 hi_fixup
= mips_hi_fixup_list
;
2509 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2511 hi_fixup
= ((struct mips_hi_fixup
*)
2512 xmalloc (sizeof (struct mips_hi_fixup
)));
2513 hi_fixup
->next
= mips_hi_fixup_list
;
2514 mips_hi_fixup_list
= hi_fixup
;
2516 hi_fixup
->fixp
= ip
->fixp
[0];
2517 hi_fixup
->seg
= now_seg
;
2520 /* Add fixups for the second and third relocations, if given.
2521 Note that the ABI allows the second relocation to be
2522 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2523 moment we only use RSS_UNDEF, but we could add support
2524 for the others if it ever becomes necessary. */
2525 for (i
= 1; i
< 3; i
++)
2526 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2528 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2529 ip
->fixp
[0]->fx_size
, NULL
, 0,
2530 FALSE
, reloc_type
[i
]);
2532 /* Use fx_tcbit to mark compound relocs. */
2533 ip
->fixp
[0]->fx_tcbit
= 1;
2534 ip
->fixp
[i
]->fx_tcbit
= 1;
2540 /* Update the register mask information. */
2541 if (! mips_opts
.mips16
)
2543 if (pinfo
& INSN_WRITE_GPR_D
)
2544 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2545 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2546 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2547 if (pinfo
& INSN_READ_GPR_S
)
2548 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2549 if (pinfo
& INSN_WRITE_GPR_31
)
2550 mips_gprmask
|= 1 << RA
;
2551 if (pinfo
& INSN_WRITE_FPR_D
)
2552 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2553 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2554 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2555 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2556 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2557 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2558 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2559 if (pinfo
& INSN_COP
)
2561 /* We don't keep enough information to sort these cases out.
2562 The itbl support does keep this information however, although
2563 we currently don't support itbl fprmats as part of the cop
2564 instruction. May want to add this support in the future. */
2566 /* Never set the bit for $0, which is always zero. */
2567 mips_gprmask
&= ~1 << 0;
2571 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2572 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2573 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2574 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2575 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2576 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2577 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2578 mips_gprmask
|= 1 << TREG
;
2579 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2580 mips_gprmask
|= 1 << SP
;
2581 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2582 mips_gprmask
|= 1 << RA
;
2583 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2584 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2585 if (pinfo
& MIPS16_INSN_READ_Z
)
2586 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2587 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2588 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2591 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2593 /* Filling the branch delay slot is more complex. We try to
2594 switch the branch with the previous instruction, which we can
2595 do if the previous instruction does not set up a condition
2596 that the branch tests and if the branch is not itself the
2597 target of any branch. */
2598 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2599 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2601 if (mips_optimize
< 2
2602 /* If we have seen .set volatile or .set nomove, don't
2604 || mips_opts
.nomove
!= 0
2605 /* We can't swap if the previous instruction's position
2607 || history
[0].fixed_p
2608 /* If the previous previous insn was in a .set
2609 noreorder, we can't swap. Actually, the MIPS
2610 assembler will swap in this situation. However, gcc
2611 configured -with-gnu-as will generate code like
2617 in which we can not swap the bne and INSN. If gcc is
2618 not configured -with-gnu-as, it does not output the
2620 || history
[1].noreorder_p
2621 /* If the branch is itself the target of a branch, we
2622 can not swap. We cheat on this; all we check for is
2623 whether there is a label on this instruction. If
2624 there are any branches to anything other than a
2625 label, users must use .set noreorder. */
2626 || insn_labels
!= NULL
2627 /* If the previous instruction is in a variant frag
2628 other than this branch's one, we cannot do the swap.
2629 This does not apply to the mips16, which uses variant
2630 frags for different purposes. */
2631 || (! mips_opts
.mips16
2632 && prev_insn_frag_type
== rs_machine_dependent
)
2633 /* Check for conflicts between the branch and the instructions
2634 before the candidate delay slot. */
2635 || nops_for_insn (history
+ 1, ip
) > 0
2636 /* Check for conflicts between the swapped sequence and the
2637 target of the branch. */
2638 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2639 /* We do not swap with a trap instruction, since it
2640 complicates trap handlers to have the trap
2641 instruction be in a delay slot. */
2642 || (prev_pinfo
& INSN_TRAP
)
2643 /* If the branch reads a register that the previous
2644 instruction sets, we can not swap. */
2645 || (! mips_opts
.mips16
2646 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2647 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2649 || (! mips_opts
.mips16
2650 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2651 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2653 || (mips_opts
.mips16
2654 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2656 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2658 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2660 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2662 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2664 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2666 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2667 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2668 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2669 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2670 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2671 && insn_uses_reg (ip
,
2672 MIPS16OP_EXTRACT_REG32R
2673 (history
[0].insn_opcode
),
2675 /* If the branch writes a register that the previous
2676 instruction sets, we can not swap (we know that
2677 branches write only to RD or to $31). */
2678 || (! mips_opts
.mips16
2679 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2680 && (((pinfo
& INSN_WRITE_GPR_D
)
2681 && (EXTRACT_OPERAND (RT
, history
[0])
2682 == EXTRACT_OPERAND (RD
, *ip
)))
2683 || ((pinfo
& INSN_WRITE_GPR_31
)
2684 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2685 || (! mips_opts
.mips16
2686 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2687 && (((pinfo
& INSN_WRITE_GPR_D
)
2688 && (EXTRACT_OPERAND (RD
, history
[0])
2689 == EXTRACT_OPERAND (RD
, *ip
)))
2690 || ((pinfo
& INSN_WRITE_GPR_31
)
2691 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2692 || (mips_opts
.mips16
2693 && (pinfo
& MIPS16_INSN_WRITE_31
)
2694 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2695 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2696 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2698 /* If the branch writes a register that the previous
2699 instruction reads, we can not swap (we know that
2700 branches only write to RD or to $31). */
2701 || (! mips_opts
.mips16
2702 && (pinfo
& INSN_WRITE_GPR_D
)
2703 && insn_uses_reg (&history
[0],
2704 EXTRACT_OPERAND (RD
, *ip
),
2706 || (! mips_opts
.mips16
2707 && (pinfo
& INSN_WRITE_GPR_31
)
2708 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2709 || (mips_opts
.mips16
2710 && (pinfo
& MIPS16_INSN_WRITE_31
)
2711 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2712 /* If one instruction sets a condition code and the
2713 other one uses a condition code, we can not swap. */
2714 || ((pinfo
& INSN_READ_COND_CODE
)
2715 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2716 || ((pinfo
& INSN_WRITE_COND_CODE
)
2717 && (prev_pinfo
& INSN_READ_COND_CODE
))
2718 /* If the previous instruction uses the PC, we can not
2720 || (mips_opts
.mips16
2721 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2722 /* If the previous instruction had a fixup in mips16
2723 mode, we can not swap. This normally means that the
2724 previous instruction was a 4 byte branch anyhow. */
2725 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2726 /* If the previous instruction is a sync, sync.l, or
2727 sync.p, we can not swap. */
2728 || (prev_pinfo
& INSN_SYNC
))
2730 if (mips_opts
.mips16
2731 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2732 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
2733 && (mips_opts
.isa
== ISA_MIPS32
2734 || mips_opts
.isa
== ISA_MIPS32R2
2735 || mips_opts
.isa
== ISA_MIPS64
2736 || mips_opts
.isa
== ISA_MIPS64R2
))
2738 /* Convert MIPS16 jr/jalr into a "compact" jump. */
2739 ip
->insn_opcode
|= 0x0080;
2741 insert_into_history (0, 1, ip
);
2745 /* We could do even better for unconditional branches to
2746 portions of this object file; we could pick up the
2747 instruction at the destination, put it in the delay
2748 slot, and bump the destination address. */
2749 insert_into_history (0, 1, ip
);
2753 if (mips_relax
.sequence
)
2754 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2758 /* It looks like we can actually do the swap. */
2759 struct mips_cl_insn delay
= history
[0];
2760 if (mips_opts
.mips16
)
2762 know (delay
.frag
== ip
->frag
);
2763 move_insn (ip
, delay
.frag
, delay
.where
);
2764 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2766 else if (relaxed_branch
)
2768 /* Add the delay slot instruction to the end of the
2769 current frag and shrink the fixed part of the
2770 original frag. If the branch occupies the tail of
2771 the latter, move it backwards to cover the gap. */
2772 delay
.frag
->fr_fix
-= 4;
2773 if (delay
.frag
== ip
->frag
)
2774 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2775 add_fixed_insn (&delay
);
2779 move_insn (&delay
, ip
->frag
, ip
->where
);
2780 move_insn (ip
, history
[0].frag
, history
[0].where
);
2784 insert_into_history (0, 1, &delay
);
2787 /* If that was an unconditional branch, forget the previous
2788 insn information. */
2789 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2790 mips_no_prev_insn ();
2792 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2794 /* We don't yet optimize a branch likely. What we should do
2795 is look at the target, copy the instruction found there
2796 into the delay slot, and increment the branch to jump to
2797 the next instruction. */
2798 insert_into_history (0, 1, ip
);
2802 insert_into_history (0, 1, ip
);
2805 insert_into_history (0, 1, ip
);
2807 /* We just output an insn, so the next one doesn't have a label. */
2808 mips_clear_insn_labels ();
2811 /* Forget that there was any previous instruction or label. */
2814 mips_no_prev_insn (void)
2816 prev_nop_frag
= NULL
;
2817 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2818 mips_clear_insn_labels ();
2821 /* This function must be called before we emit something other than
2822 instructions. It is like mips_no_prev_insn except that it inserts
2823 any NOPS that might be needed by previous instructions. */
2826 mips_emit_delays (void)
2828 if (! mips_opts
.noreorder
)
2830 int nops
= nops_for_insn (history
, NULL
);
2834 add_fixed_insn (NOP_INSN
);
2835 mips_move_labels ();
2838 mips_no_prev_insn ();
2841 /* Start a (possibly nested) noreorder block. */
2844 start_noreorder (void)
2846 if (mips_opts
.noreorder
== 0)
2851 /* None of the instructions before the .set noreorder can be moved. */
2852 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2853 history
[i
].fixed_p
= 1;
2855 /* Insert any nops that might be needed between the .set noreorder
2856 block and the previous instructions. We will later remove any
2857 nops that turn out not to be needed. */
2858 nops
= nops_for_insn (history
, NULL
);
2861 if (mips_optimize
!= 0)
2863 /* Record the frag which holds the nop instructions, so
2864 that we can remove them if we don't need them. */
2865 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2866 prev_nop_frag
= frag_now
;
2867 prev_nop_frag_holds
= nops
;
2868 prev_nop_frag_required
= 0;
2869 prev_nop_frag_since
= 0;
2872 for (; nops
> 0; --nops
)
2873 add_fixed_insn (NOP_INSN
);
2875 /* Move on to a new frag, so that it is safe to simply
2876 decrease the size of prev_nop_frag. */
2877 frag_wane (frag_now
);
2879 mips_move_labels ();
2881 mips16_mark_labels ();
2882 mips_clear_insn_labels ();
2884 mips_opts
.noreorder
++;
2885 mips_any_noreorder
= 1;
2888 /* End a nested noreorder block. */
2891 end_noreorder (void)
2893 mips_opts
.noreorder
--;
2894 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2896 /* Commit to inserting prev_nop_frag_required nops and go back to
2897 handling nop insertion the .set reorder way. */
2898 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2899 * (mips_opts
.mips16
? 2 : 4));
2900 insert_into_history (prev_nop_frag_since
,
2901 prev_nop_frag_required
, NOP_INSN
);
2902 prev_nop_frag
= NULL
;
2906 /* Set up global variables for the start of a new macro. */
2911 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2912 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2913 && (history
[0].insn_mo
->pinfo
2914 & (INSN_UNCOND_BRANCH_DELAY
2915 | INSN_COND_BRANCH_DELAY
2916 | INSN_COND_BRANCH_LIKELY
)) != 0);
2919 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2920 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2921 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2924 macro_warning (relax_substateT subtype
)
2926 if (subtype
& RELAX_DELAY_SLOT
)
2927 return _("Macro instruction expanded into multiple instructions"
2928 " in a branch delay slot");
2929 else if (subtype
& RELAX_NOMACRO
)
2930 return _("Macro instruction expanded into multiple instructions");
2935 /* Finish up a macro. Emit warnings as appropriate. */
2940 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2942 relax_substateT subtype
;
2944 /* Set up the relaxation warning flags. */
2946 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2947 subtype
|= RELAX_SECOND_LONGER
;
2948 if (mips_opts
.warn_about_macros
)
2949 subtype
|= RELAX_NOMACRO
;
2950 if (mips_macro_warning
.delay_slot_p
)
2951 subtype
|= RELAX_DELAY_SLOT
;
2953 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2955 /* Either the macro has a single implementation or both
2956 implementations are longer than 4 bytes. Emit the
2958 const char *msg
= macro_warning (subtype
);
2964 /* One implementation might need a warning but the other
2965 definitely doesn't. */
2966 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2971 /* Read a macro's relocation codes from *ARGS and store them in *R.
2972 The first argument in *ARGS will be either the code for a single
2973 relocation or -1 followed by the three codes that make up a
2974 composite relocation. */
2977 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2981 next
= va_arg (*args
, int);
2983 r
[0] = (bfd_reloc_code_real_type
) next
;
2985 for (i
= 0; i
< 3; i
++)
2986 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2989 /* Build an instruction created by a macro expansion. This is passed
2990 a pointer to the count of instructions created so far, an
2991 expression, the name of the instruction to build, an operand format
2992 string, and corresponding arguments. */
2995 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2997 const struct mips_opcode
*mo
;
2998 struct mips_cl_insn insn
;
2999 bfd_reloc_code_real_type r
[3];
3002 va_start (args
, fmt
);
3004 if (mips_opts
.mips16
)
3006 mips16_macro_build (ep
, name
, fmt
, args
);
3011 r
[0] = BFD_RELOC_UNUSED
;
3012 r
[1] = BFD_RELOC_UNUSED
;
3013 r
[2] = BFD_RELOC_UNUSED
;
3014 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3016 assert (strcmp (name
, mo
->name
) == 0);
3018 /* Search until we get a match for NAME. It is assumed here that
3019 macros will never generate MDMX or MIPS-3D instructions. */
3020 while (strcmp (fmt
, mo
->args
) != 0
3021 || mo
->pinfo
== INSN_MACRO
3022 || !OPCODE_IS_MEMBER (mo
,
3024 | (file_ase_mips16
? INSN_MIPS16
: 0)
3025 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
3027 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
3031 assert (strcmp (name
, mo
->name
) == 0);
3034 create_insn (&insn
, mo
);
3052 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3057 /* Note that in the macro case, these arguments are already
3058 in MSB form. (When handling the instruction in the
3059 non-macro case, these arguments are sizes from which
3060 MSB values must be calculated.) */
3061 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3067 /* Note that in the macro case, these arguments are already
3068 in MSBD form. (When handling the instruction in the
3069 non-macro case, these arguments are sizes from which
3070 MSBD values must be calculated.) */
3071 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3082 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3086 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3091 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3097 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3102 int tmp
= va_arg (args
, int);
3104 INSERT_OPERAND (RT
, insn
, tmp
);
3105 INSERT_OPERAND (RD
, insn
, tmp
);
3111 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3118 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3122 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3126 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3130 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3134 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3141 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3147 macro_read_relocs (&args
, r
);
3148 assert (*r
== BFD_RELOC_GPREL16
3149 || *r
== BFD_RELOC_MIPS_LITERAL
3150 || *r
== BFD_RELOC_MIPS_HIGHER
3151 || *r
== BFD_RELOC_HI16_S
3152 || *r
== BFD_RELOC_LO16
3153 || *r
== BFD_RELOC_MIPS_GOT16
3154 || *r
== BFD_RELOC_MIPS_CALL16
3155 || *r
== BFD_RELOC_MIPS_GOT_DISP
3156 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3157 || *r
== BFD_RELOC_MIPS_GOT_OFST
3158 || *r
== BFD_RELOC_MIPS_GOT_LO16
3159 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3163 macro_read_relocs (&args
, r
);
3165 && (ep
->X_op
== O_constant
3166 || (ep
->X_op
== O_symbol
3167 && (*r
== BFD_RELOC_MIPS_HIGHEST
3168 || *r
== BFD_RELOC_HI16_S
3169 || *r
== BFD_RELOC_HI16
3170 || *r
== BFD_RELOC_GPREL16
3171 || *r
== BFD_RELOC_MIPS_GOT_HI16
3172 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3176 assert (ep
!= NULL
);
3179 * This allows macro() to pass an immediate expression for
3180 * creating short branches without creating a symbol.
3182 * We don't allow branch relaxation for these branches, as
3183 * they should only appear in ".set nomacro" anyway.
3185 if (ep
->X_op
== O_constant
)
3187 if ((ep
->X_add_number
& 3) != 0)
3188 as_bad (_("branch to misaligned address (0x%lx)"),
3189 (unsigned long) ep
->X_add_number
);
3190 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3191 as_bad (_("branch address range overflow (0x%lx)"),
3192 (unsigned long) ep
->X_add_number
);
3193 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3197 *r
= BFD_RELOC_16_PCREL_S2
;
3201 assert (ep
!= NULL
);
3202 *r
= BFD_RELOC_MIPS_JMP
;
3206 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3210 insn
.insn_opcode
|= va_arg (args
, unsigned long) << OP_SH_CACHE
;
3219 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3221 append_insn (&insn
, ep
, r
);
3225 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3228 struct mips_opcode
*mo
;
3229 struct mips_cl_insn insn
;
3230 bfd_reloc_code_real_type r
[3]
3231 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3233 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3235 assert (strcmp (name
, mo
->name
) == 0);
3237 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3241 assert (strcmp (name
, mo
->name
) == 0);
3244 create_insn (&insn
, mo
);
3262 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3267 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3271 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3275 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3285 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3292 regno
= va_arg (args
, int);
3293 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3294 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3315 assert (ep
!= NULL
);
3317 if (ep
->X_op
!= O_constant
)
3318 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3321 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3322 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3325 *r
= BFD_RELOC_UNUSED
;
3331 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3338 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3340 append_insn (&insn
, ep
, r
);
3344 * Sign-extend 32-bit mode constants that have bit 31 set and all
3345 * higher bits unset.
3348 normalize_constant_expr (expressionS
*ex
)
3350 if (ex
->X_op
== O_constant
3351 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3352 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3357 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3358 * all higher bits unset.
3361 normalize_address_expr (expressionS
*ex
)
3363 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3364 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3365 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3366 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3371 * Generate a "jalr" instruction with a relocation hint to the called
3372 * function. This occurs in NewABI PIC code.
3375 macro_build_jalr (expressionS
*ep
)
3384 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3386 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3387 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3391 * Generate a "lui" instruction.
3394 macro_build_lui (expressionS
*ep
, int regnum
)
3396 expressionS high_expr
;
3397 const struct mips_opcode
*mo
;
3398 struct mips_cl_insn insn
;
3399 bfd_reloc_code_real_type r
[3]
3400 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3401 const char *name
= "lui";
3402 const char *fmt
= "t,u";
3404 assert (! mips_opts
.mips16
);
3408 if (high_expr
.X_op
== O_constant
)
3410 /* we can compute the instruction now without a relocation entry */
3411 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3413 *r
= BFD_RELOC_UNUSED
;
3417 assert (ep
->X_op
== O_symbol
);
3418 /* _gp_disp is a special case, used from s_cpload.
3419 __gnu_local_gp is used if mips_no_shared. */
3420 assert (mips_pic
== NO_PIC
3422 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3423 || (! mips_in_shared
3424 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3425 "__gnu_local_gp") == 0));
3426 *r
= BFD_RELOC_HI16_S
;
3429 mo
= hash_find (op_hash
, name
);
3430 assert (strcmp (name
, mo
->name
) == 0);
3431 assert (strcmp (fmt
, mo
->args
) == 0);
3432 create_insn (&insn
, mo
);
3434 insn
.insn_opcode
= insn
.insn_mo
->match
;
3435 INSERT_OPERAND (RT
, insn
, regnum
);
3436 if (*r
== BFD_RELOC_UNUSED
)
3438 insn
.insn_opcode
|= high_expr
.X_add_number
;
3439 append_insn (&insn
, NULL
, r
);
3442 append_insn (&insn
, &high_expr
, r
);
3445 /* Generate a sequence of instructions to do a load or store from a constant
3446 offset off of a base register (breg) into/from a target register (treg),
3447 using AT if necessary. */
3449 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3450 int treg
, int breg
, int dbl
)
3452 assert (ep
->X_op
== O_constant
);
3454 /* Sign-extending 32-bit constants makes their handling easier. */
3456 normalize_constant_expr (ep
);
3458 /* Right now, this routine can only handle signed 32-bit constants. */
3459 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3460 as_warn (_("operand overflow"));
3462 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3464 /* Signed 16-bit offset will fit in the op. Easy! */
3465 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3469 /* 32-bit offset, need multiple instructions and AT, like:
3470 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3471 addu $tempreg,$tempreg,$breg
3472 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3473 to handle the complete offset. */
3474 macro_build_lui (ep
, AT
);
3475 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3476 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3479 as_bad (_("Macro used $at after \".set noat\""));
3484 * Generates code to set the $at register to true (one)
3485 * if reg is less than the immediate expression.
3488 set_at (int reg
, int unsignedp
)
3490 if (imm_expr
.X_op
== O_constant
3491 && imm_expr
.X_add_number
>= -0x8000
3492 && imm_expr
.X_add_number
< 0x8000)
3493 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3494 AT
, reg
, BFD_RELOC_LO16
);
3497 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3498 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3502 /* Warn if an expression is not a constant. */
3505 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3507 if (ex
->X_op
== O_big
)
3508 as_bad (_("unsupported large constant"));
3509 else if (ex
->X_op
!= O_constant
)
3510 as_bad (_("Instruction %s requires absolute expression"),
3513 if (HAVE_32BIT_GPRS
)
3514 normalize_constant_expr (ex
);
3517 /* Count the leading zeroes by performing a binary chop. This is a
3518 bulky bit of source, but performance is a LOT better for the
3519 majority of values than a simple loop to count the bits:
3520 for (lcnt = 0; (lcnt < 32); lcnt++)
3521 if ((v) & (1 << (31 - lcnt)))
3523 However it is not code size friendly, and the gain will drop a bit
3524 on certain cached systems.
3526 #define COUNT_TOP_ZEROES(v) \
3527 (((v) & ~0xffff) == 0 \
3528 ? ((v) & ~0xff) == 0 \
3529 ? ((v) & ~0xf) == 0 \
3530 ? ((v) & ~0x3) == 0 \
3531 ? ((v) & ~0x1) == 0 \
3536 : ((v) & ~0x7) == 0 \
3539 : ((v) & ~0x3f) == 0 \
3540 ? ((v) & ~0x1f) == 0 \
3543 : ((v) & ~0x7f) == 0 \
3546 : ((v) & ~0xfff) == 0 \
3547 ? ((v) & ~0x3ff) == 0 \
3548 ? ((v) & ~0x1ff) == 0 \
3551 : ((v) & ~0x7ff) == 0 \
3554 : ((v) & ~0x3fff) == 0 \
3555 ? ((v) & ~0x1fff) == 0 \
3558 : ((v) & ~0x7fff) == 0 \
3561 : ((v) & ~0xffffff) == 0 \
3562 ? ((v) & ~0xfffff) == 0 \
3563 ? ((v) & ~0x3ffff) == 0 \
3564 ? ((v) & ~0x1ffff) == 0 \
3567 : ((v) & ~0x7ffff) == 0 \
3570 : ((v) & ~0x3fffff) == 0 \
3571 ? ((v) & ~0x1fffff) == 0 \
3574 : ((v) & ~0x7fffff) == 0 \
3577 : ((v) & ~0xfffffff) == 0 \
3578 ? ((v) & ~0x3ffffff) == 0 \
3579 ? ((v) & ~0x1ffffff) == 0 \
3582 : ((v) & ~0x7ffffff) == 0 \
3585 : ((v) & ~0x3fffffff) == 0 \
3586 ? ((v) & ~0x1fffffff) == 0 \
3589 : ((v) & ~0x7fffffff) == 0 \
3594 * This routine generates the least number of instructions necessary to load
3595 * an absolute expression value into a register.
3598 load_register (int reg
, expressionS
*ep
, int dbl
)
3601 expressionS hi32
, lo32
;
3603 if (ep
->X_op
!= O_big
)
3605 assert (ep
->X_op
== O_constant
);
3607 /* Sign-extending 32-bit constants makes their handling easier. */
3609 normalize_constant_expr (ep
);
3611 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3613 /* We can handle 16 bit signed values with an addiu to
3614 $zero. No need to ever use daddiu here, since $zero and
3615 the result are always correct in 32 bit mode. */
3616 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3619 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3621 /* We can handle 16 bit unsigned values with an ori to
3623 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3626 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3628 /* 32 bit values require an lui. */
3629 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3630 if ((ep
->X_add_number
& 0xffff) != 0)
3631 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3636 /* The value is larger than 32 bits. */
3638 if (!dbl
|| HAVE_32BIT_GPRS
)
3642 sprintf_vma (value
, ep
->X_add_number
);
3643 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3644 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3648 if (ep
->X_op
!= O_big
)
3651 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3652 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3653 hi32
.X_add_number
&= 0xffffffff;
3655 lo32
.X_add_number
&= 0xffffffff;
3659 assert (ep
->X_add_number
> 2);
3660 if (ep
->X_add_number
== 3)
3661 generic_bignum
[3] = 0;
3662 else if (ep
->X_add_number
> 4)
3663 as_bad (_("Number larger than 64 bits"));
3664 lo32
.X_op
= O_constant
;
3665 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3666 hi32
.X_op
= O_constant
;
3667 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3670 if (hi32
.X_add_number
== 0)
3675 unsigned long hi
, lo
;
3677 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3679 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3681 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3684 if (lo32
.X_add_number
& 0x80000000)
3686 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3687 if (lo32
.X_add_number
& 0xffff)
3688 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3693 /* Check for 16bit shifted constant. We know that hi32 is
3694 non-zero, so start the mask on the first bit of the hi32
3699 unsigned long himask
, lomask
;
3703 himask
= 0xffff >> (32 - shift
);
3704 lomask
= (0xffff << shift
) & 0xffffffff;
3708 himask
= 0xffff << (shift
- 32);
3711 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3712 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3716 tmp
.X_op
= O_constant
;
3718 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3719 | (lo32
.X_add_number
>> shift
));
3721 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3722 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3723 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3724 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3729 while (shift
<= (64 - 16));
3731 /* Find the bit number of the lowest one bit, and store the
3732 shifted value in hi/lo. */
3733 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3734 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3738 while ((lo
& 1) == 0)
3743 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3749 while ((hi
& 1) == 0)
3758 /* Optimize if the shifted value is a (power of 2) - 1. */
3759 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3760 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3762 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3767 /* This instruction will set the register to be all
3769 tmp
.X_op
= O_constant
;
3770 tmp
.X_add_number
= (offsetT
) -1;
3771 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3775 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3776 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3778 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3779 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3784 /* Sign extend hi32 before calling load_register, because we can
3785 generally get better code when we load a sign extended value. */
3786 if ((hi32
.X_add_number
& 0x80000000) != 0)
3787 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3788 load_register (reg
, &hi32
, 0);
3791 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3795 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3803 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3805 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3806 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3812 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3816 mid16
.X_add_number
>>= 16;
3817 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3818 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3821 if ((lo32
.X_add_number
& 0xffff) != 0)
3822 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3826 load_delay_nop (void)
3828 if (!gpr_interlocks
)
3829 macro_build (NULL
, "nop", "");
3832 /* Load an address into a register. */
3835 load_address (int reg
, expressionS
*ep
, int *used_at
)
3837 if (ep
->X_op
!= O_constant
3838 && ep
->X_op
!= O_symbol
)
3840 as_bad (_("expression too complex"));
3841 ep
->X_op
= O_constant
;
3844 if (ep
->X_op
== O_constant
)
3846 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3850 if (mips_pic
== NO_PIC
)
3852 /* If this is a reference to a GP relative symbol, we want
3853 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3855 lui $reg,<sym> (BFD_RELOC_HI16_S)
3856 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3857 If we have an addend, we always use the latter form.
3859 With 64bit address space and a usable $at we want
3860 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3861 lui $at,<sym> (BFD_RELOC_HI16_S)
3862 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3863 daddiu $at,<sym> (BFD_RELOC_LO16)
3867 If $at is already in use, we use a path which is suboptimal
3868 on superscalar processors.
3869 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3870 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3872 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3874 daddiu $reg,<sym> (BFD_RELOC_LO16)
3876 For GP relative symbols in 64bit address space we can use
3877 the same sequence as in 32bit address space. */
3878 if (HAVE_64BIT_SYMBOLS
)
3880 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3881 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3883 relax_start (ep
->X_add_symbol
);
3884 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3885 mips_gp_register
, BFD_RELOC_GPREL16
);
3889 if (*used_at
== 0 && !mips_opts
.noat
)
3891 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3892 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3893 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3894 BFD_RELOC_MIPS_HIGHER
);
3895 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3896 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3897 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3902 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3903 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3904 BFD_RELOC_MIPS_HIGHER
);
3905 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3906 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3907 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3908 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3911 if (mips_relax
.sequence
)
3916 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3917 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3919 relax_start (ep
->X_add_symbol
);
3920 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3921 mips_gp_register
, BFD_RELOC_GPREL16
);
3924 macro_build_lui (ep
, reg
);
3925 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3926 reg
, reg
, BFD_RELOC_LO16
);
3927 if (mips_relax
.sequence
)
3931 else if (!mips_big_got
)
3935 /* If this is a reference to an external symbol, we want
3936 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3938 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3940 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3941 If there is a constant, it must be added in after.
3943 If we have NewABI, we want
3944 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3945 unless we're referencing a global symbol with a non-zero
3946 offset, in which case cst must be added separately. */
3949 if (ep
->X_add_number
)
3951 ex
.X_add_number
= ep
->X_add_number
;
3952 ep
->X_add_number
= 0;
3953 relax_start (ep
->X_add_symbol
);
3954 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3955 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3956 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3957 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3958 ex
.X_op
= O_constant
;
3959 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3960 reg
, reg
, BFD_RELOC_LO16
);
3961 ep
->X_add_number
= ex
.X_add_number
;
3964 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3965 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3966 if (mips_relax
.sequence
)
3971 ex
.X_add_number
= ep
->X_add_number
;
3972 ep
->X_add_number
= 0;
3973 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3974 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3976 relax_start (ep
->X_add_symbol
);
3978 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3982 if (ex
.X_add_number
!= 0)
3984 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3985 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3986 ex
.X_op
= O_constant
;
3987 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3988 reg
, reg
, BFD_RELOC_LO16
);
3992 else if (mips_big_got
)
3996 /* This is the large GOT case. If this is a reference to an
3997 external symbol, we want
3998 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4000 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4002 Otherwise, for a reference to a local symbol in old ABI, we want
4003 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4005 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4006 If there is a constant, it must be added in after.
4008 In the NewABI, for local symbols, with or without offsets, we want:
4009 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4010 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4014 ex
.X_add_number
= ep
->X_add_number
;
4015 ep
->X_add_number
= 0;
4016 relax_start (ep
->X_add_symbol
);
4017 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4018 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4019 reg
, reg
, mips_gp_register
);
4020 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4021 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4022 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4023 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4024 else if (ex
.X_add_number
)
4026 ex
.X_op
= O_constant
;
4027 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4031 ep
->X_add_number
= ex
.X_add_number
;
4033 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4034 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4035 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4036 BFD_RELOC_MIPS_GOT_OFST
);
4041 ex
.X_add_number
= ep
->X_add_number
;
4042 ep
->X_add_number
= 0;
4043 relax_start (ep
->X_add_symbol
);
4044 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4045 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4046 reg
, reg
, mips_gp_register
);
4047 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4048 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4050 if (reg_needs_delay (mips_gp_register
))
4052 /* We need a nop before loading from $gp. This special
4053 check is required because the lui which starts the main
4054 instruction stream does not refer to $gp, and so will not
4055 insert the nop which may be required. */
4056 macro_build (NULL
, "nop", "");
4058 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4059 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4061 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4065 if (ex
.X_add_number
!= 0)
4067 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4068 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4069 ex
.X_op
= O_constant
;
4070 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4078 if (mips_opts
.noat
&& *used_at
== 1)
4079 as_bad (_("Macro used $at after \".set noat\""));
4082 /* Move the contents of register SOURCE into register DEST. */
4085 move_register (int dest
, int source
)
4087 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4091 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4092 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4093 The two alternatives are:
4095 Global symbol Local sybmol
4096 ------------- ------------
4097 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4099 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4101 load_got_offset emits the first instruction and add_got_offset
4102 emits the second for a 16-bit offset or add_got_offset_hilo emits
4103 a sequence to add a 32-bit offset using a scratch register. */
4106 load_got_offset (int dest
, expressionS
*local
)
4111 global
.X_add_number
= 0;
4113 relax_start (local
->X_add_symbol
);
4114 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4115 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4117 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4118 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4123 add_got_offset (int dest
, expressionS
*local
)
4127 global
.X_op
= O_constant
;
4128 global
.X_op_symbol
= NULL
;
4129 global
.X_add_symbol
= NULL
;
4130 global
.X_add_number
= local
->X_add_number
;
4132 relax_start (local
->X_add_symbol
);
4133 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4134 dest
, dest
, BFD_RELOC_LO16
);
4136 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4141 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4144 int hold_mips_optimize
;
4146 global
.X_op
= O_constant
;
4147 global
.X_op_symbol
= NULL
;
4148 global
.X_add_symbol
= NULL
;
4149 global
.X_add_number
= local
->X_add_number
;
4151 relax_start (local
->X_add_symbol
);
4152 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4154 /* Set mips_optimize around the lui instruction to avoid
4155 inserting an unnecessary nop after the lw. */
4156 hold_mips_optimize
= mips_optimize
;
4158 macro_build_lui (&global
, tmp
);
4159 mips_optimize
= hold_mips_optimize
;
4160 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4163 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4168 * This routine implements the seemingly endless macro or synthesized
4169 * instructions and addressing modes in the mips assembly language. Many
4170 * of these macros are simple and are similar to each other. These could
4171 * probably be handled by some kind of table or grammar approach instead of
4172 * this verbose method. Others are not simple macros but are more like
4173 * optimizing code generation.
4174 * One interesting optimization is when several store macros appear
4175 * consecutively that would load AT with the upper half of the same address.
4176 * The ensuing load upper instructions are ommited. This implies some kind
4177 * of global optimization. We currently only optimize within a single macro.
4178 * For many of the load and store macros if the address is specified as a
4179 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4180 * first load register 'at' with zero and use it as the base register. The
4181 * mips assembler simply uses register $zero. Just one tiny optimization
4185 macro (struct mips_cl_insn
*ip
)
4187 register int treg
, sreg
, dreg
, breg
;
4203 bfd_reloc_code_real_type r
;
4204 int hold_mips_optimize
;
4206 assert (! mips_opts
.mips16
);
4208 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4209 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4210 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4211 mask
= ip
->insn_mo
->mask
;
4213 expr1
.X_op
= O_constant
;
4214 expr1
.X_op_symbol
= NULL
;
4215 expr1
.X_add_symbol
= NULL
;
4216 expr1
.X_add_number
= 1;
4230 expr1
.X_add_number
= 8;
4231 macro_build (&expr1
, "bgez", "s,p", sreg
);
4233 macro_build (NULL
, "nop", "", 0);
4235 move_register (dreg
, sreg
);
4236 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4259 if (imm_expr
.X_op
== O_constant
4260 && imm_expr
.X_add_number
>= -0x8000
4261 && imm_expr
.X_add_number
< 0x8000)
4263 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4267 load_register (AT
, &imm_expr
, dbl
);
4268 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4287 if (imm_expr
.X_op
== O_constant
4288 && imm_expr
.X_add_number
>= 0
4289 && imm_expr
.X_add_number
< 0x10000)
4291 if (mask
!= M_NOR_I
)
4292 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4295 macro_build (&imm_expr
, "ori", "t,r,i",
4296 treg
, sreg
, BFD_RELOC_LO16
);
4297 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4303 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4304 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4321 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4323 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4327 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4328 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4336 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4341 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4345 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4346 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4352 /* check for > max integer */
4353 maxnum
= 0x7fffffff;
4354 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4361 if (imm_expr
.X_op
== O_constant
4362 && imm_expr
.X_add_number
>= maxnum
4363 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4366 /* result is always false */
4368 macro_build (NULL
, "nop", "", 0);
4370 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4373 if (imm_expr
.X_op
!= O_constant
)
4374 as_bad (_("Unsupported large constant"));
4375 ++imm_expr
.X_add_number
;
4379 if (mask
== M_BGEL_I
)
4381 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4383 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4386 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4388 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4391 maxnum
= 0x7fffffff;
4392 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4399 maxnum
= - maxnum
- 1;
4400 if (imm_expr
.X_op
== O_constant
4401 && imm_expr
.X_add_number
<= maxnum
4402 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4405 /* result is always true */
4406 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4407 macro_build (&offset_expr
, "b", "p");
4412 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4422 macro_build (&offset_expr
, likely
? "beql" : "beq",
4427 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4428 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4436 && imm_expr
.X_op
== O_constant
4437 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4439 if (imm_expr
.X_op
!= O_constant
)
4440 as_bad (_("Unsupported large constant"));
4441 ++imm_expr
.X_add_number
;
4445 if (mask
== M_BGEUL_I
)
4447 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4449 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4451 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4457 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4465 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4470 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4474 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4475 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4483 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4490 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4491 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4499 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4504 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4508 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4509 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4515 maxnum
= 0x7fffffff;
4516 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4523 if (imm_expr
.X_op
== O_constant
4524 && imm_expr
.X_add_number
>= maxnum
4525 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4527 if (imm_expr
.X_op
!= O_constant
)
4528 as_bad (_("Unsupported large constant"));
4529 ++imm_expr
.X_add_number
;
4533 if (mask
== M_BLTL_I
)
4535 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4537 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4540 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4542 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4547 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4555 macro_build (&offset_expr
, likely
? "beql" : "beq",
4562 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4563 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4571 && imm_expr
.X_op
== O_constant
4572 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4574 if (imm_expr
.X_op
!= O_constant
)
4575 as_bad (_("Unsupported large constant"));
4576 ++imm_expr
.X_add_number
;
4580 if (mask
== M_BLTUL_I
)
4582 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4584 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4586 macro_build (&offset_expr
, likely
? "beql" : "beq",
4592 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4600 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4605 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4609 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4610 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4620 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4625 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4626 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4634 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4636 as_bad (_("Unsupported large constant"));
4641 pos
= (unsigned long) imm_expr
.X_add_number
;
4642 size
= (unsigned long) imm2_expr
.X_add_number
;
4647 as_bad (_("Improper position (%lu)"), pos
);
4650 if (size
== 0 || size
> 64
4651 || (pos
+ size
- 1) > 63)
4653 as_bad (_("Improper extract size (%lu, position %lu)"),
4658 if (size
<= 32 && pos
< 32)
4663 else if (size
<= 32)
4673 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4682 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4684 as_bad (_("Unsupported large constant"));
4689 pos
= (unsigned long) imm_expr
.X_add_number
;
4690 size
= (unsigned long) imm2_expr
.X_add_number
;
4695 as_bad (_("Improper position (%lu)"), pos
);
4698 if (size
== 0 || size
> 64
4699 || (pos
+ size
- 1) > 63)
4701 as_bad (_("Improper insert size (%lu, position %lu)"),
4706 if (pos
< 32 && (pos
+ size
- 1) < 32)
4721 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4738 as_warn (_("Divide by zero."));
4740 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4742 macro_build (NULL
, "break", "c", 7);
4749 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4750 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4754 expr1
.X_add_number
= 8;
4755 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4756 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4757 macro_build (NULL
, "break", "c", 7);
4759 expr1
.X_add_number
= -1;
4761 load_register (AT
, &expr1
, dbl
);
4762 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4763 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4766 expr1
.X_add_number
= 1;
4767 load_register (AT
, &expr1
, dbl
);
4768 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4772 expr1
.X_add_number
= 0x80000000;
4773 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4777 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4778 /* We want to close the noreorder block as soon as possible, so
4779 that later insns are available for delay slot filling. */
4784 expr1
.X_add_number
= 8;
4785 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4786 macro_build (NULL
, "nop", "", 0);
4788 /* We want to close the noreorder block as soon as possible, so
4789 that later insns are available for delay slot filling. */
4792 macro_build (NULL
, "break", "c", 6);
4794 macro_build (NULL
, s
, "d", dreg
);
4833 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4835 as_warn (_("Divide by zero."));
4837 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4839 macro_build (NULL
, "break", "c", 7);
4842 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4844 if (strcmp (s2
, "mflo") == 0)
4845 move_register (dreg
, sreg
);
4847 move_register (dreg
, 0);
4850 if (imm_expr
.X_op
== O_constant
4851 && imm_expr
.X_add_number
== -1
4852 && s
[strlen (s
) - 1] != 'u')
4854 if (strcmp (s2
, "mflo") == 0)
4856 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4859 move_register (dreg
, 0);
4864 load_register (AT
, &imm_expr
, dbl
);
4865 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4866 macro_build (NULL
, s2
, "d", dreg
);
4888 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4889 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4890 /* We want to close the noreorder block as soon as possible, so
4891 that later insns are available for delay slot filling. */
4896 expr1
.X_add_number
= 8;
4897 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4898 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4900 /* We want to close the noreorder block as soon as possible, so
4901 that later insns are available for delay slot filling. */
4903 macro_build (NULL
, "break", "c", 7);
4905 macro_build (NULL
, s2
, "d", dreg
);
4917 /* Load the address of a symbol into a register. If breg is not
4918 zero, we then add a base register to it. */
4920 if (dbl
&& HAVE_32BIT_GPRS
)
4921 as_warn (_("dla used to load 32-bit register"));
4923 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4924 as_warn (_("la used to load 64-bit address"));
4926 if (offset_expr
.X_op
== O_constant
4927 && offset_expr
.X_add_number
>= -0x8000
4928 && offset_expr
.X_add_number
< 0x8000)
4930 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4931 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4935 if (!mips_opts
.noat
&& (treg
== breg
))
4945 if (offset_expr
.X_op
!= O_symbol
4946 && offset_expr
.X_op
!= O_constant
)
4948 as_bad (_("expression too complex"));
4949 offset_expr
.X_op
= O_constant
;
4952 if (offset_expr
.X_op
== O_constant
)
4953 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4954 else if (mips_pic
== NO_PIC
)
4956 /* If this is a reference to a GP relative symbol, we want
4957 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4959 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4960 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4961 If we have a constant, we need two instructions anyhow,
4962 so we may as well always use the latter form.
4964 With 64bit address space and a usable $at we want
4965 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4966 lui $at,<sym> (BFD_RELOC_HI16_S)
4967 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4968 daddiu $at,<sym> (BFD_RELOC_LO16)
4970 daddu $tempreg,$tempreg,$at
4972 If $at is already in use, we use a path which is suboptimal
4973 on superscalar processors.
4974 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4975 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4977 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4979 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4981 For GP relative symbols in 64bit address space we can use
4982 the same sequence as in 32bit address space. */
4983 if (HAVE_64BIT_SYMBOLS
)
4985 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4986 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4988 relax_start (offset_expr
.X_add_symbol
);
4989 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4990 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4994 if (used_at
== 0 && !mips_opts
.noat
)
4996 macro_build (&offset_expr
, "lui", "t,u",
4997 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4998 macro_build (&offset_expr
, "lui", "t,u",
4999 AT
, BFD_RELOC_HI16_S
);
5000 macro_build (&offset_expr
, "daddiu", "t,r,j",
5001 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5002 macro_build (&offset_expr
, "daddiu", "t,r,j",
5003 AT
, AT
, BFD_RELOC_LO16
);
5004 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5005 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5010 macro_build (&offset_expr
, "lui", "t,u",
5011 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5012 macro_build (&offset_expr
, "daddiu", "t,r,j",
5013 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5014 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5015 macro_build (&offset_expr
, "daddiu", "t,r,j",
5016 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5017 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5018 macro_build (&offset_expr
, "daddiu", "t,r,j",
5019 tempreg
, tempreg
, BFD_RELOC_LO16
);
5022 if (mips_relax
.sequence
)
5027 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5028 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5030 relax_start (offset_expr
.X_add_symbol
);
5031 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5032 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5035 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5036 as_bad (_("offset too large"));
5037 macro_build_lui (&offset_expr
, tempreg
);
5038 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5039 tempreg
, tempreg
, BFD_RELOC_LO16
);
5040 if (mips_relax
.sequence
)
5044 else if (!mips_big_got
&& !HAVE_NEWABI
)
5046 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5048 /* If this is a reference to an external symbol, and there
5049 is no constant, we want
5050 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5051 or for lca or if tempreg is PIC_CALL_REG
5052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5053 For a local symbol, we want
5054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5056 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5058 If we have a small constant, and this is a reference to
5059 an external symbol, we want
5060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5062 addiu $tempreg,$tempreg,<constant>
5063 For a local symbol, we want the same instruction
5064 sequence, but we output a BFD_RELOC_LO16 reloc on the
5067 If we have a large constant, and this is a reference to
5068 an external symbol, we want
5069 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5070 lui $at,<hiconstant>
5071 addiu $at,$at,<loconstant>
5072 addu $tempreg,$tempreg,$at
5073 For a local symbol, we want the same instruction
5074 sequence, but we output a BFD_RELOC_LO16 reloc on the
5078 if (offset_expr
.X_add_number
== 0)
5080 if (mips_pic
== SVR4_PIC
5082 && (call
|| tempreg
== PIC_CALL_REG
))
5083 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5085 relax_start (offset_expr
.X_add_symbol
);
5086 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5087 lw_reloc_type
, mips_gp_register
);
5090 /* We're going to put in an addu instruction using
5091 tempreg, so we may as well insert the nop right
5096 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5097 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5099 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5100 tempreg
, tempreg
, BFD_RELOC_LO16
);
5102 /* FIXME: If breg == 0, and the next instruction uses
5103 $tempreg, then if this variant case is used an extra
5104 nop will be generated. */
5106 else if (offset_expr
.X_add_number
>= -0x8000
5107 && offset_expr
.X_add_number
< 0x8000)
5109 load_got_offset (tempreg
, &offset_expr
);
5111 add_got_offset (tempreg
, &offset_expr
);
5115 expr1
.X_add_number
= offset_expr
.X_add_number
;
5116 offset_expr
.X_add_number
=
5117 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5118 load_got_offset (tempreg
, &offset_expr
);
5119 offset_expr
.X_add_number
= expr1
.X_add_number
;
5120 /* If we are going to add in a base register, and the
5121 target register and the base register are the same,
5122 then we are using AT as a temporary register. Since
5123 we want to load the constant into AT, we add our
5124 current AT (from the global offset table) and the
5125 register into the register now, and pretend we were
5126 not using a base register. */
5130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5135 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5139 else if (!mips_big_got
&& HAVE_NEWABI
)
5141 int add_breg_early
= 0;
5143 /* If this is a reference to an external, and there is no
5144 constant, or local symbol (*), with or without a
5146 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5147 or for lca or if tempreg is PIC_CALL_REG
5148 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5150 If we have a small constant, and this is a reference to
5151 an external symbol, we want
5152 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5153 addiu $tempreg,$tempreg,<constant>
5155 If we have a large constant, and this is a reference to
5156 an external symbol, we want
5157 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5158 lui $at,<hiconstant>
5159 addiu $at,$at,<loconstant>
5160 addu $tempreg,$tempreg,$at
5162 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5163 local symbols, even though it introduces an additional
5166 if (offset_expr
.X_add_number
)
5168 expr1
.X_add_number
= offset_expr
.X_add_number
;
5169 offset_expr
.X_add_number
= 0;
5171 relax_start (offset_expr
.X_add_symbol
);
5172 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5173 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5175 if (expr1
.X_add_number
>= -0x8000
5176 && expr1
.X_add_number
< 0x8000)
5178 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5179 tempreg
, tempreg
, BFD_RELOC_LO16
);
5181 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5185 /* If we are going to add in a base register, and the
5186 target register and the base register are the same,
5187 then we are using AT as a temporary register. Since
5188 we want to load the constant into AT, we add our
5189 current AT (from the global offset table) and the
5190 register into the register now, and pretend we were
5191 not using a base register. */
5196 assert (tempreg
== AT
);
5197 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5203 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5204 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5210 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5213 offset_expr
.X_add_number
= expr1
.X_add_number
;
5215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5216 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5219 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5220 treg
, tempreg
, breg
);
5226 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5228 relax_start (offset_expr
.X_add_symbol
);
5229 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5230 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5232 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5233 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5238 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5239 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5242 else if (mips_big_got
&& !HAVE_NEWABI
)
5245 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5246 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5247 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5249 /* This is the large GOT case. If this is a reference to an
5250 external symbol, and there is no constant, we want
5251 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5252 addu $tempreg,$tempreg,$gp
5253 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5254 or for lca or if tempreg is PIC_CALL_REG
5255 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5256 addu $tempreg,$tempreg,$gp
5257 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5258 For a local symbol, we want
5259 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5261 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5263 If we have a small constant, and this is a reference to
5264 an external symbol, we want
5265 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5266 addu $tempreg,$tempreg,$gp
5267 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5269 addiu $tempreg,$tempreg,<constant>
5270 For a local symbol, we want
5271 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5273 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5275 If we have a large constant, and this is a reference to
5276 an external symbol, we want
5277 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5278 addu $tempreg,$tempreg,$gp
5279 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5280 lui $at,<hiconstant>
5281 addiu $at,$at,<loconstant>
5282 addu $tempreg,$tempreg,$at
5283 For a local symbol, we want
5284 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5285 lui $at,<hiconstant>
5286 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5287 addu $tempreg,$tempreg,$at
5290 expr1
.X_add_number
= offset_expr
.X_add_number
;
5291 offset_expr
.X_add_number
= 0;
5292 relax_start (offset_expr
.X_add_symbol
);
5293 gpdelay
= reg_needs_delay (mips_gp_register
);
5294 if (expr1
.X_add_number
== 0 && breg
== 0
5295 && (call
|| tempreg
== PIC_CALL_REG
))
5297 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5298 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5300 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5301 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5302 tempreg
, tempreg
, mips_gp_register
);
5303 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5304 tempreg
, lw_reloc_type
, tempreg
);
5305 if (expr1
.X_add_number
== 0)
5309 /* We're going to put in an addu instruction using
5310 tempreg, so we may as well insert the nop right
5315 else if (expr1
.X_add_number
>= -0x8000
5316 && expr1
.X_add_number
< 0x8000)
5319 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5320 tempreg
, tempreg
, BFD_RELOC_LO16
);
5326 /* If we are going to add in a base register, and the
5327 target register and the base register are the same,
5328 then we are using AT as a temporary register. Since
5329 we want to load the constant into AT, we add our
5330 current AT (from the global offset table) and the
5331 register into the register now, and pretend we were
5332 not using a base register. */
5337 assert (tempreg
== AT
);
5339 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5344 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5345 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5349 offset_expr
.X_add_number
=
5350 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5355 /* This is needed because this instruction uses $gp, but
5356 the first instruction on the main stream does not. */
5357 macro_build (NULL
, "nop", "");
5360 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5361 local_reloc_type
, mips_gp_register
);
5362 if (expr1
.X_add_number
>= -0x8000
5363 && expr1
.X_add_number
< 0x8000)
5366 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5367 tempreg
, tempreg
, BFD_RELOC_LO16
);
5368 /* FIXME: If add_number is 0, and there was no base
5369 register, the external symbol case ended with a load,
5370 so if the symbol turns out to not be external, and
5371 the next instruction uses tempreg, an unnecessary nop
5372 will be inserted. */
5378 /* We must add in the base register now, as in the
5379 external symbol case. */
5380 assert (tempreg
== AT
);
5382 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5385 /* We set breg to 0 because we have arranged to add
5386 it in in both cases. */
5390 macro_build_lui (&expr1
, AT
);
5391 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5392 AT
, AT
, BFD_RELOC_LO16
);
5393 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5394 tempreg
, tempreg
, AT
);
5399 else if (mips_big_got
&& HAVE_NEWABI
)
5401 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5402 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5403 int add_breg_early
= 0;
5405 /* This is the large GOT case. If this is a reference to an
5406 external symbol, and there is no constant, we want
5407 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5408 add $tempreg,$tempreg,$gp
5409 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5410 or for lca or if tempreg is PIC_CALL_REG
5411 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5412 add $tempreg,$tempreg,$gp
5413 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5415 If we have a small constant, and this is a reference to
5416 an external symbol, we want
5417 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5418 add $tempreg,$tempreg,$gp
5419 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5420 addi $tempreg,$tempreg,<constant>
5422 If we have a large constant, and this is a reference to
5423 an external symbol, we want
5424 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5425 addu $tempreg,$tempreg,$gp
5426 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5427 lui $at,<hiconstant>
5428 addi $at,$at,<loconstant>
5429 add $tempreg,$tempreg,$at
5431 If we have NewABI, and we know it's a local symbol, we want
5432 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5433 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5434 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5436 relax_start (offset_expr
.X_add_symbol
);
5438 expr1
.X_add_number
= offset_expr
.X_add_number
;
5439 offset_expr
.X_add_number
= 0;
5441 if (expr1
.X_add_number
== 0 && breg
== 0
5442 && (call
|| tempreg
== PIC_CALL_REG
))
5444 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5445 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5447 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5448 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5449 tempreg
, tempreg
, mips_gp_register
);
5450 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5451 tempreg
, lw_reloc_type
, tempreg
);
5453 if (expr1
.X_add_number
== 0)
5455 else if (expr1
.X_add_number
>= -0x8000
5456 && expr1
.X_add_number
< 0x8000)
5458 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5459 tempreg
, tempreg
, BFD_RELOC_LO16
);
5461 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5465 /* If we are going to add in a base register, and the
5466 target register and the base register are the same,
5467 then we are using AT as a temporary register. Since
5468 we want to load the constant into AT, we add our
5469 current AT (from the global offset table) and the
5470 register into the register now, and pretend we were
5471 not using a base register. */
5476 assert (tempreg
== AT
);
5477 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5483 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5484 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5489 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5492 offset_expr
.X_add_number
= expr1
.X_add_number
;
5493 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5494 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5495 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5496 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5499 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5500 treg
, tempreg
, breg
);
5510 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5514 /* The j instruction may not be used in PIC code, since it
5515 requires an absolute address. We convert it to a b
5517 if (mips_pic
== NO_PIC
)
5518 macro_build (&offset_expr
, "j", "a");
5520 macro_build (&offset_expr
, "b", "p");
5523 /* The jal instructions must be handled as macros because when
5524 generating PIC code they expand to multi-instruction
5525 sequences. Normally they are simple instructions. */
5530 if (mips_pic
== NO_PIC
)
5531 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5534 if (sreg
!= PIC_CALL_REG
)
5535 as_warn (_("MIPS PIC call to register other than $25"));
5537 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5538 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5540 if (mips_cprestore_offset
< 0)
5541 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5544 if (! mips_frame_reg_valid
)
5546 as_warn (_("No .frame pseudo-op used in PIC code"));
5547 /* Quiet this warning. */
5548 mips_frame_reg_valid
= 1;
5550 if (! mips_cprestore_valid
)
5552 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5553 /* Quiet this warning. */
5554 mips_cprestore_valid
= 1;
5556 expr1
.X_add_number
= mips_cprestore_offset
;
5557 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5560 HAVE_64BIT_ADDRESSES
);
5568 if (mips_pic
== NO_PIC
)
5569 macro_build (&offset_expr
, "jal", "a");
5570 else if (mips_pic
== SVR4_PIC
)
5572 /* If this is a reference to an external symbol, and we are
5573 using a small GOT, we want
5574 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5578 lw $gp,cprestore($sp)
5579 The cprestore value is set using the .cprestore
5580 pseudo-op. If we are using a big GOT, we want
5581 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5583 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5587 lw $gp,cprestore($sp)
5588 If the symbol is not external, we want
5589 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5591 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5594 lw $gp,cprestore($sp)
5596 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5597 sequences above, minus nops, unless the symbol is local,
5598 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5604 relax_start (offset_expr
.X_add_symbol
);
5605 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5606 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5609 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5610 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5616 relax_start (offset_expr
.X_add_symbol
);
5617 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5618 BFD_RELOC_MIPS_CALL_HI16
);
5619 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5620 PIC_CALL_REG
, mips_gp_register
);
5621 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5622 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5625 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5626 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5628 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5629 PIC_CALL_REG
, PIC_CALL_REG
,
5630 BFD_RELOC_MIPS_GOT_OFST
);
5634 macro_build_jalr (&offset_expr
);
5638 relax_start (offset_expr
.X_add_symbol
);
5641 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5642 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5651 gpdelay
= reg_needs_delay (mips_gp_register
);
5652 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5653 BFD_RELOC_MIPS_CALL_HI16
);
5654 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5655 PIC_CALL_REG
, mips_gp_register
);
5656 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5657 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5662 macro_build (NULL
, "nop", "");
5664 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5665 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5668 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5669 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5671 macro_build_jalr (&offset_expr
);
5673 if (mips_cprestore_offset
< 0)
5674 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5677 if (! mips_frame_reg_valid
)
5679 as_warn (_("No .frame pseudo-op used in PIC code"));
5680 /* Quiet this warning. */
5681 mips_frame_reg_valid
= 1;
5683 if (! mips_cprestore_valid
)
5685 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5686 /* Quiet this warning. */
5687 mips_cprestore_valid
= 1;
5689 if (mips_opts
.noreorder
)
5690 macro_build (NULL
, "nop", "");
5691 expr1
.X_add_number
= mips_cprestore_offset
;
5692 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5695 HAVE_64BIT_ADDRESSES
);
5699 else if (mips_pic
== VXWORKS_PIC
)
5700 as_bad (_("Non-PIC jump used in PIC library"));
5723 /* Itbl support may require additional care here. */
5728 /* Itbl support may require additional care here. */
5733 /* Itbl support may require additional care here. */
5738 /* Itbl support may require additional care here. */
5750 if (mips_opts
.arch
== CPU_R4650
)
5752 as_bad (_("opcode not supported on this processor"));
5756 /* Itbl support may require additional care here. */
5761 /* Itbl support may require additional care here. */
5766 /* Itbl support may require additional care here. */
5786 if (breg
== treg
|| coproc
|| lr
)
5807 /* Itbl support may require additional care here. */
5812 /* Itbl support may require additional care here. */
5817 /* Itbl support may require additional care here. */
5822 /* Itbl support may require additional care here. */
5841 if (mips_opts
.arch
== CPU_R4650
)
5843 as_bad (_("opcode not supported on this processor"));
5848 /* Itbl support may require additional care here. */
5852 /* Itbl support may require additional care here. */
5857 /* Itbl support may require additional care here. */
5869 /* Itbl support may require additional care here. */
5870 if (mask
== M_LWC1_AB
5871 || mask
== M_SWC1_AB
5872 || mask
== M_LDC1_AB
5873 || mask
== M_SDC1_AB
5877 else if (mask
== M_CACHE_AB
)
5884 if (offset_expr
.X_op
!= O_constant
5885 && offset_expr
.X_op
!= O_symbol
)
5887 as_bad (_("expression too complex"));
5888 offset_expr
.X_op
= O_constant
;
5891 if (HAVE_32BIT_ADDRESSES
5892 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5896 sprintf_vma (value
, offset_expr
.X_add_number
);
5897 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5900 /* A constant expression in PIC code can be handled just as it
5901 is in non PIC code. */
5902 if (offset_expr
.X_op
== O_constant
)
5904 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5905 & ~(bfd_vma
) 0xffff);
5906 normalize_address_expr (&expr1
);
5907 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5909 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5910 tempreg
, tempreg
, breg
);
5911 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5913 else if (mips_pic
== NO_PIC
)
5915 /* If this is a reference to a GP relative symbol, and there
5916 is no base register, we want
5917 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5918 Otherwise, if there is no base register, we want
5919 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5920 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5921 If we have a constant, we need two instructions anyhow,
5922 so we always use the latter form.
5924 If we have a base register, and this is a reference to a
5925 GP relative symbol, we want
5926 addu $tempreg,$breg,$gp
5927 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5929 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5930 addu $tempreg,$tempreg,$breg
5931 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5932 With a constant we always use the latter case.
5934 With 64bit address space and no base register and $at usable,
5936 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5937 lui $at,<sym> (BFD_RELOC_HI16_S)
5938 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5941 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5942 If we have a base register, we want
5943 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5944 lui $at,<sym> (BFD_RELOC_HI16_S)
5945 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5949 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5951 Without $at we can't generate the optimal path for superscalar
5952 processors here since this would require two temporary registers.
5953 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5954 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5956 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5958 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5959 If we have a base register, we want
5960 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5961 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5963 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5965 daddu $tempreg,$tempreg,$breg
5966 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5968 For GP relative symbols in 64bit address space we can use
5969 the same sequence as in 32bit address space. */
5970 if (HAVE_64BIT_SYMBOLS
)
5972 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5973 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5975 relax_start (offset_expr
.X_add_symbol
);
5978 macro_build (&offset_expr
, s
, fmt
, treg
,
5979 BFD_RELOC_GPREL16
, mips_gp_register
);
5983 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5984 tempreg
, breg
, mips_gp_register
);
5985 macro_build (&offset_expr
, s
, fmt
, treg
,
5986 BFD_RELOC_GPREL16
, tempreg
);
5991 if (used_at
== 0 && !mips_opts
.noat
)
5993 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5994 BFD_RELOC_MIPS_HIGHEST
);
5995 macro_build (&offset_expr
, "lui", "t,u", AT
,
5997 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5998 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6000 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6001 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6002 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6003 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6009 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6010 BFD_RELOC_MIPS_HIGHEST
);
6011 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6012 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6013 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6014 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6015 tempreg
, BFD_RELOC_HI16_S
);
6016 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6018 macro_build (NULL
, "daddu", "d,v,t",
6019 tempreg
, tempreg
, breg
);
6020 macro_build (&offset_expr
, s
, fmt
, treg
,
6021 BFD_RELOC_LO16
, tempreg
);
6024 if (mips_relax
.sequence
)
6031 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6032 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6034 relax_start (offset_expr
.X_add_symbol
);
6035 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6039 macro_build_lui (&offset_expr
, tempreg
);
6040 macro_build (&offset_expr
, s
, fmt
, treg
,
6041 BFD_RELOC_LO16
, tempreg
);
6042 if (mips_relax
.sequence
)
6047 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6048 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6050 relax_start (offset_expr
.X_add_symbol
);
6051 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6052 tempreg
, breg
, mips_gp_register
);
6053 macro_build (&offset_expr
, s
, fmt
, treg
,
6054 BFD_RELOC_GPREL16
, tempreg
);
6057 macro_build_lui (&offset_expr
, tempreg
);
6058 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6059 tempreg
, tempreg
, breg
);
6060 macro_build (&offset_expr
, s
, fmt
, treg
,
6061 BFD_RELOC_LO16
, tempreg
);
6062 if (mips_relax
.sequence
)
6066 else if (!mips_big_got
)
6068 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6070 /* If this is a reference to an external symbol, we want
6071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6073 <op> $treg,0($tempreg)
6075 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6077 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6078 <op> $treg,0($tempreg)
6081 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6082 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6084 If there is a base register, we add it to $tempreg before
6085 the <op>. If there is a constant, we stick it in the
6086 <op> instruction. We don't handle constants larger than
6087 16 bits, because we have no way to load the upper 16 bits
6088 (actually, we could handle them for the subset of cases
6089 in which we are not using $at). */
6090 assert (offset_expr
.X_op
== O_symbol
);
6093 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6094 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6096 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6097 tempreg
, tempreg
, breg
);
6098 macro_build (&offset_expr
, s
, fmt
, treg
,
6099 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6102 expr1
.X_add_number
= offset_expr
.X_add_number
;
6103 offset_expr
.X_add_number
= 0;
6104 if (expr1
.X_add_number
< -0x8000
6105 || expr1
.X_add_number
>= 0x8000)
6106 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6107 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6108 lw_reloc_type
, mips_gp_register
);
6110 relax_start (offset_expr
.X_add_symbol
);
6112 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6113 tempreg
, BFD_RELOC_LO16
);
6116 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6117 tempreg
, tempreg
, breg
);
6118 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6120 else if (mips_big_got
&& !HAVE_NEWABI
)
6124 /* If this is a reference to an external symbol, we want
6125 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6126 addu $tempreg,$tempreg,$gp
6127 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6128 <op> $treg,0($tempreg)
6130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6132 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6133 <op> $treg,0($tempreg)
6134 If there is a base register, we add it to $tempreg before
6135 the <op>. If there is a constant, we stick it in the
6136 <op> instruction. We don't handle constants larger than
6137 16 bits, because we have no way to load the upper 16 bits
6138 (actually, we could handle them for the subset of cases
6139 in which we are not using $at). */
6140 assert (offset_expr
.X_op
== O_symbol
);
6141 expr1
.X_add_number
= offset_expr
.X_add_number
;
6142 offset_expr
.X_add_number
= 0;
6143 if (expr1
.X_add_number
< -0x8000
6144 || expr1
.X_add_number
>= 0x8000)
6145 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6146 gpdelay
= reg_needs_delay (mips_gp_register
);
6147 relax_start (offset_expr
.X_add_symbol
);
6148 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6149 BFD_RELOC_MIPS_GOT_HI16
);
6150 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6152 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6153 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6156 macro_build (NULL
, "nop", "");
6157 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6158 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6160 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6161 tempreg
, BFD_RELOC_LO16
);
6165 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6166 tempreg
, tempreg
, breg
);
6167 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6169 else if (mips_big_got
&& HAVE_NEWABI
)
6171 /* If this is a reference to an external symbol, we want
6172 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6173 add $tempreg,$tempreg,$gp
6174 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6175 <op> $treg,<ofst>($tempreg)
6176 Otherwise, for local symbols, we want:
6177 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6178 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6179 assert (offset_expr
.X_op
== O_symbol
);
6180 expr1
.X_add_number
= offset_expr
.X_add_number
;
6181 offset_expr
.X_add_number
= 0;
6182 if (expr1
.X_add_number
< -0x8000
6183 || expr1
.X_add_number
>= 0x8000)
6184 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6185 relax_start (offset_expr
.X_add_symbol
);
6186 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6187 BFD_RELOC_MIPS_GOT_HI16
);
6188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6190 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6191 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6194 tempreg
, tempreg
, breg
);
6195 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6198 offset_expr
.X_add_number
= expr1
.X_add_number
;
6199 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6200 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6203 tempreg
, tempreg
, breg
);
6204 macro_build (&offset_expr
, s
, fmt
, treg
,
6205 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6215 load_register (treg
, &imm_expr
, 0);
6219 load_register (treg
, &imm_expr
, 1);
6223 if (imm_expr
.X_op
== O_constant
)
6226 load_register (AT
, &imm_expr
, 0);
6227 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6232 assert (offset_expr
.X_op
== O_symbol
6233 && strcmp (segment_name (S_GET_SEGMENT
6234 (offset_expr
.X_add_symbol
)),
6236 && offset_expr
.X_add_number
== 0);
6237 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6238 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6243 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6244 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6245 order 32 bits of the value and the low order 32 bits are either
6246 zero or in OFFSET_EXPR. */
6247 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6249 if (HAVE_64BIT_GPRS
)
6250 load_register (treg
, &imm_expr
, 1);
6255 if (target_big_endian
)
6267 load_register (hreg
, &imm_expr
, 0);
6270 if (offset_expr
.X_op
== O_absent
)
6271 move_register (lreg
, 0);
6274 assert (offset_expr
.X_op
== O_constant
);
6275 load_register (lreg
, &offset_expr
, 0);
6282 /* We know that sym is in the .rdata section. First we get the
6283 upper 16 bits of the address. */
6284 if (mips_pic
== NO_PIC
)
6286 macro_build_lui (&offset_expr
, AT
);
6291 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6292 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6296 /* Now we load the register(s). */
6297 if (HAVE_64BIT_GPRS
)
6300 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6305 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6308 /* FIXME: How in the world do we deal with the possible
6310 offset_expr
.X_add_number
+= 4;
6311 macro_build (&offset_expr
, "lw", "t,o(b)",
6312 treg
+ 1, BFD_RELOC_LO16
, AT
);
6318 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6319 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6320 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6321 the value and the low order 32 bits are either zero or in
6323 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6326 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6327 if (HAVE_64BIT_FPRS
)
6329 assert (HAVE_64BIT_GPRS
);
6330 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6334 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6335 if (offset_expr
.X_op
== O_absent
)
6336 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6339 assert (offset_expr
.X_op
== O_constant
);
6340 load_register (AT
, &offset_expr
, 0);
6341 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6347 assert (offset_expr
.X_op
== O_symbol
6348 && offset_expr
.X_add_number
== 0);
6349 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6350 if (strcmp (s
, ".lit8") == 0)
6352 if (mips_opts
.isa
!= ISA_MIPS1
)
6354 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6355 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6358 breg
= mips_gp_register
;
6359 r
= BFD_RELOC_MIPS_LITERAL
;
6364 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6366 if (mips_pic
!= NO_PIC
)
6367 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6368 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6371 /* FIXME: This won't work for a 64 bit address. */
6372 macro_build_lui (&offset_expr
, AT
);
6375 if (mips_opts
.isa
!= ISA_MIPS1
)
6377 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6378 treg
, BFD_RELOC_LO16
, AT
);
6387 if (mips_opts
.arch
== CPU_R4650
)
6389 as_bad (_("opcode not supported on this processor"));
6392 /* Even on a big endian machine $fn comes before $fn+1. We have
6393 to adjust when loading from memory. */
6396 assert (mips_opts
.isa
== ISA_MIPS1
);
6397 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6398 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6399 /* FIXME: A possible overflow which I don't know how to deal
6401 offset_expr
.X_add_number
+= 4;
6402 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6403 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6408 * The MIPS assembler seems to check for X_add_number not
6409 * being double aligned and generating:
6412 * addiu at,at,%lo(foo+1)
6415 * But, the resulting address is the same after relocation so why
6416 * generate the extra instruction?
6418 if (mips_opts
.arch
== CPU_R4650
)
6420 as_bad (_("opcode not supported on this processor"));
6423 /* Itbl support may require additional care here. */
6425 if (mips_opts
.isa
!= ISA_MIPS1
)
6436 if (mips_opts
.arch
== CPU_R4650
)
6438 as_bad (_("opcode not supported on this processor"));
6442 if (mips_opts
.isa
!= ISA_MIPS1
)
6450 /* Itbl support may require additional care here. */
6455 if (HAVE_64BIT_GPRS
)
6466 if (HAVE_64BIT_GPRS
)
6476 if (offset_expr
.X_op
!= O_symbol
6477 && offset_expr
.X_op
!= O_constant
)
6479 as_bad (_("expression too complex"));
6480 offset_expr
.X_op
= O_constant
;
6483 if (HAVE_32BIT_ADDRESSES
6484 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6488 sprintf_vma (value
, offset_expr
.X_add_number
);
6489 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6492 /* Even on a big endian machine $fn comes before $fn+1. We have
6493 to adjust when loading from memory. We set coproc if we must
6494 load $fn+1 first. */
6495 /* Itbl support may require additional care here. */
6496 if (! target_big_endian
)
6499 if (mips_pic
== NO_PIC
6500 || offset_expr
.X_op
== O_constant
)
6502 /* If this is a reference to a GP relative symbol, we want
6503 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6504 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6505 If we have a base register, we use this
6507 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6508 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6509 If this is not a GP relative symbol, we want
6510 lui $at,<sym> (BFD_RELOC_HI16_S)
6511 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6512 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6513 If there is a base register, we add it to $at after the
6514 lui instruction. If there is a constant, we always use
6516 if (offset_expr
.X_op
== O_symbol
6517 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6518 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6520 relax_start (offset_expr
.X_add_symbol
);
6523 tempreg
= mips_gp_register
;
6527 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6528 AT
, breg
, mips_gp_register
);
6533 /* Itbl support may require additional care here. */
6534 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6535 BFD_RELOC_GPREL16
, tempreg
);
6536 offset_expr
.X_add_number
+= 4;
6538 /* Set mips_optimize to 2 to avoid inserting an
6540 hold_mips_optimize
= mips_optimize
;
6542 /* Itbl support may require additional care here. */
6543 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6544 BFD_RELOC_GPREL16
, tempreg
);
6545 mips_optimize
= hold_mips_optimize
;
6549 /* We just generated two relocs. When tc_gen_reloc
6550 handles this case, it will skip the first reloc and
6551 handle the second. The second reloc already has an
6552 extra addend of 4, which we added above. We must
6553 subtract it out, and then subtract another 4 to make
6554 the first reloc come out right. The second reloc
6555 will come out right because we are going to add 4 to
6556 offset_expr when we build its instruction below.
6558 If we have a symbol, then we don't want to include
6559 the offset, because it will wind up being included
6560 when we generate the reloc. */
6562 if (offset_expr
.X_op
== O_constant
)
6563 offset_expr
.X_add_number
-= 8;
6566 offset_expr
.X_add_number
= -4;
6567 offset_expr
.X_op
= O_constant
;
6571 macro_build_lui (&offset_expr
, AT
);
6573 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6574 /* Itbl support may require additional care here. */
6575 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6576 BFD_RELOC_LO16
, AT
);
6577 /* FIXME: How do we handle overflow here? */
6578 offset_expr
.X_add_number
+= 4;
6579 /* Itbl support may require additional care here. */
6580 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6581 BFD_RELOC_LO16
, AT
);
6582 if (mips_relax
.sequence
)
6585 else if (!mips_big_got
)
6587 /* If this is a reference to an external symbol, we want
6588 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6593 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6595 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6596 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6597 If there is a base register we add it to $at before the
6598 lwc1 instructions. If there is a constant we include it
6599 in the lwc1 instructions. */
6601 expr1
.X_add_number
= offset_expr
.X_add_number
;
6602 if (expr1
.X_add_number
< -0x8000
6603 || expr1
.X_add_number
>= 0x8000 - 4)
6604 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6605 load_got_offset (AT
, &offset_expr
);
6608 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6610 /* Set mips_optimize to 2 to avoid inserting an undesired
6612 hold_mips_optimize
= mips_optimize
;
6615 /* Itbl support may require additional care here. */
6616 relax_start (offset_expr
.X_add_symbol
);
6617 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6618 BFD_RELOC_LO16
, AT
);
6619 expr1
.X_add_number
+= 4;
6620 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6621 BFD_RELOC_LO16
, AT
);
6623 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6624 BFD_RELOC_LO16
, AT
);
6625 offset_expr
.X_add_number
+= 4;
6626 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6627 BFD_RELOC_LO16
, AT
);
6630 mips_optimize
= hold_mips_optimize
;
6632 else if (mips_big_got
)
6636 /* If this is a reference to an external symbol, we want
6637 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6639 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6644 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6646 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6647 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6648 If there is a base register we add it to $at before the
6649 lwc1 instructions. If there is a constant we include it
6650 in the lwc1 instructions. */
6652 expr1
.X_add_number
= offset_expr
.X_add_number
;
6653 offset_expr
.X_add_number
= 0;
6654 if (expr1
.X_add_number
< -0x8000
6655 || expr1
.X_add_number
>= 0x8000 - 4)
6656 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6657 gpdelay
= reg_needs_delay (mips_gp_register
);
6658 relax_start (offset_expr
.X_add_symbol
);
6659 macro_build (&offset_expr
, "lui", "t,u",
6660 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6661 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6662 AT
, AT
, mips_gp_register
);
6663 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6664 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6668 /* Itbl support may require additional care here. */
6669 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6670 BFD_RELOC_LO16
, AT
);
6671 expr1
.X_add_number
+= 4;
6673 /* Set mips_optimize to 2 to avoid inserting an undesired
6675 hold_mips_optimize
= mips_optimize
;
6677 /* Itbl support may require additional care here. */
6678 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6679 BFD_RELOC_LO16
, AT
);
6680 mips_optimize
= hold_mips_optimize
;
6681 expr1
.X_add_number
-= 4;
6684 offset_expr
.X_add_number
= expr1
.X_add_number
;
6686 macro_build (NULL
, "nop", "");
6687 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6688 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6691 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6692 /* Itbl support may require additional care here. */
6693 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6694 BFD_RELOC_LO16
, AT
);
6695 offset_expr
.X_add_number
+= 4;
6697 /* Set mips_optimize to 2 to avoid inserting an undesired
6699 hold_mips_optimize
= mips_optimize
;
6701 /* Itbl support may require additional care here. */
6702 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6703 BFD_RELOC_LO16
, AT
);
6704 mips_optimize
= hold_mips_optimize
;
6718 assert (HAVE_32BIT_ADDRESSES
);
6719 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6720 offset_expr
.X_add_number
+= 4;
6721 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6724 /* New code added to support COPZ instructions.
6725 This code builds table entries out of the macros in mip_opcodes.
6726 R4000 uses interlocks to handle coproc delays.
6727 Other chips (like the R3000) require nops to be inserted for delays.
6729 FIXME: Currently, we require that the user handle delays.
6730 In order to fill delay slots for non-interlocked chips,
6731 we must have a way to specify delays based on the coprocessor.
6732 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6733 What are the side-effects of the cop instruction?
6734 What cache support might we have and what are its effects?
6735 Both coprocessor & memory require delays. how long???
6736 What registers are read/set/modified?
6738 If an itbl is provided to interpret cop instructions,
6739 this knowledge can be encoded in the itbl spec. */
6753 /* For now we just do C (same as Cz). The parameter will be
6754 stored in insn_opcode by mips_ip. */
6755 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6759 move_register (dreg
, sreg
);
6762 #ifdef LOSING_COMPILER
6764 /* Try and see if this is a new itbl instruction.
6765 This code builds table entries out of the macros in mip_opcodes.
6766 FIXME: For now we just assemble the expression and pass it's
6767 value along as a 32-bit immediate.
6768 We may want to have the assembler assemble this value,
6769 so that we gain the assembler's knowledge of delay slots,
6771 Would it be more efficient to use mask (id) here? */
6772 if (itbl_have_entries
6773 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6775 s
= ip
->insn_mo
->name
;
6777 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6778 macro_build (&immed_expr
, s
, "C");
6784 if (mips_opts
.noat
&& used_at
)
6785 as_bad (_("Macro used $at after \".set noat\""));
6789 macro2 (struct mips_cl_insn
*ip
)
6791 register int treg
, sreg
, dreg
, breg
;
6806 bfd_reloc_code_real_type r
;
6808 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6809 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6810 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6811 mask
= ip
->insn_mo
->mask
;
6813 expr1
.X_op
= O_constant
;
6814 expr1
.X_op_symbol
= NULL
;
6815 expr1
.X_add_symbol
= NULL
;
6816 expr1
.X_add_number
= 1;
6820 #endif /* LOSING_COMPILER */
6825 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6826 macro_build (NULL
, "mflo", "d", dreg
);
6832 /* The MIPS assembler some times generates shifts and adds. I'm
6833 not trying to be that fancy. GCC should do this for us
6836 load_register (AT
, &imm_expr
, dbl
);
6837 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6838 macro_build (NULL
, "mflo", "d", dreg
);
6854 load_register (AT
, &imm_expr
, dbl
);
6855 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6856 macro_build (NULL
, "mflo", "d", dreg
);
6857 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6858 macro_build (NULL
, "mfhi", "d", AT
);
6860 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6863 expr1
.X_add_number
= 8;
6864 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6865 macro_build (NULL
, "nop", "", 0);
6866 macro_build (NULL
, "break", "c", 6);
6869 macro_build (NULL
, "mflo", "d", dreg
);
6885 load_register (AT
, &imm_expr
, dbl
);
6886 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6887 sreg
, imm
? AT
: treg
);
6888 macro_build (NULL
, "mfhi", "d", AT
);
6889 macro_build (NULL
, "mflo", "d", dreg
);
6891 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6894 expr1
.X_add_number
= 8;
6895 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6896 macro_build (NULL
, "nop", "", 0);
6897 macro_build (NULL
, "break", "c", 6);
6903 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6914 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6915 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6919 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6920 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6921 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6922 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6926 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6937 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6938 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6942 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6943 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6944 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6945 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6953 if (imm_expr
.X_op
!= O_constant
)
6954 as_bad (_("Improper rotate count"));
6955 rot
= imm_expr
.X_add_number
& 0x3f;
6956 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6958 rot
= (64 - rot
) & 0x3f;
6960 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6962 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6967 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6970 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6971 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6974 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6975 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6976 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6984 if (imm_expr
.X_op
!= O_constant
)
6985 as_bad (_("Improper rotate count"));
6986 rot
= imm_expr
.X_add_number
& 0x1f;
6987 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6989 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6994 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6998 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6999 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7000 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7005 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7007 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7011 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7012 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7013 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7014 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7018 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7020 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7024 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7025 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7026 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7027 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7035 if (imm_expr
.X_op
!= O_constant
)
7036 as_bad (_("Improper rotate count"));
7037 rot
= imm_expr
.X_add_number
& 0x3f;
7038 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7041 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7043 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7048 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7051 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7052 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7055 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7056 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7057 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7065 if (imm_expr
.X_op
!= O_constant
)
7066 as_bad (_("Improper rotate count"));
7067 rot
= imm_expr
.X_add_number
& 0x1f;
7068 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7070 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7075 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7079 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7080 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7081 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7086 if (mips_opts
.arch
== CPU_R4650
)
7088 as_bad (_("opcode not supported on this processor"));
7091 assert (mips_opts
.isa
== ISA_MIPS1
);
7092 /* Even on a big endian machine $fn comes before $fn+1. We have
7093 to adjust when storing to memory. */
7094 macro_build (&offset_expr
, "swc1", "T,o(b)",
7095 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7096 offset_expr
.X_add_number
+= 4;
7097 macro_build (&offset_expr
, "swc1", "T,o(b)",
7098 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7103 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7105 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7108 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7109 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7114 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7116 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7121 as_warn (_("Instruction %s: result is always false"),
7123 move_register (dreg
, 0);
7126 if (imm_expr
.X_op
== O_constant
7127 && imm_expr
.X_add_number
>= 0
7128 && imm_expr
.X_add_number
< 0x10000)
7130 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7132 else if (imm_expr
.X_op
== O_constant
7133 && imm_expr
.X_add_number
> -0x8000
7134 && imm_expr
.X_add_number
< 0)
7136 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7137 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7138 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7142 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7143 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7146 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7149 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7155 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7156 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7159 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7161 if (imm_expr
.X_op
== O_constant
7162 && imm_expr
.X_add_number
>= -0x8000
7163 && imm_expr
.X_add_number
< 0x8000)
7165 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7166 dreg
, sreg
, BFD_RELOC_LO16
);
7170 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7171 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7175 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7178 case M_SGT
: /* sreg > treg <==> treg < sreg */
7184 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7187 case M_SGT_I
: /* sreg > I <==> I < sreg */
7194 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7195 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7198 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7204 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7205 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7208 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7215 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7216 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7217 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7221 if (imm_expr
.X_op
== O_constant
7222 && imm_expr
.X_add_number
>= -0x8000
7223 && imm_expr
.X_add_number
< 0x8000)
7225 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7229 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7230 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7234 if (imm_expr
.X_op
== O_constant
7235 && imm_expr
.X_add_number
>= -0x8000
7236 && imm_expr
.X_add_number
< 0x8000)
7238 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7243 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7244 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7249 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7251 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7254 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7255 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7260 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7262 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7267 as_warn (_("Instruction %s: result is always true"),
7269 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7270 dreg
, 0, BFD_RELOC_LO16
);
7273 if (imm_expr
.X_op
== O_constant
7274 && imm_expr
.X_add_number
>= 0
7275 && imm_expr
.X_add_number
< 0x10000)
7277 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7279 else if (imm_expr
.X_op
== O_constant
7280 && imm_expr
.X_add_number
> -0x8000
7281 && imm_expr
.X_add_number
< 0)
7283 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7284 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7285 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7289 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7290 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7293 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7299 if (imm_expr
.X_op
== O_constant
7300 && imm_expr
.X_add_number
> -0x8000
7301 && imm_expr
.X_add_number
<= 0x8000)
7303 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7304 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7305 dreg
, sreg
, BFD_RELOC_LO16
);
7309 load_register (AT
, &imm_expr
, dbl
);
7310 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7316 if (imm_expr
.X_op
== O_constant
7317 && imm_expr
.X_add_number
> -0x8000
7318 && imm_expr
.X_add_number
<= 0x8000)
7320 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7321 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7322 dreg
, sreg
, BFD_RELOC_LO16
);
7326 load_register (AT
, &imm_expr
, dbl
);
7327 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7349 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7350 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7355 assert (mips_opts
.isa
== ISA_MIPS1
);
7357 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7358 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7361 * Is the double cfc1 instruction a bug in the mips assembler;
7362 * or is there a reason for it?
7365 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7366 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7367 macro_build (NULL
, "nop", "");
7368 expr1
.X_add_number
= 3;
7369 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7370 expr1
.X_add_number
= 2;
7371 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7372 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7373 macro_build (NULL
, "nop", "");
7374 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7376 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7377 macro_build (NULL
, "nop", "");
7388 if (offset_expr
.X_add_number
>= 0x7fff)
7389 as_bad (_("operand overflow"));
7390 if (! target_big_endian
)
7391 ++offset_expr
.X_add_number
;
7392 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7393 if (! target_big_endian
)
7394 --offset_expr
.X_add_number
;
7396 ++offset_expr
.X_add_number
;
7397 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7398 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7399 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7412 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7413 as_bad (_("operand overflow"));
7421 if (! target_big_endian
)
7422 offset_expr
.X_add_number
+= off
;
7423 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7424 if (! target_big_endian
)
7425 offset_expr
.X_add_number
-= off
;
7427 offset_expr
.X_add_number
+= off
;
7428 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7430 /* If necessary, move the result in tempreg the final destination. */
7431 if (treg
== tempreg
)
7433 /* Protect second load's delay slot. */
7435 move_register (treg
, tempreg
);
7449 load_address (AT
, &offset_expr
, &used_at
);
7451 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7452 if (! target_big_endian
)
7453 expr1
.X_add_number
= off
;
7455 expr1
.X_add_number
= 0;
7456 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7457 if (! target_big_endian
)
7458 expr1
.X_add_number
= 0;
7460 expr1
.X_add_number
= off
;
7461 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7467 load_address (AT
, &offset_expr
, &used_at
);
7469 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7470 if (target_big_endian
)
7471 expr1
.X_add_number
= 0;
7472 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7473 treg
, BFD_RELOC_LO16
, AT
);
7474 if (target_big_endian
)
7475 expr1
.X_add_number
= 1;
7477 expr1
.X_add_number
= 0;
7478 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7479 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7480 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7485 if (offset_expr
.X_add_number
>= 0x7fff)
7486 as_bad (_("operand overflow"));
7487 if (target_big_endian
)
7488 ++offset_expr
.X_add_number
;
7489 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7490 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7491 if (target_big_endian
)
7492 --offset_expr
.X_add_number
;
7494 ++offset_expr
.X_add_number
;
7495 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7508 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7509 as_bad (_("operand overflow"));
7510 if (! target_big_endian
)
7511 offset_expr
.X_add_number
+= off
;
7512 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7513 if (! target_big_endian
)
7514 offset_expr
.X_add_number
-= off
;
7516 offset_expr
.X_add_number
+= off
;
7517 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7531 load_address (AT
, &offset_expr
, &used_at
);
7533 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7534 if (! target_big_endian
)
7535 expr1
.X_add_number
= off
;
7537 expr1
.X_add_number
= 0;
7538 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7539 if (! target_big_endian
)
7540 expr1
.X_add_number
= 0;
7542 expr1
.X_add_number
= off
;
7543 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7548 load_address (AT
, &offset_expr
, &used_at
);
7550 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7551 if (! target_big_endian
)
7552 expr1
.X_add_number
= 0;
7553 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7554 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7555 if (! target_big_endian
)
7556 expr1
.X_add_number
= 1;
7558 expr1
.X_add_number
= 0;
7559 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7560 if (! target_big_endian
)
7561 expr1
.X_add_number
= 0;
7563 expr1
.X_add_number
= 1;
7564 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7565 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7566 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7570 /* FIXME: Check if this is one of the itbl macros, since they
7571 are added dynamically. */
7572 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7575 if (mips_opts
.noat
&& used_at
)
7576 as_bad (_("Macro used $at after \".set noat\""));
7579 /* Implement macros in mips16 mode. */
7582 mips16_macro (struct mips_cl_insn
*ip
)
7585 int xreg
, yreg
, zreg
, tmp
;
7588 const char *s
, *s2
, *s3
;
7590 mask
= ip
->insn_mo
->mask
;
7592 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7593 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7594 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7596 expr1
.X_op
= O_constant
;
7597 expr1
.X_op_symbol
= NULL
;
7598 expr1
.X_add_symbol
= NULL
;
7599 expr1
.X_add_number
= 1;
7619 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7620 expr1
.X_add_number
= 2;
7621 macro_build (&expr1
, "bnez", "x,p", yreg
);
7622 macro_build (NULL
, "break", "6", 7);
7624 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7625 since that causes an overflow. We should do that as well,
7626 but I don't see how to do the comparisons without a temporary
7629 macro_build (NULL
, s
, "x", zreg
);
7649 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7650 expr1
.X_add_number
= 2;
7651 macro_build (&expr1
, "bnez", "x,p", yreg
);
7652 macro_build (NULL
, "break", "6", 7);
7654 macro_build (NULL
, s2
, "x", zreg
);
7660 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7661 macro_build (NULL
, "mflo", "x", zreg
);
7669 if (imm_expr
.X_op
!= O_constant
)
7670 as_bad (_("Unsupported large constant"));
7671 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7672 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7676 if (imm_expr
.X_op
!= O_constant
)
7677 as_bad (_("Unsupported large constant"));
7678 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7679 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7683 if (imm_expr
.X_op
!= O_constant
)
7684 as_bad (_("Unsupported large constant"));
7685 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7686 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7708 goto do_reverse_branch
;
7712 goto do_reverse_branch
;
7724 goto do_reverse_branch
;
7735 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7736 macro_build (&offset_expr
, s2
, "p");
7763 goto do_addone_branch_i
;
7768 goto do_addone_branch_i
;
7783 goto do_addone_branch_i
;
7790 if (imm_expr
.X_op
!= O_constant
)
7791 as_bad (_("Unsupported large constant"));
7792 ++imm_expr
.X_add_number
;
7795 macro_build (&imm_expr
, s
, s3
, xreg
);
7796 macro_build (&offset_expr
, s2
, "p");
7800 expr1
.X_add_number
= 0;
7801 macro_build (&expr1
, "slti", "x,8", yreg
);
7803 move_register (xreg
, yreg
);
7804 expr1
.X_add_number
= 2;
7805 macro_build (&expr1
, "bteqz", "p");
7806 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7810 /* For consistency checking, verify that all bits are specified either
7811 by the match/mask part of the instruction definition, or by the
7814 validate_mips_insn (const struct mips_opcode
*opc
)
7816 const char *p
= opc
->args
;
7818 unsigned long used_bits
= opc
->mask
;
7820 if ((used_bits
& opc
->match
) != opc
->match
)
7822 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7823 opc
->name
, opc
->args
);
7826 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7836 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
7837 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
7838 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
7839 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
7840 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7841 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7842 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7843 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7844 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7845 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7846 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7847 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7848 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7850 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7851 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
7852 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7854 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7855 c
, opc
->name
, opc
->args
);
7859 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7860 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7862 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7863 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7864 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7865 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7867 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7868 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7870 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7871 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7873 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7874 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7875 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7876 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7877 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7878 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7879 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7880 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7881 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7882 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7883 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7884 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7885 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7886 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7887 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7888 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7889 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7891 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7892 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7893 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7894 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7896 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7897 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7898 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7899 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7900 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7901 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7902 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7903 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7904 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7907 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7908 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7909 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7910 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7911 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7914 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
7915 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
7916 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
7917 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7918 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
7919 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
7920 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
7921 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
7922 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
7923 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
7924 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
7925 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
7926 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
7927 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
7928 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
7929 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7931 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7932 c
, opc
->name
, opc
->args
);
7936 if (used_bits
!= 0xffffffff)
7938 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7939 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7945 /* UDI immediates. */
7953 static const struct mips_immed mips_immed
[] = {
7954 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
7955 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
7956 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
7957 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
7961 /* This routine assembles an instruction into its binary format. As a
7962 side effect, it sets one of the global variables imm_reloc or
7963 offset_reloc to the type of relocation to do if one of the operands
7964 is an address expression. */
7967 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7972 struct mips_opcode
*insn
;
7975 unsigned int lastregno
= 0;
7976 unsigned int lastpos
= 0;
7977 unsigned int limlo
, limhi
;
7980 offsetT min_range
, max_range
;
7984 /* If the instruction contains a '.', we first try to match an instruction
7985 including the '.'. Then we try again without the '.'. */
7987 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7990 /* If we stopped on whitespace, then replace the whitespace with null for
7991 the call to hash_find. Save the character we replaced just in case we
7992 have to re-parse the instruction. */
7999 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8001 /* If we didn't find the instruction in the opcode table, try again, but
8002 this time with just the instruction up to, but not including the
8006 /* Restore the character we overwrite above (if any). */
8010 /* Scan up to the first '.' or whitespace. */
8012 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8016 /* If we did not find a '.', then we can quit now. */
8019 insn_error
= "unrecognized opcode";
8023 /* Lookup the instruction in the hash table. */
8025 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8027 insn_error
= "unrecognized opcode";
8037 assert (strcmp (insn
->name
, str
) == 0);
8039 if (OPCODE_IS_MEMBER (insn
,
8041 | (file_ase_mips16
? INSN_MIPS16
: 0)
8042 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8043 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
8044 | (mips_opts
.ase_mt
? INSN_MT
: 0)
8045 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)
8046 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
8052 if (insn
->pinfo
!= INSN_MACRO
)
8054 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8060 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8061 && strcmp (insn
->name
, insn
[1].name
) == 0)
8070 static char buf
[100];
8072 _("opcode not supported on this processor: %s (%s)"),
8073 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8074 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8083 create_insn (ip
, insn
);
8085 for (args
= insn
->args
;; ++args
)
8089 s
+= strspn (s
, " \t");
8093 case '\0': /* end of args */
8098 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8099 my_getExpression (&imm_expr
, s
);
8100 check_absolute_expr (ip
, &imm_expr
);
8101 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8103 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8104 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8105 imm_expr
.X_add_number
&= OP_MASK_SA3
;
8107 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA3
;
8108 imm_expr
.X_op
= O_absent
;
8112 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8113 my_getExpression (&imm_expr
, s
);
8114 check_absolute_expr (ip
, &imm_expr
);
8115 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8117 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8118 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8119 imm_expr
.X_add_number
&= OP_MASK_SA4
;
8121 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA4
;
8122 imm_expr
.X_op
= O_absent
;
8126 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8127 my_getExpression (&imm_expr
, s
);
8128 check_absolute_expr (ip
, &imm_expr
);
8129 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8131 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8132 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8133 imm_expr
.X_add_number
&= OP_MASK_IMM8
;
8135 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_IMM8
;
8136 imm_expr
.X_op
= O_absent
;
8140 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8141 my_getExpression (&imm_expr
, s
);
8142 check_absolute_expr (ip
, &imm_expr
);
8143 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8145 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8146 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8147 imm_expr
.X_add_number
&= OP_MASK_RS
;
8149 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RS
;
8150 imm_expr
.X_op
= O_absent
;
8154 case '7': /* four dsp accumulators in bits 11,12 */
8155 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8156 s
[3] >= '0' && s
[3] <= '3')
8160 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC
;
8164 as_bad (_("Invalid dsp acc register"));
8167 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8168 my_getExpression (&imm_expr
, s
);
8169 check_absolute_expr (ip
, &imm_expr
);
8170 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8172 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8174 (unsigned long) imm_expr
.X_add_number
);
8175 imm_expr
.X_add_number
&= OP_MASK_WRDSP
;
8177 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_WRDSP
;
8178 imm_expr
.X_op
= O_absent
;
8182 case '9': /* four dsp accumulators in bits 21,22 */
8183 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8184 s
[3] >= '0' && s
[3] <= '3')
8188 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC_S
;
8192 as_bad (_("Invalid dsp acc register"));
8195 case '0': /* dsp 6-bit signed immediate in bit 20 */
8196 my_getExpression (&imm_expr
, s
);
8197 check_absolute_expr (ip
, &imm_expr
);
8198 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8199 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8200 if (imm_expr
.X_add_number
< min_range
||
8201 imm_expr
.X_add_number
> max_range
)
8203 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8204 (long) min_range
, (long) max_range
,
8205 (long) imm_expr
.X_add_number
);
8207 imm_expr
.X_add_number
&= OP_MASK_DSPSFT
;
8208 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8210 imm_expr
.X_op
= O_absent
;
8214 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8215 my_getExpression (&imm_expr
, s
);
8216 check_absolute_expr (ip
, &imm_expr
);
8217 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8219 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8221 (unsigned long) imm_expr
.X_add_number
);
8222 imm_expr
.X_add_number
&= OP_MASK_RDDSP
;
8224 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RDDSP
;
8225 imm_expr
.X_op
= O_absent
;
8229 case ':': /* dsp 7-bit signed immediate in bit 19 */
8230 my_getExpression (&imm_expr
, s
);
8231 check_absolute_expr (ip
, &imm_expr
);
8232 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8233 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8234 if (imm_expr
.X_add_number
< min_range
||
8235 imm_expr
.X_add_number
> max_range
)
8237 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8238 (long) min_range
, (long) max_range
,
8239 (long) imm_expr
.X_add_number
);
8241 imm_expr
.X_add_number
&= OP_MASK_DSPSFT_7
;
8242 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8244 imm_expr
.X_op
= O_absent
;
8248 case '@': /* dsp 10-bit signed immediate in bit 16 */
8249 my_getExpression (&imm_expr
, s
);
8250 check_absolute_expr (ip
, &imm_expr
);
8251 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8252 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8253 if (imm_expr
.X_add_number
< min_range
||
8254 imm_expr
.X_add_number
> max_range
)
8256 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8257 (long) min_range
, (long) max_range
,
8258 (long) imm_expr
.X_add_number
);
8260 imm_expr
.X_add_number
&= OP_MASK_IMM10
;
8261 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8263 imm_expr
.X_op
= O_absent
;
8267 case '!': /* mt 1-bit unsigned immediate in bit 5 */
8268 my_getExpression (&imm_expr
, s
);
8269 check_absolute_expr (ip
, &imm_expr
);
8270 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8272 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8273 OP_MASK_MT_U
, (unsigned long) imm_expr
.X_add_number
);
8274 imm_expr
.X_add_number
&= OP_MASK_MT_U
;
8276 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_MT_U
;
8277 imm_expr
.X_op
= O_absent
;
8281 case '$': /* mt 1-bit unsigned immediate in bit 4 */
8282 my_getExpression (&imm_expr
, s
);
8283 check_absolute_expr (ip
, &imm_expr
);
8284 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8286 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8287 OP_MASK_MT_H
, (unsigned long) imm_expr
.X_add_number
);
8288 imm_expr
.X_add_number
&= OP_MASK_MT_H
;
8290 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_MT_H
;
8291 imm_expr
.X_op
= O_absent
;
8295 case '*': /* four dsp accumulators in bits 18,19 */
8296 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8297 s
[3] >= '0' && s
[3] <= '3')
8301 ip
->insn_opcode
|= regno
<< OP_SH_MTACC_T
;
8305 as_bad (_("Invalid dsp/smartmips acc register"));
8308 case '&': /* four dsp accumulators in bits 13,14 */
8309 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8310 s
[3] >= '0' && s
[3] <= '3')
8314 ip
->insn_opcode
|= regno
<< OP_SH_MTACC_D
;
8318 as_bad (_("Invalid dsp/smartmips acc register"));
8329 INSERT_OPERAND (RS
, *ip
, lastregno
);
8333 INSERT_OPERAND (RT
, *ip
, lastregno
);
8337 INSERT_OPERAND (FT
, *ip
, lastregno
);
8341 INSERT_OPERAND (FS
, *ip
, lastregno
);
8347 /* Handle optional base register.
8348 Either the base register is omitted or
8349 we must have a left paren. */
8350 /* This is dependent on the next operand specifier
8351 is a base register specification. */
8352 assert (args
[1] == 'b' || args
[1] == '5'
8353 || args
[1] == '-' || args
[1] == '4');
8357 case ')': /* these must match exactly */
8364 case '+': /* Opcode extension character. */
8367 case '1': /* UDI immediates. */
8372 const struct mips_immed
*imm
= mips_immed
;
8374 while (imm
->type
&& imm
->type
!= *args
)
8378 my_getExpression (&imm_expr
, s
);
8379 check_absolute_expr (ip
, &imm_expr
);
8380 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8382 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8383 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8384 (unsigned long) imm_expr
.X_add_number
,
8385 (unsigned long) imm_expr
.X_add_number
);
8386 imm_expr
.X_add_number
&= imm
->mask
;
8388 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8390 imm_expr
.X_op
= O_absent
;
8395 case 'A': /* ins/ext position, becomes LSB. */
8404 my_getExpression (&imm_expr
, s
);
8405 check_absolute_expr (ip
, &imm_expr
);
8406 if ((unsigned long) imm_expr
.X_add_number
< limlo
8407 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8409 as_bad (_("Improper position (%lu)"),
8410 (unsigned long) imm_expr
.X_add_number
);
8411 imm_expr
.X_add_number
= limlo
;
8413 lastpos
= imm_expr
.X_add_number
;
8414 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8415 imm_expr
.X_op
= O_absent
;
8419 case 'B': /* ins size, becomes MSB. */
8428 my_getExpression (&imm_expr
, s
);
8429 check_absolute_expr (ip
, &imm_expr
);
8430 /* Check for negative input so that small negative numbers
8431 will not succeed incorrectly. The checks against
8432 (pos+size) transitively check "size" itself,
8433 assuming that "pos" is reasonable. */
8434 if ((long) imm_expr
.X_add_number
< 0
8435 || ((unsigned long) imm_expr
.X_add_number
8437 || ((unsigned long) imm_expr
.X_add_number
8440 as_bad (_("Improper insert size (%lu, position %lu)"),
8441 (unsigned long) imm_expr
.X_add_number
,
8442 (unsigned long) lastpos
);
8443 imm_expr
.X_add_number
= limlo
- lastpos
;
8445 INSERT_OPERAND (INSMSB
, *ip
,
8446 lastpos
+ imm_expr
.X_add_number
- 1);
8447 imm_expr
.X_op
= O_absent
;
8451 case 'C': /* ext size, becomes MSBD. */
8464 my_getExpression (&imm_expr
, s
);
8465 check_absolute_expr (ip
, &imm_expr
);
8466 /* Check for negative input so that small negative numbers
8467 will not succeed incorrectly. The checks against
8468 (pos+size) transitively check "size" itself,
8469 assuming that "pos" is reasonable. */
8470 if ((long) imm_expr
.X_add_number
< 0
8471 || ((unsigned long) imm_expr
.X_add_number
8473 || ((unsigned long) imm_expr
.X_add_number
8476 as_bad (_("Improper extract size (%lu, position %lu)"),
8477 (unsigned long) imm_expr
.X_add_number
,
8478 (unsigned long) lastpos
);
8479 imm_expr
.X_add_number
= limlo
- lastpos
;
8481 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8482 imm_expr
.X_op
= O_absent
;
8487 /* +D is for disassembly only; never match. */
8491 /* "+I" is like "I", except that imm2_expr is used. */
8492 my_getExpression (&imm2_expr
, s
);
8493 if (imm2_expr
.X_op
!= O_big
8494 && imm2_expr
.X_op
!= O_constant
)
8495 insn_error
= _("absolute expression required");
8496 if (HAVE_32BIT_GPRS
)
8497 normalize_constant_expr (&imm2_expr
);
8501 case 'T': /* Coprocessor register */
8502 /* +T is for disassembly only; never match. */
8505 case 't': /* Coprocessor register number */
8506 if (s
[0] == '$' && ISDIGIT (s
[1]))
8516 while (ISDIGIT (*s
));
8518 as_bad (_("Invalid register number (%d)"), regno
);
8521 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8526 as_bad (_("Invalid coprocessor 0 register number"));
8530 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8531 *args
, insn
->name
, insn
->args
);
8532 /* Further processing is fruitless. */
8537 case '<': /* must be at least one digit */
8539 * According to the manual, if the shift amount is greater
8540 * than 31 or less than 0, then the shift amount should be
8541 * mod 32. In reality the mips assembler issues an error.
8542 * We issue a warning and mask out all but the low 5 bits.
8544 my_getExpression (&imm_expr
, s
);
8545 check_absolute_expr (ip
, &imm_expr
);
8546 if ((unsigned long) imm_expr
.X_add_number
> 31)
8547 as_warn (_("Improper shift amount (%lu)"),
8548 (unsigned long) imm_expr
.X_add_number
);
8549 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8550 imm_expr
.X_op
= O_absent
;
8554 case '>': /* shift amount minus 32 */
8555 my_getExpression (&imm_expr
, s
);
8556 check_absolute_expr (ip
, &imm_expr
);
8557 if ((unsigned long) imm_expr
.X_add_number
< 32
8558 || (unsigned long) imm_expr
.X_add_number
> 63)
8560 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8561 imm_expr
.X_op
= O_absent
;
8565 case 'k': /* cache code */
8566 case 'h': /* prefx code */
8567 my_getExpression (&imm_expr
, s
);
8568 check_absolute_expr (ip
, &imm_expr
);
8569 if ((unsigned long) imm_expr
.X_add_number
> 31)
8570 as_warn (_("Invalid value for `%s' (%lu)"),
8572 (unsigned long) imm_expr
.X_add_number
);
8574 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8576 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8577 imm_expr
.X_op
= O_absent
;
8581 case 'c': /* break code */
8582 my_getExpression (&imm_expr
, s
);
8583 check_absolute_expr (ip
, &imm_expr
);
8584 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8585 as_warn (_("Illegal break code (%lu)"),
8586 (unsigned long) imm_expr
.X_add_number
);
8587 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8588 imm_expr
.X_op
= O_absent
;
8592 case 'q': /* lower break code */
8593 my_getExpression (&imm_expr
, s
);
8594 check_absolute_expr (ip
, &imm_expr
);
8595 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8596 as_warn (_("Illegal lower break code (%lu)"),
8597 (unsigned long) imm_expr
.X_add_number
);
8598 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8599 imm_expr
.X_op
= O_absent
;
8603 case 'B': /* 20-bit syscall/break code. */
8604 my_getExpression (&imm_expr
, s
);
8605 check_absolute_expr (ip
, &imm_expr
);
8606 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8607 as_warn (_("Illegal 20-bit code (%lu)"),
8608 (unsigned long) imm_expr
.X_add_number
);
8609 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8610 imm_expr
.X_op
= O_absent
;
8614 case 'C': /* Coprocessor code */
8615 my_getExpression (&imm_expr
, s
);
8616 check_absolute_expr (ip
, &imm_expr
);
8617 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8619 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8620 (unsigned long) imm_expr
.X_add_number
);
8621 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8623 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8624 imm_expr
.X_op
= O_absent
;
8628 case 'J': /* 19-bit wait code. */
8629 my_getExpression (&imm_expr
, s
);
8630 check_absolute_expr (ip
, &imm_expr
);
8631 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8632 as_warn (_("Illegal 19-bit code (%lu)"),
8633 (unsigned long) imm_expr
.X_add_number
);
8634 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8635 imm_expr
.X_op
= O_absent
;
8639 case 'P': /* Performance register */
8640 my_getExpression (&imm_expr
, s
);
8641 check_absolute_expr (ip
, &imm_expr
);
8642 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8643 as_warn (_("Invalid performance register (%lu)"),
8644 (unsigned long) imm_expr
.X_add_number
);
8645 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8646 imm_expr
.X_op
= O_absent
;
8650 case 'b': /* base register */
8651 case 'd': /* destination register */
8652 case 's': /* source register */
8653 case 't': /* target register */
8654 case 'r': /* both target and source */
8655 case 'v': /* both dest and source */
8656 case 'w': /* both dest and target */
8657 case 'E': /* coprocessor target register */
8658 case 'G': /* coprocessor destination register */
8659 case 'K': /* 'rdhwr' destination register */
8660 case 'x': /* ignore register name */
8661 case 'z': /* must be zero register */
8662 case 'U': /* destination register (clo/clz). */
8663 case 'g': /* coprocessor destination register */
8677 while (ISDIGIT (*s
));
8679 as_bad (_("Invalid register number (%d)"), regno
);
8681 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8685 if (s
[1] == 'r' && s
[2] == 'a')
8690 else if (s
[1] == 'f' && s
[2] == 'p')
8695 else if (s
[1] == 's' && s
[2] == 'p')
8700 else if (s
[1] == 'g' && s
[2] == 'p')
8705 else if (s
[1] == 'a' && s
[2] == 't')
8710 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8715 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8720 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8725 else if (itbl_have_entries
)
8730 p
= s
+ 1; /* advance past '$' */
8731 n
= itbl_get_field (&p
); /* n is name */
8733 /* See if this is a register defined in an
8735 if (itbl_get_reg_val (n
, &r
))
8737 /* Get_field advances to the start of
8738 the next field, so we need to back
8739 rack to the end of the last field. */
8743 s
= strchr (s
, '\0');
8757 as_warn (_("Used $at without \".set noat\""));
8763 if (c
== 'r' || c
== 'v' || c
== 'w')
8770 /* 'z' only matches $0. */
8771 if (c
== 'z' && regno
!= 0)
8774 /* Now that we have assembled one operand, we use the args string
8775 * to figure out where it goes in the instruction. */
8782 INSERT_OPERAND (RS
, *ip
, regno
);
8788 INSERT_OPERAND (RD
, *ip
, regno
);
8791 INSERT_OPERAND (RD
, *ip
, regno
);
8792 INSERT_OPERAND (RT
, *ip
, regno
);
8797 INSERT_OPERAND (RT
, *ip
, regno
);
8800 /* This case exists because on the r3000 trunc
8801 expands into a macro which requires a gp
8802 register. On the r6000 or r4000 it is
8803 assembled into a single instruction which
8804 ignores the register. Thus the insn version
8805 is MIPS_ISA2 and uses 'x', and the macro
8806 version is MIPS_ISA1 and uses 't'. */
8809 /* This case is for the div instruction, which
8810 acts differently if the destination argument
8811 is $0. This only matches $0, and is checked
8812 outside the switch. */
8815 /* Itbl operand; not yet implemented. FIXME ?? */
8817 /* What about all other operands like 'i', which
8818 can be specified in the opcode table? */
8828 INSERT_OPERAND (RS
, *ip
, lastregno
);
8831 INSERT_OPERAND (RT
, *ip
, lastregno
);
8836 case 'O': /* MDMX alignment immediate constant. */
8837 my_getExpression (&imm_expr
, s
);
8838 check_absolute_expr (ip
, &imm_expr
);
8839 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8840 as_warn ("Improper align amount (%ld), using low bits",
8841 (long) imm_expr
.X_add_number
);
8842 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8843 imm_expr
.X_op
= O_absent
;
8847 case 'Q': /* MDMX vector, element sel, or const. */
8850 /* MDMX Immediate. */
8851 my_getExpression (&imm_expr
, s
);
8852 check_absolute_expr (ip
, &imm_expr
);
8853 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8854 as_warn (_("Invalid MDMX Immediate (%ld)"),
8855 (long) imm_expr
.X_add_number
);
8856 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8857 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8858 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8860 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8861 imm_expr
.X_op
= O_absent
;
8865 /* Not MDMX Immediate. Fall through. */
8866 case 'X': /* MDMX destination register. */
8867 case 'Y': /* MDMX source register. */
8868 case 'Z': /* MDMX target register. */
8870 case 'D': /* floating point destination register */
8871 case 'S': /* floating point source register */
8872 case 'T': /* floating point target register */
8873 case 'R': /* floating point source register */
8877 /* Accept $fN for FP and MDMX register numbers, and in
8878 addition accept $vN for MDMX register numbers. */
8879 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8880 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8891 while (ISDIGIT (*s
));
8894 as_bad (_("Invalid float register number (%d)"), regno
);
8896 if ((regno
& 1) != 0
8898 && ! (strcmp (str
, "mtc1") == 0
8899 || strcmp (str
, "mfc1") == 0
8900 || strcmp (str
, "lwc1") == 0
8901 || strcmp (str
, "swc1") == 0
8902 || strcmp (str
, "l.s") == 0
8903 || strcmp (str
, "s.s") == 0
8904 || strcmp (str
, "mftc1") == 0
8905 || strcmp (str
, "mfthc1") == 0
8906 || strcmp (str
, "cftc1") == 0
8907 || strcmp (str
, "mttc1") == 0
8908 || strcmp (str
, "mtthc1") == 0
8909 || strcmp (str
, "cttc1") == 0))
8910 as_warn (_("Float register should be even, was %d"),
8918 if (c
== 'V' || c
== 'W')
8929 INSERT_OPERAND (FD
, *ip
, regno
);
8934 INSERT_OPERAND (FS
, *ip
, regno
);
8937 /* This is like 'Z', but also needs to fix the MDMX
8938 vector/scalar select bits. Note that the
8939 scalar immediate case is handled above. */
8942 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8943 int max_el
= (is_qh
? 3 : 7);
8945 my_getExpression(&imm_expr
, s
);
8946 check_absolute_expr (ip
, &imm_expr
);
8948 if (imm_expr
.X_add_number
> max_el
)
8949 as_bad(_("Bad element selector %ld"),
8950 (long) imm_expr
.X_add_number
);
8951 imm_expr
.X_add_number
&= max_el
;
8952 ip
->insn_opcode
|= (imm_expr
.X_add_number
8955 imm_expr
.X_op
= O_absent
;
8957 as_warn(_("Expecting ']' found '%s'"), s
);
8963 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8964 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8967 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8974 INSERT_OPERAND (FT
, *ip
, regno
);
8977 INSERT_OPERAND (FR
, *ip
, regno
);
8987 INSERT_OPERAND (FS
, *ip
, lastregno
);
8990 INSERT_OPERAND (FT
, *ip
, lastregno
);
8996 my_getExpression (&imm_expr
, s
);
8997 if (imm_expr
.X_op
!= O_big
8998 && imm_expr
.X_op
!= O_constant
)
8999 insn_error
= _("absolute expression required");
9000 if (HAVE_32BIT_GPRS
)
9001 normalize_constant_expr (&imm_expr
);
9006 my_getExpression (&offset_expr
, s
);
9007 normalize_address_expr (&offset_expr
);
9008 *imm_reloc
= BFD_RELOC_32
;
9021 unsigned char temp
[8];
9023 unsigned int length
;
9028 /* These only appear as the last operand in an
9029 instruction, and every instruction that accepts
9030 them in any variant accepts them in all variants.
9031 This means we don't have to worry about backing out
9032 any changes if the instruction does not match.
9034 The difference between them is the size of the
9035 floating point constant and where it goes. For 'F'
9036 and 'L' the constant is 64 bits; for 'f' and 'l' it
9037 is 32 bits. Where the constant is placed is based
9038 on how the MIPS assembler does things:
9041 f -- immediate value
9044 The .lit4 and .lit8 sections are only used if
9045 permitted by the -G argument.
9047 The code below needs to know whether the target register
9048 is 32 or 64 bits wide. It relies on the fact 'f' and
9049 'F' are used with GPR-based instructions and 'l' and
9050 'L' are used with FPR-based instructions. */
9052 f64
= *args
== 'F' || *args
== 'L';
9053 using_gprs
= *args
== 'F' || *args
== 'f';
9055 save_in
= input_line_pointer
;
9056 input_line_pointer
= s
;
9057 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9059 s
= input_line_pointer
;
9060 input_line_pointer
= save_in
;
9061 if (err
!= NULL
&& *err
!= '\0')
9063 as_bad (_("Bad floating point constant: %s"), err
);
9064 memset (temp
, '\0', sizeof temp
);
9065 length
= f64
? 8 : 4;
9068 assert (length
== (unsigned) (f64
? 8 : 4));
9072 && (g_switch_value
< 4
9073 || (temp
[0] == 0 && temp
[1] == 0)
9074 || (temp
[2] == 0 && temp
[3] == 0))))
9076 imm_expr
.X_op
= O_constant
;
9077 if (! target_big_endian
)
9078 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9080 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9083 && ! mips_disable_float_construction
9084 /* Constants can only be constructed in GPRs and
9085 copied to FPRs if the GPRs are at least as wide
9086 as the FPRs. Force the constant into memory if
9087 we are using 64-bit FPRs but the GPRs are only
9090 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9091 && ((temp
[0] == 0 && temp
[1] == 0)
9092 || (temp
[2] == 0 && temp
[3] == 0))
9093 && ((temp
[4] == 0 && temp
[5] == 0)
9094 || (temp
[6] == 0 && temp
[7] == 0)))
9096 /* The value is simple enough to load with a couple of
9097 instructions. If using 32-bit registers, set
9098 imm_expr to the high order 32 bits and offset_expr to
9099 the low order 32 bits. Otherwise, set imm_expr to
9100 the entire 64 bit constant. */
9101 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9103 imm_expr
.X_op
= O_constant
;
9104 offset_expr
.X_op
= O_constant
;
9105 if (! target_big_endian
)
9107 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9108 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9112 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9113 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9115 if (offset_expr
.X_add_number
== 0)
9116 offset_expr
.X_op
= O_absent
;
9118 else if (sizeof (imm_expr
.X_add_number
) > 4)
9120 imm_expr
.X_op
= O_constant
;
9121 if (! target_big_endian
)
9122 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9124 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9128 imm_expr
.X_op
= O_big
;
9129 imm_expr
.X_add_number
= 4;
9130 if (! target_big_endian
)
9132 generic_bignum
[0] = bfd_getl16 (temp
);
9133 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9134 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9135 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9139 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9140 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9141 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9142 generic_bignum
[3] = bfd_getb16 (temp
);
9148 const char *newname
;
9151 /* Switch to the right section. */
9153 subseg
= now_subseg
;
9156 default: /* unused default case avoids warnings. */
9158 newname
= RDATA_SECTION_NAME
;
9159 if (g_switch_value
>= 8)
9163 newname
= RDATA_SECTION_NAME
;
9166 assert (g_switch_value
>= 4);
9170 new_seg
= subseg_new (newname
, (subsegT
) 0);
9171 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9172 bfd_set_section_flags (stdoutput
, new_seg
,
9177 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9178 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9179 && strcmp (TARGET_OS
, "elf") != 0)
9180 record_alignment (new_seg
, 4);
9182 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9184 as_bad (_("Can't use floating point insn in this section"));
9186 /* Set the argument to the current address in the
9188 offset_expr
.X_op
= O_symbol
;
9189 offset_expr
.X_add_symbol
=
9190 symbol_new ("L0\001", now_seg
,
9191 (valueT
) frag_now_fix (), frag_now
);
9192 offset_expr
.X_add_number
= 0;
9194 /* Put the floating point number into the section. */
9195 p
= frag_more ((int) length
);
9196 memcpy (p
, temp
, length
);
9198 /* Switch back to the original section. */
9199 subseg_set (seg
, subseg
);
9204 case 'i': /* 16 bit unsigned immediate */
9205 case 'j': /* 16 bit signed immediate */
9206 *imm_reloc
= BFD_RELOC_LO16
;
9207 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9210 offsetT minval
, maxval
;
9212 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9213 && strcmp (insn
->name
, insn
[1].name
) == 0);
9215 /* If the expression was written as an unsigned number,
9216 only treat it as signed if there are no more
9220 && sizeof (imm_expr
.X_add_number
) <= 4
9221 && imm_expr
.X_op
== O_constant
9222 && imm_expr
.X_add_number
< 0
9223 && imm_expr
.X_unsigned
9227 /* For compatibility with older assemblers, we accept
9228 0x8000-0xffff as signed 16-bit numbers when only
9229 signed numbers are allowed. */
9231 minval
= 0, maxval
= 0xffff;
9233 minval
= -0x8000, maxval
= 0x7fff;
9235 minval
= -0x8000, maxval
= 0xffff;
9237 if (imm_expr
.X_op
!= O_constant
9238 || imm_expr
.X_add_number
< minval
9239 || imm_expr
.X_add_number
> maxval
)
9243 if (imm_expr
.X_op
== O_constant
9244 || imm_expr
.X_op
== O_big
)
9245 as_bad (_("expression out of range"));
9251 case 'o': /* 16 bit offset */
9252 /* Check whether there is only a single bracketed expression
9253 left. If so, it must be the base register and the
9254 constant must be zero. */
9255 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9257 offset_expr
.X_op
= O_constant
;
9258 offset_expr
.X_add_number
= 0;
9262 /* If this value won't fit into a 16 bit offset, then go
9263 find a macro that will generate the 32 bit offset
9265 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9266 && (offset_expr
.X_op
!= O_constant
9267 || offset_expr
.X_add_number
>= 0x8000
9268 || offset_expr
.X_add_number
< -0x8000))
9274 case 'p': /* pc relative offset */
9275 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9276 my_getExpression (&offset_expr
, s
);
9280 case 'u': /* upper 16 bits */
9281 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9282 && imm_expr
.X_op
== O_constant
9283 && (imm_expr
.X_add_number
< 0
9284 || imm_expr
.X_add_number
>= 0x10000))
9285 as_bad (_("lui expression not in range 0..65535"));
9289 case 'a': /* 26 bit address */
9290 my_getExpression (&offset_expr
, s
);
9292 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9295 case 'N': /* 3 bit branch condition code */
9296 case 'M': /* 3 bit compare condition code */
9297 if (strncmp (s
, "$fcc", 4) != 0)
9307 while (ISDIGIT (*s
));
9309 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9310 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9311 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9312 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9313 && (regno
& 1) != 0)
9314 as_warn(_("Condition code register should be even for %s, was %d"),
9316 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9317 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9318 && (regno
& 3) != 0)
9319 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9322 INSERT_OPERAND (BCC
, *ip
, regno
);
9324 INSERT_OPERAND (CCC
, *ip
, regno
);
9328 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9339 while (ISDIGIT (*s
));
9342 c
= 8; /* Invalid sel value. */
9345 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9346 ip
->insn_opcode
|= c
;
9350 /* Must be at least one digit. */
9351 my_getExpression (&imm_expr
, s
);
9352 check_absolute_expr (ip
, &imm_expr
);
9354 if ((unsigned long) imm_expr
.X_add_number
9355 > (unsigned long) OP_MASK_VECBYTE
)
9357 as_bad (_("bad byte vector index (%ld)"),
9358 (long) imm_expr
.X_add_number
);
9359 imm_expr
.X_add_number
= 0;
9362 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9363 imm_expr
.X_op
= O_absent
;
9368 my_getExpression (&imm_expr
, s
);
9369 check_absolute_expr (ip
, &imm_expr
);
9371 if ((unsigned long) imm_expr
.X_add_number
9372 > (unsigned long) OP_MASK_VECALIGN
)
9374 as_bad (_("bad byte vector index (%ld)"),
9375 (long) imm_expr
.X_add_number
);
9376 imm_expr
.X_add_number
= 0;
9379 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9380 imm_expr
.X_op
= O_absent
;
9385 as_bad (_("bad char = '%c'\n"), *args
);
9390 /* Args don't match. */
9391 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9392 !strcmp (insn
->name
, insn
[1].name
))
9396 insn_error
= _("illegal operands");
9401 insn_error
= _("illegal operands");
9406 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9408 /* This routine assembles an instruction into its binary format when
9409 assembling for the mips16. As a side effect, it sets one of the
9410 global variables imm_reloc or offset_reloc to the type of
9411 relocation to do if one of the operands is an address expression.
9412 It also sets mips16_small and mips16_ext if the user explicitly
9413 requested a small or extended instruction. */
9416 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9420 struct mips_opcode
*insn
;
9423 unsigned int lastregno
= 0;
9429 mips16_small
= FALSE
;
9432 for (s
= str
; ISLOWER (*s
); ++s
)
9444 if (s
[1] == 't' && s
[2] == ' ')
9447 mips16_small
= TRUE
;
9451 else if (s
[1] == 'e' && s
[2] == ' ')
9460 insn_error
= _("unknown opcode");
9464 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9465 mips16_small
= TRUE
;
9467 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9469 insn_error
= _("unrecognized opcode");
9476 assert (strcmp (insn
->name
, str
) == 0);
9478 create_insn (ip
, insn
);
9479 imm_expr
.X_op
= O_absent
;
9480 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9481 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9482 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9483 imm2_expr
.X_op
= O_absent
;
9484 offset_expr
.X_op
= O_absent
;
9485 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9486 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9487 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9488 for (args
= insn
->args
; 1; ++args
)
9495 /* In this switch statement we call break if we did not find
9496 a match, continue if we did find a match, or return if we
9505 /* Stuff the immediate value in now, if we can. */
9506 if (imm_expr
.X_op
== O_constant
9507 && *imm_reloc
> BFD_RELOC_UNUSED
9508 && insn
->pinfo
!= INSN_MACRO
)
9512 switch (*offset_reloc
)
9514 case BFD_RELOC_MIPS16_HI16_S
:
9515 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9518 case BFD_RELOC_MIPS16_HI16
:
9519 tmp
= imm_expr
.X_add_number
>> 16;
9522 case BFD_RELOC_MIPS16_LO16
:
9523 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9527 case BFD_RELOC_UNUSED
:
9528 tmp
= imm_expr
.X_add_number
;
9534 *offset_reloc
= BFD_RELOC_UNUSED
;
9536 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9537 tmp
, TRUE
, mips16_small
,
9538 mips16_ext
, &ip
->insn_opcode
,
9539 &ip
->use_extend
, &ip
->extend
);
9540 imm_expr
.X_op
= O_absent
;
9541 *imm_reloc
= BFD_RELOC_UNUSED
;
9555 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9558 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9574 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9576 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9603 while (ISDIGIT (*s
));
9606 as_bad (_("invalid register number (%d)"), regno
);
9612 if (s
[1] == 'r' && s
[2] == 'a')
9617 else if (s
[1] == 'f' && s
[2] == 'p')
9622 else if (s
[1] == 's' && s
[2] == 'p')
9627 else if (s
[1] == 'g' && s
[2] == 'p')
9632 else if (s
[1] == 'a' && s
[2] == 't')
9637 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9642 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9647 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9660 if (c
== 'v' || c
== 'w')
9662 regno
= mips16_to_32_reg_map
[lastregno
];
9676 regno
= mips32_to_16_reg_map
[regno
];
9681 regno
= ILLEGAL_REG
;
9686 regno
= ILLEGAL_REG
;
9691 regno
= ILLEGAL_REG
;
9696 if (regno
== AT
&& ! mips_opts
.noat
)
9697 as_warn (_("used $at without \".set noat\""));
9704 if (regno
== ILLEGAL_REG
)
9711 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9715 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9718 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9721 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9727 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9730 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9731 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9741 if (strncmp (s
, "$pc", 3) == 0)
9758 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9761 if (imm_expr
.X_op
!= O_constant
)
9764 ip
->use_extend
= TRUE
;
9769 /* We need to relax this instruction. */
9770 *offset_reloc
= *imm_reloc
;
9771 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9776 *imm_reloc
= BFD_RELOC_UNUSED
;
9784 my_getExpression (&imm_expr
, s
);
9785 if (imm_expr
.X_op
== O_register
)
9787 /* What we thought was an expression turned out to
9790 if (s
[0] == '(' && args
[1] == '(')
9792 /* It looks like the expression was omitted
9793 before a register indirection, which means
9794 that the expression is implicitly zero. We
9795 still set up imm_expr, so that we handle
9796 explicit extensions correctly. */
9797 imm_expr
.X_op
= O_constant
;
9798 imm_expr
.X_add_number
= 0;
9799 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9806 /* We need to relax this instruction. */
9807 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9816 /* We use offset_reloc rather than imm_reloc for the PC
9817 relative operands. This lets macros with both
9818 immediate and address operands work correctly. */
9819 my_getExpression (&offset_expr
, s
);
9821 if (offset_expr
.X_op
== O_register
)
9824 /* We need to relax this instruction. */
9825 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9829 case '6': /* break code */
9830 my_getExpression (&imm_expr
, s
);
9831 check_absolute_expr (ip
, &imm_expr
);
9832 if ((unsigned long) imm_expr
.X_add_number
> 63)
9833 as_warn (_("Invalid value for `%s' (%lu)"),
9835 (unsigned long) imm_expr
.X_add_number
);
9836 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9837 imm_expr
.X_op
= O_absent
;
9841 case 'a': /* 26 bit address */
9842 my_getExpression (&offset_expr
, s
);
9844 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9845 ip
->insn_opcode
<<= 16;
9848 case 'l': /* register list for entry macro */
9849 case 'L': /* register list for exit macro */
9859 int freg
, reg1
, reg2
;
9861 while (*s
== ' ' || *s
== ',')
9865 as_bad (_("can't parse register list"));
9877 while (ISDIGIT (*s
))
9899 as_bad (_("invalid register list"));
9904 while (ISDIGIT (*s
))
9911 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9916 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9921 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9922 mask
|= (reg2
- 3) << 3;
9923 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9924 mask
|= (reg2
- 15) << 1;
9925 else if (reg1
== RA
&& reg2
== RA
)
9929 as_bad (_("invalid register list"));
9933 /* The mask is filled in in the opcode table for the
9934 benefit of the disassembler. We remove it before
9935 applying the actual mask. */
9936 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9937 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9941 case 'm': /* Register list for save insn. */
9942 case 'M': /* Register list for restore insn. */
9945 int framesz
= 0, seen_framesz
= 0;
9946 int args
= 0, statics
= 0, sregs
= 0;
9950 unsigned int reg1
, reg2
;
9952 SKIP_SPACE_TABS (s
);
9955 SKIP_SPACE_TABS (s
);
9957 my_getExpression (&imm_expr
, s
);
9958 if (imm_expr
.X_op
== O_constant
)
9960 /* Handle the frame size. */
9963 as_bad (_("more than one frame size in list"));
9967 framesz
= imm_expr
.X_add_number
;
9968 imm_expr
.X_op
= O_absent
;
9975 as_bad (_("can't parse register list"));
9981 while (ISDIGIT (*s
))
9987 SKIP_SPACE_TABS (s
);
9995 as_bad (_("can't parse register list"));
10000 while (ISDIGIT (*s
))
10008 while (reg1
<= reg2
)
10010 if (reg1
>= 4 && reg1
<= 7)
10012 if (c
== 'm' && !seen_framesz
)
10014 args
|= 1 << (reg1
- 4);
10016 /* statics $a0-$a3 */
10017 statics
|= 1 << (reg1
- 4);
10019 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10022 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10024 else if (reg1
== 31)
10026 /* Add $ra to insn. */
10031 as_bad (_("unexpected register in list"));
10039 /* Encode args/statics combination. */
10040 if (args
& statics
)
10041 as_bad (_("arg/static registers overlap"));
10042 else if (args
== 0xf)
10043 /* All $a0-$a3 are args. */
10044 opcode
|= MIPS16_ALL_ARGS
<< 16;
10045 else if (statics
== 0xf)
10046 /* All $a0-$a3 are statics. */
10047 opcode
|= MIPS16_ALL_STATICS
<< 16;
10050 int narg
= 0, nstat
= 0;
10052 /* Count arg registers. */
10059 as_bad (_("invalid arg register list"));
10061 /* Count static registers. */
10062 while (statics
& 0x8)
10064 statics
= (statics
<< 1) & 0xf;
10068 as_bad (_("invalid static register list"));
10070 /* Encode args/statics. */
10071 opcode
|= ((narg
<< 2) | nstat
) << 16;
10074 /* Encode $s0/$s1. */
10075 if (sregs
& (1 << 0)) /* $s0 */
10077 if (sregs
& (1 << 1)) /* $s1 */
10083 /* Count regs $s2-$s8. */
10091 as_bad (_("invalid static register list"));
10092 /* Encode $s2-$s8. */
10093 opcode
|= nsreg
<< 24;
10096 /* Encode frame size. */
10098 as_bad (_("missing frame size"));
10099 else if ((framesz
& 7) != 0 || framesz
< 0
10100 || framesz
> 0xff * 8)
10101 as_bad (_("invalid frame size"));
10102 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10105 opcode
|= (((framesz
& 0xf0) << 16)
10106 | (framesz
& 0x0f));
10109 /* Finally build the instruction. */
10110 if ((opcode
>> 16) != 0 || framesz
== 0)
10112 ip
->use_extend
= TRUE
;
10113 ip
->extend
= opcode
>> 16;
10115 ip
->insn_opcode
|= opcode
& 0x7f;
10119 case 'e': /* extend code */
10120 my_getExpression (&imm_expr
, s
);
10121 check_absolute_expr (ip
, &imm_expr
);
10122 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10124 as_warn (_("Invalid value for `%s' (%lu)"),
10126 (unsigned long) imm_expr
.X_add_number
);
10127 imm_expr
.X_add_number
&= 0x7ff;
10129 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10130 imm_expr
.X_op
= O_absent
;
10140 /* Args don't match. */
10141 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10142 strcmp (insn
->name
, insn
[1].name
) == 0)
10149 insn_error
= _("illegal operands");
10155 /* This structure holds information we know about a mips16 immediate
10158 struct mips16_immed_operand
10160 /* The type code used in the argument string in the opcode table. */
10162 /* The number of bits in the short form of the opcode. */
10164 /* The number of bits in the extended form of the opcode. */
10166 /* The amount by which the short form is shifted when it is used;
10167 for example, the sw instruction has a shift count of 2. */
10169 /* The amount by which the short form is shifted when it is stored
10170 into the instruction code. */
10172 /* Non-zero if the short form is unsigned. */
10174 /* Non-zero if the extended form is unsigned. */
10176 /* Non-zero if the value is PC relative. */
10180 /* The mips16 immediate operand types. */
10182 static const struct mips16_immed_operand mips16_immed_operands
[] =
10184 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10185 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10186 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10187 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10188 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10189 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10190 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10191 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10192 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10193 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10194 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10195 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10196 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10197 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10198 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10199 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10200 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10201 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10202 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10203 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10204 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10207 #define MIPS16_NUM_IMMED \
10208 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10210 /* Handle a mips16 instruction with an immediate value. This or's the
10211 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10212 whether an extended value is needed; if one is needed, it sets
10213 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10214 If SMALL is true, an unextended opcode was explicitly requested.
10215 If EXT is true, an extended opcode was explicitly requested. If
10216 WARN is true, warn if EXT does not match reality. */
10219 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10220 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10221 unsigned long *insn
, bfd_boolean
*use_extend
,
10222 unsigned short *extend
)
10224 register const struct mips16_immed_operand
*op
;
10225 int mintiny
, maxtiny
;
10226 bfd_boolean needext
;
10228 op
= mips16_immed_operands
;
10229 while (op
->type
!= type
)
10232 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10237 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10240 maxtiny
= 1 << op
->nbits
;
10245 maxtiny
= (1 << op
->nbits
) - 1;
10250 mintiny
= - (1 << (op
->nbits
- 1));
10251 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10254 /* Branch offsets have an implicit 0 in the lowest bit. */
10255 if (type
== 'p' || type
== 'q')
10258 if ((val
& ((1 << op
->shift
) - 1)) != 0
10259 || val
< (mintiny
<< op
->shift
)
10260 || val
> (maxtiny
<< op
->shift
))
10265 if (warn
&& ext
&& ! needext
)
10266 as_warn_where (file
, line
,
10267 _("extended operand requested but not required"));
10268 if (small
&& needext
)
10269 as_bad_where (file
, line
, _("invalid unextended operand value"));
10271 if (small
|| (! ext
&& ! needext
))
10275 *use_extend
= FALSE
;
10276 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10277 insnval
<<= op
->op_shift
;
10282 long minext
, maxext
;
10288 maxext
= (1 << op
->extbits
) - 1;
10292 minext
= - (1 << (op
->extbits
- 1));
10293 maxext
= (1 << (op
->extbits
- 1)) - 1;
10295 if (val
< minext
|| val
> maxext
)
10296 as_bad_where (file
, line
,
10297 _("operand value out of range for instruction"));
10299 *use_extend
= TRUE
;
10300 if (op
->extbits
== 16)
10302 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10305 else if (op
->extbits
== 15)
10307 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10312 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10316 *extend
= (unsigned short) extval
;
10321 struct percent_op_match
10324 bfd_reloc_code_real_type reloc
;
10327 static const struct percent_op_match mips_percent_op
[] =
10329 {"%lo", BFD_RELOC_LO16
},
10331 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10332 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10333 {"%call16", BFD_RELOC_MIPS_CALL16
},
10334 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10335 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10336 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10337 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10338 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10339 {"%got", BFD_RELOC_MIPS_GOT16
},
10340 {"%gp_rel", BFD_RELOC_GPREL16
},
10341 {"%half", BFD_RELOC_16
},
10342 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10343 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10344 {"%neg", BFD_RELOC_MIPS_SUB
},
10345 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10346 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10347 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10348 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10349 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10350 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10351 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10353 {"%hi", BFD_RELOC_HI16_S
}
10356 static const struct percent_op_match mips16_percent_op
[] =
10358 {"%lo", BFD_RELOC_MIPS16_LO16
},
10359 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10360 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10364 /* Return true if *STR points to a relocation operator. When returning true,
10365 move *STR over the operator and store its relocation code in *RELOC.
10366 Leave both *STR and *RELOC alone when returning false. */
10369 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10371 const struct percent_op_match
*percent_op
;
10374 if (mips_opts
.mips16
)
10376 percent_op
= mips16_percent_op
;
10377 limit
= ARRAY_SIZE (mips16_percent_op
);
10381 percent_op
= mips_percent_op
;
10382 limit
= ARRAY_SIZE (mips_percent_op
);
10385 for (i
= 0; i
< limit
; i
++)
10386 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10388 int len
= strlen (percent_op
[i
].str
);
10390 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10393 *str
+= strlen (percent_op
[i
].str
);
10394 *reloc
= percent_op
[i
].reloc
;
10396 /* Check whether the output BFD supports this relocation.
10397 If not, issue an error and fall back on something safe. */
10398 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10400 as_bad ("relocation %s isn't supported by the current ABI",
10401 percent_op
[i
].str
);
10402 *reloc
= BFD_RELOC_UNUSED
;
10410 /* Parse string STR as a 16-bit relocatable operand. Store the
10411 expression in *EP and the relocations in the array starting
10412 at RELOC. Return the number of relocation operators used.
10414 On exit, EXPR_END points to the first character after the expression. */
10417 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10420 bfd_reloc_code_real_type reversed_reloc
[3];
10421 size_t reloc_index
, i
;
10422 int crux_depth
, str_depth
;
10425 /* Search for the start of the main expression, recoding relocations
10426 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10427 of the main expression and with CRUX_DEPTH containing the number
10428 of open brackets at that point. */
10435 crux_depth
= str_depth
;
10437 /* Skip over whitespace and brackets, keeping count of the number
10439 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10444 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10445 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10447 my_getExpression (ep
, crux
);
10450 /* Match every open bracket. */
10451 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10455 if (crux_depth
> 0)
10456 as_bad ("unclosed '('");
10460 if (reloc_index
!= 0)
10462 prev_reloc_op_frag
= frag_now
;
10463 for (i
= 0; i
< reloc_index
; i
++)
10464 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10467 return reloc_index
;
10471 my_getExpression (expressionS
*ep
, char *str
)
10476 save_in
= input_line_pointer
;
10477 input_line_pointer
= str
;
10479 expr_end
= input_line_pointer
;
10480 input_line_pointer
= save_in
;
10482 /* If we are in mips16 mode, and this is an expression based on `.',
10483 then we bump the value of the symbol by 1 since that is how other
10484 text symbols are handled. We don't bother to handle complex
10485 expressions, just `.' plus or minus a constant. */
10486 if (mips_opts
.mips16
10487 && ep
->X_op
== O_symbol
10488 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10489 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10490 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10491 && symbol_constant_p (ep
->X_add_symbol
)
10492 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10493 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10496 /* Turn a string in input_line_pointer into a floating point constant
10497 of type TYPE, and store the appropriate bytes in *LITP. The number
10498 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10499 returned, or NULL on OK. */
10502 md_atof (int type
, char *litP
, int *sizeP
)
10505 LITTLENUM_TYPE words
[4];
10521 return _("bad call to md_atof");
10524 t
= atof_ieee (input_line_pointer
, type
, words
);
10526 input_line_pointer
= t
;
10530 if (! target_big_endian
)
10532 for (i
= prec
- 1; i
>= 0; i
--)
10534 md_number_to_chars (litP
, words
[i
], 2);
10540 for (i
= 0; i
< prec
; i
++)
10542 md_number_to_chars (litP
, words
[i
], 2);
10551 md_number_to_chars (char *buf
, valueT val
, int n
)
10553 if (target_big_endian
)
10554 number_to_chars_bigendian (buf
, val
, n
);
10556 number_to_chars_littleendian (buf
, val
, n
);
10560 static int support_64bit_objects(void)
10562 const char **list
, **l
;
10565 list
= bfd_target_list ();
10566 for (l
= list
; *l
!= NULL
; l
++)
10568 /* This is traditional mips */
10569 if (strcmp (*l
, "elf64-tradbigmips") == 0
10570 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10572 if (strcmp (*l
, "elf64-bigmips") == 0
10573 || strcmp (*l
, "elf64-littlemips") == 0)
10576 yes
= (*l
!= NULL
);
10580 #endif /* OBJ_ELF */
10582 const char *md_shortopts
= "O::g::G:";
10584 struct option md_longopts
[] =
10586 /* Options which specify architecture. */
10587 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10588 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10589 {"march", required_argument
, NULL
, OPTION_MARCH
},
10590 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10591 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10592 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10593 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10594 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10595 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10596 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10597 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10598 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10599 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10600 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10601 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10602 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10603 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10604 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10605 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10606 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10607 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10608 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10609 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10610 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10612 /* Options which specify Application Specific Extensions (ASEs). */
10613 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10614 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10615 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10616 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10617 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10618 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10619 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10620 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10621 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10622 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10623 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10624 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10625 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10626 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10627 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10628 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10629 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10630 #define OPTION_MT (OPTION_ASE_BASE + 8)
10631 {"mmt", no_argument
, NULL
, OPTION_MT
},
10632 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10633 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10634 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10635 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
10636 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10637 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
10639 /* Old-style architecture options. Don't add more of these. */
10640 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
10641 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10642 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10643 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10644 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10645 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10646 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10647 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10648 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10649 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10650 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10651 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10652 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10653 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10654 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10655 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10656 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10658 /* Options which enable bug fixes. */
10659 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10660 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10661 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10662 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10663 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10664 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10665 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10666 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10667 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10668 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10669 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10670 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10671 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10672 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10674 /* Miscellaneous options. */
10675 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10676 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10677 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10678 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10679 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10680 {"break", no_argument
, NULL
, OPTION_BREAK
},
10681 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10682 #define OPTION_EB (OPTION_MISC_BASE + 2)
10683 {"EB", no_argument
, NULL
, OPTION_EB
},
10684 #define OPTION_EL (OPTION_MISC_BASE + 3)
10685 {"EL", no_argument
, NULL
, OPTION_EL
},
10686 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10687 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10688 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10689 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10690 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10691 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10692 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10693 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10694 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10695 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10696 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10697 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10698 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10699 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10700 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10701 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10702 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10703 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10704 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10705 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10706 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10707 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10708 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10709 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10711 /* ELF-specific options. */
10713 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10714 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10715 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10716 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10717 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10718 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10719 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10720 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10721 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10722 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10723 #define OPTION_32 (OPTION_ELF_BASE + 4)
10724 {"32", no_argument
, NULL
, OPTION_32
},
10725 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10726 {"n32", no_argument
, NULL
, OPTION_N32
},
10727 #define OPTION_64 (OPTION_ELF_BASE + 6)
10728 {"64", no_argument
, NULL
, OPTION_64
},
10729 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10730 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10731 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10732 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10733 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10734 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10735 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10736 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10737 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10738 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
10739 #endif /* OBJ_ELF */
10741 {NULL
, no_argument
, NULL
, 0}
10743 size_t md_longopts_size
= sizeof (md_longopts
);
10745 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10746 NEW_VALUE. Warn if another value was already specified. Note:
10747 we have to defer parsing the -march and -mtune arguments in order
10748 to handle 'from-abi' correctly, since the ABI might be specified
10749 in a later argument. */
10752 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10754 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10755 as_warn (_("A different %s was already specified, is now %s"),
10756 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10759 *string_ptr
= new_value
;
10763 md_parse_option (int c
, char *arg
)
10767 case OPTION_CONSTRUCT_FLOATS
:
10768 mips_disable_float_construction
= 0;
10771 case OPTION_NO_CONSTRUCT_FLOATS
:
10772 mips_disable_float_construction
= 1;
10784 target_big_endian
= 1;
10788 target_big_endian
= 0;
10792 if (arg
&& arg
[1] == '0')
10802 mips_debug
= atoi (arg
);
10803 /* When the MIPS assembler sees -g or -g2, it does not do
10804 optimizations which limit full symbolic debugging. We take
10805 that to be equivalent to -O0. */
10806 if (mips_debug
== 2)
10811 file_mips_isa
= ISA_MIPS1
;
10815 file_mips_isa
= ISA_MIPS2
;
10819 file_mips_isa
= ISA_MIPS3
;
10823 file_mips_isa
= ISA_MIPS4
;
10827 file_mips_isa
= ISA_MIPS5
;
10830 case OPTION_MIPS32
:
10831 file_mips_isa
= ISA_MIPS32
;
10834 case OPTION_MIPS32R2
:
10835 file_mips_isa
= ISA_MIPS32R2
;
10838 case OPTION_MIPS64R2
:
10839 file_mips_isa
= ISA_MIPS64R2
;
10842 case OPTION_MIPS64
:
10843 file_mips_isa
= ISA_MIPS64
;
10847 mips_set_option_string (&mips_tune_string
, arg
);
10851 mips_set_option_string (&mips_arch_string
, arg
);
10855 mips_set_option_string (&mips_arch_string
, "4650");
10856 mips_set_option_string (&mips_tune_string
, "4650");
10859 case OPTION_NO_M4650
:
10863 mips_set_option_string (&mips_arch_string
, "4010");
10864 mips_set_option_string (&mips_tune_string
, "4010");
10867 case OPTION_NO_M4010
:
10871 mips_set_option_string (&mips_arch_string
, "4100");
10872 mips_set_option_string (&mips_tune_string
, "4100");
10875 case OPTION_NO_M4100
:
10879 mips_set_option_string (&mips_arch_string
, "3900");
10880 mips_set_option_string (&mips_tune_string
, "3900");
10883 case OPTION_NO_M3900
:
10887 mips_opts
.ase_mdmx
= 1;
10890 case OPTION_NO_MDMX
:
10891 mips_opts
.ase_mdmx
= 0;
10895 mips_opts
.ase_dsp
= 1;
10898 case OPTION_NO_DSP
:
10899 mips_opts
.ase_dsp
= 0;
10903 mips_opts
.ase_mt
= 1;
10907 mips_opts
.ase_mt
= 0;
10910 case OPTION_MIPS16
:
10911 mips_opts
.mips16
= 1;
10912 mips_no_prev_insn ();
10915 case OPTION_NO_MIPS16
:
10916 mips_opts
.mips16
= 0;
10917 mips_no_prev_insn ();
10920 case OPTION_MIPS3D
:
10921 mips_opts
.ase_mips3d
= 1;
10924 case OPTION_NO_MIPS3D
:
10925 mips_opts
.ase_mips3d
= 0;
10928 case OPTION_SMARTMIPS
:
10929 mips_opts
.ase_smartmips
= 1;
10932 case OPTION_NO_SMARTMIPS
:
10933 mips_opts
.ase_smartmips
= 0;
10936 case OPTION_FIX_VR4120
:
10937 mips_fix_vr4120
= 1;
10940 case OPTION_NO_FIX_VR4120
:
10941 mips_fix_vr4120
= 0;
10944 case OPTION_FIX_VR4130
:
10945 mips_fix_vr4130
= 1;
10948 case OPTION_NO_FIX_VR4130
:
10949 mips_fix_vr4130
= 0;
10952 case OPTION_RELAX_BRANCH
:
10953 mips_relax_branch
= 1;
10956 case OPTION_NO_RELAX_BRANCH
:
10957 mips_relax_branch
= 0;
10960 case OPTION_MSHARED
:
10961 mips_in_shared
= TRUE
;
10964 case OPTION_MNO_SHARED
:
10965 mips_in_shared
= FALSE
;
10968 case OPTION_MSYM32
:
10969 mips_opts
.sym32
= TRUE
;
10972 case OPTION_MNO_SYM32
:
10973 mips_opts
.sym32
= FALSE
;
10977 /* When generating ELF code, we permit -KPIC and -call_shared to
10978 select SVR4_PIC, and -non_shared to select no PIC. This is
10979 intended to be compatible with Irix 5. */
10980 case OPTION_CALL_SHARED
:
10981 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10983 as_bad (_("-call_shared is supported only for ELF format"));
10986 mips_pic
= SVR4_PIC
;
10987 mips_abicalls
= TRUE
;
10990 case OPTION_NON_SHARED
:
10991 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10993 as_bad (_("-non_shared is supported only for ELF format"));
10997 mips_abicalls
= FALSE
;
11000 /* The -xgot option tells the assembler to use 32 bit offsets
11001 when accessing the got in SVR4_PIC mode. It is for Irix
11006 #endif /* OBJ_ELF */
11009 g_switch_value
= atoi (arg
);
11014 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11017 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11019 as_bad (_("-32 is supported for ELF format only"));
11022 mips_abi
= O32_ABI
;
11026 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11028 as_bad (_("-n32 is supported for ELF format only"));
11031 mips_abi
= N32_ABI
;
11035 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11037 as_bad (_("-64 is supported for ELF format only"));
11040 mips_abi
= N64_ABI
;
11041 if (! support_64bit_objects())
11042 as_fatal (_("No compiled in support for 64 bit object file format"));
11044 #endif /* OBJ_ELF */
11047 file_mips_gp32
= 1;
11051 file_mips_gp32
= 0;
11055 file_mips_fp32
= 1;
11059 file_mips_fp32
= 0;
11064 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11066 as_bad (_("-mabi is supported for ELF format only"));
11069 if (strcmp (arg
, "32") == 0)
11070 mips_abi
= O32_ABI
;
11071 else if (strcmp (arg
, "o64") == 0)
11072 mips_abi
= O64_ABI
;
11073 else if (strcmp (arg
, "n32") == 0)
11074 mips_abi
= N32_ABI
;
11075 else if (strcmp (arg
, "64") == 0)
11077 mips_abi
= N64_ABI
;
11078 if (! support_64bit_objects())
11079 as_fatal (_("No compiled in support for 64 bit object file "
11082 else if (strcmp (arg
, "eabi") == 0)
11083 mips_abi
= EABI_ABI
;
11086 as_fatal (_("invalid abi -mabi=%s"), arg
);
11090 #endif /* OBJ_ELF */
11092 case OPTION_M7000_HILO_FIX
:
11093 mips_7000_hilo_fix
= TRUE
;
11096 case OPTION_MNO_7000_HILO_FIX
:
11097 mips_7000_hilo_fix
= FALSE
;
11101 case OPTION_MDEBUG
:
11102 mips_flag_mdebug
= TRUE
;
11105 case OPTION_NO_MDEBUG
:
11106 mips_flag_mdebug
= FALSE
;
11110 mips_flag_pdr
= TRUE
;
11113 case OPTION_NO_PDR
:
11114 mips_flag_pdr
= FALSE
;
11117 case OPTION_MVXWORKS_PIC
:
11118 mips_pic
= VXWORKS_PIC
;
11120 #endif /* OBJ_ELF */
11129 /* Set up globals to generate code for the ISA or processor
11130 described by INFO. */
11133 mips_set_architecture (const struct mips_cpu_info
*info
)
11137 file_mips_arch
= info
->cpu
;
11138 mips_opts
.arch
= info
->cpu
;
11139 mips_opts
.isa
= info
->isa
;
11144 /* Likewise for tuning. */
11147 mips_set_tune (const struct mips_cpu_info
*info
)
11150 mips_tune
= info
->cpu
;
11155 mips_after_parse_args (void)
11157 const struct mips_cpu_info
*arch_info
= 0;
11158 const struct mips_cpu_info
*tune_info
= 0;
11160 /* GP relative stuff not working for PE */
11161 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11163 if (g_switch_seen
&& g_switch_value
!= 0)
11164 as_bad (_("-G not supported in this configuration."));
11165 g_switch_value
= 0;
11168 if (mips_abi
== NO_ABI
)
11169 mips_abi
= MIPS_DEFAULT_ABI
;
11171 /* The following code determines the architecture and register size.
11172 Similar code was added to GCC 3.3 (see override_options() in
11173 config/mips/mips.c). The GAS and GCC code should be kept in sync
11174 as much as possible. */
11176 if (mips_arch_string
!= 0)
11177 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11179 if (file_mips_isa
!= ISA_UNKNOWN
)
11181 /* Handle -mipsN. At this point, file_mips_isa contains the
11182 ISA level specified by -mipsN, while arch_info->isa contains
11183 the -march selection (if any). */
11184 if (arch_info
!= 0)
11186 /* -march takes precedence over -mipsN, since it is more descriptive.
11187 There's no harm in specifying both as long as the ISA levels
11189 if (file_mips_isa
!= arch_info
->isa
)
11190 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11191 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11192 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11195 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11198 if (arch_info
== 0)
11199 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11201 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11202 as_bad ("-march=%s is not compatible with the selected ABI",
11205 mips_set_architecture (arch_info
);
11207 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11208 if (mips_tune_string
!= 0)
11209 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11211 if (tune_info
== 0)
11212 mips_set_tune (arch_info
);
11214 mips_set_tune (tune_info
);
11216 if (file_mips_gp32
>= 0)
11218 /* The user specified the size of the integer registers. Make sure
11219 it agrees with the ABI and ISA. */
11220 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11221 as_bad (_("-mgp64 used with a 32-bit processor"));
11222 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11223 as_bad (_("-mgp32 used with a 64-bit ABI"));
11224 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11225 as_bad (_("-mgp64 used with a 32-bit ABI"));
11229 /* Infer the integer register size from the ABI and processor.
11230 Restrict ourselves to 32-bit registers if that's all the
11231 processor has, or if the ABI cannot handle 64-bit registers. */
11232 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11233 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11236 /* ??? GAS treats single-float processors as though they had 64-bit
11237 float registers (although it complains when double-precision
11238 instructions are used). As things stand, saying they have 32-bit
11239 registers would lead to spurious "register must be even" messages.
11240 So here we assume float registers are always the same size as
11241 integer ones, unless the user says otherwise. */
11242 if (file_mips_fp32
< 0)
11243 file_mips_fp32
= file_mips_gp32
;
11245 /* End of GCC-shared inference code. */
11247 /* This flag is set when we have a 64-bit capable CPU but use only
11248 32-bit wide registers. Note that EABI does not use it. */
11249 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11250 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11251 || mips_abi
== O32_ABI
))
11252 mips_32bitmode
= 1;
11254 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11255 as_bad (_("trap exception not supported at ISA 1"));
11257 /* If the selected architecture includes support for ASEs, enable
11258 generation of code for them. */
11259 if (mips_opts
.mips16
== -1)
11260 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11261 if (mips_opts
.ase_mips3d
== -1)
11262 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
11263 if (mips_opts
.ase_mdmx
== -1)
11264 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
11265 if (mips_opts
.ase_dsp
== -1)
11266 mips_opts
.ase_dsp
= (CPU_HAS_DSP (file_mips_arch
)) ? 1 : 0;
11267 if (mips_opts
.ase_mt
== -1)
11268 mips_opts
.ase_mt
= (CPU_HAS_MT (file_mips_arch
)) ? 1 : 0;
11270 file_mips_isa
= mips_opts
.isa
;
11271 file_ase_mips16
= mips_opts
.mips16
;
11272 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11273 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11274 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11275 file_ase_dsp
= mips_opts
.ase_dsp
;
11276 file_ase_mt
= mips_opts
.ase_mt
;
11277 mips_opts
.gp32
= file_mips_gp32
;
11278 mips_opts
.fp32
= file_mips_fp32
;
11280 if (mips_flag_mdebug
< 0)
11282 #ifdef OBJ_MAYBE_ECOFF
11283 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11284 mips_flag_mdebug
= 1;
11286 #endif /* OBJ_MAYBE_ECOFF */
11287 mips_flag_mdebug
= 0;
11292 mips_init_after_args (void)
11294 /* initialize opcodes */
11295 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11296 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11300 md_pcrel_from (fixS
*fixP
)
11302 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11303 switch (fixP
->fx_r_type
)
11305 case BFD_RELOC_16_PCREL_S2
:
11306 case BFD_RELOC_MIPS_JMP
:
11307 /* Return the address of the delay slot. */
11314 /* This is called before the symbol table is processed. In order to
11315 work with gcc when using mips-tfile, we must keep all local labels.
11316 However, in other cases, we want to discard them. If we were
11317 called with -g, but we didn't see any debugging information, it may
11318 mean that gcc is smuggling debugging information through to
11319 mips-tfile, in which case we must generate all local labels. */
11322 mips_frob_file_before_adjust (void)
11324 #ifndef NO_ECOFF_DEBUGGING
11325 if (ECOFF_DEBUGGING
11327 && ! ecoff_debugging_seen
)
11328 flag_keep_locals
= 1;
11332 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11333 the corresponding LO16 reloc. This is called before md_apply_fix and
11334 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11335 relocation operators.
11337 For our purposes, a %lo() expression matches a %got() or %hi()
11340 (a) it refers to the same symbol; and
11341 (b) the offset applied in the %lo() expression is no lower than
11342 the offset applied in the %got() or %hi().
11344 (b) allows us to cope with code like:
11347 lh $4,%lo(foo+2)($4)
11349 ...which is legal on RELA targets, and has a well-defined behaviour
11350 if the user knows that adding 2 to "foo" will not induce a carry to
11353 When several %lo()s match a particular %got() or %hi(), we use the
11354 following rules to distinguish them:
11356 (1) %lo()s with smaller offsets are a better match than %lo()s with
11359 (2) %lo()s with no matching %got() or %hi() are better than those
11360 that already have a matching %got() or %hi().
11362 (3) later %lo()s are better than earlier %lo()s.
11364 These rules are applied in order.
11366 (1) means, among other things, that %lo()s with identical offsets are
11367 chosen if they exist.
11369 (2) means that we won't associate several high-part relocations with
11370 the same low-part relocation unless there's no alternative. Having
11371 several high parts for the same low part is a GNU extension; this rule
11372 allows careful users to avoid it.
11374 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11375 with the last high-part relocation being at the front of the list.
11376 It therefore makes sense to choose the last matching low-part
11377 relocation, all other things being equal. It's also easier
11378 to code that way. */
11381 mips_frob_file (void)
11383 struct mips_hi_fixup
*l
;
11385 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11387 segment_info_type
*seginfo
;
11388 bfd_boolean matched_lo_p
;
11389 fixS
**hi_pos
, **lo_pos
, **pos
;
11391 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11393 /* If a GOT16 relocation turns out to be against a global symbol,
11394 there isn't supposed to be a matching LO. */
11395 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11396 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11399 /* Check quickly whether the next fixup happens to be a matching %lo. */
11400 if (fixup_has_matching_lo_p (l
->fixp
))
11403 seginfo
= seg_info (l
->seg
);
11405 /* Set HI_POS to the position of this relocation in the chain.
11406 Set LO_POS to the position of the chosen low-part relocation.
11407 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11408 relocation that matches an immediately-preceding high-part
11412 matched_lo_p
= FALSE
;
11413 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11415 if (*pos
== l
->fixp
)
11418 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11419 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11420 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11421 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11423 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11425 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11428 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11429 && fixup_has_matching_lo_p (*pos
));
11432 /* If we found a match, remove the high-part relocation from its
11433 current position and insert it before the low-part relocation.
11434 Make the offsets match so that fixup_has_matching_lo_p()
11437 We don't warn about unmatched high-part relocations since some
11438 versions of gcc have been known to emit dead "lui ...%hi(...)"
11440 if (lo_pos
!= NULL
)
11442 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11443 if (l
->fixp
->fx_next
!= *lo_pos
)
11445 *hi_pos
= l
->fixp
->fx_next
;
11446 l
->fixp
->fx_next
= *lo_pos
;
11453 /* We may have combined relocations without symbols in the N32/N64 ABI.
11454 We have to prevent gas from dropping them. */
11457 mips_force_relocation (fixS
*fixp
)
11459 if (generic_force_reloc (fixp
))
11463 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11464 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11465 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11466 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11472 /* Apply a fixup to the object file. */
11475 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11479 reloc_howto_type
*howto
;
11481 /* We ignore generic BFD relocations we don't know about. */
11482 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11486 assert (fixP
->fx_size
== 4
11487 || fixP
->fx_r_type
== BFD_RELOC_16
11488 || fixP
->fx_r_type
== BFD_RELOC_64
11489 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11490 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11491 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11492 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11494 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11496 assert (! fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
11498 /* Don't treat parts of a composite relocation as done. There are two
11501 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11502 should nevertheless be emitted if the first part is.
11504 (2) In normal usage, composite relocations are never assembly-time
11505 constants. The easiest way of dealing with the pathological
11506 exceptions is to generate a relocation against STN_UNDEF and
11507 leave everything up to the linker. */
11508 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
11511 switch (fixP
->fx_r_type
)
11513 case BFD_RELOC_MIPS_TLS_GD
:
11514 case BFD_RELOC_MIPS_TLS_LDM
:
11515 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11516 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11517 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11518 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11519 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11520 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11523 case BFD_RELOC_MIPS_JMP
:
11524 case BFD_RELOC_MIPS_SHIFT5
:
11525 case BFD_RELOC_MIPS_SHIFT6
:
11526 case BFD_RELOC_MIPS_GOT_DISP
:
11527 case BFD_RELOC_MIPS_GOT_PAGE
:
11528 case BFD_RELOC_MIPS_GOT_OFST
:
11529 case BFD_RELOC_MIPS_SUB
:
11530 case BFD_RELOC_MIPS_INSERT_A
:
11531 case BFD_RELOC_MIPS_INSERT_B
:
11532 case BFD_RELOC_MIPS_DELETE
:
11533 case BFD_RELOC_MIPS_HIGHEST
:
11534 case BFD_RELOC_MIPS_HIGHER
:
11535 case BFD_RELOC_MIPS_SCN_DISP
:
11536 case BFD_RELOC_MIPS_REL16
:
11537 case BFD_RELOC_MIPS_RELGOT
:
11538 case BFD_RELOC_MIPS_JALR
:
11539 case BFD_RELOC_HI16
:
11540 case BFD_RELOC_HI16_S
:
11541 case BFD_RELOC_GPREL16
:
11542 case BFD_RELOC_MIPS_LITERAL
:
11543 case BFD_RELOC_MIPS_CALL16
:
11544 case BFD_RELOC_MIPS_GOT16
:
11545 case BFD_RELOC_GPREL32
:
11546 case BFD_RELOC_MIPS_GOT_HI16
:
11547 case BFD_RELOC_MIPS_GOT_LO16
:
11548 case BFD_RELOC_MIPS_CALL_HI16
:
11549 case BFD_RELOC_MIPS_CALL_LO16
:
11550 case BFD_RELOC_MIPS16_GPREL
:
11551 case BFD_RELOC_MIPS16_HI16
:
11552 case BFD_RELOC_MIPS16_HI16_S
:
11553 /* Nothing needed to do. The value comes from the reloc entry */
11556 case BFD_RELOC_MIPS16_JMP
:
11557 /* We currently always generate a reloc against a symbol, which
11558 means that we don't want an addend even if the symbol is
11564 /* This is handled like BFD_RELOC_32, but we output a sign
11565 extended value if we are only 32 bits. */
11568 if (8 <= sizeof (valueT
))
11569 md_number_to_chars ((char *) buf
, *valP
, 8);
11574 if ((*valP
& 0x80000000) != 0)
11578 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11580 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11586 case BFD_RELOC_RVA
:
11588 /* If we are deleting this reloc entry, we must fill in the
11589 value now. This can happen if we have a .word which is not
11590 resolved when it appears but is later defined. */
11592 md_number_to_chars ((char *) buf
, *valP
, 4);
11596 /* If we are deleting this reloc entry, we must fill in the
11599 md_number_to_chars ((char *) buf
, *valP
, 2);
11602 case BFD_RELOC_LO16
:
11603 case BFD_RELOC_MIPS16_LO16
:
11604 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11605 may be safe to remove, but if so it's not obvious. */
11606 /* When handling an embedded PIC switch statement, we can wind
11607 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11610 if (*valP
+ 0x8000 > 0xffff)
11611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11612 _("relocation overflow"));
11613 if (target_big_endian
)
11615 md_number_to_chars ((char *) buf
, *valP
, 2);
11619 case BFD_RELOC_16_PCREL_S2
:
11620 if ((*valP
& 0x3) != 0)
11621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11622 _("Branch to misaligned address (%lx)"), (long) *valP
);
11625 * We need to save the bits in the instruction since fixup_segment()
11626 * might be deleting the relocation entry (i.e., a branch within
11627 * the current segment).
11629 if (! fixP
->fx_done
)
11632 /* update old instruction data */
11633 if (target_big_endian
)
11634 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11636 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11638 if (*valP
+ 0x20000 <= 0x3ffff)
11640 insn
|= (*valP
>> 2) & 0xffff;
11641 md_number_to_chars ((char *) buf
, insn
, 4);
11643 else if (mips_pic
== NO_PIC
11645 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11646 && (fixP
->fx_frag
->fr_address
11647 < text_section
->vma
+ bfd_get_section_size (text_section
))
11648 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11649 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11650 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11652 /* The branch offset is too large. If this is an
11653 unconditional branch, and we are not generating PIC code,
11654 we can convert it to an absolute jump instruction. */
11655 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11656 insn
= 0x0c000000; /* jal */
11658 insn
= 0x08000000; /* j */
11659 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11661 fixP
->fx_addsy
= section_symbol (text_section
);
11662 *valP
+= md_pcrel_from (fixP
);
11663 md_number_to_chars ((char *) buf
, insn
, 4);
11667 /* If we got here, we have branch-relaxation disabled,
11668 and there's nothing we can do to fix this instruction
11669 without turning it into a longer sequence. */
11670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11671 _("Branch out of range"));
11675 case BFD_RELOC_VTABLE_INHERIT
:
11678 && !S_IS_DEFINED (fixP
->fx_addsy
)
11679 && !S_IS_WEAK (fixP
->fx_addsy
))
11680 S_SET_WEAK (fixP
->fx_addsy
);
11683 case BFD_RELOC_VTABLE_ENTRY
:
11691 /* Remember value for tc_gen_reloc. */
11692 fixP
->fx_addnumber
= *valP
;
11702 name
= input_line_pointer
;
11703 c
= get_symbol_end ();
11704 p
= (symbolS
*) symbol_find_or_make (name
);
11705 *input_line_pointer
= c
;
11709 /* Align the current frag to a given power of two. The MIPS assembler
11710 also automatically adjusts any preceding label. */
11713 mips_align (int to
, int fill
, symbolS
*label
)
11715 mips_emit_delays ();
11716 frag_align (to
, fill
, 0);
11717 record_alignment (now_seg
, to
);
11720 assert (S_GET_SEGMENT (label
) == now_seg
);
11721 symbol_set_frag (label
, frag_now
);
11722 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11726 /* Align to a given power of two. .align 0 turns off the automatic
11727 alignment used by the data creating pseudo-ops. */
11730 s_align (int x ATTRIBUTE_UNUSED
)
11733 register long temp_fill
;
11734 long max_alignment
= 15;
11738 o Note that the assembler pulls down any immediately preceding label
11739 to the aligned address.
11740 o It's not documented but auto alignment is reinstated by
11741 a .align pseudo instruction.
11742 o Note also that after auto alignment is turned off the mips assembler
11743 issues an error on attempt to assemble an improperly aligned data item.
11748 temp
= get_absolute_expression ();
11749 if (temp
> max_alignment
)
11750 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11753 as_warn (_("Alignment negative: 0 assumed."));
11756 if (*input_line_pointer
== ',')
11758 ++input_line_pointer
;
11759 temp_fill
= get_absolute_expression ();
11766 mips_align (temp
, (int) temp_fill
,
11767 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11774 demand_empty_rest_of_line ();
11778 s_change_sec (int sec
)
11783 /* The ELF backend needs to know that we are changing sections, so
11784 that .previous works correctly. We could do something like check
11785 for an obj_section_change_hook macro, but that might be confusing
11786 as it would not be appropriate to use it in the section changing
11787 functions in read.c, since obj-elf.c intercepts those. FIXME:
11788 This should be cleaner, somehow. */
11789 obj_elf_section_change_hook ();
11792 mips_emit_delays ();
11802 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11803 demand_empty_rest_of_line ();
11807 seg
= subseg_new (RDATA_SECTION_NAME
,
11808 (subsegT
) get_absolute_expression ());
11809 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11811 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11812 | SEC_READONLY
| SEC_RELOC
11814 if (strcmp (TARGET_OS
, "elf") != 0)
11815 record_alignment (seg
, 4);
11817 demand_empty_rest_of_line ();
11821 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11822 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11824 bfd_set_section_flags (stdoutput
, seg
,
11825 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11826 if (strcmp (TARGET_OS
, "elf") != 0)
11827 record_alignment (seg
, 4);
11829 demand_empty_rest_of_line ();
11837 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11840 char *section_name
;
11845 int section_entry_size
;
11846 int section_alignment
;
11848 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11851 section_name
= input_line_pointer
;
11852 c
= get_symbol_end ();
11854 next_c
= *(input_line_pointer
+ 1);
11856 /* Do we have .section Name<,"flags">? */
11857 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11859 /* just after name is now '\0'. */
11860 *input_line_pointer
= c
;
11861 input_line_pointer
= section_name
;
11862 obj_elf_section (ignore
);
11865 input_line_pointer
++;
11867 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11869 section_type
= get_absolute_expression ();
11872 if (*input_line_pointer
++ == ',')
11873 section_flag
= get_absolute_expression ();
11876 if (*input_line_pointer
++ == ',')
11877 section_entry_size
= get_absolute_expression ();
11879 section_entry_size
= 0;
11880 if (*input_line_pointer
++ == ',')
11881 section_alignment
= get_absolute_expression ();
11883 section_alignment
= 0;
11885 section_name
= xstrdup (section_name
);
11887 /* When using the generic form of .section (as implemented by obj-elf.c),
11888 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11889 traditionally had to fall back on the more common @progbits instead.
11891 There's nothing really harmful in this, since bfd will correct
11892 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11893 means that, for backwards compatibility, the special_section entries
11894 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11896 Even so, we shouldn't force users of the MIPS .section syntax to
11897 incorrectly label the sections as SHT_PROGBITS. The best compromise
11898 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11899 generic type-checking code. */
11900 if (section_type
== SHT_MIPS_DWARF
)
11901 section_type
= SHT_PROGBITS
;
11903 obj_elf_change_section (section_name
, section_type
, section_flag
,
11904 section_entry_size
, 0, 0, 0);
11906 if (now_seg
->name
!= section_name
)
11907 free (section_name
);
11908 #endif /* OBJ_ELF */
11912 mips_enable_auto_align (void)
11918 s_cons (int log_size
)
11922 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11923 mips_emit_delays ();
11924 if (log_size
> 0 && auto_align
)
11925 mips_align (log_size
, 0, label
);
11926 mips_clear_insn_labels ();
11927 cons (1 << log_size
);
11931 s_float_cons (int type
)
11935 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11937 mips_emit_delays ();
11942 mips_align (3, 0, label
);
11944 mips_align (2, 0, label
);
11947 mips_clear_insn_labels ();
11952 /* Handle .globl. We need to override it because on Irix 5 you are
11955 where foo is an undefined symbol, to mean that foo should be
11956 considered to be the address of a function. */
11959 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11968 name
= input_line_pointer
;
11969 c
= get_symbol_end ();
11970 symbolP
= symbol_find_or_make (name
);
11971 S_SET_EXTERNAL (symbolP
);
11973 *input_line_pointer
= c
;
11974 SKIP_WHITESPACE ();
11976 /* On Irix 5, every global symbol that is not explicitly labelled as
11977 being a function is apparently labelled as being an object. */
11980 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
11981 && (*input_line_pointer
!= ','))
11986 secname
= input_line_pointer
;
11987 c
= get_symbol_end ();
11988 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11990 as_bad (_("%s: no such section"), secname
);
11991 *input_line_pointer
= c
;
11993 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11994 flag
= BSF_FUNCTION
;
11997 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11999 c
= *input_line_pointer
;
12002 input_line_pointer
++;
12003 SKIP_WHITESPACE ();
12004 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12010 demand_empty_rest_of_line ();
12014 s_option (int x ATTRIBUTE_UNUSED
)
12019 opt
= input_line_pointer
;
12020 c
= get_symbol_end ();
12024 /* FIXME: What does this mean? */
12026 else if (strncmp (opt
, "pic", 3) == 0)
12030 i
= atoi (opt
+ 3);
12035 mips_pic
= SVR4_PIC
;
12036 mips_abicalls
= TRUE
;
12039 as_bad (_(".option pic%d not supported"), i
);
12041 if (mips_pic
== SVR4_PIC
)
12043 if (g_switch_seen
&& g_switch_value
!= 0)
12044 as_warn (_("-G may not be used with SVR4 PIC code"));
12045 g_switch_value
= 0;
12046 bfd_set_gp_size (stdoutput
, 0);
12050 as_warn (_("Unrecognized option \"%s\""), opt
);
12052 *input_line_pointer
= c
;
12053 demand_empty_rest_of_line ();
12056 /* This structure is used to hold a stack of .set values. */
12058 struct mips_option_stack
12060 struct mips_option_stack
*next
;
12061 struct mips_set_options options
;
12064 static struct mips_option_stack
*mips_opts_stack
;
12066 /* Handle the .set pseudo-op. */
12069 s_mipsset (int x ATTRIBUTE_UNUSED
)
12071 char *name
= input_line_pointer
, ch
;
12073 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12074 ++input_line_pointer
;
12075 ch
= *input_line_pointer
;
12076 *input_line_pointer
= '\0';
12078 if (strcmp (name
, "reorder") == 0)
12080 if (mips_opts
.noreorder
)
12083 else if (strcmp (name
, "noreorder") == 0)
12085 if (!mips_opts
.noreorder
)
12086 start_noreorder ();
12088 else if (strcmp (name
, "at") == 0)
12090 mips_opts
.noat
= 0;
12092 else if (strcmp (name
, "noat") == 0)
12094 mips_opts
.noat
= 1;
12096 else if (strcmp (name
, "macro") == 0)
12098 mips_opts
.warn_about_macros
= 0;
12100 else if (strcmp (name
, "nomacro") == 0)
12102 if (mips_opts
.noreorder
== 0)
12103 as_bad (_("`noreorder' must be set before `nomacro'"));
12104 mips_opts
.warn_about_macros
= 1;
12106 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12108 mips_opts
.nomove
= 0;
12110 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12112 mips_opts
.nomove
= 1;
12114 else if (strcmp (name
, "bopt") == 0)
12116 mips_opts
.nobopt
= 0;
12118 else if (strcmp (name
, "nobopt") == 0)
12120 mips_opts
.nobopt
= 1;
12122 else if (strcmp (name
, "mips16") == 0
12123 || strcmp (name
, "MIPS-16") == 0)
12124 mips_opts
.mips16
= 1;
12125 else if (strcmp (name
, "nomips16") == 0
12126 || strcmp (name
, "noMIPS-16") == 0)
12127 mips_opts
.mips16
= 0;
12128 else if (strcmp (name
, "smartmips") == 0)
12130 if (!ISA_SUPPORT_SMARTMIPS
)
12131 as_warn ("%s ISA does not support SmartMIPS ASE",
12132 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12133 mips_opts
.ase_smartmips
= 1;
12135 else if (strcmp (name
, "nosmartmips") == 0)
12136 mips_opts
.ase_smartmips
= 0;
12137 else if (strcmp (name
, "mips3d") == 0)
12138 mips_opts
.ase_mips3d
= 1;
12139 else if (strcmp (name
, "nomips3d") == 0)
12140 mips_opts
.ase_mips3d
= 0;
12141 else if (strcmp (name
, "mdmx") == 0)
12142 mips_opts
.ase_mdmx
= 1;
12143 else if (strcmp (name
, "nomdmx") == 0)
12144 mips_opts
.ase_mdmx
= 0;
12145 else if (strcmp (name
, "dsp") == 0)
12146 mips_opts
.ase_dsp
= 1;
12147 else if (strcmp (name
, "nodsp") == 0)
12148 mips_opts
.ase_dsp
= 0;
12149 else if (strcmp (name
, "mt") == 0)
12150 mips_opts
.ase_mt
= 1;
12151 else if (strcmp (name
, "nomt") == 0)
12152 mips_opts
.ase_mt
= 0;
12153 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12157 /* Permit the user to change the ISA and architecture on the fly.
12158 Needless to say, misuse can cause serious problems. */
12159 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12162 mips_opts
.isa
= file_mips_isa
;
12163 mips_opts
.arch
= file_mips_arch
;
12165 else if (strncmp (name
, "arch=", 5) == 0)
12167 const struct mips_cpu_info
*p
;
12169 p
= mips_parse_cpu("internal use", name
+ 5);
12171 as_bad (_("unknown architecture %s"), name
+ 5);
12174 mips_opts
.arch
= p
->cpu
;
12175 mips_opts
.isa
= p
->isa
;
12178 else if (strncmp (name
, "mips", 4) == 0)
12180 const struct mips_cpu_info
*p
;
12182 p
= mips_parse_cpu("internal use", name
);
12184 as_bad (_("unknown ISA level %s"), name
+ 4);
12187 mips_opts
.arch
= p
->cpu
;
12188 mips_opts
.isa
= p
->isa
;
12192 as_bad (_("unknown ISA or architecture %s"), name
);
12194 switch (mips_opts
.isa
)
12202 mips_opts
.gp32
= 1;
12203 mips_opts
.fp32
= 1;
12210 mips_opts
.gp32
= 0;
12211 mips_opts
.fp32
= 0;
12214 as_bad (_("unknown ISA level %s"), name
+ 4);
12219 mips_opts
.gp32
= file_mips_gp32
;
12220 mips_opts
.fp32
= file_mips_fp32
;
12223 else if (strcmp (name
, "autoextend") == 0)
12224 mips_opts
.noautoextend
= 0;
12225 else if (strcmp (name
, "noautoextend") == 0)
12226 mips_opts
.noautoextend
= 1;
12227 else if (strcmp (name
, "push") == 0)
12229 struct mips_option_stack
*s
;
12231 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12232 s
->next
= mips_opts_stack
;
12233 s
->options
= mips_opts
;
12234 mips_opts_stack
= s
;
12236 else if (strcmp (name
, "pop") == 0)
12238 struct mips_option_stack
*s
;
12240 s
= mips_opts_stack
;
12242 as_bad (_(".set pop with no .set push"));
12245 /* If we're changing the reorder mode we need to handle
12246 delay slots correctly. */
12247 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12248 start_noreorder ();
12249 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12252 mips_opts
= s
->options
;
12253 mips_opts_stack
= s
->next
;
12257 else if (strcmp (name
, "sym32") == 0)
12258 mips_opts
.sym32
= TRUE
;
12259 else if (strcmp (name
, "nosym32") == 0)
12260 mips_opts
.sym32
= FALSE
;
12263 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12265 *input_line_pointer
= ch
;
12266 demand_empty_rest_of_line ();
12269 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12270 .option pic2. It means to generate SVR4 PIC calls. */
12273 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12275 mips_pic
= SVR4_PIC
;
12276 mips_abicalls
= TRUE
;
12278 if (g_switch_seen
&& g_switch_value
!= 0)
12279 as_warn (_("-G may not be used with SVR4 PIC code"));
12280 g_switch_value
= 0;
12282 bfd_set_gp_size (stdoutput
, 0);
12283 demand_empty_rest_of_line ();
12286 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12287 PIC code. It sets the $gp register for the function based on the
12288 function address, which is in the register named in the argument.
12289 This uses a relocation against _gp_disp, which is handled specially
12290 by the linker. The result is:
12291 lui $gp,%hi(_gp_disp)
12292 addiu $gp,$gp,%lo(_gp_disp)
12293 addu $gp,$gp,.cpload argument
12294 The .cpload argument is normally $25 == $t9.
12296 The -mno-shared option changes this to:
12297 lui $gp,%hi(__gnu_local_gp)
12298 addiu $gp,$gp,%lo(__gnu_local_gp)
12299 and the argument is ignored. This saves an instruction, but the
12300 resulting code is not position independent; it uses an absolute
12301 address for __gnu_local_gp. Thus code assembled with -mno-shared
12302 can go into an ordinary executable, but not into a shared library. */
12305 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12311 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12312 .cpload is ignored. */
12313 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12319 /* .cpload should be in a .set noreorder section. */
12320 if (mips_opts
.noreorder
== 0)
12321 as_warn (_(".cpload not in noreorder section"));
12323 reg
= tc_get_register (0);
12325 /* If we need to produce a 64-bit address, we are better off using
12326 the default instruction sequence. */
12327 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12329 ex
.X_op
= O_symbol
;
12330 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12332 ex
.X_op_symbol
= NULL
;
12333 ex
.X_add_number
= 0;
12335 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12336 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12339 macro_build_lui (&ex
, mips_gp_register
);
12340 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12341 mips_gp_register
, BFD_RELOC_LO16
);
12343 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12344 mips_gp_register
, reg
);
12347 demand_empty_rest_of_line ();
12350 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12351 .cpsetup $reg1, offset|$reg2, label
12353 If offset is given, this results in:
12354 sd $gp, offset($sp)
12355 lui $gp, %hi(%neg(%gp_rel(label)))
12356 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12357 daddu $gp, $gp, $reg1
12359 If $reg2 is given, this results in:
12360 daddu $reg2, $gp, $0
12361 lui $gp, %hi(%neg(%gp_rel(label)))
12362 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12363 daddu $gp, $gp, $reg1
12364 $reg1 is normally $25 == $t9.
12366 The -mno-shared option replaces the last three instructions with
12368 addiu $gp,$gp,%lo(_gp)
12372 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12374 expressionS ex_off
;
12375 expressionS ex_sym
;
12378 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12379 We also need NewABI support. */
12380 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12386 reg1
= tc_get_register (0);
12387 SKIP_WHITESPACE ();
12388 if (*input_line_pointer
!= ',')
12390 as_bad (_("missing argument separator ',' for .cpsetup"));
12394 ++input_line_pointer
;
12395 SKIP_WHITESPACE ();
12396 if (*input_line_pointer
== '$')
12398 mips_cpreturn_register
= tc_get_register (0);
12399 mips_cpreturn_offset
= -1;
12403 mips_cpreturn_offset
= get_absolute_expression ();
12404 mips_cpreturn_register
= -1;
12406 SKIP_WHITESPACE ();
12407 if (*input_line_pointer
!= ',')
12409 as_bad (_("missing argument separator ',' for .cpsetup"));
12413 ++input_line_pointer
;
12414 SKIP_WHITESPACE ();
12415 expression (&ex_sym
);
12418 if (mips_cpreturn_register
== -1)
12420 ex_off
.X_op
= O_constant
;
12421 ex_off
.X_add_symbol
= NULL
;
12422 ex_off
.X_op_symbol
= NULL
;
12423 ex_off
.X_add_number
= mips_cpreturn_offset
;
12425 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12426 BFD_RELOC_LO16
, SP
);
12429 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12430 mips_gp_register
, 0);
12432 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12434 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12435 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12438 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12439 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12440 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12442 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12443 mips_gp_register
, reg1
);
12449 ex
.X_op
= O_symbol
;
12450 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12451 ex
.X_op_symbol
= NULL
;
12452 ex
.X_add_number
= 0;
12454 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12455 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12457 macro_build_lui (&ex
, mips_gp_register
);
12458 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12459 mips_gp_register
, BFD_RELOC_LO16
);
12464 demand_empty_rest_of_line ();
12468 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12470 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12471 .cplocal is ignored. */
12472 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12478 mips_gp_register
= tc_get_register (0);
12479 demand_empty_rest_of_line ();
12482 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12483 offset from $sp. The offset is remembered, and after making a PIC
12484 call $gp is restored from that location. */
12487 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12491 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12492 .cprestore is ignored. */
12493 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12499 mips_cprestore_offset
= get_absolute_expression ();
12500 mips_cprestore_valid
= 1;
12502 ex
.X_op
= O_constant
;
12503 ex
.X_add_symbol
= NULL
;
12504 ex
.X_op_symbol
= NULL
;
12505 ex
.X_add_number
= mips_cprestore_offset
;
12508 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12509 SP
, HAVE_64BIT_ADDRESSES
);
12512 demand_empty_rest_of_line ();
12515 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12516 was given in the preceding .cpsetup, it results in:
12517 ld $gp, offset($sp)
12519 If a register $reg2 was given there, it results in:
12520 daddu $gp, $reg2, $0
12523 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12527 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12528 We also need NewABI support. */
12529 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12536 if (mips_cpreturn_register
== -1)
12538 ex
.X_op
= O_constant
;
12539 ex
.X_add_symbol
= NULL
;
12540 ex
.X_op_symbol
= NULL
;
12541 ex
.X_add_number
= mips_cpreturn_offset
;
12543 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12546 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12547 mips_cpreturn_register
, 0);
12550 demand_empty_rest_of_line ();
12553 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12554 code. It sets the offset to use in gp_rel relocations. */
12557 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12559 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12560 We also need NewABI support. */
12561 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12567 mips_gprel_offset
= get_absolute_expression ();
12569 demand_empty_rest_of_line ();
12572 /* Handle the .gpword pseudo-op. This is used when generating PIC
12573 code. It generates a 32 bit GP relative reloc. */
12576 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12582 /* When not generating PIC code, this is treated as .word. */
12583 if (mips_pic
!= SVR4_PIC
)
12589 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12590 mips_emit_delays ();
12592 mips_align (2, 0, label
);
12593 mips_clear_insn_labels ();
12597 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12599 as_bad (_("Unsupported use of .gpword"));
12600 ignore_rest_of_line ();
12604 md_number_to_chars (p
, 0, 4);
12605 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12606 BFD_RELOC_GPREL32
);
12608 demand_empty_rest_of_line ();
12612 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12618 /* When not generating PIC code, this is treated as .dword. */
12619 if (mips_pic
!= SVR4_PIC
)
12625 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12626 mips_emit_delays ();
12628 mips_align (3, 0, label
);
12629 mips_clear_insn_labels ();
12633 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12635 as_bad (_("Unsupported use of .gpdword"));
12636 ignore_rest_of_line ();
12640 md_number_to_chars (p
, 0, 8);
12641 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12642 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12644 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12645 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12646 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12648 demand_empty_rest_of_line ();
12651 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12652 tables in SVR4 PIC code. */
12655 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12659 /* This is ignored when not generating SVR4 PIC code. */
12660 if (mips_pic
!= SVR4_PIC
)
12666 /* Add $gp to the register named as an argument. */
12668 reg
= tc_get_register (0);
12669 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12672 demand_empty_rest_of_line ();
12675 /* Handle the .insn pseudo-op. This marks instruction labels in
12676 mips16 mode. This permits the linker to handle them specially,
12677 such as generating jalx instructions when needed. We also make
12678 them odd for the duration of the assembly, in order to generate the
12679 right sort of code. We will make them even in the adjust_symtab
12680 routine, while leaving them marked. This is convenient for the
12681 debugger and the disassembler. The linker knows to make them odd
12685 s_insn (int ignore ATTRIBUTE_UNUSED
)
12687 mips16_mark_labels ();
12689 demand_empty_rest_of_line ();
12692 /* Handle a .stabn directive. We need these in order to mark a label
12693 as being a mips16 text label correctly. Sometimes the compiler
12694 will emit a label, followed by a .stabn, and then switch sections.
12695 If the label and .stabn are in mips16 mode, then the label is
12696 really a mips16 text label. */
12699 s_mips_stab (int type
)
12702 mips16_mark_labels ();
12707 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12711 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12718 name
= input_line_pointer
;
12719 c
= get_symbol_end ();
12720 symbolP
= symbol_find_or_make (name
);
12721 S_SET_WEAK (symbolP
);
12722 *input_line_pointer
= c
;
12724 SKIP_WHITESPACE ();
12726 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12728 if (S_IS_DEFINED (symbolP
))
12730 as_bad ("ignoring attempt to redefine symbol %s",
12731 S_GET_NAME (symbolP
));
12732 ignore_rest_of_line ();
12736 if (*input_line_pointer
== ',')
12738 ++input_line_pointer
;
12739 SKIP_WHITESPACE ();
12743 if (exp
.X_op
!= O_symbol
)
12745 as_bad ("bad .weakext directive");
12746 ignore_rest_of_line ();
12749 symbol_set_value_expression (symbolP
, &exp
);
12752 demand_empty_rest_of_line ();
12755 /* Parse a register string into a number. Called from the ECOFF code
12756 to parse .frame. The argument is non-zero if this is the frame
12757 register, so that we can record it in mips_frame_reg. */
12760 tc_get_register (int frame
)
12764 SKIP_WHITESPACE ();
12765 if (*input_line_pointer
++ != '$')
12767 as_warn (_("expected `$'"));
12770 else if (ISDIGIT (*input_line_pointer
))
12772 reg
= get_absolute_expression ();
12773 if (reg
< 0 || reg
>= 32)
12775 as_warn (_("Bad register number"));
12781 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12784 input_line_pointer
+= 2;
12786 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12789 input_line_pointer
+= 2;
12791 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12794 input_line_pointer
+= 2;
12796 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12799 input_line_pointer
+= 2;
12801 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12804 input_line_pointer
+= 2;
12806 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12809 input_line_pointer
+= 3;
12811 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12814 input_line_pointer
+= 3;
12816 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12819 input_line_pointer
+= 4;
12823 as_warn (_("Unrecognized register name"));
12825 while (ISALNUM(*input_line_pointer
))
12826 input_line_pointer
++;
12831 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12832 mips_frame_reg_valid
= 1;
12833 mips_cprestore_valid
= 0;
12839 md_section_align (asection
*seg
, valueT addr
)
12841 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12844 /* We don't need to align ELF sections to the full alignment.
12845 However, Irix 5 may prefer that we align them at least to a 16
12846 byte boundary. We don't bother to align the sections if we are
12847 targeted for an embedded system. */
12848 if (strcmp (TARGET_OS
, "elf") == 0)
12854 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12857 /* Utility routine, called from above as well. If called while the
12858 input file is still being read, it's only an approximation. (For
12859 example, a symbol may later become defined which appeared to be
12860 undefined earlier.) */
12863 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12868 if (g_switch_value
> 0)
12870 const char *symname
;
12873 /* Find out whether this symbol can be referenced off the $gp
12874 register. It can be if it is smaller than the -G size or if
12875 it is in the .sdata or .sbss section. Certain symbols can
12876 not be referenced off the $gp, although it appears as though
12878 symname
= S_GET_NAME (sym
);
12879 if (symname
!= (const char *) NULL
12880 && (strcmp (symname
, "eprol") == 0
12881 || strcmp (symname
, "etext") == 0
12882 || strcmp (symname
, "_gp") == 0
12883 || strcmp (symname
, "edata") == 0
12884 || strcmp (symname
, "_fbss") == 0
12885 || strcmp (symname
, "_fdata") == 0
12886 || strcmp (symname
, "_ftext") == 0
12887 || strcmp (symname
, "end") == 0
12888 || strcmp (symname
, "_gp_disp") == 0))
12890 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12892 #ifndef NO_ECOFF_DEBUGGING
12893 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12894 && (symbol_get_obj (sym
)->ecoff_extern_size
12895 <= g_switch_value
))
12897 /* We must defer this decision until after the whole
12898 file has been read, since there might be a .extern
12899 after the first use of this symbol. */
12900 || (before_relaxing
12901 #ifndef NO_ECOFF_DEBUGGING
12902 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12904 && S_GET_VALUE (sym
) == 0)
12905 || (S_GET_VALUE (sym
) != 0
12906 && S_GET_VALUE (sym
) <= g_switch_value
)))
12910 const char *segname
;
12912 segname
= segment_name (S_GET_SEGMENT (sym
));
12913 assert (strcmp (segname
, ".lit8") != 0
12914 && strcmp (segname
, ".lit4") != 0);
12915 change
= (strcmp (segname
, ".sdata") != 0
12916 && strcmp (segname
, ".sbss") != 0
12917 && strncmp (segname
, ".sdata.", 7) != 0
12918 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12923 /* We are not optimizing for the $gp register. */
12928 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12931 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12934 bfd_boolean linkonce
;
12936 /* Handle the case of a symbol equated to another symbol. */
12937 while (symbol_equated_reloc_p (sym
))
12941 /* It's possible to get a loop here in a badly written
12943 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12949 symsec
= S_GET_SEGMENT (sym
);
12951 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12953 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12955 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12959 /* The GNU toolchain uses an extension for ELF: a section
12960 beginning with the magic string .gnu.linkonce is a linkonce
12962 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12963 sizeof ".gnu.linkonce" - 1) == 0)
12967 /* This must duplicate the test in adjust_reloc_syms. */
12968 return (symsec
!= &bfd_und_section
12969 && symsec
!= &bfd_abs_section
12970 && ! bfd_is_com_section (symsec
)
12973 /* A global or weak symbol is treated as external. */
12974 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12975 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12981 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12982 extended opcode. SEC is the section the frag is in. */
12985 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12988 register const struct mips16_immed_operand
*op
;
12990 int mintiny
, maxtiny
;
12994 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12996 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12999 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13000 op
= mips16_immed_operands
;
13001 while (op
->type
!= type
)
13004 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13009 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13012 maxtiny
= 1 << op
->nbits
;
13017 maxtiny
= (1 << op
->nbits
) - 1;
13022 mintiny
= - (1 << (op
->nbits
- 1));
13023 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13026 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13027 val
= S_GET_VALUE (fragp
->fr_symbol
);
13028 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13034 /* We won't have the section when we are called from
13035 mips_relax_frag. However, we will always have been called
13036 from md_estimate_size_before_relax first. If this is a
13037 branch to a different section, we mark it as such. If SEC is
13038 NULL, and the frag is not marked, then it must be a branch to
13039 the same section. */
13042 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13047 /* Must have been called from md_estimate_size_before_relax. */
13050 fragp
->fr_subtype
=
13051 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13053 /* FIXME: We should support this, and let the linker
13054 catch branches and loads that are out of range. */
13055 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13056 _("unsupported PC relative reference to different section"));
13060 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13061 /* Assume non-extended on the first relaxation pass.
13062 The address we have calculated will be bogus if this is
13063 a forward branch to another frag, as the forward frag
13064 will have fr_address == 0. */
13068 /* In this case, we know for sure that the symbol fragment is in
13069 the same section. If the relax_marker of the symbol fragment
13070 differs from the relax_marker of this fragment, we have not
13071 yet adjusted the symbol fragment fr_address. We want to add
13072 in STRETCH in order to get a better estimate of the address.
13073 This particularly matters because of the shift bits. */
13075 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13079 /* Adjust stretch for any alignment frag. Note that if have
13080 been expanding the earlier code, the symbol may be
13081 defined in what appears to be an earlier frag. FIXME:
13082 This doesn't handle the fr_subtype field, which specifies
13083 a maximum number of bytes to skip when doing an
13085 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13087 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13090 stretch
= - ((- stretch
)
13091 & ~ ((1 << (int) f
->fr_offset
) - 1));
13093 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13102 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13104 /* The base address rules are complicated. The base address of
13105 a branch is the following instruction. The base address of a
13106 PC relative load or add is the instruction itself, but if it
13107 is in a delay slot (in which case it can not be extended) use
13108 the address of the instruction whose delay slot it is in. */
13109 if (type
== 'p' || type
== 'q')
13113 /* If we are currently assuming that this frag should be
13114 extended, then, the current address is two bytes
13116 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13119 /* Ignore the low bit in the target, since it will be set
13120 for a text label. */
13121 if ((val
& 1) != 0)
13124 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13126 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13129 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13131 /* Branch offsets have an implicit 0 in the lowest bit. */
13132 if (type
== 'p' || type
== 'q')
13135 /* If any of the shifted bits are set, we must use an extended
13136 opcode. If the address depends on the size of this
13137 instruction, this can lead to a loop, so we arrange to always
13138 use an extended opcode. We only check this when we are in
13139 the main relaxation loop, when SEC is NULL. */
13140 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13142 fragp
->fr_subtype
=
13143 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13147 /* If we are about to mark a frag as extended because the value
13148 is precisely maxtiny + 1, then there is a chance of an
13149 infinite loop as in the following code:
13154 In this case when the la is extended, foo is 0x3fc bytes
13155 away, so the la can be shrunk, but then foo is 0x400 away, so
13156 the la must be extended. To avoid this loop, we mark the
13157 frag as extended if it was small, and is about to become
13158 extended with a value of maxtiny + 1. */
13159 if (val
== ((maxtiny
+ 1) << op
->shift
)
13160 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13163 fragp
->fr_subtype
=
13164 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13168 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13169 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13171 if ((val
& ((1 << op
->shift
) - 1)) != 0
13172 || val
< (mintiny
<< op
->shift
)
13173 || val
> (maxtiny
<< op
->shift
))
13179 /* Compute the length of a branch sequence, and adjust the
13180 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13181 worst-case length is computed, with UPDATE being used to indicate
13182 whether an unconditional (-1), branch-likely (+1) or regular (0)
13183 branch is to be computed. */
13185 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13187 bfd_boolean toofar
;
13191 && S_IS_DEFINED (fragp
->fr_symbol
)
13192 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13197 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13199 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13203 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13206 /* If the symbol is not defined or it's in a different segment,
13207 assume the user knows what's going on and emit a short
13213 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13215 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13216 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13217 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13223 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13226 if (mips_pic
!= NO_PIC
)
13228 /* Additional space for PIC loading of target address. */
13230 if (mips_opts
.isa
== ISA_MIPS1
)
13231 /* Additional space for $at-stabilizing nop. */
13235 /* If branch is conditional. */
13236 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13243 /* Estimate the size of a frag before relaxing. Unless this is the
13244 mips16, we are not really relaxing here, and the final size is
13245 encoded in the subtype information. For the mips16, we have to
13246 decide whether we are using an extended opcode or not. */
13249 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13253 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13256 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13258 return fragp
->fr_var
;
13261 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13262 /* We don't want to modify the EXTENDED bit here; it might get us
13263 into infinite loops. We change it only in mips_relax_frag(). */
13264 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13266 if (mips_pic
== NO_PIC
)
13267 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13268 else if (mips_pic
== SVR4_PIC
)
13269 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13270 else if (mips_pic
== VXWORKS_PIC
)
13271 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13278 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13279 return -RELAX_FIRST (fragp
->fr_subtype
);
13282 return -RELAX_SECOND (fragp
->fr_subtype
);
13285 /* This is called to see whether a reloc against a defined symbol
13286 should be converted into a reloc against a section. */
13289 mips_fix_adjustable (fixS
*fixp
)
13291 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13292 about the format of the offset in the .o file. */
13293 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13296 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13297 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13300 if (fixp
->fx_addsy
== NULL
)
13303 /* If symbol SYM is in a mergeable section, relocations of the form
13304 SYM + 0 can usually be made section-relative. The mergeable data
13305 is then identified by the section offset rather than by the symbol.
13307 However, if we're generating REL LO16 relocations, the offset is split
13308 between the LO16 and parterning high part relocation. The linker will
13309 need to recalculate the complete offset in order to correctly identify
13312 The linker has traditionally not looked for the parterning high part
13313 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13314 placed anywhere. Rather than break backwards compatibility by changing
13315 this, it seems better not to force the issue, and instead keep the
13316 original symbol. This will work with either linker behavior. */
13317 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13318 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13319 || reloc_needs_lo_p (fixp
->fx_r_type
))
13320 && HAVE_IN_PLACE_ADDENDS
13321 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13325 /* Don't adjust relocations against mips16 symbols, so that the linker
13326 can find them if it needs to set up a stub. */
13327 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13328 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13329 && fixp
->fx_subsy
== NULL
)
13336 /* Translate internal representation of relocation info to BFD target
13340 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13342 static arelent
*retval
[4];
13344 bfd_reloc_code_real_type code
;
13346 memset (retval
, 0, sizeof(retval
));
13347 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13348 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13349 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13350 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13352 if (fixp
->fx_pcrel
)
13354 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13356 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13357 Relocations want only the symbol offset. */
13358 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13359 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13361 /* A gruesome hack which is a result of the gruesome gas
13362 reloc handling. What's worse, for COFF (as opposed to
13363 ECOFF), we might need yet another copy of reloc->address.
13364 See bfd_install_relocation. */
13365 reloc
->addend
+= reloc
->address
;
13369 reloc
->addend
= fixp
->fx_addnumber
;
13371 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13372 entry to be used in the relocation's section offset. */
13373 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13375 reloc
->address
= reloc
->addend
;
13379 code
= fixp
->fx_r_type
;
13381 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13382 if (reloc
->howto
== NULL
)
13384 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13385 _("Can not represent %s relocation in this object file format"),
13386 bfd_get_reloc_code_name (code
));
13393 /* Relax a machine dependent frag. This returns the amount by which
13394 the current size of the frag should change. */
13397 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13399 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13401 offsetT old_var
= fragp
->fr_var
;
13403 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13405 return fragp
->fr_var
- old_var
;
13408 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13411 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13413 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13415 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13420 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13422 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13429 /* Convert a machine dependent frag. */
13432 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13434 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13437 unsigned long insn
;
13441 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13443 if (target_big_endian
)
13444 insn
= bfd_getb32 (buf
);
13446 insn
= bfd_getl32 (buf
);
13448 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13450 /* We generate a fixup instead of applying it right now
13451 because, if there are linker relaxations, we're going to
13452 need the relocations. */
13453 exp
.X_op
= O_symbol
;
13454 exp
.X_add_symbol
= fragp
->fr_symbol
;
13455 exp
.X_add_number
= fragp
->fr_offset
;
13457 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13458 4, &exp
, 1, BFD_RELOC_16_PCREL_S2
);
13459 fixp
->fx_file
= fragp
->fr_file
;
13460 fixp
->fx_line
= fragp
->fr_line
;
13462 md_number_to_chars ((char *) buf
, insn
, 4);
13469 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13470 _("relaxed out-of-range branch into a jump"));
13472 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13475 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13477 /* Reverse the branch. */
13478 switch ((insn
>> 28) & 0xf)
13481 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13482 have the condition reversed by tweaking a single
13483 bit, and their opcodes all have 0x4???????. */
13484 assert ((insn
& 0xf1000000) == 0x41000000);
13485 insn
^= 0x00010000;
13489 /* bltz 0x04000000 bgez 0x04010000
13490 bltzal 0x04100000 bgezal 0x04110000 */
13491 assert ((insn
& 0xfc0e0000) == 0x04000000);
13492 insn
^= 0x00010000;
13496 /* beq 0x10000000 bne 0x14000000
13497 blez 0x18000000 bgtz 0x1c000000 */
13498 insn
^= 0x04000000;
13506 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13508 /* Clear the and-link bit. */
13509 assert ((insn
& 0xfc1c0000) == 0x04100000);
13511 /* bltzal 0x04100000 bgezal 0x04110000
13512 bltzall 0x04120000 bgezall 0x04130000 */
13513 insn
&= ~0x00100000;
13516 /* Branch over the branch (if the branch was likely) or the
13517 full jump (not likely case). Compute the offset from the
13518 current instruction to branch to. */
13519 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13523 /* How many bytes in instructions we've already emitted? */
13524 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13525 /* How many bytes in instructions from here to the end? */
13526 i
= fragp
->fr_var
- i
;
13528 /* Convert to instruction count. */
13530 /* Branch counts from the next instruction. */
13533 /* Branch over the jump. */
13534 md_number_to_chars ((char *) buf
, insn
, 4);
13538 md_number_to_chars ((char *) buf
, 0, 4);
13541 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13543 /* beql $0, $0, 2f */
13545 /* Compute the PC offset from the current instruction to
13546 the end of the variable frag. */
13547 /* How many bytes in instructions we've already emitted? */
13548 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13549 /* How many bytes in instructions from here to the end? */
13550 i
= fragp
->fr_var
- i
;
13551 /* Convert to instruction count. */
13553 /* Don't decrement i, because we want to branch over the
13557 md_number_to_chars ((char *) buf
, insn
, 4);
13560 md_number_to_chars ((char *) buf
, 0, 4);
13565 if (mips_pic
== NO_PIC
)
13568 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13569 ? 0x0c000000 : 0x08000000);
13570 exp
.X_op
= O_symbol
;
13571 exp
.X_add_symbol
= fragp
->fr_symbol
;
13572 exp
.X_add_number
= fragp
->fr_offset
;
13574 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13575 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13576 fixp
->fx_file
= fragp
->fr_file
;
13577 fixp
->fx_line
= fragp
->fr_line
;
13579 md_number_to_chars ((char *) buf
, insn
, 4);
13584 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13585 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13586 exp
.X_op
= O_symbol
;
13587 exp
.X_add_symbol
= fragp
->fr_symbol
;
13588 exp
.X_add_number
= fragp
->fr_offset
;
13590 if (fragp
->fr_offset
)
13592 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13593 exp
.X_add_number
= 0;
13596 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13597 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13598 fixp
->fx_file
= fragp
->fr_file
;
13599 fixp
->fx_line
= fragp
->fr_line
;
13601 md_number_to_chars ((char *) buf
, insn
, 4);
13604 if (mips_opts
.isa
== ISA_MIPS1
)
13607 md_number_to_chars ((char *) buf
, 0, 4);
13611 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13612 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13614 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13615 4, &exp
, 0, BFD_RELOC_LO16
);
13616 fixp
->fx_file
= fragp
->fr_file
;
13617 fixp
->fx_line
= fragp
->fr_line
;
13619 md_number_to_chars ((char *) buf
, insn
, 4);
13623 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13628 md_number_to_chars ((char *) buf
, insn
, 4);
13633 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13634 + fragp
->fr_fix
+ fragp
->fr_var
);
13636 fragp
->fr_fix
+= fragp
->fr_var
;
13641 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13644 register const struct mips16_immed_operand
*op
;
13645 bfd_boolean small
, ext
;
13648 unsigned long insn
;
13649 bfd_boolean use_extend
;
13650 unsigned short extend
;
13652 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13653 op
= mips16_immed_operands
;
13654 while (op
->type
!= type
)
13657 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13668 resolve_symbol_value (fragp
->fr_symbol
);
13669 val
= S_GET_VALUE (fragp
->fr_symbol
);
13674 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13676 /* The rules for the base address of a PC relative reloc are
13677 complicated; see mips16_extended_frag. */
13678 if (type
== 'p' || type
== 'q')
13683 /* Ignore the low bit in the target, since it will be
13684 set for a text label. */
13685 if ((val
& 1) != 0)
13688 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13690 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13693 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13696 /* Make sure the section winds up with the alignment we have
13699 record_alignment (asec
, op
->shift
);
13703 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13704 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13705 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13706 _("extended instruction in delay slot"));
13708 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13710 if (target_big_endian
)
13711 insn
= bfd_getb16 (buf
);
13713 insn
= bfd_getl16 (buf
);
13715 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13716 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13717 small
, ext
, &insn
, &use_extend
, &extend
);
13721 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13722 fragp
->fr_fix
+= 2;
13726 md_number_to_chars ((char *) buf
, insn
, 2);
13727 fragp
->fr_fix
+= 2;
13735 first
= RELAX_FIRST (fragp
->fr_subtype
);
13736 second
= RELAX_SECOND (fragp
->fr_subtype
);
13737 fixp
= (fixS
*) fragp
->fr_opcode
;
13739 /* Possibly emit a warning if we've chosen the longer option. */
13740 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13741 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13743 const char *msg
= macro_warning (fragp
->fr_subtype
);
13745 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13748 /* Go through all the fixups for the first sequence. Disable them
13749 (by marking them as done) if we're going to use the second
13750 sequence instead. */
13752 && fixp
->fx_frag
== fragp
13753 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13755 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13757 fixp
= fixp
->fx_next
;
13760 /* Go through the fixups for the second sequence. Disable them if
13761 we're going to use the first sequence, otherwise adjust their
13762 addresses to account for the relaxation. */
13763 while (fixp
&& fixp
->fx_frag
== fragp
)
13765 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13766 fixp
->fx_where
-= first
;
13769 fixp
= fixp
->fx_next
;
13772 /* Now modify the frag contents. */
13773 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13777 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13778 memmove (start
, start
+ first
, second
);
13779 fragp
->fr_fix
-= first
;
13782 fragp
->fr_fix
-= second
;
13788 /* This function is called after the relocs have been generated.
13789 We've been storing mips16 text labels as odd. Here we convert them
13790 back to even for the convenience of the debugger. */
13793 mips_frob_file_after_relocs (void)
13796 unsigned int count
, i
;
13798 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13801 syms
= bfd_get_outsymbols (stdoutput
);
13802 count
= bfd_get_symcount (stdoutput
);
13803 for (i
= 0; i
< count
; i
++, syms
++)
13805 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13806 && ((*syms
)->value
& 1) != 0)
13808 (*syms
)->value
&= ~1;
13809 /* If the symbol has an odd size, it was probably computed
13810 incorrectly, so adjust that as well. */
13811 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13812 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13819 /* This function is called whenever a label is defined. It is used
13820 when handling branch delays; if a branch has a label, we assume we
13821 can not move it. */
13824 mips_define_label (symbolS
*sym
)
13826 struct insn_label_list
*l
;
13828 if (free_insn_labels
== NULL
)
13829 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13832 l
= free_insn_labels
;
13833 free_insn_labels
= l
->next
;
13837 l
->next
= insn_labels
;
13841 dwarf2_emit_label (sym
);
13845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13847 /* Some special processing for a MIPS ELF file. */
13850 mips_elf_final_processing (void)
13852 /* Write out the register information. */
13853 if (mips_abi
!= N64_ABI
)
13857 s
.ri_gprmask
= mips_gprmask
;
13858 s
.ri_cprmask
[0] = mips_cprmask
[0];
13859 s
.ri_cprmask
[1] = mips_cprmask
[1];
13860 s
.ri_cprmask
[2] = mips_cprmask
[2];
13861 s
.ri_cprmask
[3] = mips_cprmask
[3];
13862 /* The gp_value field is set by the MIPS ELF backend. */
13864 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13865 ((Elf32_External_RegInfo
*)
13866 mips_regmask_frag
));
13870 Elf64_Internal_RegInfo s
;
13872 s
.ri_gprmask
= mips_gprmask
;
13874 s
.ri_cprmask
[0] = mips_cprmask
[0];
13875 s
.ri_cprmask
[1] = mips_cprmask
[1];
13876 s
.ri_cprmask
[2] = mips_cprmask
[2];
13877 s
.ri_cprmask
[3] = mips_cprmask
[3];
13878 /* The gp_value field is set by the MIPS ELF backend. */
13880 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13881 ((Elf64_External_RegInfo
*)
13882 mips_regmask_frag
));
13885 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13886 sort of BFD interface for this. */
13887 if (mips_any_noreorder
)
13888 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13889 if (mips_pic
!= NO_PIC
)
13891 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13892 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13895 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13897 /* Set MIPS ELF flags for ASEs. */
13898 /* We may need to define a new flag for DSP ASE, and set this flag when
13899 file_ase_dsp is true. */
13900 /* We may need to define a new flag for MT ASE, and set this flag when
13901 file_ase_mt is true. */
13902 if (file_ase_mips16
)
13903 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13904 #if 0 /* XXX FIXME */
13905 if (file_ase_mips3d
)
13906 elf_elfheader (stdoutput
)->e_flags
|= ???;
13909 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13911 /* Set the MIPS ELF ABI flags. */
13912 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13913 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13914 else if (mips_abi
== O64_ABI
)
13915 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13916 else if (mips_abi
== EABI_ABI
)
13918 if (!file_mips_gp32
)
13919 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13921 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13923 else if (mips_abi
== N32_ABI
)
13924 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13926 /* Nothing to do for N64_ABI. */
13928 if (mips_32bitmode
)
13929 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13932 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13934 typedef struct proc
{
13936 symbolS
*func_end_sym
;
13937 unsigned long reg_mask
;
13938 unsigned long reg_offset
;
13939 unsigned long fpreg_mask
;
13940 unsigned long fpreg_offset
;
13941 unsigned long frame_offset
;
13942 unsigned long frame_reg
;
13943 unsigned long pc_reg
;
13946 static procS cur_proc
;
13947 static procS
*cur_proc_ptr
;
13948 static int numprocs
;
13950 /* Fill in an rs_align_code fragment. */
13953 mips_handle_align (fragS
*fragp
)
13955 if (fragp
->fr_type
!= rs_align_code
)
13958 if (mips_opts
.mips16
)
13960 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13961 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13966 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13967 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13975 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13979 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13983 md_obj_begin (void)
13990 /* check for premature end, nesting errors, etc */
13992 as_warn (_("missing .end at end of assembly"));
14001 if (*input_line_pointer
== '-')
14003 ++input_line_pointer
;
14006 if (!ISDIGIT (*input_line_pointer
))
14007 as_bad (_("expected simple number"));
14008 if (input_line_pointer
[0] == '0')
14010 if (input_line_pointer
[1] == 'x')
14012 input_line_pointer
+= 2;
14013 while (ISXDIGIT (*input_line_pointer
))
14016 val
|= hex_value (*input_line_pointer
++);
14018 return negative
? -val
: val
;
14022 ++input_line_pointer
;
14023 while (ISDIGIT (*input_line_pointer
))
14026 val
|= *input_line_pointer
++ - '0';
14028 return negative
? -val
: val
;
14031 if (!ISDIGIT (*input_line_pointer
))
14033 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14034 *input_line_pointer
, *input_line_pointer
);
14035 as_warn (_("invalid number"));
14038 while (ISDIGIT (*input_line_pointer
))
14041 val
+= *input_line_pointer
++ - '0';
14043 return negative
? -val
: val
;
14046 /* The .file directive; just like the usual .file directive, but there
14047 is an initial number which is the ECOFF file index. In the non-ECOFF
14048 case .file implies DWARF-2. */
14051 s_mips_file (int x ATTRIBUTE_UNUSED
)
14053 static int first_file_directive
= 0;
14055 if (ECOFF_DEBUGGING
)
14064 filename
= dwarf2_directive_file (0);
14066 /* Versions of GCC up to 3.1 start files with a ".file"
14067 directive even for stabs output. Make sure that this
14068 ".file" is handled. Note that you need a version of GCC
14069 after 3.1 in order to support DWARF-2 on MIPS. */
14070 if (filename
!= NULL
&& ! first_file_directive
)
14072 (void) new_logical_line (filename
, -1);
14073 s_app_file_string (filename
, 0);
14075 first_file_directive
= 1;
14079 /* The .loc directive, implying DWARF-2. */
14082 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14084 if (!ECOFF_DEBUGGING
)
14085 dwarf2_directive_loc (0);
14088 /* The .end directive. */
14091 s_mips_end (int x ATTRIBUTE_UNUSED
)
14095 /* Following functions need their own .frame and .cprestore directives. */
14096 mips_frame_reg_valid
= 0;
14097 mips_cprestore_valid
= 0;
14099 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14102 demand_empty_rest_of_line ();
14107 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14108 as_warn (_(".end not in text section"));
14112 as_warn (_(".end directive without a preceding .ent directive."));
14113 demand_empty_rest_of_line ();
14119 assert (S_GET_NAME (p
));
14120 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14121 as_warn (_(".end symbol does not match .ent symbol."));
14123 if (debug_type
== DEBUG_STABS
)
14124 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14128 as_warn (_(".end directive missing or unknown symbol"));
14131 /* Create an expression to calculate the size of the function. */
14132 if (p
&& cur_proc_ptr
)
14134 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14135 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14138 exp
->X_op
= O_subtract
;
14139 exp
->X_add_symbol
= symbol_temp_new_now ();
14140 exp
->X_op_symbol
= p
;
14141 exp
->X_add_number
= 0;
14143 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14146 /* Generate a .pdr section. */
14147 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
14150 segT saved_seg
= now_seg
;
14151 subsegT saved_subseg
= now_subseg
;
14156 dot
= frag_now_fix ();
14158 #ifdef md_flush_pending_output
14159 md_flush_pending_output ();
14163 subseg_set (pdr_seg
, 0);
14165 /* Write the symbol. */
14166 exp
.X_op
= O_symbol
;
14167 exp
.X_add_symbol
= p
;
14168 exp
.X_add_number
= 0;
14169 emit_expr (&exp
, 4);
14171 fragp
= frag_more (7 * 4);
14173 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14174 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14175 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14176 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14177 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14178 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14179 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14181 subseg_set (saved_seg
, saved_subseg
);
14183 #endif /* OBJ_ELF */
14185 cur_proc_ptr
= NULL
;
14188 /* The .aent and .ent directives. */
14191 s_mips_ent (int aent
)
14195 symbolP
= get_symbol ();
14196 if (*input_line_pointer
== ',')
14197 ++input_line_pointer
;
14198 SKIP_WHITESPACE ();
14199 if (ISDIGIT (*input_line_pointer
)
14200 || *input_line_pointer
== '-')
14203 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14204 as_warn (_(".ent or .aent not in text section."));
14206 if (!aent
&& cur_proc_ptr
)
14207 as_warn (_("missing .end"));
14211 /* This function needs its own .frame and .cprestore directives. */
14212 mips_frame_reg_valid
= 0;
14213 mips_cprestore_valid
= 0;
14215 cur_proc_ptr
= &cur_proc
;
14216 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14218 cur_proc_ptr
->func_sym
= symbolP
;
14220 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14224 if (debug_type
== DEBUG_STABS
)
14225 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14226 S_GET_NAME (symbolP
));
14229 demand_empty_rest_of_line ();
14232 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14233 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14234 s_mips_frame is used so that we can set the PDR information correctly.
14235 We can't use the ecoff routines because they make reference to the ecoff
14236 symbol table (in the mdebug section). */
14239 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14242 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14246 if (cur_proc_ptr
== (procS
*) NULL
)
14248 as_warn (_(".frame outside of .ent"));
14249 demand_empty_rest_of_line ();
14253 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14255 SKIP_WHITESPACE ();
14256 if (*input_line_pointer
++ != ','
14257 || get_absolute_expression_and_terminator (&val
) != ',')
14259 as_warn (_("Bad .frame directive"));
14260 --input_line_pointer
;
14261 demand_empty_rest_of_line ();
14265 cur_proc_ptr
->frame_offset
= val
;
14266 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14268 demand_empty_rest_of_line ();
14271 #endif /* OBJ_ELF */
14275 /* The .fmask and .mask directives. If the mdebug section is present
14276 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14277 embedded targets, s_mips_mask is used so that we can set the PDR
14278 information correctly. We can't use the ecoff routines because they
14279 make reference to the ecoff symbol table (in the mdebug section). */
14282 s_mips_mask (int reg_type
)
14285 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14289 if (cur_proc_ptr
== (procS
*) NULL
)
14291 as_warn (_(".mask/.fmask outside of .ent"));
14292 demand_empty_rest_of_line ();
14296 if (get_absolute_expression_and_terminator (&mask
) != ',')
14298 as_warn (_("Bad .mask/.fmask directive"));
14299 --input_line_pointer
;
14300 demand_empty_rest_of_line ();
14304 off
= get_absolute_expression ();
14306 if (reg_type
== 'F')
14308 cur_proc_ptr
->fpreg_mask
= mask
;
14309 cur_proc_ptr
->fpreg_offset
= off
;
14313 cur_proc_ptr
->reg_mask
= mask
;
14314 cur_proc_ptr
->reg_offset
= off
;
14317 demand_empty_rest_of_line ();
14320 #endif /* OBJ_ELF */
14321 s_ignore (reg_type
);
14324 /* A table describing all the processors gas knows about. Names are
14325 matched in the order listed.
14327 To ease comparison, please keep this table in the same order as
14328 gcc's mips_cpu_info_table[]. */
14329 static const struct mips_cpu_info mips_cpu_info_table
[] =
14331 /* Entries for generic ISAs */
14332 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14333 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14334 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14335 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14336 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14337 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14338 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14339 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14340 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
14343 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14344 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14345 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14348 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14351 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14352 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14353 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14354 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14355 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14356 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14357 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14358 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14359 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14360 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14361 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14362 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14365 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14366 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14367 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14368 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14369 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14370 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14371 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14372 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14373 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14374 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14375 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14376 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14377 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14380 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14381 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14382 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14384 /* MIPS32 Release 2 */
14385 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14386 { "24k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14387 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14388 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14389 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14392 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14393 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14394 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14396 /* Broadcom SB-1 CPU core */
14397 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14404 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14405 with a final "000" replaced by "k". Ignore case.
14407 Note: this function is shared between GCC and GAS. */
14410 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14412 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14413 given
++, canonical
++;
14415 return ((*given
== 0 && *canonical
== 0)
14416 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14420 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14421 CPU name. We've traditionally allowed a lot of variation here.
14423 Note: this function is shared between GCC and GAS. */
14426 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14428 /* First see if the name matches exactly, or with a final "000"
14429 turned into "k". */
14430 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14433 /* If not, try comparing based on numerical designation alone.
14434 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14435 if (TOLOWER (*given
) == 'r')
14437 if (!ISDIGIT (*given
))
14440 /* Skip over some well-known prefixes in the canonical name,
14441 hoping to find a number there too. */
14442 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14444 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14446 else if (TOLOWER (canonical
[0]) == 'r')
14449 return mips_strict_matching_cpu_name_p (canonical
, given
);
14453 /* Parse an option that takes the name of a processor as its argument.
14454 OPTION is the name of the option and CPU_STRING is the argument.
14455 Return the corresponding processor enumeration if the CPU_STRING is
14456 recognized, otherwise report an error and return null.
14458 A similar function exists in GCC. */
14460 static const struct mips_cpu_info
*
14461 mips_parse_cpu (const char *option
, const char *cpu_string
)
14463 const struct mips_cpu_info
*p
;
14465 /* 'from-abi' selects the most compatible architecture for the given
14466 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14467 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14468 version. Look first at the -mgp options, if given, otherwise base
14469 the choice on MIPS_DEFAULT_64BIT.
14471 Treat NO_ABI like the EABIs. One reason to do this is that the
14472 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14473 architecture. This code picks MIPS I for 'mips' and MIPS III for
14474 'mips64', just as we did in the days before 'from-abi'. */
14475 if (strcasecmp (cpu_string
, "from-abi") == 0)
14477 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14478 return mips_cpu_info_from_isa (ISA_MIPS1
);
14480 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14481 return mips_cpu_info_from_isa (ISA_MIPS3
);
14483 if (file_mips_gp32
>= 0)
14484 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14486 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14491 /* 'default' has traditionally been a no-op. Probably not very useful. */
14492 if (strcasecmp (cpu_string
, "default") == 0)
14495 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14496 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14499 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14503 /* Return the canonical processor information for ISA (a member of the
14504 ISA_MIPS* enumeration). */
14506 static const struct mips_cpu_info
*
14507 mips_cpu_info_from_isa (int isa
)
14511 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14512 if (mips_cpu_info_table
[i
].is_isa
14513 && isa
== mips_cpu_info_table
[i
].isa
)
14514 return (&mips_cpu_info_table
[i
]);
14519 static const struct mips_cpu_info
*
14520 mips_cpu_info_from_arch (int arch
)
14524 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14525 if (arch
== mips_cpu_info_table
[i
].cpu
)
14526 return (&mips_cpu_info_table
[i
]);
14532 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14536 fprintf (stream
, "%24s", "");
14541 fprintf (stream
, ", ");
14545 if (*col_p
+ strlen (string
) > 72)
14547 fprintf (stream
, "\n%24s", "");
14551 fprintf (stream
, "%s", string
);
14552 *col_p
+= strlen (string
);
14558 md_show_usage (FILE *stream
)
14563 fprintf (stream
, _("\
14565 -EB generate big endian output\n\
14566 -EL generate little endian output\n\
14567 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14568 -G NUM allow referencing objects up to NUM bytes\n\
14569 implicitly with the gp register [default 8]\n"));
14570 fprintf (stream
, _("\
14571 -mips1 generate MIPS ISA I instructions\n\
14572 -mips2 generate MIPS ISA II instructions\n\
14573 -mips3 generate MIPS ISA III instructions\n\
14574 -mips4 generate MIPS ISA IV instructions\n\
14575 -mips5 generate MIPS ISA V instructions\n\
14576 -mips32 generate MIPS32 ISA instructions\n\
14577 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14578 -mips64 generate MIPS64 ISA instructions\n\
14579 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14580 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14584 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14585 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14586 show (stream
, "from-abi", &column
, &first
);
14587 fputc ('\n', stream
);
14589 fprintf (stream
, _("\
14590 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14591 -no-mCPU don't generate code specific to CPU.\n\
14592 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14596 show (stream
, "3900", &column
, &first
);
14597 show (stream
, "4010", &column
, &first
);
14598 show (stream
, "4100", &column
, &first
);
14599 show (stream
, "4650", &column
, &first
);
14600 fputc ('\n', stream
);
14602 fprintf (stream
, _("\
14603 -mips16 generate mips16 instructions\n\
14604 -no-mips16 do not generate mips16 instructions\n"));
14605 fprintf (stream
, _("\
14606 -msmartmips generate smartmips instructions\n\
14607 -mno-smartmips do not generate smartmips instructions\n"));
14608 fprintf (stream
, _("\
14609 -mdsp generate DSP instructions\n\
14610 -mno-dsp do not generate DSP instructions\n"));
14611 fprintf (stream
, _("\
14612 -mmt generate MT instructions\n\
14613 -mno-mt do not generate MT instructions\n"));
14614 fprintf (stream
, _("\
14615 -mfix-vr4120 work around certain VR4120 errata\n\
14616 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14617 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14618 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14619 -mno-shared optimize output for executables\n\
14620 -msym32 assume all symbols have 32-bit values\n\
14621 -O0 remove unneeded NOPs, do not swap branches\n\
14622 -O remove unneeded NOPs and swap branches\n\
14623 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14624 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14625 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14627 fprintf (stream
, _("\
14628 -KPIC, -call_shared generate SVR4 position independent code\n\
14629 -non_shared do not generate position independent code\n\
14630 -xgot assume a 32 bit GOT\n\
14631 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14632 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14634 -mabi=ABI create ABI conformant object file for:\n"));
14638 show (stream
, "32", &column
, &first
);
14639 show (stream
, "o64", &column
, &first
);
14640 show (stream
, "n32", &column
, &first
);
14641 show (stream
, "64", &column
, &first
);
14642 show (stream
, "eabi", &column
, &first
);
14644 fputc ('\n', stream
);
14646 fprintf (stream
, _("\
14647 -32 create o32 ABI object file (default)\n\
14648 -n32 create n32 ABI object file\n\
14649 -64 create 64 ABI object file\n"));
14654 mips_dwarf2_format (void)
14656 if (mips_abi
== N64_ABI
)
14659 return dwarf2_format_64bit_irix
;
14661 return dwarf2_format_64bit
;
14665 return dwarf2_format_32bit
;
14669 mips_dwarf2_addr_size (void)
14671 if (mips_abi
== N64_ABI
)
14677 /* Standard calling conventions leave the CFA at SP on entry. */
14679 mips_cfi_frame_initial_instructions (void)
14681 cfi_add_CFA_def_cfa_register (SP
);