1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode
;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p
: 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p
: 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p
: 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p
: 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p
: 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi
= NO_ABI
;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls
= FALSE
;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared
= TRUE
;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
223 /* Whether we are assembling for the mips16 processor. 0 if we are
224 not, 1 if we are, and -1 if the value has not been initialized.
225 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
226 -nomips16 command line options, and the default CPU. */
228 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
229 1 if we are, and -1 if the value has not been initialized. Changed
230 by `.set micromips' and `.set nomicromips', and the -mmicromips
231 and -mno-micromips command line options, and the default CPU. */
233 /* Non-zero if we should not reorder instructions. Changed by `.set
234 reorder' and `.set noreorder'. */
236 /* Non-zero if we should not permit the register designated "assembler
237 temporary" to be used in instructions. The value is the register
238 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
239 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
241 /* Non-zero if we should warn when a macro instruction expands into
242 more than one machine instruction. Changed by `.set nomacro' and
244 int warn_about_macros
;
245 /* Non-zero if we should not move instructions. Changed by `.set
246 move', `.set volatile', `.set nomove', and `.set novolatile'. */
248 /* Non-zero if we should not optimize branches by moving the target
249 of the branch into the delay slot. Actually, we don't perform
250 this optimization anyhow. Changed by `.set bopt' and `.set
253 /* Non-zero if we should not autoextend mips16 instructions.
254 Changed by `.set autoextend' and `.set noautoextend'. */
256 /* Restrict general purpose registers and floating point registers
257 to 32 bit. This is initially determined when -mgp32 or -mfp32
258 is passed but can changed if the assembler code uses .set mipsN. */
261 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
262 command line option, and the default CPU. */
264 /* True if ".set sym32" is in effect. */
266 /* True if floating-point operations are not allowed. Changed by .set
267 softfloat or .set hardfloat, by command line options -msoft-float or
268 -mhard-float. The default is false. */
269 bfd_boolean soft_float
;
271 /* True if only single-precision floating-point operations are allowed.
272 Changed by .set singlefloat or .set doublefloat, command-line options
273 -msingle-float or -mdouble-float. The default is false. */
274 bfd_boolean single_float
;
277 /* This is the struct we use to hold the current set of options. Note
278 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
279 -1 to indicate that they have not been initialized. */
281 /* True if -mgp32 was passed. */
282 static int file_mips_gp32
= -1;
284 /* True if -mfp32 was passed. */
285 static int file_mips_fp32
= -1;
287 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
288 static int file_mips_soft_float
= 0;
290 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
291 static int file_mips_single_float
= 0;
293 static struct mips_set_options mips_opts
=
295 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
296 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1,
297 /* ase_eva */ -1, /* ase_mt */ -1, /* ase_mcu */ -1,
298 /* ase_virt */ -1, /* mips16 */ -1, /* micromips */ -1,
299 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
300 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
301 /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
302 /* soft_float */ FALSE
, /* single_float */ FALSE
305 /* These variables are filled in with the masks of registers used.
306 The object format code reads them and puts them in the appropriate
308 unsigned long mips_gprmask
;
309 unsigned long mips_cprmask
[4];
311 /* MIPS ISA we are using for this output file. */
312 static int file_mips_isa
= ISA_UNKNOWN
;
314 /* True if any MIPS16 code was produced. */
315 static int file_ase_mips16
;
317 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
318 || mips_opts.isa == ISA_MIPS32R2 \
319 || mips_opts.isa == ISA_MIPS64 \
320 || mips_opts.isa == ISA_MIPS64R2)
322 /* True if any microMIPS code was produced. */
323 static int file_ase_micromips
;
325 /* True if we want to create R_MIPS_JALR for jalr $25. */
327 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
329 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
330 because there's no place for any addend, the only acceptable
331 expression is a bare symbol. */
332 #define MIPS_JALR_HINT_P(EXPR) \
333 (!HAVE_IN_PLACE_ADDENDS \
334 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
337 /* True if -mips3d was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mips3d
;
341 /* True if -mdmx was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_mdmx
;
345 /* True if -msmartmips was passed or implied by arguments passed on the
346 command line (e.g., by -march). */
347 static int file_ase_smartmips
;
349 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
350 || mips_opts.isa == ISA_MIPS32R2)
352 /* True if -mdsp was passed or implied by arguments passed on the
353 command line (e.g., by -march). */
354 static int file_ase_dsp
;
356 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
357 || mips_opts.isa == ISA_MIPS64R2 \
358 || mips_opts.micromips)
360 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
362 /* True if -mdspr2 was passed or implied by arguments passed on the
363 command line (e.g., by -march). */
364 static int file_ase_dspr2
;
366 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
367 || mips_opts.isa == ISA_MIPS64R2 \
368 || mips_opts.micromips)
370 /* True if -meva was passed or implied by arguments passed on the
371 command line (e.g., by -march). */
372 static int file_ase_eva
;
374 #define ISA_SUPPORTS_EVA_ASE (mips_opts.isa == ISA_MIPS32R2 \
375 || mips_opts.isa == ISA_MIPS64R2 \
376 || mips_opts.micromips)
378 /* True if -mmt was passed or implied by arguments passed on the
379 command line (e.g., by -march). */
380 static int file_ase_mt
;
382 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
383 || mips_opts.isa == ISA_MIPS64R2)
385 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
386 || mips_opts.isa == ISA_MIPS64R2 \
387 || mips_opts.micromips)
389 /* True if -mvirt was passed or implied by arguments passed on the
390 command line (e.g., by -march). */
391 static int file_ase_virt
;
393 #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \
394 || mips_opts.isa == ISA_MIPS64R2 \
395 || mips_opts.micromips)
397 #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2 \
398 || (mips_opts.micromips \
399 && ISA_HAS_64BIT_REGS (mips_opts.isa)))
401 /* The argument of the -march= flag. The architecture we are assembling. */
402 static int file_mips_arch
= CPU_UNKNOWN
;
403 static const char *mips_arch_string
;
405 /* The argument of the -mtune= flag. The architecture for which we
407 static int mips_tune
= CPU_UNKNOWN
;
408 static const char *mips_tune_string
;
410 /* True when generating 32-bit code for a 64-bit processor. */
411 static int mips_32bitmode
= 0;
413 /* True if the given ABI requires 32-bit registers. */
414 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
416 /* Likewise 64-bit registers. */
417 #define ABI_NEEDS_64BIT_REGS(ABI) \
419 || (ABI) == N64_ABI \
422 /* Return true if ISA supports 64 bit wide gp registers. */
423 #define ISA_HAS_64BIT_REGS(ISA) \
424 ((ISA) == ISA_MIPS3 \
425 || (ISA) == ISA_MIPS4 \
426 || (ISA) == ISA_MIPS5 \
427 || (ISA) == ISA_MIPS64 \
428 || (ISA) == ISA_MIPS64R2)
430 /* Return true if ISA supports 64 bit wide float registers. */
431 #define ISA_HAS_64BIT_FPRS(ISA) \
432 ((ISA) == ISA_MIPS3 \
433 || (ISA) == ISA_MIPS4 \
434 || (ISA) == ISA_MIPS5 \
435 || (ISA) == ISA_MIPS32R2 \
436 || (ISA) == ISA_MIPS64 \
437 || (ISA) == ISA_MIPS64R2)
439 /* Return true if ISA supports 64-bit right rotate (dror et al.)
441 #define ISA_HAS_DROR(ISA) \
442 ((ISA) == ISA_MIPS64R2 \
443 || (mips_opts.micromips \
444 && ISA_HAS_64BIT_REGS (ISA)) \
447 /* Return true if ISA supports 32-bit right rotate (ror et al.)
449 #define ISA_HAS_ROR(ISA) \
450 ((ISA) == ISA_MIPS32R2 \
451 || (ISA) == ISA_MIPS64R2 \
452 || mips_opts.ase_smartmips \
453 || mips_opts.micromips \
456 /* Return true if ISA supports single-precision floats in odd registers. */
457 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
458 ((ISA) == ISA_MIPS32 \
459 || (ISA) == ISA_MIPS32R2 \
460 || (ISA) == ISA_MIPS64 \
461 || (ISA) == ISA_MIPS64R2)
463 /* Return true if ISA supports move to/from high part of a 64-bit
464 floating-point register. */
465 #define ISA_HAS_MXHC1(ISA) \
466 ((ISA) == ISA_MIPS32R2 \
467 || (ISA) == ISA_MIPS64R2)
469 #define HAVE_32BIT_GPRS \
470 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
472 #define HAVE_32BIT_FPRS \
473 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
475 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
476 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
478 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
480 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
482 /* True if relocations are stored in-place. */
483 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
485 /* The ABI-derived address size. */
486 #define HAVE_64BIT_ADDRESSES \
487 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
488 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
490 /* The size of symbolic constants (i.e., expressions of the form
491 "SYMBOL" or "SYMBOL + OFFSET"). */
492 #define HAVE_32BIT_SYMBOLS \
493 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
494 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
496 /* Addresses are loaded in different ways, depending on the address size
497 in use. The n32 ABI Documentation also mandates the use of additions
498 with overflow checking, but existing implementations don't follow it. */
499 #define ADDRESS_ADD_INSN \
500 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
502 #define ADDRESS_ADDI_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
505 #define ADDRESS_LOAD_INSN \
506 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
508 #define ADDRESS_STORE_INSN \
509 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
511 /* Return true if the given CPU supports the MIPS16 ASE. */
512 #define CPU_HAS_MIPS16(cpu) \
513 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
514 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
516 /* Return true if the given CPU supports the microMIPS ASE. */
517 #define CPU_HAS_MICROMIPS(cpu) 0
519 /* True if CPU has a dror instruction. */
520 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
522 /* True if CPU has a ror instruction. */
523 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
525 /* True if CPU is in the Octeon family */
526 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
528 /* True if CPU has seq/sne and seqi/snei instructions. */
529 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
531 /* True, if CPU has support for ldc1 and sdc1. */
532 #define CPU_HAS_LDC1_SDC1(CPU) \
533 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
535 /* True if mflo and mfhi can be immediately followed by instructions
536 which write to the HI and LO registers.
538 According to MIPS specifications, MIPS ISAs I, II, and III need
539 (at least) two instructions between the reads of HI/LO and
540 instructions which write them, and later ISAs do not. Contradicting
541 the MIPS specifications, some MIPS IV processor user manuals (e.g.
542 the UM for the NEC Vr5000) document needing the instructions between
543 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
544 MIPS64 and later ISAs to have the interlocks, plus any specific
545 earlier-ISA CPUs for which CPU documentation declares that the
546 instructions are really interlocked. */
547 #define hilo_interlocks \
548 (mips_opts.isa == ISA_MIPS32 \
549 || mips_opts.isa == ISA_MIPS32R2 \
550 || mips_opts.isa == ISA_MIPS64 \
551 || mips_opts.isa == ISA_MIPS64R2 \
552 || mips_opts.arch == CPU_R4010 \
553 || mips_opts.arch == CPU_R5900 \
554 || mips_opts.arch == CPU_R10000 \
555 || mips_opts.arch == CPU_R12000 \
556 || mips_opts.arch == CPU_R14000 \
557 || mips_opts.arch == CPU_R16000 \
558 || mips_opts.arch == CPU_RM7000 \
559 || mips_opts.arch == CPU_VR5500 \
560 || mips_opts.micromips \
563 /* Whether the processor uses hardware interlocks to protect reads
564 from the GPRs after they are loaded from memory, and thus does not
565 require nops to be inserted. This applies to instructions marked
566 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
567 level I and microMIPS mode instructions are always interlocked. */
568 #define gpr_interlocks \
569 (mips_opts.isa != ISA_MIPS1 \
570 || mips_opts.arch == CPU_R3900 \
571 || mips_opts.arch == CPU_R5900 \
572 || mips_opts.micromips \
575 /* Whether the processor uses hardware interlocks to avoid delays
576 required by coprocessor instructions, and thus does not require
577 nops to be inserted. This applies to instructions marked
578 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
579 between instructions marked INSN_WRITE_COND_CODE and ones marked
580 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
581 levels I, II, and III and microMIPS mode instructions are always
583 /* Itbl support may require additional care here. */
584 #define cop_interlocks \
585 ((mips_opts.isa != ISA_MIPS1 \
586 && mips_opts.isa != ISA_MIPS2 \
587 && mips_opts.isa != ISA_MIPS3) \
588 || mips_opts.arch == CPU_R4300 \
589 || mips_opts.micromips \
592 /* Whether the processor uses hardware interlocks to protect reads
593 from coprocessor registers after they are loaded from memory, and
594 thus does not require nops to be inserted. This applies to
595 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
596 requires at MIPS ISA level I and microMIPS mode instructions are
597 always interlocked. */
598 #define cop_mem_interlocks \
599 (mips_opts.isa != ISA_MIPS1 \
600 || mips_opts.micromips \
603 /* Is this a mfhi or mflo instruction? */
604 #define MF_HILO_INSN(PINFO) \
605 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
607 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
608 has been selected. This implies, in particular, that addresses of text
609 labels have their LSB set. */
610 #define HAVE_CODE_COMPRESSION \
611 ((mips_opts.mips16 | mips_opts.micromips) != 0)
613 /* MIPS PIC level. */
615 enum mips_pic_level mips_pic
;
617 /* 1 if we should generate 32 bit offsets from the $gp register in
618 SVR4_PIC mode. Currently has no meaning in other modes. */
619 static int mips_big_got
= 0;
621 /* 1 if trap instructions should used for overflow rather than break
623 static int mips_trap
= 0;
625 /* 1 if double width floating point constants should not be constructed
626 by assembling two single width halves into two single width floating
627 point registers which just happen to alias the double width destination
628 register. On some architectures this aliasing can be disabled by a bit
629 in the status register, and the setting of this bit cannot be determined
630 automatically at assemble time. */
631 static int mips_disable_float_construction
;
633 /* Non-zero if any .set noreorder directives were used. */
635 static int mips_any_noreorder
;
637 /* Non-zero if nops should be inserted when the register referenced in
638 an mfhi/mflo instruction is read in the next two instructions. */
639 static int mips_7000_hilo_fix
;
641 /* The size of objects in the small data section. */
642 static unsigned int g_switch_value
= 8;
643 /* Whether the -G option was used. */
644 static int g_switch_seen
= 0;
649 /* If we can determine in advance that GP optimization won't be
650 possible, we can skip the relaxation stuff that tries to produce
651 GP-relative references. This makes delay slot optimization work
654 This function can only provide a guess, but it seems to work for
655 gcc output. It needs to guess right for gcc, otherwise gcc
656 will put what it thinks is a GP-relative instruction in a branch
659 I don't know if a fix is needed for the SVR4_PIC mode. I've only
660 fixed it for the non-PIC mode. KR 95/04/07 */
661 static int nopic_need_relax (symbolS
*, int);
663 /* handle of the OPCODE hash table */
664 static struct hash_control
*op_hash
= NULL
;
666 /* The opcode hash table we use for the mips16. */
667 static struct hash_control
*mips16_op_hash
= NULL
;
669 /* The opcode hash table we use for the microMIPS ASE. */
670 static struct hash_control
*micromips_op_hash
= NULL
;
672 /* This array holds the chars that always start a comment. If the
673 pre-processor is disabled, these aren't very useful */
674 const char comment_chars
[] = "#";
676 /* This array holds the chars that only start a comment at the beginning of
677 a line. If the line seems to have the form '# 123 filename'
678 .line and .file directives will appear in the pre-processed output */
679 /* Note that input_file.c hand checks for '#' at the beginning of the
680 first line of the input file. This is because the compiler outputs
681 #NO_APP at the beginning of its output. */
682 /* Also note that C style comments are always supported. */
683 const char line_comment_chars
[] = "#";
685 /* This array holds machine specific line separator characters. */
686 const char line_separator_chars
[] = ";";
688 /* Chars that can be used to separate mant from exp in floating point nums */
689 const char EXP_CHARS
[] = "eE";
691 /* Chars that mean this number is a floating point constant */
694 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
696 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
697 changed in read.c . Ideally it shouldn't have to know about it at all,
698 but nothing is ideal around here.
701 static char *insn_error
;
703 static int auto_align
= 1;
705 /* When outputting SVR4 PIC code, the assembler needs to know the
706 offset in the stack frame from which to restore the $gp register.
707 This is set by the .cprestore pseudo-op, and saved in this
709 static offsetT mips_cprestore_offset
= -1;
711 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
712 more optimizations, it can use a register value instead of a memory-saved
713 offset and even an other register than $gp as global pointer. */
714 static offsetT mips_cpreturn_offset
= -1;
715 static int mips_cpreturn_register
= -1;
716 static int mips_gp_register
= GP
;
717 static int mips_gprel_offset
= 0;
719 /* Whether mips_cprestore_offset has been set in the current function
720 (or whether it has already been warned about, if not). */
721 static int mips_cprestore_valid
= 0;
723 /* This is the register which holds the stack frame, as set by the
724 .frame pseudo-op. This is needed to implement .cprestore. */
725 static int mips_frame_reg
= SP
;
727 /* Whether mips_frame_reg has been set in the current function
728 (or whether it has already been warned about, if not). */
729 static int mips_frame_reg_valid
= 0;
731 /* To output NOP instructions correctly, we need to keep information
732 about the previous two instructions. */
734 /* Whether we are optimizing. The default value of 2 means to remove
735 unneeded NOPs and swap branch instructions when possible. A value
736 of 1 means to not swap branches. A value of 0 means to always
738 static int mips_optimize
= 2;
740 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
741 equivalent to seeing no -g option at all. */
742 static int mips_debug
= 0;
744 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
745 #define MAX_VR4130_NOPS 4
747 /* The maximum number of NOPs needed to fill delay slots. */
748 #define MAX_DELAY_NOPS 2
750 /* The maximum number of NOPs needed for any purpose. */
753 /* A list of previous instructions, with index 0 being the most recent.
754 We need to look back MAX_NOPS instructions when filling delay slots
755 or working around processor errata. We need to look back one
756 instruction further if we're thinking about using history[0] to
757 fill a branch delay slot. */
758 static struct mips_cl_insn history
[1 + MAX_NOPS
];
760 /* Nop instructions used by emit_nop. */
761 static struct mips_cl_insn nop_insn
;
762 static struct mips_cl_insn mips16_nop_insn
;
763 static struct mips_cl_insn micromips_nop16_insn
;
764 static struct mips_cl_insn micromips_nop32_insn
;
766 /* The appropriate nop for the current mode. */
767 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
768 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
770 /* The size of NOP_INSN in bytes. */
771 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
773 /* If this is set, it points to a frag holding nop instructions which
774 were inserted before the start of a noreorder section. If those
775 nops turn out to be unnecessary, the size of the frag can be
777 static fragS
*prev_nop_frag
;
779 /* The number of nop instructions we created in prev_nop_frag. */
780 static int prev_nop_frag_holds
;
782 /* The number of nop instructions that we know we need in
784 static int prev_nop_frag_required
;
786 /* The number of instructions we've seen since prev_nop_frag. */
787 static int prev_nop_frag_since
;
789 /* For ECOFF and ELF, relocations against symbols are done in two
790 parts, with a HI relocation and a LO relocation. Each relocation
791 has only 16 bits of space to store an addend. This means that in
792 order for the linker to handle carries correctly, it must be able
793 to locate both the HI and the LO relocation. This means that the
794 relocations must appear in order in the relocation table.
796 In order to implement this, we keep track of each unmatched HI
797 relocation. We then sort them so that they immediately precede the
798 corresponding LO relocation. */
803 struct mips_hi_fixup
*next
;
806 /* The section this fixup is in. */
810 /* The list of unmatched HI relocs. */
812 static struct mips_hi_fixup
*mips_hi_fixup_list
;
814 /* The frag containing the last explicit relocation operator.
815 Null if explicit relocations have not been used. */
817 static fragS
*prev_reloc_op_frag
;
819 /* Map normal MIPS register numbers to mips16 register numbers. */
821 #define X ILLEGAL_REG
822 static const int mips32_to_16_reg_map
[] =
824 X
, X
, 2, 3, 4, 5, 6, 7,
825 X
, X
, X
, X
, X
, X
, X
, X
,
826 0, 1, X
, X
, X
, X
, X
, X
,
827 X
, X
, X
, X
, X
, X
, X
, X
831 /* Map mips16 register numbers to normal MIPS register numbers. */
833 static const unsigned int mips16_to_32_reg_map
[] =
835 16, 17, 2, 3, 4, 5, 6, 7
838 /* Map normal MIPS register numbers to microMIPS register numbers. */
840 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
841 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
842 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
843 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
844 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
845 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
846 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
848 #define X ILLEGAL_REG
849 /* reg type h: 4, 5, 6. */
850 static const int mips32_to_micromips_reg_h_map
[] =
852 X
, X
, X
, X
, 4, 5, 6, X
,
853 X
, X
, X
, X
, X
, X
, X
, X
,
854 X
, X
, X
, X
, X
, X
, X
, X
,
855 X
, X
, X
, X
, X
, X
, X
, X
858 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
859 static const int mips32_to_micromips_reg_m_map
[] =
861 0, X
, 2, 3, X
, X
, X
, X
,
862 X
, X
, X
, X
, X
, X
, X
, X
,
863 4, 1, 5, 6, 7, X
, X
, X
,
864 X
, X
, X
, X
, X
, X
, X
, X
867 /* reg type q: 0, 2-7. 17. */
868 static const int mips32_to_micromips_reg_q_map
[] =
870 0, X
, 2, 3, 4, 5, 6, 7,
871 X
, X
, X
, X
, X
, X
, X
, X
,
872 X
, 1, X
, X
, X
, X
, X
, X
,
873 X
, X
, X
, X
, X
, X
, X
, X
876 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
879 /* Map microMIPS register numbers to normal MIPS register numbers. */
881 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
882 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
883 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
884 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
885 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
886 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
888 /* The microMIPS registers with type h. */
889 static const unsigned int micromips_to_32_reg_h_map
[] =
891 5, 5, 6, 4, 4, 4, 4, 4
894 /* The microMIPS registers with type i. */
895 static const unsigned int micromips_to_32_reg_i_map
[] =
897 6, 7, 7, 21, 22, 5, 6, 7
900 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
902 /* The microMIPS registers with type m. */
903 static const unsigned int micromips_to_32_reg_m_map
[] =
905 0, 17, 2, 3, 16, 18, 19, 20
908 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
910 /* The microMIPS registers with type q. */
911 static const unsigned int micromips_to_32_reg_q_map
[] =
913 0, 17, 2, 3, 4, 5, 6, 7
916 /* microMIPS imm type B. */
917 static const int micromips_imm_b_map
[] =
919 1, 4, 8, 12, 16, 20, 24, -1
922 /* microMIPS imm type C. */
923 static const int micromips_imm_c_map
[] =
925 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
928 /* Classifies the kind of instructions we're interested in when
929 implementing -mfix-vr4120. */
930 enum fix_vr4120_class
938 NUM_FIX_VR4120_CLASSES
941 /* ...likewise -mfix-loongson2f-jump. */
942 static bfd_boolean mips_fix_loongson2f_jump
;
944 /* ...likewise -mfix-loongson2f-nop. */
945 static bfd_boolean mips_fix_loongson2f_nop
;
947 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
948 static bfd_boolean mips_fix_loongson2f
;
950 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
951 there must be at least one other instruction between an instruction
952 of type X and an instruction of type Y. */
953 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
955 /* True if -mfix-vr4120 is in force. */
956 static int mips_fix_vr4120
;
958 /* ...likewise -mfix-vr4130. */
959 static int mips_fix_vr4130
;
961 /* ...likewise -mfix-24k. */
962 static int mips_fix_24k
;
964 /* ...likewise -mfix-cn63xxp1 */
965 static bfd_boolean mips_fix_cn63xxp1
;
967 /* We don't relax branches by default, since this causes us to expand
968 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
969 fail to compute the offset before expanding the macro to the most
970 efficient expansion. */
972 static int mips_relax_branch
;
974 /* The expansion of many macros depends on the type of symbol that
975 they refer to. For example, when generating position-dependent code,
976 a macro that refers to a symbol may have two different expansions,
977 one which uses GP-relative addresses and one which uses absolute
978 addresses. When generating SVR4-style PIC, a macro may have
979 different expansions for local and global symbols.
981 We handle these situations by generating both sequences and putting
982 them in variant frags. In position-dependent code, the first sequence
983 will be the GP-relative one and the second sequence will be the
984 absolute one. In SVR4 PIC, the first sequence will be for global
985 symbols and the second will be for local symbols.
987 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
988 SECOND are the lengths of the two sequences in bytes. These fields
989 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
990 the subtype has the following flags:
993 Set if it has been decided that we should use the second
994 sequence instead of the first.
997 Set in the first variant frag if the macro's second implementation
998 is longer than its first. This refers to the macro as a whole,
999 not an individual relaxation.
1002 Set in the first variant frag if the macro appeared in a .set nomacro
1003 block and if one alternative requires a warning but the other does not.
1006 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1009 RELAX_DELAY_SLOT_16BIT
1010 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1013 RELAX_DELAY_SLOT_SIZE_FIRST
1014 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1015 the macro is of the wrong size for the branch delay slot.
1017 RELAX_DELAY_SLOT_SIZE_SECOND
1018 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1019 the macro is of the wrong size for the branch delay slot.
1021 The frag's "opcode" points to the first fixup for relaxable code.
1023 Relaxable macros are generated using a sequence such as:
1025 relax_start (SYMBOL);
1026 ... generate first expansion ...
1028 ... generate second expansion ...
1031 The code and fixups for the unwanted alternative are discarded
1032 by md_convert_frag. */
1033 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1035 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1036 #define RELAX_SECOND(X) ((X) & 0xff)
1037 #define RELAX_USE_SECOND 0x10000
1038 #define RELAX_SECOND_LONGER 0x20000
1039 #define RELAX_NOMACRO 0x40000
1040 #define RELAX_DELAY_SLOT 0x80000
1041 #define RELAX_DELAY_SLOT_16BIT 0x100000
1042 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1043 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1045 /* Branch without likely bit. If label is out of range, we turn:
1047 beq reg1, reg2, label
1057 with the following opcode replacements:
1064 bltzal <-> bgezal (with jal label instead of j label)
1066 Even though keeping the delay slot instruction in the delay slot of
1067 the branch would be more efficient, it would be very tricky to do
1068 correctly, because we'd have to introduce a variable frag *after*
1069 the delay slot instruction, and expand that instead. Let's do it
1070 the easy way for now, even if the branch-not-taken case now costs
1071 one additional instruction. Out-of-range branches are not supposed
1072 to be common, anyway.
1074 Branch likely. If label is out of range, we turn:
1076 beql reg1, reg2, label
1077 delay slot (annulled if branch not taken)
1086 delay slot (executed only if branch taken)
1089 It would be possible to generate a shorter sequence by losing the
1090 likely bit, generating something like:
1095 delay slot (executed only if branch taken)
1107 bltzall -> bgezal (with jal label instead of j label)
1108 bgezall -> bltzal (ditto)
1111 but it's not clear that it would actually improve performance. */
1112 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1113 ((relax_substateT) \
1116 | ((toofar) ? 0x20 : 0) \
1117 | ((link) ? 0x40 : 0) \
1118 | ((likely) ? 0x80 : 0) \
1119 | ((uncond) ? 0x100 : 0)))
1120 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1121 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1122 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1123 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1124 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1125 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1127 /* For mips16 code, we use an entirely different form of relaxation.
1128 mips16 supports two versions of most instructions which take
1129 immediate values: a small one which takes some small value, and a
1130 larger one which takes a 16 bit value. Since branches also follow
1131 this pattern, relaxing these values is required.
1133 We can assemble both mips16 and normal MIPS code in a single
1134 object. Therefore, we need to support this type of relaxation at
1135 the same time that we support the relaxation described above. We
1136 use the high bit of the subtype field to distinguish these cases.
1138 The information we store for this type of relaxation is the
1139 argument code found in the opcode file for this relocation, whether
1140 the user explicitly requested a small or extended form, and whether
1141 the relocation is in a jump or jal delay slot. That tells us the
1142 size of the value, and how it should be stored. We also store
1143 whether the fragment is considered to be extended or not. We also
1144 store whether this is known to be a branch to a different section,
1145 whether we have tried to relax this frag yet, and whether we have
1146 ever extended a PC relative fragment because of a shift count. */
1147 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1150 | ((small) ? 0x100 : 0) \
1151 | ((ext) ? 0x200 : 0) \
1152 | ((dslot) ? 0x400 : 0) \
1153 | ((jal_dslot) ? 0x800 : 0))
1154 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1155 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1156 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1157 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1158 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1159 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1160 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1161 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1162 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1163 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1164 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1165 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1167 /* For microMIPS code, we use relaxation similar to one we use for
1168 MIPS16 code. Some instructions that take immediate values support
1169 two encodings: a small one which takes some small value, and a
1170 larger one which takes a 16 bit value. As some branches also follow
1171 this pattern, relaxing these values is required.
1173 We can assemble both microMIPS and normal MIPS code in a single
1174 object. Therefore, we need to support this type of relaxation at
1175 the same time that we support the relaxation described above. We
1176 use one of the high bits of the subtype field to distinguish these
1179 The information we store for this type of relaxation is the argument
1180 code found in the opcode file for this relocation, the register
1181 selected as the assembler temporary, whether the branch is
1182 unconditional, whether it is compact, whether it stores the link
1183 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1184 branches to a sequence of instructions is enabled, and whether the
1185 displacement of a branch is too large to fit as an immediate argument
1186 of a 16-bit and a 32-bit branch, respectively. */
1187 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1188 relax32, toofar16, toofar32) \
1191 | (((at) & 0x1f) << 8) \
1192 | ((uncond) ? 0x2000 : 0) \
1193 | ((compact) ? 0x4000 : 0) \
1194 | ((link) ? 0x8000 : 0) \
1195 | ((relax32) ? 0x10000 : 0) \
1196 | ((toofar16) ? 0x20000 : 0) \
1197 | ((toofar32) ? 0x40000 : 0))
1198 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1199 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1200 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1201 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1202 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1203 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1204 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1206 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1207 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1208 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1209 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1210 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1211 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1213 /* Sign-extend 16-bit value X. */
1214 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1216 /* Is the given value a sign-extended 32-bit value? */
1217 #define IS_SEXT_32BIT_NUM(x) \
1218 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1219 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1221 /* Is the given value a sign-extended 16-bit value? */
1222 #define IS_SEXT_16BIT_NUM(x) \
1223 (((x) &~ (offsetT) 0x7fff) == 0 \
1224 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1226 /* Is the given value a sign-extended 12-bit value? */
1227 #define IS_SEXT_12BIT_NUM(x) \
1228 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1230 /* Is the given value a sign-extended 9-bit value? */
1231 #define IS_SEXT_9BIT_NUM(x) \
1232 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1234 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1235 #define IS_ZEXT_32BIT_NUM(x) \
1236 (((x) &~ (offsetT) 0xffffffff) == 0 \
1237 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1239 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1240 VALUE << SHIFT. VALUE is evaluated exactly once. */
1241 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1242 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1243 | (((VALUE) & (MASK)) << (SHIFT)))
1245 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1247 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1248 (((STRUCT) >> (SHIFT)) & (MASK))
1250 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1251 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1253 include/opcode/mips.h specifies operand fields using the macros
1254 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1255 with "MIPS16OP" instead of "OP". */
1256 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1259 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1260 OP_MASK_##FIELD, OP_SH_##FIELD); \
1262 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1263 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1265 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1266 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1267 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1269 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1270 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1272 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1273 : EXTRACT_BITS ((INSN).insn_opcode, \
1274 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1275 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1276 EXTRACT_BITS ((INSN).insn_opcode, \
1277 MIPS16OP_MASK_##FIELD, \
1278 MIPS16OP_SH_##FIELD)
1280 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1281 #define MIPS16_EXTEND (0xf000U << 16)
1283 /* Whether or not we are emitting a branch-likely macro. */
1284 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1286 /* Global variables used when generating relaxable macros. See the
1287 comment above RELAX_ENCODE for more details about how relaxation
1290 /* 0 if we're not emitting a relaxable macro.
1291 1 if we're emitting the first of the two relaxation alternatives.
1292 2 if we're emitting the second alternative. */
1295 /* The first relaxable fixup in the current frag. (In other words,
1296 the first fixup that refers to relaxable code.) */
1299 /* sizes[0] says how many bytes of the first alternative are stored in
1300 the current frag. Likewise sizes[1] for the second alternative. */
1301 unsigned int sizes
[2];
1303 /* The symbol on which the choice of sequence depends. */
1307 /* Global variables used to decide whether a macro needs a warning. */
1309 /* True if the macro is in a branch delay slot. */
1310 bfd_boolean delay_slot_p
;
1312 /* Set to the length in bytes required if the macro is in a delay slot
1313 that requires a specific length of instruction, otherwise zero. */
1314 unsigned int delay_slot_length
;
1316 /* For relaxable macros, sizes[0] is the length of the first alternative
1317 in bytes and sizes[1] is the length of the second alternative.
1318 For non-relaxable macros, both elements give the length of the
1320 unsigned int sizes
[2];
1322 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1323 instruction of the first alternative in bytes and first_insn_sizes[1]
1324 is the length of the first instruction of the second alternative.
1325 For non-relaxable macros, both elements give the length of the first
1326 instruction in bytes.
1328 Set to zero if we haven't yet seen the first instruction. */
1329 unsigned int first_insn_sizes
[2];
1331 /* For relaxable macros, insns[0] is the number of instructions for the
1332 first alternative and insns[1] is the number of instructions for the
1335 For non-relaxable macros, both elements give the number of
1336 instructions for the macro. */
1337 unsigned int insns
[2];
1339 /* The first variant frag for this macro. */
1341 } mips_macro_warning
;
1343 /* Prototypes for static functions. */
1345 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1347 static void append_insn
1348 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1349 bfd_boolean expansionp
);
1350 static void mips_no_prev_insn (void);
1351 static void macro_build (expressionS
*, const char *, const char *, ...);
1352 static void mips16_macro_build
1353 (expressionS
*, const char *, const char *, va_list *);
1354 static void load_register (int, expressionS
*, int);
1355 static void macro_start (void);
1356 static void macro_end (void);
1357 static void macro (struct mips_cl_insn
* ip
);
1358 static void mips16_macro (struct mips_cl_insn
* ip
);
1359 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1360 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1361 static void mips16_immed
1362 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1363 unsigned int, unsigned long *);
1364 static size_t my_getSmallExpression
1365 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1366 static void my_getExpression (expressionS
*, char *);
1367 static void s_align (int);
1368 static void s_change_sec (int);
1369 static void s_change_section (int);
1370 static void s_cons (int);
1371 static void s_float_cons (int);
1372 static void s_mips_globl (int);
1373 static void s_option (int);
1374 static void s_mipsset (int);
1375 static void s_abicalls (int);
1376 static void s_cpload (int);
1377 static void s_cpsetup (int);
1378 static void s_cplocal (int);
1379 static void s_cprestore (int);
1380 static void s_cpreturn (int);
1381 static void s_dtprelword (int);
1382 static void s_dtpreldword (int);
1383 static void s_tprelword (int);
1384 static void s_tpreldword (int);
1385 static void s_gpvalue (int);
1386 static void s_gpword (int);
1387 static void s_gpdword (int);
1388 static void s_ehword (int);
1389 static void s_cpadd (int);
1390 static void s_insn (int);
1391 static void md_obj_begin (void);
1392 static void md_obj_end (void);
1393 static void s_mips_ent (int);
1394 static void s_mips_end (int);
1395 static void s_mips_frame (int);
1396 static void s_mips_mask (int reg_type
);
1397 static void s_mips_stab (int);
1398 static void s_mips_weakext (int);
1399 static void s_mips_file (int);
1400 static void s_mips_loc (int);
1401 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1402 static int relaxed_branch_length (fragS
*, asection
*, int);
1403 static int validate_mips_insn (const struct mips_opcode
*);
1404 static int validate_micromips_insn (const struct mips_opcode
*);
1405 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1406 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1408 /* Table and functions used to map between CPU/ISA names, and
1409 ISA levels, and CPU numbers. */
1411 struct mips_cpu_info
1413 const char *name
; /* CPU or ISA name. */
1414 int flags
; /* ASEs available, or ISA flag. */
1415 int isa
; /* ISA level. */
1416 int cpu
; /* CPU number (default CPU if ISA). */
1419 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1420 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1421 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1422 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1423 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1424 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1425 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1426 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1427 #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */
1428 #define MIPS_CPU_ASE_EVA 0x0200 /* CPU implements EVA ASE */
1430 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1431 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1432 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1436 The following pseudo-ops from the Kane and Heinrich MIPS book
1437 should be defined here, but are currently unsupported: .alias,
1438 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1440 The following pseudo-ops from the Kane and Heinrich MIPS book are
1441 specific to the type of debugging information being generated, and
1442 should be defined by the object format: .aent, .begin, .bend,
1443 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1446 The following pseudo-ops from the Kane and Heinrich MIPS book are
1447 not MIPS CPU specific, but are also not specific to the object file
1448 format. This file is probably the best place to define them, but
1449 they are not currently supported: .asm0, .endr, .lab, .struct. */
1451 static const pseudo_typeS mips_pseudo_table
[] =
1453 /* MIPS specific pseudo-ops. */
1454 {"option", s_option
, 0},
1455 {"set", s_mipsset
, 0},
1456 {"rdata", s_change_sec
, 'r'},
1457 {"sdata", s_change_sec
, 's'},
1458 {"livereg", s_ignore
, 0},
1459 {"abicalls", s_abicalls
, 0},
1460 {"cpload", s_cpload
, 0},
1461 {"cpsetup", s_cpsetup
, 0},
1462 {"cplocal", s_cplocal
, 0},
1463 {"cprestore", s_cprestore
, 0},
1464 {"cpreturn", s_cpreturn
, 0},
1465 {"dtprelword", s_dtprelword
, 0},
1466 {"dtpreldword", s_dtpreldword
, 0},
1467 {"tprelword", s_tprelword
, 0},
1468 {"tpreldword", s_tpreldword
, 0},
1469 {"gpvalue", s_gpvalue
, 0},
1470 {"gpword", s_gpword
, 0},
1471 {"gpdword", s_gpdword
, 0},
1472 {"ehword", s_ehword
, 0},
1473 {"cpadd", s_cpadd
, 0},
1474 {"insn", s_insn
, 0},
1476 /* Relatively generic pseudo-ops that happen to be used on MIPS
1478 {"asciiz", stringer
, 8 + 1},
1479 {"bss", s_change_sec
, 'b'},
1481 {"half", s_cons
, 1},
1482 {"dword", s_cons
, 3},
1483 {"weakext", s_mips_weakext
, 0},
1484 {"origin", s_org
, 0},
1485 {"repeat", s_rept
, 0},
1487 /* For MIPS this is non-standard, but we define it for consistency. */
1488 {"sbss", s_change_sec
, 'B'},
1490 /* These pseudo-ops are defined in read.c, but must be overridden
1491 here for one reason or another. */
1492 {"align", s_align
, 0},
1493 {"byte", s_cons
, 0},
1494 {"data", s_change_sec
, 'd'},
1495 {"double", s_float_cons
, 'd'},
1496 {"float", s_float_cons
, 'f'},
1497 {"globl", s_mips_globl
, 0},
1498 {"global", s_mips_globl
, 0},
1499 {"hword", s_cons
, 1},
1501 {"long", s_cons
, 2},
1502 {"octa", s_cons
, 4},
1503 {"quad", s_cons
, 3},
1504 {"section", s_change_section
, 0},
1505 {"short", s_cons
, 1},
1506 {"single", s_float_cons
, 'f'},
1507 {"stabd", s_mips_stab
, 'd'},
1508 {"stabn", s_mips_stab
, 'n'},
1509 {"stabs", s_mips_stab
, 's'},
1510 {"text", s_change_sec
, 't'},
1511 {"word", s_cons
, 2},
1513 { "extern", ecoff_directive_extern
, 0},
1518 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1520 /* These pseudo-ops should be defined by the object file format.
1521 However, a.out doesn't support them, so we have versions here. */
1522 {"aent", s_mips_ent
, 1},
1523 {"bgnb", s_ignore
, 0},
1524 {"end", s_mips_end
, 0},
1525 {"endb", s_ignore
, 0},
1526 {"ent", s_mips_ent
, 0},
1527 {"file", s_mips_file
, 0},
1528 {"fmask", s_mips_mask
, 'F'},
1529 {"frame", s_mips_frame
, 0},
1530 {"loc", s_mips_loc
, 0},
1531 {"mask", s_mips_mask
, 'R'},
1532 {"verstamp", s_ignore
, 0},
1536 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1537 purpose of the `.dc.a' internal pseudo-op. */
1540 mips_address_bytes (void)
1542 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1545 extern void pop_insert (const pseudo_typeS
*);
1548 mips_pop_insert (void)
1550 pop_insert (mips_pseudo_table
);
1551 if (! ECOFF_DEBUGGING
)
1552 pop_insert (mips_nonecoff_pseudo_table
);
1555 /* Symbols labelling the current insn. */
1557 struct insn_label_list
1559 struct insn_label_list
*next
;
1563 static struct insn_label_list
*free_insn_labels
;
1564 #define label_list tc_segment_info_data.labels
1566 static void mips_clear_insn_labels (void);
1567 static void mips_mark_labels (void);
1568 static void mips_compressed_mark_labels (void);
1571 mips_clear_insn_labels (void)
1573 register struct insn_label_list
**pl
;
1574 segment_info_type
*si
;
1578 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1581 si
= seg_info (now_seg
);
1582 *pl
= si
->label_list
;
1583 si
->label_list
= NULL
;
1587 /* Mark instruction labels in MIPS16/microMIPS mode. */
1590 mips_mark_labels (void)
1592 if (HAVE_CODE_COMPRESSION
)
1593 mips_compressed_mark_labels ();
1596 static char *expr_end
;
1598 /* Expressions which appear in instructions. These are set by
1601 static expressionS imm_expr
;
1602 static expressionS imm2_expr
;
1603 static expressionS offset_expr
;
1605 /* Relocs associated with imm_expr and offset_expr. */
1607 static bfd_reloc_code_real_type imm_reloc
[3]
1608 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1609 static bfd_reloc_code_real_type offset_reloc
[3]
1610 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1612 /* This is set to the resulting size of the instruction to be produced
1613 by mips16_ip if an explicit extension is used or by mips_ip if an
1614 explicit size is supplied. */
1616 static unsigned int forced_insn_length
;
1618 /* True if we are assembling an instruction. All dot symbols defined during
1619 this time should be treated as code labels. */
1621 static bfd_boolean mips_assembling_insn
;
1624 /* The pdr segment for per procedure frame/regmask info. Not used for
1627 static segT pdr_seg
;
1630 /* The default target format to use. */
1632 #if defined (TE_FreeBSD)
1633 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1634 #elif defined (TE_TMIPS)
1635 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1637 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1641 mips_target_format (void)
1643 switch (OUTPUT_FLAVOR
)
1645 case bfd_target_ecoff_flavour
:
1646 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1647 case bfd_target_coff_flavour
:
1649 case bfd_target_elf_flavour
:
1651 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1652 return (target_big_endian
1653 ? "elf32-bigmips-vxworks"
1654 : "elf32-littlemips-vxworks");
1656 return (target_big_endian
1657 ? (HAVE_64BIT_OBJECTS
1658 ? ELF_TARGET ("elf64-", "big")
1660 ? ELF_TARGET ("elf32-n", "big")
1661 : ELF_TARGET ("elf32-", "big")))
1662 : (HAVE_64BIT_OBJECTS
1663 ? ELF_TARGET ("elf64-", "little")
1665 ? ELF_TARGET ("elf32-n", "little")
1666 : ELF_TARGET ("elf32-", "little"))));
1673 /* Return the length of a microMIPS instruction in bytes. If bits of
1674 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1675 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1676 major opcode) will require further modifications to the opcode
1679 static inline unsigned int
1680 micromips_insn_length (const struct mips_opcode
*mo
)
1682 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1685 /* Return the length of MIPS16 instruction OPCODE. */
1687 static inline unsigned int
1688 mips16_opcode_length (unsigned long opcode
)
1690 return (opcode
>> 16) == 0 ? 2 : 4;
1693 /* Return the length of instruction INSN. */
1695 static inline unsigned int
1696 insn_length (const struct mips_cl_insn
*insn
)
1698 if (mips_opts
.micromips
)
1699 return micromips_insn_length (insn
->insn_mo
);
1700 else if (mips_opts
.mips16
)
1701 return mips16_opcode_length (insn
->insn_opcode
);
1706 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1709 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1714 insn
->insn_opcode
= mo
->match
;
1717 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1718 insn
->fixp
[i
] = NULL
;
1719 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1720 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1721 insn
->mips16_absolute_jump_p
= 0;
1722 insn
->complete_p
= 0;
1723 insn
->cleared_p
= 0;
1726 /* Record the current MIPS16/microMIPS mode in now_seg. */
1729 mips_record_compressed_mode (void)
1731 segment_info_type
*si
;
1733 si
= seg_info (now_seg
);
1734 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1735 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1736 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1737 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1740 /* Read a standard MIPS instruction from BUF. */
1742 static unsigned long
1743 read_insn (char *buf
)
1745 if (target_big_endian
)
1746 return bfd_getb32 ((bfd_byte
*) buf
);
1748 return bfd_getl32 ((bfd_byte
*) buf
);
1751 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1755 write_insn (char *buf
, unsigned int insn
)
1757 md_number_to_chars (buf
, insn
, 4);
1761 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1762 has length LENGTH. */
1764 static unsigned long
1765 read_compressed_insn (char *buf
, unsigned int length
)
1771 for (i
= 0; i
< length
; i
+= 2)
1774 if (target_big_endian
)
1775 insn
|= bfd_getb16 ((char *) buf
);
1777 insn
|= bfd_getl16 ((char *) buf
);
1783 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1784 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1787 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
1791 for (i
= 0; i
< length
; i
+= 2)
1792 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
1793 return buf
+ length
;
1796 /* Install INSN at the location specified by its "frag" and "where" fields. */
1799 install_insn (const struct mips_cl_insn
*insn
)
1801 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1802 if (HAVE_CODE_COMPRESSION
)
1803 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
1805 write_insn (f
, insn
->insn_opcode
);
1806 mips_record_compressed_mode ();
1809 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1810 and install the opcode in the new location. */
1813 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1818 insn
->where
= where
;
1819 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1820 if (insn
->fixp
[i
] != NULL
)
1822 insn
->fixp
[i
]->fx_frag
= frag
;
1823 insn
->fixp
[i
]->fx_where
= where
;
1825 install_insn (insn
);
1828 /* Add INSN to the end of the output. */
1831 add_fixed_insn (struct mips_cl_insn
*insn
)
1833 char *f
= frag_more (insn_length (insn
));
1834 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1837 /* Start a variant frag and move INSN to the start of the variant part,
1838 marking it as fixed. The other arguments are as for frag_var. */
1841 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1842 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1844 frag_grow (max_chars
);
1845 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1847 frag_var (rs_machine_dependent
, max_chars
, var
,
1848 subtype
, symbol
, offset
, NULL
);
1851 /* Insert N copies of INSN into the history buffer, starting at
1852 position FIRST. Neither FIRST nor N need to be clipped. */
1855 insert_into_history (unsigned int first
, unsigned int n
,
1856 const struct mips_cl_insn
*insn
)
1858 if (mips_relax
.sequence
!= 2)
1862 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1864 history
[i
] = history
[i
- n
];
1870 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1871 the idea is to make it obvious at a glance that each errata is
1875 init_vr4120_conflicts (void)
1877 #define CONFLICT(FIRST, SECOND) \
1878 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1880 /* Errata 21 - [D]DIV[U] after [D]MACC */
1881 CONFLICT (MACC
, DIV
);
1882 CONFLICT (DMACC
, DIV
);
1884 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1885 CONFLICT (DMULT
, DMULT
);
1886 CONFLICT (DMULT
, DMACC
);
1887 CONFLICT (DMACC
, DMULT
);
1888 CONFLICT (DMACC
, DMACC
);
1890 /* Errata 24 - MT{LO,HI} after [D]MACC */
1891 CONFLICT (MACC
, MTHILO
);
1892 CONFLICT (DMACC
, MTHILO
);
1894 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1895 instruction is executed immediately after a MACC or DMACC
1896 instruction, the result of [either instruction] is incorrect." */
1897 CONFLICT (MACC
, MULT
);
1898 CONFLICT (MACC
, DMULT
);
1899 CONFLICT (DMACC
, MULT
);
1900 CONFLICT (DMACC
, DMULT
);
1902 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1903 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1904 DDIV or DDIVU instruction, the result of the MACC or
1905 DMACC instruction is incorrect.". */
1906 CONFLICT (DMULT
, MACC
);
1907 CONFLICT (DMULT
, DMACC
);
1908 CONFLICT (DIV
, MACC
);
1909 CONFLICT (DIV
, DMACC
);
1919 #define RTYPE_MASK 0x1ff00
1920 #define RTYPE_NUM 0x00100
1921 #define RTYPE_FPU 0x00200
1922 #define RTYPE_FCC 0x00400
1923 #define RTYPE_VEC 0x00800
1924 #define RTYPE_GP 0x01000
1925 #define RTYPE_CP0 0x02000
1926 #define RTYPE_PC 0x04000
1927 #define RTYPE_ACC 0x08000
1928 #define RTYPE_CCC 0x10000
1929 #define RNUM_MASK 0x000ff
1930 #define RWARN 0x80000
1932 #define GENERIC_REGISTER_NUMBERS \
1933 {"$0", RTYPE_NUM | 0}, \
1934 {"$1", RTYPE_NUM | 1}, \
1935 {"$2", RTYPE_NUM | 2}, \
1936 {"$3", RTYPE_NUM | 3}, \
1937 {"$4", RTYPE_NUM | 4}, \
1938 {"$5", RTYPE_NUM | 5}, \
1939 {"$6", RTYPE_NUM | 6}, \
1940 {"$7", RTYPE_NUM | 7}, \
1941 {"$8", RTYPE_NUM | 8}, \
1942 {"$9", RTYPE_NUM | 9}, \
1943 {"$10", RTYPE_NUM | 10}, \
1944 {"$11", RTYPE_NUM | 11}, \
1945 {"$12", RTYPE_NUM | 12}, \
1946 {"$13", RTYPE_NUM | 13}, \
1947 {"$14", RTYPE_NUM | 14}, \
1948 {"$15", RTYPE_NUM | 15}, \
1949 {"$16", RTYPE_NUM | 16}, \
1950 {"$17", RTYPE_NUM | 17}, \
1951 {"$18", RTYPE_NUM | 18}, \
1952 {"$19", RTYPE_NUM | 19}, \
1953 {"$20", RTYPE_NUM | 20}, \
1954 {"$21", RTYPE_NUM | 21}, \
1955 {"$22", RTYPE_NUM | 22}, \
1956 {"$23", RTYPE_NUM | 23}, \
1957 {"$24", RTYPE_NUM | 24}, \
1958 {"$25", RTYPE_NUM | 25}, \
1959 {"$26", RTYPE_NUM | 26}, \
1960 {"$27", RTYPE_NUM | 27}, \
1961 {"$28", RTYPE_NUM | 28}, \
1962 {"$29", RTYPE_NUM | 29}, \
1963 {"$30", RTYPE_NUM | 30}, \
1964 {"$31", RTYPE_NUM | 31}
1966 #define FPU_REGISTER_NAMES \
1967 {"$f0", RTYPE_FPU | 0}, \
1968 {"$f1", RTYPE_FPU | 1}, \
1969 {"$f2", RTYPE_FPU | 2}, \
1970 {"$f3", RTYPE_FPU | 3}, \
1971 {"$f4", RTYPE_FPU | 4}, \
1972 {"$f5", RTYPE_FPU | 5}, \
1973 {"$f6", RTYPE_FPU | 6}, \
1974 {"$f7", RTYPE_FPU | 7}, \
1975 {"$f8", RTYPE_FPU | 8}, \
1976 {"$f9", RTYPE_FPU | 9}, \
1977 {"$f10", RTYPE_FPU | 10}, \
1978 {"$f11", RTYPE_FPU | 11}, \
1979 {"$f12", RTYPE_FPU | 12}, \
1980 {"$f13", RTYPE_FPU | 13}, \
1981 {"$f14", RTYPE_FPU | 14}, \
1982 {"$f15", RTYPE_FPU | 15}, \
1983 {"$f16", RTYPE_FPU | 16}, \
1984 {"$f17", RTYPE_FPU | 17}, \
1985 {"$f18", RTYPE_FPU | 18}, \
1986 {"$f19", RTYPE_FPU | 19}, \
1987 {"$f20", RTYPE_FPU | 20}, \
1988 {"$f21", RTYPE_FPU | 21}, \
1989 {"$f22", RTYPE_FPU | 22}, \
1990 {"$f23", RTYPE_FPU | 23}, \
1991 {"$f24", RTYPE_FPU | 24}, \
1992 {"$f25", RTYPE_FPU | 25}, \
1993 {"$f26", RTYPE_FPU | 26}, \
1994 {"$f27", RTYPE_FPU | 27}, \
1995 {"$f28", RTYPE_FPU | 28}, \
1996 {"$f29", RTYPE_FPU | 29}, \
1997 {"$f30", RTYPE_FPU | 30}, \
1998 {"$f31", RTYPE_FPU | 31}
2000 #define FPU_CONDITION_CODE_NAMES \
2001 {"$fcc0", RTYPE_FCC | 0}, \
2002 {"$fcc1", RTYPE_FCC | 1}, \
2003 {"$fcc2", RTYPE_FCC | 2}, \
2004 {"$fcc3", RTYPE_FCC | 3}, \
2005 {"$fcc4", RTYPE_FCC | 4}, \
2006 {"$fcc5", RTYPE_FCC | 5}, \
2007 {"$fcc6", RTYPE_FCC | 6}, \
2008 {"$fcc7", RTYPE_FCC | 7}
2010 #define COPROC_CONDITION_CODE_NAMES \
2011 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2012 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2013 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2014 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2015 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2016 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2017 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2018 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2020 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2021 {"$a4", RTYPE_GP | 8}, \
2022 {"$a5", RTYPE_GP | 9}, \
2023 {"$a6", RTYPE_GP | 10}, \
2024 {"$a7", RTYPE_GP | 11}, \
2025 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2026 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2027 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2028 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2029 {"$t0", RTYPE_GP | 12}, \
2030 {"$t1", RTYPE_GP | 13}, \
2031 {"$t2", RTYPE_GP | 14}, \
2032 {"$t3", RTYPE_GP | 15}
2034 #define O32_SYMBOLIC_REGISTER_NAMES \
2035 {"$t0", RTYPE_GP | 8}, \
2036 {"$t1", RTYPE_GP | 9}, \
2037 {"$t2", RTYPE_GP | 10}, \
2038 {"$t3", RTYPE_GP | 11}, \
2039 {"$t4", RTYPE_GP | 12}, \
2040 {"$t5", RTYPE_GP | 13}, \
2041 {"$t6", RTYPE_GP | 14}, \
2042 {"$t7", RTYPE_GP | 15}, \
2043 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2044 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2045 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2046 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2048 /* Remaining symbolic register names */
2049 #define SYMBOLIC_REGISTER_NAMES \
2050 {"$zero", RTYPE_GP | 0}, \
2051 {"$at", RTYPE_GP | 1}, \
2052 {"$AT", RTYPE_GP | 1}, \
2053 {"$v0", RTYPE_GP | 2}, \
2054 {"$v1", RTYPE_GP | 3}, \
2055 {"$a0", RTYPE_GP | 4}, \
2056 {"$a1", RTYPE_GP | 5}, \
2057 {"$a2", RTYPE_GP | 6}, \
2058 {"$a3", RTYPE_GP | 7}, \
2059 {"$s0", RTYPE_GP | 16}, \
2060 {"$s1", RTYPE_GP | 17}, \
2061 {"$s2", RTYPE_GP | 18}, \
2062 {"$s3", RTYPE_GP | 19}, \
2063 {"$s4", RTYPE_GP | 20}, \
2064 {"$s5", RTYPE_GP | 21}, \
2065 {"$s6", RTYPE_GP | 22}, \
2066 {"$s7", RTYPE_GP | 23}, \
2067 {"$t8", RTYPE_GP | 24}, \
2068 {"$t9", RTYPE_GP | 25}, \
2069 {"$k0", RTYPE_GP | 26}, \
2070 {"$kt0", RTYPE_GP | 26}, \
2071 {"$k1", RTYPE_GP | 27}, \
2072 {"$kt1", RTYPE_GP | 27}, \
2073 {"$gp", RTYPE_GP | 28}, \
2074 {"$sp", RTYPE_GP | 29}, \
2075 {"$s8", RTYPE_GP | 30}, \
2076 {"$fp", RTYPE_GP | 30}, \
2077 {"$ra", RTYPE_GP | 31}
2079 #define MIPS16_SPECIAL_REGISTER_NAMES \
2080 {"$pc", RTYPE_PC | 0}
2082 #define MDMX_VECTOR_REGISTER_NAMES \
2083 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2084 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2085 {"$v2", RTYPE_VEC | 2}, \
2086 {"$v3", RTYPE_VEC | 3}, \
2087 {"$v4", RTYPE_VEC | 4}, \
2088 {"$v5", RTYPE_VEC | 5}, \
2089 {"$v6", RTYPE_VEC | 6}, \
2090 {"$v7", RTYPE_VEC | 7}, \
2091 {"$v8", RTYPE_VEC | 8}, \
2092 {"$v9", RTYPE_VEC | 9}, \
2093 {"$v10", RTYPE_VEC | 10}, \
2094 {"$v11", RTYPE_VEC | 11}, \
2095 {"$v12", RTYPE_VEC | 12}, \
2096 {"$v13", RTYPE_VEC | 13}, \
2097 {"$v14", RTYPE_VEC | 14}, \
2098 {"$v15", RTYPE_VEC | 15}, \
2099 {"$v16", RTYPE_VEC | 16}, \
2100 {"$v17", RTYPE_VEC | 17}, \
2101 {"$v18", RTYPE_VEC | 18}, \
2102 {"$v19", RTYPE_VEC | 19}, \
2103 {"$v20", RTYPE_VEC | 20}, \
2104 {"$v21", RTYPE_VEC | 21}, \
2105 {"$v22", RTYPE_VEC | 22}, \
2106 {"$v23", RTYPE_VEC | 23}, \
2107 {"$v24", RTYPE_VEC | 24}, \
2108 {"$v25", RTYPE_VEC | 25}, \
2109 {"$v26", RTYPE_VEC | 26}, \
2110 {"$v27", RTYPE_VEC | 27}, \
2111 {"$v28", RTYPE_VEC | 28}, \
2112 {"$v29", RTYPE_VEC | 29}, \
2113 {"$v30", RTYPE_VEC | 30}, \
2114 {"$v31", RTYPE_VEC | 31}
2116 #define MIPS_DSP_ACCUMULATOR_NAMES \
2117 {"$ac0", RTYPE_ACC | 0}, \
2118 {"$ac1", RTYPE_ACC | 1}, \
2119 {"$ac2", RTYPE_ACC | 2}, \
2120 {"$ac3", RTYPE_ACC | 3}
2122 static const struct regname reg_names
[] = {
2123 GENERIC_REGISTER_NUMBERS
,
2125 FPU_CONDITION_CODE_NAMES
,
2126 COPROC_CONDITION_CODE_NAMES
,
2128 /* The $txx registers depends on the abi,
2129 these will be added later into the symbol table from
2130 one of the tables below once mips_abi is set after
2131 parsing of arguments from the command line. */
2132 SYMBOLIC_REGISTER_NAMES
,
2134 MIPS16_SPECIAL_REGISTER_NAMES
,
2135 MDMX_VECTOR_REGISTER_NAMES
,
2136 MIPS_DSP_ACCUMULATOR_NAMES
,
2140 static const struct regname reg_names_o32
[] = {
2141 O32_SYMBOLIC_REGISTER_NAMES
,
2145 static const struct regname reg_names_n32n64
[] = {
2146 N32N64_SYMBOLIC_REGISTER_NAMES
,
2150 /* Check if S points at a valid register specifier according to TYPES.
2151 If so, then return 1, advance S to consume the specifier and store
2152 the register's number in REGNOP, otherwise return 0. */
2155 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2162 /* Find end of name. */
2164 if (is_name_beginner (*e
))
2166 while (is_part_of_name (*e
))
2169 /* Terminate name. */
2173 /* Look for a register symbol. */
2174 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2176 int r
= S_GET_VALUE (symbolP
);
2178 reg
= r
& RNUM_MASK
;
2179 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2180 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2181 reg
= (r
& RNUM_MASK
) - 2;
2183 /* Else see if this is a register defined in an itbl entry. */
2184 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2191 if (itbl_get_reg_val (n
, &r
))
2192 reg
= r
& RNUM_MASK
;
2195 /* Advance to next token if a register was recognised. */
2198 else if (types
& RWARN
)
2199 as_warn (_("Unrecognized register name `%s'"), *s
);
2207 /* Check if S points at a valid register list according to TYPES.
2208 If so, then return 1, advance S to consume the list and store
2209 the registers present on the list as a bitmask of ones in REGLISTP,
2210 otherwise return 0. A valid list comprises a comma-separated
2211 enumeration of valid single registers and/or dash-separated
2212 contiguous register ranges as determined by their numbers.
2214 As a special exception if one of s0-s7 registers is specified as
2215 the range's lower delimiter and s8 (fp) is its upper one, then no
2216 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2217 are selected; they have to be listed separately if needed. */
2220 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2222 unsigned int reglist
= 0;
2223 unsigned int lastregno
;
2224 bfd_boolean ok
= TRUE
;
2225 unsigned int regmask
;
2226 char *s_endlist
= *s
;
2230 while (reg_lookup (s
, types
, ®no
))
2236 ok
= reg_lookup (s
, types
, &lastregno
);
2237 if (ok
&& lastregno
< regno
)
2243 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2248 regmask
= 1 << lastregno
;
2249 regmask
= (regmask
<< 1) - 1;
2250 regmask
^= (1 << regno
) - 1;
2264 *reglistp
= reglist
;
2265 return ok
&& reglist
!= 0;
2268 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2269 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2272 is_opcode_valid (const struct mips_opcode
*mo
)
2274 int isa
= mips_opts
.isa
;
2278 if (mips_opts
.ase_mdmx
)
2280 if (mips_opts
.ase_dsp
)
2282 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2284 if (mips_opts
.ase_dspr2
)
2286 if (mips_opts
.ase_eva
)
2288 if (mips_opts
.ase_mt
)
2290 if (mips_opts
.ase_mips3d
)
2292 if (mips_opts
.ase_smartmips
)
2293 ase
|= ASE_SMARTMIPS
;
2294 if (mips_opts
.ase_mcu
)
2296 if (mips_opts
.ase_virt
)
2298 if (mips_opts
.ase_virt
&& ISA_SUPPORTS_VIRT64_ASE
)
2301 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2304 /* Check whether the instruction or macro requires single-precision or
2305 double-precision floating-point support. Note that this information is
2306 stored differently in the opcode table for insns and macros. */
2307 if (mo
->pinfo
== INSN_MACRO
)
2309 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2310 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2314 fp_s
= mo
->pinfo
& FP_S
;
2315 fp_d
= mo
->pinfo
& FP_D
;
2318 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2321 if (fp_s
&& mips_opts
.soft_float
)
2327 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2328 selected ISA and architecture. */
2331 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2333 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2336 /* Return TRUE if the size of the microMIPS opcode MO matches one
2337 explicitly requested. Always TRUE in the standard MIPS mode. */
2340 is_size_valid (const struct mips_opcode
*mo
)
2342 if (!mips_opts
.micromips
)
2345 if (!forced_insn_length
)
2347 if (mo
->pinfo
== INSN_MACRO
)
2349 return forced_insn_length
== micromips_insn_length (mo
);
2352 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2353 of the preceding instruction. Always TRUE in the standard MIPS mode.
2355 We don't accept macros in 16-bit delay slots to avoid a case where
2356 a macro expansion fails because it relies on a preceding 32-bit real
2357 instruction to have matched and does not handle the operands correctly.
2358 The only macros that may expand to 16-bit instructions are JAL that
2359 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2360 and BGT (that likewise cannot be placed in a delay slot) that decay to
2361 a NOP. In all these cases the macros precede any corresponding real
2362 instruction definitions in the opcode table, so they will match in the
2363 second pass where the size of the delay slot is ignored and therefore
2364 produce correct code. */
2367 is_delay_slot_valid (const struct mips_opcode
*mo
)
2369 if (!mips_opts
.micromips
)
2372 if (mo
->pinfo
== INSN_MACRO
)
2373 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2374 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2375 && micromips_insn_length (mo
) != 4)
2377 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2378 && micromips_insn_length (mo
) != 2)
2384 /* This function is called once, at assembler startup time. It should set up
2385 all the tables, etc. that the MD part of the assembler will need. */
2390 const char *retval
= NULL
;
2394 if (mips_pic
!= NO_PIC
)
2396 if (g_switch_seen
&& g_switch_value
!= 0)
2397 as_bad (_("-G may not be used in position-independent code"));
2401 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2402 as_warn (_("Could not set architecture and machine"));
2404 op_hash
= hash_new ();
2406 for (i
= 0; i
< NUMOPCODES
;)
2408 const char *name
= mips_opcodes
[i
].name
;
2410 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2413 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2414 mips_opcodes
[i
].name
, retval
);
2415 /* Probably a memory allocation problem? Give up now. */
2416 as_fatal (_("Broken assembler. No assembly attempted."));
2420 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2422 if (!validate_mips_insn (&mips_opcodes
[i
]))
2424 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2426 create_insn (&nop_insn
, mips_opcodes
+ i
);
2427 if (mips_fix_loongson2f_nop
)
2428 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2429 nop_insn
.fixed_p
= 1;
2434 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2437 mips16_op_hash
= hash_new ();
2440 while (i
< bfd_mips16_num_opcodes
)
2442 const char *name
= mips16_opcodes
[i
].name
;
2444 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2446 as_fatal (_("internal: can't hash `%s': %s"),
2447 mips16_opcodes
[i
].name
, retval
);
2450 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2451 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2452 != mips16_opcodes
[i
].match
))
2454 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2455 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2458 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2460 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2461 mips16_nop_insn
.fixed_p
= 1;
2465 while (i
< bfd_mips16_num_opcodes
2466 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2469 micromips_op_hash
= hash_new ();
2472 while (i
< bfd_micromips_num_opcodes
)
2474 const char *name
= micromips_opcodes
[i
].name
;
2476 retval
= hash_insert (micromips_op_hash
, name
,
2477 (void *) µmips_opcodes
[i
]);
2479 as_fatal (_("internal: can't hash `%s': %s"),
2480 micromips_opcodes
[i
].name
, retval
);
2482 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2484 struct mips_cl_insn
*micromips_nop_insn
;
2486 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2489 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2490 micromips_nop_insn
= µmips_nop16_insn
;
2491 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2492 micromips_nop_insn
= µmips_nop32_insn
;
2496 if (micromips_nop_insn
->insn_mo
== NULL
2497 && strcmp (name
, "nop") == 0)
2499 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2500 micromips_nop_insn
->fixed_p
= 1;
2503 while (++i
< bfd_micromips_num_opcodes
2504 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2508 as_fatal (_("Broken assembler. No assembly attempted."));
2510 /* We add all the general register names to the symbol table. This
2511 helps us detect invalid uses of them. */
2512 for (i
= 0; reg_names
[i
].name
; i
++)
2513 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2514 reg_names
[i
].num
, /* & RNUM_MASK, */
2515 &zero_address_frag
));
2517 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2518 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2519 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2520 &zero_address_frag
));
2522 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2523 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2524 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2525 &zero_address_frag
));
2527 mips_no_prev_insn ();
2530 mips_cprmask
[0] = 0;
2531 mips_cprmask
[1] = 0;
2532 mips_cprmask
[2] = 0;
2533 mips_cprmask
[3] = 0;
2535 /* set the default alignment for the text section (2**2) */
2536 record_alignment (text_section
, 2);
2538 bfd_set_gp_size (stdoutput
, g_switch_value
);
2543 /* On a native system other than VxWorks, sections must be aligned
2544 to 16 byte boundaries. When configured for an embedded ELF
2545 target, we don't bother. */
2546 if (strncmp (TARGET_OS
, "elf", 3) != 0
2547 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2549 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2550 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2551 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2554 /* Create a .reginfo section for register masks and a .mdebug
2555 section for debugging information. */
2563 subseg
= now_subseg
;
2565 /* The ABI says this section should be loaded so that the
2566 running program can access it. However, we don't load it
2567 if we are configured for an embedded target */
2568 flags
= SEC_READONLY
| SEC_DATA
;
2569 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2570 flags
|= SEC_ALLOC
| SEC_LOAD
;
2572 if (mips_abi
!= N64_ABI
)
2574 sec
= subseg_new (".reginfo", (subsegT
) 0);
2576 bfd_set_section_flags (stdoutput
, sec
, flags
);
2577 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2579 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2583 /* The 64-bit ABI uses a .MIPS.options section rather than
2584 .reginfo section. */
2585 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2586 bfd_set_section_flags (stdoutput
, sec
, flags
);
2587 bfd_set_section_alignment (stdoutput
, sec
, 3);
2589 /* Set up the option header. */
2591 Elf_Internal_Options opthdr
;
2594 opthdr
.kind
= ODK_REGINFO
;
2595 opthdr
.size
= (sizeof (Elf_External_Options
)
2596 + sizeof (Elf64_External_RegInfo
));
2599 f
= frag_more (sizeof (Elf_External_Options
));
2600 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2601 (Elf_External_Options
*) f
);
2603 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2607 if (ECOFF_DEBUGGING
)
2609 sec
= subseg_new (".mdebug", (subsegT
) 0);
2610 (void) bfd_set_section_flags (stdoutput
, sec
,
2611 SEC_HAS_CONTENTS
| SEC_READONLY
);
2612 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2614 else if (mips_flag_pdr
)
2616 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2617 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2618 SEC_READONLY
| SEC_RELOC
2620 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2623 subseg_set (seg
, subseg
);
2626 #endif /* OBJ_ELF */
2628 if (! ECOFF_DEBUGGING
)
2631 if (mips_fix_vr4120
)
2632 init_vr4120_conflicts ();
2638 mips_emit_delays ();
2639 if (! ECOFF_DEBUGGING
)
2644 md_assemble (char *str
)
2646 struct mips_cl_insn insn
;
2647 bfd_reloc_code_real_type unused_reloc
[3]
2648 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2650 imm_expr
.X_op
= O_absent
;
2651 imm2_expr
.X_op
= O_absent
;
2652 offset_expr
.X_op
= O_absent
;
2653 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2654 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2655 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2656 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2657 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2658 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2660 mips_mark_labels ();
2661 mips_assembling_insn
= TRUE
;
2663 if (mips_opts
.mips16
)
2664 mips16_ip (str
, &insn
);
2667 mips_ip (str
, &insn
);
2668 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2669 str
, insn
.insn_opcode
));
2673 as_bad ("%s `%s'", insn_error
, str
);
2674 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2677 if (mips_opts
.mips16
)
2678 mips16_macro (&insn
);
2685 if (imm_expr
.X_op
!= O_absent
)
2686 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2687 else if (offset_expr
.X_op
!= O_absent
)
2688 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2690 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2693 mips_assembling_insn
= FALSE
;
2696 /* Convenience functions for abstracting away the differences between
2697 MIPS16 and non-MIPS16 relocations. */
2699 static inline bfd_boolean
2700 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2704 case BFD_RELOC_MIPS16_JMP
:
2705 case BFD_RELOC_MIPS16_GPREL
:
2706 case BFD_RELOC_MIPS16_GOT16
:
2707 case BFD_RELOC_MIPS16_CALL16
:
2708 case BFD_RELOC_MIPS16_HI16_S
:
2709 case BFD_RELOC_MIPS16_HI16
:
2710 case BFD_RELOC_MIPS16_LO16
:
2718 static inline bfd_boolean
2719 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2723 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2724 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2725 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2726 case BFD_RELOC_MICROMIPS_GPREL16
:
2727 case BFD_RELOC_MICROMIPS_JMP
:
2728 case BFD_RELOC_MICROMIPS_HI16
:
2729 case BFD_RELOC_MICROMIPS_HI16_S
:
2730 case BFD_RELOC_MICROMIPS_LO16
:
2731 case BFD_RELOC_MICROMIPS_LITERAL
:
2732 case BFD_RELOC_MICROMIPS_GOT16
:
2733 case BFD_RELOC_MICROMIPS_CALL16
:
2734 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2735 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2736 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2737 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2738 case BFD_RELOC_MICROMIPS_SUB
:
2739 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2740 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2741 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2742 case BFD_RELOC_MICROMIPS_HIGHEST
:
2743 case BFD_RELOC_MICROMIPS_HIGHER
:
2744 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2745 case BFD_RELOC_MICROMIPS_JALR
:
2753 static inline bfd_boolean
2754 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2756 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2759 static inline bfd_boolean
2760 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2762 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2763 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2766 static inline bfd_boolean
2767 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2769 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2770 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2773 static inline bfd_boolean
2774 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2776 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2777 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2780 static inline bfd_boolean
2781 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2783 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2786 /* Return true if RELOC is a PC-relative relocation that does not have
2787 full address range. */
2789 static inline bfd_boolean
2790 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
2794 case BFD_RELOC_16_PCREL_S2
:
2795 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2796 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2797 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2800 case BFD_RELOC_32_PCREL
:
2801 return HAVE_64BIT_ADDRESSES
;
2808 /* Return true if the given relocation might need a matching %lo().
2809 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2810 need a matching %lo() when applied to local symbols. */
2812 static inline bfd_boolean
2813 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2815 return (HAVE_IN_PLACE_ADDENDS
2816 && (hi16_reloc_p (reloc
)
2817 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2818 all GOT16 relocations evaluate to "G". */
2819 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2822 /* Return the type of %lo() reloc needed by RELOC, given that
2823 reloc_needs_lo_p. */
2825 static inline bfd_reloc_code_real_type
2826 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2828 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2829 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2833 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2836 static inline bfd_boolean
2837 fixup_has_matching_lo_p (fixS
*fixp
)
2839 return (fixp
->fx_next
!= NULL
2840 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2841 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2842 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2845 /* This function returns true if modifying a register requires a
2849 reg_needs_delay (unsigned int reg
)
2851 unsigned long prev_pinfo
;
2853 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2854 if (! mips_opts
.noreorder
2855 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2856 && ! gpr_interlocks
)
2857 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2858 && ! cop_interlocks
)))
2860 /* A load from a coprocessor or from memory. All load delays
2861 delay the use of general register rt for one instruction. */
2862 /* Itbl support may require additional care here. */
2863 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2864 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2871 /* Move all labels in LABELS to the current insertion point. TEXT_P
2872 says whether the labels refer to text or data. */
2875 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2877 struct insn_label_list
*l
;
2880 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2882 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2883 symbol_set_frag (l
->label
, frag_now
);
2884 val
= (valueT
) frag_now_fix ();
2885 /* MIPS16/microMIPS text labels are stored as odd. */
2886 if (text_p
&& HAVE_CODE_COMPRESSION
)
2888 S_SET_VALUE (l
->label
, val
);
2892 /* Move all labels in insn_labels to the current insertion point
2893 and treat them as text labels. */
2896 mips_move_text_labels (void)
2898 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2902 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2904 bfd_boolean linkonce
= FALSE
;
2905 segT symseg
= S_GET_SEGMENT (sym
);
2907 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2909 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2912 /* The GNU toolchain uses an extension for ELF: a section
2913 beginning with the magic string .gnu.linkonce is a
2914 linkonce section. */
2915 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2916 sizeof ".gnu.linkonce" - 1) == 0)
2923 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2924 linker to handle them specially, such as generating jalx instructions
2925 when needed. We also make them odd for the duration of the assembly,
2926 in order to generate the right sort of code. We will make them even
2927 in the adjust_symtab routine, while leaving them marked. This is
2928 convenient for the debugger and the disassembler. The linker knows
2929 to make them odd again. */
2932 mips_compressed_mark_label (symbolS
*label
)
2934 gas_assert (HAVE_CODE_COMPRESSION
);
2936 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2939 if (mips_opts
.mips16
)
2940 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2942 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2945 if ((S_GET_VALUE (label
) & 1) == 0
2946 /* Don't adjust the address if the label is global or weak, or
2947 in a link-once section, since we'll be emitting symbol reloc
2948 references to it which will be patched up by the linker, and
2949 the final value of the symbol may or may not be MIPS16/microMIPS. */
2950 && !S_IS_WEAK (label
)
2951 && !S_IS_EXTERNAL (label
)
2952 && !s_is_linkonce (label
, now_seg
))
2953 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2956 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2959 mips_compressed_mark_labels (void)
2961 struct insn_label_list
*l
;
2963 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
2964 mips_compressed_mark_label (l
->label
);
2967 /* End the current frag. Make it a variant frag and record the
2971 relax_close_frag (void)
2973 mips_macro_warning
.first_frag
= frag_now
;
2974 frag_var (rs_machine_dependent
, 0, 0,
2975 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2976 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2978 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2979 mips_relax
.first_fixup
= 0;
2982 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2983 See the comment above RELAX_ENCODE for more details. */
2986 relax_start (symbolS
*symbol
)
2988 gas_assert (mips_relax
.sequence
== 0);
2989 mips_relax
.sequence
= 1;
2990 mips_relax
.symbol
= symbol
;
2993 /* Start generating the second version of a relaxable sequence.
2994 See the comment above RELAX_ENCODE for more details. */
2999 gas_assert (mips_relax
.sequence
== 1);
3000 mips_relax
.sequence
= 2;
3003 /* End the current relaxable sequence. */
3008 gas_assert (mips_relax
.sequence
== 2);
3009 relax_close_frag ();
3010 mips_relax
.sequence
= 0;
3013 /* Return true if IP is a delayed branch or jump. */
3015 static inline bfd_boolean
3016 delayed_branch_p (const struct mips_cl_insn
*ip
)
3018 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3019 | INSN_COND_BRANCH_DELAY
3020 | INSN_COND_BRANCH_LIKELY
)) != 0;
3023 /* Return true if IP is a compact branch or jump. */
3025 static inline bfd_boolean
3026 compact_branch_p (const struct mips_cl_insn
*ip
)
3028 if (mips_opts
.mips16
)
3029 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3030 | MIPS16_INSN_COND_BRANCH
)) != 0;
3032 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3033 | INSN2_COND_BRANCH
)) != 0;
3036 /* Return true if IP is an unconditional branch or jump. */
3038 static inline bfd_boolean
3039 uncond_branch_p (const struct mips_cl_insn
*ip
)
3041 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3042 || (mips_opts
.mips16
3043 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3044 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3047 /* Return true if IP is a branch-likely instruction. */
3049 static inline bfd_boolean
3050 branch_likely_p (const struct mips_cl_insn
*ip
)
3052 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3055 /* Return the type of nop that should be used to fill the delay slot
3056 of delayed branch IP. */
3058 static struct mips_cl_insn
*
3059 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3061 if (mips_opts
.micromips
3062 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3063 return µmips_nop32_insn
;
3067 /* Return the mask of core registers that IP reads or writes. */
3070 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3072 unsigned long pinfo2
;
3076 pinfo2
= ip
->insn_mo
->pinfo2
;
3077 if (mips_opts
.micromips
)
3079 if (pinfo2
& INSN2_MOD_GPR_MD
)
3080 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3081 if (pinfo2
& INSN2_MOD_GPR_MF
)
3082 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3083 if (pinfo2
& INSN2_MOD_SP
)
3089 /* Return the mask of core registers that IP reads. */
3092 gpr_read_mask (const struct mips_cl_insn
*ip
)
3094 unsigned long pinfo
, pinfo2
;
3097 mask
= gpr_mod_mask (ip
);
3098 pinfo
= ip
->insn_mo
->pinfo
;
3099 pinfo2
= ip
->insn_mo
->pinfo2
;
3100 if (mips_opts
.mips16
)
3102 if (pinfo
& MIPS16_INSN_READ_X
)
3103 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3104 if (pinfo
& MIPS16_INSN_READ_Y
)
3105 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3106 if (pinfo
& MIPS16_INSN_READ_T
)
3108 if (pinfo
& MIPS16_INSN_READ_SP
)
3110 if (pinfo
& MIPS16_INSN_READ_31
)
3112 if (pinfo
& MIPS16_INSN_READ_Z
)
3113 mask
|= 1 << (mips16_to_32_reg_map
3114 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3115 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3116 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3120 if (pinfo2
& INSN2_READ_GPR_D
)
3121 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3122 if (pinfo
& INSN_READ_GPR_T
)
3123 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3124 if (pinfo
& INSN_READ_GPR_S
)
3125 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3126 if (pinfo2
& INSN2_READ_GP
)
3128 if (pinfo2
& INSN2_READ_GPR_31
)
3130 if (pinfo2
& INSN2_READ_GPR_Z
)
3131 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3133 if (mips_opts
.micromips
)
3135 if (pinfo2
& INSN2_READ_GPR_MC
)
3136 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3137 if (pinfo2
& INSN2_READ_GPR_ME
)
3138 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3139 if (pinfo2
& INSN2_READ_GPR_MG
)
3140 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3141 if (pinfo2
& INSN2_READ_GPR_MJ
)
3142 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3143 if (pinfo2
& INSN2_READ_GPR_MMN
)
3145 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3146 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3148 if (pinfo2
& INSN2_READ_GPR_MP
)
3149 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3150 if (pinfo2
& INSN2_READ_GPR_MQ
)
3151 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3153 /* Don't include register 0. */
3157 /* Return the mask of core registers that IP writes. */
3160 gpr_write_mask (const struct mips_cl_insn
*ip
)
3162 unsigned long pinfo
, pinfo2
;
3165 mask
= gpr_mod_mask (ip
);
3166 pinfo
= ip
->insn_mo
->pinfo
;
3167 pinfo2
= ip
->insn_mo
->pinfo2
;
3168 if (mips_opts
.mips16
)
3170 if (pinfo
& MIPS16_INSN_WRITE_X
)
3171 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3172 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3173 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3174 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3175 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3176 if (pinfo
& MIPS16_INSN_WRITE_T
)
3178 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3180 if (pinfo
& MIPS16_INSN_WRITE_31
)
3182 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3183 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3187 if (pinfo
& INSN_WRITE_GPR_D
)
3188 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3189 if (pinfo
& INSN_WRITE_GPR_T
)
3190 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3191 if (pinfo
& INSN_WRITE_GPR_S
)
3192 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3193 if (pinfo
& INSN_WRITE_GPR_31
)
3195 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3196 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3198 if (mips_opts
.micromips
)
3200 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3201 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3202 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3204 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3205 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3207 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3208 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3209 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3210 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3212 /* Don't include register 0. */
3216 /* Return the mask of floating-point registers that IP reads. */
3219 fpr_read_mask (const struct mips_cl_insn
*ip
)
3221 unsigned long pinfo
, pinfo2
;
3225 pinfo
= ip
->insn_mo
->pinfo
;
3226 pinfo2
= ip
->insn_mo
->pinfo2
;
3227 if (!mips_opts
.mips16
)
3229 if (pinfo2
& INSN2_READ_FPR_D
)
3230 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3231 if (pinfo
& INSN_READ_FPR_S
)
3232 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3233 if (pinfo
& INSN_READ_FPR_T
)
3234 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3235 if (pinfo
& INSN_READ_FPR_R
)
3236 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3237 if (pinfo2
& INSN2_READ_FPR_Z
)
3238 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3240 /* Conservatively treat all operands to an FP_D instruction are doubles.
3241 (This is overly pessimistic for things like cvt.d.s.) */
3242 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3247 /* Return the mask of floating-point registers that IP writes. */
3250 fpr_write_mask (const struct mips_cl_insn
*ip
)
3252 unsigned long pinfo
, pinfo2
;
3256 pinfo
= ip
->insn_mo
->pinfo
;
3257 pinfo2
= ip
->insn_mo
->pinfo2
;
3258 if (!mips_opts
.mips16
)
3260 if (pinfo
& INSN_WRITE_FPR_D
)
3261 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3262 if (pinfo
& INSN_WRITE_FPR_S
)
3263 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3264 if (pinfo
& INSN_WRITE_FPR_T
)
3265 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3266 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3267 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3269 /* Conservatively treat all operands to an FP_D instruction are doubles.
3270 (This is overly pessimistic for things like cvt.s.d.) */
3271 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3276 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3277 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3278 by VR4120 errata. */
3281 classify_vr4120_insn (const char *name
)
3283 if (strncmp (name
, "macc", 4) == 0)
3284 return FIX_VR4120_MACC
;
3285 if (strncmp (name
, "dmacc", 5) == 0)
3286 return FIX_VR4120_DMACC
;
3287 if (strncmp (name
, "mult", 4) == 0)
3288 return FIX_VR4120_MULT
;
3289 if (strncmp (name
, "dmult", 5) == 0)
3290 return FIX_VR4120_DMULT
;
3291 if (strstr (name
, "div"))
3292 return FIX_VR4120_DIV
;
3293 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3294 return FIX_VR4120_MTHILO
;
3295 return NUM_FIX_VR4120_CLASSES
;
3298 #define INSN_ERET 0x42000018
3299 #define INSN_DERET 0x4200001f
3301 /* Return the number of instructions that must separate INSN1 and INSN2,
3302 where INSN1 is the earlier instruction. Return the worst-case value
3303 for any INSN2 if INSN2 is null. */
3306 insns_between (const struct mips_cl_insn
*insn1
,
3307 const struct mips_cl_insn
*insn2
)
3309 unsigned long pinfo1
, pinfo2
;
3312 /* This function needs to know which pinfo flags are set for INSN2
3313 and which registers INSN2 uses. The former is stored in PINFO2 and
3314 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3315 will have every flag set and INSN2_USES_GPR will always return true. */
3316 pinfo1
= insn1
->insn_mo
->pinfo
;
3317 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3319 #define INSN2_USES_GPR(REG) \
3320 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3322 /* For most targets, write-after-read dependencies on the HI and LO
3323 registers must be separated by at least two instructions. */
3324 if (!hilo_interlocks
)
3326 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3328 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3332 /* If we're working around r7000 errata, there must be two instructions
3333 between an mfhi or mflo and any instruction that uses the result. */
3334 if (mips_7000_hilo_fix
3335 && !mips_opts
.micromips
3336 && MF_HILO_INSN (pinfo1
)
3337 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3340 /* If we're working around 24K errata, one instruction is required
3341 if an ERET or DERET is followed by a branch instruction. */
3342 if (mips_fix_24k
&& !mips_opts
.micromips
)
3344 if (insn1
->insn_opcode
== INSN_ERET
3345 || insn1
->insn_opcode
== INSN_DERET
)
3348 || insn2
->insn_opcode
== INSN_ERET
3349 || insn2
->insn_opcode
== INSN_DERET
3350 || delayed_branch_p (insn2
))
3355 /* If working around VR4120 errata, check for combinations that need
3356 a single intervening instruction. */
3357 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3359 unsigned int class1
, class2
;
3361 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3362 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3366 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3367 if (vr4120_conflicts
[class1
] & (1 << class2
))
3372 if (!HAVE_CODE_COMPRESSION
)
3374 /* Check for GPR or coprocessor load delays. All such delays
3375 are on the RT register. */
3376 /* Itbl support may require additional care here. */
3377 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3378 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3380 know (pinfo1
& INSN_WRITE_GPR_T
);
3381 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3385 /* Check for generic coprocessor hazards.
3387 This case is not handled very well. There is no special
3388 knowledge of CP0 handling, and the coprocessors other than
3389 the floating point unit are not distinguished at all. */
3390 /* Itbl support may require additional care here. FIXME!
3391 Need to modify this to include knowledge about
3392 user specified delays! */
3393 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3394 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3396 /* Handle cases where INSN1 writes to a known general coprocessor
3397 register. There must be a one instruction delay before INSN2
3398 if INSN2 reads that register, otherwise no delay is needed. */
3399 mask
= fpr_write_mask (insn1
);
3402 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3407 /* Read-after-write dependencies on the control registers
3408 require a two-instruction gap. */
3409 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3410 && (pinfo2
& INSN_READ_COND_CODE
))
3413 /* We don't know exactly what INSN1 does. If INSN2 is
3414 also a coprocessor instruction, assume there must be
3415 a one instruction gap. */
3416 if (pinfo2
& INSN_COP
)
3421 /* Check for read-after-write dependencies on the coprocessor
3422 control registers in cases where INSN1 does not need a general
3423 coprocessor delay. This means that INSN1 is a floating point
3424 comparison instruction. */
3425 /* Itbl support may require additional care here. */
3426 else if (!cop_interlocks
3427 && (pinfo1
& INSN_WRITE_COND_CODE
)
3428 && (pinfo2
& INSN_READ_COND_CODE
))
3432 #undef INSN2_USES_GPR
3437 /* Return the number of nops that would be needed to work around the
3438 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3439 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3440 that are contained within the first IGNORE instructions of HIST. */
3443 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3444 const struct mips_cl_insn
*insn
)
3449 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3450 are not affected by the errata. */
3452 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3453 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3454 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3457 /* Search for the first MFLO or MFHI. */
3458 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3459 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3461 /* Extract the destination register. */
3462 mask
= gpr_write_mask (&hist
[i
]);
3464 /* No nops are needed if INSN reads that register. */
3465 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3468 /* ...or if any of the intervening instructions do. */
3469 for (j
= 0; j
< i
; j
++)
3470 if (gpr_read_mask (&hist
[j
]) & mask
)
3474 return MAX_VR4130_NOPS
- i
;
3479 #define BASE_REG_EQ(INSN1, INSN2) \
3480 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3481 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3483 /* Return the minimum alignment for this store instruction. */
3486 fix_24k_align_to (const struct mips_opcode
*mo
)
3488 if (strcmp (mo
->name
, "sh") == 0)
3491 if (strcmp (mo
->name
, "swc1") == 0
3492 || strcmp (mo
->name
, "swc2") == 0
3493 || strcmp (mo
->name
, "sw") == 0
3494 || strcmp (mo
->name
, "sc") == 0
3495 || strcmp (mo
->name
, "s.s") == 0)
3498 if (strcmp (mo
->name
, "sdc1") == 0
3499 || strcmp (mo
->name
, "sdc2") == 0
3500 || strcmp (mo
->name
, "s.d") == 0)
3507 struct fix_24k_store_info
3509 /* Immediate offset, if any, for this store instruction. */
3511 /* Alignment required by this store instruction. */
3513 /* True for register offsets. */
3514 int register_offset
;
3517 /* Comparison function used by qsort. */
3520 fix_24k_sort (const void *a
, const void *b
)
3522 const struct fix_24k_store_info
*pos1
= a
;
3523 const struct fix_24k_store_info
*pos2
= b
;
3525 return (pos1
->off
- pos2
->off
);
3528 /* INSN is a store instruction. Try to record the store information
3529 in STINFO. Return false if the information isn't known. */
3532 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3533 const struct mips_cl_insn
*insn
)
3535 /* The instruction must have a known offset. */
3536 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3539 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3540 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3544 /* Return the number of nops that would be needed to work around the 24k
3545 "lost data on stores during refill" errata if instruction INSN
3546 immediately followed the 2 instructions described by HIST.
3547 Ignore hazards that are contained within the first IGNORE
3548 instructions of HIST.
3550 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3551 for the data cache refills and store data. The following describes
3552 the scenario where the store data could be lost.
3554 * A data cache miss, due to either a load or a store, causing fill
3555 data to be supplied by the memory subsystem
3556 * The first three doublewords of fill data are returned and written
3558 * A sequence of four stores occurs in consecutive cycles around the
3559 final doubleword of the fill:
3563 * Zero, One or more instructions
3566 The four stores A-D must be to different doublewords of the line that
3567 is being filled. The fourth instruction in the sequence above permits
3568 the fill of the final doubleword to be transferred from the FSB into
3569 the cache. In the sequence above, the stores may be either integer
3570 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3571 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3572 different doublewords on the line. If the floating point unit is
3573 running in 1:2 mode, it is not possible to create the sequence above
3574 using only floating point store instructions.
3576 In this case, the cache line being filled is incorrectly marked
3577 invalid, thereby losing the data from any store to the line that
3578 occurs between the original miss and the completion of the five
3579 cycle sequence shown above.
3581 The workarounds are:
3583 * Run the data cache in write-through mode.
3584 * Insert a non-store instruction between
3585 Store A and Store B or Store B and Store C. */
3588 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3589 const struct mips_cl_insn
*insn
)
3591 struct fix_24k_store_info pos
[3];
3592 int align
, i
, base_offset
;
3597 /* If the previous instruction wasn't a store, there's nothing to
3599 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3602 /* If the instructions after the previous one are unknown, we have
3603 to assume the worst. */
3607 /* Check whether we are dealing with three consecutive stores. */
3608 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3609 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3612 /* If we don't know the relationship between the store addresses,
3613 assume the worst. */
3614 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3615 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3618 if (!fix_24k_record_store_info (&pos
[0], insn
)
3619 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3620 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3623 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3625 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3626 X bytes and such that the base register + X is known to be aligned
3629 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3633 align
= pos
[0].align_to
;
3634 base_offset
= pos
[0].off
;
3635 for (i
= 1; i
< 3; i
++)
3636 if (align
< pos
[i
].align_to
)
3638 align
= pos
[i
].align_to
;
3639 base_offset
= pos
[i
].off
;
3641 for (i
= 0; i
< 3; i
++)
3642 pos
[i
].off
-= base_offset
;
3645 pos
[0].off
&= ~align
+ 1;
3646 pos
[1].off
&= ~align
+ 1;
3647 pos
[2].off
&= ~align
+ 1;
3649 /* If any two stores write to the same chunk, they also write to the
3650 same doubleword. The offsets are still sorted at this point. */
3651 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3654 /* A range of at least 9 bytes is needed for the stores to be in
3655 non-overlapping doublewords. */
3656 if (pos
[2].off
- pos
[0].off
<= 8)
3659 if (pos
[2].off
- pos
[1].off
>= 24
3660 || pos
[1].off
- pos
[0].off
>= 24
3661 || pos
[2].off
- pos
[0].off
>= 32)
3667 /* Return the number of nops that would be needed if instruction INSN
3668 immediately followed the MAX_NOPS instructions given by HIST,
3669 where HIST[0] is the most recent instruction. Ignore hazards
3670 between INSN and the first IGNORE instructions in HIST.
3672 If INSN is null, return the worse-case number of nops for any
3676 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3677 const struct mips_cl_insn
*insn
)
3679 int i
, nops
, tmp_nops
;
3682 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3684 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3685 if (tmp_nops
> nops
)
3689 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3691 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3692 if (tmp_nops
> nops
)
3696 if (mips_fix_24k
&& !mips_opts
.micromips
)
3698 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3699 if (tmp_nops
> nops
)
3706 /* The variable arguments provide NUM_INSNS extra instructions that
3707 might be added to HIST. Return the largest number of nops that
3708 would be needed after the extended sequence, ignoring hazards
3709 in the first IGNORE instructions. */
3712 nops_for_sequence (int num_insns
, int ignore
,
3713 const struct mips_cl_insn
*hist
, ...)
3716 struct mips_cl_insn buffer
[MAX_NOPS
];
3717 struct mips_cl_insn
*cursor
;
3720 va_start (args
, hist
);
3721 cursor
= buffer
+ num_insns
;
3722 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3723 while (cursor
> buffer
)
3724 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3726 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3731 /* Like nops_for_insn, but if INSN is a branch, take into account the
3732 worst-case delay for the branch target. */
3735 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3736 const struct mips_cl_insn
*insn
)
3740 nops
= nops_for_insn (ignore
, hist
, insn
);
3741 if (delayed_branch_p (insn
))
3743 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3744 hist
, insn
, get_delay_slot_nop (insn
));
3745 if (tmp_nops
> nops
)
3748 else if (compact_branch_p (insn
))
3750 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3751 if (tmp_nops
> nops
)
3757 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3760 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3762 gas_assert (!HAVE_CODE_COMPRESSION
);
3763 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3764 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3767 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3768 jr target pc &= 'hffff_ffff_cfff_ffff. */
3771 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3773 gas_assert (!HAVE_CODE_COMPRESSION
);
3774 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3775 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3776 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3784 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3785 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3788 ep
.X_op
= O_constant
;
3789 ep
.X_add_number
= 0xcfff0000;
3790 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3791 ep
.X_add_number
= 0xffff;
3792 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3793 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3798 fix_loongson2f (struct mips_cl_insn
* ip
)
3800 if (mips_fix_loongson2f_nop
)
3801 fix_loongson2f_nop (ip
);
3803 if (mips_fix_loongson2f_jump
)
3804 fix_loongson2f_jump (ip
);
3807 /* IP is a branch that has a delay slot, and we need to fill it
3808 automatically. Return true if we can do that by swapping IP
3809 with the previous instruction.
3810 ADDRESS_EXPR is an operand of the instruction to be used with
3814 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3815 bfd_reloc_code_real_type
*reloc_type
)
3817 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3818 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3820 /* -O2 and above is required for this optimization. */
3821 if (mips_optimize
< 2)
3824 /* If we have seen .set volatile or .set nomove, don't optimize. */
3825 if (mips_opts
.nomove
)
3828 /* We can't swap if the previous instruction's position is fixed. */
3829 if (history
[0].fixed_p
)
3832 /* If the previous previous insn was in a .set noreorder, we can't
3833 swap. Actually, the MIPS assembler will swap in this situation.
3834 However, gcc configured -with-gnu-as will generate code like
3842 in which we can not swap the bne and INSN. If gcc is not configured
3843 -with-gnu-as, it does not output the .set pseudo-ops. */
3844 if (history
[1].noreorder_p
)
3847 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3848 This means that the previous instruction was a 4-byte one anyhow. */
3849 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3852 /* If the branch is itself the target of a branch, we can not swap.
3853 We cheat on this; all we check for is whether there is a label on
3854 this instruction. If there are any branches to anything other than
3855 a label, users must use .set noreorder. */
3856 if (seg_info (now_seg
)->label_list
)
3859 /* If the previous instruction is in a variant frag other than this
3860 branch's one, we cannot do the swap. This does not apply to
3861 MIPS16 code, which uses variant frags for different purposes. */
3862 if (!mips_opts
.mips16
3864 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3867 /* We do not swap with instructions that cannot architecturally
3868 be placed in a branch delay slot, such as SYNC or ERET. We
3869 also refrain from swapping with a trap instruction, since it
3870 complicates trap handlers to have the trap instruction be in
3872 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3873 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3876 /* Check for conflicts between the branch and the instructions
3877 before the candidate delay slot. */
3878 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3881 /* Check for conflicts between the swapped sequence and the
3882 target of the branch. */
3883 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3886 /* If the branch reads a register that the previous
3887 instruction sets, we can not swap. */
3888 gpr_read
= gpr_read_mask (ip
);
3889 prev_gpr_write
= gpr_write_mask (&history
[0]);
3890 if (gpr_read
& prev_gpr_write
)
3893 /* If the branch writes a register that the previous
3894 instruction sets, we can not swap. */
3895 gpr_write
= gpr_write_mask (ip
);
3896 if (gpr_write
& prev_gpr_write
)
3899 /* If the branch writes a register that the previous
3900 instruction reads, we can not swap. */
3901 prev_gpr_read
= gpr_read_mask (&history
[0]);
3902 if (gpr_write
& prev_gpr_read
)
3905 /* If one instruction sets a condition code and the
3906 other one uses a condition code, we can not swap. */
3907 pinfo
= ip
->insn_mo
->pinfo
;
3908 if ((pinfo
& INSN_READ_COND_CODE
)
3909 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3911 if ((pinfo
& INSN_WRITE_COND_CODE
)
3912 && (prev_pinfo
& INSN_READ_COND_CODE
))
3915 /* If the previous instruction uses the PC, we can not swap. */
3916 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3917 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3919 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3922 /* If the previous instruction has an incorrect size for a fixed
3923 branch delay slot in microMIPS mode, we cannot swap. */
3924 pinfo2
= ip
->insn_mo
->pinfo2
;
3925 if (mips_opts
.micromips
3926 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3927 && insn_length (history
) != 2)
3929 if (mips_opts
.micromips
3930 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3931 && insn_length (history
) != 4)
3934 /* On R5900 short loops need to be fixed by inserting a nop in
3935 the branch delay slots.
3936 A short loop can be terminated too early. */
3937 if (mips_opts
.arch
== CPU_R5900
3938 /* Check if instruction has a parameter, ignore "j $31". */
3939 && (address_expr
!= NULL
)
3940 /* Parameter must be 16 bit. */
3941 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
3942 /* Branch to same segment. */
3943 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
3944 /* Branch to same code fragment. */
3945 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
3946 /* Can only calculate branch offset if value is known. */
3947 && symbol_constant_p(address_expr
->X_add_symbol
)
3948 /* Check if branch is really conditional. */
3949 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
3950 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
3951 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
3954 /* Check if loop is shorter than 6 instructions including
3955 branch and delay slot. */
3956 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
3963 /* When the loop includes branches or jumps,
3964 it is not a short loop. */
3965 for (i
= 0; i
< (distance
/ 4); i
++)
3967 if ((history
[i
].cleared_p
)
3968 || delayed_branch_p(&history
[i
]))
3976 /* Insert nop after branch to fix short loop. */
3985 /* Decide how we should add IP to the instruction stream.
3986 ADDRESS_EXPR is an operand of the instruction to be used with
3989 static enum append_method
3990 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3991 bfd_reloc_code_real_type
*reloc_type
)
3993 unsigned long pinfo
;
3995 /* The relaxed version of a macro sequence must be inherently
3997 if (mips_relax
.sequence
== 2)
4000 /* We must not dabble with instructions in a ".set norerorder" block. */
4001 if (mips_opts
.noreorder
)
4004 /* Otherwise, it's our responsibility to fill branch delay slots. */
4005 if (delayed_branch_p (ip
))
4007 if (!branch_likely_p (ip
)
4008 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
4011 pinfo
= ip
->insn_mo
->pinfo
;
4012 if (mips_opts
.mips16
4013 && ISA_SUPPORTS_MIPS16E
4014 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
4015 return APPEND_ADD_COMPACT
;
4017 return APPEND_ADD_WITH_NOP
;
4023 /* IP is a MIPS16 instruction whose opcode we have just changed.
4024 Point IP->insn_mo to the new opcode's definition. */
4027 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
4029 const struct mips_opcode
*mo
, *end
;
4031 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
4032 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
4033 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
4041 /* For microMIPS macros, we need to generate a local number label
4042 as the target of branches. */
4043 #define MICROMIPS_LABEL_CHAR '\037'
4044 static unsigned long micromips_target_label
;
4045 static char micromips_target_name
[32];
4048 micromips_label_name (void)
4050 char *p
= micromips_target_name
;
4051 char symbol_name_temporary
[24];
4059 l
= micromips_target_label
;
4060 #ifdef LOCAL_LABEL_PREFIX
4061 *p
++ = LOCAL_LABEL_PREFIX
;
4064 *p
++ = MICROMIPS_LABEL_CHAR
;
4067 symbol_name_temporary
[i
++] = l
% 10 + '0';
4072 *p
++ = symbol_name_temporary
[--i
];
4075 return micromips_target_name
;
4079 micromips_label_expr (expressionS
*label_expr
)
4081 label_expr
->X_op
= O_symbol
;
4082 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4083 label_expr
->X_add_number
= 0;
4087 micromips_label_inc (void)
4089 micromips_target_label
++;
4090 *micromips_target_name
= '\0';
4094 micromips_add_label (void)
4098 s
= colon (micromips_label_name ());
4099 micromips_label_inc ();
4100 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4102 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4108 /* If assembling microMIPS code, then return the microMIPS reloc
4109 corresponding to the requested one if any. Otherwise return
4110 the reloc unchanged. */
4112 static bfd_reloc_code_real_type
4113 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4115 static const bfd_reloc_code_real_type relocs
[][2] =
4117 /* Keep sorted incrementally by the left-hand key. */
4118 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4119 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4120 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4121 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4122 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4123 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4124 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4125 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4126 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4127 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4128 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4129 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4130 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4131 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4132 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4133 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4134 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4135 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4136 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4137 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4138 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4139 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4140 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4141 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4142 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4143 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4144 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4146 bfd_reloc_code_real_type r
;
4149 if (!mips_opts
.micromips
)
4151 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4157 return relocs
[i
][1];
4162 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4163 Return true on success, storing the resolved value in RESULT. */
4166 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4171 case BFD_RELOC_MIPS_HIGHEST
:
4172 case BFD_RELOC_MICROMIPS_HIGHEST
:
4173 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4176 case BFD_RELOC_MIPS_HIGHER
:
4177 case BFD_RELOC_MICROMIPS_HIGHER
:
4178 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4181 case BFD_RELOC_HI16_S
:
4182 case BFD_RELOC_MICROMIPS_HI16_S
:
4183 case BFD_RELOC_MIPS16_HI16_S
:
4184 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4187 case BFD_RELOC_HI16
:
4188 case BFD_RELOC_MICROMIPS_HI16
:
4189 case BFD_RELOC_MIPS16_HI16
:
4190 *result
= (operand
>> 16) & 0xffff;
4193 case BFD_RELOC_LO16
:
4194 case BFD_RELOC_MICROMIPS_LO16
:
4195 case BFD_RELOC_MIPS16_LO16
:
4196 *result
= operand
& 0xffff;
4199 case BFD_RELOC_UNUSED
:
4208 /* Output an instruction. IP is the instruction information.
4209 ADDRESS_EXPR is an operand of the instruction to be used with
4210 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4211 a macro expansion. */
4214 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4215 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4217 unsigned long prev_pinfo2
, pinfo
;
4218 bfd_boolean relaxed_branch
= FALSE
;
4219 enum append_method method
;
4220 bfd_boolean relax32
;
4223 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4224 fix_loongson2f (ip
);
4226 file_ase_mips16
|= mips_opts
.mips16
;
4227 file_ase_micromips
|= mips_opts
.micromips
;
4229 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4230 pinfo
= ip
->insn_mo
->pinfo
;
4232 if (mips_opts
.micromips
4234 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4235 && micromips_insn_length (ip
->insn_mo
) != 2)
4236 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4237 && micromips_insn_length (ip
->insn_mo
) != 4)))
4238 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4239 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4241 if (address_expr
== NULL
)
4243 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4244 && reloc_type
[1] == BFD_RELOC_UNUSED
4245 && reloc_type
[2] == BFD_RELOC_UNUSED
4246 && address_expr
->X_op
== O_constant
)
4248 switch (*reloc_type
)
4250 case BFD_RELOC_MIPS_JMP
:
4254 shift
= mips_opts
.micromips
? 1 : 2;
4255 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4256 as_bad (_("jump to misaligned address (0x%lx)"),
4257 (unsigned long) address_expr
->X_add_number
);
4258 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4264 case BFD_RELOC_MIPS16_JMP
:
4265 if ((address_expr
->X_add_number
& 3) != 0)
4266 as_bad (_("jump to misaligned address (0x%lx)"),
4267 (unsigned long) address_expr
->X_add_number
);
4269 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4270 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4271 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4275 case BFD_RELOC_16_PCREL_S2
:
4279 shift
= mips_opts
.micromips
? 1 : 2;
4280 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4281 as_bad (_("branch to misaligned address (0x%lx)"),
4282 (unsigned long) address_expr
->X_add_number
);
4283 if (!mips_relax_branch
)
4285 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4286 & ~((1 << (shift
+ 16)) - 1))
4287 as_bad (_("branch address range overflow (0x%lx)"),
4288 (unsigned long) address_expr
->X_add_number
);
4289 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4299 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4302 ip
->insn_opcode
|= value
& 0xffff;
4310 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4312 /* There are a lot of optimizations we could do that we don't.
4313 In particular, we do not, in general, reorder instructions.
4314 If you use gcc with optimization, it will reorder
4315 instructions and generally do much more optimization then we
4316 do here; repeating all that work in the assembler would only
4317 benefit hand written assembly code, and does not seem worth
4319 int nops
= (mips_optimize
== 0
4320 ? nops_for_insn (0, history
, NULL
)
4321 : nops_for_insn_or_target (0, history
, ip
));
4325 unsigned long old_frag_offset
;
4328 old_frag
= frag_now
;
4329 old_frag_offset
= frag_now_fix ();
4331 for (i
= 0; i
< nops
; i
++)
4332 add_fixed_insn (NOP_INSN
);
4333 insert_into_history (0, nops
, NOP_INSN
);
4337 listing_prev_line ();
4338 /* We may be at the start of a variant frag. In case we
4339 are, make sure there is enough space for the frag
4340 after the frags created by listing_prev_line. The
4341 argument to frag_grow here must be at least as large
4342 as the argument to all other calls to frag_grow in
4343 this file. We don't have to worry about being in the
4344 middle of a variant frag, because the variants insert
4345 all needed nop instructions themselves. */
4349 mips_move_text_labels ();
4351 #ifndef NO_ECOFF_DEBUGGING
4352 if (ECOFF_DEBUGGING
)
4353 ecoff_fix_loc (old_frag
, old_frag_offset
);
4357 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4361 /* Work out how many nops in prev_nop_frag are needed by IP,
4362 ignoring hazards generated by the first prev_nop_frag_since
4364 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4365 gas_assert (nops
<= prev_nop_frag_holds
);
4367 /* Enforce NOPS as a minimum. */
4368 if (nops
> prev_nop_frag_required
)
4369 prev_nop_frag_required
= nops
;
4371 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4373 /* Settle for the current number of nops. Update the history
4374 accordingly (for the benefit of any future .set reorder code). */
4375 prev_nop_frag
= NULL
;
4376 insert_into_history (prev_nop_frag_since
,
4377 prev_nop_frag_holds
, NOP_INSN
);
4381 /* Allow this instruction to replace one of the nops that was
4382 tentatively added to prev_nop_frag. */
4383 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4384 prev_nop_frag_holds
--;
4385 prev_nop_frag_since
++;
4389 method
= get_append_method (ip
, address_expr
, reloc_type
);
4390 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4393 dwarf2_emit_insn (0);
4394 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4395 so "move" the instruction address accordingly.
4397 Also, it doesn't seem appropriate for the assembler to reorder .loc
4398 entries. If this instruction is a branch that we are going to swap
4399 with the previous instruction, the two instructions should be
4400 treated as a unit, and the debug information for both instructions
4401 should refer to the start of the branch sequence. Using the
4402 current position is certainly wrong when swapping a 32-bit branch
4403 and a 16-bit delay slot, since the current position would then be
4404 in the middle of a branch. */
4405 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
4408 relax32
= (mips_relax_branch
4409 /* Don't try branch relaxation within .set nomacro, or within
4410 .set noat if we use $at for PIC computations. If it turns
4411 out that the branch was out-of-range, we'll get an error. */
4412 && !mips_opts
.warn_about_macros
4413 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4414 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4415 as they have no complementing branches. */
4416 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
4418 if (!HAVE_CODE_COMPRESSION
4421 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4422 && delayed_branch_p (ip
))
4424 relaxed_branch
= TRUE
;
4425 add_relaxed_insn (ip
, (relaxed_branch_length
4427 uncond_branch_p (ip
) ? -1
4428 : branch_likely_p (ip
) ? 1
4432 uncond_branch_p (ip
),
4433 branch_likely_p (ip
),
4434 pinfo
& INSN_WRITE_GPR_31
,
4436 address_expr
->X_add_symbol
,
4437 address_expr
->X_add_number
);
4438 *reloc_type
= BFD_RELOC_UNUSED
;
4440 else if (mips_opts
.micromips
4442 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4443 || *reloc_type
> BFD_RELOC_UNUSED
)
4444 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4445 /* Don't try branch relaxation when users specify
4446 16-bit/32-bit instructions. */
4447 && !forced_insn_length
)
4449 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4450 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4451 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4452 int compact
= compact_branch_p (ip
);
4453 int al
= pinfo
& INSN_WRITE_GPR_31
;
4456 gas_assert (address_expr
!= NULL
);
4457 gas_assert (!mips_relax
.sequence
);
4459 relaxed_branch
= TRUE
;
4460 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4461 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4462 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4464 address_expr
->X_add_symbol
,
4465 address_expr
->X_add_number
);
4466 *reloc_type
= BFD_RELOC_UNUSED
;
4468 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4470 /* We need to set up a variant frag. */
4471 gas_assert (address_expr
!= NULL
);
4472 add_relaxed_insn (ip
, 4, 0,
4474 (*reloc_type
- BFD_RELOC_UNUSED
,
4475 forced_insn_length
== 2, forced_insn_length
== 4,
4476 delayed_branch_p (&history
[0]),
4477 history
[0].mips16_absolute_jump_p
),
4478 make_expr_symbol (address_expr
), 0);
4480 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4482 if (!delayed_branch_p (ip
))
4483 /* Make sure there is enough room to swap this instruction with
4484 a following jump instruction. */
4486 add_fixed_insn (ip
);
4490 if (mips_opts
.mips16
4491 && mips_opts
.noreorder
4492 && delayed_branch_p (&history
[0]))
4493 as_warn (_("extended instruction in delay slot"));
4495 if (mips_relax
.sequence
)
4497 /* If we've reached the end of this frag, turn it into a variant
4498 frag and record the information for the instructions we've
4500 if (frag_room () < 4)
4501 relax_close_frag ();
4502 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4505 if (mips_relax
.sequence
!= 2)
4507 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4508 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4509 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4510 mips_macro_warning
.insns
[0]++;
4512 if (mips_relax
.sequence
!= 1)
4514 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4515 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4516 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4517 mips_macro_warning
.insns
[1]++;
4520 if (mips_opts
.mips16
)
4523 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4525 add_fixed_insn (ip
);
4528 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4530 bfd_reloc_code_real_type final_type
[3];
4531 reloc_howto_type
*howto0
;
4532 reloc_howto_type
*howto
;
4535 /* Perform any necessary conversion to microMIPS relocations
4536 and find out how many relocations there actually are. */
4537 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4538 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4540 /* In a compound relocation, it is the final (outermost)
4541 operator that determines the relocated field. */
4542 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4546 /* To reproduce this failure try assembling gas/testsuites/
4547 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4549 as_bad (_("Unsupported MIPS relocation number %d"),
4551 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4555 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4556 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4557 bfd_get_reloc_size (howto
),
4559 howto0
&& howto0
->pc_relative
,
4562 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4563 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4564 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4566 /* These relocations can have an addend that won't fit in
4567 4 octets for 64bit assembly. */
4569 && ! howto
->partial_inplace
4570 && (reloc_type
[0] == BFD_RELOC_16
4571 || reloc_type
[0] == BFD_RELOC_32
4572 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4573 || reloc_type
[0] == BFD_RELOC_GPREL16
4574 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4575 || reloc_type
[0] == BFD_RELOC_GPREL32
4576 || reloc_type
[0] == BFD_RELOC_64
4577 || reloc_type
[0] == BFD_RELOC_CTOR
4578 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4579 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4580 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4581 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4582 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4583 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4584 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4585 || hi16_reloc_p (reloc_type
[0])
4586 || lo16_reloc_p (reloc_type
[0])))
4587 ip
->fixp
[0]->fx_no_overflow
= 1;
4589 /* These relocations can have an addend that won't fit in 2 octets. */
4590 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4591 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4592 ip
->fixp
[0]->fx_no_overflow
= 1;
4594 if (mips_relax
.sequence
)
4596 if (mips_relax
.first_fixup
== 0)
4597 mips_relax
.first_fixup
= ip
->fixp
[0];
4599 else if (reloc_needs_lo_p (*reloc_type
))
4601 struct mips_hi_fixup
*hi_fixup
;
4603 /* Reuse the last entry if it already has a matching %lo. */
4604 hi_fixup
= mips_hi_fixup_list
;
4606 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4608 hi_fixup
= ((struct mips_hi_fixup
*)
4609 xmalloc (sizeof (struct mips_hi_fixup
)));
4610 hi_fixup
->next
= mips_hi_fixup_list
;
4611 mips_hi_fixup_list
= hi_fixup
;
4613 hi_fixup
->fixp
= ip
->fixp
[0];
4614 hi_fixup
->seg
= now_seg
;
4617 /* Add fixups for the second and third relocations, if given.
4618 Note that the ABI allows the second relocation to be
4619 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4620 moment we only use RSS_UNDEF, but we could add support
4621 for the others if it ever becomes necessary. */
4622 for (i
= 1; i
< 3; i
++)
4623 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4625 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4626 ip
->fixp
[0]->fx_size
, NULL
, 0,
4627 FALSE
, final_type
[i
]);
4629 /* Use fx_tcbit to mark compound relocs. */
4630 ip
->fixp
[0]->fx_tcbit
= 1;
4631 ip
->fixp
[i
]->fx_tcbit
= 1;
4636 /* Update the register mask information. */
4637 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4638 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4643 insert_into_history (0, 1, ip
);
4646 case APPEND_ADD_WITH_NOP
:
4648 struct mips_cl_insn
*nop
;
4650 insert_into_history (0, 1, ip
);
4651 nop
= get_delay_slot_nop (ip
);
4652 add_fixed_insn (nop
);
4653 insert_into_history (0, 1, nop
);
4654 if (mips_relax
.sequence
)
4655 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4659 case APPEND_ADD_COMPACT
:
4660 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4661 gas_assert (mips_opts
.mips16
);
4662 ip
->insn_opcode
|= 0x0080;
4663 find_altered_mips16_opcode (ip
);
4665 insert_into_history (0, 1, ip
);
4670 struct mips_cl_insn delay
= history
[0];
4671 if (mips_opts
.mips16
)
4673 know (delay
.frag
== ip
->frag
);
4674 move_insn (ip
, delay
.frag
, delay
.where
);
4675 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4677 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4679 /* Add the delay slot instruction to the end of the
4680 current frag and shrink the fixed part of the
4681 original frag. If the branch occupies the tail of
4682 the latter, move it backwards to cover the gap. */
4683 delay
.frag
->fr_fix
-= branch_disp
;
4684 if (delay
.frag
== ip
->frag
)
4685 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4686 add_fixed_insn (&delay
);
4690 move_insn (&delay
, ip
->frag
,
4691 ip
->where
- branch_disp
+ insn_length (ip
));
4692 move_insn (ip
, history
[0].frag
, history
[0].where
);
4696 insert_into_history (0, 1, &delay
);
4701 /* If we have just completed an unconditional branch, clear the history. */
4702 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4703 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4707 mips_no_prev_insn ();
4709 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4710 history
[i
].cleared_p
= 1;
4713 /* We need to emit a label at the end of branch-likely macros. */
4714 if (emit_branch_likely_macro
)
4716 emit_branch_likely_macro
= FALSE
;
4717 micromips_add_label ();
4720 /* We just output an insn, so the next one doesn't have a label. */
4721 mips_clear_insn_labels ();
4724 /* Forget that there was any previous instruction or label.
4725 When BRANCH is true, the branch history is also flushed. */
4728 mips_no_prev_insn (void)
4730 prev_nop_frag
= NULL
;
4731 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4732 mips_clear_insn_labels ();
4735 /* This function must be called before we emit something other than
4736 instructions. It is like mips_no_prev_insn except that it inserts
4737 any NOPS that might be needed by previous instructions. */
4740 mips_emit_delays (void)
4742 if (! mips_opts
.noreorder
)
4744 int nops
= nops_for_insn (0, history
, NULL
);
4748 add_fixed_insn (NOP_INSN
);
4749 mips_move_text_labels ();
4752 mips_no_prev_insn ();
4755 /* Start a (possibly nested) noreorder block. */
4758 start_noreorder (void)
4760 if (mips_opts
.noreorder
== 0)
4765 /* None of the instructions before the .set noreorder can be moved. */
4766 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4767 history
[i
].fixed_p
= 1;
4769 /* Insert any nops that might be needed between the .set noreorder
4770 block and the previous instructions. We will later remove any
4771 nops that turn out not to be needed. */
4772 nops
= nops_for_insn (0, history
, NULL
);
4775 if (mips_optimize
!= 0)
4777 /* Record the frag which holds the nop instructions, so
4778 that we can remove them if we don't need them. */
4779 frag_grow (nops
* NOP_INSN_SIZE
);
4780 prev_nop_frag
= frag_now
;
4781 prev_nop_frag_holds
= nops
;
4782 prev_nop_frag_required
= 0;
4783 prev_nop_frag_since
= 0;
4786 for (; nops
> 0; --nops
)
4787 add_fixed_insn (NOP_INSN
);
4789 /* Move on to a new frag, so that it is safe to simply
4790 decrease the size of prev_nop_frag. */
4791 frag_wane (frag_now
);
4793 mips_move_text_labels ();
4795 mips_mark_labels ();
4796 mips_clear_insn_labels ();
4798 mips_opts
.noreorder
++;
4799 mips_any_noreorder
= 1;
4802 /* End a nested noreorder block. */
4805 end_noreorder (void)
4807 mips_opts
.noreorder
--;
4808 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4810 /* Commit to inserting prev_nop_frag_required nops and go back to
4811 handling nop insertion the .set reorder way. */
4812 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4814 insert_into_history (prev_nop_frag_since
,
4815 prev_nop_frag_required
, NOP_INSN
);
4816 prev_nop_frag
= NULL
;
4820 /* Set up global variables for the start of a new macro. */
4825 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4826 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4827 sizeof (mips_macro_warning
.first_insn_sizes
));
4828 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4829 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4830 && delayed_branch_p (&history
[0]));
4831 switch (history
[0].insn_mo
->pinfo2
4832 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4834 case INSN2_BRANCH_DELAY_32BIT
:
4835 mips_macro_warning
.delay_slot_length
= 4;
4837 case INSN2_BRANCH_DELAY_16BIT
:
4838 mips_macro_warning
.delay_slot_length
= 2;
4841 mips_macro_warning
.delay_slot_length
= 0;
4844 mips_macro_warning
.first_frag
= NULL
;
4847 /* Given that a macro is longer than one instruction or of the wrong size,
4848 return the appropriate warning for it. Return null if no warning is
4849 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4850 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4851 and RELAX_NOMACRO. */
4854 macro_warning (relax_substateT subtype
)
4856 if (subtype
& RELAX_DELAY_SLOT
)
4857 return _("Macro instruction expanded into multiple instructions"
4858 " in a branch delay slot");
4859 else if (subtype
& RELAX_NOMACRO
)
4860 return _("Macro instruction expanded into multiple instructions");
4861 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4862 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4863 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4864 ? _("Macro instruction expanded into a wrong size instruction"
4865 " in a 16-bit branch delay slot")
4866 : _("Macro instruction expanded into a wrong size instruction"
4867 " in a 32-bit branch delay slot"));
4872 /* Finish up a macro. Emit warnings as appropriate. */
4877 /* Relaxation warning flags. */
4878 relax_substateT subtype
= 0;
4880 /* Check delay slot size requirements. */
4881 if (mips_macro_warning
.delay_slot_length
== 2)
4882 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4883 if (mips_macro_warning
.delay_slot_length
!= 0)
4885 if (mips_macro_warning
.delay_slot_length
4886 != mips_macro_warning
.first_insn_sizes
[0])
4887 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4888 if (mips_macro_warning
.delay_slot_length
4889 != mips_macro_warning
.first_insn_sizes
[1])
4890 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4893 /* Check instruction count requirements. */
4894 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4896 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4897 subtype
|= RELAX_SECOND_LONGER
;
4898 if (mips_opts
.warn_about_macros
)
4899 subtype
|= RELAX_NOMACRO
;
4900 if (mips_macro_warning
.delay_slot_p
)
4901 subtype
|= RELAX_DELAY_SLOT
;
4904 /* If both alternatives fail to fill a delay slot correctly,
4905 emit the warning now. */
4906 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4907 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4912 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4913 | RELAX_DELAY_SLOT_SIZE_FIRST
4914 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4915 msg
= macro_warning (s
);
4917 as_warn ("%s", msg
);
4921 /* If both implementations are longer than 1 instruction, then emit the
4923 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4928 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4929 msg
= macro_warning (s
);
4931 as_warn ("%s", msg
);
4935 /* If any flags still set, then one implementation might need a warning
4936 and the other either will need one of a different kind or none at all.
4937 Pass any remaining flags over to relaxation. */
4938 if (mips_macro_warning
.first_frag
!= NULL
)
4939 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4942 /* Instruction operand formats used in macros that vary between
4943 standard MIPS and microMIPS code. */
4945 static const char * const brk_fmt
[2] = { "c", "mF" };
4946 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4947 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4948 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4949 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4950 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4951 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4952 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4954 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4955 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4956 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4957 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4958 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4959 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4960 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4961 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4963 /* Read a macro's relocation codes from *ARGS and store them in *R.
4964 The first argument in *ARGS will be either the code for a single
4965 relocation or -1 followed by the three codes that make up a
4966 composite relocation. */
4969 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4973 next
= va_arg (*args
, int);
4975 r
[0] = (bfd_reloc_code_real_type
) next
;
4977 for (i
= 0; i
< 3; i
++)
4978 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4981 /* Build an instruction created by a macro expansion. This is passed
4982 a pointer to the count of instructions created so far, an
4983 expression, the name of the instruction to build, an operand format
4984 string, and corresponding arguments. */
4987 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4989 const struct mips_opcode
*mo
= NULL
;
4990 bfd_reloc_code_real_type r
[3];
4991 const struct mips_opcode
*amo
;
4992 struct hash_control
*hash
;
4993 struct mips_cl_insn insn
;
4996 va_start (args
, fmt
);
4998 if (mips_opts
.mips16
)
5000 mips16_macro_build (ep
, name
, fmt
, &args
);
5005 r
[0] = BFD_RELOC_UNUSED
;
5006 r
[1] = BFD_RELOC_UNUSED
;
5007 r
[2] = BFD_RELOC_UNUSED
;
5008 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
5009 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
5011 gas_assert (strcmp (name
, amo
->name
) == 0);
5015 /* Search until we get a match for NAME. It is assumed here that
5016 macros will never generate MDMX, MIPS-3D, or MT instructions.
5017 We try to match an instruction that fulfils the branch delay
5018 slot instruction length requirement (if any) of the previous
5019 instruction. While doing this we record the first instruction
5020 seen that matches all the other conditions and use it anyway
5021 if the requirement cannot be met; we will issue an appropriate
5022 warning later on. */
5023 if (strcmp (fmt
, amo
->args
) == 0
5024 && amo
->pinfo
!= INSN_MACRO
5025 && is_opcode_valid (amo
)
5026 && is_size_valid (amo
))
5028 if (is_delay_slot_valid (amo
))
5038 gas_assert (amo
->name
);
5040 while (strcmp (name
, amo
->name
) == 0);
5043 create_insn (&insn
, mo
);
5061 INSERT_OPERAND (mips_opts
.micromips
,
5062 EXTLSB
, insn
, va_arg (args
, int));
5067 /* Note that in the macro case, these arguments are already
5068 in MSB form. (When handling the instruction in the
5069 non-macro case, these arguments are sizes from which
5070 MSB values must be calculated.) */
5071 INSERT_OPERAND (mips_opts
.micromips
,
5072 INSMSB
, insn
, va_arg (args
, int));
5076 gas_assert (!mips_opts
.micromips
);
5077 INSERT_OPERAND (0, CODE10
, insn
, va_arg (args
, int));
5083 /* Note that in the macro case, these arguments are already
5084 in MSBD form. (When handling the instruction in the
5085 non-macro case, these arguments are sizes from which
5086 MSBD values must be calculated.) */
5087 INSERT_OPERAND (mips_opts
.micromips
,
5088 EXTMSBD
, insn
, va_arg (args
, int));
5092 gas_assert (!mips_opts
.micromips
);
5093 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5097 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, insn
, va_arg (args
, int));
5106 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5110 gas_assert (mips_opts
.micromips
);
5114 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5118 gas_assert (!mips_opts
.micromips
);
5119 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
5123 gas_assert (!mips_opts
.micromips
);
5125 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5129 if (mips_opts
.micromips
)
5130 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5132 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5136 gas_assert (!mips_opts
.micromips
);
5138 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5142 gas_assert (!mips_opts
.micromips
);
5144 int tmp
= va_arg (args
, int);
5146 INSERT_OPERAND (0, RT
, insn
, tmp
);
5147 INSERT_OPERAND (0, RD
, insn
, tmp
);
5153 gas_assert (!mips_opts
.micromips
);
5154 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5161 INSERT_OPERAND (mips_opts
.micromips
,
5162 SHAMT
, insn
, va_arg (args
, int));
5166 gas_assert (!mips_opts
.micromips
);
5167 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5171 gas_assert (!mips_opts
.micromips
);
5172 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5176 gas_assert (!mips_opts
.micromips
);
5177 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5181 gas_assert (!mips_opts
.micromips
);
5182 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5189 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5194 macro_read_relocs (&args
, r
);
5195 gas_assert (*r
== BFD_RELOC_GPREL16
5196 || *r
== BFD_RELOC_MIPS_HIGHER
5197 || *r
== BFD_RELOC_HI16_S
5198 || *r
== BFD_RELOC_LO16
5199 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5203 macro_read_relocs (&args
, r
);
5207 macro_read_relocs (&args
, r
);
5208 gas_assert (ep
!= NULL
5209 && (ep
->X_op
== O_constant
5210 || (ep
->X_op
== O_symbol
5211 && (*r
== BFD_RELOC_MIPS_HIGHEST
5212 || *r
== BFD_RELOC_HI16_S
5213 || *r
== BFD_RELOC_HI16
5214 || *r
== BFD_RELOC_GPREL16
5215 || *r
== BFD_RELOC_MIPS_GOT_HI16
5216 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5220 gas_assert (ep
!= NULL
);
5223 * This allows macro() to pass an immediate expression for
5224 * creating short branches without creating a symbol.
5226 * We don't allow branch relaxation for these branches, as
5227 * they should only appear in ".set nomacro" anyway.
5229 if (ep
->X_op
== O_constant
)
5231 /* For microMIPS we always use relocations for branches.
5232 So we should not resolve immediate values. */
5233 gas_assert (!mips_opts
.micromips
);
5235 if ((ep
->X_add_number
& 3) != 0)
5236 as_bad (_("branch to misaligned address (0x%lx)"),
5237 (unsigned long) ep
->X_add_number
);
5238 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5239 as_bad (_("branch address range overflow (0x%lx)"),
5240 (unsigned long) ep
->X_add_number
);
5241 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5245 *r
= BFD_RELOC_16_PCREL_S2
;
5249 gas_assert (ep
!= NULL
);
5250 *r
= BFD_RELOC_MIPS_JMP
;
5254 gas_assert (!mips_opts
.micromips
);
5255 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5259 INSERT_OPERAND (mips_opts
.micromips
,
5260 CACHE
, insn
, va_arg (args
, unsigned long));
5264 gas_assert (mips_opts
.micromips
);
5265 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5269 gas_assert (mips_opts
.micromips
);
5270 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5274 INSERT_OPERAND (mips_opts
.micromips
,
5275 3BITPOS
, insn
, va_arg (args
, unsigned int));
5279 INSERT_OPERAND (mips_opts
.micromips
,
5280 OFFSET12
, insn
, va_arg (args
, unsigned long));
5284 gas_assert (mips_opts
.micromips
);
5285 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5288 case 'm': /* Opcode extension character. */
5289 gas_assert (mips_opts
.micromips
);
5293 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5297 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5301 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5315 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5317 append_insn (&insn
, ep
, r
, TRUE
);
5321 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5324 struct mips_opcode
*mo
;
5325 struct mips_cl_insn insn
;
5326 bfd_reloc_code_real_type r
[3]
5327 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5329 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5331 gas_assert (strcmp (name
, mo
->name
) == 0);
5333 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5336 gas_assert (mo
->name
);
5337 gas_assert (strcmp (name
, mo
->name
) == 0);
5340 create_insn (&insn
, mo
);
5358 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5363 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5367 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5371 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5381 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5388 regno
= va_arg (*args
, int);
5389 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5390 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5413 gas_assert (ep
!= NULL
);
5415 if (ep
->X_op
!= O_constant
)
5416 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5417 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5419 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5421 *r
= BFD_RELOC_UNUSED
;
5427 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5434 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5436 append_insn (&insn
, ep
, r
, TRUE
);
5440 * Sign-extend 32-bit mode constants that have bit 31 set and all
5441 * higher bits unset.
5444 normalize_constant_expr (expressionS
*ex
)
5446 if (ex
->X_op
== O_constant
5447 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5448 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5453 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5454 * all higher bits unset.
5457 normalize_address_expr (expressionS
*ex
)
5459 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5460 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5461 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5462 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5467 * Generate a "jalr" instruction with a relocation hint to the called
5468 * function. This occurs in NewABI PIC code.
5471 macro_build_jalr (expressionS
*ep
, int cprestore
)
5473 static const bfd_reloc_code_real_type jalr_relocs
[2]
5474 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5475 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5479 if (MIPS_JALR_HINT_P (ep
))
5484 if (mips_opts
.micromips
)
5486 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5487 if (MIPS_JALR_HINT_P (ep
)
5488 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5489 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5491 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5494 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5495 if (MIPS_JALR_HINT_P (ep
))
5496 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5500 * Generate a "lui" instruction.
5503 macro_build_lui (expressionS
*ep
, int regnum
)
5505 gas_assert (! mips_opts
.mips16
);
5507 if (ep
->X_op
!= O_constant
)
5509 gas_assert (ep
->X_op
== O_symbol
);
5510 /* _gp_disp is a special case, used from s_cpload.
5511 __gnu_local_gp is used if mips_no_shared. */
5512 gas_assert (mips_pic
== NO_PIC
5514 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5515 || (! mips_in_shared
5516 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5517 "__gnu_local_gp") == 0));
5520 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5523 /* Generate a sequence of instructions to do a load or store from a constant
5524 offset off of a base register (breg) into/from a target register (treg),
5525 using AT if necessary. */
5527 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5528 int treg
, int breg
, int dbl
)
5530 gas_assert (ep
->X_op
== O_constant
);
5532 /* Sign-extending 32-bit constants makes their handling easier. */
5534 normalize_constant_expr (ep
);
5536 /* Right now, this routine can only handle signed 32-bit constants. */
5537 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5538 as_warn (_("operand overflow"));
5540 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5542 /* Signed 16-bit offset will fit in the op. Easy! */
5543 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5547 /* 32-bit offset, need multiple instructions and AT, like:
5548 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5549 addu $tempreg,$tempreg,$breg
5550 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5551 to handle the complete offset. */
5552 macro_build_lui (ep
, AT
);
5553 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5554 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5557 as_bad (_("Macro used $at after \".set noat\""));
5562 * Generates code to set the $at register to true (one)
5563 * if reg is less than the immediate expression.
5566 set_at (int reg
, int unsignedp
)
5568 if (imm_expr
.X_op
== O_constant
5569 && imm_expr
.X_add_number
>= -0x8000
5570 && imm_expr
.X_add_number
< 0x8000)
5571 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5572 AT
, reg
, BFD_RELOC_LO16
);
5575 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5576 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5580 /* Warn if an expression is not a constant. */
5583 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5585 if (ex
->X_op
== O_big
)
5586 as_bad (_("unsupported large constant"));
5587 else if (ex
->X_op
!= O_constant
)
5588 as_bad (_("Instruction %s requires absolute expression"),
5591 if (HAVE_32BIT_GPRS
)
5592 normalize_constant_expr (ex
);
5595 /* Count the leading zeroes by performing a binary chop. This is a
5596 bulky bit of source, but performance is a LOT better for the
5597 majority of values than a simple loop to count the bits:
5598 for (lcnt = 0; (lcnt < 32); lcnt++)
5599 if ((v) & (1 << (31 - lcnt)))
5601 However it is not code size friendly, and the gain will drop a bit
5602 on certain cached systems.
5604 #define COUNT_TOP_ZEROES(v) \
5605 (((v) & ~0xffff) == 0 \
5606 ? ((v) & ~0xff) == 0 \
5607 ? ((v) & ~0xf) == 0 \
5608 ? ((v) & ~0x3) == 0 \
5609 ? ((v) & ~0x1) == 0 \
5614 : ((v) & ~0x7) == 0 \
5617 : ((v) & ~0x3f) == 0 \
5618 ? ((v) & ~0x1f) == 0 \
5621 : ((v) & ~0x7f) == 0 \
5624 : ((v) & ~0xfff) == 0 \
5625 ? ((v) & ~0x3ff) == 0 \
5626 ? ((v) & ~0x1ff) == 0 \
5629 : ((v) & ~0x7ff) == 0 \
5632 : ((v) & ~0x3fff) == 0 \
5633 ? ((v) & ~0x1fff) == 0 \
5636 : ((v) & ~0x7fff) == 0 \
5639 : ((v) & ~0xffffff) == 0 \
5640 ? ((v) & ~0xfffff) == 0 \
5641 ? ((v) & ~0x3ffff) == 0 \
5642 ? ((v) & ~0x1ffff) == 0 \
5645 : ((v) & ~0x7ffff) == 0 \
5648 : ((v) & ~0x3fffff) == 0 \
5649 ? ((v) & ~0x1fffff) == 0 \
5652 : ((v) & ~0x7fffff) == 0 \
5655 : ((v) & ~0xfffffff) == 0 \
5656 ? ((v) & ~0x3ffffff) == 0 \
5657 ? ((v) & ~0x1ffffff) == 0 \
5660 : ((v) & ~0x7ffffff) == 0 \
5663 : ((v) & ~0x3fffffff) == 0 \
5664 ? ((v) & ~0x1fffffff) == 0 \
5667 : ((v) & ~0x7fffffff) == 0 \
5672 * This routine generates the least number of instructions necessary to load
5673 * an absolute expression value into a register.
5676 load_register (int reg
, expressionS
*ep
, int dbl
)
5679 expressionS hi32
, lo32
;
5681 if (ep
->X_op
!= O_big
)
5683 gas_assert (ep
->X_op
== O_constant
);
5685 /* Sign-extending 32-bit constants makes their handling easier. */
5687 normalize_constant_expr (ep
);
5689 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5691 /* We can handle 16 bit signed values with an addiu to
5692 $zero. No need to ever use daddiu here, since $zero and
5693 the result are always correct in 32 bit mode. */
5694 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5697 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5699 /* We can handle 16 bit unsigned values with an ori to
5701 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5704 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5706 /* 32 bit values require an lui. */
5707 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5708 if ((ep
->X_add_number
& 0xffff) != 0)
5709 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5714 /* The value is larger than 32 bits. */
5716 if (!dbl
|| HAVE_32BIT_GPRS
)
5720 sprintf_vma (value
, ep
->X_add_number
);
5721 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5722 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5726 if (ep
->X_op
!= O_big
)
5729 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5730 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5731 hi32
.X_add_number
&= 0xffffffff;
5733 lo32
.X_add_number
&= 0xffffffff;
5737 gas_assert (ep
->X_add_number
> 2);
5738 if (ep
->X_add_number
== 3)
5739 generic_bignum
[3] = 0;
5740 else if (ep
->X_add_number
> 4)
5741 as_bad (_("Number larger than 64 bits"));
5742 lo32
.X_op
= O_constant
;
5743 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5744 hi32
.X_op
= O_constant
;
5745 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5748 if (hi32
.X_add_number
== 0)
5753 unsigned long hi
, lo
;
5755 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5757 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5759 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5762 if (lo32
.X_add_number
& 0x80000000)
5764 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5765 if (lo32
.X_add_number
& 0xffff)
5766 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5771 /* Check for 16bit shifted constant. We know that hi32 is
5772 non-zero, so start the mask on the first bit of the hi32
5777 unsigned long himask
, lomask
;
5781 himask
= 0xffff >> (32 - shift
);
5782 lomask
= (0xffff << shift
) & 0xffffffff;
5786 himask
= 0xffff << (shift
- 32);
5789 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5790 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5794 tmp
.X_op
= O_constant
;
5796 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5797 | (lo32
.X_add_number
>> shift
));
5799 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5800 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5801 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5802 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5807 while (shift
<= (64 - 16));
5809 /* Find the bit number of the lowest one bit, and store the
5810 shifted value in hi/lo. */
5811 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5812 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5816 while ((lo
& 1) == 0)
5821 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5827 while ((hi
& 1) == 0)
5836 /* Optimize if the shifted value is a (power of 2) - 1. */
5837 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5838 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5840 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5845 /* This instruction will set the register to be all
5847 tmp
.X_op
= O_constant
;
5848 tmp
.X_add_number
= (offsetT
) -1;
5849 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5853 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5854 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5856 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5857 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5862 /* Sign extend hi32 before calling load_register, because we can
5863 generally get better code when we load a sign extended value. */
5864 if ((hi32
.X_add_number
& 0x80000000) != 0)
5865 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5866 load_register (reg
, &hi32
, 0);
5869 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5873 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5881 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5883 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5884 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5890 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5894 mid16
.X_add_number
>>= 16;
5895 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5896 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5899 if ((lo32
.X_add_number
& 0xffff) != 0)
5900 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5904 load_delay_nop (void)
5906 if (!gpr_interlocks
)
5907 macro_build (NULL
, "nop", "");
5910 /* Load an address into a register. */
5913 load_address (int reg
, expressionS
*ep
, int *used_at
)
5915 if (ep
->X_op
!= O_constant
5916 && ep
->X_op
!= O_symbol
)
5918 as_bad (_("expression too complex"));
5919 ep
->X_op
= O_constant
;
5922 if (ep
->X_op
== O_constant
)
5924 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5928 if (mips_pic
== NO_PIC
)
5930 /* If this is a reference to a GP relative symbol, we want
5931 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5933 lui $reg,<sym> (BFD_RELOC_HI16_S)
5934 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5935 If we have an addend, we always use the latter form.
5937 With 64bit address space and a usable $at we want
5938 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5939 lui $at,<sym> (BFD_RELOC_HI16_S)
5940 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5941 daddiu $at,<sym> (BFD_RELOC_LO16)
5945 If $at is already in use, we use a path which is suboptimal
5946 on superscalar processors.
5947 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5948 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5950 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5952 daddiu $reg,<sym> (BFD_RELOC_LO16)
5954 For GP relative symbols in 64bit address space we can use
5955 the same sequence as in 32bit address space. */
5956 if (HAVE_64BIT_SYMBOLS
)
5958 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5959 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5961 relax_start (ep
->X_add_symbol
);
5962 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5963 mips_gp_register
, BFD_RELOC_GPREL16
);
5967 if (*used_at
== 0 && mips_opts
.at
)
5969 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5970 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5971 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5972 BFD_RELOC_MIPS_HIGHER
);
5973 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5974 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5975 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5980 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5981 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5982 BFD_RELOC_MIPS_HIGHER
);
5983 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5984 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5985 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5986 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5989 if (mips_relax
.sequence
)
5994 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5995 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5997 relax_start (ep
->X_add_symbol
);
5998 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5999 mips_gp_register
, BFD_RELOC_GPREL16
);
6002 macro_build_lui (ep
, reg
);
6003 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
6004 reg
, reg
, BFD_RELOC_LO16
);
6005 if (mips_relax
.sequence
)
6009 else if (!mips_big_got
)
6013 /* If this is a reference to an external symbol, we want
6014 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6016 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6018 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6019 If there is a constant, it must be added in after.
6021 If we have NewABI, we want
6022 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6023 unless we're referencing a global symbol with a non-zero
6024 offset, in which case cst must be added separately. */
6027 if (ep
->X_add_number
)
6029 ex
.X_add_number
= ep
->X_add_number
;
6030 ep
->X_add_number
= 0;
6031 relax_start (ep
->X_add_symbol
);
6032 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6033 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6034 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6035 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6036 ex
.X_op
= O_constant
;
6037 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6038 reg
, reg
, BFD_RELOC_LO16
);
6039 ep
->X_add_number
= ex
.X_add_number
;
6042 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6043 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6044 if (mips_relax
.sequence
)
6049 ex
.X_add_number
= ep
->X_add_number
;
6050 ep
->X_add_number
= 0;
6051 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6052 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6054 relax_start (ep
->X_add_symbol
);
6056 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6060 if (ex
.X_add_number
!= 0)
6062 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6063 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6064 ex
.X_op
= O_constant
;
6065 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6066 reg
, reg
, BFD_RELOC_LO16
);
6070 else if (mips_big_got
)
6074 /* This is the large GOT case. If this is a reference to an
6075 external symbol, we want
6076 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6078 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6080 Otherwise, for a reference to a local symbol in old ABI, we want
6081 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6083 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6084 If there is a constant, it must be added in after.
6086 In the NewABI, for local symbols, with or without offsets, we want:
6087 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6088 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6092 ex
.X_add_number
= ep
->X_add_number
;
6093 ep
->X_add_number
= 0;
6094 relax_start (ep
->X_add_symbol
);
6095 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6096 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6097 reg
, reg
, mips_gp_register
);
6098 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6099 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6100 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6101 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6102 else if (ex
.X_add_number
)
6104 ex
.X_op
= O_constant
;
6105 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6109 ep
->X_add_number
= ex
.X_add_number
;
6111 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6112 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6113 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6114 BFD_RELOC_MIPS_GOT_OFST
);
6119 ex
.X_add_number
= ep
->X_add_number
;
6120 ep
->X_add_number
= 0;
6121 relax_start (ep
->X_add_symbol
);
6122 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6123 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6124 reg
, reg
, mips_gp_register
);
6125 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6126 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6128 if (reg_needs_delay (mips_gp_register
))
6130 /* We need a nop before loading from $gp. This special
6131 check is required because the lui which starts the main
6132 instruction stream does not refer to $gp, and so will not
6133 insert the nop which may be required. */
6134 macro_build (NULL
, "nop", "");
6136 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6137 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6139 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6143 if (ex
.X_add_number
!= 0)
6145 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6146 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6147 ex
.X_op
= O_constant
;
6148 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6156 if (!mips_opts
.at
&& *used_at
== 1)
6157 as_bad (_("Macro used $at after \".set noat\""));
6160 /* Move the contents of register SOURCE into register DEST. */
6163 move_register (int dest
, int source
)
6165 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6166 instruction specifically requires a 32-bit one. */
6167 if (mips_opts
.micromips
6168 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6169 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6171 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6175 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6176 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6177 The two alternatives are:
6179 Global symbol Local sybmol
6180 ------------- ------------
6181 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6183 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6185 load_got_offset emits the first instruction and add_got_offset
6186 emits the second for a 16-bit offset or add_got_offset_hilo emits
6187 a sequence to add a 32-bit offset using a scratch register. */
6190 load_got_offset (int dest
, expressionS
*local
)
6195 global
.X_add_number
= 0;
6197 relax_start (local
->X_add_symbol
);
6198 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6199 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6201 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6202 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6207 add_got_offset (int dest
, expressionS
*local
)
6211 global
.X_op
= O_constant
;
6212 global
.X_op_symbol
= NULL
;
6213 global
.X_add_symbol
= NULL
;
6214 global
.X_add_number
= local
->X_add_number
;
6216 relax_start (local
->X_add_symbol
);
6217 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6218 dest
, dest
, BFD_RELOC_LO16
);
6220 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6225 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6228 int hold_mips_optimize
;
6230 global
.X_op
= O_constant
;
6231 global
.X_op_symbol
= NULL
;
6232 global
.X_add_symbol
= NULL
;
6233 global
.X_add_number
= local
->X_add_number
;
6235 relax_start (local
->X_add_symbol
);
6236 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6238 /* Set mips_optimize around the lui instruction to avoid
6239 inserting an unnecessary nop after the lw. */
6240 hold_mips_optimize
= mips_optimize
;
6242 macro_build_lui (&global
, tmp
);
6243 mips_optimize
= hold_mips_optimize
;
6244 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6247 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6250 /* Emit a sequence of instructions to emulate a branch likely operation.
6251 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6252 is its complementing branch with the original condition negated.
6253 CALL is set if the original branch specified the link operation.
6254 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6256 Code like this is produced in the noreorder mode:
6261 delay slot (executed only if branch taken)
6269 delay slot (executed only if branch taken)
6272 In the reorder mode the delay slot would be filled with a nop anyway,
6273 so code produced is simply:
6278 This function is used when producing code for the microMIPS ASE that
6279 does not implement branch likely instructions in hardware. */
6282 macro_build_branch_likely (const char *br
, const char *brneg
,
6283 int call
, expressionS
*ep
, const char *fmt
,
6284 unsigned int sreg
, unsigned int treg
)
6286 int noreorder
= mips_opts
.noreorder
;
6289 gas_assert (mips_opts
.micromips
);
6293 micromips_label_expr (&expr1
);
6294 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6295 macro_build (NULL
, "nop", "");
6296 macro_build (ep
, call
? "bal" : "b", "p");
6298 /* Set to true so that append_insn adds a label. */
6299 emit_branch_likely_macro
= TRUE
;
6303 macro_build (ep
, br
, fmt
, sreg
, treg
);
6304 macro_build (NULL
, "nop", "");
6309 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6310 the condition code tested. EP specifies the branch target. */
6313 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6340 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6343 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6344 the register tested. EP specifies the branch target. */
6347 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6349 const char *brneg
= NULL
;
6359 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6363 gas_assert (mips_opts
.micromips
);
6372 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6379 br
= mips_opts
.micromips
? "blez" : "blezl";
6386 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6390 gas_assert (mips_opts
.micromips
);
6398 if (mips_opts
.micromips
&& brneg
)
6399 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6401 macro_build (ep
, br
, "s,p", sreg
);
6404 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6405 TREG as the registers tested. EP specifies the branch target. */
6408 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6409 unsigned int sreg
, unsigned int treg
)
6411 const char *brneg
= NULL
;
6423 br
= mips_opts
.micromips
? "beq" : "beql";
6432 br
= mips_opts
.micromips
? "bne" : "bnel";
6438 if (mips_opts
.micromips
&& brneg
)
6439 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6441 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6446 * This routine implements the seemingly endless macro or synthesized
6447 * instructions and addressing modes in the mips assembly language. Many
6448 * of these macros are simple and are similar to each other. These could
6449 * probably be handled by some kind of table or grammar approach instead of
6450 * this verbose method. Others are not simple macros but are more like
6451 * optimizing code generation.
6452 * One interesting optimization is when several store macros appear
6453 * consecutively that would load AT with the upper half of the same address.
6454 * The ensuing load upper instructions are ommited. This implies some kind
6455 * of global optimization. We currently only optimize within a single macro.
6456 * For many of the load and store macros if the address is specified as a
6457 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6458 * first load register 'at' with zero and use it as the base register. The
6459 * mips assembler simply uses register $zero. Just one tiny optimization
6463 macro (struct mips_cl_insn
*ip
)
6465 unsigned int treg
, sreg
, dreg
, breg
;
6466 unsigned int tempreg
;
6469 expressionS label_expr
;
6487 bfd_reloc_code_real_type r
;
6488 int hold_mips_optimize
;
6490 gas_assert (! mips_opts
.mips16
);
6492 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6493 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6494 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6495 mask
= ip
->insn_mo
->mask
;
6497 label_expr
.X_op
= O_constant
;
6498 label_expr
.X_op_symbol
= NULL
;
6499 label_expr
.X_add_symbol
= NULL
;
6500 label_expr
.X_add_number
= 0;
6502 expr1
.X_op
= O_constant
;
6503 expr1
.X_op_symbol
= NULL
;
6504 expr1
.X_add_symbol
= NULL
;
6505 expr1
.X_add_number
= 1;
6520 if (mips_opts
.micromips
)
6521 micromips_label_expr (&label_expr
);
6523 label_expr
.X_add_number
= 8;
6524 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6526 macro_build (NULL
, "nop", "");
6528 move_register (dreg
, sreg
);
6529 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6530 if (mips_opts
.micromips
)
6531 micromips_add_label ();
6548 if (!mips_opts
.micromips
)
6550 if (imm_expr
.X_op
== O_constant
6551 && imm_expr
.X_add_number
>= -0x200
6552 && imm_expr
.X_add_number
< 0x200)
6554 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6563 if (imm_expr
.X_op
== O_constant
6564 && imm_expr
.X_add_number
>= -0x8000
6565 && imm_expr
.X_add_number
< 0x8000)
6567 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6572 load_register (AT
, &imm_expr
, dbl
);
6573 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6592 if (imm_expr
.X_op
== O_constant
6593 && imm_expr
.X_add_number
>= 0
6594 && imm_expr
.X_add_number
< 0x10000)
6596 if (mask
!= M_NOR_I
)
6597 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6600 macro_build (&imm_expr
, "ori", "t,r,i",
6601 treg
, sreg
, BFD_RELOC_LO16
);
6602 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6608 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6609 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6613 switch (imm_expr
.X_add_number
)
6616 macro_build (NULL
, "nop", "");
6619 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6623 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6624 (int) imm_expr
.X_add_number
);
6627 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6628 (unsigned long) imm_expr
.X_add_number
);
6637 gas_assert (mips_opts
.micromips
);
6638 macro_build_branch_ccl (mask
, &offset_expr
,
6639 EXTRACT_OPERAND (1, BCC
, *ip
));
6646 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6652 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6657 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6664 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6666 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6670 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6671 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6672 &offset_expr
, AT
, ZERO
);
6682 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6688 /* Check for > max integer. */
6689 maxnum
= 0x7fffffff;
6690 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6697 if (imm_expr
.X_op
== O_constant
6698 && imm_expr
.X_add_number
>= maxnum
6699 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6702 /* Result is always false. */
6704 macro_build (NULL
, "nop", "");
6706 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6709 if (imm_expr
.X_op
!= O_constant
)
6710 as_bad (_("Unsupported large constant"));
6711 ++imm_expr
.X_add_number
;
6715 if (mask
== M_BGEL_I
)
6717 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6719 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6720 &offset_expr
, sreg
);
6723 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6725 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6726 &offset_expr
, sreg
);
6729 maxnum
= 0x7fffffff;
6730 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6737 maxnum
= - maxnum
- 1;
6738 if (imm_expr
.X_op
== O_constant
6739 && imm_expr
.X_add_number
<= maxnum
6740 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6743 /* result is always true */
6744 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6745 macro_build (&offset_expr
, "b", "p");
6750 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6751 &offset_expr
, AT
, ZERO
);
6760 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6761 &offset_expr
, ZERO
, treg
);
6765 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6766 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6767 &offset_expr
, AT
, ZERO
);
6776 && imm_expr
.X_op
== O_constant
6777 && imm_expr
.X_add_number
== -1))
6779 if (imm_expr
.X_op
!= O_constant
)
6780 as_bad (_("Unsupported large constant"));
6781 ++imm_expr
.X_add_number
;
6785 if (mask
== M_BGEUL_I
)
6787 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6789 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6790 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6791 &offset_expr
, sreg
, ZERO
);
6796 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6797 &offset_expr
, AT
, ZERO
);
6805 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6807 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6811 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6812 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6813 &offset_expr
, AT
, ZERO
);
6821 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6822 &offset_expr
, sreg
, ZERO
);
6828 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6829 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6830 &offset_expr
, AT
, ZERO
);
6838 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6840 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6844 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6845 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6846 &offset_expr
, AT
, ZERO
);
6853 maxnum
= 0x7fffffff;
6854 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6861 if (imm_expr
.X_op
== O_constant
6862 && imm_expr
.X_add_number
>= maxnum
6863 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6865 if (imm_expr
.X_op
!= O_constant
)
6866 as_bad (_("Unsupported large constant"));
6867 ++imm_expr
.X_add_number
;
6871 if (mask
== M_BLTL_I
)
6873 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6874 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6875 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6876 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6881 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6882 &offset_expr
, AT
, ZERO
);
6890 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6891 &offset_expr
, sreg
, ZERO
);
6897 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6898 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6899 &offset_expr
, AT
, ZERO
);
6908 && imm_expr
.X_op
== O_constant
6909 && imm_expr
.X_add_number
== -1))
6911 if (imm_expr
.X_op
!= O_constant
)
6912 as_bad (_("Unsupported large constant"));
6913 ++imm_expr
.X_add_number
;
6917 if (mask
== M_BLTUL_I
)
6919 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6921 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6922 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6923 &offset_expr
, sreg
, ZERO
);
6928 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6929 &offset_expr
, AT
, ZERO
);
6937 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6939 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6943 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6944 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6945 &offset_expr
, AT
, ZERO
);
6955 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6956 &offset_expr
, ZERO
, treg
);
6960 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6961 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6962 &offset_expr
, AT
, ZERO
);
6968 /* Use unsigned arithmetic. */
6972 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6974 as_bad (_("Unsupported large constant"));
6979 pos
= imm_expr
.X_add_number
;
6980 size
= imm2_expr
.X_add_number
;
6985 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6988 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6990 as_bad (_("Improper extract size (%lu, position %lu)"),
6991 (unsigned long) size
, (unsigned long) pos
);
6995 if (size
<= 32 && pos
< 32)
7000 else if (size
<= 32)
7010 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7017 /* Use unsigned arithmetic. */
7021 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7023 as_bad (_("Unsupported large constant"));
7028 pos
= imm_expr
.X_add_number
;
7029 size
= imm2_expr
.X_add_number
;
7034 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7037 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7039 as_bad (_("Improper insert size (%lu, position %lu)"),
7040 (unsigned long) size
, (unsigned long) pos
);
7044 if (pos
< 32 && (pos
+ size
- 1) < 32)
7059 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7060 (int) (pos
+ size
- 1));
7076 as_warn (_("Divide by zero."));
7078 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7080 macro_build (NULL
, "break", BRK_FMT
, 7);
7087 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7088 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7092 if (mips_opts
.micromips
)
7093 micromips_label_expr (&label_expr
);
7095 label_expr
.X_add_number
= 8;
7096 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7097 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7098 macro_build (NULL
, "break", BRK_FMT
, 7);
7099 if (mips_opts
.micromips
)
7100 micromips_add_label ();
7102 expr1
.X_add_number
= -1;
7104 load_register (AT
, &expr1
, dbl
);
7105 if (mips_opts
.micromips
)
7106 micromips_label_expr (&label_expr
);
7108 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7109 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7112 expr1
.X_add_number
= 1;
7113 load_register (AT
, &expr1
, dbl
);
7114 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7118 expr1
.X_add_number
= 0x80000000;
7119 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7123 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7124 /* We want to close the noreorder block as soon as possible, so
7125 that later insns are available for delay slot filling. */
7130 if (mips_opts
.micromips
)
7131 micromips_label_expr (&label_expr
);
7133 label_expr
.X_add_number
= 8;
7134 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7135 macro_build (NULL
, "nop", "");
7137 /* We want to close the noreorder block as soon as possible, so
7138 that later insns are available for delay slot filling. */
7141 macro_build (NULL
, "break", BRK_FMT
, 6);
7143 if (mips_opts
.micromips
)
7144 micromips_add_label ();
7145 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7184 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7186 as_warn (_("Divide by zero."));
7188 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7190 macro_build (NULL
, "break", BRK_FMT
, 7);
7193 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7195 if (strcmp (s2
, "mflo") == 0)
7196 move_register (dreg
, sreg
);
7198 move_register (dreg
, ZERO
);
7201 if (imm_expr
.X_op
== O_constant
7202 && imm_expr
.X_add_number
== -1
7203 && s
[strlen (s
) - 1] != 'u')
7205 if (strcmp (s2
, "mflo") == 0)
7207 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7210 move_register (dreg
, ZERO
);
7215 load_register (AT
, &imm_expr
, dbl
);
7216 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7217 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7239 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7240 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7241 /* We want to close the noreorder block as soon as possible, so
7242 that later insns are available for delay slot filling. */
7247 if (mips_opts
.micromips
)
7248 micromips_label_expr (&label_expr
);
7250 label_expr
.X_add_number
= 8;
7251 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7252 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7254 /* We want to close the noreorder block as soon as possible, so
7255 that later insns are available for delay slot filling. */
7257 macro_build (NULL
, "break", BRK_FMT
, 7);
7258 if (mips_opts
.micromips
)
7259 micromips_add_label ();
7261 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7273 /* Load the address of a symbol into a register. If breg is not
7274 zero, we then add a base register to it. */
7276 if (dbl
&& HAVE_32BIT_GPRS
)
7277 as_warn (_("dla used to load 32-bit register"));
7279 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7280 as_warn (_("la used to load 64-bit address"));
7282 if (offset_expr
.X_op
== O_constant
7283 && offset_expr
.X_add_number
>= -0x8000
7284 && offset_expr
.X_add_number
< 0x8000)
7286 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7287 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7291 if (mips_opts
.at
&& (treg
== breg
))
7301 if (offset_expr
.X_op
!= O_symbol
7302 && offset_expr
.X_op
!= O_constant
)
7304 as_bad (_("Expression too complex"));
7305 offset_expr
.X_op
= O_constant
;
7308 if (offset_expr
.X_op
== O_constant
)
7309 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7310 else if (mips_pic
== NO_PIC
)
7312 /* If this is a reference to a GP relative symbol, we want
7313 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7315 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7316 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7317 If we have a constant, we need two instructions anyhow,
7318 so we may as well always use the latter form.
7320 With 64bit address space and a usable $at we want
7321 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7322 lui $at,<sym> (BFD_RELOC_HI16_S)
7323 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7324 daddiu $at,<sym> (BFD_RELOC_LO16)
7326 daddu $tempreg,$tempreg,$at
7328 If $at is already in use, we use a path which is suboptimal
7329 on superscalar processors.
7330 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7331 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7333 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7335 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7337 For GP relative symbols in 64bit address space we can use
7338 the same sequence as in 32bit address space. */
7339 if (HAVE_64BIT_SYMBOLS
)
7341 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7342 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7344 relax_start (offset_expr
.X_add_symbol
);
7345 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7346 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7350 if (used_at
== 0 && mips_opts
.at
)
7352 macro_build (&offset_expr
, "lui", LUI_FMT
,
7353 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7354 macro_build (&offset_expr
, "lui", LUI_FMT
,
7355 AT
, BFD_RELOC_HI16_S
);
7356 macro_build (&offset_expr
, "daddiu", "t,r,j",
7357 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7358 macro_build (&offset_expr
, "daddiu", "t,r,j",
7359 AT
, AT
, BFD_RELOC_LO16
);
7360 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7361 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7366 macro_build (&offset_expr
, "lui", LUI_FMT
,
7367 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7368 macro_build (&offset_expr
, "daddiu", "t,r,j",
7369 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7370 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7371 macro_build (&offset_expr
, "daddiu", "t,r,j",
7372 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7373 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7374 macro_build (&offset_expr
, "daddiu", "t,r,j",
7375 tempreg
, tempreg
, BFD_RELOC_LO16
);
7378 if (mips_relax
.sequence
)
7383 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7384 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7386 relax_start (offset_expr
.X_add_symbol
);
7387 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7388 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7391 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7392 as_bad (_("Offset too large"));
7393 macro_build_lui (&offset_expr
, tempreg
);
7394 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7395 tempreg
, tempreg
, BFD_RELOC_LO16
);
7396 if (mips_relax
.sequence
)
7400 else if (!mips_big_got
&& !HAVE_NEWABI
)
7402 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7404 /* If this is a reference to an external symbol, and there
7405 is no constant, we want
7406 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7407 or for lca or if tempreg is PIC_CALL_REG
7408 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7409 For a local symbol, we want
7410 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7412 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7414 If we have a small constant, and this is a reference to
7415 an external symbol, we want
7416 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7418 addiu $tempreg,$tempreg,<constant>
7419 For a local symbol, we want the same instruction
7420 sequence, but we output a BFD_RELOC_LO16 reloc on the
7423 If we have a large constant, and this is a reference to
7424 an external symbol, we want
7425 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7426 lui $at,<hiconstant>
7427 addiu $at,$at,<loconstant>
7428 addu $tempreg,$tempreg,$at
7429 For a local symbol, we want the same instruction
7430 sequence, but we output a BFD_RELOC_LO16 reloc on the
7434 if (offset_expr
.X_add_number
== 0)
7436 if (mips_pic
== SVR4_PIC
7438 && (call
|| tempreg
== PIC_CALL_REG
))
7439 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7441 relax_start (offset_expr
.X_add_symbol
);
7442 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7443 lw_reloc_type
, mips_gp_register
);
7446 /* We're going to put in an addu instruction using
7447 tempreg, so we may as well insert the nop right
7452 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7453 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7455 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7456 tempreg
, tempreg
, BFD_RELOC_LO16
);
7458 /* FIXME: If breg == 0, and the next instruction uses
7459 $tempreg, then if this variant case is used an extra
7460 nop will be generated. */
7462 else if (offset_expr
.X_add_number
>= -0x8000
7463 && offset_expr
.X_add_number
< 0x8000)
7465 load_got_offset (tempreg
, &offset_expr
);
7467 add_got_offset (tempreg
, &offset_expr
);
7471 expr1
.X_add_number
= offset_expr
.X_add_number
;
7472 offset_expr
.X_add_number
=
7473 SEXT_16BIT (offset_expr
.X_add_number
);
7474 load_got_offset (tempreg
, &offset_expr
);
7475 offset_expr
.X_add_number
= expr1
.X_add_number
;
7476 /* If we are going to add in a base register, and the
7477 target register and the base register are the same,
7478 then we are using AT as a temporary register. Since
7479 we want to load the constant into AT, we add our
7480 current AT (from the global offset table) and the
7481 register into the register now, and pretend we were
7482 not using a base register. */
7486 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7491 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7495 else if (!mips_big_got
&& HAVE_NEWABI
)
7497 int add_breg_early
= 0;
7499 /* If this is a reference to an external, and there is no
7500 constant, or local symbol (*), with or without a
7502 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7503 or for lca or if tempreg is PIC_CALL_REG
7504 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7506 If we have a small constant, and this is a reference to
7507 an external symbol, we want
7508 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7509 addiu $tempreg,$tempreg,<constant>
7511 If we have a large constant, and this is a reference to
7512 an external symbol, we want
7513 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7514 lui $at,<hiconstant>
7515 addiu $at,$at,<loconstant>
7516 addu $tempreg,$tempreg,$at
7518 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7519 local symbols, even though it introduces an additional
7522 if (offset_expr
.X_add_number
)
7524 expr1
.X_add_number
= offset_expr
.X_add_number
;
7525 offset_expr
.X_add_number
= 0;
7527 relax_start (offset_expr
.X_add_symbol
);
7528 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7529 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7531 if (expr1
.X_add_number
>= -0x8000
7532 && expr1
.X_add_number
< 0x8000)
7534 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7535 tempreg
, tempreg
, BFD_RELOC_LO16
);
7537 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7539 /* If we are going to add in a base register, and the
7540 target register and the base register are the same,
7541 then we are using AT as a temporary register. Since
7542 we want to load the constant into AT, we add our
7543 current AT (from the global offset table) and the
7544 register into the register now, and pretend we were
7545 not using a base register. */
7550 gas_assert (tempreg
== AT
);
7551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7557 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7558 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7564 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7567 offset_expr
.X_add_number
= expr1
.X_add_number
;
7569 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7570 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7573 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7574 treg
, tempreg
, breg
);
7580 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7582 relax_start (offset_expr
.X_add_symbol
);
7583 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7584 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7586 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7587 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7592 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7593 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7596 else if (mips_big_got
&& !HAVE_NEWABI
)
7599 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7600 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7601 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7603 /* This is the large GOT case. If this is a reference to an
7604 external symbol, and there is no constant, we want
7605 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7606 addu $tempreg,$tempreg,$gp
7607 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7608 or for lca or if tempreg is PIC_CALL_REG
7609 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7610 addu $tempreg,$tempreg,$gp
7611 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7612 For a local symbol, we want
7613 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7615 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7617 If we have a small constant, and this is a reference to
7618 an external symbol, we want
7619 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7620 addu $tempreg,$tempreg,$gp
7621 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7623 addiu $tempreg,$tempreg,<constant>
7624 For a local symbol, we want
7625 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7627 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7629 If we have a large constant, and this is a reference to
7630 an external symbol, we want
7631 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7632 addu $tempreg,$tempreg,$gp
7633 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7634 lui $at,<hiconstant>
7635 addiu $at,$at,<loconstant>
7636 addu $tempreg,$tempreg,$at
7637 For a local symbol, we want
7638 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7639 lui $at,<hiconstant>
7640 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7641 addu $tempreg,$tempreg,$at
7644 expr1
.X_add_number
= offset_expr
.X_add_number
;
7645 offset_expr
.X_add_number
= 0;
7646 relax_start (offset_expr
.X_add_symbol
);
7647 gpdelay
= reg_needs_delay (mips_gp_register
);
7648 if (expr1
.X_add_number
== 0 && breg
== 0
7649 && (call
|| tempreg
== PIC_CALL_REG
))
7651 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7652 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7654 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7655 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7656 tempreg
, tempreg
, mips_gp_register
);
7657 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7658 tempreg
, lw_reloc_type
, tempreg
);
7659 if (expr1
.X_add_number
== 0)
7663 /* We're going to put in an addu instruction using
7664 tempreg, so we may as well insert the nop right
7669 else if (expr1
.X_add_number
>= -0x8000
7670 && expr1
.X_add_number
< 0x8000)
7673 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7674 tempreg
, tempreg
, BFD_RELOC_LO16
);
7678 /* If we are going to add in a base register, and the
7679 target register and the base register are the same,
7680 then we are using AT as a temporary register. Since
7681 we want to load the constant into AT, we add our
7682 current AT (from the global offset table) and the
7683 register into the register now, and pretend we were
7684 not using a base register. */
7689 gas_assert (tempreg
== AT
);
7691 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7696 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7697 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7701 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7706 /* This is needed because this instruction uses $gp, but
7707 the first instruction on the main stream does not. */
7708 macro_build (NULL
, "nop", "");
7711 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7712 local_reloc_type
, mips_gp_register
);
7713 if (expr1
.X_add_number
>= -0x8000
7714 && expr1
.X_add_number
< 0x8000)
7717 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7718 tempreg
, tempreg
, BFD_RELOC_LO16
);
7719 /* FIXME: If add_number is 0, and there was no base
7720 register, the external symbol case ended with a load,
7721 so if the symbol turns out to not be external, and
7722 the next instruction uses tempreg, an unnecessary nop
7723 will be inserted. */
7729 /* We must add in the base register now, as in the
7730 external symbol case. */
7731 gas_assert (tempreg
== AT
);
7733 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7736 /* We set breg to 0 because we have arranged to add
7737 it in in both cases. */
7741 macro_build_lui (&expr1
, AT
);
7742 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7743 AT
, AT
, BFD_RELOC_LO16
);
7744 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7745 tempreg
, tempreg
, AT
);
7750 else if (mips_big_got
&& HAVE_NEWABI
)
7752 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7753 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7754 int add_breg_early
= 0;
7756 /* This is the large GOT case. If this is a reference to an
7757 external symbol, and there is no constant, we want
7758 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7759 add $tempreg,$tempreg,$gp
7760 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7761 or for lca or if tempreg is PIC_CALL_REG
7762 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7763 add $tempreg,$tempreg,$gp
7764 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7766 If we have a small constant, and this is a reference to
7767 an external symbol, we want
7768 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7769 add $tempreg,$tempreg,$gp
7770 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7771 addi $tempreg,$tempreg,<constant>
7773 If we have a large constant, and this is a reference to
7774 an external symbol, we want
7775 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7776 addu $tempreg,$tempreg,$gp
7777 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7778 lui $at,<hiconstant>
7779 addi $at,$at,<loconstant>
7780 add $tempreg,$tempreg,$at
7782 If we have NewABI, and we know it's a local symbol, we want
7783 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7784 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7785 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7787 relax_start (offset_expr
.X_add_symbol
);
7789 expr1
.X_add_number
= offset_expr
.X_add_number
;
7790 offset_expr
.X_add_number
= 0;
7792 if (expr1
.X_add_number
== 0 && breg
== 0
7793 && (call
|| tempreg
== PIC_CALL_REG
))
7795 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7796 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7798 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7799 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7800 tempreg
, tempreg
, mips_gp_register
);
7801 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7802 tempreg
, lw_reloc_type
, tempreg
);
7804 if (expr1
.X_add_number
== 0)
7806 else if (expr1
.X_add_number
>= -0x8000
7807 && expr1
.X_add_number
< 0x8000)
7809 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7810 tempreg
, tempreg
, BFD_RELOC_LO16
);
7812 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7814 /* If we are going to add in a base register, and the
7815 target register and the base register are the same,
7816 then we are using AT as a temporary register. Since
7817 we want to load the constant into AT, we add our
7818 current AT (from the global offset table) and the
7819 register into the register now, and pretend we were
7820 not using a base register. */
7825 gas_assert (tempreg
== AT
);
7826 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7832 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7833 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7838 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7841 offset_expr
.X_add_number
= expr1
.X_add_number
;
7842 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7843 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7844 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7845 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7848 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7849 treg
, tempreg
, breg
);
7859 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7863 gas_assert (!mips_opts
.micromips
);
7865 unsigned long temp
= (treg
<< 16) | (0x01);
7866 macro_build (NULL
, "c2", "C", temp
);
7871 gas_assert (!mips_opts
.micromips
);
7873 unsigned long temp
= (0x02);
7874 macro_build (NULL
, "c2", "C", temp
);
7879 gas_assert (!mips_opts
.micromips
);
7881 unsigned long temp
= (treg
<< 16) | (0x02);
7882 macro_build (NULL
, "c2", "C", temp
);
7887 gas_assert (!mips_opts
.micromips
);
7888 macro_build (NULL
, "c2", "C", 3);
7892 gas_assert (!mips_opts
.micromips
);
7894 unsigned long temp
= (treg
<< 16) | 0x03;
7895 macro_build (NULL
, "c2", "C", temp
);
7900 /* The j instruction may not be used in PIC code, since it
7901 requires an absolute address. We convert it to a b
7903 if (mips_pic
== NO_PIC
)
7904 macro_build (&offset_expr
, "j", "a");
7906 macro_build (&offset_expr
, "b", "p");
7909 /* The jal instructions must be handled as macros because when
7910 generating PIC code they expand to multi-instruction
7911 sequences. Normally they are simple instructions. */
7916 gas_assert (mips_opts
.micromips
);
7924 if (mips_pic
== NO_PIC
)
7926 s
= jals
? "jalrs" : "jalr";
7927 if (mips_opts
.micromips
7929 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7930 macro_build (NULL
, s
, "mj", sreg
);
7932 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7936 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7937 && mips_cprestore_offset
>= 0);
7939 if (sreg
!= PIC_CALL_REG
)
7940 as_warn (_("MIPS PIC call to register other than $25"));
7942 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7943 ? "jalrs" : "jalr");
7944 if (mips_opts
.micromips
7946 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7947 macro_build (NULL
, s
, "mj", sreg
);
7949 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7950 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7952 if (mips_cprestore_offset
< 0)
7953 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7956 if (!mips_frame_reg_valid
)
7958 as_warn (_("No .frame pseudo-op used in PIC code"));
7959 /* Quiet this warning. */
7960 mips_frame_reg_valid
= 1;
7962 if (!mips_cprestore_valid
)
7964 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7965 /* Quiet this warning. */
7966 mips_cprestore_valid
= 1;
7968 if (mips_opts
.noreorder
)
7969 macro_build (NULL
, "nop", "");
7970 expr1
.X_add_number
= mips_cprestore_offset
;
7971 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7974 HAVE_64BIT_ADDRESSES
);
7982 gas_assert (mips_opts
.micromips
);
7986 if (mips_pic
== NO_PIC
)
7987 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7988 else if (mips_pic
== SVR4_PIC
)
7990 /* If this is a reference to an external symbol, and we are
7991 using a small GOT, we want
7992 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7996 lw $gp,cprestore($sp)
7997 The cprestore value is set using the .cprestore
7998 pseudo-op. If we are using a big GOT, we want
7999 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8001 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8005 lw $gp,cprestore($sp)
8006 If the symbol is not external, we want
8007 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8009 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8012 lw $gp,cprestore($sp)
8014 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8015 sequences above, minus nops, unless the symbol is local,
8016 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8022 relax_start (offset_expr
.X_add_symbol
);
8023 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8024 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8027 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8028 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
8034 relax_start (offset_expr
.X_add_symbol
);
8035 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8036 BFD_RELOC_MIPS_CALL_HI16
);
8037 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8038 PIC_CALL_REG
, mips_gp_register
);
8039 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8040 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8043 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8044 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
8046 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8047 PIC_CALL_REG
, PIC_CALL_REG
,
8048 BFD_RELOC_MIPS_GOT_OFST
);
8052 macro_build_jalr (&offset_expr
, 0);
8056 relax_start (offset_expr
.X_add_symbol
);
8059 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8060 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8069 gpdelay
= reg_needs_delay (mips_gp_register
);
8070 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8071 BFD_RELOC_MIPS_CALL_HI16
);
8072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8073 PIC_CALL_REG
, mips_gp_register
);
8074 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8075 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8080 macro_build (NULL
, "nop", "");
8082 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8083 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8086 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8087 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8089 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8091 if (mips_cprestore_offset
< 0)
8092 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8095 if (!mips_frame_reg_valid
)
8097 as_warn (_("No .frame pseudo-op used in PIC code"));
8098 /* Quiet this warning. */
8099 mips_frame_reg_valid
= 1;
8101 if (!mips_cprestore_valid
)
8103 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8104 /* Quiet this warning. */
8105 mips_cprestore_valid
= 1;
8107 if (mips_opts
.noreorder
)
8108 macro_build (NULL
, "nop", "");
8109 expr1
.X_add_number
= mips_cprestore_offset
;
8110 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8113 HAVE_64BIT_ADDRESSES
);
8117 else if (mips_pic
== VXWORKS_PIC
)
8118 as_bad (_("Non-PIC jump used in PIC library"));
8226 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8234 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8265 gas_assert (!mips_opts
.micromips
);
8268 /* Itbl support may require additional care here. */
8275 /* Itbl support may require additional care here. */
8283 offbits
= (mips_opts
.micromips
? 12 : 16);
8284 /* Itbl support may require additional care here. */
8289 gas_assert (!mips_opts
.micromips
);
8292 /* Itbl support may require additional care here. */
8300 offbits
= (mips_opts
.micromips
? 12 : 16);
8307 offbits
= (mips_opts
.micromips
? 12 : 16);
8313 /* Itbl support may require additional care here. */
8321 offbits
= (mips_opts
.micromips
? 12 : 16);
8322 /* Itbl support may require additional care here. */
8329 /* Itbl support may require additional care here. */
8336 /* Itbl support may require additional care here. */
8344 offbits
= (mips_opts
.micromips
? 12 : 16);
8351 offbits
= (mips_opts
.micromips
? 12 : 16);
8358 offbits
= (mips_opts
.micromips
? 12 : 16);
8365 offbits
= (mips_opts
.micromips
? 12 : 16);
8372 offbits
= (mips_opts
.micromips
? 12 : 16);
8377 gas_assert (mips_opts
.micromips
);
8386 gas_assert (mips_opts
.micromips
);
8395 gas_assert (mips_opts
.micromips
);
8403 gas_assert (mips_opts
.micromips
);
8410 /* We don't want to use $0 as tempreg. */
8411 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
8414 tempreg
= treg
+ lp
;
8434 gas_assert (!mips_opts
.micromips
);
8437 /* Itbl support may require additional care here. */
8444 /* Itbl support may require additional care here. */
8452 offbits
= (mips_opts
.micromips
? 12 : 16);
8453 /* Itbl support may require additional care here. */
8458 gas_assert (!mips_opts
.micromips
);
8461 /* Itbl support may require additional care here. */
8469 offbits
= (mips_opts
.micromips
? 12 : 16);
8476 offbits
= (mips_opts
.micromips
? 12 : 16);
8483 offbits
= (mips_opts
.micromips
? 12 : 16);
8490 offbits
= (mips_opts
.micromips
? 12 : 16);
8496 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8497 offbits
= (mips_opts
.micromips
? 12 : 16);
8510 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8511 offbits
= (mips_opts
.micromips
? 12 : 16);
8525 /* Itbl support may require additional care here. */
8532 offbits
= (mips_opts
.micromips
? 12 : 16);
8533 /* Itbl support may require additional care here. */
8540 /* Itbl support may require additional care here. */
8545 gas_assert (!mips_opts
.micromips
);
8548 /* Itbl support may require additional care here. */
8556 offbits
= (mips_opts
.micromips
? 12 : 16);
8563 offbits
= (mips_opts
.micromips
? 12 : 16);
8568 gas_assert (mips_opts
.micromips
);
8576 gas_assert (mips_opts
.micromips
);
8584 gas_assert (mips_opts
.micromips
);
8592 gas_assert (mips_opts
.micromips
);
8601 if (offset_expr
.X_op
!= O_constant
8602 && offset_expr
.X_op
!= O_symbol
)
8604 as_bad (_("Expression too complex"));
8605 offset_expr
.X_op
= O_constant
;
8608 if (HAVE_32BIT_ADDRESSES
8609 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8613 sprintf_vma (value
, offset_expr
.X_add_number
);
8614 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8617 /* A constant expression in PIC code can be handled just as it
8618 is in non PIC code. */
8619 if (offset_expr
.X_op
== O_constant
)
8623 expr1
.X_add_number
= offset_expr
.X_add_number
;
8624 normalize_address_expr (&expr1
);
8625 if ((offbits
== 0 || offbits
== 16)
8626 && !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8628 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8629 & ~(bfd_vma
) 0xffff);
8632 else if (offbits
== 12 && !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8634 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8635 & ~(bfd_vma
) 0xfff);
8638 else if (offbits
== 9 && !IS_SEXT_9BIT_NUM (expr1
.X_add_number
))
8640 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x100)
8641 & ~(bfd_vma
) 0x1ff);
8646 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8648 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8649 tempreg
, tempreg
, breg
);
8654 if (offset_expr
.X_add_number
== 0)
8657 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8658 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8659 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8661 else if (offbits
== 16)
8662 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8664 macro_build (NULL
, s
, fmt
,
8665 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8667 else if (offbits
!= 16)
8669 /* The offset field is too narrow to be used for a low-part
8670 relocation, so load the whole address into the auxillary
8671 register. In the case of "A(b)" addresses, we first load
8672 absolute address "A" into the register and then add base
8673 register "b". In the case of "o(b)" addresses, we simply
8674 need to add 16-bit offset "o" to base register "b", and
8675 offset_reloc already contains the relocations associated
8679 load_address (tempreg
, &offset_expr
, &used_at
);
8681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8682 tempreg
, tempreg
, breg
);
8685 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8687 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8688 expr1
.X_add_number
= 0;
8690 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8692 macro_build (NULL
, s
, fmt
,
8693 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8695 else if (mips_pic
== NO_PIC
)
8697 /* If this is a reference to a GP relative symbol, and there
8698 is no base register, we want
8699 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8700 Otherwise, if there is no base register, we want
8701 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8702 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8703 If we have a constant, we need two instructions anyhow,
8704 so we always use the latter form.
8706 If we have a base register, and this is a reference to a
8707 GP relative symbol, we want
8708 addu $tempreg,$breg,$gp
8709 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8711 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8712 addu $tempreg,$tempreg,$breg
8713 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8714 With a constant we always use the latter case.
8716 With 64bit address space and no base register and $at usable,
8718 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8719 lui $at,<sym> (BFD_RELOC_HI16_S)
8720 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8723 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8724 If we have a base register, we want
8725 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8726 lui $at,<sym> (BFD_RELOC_HI16_S)
8727 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8731 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8733 Without $at we can't generate the optimal path for superscalar
8734 processors here since this would require two temporary registers.
8735 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8736 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8738 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8740 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8741 If we have a base register, we want
8742 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8743 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8745 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8747 daddu $tempreg,$tempreg,$breg
8748 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8750 For GP relative symbols in 64bit address space we can use
8751 the same sequence as in 32bit address space. */
8752 if (HAVE_64BIT_SYMBOLS
)
8754 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8755 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8757 relax_start (offset_expr
.X_add_symbol
);
8760 macro_build (&offset_expr
, s
, fmt
, treg
,
8761 BFD_RELOC_GPREL16
, mips_gp_register
);
8765 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8766 tempreg
, breg
, mips_gp_register
);
8767 macro_build (&offset_expr
, s
, fmt
, treg
,
8768 BFD_RELOC_GPREL16
, tempreg
);
8773 if (used_at
== 0 && mips_opts
.at
)
8775 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8776 BFD_RELOC_MIPS_HIGHEST
);
8777 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8779 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8780 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8782 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8783 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8784 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8785 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8791 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8792 BFD_RELOC_MIPS_HIGHEST
);
8793 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8794 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8795 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8796 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8797 tempreg
, BFD_RELOC_HI16_S
);
8798 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8800 macro_build (NULL
, "daddu", "d,v,t",
8801 tempreg
, tempreg
, breg
);
8802 macro_build (&offset_expr
, s
, fmt
, treg
,
8803 BFD_RELOC_LO16
, tempreg
);
8806 if (mips_relax
.sequence
)
8813 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8814 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8816 relax_start (offset_expr
.X_add_symbol
);
8817 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8821 macro_build_lui (&offset_expr
, tempreg
);
8822 macro_build (&offset_expr
, s
, fmt
, treg
,
8823 BFD_RELOC_LO16
, tempreg
);
8824 if (mips_relax
.sequence
)
8829 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8830 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8832 relax_start (offset_expr
.X_add_symbol
);
8833 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8834 tempreg
, breg
, mips_gp_register
);
8835 macro_build (&offset_expr
, s
, fmt
, treg
,
8836 BFD_RELOC_GPREL16
, tempreg
);
8839 macro_build_lui (&offset_expr
, tempreg
);
8840 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8841 tempreg
, tempreg
, breg
);
8842 macro_build (&offset_expr
, s
, fmt
, treg
,
8843 BFD_RELOC_LO16
, tempreg
);
8844 if (mips_relax
.sequence
)
8848 else if (!mips_big_got
)
8850 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8852 /* If this is a reference to an external symbol, we want
8853 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8855 <op> $treg,0($tempreg)
8857 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8859 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8860 <op> $treg,0($tempreg)
8863 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8864 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8866 If there is a base register, we add it to $tempreg before
8867 the <op>. If there is a constant, we stick it in the
8868 <op> instruction. We don't handle constants larger than
8869 16 bits, because we have no way to load the upper 16 bits
8870 (actually, we could handle them for the subset of cases
8871 in which we are not using $at). */
8872 gas_assert (offset_expr
.X_op
== O_symbol
);
8875 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8876 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8878 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8879 tempreg
, tempreg
, breg
);
8880 macro_build (&offset_expr
, s
, fmt
, treg
,
8881 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8884 expr1
.X_add_number
= offset_expr
.X_add_number
;
8885 offset_expr
.X_add_number
= 0;
8886 if (expr1
.X_add_number
< -0x8000
8887 || expr1
.X_add_number
>= 0x8000)
8888 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8889 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8890 lw_reloc_type
, mips_gp_register
);
8892 relax_start (offset_expr
.X_add_symbol
);
8894 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8895 tempreg
, BFD_RELOC_LO16
);
8898 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8899 tempreg
, tempreg
, breg
);
8900 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8902 else if (mips_big_got
&& !HAVE_NEWABI
)
8906 /* If this is a reference to an external symbol, we want
8907 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8908 addu $tempreg,$tempreg,$gp
8909 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8910 <op> $treg,0($tempreg)
8912 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8914 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8915 <op> $treg,0($tempreg)
8916 If there is a base register, we add it to $tempreg before
8917 the <op>. If there is a constant, we stick it in the
8918 <op> instruction. We don't handle constants larger than
8919 16 bits, because we have no way to load the upper 16 bits
8920 (actually, we could handle them for the subset of cases
8921 in which we are not using $at). */
8922 gas_assert (offset_expr
.X_op
== O_symbol
);
8923 expr1
.X_add_number
= offset_expr
.X_add_number
;
8924 offset_expr
.X_add_number
= 0;
8925 if (expr1
.X_add_number
< -0x8000
8926 || expr1
.X_add_number
>= 0x8000)
8927 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8928 gpdelay
= reg_needs_delay (mips_gp_register
);
8929 relax_start (offset_expr
.X_add_symbol
);
8930 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8931 BFD_RELOC_MIPS_GOT_HI16
);
8932 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8934 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8935 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8938 macro_build (NULL
, "nop", "");
8939 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8940 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8942 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8943 tempreg
, BFD_RELOC_LO16
);
8947 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8948 tempreg
, tempreg
, breg
);
8949 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8951 else if (mips_big_got
&& HAVE_NEWABI
)
8953 /* If this is a reference to an external symbol, we want
8954 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8955 add $tempreg,$tempreg,$gp
8956 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8957 <op> $treg,<ofst>($tempreg)
8958 Otherwise, for local symbols, we want:
8959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8960 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8961 gas_assert (offset_expr
.X_op
== O_symbol
);
8962 expr1
.X_add_number
= offset_expr
.X_add_number
;
8963 offset_expr
.X_add_number
= 0;
8964 if (expr1
.X_add_number
< -0x8000
8965 || expr1
.X_add_number
>= 0x8000)
8966 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8967 relax_start (offset_expr
.X_add_symbol
);
8968 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8969 BFD_RELOC_MIPS_GOT_HI16
);
8970 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8972 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8973 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8975 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8976 tempreg
, tempreg
, breg
);
8977 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8980 offset_expr
.X_add_number
= expr1
.X_add_number
;
8981 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8982 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8984 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8985 tempreg
, tempreg
, breg
);
8986 macro_build (&offset_expr
, s
, fmt
, treg
,
8987 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8997 load_register (treg
, &imm_expr
, 0);
9001 load_register (treg
, &imm_expr
, 1);
9005 if (imm_expr
.X_op
== O_constant
)
9008 load_register (AT
, &imm_expr
, 0);
9009 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9014 gas_assert (offset_expr
.X_op
== O_symbol
9015 && strcmp (segment_name (S_GET_SEGMENT
9016 (offset_expr
.X_add_symbol
)),
9018 && offset_expr
.X_add_number
== 0);
9019 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
9020 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9025 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9026 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9027 order 32 bits of the value and the low order 32 bits are either
9028 zero or in OFFSET_EXPR. */
9029 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9031 if (HAVE_64BIT_GPRS
)
9032 load_register (treg
, &imm_expr
, 1);
9037 if (target_big_endian
)
9049 load_register (hreg
, &imm_expr
, 0);
9052 if (offset_expr
.X_op
== O_absent
)
9053 move_register (lreg
, 0);
9056 gas_assert (offset_expr
.X_op
== O_constant
);
9057 load_register (lreg
, &offset_expr
, 0);
9064 /* We know that sym is in the .rdata section. First we get the
9065 upper 16 bits of the address. */
9066 if (mips_pic
== NO_PIC
)
9068 macro_build_lui (&offset_expr
, AT
);
9073 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9074 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9078 /* Now we load the register(s). */
9079 if (HAVE_64BIT_GPRS
)
9082 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9087 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9090 /* FIXME: How in the world do we deal with the possible
9092 offset_expr
.X_add_number
+= 4;
9093 macro_build (&offset_expr
, "lw", "t,o(b)",
9094 treg
+ 1, BFD_RELOC_LO16
, AT
);
9100 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9101 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9102 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9103 the value and the low order 32 bits are either zero or in
9105 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9108 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
9109 if (HAVE_64BIT_FPRS
)
9111 gas_assert (HAVE_64BIT_GPRS
);
9112 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
9116 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
9117 if (offset_expr
.X_op
== O_absent
)
9118 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
9121 gas_assert (offset_expr
.X_op
== O_constant
);
9122 load_register (AT
, &offset_expr
, 0);
9123 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9129 gas_assert (offset_expr
.X_op
== O_symbol
9130 && offset_expr
.X_add_number
== 0);
9131 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
9132 if (strcmp (s
, ".lit8") == 0)
9134 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9136 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
9137 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9140 breg
= mips_gp_register
;
9141 r
= BFD_RELOC_MIPS_LITERAL
;
9146 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
9148 if (mips_pic
!= NO_PIC
)
9149 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9150 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9153 /* FIXME: This won't work for a 64 bit address. */
9154 macro_build_lui (&offset_expr
, AT
);
9157 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9159 macro_build (&offset_expr
, "ldc1", "T,o(b)",
9160 treg
, BFD_RELOC_LO16
, AT
);
9169 /* Even on a big endian machine $fn comes before $fn+1. We have
9170 to adjust when loading from memory. */
9173 gas_assert (!mips_opts
.micromips
);
9174 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9175 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9176 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
9177 /* FIXME: A possible overflow which I don't know how to deal
9179 offset_expr
.X_add_number
+= 4;
9180 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9181 target_big_endian
? treg
: treg
+ 1, r
, breg
);
9185 gas_assert (!mips_opts
.micromips
);
9186 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9187 /* Even on a big endian machine $fn comes before $fn+1. We have
9188 to adjust when storing to memory. */
9189 macro_build (&offset_expr
, "swc1", "T,o(b)",
9190 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
9191 offset_expr
.X_add_number
+= 4;
9192 macro_build (&offset_expr
, "swc1", "T,o(b)",
9193 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
9197 gas_assert (!mips_opts
.micromips
);
9199 * The MIPS assembler seems to check for X_add_number not
9200 * being double aligned and generating:
9203 * addiu at,at,%lo(foo+1)
9206 * But, the resulting address is the same after relocation so why
9207 * generate the extra instruction?
9209 /* Itbl support may require additional care here. */
9212 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9221 gas_assert (!mips_opts
.micromips
);
9222 /* Itbl support may require additional care here. */
9225 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9245 if (HAVE_64BIT_GPRS
)
9255 if (HAVE_64BIT_GPRS
)
9263 if (offset_expr
.X_op
!= O_symbol
9264 && offset_expr
.X_op
!= O_constant
)
9266 as_bad (_("Expression too complex"));
9267 offset_expr
.X_op
= O_constant
;
9270 if (HAVE_32BIT_ADDRESSES
9271 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9275 sprintf_vma (value
, offset_expr
.X_add_number
);
9276 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9279 /* Even on a big endian machine $fn comes before $fn+1. We have
9280 to adjust when loading from memory. We set coproc if we must
9281 load $fn+1 first. */
9282 /* Itbl support may require additional care here. */
9283 if (!target_big_endian
)
9286 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9288 /* If this is a reference to a GP relative symbol, we want
9289 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9290 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9291 If we have a base register, we use this
9293 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9294 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9295 If this is not a GP relative symbol, we want
9296 lui $at,<sym> (BFD_RELOC_HI16_S)
9297 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9298 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9299 If there is a base register, we add it to $at after the
9300 lui instruction. If there is a constant, we always use
9302 if (offset_expr
.X_op
== O_symbol
9303 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9304 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9306 relax_start (offset_expr
.X_add_symbol
);
9309 tempreg
= mips_gp_register
;
9313 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9314 AT
, breg
, mips_gp_register
);
9319 /* Itbl support may require additional care here. */
9320 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9321 BFD_RELOC_GPREL16
, tempreg
);
9322 offset_expr
.X_add_number
+= 4;
9324 /* Set mips_optimize to 2 to avoid inserting an
9326 hold_mips_optimize
= mips_optimize
;
9328 /* Itbl support may require additional care here. */
9329 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9330 BFD_RELOC_GPREL16
, tempreg
);
9331 mips_optimize
= hold_mips_optimize
;
9335 offset_expr
.X_add_number
-= 4;
9338 macro_build_lui (&offset_expr
, AT
);
9340 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9341 /* Itbl support may require additional care here. */
9342 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9343 BFD_RELOC_LO16
, AT
);
9344 /* FIXME: How do we handle overflow here? */
9345 offset_expr
.X_add_number
+= 4;
9346 /* Itbl support may require additional care here. */
9347 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9348 BFD_RELOC_LO16
, AT
);
9349 if (mips_relax
.sequence
)
9352 else if (!mips_big_got
)
9354 /* If this is a reference to an external symbol, we want
9355 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9360 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9362 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9363 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9364 If there is a base register we add it to $at before the
9365 lwc1 instructions. If there is a constant we include it
9366 in the lwc1 instructions. */
9368 expr1
.X_add_number
= offset_expr
.X_add_number
;
9369 if (expr1
.X_add_number
< -0x8000
9370 || expr1
.X_add_number
>= 0x8000 - 4)
9371 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9372 load_got_offset (AT
, &offset_expr
);
9375 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9377 /* Set mips_optimize to 2 to avoid inserting an undesired
9379 hold_mips_optimize
= mips_optimize
;
9382 /* Itbl support may require additional care here. */
9383 relax_start (offset_expr
.X_add_symbol
);
9384 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9385 BFD_RELOC_LO16
, AT
);
9386 expr1
.X_add_number
+= 4;
9387 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9388 BFD_RELOC_LO16
, AT
);
9390 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9391 BFD_RELOC_LO16
, AT
);
9392 offset_expr
.X_add_number
+= 4;
9393 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9394 BFD_RELOC_LO16
, AT
);
9397 mips_optimize
= hold_mips_optimize
;
9399 else if (mips_big_got
)
9403 /* If this is a reference to an external symbol, we want
9404 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9406 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9411 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9413 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9414 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9415 If there is a base register we add it to $at before the
9416 lwc1 instructions. If there is a constant we include it
9417 in the lwc1 instructions. */
9419 expr1
.X_add_number
= offset_expr
.X_add_number
;
9420 offset_expr
.X_add_number
= 0;
9421 if (expr1
.X_add_number
< -0x8000
9422 || expr1
.X_add_number
>= 0x8000 - 4)
9423 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9424 gpdelay
= reg_needs_delay (mips_gp_register
);
9425 relax_start (offset_expr
.X_add_symbol
);
9426 macro_build (&offset_expr
, "lui", LUI_FMT
,
9427 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9428 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9429 AT
, AT
, mips_gp_register
);
9430 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9431 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9435 /* Itbl support may require additional care here. */
9436 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9437 BFD_RELOC_LO16
, AT
);
9438 expr1
.X_add_number
+= 4;
9440 /* Set mips_optimize to 2 to avoid inserting an undesired
9442 hold_mips_optimize
= mips_optimize
;
9444 /* Itbl support may require additional care here. */
9445 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9446 BFD_RELOC_LO16
, AT
);
9447 mips_optimize
= hold_mips_optimize
;
9448 expr1
.X_add_number
-= 4;
9451 offset_expr
.X_add_number
= expr1
.X_add_number
;
9453 macro_build (NULL
, "nop", "");
9454 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9455 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9458 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9459 /* Itbl support may require additional care here. */
9460 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9461 BFD_RELOC_LO16
, AT
);
9462 offset_expr
.X_add_number
+= 4;
9464 /* Set mips_optimize to 2 to avoid inserting an undesired
9466 hold_mips_optimize
= mips_optimize
;
9468 /* Itbl support may require additional care here. */
9469 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9470 BFD_RELOC_LO16
, AT
);
9471 mips_optimize
= hold_mips_optimize
;
9480 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9483 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9485 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9486 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9488 if (!HAVE_64BIT_GPRS
)
9490 offset_expr
.X_add_number
+= 4;
9491 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9492 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9513 /* New code added to support COPZ instructions.
9514 This code builds table entries out of the macros in mip_opcodes.
9515 R4000 uses interlocks to handle coproc delays.
9516 Other chips (like the R3000) require nops to be inserted for delays.
9518 FIXME: Currently, we require that the user handle delays.
9519 In order to fill delay slots for non-interlocked chips,
9520 we must have a way to specify delays based on the coprocessor.
9521 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9522 What are the side-effects of the cop instruction?
9523 What cache support might we have and what are its effects?
9524 Both coprocessor & memory require delays. how long???
9525 What registers are read/set/modified?
9527 If an itbl is provided to interpret cop instructions,
9528 this knowledge can be encoded in the itbl spec. */
9542 gas_assert (!mips_opts
.micromips
);
9543 /* For now we just do C (same as Cz). The parameter will be
9544 stored in insn_opcode by mips_ip. */
9545 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9549 move_register (dreg
, sreg
);
9555 if (mips_opts
.arch
== CPU_R5900
)
9557 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9561 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9562 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9569 /* The MIPS assembler some times generates shifts and adds. I'm
9570 not trying to be that fancy. GCC should do this for us
9573 load_register (AT
, &imm_expr
, dbl
);
9574 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9575 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9591 load_register (AT
, &imm_expr
, dbl
);
9592 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9593 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9594 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9595 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9597 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9600 if (mips_opts
.micromips
)
9601 micromips_label_expr (&label_expr
);
9603 label_expr
.X_add_number
= 8;
9604 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9605 macro_build (NULL
, "nop", "");
9606 macro_build (NULL
, "break", BRK_FMT
, 6);
9607 if (mips_opts
.micromips
)
9608 micromips_add_label ();
9611 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9627 load_register (AT
, &imm_expr
, dbl
);
9628 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9629 sreg
, imm
? AT
: treg
);
9630 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9631 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9633 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9636 if (mips_opts
.micromips
)
9637 micromips_label_expr (&label_expr
);
9639 label_expr
.X_add_number
= 8;
9640 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9641 macro_build (NULL
, "nop", "");
9642 macro_build (NULL
, "break", BRK_FMT
, 6);
9643 if (mips_opts
.micromips
)
9644 micromips_add_label ();
9650 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9661 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9662 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9666 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9667 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9668 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9669 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9673 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9684 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9685 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9689 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9690 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9691 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9692 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9701 if (imm_expr
.X_op
!= O_constant
)
9702 as_bad (_("Improper rotate count"));
9703 rot
= imm_expr
.X_add_number
& 0x3f;
9704 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9706 rot
= (64 - rot
) & 0x3f;
9708 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9710 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9715 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9718 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9719 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9722 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9723 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9724 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9732 if (imm_expr
.X_op
!= O_constant
)
9733 as_bad (_("Improper rotate count"));
9734 rot
= imm_expr
.X_add_number
& 0x1f;
9735 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9737 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9742 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9746 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9747 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9748 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9753 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9755 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9759 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9760 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9761 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9762 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9766 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9768 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9772 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9773 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9774 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9775 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9784 if (imm_expr
.X_op
!= O_constant
)
9785 as_bad (_("Improper rotate count"));
9786 rot
= imm_expr
.X_add_number
& 0x3f;
9787 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9790 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9792 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9797 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9800 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9801 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9804 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9805 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9806 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9814 if (imm_expr
.X_op
!= O_constant
)
9815 as_bad (_("Improper rotate count"));
9816 rot
= imm_expr
.X_add_number
& 0x1f;
9817 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9819 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9824 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9828 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9829 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9830 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9836 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9838 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9841 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9842 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9847 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9849 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9854 as_warn (_("Instruction %s: result is always false"),
9856 move_register (dreg
, 0);
9859 if (CPU_HAS_SEQ (mips_opts
.arch
)
9860 && -512 <= imm_expr
.X_add_number
9861 && imm_expr
.X_add_number
< 512)
9863 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9864 (int) imm_expr
.X_add_number
);
9867 if (imm_expr
.X_op
== O_constant
9868 && imm_expr
.X_add_number
>= 0
9869 && imm_expr
.X_add_number
< 0x10000)
9871 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9873 else if (imm_expr
.X_op
== O_constant
9874 && imm_expr
.X_add_number
> -0x8000
9875 && imm_expr
.X_add_number
< 0)
9877 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9878 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9879 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9881 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9884 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9885 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9890 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9891 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9894 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9897 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9903 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9904 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9907 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9909 if (imm_expr
.X_op
== O_constant
9910 && imm_expr
.X_add_number
>= -0x8000
9911 && imm_expr
.X_add_number
< 0x8000)
9913 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9914 dreg
, sreg
, BFD_RELOC_LO16
);
9918 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9919 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9923 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9926 case M_SGT
: /* sreg > treg <==> treg < sreg */
9932 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9935 case M_SGT_I
: /* sreg > I <==> I < sreg */
9942 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9943 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9946 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9952 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9953 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9956 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9963 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9964 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9965 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9969 if (imm_expr
.X_op
== O_constant
9970 && imm_expr
.X_add_number
>= -0x8000
9971 && imm_expr
.X_add_number
< 0x8000)
9973 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9977 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9978 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9982 if (imm_expr
.X_op
== O_constant
9983 && imm_expr
.X_add_number
>= -0x8000
9984 && imm_expr
.X_add_number
< 0x8000)
9986 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9991 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9992 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9997 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9999 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10002 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10003 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10008 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10010 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10015 as_warn (_("Instruction %s: result is always true"),
10016 ip
->insn_mo
->name
);
10017 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
10018 dreg
, 0, BFD_RELOC_LO16
);
10021 if (CPU_HAS_SEQ (mips_opts
.arch
)
10022 && -512 <= imm_expr
.X_add_number
10023 && imm_expr
.X_add_number
< 512)
10025 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
10026 (int) imm_expr
.X_add_number
);
10029 if (imm_expr
.X_op
== O_constant
10030 && imm_expr
.X_add_number
>= 0
10031 && imm_expr
.X_add_number
< 0x10000)
10033 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10035 else if (imm_expr
.X_op
== O_constant
10036 && imm_expr
.X_add_number
> -0x8000
10037 && imm_expr
.X_add_number
< 0)
10039 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10040 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10041 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10043 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10046 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10047 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
10052 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10053 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10056 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10071 if (!mips_opts
.micromips
)
10073 if (imm_expr
.X_op
== O_constant
10074 && imm_expr
.X_add_number
> -0x200
10075 && imm_expr
.X_add_number
<= 0x200)
10077 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
10086 if (imm_expr
.X_op
== O_constant
10087 && imm_expr
.X_add_number
> -0x8000
10088 && imm_expr
.X_add_number
<= 0x8000)
10090 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10091 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10096 load_register (AT
, &imm_expr
, dbl
);
10097 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
10119 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10120 macro_build (NULL
, s
, "s,t", sreg
, AT
);
10125 gas_assert (!mips_opts
.micromips
);
10126 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
10128 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
10129 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
10132 * Is the double cfc1 instruction a bug in the mips assembler;
10133 * or is there a reason for it?
10135 start_noreorder ();
10136 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10137 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10138 macro_build (NULL
, "nop", "");
10139 expr1
.X_add_number
= 3;
10140 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
10141 expr1
.X_add_number
= 2;
10142 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
10143 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
10144 macro_build (NULL
, "nop", "");
10145 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
10147 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
10148 macro_build (NULL
, "nop", "");
10171 offbits
= (mips_opts
.micromips
? 12 : 16);
10179 offbits
= (mips_opts
.micromips
? 12 : 16);
10195 offbits
= (mips_opts
.micromips
? 12 : 16);
10204 offbits
= (mips_opts
.micromips
? 12 : 16);
10209 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
10210 as_bad (_("Operand overflow"));
10213 expr1
.X_add_number
= 0;
10218 load_address (tempreg
, ep
, &used_at
);
10220 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10221 tempreg
, tempreg
, breg
);
10226 else if (offbits
== 12
10227 && (offset_expr
.X_op
!= O_constant
10228 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
10229 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
10233 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
10234 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10239 else if (!ust
&& treg
== breg
)
10250 if (!target_big_endian
)
10251 ep
->X_add_number
+= off
;
10253 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10255 macro_build (NULL
, s
, "t,~(b)",
10256 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10258 if (!target_big_endian
)
10259 ep
->X_add_number
-= off
;
10261 ep
->X_add_number
+= off
;
10263 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10265 macro_build (NULL
, s2
, "t,~(b)",
10266 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10268 /* If necessary, move the result in tempreg to the final destination. */
10269 if (!ust
&& treg
!= tempreg
)
10271 /* Protect second load's delay slot. */
10273 move_register (treg
, tempreg
);
10279 if (target_big_endian
== ust
)
10280 ep
->X_add_number
+= off
;
10281 tempreg
= ust
|| ab
? treg
: AT
;
10282 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10284 /* For halfword transfers we need a temporary register to shuffle
10285 bytes. Unfortunately for M_USH_A we have none available before
10286 the next store as AT holds the base address. We deal with this
10287 case by clobbering TREG and then restoring it as with ULH. */
10288 tempreg
= ust
== ab
? treg
: AT
;
10290 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10292 if (target_big_endian
== ust
)
10293 ep
->X_add_number
-= off
;
10295 ep
->X_add_number
+= off
;
10296 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10298 /* For M_USH_A re-retrieve the LSB. */
10301 if (target_big_endian
)
10302 ep
->X_add_number
+= off
;
10304 ep
->X_add_number
-= off
;
10305 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
10307 /* For ULH and M_USH_A OR the LSB in. */
10310 tempreg
= !ab
? AT
: treg
;
10311 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10312 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10317 /* FIXME: Check if this is one of the itbl macros, since they
10318 are added dynamically. */
10319 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10322 if (!mips_opts
.at
&& used_at
)
10323 as_bad (_("Macro used $at after \".set noat\""));
10326 /* Implement macros in mips16 mode. */
10329 mips16_macro (struct mips_cl_insn
*ip
)
10332 int xreg
, yreg
, zreg
, tmp
;
10335 const char *s
, *s2
, *s3
;
10337 mask
= ip
->insn_mo
->mask
;
10339 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10340 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10341 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10343 expr1
.X_op
= O_constant
;
10344 expr1
.X_op_symbol
= NULL
;
10345 expr1
.X_add_symbol
= NULL
;
10346 expr1
.X_add_number
= 1;
10365 start_noreorder ();
10366 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10367 expr1
.X_add_number
= 2;
10368 macro_build (&expr1
, "bnez", "x,p", yreg
);
10369 macro_build (NULL
, "break", "6", 7);
10371 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10372 since that causes an overflow. We should do that as well,
10373 but I don't see how to do the comparisons without a temporary
10376 macro_build (NULL
, s
, "x", zreg
);
10395 start_noreorder ();
10396 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10397 expr1
.X_add_number
= 2;
10398 macro_build (&expr1
, "bnez", "x,p", yreg
);
10399 macro_build (NULL
, "break", "6", 7);
10401 macro_build (NULL
, s2
, "x", zreg
);
10407 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10408 macro_build (NULL
, "mflo", "x", zreg
);
10416 if (imm_expr
.X_op
!= O_constant
)
10417 as_bad (_("Unsupported large constant"));
10418 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10419 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10423 if (imm_expr
.X_op
!= O_constant
)
10424 as_bad (_("Unsupported large constant"));
10425 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10426 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10430 if (imm_expr
.X_op
!= O_constant
)
10431 as_bad (_("Unsupported large constant"));
10432 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10433 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10455 goto do_reverse_branch
;
10459 goto do_reverse_branch
;
10471 goto do_reverse_branch
;
10482 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10483 macro_build (&offset_expr
, s2
, "p");
10510 goto do_addone_branch_i
;
10515 goto do_addone_branch_i
;
10530 goto do_addone_branch_i
;
10536 do_addone_branch_i
:
10537 if (imm_expr
.X_op
!= O_constant
)
10538 as_bad (_("Unsupported large constant"));
10539 ++imm_expr
.X_add_number
;
10542 macro_build (&imm_expr
, s
, s3
, xreg
);
10543 macro_build (&offset_expr
, s2
, "p");
10547 expr1
.X_add_number
= 0;
10548 macro_build (&expr1
, "slti", "x,8", yreg
);
10550 move_register (xreg
, yreg
);
10551 expr1
.X_add_number
= 2;
10552 macro_build (&expr1
, "bteqz", "p");
10553 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10557 /* For consistency checking, verify that all bits are specified either
10558 by the match/mask part of the instruction definition, or by the
10561 validate_mips_insn (const struct mips_opcode
*opc
)
10563 const char *p
= opc
->args
;
10565 unsigned long used_bits
= opc
->mask
;
10567 if ((used_bits
& opc
->match
) != opc
->match
)
10569 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10570 opc
->name
, opc
->args
);
10573 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10583 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10584 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10585 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10586 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10587 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10588 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10589 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10590 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10591 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10592 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10593 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10594 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10595 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10597 case 'J': USE_BITS (OP_MASK_CODE10
, OP_SH_CODE10
); break;
10598 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10599 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10600 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10601 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10602 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10603 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10604 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10605 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10606 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10607 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10608 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10609 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10610 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10611 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10612 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10613 case 'j': USE_BITS (OP_MASK_EVAOFFSET
, OP_SH_EVAOFFSET
); break;
10616 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10617 c
, opc
->name
, opc
->args
);
10621 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10622 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10624 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10625 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10626 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10627 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10629 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10630 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10632 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10633 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10635 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10636 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10637 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10638 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10639 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10640 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10641 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10642 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10643 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10644 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10645 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10646 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10647 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10648 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10649 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10650 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10651 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10653 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10654 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10655 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10656 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10658 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10659 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10660 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10661 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10662 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10663 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10664 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10665 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10666 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10669 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10670 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10671 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10672 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10673 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10676 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10677 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10678 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10679 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10680 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10681 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10682 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10683 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10684 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10685 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10686 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10687 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10688 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10689 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10690 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10691 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10692 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10693 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10694 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10695 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10697 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10698 c
, opc
->name
, opc
->args
);
10702 if (used_bits
!= 0xffffffff)
10704 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10705 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10711 /* For consistency checking, verify that the length implied matches the
10712 major opcode and that all bits are specified either by the match/mask
10713 part of the instruction definition, or by the operand list. */
10716 validate_micromips_insn (const struct mips_opcode
*opc
)
10718 unsigned long match
= opc
->match
;
10719 unsigned long mask
= opc
->mask
;
10720 const char *p
= opc
->args
;
10721 unsigned long insn_bits
;
10722 unsigned long used_bits
;
10723 unsigned long major
;
10724 unsigned int length
;
10728 if ((mask
& match
) != match
)
10730 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10731 opc
->name
, opc
->args
);
10734 length
= micromips_insn_length (opc
);
10735 if (length
!= 2 && length
!= 4)
10737 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10738 "%s %s"), length
, opc
->name
, opc
->args
);
10741 major
= match
>> (10 + 8 * (length
- 2));
10742 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10743 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10745 as_bad (_("Internal error: bad microMIPS opcode "
10746 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10750 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10751 insn_bits
= 1 << 4 * length
;
10752 insn_bits
<<= 4 * length
;
10755 #define USE_BITS(field) \
10756 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10767 case 'A': USE_BITS (EXTLSB
); break;
10768 case 'B': USE_BITS (INSMSB
); break;
10769 case 'C': USE_BITS (EXTMSBD
); break;
10770 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10771 case 'E': USE_BITS (EXTLSB
); break;
10772 case 'F': USE_BITS (INSMSB
); break;
10773 case 'G': USE_BITS (EXTMSBD
); break;
10774 case 'H': USE_BITS (EXTMSBD
); break;
10775 case 'j': USE_BITS (EVAOFFSET
); break;
10777 as_bad (_("Internal error: bad mips opcode "
10778 "(unknown extension operand type `%c%c'): %s %s"),
10779 e
, c
, opc
->name
, opc
->args
);
10787 case 'A': USE_BITS (IMMA
); break;
10788 case 'B': USE_BITS (IMMB
); break;
10789 case 'C': USE_BITS (IMMC
); break;
10790 case 'D': USE_BITS (IMMD
); break;
10791 case 'E': USE_BITS (IMME
); break;
10792 case 'F': USE_BITS (IMMF
); break;
10793 case 'G': USE_BITS (IMMG
); break;
10794 case 'H': USE_BITS (IMMH
); break;
10795 case 'I': USE_BITS (IMMI
); break;
10796 case 'J': USE_BITS (IMMJ
); break;
10797 case 'L': USE_BITS (IMML
); break;
10798 case 'M': USE_BITS (IMMM
); break;
10799 case 'N': USE_BITS (IMMN
); break;
10800 case 'O': USE_BITS (IMMO
); break;
10801 case 'P': USE_BITS (IMMP
); break;
10802 case 'Q': USE_BITS (IMMQ
); break;
10803 case 'U': USE_BITS (IMMU
); break;
10804 case 'W': USE_BITS (IMMW
); break;
10805 case 'X': USE_BITS (IMMX
); break;
10806 case 'Y': USE_BITS (IMMY
); break;
10809 case 'b': USE_BITS (MB
); break;
10810 case 'c': USE_BITS (MC
); break;
10811 case 'd': USE_BITS (MD
); break;
10812 case 'e': USE_BITS (ME
); break;
10813 case 'f': USE_BITS (MF
); break;
10814 case 'g': USE_BITS (MG
); break;
10815 case 'h': USE_BITS (MH
); break;
10816 case 'i': USE_BITS (MI
); break;
10817 case 'j': USE_BITS (MJ
); break;
10818 case 'l': USE_BITS (ML
); break;
10819 case 'm': USE_BITS (MM
); break;
10820 case 'n': USE_BITS (MN
); break;
10821 case 'p': USE_BITS (MP
); break;
10822 case 'q': USE_BITS (MQ
); break;
10830 as_bad (_("Internal error: bad mips opcode "
10831 "(unknown extension operand type `%c%c'): %s %s"),
10832 e
, c
, opc
->name
, opc
->args
);
10836 case '.': USE_BITS (OFFSET10
); break;
10837 case '1': USE_BITS (STYPE
); break;
10838 case '2': USE_BITS (BP
); break;
10839 case '3': USE_BITS (SA3
); break;
10840 case '4': USE_BITS (SA4
); break;
10841 case '5': USE_BITS (IMM8
); break;
10842 case '6': USE_BITS (RS
); break;
10843 case '7': USE_BITS (DSPACC
); break;
10844 case '8': USE_BITS (WRDSP
); break;
10845 case '0': USE_BITS (DSPSFT
); break;
10846 case '<': USE_BITS (SHAMT
); break;
10847 case '>': USE_BITS (SHAMT
); break;
10848 case '@': USE_BITS (IMM10
); break;
10849 case 'B': USE_BITS (CODE10
); break;
10850 case 'C': USE_BITS (COPZ
); break;
10851 case 'D': USE_BITS (FD
); break;
10852 case 'E': USE_BITS (RT
); break;
10853 case 'G': USE_BITS (RS
); break;
10854 case 'H': USE_BITS (SEL
); break;
10855 case 'K': USE_BITS (RS
); break;
10856 case 'M': USE_BITS (CCC
); break;
10857 case 'N': USE_BITS (BCC
); break;
10858 case 'R': USE_BITS (FR
); break;
10859 case 'S': USE_BITS (FS
); break;
10860 case 'T': USE_BITS (FT
); break;
10861 case 'V': USE_BITS (FS
); break;
10862 case '\\': USE_BITS (3BITPOS
); break;
10863 case '^': USE_BITS (RD
); break;
10864 case 'a': USE_BITS (TARGET
); break;
10865 case 'b': USE_BITS (RS
); break;
10866 case 'c': USE_BITS (CODE
); break;
10867 case 'd': USE_BITS (RD
); break;
10868 case 'h': USE_BITS (PREFX
); break;
10869 case 'i': USE_BITS (IMMEDIATE
); break;
10870 case 'j': USE_BITS (DELTA
); break;
10871 case 'k': USE_BITS (CACHE
); break;
10872 case 'n': USE_BITS (RT
); break;
10873 case 'o': USE_BITS (DELTA
); break;
10874 case 'p': USE_BITS (DELTA
); break;
10875 case 'q': USE_BITS (CODE2
); break;
10876 case 'r': USE_BITS (RS
); break;
10877 case 's': USE_BITS (RS
); break;
10878 case 't': USE_BITS (RT
); break;
10879 case 'u': USE_BITS (IMMEDIATE
); break;
10880 case 'v': USE_BITS (RS
); break;
10881 case 'w': USE_BITS (RT
); break;
10882 case 'y': USE_BITS (RS3
); break;
10884 case '|': USE_BITS (TRAP
); break;
10885 case '~': USE_BITS (OFFSET12
); break;
10887 as_bad (_("Internal error: bad microMIPS opcode "
10888 "(unknown operand type `%c'): %s %s"),
10889 c
, opc
->name
, opc
->args
);
10893 if (used_bits
!= insn_bits
)
10895 if (~used_bits
& insn_bits
)
10896 as_bad (_("Internal error: bad microMIPS opcode "
10897 "(bits 0x%lx undefined): %s %s"),
10898 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10899 if (used_bits
& ~insn_bits
)
10900 as_bad (_("Internal error: bad microMIPS opcode "
10901 "(bits 0x%lx defined): %s %s"),
10902 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10908 /* UDI immediates. */
10909 struct mips_immed
{
10911 unsigned int shift
;
10912 unsigned long mask
;
10916 static const struct mips_immed mips_immed
[] = {
10917 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10918 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10919 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10920 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10924 /* Check whether an odd floating-point register is allowed. */
10926 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10928 const char *s
= insn
->name
;
10930 if (insn
->pinfo
== INSN_MACRO
)
10931 /* Let a macro pass, we'll catch it later when it is expanded. */
10934 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
10936 /* Allow odd registers for single-precision ops. */
10937 switch (insn
->pinfo
& (FP_S
| FP_D
))
10941 return 1; /* both single precision - ok */
10943 return 0; /* both double precision - fail */
10948 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10949 s
= strchr (insn
->name
, '.');
10951 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10952 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10955 /* Single-precision coprocessor loads and moves are OK too. */
10956 if ((insn
->pinfo
& FP_S
)
10957 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10958 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10964 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10965 taking bits from BIT up. */
10967 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10969 return (ep
->X_op
== O_constant
10970 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10971 && ep
->X_add_number
>= min
<< bit
10972 && ep
->X_add_number
< max
<< bit
);
10975 /* This routine assembles an instruction into its binary format. As a
10976 side effect, it sets one of the global variables imm_reloc or
10977 offset_reloc to the type of relocation to do if one of the operands
10978 is an address expression. */
10981 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10983 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10984 bfd_boolean need_delay_slot_ok
= TRUE
;
10985 struct mips_opcode
*firstinsn
= NULL
;
10986 const struct mips_opcode
*past
;
10987 struct hash_control
*hash
;
10991 struct mips_opcode
*insn
;
10993 unsigned int regno
;
10994 unsigned int lastregno
;
10995 unsigned int destregno
= 0;
10996 unsigned int lastpos
= 0;
10997 unsigned int limlo
, limhi
;
11000 offsetT min_range
, max_range
;
11004 unsigned int rtype
;
11010 if (mips_opts
.micromips
)
11012 hash
= micromips_op_hash
;
11013 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
11018 past
= &mips_opcodes
[NUMOPCODES
];
11020 forced_insn_length
= 0;
11023 /* We first try to match an instruction up to a space or to the end. */
11024 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
11027 /* Make a copy of the instruction so that we can fiddle with it. */
11028 name
= alloca (end
+ 1);
11029 memcpy (name
, str
, end
);
11034 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
11036 if (insn
!= NULL
|| !mips_opts
.micromips
)
11038 if (forced_insn_length
)
11041 /* See if there's an instruction size override suffix,
11042 either `16' or `32', at the end of the mnemonic proper,
11043 that defines the operation, i.e. before the first `.'
11044 character if any. Strip it and retry. */
11045 dot
= strchr (name
, '.');
11046 opend
= dot
!= NULL
? dot
- name
: end
;
11049 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
11050 forced_insn_length
= 2;
11051 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
11052 forced_insn_length
= 4;
11055 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
11059 insn_error
= _("Unrecognized opcode");
11063 /* For microMIPS instructions placed in a fixed-length branch delay slot
11064 we make up to two passes over the relevant fragment of the opcode
11065 table. First we try instructions that meet the delay slot's length
11066 requirement. If none matched, then we retry with the remaining ones
11067 and if one matches, then we use it and then issue an appropriate
11068 warning later on. */
11069 argsStart
= s
= str
+ end
;
11072 bfd_boolean delay_slot_ok
;
11073 bfd_boolean size_ok
;
11076 gas_assert (strcmp (insn
->name
, name
) == 0);
11078 ok
= is_opcode_valid (insn
);
11079 size_ok
= is_size_valid (insn
);
11080 delay_slot_ok
= is_delay_slot_valid (insn
);
11081 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
11084 wrong_delay_slot_insns
= TRUE
;
11086 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
11088 static char buf
[256];
11090 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
11095 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
11097 gas_assert (firstinsn
);
11098 need_delay_slot_ok
= FALSE
;
11108 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
11109 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
11110 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11112 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
11113 8 * forced_insn_length
);
11119 create_insn (ip
, insn
);
11122 lastregno
= 0xffffffff;
11123 for (args
= insn
->args
;; ++args
)
11127 s
+= strspn (s
, " \t");
11131 case '\0': /* end of args */
11137 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11138 code) or 14 (for microMIPS code). */
11139 my_getExpression (&imm_expr
, s
);
11140 check_absolute_expr (ip
, &imm_expr
);
11141 if ((unsigned long) imm_expr
.X_add_number
!= 1
11142 && (unsigned long) imm_expr
.X_add_number
!= 3)
11144 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11145 (unsigned long) imm_expr
.X_add_number
);
11147 INSERT_OPERAND (mips_opts
.micromips
,
11148 BP
, *ip
, imm_expr
.X_add_number
);
11149 imm_expr
.X_op
= O_absent
;
11154 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
11155 code) or 21 (for microMIPS code). */
11157 unsigned long mask
= (mips_opts
.micromips
11158 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
11160 my_getExpression (&imm_expr
, s
);
11161 check_absolute_expr (ip
, &imm_expr
);
11162 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11163 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11164 mask
, (unsigned long) imm_expr
.X_add_number
);
11165 INSERT_OPERAND (mips_opts
.micromips
,
11166 SA3
, *ip
, imm_expr
.X_add_number
);
11167 imm_expr
.X_op
= O_absent
;
11173 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
11174 code) or 21 (for microMIPS code). */
11176 unsigned long mask
= (mips_opts
.micromips
11177 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
11179 my_getExpression (&imm_expr
, s
);
11180 check_absolute_expr (ip
, &imm_expr
);
11181 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11182 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11183 mask
, (unsigned long) imm_expr
.X_add_number
);
11184 INSERT_OPERAND (mips_opts
.micromips
,
11185 SA4
, *ip
, imm_expr
.X_add_number
);
11186 imm_expr
.X_op
= O_absent
;
11192 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11193 code) or 16 (for microMIPS code). */
11195 unsigned long mask
= (mips_opts
.micromips
11196 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11198 my_getExpression (&imm_expr
, s
);
11199 check_absolute_expr (ip
, &imm_expr
);
11200 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11201 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11202 mask
, (unsigned long) imm_expr
.X_add_number
);
11203 INSERT_OPERAND (mips_opts
.micromips
,
11204 IMM8
, *ip
, imm_expr
.X_add_number
);
11205 imm_expr
.X_op
= O_absent
;
11211 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11212 code) or 21 (for microMIPS code). */
11214 unsigned long mask
= (mips_opts
.micromips
11215 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11217 my_getExpression (&imm_expr
, s
);
11218 check_absolute_expr (ip
, &imm_expr
);
11219 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11220 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11221 mask
, (unsigned long) imm_expr
.X_add_number
);
11222 INSERT_OPERAND (mips_opts
.micromips
,
11223 RS
, *ip
, imm_expr
.X_add_number
);
11224 imm_expr
.X_op
= O_absent
;
11229 case '7': /* Four DSP accumulators in bits 11,12. */
11230 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11231 && s
[3] >= '0' && s
[3] <= '3')
11233 regno
= s
[3] - '0';
11235 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11239 as_bad (_("Invalid dsp acc register"));
11243 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11244 code) or 14 (for microMIPS code). */
11246 unsigned long mask
= (mips_opts
.micromips
11247 ? MICROMIPSOP_MASK_WRDSP
11250 my_getExpression (&imm_expr
, s
);
11251 check_absolute_expr (ip
, &imm_expr
);
11252 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11253 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11254 mask
, (unsigned long) imm_expr
.X_add_number
);
11255 INSERT_OPERAND (mips_opts
.micromips
,
11256 WRDSP
, *ip
, imm_expr
.X_add_number
);
11257 imm_expr
.X_op
= O_absent
;
11262 case '9': /* Four DSP accumulators in bits 21,22. */
11263 gas_assert (!mips_opts
.micromips
);
11264 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11265 && s
[3] >= '0' && s
[3] <= '3')
11267 regno
= s
[3] - '0';
11269 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11273 as_bad (_("Invalid dsp acc register"));
11277 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11278 code) or 20 (for microMIPS code). */
11280 long mask
= (mips_opts
.micromips
11281 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11283 my_getExpression (&imm_expr
, s
);
11284 check_absolute_expr (ip
, &imm_expr
);
11285 min_range
= -((mask
+ 1) >> 1);
11286 max_range
= ((mask
+ 1) >> 1) - 1;
11287 if (imm_expr
.X_add_number
< min_range
11288 || imm_expr
.X_add_number
> max_range
)
11289 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11290 (long) min_range
, (long) max_range
,
11291 (long) imm_expr
.X_add_number
);
11292 INSERT_OPERAND (mips_opts
.micromips
,
11293 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11294 imm_expr
.X_op
= O_absent
;
11299 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11300 gas_assert (!mips_opts
.micromips
);
11301 my_getExpression (&imm_expr
, s
);
11302 check_absolute_expr (ip
, &imm_expr
);
11303 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11305 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11307 (unsigned long) imm_expr
.X_add_number
);
11309 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11310 imm_expr
.X_op
= O_absent
;
11314 case ':': /* DSP 7-bit signed immediate in bit 19. */
11315 gas_assert (!mips_opts
.micromips
);
11316 my_getExpression (&imm_expr
, s
);
11317 check_absolute_expr (ip
, &imm_expr
);
11318 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11319 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11320 if (imm_expr
.X_add_number
< min_range
||
11321 imm_expr
.X_add_number
> max_range
)
11323 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11324 (long) min_range
, (long) max_range
,
11325 (long) imm_expr
.X_add_number
);
11327 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11328 imm_expr
.X_op
= O_absent
;
11332 case '@': /* DSP 10-bit signed immediate in bit 16. */
11334 long mask
= (mips_opts
.micromips
11335 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11337 my_getExpression (&imm_expr
, s
);
11338 check_absolute_expr (ip
, &imm_expr
);
11339 min_range
= -((mask
+ 1) >> 1);
11340 max_range
= ((mask
+ 1) >> 1) - 1;
11341 if (imm_expr
.X_add_number
< min_range
11342 || imm_expr
.X_add_number
> max_range
)
11343 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11344 (long) min_range
, (long) max_range
,
11345 (long) imm_expr
.X_add_number
);
11346 INSERT_OPERAND (mips_opts
.micromips
,
11347 IMM10
, *ip
, imm_expr
.X_add_number
);
11348 imm_expr
.X_op
= O_absent
;
11353 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11354 gas_assert (mips_opts
.micromips
);
11355 my_getExpression (&imm_expr
, s
);
11356 check_absolute_expr (ip
, &imm_expr
);
11357 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11358 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11359 MICROMIPSOP_MASK_RD
,
11360 (unsigned long) imm_expr
.X_add_number
);
11361 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11362 imm_expr
.X_op
= O_absent
;
11366 case '!': /* MT usermode flag bit. */
11367 gas_assert (!mips_opts
.micromips
);
11368 my_getExpression (&imm_expr
, s
);
11369 check_absolute_expr (ip
, &imm_expr
);
11370 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11371 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11372 (unsigned long) imm_expr
.X_add_number
);
11373 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11374 imm_expr
.X_op
= O_absent
;
11378 case '$': /* MT load high flag bit. */
11379 gas_assert (!mips_opts
.micromips
);
11380 my_getExpression (&imm_expr
, s
);
11381 check_absolute_expr (ip
, &imm_expr
);
11382 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11383 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11384 (unsigned long) imm_expr
.X_add_number
);
11385 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11386 imm_expr
.X_op
= O_absent
;
11390 case '*': /* Four DSP accumulators in bits 18,19. */
11391 gas_assert (!mips_opts
.micromips
);
11392 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11393 s
[3] >= '0' && s
[3] <= '3')
11395 regno
= s
[3] - '0';
11397 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11401 as_bad (_("Invalid dsp/smartmips acc register"));
11404 case '&': /* Four DSP accumulators in bits 13,14. */
11405 gas_assert (!mips_opts
.micromips
);
11406 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11407 s
[3] >= '0' && s
[3] <= '3')
11409 regno
= s
[3] - '0';
11411 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11415 as_bad (_("Invalid dsp/smartmips acc register"));
11418 case '\\': /* 3-bit bit position. */
11420 unsigned long mask
= (mips_opts
.micromips
11421 ? MICROMIPSOP_MASK_3BITPOS
11422 : OP_MASK_3BITPOS
);
11424 my_getExpression (&imm_expr
, s
);
11425 check_absolute_expr (ip
, &imm_expr
);
11426 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11427 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11429 mask
, (unsigned long) imm_expr
.X_add_number
);
11430 INSERT_OPERAND (mips_opts
.micromips
,
11431 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11432 imm_expr
.X_op
= O_absent
;
11446 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11450 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11454 gas_assert (!mips_opts
.micromips
);
11455 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11459 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11465 /* Handle optional base register.
11466 Either the base register is omitted or
11467 we must have a left paren. */
11468 /* This is dependent on the next operand specifier
11469 is a base register specification. */
11470 gas_assert (args
[1] == 'b'
11471 || (mips_opts
.micromips
11473 && (args
[2] == 'l' || args
[2] == 'n'
11474 || args
[2] == 's' || args
[2] == 'a')));
11475 if (*s
== '\0' && args
[1] == 'b')
11477 /* Fall through. */
11479 case ')': /* These must match exactly. */
11484 case '[': /* These must match exactly. */
11486 gas_assert (!mips_opts
.micromips
);
11491 case '+': /* Opcode extension character. */
11494 case '1': /* UDI immediates. */
11498 gas_assert (!mips_opts
.micromips
);
11500 const struct mips_immed
*imm
= mips_immed
;
11502 while (imm
->type
&& imm
->type
!= *args
)
11506 my_getExpression (&imm_expr
, s
);
11507 check_absolute_expr (ip
, &imm_expr
);
11508 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11510 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11511 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11512 (unsigned long) imm_expr
.X_add_number
,
11513 (unsigned long) imm_expr
.X_add_number
);
11514 imm_expr
.X_add_number
&= imm
->mask
;
11516 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11518 imm_expr
.X_op
= O_absent
;
11523 case 'J': /* 10-bit hypcall code. */
11524 gas_assert (!mips_opts
.micromips
);
11526 unsigned long mask
= OP_MASK_CODE10
;
11528 my_getExpression (&imm_expr
, s
);
11529 check_absolute_expr (ip
, &imm_expr
);
11530 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11531 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11533 mask
, (unsigned long) imm_expr
.X_add_number
);
11534 INSERT_OPERAND (0, CODE10
, *ip
, imm_expr
.X_add_number
);
11535 imm_expr
.X_op
= O_absent
;
11540 case 'A': /* ins/ext position, becomes LSB. */
11549 my_getExpression (&imm_expr
, s
);
11550 check_absolute_expr (ip
, &imm_expr
);
11551 if ((unsigned long) imm_expr
.X_add_number
< limlo
11552 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11554 as_bad (_("Improper position (%lu)"),
11555 (unsigned long) imm_expr
.X_add_number
);
11556 imm_expr
.X_add_number
= limlo
;
11558 lastpos
= imm_expr
.X_add_number
;
11559 INSERT_OPERAND (mips_opts
.micromips
,
11560 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11561 imm_expr
.X_op
= O_absent
;
11565 case 'B': /* ins size, becomes MSB. */
11574 my_getExpression (&imm_expr
, s
);
11575 check_absolute_expr (ip
, &imm_expr
);
11576 /* Check for negative input so that small negative numbers
11577 will not succeed incorrectly. The checks against
11578 (pos+size) transitively check "size" itself,
11579 assuming that "pos" is reasonable. */
11580 if ((long) imm_expr
.X_add_number
< 0
11581 || ((unsigned long) imm_expr
.X_add_number
11583 || ((unsigned long) imm_expr
.X_add_number
11584 + lastpos
) > limhi
)
11586 as_bad (_("Improper insert size (%lu, position %lu)"),
11587 (unsigned long) imm_expr
.X_add_number
,
11588 (unsigned long) lastpos
);
11589 imm_expr
.X_add_number
= limlo
- lastpos
;
11591 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11592 lastpos
+ imm_expr
.X_add_number
- 1);
11593 imm_expr
.X_op
= O_absent
;
11597 case 'C': /* ext size, becomes MSBD. */
11613 my_getExpression (&imm_expr
, s
);
11614 check_absolute_expr (ip
, &imm_expr
);
11615 /* The checks against (pos+size) don't transitively check
11616 "size" itself, assuming that "pos" is reasonable.
11617 We also need to check the lower bound of "size". */
11618 if ((long) imm_expr
.X_add_number
< sizelo
11619 || ((unsigned long) imm_expr
.X_add_number
11621 || ((unsigned long) imm_expr
.X_add_number
11622 + lastpos
) > limhi
)
11624 as_bad (_("Improper extract size (%lu, position %lu)"),
11625 (unsigned long) imm_expr
.X_add_number
,
11626 (unsigned long) lastpos
);
11627 imm_expr
.X_add_number
= limlo
- lastpos
;
11629 INSERT_OPERAND (mips_opts
.micromips
,
11630 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11631 imm_expr
.X_op
= O_absent
;
11636 /* +D is for disassembly only; never match. */
11640 /* "+I" is like "I", except that imm2_expr is used. */
11641 my_getExpression (&imm2_expr
, s
);
11642 if (imm2_expr
.X_op
!= O_big
11643 && imm2_expr
.X_op
!= O_constant
)
11644 insn_error
= _("absolute expression required");
11645 if (HAVE_32BIT_GPRS
)
11646 normalize_constant_expr (&imm2_expr
);
11650 case 'T': /* Coprocessor register. */
11651 gas_assert (!mips_opts
.micromips
);
11652 /* +T is for disassembly only; never match. */
11655 case 't': /* Coprocessor register number. */
11656 gas_assert (!mips_opts
.micromips
);
11657 if (s
[0] == '$' && ISDIGIT (s
[1]))
11667 while (ISDIGIT (*s
));
11669 as_bad (_("Invalid register number (%d)"), regno
);
11672 INSERT_OPERAND (0, RT
, *ip
, regno
);
11677 as_bad (_("Invalid coprocessor 0 register number"));
11681 /* bbit[01] and bbit[01]32 bit index. Give error if index
11682 is not in the valid range. */
11683 gas_assert (!mips_opts
.micromips
);
11684 my_getExpression (&imm_expr
, s
);
11685 check_absolute_expr (ip
, &imm_expr
);
11686 if ((unsigned) imm_expr
.X_add_number
> 31)
11688 as_bad (_("Improper bit index (%lu)"),
11689 (unsigned long) imm_expr
.X_add_number
);
11690 imm_expr
.X_add_number
= 0;
11692 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11693 imm_expr
.X_op
= O_absent
;
11698 /* bbit[01] bit index when bbit is used but we generate
11699 bbit[01]32 because the index is over 32. Move to the
11700 next candidate if index is not in the valid range. */
11701 gas_assert (!mips_opts
.micromips
);
11702 my_getExpression (&imm_expr
, s
);
11703 check_absolute_expr (ip
, &imm_expr
);
11704 if ((unsigned) imm_expr
.X_add_number
< 32
11705 || (unsigned) imm_expr
.X_add_number
> 63)
11707 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11708 imm_expr
.X_op
= O_absent
;
11713 /* cins, cins32, exts and exts32 position field. Give error
11714 if it's not in the valid range. */
11715 gas_assert (!mips_opts
.micromips
);
11716 my_getExpression (&imm_expr
, s
);
11717 check_absolute_expr (ip
, &imm_expr
);
11718 if ((unsigned) imm_expr
.X_add_number
> 31)
11720 as_bad (_("Improper position (%lu)"),
11721 (unsigned long) imm_expr
.X_add_number
);
11722 imm_expr
.X_add_number
= 0;
11724 /* Make the pos explicit to simplify +S. */
11725 lastpos
= imm_expr
.X_add_number
+ 32;
11726 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11727 imm_expr
.X_op
= O_absent
;
11732 /* cins, cins32, exts and exts32 position field. Move to
11733 the next candidate if it's not in the valid range. */
11734 gas_assert (!mips_opts
.micromips
);
11735 my_getExpression (&imm_expr
, s
);
11736 check_absolute_expr (ip
, &imm_expr
);
11737 if ((unsigned) imm_expr
.X_add_number
< 32
11738 || (unsigned) imm_expr
.X_add_number
> 63)
11740 lastpos
= imm_expr
.X_add_number
;
11741 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11742 imm_expr
.X_op
= O_absent
;
11747 /* cins and exts length-minus-one field. */
11748 gas_assert (!mips_opts
.micromips
);
11749 my_getExpression (&imm_expr
, s
);
11750 check_absolute_expr (ip
, &imm_expr
);
11751 if ((unsigned long) imm_expr
.X_add_number
> 31)
11753 as_bad (_("Improper size (%lu)"),
11754 (unsigned long) imm_expr
.X_add_number
);
11755 imm_expr
.X_add_number
= 0;
11757 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11758 imm_expr
.X_op
= O_absent
;
11763 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11764 length-minus-one field. */
11765 gas_assert (!mips_opts
.micromips
);
11766 my_getExpression (&imm_expr
, s
);
11767 check_absolute_expr (ip
, &imm_expr
);
11768 if ((long) imm_expr
.X_add_number
< 0
11769 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11771 as_bad (_("Improper size (%lu)"),
11772 (unsigned long) imm_expr
.X_add_number
);
11773 imm_expr
.X_add_number
= 0;
11775 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11776 imm_expr
.X_op
= O_absent
;
11781 /* seqi/snei immediate field. */
11782 gas_assert (!mips_opts
.micromips
);
11783 my_getExpression (&imm_expr
, s
);
11784 check_absolute_expr (ip
, &imm_expr
);
11785 if ((long) imm_expr
.X_add_number
< -512
11786 || (long) imm_expr
.X_add_number
>= 512)
11788 as_bad (_("Improper immediate (%ld)"),
11789 (long) imm_expr
.X_add_number
);
11790 imm_expr
.X_add_number
= 0;
11792 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11793 imm_expr
.X_op
= O_absent
;
11797 case 'a': /* 8-bit signed offset in bit 6 */
11798 gas_assert (!mips_opts
.micromips
);
11799 my_getExpression (&imm_expr
, s
);
11800 check_absolute_expr (ip
, &imm_expr
);
11801 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11802 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11803 if (imm_expr
.X_add_number
< min_range
11804 || imm_expr
.X_add_number
> max_range
)
11806 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11807 (long) min_range
, (long) max_range
,
11808 (long) imm_expr
.X_add_number
);
11810 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11811 imm_expr
.X_op
= O_absent
;
11815 case 'b': /* 8-bit signed offset in bit 3 */
11816 gas_assert (!mips_opts
.micromips
);
11817 my_getExpression (&imm_expr
, s
);
11818 check_absolute_expr (ip
, &imm_expr
);
11819 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11820 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11821 if (imm_expr
.X_add_number
< min_range
11822 || imm_expr
.X_add_number
> max_range
)
11824 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11825 (long) min_range
, (long) max_range
,
11826 (long) imm_expr
.X_add_number
);
11828 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11829 imm_expr
.X_op
= O_absent
;
11833 case 'c': /* 9-bit signed offset in bit 6 */
11834 gas_assert (!mips_opts
.micromips
);
11835 my_getExpression (&imm_expr
, s
);
11836 check_absolute_expr (ip
, &imm_expr
);
11837 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11838 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11839 /* We check the offset range before adjusted. */
11842 if (imm_expr
.X_add_number
< min_range
11843 || imm_expr
.X_add_number
> max_range
)
11845 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11846 (long) min_range
, (long) max_range
,
11847 (long) imm_expr
.X_add_number
);
11849 if (imm_expr
.X_add_number
& 0xf)
11851 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11852 (long) imm_expr
.X_add_number
);
11854 /* Right shift 4 bits to adjust the offset operand. */
11855 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11856 imm_expr
.X_add_number
>> 4);
11857 imm_expr
.X_op
= O_absent
;
11862 gas_assert (!mips_opts
.micromips
);
11863 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11865 if (regno
== AT
&& mips_opts
.at
)
11867 if (mips_opts
.at
== ATREG
)
11868 as_warn (_("used $at without \".set noat\""));
11870 as_warn (_("used $%u with \".set at=$%u\""),
11871 regno
, mips_opts
.at
);
11873 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11877 gas_assert (!mips_opts
.micromips
);
11878 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11880 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11887 /* Check whether there is only a single bracketed expression
11888 left. If so, it must be the base register and the
11889 constant must be zero. */
11890 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11893 /* If this value won't fit into the offset, then go find
11894 a macro that will generate a 16- or 32-bit offset code
11896 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11897 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11898 || imm_expr
.X_add_number
>= 1 << shift
11899 || imm_expr
.X_add_number
< -1 << shift
))
11902 imm_expr
.X_op
= O_absent
;
11905 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, *ip
,
11906 imm_expr
.X_add_number
);
11907 imm_expr
.X_op
= O_absent
;
11913 as_bad (_("Internal error: bad %s opcode "
11914 "(unknown extension operand type `+%c'): %s %s"),
11915 mips_opts
.micromips
? "microMIPS" : "MIPS",
11916 *args
, insn
->name
, insn
->args
);
11917 /* Further processing is fruitless. */
11922 case '.': /* 10-bit offset. */
11923 gas_assert (mips_opts
.micromips
);
11924 case '~': /* 12-bit offset. */
11926 int shift
= *args
== '.' ? 9 : 11;
11929 /* Check whether there is only a single bracketed expression
11930 left. If so, it must be the base register and the
11931 constant must be zero. */
11932 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11935 /* If this value won't fit into the offset, then go find
11936 a macro that will generate a 16- or 32-bit offset code
11938 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11939 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11940 || imm_expr
.X_add_number
>= 1 << shift
11941 || imm_expr
.X_add_number
< -1 << shift
))
11944 imm_expr
.X_op
= O_absent
;
11948 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11950 INSERT_OPERAND (mips_opts
.micromips
,
11951 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11952 imm_expr
.X_op
= O_absent
;
11957 case '<': /* must be at least one digit */
11959 * According to the manual, if the shift amount is greater
11960 * than 31 or less than 0, then the shift amount should be
11961 * mod 32. In reality the mips assembler issues an error.
11962 * We issue a warning and mask out all but the low 5 bits.
11964 my_getExpression (&imm_expr
, s
);
11965 check_absolute_expr (ip
, &imm_expr
);
11966 if ((unsigned long) imm_expr
.X_add_number
> 31)
11967 as_warn (_("Improper shift amount (%lu)"),
11968 (unsigned long) imm_expr
.X_add_number
);
11969 INSERT_OPERAND (mips_opts
.micromips
,
11970 SHAMT
, *ip
, imm_expr
.X_add_number
);
11971 imm_expr
.X_op
= O_absent
;
11975 case '>': /* shift amount minus 32 */
11976 my_getExpression (&imm_expr
, s
);
11977 check_absolute_expr (ip
, &imm_expr
);
11978 if ((unsigned long) imm_expr
.X_add_number
< 32
11979 || (unsigned long) imm_expr
.X_add_number
> 63)
11981 INSERT_OPERAND (mips_opts
.micromips
,
11982 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11983 imm_expr
.X_op
= O_absent
;
11987 case 'k': /* CACHE code. */
11988 case 'h': /* PREFX code. */
11989 case '1': /* SYNC type. */
11990 my_getExpression (&imm_expr
, s
);
11991 check_absolute_expr (ip
, &imm_expr
);
11992 if ((unsigned long) imm_expr
.X_add_number
> 31)
11993 as_warn (_("Invalid value for `%s' (%lu)"),
11995 (unsigned long) imm_expr
.X_add_number
);
11999 if (mips_fix_cn63xxp1
12000 && !mips_opts
.micromips
12001 && strcmp ("pref", insn
->name
) == 0)
12002 switch (imm_expr
.X_add_number
)
12011 case 31: /* These are ok. */
12014 default: /* The rest must be changed to 28. */
12015 imm_expr
.X_add_number
= 28;
12018 INSERT_OPERAND (mips_opts
.micromips
,
12019 CACHE
, *ip
, imm_expr
.X_add_number
);
12022 INSERT_OPERAND (mips_opts
.micromips
,
12023 PREFX
, *ip
, imm_expr
.X_add_number
);
12026 INSERT_OPERAND (mips_opts
.micromips
,
12027 STYPE
, *ip
, imm_expr
.X_add_number
);
12030 imm_expr
.X_op
= O_absent
;
12034 case 'c': /* BREAK code. */
12036 unsigned long mask
= (mips_opts
.micromips
12037 ? MICROMIPSOP_MASK_CODE
12040 my_getExpression (&imm_expr
, s
);
12041 check_absolute_expr (ip
, &imm_expr
);
12042 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12043 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12045 mask
, (unsigned long) imm_expr
.X_add_number
);
12046 INSERT_OPERAND (mips_opts
.micromips
,
12047 CODE
, *ip
, imm_expr
.X_add_number
);
12048 imm_expr
.X_op
= O_absent
;
12053 case 'q': /* Lower BREAK code. */
12055 unsigned long mask
= (mips_opts
.micromips
12056 ? MICROMIPSOP_MASK_CODE2
12059 my_getExpression (&imm_expr
, s
);
12060 check_absolute_expr (ip
, &imm_expr
);
12061 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12062 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12064 mask
, (unsigned long) imm_expr
.X_add_number
);
12065 INSERT_OPERAND (mips_opts
.micromips
,
12066 CODE2
, *ip
, imm_expr
.X_add_number
);
12067 imm_expr
.X_op
= O_absent
;
12072 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12074 unsigned long mask
= (mips_opts
.micromips
12075 ? MICROMIPSOP_MASK_CODE10
12078 my_getExpression (&imm_expr
, s
);
12079 check_absolute_expr (ip
, &imm_expr
);
12080 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12081 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12083 mask
, (unsigned long) imm_expr
.X_add_number
);
12084 if (mips_opts
.micromips
)
12085 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
12087 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
12088 imm_expr
.X_op
= O_absent
;
12093 case 'C': /* 25- or 23-bit coprocessor code. */
12095 unsigned long mask
= (mips_opts
.micromips
12096 ? MICROMIPSOP_MASK_COPZ
12099 my_getExpression (&imm_expr
, s
);
12100 check_absolute_expr (ip
, &imm_expr
);
12101 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12102 as_warn (_("Coproccesor code > %u bits (%lu)"),
12103 mips_opts
.micromips
? 23U : 25U,
12104 (unsigned long) imm_expr
.X_add_number
);
12105 INSERT_OPERAND (mips_opts
.micromips
,
12106 COPZ
, *ip
, imm_expr
.X_add_number
);
12107 imm_expr
.X_op
= O_absent
;
12112 case 'J': /* 19-bit WAIT code. */
12113 gas_assert (!mips_opts
.micromips
);
12114 my_getExpression (&imm_expr
, s
);
12115 check_absolute_expr (ip
, &imm_expr
);
12116 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
12118 as_warn (_("Illegal 19-bit code (%lu)"),
12119 (unsigned long) imm_expr
.X_add_number
);
12120 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
12122 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
12123 imm_expr
.X_op
= O_absent
;
12127 case 'P': /* Performance register. */
12128 gas_assert (!mips_opts
.micromips
);
12129 my_getExpression (&imm_expr
, s
);
12130 check_absolute_expr (ip
, &imm_expr
);
12131 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
12132 as_warn (_("Invalid performance register (%lu)"),
12133 (unsigned long) imm_expr
.X_add_number
);
12134 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
12135 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
12136 as_warn (_("Invalid performance register (%lu)"),
12137 (unsigned long) imm_expr
.X_add_number
);
12138 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
12139 imm_expr
.X_op
= O_absent
;
12143 case 'G': /* Coprocessor destination register. */
12145 unsigned long opcode
= ip
->insn_opcode
;
12146 unsigned long mask
;
12147 unsigned int types
;
12150 if (mips_opts
.micromips
)
12152 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
12153 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
12154 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
12158 case 0x000000fc: /* mfc0 */
12159 case 0x000002fc: /* mtc0 */
12160 case 0x580000fc: /* dmfc0 */
12161 case 0x580002fc: /* dmtc0 */
12171 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
12172 cop0
= opcode
== OP_OP_COP0
;
12174 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
12175 ok
= reg_lookup (&s
, types
, ®no
);
12176 if (mips_opts
.micromips
)
12177 INSERT_OPERAND (1, RS
, *ip
, regno
);
12179 INSERT_OPERAND (0, RD
, *ip
, regno
);
12188 case 'y': /* ALNV.PS source register. */
12189 gas_assert (mips_opts
.micromips
);
12191 case 'x': /* Ignore register name. */
12192 case 'U': /* Destination register (CLO/CLZ). */
12193 case 'g': /* Coprocessor destination register. */
12194 gas_assert (!mips_opts
.micromips
);
12195 case 'b': /* Base register. */
12196 case 'd': /* Destination register. */
12197 case 's': /* Source register. */
12198 case 't': /* Target register. */
12199 case 'r': /* Both target and source. */
12200 case 'v': /* Both dest and source. */
12201 case 'w': /* Both dest and target. */
12202 case 'E': /* Coprocessor target register. */
12203 case 'K': /* RDHWR destination register. */
12204 case 'z': /* Must be zero register. */
12207 if (*args
== 'E' || *args
== 'K')
12208 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
12211 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12212 if (regno
== AT
&& mips_opts
.at
)
12214 if (mips_opts
.at
== ATREG
)
12215 as_warn (_("Used $at without \".set noat\""));
12217 as_warn (_("Used $%u with \".set at=$%u\""),
12218 regno
, mips_opts
.at
);
12228 if (c
== 'r' || c
== 'v' || c
== 'w')
12235 /* 'z' only matches $0. */
12236 if (c
== 'z' && regno
!= 0)
12239 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12241 if (regno
== lastregno
)
12244 = _("Source and destination must be different");
12247 if (regno
== 31 && lastregno
== 0xffffffff)
12250 = _("A destination register must be supplied");
12254 /* Now that we have assembled one operand, we use the args
12255 string to figure out where it goes in the instruction. */
12262 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12266 if (mips_opts
.micromips
)
12267 INSERT_OPERAND (1, RS
, *ip
, regno
);
12269 INSERT_OPERAND (0, RD
, *ip
, regno
);
12274 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12278 gas_assert (!mips_opts
.micromips
);
12279 INSERT_OPERAND (0, RD
, *ip
, regno
);
12280 INSERT_OPERAND (0, RT
, *ip
, regno
);
12286 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12290 gas_assert (mips_opts
.micromips
);
12291 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12295 /* This case exists because on the r3000 trunc
12296 expands into a macro which requires a gp
12297 register. On the r6000 or r4000 it is
12298 assembled into a single instruction which
12299 ignores the register. Thus the insn version
12300 is MIPS_ISA2 and uses 'x', and the macro
12301 version is MIPS_ISA1 and uses 't'. */
12305 /* This case is for the div instruction, which
12306 acts differently if the destination argument
12307 is $0. This only matches $0, and is checked
12308 outside the switch. */
12318 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12322 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12327 case 'O': /* MDMX alignment immediate constant. */
12328 gas_assert (!mips_opts
.micromips
);
12329 my_getExpression (&imm_expr
, s
);
12330 check_absolute_expr (ip
, &imm_expr
);
12331 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12332 as_warn (_("Improper align amount (%ld), using low bits"),
12333 (long) imm_expr
.X_add_number
);
12334 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12335 imm_expr
.X_op
= O_absent
;
12339 case 'Q': /* MDMX vector, element sel, or const. */
12342 /* MDMX Immediate. */
12343 gas_assert (!mips_opts
.micromips
);
12344 my_getExpression (&imm_expr
, s
);
12345 check_absolute_expr (ip
, &imm_expr
);
12346 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12347 as_warn (_("Invalid MDMX Immediate (%ld)"),
12348 (long) imm_expr
.X_add_number
);
12349 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12350 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12351 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12353 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12354 imm_expr
.X_op
= O_absent
;
12358 /* Not MDMX Immediate. Fall through. */
12359 case 'X': /* MDMX destination register. */
12360 case 'Y': /* MDMX source register. */
12361 case 'Z': /* MDMX target register. */
12364 gas_assert (!mips_opts
.micromips
);
12365 case 'D': /* Floating point destination register. */
12366 case 'S': /* Floating point source register. */
12367 case 'T': /* Floating point target register. */
12368 case 'R': /* Floating point source register. */
12372 || (mips_opts
.ase_mdmx
12373 && (ip
->insn_mo
->pinfo
& FP_D
)
12374 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12375 | INSN_COPROC_MEMORY_DELAY
12376 | INSN_LOAD_COPROC_DELAY
12377 | INSN_LOAD_MEMORY_DELAY
12378 | INSN_STORE_MEMORY
))))
12379 rtype
|= RTYPE_VEC
;
12381 if (reg_lookup (&s
, rtype
, ®no
))
12383 if ((regno
& 1) != 0
12385 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12386 as_warn (_("Float register should be even, was %d"),
12394 if (c
== 'V' || c
== 'W')
12405 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12411 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12415 /* This is like 'Z', but also needs to fix the MDMX
12416 vector/scalar select bits. Note that the
12417 scalar immediate case is handled above. */
12420 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12421 int max_el
= (is_qh
? 3 : 7);
12423 my_getExpression(&imm_expr
, s
);
12424 check_absolute_expr (ip
, &imm_expr
);
12426 if (imm_expr
.X_add_number
> max_el
)
12427 as_bad (_("Bad element selector %ld"),
12428 (long) imm_expr
.X_add_number
);
12429 imm_expr
.X_add_number
&= max_el
;
12430 ip
->insn_opcode
|= (imm_expr
.X_add_number
12433 imm_expr
.X_op
= O_absent
;
12435 as_warn (_("Expecting ']' found '%s'"), s
);
12441 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12442 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12445 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12448 /* Fall through. */
12452 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12456 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12466 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12470 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12476 my_getExpression (&imm_expr
, s
);
12477 if (imm_expr
.X_op
!= O_big
12478 && imm_expr
.X_op
!= O_constant
)
12479 insn_error
= _("absolute expression required");
12480 if (HAVE_32BIT_GPRS
)
12481 normalize_constant_expr (&imm_expr
);
12486 my_getExpression (&offset_expr
, s
);
12487 normalize_address_expr (&offset_expr
);
12488 *imm_reloc
= BFD_RELOC_32
;
12501 unsigned char temp
[8];
12503 unsigned int length
;
12508 /* These only appear as the last operand in an
12509 instruction, and every instruction that accepts
12510 them in any variant accepts them in all variants.
12511 This means we don't have to worry about backing out
12512 any changes if the instruction does not match.
12514 The difference between them is the size of the
12515 floating point constant and where it goes. For 'F'
12516 and 'L' the constant is 64 bits; for 'f' and 'l' it
12517 is 32 bits. Where the constant is placed is based
12518 on how the MIPS assembler does things:
12521 f -- immediate value
12524 The .lit4 and .lit8 sections are only used if
12525 permitted by the -G argument.
12527 The code below needs to know whether the target register
12528 is 32 or 64 bits wide. It relies on the fact 'f' and
12529 'F' are used with GPR-based instructions and 'l' and
12530 'L' are used with FPR-based instructions. */
12532 f64
= *args
== 'F' || *args
== 'L';
12533 using_gprs
= *args
== 'F' || *args
== 'f';
12535 save_in
= input_line_pointer
;
12536 input_line_pointer
= s
;
12537 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12539 s
= input_line_pointer
;
12540 input_line_pointer
= save_in
;
12541 if (err
!= NULL
&& *err
!= '\0')
12543 as_bad (_("Bad floating point constant: %s"), err
);
12544 memset (temp
, '\0', sizeof temp
);
12545 length
= f64
? 8 : 4;
12548 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12552 && (g_switch_value
< 4
12553 || (temp
[0] == 0 && temp
[1] == 0)
12554 || (temp
[2] == 0 && temp
[3] == 0))))
12556 imm_expr
.X_op
= O_constant
;
12557 if (!target_big_endian
)
12558 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12560 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12562 else if (length
> 4
12563 && !mips_disable_float_construction
12564 /* Constants can only be constructed in GPRs and
12565 copied to FPRs if the GPRs are at least as wide
12566 as the FPRs. Force the constant into memory if
12567 we are using 64-bit FPRs but the GPRs are only
12570 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12571 && ((temp
[0] == 0 && temp
[1] == 0)
12572 || (temp
[2] == 0 && temp
[3] == 0))
12573 && ((temp
[4] == 0 && temp
[5] == 0)
12574 || (temp
[6] == 0 && temp
[7] == 0)))
12576 /* The value is simple enough to load with a couple of
12577 instructions. If using 32-bit registers, set
12578 imm_expr to the high order 32 bits and offset_expr to
12579 the low order 32 bits. Otherwise, set imm_expr to
12580 the entire 64 bit constant. */
12581 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12583 imm_expr
.X_op
= O_constant
;
12584 offset_expr
.X_op
= O_constant
;
12585 if (!target_big_endian
)
12587 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12588 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12592 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12593 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12595 if (offset_expr
.X_add_number
== 0)
12596 offset_expr
.X_op
= O_absent
;
12598 else if (sizeof (imm_expr
.X_add_number
) > 4)
12600 imm_expr
.X_op
= O_constant
;
12601 if (!target_big_endian
)
12602 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12604 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12608 imm_expr
.X_op
= O_big
;
12609 imm_expr
.X_add_number
= 4;
12610 if (!target_big_endian
)
12612 generic_bignum
[0] = bfd_getl16 (temp
);
12613 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12614 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12615 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12619 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12620 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12621 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12622 generic_bignum
[3] = bfd_getb16 (temp
);
12628 const char *newname
;
12631 /* Switch to the right section. */
12633 subseg
= now_subseg
;
12636 default: /* unused default case avoids warnings. */
12638 newname
= RDATA_SECTION_NAME
;
12639 if (g_switch_value
>= 8)
12643 newname
= RDATA_SECTION_NAME
;
12646 gas_assert (g_switch_value
>= 4);
12650 new_seg
= subseg_new (newname
, (subsegT
) 0);
12652 bfd_set_section_flags (stdoutput
, new_seg
,
12657 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12658 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12659 record_alignment (new_seg
, 4);
12661 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12662 if (seg
== now_seg
)
12663 as_bad (_("Can't use floating point insn in this section"));
12665 /* Set the argument to the current address in the
12667 offset_expr
.X_op
= O_symbol
;
12668 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12669 offset_expr
.X_add_number
= 0;
12671 /* Put the floating point number into the section. */
12672 p
= frag_more ((int) length
);
12673 memcpy (p
, temp
, length
);
12675 /* Switch back to the original section. */
12676 subseg_set (seg
, subseg
);
12681 case 'i': /* 16-bit unsigned immediate. */
12682 case 'j': /* 16-bit signed immediate. */
12683 *imm_reloc
= BFD_RELOC_LO16
;
12684 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12687 offsetT minval
, maxval
;
12689 more
= (insn
+ 1 < past
12690 && strcmp (insn
->name
, insn
[1].name
) == 0);
12692 /* If the expression was written as an unsigned number,
12693 only treat it as signed if there are no more
12697 && sizeof (imm_expr
.X_add_number
) <= 4
12698 && imm_expr
.X_op
== O_constant
12699 && imm_expr
.X_add_number
< 0
12700 && imm_expr
.X_unsigned
12701 && HAVE_64BIT_GPRS
)
12704 /* For compatibility with older assemblers, we accept
12705 0x8000-0xffff as signed 16-bit numbers when only
12706 signed numbers are allowed. */
12708 minval
= 0, maxval
= 0xffff;
12710 minval
= -0x8000, maxval
= 0x7fff;
12712 minval
= -0x8000, maxval
= 0xffff;
12714 if (imm_expr
.X_op
!= O_constant
12715 || imm_expr
.X_add_number
< minval
12716 || imm_expr
.X_add_number
> maxval
)
12720 if (imm_expr
.X_op
== O_constant
12721 || imm_expr
.X_op
== O_big
)
12722 as_bad (_("Expression out of range"));
12728 case 'o': /* 16-bit offset. */
12729 offset_reloc
[0] = BFD_RELOC_LO16
;
12730 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12731 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12733 /* Check whether there is only a single bracketed expression
12734 left. If so, it must be the base register and the
12735 constant must be zero. */
12736 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12738 offset_expr
.X_op
= O_constant
;
12739 offset_expr
.X_add_number
= 0;
12743 /* If this value won't fit into a 16 bit offset, then go
12744 find a macro that will generate the 32 bit offset
12746 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12747 && (offset_expr
.X_op
!= O_constant
12748 || offset_expr
.X_add_number
>= 0x8000
12749 || offset_expr
.X_add_number
< -0x8000))
12755 case 'p': /* PC-relative offset. */
12756 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12757 my_getExpression (&offset_expr
, s
);
12761 case 'u': /* Upper 16 bits. */
12762 *imm_reloc
= BFD_RELOC_LO16
;
12763 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12764 && imm_expr
.X_op
== O_constant
12765 && (imm_expr
.X_add_number
< 0
12766 || imm_expr
.X_add_number
>= 0x10000))
12767 as_bad (_("lui expression (%lu) not in range 0..65535"),
12768 (unsigned long) imm_expr
.X_add_number
);
12772 case 'a': /* 26-bit address. */
12773 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12774 my_getExpression (&offset_expr
, s
);
12778 case 'N': /* 3-bit branch condition code. */
12779 case 'M': /* 3-bit compare condition code. */
12781 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12782 rtype
|= RTYPE_FCC
;
12783 if (!reg_lookup (&s
, rtype
, ®no
))
12785 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12786 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12787 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12788 && (regno
& 1) != 0)
12789 as_warn (_("Condition code register should be even for %s, "
12792 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12793 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12794 && (regno
& 3) != 0)
12795 as_warn (_("Condition code register should be 0 or 4 for %s, "
12799 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12801 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12805 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12816 while (ISDIGIT (*s
));
12819 c
= 8; /* Invalid sel value. */
12822 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12823 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12827 gas_assert (!mips_opts
.micromips
);
12828 /* Must be at least one digit. */
12829 my_getExpression (&imm_expr
, s
);
12830 check_absolute_expr (ip
, &imm_expr
);
12832 if ((unsigned long) imm_expr
.X_add_number
12833 > (unsigned long) OP_MASK_VECBYTE
)
12835 as_bad (_("bad byte vector index (%ld)"),
12836 (long) imm_expr
.X_add_number
);
12837 imm_expr
.X_add_number
= 0;
12840 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12841 imm_expr
.X_op
= O_absent
;
12846 gas_assert (!mips_opts
.micromips
);
12847 my_getExpression (&imm_expr
, s
);
12848 check_absolute_expr (ip
, &imm_expr
);
12850 if ((unsigned long) imm_expr
.X_add_number
12851 > (unsigned long) OP_MASK_VECALIGN
)
12853 as_bad (_("bad byte vector index (%ld)"),
12854 (long) imm_expr
.X_add_number
);
12855 imm_expr
.X_add_number
= 0;
12858 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12859 imm_expr
.X_op
= O_absent
;
12863 case 'm': /* Opcode extension character. */
12864 gas_assert (mips_opts
.micromips
);
12869 if (strncmp (s
, "$pc", 3) == 0)
12897 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12898 if (regno
== AT
&& mips_opts
.at
)
12900 if (mips_opts
.at
== ATREG
)
12901 as_warn (_("Used $at without \".set noat\""));
12903 as_warn (_("Used $%u with \".set at=$%u\""),
12904 regno
, mips_opts
.at
);
12910 gas_assert (args
[1] == ',');
12916 gas_assert (args
[1] == ',');
12918 continue; /* Nothing to do. */
12924 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12926 if (regno
== lastregno
)
12929 = _("Source and destination must be different");
12932 if (regno
== 31 && lastregno
== 0xffffffff)
12935 = _("A destination register must be supplied");
12946 gas_assert (args
[1] == ',');
12953 gas_assert (args
[1] == ',');
12956 continue; /* Nothing to do. */
12960 /* Make sure regno is the same as lastregno. */
12961 if (c
== 't' && regno
!= lastregno
)
12964 /* Make sure regno is the same as destregno. */
12965 if (c
== 'x' && regno
!= destregno
)
12968 /* We need to save regno, before regno maps to the
12969 microMIPS register encoding. */
12979 regno
= ILLEGAL_REG
;
12983 regno
= mips32_to_micromips_reg_b_map
[regno
];
12987 regno
= mips32_to_micromips_reg_c_map
[regno
];
12991 regno
= mips32_to_micromips_reg_d_map
[regno
];
12995 regno
= mips32_to_micromips_reg_e_map
[regno
];
12999 regno
= mips32_to_micromips_reg_f_map
[regno
];
13003 regno
= mips32_to_micromips_reg_g_map
[regno
];
13007 regno
= mips32_to_micromips_reg_h_map
[regno
];
13011 switch (EXTRACT_OPERAND (1, MI
, *ip
))
13016 else if (regno
== 22)
13018 else if (regno
== 5)
13020 else if (regno
== 6)
13022 else if (regno
== 7)
13025 regno
= ILLEGAL_REG
;
13031 else if (regno
== 7)
13034 regno
= ILLEGAL_REG
;
13041 regno
= ILLEGAL_REG
;
13045 regno
= ILLEGAL_REG
;
13051 regno
= mips32_to_micromips_reg_l_map
[regno
];
13055 regno
= mips32_to_micromips_reg_m_map
[regno
];
13059 regno
= mips32_to_micromips_reg_n_map
[regno
];
13063 regno
= mips32_to_micromips_reg_q_map
[regno
];
13068 regno
= ILLEGAL_REG
;
13073 regno
= ILLEGAL_REG
;
13078 regno
= ILLEGAL_REG
;
13081 case 'j': /* Do nothing. */
13091 if (regno
== ILLEGAL_REG
)
13097 INSERT_OPERAND (1, MB
, *ip
, regno
);
13101 INSERT_OPERAND (1, MC
, *ip
, regno
);
13105 INSERT_OPERAND (1, MD
, *ip
, regno
);
13109 INSERT_OPERAND (1, ME
, *ip
, regno
);
13113 INSERT_OPERAND (1, MF
, *ip
, regno
);
13117 INSERT_OPERAND (1, MG
, *ip
, regno
);
13121 INSERT_OPERAND (1, MH
, *ip
, regno
);
13125 INSERT_OPERAND (1, MI
, *ip
, regno
);
13129 INSERT_OPERAND (1, MJ
, *ip
, regno
);
13133 INSERT_OPERAND (1, ML
, *ip
, regno
);
13137 INSERT_OPERAND (1, MM
, *ip
, regno
);
13141 INSERT_OPERAND (1, MN
, *ip
, regno
);
13145 INSERT_OPERAND (1, MP
, *ip
, regno
);
13149 INSERT_OPERAND (1, MQ
, *ip
, regno
);
13152 case 'a': /* Do nothing. */
13153 case 's': /* Do nothing. */
13154 case 't': /* Do nothing. */
13155 case 'x': /* Do nothing. */
13156 case 'y': /* Do nothing. */
13157 case 'z': /* Do nothing. */
13167 bfd_reloc_code_real_type r
[3];
13171 /* Check whether there is only a single bracketed
13172 expression left. If so, it must be the base register
13173 and the constant must be zero. */
13174 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13176 INSERT_OPERAND (1, IMMA
, *ip
, 0);
13180 if (my_getSmallExpression (&ep
, r
, s
) > 0
13181 || !expr_const_in_range (&ep
, -64, 64, 2))
13184 imm
= ep
.X_add_number
>> 2;
13185 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
13192 bfd_reloc_code_real_type r
[3];
13196 if (my_getSmallExpression (&ep
, r
, s
) > 0
13197 || ep
.X_op
!= O_constant
)
13200 for (imm
= 0; imm
< 8; imm
++)
13201 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
13206 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
13213 bfd_reloc_code_real_type r
[3];
13217 if (my_getSmallExpression (&ep
, r
, s
) > 0
13218 || ep
.X_op
!= O_constant
)
13221 for (imm
= 0; imm
< 16; imm
++)
13222 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
13227 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13232 case 'D': /* pc relative offset */
13233 case 'E': /* pc relative offset */
13234 my_getExpression (&offset_expr
, s
);
13235 if (offset_expr
.X_op
== O_register
)
13238 if (!forced_insn_length
)
13239 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13241 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13243 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13249 bfd_reloc_code_real_type r
[3];
13253 if (my_getSmallExpression (&ep
, r
, s
) > 0
13254 || !expr_const_in_range (&ep
, 0, 16, 0))
13257 imm
= ep
.X_add_number
;
13258 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13265 bfd_reloc_code_real_type r
[3];
13269 /* Check whether there is only a single bracketed
13270 expression left. If so, it must be the base register
13271 and the constant must be zero. */
13272 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13274 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13278 if (my_getSmallExpression (&ep
, r
, s
) > 0
13279 || !expr_const_in_range (&ep
, -1, 15, 0))
13282 imm
= ep
.X_add_number
& 15;
13283 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13290 bfd_reloc_code_real_type r
[3];
13294 /* Check whether there is only a single bracketed
13295 expression left. If so, it must be the base register
13296 and the constant must be zero. */
13297 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13299 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13303 if (my_getSmallExpression (&ep
, r
, s
) > 0
13304 || !expr_const_in_range (&ep
, 0, 16, 1))
13307 imm
= ep
.X_add_number
>> 1;
13308 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13315 bfd_reloc_code_real_type r
[3];
13319 if (my_getSmallExpression (&ep
, r
, s
) > 0
13320 || !expr_const_in_range (&ep
, -1, 127, 0))
13323 imm
= ep
.X_add_number
& 127;
13324 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13331 bfd_reloc_code_real_type r
[3];
13335 /* Check whether there is only a single bracketed
13336 expression left. If so, it must be the base register
13337 and the constant must be zero. */
13338 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13340 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13344 if (my_getSmallExpression (&ep
, r
, s
) > 0
13345 || !expr_const_in_range (&ep
, 0, 16, 2))
13348 imm
= ep
.X_add_number
>> 2;
13349 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13356 bfd_reloc_code_real_type r
[3];
13360 /* Check whether there is only a single bracketed
13361 expression left. If so, it must be the base register
13362 and the constant must be zero. */
13363 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13365 INSERT_OPERAND (1, IMML
, *ip
, 0);
13369 if (my_getSmallExpression (&ep
, r
, s
) > 0
13370 || !expr_const_in_range (&ep
, 0, 16, 0))
13373 imm
= ep
.X_add_number
;
13374 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13381 bfd_reloc_code_real_type r
[3];
13385 if (my_getSmallExpression (&ep
, r
, s
) > 0
13386 || !expr_const_in_range (&ep
, 1, 9, 0))
13389 imm
= ep
.X_add_number
& 7;
13390 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13395 case 'N': /* Register list for lwm and swm. */
13397 /* A comma-separated list of registers and/or
13398 dash-separated contiguous ranges including
13399 both ra and a set of one or more registers
13400 starting at s0 up to s3 which have to be
13407 and any permutations of these. */
13408 unsigned int reglist
;
13411 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13414 if ((reglist
& 0xfff1ffff) != 0x80010000)
13417 reglist
= (reglist
>> 17) & 7;
13419 if ((reglist
& -reglist
) != reglist
)
13422 imm
= ffs (reglist
) - 1;
13423 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13427 case 'O': /* sdbbp 4-bit code. */
13429 bfd_reloc_code_real_type r
[3];
13433 if (my_getSmallExpression (&ep
, r
, s
) > 0
13434 || !expr_const_in_range (&ep
, 0, 16, 0))
13437 imm
= ep
.X_add_number
;
13438 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13445 bfd_reloc_code_real_type r
[3];
13449 if (my_getSmallExpression (&ep
, r
, s
) > 0
13450 || !expr_const_in_range (&ep
, 0, 32, 2))
13453 imm
= ep
.X_add_number
>> 2;
13454 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13461 bfd_reloc_code_real_type r
[3];
13465 if (my_getSmallExpression (&ep
, r
, s
) > 0
13466 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13469 imm
= ep
.X_add_number
>> 2;
13470 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13477 bfd_reloc_code_real_type r
[3];
13481 /* Check whether there is only a single bracketed
13482 expression left. If so, it must be the base register
13483 and the constant must be zero. */
13484 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13486 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13490 if (my_getSmallExpression (&ep
, r
, s
) > 0
13491 || !expr_const_in_range (&ep
, 0, 32, 2))
13494 imm
= ep
.X_add_number
>> 2;
13495 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13502 bfd_reloc_code_real_type r
[3];
13506 if (my_getSmallExpression (&ep
, r
, s
) > 0
13507 || !expr_const_in_range (&ep
, 0, 64, 2))
13510 imm
= ep
.X_add_number
>> 2;
13511 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13518 bfd_reloc_code_real_type r
[3];
13522 if (my_getSmallExpression (&ep
, r
, s
) > 0
13523 || !expr_const_in_range (&ep
, -8, 8, 0))
13526 imm
= ep
.X_add_number
;
13527 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13534 bfd_reloc_code_real_type r
[3];
13538 if (my_getSmallExpression (&ep
, r
, s
) > 0
13539 || expr_const_in_range (&ep
, -2, 2, 2)
13540 || !expr_const_in_range (&ep
, -258, 258, 2))
13543 imm
= ep
.X_add_number
>> 2;
13544 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13545 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13552 bfd_reloc_code_real_type r
[3];
13555 if (my_getSmallExpression (&ep
, r
, s
) > 0
13556 || !expr_const_in_range (&ep
, 0, 1, 0))
13563 as_bad (_("Internal error: bad microMIPS opcode "
13564 "(unknown extension operand type `m%c'): %s %s"),
13565 *args
, insn
->name
, insn
->args
);
13566 /* Further processing is fruitless. */
13571 case 'n': /* Register list for 32-bit lwm and swm. */
13572 gas_assert (mips_opts
.micromips
);
13574 /* A comma-separated list of registers and/or
13575 dash-separated contiguous ranges including
13576 at least one of ra and a set of one or more
13577 registers starting at s0 up to s7 and then
13578 s8 which have to be consecutive, e.g.:
13586 and any permutations of these. */
13587 unsigned int reglist
;
13591 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13594 if ((reglist
& 0x3f00ffff) != 0)
13597 ra
= (reglist
>> 27) & 0x10;
13598 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13600 if ((reglist
& -reglist
) != reglist
)
13603 imm
= (ffs (reglist
) - 1) | ra
;
13604 INSERT_OPERAND (1, RT
, *ip
, imm
);
13605 imm_expr
.X_op
= O_absent
;
13609 case '|': /* 4-bit trap code. */
13610 gas_assert (mips_opts
.micromips
);
13611 my_getExpression (&imm_expr
, s
);
13612 check_absolute_expr (ip
, &imm_expr
);
13613 if ((unsigned long) imm_expr
.X_add_number
13614 > MICROMIPSOP_MASK_TRAP
)
13615 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13616 (unsigned long) imm_expr
.X_add_number
,
13617 ip
->insn_mo
->name
);
13618 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13619 imm_expr
.X_op
= O_absent
;
13624 as_bad (_("Bad char = '%c'\n"), *args
);
13629 /* Args don't match. */
13631 insn_error
= _("Illegal operands");
13632 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13637 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13639 gas_assert (firstinsn
);
13640 need_delay_slot_ok
= FALSE
;
13649 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13651 /* This routine assembles an instruction into its binary format when
13652 assembling for the mips16. As a side effect, it sets one of the
13653 global variables imm_reloc or offset_reloc to the type of relocation
13654 to do if one of the operands is an address expression. It also sets
13655 forced_insn_length to the resulting instruction size in bytes if the
13656 user explicitly requested a small or extended instruction. */
13659 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13663 struct mips_opcode
*insn
;
13665 unsigned int regno
;
13666 unsigned int lastregno
= 0;
13672 forced_insn_length
= 0;
13674 for (s
= str
; ISLOWER (*s
); ++s
)
13686 if (s
[1] == 't' && s
[2] == ' ')
13689 forced_insn_length
= 2;
13693 else if (s
[1] == 'e' && s
[2] == ' ')
13696 forced_insn_length
= 4;
13700 /* Fall through. */
13702 insn_error
= _("unknown opcode");
13706 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13707 forced_insn_length
= 2;
13709 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13711 insn_error
= _("unrecognized opcode");
13720 gas_assert (strcmp (insn
->name
, str
) == 0);
13722 ok
= is_opcode_valid_16 (insn
);
13725 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13726 && strcmp (insn
->name
, insn
[1].name
) == 0)
13735 static char buf
[100];
13737 _("Opcode not supported on this processor: %s (%s)"),
13738 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13739 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13746 create_insn (ip
, insn
);
13747 imm_expr
.X_op
= O_absent
;
13748 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13749 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13750 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13751 imm2_expr
.X_op
= O_absent
;
13752 offset_expr
.X_op
= O_absent
;
13753 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13754 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13755 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13756 for (args
= insn
->args
; 1; ++args
)
13763 /* In this switch statement we call break if we did not find
13764 a match, continue if we did find a match, or return if we
13775 /* Stuff the immediate value in now, if we can. */
13776 if (imm_expr
.X_op
== O_constant
13777 && *imm_reloc
> BFD_RELOC_UNUSED
13778 && insn
->pinfo
!= INSN_MACRO
13779 && calculate_reloc (*offset_reloc
,
13780 imm_expr
.X_add_number
, &value
))
13782 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13783 *offset_reloc
, value
, forced_insn_length
,
13785 imm_expr
.X_op
= O_absent
;
13786 *imm_reloc
= BFD_RELOC_UNUSED
;
13787 *offset_reloc
= BFD_RELOC_UNUSED
;
13801 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13804 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13820 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13822 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13826 /* Fall through. */
13837 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13839 if (c
== 'v' || c
== 'w')
13842 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13844 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13855 if (c
== 'v' || c
== 'w')
13857 regno
= mips16_to_32_reg_map
[lastregno
];
13871 regno
= mips32_to_16_reg_map
[regno
];
13876 regno
= ILLEGAL_REG
;
13881 regno
= ILLEGAL_REG
;
13886 regno
= ILLEGAL_REG
;
13891 if (regno
== AT
&& mips_opts
.at
)
13893 if (mips_opts
.at
== ATREG
)
13894 as_warn (_("used $at without \".set noat\""));
13896 as_warn (_("used $%u with \".set at=$%u\""),
13897 regno
, mips_opts
.at
);
13905 if (regno
== ILLEGAL_REG
)
13912 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13916 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13919 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13922 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13928 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13931 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13932 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13942 if (strncmp (s
, "$pc", 3) == 0)
13959 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13962 if (imm_expr
.X_op
!= O_constant
)
13964 forced_insn_length
= 4;
13965 ip
->insn_opcode
|= MIPS16_EXTEND
;
13969 /* We need to relax this instruction. */
13970 *offset_reloc
= *imm_reloc
;
13971 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13976 *imm_reloc
= BFD_RELOC_UNUSED
;
13977 /* Fall through. */
13984 my_getExpression (&imm_expr
, s
);
13985 if (imm_expr
.X_op
== O_register
)
13987 /* What we thought was an expression turned out to
13990 if (s
[0] == '(' && args
[1] == '(')
13992 /* It looks like the expression was omitted
13993 before a register indirection, which means
13994 that the expression is implicitly zero. We
13995 still set up imm_expr, so that we handle
13996 explicit extensions correctly. */
13997 imm_expr
.X_op
= O_constant
;
13998 imm_expr
.X_add_number
= 0;
13999 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14006 /* We need to relax this instruction. */
14007 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14016 /* We use offset_reloc rather than imm_reloc for the PC
14017 relative operands. This lets macros with both
14018 immediate and address operands work correctly. */
14019 my_getExpression (&offset_expr
, s
);
14021 if (offset_expr
.X_op
== O_register
)
14024 /* We need to relax this instruction. */
14025 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14029 case '6': /* break code */
14030 my_getExpression (&imm_expr
, s
);
14031 check_absolute_expr (ip
, &imm_expr
);
14032 if ((unsigned long) imm_expr
.X_add_number
> 63)
14033 as_warn (_("Invalid value for `%s' (%lu)"),
14035 (unsigned long) imm_expr
.X_add_number
);
14036 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
14037 imm_expr
.X_op
= O_absent
;
14041 case 'a': /* 26 bit address */
14042 my_getExpression (&offset_expr
, s
);
14044 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
14045 ip
->insn_opcode
<<= 16;
14048 case 'l': /* register list for entry macro */
14049 case 'L': /* register list for exit macro */
14059 unsigned int freg
, reg1
, reg2
;
14061 while (*s
== ' ' || *s
== ',')
14063 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14065 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
14069 as_bad (_("can't parse register list"));
14079 if (!reg_lookup (&s
, freg
? RTYPE_FPU
14080 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
14082 as_bad (_("invalid register list"));
14086 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
14088 mask
&= ~ (7 << 3);
14091 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
14093 mask
&= ~ (7 << 3);
14096 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
14097 mask
|= (reg2
- 3) << 3;
14098 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
14099 mask
|= (reg2
- 15) << 1;
14100 else if (reg1
== RA
&& reg2
== RA
)
14104 as_bad (_("invalid register list"));
14108 /* The mask is filled in in the opcode table for the
14109 benefit of the disassembler. We remove it before
14110 applying the actual mask. */
14111 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
14112 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
14116 case 'm': /* Register list for save insn. */
14117 case 'M': /* Register list for restore insn. */
14119 int opcode
= ip
->insn_opcode
;
14120 int framesz
= 0, seen_framesz
= 0;
14121 int nargs
= 0, statics
= 0, sregs
= 0;
14125 unsigned int reg1
, reg2
;
14127 SKIP_SPACE_TABS (s
);
14130 SKIP_SPACE_TABS (s
);
14132 my_getExpression (&imm_expr
, s
);
14133 if (imm_expr
.X_op
== O_constant
)
14135 /* Handle the frame size. */
14138 as_bad (_("more than one frame size in list"));
14142 framesz
= imm_expr
.X_add_number
;
14143 imm_expr
.X_op
= O_absent
;
14148 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14150 as_bad (_("can't parse register list"));
14162 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
14165 as_bad (_("can't parse register list"));
14170 while (reg1
<= reg2
)
14172 if (reg1
>= 4 && reg1
<= 7)
14176 nargs
|= 1 << (reg1
- 4);
14178 /* statics $a0-$a3 */
14179 statics
|= 1 << (reg1
- 4);
14181 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
14184 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
14186 else if (reg1
== 31)
14188 /* Add $ra to insn. */
14193 as_bad (_("unexpected register in list"));
14201 /* Encode args/statics combination. */
14202 if (nargs
& statics
)
14203 as_bad (_("arg/static registers overlap"));
14204 else if (nargs
== 0xf)
14205 /* All $a0-$a3 are args. */
14206 opcode
|= MIPS16_ALL_ARGS
<< 16;
14207 else if (statics
== 0xf)
14208 /* All $a0-$a3 are statics. */
14209 opcode
|= MIPS16_ALL_STATICS
<< 16;
14212 int narg
= 0, nstat
= 0;
14214 /* Count arg registers. */
14215 while (nargs
& 0x1)
14221 as_bad (_("invalid arg register list"));
14223 /* Count static registers. */
14224 while (statics
& 0x8)
14226 statics
= (statics
<< 1) & 0xf;
14230 as_bad (_("invalid static register list"));
14232 /* Encode args/statics. */
14233 opcode
|= ((narg
<< 2) | nstat
) << 16;
14236 /* Encode $s0/$s1. */
14237 if (sregs
& (1 << 0)) /* $s0 */
14239 if (sregs
& (1 << 1)) /* $s1 */
14245 /* Count regs $s2-$s8. */
14253 as_bad (_("invalid static register list"));
14254 /* Encode $s2-$s8. */
14255 opcode
|= nsreg
<< 24;
14258 /* Encode frame size. */
14260 as_bad (_("missing frame size"));
14261 else if ((framesz
& 7) != 0 || framesz
< 0
14262 || framesz
> 0xff * 8)
14263 as_bad (_("invalid frame size"));
14264 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14267 opcode
|= (((framesz
& 0xf0) << 16)
14268 | (framesz
& 0x0f));
14271 /* Finally build the instruction. */
14272 if ((opcode
>> 16) != 0 || framesz
== 0)
14273 opcode
|= MIPS16_EXTEND
;
14274 ip
->insn_opcode
= opcode
;
14278 case 'e': /* extend code */
14279 my_getExpression (&imm_expr
, s
);
14280 check_absolute_expr (ip
, &imm_expr
);
14281 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14283 as_warn (_("Invalid value for `%s' (%lu)"),
14285 (unsigned long) imm_expr
.X_add_number
);
14286 imm_expr
.X_add_number
&= 0x7ff;
14288 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14289 imm_expr
.X_op
= O_absent
;
14299 /* Args don't match. */
14300 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14301 strcmp (insn
->name
, insn
[1].name
) == 0)
14308 insn_error
= _("illegal operands");
14314 /* This structure holds information we know about a mips16 immediate
14317 struct mips16_immed_operand
14319 /* The type code used in the argument string in the opcode table. */
14321 /* The number of bits in the short form of the opcode. */
14323 /* The number of bits in the extended form of the opcode. */
14325 /* The amount by which the short form is shifted when it is used;
14326 for example, the sw instruction has a shift count of 2. */
14328 /* The amount by which the short form is shifted when it is stored
14329 into the instruction code. */
14331 /* Non-zero if the short form is unsigned. */
14333 /* Non-zero if the extended form is unsigned. */
14335 /* Non-zero if the value is PC relative. */
14339 /* The mips16 immediate operand types. */
14341 static const struct mips16_immed_operand mips16_immed_operands
[] =
14343 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14344 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14345 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14346 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14347 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14348 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14349 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14350 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14351 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14352 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14353 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14354 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14355 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14356 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14357 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14358 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14359 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14360 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14361 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14362 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14363 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14366 #define MIPS16_NUM_IMMED \
14367 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14369 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14370 NBITS is the number of significant bits in VAL. */
14372 static unsigned long
14373 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14378 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14381 else if (nbits
== 15)
14383 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14388 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14391 return (extval
<< 16) | val
;
14394 /* Install immediate value VAL into MIPS16 instruction *INSN,
14395 extending it if necessary. The instruction in *INSN may
14396 already be extended.
14398 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14399 if none. In the former case, VAL is a 16-bit number with no
14400 defined signedness.
14402 TYPE is the type of the immediate field. USER_INSN_LENGTH
14403 is the length that the user requested, or 0 if none. */
14406 mips16_immed (char *file
, unsigned int line
, int type
,
14407 bfd_reloc_code_real_type reloc
, offsetT val
,
14408 unsigned int user_insn_length
, unsigned long *insn
)
14410 const struct mips16_immed_operand
*op
;
14411 int mintiny
, maxtiny
;
14413 op
= mips16_immed_operands
;
14414 while (op
->type
!= type
)
14417 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14422 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14425 maxtiny
= 1 << op
->nbits
;
14430 maxtiny
= (1 << op
->nbits
) - 1;
14432 if (reloc
!= BFD_RELOC_UNUSED
)
14437 mintiny
= - (1 << (op
->nbits
- 1));
14438 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14439 if (reloc
!= BFD_RELOC_UNUSED
)
14440 val
= SEXT_16BIT (val
);
14443 /* Branch offsets have an implicit 0 in the lowest bit. */
14444 if (type
== 'p' || type
== 'q')
14447 if ((val
& ((1 << op
->shift
) - 1)) != 0
14448 || val
< (mintiny
<< op
->shift
)
14449 || val
> (maxtiny
<< op
->shift
))
14451 /* We need an extended instruction. */
14452 if (user_insn_length
== 2)
14453 as_bad_where (file
, line
, _("invalid unextended operand value"));
14455 *insn
|= MIPS16_EXTEND
;
14457 else if (user_insn_length
== 4)
14459 /* The operand doesn't force an unextended instruction to be extended.
14460 Warn if the user wanted an extended instruction anyway. */
14461 *insn
|= MIPS16_EXTEND
;
14462 as_warn_where (file
, line
,
14463 _("extended operand requested but not required"));
14466 if (mips16_opcode_length (*insn
) == 2)
14470 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14471 insnval
<<= op
->op_shift
;
14476 long minext
, maxext
;
14478 if (reloc
== BFD_RELOC_UNUSED
)
14483 maxext
= (1 << op
->extbits
) - 1;
14487 minext
= - (1 << (op
->extbits
- 1));
14488 maxext
= (1 << (op
->extbits
- 1)) - 1;
14490 if (val
< minext
|| val
> maxext
)
14491 as_bad_where (file
, line
,
14492 _("operand value out of range for instruction"));
14495 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14499 struct percent_op_match
14502 bfd_reloc_code_real_type reloc
;
14505 static const struct percent_op_match mips_percent_op
[] =
14507 {"%lo", BFD_RELOC_LO16
},
14509 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14510 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14511 {"%call16", BFD_RELOC_MIPS_CALL16
},
14512 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14513 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14514 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14515 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14516 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14517 {"%got", BFD_RELOC_MIPS_GOT16
},
14518 {"%gp_rel", BFD_RELOC_GPREL16
},
14519 {"%half", BFD_RELOC_16
},
14520 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14521 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14522 {"%neg", BFD_RELOC_MIPS_SUB
},
14523 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14524 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14525 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14526 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14527 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14528 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14529 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14531 {"%hi", BFD_RELOC_HI16_S
}
14534 static const struct percent_op_match mips16_percent_op
[] =
14536 {"%lo", BFD_RELOC_MIPS16_LO16
},
14537 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14538 {"%got", BFD_RELOC_MIPS16_GOT16
},
14539 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14540 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14541 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14542 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14543 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14544 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14545 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14546 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14547 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14551 /* Return true if *STR points to a relocation operator. When returning true,
14552 move *STR over the operator and store its relocation code in *RELOC.
14553 Leave both *STR and *RELOC alone when returning false. */
14556 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14558 const struct percent_op_match
*percent_op
;
14561 if (mips_opts
.mips16
)
14563 percent_op
= mips16_percent_op
;
14564 limit
= ARRAY_SIZE (mips16_percent_op
);
14568 percent_op
= mips_percent_op
;
14569 limit
= ARRAY_SIZE (mips_percent_op
);
14572 for (i
= 0; i
< limit
; i
++)
14573 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14575 int len
= strlen (percent_op
[i
].str
);
14577 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14580 *str
+= strlen (percent_op
[i
].str
);
14581 *reloc
= percent_op
[i
].reloc
;
14583 /* Check whether the output BFD supports this relocation.
14584 If not, issue an error and fall back on something safe. */
14585 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14587 as_bad (_("relocation %s isn't supported by the current ABI"),
14588 percent_op
[i
].str
);
14589 *reloc
= BFD_RELOC_UNUSED
;
14597 /* Parse string STR as a 16-bit relocatable operand. Store the
14598 expression in *EP and the relocations in the array starting
14599 at RELOC. Return the number of relocation operators used.
14601 On exit, EXPR_END points to the first character after the expression. */
14604 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14607 bfd_reloc_code_real_type reversed_reloc
[3];
14608 size_t reloc_index
, i
;
14609 int crux_depth
, str_depth
;
14612 /* Search for the start of the main expression, recoding relocations
14613 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14614 of the main expression and with CRUX_DEPTH containing the number
14615 of open brackets at that point. */
14622 crux_depth
= str_depth
;
14624 /* Skip over whitespace and brackets, keeping count of the number
14626 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14631 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14632 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14634 my_getExpression (ep
, crux
);
14637 /* Match every open bracket. */
14638 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14642 if (crux_depth
> 0)
14643 as_bad (_("unclosed '('"));
14647 if (reloc_index
!= 0)
14649 prev_reloc_op_frag
= frag_now
;
14650 for (i
= 0; i
< reloc_index
; i
++)
14651 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14654 return reloc_index
;
14658 my_getExpression (expressionS
*ep
, char *str
)
14662 save_in
= input_line_pointer
;
14663 input_line_pointer
= str
;
14665 expr_end
= input_line_pointer
;
14666 input_line_pointer
= save_in
;
14670 md_atof (int type
, char *litP
, int *sizeP
)
14672 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14676 md_number_to_chars (char *buf
, valueT val
, int n
)
14678 if (target_big_endian
)
14679 number_to_chars_bigendian (buf
, val
, n
);
14681 number_to_chars_littleendian (buf
, val
, n
);
14685 static int support_64bit_objects(void)
14687 const char **list
, **l
;
14690 list
= bfd_target_list ();
14691 for (l
= list
; *l
!= NULL
; l
++)
14692 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14693 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14695 yes
= (*l
!= NULL
);
14699 #endif /* OBJ_ELF */
14701 const char *md_shortopts
= "O::g::G:";
14705 OPTION_MARCH
= OPTION_MD_BASE
,
14729 OPTION_NO_SMARTMIPS
,
14735 OPTION_NO_MICROMIPS
,
14738 OPTION_COMPAT_ARCH_BASE
,
14747 OPTION_M7000_HILO_FIX
,
14748 OPTION_MNO_7000_HILO_FIX
,
14751 OPTION_FIX_LOONGSON2F_JUMP
,
14752 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14753 OPTION_FIX_LOONGSON2F_NOP
,
14754 OPTION_NO_FIX_LOONGSON2F_NOP
,
14756 OPTION_NO_FIX_VR4120
,
14758 OPTION_NO_FIX_VR4130
,
14759 OPTION_FIX_CN63XXP1
,
14760 OPTION_NO_FIX_CN63XXP1
,
14767 OPTION_CONSTRUCT_FLOATS
,
14768 OPTION_NO_CONSTRUCT_FLOATS
,
14771 OPTION_RELAX_BRANCH
,
14772 OPTION_NO_RELAX_BRANCH
,
14779 OPTION_SINGLE_FLOAT
,
14780 OPTION_DOUBLE_FLOAT
,
14783 OPTION_CALL_SHARED
,
14784 OPTION_CALL_NONPIC
,
14794 OPTION_MVXWORKS_PIC
,
14795 #endif /* OBJ_ELF */
14799 struct option md_longopts
[] =
14801 /* Options which specify architecture. */
14802 {"march", required_argument
, NULL
, OPTION_MARCH
},
14803 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14804 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14805 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14806 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14807 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14808 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14809 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14810 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14811 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14812 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14813 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14815 /* Options which specify Application Specific Extensions (ASEs). */
14816 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14817 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14818 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14819 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14820 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14821 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14822 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14823 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14824 {"mmt", no_argument
, NULL
, OPTION_MT
},
14825 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14826 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14827 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14828 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14829 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14830 {"meva", no_argument
, NULL
, OPTION_EVA
},
14831 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
14832 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14833 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14834 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14835 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14836 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
14837 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
14839 /* Old-style architecture options. Don't add more of these. */
14840 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14841 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14842 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14843 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14844 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14845 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14846 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14847 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14849 /* Options which enable bug fixes. */
14850 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14851 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14852 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14853 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14854 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14855 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14856 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14857 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14858 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14859 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14860 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14861 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14862 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14863 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14864 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14866 /* Miscellaneous options. */
14867 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14868 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14869 {"break", no_argument
, NULL
, OPTION_BREAK
},
14870 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14871 {"EB", no_argument
, NULL
, OPTION_EB
},
14872 {"EL", no_argument
, NULL
, OPTION_EL
},
14873 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14874 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14875 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14876 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14877 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14878 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14879 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14880 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14881 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14882 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14883 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14884 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14885 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14886 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14887 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14888 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14890 /* Strictly speaking this next option is ELF specific,
14891 but we allow it for other ports as well in order to
14892 make testing easier. */
14893 {"32", no_argument
, NULL
, OPTION_32
},
14895 /* ELF-specific options. */
14897 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14898 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14899 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14900 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14901 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14902 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14903 {"n32", no_argument
, NULL
, OPTION_N32
},
14904 {"64", no_argument
, NULL
, OPTION_64
},
14905 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14906 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14907 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14908 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14909 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14910 #endif /* OBJ_ELF */
14912 {NULL
, no_argument
, NULL
, 0}
14914 size_t md_longopts_size
= sizeof (md_longopts
);
14916 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14917 NEW_VALUE. Warn if another value was already specified. Note:
14918 we have to defer parsing the -march and -mtune arguments in order
14919 to handle 'from-abi' correctly, since the ABI might be specified
14920 in a later argument. */
14923 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14925 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14926 as_warn (_("A different %s was already specified, is now %s"),
14927 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14930 *string_ptr
= new_value
;
14934 md_parse_option (int c
, char *arg
)
14938 case OPTION_CONSTRUCT_FLOATS
:
14939 mips_disable_float_construction
= 0;
14942 case OPTION_NO_CONSTRUCT_FLOATS
:
14943 mips_disable_float_construction
= 1;
14955 target_big_endian
= 1;
14959 target_big_endian
= 0;
14965 else if (arg
[0] == '0')
14967 else if (arg
[0] == '1')
14977 mips_debug
= atoi (arg
);
14981 file_mips_isa
= ISA_MIPS1
;
14985 file_mips_isa
= ISA_MIPS2
;
14989 file_mips_isa
= ISA_MIPS3
;
14993 file_mips_isa
= ISA_MIPS4
;
14997 file_mips_isa
= ISA_MIPS5
;
15000 case OPTION_MIPS32
:
15001 file_mips_isa
= ISA_MIPS32
;
15004 case OPTION_MIPS32R2
:
15005 file_mips_isa
= ISA_MIPS32R2
;
15008 case OPTION_MIPS64R2
:
15009 file_mips_isa
= ISA_MIPS64R2
;
15012 case OPTION_MIPS64
:
15013 file_mips_isa
= ISA_MIPS64
;
15017 mips_set_option_string (&mips_tune_string
, arg
);
15021 mips_set_option_string (&mips_arch_string
, arg
);
15025 mips_set_option_string (&mips_arch_string
, "4650");
15026 mips_set_option_string (&mips_tune_string
, "4650");
15029 case OPTION_NO_M4650
:
15033 mips_set_option_string (&mips_arch_string
, "4010");
15034 mips_set_option_string (&mips_tune_string
, "4010");
15037 case OPTION_NO_M4010
:
15041 mips_set_option_string (&mips_arch_string
, "4100");
15042 mips_set_option_string (&mips_tune_string
, "4100");
15045 case OPTION_NO_M4100
:
15049 mips_set_option_string (&mips_arch_string
, "3900");
15050 mips_set_option_string (&mips_tune_string
, "3900");
15053 case OPTION_NO_M3900
:
15057 mips_opts
.ase_mdmx
= 1;
15060 case OPTION_NO_MDMX
:
15061 mips_opts
.ase_mdmx
= 0;
15065 mips_opts
.ase_dsp
= 1;
15066 mips_opts
.ase_dspr2
= 0;
15069 case OPTION_NO_DSP
:
15070 mips_opts
.ase_dsp
= 0;
15071 mips_opts
.ase_dspr2
= 0;
15075 mips_opts
.ase_dspr2
= 1;
15076 mips_opts
.ase_dsp
= 1;
15079 case OPTION_NO_DSPR2
:
15080 mips_opts
.ase_dspr2
= 0;
15081 mips_opts
.ase_dsp
= 0;
15085 mips_opts
.ase_eva
= 1;
15088 case OPTION_NO_EVA
:
15089 mips_opts
.ase_eva
= 0;
15093 mips_opts
.ase_mt
= 1;
15097 mips_opts
.ase_mt
= 0;
15101 mips_opts
.ase_mcu
= 1;
15104 case OPTION_NO_MCU
:
15105 mips_opts
.ase_mcu
= 0;
15108 case OPTION_MICROMIPS
:
15109 if (mips_opts
.mips16
== 1)
15111 as_bad (_("-mmicromips cannot be used with -mips16"));
15114 mips_opts
.micromips
= 1;
15115 mips_no_prev_insn ();
15118 case OPTION_NO_MICROMIPS
:
15119 mips_opts
.micromips
= 0;
15120 mips_no_prev_insn ();
15124 mips_opts
.ase_virt
= 1;
15127 case OPTION_NO_VIRT
:
15128 mips_opts
.ase_virt
= 0;
15131 case OPTION_MIPS16
:
15132 if (mips_opts
.micromips
== 1)
15134 as_bad (_("-mips16 cannot be used with -micromips"));
15137 mips_opts
.mips16
= 1;
15138 mips_no_prev_insn ();
15141 case OPTION_NO_MIPS16
:
15142 mips_opts
.mips16
= 0;
15143 mips_no_prev_insn ();
15146 case OPTION_MIPS3D
:
15147 mips_opts
.ase_mips3d
= 1;
15150 case OPTION_NO_MIPS3D
:
15151 mips_opts
.ase_mips3d
= 0;
15154 case OPTION_SMARTMIPS
:
15155 mips_opts
.ase_smartmips
= 1;
15158 case OPTION_NO_SMARTMIPS
:
15159 mips_opts
.ase_smartmips
= 0;
15162 case OPTION_FIX_24K
:
15166 case OPTION_NO_FIX_24K
:
15170 case OPTION_FIX_LOONGSON2F_JUMP
:
15171 mips_fix_loongson2f_jump
= TRUE
;
15174 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
15175 mips_fix_loongson2f_jump
= FALSE
;
15178 case OPTION_FIX_LOONGSON2F_NOP
:
15179 mips_fix_loongson2f_nop
= TRUE
;
15182 case OPTION_NO_FIX_LOONGSON2F_NOP
:
15183 mips_fix_loongson2f_nop
= FALSE
;
15186 case OPTION_FIX_VR4120
:
15187 mips_fix_vr4120
= 1;
15190 case OPTION_NO_FIX_VR4120
:
15191 mips_fix_vr4120
= 0;
15194 case OPTION_FIX_VR4130
:
15195 mips_fix_vr4130
= 1;
15198 case OPTION_NO_FIX_VR4130
:
15199 mips_fix_vr4130
= 0;
15202 case OPTION_FIX_CN63XXP1
:
15203 mips_fix_cn63xxp1
= TRUE
;
15206 case OPTION_NO_FIX_CN63XXP1
:
15207 mips_fix_cn63xxp1
= FALSE
;
15210 case OPTION_RELAX_BRANCH
:
15211 mips_relax_branch
= 1;
15214 case OPTION_NO_RELAX_BRANCH
:
15215 mips_relax_branch
= 0;
15218 case OPTION_MSHARED
:
15219 mips_in_shared
= TRUE
;
15222 case OPTION_MNO_SHARED
:
15223 mips_in_shared
= FALSE
;
15226 case OPTION_MSYM32
:
15227 mips_opts
.sym32
= TRUE
;
15230 case OPTION_MNO_SYM32
:
15231 mips_opts
.sym32
= FALSE
;
15235 /* When generating ELF code, we permit -KPIC and -call_shared to
15236 select SVR4_PIC, and -non_shared to select no PIC. This is
15237 intended to be compatible with Irix 5. */
15238 case OPTION_CALL_SHARED
:
15241 as_bad (_("-call_shared is supported only for ELF format"));
15244 mips_pic
= SVR4_PIC
;
15245 mips_abicalls
= TRUE
;
15248 case OPTION_CALL_NONPIC
:
15251 as_bad (_("-call_nonpic is supported only for ELF format"));
15255 mips_abicalls
= TRUE
;
15258 case OPTION_NON_SHARED
:
15261 as_bad (_("-non_shared is supported only for ELF format"));
15265 mips_abicalls
= FALSE
;
15268 /* The -xgot option tells the assembler to use 32 bit offsets
15269 when accessing the got in SVR4_PIC mode. It is for Irix
15274 #endif /* OBJ_ELF */
15277 g_switch_value
= atoi (arg
);
15281 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15285 mips_abi
= O32_ABI
;
15286 /* We silently ignore -32 for non-ELF targets. This greatly
15287 simplifies the construction of the MIPS GAS test cases. */
15294 as_bad (_("-n32 is supported for ELF format only"));
15297 mips_abi
= N32_ABI
;
15303 as_bad (_("-64 is supported for ELF format only"));
15306 mips_abi
= N64_ABI
;
15307 if (!support_64bit_objects())
15308 as_fatal (_("No compiled in support for 64 bit object file format"));
15310 #endif /* OBJ_ELF */
15313 file_mips_gp32
= 1;
15317 file_mips_gp32
= 0;
15321 file_mips_fp32
= 1;
15325 file_mips_fp32
= 0;
15328 case OPTION_SINGLE_FLOAT
:
15329 file_mips_single_float
= 1;
15332 case OPTION_DOUBLE_FLOAT
:
15333 file_mips_single_float
= 0;
15336 case OPTION_SOFT_FLOAT
:
15337 file_mips_soft_float
= 1;
15340 case OPTION_HARD_FLOAT
:
15341 file_mips_soft_float
= 0;
15348 as_bad (_("-mabi is supported for ELF format only"));
15351 if (strcmp (arg
, "32") == 0)
15352 mips_abi
= O32_ABI
;
15353 else if (strcmp (arg
, "o64") == 0)
15354 mips_abi
= O64_ABI
;
15355 else if (strcmp (arg
, "n32") == 0)
15356 mips_abi
= N32_ABI
;
15357 else if (strcmp (arg
, "64") == 0)
15359 mips_abi
= N64_ABI
;
15360 if (! support_64bit_objects())
15361 as_fatal (_("No compiled in support for 64 bit object file "
15364 else if (strcmp (arg
, "eabi") == 0)
15365 mips_abi
= EABI_ABI
;
15368 as_fatal (_("invalid abi -mabi=%s"), arg
);
15372 #endif /* OBJ_ELF */
15374 case OPTION_M7000_HILO_FIX
:
15375 mips_7000_hilo_fix
= TRUE
;
15378 case OPTION_MNO_7000_HILO_FIX
:
15379 mips_7000_hilo_fix
= FALSE
;
15383 case OPTION_MDEBUG
:
15384 mips_flag_mdebug
= TRUE
;
15387 case OPTION_NO_MDEBUG
:
15388 mips_flag_mdebug
= FALSE
;
15392 mips_flag_pdr
= TRUE
;
15395 case OPTION_NO_PDR
:
15396 mips_flag_pdr
= FALSE
;
15399 case OPTION_MVXWORKS_PIC
:
15400 mips_pic
= VXWORKS_PIC
;
15402 #endif /* OBJ_ELF */
15408 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15413 /* Set up globals to generate code for the ISA or processor
15414 described by INFO. */
15417 mips_set_architecture (const struct mips_cpu_info
*info
)
15421 file_mips_arch
= info
->cpu
;
15422 mips_opts
.arch
= info
->cpu
;
15423 mips_opts
.isa
= info
->isa
;
15428 /* Likewise for tuning. */
15431 mips_set_tune (const struct mips_cpu_info
*info
)
15434 mips_tune
= info
->cpu
;
15439 mips_after_parse_args (void)
15441 const struct mips_cpu_info
*arch_info
= 0;
15442 const struct mips_cpu_info
*tune_info
= 0;
15444 /* GP relative stuff not working for PE */
15445 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15447 if (g_switch_seen
&& g_switch_value
!= 0)
15448 as_bad (_("-G not supported in this configuration."));
15449 g_switch_value
= 0;
15452 if (mips_abi
== NO_ABI
)
15453 mips_abi
= MIPS_DEFAULT_ABI
;
15455 /* The following code determines the architecture and register size.
15456 Similar code was added to GCC 3.3 (see override_options() in
15457 config/mips/mips.c). The GAS and GCC code should be kept in sync
15458 as much as possible. */
15460 if (mips_arch_string
!= 0)
15461 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15463 if (file_mips_isa
!= ISA_UNKNOWN
)
15465 /* Handle -mipsN. At this point, file_mips_isa contains the
15466 ISA level specified by -mipsN, while arch_info->isa contains
15467 the -march selection (if any). */
15468 if (arch_info
!= 0)
15470 /* -march takes precedence over -mipsN, since it is more descriptive.
15471 There's no harm in specifying both as long as the ISA levels
15473 if (file_mips_isa
!= arch_info
->isa
)
15474 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15475 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15476 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15479 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15482 if (arch_info
== 0)
15484 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15485 gas_assert (arch_info
);
15488 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15489 as_bad (_("-march=%s is not compatible with the selected ABI"),
15492 mips_set_architecture (arch_info
);
15494 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15495 if (mips_tune_string
!= 0)
15496 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15498 if (tune_info
== 0)
15499 mips_set_tune (arch_info
);
15501 mips_set_tune (tune_info
);
15503 if (file_mips_gp32
>= 0)
15505 /* The user specified the size of the integer registers. Make sure
15506 it agrees with the ABI and ISA. */
15507 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15508 as_bad (_("-mgp64 used with a 32-bit processor"));
15509 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15510 as_bad (_("-mgp32 used with a 64-bit ABI"));
15511 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15512 as_bad (_("-mgp64 used with a 32-bit ABI"));
15516 /* Infer the integer register size from the ABI and processor.
15517 Restrict ourselves to 32-bit registers if that's all the
15518 processor has, or if the ABI cannot handle 64-bit registers. */
15519 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15520 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15523 switch (file_mips_fp32
)
15527 /* No user specified float register size.
15528 ??? GAS treats single-float processors as though they had 64-bit
15529 float registers (although it complains when double-precision
15530 instructions are used). As things stand, saying they have 32-bit
15531 registers would lead to spurious "register must be even" messages.
15532 So here we assume float registers are never smaller than the
15534 if (file_mips_gp32
== 0)
15535 /* 64-bit integer registers implies 64-bit float registers. */
15536 file_mips_fp32
= 0;
15537 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15538 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15539 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15540 file_mips_fp32
= 0;
15542 /* 32-bit float registers. */
15543 file_mips_fp32
= 1;
15546 /* The user specified the size of the float registers. Check if it
15547 agrees with the ABI and ISA. */
15549 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15550 as_bad (_("-mfp64 used with a 32-bit fpu"));
15551 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15552 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15553 as_warn (_("-mfp64 used with a 32-bit ABI"));
15556 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15557 as_warn (_("-mfp32 used with a 64-bit ABI"));
15561 /* End of GCC-shared inference code. */
15563 /* This flag is set when we have a 64-bit capable CPU but use only
15564 32-bit wide registers. Note that EABI does not use it. */
15565 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15566 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15567 || mips_abi
== O32_ABI
))
15568 mips_32bitmode
= 1;
15570 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15571 as_bad (_("trap exception not supported at ISA 1"));
15573 /* If the selected architecture includes support for ASEs, enable
15574 generation of code for them. */
15575 if (mips_opts
.mips16
== -1)
15576 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15577 if (mips_opts
.micromips
== -1)
15578 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15579 if (mips_opts
.ase_mips3d
== -1)
15580 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15581 && file_mips_fp32
== 0) ? 1 : 0;
15582 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15583 as_bad (_("-mfp32 used with -mips3d"));
15585 if (mips_opts
.ase_mdmx
== -1)
15586 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15587 && file_mips_fp32
== 0) ? 1 : 0;
15588 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15589 as_bad (_("-mfp32 used with -mdmx"));
15591 if (mips_opts
.ase_smartmips
== -1)
15592 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15593 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15594 as_warn (_("%s ISA does not support SmartMIPS"),
15595 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15597 if (mips_opts
.ase_dsp
== -1)
15598 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15599 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15600 as_warn (_("%s ISA does not support DSP ASE"),
15601 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15603 if (mips_opts
.ase_dspr2
== -1)
15605 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15606 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15608 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15609 as_warn (_("%s ISA does not support DSP R2 ASE"),
15610 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15612 if (mips_opts
.ase_eva
== -1)
15613 mips_opts
.ase_eva
= (arch_info
->flags
& MIPS_CPU_ASE_EVA
) ? 1 : 0;
15614 if (mips_opts
.ase_eva
&& !ISA_SUPPORTS_EVA_ASE
)
15615 as_warn (_("%s ISA does not support EVA ASE"),
15616 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15618 if (mips_opts
.ase_mt
== -1)
15619 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15620 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15621 as_warn (_("%s ISA does not support MT ASE"),
15622 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15624 if (mips_opts
.ase_mcu
== -1)
15625 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15626 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15627 as_warn (_("%s ISA does not support MCU ASE"),
15628 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15630 if (mips_opts
.ase_virt
== -1)
15631 mips_opts
.ase_virt
= (arch_info
->flags
& MIPS_CPU_ASE_VIRT
) ? 1 : 0;
15632 if (mips_opts
.ase_virt
&& !ISA_SUPPORTS_VIRT_ASE
)
15633 as_warn (_("%s ISA does not support Virtualization ASE"),
15634 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15636 file_mips_isa
= mips_opts
.isa
;
15637 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15638 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15639 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15640 file_ase_dsp
= mips_opts
.ase_dsp
;
15641 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15642 file_ase_eva
= mips_opts
.ase_eva
;
15643 file_ase_mt
= mips_opts
.ase_mt
;
15644 file_ase_virt
= mips_opts
.ase_virt
;
15645 mips_opts
.gp32
= file_mips_gp32
;
15646 mips_opts
.fp32
= file_mips_fp32
;
15647 mips_opts
.soft_float
= file_mips_soft_float
;
15648 mips_opts
.single_float
= file_mips_single_float
;
15650 if (mips_flag_mdebug
< 0)
15652 #ifdef OBJ_MAYBE_ECOFF
15653 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15654 mips_flag_mdebug
= 1;
15656 #endif /* OBJ_MAYBE_ECOFF */
15657 mips_flag_mdebug
= 0;
15662 mips_init_after_args (void)
15664 /* initialize opcodes */
15665 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15666 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15670 md_pcrel_from (fixS
*fixP
)
15672 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15673 switch (fixP
->fx_r_type
)
15675 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15676 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15677 /* Return the address of the delay slot. */
15680 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15681 case BFD_RELOC_MICROMIPS_JMP
:
15682 case BFD_RELOC_16_PCREL_S2
:
15683 case BFD_RELOC_MIPS_JMP
:
15684 /* Return the address of the delay slot. */
15687 case BFD_RELOC_32_PCREL
:
15691 /* We have no relocation type for PC relative MIPS16 instructions. */
15692 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15694 _("PC relative MIPS16 instruction references a different section"));
15699 /* This is called before the symbol table is processed. In order to
15700 work with gcc when using mips-tfile, we must keep all local labels.
15701 However, in other cases, we want to discard them. If we were
15702 called with -g, but we didn't see any debugging information, it may
15703 mean that gcc is smuggling debugging information through to
15704 mips-tfile, in which case we must generate all local labels. */
15707 mips_frob_file_before_adjust (void)
15709 #ifndef NO_ECOFF_DEBUGGING
15710 if (ECOFF_DEBUGGING
15712 && ! ecoff_debugging_seen
)
15713 flag_keep_locals
= 1;
15717 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15718 the corresponding LO16 reloc. This is called before md_apply_fix and
15719 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15720 relocation operators.
15722 For our purposes, a %lo() expression matches a %got() or %hi()
15725 (a) it refers to the same symbol; and
15726 (b) the offset applied in the %lo() expression is no lower than
15727 the offset applied in the %got() or %hi().
15729 (b) allows us to cope with code like:
15732 lh $4,%lo(foo+2)($4)
15734 ...which is legal on RELA targets, and has a well-defined behaviour
15735 if the user knows that adding 2 to "foo" will not induce a carry to
15738 When several %lo()s match a particular %got() or %hi(), we use the
15739 following rules to distinguish them:
15741 (1) %lo()s with smaller offsets are a better match than %lo()s with
15744 (2) %lo()s with no matching %got() or %hi() are better than those
15745 that already have a matching %got() or %hi().
15747 (3) later %lo()s are better than earlier %lo()s.
15749 These rules are applied in order.
15751 (1) means, among other things, that %lo()s with identical offsets are
15752 chosen if they exist.
15754 (2) means that we won't associate several high-part relocations with
15755 the same low-part relocation unless there's no alternative. Having
15756 several high parts for the same low part is a GNU extension; this rule
15757 allows careful users to avoid it.
15759 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15760 with the last high-part relocation being at the front of the list.
15761 It therefore makes sense to choose the last matching low-part
15762 relocation, all other things being equal. It's also easier
15763 to code that way. */
15766 mips_frob_file (void)
15768 struct mips_hi_fixup
*l
;
15769 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15771 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15773 segment_info_type
*seginfo
;
15774 bfd_boolean matched_lo_p
;
15775 fixS
**hi_pos
, **lo_pos
, **pos
;
15777 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15779 /* If a GOT16 relocation turns out to be against a global symbol,
15780 there isn't supposed to be a matching LO. Ignore %gots against
15781 constants; we'll report an error for those later. */
15782 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15783 && !(l
->fixp
->fx_addsy
15784 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15787 /* Check quickly whether the next fixup happens to be a matching %lo. */
15788 if (fixup_has_matching_lo_p (l
->fixp
))
15791 seginfo
= seg_info (l
->seg
);
15793 /* Set HI_POS to the position of this relocation in the chain.
15794 Set LO_POS to the position of the chosen low-part relocation.
15795 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15796 relocation that matches an immediately-preceding high-part
15800 matched_lo_p
= FALSE
;
15801 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15803 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15805 if (*pos
== l
->fixp
)
15808 if ((*pos
)->fx_r_type
== looking_for_rtype
15809 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15810 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15812 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15814 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15817 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15818 && fixup_has_matching_lo_p (*pos
));
15821 /* If we found a match, remove the high-part relocation from its
15822 current position and insert it before the low-part relocation.
15823 Make the offsets match so that fixup_has_matching_lo_p()
15826 We don't warn about unmatched high-part relocations since some
15827 versions of gcc have been known to emit dead "lui ...%hi(...)"
15829 if (lo_pos
!= NULL
)
15831 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15832 if (l
->fixp
->fx_next
!= *lo_pos
)
15834 *hi_pos
= l
->fixp
->fx_next
;
15835 l
->fixp
->fx_next
= *lo_pos
;
15843 mips_force_relocation (fixS
*fixp
)
15845 if (generic_force_reloc (fixp
))
15848 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15849 so that the linker relaxation can update targets. */
15850 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15851 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15852 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15858 /* Read the instruction associated with RELOC from BUF. */
15860 static unsigned int
15861 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15863 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15864 return read_compressed_insn (buf
, 4);
15866 return read_insn (buf
);
15869 /* Write instruction INSN to BUF, given that it has been relocated
15873 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15874 unsigned long insn
)
15876 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15877 write_compressed_insn (buf
, insn
, 4);
15879 write_insn (buf
, insn
);
15882 /* Apply a fixup to the object file. */
15885 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15888 unsigned long insn
;
15889 reloc_howto_type
*howto
;
15891 /* We ignore generic BFD relocations we don't know about. */
15892 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15896 gas_assert (fixP
->fx_size
== 2
15897 || fixP
->fx_size
== 4
15898 || fixP
->fx_r_type
== BFD_RELOC_16
15899 || fixP
->fx_r_type
== BFD_RELOC_64
15900 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15901 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15902 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15903 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15904 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15905 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15907 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15909 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15910 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15911 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15912 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
15913 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
15915 /* Don't treat parts of a composite relocation as done. There are two
15918 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15919 should nevertheless be emitted if the first part is.
15921 (2) In normal usage, composite relocations are never assembly-time
15922 constants. The easiest way of dealing with the pathological
15923 exceptions is to generate a relocation against STN_UNDEF and
15924 leave everything up to the linker. */
15925 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15928 switch (fixP
->fx_r_type
)
15930 case BFD_RELOC_MIPS_TLS_GD
:
15931 case BFD_RELOC_MIPS_TLS_LDM
:
15932 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15933 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15934 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15935 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15936 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15937 case BFD_RELOC_MIPS_TLS_TPREL32
:
15938 case BFD_RELOC_MIPS_TLS_TPREL64
:
15939 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15940 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15941 case BFD_RELOC_MICROMIPS_TLS_GD
:
15942 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15943 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15944 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15945 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15946 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15947 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15948 case BFD_RELOC_MIPS16_TLS_GD
:
15949 case BFD_RELOC_MIPS16_TLS_LDM
:
15950 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15951 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15952 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15953 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15954 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15955 if (!fixP
->fx_addsy
)
15957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15958 _("TLS relocation against a constant"));
15961 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15964 case BFD_RELOC_MIPS_JMP
:
15965 case BFD_RELOC_MIPS_SHIFT5
:
15966 case BFD_RELOC_MIPS_SHIFT6
:
15967 case BFD_RELOC_MIPS_GOT_DISP
:
15968 case BFD_RELOC_MIPS_GOT_PAGE
:
15969 case BFD_RELOC_MIPS_GOT_OFST
:
15970 case BFD_RELOC_MIPS_SUB
:
15971 case BFD_RELOC_MIPS_INSERT_A
:
15972 case BFD_RELOC_MIPS_INSERT_B
:
15973 case BFD_RELOC_MIPS_DELETE
:
15974 case BFD_RELOC_MIPS_HIGHEST
:
15975 case BFD_RELOC_MIPS_HIGHER
:
15976 case BFD_RELOC_MIPS_SCN_DISP
:
15977 case BFD_RELOC_MIPS_REL16
:
15978 case BFD_RELOC_MIPS_RELGOT
:
15979 case BFD_RELOC_MIPS_JALR
:
15980 case BFD_RELOC_HI16
:
15981 case BFD_RELOC_HI16_S
:
15982 case BFD_RELOC_LO16
:
15983 case BFD_RELOC_GPREL16
:
15984 case BFD_RELOC_MIPS_LITERAL
:
15985 case BFD_RELOC_MIPS_CALL16
:
15986 case BFD_RELOC_MIPS_GOT16
:
15987 case BFD_RELOC_GPREL32
:
15988 case BFD_RELOC_MIPS_GOT_HI16
:
15989 case BFD_RELOC_MIPS_GOT_LO16
:
15990 case BFD_RELOC_MIPS_CALL_HI16
:
15991 case BFD_RELOC_MIPS_CALL_LO16
:
15992 case BFD_RELOC_MIPS16_GPREL
:
15993 case BFD_RELOC_MIPS16_GOT16
:
15994 case BFD_RELOC_MIPS16_CALL16
:
15995 case BFD_RELOC_MIPS16_HI16
:
15996 case BFD_RELOC_MIPS16_HI16_S
:
15997 case BFD_RELOC_MIPS16_LO16
:
15998 case BFD_RELOC_MIPS16_JMP
:
15999 case BFD_RELOC_MICROMIPS_JMP
:
16000 case BFD_RELOC_MICROMIPS_GOT_DISP
:
16001 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
16002 case BFD_RELOC_MICROMIPS_GOT_OFST
:
16003 case BFD_RELOC_MICROMIPS_SUB
:
16004 case BFD_RELOC_MICROMIPS_HIGHEST
:
16005 case BFD_RELOC_MICROMIPS_HIGHER
:
16006 case BFD_RELOC_MICROMIPS_SCN_DISP
:
16007 case BFD_RELOC_MICROMIPS_JALR
:
16008 case BFD_RELOC_MICROMIPS_HI16
:
16009 case BFD_RELOC_MICROMIPS_HI16_S
:
16010 case BFD_RELOC_MICROMIPS_LO16
:
16011 case BFD_RELOC_MICROMIPS_GPREL16
:
16012 case BFD_RELOC_MICROMIPS_LITERAL
:
16013 case BFD_RELOC_MICROMIPS_CALL16
:
16014 case BFD_RELOC_MICROMIPS_GOT16
:
16015 case BFD_RELOC_MICROMIPS_GOT_HI16
:
16016 case BFD_RELOC_MICROMIPS_GOT_LO16
:
16017 case BFD_RELOC_MICROMIPS_CALL_HI16
:
16018 case BFD_RELOC_MICROMIPS_CALL_LO16
:
16019 case BFD_RELOC_MIPS_EH
:
16024 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
16026 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
16027 if (mips16_reloc_p (fixP
->fx_r_type
))
16028 insn
|= mips16_immed_extend (value
, 16);
16030 insn
|= (value
& 0xffff);
16031 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
16034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16035 _("Unsupported constant in relocation"));
16040 /* This is handled like BFD_RELOC_32, but we output a sign
16041 extended value if we are only 32 bits. */
16044 if (8 <= sizeof (valueT
))
16045 md_number_to_chars (buf
, *valP
, 8);
16050 if ((*valP
& 0x80000000) != 0)
16054 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16055 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16060 case BFD_RELOC_RVA
:
16062 case BFD_RELOC_32_PCREL
:
16064 /* If we are deleting this reloc entry, we must fill in the
16065 value now. This can happen if we have a .word which is not
16066 resolved when it appears but is later defined. */
16068 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16071 case BFD_RELOC_16_PCREL_S2
:
16072 if ((*valP
& 0x3) != 0)
16073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16074 _("Branch to misaligned address (%lx)"), (long) *valP
);
16076 /* We need to save the bits in the instruction since fixup_segment()
16077 might be deleting the relocation entry (i.e., a branch within
16078 the current segment). */
16079 if (! fixP
->fx_done
)
16082 /* Update old instruction data. */
16083 insn
= read_insn (buf
);
16085 if (*valP
+ 0x20000 <= 0x3ffff)
16087 insn
|= (*valP
>> 2) & 0xffff;
16088 write_insn (buf
, insn
);
16090 else if (mips_pic
== NO_PIC
16092 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16093 && (fixP
->fx_frag
->fr_address
16094 < text_section
->vma
+ bfd_get_section_size (text_section
))
16095 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16096 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16097 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16099 /* The branch offset is too large. If this is an
16100 unconditional branch, and we are not generating PIC code,
16101 we can convert it to an absolute jump instruction. */
16102 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16103 insn
= 0x0c000000; /* jal */
16105 insn
= 0x08000000; /* j */
16106 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16108 fixP
->fx_addsy
= section_symbol (text_section
);
16109 *valP
+= md_pcrel_from (fixP
);
16110 write_insn (buf
, insn
);
16114 /* If we got here, we have branch-relaxation disabled,
16115 and there's nothing we can do to fix this instruction
16116 without turning it into a longer sequence. */
16117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16118 _("Branch out of range"));
16122 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16123 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16124 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16125 /* We adjust the offset back to even. */
16126 if ((*valP
& 0x1) != 0)
16129 if (! fixP
->fx_done
)
16132 /* Should never visit here, because we keep the relocation. */
16136 case BFD_RELOC_VTABLE_INHERIT
:
16139 && !S_IS_DEFINED (fixP
->fx_addsy
)
16140 && !S_IS_WEAK (fixP
->fx_addsy
))
16141 S_SET_WEAK (fixP
->fx_addsy
);
16144 case BFD_RELOC_VTABLE_ENTRY
:
16152 /* Remember value for tc_gen_reloc. */
16153 fixP
->fx_addnumber
= *valP
;
16163 name
= input_line_pointer
;
16164 c
= get_symbol_end ();
16165 p
= (symbolS
*) symbol_find_or_make (name
);
16166 *input_line_pointer
= c
;
16170 /* Align the current frag to a given power of two. If a particular
16171 fill byte should be used, FILL points to an integer that contains
16172 that byte, otherwise FILL is null.
16174 This function used to have the comment:
16176 The MIPS assembler also automatically adjusts any preceding label.
16178 The implementation therefore applied the adjustment to a maximum of
16179 one label. However, other label adjustments are applied to batches
16180 of labels, and adjusting just one caused problems when new labels
16181 were added for the sake of debugging or unwind information.
16182 We therefore adjust all preceding labels (given as LABELS) instead. */
16185 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16187 mips_emit_delays ();
16188 mips_record_compressed_mode ();
16189 if (fill
== NULL
&& subseg_text_p (now_seg
))
16190 frag_align_code (to
, 0);
16192 frag_align (to
, fill
? *fill
: 0, 0);
16193 record_alignment (now_seg
, to
);
16194 mips_move_labels (labels
, FALSE
);
16197 /* Align to a given power of two. .align 0 turns off the automatic
16198 alignment used by the data creating pseudo-ops. */
16201 s_align (int x ATTRIBUTE_UNUSED
)
16203 int temp
, fill_value
, *fill_ptr
;
16204 long max_alignment
= 28;
16206 /* o Note that the assembler pulls down any immediately preceding label
16207 to the aligned address.
16208 o It's not documented but auto alignment is reinstated by
16209 a .align pseudo instruction.
16210 o Note also that after auto alignment is turned off the mips assembler
16211 issues an error on attempt to assemble an improperly aligned data item.
16214 temp
= get_absolute_expression ();
16215 if (temp
> max_alignment
)
16216 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
16219 as_warn (_("Alignment negative: 0 assumed."));
16222 if (*input_line_pointer
== ',')
16224 ++input_line_pointer
;
16225 fill_value
= get_absolute_expression ();
16226 fill_ptr
= &fill_value
;
16232 segment_info_type
*si
= seg_info (now_seg
);
16233 struct insn_label_list
*l
= si
->label_list
;
16234 /* Auto alignment should be switched on by next section change. */
16236 mips_align (temp
, fill_ptr
, l
);
16243 demand_empty_rest_of_line ();
16247 s_change_sec (int sec
)
16252 /* The ELF backend needs to know that we are changing sections, so
16253 that .previous works correctly. We could do something like check
16254 for an obj_section_change_hook macro, but that might be confusing
16255 as it would not be appropriate to use it in the section changing
16256 functions in read.c, since obj-elf.c intercepts those. FIXME:
16257 This should be cleaner, somehow. */
16259 obj_elf_section_change_hook ();
16262 mips_emit_delays ();
16273 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16274 demand_empty_rest_of_line ();
16278 seg
= subseg_new (RDATA_SECTION_NAME
,
16279 (subsegT
) get_absolute_expression ());
16282 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16283 | SEC_READONLY
| SEC_RELOC
16285 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16286 record_alignment (seg
, 4);
16288 demand_empty_rest_of_line ();
16292 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16295 bfd_set_section_flags (stdoutput
, seg
,
16296 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16297 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16298 record_alignment (seg
, 4);
16300 demand_empty_rest_of_line ();
16304 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16307 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16308 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16309 record_alignment (seg
, 4);
16311 demand_empty_rest_of_line ();
16319 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16322 char *section_name
;
16327 int section_entry_size
;
16328 int section_alignment
;
16333 section_name
= input_line_pointer
;
16334 c
= get_symbol_end ();
16336 next_c
= *(input_line_pointer
+ 1);
16338 /* Do we have .section Name<,"flags">? */
16339 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16341 /* just after name is now '\0'. */
16342 *input_line_pointer
= c
;
16343 input_line_pointer
= section_name
;
16344 obj_elf_section (ignore
);
16347 input_line_pointer
++;
16349 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16351 section_type
= get_absolute_expression ();
16354 if (*input_line_pointer
++ == ',')
16355 section_flag
= get_absolute_expression ();
16358 if (*input_line_pointer
++ == ',')
16359 section_entry_size
= get_absolute_expression ();
16361 section_entry_size
= 0;
16362 if (*input_line_pointer
++ == ',')
16363 section_alignment
= get_absolute_expression ();
16365 section_alignment
= 0;
16366 /* FIXME: really ignore? */
16367 (void) section_alignment
;
16369 section_name
= xstrdup (section_name
);
16371 /* When using the generic form of .section (as implemented by obj-elf.c),
16372 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16373 traditionally had to fall back on the more common @progbits instead.
16375 There's nothing really harmful in this, since bfd will correct
16376 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16377 means that, for backwards compatibility, the special_section entries
16378 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16380 Even so, we shouldn't force users of the MIPS .section syntax to
16381 incorrectly label the sections as SHT_PROGBITS. The best compromise
16382 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16383 generic type-checking code. */
16384 if (section_type
== SHT_MIPS_DWARF
)
16385 section_type
= SHT_PROGBITS
;
16387 obj_elf_change_section (section_name
, section_type
, section_flag
,
16388 section_entry_size
, 0, 0, 0);
16390 if (now_seg
->name
!= section_name
)
16391 free (section_name
);
16392 #endif /* OBJ_ELF */
16396 mips_enable_auto_align (void)
16402 s_cons (int log_size
)
16404 segment_info_type
*si
= seg_info (now_seg
);
16405 struct insn_label_list
*l
= si
->label_list
;
16407 mips_emit_delays ();
16408 if (log_size
> 0 && auto_align
)
16409 mips_align (log_size
, 0, l
);
16410 cons (1 << log_size
);
16411 mips_clear_insn_labels ();
16415 s_float_cons (int type
)
16417 segment_info_type
*si
= seg_info (now_seg
);
16418 struct insn_label_list
*l
= si
->label_list
;
16420 mips_emit_delays ();
16425 mips_align (3, 0, l
);
16427 mips_align (2, 0, l
);
16431 mips_clear_insn_labels ();
16434 /* Handle .globl. We need to override it because on Irix 5 you are
16437 where foo is an undefined symbol, to mean that foo should be
16438 considered to be the address of a function. */
16441 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16450 name
= input_line_pointer
;
16451 c
= get_symbol_end ();
16452 symbolP
= symbol_find_or_make (name
);
16453 S_SET_EXTERNAL (symbolP
);
16455 *input_line_pointer
= c
;
16456 SKIP_WHITESPACE ();
16458 /* On Irix 5, every global symbol that is not explicitly labelled as
16459 being a function is apparently labelled as being an object. */
16462 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16463 && (*input_line_pointer
!= ','))
16468 secname
= input_line_pointer
;
16469 c
= get_symbol_end ();
16470 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16472 as_bad (_("%s: no such section"), secname
);
16473 *input_line_pointer
= c
;
16475 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16476 flag
= BSF_FUNCTION
;
16479 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16481 c
= *input_line_pointer
;
16484 input_line_pointer
++;
16485 SKIP_WHITESPACE ();
16486 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16492 demand_empty_rest_of_line ();
16496 s_option (int x ATTRIBUTE_UNUSED
)
16501 opt
= input_line_pointer
;
16502 c
= get_symbol_end ();
16506 /* FIXME: What does this mean? */
16508 else if (strncmp (opt
, "pic", 3) == 0)
16512 i
= atoi (opt
+ 3);
16517 mips_pic
= SVR4_PIC
;
16518 mips_abicalls
= TRUE
;
16521 as_bad (_(".option pic%d not supported"), i
);
16523 if (mips_pic
== SVR4_PIC
)
16525 if (g_switch_seen
&& g_switch_value
!= 0)
16526 as_warn (_("-G may not be used with SVR4 PIC code"));
16527 g_switch_value
= 0;
16528 bfd_set_gp_size (stdoutput
, 0);
16532 as_warn (_("Unrecognized option \"%s\""), opt
);
16534 *input_line_pointer
= c
;
16535 demand_empty_rest_of_line ();
16538 /* This structure is used to hold a stack of .set values. */
16540 struct mips_option_stack
16542 struct mips_option_stack
*next
;
16543 struct mips_set_options options
;
16546 static struct mips_option_stack
*mips_opts_stack
;
16548 /* Handle the .set pseudo-op. */
16551 s_mipsset (int x ATTRIBUTE_UNUSED
)
16553 char *name
= input_line_pointer
, ch
;
16555 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16556 ++input_line_pointer
;
16557 ch
= *input_line_pointer
;
16558 *input_line_pointer
= '\0';
16560 if (strcmp (name
, "reorder") == 0)
16562 if (mips_opts
.noreorder
)
16565 else if (strcmp (name
, "noreorder") == 0)
16567 if (!mips_opts
.noreorder
)
16568 start_noreorder ();
16570 else if (strncmp (name
, "at=", 3) == 0)
16572 char *s
= name
+ 3;
16574 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16575 as_bad (_("Unrecognized register name `%s'"), s
);
16577 else if (strcmp (name
, "at") == 0)
16579 mips_opts
.at
= ATREG
;
16581 else if (strcmp (name
, "noat") == 0)
16583 mips_opts
.at
= ZERO
;
16585 else if (strcmp (name
, "macro") == 0)
16587 mips_opts
.warn_about_macros
= 0;
16589 else if (strcmp (name
, "nomacro") == 0)
16591 if (mips_opts
.noreorder
== 0)
16592 as_bad (_("`noreorder' must be set before `nomacro'"));
16593 mips_opts
.warn_about_macros
= 1;
16595 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16597 mips_opts
.nomove
= 0;
16599 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16601 mips_opts
.nomove
= 1;
16603 else if (strcmp (name
, "bopt") == 0)
16605 mips_opts
.nobopt
= 0;
16607 else if (strcmp (name
, "nobopt") == 0)
16609 mips_opts
.nobopt
= 1;
16611 else if (strcmp (name
, "gp=default") == 0)
16612 mips_opts
.gp32
= file_mips_gp32
;
16613 else if (strcmp (name
, "gp=32") == 0)
16614 mips_opts
.gp32
= 1;
16615 else if (strcmp (name
, "gp=64") == 0)
16617 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16618 as_warn (_("%s isa does not support 64-bit registers"),
16619 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16620 mips_opts
.gp32
= 0;
16622 else if (strcmp (name
, "fp=default") == 0)
16623 mips_opts
.fp32
= file_mips_fp32
;
16624 else if (strcmp (name
, "fp=32") == 0)
16625 mips_opts
.fp32
= 1;
16626 else if (strcmp (name
, "fp=64") == 0)
16628 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16629 as_warn (_("%s isa does not support 64-bit floating point registers"),
16630 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16631 mips_opts
.fp32
= 0;
16633 else if (strcmp (name
, "softfloat") == 0)
16634 mips_opts
.soft_float
= 1;
16635 else if (strcmp (name
, "hardfloat") == 0)
16636 mips_opts
.soft_float
= 0;
16637 else if (strcmp (name
, "singlefloat") == 0)
16638 mips_opts
.single_float
= 1;
16639 else if (strcmp (name
, "doublefloat") == 0)
16640 mips_opts
.single_float
= 0;
16641 else if (strcmp (name
, "mips16") == 0
16642 || strcmp (name
, "MIPS-16") == 0)
16644 if (mips_opts
.micromips
== 1)
16645 as_fatal (_("`mips16' cannot be used with `micromips'"));
16646 mips_opts
.mips16
= 1;
16648 else if (strcmp (name
, "nomips16") == 0
16649 || strcmp (name
, "noMIPS-16") == 0)
16650 mips_opts
.mips16
= 0;
16651 else if (strcmp (name
, "micromips") == 0)
16653 if (mips_opts
.mips16
== 1)
16654 as_fatal (_("`micromips' cannot be used with `mips16'"));
16655 mips_opts
.micromips
= 1;
16657 else if (strcmp (name
, "nomicromips") == 0)
16658 mips_opts
.micromips
= 0;
16659 else if (strcmp (name
, "smartmips") == 0)
16661 if (!ISA_SUPPORTS_SMARTMIPS
)
16662 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16663 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16664 mips_opts
.ase_smartmips
= 1;
16666 else if (strcmp (name
, "nosmartmips") == 0)
16667 mips_opts
.ase_smartmips
= 0;
16668 else if (strcmp (name
, "mips3d") == 0)
16669 mips_opts
.ase_mips3d
= 1;
16670 else if (strcmp (name
, "nomips3d") == 0)
16671 mips_opts
.ase_mips3d
= 0;
16672 else if (strcmp (name
, "mdmx") == 0)
16673 mips_opts
.ase_mdmx
= 1;
16674 else if (strcmp (name
, "nomdmx") == 0)
16675 mips_opts
.ase_mdmx
= 0;
16676 else if (strcmp (name
, "dsp") == 0)
16678 if (!ISA_SUPPORTS_DSP_ASE
)
16679 as_warn (_("%s ISA does not support DSP ASE"),
16680 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16681 mips_opts
.ase_dsp
= 1;
16682 mips_opts
.ase_dspr2
= 0;
16684 else if (strcmp (name
, "nodsp") == 0)
16686 mips_opts
.ase_dsp
= 0;
16687 mips_opts
.ase_dspr2
= 0;
16689 else if (strcmp (name
, "dspr2") == 0)
16691 if (!ISA_SUPPORTS_DSPR2_ASE
)
16692 as_warn (_("%s ISA does not support DSP R2 ASE"),
16693 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16694 mips_opts
.ase_dspr2
= 1;
16695 mips_opts
.ase_dsp
= 1;
16697 else if (strcmp (name
, "nodspr2") == 0)
16699 mips_opts
.ase_dspr2
= 0;
16700 mips_opts
.ase_dsp
= 0;
16702 else if (strcmp (name
, "eva") == 0)
16704 if (!ISA_SUPPORTS_EVA_ASE
)
16705 as_warn (_("%s ISA does not support EVA ASE"),
16706 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16707 mips_opts
.ase_eva
= 1;
16709 else if (strcmp (name
, "noeva") == 0)
16710 mips_opts
.ase_eva
= 0;
16711 else if (strcmp (name
, "mt") == 0)
16713 if (!ISA_SUPPORTS_MT_ASE
)
16714 as_warn (_("%s ISA does not support MT ASE"),
16715 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16716 mips_opts
.ase_mt
= 1;
16718 else if (strcmp (name
, "nomt") == 0)
16719 mips_opts
.ase_mt
= 0;
16720 else if (strcmp (name
, "mcu") == 0)
16721 mips_opts
.ase_mcu
= 1;
16722 else if (strcmp (name
, "nomcu") == 0)
16723 mips_opts
.ase_mcu
= 0;
16724 else if (strcmp (name
, "virt") == 0)
16726 if (!ISA_SUPPORTS_VIRT_ASE
)
16727 as_warn (_("%s ISA does not support Virtualization ASE"),
16728 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16729 mips_opts
.ase_virt
= 1;
16731 else if (strcmp (name
, "novirt") == 0)
16732 mips_opts
.ase_virt
= 0;
16733 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16737 /* Permit the user to change the ISA and architecture on the fly.
16738 Needless to say, misuse can cause serious problems. */
16739 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16742 mips_opts
.isa
= file_mips_isa
;
16743 mips_opts
.arch
= file_mips_arch
;
16745 else if (strncmp (name
, "arch=", 5) == 0)
16747 const struct mips_cpu_info
*p
;
16749 p
= mips_parse_cpu("internal use", name
+ 5);
16751 as_bad (_("unknown architecture %s"), name
+ 5);
16754 mips_opts
.arch
= p
->cpu
;
16755 mips_opts
.isa
= p
->isa
;
16758 else if (strncmp (name
, "mips", 4) == 0)
16760 const struct mips_cpu_info
*p
;
16762 p
= mips_parse_cpu("internal use", name
);
16764 as_bad (_("unknown ISA level %s"), name
+ 4);
16767 mips_opts
.arch
= p
->cpu
;
16768 mips_opts
.isa
= p
->isa
;
16772 as_bad (_("unknown ISA or architecture %s"), name
);
16774 switch (mips_opts
.isa
)
16782 mips_opts
.gp32
= 1;
16783 mips_opts
.fp32
= 1;
16790 mips_opts
.gp32
= 0;
16791 if (mips_opts
.arch
== CPU_R5900
)
16793 mips_opts
.fp32
= 1;
16797 mips_opts
.fp32
= 0;
16801 as_bad (_("unknown ISA level %s"), name
+ 4);
16806 mips_opts
.gp32
= file_mips_gp32
;
16807 mips_opts
.fp32
= file_mips_fp32
;
16810 else if (strcmp (name
, "autoextend") == 0)
16811 mips_opts
.noautoextend
= 0;
16812 else if (strcmp (name
, "noautoextend") == 0)
16813 mips_opts
.noautoextend
= 1;
16814 else if (strcmp (name
, "push") == 0)
16816 struct mips_option_stack
*s
;
16818 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16819 s
->next
= mips_opts_stack
;
16820 s
->options
= mips_opts
;
16821 mips_opts_stack
= s
;
16823 else if (strcmp (name
, "pop") == 0)
16825 struct mips_option_stack
*s
;
16827 s
= mips_opts_stack
;
16829 as_bad (_(".set pop with no .set push"));
16832 /* If we're changing the reorder mode we need to handle
16833 delay slots correctly. */
16834 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16835 start_noreorder ();
16836 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16839 mips_opts
= s
->options
;
16840 mips_opts_stack
= s
->next
;
16844 else if (strcmp (name
, "sym32") == 0)
16845 mips_opts
.sym32
= TRUE
;
16846 else if (strcmp (name
, "nosym32") == 0)
16847 mips_opts
.sym32
= FALSE
;
16848 else if (strchr (name
, ','))
16850 /* Generic ".set" directive; use the generic handler. */
16851 *input_line_pointer
= ch
;
16852 input_line_pointer
= name
;
16858 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16860 *input_line_pointer
= ch
;
16861 demand_empty_rest_of_line ();
16864 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16865 .option pic2. It means to generate SVR4 PIC calls. */
16868 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16870 mips_pic
= SVR4_PIC
;
16871 mips_abicalls
= TRUE
;
16873 if (g_switch_seen
&& g_switch_value
!= 0)
16874 as_warn (_("-G may not be used with SVR4 PIC code"));
16875 g_switch_value
= 0;
16877 bfd_set_gp_size (stdoutput
, 0);
16878 demand_empty_rest_of_line ();
16881 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16882 PIC code. It sets the $gp register for the function based on the
16883 function address, which is in the register named in the argument.
16884 This uses a relocation against _gp_disp, which is handled specially
16885 by the linker. The result is:
16886 lui $gp,%hi(_gp_disp)
16887 addiu $gp,$gp,%lo(_gp_disp)
16888 addu $gp,$gp,.cpload argument
16889 The .cpload argument is normally $25 == $t9.
16891 The -mno-shared option changes this to:
16892 lui $gp,%hi(__gnu_local_gp)
16893 addiu $gp,$gp,%lo(__gnu_local_gp)
16894 and the argument is ignored. This saves an instruction, but the
16895 resulting code is not position independent; it uses an absolute
16896 address for __gnu_local_gp. Thus code assembled with -mno-shared
16897 can go into an ordinary executable, but not into a shared library. */
16900 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16906 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16907 .cpload is ignored. */
16908 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16914 if (mips_opts
.mips16
)
16916 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16917 ignore_rest_of_line ();
16921 /* .cpload should be in a .set noreorder section. */
16922 if (mips_opts
.noreorder
== 0)
16923 as_warn (_(".cpload not in noreorder section"));
16925 reg
= tc_get_register (0);
16927 /* If we need to produce a 64-bit address, we are better off using
16928 the default instruction sequence. */
16929 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16931 ex
.X_op
= O_symbol
;
16932 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16934 ex
.X_op_symbol
= NULL
;
16935 ex
.X_add_number
= 0;
16937 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16938 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16940 mips_mark_labels ();
16941 mips_assembling_insn
= TRUE
;
16944 macro_build_lui (&ex
, mips_gp_register
);
16945 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16946 mips_gp_register
, BFD_RELOC_LO16
);
16948 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16949 mips_gp_register
, reg
);
16952 mips_assembling_insn
= FALSE
;
16953 demand_empty_rest_of_line ();
16956 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16957 .cpsetup $reg1, offset|$reg2, label
16959 If offset is given, this results in:
16960 sd $gp, offset($sp)
16961 lui $gp, %hi(%neg(%gp_rel(label)))
16962 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16963 daddu $gp, $gp, $reg1
16965 If $reg2 is given, this results in:
16966 daddu $reg2, $gp, $0
16967 lui $gp, %hi(%neg(%gp_rel(label)))
16968 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16969 daddu $gp, $gp, $reg1
16970 $reg1 is normally $25 == $t9.
16972 The -mno-shared option replaces the last three instructions with
16974 addiu $gp,$gp,%lo(_gp) */
16977 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16979 expressionS ex_off
;
16980 expressionS ex_sym
;
16983 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16984 We also need NewABI support. */
16985 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16991 if (mips_opts
.mips16
)
16993 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16994 ignore_rest_of_line ();
16998 reg1
= tc_get_register (0);
16999 SKIP_WHITESPACE ();
17000 if (*input_line_pointer
!= ',')
17002 as_bad (_("missing argument separator ',' for .cpsetup"));
17006 ++input_line_pointer
;
17007 SKIP_WHITESPACE ();
17008 if (*input_line_pointer
== '$')
17010 mips_cpreturn_register
= tc_get_register (0);
17011 mips_cpreturn_offset
= -1;
17015 mips_cpreturn_offset
= get_absolute_expression ();
17016 mips_cpreturn_register
= -1;
17018 SKIP_WHITESPACE ();
17019 if (*input_line_pointer
!= ',')
17021 as_bad (_("missing argument separator ',' for .cpsetup"));
17025 ++input_line_pointer
;
17026 SKIP_WHITESPACE ();
17027 expression (&ex_sym
);
17029 mips_mark_labels ();
17030 mips_assembling_insn
= TRUE
;
17033 if (mips_cpreturn_register
== -1)
17035 ex_off
.X_op
= O_constant
;
17036 ex_off
.X_add_symbol
= NULL
;
17037 ex_off
.X_op_symbol
= NULL
;
17038 ex_off
.X_add_number
= mips_cpreturn_offset
;
17040 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17041 BFD_RELOC_LO16
, SP
);
17044 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
17045 mips_gp_register
, 0);
17047 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17049 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17050 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17053 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17054 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17055 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17057 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17058 mips_gp_register
, reg1
);
17064 ex
.X_op
= O_symbol
;
17065 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17066 ex
.X_op_symbol
= NULL
;
17067 ex
.X_add_number
= 0;
17069 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17070 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17072 macro_build_lui (&ex
, mips_gp_register
);
17073 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17074 mips_gp_register
, BFD_RELOC_LO16
);
17079 mips_assembling_insn
= FALSE
;
17080 demand_empty_rest_of_line ();
17084 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17086 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17087 .cplocal is ignored. */
17088 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17094 if (mips_opts
.mips16
)
17096 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17097 ignore_rest_of_line ();
17101 mips_gp_register
= tc_get_register (0);
17102 demand_empty_rest_of_line ();
17105 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17106 offset from $sp. The offset is remembered, and after making a PIC
17107 call $gp is restored from that location. */
17110 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17114 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17115 .cprestore is ignored. */
17116 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17122 if (mips_opts
.mips16
)
17124 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17125 ignore_rest_of_line ();
17129 mips_cprestore_offset
= get_absolute_expression ();
17130 mips_cprestore_valid
= 1;
17132 ex
.X_op
= O_constant
;
17133 ex
.X_add_symbol
= NULL
;
17134 ex
.X_op_symbol
= NULL
;
17135 ex
.X_add_number
= mips_cprestore_offset
;
17137 mips_mark_labels ();
17138 mips_assembling_insn
= TRUE
;
17141 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17142 SP
, HAVE_64BIT_ADDRESSES
);
17145 mips_assembling_insn
= FALSE
;
17146 demand_empty_rest_of_line ();
17149 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17150 was given in the preceding .cpsetup, it results in:
17151 ld $gp, offset($sp)
17153 If a register $reg2 was given there, it results in:
17154 daddu $gp, $reg2, $0 */
17157 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17161 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17162 We also need NewABI support. */
17163 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17169 if (mips_opts
.mips16
)
17171 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17172 ignore_rest_of_line ();
17176 mips_mark_labels ();
17177 mips_assembling_insn
= TRUE
;
17180 if (mips_cpreturn_register
== -1)
17182 ex
.X_op
= O_constant
;
17183 ex
.X_add_symbol
= NULL
;
17184 ex
.X_op_symbol
= NULL
;
17185 ex
.X_add_number
= mips_cpreturn_offset
;
17187 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17190 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
17191 mips_cpreturn_register
, 0);
17194 mips_assembling_insn
= FALSE
;
17195 demand_empty_rest_of_line ();
17198 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17199 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17200 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17201 debug information or MIPS16 TLS. */
17204 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17205 bfd_reloc_code_real_type rtype
)
17212 if (ex
.X_op
!= O_symbol
)
17214 as_bad (_("Unsupported use of %s"), dirstr
);
17215 ignore_rest_of_line ();
17218 p
= frag_more (bytes
);
17219 md_number_to_chars (p
, 0, bytes
);
17220 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17221 demand_empty_rest_of_line ();
17222 mips_clear_insn_labels ();
17225 /* Handle .dtprelword. */
17228 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17230 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17233 /* Handle .dtpreldword. */
17236 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17238 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17241 /* Handle .tprelword. */
17244 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17246 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17249 /* Handle .tpreldword. */
17252 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17254 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17257 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17258 code. It sets the offset to use in gp_rel relocations. */
17261 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17263 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17264 We also need NewABI support. */
17265 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17271 mips_gprel_offset
= get_absolute_expression ();
17273 demand_empty_rest_of_line ();
17276 /* Handle the .gpword pseudo-op. This is used when generating PIC
17277 code. It generates a 32 bit GP relative reloc. */
17280 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17282 segment_info_type
*si
;
17283 struct insn_label_list
*l
;
17287 /* When not generating PIC code, this is treated as .word. */
17288 if (mips_pic
!= SVR4_PIC
)
17294 si
= seg_info (now_seg
);
17295 l
= si
->label_list
;
17296 mips_emit_delays ();
17298 mips_align (2, 0, l
);
17301 mips_clear_insn_labels ();
17303 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17305 as_bad (_("Unsupported use of .gpword"));
17306 ignore_rest_of_line ();
17310 md_number_to_chars (p
, 0, 4);
17311 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17312 BFD_RELOC_GPREL32
);
17314 demand_empty_rest_of_line ();
17318 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17320 segment_info_type
*si
;
17321 struct insn_label_list
*l
;
17325 /* When not generating PIC code, this is treated as .dword. */
17326 if (mips_pic
!= SVR4_PIC
)
17332 si
= seg_info (now_seg
);
17333 l
= si
->label_list
;
17334 mips_emit_delays ();
17336 mips_align (3, 0, l
);
17339 mips_clear_insn_labels ();
17341 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17343 as_bad (_("Unsupported use of .gpdword"));
17344 ignore_rest_of_line ();
17348 md_number_to_chars (p
, 0, 8);
17349 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17350 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17352 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17353 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17354 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17356 demand_empty_rest_of_line ();
17359 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17360 tables. It generates a R_MIPS_EH reloc. */
17363 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17368 mips_emit_delays ();
17371 mips_clear_insn_labels ();
17373 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17375 as_bad (_("Unsupported use of .ehword"));
17376 ignore_rest_of_line ();
17380 md_number_to_chars (p
, 0, 4);
17381 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17382 BFD_RELOC_MIPS_EH
);
17384 demand_empty_rest_of_line ();
17387 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17388 tables in SVR4 PIC code. */
17391 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17395 /* This is ignored when not generating SVR4 PIC code. */
17396 if (mips_pic
!= SVR4_PIC
)
17402 mips_mark_labels ();
17403 mips_assembling_insn
= TRUE
;
17405 /* Add $gp to the register named as an argument. */
17407 reg
= tc_get_register (0);
17408 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17411 mips_assembling_insn
= FALSE
;
17412 demand_empty_rest_of_line ();
17415 /* Handle the .insn pseudo-op. This marks instruction labels in
17416 mips16/micromips mode. This permits the linker to handle them specially,
17417 such as generating jalx instructions when needed. We also make
17418 them odd for the duration of the assembly, in order to generate the
17419 right sort of code. We will make them even in the adjust_symtab
17420 routine, while leaving them marked. This is convenient for the
17421 debugger and the disassembler. The linker knows to make them odd
17425 s_insn (int ignore ATTRIBUTE_UNUSED
)
17427 mips_mark_labels ();
17429 demand_empty_rest_of_line ();
17432 /* Handle a .stab[snd] directive. Ideally these directives would be
17433 implemented in a transparent way, so that removing them would not
17434 have any effect on the generated instructions. However, s_stab
17435 internally changes the section, so in practice we need to decide
17436 now whether the preceding label marks compressed code. We do not
17437 support changing the compression mode of a label after a .stab*
17438 directive, such as in:
17444 so the current mode wins. */
17447 s_mips_stab (int type
)
17449 mips_mark_labels ();
17453 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17456 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17463 name
= input_line_pointer
;
17464 c
= get_symbol_end ();
17465 symbolP
= symbol_find_or_make (name
);
17466 S_SET_WEAK (symbolP
);
17467 *input_line_pointer
= c
;
17469 SKIP_WHITESPACE ();
17471 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17473 if (S_IS_DEFINED (symbolP
))
17475 as_bad (_("ignoring attempt to redefine symbol %s"),
17476 S_GET_NAME (symbolP
));
17477 ignore_rest_of_line ();
17481 if (*input_line_pointer
== ',')
17483 ++input_line_pointer
;
17484 SKIP_WHITESPACE ();
17488 if (exp
.X_op
!= O_symbol
)
17490 as_bad (_("bad .weakext directive"));
17491 ignore_rest_of_line ();
17494 symbol_set_value_expression (symbolP
, &exp
);
17497 demand_empty_rest_of_line ();
17500 /* Parse a register string into a number. Called from the ECOFF code
17501 to parse .frame. The argument is non-zero if this is the frame
17502 register, so that we can record it in mips_frame_reg. */
17505 tc_get_register (int frame
)
17509 SKIP_WHITESPACE ();
17510 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17514 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17515 mips_frame_reg_valid
= 1;
17516 mips_cprestore_valid
= 0;
17522 md_section_align (asection
*seg
, valueT addr
)
17524 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17528 /* We don't need to align ELF sections to the full alignment.
17529 However, Irix 5 may prefer that we align them at least to a 16
17530 byte boundary. We don't bother to align the sections if we
17531 are targeted for an embedded system. */
17532 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17538 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17541 /* Utility routine, called from above as well. If called while the
17542 input file is still being read, it's only an approximation. (For
17543 example, a symbol may later become defined which appeared to be
17544 undefined earlier.) */
17547 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17552 if (g_switch_value
> 0)
17554 const char *symname
;
17557 /* Find out whether this symbol can be referenced off the $gp
17558 register. It can be if it is smaller than the -G size or if
17559 it is in the .sdata or .sbss section. Certain symbols can
17560 not be referenced off the $gp, although it appears as though
17562 symname
= S_GET_NAME (sym
);
17563 if (symname
!= (const char *) NULL
17564 && (strcmp (symname
, "eprol") == 0
17565 || strcmp (symname
, "etext") == 0
17566 || strcmp (symname
, "_gp") == 0
17567 || strcmp (symname
, "edata") == 0
17568 || strcmp (symname
, "_fbss") == 0
17569 || strcmp (symname
, "_fdata") == 0
17570 || strcmp (symname
, "_ftext") == 0
17571 || strcmp (symname
, "end") == 0
17572 || strcmp (symname
, "_gp_disp") == 0))
17574 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17576 #ifndef NO_ECOFF_DEBUGGING
17577 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17578 && (symbol_get_obj (sym
)->ecoff_extern_size
17579 <= g_switch_value
))
17581 /* We must defer this decision until after the whole
17582 file has been read, since there might be a .extern
17583 after the first use of this symbol. */
17584 || (before_relaxing
17585 #ifndef NO_ECOFF_DEBUGGING
17586 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17588 && S_GET_VALUE (sym
) == 0)
17589 || (S_GET_VALUE (sym
) != 0
17590 && S_GET_VALUE (sym
) <= g_switch_value
)))
17594 const char *segname
;
17596 segname
= segment_name (S_GET_SEGMENT (sym
));
17597 gas_assert (strcmp (segname
, ".lit8") != 0
17598 && strcmp (segname
, ".lit4") != 0);
17599 change
= (strcmp (segname
, ".sdata") != 0
17600 && strcmp (segname
, ".sbss") != 0
17601 && strncmp (segname
, ".sdata.", 7) != 0
17602 && strncmp (segname
, ".sbss.", 6) != 0
17603 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17604 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17609 /* We are not optimizing for the $gp register. */
17614 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17617 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17621 /* Handle the case of a symbol equated to another symbol. */
17622 while (symbol_equated_reloc_p (sym
))
17626 /* It's possible to get a loop here in a badly written program. */
17627 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17633 if (symbol_section_p (sym
))
17636 symsec
= S_GET_SEGMENT (sym
);
17638 /* This must duplicate the test in adjust_reloc_syms. */
17639 return (!bfd_is_und_section (symsec
)
17640 && !bfd_is_abs_section (symsec
)
17641 && !bfd_is_com_section (symsec
)
17642 && !s_is_linkonce (sym
, segtype
)
17644 /* A global or weak symbol is treated as external. */
17645 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17651 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17652 extended opcode. SEC is the section the frag is in. */
17655 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17658 const struct mips16_immed_operand
*op
;
17660 int mintiny
, maxtiny
;
17664 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17666 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17669 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17670 op
= mips16_immed_operands
;
17671 while (op
->type
!= type
)
17674 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17679 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17682 maxtiny
= 1 << op
->nbits
;
17687 maxtiny
= (1 << op
->nbits
) - 1;
17692 mintiny
= - (1 << (op
->nbits
- 1));
17693 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17696 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17697 val
= S_GET_VALUE (fragp
->fr_symbol
);
17698 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17704 /* We won't have the section when we are called from
17705 mips_relax_frag. However, we will always have been called
17706 from md_estimate_size_before_relax first. If this is a
17707 branch to a different section, we mark it as such. If SEC is
17708 NULL, and the frag is not marked, then it must be a branch to
17709 the same section. */
17712 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17717 /* Must have been called from md_estimate_size_before_relax. */
17720 fragp
->fr_subtype
=
17721 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17723 /* FIXME: We should support this, and let the linker
17724 catch branches and loads that are out of range. */
17725 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17726 _("unsupported PC relative reference to different section"));
17730 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17731 /* Assume non-extended on the first relaxation pass.
17732 The address we have calculated will be bogus if this is
17733 a forward branch to another frag, as the forward frag
17734 will have fr_address == 0. */
17738 /* In this case, we know for sure that the symbol fragment is in
17739 the same section. If the relax_marker of the symbol fragment
17740 differs from the relax_marker of this fragment, we have not
17741 yet adjusted the symbol fragment fr_address. We want to add
17742 in STRETCH in order to get a better estimate of the address.
17743 This particularly matters because of the shift bits. */
17745 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17749 /* Adjust stretch for any alignment frag. Note that if have
17750 been expanding the earlier code, the symbol may be
17751 defined in what appears to be an earlier frag. FIXME:
17752 This doesn't handle the fr_subtype field, which specifies
17753 a maximum number of bytes to skip when doing an
17755 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17757 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17760 stretch
= - ((- stretch
)
17761 & ~ ((1 << (int) f
->fr_offset
) - 1));
17763 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17772 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17774 /* The base address rules are complicated. The base address of
17775 a branch is the following instruction. The base address of a
17776 PC relative load or add is the instruction itself, but if it
17777 is in a delay slot (in which case it can not be extended) use
17778 the address of the instruction whose delay slot it is in. */
17779 if (type
== 'p' || type
== 'q')
17783 /* If we are currently assuming that this frag should be
17784 extended, then, the current address is two bytes
17786 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17789 /* Ignore the low bit in the target, since it will be set
17790 for a text label. */
17791 if ((val
& 1) != 0)
17794 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17796 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17799 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17801 /* Branch offsets have an implicit 0 in the lowest bit. */
17802 if (type
== 'p' || type
== 'q')
17805 /* If any of the shifted bits are set, we must use an extended
17806 opcode. If the address depends on the size of this
17807 instruction, this can lead to a loop, so we arrange to always
17808 use an extended opcode. We only check this when we are in
17809 the main relaxation loop, when SEC is NULL. */
17810 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17812 fragp
->fr_subtype
=
17813 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17817 /* If we are about to mark a frag as extended because the value
17818 is precisely maxtiny + 1, then there is a chance of an
17819 infinite loop as in the following code:
17824 In this case when the la is extended, foo is 0x3fc bytes
17825 away, so the la can be shrunk, but then foo is 0x400 away, so
17826 the la must be extended. To avoid this loop, we mark the
17827 frag as extended if it was small, and is about to become
17828 extended with a value of maxtiny + 1. */
17829 if (val
== ((maxtiny
+ 1) << op
->shift
)
17830 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17833 fragp
->fr_subtype
=
17834 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17838 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17839 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17841 if ((val
& ((1 << op
->shift
) - 1)) != 0
17842 || val
< (mintiny
<< op
->shift
)
17843 || val
> (maxtiny
<< op
->shift
))
17849 /* Compute the length of a branch sequence, and adjust the
17850 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17851 worst-case length is computed, with UPDATE being used to indicate
17852 whether an unconditional (-1), branch-likely (+1) or regular (0)
17853 branch is to be computed. */
17855 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17857 bfd_boolean toofar
;
17861 && S_IS_DEFINED (fragp
->fr_symbol
)
17862 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17867 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17869 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17873 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17876 /* If the symbol is not defined or it's in a different segment,
17877 assume the user knows what's going on and emit a short
17883 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17885 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17886 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17887 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17888 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17894 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17897 if (mips_pic
!= NO_PIC
)
17899 /* Additional space for PIC loading of target address. */
17901 if (mips_opts
.isa
== ISA_MIPS1
)
17902 /* Additional space for $at-stabilizing nop. */
17906 /* If branch is conditional. */
17907 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17914 /* Compute the length of a branch sequence, and adjust the
17915 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17916 worst-case length is computed, with UPDATE being used to indicate
17917 whether an unconditional (-1), or regular (0) branch is to be
17921 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17923 bfd_boolean toofar
;
17927 && S_IS_DEFINED (fragp
->fr_symbol
)
17928 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17933 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17934 /* Ignore the low bit in the target, since it will be set
17935 for a text label. */
17936 if ((val
& 1) != 0)
17939 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17943 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17946 /* If the symbol is not defined or it's in a different segment,
17947 assume the user knows what's going on and emit a short
17953 if (fragp
&& update
17954 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17955 fragp
->fr_subtype
= (toofar
17956 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17957 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17962 bfd_boolean compact_known
= fragp
!= NULL
;
17963 bfd_boolean compact
= FALSE
;
17964 bfd_boolean uncond
;
17967 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17969 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17971 uncond
= update
< 0;
17973 /* If label is out of range, we turn branch <br>:
17975 <br> label # 4 bytes
17981 nop # 2 bytes if compact && !PIC
17984 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17987 /* If assembling PIC code, we further turn:
17993 lw/ld at, %got(label)(gp) # 4 bytes
17994 d/addiu at, %lo(label) # 4 bytes
17997 if (mips_pic
!= NO_PIC
)
18000 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18002 <brneg> 0f # 4 bytes
18003 nop # 2 bytes if !compact
18006 length
+= (compact_known
&& compact
) ? 4 : 6;
18012 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18013 bit accordingly. */
18016 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18018 bfd_boolean toofar
;
18021 && S_IS_DEFINED (fragp
->fr_symbol
)
18022 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18028 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18029 /* Ignore the low bit in the target, since it will be set
18030 for a text label. */
18031 if ((val
& 1) != 0)
18034 /* Assume this is a 2-byte branch. */
18035 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18037 /* We try to avoid the infinite loop by not adding 2 more bytes for
18042 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18044 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18045 else if (type
== 'E')
18046 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18051 /* If the symbol is not defined or it's in a different segment,
18052 we emit a normal 32-bit branch. */
18055 if (fragp
&& update
18056 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18058 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18059 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18067 /* Estimate the size of a frag before relaxing. Unless this is the
18068 mips16, we are not really relaxing here, and the final size is
18069 encoded in the subtype information. For the mips16, we have to
18070 decide whether we are using an extended opcode or not. */
18073 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18077 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18080 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18082 return fragp
->fr_var
;
18085 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18086 /* We don't want to modify the EXTENDED bit here; it might get us
18087 into infinite loops. We change it only in mips_relax_frag(). */
18088 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
18090 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18094 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18095 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18096 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18097 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18098 fragp
->fr_var
= length
;
18103 if (mips_pic
== NO_PIC
)
18104 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18105 else if (mips_pic
== SVR4_PIC
)
18106 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
18107 else if (mips_pic
== VXWORKS_PIC
)
18108 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18115 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18116 return -RELAX_FIRST (fragp
->fr_subtype
);
18119 return -RELAX_SECOND (fragp
->fr_subtype
);
18122 /* This is called to see whether a reloc against a defined symbol
18123 should be converted into a reloc against a section. */
18126 mips_fix_adjustable (fixS
*fixp
)
18128 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18129 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18132 if (fixp
->fx_addsy
== NULL
)
18135 /* If symbol SYM is in a mergeable section, relocations of the form
18136 SYM + 0 can usually be made section-relative. The mergeable data
18137 is then identified by the section offset rather than by the symbol.
18139 However, if we're generating REL LO16 relocations, the offset is split
18140 between the LO16 and parterning high part relocation. The linker will
18141 need to recalculate the complete offset in order to correctly identify
18144 The linker has traditionally not looked for the parterning high part
18145 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18146 placed anywhere. Rather than break backwards compatibility by changing
18147 this, it seems better not to force the issue, and instead keep the
18148 original symbol. This will work with either linker behavior. */
18149 if ((lo16_reloc_p (fixp
->fx_r_type
)
18150 || reloc_needs_lo_p (fixp
->fx_r_type
))
18151 && HAVE_IN_PLACE_ADDENDS
18152 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18155 /* There is no place to store an in-place offset for JALR relocations.
18156 Likewise an in-range offset of limited PC-relative relocations may
18157 overflow the in-place relocatable field if recalculated against the
18158 start address of the symbol's containing section. */
18159 if (HAVE_IN_PLACE_ADDENDS
18160 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18161 || jalr_reloc_p (fixp
->fx_r_type
)))
18165 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18166 to a floating-point stub. The same is true for non-R_MIPS16_26
18167 relocations against MIPS16 functions; in this case, the stub becomes
18168 the function's canonical address.
18170 Floating-point stubs are stored in unique .mips16.call.* or
18171 .mips16.fn.* sections. If a stub T for function F is in section S,
18172 the first relocation in section S must be against F; this is how the
18173 linker determines the target function. All relocations that might
18174 resolve to T must also be against F. We therefore have the following
18175 restrictions, which are given in an intentionally-redundant way:
18177 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18180 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18181 if that stub might be used.
18183 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18186 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18187 that stub might be used.
18189 There is a further restriction:
18191 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18192 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
18193 targets with in-place addends; the relocation field cannot
18194 encode the low bit.
18196 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18197 against a MIPS16 symbol. We deal with (5) by by not reducing any
18198 such relocations on REL targets.
18200 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18201 relocation against some symbol R, no relocation against R may be
18202 reduced. (Note that this deals with (2) as well as (1) because
18203 relocations against global symbols will never be reduced on ELF
18204 targets.) This approach is a little simpler than trying to detect
18205 stub sections, and gives the "all or nothing" per-symbol consistency
18206 that we have for MIPS16 symbols. */
18208 && fixp
->fx_subsy
== NULL
18209 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18210 || *symbol_get_tc (fixp
->fx_addsy
)
18211 || (HAVE_IN_PLACE_ADDENDS
18212 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18213 && jmp_reloc_p (fixp
->fx_r_type
))))
18220 /* Translate internal representation of relocation info to BFD target
18224 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18226 static arelent
*retval
[4];
18228 bfd_reloc_code_real_type code
;
18230 memset (retval
, 0, sizeof(retval
));
18231 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
18232 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
18233 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18234 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18236 if (fixp
->fx_pcrel
)
18238 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18239 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18240 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18241 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18242 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
18244 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18245 Relocations want only the symbol offset. */
18246 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18249 /* A gruesome hack which is a result of the gruesome gas
18250 reloc handling. What's worse, for COFF (as opposed to
18251 ECOFF), we might need yet another copy of reloc->address.
18252 See bfd_install_relocation. */
18253 reloc
->addend
+= reloc
->address
;
18257 reloc
->addend
= fixp
->fx_addnumber
;
18259 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18260 entry to be used in the relocation's section offset. */
18261 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18263 reloc
->address
= reloc
->addend
;
18267 code
= fixp
->fx_r_type
;
18269 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18270 if (reloc
->howto
== NULL
)
18272 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18273 _("Can not represent %s relocation in this object file format"),
18274 bfd_get_reloc_code_name (code
));
18281 /* Relax a machine dependent frag. This returns the amount by which
18282 the current size of the frag should change. */
18285 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18287 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18289 offsetT old_var
= fragp
->fr_var
;
18291 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18293 return fragp
->fr_var
- old_var
;
18296 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18298 offsetT old_var
= fragp
->fr_var
;
18299 offsetT new_var
= 4;
18301 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18302 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18303 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18304 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18305 fragp
->fr_var
= new_var
;
18307 return new_var
- old_var
;
18310 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18313 if (mips16_extended_frag (fragp
, NULL
, stretch
))
18315 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18317 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18322 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18324 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18331 /* Convert a machine dependent frag. */
18334 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18336 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18339 unsigned long insn
;
18343 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18344 insn
= read_insn (buf
);
18346 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18348 /* We generate a fixup instead of applying it right now
18349 because, if there are linker relaxations, we're going to
18350 need the relocations. */
18351 exp
.X_op
= O_symbol
;
18352 exp
.X_add_symbol
= fragp
->fr_symbol
;
18353 exp
.X_add_number
= fragp
->fr_offset
;
18355 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18356 BFD_RELOC_16_PCREL_S2
);
18357 fixp
->fx_file
= fragp
->fr_file
;
18358 fixp
->fx_line
= fragp
->fr_line
;
18360 buf
= write_insn (buf
, insn
);
18366 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18367 _("Relaxed out-of-range branch into a jump"));
18369 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18372 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18374 /* Reverse the branch. */
18375 switch ((insn
>> 28) & 0xf)
18378 /* bc[0-3][tf]l? instructions can have the condition
18379 reversed by tweaking a single TF bit, and their
18380 opcodes all have 0x4???????. */
18381 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18382 insn
^= 0x00010000;
18386 /* bltz 0x04000000 bgez 0x04010000
18387 bltzal 0x04100000 bgezal 0x04110000 */
18388 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18389 insn
^= 0x00010000;
18393 /* beq 0x10000000 bne 0x14000000
18394 blez 0x18000000 bgtz 0x1c000000 */
18395 insn
^= 0x04000000;
18403 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18405 /* Clear the and-link bit. */
18406 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18408 /* bltzal 0x04100000 bgezal 0x04110000
18409 bltzall 0x04120000 bgezall 0x04130000 */
18410 insn
&= ~0x00100000;
18413 /* Branch over the branch (if the branch was likely) or the
18414 full jump (not likely case). Compute the offset from the
18415 current instruction to branch to. */
18416 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18420 /* How many bytes in instructions we've already emitted? */
18421 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18422 /* How many bytes in instructions from here to the end? */
18423 i
= fragp
->fr_var
- i
;
18425 /* Convert to instruction count. */
18427 /* Branch counts from the next instruction. */
18430 /* Branch over the jump. */
18431 buf
= write_insn (buf
, insn
);
18434 buf
= write_insn (buf
, 0);
18436 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18438 /* beql $0, $0, 2f */
18440 /* Compute the PC offset from the current instruction to
18441 the end of the variable frag. */
18442 /* How many bytes in instructions we've already emitted? */
18443 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18444 /* How many bytes in instructions from here to the end? */
18445 i
= fragp
->fr_var
- i
;
18446 /* Convert to instruction count. */
18448 /* Don't decrement i, because we want to branch over the
18452 buf
= write_insn (buf
, insn
);
18453 buf
= write_insn (buf
, 0);
18457 if (mips_pic
== NO_PIC
)
18460 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18461 ? 0x0c000000 : 0x08000000);
18462 exp
.X_op
= O_symbol
;
18463 exp
.X_add_symbol
= fragp
->fr_symbol
;
18464 exp
.X_add_number
= fragp
->fr_offset
;
18466 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18467 FALSE
, BFD_RELOC_MIPS_JMP
);
18468 fixp
->fx_file
= fragp
->fr_file
;
18469 fixp
->fx_line
= fragp
->fr_line
;
18471 buf
= write_insn (buf
, insn
);
18475 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18477 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18478 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18479 insn
|= at
<< OP_SH_RT
;
18480 exp
.X_op
= O_symbol
;
18481 exp
.X_add_symbol
= fragp
->fr_symbol
;
18482 exp
.X_add_number
= fragp
->fr_offset
;
18484 if (fragp
->fr_offset
)
18486 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18487 exp
.X_add_number
= 0;
18490 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18491 FALSE
, BFD_RELOC_MIPS_GOT16
);
18492 fixp
->fx_file
= fragp
->fr_file
;
18493 fixp
->fx_line
= fragp
->fr_line
;
18495 buf
= write_insn (buf
, insn
);
18497 if (mips_opts
.isa
== ISA_MIPS1
)
18499 buf
= write_insn (buf
, 0);
18501 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18502 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18503 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18505 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18506 FALSE
, BFD_RELOC_LO16
);
18507 fixp
->fx_file
= fragp
->fr_file
;
18508 fixp
->fx_line
= fragp
->fr_line
;
18510 buf
= write_insn (buf
, insn
);
18513 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18517 insn
|= at
<< OP_SH_RS
;
18519 buf
= write_insn (buf
, insn
);
18523 fragp
->fr_fix
+= fragp
->fr_var
;
18524 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18528 /* Relax microMIPS branches. */
18529 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18531 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18532 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18533 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18534 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18535 bfd_boolean short_ds
;
18536 unsigned long insn
;
18540 exp
.X_op
= O_symbol
;
18541 exp
.X_add_symbol
= fragp
->fr_symbol
;
18542 exp
.X_add_number
= fragp
->fr_offset
;
18544 fragp
->fr_fix
+= fragp
->fr_var
;
18546 /* Handle 16-bit branches that fit or are forced to fit. */
18547 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18549 /* We generate a fixup instead of applying it right now,
18550 because if there is linker relaxation, we're going to
18551 need the relocations. */
18553 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18554 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18555 else if (type
== 'E')
18556 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18557 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18561 fixp
->fx_file
= fragp
->fr_file
;
18562 fixp
->fx_line
= fragp
->fr_line
;
18564 /* These relocations can have an addend that won't fit in
18566 fixp
->fx_no_overflow
= 1;
18571 /* Handle 32-bit branches that fit or are forced to fit. */
18572 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18573 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18575 /* We generate a fixup instead of applying it right now,
18576 because if there is linker relaxation, we're going to
18577 need the relocations. */
18578 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18579 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18580 fixp
->fx_file
= fragp
->fr_file
;
18581 fixp
->fx_line
= fragp
->fr_line
;
18587 /* Relax 16-bit branches to 32-bit branches. */
18590 insn
= read_compressed_insn (buf
, 2);
18592 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18593 insn
= 0x94000000; /* beq */
18594 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18596 unsigned long regno
;
18598 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18599 regno
= micromips_to_32_reg_d_map
[regno
];
18600 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18601 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18606 /* Nothing else to do, just write it out. */
18607 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18608 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18610 buf
= write_compressed_insn (buf
, insn
, 4);
18611 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18616 insn
= read_compressed_insn (buf
, 4);
18618 /* Relax 32-bit branches to a sequence of instructions. */
18619 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18620 _("Relaxed out-of-range branch into a jump"));
18622 /* Set the short-delay-slot bit. */
18623 short_ds
= al
&& (insn
& 0x02000000) != 0;
18625 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18629 /* Reverse the branch. */
18630 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18631 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18632 insn
^= 0x20000000;
18633 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18634 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18635 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18636 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18637 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18638 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18639 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18640 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18641 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18642 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18643 insn
^= 0x00400000;
18644 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18645 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18646 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18647 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18648 insn
^= 0x00200000;
18654 /* Clear the and-link and short-delay-slot bits. */
18655 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18657 /* bltzal 0x40200000 bgezal 0x40600000 */
18658 /* bltzals 0x42200000 bgezals 0x42600000 */
18659 insn
&= ~0x02200000;
18662 /* Make a label at the end for use with the branch. */
18663 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18664 micromips_label_inc ();
18665 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18667 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18671 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18672 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18673 fixp
->fx_file
= fragp
->fr_file
;
18674 fixp
->fx_line
= fragp
->fr_line
;
18676 /* Branch over the jump. */
18677 buf
= write_compressed_insn (buf
, insn
, 4);
18680 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18683 if (mips_pic
== NO_PIC
)
18685 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18687 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18688 insn
= al
? jal
: 0xd4000000;
18690 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18691 BFD_RELOC_MICROMIPS_JMP
);
18692 fixp
->fx_file
= fragp
->fr_file
;
18693 fixp
->fx_line
= fragp
->fr_line
;
18695 buf
= write_compressed_insn (buf
, insn
, 4);
18698 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18702 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18703 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18704 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18706 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18707 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18708 insn
|= at
<< MICROMIPSOP_SH_RT
;
18710 if (exp
.X_add_number
)
18712 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18713 exp
.X_add_number
= 0;
18716 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18717 BFD_RELOC_MICROMIPS_GOT16
);
18718 fixp
->fx_file
= fragp
->fr_file
;
18719 fixp
->fx_line
= fragp
->fr_line
;
18721 buf
= write_compressed_insn (buf
, insn
, 4);
18723 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18724 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18725 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18727 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18728 BFD_RELOC_MICROMIPS_LO16
);
18729 fixp
->fx_file
= fragp
->fr_file
;
18730 fixp
->fx_line
= fragp
->fr_line
;
18732 buf
= write_compressed_insn (buf
, insn
, 4);
18734 /* jr/jrc/jalr/jalrs $at */
18735 insn
= al
? jalr
: jr
;
18736 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18738 buf
= write_compressed_insn (buf
, insn
, 2);
18741 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18745 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18748 const struct mips16_immed_operand
*op
;
18751 unsigned int user_length
, length
;
18752 unsigned long insn
;
18755 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18756 op
= mips16_immed_operands
;
18757 while (op
->type
!= type
)
18760 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18761 val
= resolve_symbol_value (fragp
->fr_symbol
);
18766 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18768 /* The rules for the base address of a PC relative reloc are
18769 complicated; see mips16_extended_frag. */
18770 if (type
== 'p' || type
== 'q')
18775 /* Ignore the low bit in the target, since it will be
18776 set for a text label. */
18777 if ((val
& 1) != 0)
18780 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18782 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18785 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18788 /* Make sure the section winds up with the alignment we have
18791 record_alignment (asec
, op
->shift
);
18795 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18796 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18797 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18798 _("extended instruction in delay slot"));
18800 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18802 insn
= read_compressed_insn (buf
, 2);
18804 insn
|= MIPS16_EXTEND
;
18806 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18808 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18813 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18814 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18816 length
= (ext
? 4 : 2);
18817 gas_assert (mips16_opcode_length (insn
) == length
);
18818 write_compressed_insn (buf
, insn
, length
);
18819 fragp
->fr_fix
+= length
;
18823 relax_substateT subtype
= fragp
->fr_subtype
;
18824 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18825 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18829 first
= RELAX_FIRST (subtype
);
18830 second
= RELAX_SECOND (subtype
);
18831 fixp
= (fixS
*) fragp
->fr_opcode
;
18833 /* If the delay slot chosen does not match the size of the instruction,
18834 then emit a warning. */
18835 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18836 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18841 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18842 | RELAX_DELAY_SLOT_SIZE_FIRST
18843 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18844 msg
= macro_warning (s
);
18846 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18850 /* Possibly emit a warning if we've chosen the longer option. */
18851 if (use_second
== second_longer
)
18857 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18858 msg
= macro_warning (s
);
18860 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18864 /* Go through all the fixups for the first sequence. Disable them
18865 (by marking them as done) if we're going to use the second
18866 sequence instead. */
18868 && fixp
->fx_frag
== fragp
18869 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18871 if (subtype
& RELAX_USE_SECOND
)
18873 fixp
= fixp
->fx_next
;
18876 /* Go through the fixups for the second sequence. Disable them if
18877 we're going to use the first sequence, otherwise adjust their
18878 addresses to account for the relaxation. */
18879 while (fixp
&& fixp
->fx_frag
== fragp
)
18881 if (subtype
& RELAX_USE_SECOND
)
18882 fixp
->fx_where
-= first
;
18885 fixp
= fixp
->fx_next
;
18888 /* Now modify the frag contents. */
18889 if (subtype
& RELAX_USE_SECOND
)
18893 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18894 memmove (start
, start
+ first
, second
);
18895 fragp
->fr_fix
-= first
;
18898 fragp
->fr_fix
-= second
;
18904 /* This function is called after the relocs have been generated.
18905 We've been storing mips16 text labels as odd. Here we convert them
18906 back to even for the convenience of the debugger. */
18909 mips_frob_file_after_relocs (void)
18912 unsigned int count
, i
;
18917 syms
= bfd_get_outsymbols (stdoutput
);
18918 count
= bfd_get_symcount (stdoutput
);
18919 for (i
= 0; i
< count
; i
++, syms
++)
18920 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18921 && ((*syms
)->value
& 1) != 0)
18923 (*syms
)->value
&= ~1;
18924 /* If the symbol has an odd size, it was probably computed
18925 incorrectly, so adjust that as well. */
18926 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18927 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18933 /* This function is called whenever a label is defined, including fake
18934 labels instantiated off the dot special symbol. It is used when
18935 handling branch delays; if a branch has a label, we assume we cannot
18936 move it. This also bumps the value of the symbol by 1 in compressed
18940 mips_record_label (symbolS
*sym
)
18942 segment_info_type
*si
= seg_info (now_seg
);
18943 struct insn_label_list
*l
;
18945 if (free_insn_labels
== NULL
)
18946 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18949 l
= free_insn_labels
;
18950 free_insn_labels
= l
->next
;
18954 l
->next
= si
->label_list
;
18955 si
->label_list
= l
;
18958 /* This function is called as tc_frob_label() whenever a label is defined
18959 and adds a DWARF-2 record we only want for true labels. */
18962 mips_define_label (symbolS
*sym
)
18964 mips_record_label (sym
);
18966 dwarf2_emit_label (sym
);
18970 /* This function is called by tc_new_dot_label whenever a new dot symbol
18974 mips_add_dot_label (symbolS
*sym
)
18976 mips_record_label (sym
);
18977 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18978 mips_compressed_mark_label (sym
);
18981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18983 /* Some special processing for a MIPS ELF file. */
18986 mips_elf_final_processing (void)
18988 /* Write out the register information. */
18989 if (mips_abi
!= N64_ABI
)
18993 s
.ri_gprmask
= mips_gprmask
;
18994 s
.ri_cprmask
[0] = mips_cprmask
[0];
18995 s
.ri_cprmask
[1] = mips_cprmask
[1];
18996 s
.ri_cprmask
[2] = mips_cprmask
[2];
18997 s
.ri_cprmask
[3] = mips_cprmask
[3];
18998 /* The gp_value field is set by the MIPS ELF backend. */
19000 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19001 ((Elf32_External_RegInfo
*)
19002 mips_regmask_frag
));
19006 Elf64_Internal_RegInfo s
;
19008 s
.ri_gprmask
= mips_gprmask
;
19010 s
.ri_cprmask
[0] = mips_cprmask
[0];
19011 s
.ri_cprmask
[1] = mips_cprmask
[1];
19012 s
.ri_cprmask
[2] = mips_cprmask
[2];
19013 s
.ri_cprmask
[3] = mips_cprmask
[3];
19014 /* The gp_value field is set by the MIPS ELF backend. */
19016 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19017 ((Elf64_External_RegInfo
*)
19018 mips_regmask_frag
));
19021 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19022 sort of BFD interface for this. */
19023 if (mips_any_noreorder
)
19024 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19025 if (mips_pic
!= NO_PIC
)
19027 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19028 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19031 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19033 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19034 defined at present; this might need to change in future. */
19035 if (file_ase_mips16
)
19036 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19037 if (file_ase_micromips
)
19038 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19039 #if 0 /* XXX FIXME */
19040 if (file_ase_mips3d
)
19041 elf_elfheader (stdoutput
)->e_flags
|= ???;
19044 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19046 /* Set the MIPS ELF ABI flags. */
19047 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19048 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19049 else if (mips_abi
== O64_ABI
)
19050 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19051 else if (mips_abi
== EABI_ABI
)
19053 if (!file_mips_gp32
)
19054 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19056 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19058 else if (mips_abi
== N32_ABI
)
19059 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
19061 /* Nothing to do for N64_ABI. */
19063 if (mips_32bitmode
)
19064 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19066 #if 0 /* XXX FIXME */
19067 /* 32 bit code with 64 bit FP registers. */
19068 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
19069 elf_elfheader (stdoutput
)->e_flags
|= ???;
19073 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
19075 typedef struct proc
{
19077 symbolS
*func_end_sym
;
19078 unsigned long reg_mask
;
19079 unsigned long reg_offset
;
19080 unsigned long fpreg_mask
;
19081 unsigned long fpreg_offset
;
19082 unsigned long frame_offset
;
19083 unsigned long frame_reg
;
19084 unsigned long pc_reg
;
19087 static procS cur_proc
;
19088 static procS
*cur_proc_ptr
;
19089 static int numprocs
;
19091 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19092 as "2", and a normal nop as "0". */
19094 #define NOP_OPCODE_MIPS 0
19095 #define NOP_OPCODE_MIPS16 1
19096 #define NOP_OPCODE_MICROMIPS 2
19099 mips_nop_opcode (void)
19101 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19102 return NOP_OPCODE_MICROMIPS
;
19103 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19104 return NOP_OPCODE_MIPS16
;
19106 return NOP_OPCODE_MIPS
;
19109 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19110 32-bit microMIPS NOPs here (if applicable). */
19113 mips_handle_align (fragS
*fragp
)
19117 int bytes
, size
, excess
;
19120 if (fragp
->fr_type
!= rs_align_code
)
19123 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19125 switch (nop_opcode
)
19127 case NOP_OPCODE_MICROMIPS
:
19128 opcode
= micromips_nop32_insn
.insn_opcode
;
19131 case NOP_OPCODE_MIPS16
:
19132 opcode
= mips16_nop_insn
.insn_opcode
;
19135 case NOP_OPCODE_MIPS
:
19137 opcode
= nop_insn
.insn_opcode
;
19142 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19143 excess
= bytes
% size
;
19145 /* Handle the leading part if we're not inserting a whole number of
19146 instructions, and make it the end of the fixed part of the frag.
19147 Try to fit in a short microMIPS NOP if applicable and possible,
19148 and use zeroes otherwise. */
19149 gas_assert (excess
< 4);
19150 fragp
->fr_fix
+= excess
;
19155 /* Fall through. */
19157 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
19159 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19163 /* Fall through. */
19166 /* Fall through. */
19171 md_number_to_chars (p
, opcode
, size
);
19172 fragp
->fr_var
= size
;
19176 md_obj_begin (void)
19183 /* Check for premature end, nesting errors, etc. */
19185 as_warn (_("missing .end at end of assembly"));
19194 if (*input_line_pointer
== '-')
19196 ++input_line_pointer
;
19199 if (!ISDIGIT (*input_line_pointer
))
19200 as_bad (_("expected simple number"));
19201 if (input_line_pointer
[0] == '0')
19203 if (input_line_pointer
[1] == 'x')
19205 input_line_pointer
+= 2;
19206 while (ISXDIGIT (*input_line_pointer
))
19209 val
|= hex_value (*input_line_pointer
++);
19211 return negative
? -val
: val
;
19215 ++input_line_pointer
;
19216 while (ISDIGIT (*input_line_pointer
))
19219 val
|= *input_line_pointer
++ - '0';
19221 return negative
? -val
: val
;
19224 if (!ISDIGIT (*input_line_pointer
))
19226 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19227 *input_line_pointer
, *input_line_pointer
);
19228 as_warn (_("invalid number"));
19231 while (ISDIGIT (*input_line_pointer
))
19234 val
+= *input_line_pointer
++ - '0';
19236 return negative
? -val
: val
;
19239 /* The .file directive; just like the usual .file directive, but there
19240 is an initial number which is the ECOFF file index. In the non-ECOFF
19241 case .file implies DWARF-2. */
19244 s_mips_file (int x ATTRIBUTE_UNUSED
)
19246 static int first_file_directive
= 0;
19248 if (ECOFF_DEBUGGING
)
19257 filename
= dwarf2_directive_file (0);
19259 /* Versions of GCC up to 3.1 start files with a ".file"
19260 directive even for stabs output. Make sure that this
19261 ".file" is handled. Note that you need a version of GCC
19262 after 3.1 in order to support DWARF-2 on MIPS. */
19263 if (filename
!= NULL
&& ! first_file_directive
)
19265 (void) new_logical_line (filename
, -1);
19266 s_app_file_string (filename
, 0);
19268 first_file_directive
= 1;
19272 /* The .loc directive, implying DWARF-2. */
19275 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19277 if (!ECOFF_DEBUGGING
)
19278 dwarf2_directive_loc (0);
19281 /* The .end directive. */
19284 s_mips_end (int x ATTRIBUTE_UNUSED
)
19288 /* Following functions need their own .frame and .cprestore directives. */
19289 mips_frame_reg_valid
= 0;
19290 mips_cprestore_valid
= 0;
19292 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19295 demand_empty_rest_of_line ();
19300 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19301 as_warn (_(".end not in text section"));
19305 as_warn (_(".end directive without a preceding .ent directive."));
19306 demand_empty_rest_of_line ();
19312 gas_assert (S_GET_NAME (p
));
19313 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19314 as_warn (_(".end symbol does not match .ent symbol."));
19316 if (debug_type
== DEBUG_STABS
)
19317 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19321 as_warn (_(".end directive missing or unknown symbol"));
19324 /* Create an expression to calculate the size of the function. */
19325 if (p
&& cur_proc_ptr
)
19327 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19328 expressionS
*exp
= xmalloc (sizeof (expressionS
));
19331 exp
->X_op
= O_subtract
;
19332 exp
->X_add_symbol
= symbol_temp_new_now ();
19333 exp
->X_op_symbol
= p
;
19334 exp
->X_add_number
= 0;
19336 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19339 /* Generate a .pdr section. */
19340 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
19342 segT saved_seg
= now_seg
;
19343 subsegT saved_subseg
= now_subseg
;
19347 #ifdef md_flush_pending_output
19348 md_flush_pending_output ();
19351 gas_assert (pdr_seg
);
19352 subseg_set (pdr_seg
, 0);
19354 /* Write the symbol. */
19355 exp
.X_op
= O_symbol
;
19356 exp
.X_add_symbol
= p
;
19357 exp
.X_add_number
= 0;
19358 emit_expr (&exp
, 4);
19360 fragp
= frag_more (7 * 4);
19362 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19363 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19364 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19365 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19366 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19367 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19368 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19370 subseg_set (saved_seg
, saved_subseg
);
19372 #endif /* OBJ_ELF */
19374 cur_proc_ptr
= NULL
;
19377 /* The .aent and .ent directives. */
19380 s_mips_ent (int aent
)
19384 symbolP
= get_symbol ();
19385 if (*input_line_pointer
== ',')
19386 ++input_line_pointer
;
19387 SKIP_WHITESPACE ();
19388 if (ISDIGIT (*input_line_pointer
)
19389 || *input_line_pointer
== '-')
19392 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19393 as_warn (_(".ent or .aent not in text section."));
19395 if (!aent
&& cur_proc_ptr
)
19396 as_warn (_("missing .end"));
19400 /* This function needs its own .frame and .cprestore directives. */
19401 mips_frame_reg_valid
= 0;
19402 mips_cprestore_valid
= 0;
19404 cur_proc_ptr
= &cur_proc
;
19405 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19407 cur_proc_ptr
->func_sym
= symbolP
;
19411 if (debug_type
== DEBUG_STABS
)
19412 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19413 S_GET_NAME (symbolP
));
19416 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19418 demand_empty_rest_of_line ();
19421 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19422 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19423 s_mips_frame is used so that we can set the PDR information correctly.
19424 We can't use the ecoff routines because they make reference to the ecoff
19425 symbol table (in the mdebug section). */
19428 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19431 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19435 if (cur_proc_ptr
== (procS
*) NULL
)
19437 as_warn (_(".frame outside of .ent"));
19438 demand_empty_rest_of_line ();
19442 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19444 SKIP_WHITESPACE ();
19445 if (*input_line_pointer
++ != ','
19446 || get_absolute_expression_and_terminator (&val
) != ',')
19448 as_warn (_("Bad .frame directive"));
19449 --input_line_pointer
;
19450 demand_empty_rest_of_line ();
19454 cur_proc_ptr
->frame_offset
= val
;
19455 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19457 demand_empty_rest_of_line ();
19460 #endif /* OBJ_ELF */
19464 /* The .fmask and .mask directives. If the mdebug section is present
19465 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19466 embedded targets, s_mips_mask is used so that we can set the PDR
19467 information correctly. We can't use the ecoff routines because they
19468 make reference to the ecoff symbol table (in the mdebug section). */
19471 s_mips_mask (int reg_type
)
19474 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19478 if (cur_proc_ptr
== (procS
*) NULL
)
19480 as_warn (_(".mask/.fmask outside of .ent"));
19481 demand_empty_rest_of_line ();
19485 if (get_absolute_expression_and_terminator (&mask
) != ',')
19487 as_warn (_("Bad .mask/.fmask directive"));
19488 --input_line_pointer
;
19489 demand_empty_rest_of_line ();
19493 off
= get_absolute_expression ();
19495 if (reg_type
== 'F')
19497 cur_proc_ptr
->fpreg_mask
= mask
;
19498 cur_proc_ptr
->fpreg_offset
= off
;
19502 cur_proc_ptr
->reg_mask
= mask
;
19503 cur_proc_ptr
->reg_offset
= off
;
19506 demand_empty_rest_of_line ();
19509 #endif /* OBJ_ELF */
19510 s_ignore (reg_type
);
19513 /* A table describing all the processors gas knows about. Names are
19514 matched in the order listed.
19516 To ease comparison, please keep this table in the same order as
19517 gcc's mips_cpu_info_table[]. */
19518 static const struct mips_cpu_info mips_cpu_info_table
[] =
19520 /* Entries for generic ISAs */
19521 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
19522 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
19523 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
19524 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
19525 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
19526 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
19527 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19528 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
19529 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
19532 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
19533 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
19534 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
19537 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
19540 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
19541 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
19542 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
19543 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
19544 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
19545 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
19546 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
19547 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
19548 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
19549 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
19550 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
19551 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
19552 { "r5900", 0, ISA_MIPS3
, CPU_R5900
},
19553 /* ST Microelectronics Loongson 2E and 2F cores */
19554 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19555 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19558 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19559 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19560 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19561 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19562 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19563 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19564 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19565 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19566 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19567 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19568 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19569 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19570 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19571 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19572 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19575 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19576 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19577 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19578 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19580 /* MIPS 32 Release 2 */
19581 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19582 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19583 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19584 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19585 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19586 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19587 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19588 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19589 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19590 ISA_MIPS32R2
, CPU_MIPS32R2
},
19591 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19592 ISA_MIPS32R2
, CPU_MIPS32R2
},
19593 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19594 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19595 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19596 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19597 /* Deprecated forms of the above. */
19598 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19599 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19600 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19601 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19602 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19603 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19604 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19605 /* Deprecated forms of the above. */
19606 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19607 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19608 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19609 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19610 ISA_MIPS32R2
, CPU_MIPS32R2
},
19611 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19612 ISA_MIPS32R2
, CPU_MIPS32R2
},
19613 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19614 ISA_MIPS32R2
, CPU_MIPS32R2
},
19615 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19616 ISA_MIPS32R2
, CPU_MIPS32R2
},
19617 /* Deprecated forms of the above. */
19618 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19619 ISA_MIPS32R2
, CPU_MIPS32R2
},
19620 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19621 ISA_MIPS32R2
, CPU_MIPS32R2
},
19622 /* 34Kn is a 34kc without DSP. */
19623 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19624 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19625 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19626 ISA_MIPS32R2
, CPU_MIPS32R2
},
19627 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19628 ISA_MIPS32R2
, CPU_MIPS32R2
},
19629 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19630 ISA_MIPS32R2
, CPU_MIPS32R2
},
19631 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19632 ISA_MIPS32R2
, CPU_MIPS32R2
},
19633 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19634 ISA_MIPS32R2
, CPU_MIPS32R2
},
19635 /* Deprecated forms of the above. */
19636 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19637 ISA_MIPS32R2
, CPU_MIPS32R2
},
19638 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19639 ISA_MIPS32R2
, CPU_MIPS32R2
},
19640 /* 1004K cores are multiprocessor versions of the 34K. */
19641 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19642 ISA_MIPS32R2
, CPU_MIPS32R2
},
19643 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19644 ISA_MIPS32R2
, CPU_MIPS32R2
},
19645 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19646 ISA_MIPS32R2
, CPU_MIPS32R2
},
19647 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19648 ISA_MIPS32R2
, CPU_MIPS32R2
},
19651 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19652 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19653 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19654 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19656 /* Broadcom SB-1 CPU core */
19657 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19658 ISA_MIPS64
, CPU_SB1
},
19659 /* Broadcom SB-1A CPU core */
19660 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19661 ISA_MIPS64
, CPU_SB1
},
19663 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19665 /* MIPS 64 Release 2 */
19667 /* Cavium Networks Octeon CPU core */
19668 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19669 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19670 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19673 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19676 XLP is mostly like XLR, with the prominent exception that it is
19677 MIPS64R2 rather than MIPS64. */
19678 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19685 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19686 with a final "000" replaced by "k". Ignore case.
19688 Note: this function is shared between GCC and GAS. */
19691 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19693 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19694 given
++, canonical
++;
19696 return ((*given
== 0 && *canonical
== 0)
19697 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19701 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19702 CPU name. We've traditionally allowed a lot of variation here.
19704 Note: this function is shared between GCC and GAS. */
19707 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19709 /* First see if the name matches exactly, or with a final "000"
19710 turned into "k". */
19711 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19714 /* If not, try comparing based on numerical designation alone.
19715 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19716 if (TOLOWER (*given
) == 'r')
19718 if (!ISDIGIT (*given
))
19721 /* Skip over some well-known prefixes in the canonical name,
19722 hoping to find a number there too. */
19723 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19725 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19727 else if (TOLOWER (canonical
[0]) == 'r')
19730 return mips_strict_matching_cpu_name_p (canonical
, given
);
19734 /* Parse an option that takes the name of a processor as its argument.
19735 OPTION is the name of the option and CPU_STRING is the argument.
19736 Return the corresponding processor enumeration if the CPU_STRING is
19737 recognized, otherwise report an error and return null.
19739 A similar function exists in GCC. */
19741 static const struct mips_cpu_info
*
19742 mips_parse_cpu (const char *option
, const char *cpu_string
)
19744 const struct mips_cpu_info
*p
;
19746 /* 'from-abi' selects the most compatible architecture for the given
19747 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19748 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19749 version. Look first at the -mgp options, if given, otherwise base
19750 the choice on MIPS_DEFAULT_64BIT.
19752 Treat NO_ABI like the EABIs. One reason to do this is that the
19753 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19754 architecture. This code picks MIPS I for 'mips' and MIPS III for
19755 'mips64', just as we did in the days before 'from-abi'. */
19756 if (strcasecmp (cpu_string
, "from-abi") == 0)
19758 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19759 return mips_cpu_info_from_isa (ISA_MIPS1
);
19761 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19762 return mips_cpu_info_from_isa (ISA_MIPS3
);
19764 if (file_mips_gp32
>= 0)
19765 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19767 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19772 /* 'default' has traditionally been a no-op. Probably not very useful. */
19773 if (strcasecmp (cpu_string
, "default") == 0)
19776 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19777 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19780 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19784 /* Return the canonical processor information for ISA (a member of the
19785 ISA_MIPS* enumeration). */
19787 static const struct mips_cpu_info
*
19788 mips_cpu_info_from_isa (int isa
)
19792 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19793 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19794 && isa
== mips_cpu_info_table
[i
].isa
)
19795 return (&mips_cpu_info_table
[i
]);
19800 static const struct mips_cpu_info
*
19801 mips_cpu_info_from_arch (int arch
)
19805 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19806 if (arch
== mips_cpu_info_table
[i
].cpu
)
19807 return (&mips_cpu_info_table
[i
]);
19813 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19817 fprintf (stream
, "%24s", "");
19822 fprintf (stream
, ", ");
19826 if (*col_p
+ strlen (string
) > 72)
19828 fprintf (stream
, "\n%24s", "");
19832 fprintf (stream
, "%s", string
);
19833 *col_p
+= strlen (string
);
19839 md_show_usage (FILE *stream
)
19844 fprintf (stream
, _("\
19846 -EB generate big endian output\n\
19847 -EL generate little endian output\n\
19848 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19849 -G NUM allow referencing objects up to NUM bytes\n\
19850 implicitly with the gp register [default 8]\n"));
19851 fprintf (stream
, _("\
19852 -mips1 generate MIPS ISA I instructions\n\
19853 -mips2 generate MIPS ISA II instructions\n\
19854 -mips3 generate MIPS ISA III instructions\n\
19855 -mips4 generate MIPS ISA IV instructions\n\
19856 -mips5 generate MIPS ISA V instructions\n\
19857 -mips32 generate MIPS32 ISA instructions\n\
19858 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19859 -mips64 generate MIPS64 ISA instructions\n\
19860 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19861 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19865 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19866 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19867 show (stream
, "from-abi", &column
, &first
);
19868 fputc ('\n', stream
);
19870 fprintf (stream
, _("\
19871 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19872 -no-mCPU don't generate code specific to CPU.\n\
19873 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19877 show (stream
, "3900", &column
, &first
);
19878 show (stream
, "4010", &column
, &first
);
19879 show (stream
, "4100", &column
, &first
);
19880 show (stream
, "4650", &column
, &first
);
19881 fputc ('\n', stream
);
19883 fprintf (stream
, _("\
19884 -mips16 generate mips16 instructions\n\
19885 -no-mips16 do not generate mips16 instructions\n"));
19886 fprintf (stream
, _("\
19887 -mmicromips generate microMIPS instructions\n\
19888 -mno-micromips do not generate microMIPS instructions\n"));
19889 fprintf (stream
, _("\
19890 -msmartmips generate smartmips instructions\n\
19891 -mno-smartmips do not generate smartmips instructions\n"));
19892 fprintf (stream
, _("\
19893 -mdsp generate DSP instructions\n\
19894 -mno-dsp do not generate DSP instructions\n"));
19895 fprintf (stream
, _("\
19896 -mdspr2 generate DSP R2 instructions\n\
19897 -mno-dspr2 do not generate DSP R2 instructions\n"));
19898 fprintf (stream
, _("\
19899 -mmt generate MT instructions\n\
19900 -mno-mt do not generate MT instructions\n"));
19901 fprintf (stream
, _("\
19902 -mmcu generate MCU instructions\n\
19903 -mno-mcu do not generate MCU instructions\n"));
19904 fprintf (stream
, _("\
19905 -mvirt generate Virtualization instructions\n\
19906 -mno-virt do not generate Virtualization instructions\n"));
19907 fprintf (stream
, _("\
19908 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19909 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19910 -mfix-vr4120 work around certain VR4120 errata\n\
19911 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19912 -mfix-24k insert a nop after ERET and DERET instructions\n\
19913 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19914 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19915 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19916 -msym32 assume all symbols have 32-bit values\n\
19917 -O0 remove unneeded NOPs, do not swap branches\n\
19918 -O remove unneeded NOPs and swap branches\n\
19919 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19920 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19921 fprintf (stream
, _("\
19922 -mhard-float allow floating-point instructions\n\
19923 -msoft-float do not allow floating-point instructions\n\
19924 -msingle-float only allow 32-bit floating-point operations\n\
19925 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19926 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19927 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19930 fprintf (stream
, _("\
19931 -KPIC, -call_shared generate SVR4 position independent code\n\
19932 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19933 -mvxworks-pic generate VxWorks position independent code\n\
19934 -non_shared do not generate code that can operate with DSOs\n\
19935 -xgot assume a 32 bit GOT\n\
19936 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19937 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19938 position dependent (non shared) code\n\
19939 -mabi=ABI create ABI conformant object file for:\n"));
19943 show (stream
, "32", &column
, &first
);
19944 show (stream
, "o64", &column
, &first
);
19945 show (stream
, "n32", &column
, &first
);
19946 show (stream
, "64", &column
, &first
);
19947 show (stream
, "eabi", &column
, &first
);
19949 fputc ('\n', stream
);
19951 fprintf (stream
, _("\
19952 -32 create o32 ABI object file (default)\n\
19953 -n32 create n32 ABI object file\n\
19954 -64 create 64 ABI object file\n"));
19960 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19962 if (HAVE_64BIT_SYMBOLS
)
19963 return dwarf2_format_64bit_irix
;
19965 return dwarf2_format_32bit
;
19970 mips_dwarf2_addr_size (void)
19972 if (HAVE_64BIT_OBJECTS
)
19978 /* Standard calling conventions leave the CFA at SP on entry. */
19980 mips_cfi_frame_initial_instructions (void)
19982 cfi_add_CFA_def_cfa_register (SP
);
19986 tc_mips_regname_to_dw2regnum (char *regname
)
19988 unsigned int regnum
= -1;
19991 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))