1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros
;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32
= -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32
= -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts
=
194 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16
;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d
;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx
;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch
= CPU_UNKNOWN
;
220 static const char *mips_arch_string
;
221 static const struct mips_cpu_info
*mips_arch_info
;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune
= CPU_UNKNOWN
;
226 static const char *mips_tune_string
;
227 static const struct mips_cpu_info
*mips_tune_info
;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode
= 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 /* Return true if ISA supports 64-bit right rotate (dror et al.)
265 #define ISA_HAS_DROR(ISA) ( \
269 /* Return true if ISA supports 32-bit right rotate (ror et al.)
271 #define ISA_HAS_ROR(ISA) ( \
272 (ISA) == ISA_MIPS32R2 \
275 #define HAVE_32BIT_GPRS \
276 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
278 #define HAVE_32BIT_FPRS \
279 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
281 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
282 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
284 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
286 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
288 /* We can only have 64bit addresses if the object file format
290 #define HAVE_32BIT_ADDRESSES \
292 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS) \
294 && mips_pic != EMBEDDED_PIC))
296 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
298 /* Return true if the given CPU supports the MIPS16 ASE. */
299 #define CPU_HAS_MIPS16(cpu) \
300 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
301 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
303 /* Return true if the given CPU supports the MIPS3D ASE. */
304 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
307 /* Return true if the given CPU supports the MDMX ASE. */
308 #define CPU_HAS_MDMX(cpu) (FALSE \
311 /* True if CPU has a dror instruction. */
312 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
314 /* True if CPU has a ror instruction. */
315 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
317 /* Whether the processor uses hardware interlocks to protect
318 reads from the HI and LO registers, and thus does not
319 require nops to be inserted. */
321 #define hilo_interlocks (mips_arch == CPU_R4010 \
322 || mips_arch == CPU_VR5500 \
323 || mips_arch == CPU_SB1 \
326 /* Whether the processor uses hardware interlocks to protect reads
327 from the GPRs, and thus does not require nops to be inserted. */
328 #define gpr_interlocks \
329 (mips_opts.isa != ISA_MIPS1 \
330 || mips_arch == CPU_VR5400 \
331 || mips_arch == CPU_VR5500 \
332 || mips_arch == CPU_R3900)
334 /* As with other "interlocks" this is used by hardware that has FP
335 (co-processor) interlocks. */
336 /* Itbl support may require additional care here. */
337 #define cop_interlocks (mips_arch == CPU_R4300 \
338 || mips_arch == CPU_VR5400 \
339 || mips_arch == CPU_VR5500 \
340 || mips_arch == CPU_SB1 \
343 /* Is this a mfhi or mflo instruction? */
344 #define MF_HILO_INSN(PINFO) \
345 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
347 /* MIPS PIC level. */
349 enum mips_pic_level mips_pic
;
351 /* Warn about all NOPS that the assembler generates. */
352 static int warn_nops
= 0;
354 /* 1 if we should generate 32 bit offsets from the $gp register in
355 SVR4_PIC mode. Currently has no meaning in other modes. */
356 static int mips_big_got
= 0;
358 /* 1 if trap instructions should used for overflow rather than break
360 static int mips_trap
= 0;
362 /* 1 if double width floating point constants should not be constructed
363 by assembling two single width halves into two single width floating
364 point registers which just happen to alias the double width destination
365 register. On some architectures this aliasing can be disabled by a bit
366 in the status register, and the setting of this bit cannot be determined
367 automatically at assemble time. */
368 static int mips_disable_float_construction
;
370 /* Non-zero if any .set noreorder directives were used. */
372 static int mips_any_noreorder
;
374 /* Non-zero if nops should be inserted when the register referenced in
375 an mfhi/mflo instruction is read in the next two instructions. */
376 static int mips_7000_hilo_fix
;
378 /* The size of the small data section. */
379 static unsigned int g_switch_value
= 8;
380 /* Whether the -G option was used. */
381 static int g_switch_seen
= 0;
386 /* If we can determine in advance that GP optimization won't be
387 possible, we can skip the relaxation stuff that tries to produce
388 GP-relative references. This makes delay slot optimization work
391 This function can only provide a guess, but it seems to work for
392 gcc output. It needs to guess right for gcc, otherwise gcc
393 will put what it thinks is a GP-relative instruction in a branch
396 I don't know if a fix is needed for the SVR4_PIC mode. I've only
397 fixed it for the non-PIC mode. KR 95/04/07 */
398 static int nopic_need_relax
PARAMS ((symbolS
*, int));
400 /* handle of the OPCODE hash table */
401 static struct hash_control
*op_hash
= NULL
;
403 /* The opcode hash table we use for the mips16. */
404 static struct hash_control
*mips16_op_hash
= NULL
;
406 /* This array holds the chars that always start a comment. If the
407 pre-processor is disabled, these aren't very useful */
408 const char comment_chars
[] = "#";
410 /* This array holds the chars that only start a comment at the beginning of
411 a line. If the line seems to have the form '# 123 filename'
412 .line and .file directives will appear in the pre-processed output */
413 /* Note that input_file.c hand checks for '#' at the beginning of the
414 first line of the input file. This is because the compiler outputs
415 #NO_APP at the beginning of its output. */
416 /* Also note that C style comments are always supported. */
417 const char line_comment_chars
[] = "#";
419 /* This array holds machine specific line separator characters. */
420 const char line_separator_chars
[] = ";";
422 /* Chars that can be used to separate mant from exp in floating point nums */
423 const char EXP_CHARS
[] = "eE";
425 /* Chars that mean this number is a floating point constant */
428 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
430 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
431 changed in read.c . Ideally it shouldn't have to know about it at all,
432 but nothing is ideal around here.
435 static char *insn_error
;
437 static int auto_align
= 1;
439 /* When outputting SVR4 PIC code, the assembler needs to know the
440 offset in the stack frame from which to restore the $gp register.
441 This is set by the .cprestore pseudo-op, and saved in this
443 static offsetT mips_cprestore_offset
= -1;
445 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
446 more optimizations, it can use a register value instead of a memory-saved
447 offset and even an other register than $gp as global pointer. */
448 static offsetT mips_cpreturn_offset
= -1;
449 static int mips_cpreturn_register
= -1;
450 static int mips_gp_register
= GP
;
451 static int mips_gprel_offset
= 0;
453 /* Whether mips_cprestore_offset has been set in the current function
454 (or whether it has already been warned about, if not). */
455 static int mips_cprestore_valid
= 0;
457 /* This is the register which holds the stack frame, as set by the
458 .frame pseudo-op. This is needed to implement .cprestore. */
459 static int mips_frame_reg
= SP
;
461 /* Whether mips_frame_reg has been set in the current function
462 (or whether it has already been warned about, if not). */
463 static int mips_frame_reg_valid
= 0;
465 /* To output NOP instructions correctly, we need to keep information
466 about the previous two instructions. */
468 /* Whether we are optimizing. The default value of 2 means to remove
469 unneeded NOPs and swap branch instructions when possible. A value
470 of 1 means to not swap branches. A value of 0 means to always
472 static int mips_optimize
= 2;
474 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
475 equivalent to seeing no -g option at all. */
476 static int mips_debug
= 0;
478 /* The previous instruction. */
479 static struct mips_cl_insn prev_insn
;
481 /* The instruction before prev_insn. */
482 static struct mips_cl_insn prev_prev_insn
;
484 /* If we don't want information for prev_insn or prev_prev_insn, we
485 point the insn_mo field at this dummy integer. */
486 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
488 /* Non-zero if prev_insn is valid. */
489 static int prev_insn_valid
;
491 /* The frag for the previous instruction. */
492 static struct frag
*prev_insn_frag
;
494 /* The offset into prev_insn_frag for the previous instruction. */
495 static long prev_insn_where
;
497 /* The reloc type for the previous instruction, if any. */
498 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
500 /* The reloc for the previous instruction, if any. */
501 static fixS
*prev_insn_fixp
[3];
503 /* Non-zero if the previous instruction was in a delay slot. */
504 static int prev_insn_is_delay_slot
;
506 /* Non-zero if the previous instruction was in a .set noreorder. */
507 static int prev_insn_unreordered
;
509 /* Non-zero if the previous instruction uses an extend opcode (if
511 static int prev_insn_extended
;
513 /* Non-zero if the previous previous instruction was in a .set
515 static int prev_prev_insn_unreordered
;
517 /* If this is set, it points to a frag holding nop instructions which
518 were inserted before the start of a noreorder section. If those
519 nops turn out to be unnecessary, the size of the frag can be
521 static fragS
*prev_nop_frag
;
523 /* The number of nop instructions we created in prev_nop_frag. */
524 static int prev_nop_frag_holds
;
526 /* The number of nop instructions that we know we need in
528 static int prev_nop_frag_required
;
530 /* The number of instructions we've seen since prev_nop_frag. */
531 static int prev_nop_frag_since
;
533 /* For ECOFF and ELF, relocations against symbols are done in two
534 parts, with a HI relocation and a LO relocation. Each relocation
535 has only 16 bits of space to store an addend. This means that in
536 order for the linker to handle carries correctly, it must be able
537 to locate both the HI and the LO relocation. This means that the
538 relocations must appear in order in the relocation table.
540 In order to implement this, we keep track of each unmatched HI
541 relocation. We then sort them so that they immediately precede the
542 corresponding LO relocation. */
547 struct mips_hi_fixup
*next
;
550 /* The section this fixup is in. */
554 /* The list of unmatched HI relocs. */
556 static struct mips_hi_fixup
*mips_hi_fixup_list
;
558 /* Map normal MIPS register numbers to mips16 register numbers. */
560 #define X ILLEGAL_REG
561 static const int mips32_to_16_reg_map
[] =
563 X
, X
, 2, 3, 4, 5, 6, 7,
564 X
, X
, X
, X
, X
, X
, X
, X
,
565 0, 1, X
, X
, X
, X
, X
, X
,
566 X
, X
, X
, X
, X
, X
, X
, X
570 /* Map mips16 register numbers to normal MIPS register numbers. */
572 static const unsigned int mips16_to_32_reg_map
[] =
574 16, 17, 2, 3, 4, 5, 6, 7
577 static int mips_fix_4122_bugs
;
579 /* We don't relax branches by default, since this causes us to expand
580 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
581 fail to compute the offset before expanding the macro to the most
582 efficient expansion. */
584 static int mips_relax_branch
;
586 /* Since the MIPS does not have multiple forms of PC relative
587 instructions, we do not have to do relaxing as is done on other
588 platforms. However, we do have to handle GP relative addressing
589 correctly, which turns out to be a similar problem.
591 Every macro that refers to a symbol can occur in (at least) two
592 forms, one with GP relative addressing and one without. For
593 example, loading a global variable into a register generally uses
594 a macro instruction like this:
596 If i can be addressed off the GP register (this is true if it is in
597 the .sbss or .sdata section, or if it is known to be smaller than
598 the -G argument) this will generate the following instruction:
600 This instruction will use a GPREL reloc. If i can not be addressed
601 off the GP register, the following instruction sequence will be used:
604 In this case the first instruction will have a HI16 reloc, and the
605 second reloc will have a LO16 reloc. Both relocs will be against
608 The issue here is that we may not know whether i is GP addressable
609 until after we see the instruction that uses it. Therefore, we
610 want to be able to choose the final instruction sequence only at
611 the end of the assembly. This is similar to the way other
612 platforms choose the size of a PC relative instruction only at the
615 When generating position independent code we do not use GP
616 addressing in quite the same way, but the issue still arises as
617 external symbols and local symbols must be handled differently.
619 We handle these issues by actually generating both possible
620 instruction sequences. The longer one is put in a frag_var with
621 type rs_machine_dependent. We encode what to do with the frag in
622 the subtype field. We encode (1) the number of existing bytes to
623 replace, (2) the number of new bytes to use, (3) the offset from
624 the start of the existing bytes to the first reloc we must generate
625 (that is, the offset is applied from the start of the existing
626 bytes after they are replaced by the new bytes, if any), (4) the
627 offset from the start of the existing bytes to the second reloc,
628 (5) whether a third reloc is needed (the third reloc is always four
629 bytes after the second reloc), and (6) whether to warn if this
630 variant is used (this is sometimes needed if .set nomacro or .set
631 noat is in effect). All these numbers are reasonably small.
633 Generating two instruction sequences must be handled carefully to
634 ensure that delay slots are handled correctly. Fortunately, there
635 are a limited number of cases. When the second instruction
636 sequence is generated, append_insn is directed to maintain the
637 existing delay slot information, so it continues to apply to any
638 code after the second instruction sequence. This means that the
639 second instruction sequence must not impose any requirements not
640 required by the first instruction sequence.
642 These variant frags are then handled in functions called by the
643 machine independent code. md_estimate_size_before_relax returns
644 the final size of the frag. md_convert_frag sets up the final form
645 of the frag. tc_gen_reloc adjust the first reloc and adds a second
647 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
651 | (((reloc1) + 64) << 9) \
652 | (((reloc2) + 64) << 2) \
653 | ((reloc3) ? (1 << 1) : 0) \
655 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
656 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
657 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
658 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
659 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
660 #define RELAX_WARN(i) ((i) & 1)
662 /* Branch without likely bit. If label is out of range, we turn:
664 beq reg1, reg2, label
674 with the following opcode replacements:
681 bltzal <-> bgezal (with jal label instead of j label)
683 Even though keeping the delay slot instruction in the delay slot of
684 the branch would be more efficient, it would be very tricky to do
685 correctly, because we'd have to introduce a variable frag *after*
686 the delay slot instruction, and expand that instead. Let's do it
687 the easy way for now, even if the branch-not-taken case now costs
688 one additional instruction. Out-of-range branches are not supposed
689 to be common, anyway.
691 Branch likely. If label is out of range, we turn:
693 beql reg1, reg2, label
694 delay slot (annulled if branch not taken)
703 delay slot (executed only if branch taken)
706 It would be possible to generate a shorter sequence by losing the
707 likely bit, generating something like:
712 delay slot (executed only if branch taken)
724 bltzall -> bgezal (with jal label instead of j label)
725 bgezall -> bltzal (ditto)
728 but it's not clear that it would actually improve performance. */
729 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
732 | ((toofar) ? 1 : 0) \
734 | ((likely) ? 4 : 0) \
735 | ((uncond) ? 8 : 0)))
736 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
737 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
738 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
739 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
740 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
742 /* For mips16 code, we use an entirely different form of relaxation.
743 mips16 supports two versions of most instructions which take
744 immediate values: a small one which takes some small value, and a
745 larger one which takes a 16 bit value. Since branches also follow
746 this pattern, relaxing these values is required.
748 We can assemble both mips16 and normal MIPS code in a single
749 object. Therefore, we need to support this type of relaxation at
750 the same time that we support the relaxation described above. We
751 use the high bit of the subtype field to distinguish these cases.
753 The information we store for this type of relaxation is the
754 argument code found in the opcode file for this relocation, whether
755 the user explicitly requested a small or extended form, and whether
756 the relocation is in a jump or jal delay slot. That tells us the
757 size of the value, and how it should be stored. We also store
758 whether the fragment is considered to be extended or not. We also
759 store whether this is known to be a branch to a different section,
760 whether we have tried to relax this frag yet, and whether we have
761 ever extended a PC relative fragment because of a shift count. */
762 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
765 | ((small) ? 0x100 : 0) \
766 | ((ext) ? 0x200 : 0) \
767 | ((dslot) ? 0x400 : 0) \
768 | ((jal_dslot) ? 0x800 : 0))
769 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
770 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
771 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
772 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
773 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
774 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
775 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
776 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
777 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
778 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
779 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
780 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
782 /* Is the given value a sign-extended 32-bit value? */
783 #define IS_SEXT_32BIT_NUM(x) \
784 (((x) &~ (offsetT) 0x7fffffff) == 0 \
785 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
787 /* Is the given value a sign-extended 16-bit value? */
788 #define IS_SEXT_16BIT_NUM(x) \
789 (((x) &~ (offsetT) 0x7fff) == 0 \
790 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
793 /* Prototypes for static functions. */
796 #define internalError() \
797 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
799 #define internalError() as_fatal (_("MIPS internal Error"));
802 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
804 static inline bfd_boolean reloc_needs_lo_p
805 PARAMS ((bfd_reloc_code_real_type
));
806 static inline bfd_boolean fixup_has_matching_lo_p
808 static int insn_uses_reg
809 PARAMS ((struct mips_cl_insn
*ip
, unsigned int reg
,
810 enum mips_regclass
class));
811 static int reg_needs_delay
812 PARAMS ((unsigned int));
813 static void mips16_mark_labels
815 static void append_insn
816 PARAMS ((char *place
, struct mips_cl_insn
* ip
, expressionS
* p
,
817 bfd_reloc_code_real_type
*r
));
818 static void mips_no_prev_insn
820 static void mips_emit_delays
821 PARAMS ((bfd_boolean
));
823 static void macro_build
824 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *name
,
825 const char *fmt
, ...));
827 static void macro_build ();
829 static void mips16_macro_build
830 PARAMS ((char *, int *, expressionS
*, const char *, const char *, va_list));
831 static void macro_build_jalr
832 PARAMS ((int, expressionS
*));
833 static void macro_build_lui
834 PARAMS ((char *place
, int *counter
, expressionS
* ep
, int regnum
));
835 static void macro_build_ldst_constoffset
836 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *op
,
837 int valreg
, int breg
));
839 PARAMS ((int *counter
, int reg
, int unsignedp
));
840 static void check_absolute_expr
841 PARAMS ((struct mips_cl_insn
* ip
, expressionS
*));
842 static void load_register
843 PARAMS ((int *, int, expressionS
*, int));
844 static void load_address
845 PARAMS ((int *, int, expressionS
*, int *));
846 static void move_register
847 PARAMS ((int *, int, int));
849 PARAMS ((struct mips_cl_insn
* ip
));
850 static void mips16_macro
851 PARAMS ((struct mips_cl_insn
* ip
));
852 #ifdef LOSING_COMPILER
854 PARAMS ((struct mips_cl_insn
* ip
));
857 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
858 static void mips16_ip
859 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
860 static void mips16_immed
861 PARAMS ((char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
,
862 bfd_boolean
, unsigned long *, bfd_boolean
*, unsigned short *));
863 static bfd_boolean parse_relocation
864 PARAMS ((char **, bfd_reloc_code_real_type
*));
865 static size_t my_getSmallExpression
866 PARAMS ((expressionS
*, bfd_reloc_code_real_type
*, char *));
867 static void my_getExpression
868 PARAMS ((expressionS
*, char *));
870 static int support_64bit_objects
873 static void mips_set_option_string
874 PARAMS ((const char **, const char *));
875 static symbolS
*get_symbol
877 static void mips_align
878 PARAMS ((int to
, int fill
, symbolS
*label
));
881 static void s_change_sec
883 static void s_change_section
887 static void s_float_cons
889 static void s_mips_globl
893 static void s_mipsset
895 static void s_abicalls
899 static void s_cpsetup
901 static void s_cplocal
903 static void s_cprestore
905 static void s_cpreturn
907 static void s_gpvalue
911 static void s_gpdword
917 static void md_obj_begin
919 static void md_obj_end
921 static long get_number
923 static void s_mips_ent
925 static void s_mips_end
927 static void s_mips_frame
929 static void s_mips_mask
931 static void s_mips_stab
933 static void s_mips_weakext
935 static void s_mips_file
937 static void s_mips_loc
939 static bfd_boolean pic_need_relax
940 PARAMS ((symbolS
*, asection
*));
941 static int mips16_extended_frag
942 PARAMS ((fragS
*, asection
*, long));
943 static int relaxed_branch_length (fragS
*, asection
*, int);
944 static int validate_mips_insn
945 PARAMS ((const struct mips_opcode
*));
947 PARAMS ((FILE *, const char *, int *, int *));
949 static int mips_need_elf_addend_fixup
953 /* Table and functions used to map between CPU/ISA names, and
954 ISA levels, and CPU numbers. */
958 const char *name
; /* CPU or ISA name. */
959 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
960 int isa
; /* ISA level. */
961 int cpu
; /* CPU number (default CPU if ISA). */
964 static void mips_set_architecture
965 PARAMS ((const struct mips_cpu_info
*));
966 static void mips_set_tune
967 PARAMS ((const struct mips_cpu_info
*));
968 static bfd_boolean mips_strict_matching_cpu_name_p
969 PARAMS ((const char *, const char *));
970 static bfd_boolean mips_matching_cpu_name_p
971 PARAMS ((const char *, const char *));
972 static const struct mips_cpu_info
*mips_parse_cpu
973 PARAMS ((const char *, const char *));
974 static const struct mips_cpu_info
*mips_cpu_info_from_isa
979 The following pseudo-ops from the Kane and Heinrich MIPS book
980 should be defined here, but are currently unsupported: .alias,
981 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
983 The following pseudo-ops from the Kane and Heinrich MIPS book are
984 specific to the type of debugging information being generated, and
985 should be defined by the object format: .aent, .begin, .bend,
986 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
989 The following pseudo-ops from the Kane and Heinrich MIPS book are
990 not MIPS CPU specific, but are also not specific to the object file
991 format. This file is probably the best place to define them, but
992 they are not currently supported: .asm0, .endr, .lab, .repeat,
995 static const pseudo_typeS mips_pseudo_table
[] =
997 /* MIPS specific pseudo-ops. */
998 {"option", s_option
, 0},
999 {"set", s_mipsset
, 0},
1000 {"rdata", s_change_sec
, 'r'},
1001 {"sdata", s_change_sec
, 's'},
1002 {"livereg", s_ignore
, 0},
1003 {"abicalls", s_abicalls
, 0},
1004 {"cpload", s_cpload
, 0},
1005 {"cpsetup", s_cpsetup
, 0},
1006 {"cplocal", s_cplocal
, 0},
1007 {"cprestore", s_cprestore
, 0},
1008 {"cpreturn", s_cpreturn
, 0},
1009 {"gpvalue", s_gpvalue
, 0},
1010 {"gpword", s_gpword
, 0},
1011 {"gpdword", s_gpdword
, 0},
1012 {"cpadd", s_cpadd
, 0},
1013 {"insn", s_insn
, 0},
1015 /* Relatively generic pseudo-ops that happen to be used on MIPS
1017 {"asciiz", stringer
, 1},
1018 {"bss", s_change_sec
, 'b'},
1020 {"half", s_cons
, 1},
1021 {"dword", s_cons
, 3},
1022 {"weakext", s_mips_weakext
, 0},
1024 /* These pseudo-ops are defined in read.c, but must be overridden
1025 here for one reason or another. */
1026 {"align", s_align
, 0},
1027 {"byte", s_cons
, 0},
1028 {"data", s_change_sec
, 'd'},
1029 {"double", s_float_cons
, 'd'},
1030 {"float", s_float_cons
, 'f'},
1031 {"globl", s_mips_globl
, 0},
1032 {"global", s_mips_globl
, 0},
1033 {"hword", s_cons
, 1},
1035 {"long", s_cons
, 2},
1036 {"octa", s_cons
, 4},
1037 {"quad", s_cons
, 3},
1038 {"section", s_change_section
, 0},
1039 {"short", s_cons
, 1},
1040 {"single", s_float_cons
, 'f'},
1041 {"stabn", s_mips_stab
, 'n'},
1042 {"text", s_change_sec
, 't'},
1043 {"word", s_cons
, 2},
1045 { "extern", ecoff_directive_extern
, 0},
1050 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1052 /* These pseudo-ops should be defined by the object file format.
1053 However, a.out doesn't support them, so we have versions here. */
1054 {"aent", s_mips_ent
, 1},
1055 {"bgnb", s_ignore
, 0},
1056 {"end", s_mips_end
, 0},
1057 {"endb", s_ignore
, 0},
1058 {"ent", s_mips_ent
, 0},
1059 {"file", s_mips_file
, 0},
1060 {"fmask", s_mips_mask
, 'F'},
1061 {"frame", s_mips_frame
, 0},
1062 {"loc", s_mips_loc
, 0},
1063 {"mask", s_mips_mask
, 'R'},
1064 {"verstamp", s_ignore
, 0},
1068 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
1073 pop_insert (mips_pseudo_table
);
1074 if (! ECOFF_DEBUGGING
)
1075 pop_insert (mips_nonecoff_pseudo_table
);
1078 /* Symbols labelling the current insn. */
1080 struct insn_label_list
1082 struct insn_label_list
*next
;
1086 static struct insn_label_list
*insn_labels
;
1087 static struct insn_label_list
*free_insn_labels
;
1089 static void mips_clear_insn_labels
PARAMS ((void));
1092 mips_clear_insn_labels ()
1094 register struct insn_label_list
**pl
;
1096 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1102 static char *expr_end
;
1104 /* Expressions which appear in instructions. These are set by
1107 static expressionS imm_expr
;
1108 static expressionS offset_expr
;
1110 /* Relocs associated with imm_expr and offset_expr. */
1112 static bfd_reloc_code_real_type imm_reloc
[3]
1113 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1114 static bfd_reloc_code_real_type offset_reloc
[3]
1115 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1117 /* These are set by mips16_ip if an explicit extension is used. */
1119 static bfd_boolean mips16_small
, mips16_ext
;
1122 /* The pdr segment for per procedure frame/regmask info. Not used for
1125 static segT pdr_seg
;
1128 /* The default target format to use. */
1131 mips_target_format ()
1133 switch (OUTPUT_FLAVOR
)
1135 case bfd_target_aout_flavour
:
1136 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1137 case bfd_target_ecoff_flavour
:
1138 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1139 case bfd_target_coff_flavour
:
1141 case bfd_target_elf_flavour
:
1143 /* This is traditional mips. */
1144 return (target_big_endian
1145 ? (HAVE_64BIT_OBJECTS
1146 ? "elf64-tradbigmips"
1148 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1149 : (HAVE_64BIT_OBJECTS
1150 ? "elf64-tradlittlemips"
1152 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1154 return (target_big_endian
1155 ? (HAVE_64BIT_OBJECTS
1158 ? "elf32-nbigmips" : "elf32-bigmips"))
1159 : (HAVE_64BIT_OBJECTS
1160 ? "elf64-littlemips"
1162 ? "elf32-nlittlemips" : "elf32-littlemips")));
1170 /* This function is called once, at assembler startup time. It should
1171 set up all the tables, etc. that the MD part of the assembler will need. */
1176 register const char *retval
= NULL
;
1180 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1181 as_warn (_("Could not set architecture and machine"));
1183 op_hash
= hash_new ();
1185 for (i
= 0; i
< NUMOPCODES
;)
1187 const char *name
= mips_opcodes
[i
].name
;
1189 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1192 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1193 mips_opcodes
[i
].name
, retval
);
1194 /* Probably a memory allocation problem? Give up now. */
1195 as_fatal (_("Broken assembler. No assembly attempted."));
1199 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1201 if (!validate_mips_insn (&mips_opcodes
[i
]))
1206 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1209 mips16_op_hash
= hash_new ();
1212 while (i
< bfd_mips16_num_opcodes
)
1214 const char *name
= mips16_opcodes
[i
].name
;
1216 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1218 as_fatal (_("internal: can't hash `%s': %s"),
1219 mips16_opcodes
[i
].name
, retval
);
1222 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1223 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1224 != mips16_opcodes
[i
].match
))
1226 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1227 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1232 while (i
< bfd_mips16_num_opcodes
1233 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1237 as_fatal (_("Broken assembler. No assembly attempted."));
1239 /* We add all the general register names to the symbol table. This
1240 helps us detect invalid uses of them. */
1241 for (i
= 0; i
< 32; i
++)
1245 sprintf (buf
, "$%d", i
);
1246 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1247 &zero_address_frag
));
1249 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1250 &zero_address_frag
));
1251 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1252 &zero_address_frag
));
1253 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1254 &zero_address_frag
));
1255 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1256 &zero_address_frag
));
1257 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1258 &zero_address_frag
));
1259 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1260 &zero_address_frag
));
1261 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1262 &zero_address_frag
));
1263 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1264 &zero_address_frag
));
1265 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1266 &zero_address_frag
));
1268 /* If we don't add these register names to the symbol table, they
1269 may end up being added as regular symbols by operand(), and then
1270 make it to the object file as undefined in case they're not
1271 regarded as local symbols. They're local in o32, since `$' is a
1272 local symbol prefix, but not in n32 or n64. */
1273 for (i
= 0; i
< 8; i
++)
1277 sprintf (buf
, "$fcc%i", i
);
1278 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1279 &zero_address_frag
));
1282 mips_no_prev_insn (FALSE
);
1285 mips_cprmask
[0] = 0;
1286 mips_cprmask
[1] = 0;
1287 mips_cprmask
[2] = 0;
1288 mips_cprmask
[3] = 0;
1290 /* set the default alignment for the text section (2**2) */
1291 record_alignment (text_section
, 2);
1293 if (USE_GLOBAL_POINTER_OPT
)
1294 bfd_set_gp_size (stdoutput
, g_switch_value
);
1296 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1298 /* On a native system, sections must be aligned to 16 byte
1299 boundaries. When configured for an embedded ELF target, we
1301 if (strcmp (TARGET_OS
, "elf") != 0)
1303 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1304 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1305 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1308 /* Create a .reginfo section for register masks and a .mdebug
1309 section for debugging information. */
1317 subseg
= now_subseg
;
1319 /* The ABI says this section should be loaded so that the
1320 running program can access it. However, we don't load it
1321 if we are configured for an embedded target */
1322 flags
= SEC_READONLY
| SEC_DATA
;
1323 if (strcmp (TARGET_OS
, "elf") != 0)
1324 flags
|= SEC_ALLOC
| SEC_LOAD
;
1326 if (mips_abi
!= N64_ABI
)
1328 sec
= subseg_new (".reginfo", (subsegT
) 0);
1330 bfd_set_section_flags (stdoutput
, sec
, flags
);
1331 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1334 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1339 /* The 64-bit ABI uses a .MIPS.options section rather than
1340 .reginfo section. */
1341 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1342 bfd_set_section_flags (stdoutput
, sec
, flags
);
1343 bfd_set_section_alignment (stdoutput
, sec
, 3);
1346 /* Set up the option header. */
1348 Elf_Internal_Options opthdr
;
1351 opthdr
.kind
= ODK_REGINFO
;
1352 opthdr
.size
= (sizeof (Elf_External_Options
)
1353 + sizeof (Elf64_External_RegInfo
));
1356 f
= frag_more (sizeof (Elf_External_Options
));
1357 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1358 (Elf_External_Options
*) f
);
1360 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1365 if (ECOFF_DEBUGGING
)
1367 sec
= subseg_new (".mdebug", (subsegT
) 0);
1368 (void) bfd_set_section_flags (stdoutput
, sec
,
1369 SEC_HAS_CONTENTS
| SEC_READONLY
);
1370 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1373 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1375 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1376 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1377 SEC_READONLY
| SEC_RELOC
1379 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1383 subseg_set (seg
, subseg
);
1387 if (! ECOFF_DEBUGGING
)
1394 if (! ECOFF_DEBUGGING
)
1402 struct mips_cl_insn insn
;
1403 bfd_reloc_code_real_type unused_reloc
[3]
1404 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1406 imm_expr
.X_op
= O_absent
;
1407 offset_expr
.X_op
= O_absent
;
1408 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1409 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1410 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1411 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1412 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1413 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1415 if (mips_opts
.mips16
)
1416 mips16_ip (str
, &insn
);
1419 mips_ip (str
, &insn
);
1420 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1421 str
, insn
.insn_opcode
));
1426 as_bad ("%s `%s'", insn_error
, str
);
1430 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1432 if (mips_opts
.mips16
)
1433 mips16_macro (&insn
);
1439 if (imm_expr
.X_op
!= O_absent
)
1440 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
);
1441 else if (offset_expr
.X_op
!= O_absent
)
1442 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
);
1444 append_insn (NULL
, &insn
, NULL
, unused_reloc
);
1448 /* Return true if the given relocation might need a matching %lo().
1449 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1450 applied to local symbols. */
1452 static inline bfd_boolean
1453 reloc_needs_lo_p (reloc
)
1454 bfd_reloc_code_real_type reloc
;
1456 return (reloc
== BFD_RELOC_HI16_S
1457 || reloc
== BFD_RELOC_MIPS_GOT16
);
1460 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1463 static inline bfd_boolean
1464 fixup_has_matching_lo_p (fixp
)
1467 return (fixp
->fx_next
!= NULL
1468 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1469 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1470 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1473 /* See whether instruction IP reads register REG. CLASS is the type
1477 insn_uses_reg (ip
, reg
, class)
1478 struct mips_cl_insn
*ip
;
1480 enum mips_regclass
class;
1482 if (class == MIPS16_REG
)
1484 assert (mips_opts
.mips16
);
1485 reg
= mips16_to_32_reg_map
[reg
];
1486 class = MIPS_GR_REG
;
1489 /* Don't report on general register ZERO, since it never changes. */
1490 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1493 if (class == MIPS_FP_REG
)
1495 assert (! mips_opts
.mips16
);
1496 /* If we are called with either $f0 or $f1, we must check $f0.
1497 This is not optimal, because it will introduce an unnecessary
1498 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1499 need to distinguish reading both $f0 and $f1 or just one of
1500 them. Note that we don't have to check the other way,
1501 because there is no instruction that sets both $f0 and $f1
1502 and requires a delay. */
1503 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1504 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1505 == (reg
&~ (unsigned) 1)))
1507 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1508 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1509 == (reg
&~ (unsigned) 1)))
1512 else if (! mips_opts
.mips16
)
1514 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1515 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1517 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1518 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1523 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1524 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1525 & MIPS16OP_MASK_RX
)]
1528 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1529 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1530 & MIPS16OP_MASK_RY
)]
1533 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1534 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1535 & MIPS16OP_MASK_MOVE32Z
)]
1538 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1540 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1542 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1544 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1545 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1546 & MIPS16OP_MASK_REGR32
) == reg
)
1553 /* This function returns true if modifying a register requires a
1557 reg_needs_delay (reg
)
1560 unsigned long prev_pinfo
;
1562 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1563 if (! mips_opts
.noreorder
1564 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1565 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1566 || (! gpr_interlocks
1567 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1569 /* A load from a coprocessor or from memory. All load
1570 delays delay the use of general register rt for one
1571 instruction on the r3000. The r6000 and r4000 use
1573 /* Itbl support may require additional care here. */
1574 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1575 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1582 /* Mark instruction labels in mips16 mode. This permits the linker to
1583 handle them specially, such as generating jalx instructions when
1584 needed. We also make them odd for the duration of the assembly, in
1585 order to generate the right sort of code. We will make them even
1586 in the adjust_symtab routine, while leaving them marked. This is
1587 convenient for the debugger and the disassembler. The linker knows
1588 to make them odd again. */
1591 mips16_mark_labels ()
1593 if (mips_opts
.mips16
)
1595 struct insn_label_list
*l
;
1598 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1601 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1602 S_SET_OTHER (l
->label
, STO_MIPS16
);
1604 val
= S_GET_VALUE (l
->label
);
1606 S_SET_VALUE (l
->label
, val
+ 1);
1611 /* Output an instruction. PLACE is where to put the instruction; if
1612 it is NULL, this uses frag_more to get room. IP is the instruction
1613 information. ADDRESS_EXPR is an operand of the instruction to be
1614 used with RELOC_TYPE. */
1617 append_insn (place
, ip
, address_expr
, reloc_type
)
1619 struct mips_cl_insn
*ip
;
1620 expressionS
*address_expr
;
1621 bfd_reloc_code_real_type
*reloc_type
;
1623 register unsigned long prev_pinfo
, pinfo
;
1628 /* Mark instruction labels in mips16 mode. */
1629 mips16_mark_labels ();
1631 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1632 pinfo
= ip
->insn_mo
->pinfo
;
1634 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1638 /* If the previous insn required any delay slots, see if we need
1639 to insert a NOP or two. There are eight kinds of possible
1640 hazards, of which an instruction can have at most one type.
1641 (1) a load from memory delay
1642 (2) a load from a coprocessor delay
1643 (3) an unconditional branch delay
1644 (4) a conditional branch delay
1645 (5) a move to coprocessor register delay
1646 (6) a load coprocessor register from memory delay
1647 (7) a coprocessor condition code delay
1648 (8) a HI/LO special register delay
1650 There are a lot of optimizations we could do that we don't.
1651 In particular, we do not, in general, reorder instructions.
1652 If you use gcc with optimization, it will reorder
1653 instructions and generally do much more optimization then we
1654 do here; repeating all that work in the assembler would only
1655 benefit hand written assembly code, and does not seem worth
1658 /* This is how a NOP is emitted. */
1659 #define emit_nop() \
1661 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1662 : md_number_to_chars (frag_more (4), 0, 4))
1664 /* The previous insn might require a delay slot, depending upon
1665 the contents of the current insn. */
1666 if (! mips_opts
.mips16
1667 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1668 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1669 && ! cop_interlocks
)
1670 || (! gpr_interlocks
1671 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1673 /* A load from a coprocessor or from memory. All load
1674 delays delay the use of general register rt for one
1675 instruction on the r3000. The r6000 and r4000 use
1677 /* Itbl support may require additional care here. */
1678 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1679 if (mips_optimize
== 0
1680 || insn_uses_reg (ip
,
1681 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1686 else if (! mips_opts
.mips16
1687 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1688 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1689 && ! cop_interlocks
)
1690 || (mips_opts
.isa
== ISA_MIPS1
1691 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1693 /* A generic coprocessor delay. The previous instruction
1694 modified a coprocessor general or control register. If
1695 it modified a control register, we need to avoid any
1696 coprocessor instruction (this is probably not always
1697 required, but it sometimes is). If it modified a general
1698 register, we avoid using that register.
1700 On the r6000 and r4000 loading a coprocessor register
1701 from memory is interlocked, and does not require a delay.
1703 This case is not handled very well. There is no special
1704 knowledge of CP0 handling, and the coprocessors other
1705 than the floating point unit are not distinguished at
1707 /* Itbl support may require additional care here. FIXME!
1708 Need to modify this to include knowledge about
1709 user specified delays! */
1710 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1712 if (mips_optimize
== 0
1713 || insn_uses_reg (ip
,
1714 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1719 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1721 if (mips_optimize
== 0
1722 || insn_uses_reg (ip
,
1723 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1730 /* We don't know exactly what the previous instruction
1731 does. If the current instruction uses a coprocessor
1732 register, we must insert a NOP. If previous
1733 instruction may set the condition codes, and the
1734 current instruction uses them, we must insert two
1736 /* Itbl support may require additional care here. */
1737 if (mips_optimize
== 0
1738 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1739 && (pinfo
& INSN_READ_COND_CODE
)))
1741 else if (pinfo
& INSN_COP
)
1745 else if (! mips_opts
.mips16
1746 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1747 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1748 && ! cop_interlocks
)
1750 /* The previous instruction sets the coprocessor condition
1751 codes, but does not require a general coprocessor delay
1752 (this means it is a floating point comparison
1753 instruction). If this instruction uses the condition
1754 codes, we need to insert a single NOP. */
1755 /* Itbl support may require additional care here. */
1756 if (mips_optimize
== 0
1757 || (pinfo
& INSN_READ_COND_CODE
))
1761 /* If we're fixing up mfhi/mflo for the r7000 and the
1762 previous insn was an mfhi/mflo and the current insn
1763 reads the register that the mfhi/mflo wrote to, then
1766 else if (mips_7000_hilo_fix
1767 && MF_HILO_INSN (prev_pinfo
)
1768 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1775 /* If we're fixing up mfhi/mflo for the r7000 and the
1776 2nd previous insn was an mfhi/mflo and the current insn
1777 reads the register that the mfhi/mflo wrote to, then
1780 else if (mips_7000_hilo_fix
1781 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1782 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1790 else if (prev_pinfo
& INSN_READ_LO
)
1792 /* The previous instruction reads the LO register; if the
1793 current instruction writes to the LO register, we must
1794 insert two NOPS. Some newer processors have interlocks.
1795 Also the tx39's multiply instructions can be exectuted
1796 immediatly after a read from HI/LO (without the delay),
1797 though the tx39's divide insns still do require the
1799 if (! (hilo_interlocks
1800 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1801 && (mips_optimize
== 0
1802 || (pinfo
& INSN_WRITE_LO
)))
1804 /* Most mips16 branch insns don't have a delay slot.
1805 If a read from LO is immediately followed by a branch
1806 to a write to LO we have a read followed by a write
1807 less than 2 insns away. We assume the target of
1808 a branch might be a write to LO, and insert a nop
1809 between a read and an immediately following branch. */
1810 else if (mips_opts
.mips16
1811 && (mips_optimize
== 0
1812 || (pinfo
& MIPS16_INSN_BRANCH
)))
1815 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1817 /* The previous instruction reads the HI register; if the
1818 current instruction writes to the HI register, we must
1819 insert a NOP. Some newer processors have interlocks.
1820 Also the note tx39's multiply above. */
1821 if (! (hilo_interlocks
1822 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1823 && (mips_optimize
== 0
1824 || (pinfo
& INSN_WRITE_HI
)))
1826 /* Most mips16 branch insns don't have a delay slot.
1827 If a read from HI is immediately followed by a branch
1828 to a write to HI we have a read followed by a write
1829 less than 2 insns away. We assume the target of
1830 a branch might be a write to HI, and insert a nop
1831 between a read and an immediately following branch. */
1832 else if (mips_opts
.mips16
1833 && (mips_optimize
== 0
1834 || (pinfo
& MIPS16_INSN_BRANCH
)))
1838 /* If the previous instruction was in a noreorder section, then
1839 we don't want to insert the nop after all. */
1840 /* Itbl support may require additional care here. */
1841 if (prev_insn_unreordered
)
1844 /* There are two cases which require two intervening
1845 instructions: 1) setting the condition codes using a move to
1846 coprocessor instruction which requires a general coprocessor
1847 delay and then reading the condition codes 2) reading the HI
1848 or LO register and then writing to it (except on processors
1849 which have interlocks). If we are not already emitting a NOP
1850 instruction, we must check for these cases compared to the
1851 instruction previous to the previous instruction. */
1852 if ((! mips_opts
.mips16
1853 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1854 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1855 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1856 && (pinfo
& INSN_READ_COND_CODE
)
1857 && ! cop_interlocks
)
1858 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1859 && (pinfo
& INSN_WRITE_LO
)
1860 && ! (hilo_interlocks
1861 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1862 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1863 && (pinfo
& INSN_WRITE_HI
)
1864 && ! (hilo_interlocks
1865 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1870 if (prev_prev_insn_unreordered
)
1873 if (prev_prev_nop
&& nops
== 0)
1876 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1878 /* We're out of bits in pinfo, so we must resort to string
1879 ops here. Shortcuts are selected based on opcodes being
1880 limited to the VR4122 instruction set. */
1882 const char *pn
= prev_insn
.insn_mo
->name
;
1883 const char *tn
= ip
->insn_mo
->name
;
1884 if (strncmp(pn
, "macc", 4) == 0
1885 || strncmp(pn
, "dmacc", 5) == 0)
1887 /* Errata 21 - [D]DIV[U] after [D]MACC */
1888 if (strstr (tn
, "div"))
1893 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1894 if (pn
[0] == 'd' /* dmacc */
1895 && (strncmp(tn
, "dmult", 5) == 0
1896 || strncmp(tn
, "dmacc", 5) == 0))
1901 /* Errata 24 - MT{LO,HI} after [D]MACC */
1902 if (strcmp (tn
, "mtlo") == 0
1903 || strcmp (tn
, "mthi") == 0)
1909 else if (strncmp(pn
, "dmult", 5) == 0
1910 && (strncmp(tn
, "dmult", 5) == 0
1911 || strncmp(tn
, "dmacc", 5) == 0))
1913 /* Here is the rest of errata 23. */
1916 if (nops
< min_nops
)
1920 /* If we are being given a nop instruction, don't bother with
1921 one of the nops we would otherwise output. This will only
1922 happen when a nop instruction is used with mips_optimize set
1925 && ! mips_opts
.noreorder
1926 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1929 /* Now emit the right number of NOP instructions. */
1930 if (nops
> 0 && ! mips_opts
.noreorder
)
1933 unsigned long old_frag_offset
;
1935 struct insn_label_list
*l
;
1937 old_frag
= frag_now
;
1938 old_frag_offset
= frag_now_fix ();
1940 for (i
= 0; i
< nops
; i
++)
1945 listing_prev_line ();
1946 /* We may be at the start of a variant frag. In case we
1947 are, make sure there is enough space for the frag
1948 after the frags created by listing_prev_line. The
1949 argument to frag_grow here must be at least as large
1950 as the argument to all other calls to frag_grow in
1951 this file. We don't have to worry about being in the
1952 middle of a variant frag, because the variants insert
1953 all needed nop instructions themselves. */
1957 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1961 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1962 symbol_set_frag (l
->label
, frag_now
);
1963 val
= (valueT
) frag_now_fix ();
1964 /* mips16 text labels are stored as odd. */
1965 if (mips_opts
.mips16
)
1967 S_SET_VALUE (l
->label
, val
);
1970 #ifndef NO_ECOFF_DEBUGGING
1971 if (ECOFF_DEBUGGING
)
1972 ecoff_fix_loc (old_frag
, old_frag_offset
);
1975 else if (prev_nop_frag
!= NULL
)
1977 /* We have a frag holding nops we may be able to remove. If
1978 we don't need any nops, we can decrease the size of
1979 prev_nop_frag by the size of one instruction. If we do
1980 need some nops, we count them in prev_nops_required. */
1981 if (prev_nop_frag_since
== 0)
1985 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1986 --prev_nop_frag_holds
;
1989 prev_nop_frag_required
+= nops
;
1993 if (prev_prev_nop
== 0)
1995 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1996 --prev_nop_frag_holds
;
1999 ++prev_nop_frag_required
;
2002 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2003 prev_nop_frag
= NULL
;
2005 ++prev_nop_frag_since
;
2007 /* Sanity check: by the time we reach the second instruction
2008 after prev_nop_frag, we should have used up all the nops
2009 one way or another. */
2010 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2016 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2017 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2018 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2019 && mips_relax_branch
2020 /* Don't try branch relaxation within .set nomacro, or within
2021 .set noat if we use $at for PIC computations. If it turns
2022 out that the branch was out-of-range, we'll get an error. */
2023 && !mips_opts
.warn_about_macros
2024 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2025 && !mips_opts
.mips16
)
2027 f
= frag_var (rs_machine_dependent
,
2028 relaxed_branch_length
2030 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2031 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2033 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2034 pinfo
& INSN_COND_BRANCH_LIKELY
,
2035 pinfo
& INSN_WRITE_GPR_31
,
2037 address_expr
->X_add_symbol
,
2038 address_expr
->X_add_number
,
2040 *reloc_type
= BFD_RELOC_UNUSED
;
2042 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2044 /* We need to set up a variant frag. */
2045 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2046 f
= frag_var (rs_machine_dependent
, 4, 0,
2047 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2048 mips16_small
, mips16_ext
,
2050 & INSN_UNCOND_BRANCH_DELAY
),
2051 (*prev_insn_reloc_type
2052 == BFD_RELOC_MIPS16_JMP
)),
2053 make_expr_symbol (address_expr
), 0, NULL
);
2055 else if (place
!= NULL
)
2057 else if (mips_opts
.mips16
2059 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2061 /* Make sure there is enough room to swap this instruction with
2062 a following jump instruction. */
2068 if (mips_opts
.mips16
2069 && mips_opts
.noreorder
2070 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2071 as_warn (_("extended instruction in delay slot"));
2076 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2077 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2079 if (address_expr
->X_op
== O_constant
)
2083 switch (*reloc_type
)
2086 ip
->insn_opcode
|= address_expr
->X_add_number
;
2089 case BFD_RELOC_MIPS_HIGHEST
:
2090 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2092 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2095 case BFD_RELOC_MIPS_HIGHER
:
2096 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2097 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2100 case BFD_RELOC_HI16_S
:
2101 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2105 case BFD_RELOC_HI16
:
2106 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2109 case BFD_RELOC_LO16
:
2110 case BFD_RELOC_MIPS_GOT_DISP
:
2111 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2114 case BFD_RELOC_MIPS_JMP
:
2115 if ((address_expr
->X_add_number
& 3) != 0)
2116 as_bad (_("jump to misaligned address (0x%lx)"),
2117 (unsigned long) address_expr
->X_add_number
);
2118 if (address_expr
->X_add_number
& ~0xfffffff)
2119 as_bad (_("jump address range overflow (0x%lx)"),
2120 (unsigned long) address_expr
->X_add_number
);
2121 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2124 case BFD_RELOC_MIPS16_JMP
:
2125 if ((address_expr
->X_add_number
& 3) != 0)
2126 as_bad (_("jump to misaligned address (0x%lx)"),
2127 (unsigned long) address_expr
->X_add_number
);
2128 if (address_expr
->X_add_number
& ~0xfffffff)
2129 as_bad (_("jump address range overflow (0x%lx)"),
2130 (unsigned long) address_expr
->X_add_number
);
2132 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2133 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2134 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2137 case BFD_RELOC_16_PCREL_S2
:
2147 /* Don't generate a reloc if we are writing into a variant frag. */
2150 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2152 *reloc_type
== BFD_RELOC_16_PCREL_S2
,
2155 /* These relocations can have an addend that won't fit in
2156 4 octets for 64bit assembly. */
2157 if (HAVE_64BIT_GPRS
&&
2158 (*reloc_type
== BFD_RELOC_16
2159 || *reloc_type
== BFD_RELOC_32
2160 || *reloc_type
== BFD_RELOC_MIPS_JMP
2161 || *reloc_type
== BFD_RELOC_HI16_S
2162 || *reloc_type
== BFD_RELOC_LO16
2163 || *reloc_type
== BFD_RELOC_GPREL16
2164 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2165 || *reloc_type
== BFD_RELOC_GPREL32
2166 || *reloc_type
== BFD_RELOC_64
2167 || *reloc_type
== BFD_RELOC_CTOR
2168 || *reloc_type
== BFD_RELOC_MIPS_SUB
2169 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2170 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2171 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2172 || *reloc_type
== BFD_RELOC_MIPS_REL16
2173 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2174 fixp
[0]->fx_no_overflow
= 1;
2176 if (reloc_needs_lo_p (*reloc_type
))
2178 struct mips_hi_fixup
*hi_fixup
;
2180 /* Reuse the last entry if it already has a matching %lo. */
2181 hi_fixup
= mips_hi_fixup_list
;
2183 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2185 hi_fixup
= ((struct mips_hi_fixup
*)
2186 xmalloc (sizeof (struct mips_hi_fixup
)));
2187 hi_fixup
->next
= mips_hi_fixup_list
;
2188 mips_hi_fixup_list
= hi_fixup
;
2190 hi_fixup
->fixp
= fixp
[0];
2191 hi_fixup
->seg
= now_seg
;
2194 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2196 /* FIXME: This symbol can be one of
2197 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2198 address_expr
->X_op
= O_absent
;
2199 address_expr
->X_add_symbol
= 0;
2200 address_expr
->X_add_number
= 0;
2202 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2203 4, address_expr
, FALSE
,
2206 /* These relocations can have an addend that won't fit in
2207 4 octets for 64bit assembly. */
2208 if (HAVE_64BIT_GPRS
&&
2209 (*reloc_type
== BFD_RELOC_16
2210 || *reloc_type
== BFD_RELOC_32
2211 || *reloc_type
== BFD_RELOC_MIPS_JMP
2212 || *reloc_type
== BFD_RELOC_HI16_S
2213 || *reloc_type
== BFD_RELOC_LO16
2214 || *reloc_type
== BFD_RELOC_GPREL16
2215 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2216 || *reloc_type
== BFD_RELOC_GPREL32
2217 || *reloc_type
== BFD_RELOC_64
2218 || *reloc_type
== BFD_RELOC_CTOR
2219 || *reloc_type
== BFD_RELOC_MIPS_SUB
2220 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2221 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2222 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2223 || *reloc_type
== BFD_RELOC_MIPS_REL16
2224 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2225 fixp
[1]->fx_no_overflow
= 1;
2227 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2229 address_expr
->X_op
= O_absent
;
2230 address_expr
->X_add_symbol
= 0;
2231 address_expr
->X_add_number
= 0;
2233 fixp
[2] = fix_new_exp (frag_now
,
2234 f
- frag_now
->fr_literal
, 4,
2235 address_expr
, FALSE
,
2238 /* These relocations can have an addend that won't fit in
2239 4 octets for 64bit assembly. */
2240 if (HAVE_64BIT_GPRS
&&
2241 (*reloc_type
== BFD_RELOC_16
2242 || *reloc_type
== BFD_RELOC_32
2243 || *reloc_type
== BFD_RELOC_MIPS_JMP
2244 || *reloc_type
== BFD_RELOC_HI16_S
2245 || *reloc_type
== BFD_RELOC_LO16
2246 || *reloc_type
== BFD_RELOC_GPREL16
2247 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2248 || *reloc_type
== BFD_RELOC_GPREL32
2249 || *reloc_type
== BFD_RELOC_64
2250 || *reloc_type
== BFD_RELOC_CTOR
2251 || *reloc_type
== BFD_RELOC_MIPS_SUB
2252 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2253 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2254 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2255 || *reloc_type
== BFD_RELOC_MIPS_REL16
2256 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2257 fixp
[2]->fx_no_overflow
= 1;
2264 if (! mips_opts
.mips16
)
2266 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2268 dwarf2_emit_insn (4);
2271 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2273 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2274 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2276 dwarf2_emit_insn (4);
2283 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2286 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2288 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2292 /* Update the register mask information. */
2293 if (! mips_opts
.mips16
)
2295 if (pinfo
& INSN_WRITE_GPR_D
)
2296 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2297 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2298 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2299 if (pinfo
& INSN_READ_GPR_S
)
2300 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2301 if (pinfo
& INSN_WRITE_GPR_31
)
2302 mips_gprmask
|= 1 << RA
;
2303 if (pinfo
& INSN_WRITE_FPR_D
)
2304 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2305 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2306 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2307 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2308 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2309 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2310 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2311 if (pinfo
& INSN_COP
)
2313 /* We don't keep enough information to sort these cases out.
2314 The itbl support does keep this information however, although
2315 we currently don't support itbl fprmats as part of the cop
2316 instruction. May want to add this support in the future. */
2318 /* Never set the bit for $0, which is always zero. */
2319 mips_gprmask
&= ~1 << 0;
2323 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2324 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2325 & MIPS16OP_MASK_RX
);
2326 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2327 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2328 & MIPS16OP_MASK_RY
);
2329 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2330 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2331 & MIPS16OP_MASK_RZ
);
2332 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2333 mips_gprmask
|= 1 << TREG
;
2334 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2335 mips_gprmask
|= 1 << SP
;
2336 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2337 mips_gprmask
|= 1 << RA
;
2338 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2339 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2340 if (pinfo
& MIPS16_INSN_READ_Z
)
2341 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2342 & MIPS16OP_MASK_MOVE32Z
);
2343 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2344 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2345 & MIPS16OP_MASK_REGR32
);
2348 if (place
== NULL
&& ! mips_opts
.noreorder
)
2350 /* Filling the branch delay slot is more complex. We try to
2351 switch the branch with the previous instruction, which we can
2352 do if the previous instruction does not set up a condition
2353 that the branch tests and if the branch is not itself the
2354 target of any branch. */
2355 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2356 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2358 if (mips_optimize
< 2
2359 /* If we have seen .set volatile or .set nomove, don't
2361 || mips_opts
.nomove
!= 0
2362 /* If we had to emit any NOP instructions, then we
2363 already know we can not swap. */
2365 /* If we don't even know the previous insn, we can not
2367 || ! prev_insn_valid
2368 /* If the previous insn is already in a branch delay
2369 slot, then we can not swap. */
2370 || prev_insn_is_delay_slot
2371 /* If the previous previous insn was in a .set
2372 noreorder, we can't swap. Actually, the MIPS
2373 assembler will swap in this situation. However, gcc
2374 configured -with-gnu-as will generate code like
2380 in which we can not swap the bne and INSN. If gcc is
2381 not configured -with-gnu-as, it does not output the
2382 .set pseudo-ops. We don't have to check
2383 prev_insn_unreordered, because prev_insn_valid will
2384 be 0 in that case. We don't want to use
2385 prev_prev_insn_valid, because we do want to be able
2386 to swap at the start of a function. */
2387 || prev_prev_insn_unreordered
2388 /* If the branch is itself the target of a branch, we
2389 can not swap. We cheat on this; all we check for is
2390 whether there is a label on this instruction. If
2391 there are any branches to anything other than a
2392 label, users must use .set noreorder. */
2393 || insn_labels
!= NULL
2394 /* If the previous instruction is in a variant frag, we
2395 can not do the swap. This does not apply to the
2396 mips16, which uses variant frags for different
2398 || (! mips_opts
.mips16
2399 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2400 /* If the branch reads the condition codes, we don't
2401 even try to swap, because in the sequence
2406 we can not swap, and I don't feel like handling that
2408 || (! mips_opts
.mips16
2409 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2410 && (pinfo
& INSN_READ_COND_CODE
))
2411 /* We can not swap with an instruction that requires a
2412 delay slot, becase the target of the branch might
2413 interfere with that instruction. */
2414 || (! mips_opts
.mips16
2415 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2417 /* Itbl support may require additional care here. */
2418 & (INSN_LOAD_COPROC_DELAY
2419 | INSN_COPROC_MOVE_DELAY
2420 | INSN_WRITE_COND_CODE
)))
2421 || (! (hilo_interlocks
2422 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2426 || (! mips_opts
.mips16
2428 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2429 || (! mips_opts
.mips16
2430 && mips_opts
.isa
== ISA_MIPS1
2431 /* Itbl support may require additional care here. */
2432 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2433 /* We can not swap with a branch instruction. */
2435 & (INSN_UNCOND_BRANCH_DELAY
2436 | INSN_COND_BRANCH_DELAY
2437 | INSN_COND_BRANCH_LIKELY
))
2438 /* We do not swap with a trap instruction, since it
2439 complicates trap handlers to have the trap
2440 instruction be in a delay slot. */
2441 || (prev_pinfo
& INSN_TRAP
)
2442 /* If the branch reads a register that the previous
2443 instruction sets, we can not swap. */
2444 || (! mips_opts
.mips16
2445 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2446 && insn_uses_reg (ip
,
2447 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2450 || (! mips_opts
.mips16
2451 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2452 && insn_uses_reg (ip
,
2453 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2456 || (mips_opts
.mips16
2457 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2458 && insn_uses_reg (ip
,
2459 ((prev_insn
.insn_opcode
2461 & MIPS16OP_MASK_RX
),
2463 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2464 && insn_uses_reg (ip
,
2465 ((prev_insn
.insn_opcode
2467 & MIPS16OP_MASK_RY
),
2469 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2470 && insn_uses_reg (ip
,
2471 ((prev_insn
.insn_opcode
2473 & MIPS16OP_MASK_RZ
),
2475 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2476 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2477 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2478 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2479 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2480 && insn_uses_reg (ip
,
2481 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2484 /* If the branch writes a register that the previous
2485 instruction sets, we can not swap (we know that
2486 branches write only to RD or to $31). */
2487 || (! mips_opts
.mips16
2488 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2489 && (((pinfo
& INSN_WRITE_GPR_D
)
2490 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2491 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2492 || ((pinfo
& INSN_WRITE_GPR_31
)
2493 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2496 || (! mips_opts
.mips16
2497 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2498 && (((pinfo
& INSN_WRITE_GPR_D
)
2499 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2500 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2501 || ((pinfo
& INSN_WRITE_GPR_31
)
2502 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2505 || (mips_opts
.mips16
2506 && (pinfo
& MIPS16_INSN_WRITE_31
)
2507 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2508 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2509 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2511 /* If the branch writes a register that the previous
2512 instruction reads, we can not swap (we know that
2513 branches only write to RD or to $31). */
2514 || (! mips_opts
.mips16
2515 && (pinfo
& INSN_WRITE_GPR_D
)
2516 && insn_uses_reg (&prev_insn
,
2517 ((ip
->insn_opcode
>> OP_SH_RD
)
2520 || (! mips_opts
.mips16
2521 && (pinfo
& INSN_WRITE_GPR_31
)
2522 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2523 || (mips_opts
.mips16
2524 && (pinfo
& MIPS16_INSN_WRITE_31
)
2525 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2526 /* If we are generating embedded PIC code, the branch
2527 might be expanded into a sequence which uses $at, so
2528 we can't swap with an instruction which reads it. */
2529 || (mips_pic
== EMBEDDED_PIC
2530 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2531 /* If the previous previous instruction has a load
2532 delay, and sets a register that the branch reads, we
2534 || (! mips_opts
.mips16
2535 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2536 /* Itbl support may require additional care here. */
2537 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2538 || (! gpr_interlocks
2539 && (prev_prev_insn
.insn_mo
->pinfo
2540 & INSN_LOAD_MEMORY_DELAY
)))
2541 && insn_uses_reg (ip
,
2542 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2545 /* If one instruction sets a condition code and the
2546 other one uses a condition code, we can not swap. */
2547 || ((pinfo
& INSN_READ_COND_CODE
)
2548 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2549 || ((pinfo
& INSN_WRITE_COND_CODE
)
2550 && (prev_pinfo
& INSN_READ_COND_CODE
))
2551 /* If the previous instruction uses the PC, we can not
2553 || (mips_opts
.mips16
2554 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2555 /* If the previous instruction was extended, we can not
2557 || (mips_opts
.mips16
&& prev_insn_extended
)
2558 /* If the previous instruction had a fixup in mips16
2559 mode, we can not swap. This normally means that the
2560 previous instruction was a 4 byte branch anyhow. */
2561 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2562 /* If the previous instruction is a sync, sync.l, or
2563 sync.p, we can not swap. */
2564 || (prev_pinfo
& INSN_SYNC
))
2566 /* We could do even better for unconditional branches to
2567 portions of this object file; we could pick up the
2568 instruction at the destination, put it in the delay
2569 slot, and bump the destination address. */
2571 /* Update the previous insn information. */
2572 prev_prev_insn
= *ip
;
2573 prev_insn
.insn_mo
= &dummy_opcode
;
2577 /* It looks like we can actually do the swap. */
2578 if (! mips_opts
.mips16
)
2583 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2584 memcpy (temp
, prev_f
, 4);
2585 memcpy (prev_f
, f
, 4);
2586 memcpy (f
, temp
, 4);
2587 if (prev_insn_fixp
[0])
2589 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2590 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2592 if (prev_insn_fixp
[1])
2594 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2595 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2597 if (prev_insn_fixp
[2])
2599 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2600 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2604 fixp
[0]->fx_frag
= prev_insn_frag
;
2605 fixp
[0]->fx_where
= prev_insn_where
;
2609 fixp
[1]->fx_frag
= prev_insn_frag
;
2610 fixp
[1]->fx_where
= prev_insn_where
;
2614 fixp
[2]->fx_frag
= prev_insn_frag
;
2615 fixp
[2]->fx_where
= prev_insn_where
;
2623 assert (prev_insn_fixp
[0] == NULL
);
2624 assert (prev_insn_fixp
[1] == NULL
);
2625 assert (prev_insn_fixp
[2] == NULL
);
2626 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2627 memcpy (temp
, prev_f
, 2);
2628 memcpy (prev_f
, f
, 2);
2629 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2631 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2632 memcpy (f
, temp
, 2);
2636 memcpy (f
, f
+ 2, 2);
2637 memcpy (f
+ 2, temp
, 2);
2641 fixp
[0]->fx_frag
= prev_insn_frag
;
2642 fixp
[0]->fx_where
= prev_insn_where
;
2646 fixp
[1]->fx_frag
= prev_insn_frag
;
2647 fixp
[1]->fx_where
= prev_insn_where
;
2651 fixp
[2]->fx_frag
= prev_insn_frag
;
2652 fixp
[2]->fx_where
= prev_insn_where
;
2656 /* Update the previous insn information; leave prev_insn
2658 prev_prev_insn
= *ip
;
2660 prev_insn_is_delay_slot
= 1;
2662 /* If that was an unconditional branch, forget the previous
2663 insn information. */
2664 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2666 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2667 prev_insn
.insn_mo
= &dummy_opcode
;
2670 prev_insn_fixp
[0] = NULL
;
2671 prev_insn_fixp
[1] = NULL
;
2672 prev_insn_fixp
[2] = NULL
;
2673 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2674 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2675 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2676 prev_insn_extended
= 0;
2678 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2680 /* We don't yet optimize a branch likely. What we should do
2681 is look at the target, copy the instruction found there
2682 into the delay slot, and increment the branch to jump to
2683 the next instruction. */
2685 /* Update the previous insn information. */
2686 prev_prev_insn
= *ip
;
2687 prev_insn
.insn_mo
= &dummy_opcode
;
2688 prev_insn_fixp
[0] = NULL
;
2689 prev_insn_fixp
[1] = NULL
;
2690 prev_insn_fixp
[2] = NULL
;
2691 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2692 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2693 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2694 prev_insn_extended
= 0;
2698 /* Update the previous insn information. */
2700 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2702 prev_prev_insn
= prev_insn
;
2705 /* Any time we see a branch, we always fill the delay slot
2706 immediately; since this insn is not a branch, we know it
2707 is not in a delay slot. */
2708 prev_insn_is_delay_slot
= 0;
2710 prev_insn_fixp
[0] = fixp
[0];
2711 prev_insn_fixp
[1] = fixp
[1];
2712 prev_insn_fixp
[2] = fixp
[2];
2713 prev_insn_reloc_type
[0] = reloc_type
[0];
2714 prev_insn_reloc_type
[1] = reloc_type
[1];
2715 prev_insn_reloc_type
[2] = reloc_type
[2];
2716 if (mips_opts
.mips16
)
2717 prev_insn_extended
= (ip
->use_extend
2718 || *reloc_type
> BFD_RELOC_UNUSED
);
2721 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2722 prev_insn_unreordered
= 0;
2723 prev_insn_frag
= frag_now
;
2724 prev_insn_where
= f
- frag_now
->fr_literal
;
2725 prev_insn_valid
= 1;
2727 else if (place
== NULL
)
2729 /* We need to record a bit of information even when we are not
2730 reordering, in order to determine the base address for mips16
2731 PC relative relocs. */
2732 prev_prev_insn
= prev_insn
;
2734 prev_insn_reloc_type
[0] = reloc_type
[0];
2735 prev_insn_reloc_type
[1] = reloc_type
[1];
2736 prev_insn_reloc_type
[2] = reloc_type
[2];
2737 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2738 prev_insn_unreordered
= 1;
2741 /* We just output an insn, so the next one doesn't have a label. */
2742 mips_clear_insn_labels ();
2745 /* This function forgets that there was any previous instruction or
2746 label. If PRESERVE is non-zero, it remembers enough information to
2747 know whether nops are needed before a noreorder section. */
2750 mips_no_prev_insn (preserve
)
2755 prev_insn
.insn_mo
= &dummy_opcode
;
2756 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2757 prev_nop_frag
= NULL
;
2758 prev_nop_frag_holds
= 0;
2759 prev_nop_frag_required
= 0;
2760 prev_nop_frag_since
= 0;
2762 prev_insn_valid
= 0;
2763 prev_insn_is_delay_slot
= 0;
2764 prev_insn_unreordered
= 0;
2765 prev_insn_extended
= 0;
2766 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2767 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2768 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2769 prev_prev_insn_unreordered
= 0;
2770 mips_clear_insn_labels ();
2773 /* This function must be called whenever we turn on noreorder or emit
2774 something other than instructions. It inserts any NOPS which might
2775 be needed by the previous instruction, and clears the information
2776 kept for the previous instructions. The INSNS parameter is true if
2777 instructions are to follow. */
2780 mips_emit_delays (insns
)
2783 if (! mips_opts
.noreorder
)
2788 if ((! mips_opts
.mips16
2789 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2790 && (! cop_interlocks
2791 && (prev_insn
.insn_mo
->pinfo
2792 & (INSN_LOAD_COPROC_DELAY
2793 | INSN_COPROC_MOVE_DELAY
2794 | INSN_WRITE_COND_CODE
))))
2795 || (! hilo_interlocks
2796 && (prev_insn
.insn_mo
->pinfo
2799 || (! mips_opts
.mips16
2801 && (prev_insn
.insn_mo
->pinfo
2802 & INSN_LOAD_MEMORY_DELAY
))
2803 || (! mips_opts
.mips16
2804 && mips_opts
.isa
== ISA_MIPS1
2805 && (prev_insn
.insn_mo
->pinfo
2806 & INSN_COPROC_MEMORY_DELAY
)))
2808 /* Itbl support may require additional care here. */
2810 if ((! mips_opts
.mips16
2811 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2812 && (! cop_interlocks
2813 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2814 || (! hilo_interlocks
2815 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2816 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2819 if (prev_insn_unreordered
)
2822 else if ((! mips_opts
.mips16
2823 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2824 && (! cop_interlocks
2825 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2826 || (! hilo_interlocks
2827 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2828 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2830 /* Itbl support may require additional care here. */
2831 if (! prev_prev_insn_unreordered
)
2835 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2838 const char *pn
= prev_insn
.insn_mo
->name
;
2839 if (strncmp(pn
, "macc", 4) == 0
2840 || strncmp(pn
, "dmacc", 5) == 0
2841 || strncmp(pn
, "dmult", 5) == 0)
2845 if (nops
< min_nops
)
2851 struct insn_label_list
*l
;
2855 /* Record the frag which holds the nop instructions, so
2856 that we can remove them if we don't need them. */
2857 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2858 prev_nop_frag
= frag_now
;
2859 prev_nop_frag_holds
= nops
;
2860 prev_nop_frag_required
= 0;
2861 prev_nop_frag_since
= 0;
2864 for (; nops
> 0; --nops
)
2869 /* Move on to a new frag, so that it is safe to simply
2870 decrease the size of prev_nop_frag. */
2871 frag_wane (frag_now
);
2875 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2879 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2880 symbol_set_frag (l
->label
, frag_now
);
2881 val
= (valueT
) frag_now_fix ();
2882 /* mips16 text labels are stored as odd. */
2883 if (mips_opts
.mips16
)
2885 S_SET_VALUE (l
->label
, val
);
2890 /* Mark instruction labels in mips16 mode. */
2892 mips16_mark_labels ();
2894 mips_no_prev_insn (insns
);
2897 /* Build an instruction created by a macro expansion. This is passed
2898 a pointer to the count of instructions created so far, an
2899 expression, the name of the instruction to build, an operand format
2900 string, and corresponding arguments. */
2904 macro_build (char *place
,
2912 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2921 struct mips_cl_insn insn
;
2922 bfd_reloc_code_real_type r
[3];
2926 va_start (args
, fmt
);
2932 * If the macro is about to expand into a second instruction,
2933 * print a warning if needed. We need to pass ip as a parameter
2934 * to generate a better warning message here...
2936 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2937 as_warn (_("Macro instruction expanded into multiple instructions"));
2940 * If the macro is about to expand into a second instruction,
2941 * and it is in a delay slot, print a warning.
2945 && mips_opts
.noreorder
2946 && (prev_prev_insn
.insn_mo
->pinfo
2947 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2948 | INSN_COND_BRANCH_LIKELY
)) != 0)
2949 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2952 ++*counter
; /* bump instruction counter */
2954 if (mips_opts
.mips16
)
2956 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2961 r
[0] = BFD_RELOC_UNUSED
;
2962 r
[1] = BFD_RELOC_UNUSED
;
2963 r
[2] = BFD_RELOC_UNUSED
;
2964 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2965 assert (insn
.insn_mo
);
2966 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2968 /* Search until we get a match for NAME. */
2971 /* It is assumed here that macros will never generate
2972 MDMX or MIPS-3D instructions. */
2973 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2974 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2975 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2977 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2979 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2983 assert (insn
.insn_mo
->name
);
2984 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2987 insn
.insn_opcode
= insn
.insn_mo
->match
;
3003 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3007 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3012 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3018 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3023 int tmp
= va_arg (args
, int);
3025 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3026 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3032 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3039 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3043 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3047 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3051 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3055 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3062 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3068 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3069 assert (*r
== BFD_RELOC_GPREL16
3070 || *r
== BFD_RELOC_MIPS_LITERAL
3071 || *r
== BFD_RELOC_MIPS_HIGHER
3072 || *r
== BFD_RELOC_HI16_S
3073 || *r
== BFD_RELOC_LO16
3074 || *r
== BFD_RELOC_MIPS_GOT16
3075 || *r
== BFD_RELOC_MIPS_CALL16
3076 || *r
== BFD_RELOC_MIPS_GOT_DISP
3077 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3078 || *r
== BFD_RELOC_MIPS_GOT_OFST
3079 || *r
== BFD_RELOC_MIPS_GOT_LO16
3080 || *r
== BFD_RELOC_MIPS_CALL_LO16
3081 || (ep
->X_op
== O_subtract
3082 && *r
== BFD_RELOC_PCREL_LO16
));
3086 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3088 && (ep
->X_op
== O_constant
3089 || (ep
->X_op
== O_symbol
3090 && (*r
== BFD_RELOC_MIPS_HIGHEST
3091 || *r
== BFD_RELOC_HI16_S
3092 || *r
== BFD_RELOC_HI16
3093 || *r
== BFD_RELOC_GPREL16
3094 || *r
== BFD_RELOC_MIPS_GOT_HI16
3095 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3096 || (ep
->X_op
== O_subtract
3097 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3101 assert (ep
!= NULL
);
3103 * This allows macro() to pass an immediate expression for
3104 * creating short branches without creating a symbol.
3105 * Note that the expression still might come from the assembly
3106 * input, in which case the value is not checked for range nor
3107 * is a relocation entry generated (yuck).
3109 if (ep
->X_op
== O_constant
)
3111 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3115 *r
= BFD_RELOC_16_PCREL_S2
;
3119 assert (ep
!= NULL
);
3120 *r
= BFD_RELOC_MIPS_JMP
;
3124 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3133 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3135 append_insn (place
, &insn
, ep
, r
);
3139 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3141 int *counter ATTRIBUTE_UNUSED
;
3147 struct mips_cl_insn insn
;
3148 bfd_reloc_code_real_type r
[3]
3149 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3151 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3152 assert (insn
.insn_mo
);
3153 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3155 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3156 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3159 assert (insn
.insn_mo
->name
);
3160 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3163 insn
.insn_opcode
= insn
.insn_mo
->match
;
3164 insn
.use_extend
= FALSE
;
3183 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3188 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3192 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3196 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3206 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3213 regno
= va_arg (args
, int);
3214 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3215 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3236 assert (ep
!= NULL
);
3238 if (ep
->X_op
!= O_constant
)
3239 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3242 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3243 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3246 *r
= BFD_RELOC_UNUSED
;
3252 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3259 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3261 append_insn (place
, &insn
, ep
, r
);
3265 * Generate a "jalr" instruction with a relocation hint to the called
3266 * function. This occurs in NewABI PIC code.
3269 macro_build_jalr (icnt
, ep
)
3280 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3283 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3284 0, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3288 * Generate a "lui" instruction.
3291 macro_build_lui (place
, counter
, ep
, regnum
)
3297 expressionS high_expr
;
3298 struct mips_cl_insn insn
;
3299 bfd_reloc_code_real_type r
[3]
3300 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3301 const char *name
= "lui";
3302 const char *fmt
= "t,u";
3304 assert (! mips_opts
.mips16
);
3310 high_expr
.X_op
= O_constant
;
3311 high_expr
.X_add_number
= ep
->X_add_number
;
3314 if (high_expr
.X_op
== O_constant
)
3316 /* we can compute the instruction now without a relocation entry */
3317 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3319 *r
= BFD_RELOC_UNUSED
;
3323 assert (ep
->X_op
== O_symbol
);
3324 /* _gp_disp is a special case, used from s_cpload. */
3325 assert (mips_pic
== NO_PIC
3327 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3328 *r
= BFD_RELOC_HI16_S
;
3332 * If the macro is about to expand into a second instruction,
3333 * print a warning if needed. We need to pass ip as a parameter
3334 * to generate a better warning message here...
3336 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3337 as_warn (_("Macro instruction expanded into multiple instructions"));
3340 ++*counter
; /* bump instruction counter */
3342 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3343 assert (insn
.insn_mo
);
3344 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3345 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3347 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3348 if (*r
== BFD_RELOC_UNUSED
)
3350 insn
.insn_opcode
|= high_expr
.X_add_number
;
3351 append_insn (place
, &insn
, NULL
, r
);
3354 append_insn (place
, &insn
, &high_expr
, r
);
3357 /* Generate a sequence of instructions to do a load or store from a constant
3358 offset off of a base register (breg) into/from a target register (treg),
3359 using AT if necessary. */
3361 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3368 assert (ep
->X_op
== O_constant
);
3370 /* Right now, this routine can only handle signed 32-bit contants. */
3371 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3372 as_warn (_("operand overflow"));
3374 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3376 /* Signed 16-bit offset will fit in the op. Easy! */
3377 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3378 (int) BFD_RELOC_LO16
, breg
);
3382 /* 32-bit offset, need multiple instructions and AT, like:
3383 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3384 addu $tempreg,$tempreg,$breg
3385 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3386 to handle the complete offset. */
3387 macro_build_lui (place
, counter
, ep
, AT
);
3390 macro_build (place
, counter
, (expressionS
*) NULL
,
3391 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3392 "d,v,t", AT
, AT
, breg
);
3395 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3396 (int) BFD_RELOC_LO16
, AT
);
3399 as_warn (_("Macro used $at after \".set noat\""));
3404 * Generates code to set the $at register to true (one)
3405 * if reg is less than the immediate expression.
3408 set_at (counter
, reg
, unsignedp
)
3413 if (imm_expr
.X_op
== O_constant
3414 && imm_expr
.X_add_number
>= -0x8000
3415 && imm_expr
.X_add_number
< 0x8000)
3416 macro_build ((char *) NULL
, counter
, &imm_expr
,
3417 unsignedp
? "sltiu" : "slti",
3418 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3421 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3422 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3423 unsignedp
? "sltu" : "slt",
3424 "d,v,t", AT
, reg
, AT
);
3428 /* Warn if an expression is not a constant. */
3431 check_absolute_expr (ip
, ex
)
3432 struct mips_cl_insn
*ip
;
3435 if (ex
->X_op
== O_big
)
3436 as_bad (_("unsupported large constant"));
3437 else if (ex
->X_op
!= O_constant
)
3438 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3441 /* Count the leading zeroes by performing a binary chop. This is a
3442 bulky bit of source, but performance is a LOT better for the
3443 majority of values than a simple loop to count the bits:
3444 for (lcnt = 0; (lcnt < 32); lcnt++)
3445 if ((v) & (1 << (31 - lcnt)))
3447 However it is not code size friendly, and the gain will drop a bit
3448 on certain cached systems.
3450 #define COUNT_TOP_ZEROES(v) \
3451 (((v) & ~0xffff) == 0 \
3452 ? ((v) & ~0xff) == 0 \
3453 ? ((v) & ~0xf) == 0 \
3454 ? ((v) & ~0x3) == 0 \
3455 ? ((v) & ~0x1) == 0 \
3460 : ((v) & ~0x7) == 0 \
3463 : ((v) & ~0x3f) == 0 \
3464 ? ((v) & ~0x1f) == 0 \
3467 : ((v) & ~0x7f) == 0 \
3470 : ((v) & ~0xfff) == 0 \
3471 ? ((v) & ~0x3ff) == 0 \
3472 ? ((v) & ~0x1ff) == 0 \
3475 : ((v) & ~0x7ff) == 0 \
3478 : ((v) & ~0x3fff) == 0 \
3479 ? ((v) & ~0x1fff) == 0 \
3482 : ((v) & ~0x7fff) == 0 \
3485 : ((v) & ~0xffffff) == 0 \
3486 ? ((v) & ~0xfffff) == 0 \
3487 ? ((v) & ~0x3ffff) == 0 \
3488 ? ((v) & ~0x1ffff) == 0 \
3491 : ((v) & ~0x7ffff) == 0 \
3494 : ((v) & ~0x3fffff) == 0 \
3495 ? ((v) & ~0x1fffff) == 0 \
3498 : ((v) & ~0x7fffff) == 0 \
3501 : ((v) & ~0xfffffff) == 0 \
3502 ? ((v) & ~0x3ffffff) == 0 \
3503 ? ((v) & ~0x1ffffff) == 0 \
3506 : ((v) & ~0x7ffffff) == 0 \
3509 : ((v) & ~0x3fffffff) == 0 \
3510 ? ((v) & ~0x1fffffff) == 0 \
3513 : ((v) & ~0x7fffffff) == 0 \
3518 * This routine generates the least number of instructions neccessary to load
3519 * an absolute expression value into a register.
3522 load_register (counter
, reg
, ep
, dbl
)
3529 expressionS hi32
, lo32
;
3531 if (ep
->X_op
!= O_big
)
3533 assert (ep
->X_op
== O_constant
);
3534 if (ep
->X_add_number
< 0x8000
3535 && (ep
->X_add_number
>= 0
3536 || (ep
->X_add_number
>= -0x8000
3539 || sizeof (ep
->X_add_number
) > 4))))
3541 /* We can handle 16 bit signed values with an addiu to
3542 $zero. No need to ever use daddiu here, since $zero and
3543 the result are always correct in 32 bit mode. */
3544 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3545 (int) BFD_RELOC_LO16
);
3548 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3550 /* We can handle 16 bit unsigned values with an ori to
3552 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3553 (int) BFD_RELOC_LO16
);
3556 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3559 || sizeof (ep
->X_add_number
) > 4
3560 || (ep
->X_add_number
& 0x80000000) == 0))
3561 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3562 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3565 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3566 == ~ (offsetT
) 0xffffffff)))
3568 /* 32 bit values require an lui. */
3569 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3570 (int) BFD_RELOC_HI16
);
3571 if ((ep
->X_add_number
& 0xffff) != 0)
3572 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3573 (int) BFD_RELOC_LO16
);
3578 /* The value is larger than 32 bits. */
3580 if (HAVE_32BIT_GPRS
)
3582 as_bad (_("Number (0x%lx) larger than 32 bits"),
3583 (unsigned long) ep
->X_add_number
);
3584 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3585 (int) BFD_RELOC_LO16
);
3589 if (ep
->X_op
!= O_big
)
3592 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3593 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3594 hi32
.X_add_number
&= 0xffffffff;
3596 lo32
.X_add_number
&= 0xffffffff;
3600 assert (ep
->X_add_number
> 2);
3601 if (ep
->X_add_number
== 3)
3602 generic_bignum
[3] = 0;
3603 else if (ep
->X_add_number
> 4)
3604 as_bad (_("Number larger than 64 bits"));
3605 lo32
.X_op
= O_constant
;
3606 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3607 hi32
.X_op
= O_constant
;
3608 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3611 if (hi32
.X_add_number
== 0)
3616 unsigned long hi
, lo
;
3618 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3620 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3622 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3623 reg
, 0, (int) BFD_RELOC_LO16
);
3626 if (lo32
.X_add_number
& 0x80000000)
3628 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3629 (int) BFD_RELOC_HI16
);
3630 if (lo32
.X_add_number
& 0xffff)
3631 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3632 reg
, reg
, (int) BFD_RELOC_LO16
);
3637 /* Check for 16bit shifted constant. We know that hi32 is
3638 non-zero, so start the mask on the first bit of the hi32
3643 unsigned long himask
, lomask
;
3647 himask
= 0xffff >> (32 - shift
);
3648 lomask
= (0xffff << shift
) & 0xffffffff;
3652 himask
= 0xffff << (shift
- 32);
3655 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3656 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3660 tmp
.X_op
= O_constant
;
3662 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3663 | (lo32
.X_add_number
>> shift
));
3665 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3666 macro_build ((char *) NULL
, counter
, &tmp
,
3667 "ori", "t,r,i", reg
, 0,
3668 (int) BFD_RELOC_LO16
);
3669 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3670 (shift
>= 32) ? "dsll32" : "dsll",
3672 (shift
>= 32) ? shift
- 32 : shift
);
3677 while (shift
<= (64 - 16));
3679 /* Find the bit number of the lowest one bit, and store the
3680 shifted value in hi/lo. */
3681 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3682 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3686 while ((lo
& 1) == 0)
3691 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3697 while ((hi
& 1) == 0)
3706 /* Optimize if the shifted value is a (power of 2) - 1. */
3707 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3708 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3710 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3715 /* This instruction will set the register to be all
3717 tmp
.X_op
= O_constant
;
3718 tmp
.X_add_number
= (offsetT
) -1;
3719 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3720 reg
, 0, (int) BFD_RELOC_LO16
);
3724 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3725 (bit
>= 32) ? "dsll32" : "dsll",
3727 (bit
>= 32) ? bit
- 32 : bit
);
3729 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3730 (shift
>= 32) ? "dsrl32" : "dsrl",
3732 (shift
>= 32) ? shift
- 32 : shift
);
3737 /* Sign extend hi32 before calling load_register, because we can
3738 generally get better code when we load a sign extended value. */
3739 if ((hi32
.X_add_number
& 0x80000000) != 0)
3740 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3741 load_register (counter
, reg
, &hi32
, 0);
3744 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3748 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3749 "dsll32", "d,w,<", reg
, freg
, 0);
3757 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3759 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3760 (int) BFD_RELOC_HI16
);
3761 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3762 "dsrl32", "d,w,<", reg
, reg
, 0);
3768 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3769 "d,w,<", reg
, freg
, 16);
3773 mid16
.X_add_number
>>= 16;
3774 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3775 freg
, (int) BFD_RELOC_LO16
);
3776 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3777 "d,w,<", reg
, reg
, 16);
3780 if ((lo32
.X_add_number
& 0xffff) != 0)
3781 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3782 (int) BFD_RELOC_LO16
);
3785 /* Load an address into a register. */
3788 load_address (counter
, reg
, ep
, used_at
)
3796 if (ep
->X_op
!= O_constant
3797 && ep
->X_op
!= O_symbol
)
3799 as_bad (_("expression too complex"));
3800 ep
->X_op
= O_constant
;
3803 if (ep
->X_op
== O_constant
)
3805 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3809 if (mips_pic
== NO_PIC
)
3811 /* If this is a reference to a GP relative symbol, we want
3812 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3814 lui $reg,<sym> (BFD_RELOC_HI16_S)
3815 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3816 If we have an addend, we always use the latter form.
3818 With 64bit address space and a usable $at we want
3819 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3820 lui $at,<sym> (BFD_RELOC_HI16_S)
3821 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3822 daddiu $at,<sym> (BFD_RELOC_LO16)
3826 If $at is already in use, we use a path which is suboptimal
3827 on superscalar processors.
3828 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3829 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3831 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3833 daddiu $reg,<sym> (BFD_RELOC_LO16)
3835 if (HAVE_64BIT_ADDRESSES
)
3837 /* We don't do GP optimization for now because RELAX_ENCODE can't
3838 hold the data for such large chunks. */
3840 if (*used_at
== 0 && ! mips_opts
.noat
)
3842 macro_build (p
, counter
, ep
, "lui", "t,u",
3843 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3844 macro_build (p
, counter
, ep
, "lui", "t,u",
3845 AT
, (int) BFD_RELOC_HI16_S
);
3846 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3847 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3848 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3849 AT
, AT
, (int) BFD_RELOC_LO16
);
3850 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3851 "d,w,<", reg
, reg
, 0);
3852 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3853 "d,v,t", reg
, reg
, AT
);
3858 macro_build (p
, counter
, ep
, "lui", "t,u",
3859 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3860 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3861 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3862 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3863 "d,w,<", reg
, reg
, 16);
3864 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3865 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3866 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3867 "d,w,<", reg
, reg
, 16);
3868 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3869 reg
, reg
, (int) BFD_RELOC_LO16
);
3874 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3875 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3878 macro_build ((char *) NULL
, counter
, ep
,
3879 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3880 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3881 p
= frag_var (rs_machine_dependent
, 8, 0,
3882 RELAX_ENCODE (4, 8, 0, 4, 0,
3883 mips_opts
.warn_about_macros
),
3884 ep
->X_add_symbol
, 0, NULL
);
3886 macro_build_lui (p
, counter
, ep
, reg
);
3889 macro_build (p
, counter
, ep
,
3890 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3891 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3894 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3898 /* If this is a reference to an external symbol, we want
3899 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3901 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3903 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3904 If we have NewABI, we want
3905 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3906 If there is a constant, it must be added in after. */
3907 ex
.X_add_number
= ep
->X_add_number
;
3908 ep
->X_add_number
= 0;
3912 macro_build ((char *) NULL
, counter
, ep
,
3913 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3914 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3918 macro_build ((char *) NULL
, counter
, ep
,
3919 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3920 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3921 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3922 p
= frag_var (rs_machine_dependent
, 4, 0,
3923 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3924 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3925 macro_build (p
, counter
, ep
,
3926 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3927 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3930 if (ex
.X_add_number
!= 0)
3932 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3933 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3934 ex
.X_op
= O_constant
;
3935 macro_build ((char *) NULL
, counter
, &ex
,
3936 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3937 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3940 else if (mips_pic
== SVR4_PIC
)
3945 /* This is the large GOT case. If this is a reference to an
3946 external symbol, we want
3947 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3949 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3950 Otherwise, for a reference to a local symbol, we want
3951 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3953 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3954 If we have NewABI, we want
3955 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3956 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3957 If there is a constant, it must be added in after. */
3958 ex
.X_add_number
= ep
->X_add_number
;
3959 ep
->X_add_number
= 0;
3962 macro_build ((char *) NULL
, counter
, ep
,
3963 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3964 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3965 macro_build (p
, counter
, ep
,
3966 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3967 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3971 if (reg_needs_delay (mips_gp_register
))
3976 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3977 (int) BFD_RELOC_MIPS_GOT_HI16
);
3978 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3979 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3980 reg
, mips_gp_register
);
3981 macro_build ((char *) NULL
, counter
, ep
,
3982 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3983 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3984 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3985 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3986 mips_opts
.warn_about_macros
),
3987 ep
->X_add_symbol
, 0, NULL
);
3990 /* We need a nop before loading from $gp. This special
3991 check is required because the lui which starts the main
3992 instruction stream does not refer to $gp, and so will not
3993 insert the nop which may be required. */
3994 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3997 macro_build (p
, counter
, ep
,
3998 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3999 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4001 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4003 macro_build (p
, counter
, ep
,
4004 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4005 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4008 if (ex
.X_add_number
!= 0)
4010 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4011 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4012 ex
.X_op
= O_constant
;
4013 macro_build ((char *) NULL
, counter
, &ex
,
4014 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4015 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4018 else if (mips_pic
== EMBEDDED_PIC
)
4021 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4023 macro_build ((char *) NULL
, counter
, ep
,
4024 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4025 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
4031 /* Move the contents of register SOURCE into register DEST. */
4034 move_register (counter
, dest
, source
)
4039 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4040 HAVE_32BIT_GPRS
? "addu" : "daddu",
4041 "d,v,t", dest
, source
, 0);
4046 * This routine implements the seemingly endless macro or synthesized
4047 * instructions and addressing modes in the mips assembly language. Many
4048 * of these macros are simple and are similar to each other. These could
4049 * probably be handled by some kind of table or grammer aproach instead of
4050 * this verbose method. Others are not simple macros but are more like
4051 * optimizing code generation.
4052 * One interesting optimization is when several store macros appear
4053 * consecutivly that would load AT with the upper half of the same address.
4054 * The ensuing load upper instructions are ommited. This implies some kind
4055 * of global optimization. We currently only optimize within a single macro.
4056 * For many of the load and store macros if the address is specified as a
4057 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4058 * first load register 'at' with zero and use it as the base register. The
4059 * mips assembler simply uses register $zero. Just one tiny optimization
4064 struct mips_cl_insn
*ip
;
4066 register int treg
, sreg
, dreg
, breg
;
4082 bfd_reloc_code_real_type r
;
4083 int hold_mips_optimize
;
4085 assert (! mips_opts
.mips16
);
4087 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4088 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4089 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4090 mask
= ip
->insn_mo
->mask
;
4092 expr1
.X_op
= O_constant
;
4093 expr1
.X_op_symbol
= NULL
;
4094 expr1
.X_add_symbol
= NULL
;
4095 expr1
.X_add_number
= 1;
4097 /* Umatched fixups should not be put in the same frag as a relaxable
4098 macro. For example, suppose we have:
4102 addiu $4,$4,%lo(l1) # 3
4104 If instructions 1 and 2 were put in the same frag, md_frob_file would
4105 move the fixup for #1 after the fixups for the "unrelaxed" version of
4106 #2. This would confuse tc_gen_reloc, which expects the relocations
4107 for #2 to be the last for that frag.
4109 If it looks like this situation could happen, put the macro
4111 if (mips_hi_fixup_list
!= 0
4112 && mips_hi_fixup_list
->fixp
->fx_frag
== frag_now
)
4114 frag_wane (frag_now
);
4128 mips_emit_delays (TRUE
);
4129 ++mips_opts
.noreorder
;
4130 mips_any_noreorder
= 1;
4132 expr1
.X_add_number
= 8;
4133 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4135 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4138 move_register (&icnt
, dreg
, sreg
);
4139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4140 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4142 --mips_opts
.noreorder
;
4163 if (imm_expr
.X_op
== O_constant
4164 && imm_expr
.X_add_number
>= -0x8000
4165 && imm_expr
.X_add_number
< 0x8000)
4167 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4168 (int) BFD_RELOC_LO16
);
4171 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4172 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4192 if (imm_expr
.X_op
== O_constant
4193 && imm_expr
.X_add_number
>= 0
4194 && imm_expr
.X_add_number
< 0x10000)
4196 if (mask
!= M_NOR_I
)
4197 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4198 sreg
, (int) BFD_RELOC_LO16
);
4201 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4202 treg
, sreg
, (int) BFD_RELOC_LO16
);
4203 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4204 "d,v,t", treg
, treg
, 0);
4209 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4210 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4228 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4230 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4234 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4235 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4244 likely
? "bgezl" : "bgez", "s,p", sreg
);
4249 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4250 likely
? "blezl" : "blez", "s,p", treg
);
4253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4255 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4256 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4262 /* check for > max integer */
4263 maxnum
= 0x7fffffff;
4264 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4271 if (imm_expr
.X_op
== O_constant
4272 && imm_expr
.X_add_number
>= maxnum
4273 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4276 /* result is always false */
4280 as_warn (_("Branch %s is always false (nop)"),
4282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4288 as_warn (_("Branch likely %s is always false"),
4290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4295 if (imm_expr
.X_op
!= O_constant
)
4296 as_bad (_("Unsupported large constant"));
4297 ++imm_expr
.X_add_number
;
4301 if (mask
== M_BGEL_I
)
4303 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4305 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4306 likely
? "bgezl" : "bgez", "s,p", sreg
);
4309 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4311 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4312 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4315 maxnum
= 0x7fffffff;
4316 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4323 maxnum
= - maxnum
- 1;
4324 if (imm_expr
.X_op
== O_constant
4325 && imm_expr
.X_add_number
<= maxnum
4326 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4329 /* result is always true */
4330 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4331 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4334 set_at (&icnt
, sreg
, 0);
4335 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4336 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4346 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4347 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4350 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4351 "d,v,t", AT
, sreg
, treg
);
4352 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4353 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4361 && imm_expr
.X_op
== O_constant
4362 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4364 if (imm_expr
.X_op
!= O_constant
)
4365 as_bad (_("Unsupported large constant"));
4366 ++imm_expr
.X_add_number
;
4370 if (mask
== M_BGEUL_I
)
4372 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4374 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4377 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4380 set_at (&icnt
, sreg
, 1);
4381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4382 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4390 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4391 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4396 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4397 likely
? "bltzl" : "bltz", "s,p", treg
);
4400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4402 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4403 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4411 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4412 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4417 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4418 "d,v,t", AT
, treg
, sreg
);
4419 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4420 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4428 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4429 likely
? "blezl" : "blez", "s,p", sreg
);
4434 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4435 likely
? "bgezl" : "bgez", "s,p", treg
);
4438 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4440 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4441 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4447 maxnum
= 0x7fffffff;
4448 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4455 if (imm_expr
.X_op
== O_constant
4456 && imm_expr
.X_add_number
>= maxnum
4457 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4459 if (imm_expr
.X_op
!= O_constant
)
4460 as_bad (_("Unsupported large constant"));
4461 ++imm_expr
.X_add_number
;
4465 if (mask
== M_BLTL_I
)
4467 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4469 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4470 likely
? "bltzl" : "bltz", "s,p", sreg
);
4473 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4475 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4476 likely
? "blezl" : "blez", "s,p", sreg
);
4479 set_at (&icnt
, sreg
, 0);
4480 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4481 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4489 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4490 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4496 "d,v,t", AT
, treg
, sreg
);
4497 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4498 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4506 && imm_expr
.X_op
== O_constant
4507 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4509 if (imm_expr
.X_op
!= O_constant
)
4510 as_bad (_("Unsupported large constant"));
4511 ++imm_expr
.X_add_number
;
4515 if (mask
== M_BLTUL_I
)
4517 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4519 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4521 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4522 likely
? "beql" : "beq",
4526 set_at (&icnt
, sreg
, 1);
4527 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4528 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4536 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4537 likely
? "bltzl" : "bltz", "s,p", sreg
);
4542 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4543 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4546 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4548 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4549 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4559 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4560 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4563 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4566 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4567 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4582 as_warn (_("Divide by zero."));
4584 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4592 mips_emit_delays (TRUE
);
4593 ++mips_opts
.noreorder
;
4594 mips_any_noreorder
= 1;
4597 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4598 "s,t,q", treg
, 0, 7);
4599 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4600 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4604 expr1
.X_add_number
= 8;
4605 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4607 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4608 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4611 expr1
.X_add_number
= -1;
4612 macro_build ((char *) NULL
, &icnt
, &expr1
,
4613 dbl
? "daddiu" : "addiu",
4614 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4615 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4616 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4619 expr1
.X_add_number
= 1;
4620 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4621 (int) BFD_RELOC_LO16
);
4622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4623 "d,w,<", AT
, AT
, 31);
4627 expr1
.X_add_number
= 0x80000000;
4628 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4629 (int) BFD_RELOC_HI16
);
4633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4634 "s,t,q", sreg
, AT
, 6);
4635 /* We want to close the noreorder block as soon as possible, so
4636 that later insns are available for delay slot filling. */
4637 --mips_opts
.noreorder
;
4641 expr1
.X_add_number
= 8;
4642 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4643 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4646 /* We want to close the noreorder block as soon as possible, so
4647 that later insns are available for delay slot filling. */
4648 --mips_opts
.noreorder
;
4650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4653 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4692 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4694 as_warn (_("Divide by zero."));
4696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4703 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4705 if (strcmp (s2
, "mflo") == 0)
4706 move_register (&icnt
, dreg
, sreg
);
4708 move_register (&icnt
, dreg
, 0);
4711 if (imm_expr
.X_op
== O_constant
4712 && imm_expr
.X_add_number
== -1
4713 && s
[strlen (s
) - 1] != 'u')
4715 if (strcmp (s2
, "mflo") == 0)
4717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4718 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4721 move_register (&icnt
, dreg
, 0);
4725 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4747 mips_emit_delays (TRUE
);
4748 ++mips_opts
.noreorder
;
4749 mips_any_noreorder
= 1;
4752 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4753 "s,t,q", treg
, 0, 7);
4754 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4756 /* We want to close the noreorder block as soon as possible, so
4757 that later insns are available for delay slot filling. */
4758 --mips_opts
.noreorder
;
4762 expr1
.X_add_number
= 8;
4763 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4767 /* We want to close the noreorder block as soon as possible, so
4768 that later insns are available for delay slot filling. */
4769 --mips_opts
.noreorder
;
4770 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4773 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4779 /* Load the address of a symbol into a register. If breg is not
4780 zero, we then add a base register to it. */
4782 if (dbl
&& HAVE_32BIT_GPRS
)
4783 as_warn (_("dla used to load 32-bit register"));
4785 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4786 as_warn (_("la used to load 64-bit address"));
4788 if (offset_expr
.X_op
== O_constant
4789 && offset_expr
.X_add_number
>= -0x8000
4790 && offset_expr
.X_add_number
< 0x8000)
4792 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4793 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4794 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4809 /* When generating embedded PIC code, we permit expressions of
4812 la $treg,foo-bar($breg)
4813 where bar is an address in the current section. These are used
4814 when getting the addresses of functions. We don't permit
4815 X_add_number to be non-zero, because if the symbol is
4816 external the relaxing code needs to know that any addend is
4817 purely the offset to X_op_symbol. */
4818 if (mips_pic
== EMBEDDED_PIC
4819 && offset_expr
.X_op
== O_subtract
4820 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4821 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4822 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4824 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4827 && (offset_expr
.X_add_number
== 0
4828 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4834 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4835 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4839 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4840 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4842 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4843 "d,v,t", tempreg
, tempreg
, breg
);
4845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4846 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4847 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4853 if (offset_expr
.X_op
!= O_symbol
4854 && offset_expr
.X_op
!= O_constant
)
4856 as_bad (_("expression too complex"));
4857 offset_expr
.X_op
= O_constant
;
4860 if (offset_expr
.X_op
== O_constant
)
4861 load_register (&icnt
, tempreg
, &offset_expr
,
4862 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4863 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4864 : HAVE_64BIT_ADDRESSES
));
4865 else if (mips_pic
== NO_PIC
)
4867 /* If this is a reference to a GP relative symbol, we want
4868 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4870 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4871 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4872 If we have a constant, we need two instructions anyhow,
4873 so we may as well always use the latter form.
4875 With 64bit address space and a usable $at we want
4876 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4877 lui $at,<sym> (BFD_RELOC_HI16_S)
4878 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4879 daddiu $at,<sym> (BFD_RELOC_LO16)
4881 daddu $tempreg,$tempreg,$at
4883 If $at is already in use, we use a path which is suboptimal
4884 on superscalar processors.
4885 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4886 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4888 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4890 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4893 if (HAVE_64BIT_ADDRESSES
)
4895 /* We don't do GP optimization for now because RELAX_ENCODE can't
4896 hold the data for such large chunks. */
4898 if (used_at
== 0 && ! mips_opts
.noat
)
4900 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4901 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4902 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4903 AT
, (int) BFD_RELOC_HI16_S
);
4904 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4905 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4906 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4907 AT
, AT
, (int) BFD_RELOC_LO16
);
4908 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4909 "d,w,<", tempreg
, tempreg
, 0);
4910 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4911 "d,v,t", tempreg
, tempreg
, AT
);
4916 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4917 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4918 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4919 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4920 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4921 tempreg
, tempreg
, 16);
4922 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4923 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4924 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4925 tempreg
, tempreg
, 16);
4926 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4927 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4932 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4933 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4936 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4937 "t,r,j", tempreg
, mips_gp_register
,
4938 (int) BFD_RELOC_GPREL16
);
4939 p
= frag_var (rs_machine_dependent
, 8, 0,
4940 RELAX_ENCODE (4, 8, 0, 4, 0,
4941 mips_opts
.warn_about_macros
),
4942 offset_expr
.X_add_symbol
, 0, NULL
);
4944 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4947 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4948 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4951 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4953 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4955 /* If this is a reference to an external symbol, and there
4956 is no constant, we want
4957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4958 or if tempreg is PIC_CALL_REG
4959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4960 For a local symbol, we want
4961 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4963 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4965 If we have a small constant, and this is a reference to
4966 an external symbol, we want
4967 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4969 addiu $tempreg,$tempreg,<constant>
4970 For a local symbol, we want the same instruction
4971 sequence, but we output a BFD_RELOC_LO16 reloc on the
4974 If we have a large constant, and this is a reference to
4975 an external symbol, we want
4976 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4977 lui $at,<hiconstant>
4978 addiu $at,$at,<loconstant>
4979 addu $tempreg,$tempreg,$at
4980 For a local symbol, we want the same instruction
4981 sequence, but we output a BFD_RELOC_LO16 reloc on the
4984 For NewABI, we want for local or external data addresses
4985 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4986 For a local function symbol, we want
4987 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4989 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4992 expr1
.X_add_number
= offset_expr
.X_add_number
;
4993 offset_expr
.X_add_number
= 0;
4995 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4996 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4997 else if (HAVE_NEWABI
)
4998 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4999 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5000 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5001 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
5002 if (expr1
.X_add_number
== 0)
5011 /* We're going to put in an addu instruction using
5012 tempreg, so we may as well insert the nop right
5014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5018 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
5019 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
5021 ? mips_opts
.warn_about_macros
5023 offset_expr
.X_add_symbol
, 0, NULL
);
5026 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5029 macro_build (p
, &icnt
, &expr1
,
5030 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5031 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5032 /* FIXME: If breg == 0, and the next instruction uses
5033 $tempreg, then if this variant case is used an extra
5034 nop will be generated. */
5036 else if (expr1
.X_add_number
>= -0x8000
5037 && expr1
.X_add_number
< 0x8000)
5039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5041 macro_build ((char *) NULL
, &icnt
, &expr1
,
5042 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5043 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5044 frag_var (rs_machine_dependent
, 0, 0,
5045 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5046 offset_expr
.X_add_symbol
, 0, NULL
);
5052 /* If we are going to add in a base register, and the
5053 target register and the base register are the same,
5054 then we are using AT as a temporary register. Since
5055 we want to load the constant into AT, we add our
5056 current AT (from the global offset table) and the
5057 register into the register now, and pretend we were
5058 not using a base register. */
5063 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5065 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5066 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5067 "d,v,t", treg
, AT
, breg
);
5073 /* Set mips_optimize around the lui instruction to avoid
5074 inserting an unnecessary nop after the lw. */
5075 hold_mips_optimize
= mips_optimize
;
5077 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5078 mips_optimize
= hold_mips_optimize
;
5080 macro_build ((char *) NULL
, &icnt
, &expr1
,
5081 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5082 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5083 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5084 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5085 "d,v,t", tempreg
, tempreg
, AT
);
5086 frag_var (rs_machine_dependent
, 0, 0,
5087 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5088 offset_expr
.X_add_symbol
, 0, NULL
);
5092 else if (mips_pic
== SVR4_PIC
)
5096 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5097 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5098 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5100 /* This is the large GOT case. If this is a reference to an
5101 external symbol, and there is no constant, we want
5102 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5103 addu $tempreg,$tempreg,$gp
5104 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5105 or if tempreg is PIC_CALL_REG
5106 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5107 addu $tempreg,$tempreg,$gp
5108 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5109 For a local symbol, we want
5110 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5112 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5114 If we have a small constant, and this is a reference to
5115 an external symbol, we want
5116 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5117 addu $tempreg,$tempreg,$gp
5118 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5120 addiu $tempreg,$tempreg,<constant>
5121 For a local symbol, we want
5122 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5124 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5126 If we have a large constant, and this is a reference to
5127 an external symbol, we want
5128 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5129 addu $tempreg,$tempreg,$gp
5130 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5131 lui $at,<hiconstant>
5132 addiu $at,$at,<loconstant>
5133 addu $tempreg,$tempreg,$at
5134 For a local symbol, we want
5135 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5136 lui $at,<hiconstant>
5137 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5138 addu $tempreg,$tempreg,$at
5140 For NewABI, we want for local data addresses
5141 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5144 expr1
.X_add_number
= offset_expr
.X_add_number
;
5145 offset_expr
.X_add_number
= 0;
5147 if (reg_needs_delay (mips_gp_register
))
5151 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5153 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5154 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5156 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5157 tempreg
, lui_reloc_type
);
5158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5159 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5160 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5161 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5162 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5163 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5164 if (expr1
.X_add_number
== 0)
5172 /* We're going to put in an addu instruction using
5173 tempreg, so we may as well insert the nop right
5175 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5180 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5181 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5184 ? mips_opts
.warn_about_macros
5186 offset_expr
.X_add_symbol
, 0, NULL
);
5188 else if (expr1
.X_add_number
>= -0x8000
5189 && expr1
.X_add_number
< 0x8000)
5191 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5193 macro_build ((char *) NULL
, &icnt
, &expr1
,
5194 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5195 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5197 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5198 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5200 ? mips_opts
.warn_about_macros
5202 offset_expr
.X_add_symbol
, 0, NULL
);
5208 /* If we are going to add in a base register, and the
5209 target register and the base register are the same,
5210 then we are using AT as a temporary register. Since
5211 we want to load the constant into AT, we add our
5212 current AT (from the global offset table) and the
5213 register into the register now, and pretend we were
5214 not using a base register. */
5222 assert (tempreg
== AT
);
5223 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5225 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5226 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5227 "d,v,t", treg
, AT
, breg
);
5232 /* Set mips_optimize around the lui instruction to avoid
5233 inserting an unnecessary nop after the lw. */
5234 hold_mips_optimize
= mips_optimize
;
5236 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5237 mips_optimize
= hold_mips_optimize
;
5239 macro_build ((char *) NULL
, &icnt
, &expr1
,
5240 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5241 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5243 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5244 "d,v,t", dreg
, dreg
, AT
);
5246 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5247 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5250 ? mips_opts
.warn_about_macros
5252 offset_expr
.X_add_symbol
, 0, NULL
);
5259 /* This is needed because this instruction uses $gp, but
5260 the first instruction on the main stream does not. */
5261 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5266 local_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5267 macro_build (p
, &icnt
, &offset_expr
,
5268 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5273 if (expr1
.X_add_number
== 0 && HAVE_NEWABI
)
5275 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5278 if (expr1
.X_add_number
>= -0x8000
5279 && expr1
.X_add_number
< 0x8000)
5281 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5283 macro_build (p
, &icnt
, &expr1
,
5284 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5285 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5286 /* FIXME: If add_number is 0, and there was no base
5287 register, the external symbol case ended with a load,
5288 so if the symbol turns out to not be external, and
5289 the next instruction uses tempreg, an unnecessary nop
5290 will be inserted. */
5296 /* We must add in the base register now, as in the
5297 external symbol case. */
5298 assert (tempreg
== AT
);
5299 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5301 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5302 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5303 "d,v,t", treg
, AT
, breg
);
5306 /* We set breg to 0 because we have arranged to add
5307 it in in both cases. */
5311 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5313 macro_build (p
, &icnt
, &expr1
,
5314 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5315 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5317 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5318 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5319 "d,v,t", tempreg
, tempreg
, AT
);
5323 else if (mips_pic
== EMBEDDED_PIC
)
5326 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5328 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5329 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5330 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5339 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5340 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5342 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5344 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5345 "d,v,t", treg
, tempreg
, breg
);
5354 /* The j instruction may not be used in PIC code, since it
5355 requires an absolute address. We convert it to a b
5357 if (mips_pic
== NO_PIC
)
5358 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5360 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5363 /* The jal instructions must be handled as macros because when
5364 generating PIC code they expand to multi-instruction
5365 sequences. Normally they are simple instructions. */
5370 if (mips_pic
== NO_PIC
5371 || mips_pic
== EMBEDDED_PIC
)
5372 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5374 else if (mips_pic
== SVR4_PIC
)
5376 if (sreg
!= PIC_CALL_REG
)
5377 as_warn (_("MIPS PIC call to register other than $25"));
5379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5383 if (mips_cprestore_offset
< 0)
5384 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5387 if (! mips_frame_reg_valid
)
5389 as_warn (_("No .frame pseudo-op used in PIC code"));
5390 /* Quiet this warning. */
5391 mips_frame_reg_valid
= 1;
5393 if (! mips_cprestore_valid
)
5395 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5396 /* Quiet this warning. */
5397 mips_cprestore_valid
= 1;
5399 expr1
.X_add_number
= mips_cprestore_offset
;
5400 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5401 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5402 mips_gp_register
, mips_frame_reg
);
5412 if (mips_pic
== NO_PIC
)
5413 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5414 else if (mips_pic
== SVR4_PIC
)
5418 /* If this is a reference to an external symbol, and we are
5419 using a small GOT, we want
5420 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5424 lw $gp,cprestore($sp)
5425 The cprestore value is set using the .cprestore
5426 pseudo-op. If we are using a big GOT, we want
5427 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5429 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5433 lw $gp,cprestore($sp)
5434 If the symbol is not external, we want
5435 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5437 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5440 lw $gp,cprestore($sp)
5442 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5443 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5447 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5448 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5449 "t,o(b)", PIC_CALL_REG
,
5450 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5451 macro_build_jalr (icnt
, &offset_expr
);
5458 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5459 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5460 "t,o(b)", PIC_CALL_REG
,
5461 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5464 p
= frag_var (rs_machine_dependent
, 4, 0,
5465 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5466 offset_expr
.X_add_symbol
, 0, NULL
);
5472 if (reg_needs_delay (mips_gp_register
))
5476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5477 "t,u", PIC_CALL_REG
,
5478 (int) BFD_RELOC_MIPS_CALL_HI16
);
5479 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5480 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5481 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5483 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5484 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5485 "t,o(b)", PIC_CALL_REG
,
5486 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5487 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5489 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5490 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5492 offset_expr
.X_add_symbol
, 0, NULL
);
5495 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5498 macro_build (p
, &icnt
, &offset_expr
,
5499 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5500 "t,o(b)", PIC_CALL_REG
,
5501 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5503 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5506 macro_build (p
, &icnt
, &offset_expr
,
5507 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5508 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5509 (int) BFD_RELOC_LO16
);
5510 macro_build_jalr (icnt
, &offset_expr
);
5512 if (mips_cprestore_offset
< 0)
5513 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5516 if (! mips_frame_reg_valid
)
5518 as_warn (_("No .frame pseudo-op used in PIC code"));
5519 /* Quiet this warning. */
5520 mips_frame_reg_valid
= 1;
5522 if (! mips_cprestore_valid
)
5524 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5525 /* Quiet this warning. */
5526 mips_cprestore_valid
= 1;
5528 if (mips_opts
.noreorder
)
5529 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5531 expr1
.X_add_number
= mips_cprestore_offset
;
5532 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5533 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5534 mips_gp_register
, mips_frame_reg
);
5538 else if (mips_pic
== EMBEDDED_PIC
)
5540 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5541 /* The linker may expand the call to a longer sequence which
5542 uses $at, so we must break rather than return. */
5567 /* Itbl support may require additional care here. */
5572 /* Itbl support may require additional care here. */
5577 /* Itbl support may require additional care here. */
5582 /* Itbl support may require additional care here. */
5594 if (mips_arch
== CPU_R4650
)
5596 as_bad (_("opcode not supported on this processor"));
5600 /* Itbl support may require additional care here. */
5605 /* Itbl support may require additional care here. */
5610 /* Itbl support may require additional care here. */
5630 if (breg
== treg
|| coproc
|| lr
)
5652 /* Itbl support may require additional care here. */
5657 /* Itbl support may require additional care here. */
5662 /* Itbl support may require additional care here. */
5667 /* Itbl support may require additional care here. */
5683 if (mips_arch
== CPU_R4650
)
5685 as_bad (_("opcode not supported on this processor"));
5690 /* Itbl support may require additional care here. */
5694 /* Itbl support may require additional care here. */
5699 /* Itbl support may require additional care here. */
5711 /* Itbl support may require additional care here. */
5712 if (mask
== M_LWC1_AB
5713 || mask
== M_SWC1_AB
5714 || mask
== M_LDC1_AB
5715 || mask
== M_SDC1_AB
5724 /* For embedded PIC, we allow loads where the offset is calculated
5725 by subtracting a symbol in the current segment from an unknown
5726 symbol, relative to a base register, e.g.:
5727 <op> $treg, <sym>-<localsym>($breg)
5728 This is used by the compiler for switch statements. */
5729 if (mips_pic
== EMBEDDED_PIC
5730 && offset_expr
.X_op
== O_subtract
5731 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5732 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5733 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5735 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5739 && (offset_expr
.X_add_number
== 0
5740 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5742 /* For this case, we output the instructions:
5743 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5744 addiu $tempreg,$tempreg,$breg
5745 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5746 If the relocation would fit entirely in 16 bits, it would be
5748 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5749 instead, but that seems quite difficult. */
5750 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5751 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5752 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5753 ((bfd_arch_bits_per_address (stdoutput
) == 32
5754 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5755 ? "addu" : "daddu"),
5756 "d,v,t", tempreg
, tempreg
, breg
);
5757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5758 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5764 if (offset_expr
.X_op
!= O_constant
5765 && offset_expr
.X_op
!= O_symbol
)
5767 as_bad (_("expression too complex"));
5768 offset_expr
.X_op
= O_constant
;
5771 /* A constant expression in PIC code can be handled just as it
5772 is in non PIC code. */
5773 if (mips_pic
== NO_PIC
5774 || offset_expr
.X_op
== O_constant
)
5778 /* If this is a reference to a GP relative symbol, and there
5779 is no base register, we want
5780 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5781 Otherwise, if there is no base register, we want
5782 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5783 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5784 If we have a constant, we need two instructions anyhow,
5785 so we always use the latter form.
5787 If we have a base register, and this is a reference to a
5788 GP relative symbol, we want
5789 addu $tempreg,$breg,$gp
5790 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5792 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5793 addu $tempreg,$tempreg,$breg
5794 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5795 With a constant we always use the latter case.
5797 With 64bit address space and no base register and $at usable,
5799 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5800 lui $at,<sym> (BFD_RELOC_HI16_S)
5801 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5804 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5805 If we have a base register, we want
5806 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5807 lui $at,<sym> (BFD_RELOC_HI16_S)
5808 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5812 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5814 Without $at we can't generate the optimal path for superscalar
5815 processors here since this would require two temporary registers.
5816 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5817 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5819 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5821 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5822 If we have a base register, we want
5823 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5824 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5826 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5828 daddu $tempreg,$tempreg,$breg
5829 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5831 If we have 64-bit addresses, as an optimization, for
5832 addresses which are 32-bit constants (e.g. kseg0/kseg1
5833 addresses) we fall back to the 32-bit address generation
5834 mechanism since it is more efficient. Note that due to
5835 the signed offset used by memory operations, the 32-bit
5836 range is shifted down by 32768 here. This code should
5837 probably attempt to generate 64-bit constants more
5838 efficiently in general.
5840 if (HAVE_64BIT_ADDRESSES
5841 && !(offset_expr
.X_op
== O_constant
5842 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5846 /* We don't do GP optimization for now because RELAX_ENCODE can't
5847 hold the data for such large chunks. */
5849 if (used_at
== 0 && ! mips_opts
.noat
)
5851 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5852 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5853 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5854 AT
, (int) BFD_RELOC_HI16_S
);
5855 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5856 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5858 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5859 "d,v,t", AT
, AT
, breg
);
5860 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5861 "d,w,<", tempreg
, tempreg
, 0);
5862 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5863 "d,v,t", tempreg
, tempreg
, AT
);
5864 macro_build (p
, &icnt
, &offset_expr
, s
,
5865 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5870 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5871 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5872 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5873 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5874 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5875 "d,w,<", tempreg
, tempreg
, 16);
5876 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5877 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5878 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5879 "d,w,<", tempreg
, tempreg
, 16);
5881 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5882 "d,v,t", tempreg
, tempreg
, breg
);
5883 macro_build (p
, &icnt
, &offset_expr
, s
,
5884 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5892 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5893 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5898 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5899 treg
, (int) BFD_RELOC_GPREL16
,
5901 p
= frag_var (rs_machine_dependent
, 8, 0,
5902 RELAX_ENCODE (4, 8, 0, 4, 0,
5903 (mips_opts
.warn_about_macros
5905 && mips_opts
.noat
))),
5906 offset_expr
.X_add_symbol
, 0, NULL
);
5909 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5912 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5913 (int) BFD_RELOC_LO16
, tempreg
);
5917 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5918 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5924 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5925 "d,v,t", tempreg
, breg
, mips_gp_register
);
5926 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5927 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5928 p
= frag_var (rs_machine_dependent
, 12, 0,
5929 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5930 offset_expr
.X_add_symbol
, 0, NULL
);
5932 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5935 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5936 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5937 "d,v,t", tempreg
, tempreg
, breg
);
5940 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5941 (int) BFD_RELOC_LO16
, tempreg
);
5944 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5947 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5949 /* If this is a reference to an external symbol, we want
5950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5952 <op> $treg,0($tempreg)
5954 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5956 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5957 <op> $treg,0($tempreg)
5958 If we have NewABI, we want
5959 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5960 If there is a base register, we add it to $tempreg before
5961 the <op>. If there is a constant, we stick it in the
5962 <op> instruction. We don't handle constants larger than
5963 16 bits, because we have no way to load the upper 16 bits
5964 (actually, we could handle them for the subset of cases
5965 in which we are not using $at). */
5966 assert (offset_expr
.X_op
== O_symbol
);
5967 expr1
.X_add_number
= offset_expr
.X_add_number
;
5968 offset_expr
.X_add_number
= 0;
5970 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5971 if (expr1
.X_add_number
< -0x8000
5972 || expr1
.X_add_number
>= 0x8000)
5973 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5975 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5976 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5977 (int) lw_reloc_type
, mips_gp_register
);
5978 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5979 p
= frag_var (rs_machine_dependent
, 4, 0,
5980 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5981 offset_expr
.X_add_symbol
, 0, NULL
);
5982 macro_build (p
, &icnt
, &offset_expr
,
5983 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5984 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5986 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5987 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5988 "d,v,t", tempreg
, tempreg
, breg
);
5989 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5990 (int) BFD_RELOC_LO16
, tempreg
);
5992 else if (mips_pic
== SVR4_PIC
)
5997 /* If this is a reference to an external symbol, we want
5998 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5999 addu $tempreg,$tempreg,$gp
6000 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6001 <op> $treg,0($tempreg)
6003 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6005 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6006 <op> $treg,0($tempreg)
6007 If there is a base register, we add it to $tempreg before
6008 the <op>. If there is a constant, we stick it in the
6009 <op> instruction. We don't handle constants larger than
6010 16 bits, because we have no way to load the upper 16 bits
6011 (actually, we could handle them for the subset of cases
6012 in which we are not using $at).
6015 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6016 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6017 <op> $treg,0($tempreg)
6019 assert (offset_expr
.X_op
== O_symbol
);
6020 expr1
.X_add_number
= offset_expr
.X_add_number
;
6021 offset_expr
.X_add_number
= 0;
6022 if (expr1
.X_add_number
< -0x8000
6023 || expr1
.X_add_number
>= 0x8000)
6024 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6027 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6028 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6029 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
6031 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6032 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6033 "t,r,j", tempreg
, tempreg
,
6034 BFD_RELOC_MIPS_GOT_OFST
);
6036 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6037 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6038 "d,v,t", tempreg
, tempreg
, breg
);
6039 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6040 (int) BFD_RELOC_LO16
, tempreg
);
6047 if (reg_needs_delay (mips_gp_register
))
6052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6053 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6054 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6055 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6056 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
6057 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6058 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6059 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6061 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
6062 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
6063 offset_expr
.X_add_symbol
, 0, NULL
);
6066 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6069 macro_build (p
, &icnt
, &offset_expr
,
6070 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6071 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
6074 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6076 macro_build (p
, &icnt
, &offset_expr
,
6077 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6078 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6081 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6082 "d,v,t", tempreg
, tempreg
, breg
);
6083 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6084 (int) BFD_RELOC_LO16
, tempreg
);
6086 else if (mips_pic
== EMBEDDED_PIC
)
6088 /* If there is no base register, we want
6089 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6090 If there is a base register, we want
6091 addu $tempreg,$breg,$gp
6092 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6094 assert (offset_expr
.X_op
== O_symbol
);
6097 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6098 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
6103 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6104 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6105 "d,v,t", tempreg
, breg
, mips_gp_register
);
6106 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6107 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6120 load_register (&icnt
, treg
, &imm_expr
, 0);
6124 load_register (&icnt
, treg
, &imm_expr
, 1);
6128 if (imm_expr
.X_op
== O_constant
)
6130 load_register (&icnt
, AT
, &imm_expr
, 0);
6131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6132 "mtc1", "t,G", AT
, treg
);
6137 assert (offset_expr
.X_op
== O_symbol
6138 && strcmp (segment_name (S_GET_SEGMENT
6139 (offset_expr
.X_add_symbol
)),
6141 && offset_expr
.X_add_number
== 0);
6142 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6143 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6148 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6149 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6150 order 32 bits of the value and the low order 32 bits are either
6151 zero or in OFFSET_EXPR. */
6152 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6154 if (HAVE_64BIT_GPRS
)
6155 load_register (&icnt
, treg
, &imm_expr
, 1);
6160 if (target_big_endian
)
6172 load_register (&icnt
, hreg
, &imm_expr
, 0);
6175 if (offset_expr
.X_op
== O_absent
)
6176 move_register (&icnt
, lreg
, 0);
6179 assert (offset_expr
.X_op
== O_constant
);
6180 load_register (&icnt
, lreg
, &offset_expr
, 0);
6187 /* We know that sym is in the .rdata section. First we get the
6188 upper 16 bits of the address. */
6189 if (mips_pic
== NO_PIC
)
6191 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6193 else if (mips_pic
== SVR4_PIC
)
6195 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6196 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6197 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6200 else if (mips_pic
== EMBEDDED_PIC
)
6202 /* For embedded PIC we pick up the entire address off $gp in
6203 a single instruction. */
6204 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6205 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
6206 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
6207 offset_expr
.X_op
= O_constant
;
6208 offset_expr
.X_add_number
= 0;
6213 /* Now we load the register(s). */
6214 if (HAVE_64BIT_GPRS
)
6215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6216 treg
, (int) BFD_RELOC_LO16
, AT
);
6219 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6220 treg
, (int) BFD_RELOC_LO16
, AT
);
6223 /* FIXME: How in the world do we deal with the possible
6225 offset_expr
.X_add_number
+= 4;
6226 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6227 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6231 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6232 does not become a variant frag. */
6233 frag_wane (frag_now
);
6239 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6240 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6241 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6242 the value and the low order 32 bits are either zero or in
6244 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6246 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6247 if (HAVE_64BIT_FPRS
)
6249 assert (HAVE_64BIT_GPRS
);
6250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6251 "dmtc1", "t,S", AT
, treg
);
6255 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6256 "mtc1", "t,G", AT
, treg
+ 1);
6257 if (offset_expr
.X_op
== O_absent
)
6258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6259 "mtc1", "t,G", 0, treg
);
6262 assert (offset_expr
.X_op
== O_constant
);
6263 load_register (&icnt
, AT
, &offset_expr
, 0);
6264 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6265 "mtc1", "t,G", AT
, treg
);
6271 assert (offset_expr
.X_op
== O_symbol
6272 && offset_expr
.X_add_number
== 0);
6273 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6274 if (strcmp (s
, ".lit8") == 0)
6276 if (mips_opts
.isa
!= ISA_MIPS1
)
6278 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6279 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6283 breg
= mips_gp_register
;
6284 r
= BFD_RELOC_MIPS_LITERAL
;
6289 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6290 if (mips_pic
== SVR4_PIC
)
6291 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6292 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6293 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6297 /* FIXME: This won't work for a 64 bit address. */
6298 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6301 if (mips_opts
.isa
!= ISA_MIPS1
)
6303 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6304 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6306 /* To avoid confusion in tc_gen_reloc, we must ensure
6307 that this does not become a variant frag. */
6308 frag_wane (frag_now
);
6319 if (mips_arch
== CPU_R4650
)
6321 as_bad (_("opcode not supported on this processor"));
6324 /* Even on a big endian machine $fn comes before $fn+1. We have
6325 to adjust when loading from memory. */
6328 assert (mips_opts
.isa
== ISA_MIPS1
);
6329 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6330 target_big_endian
? treg
+ 1 : treg
,
6332 /* FIXME: A possible overflow which I don't know how to deal
6334 offset_expr
.X_add_number
+= 4;
6335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6336 target_big_endian
? treg
: treg
+ 1,
6339 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6340 does not become a variant frag. */
6341 frag_wane (frag_now
);
6350 * The MIPS assembler seems to check for X_add_number not
6351 * being double aligned and generating:
6354 * addiu at,at,%lo(foo+1)
6357 * But, the resulting address is the same after relocation so why
6358 * generate the extra instruction?
6360 if (mips_arch
== CPU_R4650
)
6362 as_bad (_("opcode not supported on this processor"));
6365 /* Itbl support may require additional care here. */
6367 if (mips_opts
.isa
!= ISA_MIPS1
)
6378 if (mips_arch
== CPU_R4650
)
6380 as_bad (_("opcode not supported on this processor"));
6384 if (mips_opts
.isa
!= ISA_MIPS1
)
6392 /* Itbl support may require additional care here. */
6397 if (HAVE_64BIT_GPRS
)
6408 if (HAVE_64BIT_GPRS
)
6418 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6419 loads for the case of doing a pair of loads to simulate an 'ld'.
6420 This is not currently done by the compiler, and assembly coders
6421 writing embedded-pic code can cope. */
6423 if (offset_expr
.X_op
!= O_symbol
6424 && offset_expr
.X_op
!= O_constant
)
6426 as_bad (_("expression too complex"));
6427 offset_expr
.X_op
= O_constant
;
6430 /* Even on a big endian machine $fn comes before $fn+1. We have
6431 to adjust when loading from memory. We set coproc if we must
6432 load $fn+1 first. */
6433 /* Itbl support may require additional care here. */
6434 if (! target_big_endian
)
6437 if (mips_pic
== NO_PIC
6438 || offset_expr
.X_op
== O_constant
)
6442 /* If this is a reference to a GP relative symbol, we want
6443 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6444 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6445 If we have a base register, we use this
6447 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6448 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6449 If this is not a GP relative symbol, we want
6450 lui $at,<sym> (BFD_RELOC_HI16_S)
6451 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6452 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6453 If there is a base register, we add it to $at after the
6454 lui instruction. If there is a constant, we always use
6456 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6457 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6469 tempreg
= mips_gp_register
;
6476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6477 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6478 "d,v,t", AT
, breg
, mips_gp_register
);
6484 /* Itbl support may require additional care here. */
6485 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6486 coproc
? treg
+ 1 : treg
,
6487 (int) BFD_RELOC_GPREL16
, tempreg
);
6488 offset_expr
.X_add_number
+= 4;
6490 /* Set mips_optimize to 2 to avoid inserting an
6492 hold_mips_optimize
= mips_optimize
;
6494 /* Itbl support may require additional care here. */
6495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6496 coproc
? treg
: treg
+ 1,
6497 (int) BFD_RELOC_GPREL16
, tempreg
);
6498 mips_optimize
= hold_mips_optimize
;
6500 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6501 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6502 used_at
&& mips_opts
.noat
),
6503 offset_expr
.X_add_symbol
, 0, NULL
);
6505 /* We just generated two relocs. When tc_gen_reloc
6506 handles this case, it will skip the first reloc and
6507 handle the second. The second reloc already has an
6508 extra addend of 4, which we added above. We must
6509 subtract it out, and then subtract another 4 to make
6510 the first reloc come out right. The second reloc
6511 will come out right because we are going to add 4 to
6512 offset_expr when we build its instruction below.
6514 If we have a symbol, then we don't want to include
6515 the offset, because it will wind up being included
6516 when we generate the reloc. */
6518 if (offset_expr
.X_op
== O_constant
)
6519 offset_expr
.X_add_number
-= 8;
6522 offset_expr
.X_add_number
= -4;
6523 offset_expr
.X_op
= O_constant
;
6526 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6531 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6532 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6533 "d,v,t", AT
, breg
, AT
);
6537 /* Itbl support may require additional care here. */
6538 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6539 coproc
? treg
+ 1 : treg
,
6540 (int) BFD_RELOC_LO16
, AT
);
6543 /* FIXME: How do we handle overflow here? */
6544 offset_expr
.X_add_number
+= 4;
6545 /* Itbl support may require additional care here. */
6546 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6547 coproc
? treg
: treg
+ 1,
6548 (int) BFD_RELOC_LO16
, AT
);
6550 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6554 /* If this is a reference to an external symbol, we want
6555 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6560 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6562 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6563 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6564 If there is a base register we add it to $at before the
6565 lwc1 instructions. If there is a constant we include it
6566 in the lwc1 instructions. */
6568 expr1
.X_add_number
= offset_expr
.X_add_number
;
6569 offset_expr
.X_add_number
= 0;
6570 if (expr1
.X_add_number
< -0x8000
6571 || expr1
.X_add_number
>= 0x8000 - 4)
6572 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6577 frag_grow (24 + off
);
6578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6579 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6580 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6581 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6583 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6584 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6585 "d,v,t", AT
, breg
, AT
);
6586 /* Itbl support may require additional care here. */
6587 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6588 coproc
? treg
+ 1 : treg
,
6589 (int) BFD_RELOC_LO16
, AT
);
6590 expr1
.X_add_number
+= 4;
6592 /* Set mips_optimize to 2 to avoid inserting an undesired
6594 hold_mips_optimize
= mips_optimize
;
6596 /* Itbl support may require additional care here. */
6597 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6598 coproc
? treg
: treg
+ 1,
6599 (int) BFD_RELOC_LO16
, AT
);
6600 mips_optimize
= hold_mips_optimize
;
6602 (void) frag_var (rs_machine_dependent
, 0, 0,
6603 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6604 offset_expr
.X_add_symbol
, 0, NULL
);
6606 else if (mips_pic
== SVR4_PIC
)
6611 /* If this is a reference to an external symbol, we want
6612 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6614 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6619 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6621 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6622 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6623 If there is a base register we add it to $at before the
6624 lwc1 instructions. If there is a constant we include it
6625 in the lwc1 instructions. */
6627 expr1
.X_add_number
= offset_expr
.X_add_number
;
6628 offset_expr
.X_add_number
= 0;
6629 if (expr1
.X_add_number
< -0x8000
6630 || expr1
.X_add_number
>= 0x8000 - 4)
6631 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6632 if (reg_needs_delay (mips_gp_register
))
6641 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6642 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6643 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6644 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6645 "d,v,t", AT
, AT
, mips_gp_register
);
6646 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6647 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6648 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6649 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6651 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6652 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6653 "d,v,t", AT
, breg
, AT
);
6654 /* Itbl support may require additional care here. */
6655 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6656 coproc
? treg
+ 1 : treg
,
6657 (int) BFD_RELOC_LO16
, AT
);
6658 expr1
.X_add_number
+= 4;
6660 /* Set mips_optimize to 2 to avoid inserting an undesired
6662 hold_mips_optimize
= mips_optimize
;
6664 /* Itbl support may require additional care here. */
6665 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6666 coproc
? treg
: treg
+ 1,
6667 (int) BFD_RELOC_LO16
, AT
);
6668 mips_optimize
= hold_mips_optimize
;
6669 expr1
.X_add_number
-= 4;
6671 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6672 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6673 8 + gpdel
+ off
, 1, 0),
6674 offset_expr
.X_add_symbol
, 0, NULL
);
6677 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6680 macro_build (p
, &icnt
, &offset_expr
,
6681 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6682 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6685 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6689 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6690 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6691 "d,v,t", AT
, breg
, AT
);
6694 /* Itbl support may require additional care here. */
6695 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6696 coproc
? treg
+ 1 : treg
,
6697 (int) BFD_RELOC_LO16
, AT
);
6699 expr1
.X_add_number
+= 4;
6701 /* Set mips_optimize to 2 to avoid inserting an undesired
6703 hold_mips_optimize
= mips_optimize
;
6705 /* Itbl support may require additional care here. */
6706 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6707 coproc
? treg
: treg
+ 1,
6708 (int) BFD_RELOC_LO16
, AT
);
6709 mips_optimize
= hold_mips_optimize
;
6711 else if (mips_pic
== EMBEDDED_PIC
)
6713 /* If there is no base register, we use
6714 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6715 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6716 If we have a base register, we use
6718 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6719 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6723 tempreg
= mips_gp_register
;
6728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6729 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6730 "d,v,t", AT
, breg
, mips_gp_register
);
6735 /* Itbl support may require additional care here. */
6736 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6737 coproc
? treg
+ 1 : treg
,
6738 (int) BFD_RELOC_GPREL16
, tempreg
);
6739 offset_expr
.X_add_number
+= 4;
6740 /* Itbl support may require additional care here. */
6741 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6742 coproc
? treg
: treg
+ 1,
6743 (int) BFD_RELOC_GPREL16
, tempreg
);
6759 assert (HAVE_32BIT_ADDRESSES
);
6760 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6761 (int) BFD_RELOC_LO16
, breg
);
6762 offset_expr
.X_add_number
+= 4;
6763 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6764 (int) BFD_RELOC_LO16
, breg
);
6767 /* New code added to support COPZ instructions.
6768 This code builds table entries out of the macros in mip_opcodes.
6769 R4000 uses interlocks to handle coproc delays.
6770 Other chips (like the R3000) require nops to be inserted for delays.
6772 FIXME: Currently, we require that the user handle delays.
6773 In order to fill delay slots for non-interlocked chips,
6774 we must have a way to specify delays based on the coprocessor.
6775 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6776 What are the side-effects of the cop instruction?
6777 What cache support might we have and what are its effects?
6778 Both coprocessor & memory require delays. how long???
6779 What registers are read/set/modified?
6781 If an itbl is provided to interpret cop instructions,
6782 this knowledge can be encoded in the itbl spec. */
6796 /* For now we just do C (same as Cz). The parameter will be
6797 stored in insn_opcode by mips_ip. */
6798 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6803 move_register (&icnt
, dreg
, sreg
);
6806 #ifdef LOSING_COMPILER
6808 /* Try and see if this is a new itbl instruction.
6809 This code builds table entries out of the macros in mip_opcodes.
6810 FIXME: For now we just assemble the expression and pass it's
6811 value along as a 32-bit immediate.
6812 We may want to have the assembler assemble this value,
6813 so that we gain the assembler's knowledge of delay slots,
6815 Would it be more efficient to use mask (id) here? */
6816 if (itbl_have_entries
6817 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6819 s
= ip
->insn_mo
->name
;
6821 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6822 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6829 as_warn (_("Macro used $at after \".set noat\""));
6834 struct mips_cl_insn
*ip
;
6836 register int treg
, sreg
, dreg
, breg
;
6852 bfd_reloc_code_real_type r
;
6855 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6856 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6857 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6858 mask
= ip
->insn_mo
->mask
;
6860 expr1
.X_op
= O_constant
;
6861 expr1
.X_op_symbol
= NULL
;
6862 expr1
.X_add_symbol
= NULL
;
6863 expr1
.X_add_number
= 1;
6867 #endif /* LOSING_COMPILER */
6872 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6873 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6881 /* The MIPS assembler some times generates shifts and adds. I'm
6882 not trying to be that fancy. GCC should do this for us
6884 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6885 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6886 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6887 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6901 mips_emit_delays (TRUE
);
6902 ++mips_opts
.noreorder
;
6903 mips_any_noreorder
= 1;
6905 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6906 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6907 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6911 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6916 "s,t,q", dreg
, AT
, 6);
6919 expr1
.X_add_number
= 8;
6920 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6922 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6924 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6927 --mips_opts
.noreorder
;
6928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6941 mips_emit_delays (TRUE
);
6942 ++mips_opts
.noreorder
;
6943 mips_any_noreorder
= 1;
6945 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6946 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6947 dbl
? "dmultu" : "multu",
6948 "s,t", sreg
, imm
? AT
: treg
);
6949 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6951 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6954 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6958 expr1
.X_add_number
= 8;
6959 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6960 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6962 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6965 --mips_opts
.noreorder
;
6969 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
6981 macro_build ((char *) NULL
, &icnt
, NULL
, "dnegu",
6982 "d,w", tempreg
, treg
);
6983 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
6984 "d,t,s", dreg
, sreg
, tempreg
);
6989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6990 "d,v,t", AT
, 0, treg
);
6991 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6992 "d,t,s", AT
, sreg
, AT
);
6993 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6994 "d,t,s", dreg
, sreg
, treg
);
6995 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6996 "d,v,t", dreg
, dreg
, AT
);
7000 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7012 macro_build ((char *) NULL
, &icnt
, NULL
, "negu",
7013 "d,w", tempreg
, treg
);
7014 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7015 "d,t,s", dreg
, sreg
, tempreg
);
7020 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7021 "d,v,t", AT
, 0, treg
);
7022 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7023 "d,t,s", AT
, sreg
, AT
);
7024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7025 "d,t,s", dreg
, sreg
, treg
);
7026 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7027 "d,v,t", dreg
, dreg
, AT
);
7035 if (imm_expr
.X_op
!= O_constant
)
7036 as_bad (_("Improper rotate count"));
7037 rot
= imm_expr
.X_add_number
& 0x3f;
7038 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7040 rot
= (64 - rot
) & 0x3f;
7042 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7043 "d,w,<", dreg
, sreg
, rot
- 32);
7045 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7046 "d,w,<", dreg
, sreg
, rot
);
7051 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7052 "d,w,<", dreg
, sreg
, 0);
7055 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7056 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7058 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7059 "d,w,<", AT
, sreg
, rot
);
7060 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7061 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7063 "d,v,t", dreg
, dreg
, AT
);
7071 if (imm_expr
.X_op
!= O_constant
)
7072 as_bad (_("Improper rotate count"));
7073 rot
= imm_expr
.X_add_number
& 0x1f;
7074 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7076 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7077 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7083 "d,w,<", dreg
, sreg
, 0);
7086 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7087 "d,w,<", AT
, sreg
, rot
);
7088 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7089 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7090 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7091 "d,v,t", dreg
, dreg
, AT
);
7096 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7098 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7099 "d,t,s", dreg
, sreg
, treg
);
7102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7103 "d,v,t", AT
, 0, treg
);
7104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7105 "d,t,s", AT
, sreg
, AT
);
7106 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7107 "d,t,s", dreg
, sreg
, treg
);
7108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7109 "d,v,t", dreg
, dreg
, AT
);
7113 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7115 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7116 "d,t,s", dreg
, sreg
, treg
);
7119 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7120 "d,v,t", AT
, 0, treg
);
7121 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7122 "d,t,s", AT
, sreg
, AT
);
7123 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7124 "d,t,s", dreg
, sreg
, treg
);
7125 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7126 "d,v,t", dreg
, dreg
, AT
);
7134 if (imm_expr
.X_op
!= O_constant
)
7135 as_bad (_("Improper rotate count"));
7136 rot
= imm_expr
.X_add_number
& 0x3f;
7137 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_arch
))
7140 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7141 "d,w,<", dreg
, sreg
, rot
- 32);
7143 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7144 "d,w,<", dreg
, sreg
, rot
);
7149 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7150 "d,w,<", dreg
, sreg
, 0);
7153 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7154 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7156 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7157 "d,w,<", AT
, sreg
, rot
);
7158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7159 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7160 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7161 "d,v,t", dreg
, dreg
, AT
);
7169 if (imm_expr
.X_op
!= O_constant
)
7170 as_bad (_("Improper rotate count"));
7171 rot
= imm_expr
.X_add_number
& 0x1f;
7172 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_arch
))
7174 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7175 "d,w,<", dreg
, sreg
, rot
);
7180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7181 "d,w,<", dreg
, sreg
, 0);
7184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7185 "d,w,<", AT
, sreg
, rot
);
7186 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7187 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7188 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7189 "d,v,t", dreg
, dreg
, AT
);
7194 if (mips_arch
== CPU_R4650
)
7196 as_bad (_("opcode not supported on this processor"));
7199 assert (mips_opts
.isa
== ISA_MIPS1
);
7200 /* Even on a big endian machine $fn comes before $fn+1. We have
7201 to adjust when storing to memory. */
7202 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7203 target_big_endian
? treg
+ 1 : treg
,
7204 (int) BFD_RELOC_LO16
, breg
);
7205 offset_expr
.X_add_number
+= 4;
7206 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7207 target_big_endian
? treg
: treg
+ 1,
7208 (int) BFD_RELOC_LO16
, breg
);
7213 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7214 treg
, (int) BFD_RELOC_LO16
);
7216 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7217 sreg
, (int) BFD_RELOC_LO16
);
7220 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7221 "d,v,t", dreg
, sreg
, treg
);
7222 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7223 dreg
, (int) BFD_RELOC_LO16
);
7228 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7230 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7231 sreg
, (int) BFD_RELOC_LO16
);
7236 as_warn (_("Instruction %s: result is always false"),
7238 move_register (&icnt
, dreg
, 0);
7241 if (imm_expr
.X_op
== O_constant
7242 && imm_expr
.X_add_number
>= 0
7243 && imm_expr
.X_add_number
< 0x10000)
7245 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
7246 sreg
, (int) BFD_RELOC_LO16
);
7249 else if (imm_expr
.X_op
== O_constant
7250 && imm_expr
.X_add_number
> -0x8000
7251 && imm_expr
.X_add_number
< 0)
7253 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7254 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7255 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7256 "t,r,j", dreg
, sreg
,
7257 (int) BFD_RELOC_LO16
);
7262 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7263 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7264 "d,v,t", dreg
, sreg
, AT
);
7267 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7268 (int) BFD_RELOC_LO16
);
7273 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7279 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7281 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7282 (int) BFD_RELOC_LO16
);
7285 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7287 if (imm_expr
.X_op
== O_constant
7288 && imm_expr
.X_add_number
>= -0x8000
7289 && imm_expr
.X_add_number
< 0x8000)
7291 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7292 mask
== M_SGE_I
? "slti" : "sltiu",
7293 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7298 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7299 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7300 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7304 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7305 (int) BFD_RELOC_LO16
);
7310 case M_SGT
: /* sreg > treg <==> treg < sreg */
7316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7320 case M_SGT_I
: /* sreg > I <==> I < sreg */
7326 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7331 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7339 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7340 (int) BFD_RELOC_LO16
);
7343 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7349 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7350 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7352 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7353 (int) BFD_RELOC_LO16
);
7357 if (imm_expr
.X_op
== O_constant
7358 && imm_expr
.X_add_number
>= -0x8000
7359 && imm_expr
.X_add_number
< 0x8000)
7361 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7362 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7365 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7366 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7371 if (imm_expr
.X_op
== O_constant
7372 && imm_expr
.X_add_number
>= -0x8000
7373 && imm_expr
.X_add_number
< 0x8000)
7375 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7376 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7379 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7380 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7381 "d,v,t", dreg
, sreg
, AT
);
7386 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7387 "d,v,t", dreg
, 0, treg
);
7389 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7390 "d,v,t", dreg
, 0, sreg
);
7393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7394 "d,v,t", dreg
, sreg
, treg
);
7395 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7396 "d,v,t", dreg
, 0, dreg
);
7401 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7403 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7404 "d,v,t", dreg
, 0, sreg
);
7409 as_warn (_("Instruction %s: result is always true"),
7411 macro_build ((char *) NULL
, &icnt
, &expr1
,
7412 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7413 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7416 if (imm_expr
.X_op
== O_constant
7417 && imm_expr
.X_add_number
>= 0
7418 && imm_expr
.X_add_number
< 0x10000)
7420 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7421 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7424 else if (imm_expr
.X_op
== O_constant
7425 && imm_expr
.X_add_number
> -0x8000
7426 && imm_expr
.X_add_number
< 0)
7428 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7429 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7430 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7431 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7436 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7438 "d,v,t", dreg
, sreg
, AT
);
7441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7442 "d,v,t", dreg
, 0, dreg
);
7450 if (imm_expr
.X_op
== O_constant
7451 && imm_expr
.X_add_number
> -0x8000
7452 && imm_expr
.X_add_number
<= 0x8000)
7454 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7455 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7456 dbl
? "daddi" : "addi",
7457 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7460 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7461 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7462 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7468 if (imm_expr
.X_op
== O_constant
7469 && imm_expr
.X_add_number
> -0x8000
7470 && imm_expr
.X_add_number
<= 0x8000)
7472 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7473 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7474 dbl
? "daddiu" : "addiu",
7475 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7478 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7479 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7480 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7501 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7502 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7508 assert (mips_opts
.isa
== ISA_MIPS1
);
7509 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7510 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7513 * Is the double cfc1 instruction a bug in the mips assembler;
7514 * or is there a reason for it?
7516 mips_emit_delays (TRUE
);
7517 ++mips_opts
.noreorder
;
7518 mips_any_noreorder
= 1;
7519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7521 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7523 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7524 expr1
.X_add_number
= 3;
7525 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7526 (int) BFD_RELOC_LO16
);
7527 expr1
.X_add_number
= 2;
7528 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7529 (int) BFD_RELOC_LO16
);
7530 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7532 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7533 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7534 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7537 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7538 --mips_opts
.noreorder
;
7547 if (offset_expr
.X_add_number
>= 0x7fff)
7548 as_bad (_("operand overflow"));
7549 /* avoid load delay */
7550 if (! target_big_endian
)
7551 ++offset_expr
.X_add_number
;
7552 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7553 (int) BFD_RELOC_LO16
, breg
);
7554 if (! target_big_endian
)
7555 --offset_expr
.X_add_number
;
7557 ++offset_expr
.X_add_number
;
7558 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7559 (int) BFD_RELOC_LO16
, breg
);
7560 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7576 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7577 as_bad (_("operand overflow"));
7578 if (! target_big_endian
)
7579 offset_expr
.X_add_number
+= off
;
7580 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7581 (int) BFD_RELOC_LO16
, breg
);
7582 if (! target_big_endian
)
7583 offset_expr
.X_add_number
-= off
;
7585 offset_expr
.X_add_number
+= off
;
7586 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7587 (int) BFD_RELOC_LO16
, breg
);
7601 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7603 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7604 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7605 "d,v,t", AT
, AT
, breg
);
7606 if (! target_big_endian
)
7607 expr1
.X_add_number
= off
;
7609 expr1
.X_add_number
= 0;
7610 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7611 (int) BFD_RELOC_LO16
, AT
);
7612 if (! target_big_endian
)
7613 expr1
.X_add_number
= 0;
7615 expr1
.X_add_number
= off
;
7616 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7617 (int) BFD_RELOC_LO16
, AT
);
7623 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7625 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7626 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7627 "d,v,t", AT
, AT
, breg
);
7628 if (target_big_endian
)
7629 expr1
.X_add_number
= 0;
7630 macro_build ((char *) NULL
, &icnt
, &expr1
,
7631 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7632 (int) BFD_RELOC_LO16
, AT
);
7633 if (target_big_endian
)
7634 expr1
.X_add_number
= 1;
7636 expr1
.X_add_number
= 0;
7637 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7638 (int) BFD_RELOC_LO16
, AT
);
7639 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7641 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7646 if (offset_expr
.X_add_number
>= 0x7fff)
7647 as_bad (_("operand overflow"));
7648 if (target_big_endian
)
7649 ++offset_expr
.X_add_number
;
7650 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7651 (int) BFD_RELOC_LO16
, breg
);
7652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7654 if (target_big_endian
)
7655 --offset_expr
.X_add_number
;
7657 ++offset_expr
.X_add_number
;
7658 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7659 (int) BFD_RELOC_LO16
, breg
);
7672 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7673 as_bad (_("operand overflow"));
7674 if (! target_big_endian
)
7675 offset_expr
.X_add_number
+= off
;
7676 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7677 (int) BFD_RELOC_LO16
, breg
);
7678 if (! target_big_endian
)
7679 offset_expr
.X_add_number
-= off
;
7681 offset_expr
.X_add_number
+= off
;
7682 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7683 (int) BFD_RELOC_LO16
, breg
);
7697 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7700 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7701 "d,v,t", AT
, AT
, breg
);
7702 if (! target_big_endian
)
7703 expr1
.X_add_number
= off
;
7705 expr1
.X_add_number
= 0;
7706 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7707 (int) BFD_RELOC_LO16
, AT
);
7708 if (! target_big_endian
)
7709 expr1
.X_add_number
= 0;
7711 expr1
.X_add_number
= off
;
7712 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7713 (int) BFD_RELOC_LO16
, AT
);
7718 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7720 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7721 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7722 "d,v,t", AT
, AT
, breg
);
7723 if (! target_big_endian
)
7724 expr1
.X_add_number
= 0;
7725 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7726 (int) BFD_RELOC_LO16
, AT
);
7727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7729 if (! target_big_endian
)
7730 expr1
.X_add_number
= 1;
7732 expr1
.X_add_number
= 0;
7733 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7734 (int) BFD_RELOC_LO16
, AT
);
7735 if (! target_big_endian
)
7736 expr1
.X_add_number
= 0;
7738 expr1
.X_add_number
= 1;
7739 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7740 (int) BFD_RELOC_LO16
, AT
);
7741 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7743 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7748 /* FIXME: Check if this is one of the itbl macros, since they
7749 are added dynamically. */
7750 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7754 as_warn (_("Macro used $at after \".set noat\""));
7757 /* Implement macros in mips16 mode. */
7761 struct mips_cl_insn
*ip
;
7764 int xreg
, yreg
, zreg
, tmp
;
7768 const char *s
, *s2
, *s3
;
7770 mask
= ip
->insn_mo
->mask
;
7772 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7773 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7774 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7778 expr1
.X_op
= O_constant
;
7779 expr1
.X_op_symbol
= NULL
;
7780 expr1
.X_add_symbol
= NULL
;
7781 expr1
.X_add_number
= 1;
7800 mips_emit_delays (TRUE
);
7801 ++mips_opts
.noreorder
;
7802 mips_any_noreorder
= 1;
7803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7804 dbl
? "ddiv" : "div",
7805 "0,x,y", xreg
, yreg
);
7806 expr1
.X_add_number
= 2;
7807 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7808 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7811 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7812 since that causes an overflow. We should do that as well,
7813 but I don't see how to do the comparisons without a temporary
7815 --mips_opts
.noreorder
;
7816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7835 mips_emit_delays (TRUE
);
7836 ++mips_opts
.noreorder
;
7837 mips_any_noreorder
= 1;
7838 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7840 expr1
.X_add_number
= 2;
7841 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7842 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7844 --mips_opts
.noreorder
;
7845 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7851 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7852 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7853 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7862 if (imm_expr
.X_op
!= O_constant
)
7863 as_bad (_("Unsupported large constant"));
7864 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7865 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7866 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7870 if (imm_expr
.X_op
!= O_constant
)
7871 as_bad (_("Unsupported large constant"));
7872 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7873 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7878 if (imm_expr
.X_op
!= O_constant
)
7879 as_bad (_("Unsupported large constant"));
7880 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7881 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7904 goto do_reverse_branch
;
7908 goto do_reverse_branch
;
7920 goto do_reverse_branch
;
7931 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7933 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7960 goto do_addone_branch_i
;
7965 goto do_addone_branch_i
;
7980 goto do_addone_branch_i
;
7987 if (imm_expr
.X_op
!= O_constant
)
7988 as_bad (_("Unsupported large constant"));
7989 ++imm_expr
.X_add_number
;
7992 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7993 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7997 expr1
.X_add_number
= 0;
7998 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
8000 move_register (&icnt
, xreg
, yreg
);
8001 expr1
.X_add_number
= 2;
8002 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
8003 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
8004 "neg", "x,w", xreg
, xreg
);
8008 /* For consistency checking, verify that all bits are specified either
8009 by the match/mask part of the instruction definition, or by the
8012 validate_mips_insn (opc
)
8013 const struct mips_opcode
*opc
;
8015 const char *p
= opc
->args
;
8017 unsigned long used_bits
= opc
->mask
;
8019 if ((used_bits
& opc
->match
) != opc
->match
)
8021 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8022 opc
->name
, opc
->args
);
8025 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8035 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8036 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8037 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8038 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8039 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8041 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8042 c
, opc
->name
, opc
->args
);
8046 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8047 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8049 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8050 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8051 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8052 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8054 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8055 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8057 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8058 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8060 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8061 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8062 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8063 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8064 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8065 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8066 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8067 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8068 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8069 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8070 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8071 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8072 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8073 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8074 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8075 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8076 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8078 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8079 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8080 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8081 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8083 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8084 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8085 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8086 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8087 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8088 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8089 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8090 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8091 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8094 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8095 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8096 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8097 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8098 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8102 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8103 c
, opc
->name
, opc
->args
);
8107 if (used_bits
!= 0xffffffff)
8109 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8110 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8116 /* This routine assembles an instruction into its binary format. As a
8117 side effect, it sets one of the global variables imm_reloc or
8118 offset_reloc to the type of relocation to do if one of the operands
8119 is an address expression. */
8124 struct mips_cl_insn
*ip
;
8129 struct mips_opcode
*insn
;
8132 unsigned int lastregno
= 0;
8133 unsigned int lastpos
= 0;
8134 unsigned int limlo
, limhi
;
8140 /* If the instruction contains a '.', we first try to match an instruction
8141 including the '.'. Then we try again without the '.'. */
8143 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8146 /* If we stopped on whitespace, then replace the whitespace with null for
8147 the call to hash_find. Save the character we replaced just in case we
8148 have to re-parse the instruction. */
8155 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8157 /* If we didn't find the instruction in the opcode table, try again, but
8158 this time with just the instruction up to, but not including the
8162 /* Restore the character we overwrite above (if any). */
8166 /* Scan up to the first '.' or whitespace. */
8168 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8172 /* If we did not find a '.', then we can quit now. */
8175 insn_error
= "unrecognized opcode";
8179 /* Lookup the instruction in the hash table. */
8181 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8183 insn_error
= "unrecognized opcode";
8193 assert (strcmp (insn
->name
, str
) == 0);
8195 if (OPCODE_IS_MEMBER (insn
,
8197 | (file_ase_mips16
? INSN_MIPS16
: 0)
8198 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8199 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8205 if (insn
->pinfo
!= INSN_MACRO
)
8207 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8213 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8214 && strcmp (insn
->name
, insn
[1].name
) == 0)
8223 static char buf
[100];
8224 if (mips_arch_info
->is_isa
)
8226 _("opcode not supported at this ISA level (%s)"),
8227 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8230 _("opcode not supported on this processor: %s (%s)"),
8231 mips_arch_info
->name
,
8232 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8242 ip
->insn_opcode
= insn
->match
;
8244 for (args
= insn
->args
;; ++args
)
8248 s
+= strspn (s
, " \t");
8252 case '\0': /* end of args */
8265 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8269 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8273 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8277 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8283 /* Handle optional base register.
8284 Either the base register is omitted or
8285 we must have a left paren. */
8286 /* This is dependent on the next operand specifier
8287 is a base register specification. */
8288 assert (args
[1] == 'b' || args
[1] == '5'
8289 || args
[1] == '-' || args
[1] == '4');
8293 case ')': /* these must match exactly */
8300 case '+': /* Opcode extension character. */
8303 case 'A': /* ins/ext position, becomes LSB. */
8306 my_getExpression (&imm_expr
, s
);
8307 check_absolute_expr (ip
, &imm_expr
);
8308 if ((unsigned long) imm_expr
.X_add_number
< limlo
8309 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8311 as_bad (_("Improper position (%lu)"),
8312 (unsigned long) imm_expr
.X_add_number
);
8313 imm_expr
.X_add_number
= limlo
;
8315 lastpos
= imm_expr
.X_add_number
;
8316 ip
->insn_opcode
|= (imm_expr
.X_add_number
8317 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8318 imm_expr
.X_op
= O_absent
;
8322 case 'B': /* ins size, becomes MSB. */
8325 my_getExpression (&imm_expr
, s
);
8326 check_absolute_expr (ip
, &imm_expr
);
8327 /* Check for negative input so that small negative numbers
8328 will not succeed incorrectly. The checks against
8329 (pos+size) transitively check "size" itself,
8330 assuming that "pos" is reasonable. */
8331 if ((long) imm_expr
.X_add_number
< 0
8332 || ((unsigned long) imm_expr
.X_add_number
8334 || ((unsigned long) imm_expr
.X_add_number
8337 as_bad (_("Improper insert size (%lu, position %lu)"),
8338 (unsigned long) imm_expr
.X_add_number
,
8339 (unsigned long) lastpos
);
8340 imm_expr
.X_add_number
= limlo
- lastpos
;
8342 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8343 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8344 imm_expr
.X_op
= O_absent
;
8348 case 'C': /* ext size, becomes MSBD. */
8351 my_getExpression (&imm_expr
, s
);
8352 check_absolute_expr (ip
, &imm_expr
);
8353 /* Check for negative input so that small negative numbers
8354 will not succeed incorrectly. The checks against
8355 (pos+size) transitively check "size" itself,
8356 assuming that "pos" is reasonable. */
8357 if ((long) imm_expr
.X_add_number
< 0
8358 || ((unsigned long) imm_expr
.X_add_number
8360 || ((unsigned long) imm_expr
.X_add_number
8363 as_bad (_("Improper extract size (%lu, position %lu)"),
8364 (unsigned long) imm_expr
.X_add_number
,
8365 (unsigned long) lastpos
);
8366 imm_expr
.X_add_number
= limlo
- lastpos
;
8368 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8369 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8370 imm_expr
.X_op
= O_absent
;
8375 /* +D is for disassembly only; never match. */
8379 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8380 *args
, insn
->name
, insn
->args
);
8381 /* Further processing is fruitless. */
8386 case '<': /* must be at least one digit */
8388 * According to the manual, if the shift amount is greater
8389 * than 31 or less than 0, then the shift amount should be
8390 * mod 32. In reality the mips assembler issues an error.
8391 * We issue a warning and mask out all but the low 5 bits.
8393 my_getExpression (&imm_expr
, s
);
8394 check_absolute_expr (ip
, &imm_expr
);
8395 if ((unsigned long) imm_expr
.X_add_number
> 31)
8397 as_warn (_("Improper shift amount (%lu)"),
8398 (unsigned long) imm_expr
.X_add_number
);
8399 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8401 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8402 imm_expr
.X_op
= O_absent
;
8406 case '>': /* shift amount minus 32 */
8407 my_getExpression (&imm_expr
, s
);
8408 check_absolute_expr (ip
, &imm_expr
);
8409 if ((unsigned long) imm_expr
.X_add_number
< 32
8410 || (unsigned long) imm_expr
.X_add_number
> 63)
8412 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8413 imm_expr
.X_op
= O_absent
;
8417 case 'k': /* cache code */
8418 case 'h': /* prefx code */
8419 my_getExpression (&imm_expr
, s
);
8420 check_absolute_expr (ip
, &imm_expr
);
8421 if ((unsigned long) imm_expr
.X_add_number
> 31)
8423 as_warn (_("Invalid value for `%s' (%lu)"),
8425 (unsigned long) imm_expr
.X_add_number
);
8426 imm_expr
.X_add_number
&= 0x1f;
8429 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8431 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8432 imm_expr
.X_op
= O_absent
;
8436 case 'c': /* break code */
8437 my_getExpression (&imm_expr
, s
);
8438 check_absolute_expr (ip
, &imm_expr
);
8439 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8441 as_warn (_("Illegal break code (%lu)"),
8442 (unsigned long) imm_expr
.X_add_number
);
8443 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8445 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8446 imm_expr
.X_op
= O_absent
;
8450 case 'q': /* lower break code */
8451 my_getExpression (&imm_expr
, s
);
8452 check_absolute_expr (ip
, &imm_expr
);
8453 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8455 as_warn (_("Illegal lower break code (%lu)"),
8456 (unsigned long) imm_expr
.X_add_number
);
8457 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8459 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8460 imm_expr
.X_op
= O_absent
;
8464 case 'B': /* 20-bit syscall/break code. */
8465 my_getExpression (&imm_expr
, s
);
8466 check_absolute_expr (ip
, &imm_expr
);
8467 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8468 as_warn (_("Illegal 20-bit code (%lu)"),
8469 (unsigned long) imm_expr
.X_add_number
);
8470 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8471 imm_expr
.X_op
= O_absent
;
8475 case 'C': /* Coprocessor code */
8476 my_getExpression (&imm_expr
, s
);
8477 check_absolute_expr (ip
, &imm_expr
);
8478 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8480 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8481 (unsigned long) imm_expr
.X_add_number
);
8482 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8484 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8485 imm_expr
.X_op
= O_absent
;
8489 case 'J': /* 19-bit wait code. */
8490 my_getExpression (&imm_expr
, s
);
8491 check_absolute_expr (ip
, &imm_expr
);
8492 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8493 as_warn (_("Illegal 19-bit code (%lu)"),
8494 (unsigned long) imm_expr
.X_add_number
);
8495 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8496 imm_expr
.X_op
= O_absent
;
8500 case 'P': /* Performance register */
8501 my_getExpression (&imm_expr
, s
);
8502 check_absolute_expr (ip
, &imm_expr
);
8503 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8505 as_warn (_("Invalid performance register (%lu)"),
8506 (unsigned long) imm_expr
.X_add_number
);
8507 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8509 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8510 imm_expr
.X_op
= O_absent
;
8514 case 'b': /* base register */
8515 case 'd': /* destination register */
8516 case 's': /* source register */
8517 case 't': /* target register */
8518 case 'r': /* both target and source */
8519 case 'v': /* both dest and source */
8520 case 'w': /* both dest and target */
8521 case 'E': /* coprocessor target register */
8522 case 'G': /* coprocessor destination register */
8523 case 'K': /* 'rdhwr' destination register */
8524 case 'x': /* ignore register name */
8525 case 'z': /* must be zero register */
8526 case 'U': /* destination register (clo/clz). */
8541 while (ISDIGIT (*s
));
8543 as_bad (_("Invalid register number (%d)"), regno
);
8545 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8549 if (s
[1] == 'r' && s
[2] == 'a')
8554 else if (s
[1] == 'f' && s
[2] == 'p')
8559 else if (s
[1] == 's' && s
[2] == 'p')
8564 else if (s
[1] == 'g' && s
[2] == 'p')
8569 else if (s
[1] == 'a' && s
[2] == 't')
8574 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8579 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8584 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8589 else if (itbl_have_entries
)
8594 p
= s
+ 1; /* advance past '$' */
8595 n
= itbl_get_field (&p
); /* n is name */
8597 /* See if this is a register defined in an
8599 if (itbl_get_reg_val (n
, &r
))
8601 /* Get_field advances to the start of
8602 the next field, so we need to back
8603 rack to the end of the last field. */
8607 s
= strchr (s
, '\0');
8621 as_warn (_("Used $at without \".set noat\""));
8627 if (c
== 'r' || c
== 'v' || c
== 'w')
8634 /* 'z' only matches $0. */
8635 if (c
== 'z' && regno
!= 0)
8638 /* Now that we have assembled one operand, we use the args string
8639 * to figure out where it goes in the instruction. */
8646 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8651 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8654 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8655 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8660 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8663 /* This case exists because on the r3000 trunc
8664 expands into a macro which requires a gp
8665 register. On the r6000 or r4000 it is
8666 assembled into a single instruction which
8667 ignores the register. Thus the insn version
8668 is MIPS_ISA2 and uses 'x', and the macro
8669 version is MIPS_ISA1 and uses 't'. */
8672 /* This case is for the div instruction, which
8673 acts differently if the destination argument
8674 is $0. This only matches $0, and is checked
8675 outside the switch. */
8678 /* Itbl operand; not yet implemented. FIXME ?? */
8680 /* What about all other operands like 'i', which
8681 can be specified in the opcode table? */
8691 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8694 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8699 case 'O': /* MDMX alignment immediate constant. */
8700 my_getExpression (&imm_expr
, s
);
8701 check_absolute_expr (ip
, &imm_expr
);
8702 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8704 as_warn ("Improper align amount (%ld), using low bits",
8705 (long) imm_expr
.X_add_number
);
8706 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8708 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8709 imm_expr
.X_op
= O_absent
;
8713 case 'Q': /* MDMX vector, element sel, or const. */
8716 /* MDMX Immediate. */
8717 my_getExpression (&imm_expr
, s
);
8718 check_absolute_expr (ip
, &imm_expr
);
8719 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8721 as_warn (_("Invalid MDMX Immediate (%ld)"),
8722 (long) imm_expr
.X_add_number
);
8723 imm_expr
.X_add_number
&= OP_MASK_FT
;
8725 imm_expr
.X_add_number
&= OP_MASK_FT
;
8726 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8727 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8729 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8730 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8731 imm_expr
.X_op
= O_absent
;
8735 /* Not MDMX Immediate. Fall through. */
8736 case 'X': /* MDMX destination register. */
8737 case 'Y': /* MDMX source register. */
8738 case 'Z': /* MDMX target register. */
8740 case 'D': /* floating point destination register */
8741 case 'S': /* floating point source register */
8742 case 'T': /* floating point target register */
8743 case 'R': /* floating point source register */
8747 /* Accept $fN for FP and MDMX register numbers, and in
8748 addition accept $vN for MDMX register numbers. */
8749 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8750 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8761 while (ISDIGIT (*s
));
8764 as_bad (_("Invalid float register number (%d)"), regno
);
8766 if ((regno
& 1) != 0
8768 && ! (strcmp (str
, "mtc1") == 0
8769 || strcmp (str
, "mfc1") == 0
8770 || strcmp (str
, "lwc1") == 0
8771 || strcmp (str
, "swc1") == 0
8772 || strcmp (str
, "l.s") == 0
8773 || strcmp (str
, "s.s") == 0))
8774 as_warn (_("Float register should be even, was %d"),
8782 if (c
== 'V' || c
== 'W')
8793 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8798 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8801 /* This is like 'Z', but also needs to fix the MDMX
8802 vector/scalar select bits. Note that the
8803 scalar immediate case is handled above. */
8806 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8807 int max_el
= (is_qh
? 3 : 7);
8809 my_getExpression(&imm_expr
, s
);
8810 check_absolute_expr (ip
, &imm_expr
);
8812 if (imm_expr
.X_add_number
> max_el
)
8813 as_bad(_("Bad element selector %ld"),
8814 (long) imm_expr
.X_add_number
);
8815 imm_expr
.X_add_number
&= max_el
;
8816 ip
->insn_opcode
|= (imm_expr
.X_add_number
8820 as_warn(_("Expecting ']' found '%s'"), s
);
8826 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8827 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8830 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8837 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8840 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8850 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8853 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8859 my_getExpression (&imm_expr
, s
);
8860 if (imm_expr
.X_op
!= O_big
8861 && imm_expr
.X_op
!= O_constant
)
8862 insn_error
= _("absolute expression required");
8867 my_getExpression (&offset_expr
, s
);
8868 *imm_reloc
= BFD_RELOC_32
;
8881 unsigned char temp
[8];
8883 unsigned int length
;
8888 /* These only appear as the last operand in an
8889 instruction, and every instruction that accepts
8890 them in any variant accepts them in all variants.
8891 This means we don't have to worry about backing out
8892 any changes if the instruction does not match.
8894 The difference between them is the size of the
8895 floating point constant and where it goes. For 'F'
8896 and 'L' the constant is 64 bits; for 'f' and 'l' it
8897 is 32 bits. Where the constant is placed is based
8898 on how the MIPS assembler does things:
8901 f -- immediate value
8904 The .lit4 and .lit8 sections are only used if
8905 permitted by the -G argument.
8907 When generating embedded PIC code, we use the
8908 .lit8 section but not the .lit4 section (we can do
8909 .lit4 inline easily; we need to put .lit8
8910 somewhere in the data segment, and using .lit8
8911 permits the linker to eventually combine identical
8914 The code below needs to know whether the target register
8915 is 32 or 64 bits wide. It relies on the fact 'f' and
8916 'F' are used with GPR-based instructions and 'l' and
8917 'L' are used with FPR-based instructions. */
8919 f64
= *args
== 'F' || *args
== 'L';
8920 using_gprs
= *args
== 'F' || *args
== 'f';
8922 save_in
= input_line_pointer
;
8923 input_line_pointer
= s
;
8924 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8926 s
= input_line_pointer
;
8927 input_line_pointer
= save_in
;
8928 if (err
!= NULL
&& *err
!= '\0')
8930 as_bad (_("Bad floating point constant: %s"), err
);
8931 memset (temp
, '\0', sizeof temp
);
8932 length
= f64
? 8 : 4;
8935 assert (length
== (unsigned) (f64
? 8 : 4));
8939 && (! USE_GLOBAL_POINTER_OPT
8940 || mips_pic
== EMBEDDED_PIC
8941 || g_switch_value
< 4
8942 || (temp
[0] == 0 && temp
[1] == 0)
8943 || (temp
[2] == 0 && temp
[3] == 0))))
8945 imm_expr
.X_op
= O_constant
;
8946 if (! target_big_endian
)
8947 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8949 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8952 && ! mips_disable_float_construction
8953 /* Constants can only be constructed in GPRs and
8954 copied to FPRs if the GPRs are at least as wide
8955 as the FPRs. Force the constant into memory if
8956 we are using 64-bit FPRs but the GPRs are only
8959 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8960 && ((temp
[0] == 0 && temp
[1] == 0)
8961 || (temp
[2] == 0 && temp
[3] == 0))
8962 && ((temp
[4] == 0 && temp
[5] == 0)
8963 || (temp
[6] == 0 && temp
[7] == 0)))
8965 /* The value is simple enough to load with a couple of
8966 instructions. If using 32-bit registers, set
8967 imm_expr to the high order 32 bits and offset_expr to
8968 the low order 32 bits. Otherwise, set imm_expr to
8969 the entire 64 bit constant. */
8970 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8972 imm_expr
.X_op
= O_constant
;
8973 offset_expr
.X_op
= O_constant
;
8974 if (! target_big_endian
)
8976 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8977 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8981 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8982 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8984 if (offset_expr
.X_add_number
== 0)
8985 offset_expr
.X_op
= O_absent
;
8987 else if (sizeof (imm_expr
.X_add_number
) > 4)
8989 imm_expr
.X_op
= O_constant
;
8990 if (! target_big_endian
)
8991 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8993 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8997 imm_expr
.X_op
= O_big
;
8998 imm_expr
.X_add_number
= 4;
8999 if (! target_big_endian
)
9001 generic_bignum
[0] = bfd_getl16 (temp
);
9002 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9003 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9004 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9008 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9009 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9010 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9011 generic_bignum
[3] = bfd_getb16 (temp
);
9017 const char *newname
;
9020 /* Switch to the right section. */
9022 subseg
= now_subseg
;
9025 default: /* unused default case avoids warnings. */
9027 newname
= RDATA_SECTION_NAME
;
9028 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
9029 || mips_pic
== EMBEDDED_PIC
)
9033 if (mips_pic
== EMBEDDED_PIC
)
9036 newname
= RDATA_SECTION_NAME
;
9039 assert (!USE_GLOBAL_POINTER_OPT
9040 || g_switch_value
>= 4);
9044 new_seg
= subseg_new (newname
, (subsegT
) 0);
9045 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9046 bfd_set_section_flags (stdoutput
, new_seg
,
9051 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9052 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9053 && strcmp (TARGET_OS
, "elf") != 0)
9054 record_alignment (new_seg
, 4);
9056 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9058 as_bad (_("Can't use floating point insn in this section"));
9060 /* Set the argument to the current address in the
9062 offset_expr
.X_op
= O_symbol
;
9063 offset_expr
.X_add_symbol
=
9064 symbol_new ("L0\001", now_seg
,
9065 (valueT
) frag_now_fix (), frag_now
);
9066 offset_expr
.X_add_number
= 0;
9068 /* Put the floating point number into the section. */
9069 p
= frag_more ((int) length
);
9070 memcpy (p
, temp
, length
);
9072 /* Switch back to the original section. */
9073 subseg_set (seg
, subseg
);
9078 case 'i': /* 16 bit unsigned immediate */
9079 case 'j': /* 16 bit signed immediate */
9080 *imm_reloc
= BFD_RELOC_LO16
;
9081 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9084 offsetT minval
, maxval
;
9086 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9087 && strcmp (insn
->name
, insn
[1].name
) == 0);
9089 /* If the expression was written as an unsigned number,
9090 only treat it as signed if there are no more
9094 && sizeof (imm_expr
.X_add_number
) <= 4
9095 && imm_expr
.X_op
== O_constant
9096 && imm_expr
.X_add_number
< 0
9097 && imm_expr
.X_unsigned
9101 /* For compatibility with older assemblers, we accept
9102 0x8000-0xffff as signed 16-bit numbers when only
9103 signed numbers are allowed. */
9105 minval
= 0, maxval
= 0xffff;
9107 minval
= -0x8000, maxval
= 0x7fff;
9109 minval
= -0x8000, maxval
= 0xffff;
9111 if (imm_expr
.X_op
!= O_constant
9112 || imm_expr
.X_add_number
< minval
9113 || imm_expr
.X_add_number
> maxval
)
9117 if (imm_expr
.X_op
== O_constant
9118 || imm_expr
.X_op
== O_big
)
9119 as_bad (_("expression out of range"));
9125 case 'o': /* 16 bit offset */
9126 /* Check whether there is only a single bracketed expression
9127 left. If so, it must be the base register and the
9128 constant must be zero. */
9129 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9131 offset_expr
.X_op
= O_constant
;
9132 offset_expr
.X_add_number
= 0;
9136 /* If this value won't fit into a 16 bit offset, then go
9137 find a macro that will generate the 32 bit offset
9139 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9140 && (offset_expr
.X_op
!= O_constant
9141 || offset_expr
.X_add_number
>= 0x8000
9142 || offset_expr
.X_add_number
< -0x8000))
9148 case 'p': /* pc relative offset */
9149 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9150 my_getExpression (&offset_expr
, s
);
9154 case 'u': /* upper 16 bits */
9155 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9156 && imm_expr
.X_op
== O_constant
9157 && (imm_expr
.X_add_number
< 0
9158 || imm_expr
.X_add_number
>= 0x10000))
9159 as_bad (_("lui expression not in range 0..65535"));
9163 case 'a': /* 26 bit address */
9164 my_getExpression (&offset_expr
, s
);
9166 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9169 case 'N': /* 3 bit branch condition code */
9170 case 'M': /* 3 bit compare condition code */
9171 if (strncmp (s
, "$fcc", 4) != 0)
9181 while (ISDIGIT (*s
));
9183 as_bad (_("invalid condition code register $fcc%d"), regno
);
9185 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9187 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9191 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9202 while (ISDIGIT (*s
));
9205 c
= 8; /* Invalid sel value. */
9208 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9209 ip
->insn_opcode
|= c
;
9213 /* Must be at least one digit. */
9214 my_getExpression (&imm_expr
, s
);
9215 check_absolute_expr (ip
, &imm_expr
);
9217 if ((unsigned long) imm_expr
.X_add_number
9218 > (unsigned long) OP_MASK_VECBYTE
)
9220 as_bad (_("bad byte vector index (%ld)"),
9221 (long) imm_expr
.X_add_number
);
9222 imm_expr
.X_add_number
= 0;
9225 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9226 imm_expr
.X_op
= O_absent
;
9231 my_getExpression (&imm_expr
, s
);
9232 check_absolute_expr (ip
, &imm_expr
);
9234 if ((unsigned long) imm_expr
.X_add_number
9235 > (unsigned long) OP_MASK_VECALIGN
)
9237 as_bad (_("bad byte vector index (%ld)"),
9238 (long) imm_expr
.X_add_number
);
9239 imm_expr
.X_add_number
= 0;
9242 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9243 imm_expr
.X_op
= O_absent
;
9248 as_bad (_("bad char = '%c'\n"), *args
);
9253 /* Args don't match. */
9254 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9255 !strcmp (insn
->name
, insn
[1].name
))
9259 insn_error
= _("illegal operands");
9264 insn_error
= _("illegal operands");
9269 /* This routine assembles an instruction into its binary format when
9270 assembling for the mips16. As a side effect, it sets one of the
9271 global variables imm_reloc or offset_reloc to the type of
9272 relocation to do if one of the operands is an address expression.
9273 It also sets mips16_small and mips16_ext if the user explicitly
9274 requested a small or extended instruction. */
9279 struct mips_cl_insn
*ip
;
9283 struct mips_opcode
*insn
;
9286 unsigned int lastregno
= 0;
9291 mips16_small
= FALSE
;
9294 for (s
= str
; ISLOWER (*s
); ++s
)
9306 if (s
[1] == 't' && s
[2] == ' ')
9309 mips16_small
= TRUE
;
9313 else if (s
[1] == 'e' && s
[2] == ' ')
9322 insn_error
= _("unknown opcode");
9326 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9327 mips16_small
= TRUE
;
9329 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9331 insn_error
= _("unrecognized opcode");
9338 assert (strcmp (insn
->name
, str
) == 0);
9341 ip
->insn_opcode
= insn
->match
;
9342 ip
->use_extend
= FALSE
;
9343 imm_expr
.X_op
= O_absent
;
9344 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9345 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9346 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9347 offset_expr
.X_op
= O_absent
;
9348 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9349 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9350 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9351 for (args
= insn
->args
; 1; ++args
)
9358 /* In this switch statement we call break if we did not find
9359 a match, continue if we did find a match, or return if we
9368 /* Stuff the immediate value in now, if we can. */
9369 if (imm_expr
.X_op
== O_constant
9370 && *imm_reloc
> BFD_RELOC_UNUSED
9371 && insn
->pinfo
!= INSN_MACRO
)
9373 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9374 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9375 mips16_ext
, &ip
->insn_opcode
,
9376 &ip
->use_extend
, &ip
->extend
);
9377 imm_expr
.X_op
= O_absent
;
9378 *imm_reloc
= BFD_RELOC_UNUSED
;
9392 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9395 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9411 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9413 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9440 while (ISDIGIT (*s
));
9443 as_bad (_("invalid register number (%d)"), regno
);
9449 if (s
[1] == 'r' && s
[2] == 'a')
9454 else if (s
[1] == 'f' && s
[2] == 'p')
9459 else if (s
[1] == 's' && s
[2] == 'p')
9464 else if (s
[1] == 'g' && s
[2] == 'p')
9469 else if (s
[1] == 'a' && s
[2] == 't')
9474 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9479 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9484 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9497 if (c
== 'v' || c
== 'w')
9499 regno
= mips16_to_32_reg_map
[lastregno
];
9513 regno
= mips32_to_16_reg_map
[regno
];
9518 regno
= ILLEGAL_REG
;
9523 regno
= ILLEGAL_REG
;
9528 regno
= ILLEGAL_REG
;
9533 if (regno
== AT
&& ! mips_opts
.noat
)
9534 as_warn (_("used $at without \".set noat\""));
9541 if (regno
== ILLEGAL_REG
)
9548 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9552 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9555 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9558 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9564 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9567 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9568 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9578 if (strncmp (s
, "$pc", 3) == 0)
9602 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9604 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9605 and generate the appropriate reloc. If the text
9606 inside %gprel is not a symbol name with an
9607 optional offset, then we generate a normal reloc
9608 and will probably fail later. */
9609 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9610 if (imm_expr
.X_op
== O_symbol
)
9613 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9615 ip
->use_extend
= TRUE
;
9622 /* Just pick up a normal expression. */
9623 my_getExpression (&imm_expr
, s
);
9626 if (imm_expr
.X_op
== O_register
)
9628 /* What we thought was an expression turned out to
9631 if (s
[0] == '(' && args
[1] == '(')
9633 /* It looks like the expression was omitted
9634 before a register indirection, which means
9635 that the expression is implicitly zero. We
9636 still set up imm_expr, so that we handle
9637 explicit extensions correctly. */
9638 imm_expr
.X_op
= O_constant
;
9639 imm_expr
.X_add_number
= 0;
9640 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9647 /* We need to relax this instruction. */
9648 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9657 /* We use offset_reloc rather than imm_reloc for the PC
9658 relative operands. This lets macros with both
9659 immediate and address operands work correctly. */
9660 my_getExpression (&offset_expr
, s
);
9662 if (offset_expr
.X_op
== O_register
)
9665 /* We need to relax this instruction. */
9666 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9670 case '6': /* break code */
9671 my_getExpression (&imm_expr
, s
);
9672 check_absolute_expr (ip
, &imm_expr
);
9673 if ((unsigned long) imm_expr
.X_add_number
> 63)
9675 as_warn (_("Invalid value for `%s' (%lu)"),
9677 (unsigned long) imm_expr
.X_add_number
);
9678 imm_expr
.X_add_number
&= 0x3f;
9680 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9681 imm_expr
.X_op
= O_absent
;
9685 case 'a': /* 26 bit address */
9686 my_getExpression (&offset_expr
, s
);
9688 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9689 ip
->insn_opcode
<<= 16;
9692 case 'l': /* register list for entry macro */
9693 case 'L': /* register list for exit macro */
9703 int freg
, reg1
, reg2
;
9705 while (*s
== ' ' || *s
== ',')
9709 as_bad (_("can't parse register list"));
9721 while (ISDIGIT (*s
))
9743 as_bad (_("invalid register list"));
9748 while (ISDIGIT (*s
))
9755 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9760 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9765 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9766 mask
|= (reg2
- 3) << 3;
9767 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9768 mask
|= (reg2
- 15) << 1;
9769 else if (reg1
== RA
&& reg2
== RA
)
9773 as_bad (_("invalid register list"));
9777 /* The mask is filled in in the opcode table for the
9778 benefit of the disassembler. We remove it before
9779 applying the actual mask. */
9780 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9781 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9785 case 'e': /* extend code */
9786 my_getExpression (&imm_expr
, s
);
9787 check_absolute_expr (ip
, &imm_expr
);
9788 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9790 as_warn (_("Invalid value for `%s' (%lu)"),
9792 (unsigned long) imm_expr
.X_add_number
);
9793 imm_expr
.X_add_number
&= 0x7ff;
9795 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9796 imm_expr
.X_op
= O_absent
;
9806 /* Args don't match. */
9807 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9808 strcmp (insn
->name
, insn
[1].name
) == 0)
9815 insn_error
= _("illegal operands");
9821 /* This structure holds information we know about a mips16 immediate
9824 struct mips16_immed_operand
9826 /* The type code used in the argument string in the opcode table. */
9828 /* The number of bits in the short form of the opcode. */
9830 /* The number of bits in the extended form of the opcode. */
9832 /* The amount by which the short form is shifted when it is used;
9833 for example, the sw instruction has a shift count of 2. */
9835 /* The amount by which the short form is shifted when it is stored
9836 into the instruction code. */
9838 /* Non-zero if the short form is unsigned. */
9840 /* Non-zero if the extended form is unsigned. */
9842 /* Non-zero if the value is PC relative. */
9846 /* The mips16 immediate operand types. */
9848 static const struct mips16_immed_operand mips16_immed_operands
[] =
9850 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9851 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9852 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9853 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9854 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9855 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9856 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9857 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9858 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9859 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9860 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9861 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9862 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9863 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9864 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9865 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9866 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9867 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9868 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9869 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9870 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9873 #define MIPS16_NUM_IMMED \
9874 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9876 /* Handle a mips16 instruction with an immediate value. This or's the
9877 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9878 whether an extended value is needed; if one is needed, it sets
9879 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9880 If SMALL is true, an unextended opcode was explicitly requested.
9881 If EXT is true, an extended opcode was explicitly requested. If
9882 WARN is true, warn if EXT does not match reality. */
9885 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9894 unsigned long *insn
;
9895 bfd_boolean
*use_extend
;
9896 unsigned short *extend
;
9898 register const struct mips16_immed_operand
*op
;
9899 int mintiny
, maxtiny
;
9900 bfd_boolean needext
;
9902 op
= mips16_immed_operands
;
9903 while (op
->type
!= type
)
9906 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9911 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9914 maxtiny
= 1 << op
->nbits
;
9919 maxtiny
= (1 << op
->nbits
) - 1;
9924 mintiny
= - (1 << (op
->nbits
- 1));
9925 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9928 /* Branch offsets have an implicit 0 in the lowest bit. */
9929 if (type
== 'p' || type
== 'q')
9932 if ((val
& ((1 << op
->shift
) - 1)) != 0
9933 || val
< (mintiny
<< op
->shift
)
9934 || val
> (maxtiny
<< op
->shift
))
9939 if (warn
&& ext
&& ! needext
)
9940 as_warn_where (file
, line
,
9941 _("extended operand requested but not required"));
9942 if (small
&& needext
)
9943 as_bad_where (file
, line
, _("invalid unextended operand value"));
9945 if (small
|| (! ext
&& ! needext
))
9949 *use_extend
= FALSE
;
9950 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9951 insnval
<<= op
->op_shift
;
9956 long minext
, maxext
;
9962 maxext
= (1 << op
->extbits
) - 1;
9966 minext
= - (1 << (op
->extbits
- 1));
9967 maxext
= (1 << (op
->extbits
- 1)) - 1;
9969 if (val
< minext
|| val
> maxext
)
9970 as_bad_where (file
, line
,
9971 _("operand value out of range for instruction"));
9974 if (op
->extbits
== 16)
9976 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9979 else if (op
->extbits
== 15)
9981 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9986 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9990 *extend
= (unsigned short) extval
;
9995 static const struct percent_op_match
9998 bfd_reloc_code_real_type reloc
;
10001 {"%lo", BFD_RELOC_LO16
},
10003 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10004 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10005 {"%call16", BFD_RELOC_MIPS_CALL16
},
10006 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10007 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10008 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10009 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10010 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10011 {"%got", BFD_RELOC_MIPS_GOT16
},
10012 {"%gp_rel", BFD_RELOC_GPREL16
},
10013 {"%half", BFD_RELOC_16
},
10014 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10015 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10016 {"%neg", BFD_RELOC_MIPS_SUB
},
10018 {"%hi", BFD_RELOC_HI16_S
}
10022 /* Return true if *STR points to a relocation operator. When returning true,
10023 move *STR over the operator and store its relocation code in *RELOC.
10024 Leave both *STR and *RELOC alone when returning false. */
10027 parse_relocation (str
, reloc
)
10029 bfd_reloc_code_real_type
*reloc
;
10033 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
10034 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10036 *str
+= strlen (percent_op
[i
].str
);
10037 *reloc
= percent_op
[i
].reloc
;
10039 /* Check whether the output BFD supports this relocation.
10040 If not, issue an error and fall back on something safe. */
10041 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10043 as_bad ("relocation %s isn't supported by the current ABI",
10044 percent_op
[i
].str
);
10045 *reloc
= BFD_RELOC_LO16
;
10053 /* Parse string STR as a 16-bit relocatable operand. Store the
10054 expression in *EP and the relocations in the array starting
10055 at RELOC. Return the number of relocation operators used.
10057 On exit, EXPR_END points to the first character after the expression.
10058 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10061 my_getSmallExpression (ep
, reloc
, str
)
10063 bfd_reloc_code_real_type
*reloc
;
10066 bfd_reloc_code_real_type reversed_reloc
[3];
10067 size_t reloc_index
, i
;
10068 int crux_depth
, str_depth
;
10071 /* Search for the start of the main expression, recoding relocations
10072 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10073 of the main expression and with CRUX_DEPTH containing the number
10074 of open brackets at that point. */
10081 crux_depth
= str_depth
;
10083 /* Skip over whitespace and brackets, keeping count of the number
10085 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10090 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10091 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10093 my_getExpression (ep
, crux
);
10096 /* Match every open bracket. */
10097 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10101 if (crux_depth
> 0)
10102 as_bad ("unclosed '('");
10106 reloc
[0] = BFD_RELOC_LO16
;
10107 for (i
= 0; i
< reloc_index
; i
++)
10108 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10110 return reloc_index
;
10114 my_getExpression (ep
, str
)
10121 save_in
= input_line_pointer
;
10122 input_line_pointer
= str
;
10124 expr_end
= input_line_pointer
;
10125 input_line_pointer
= save_in
;
10127 /* If we are in mips16 mode, and this is an expression based on `.',
10128 then we bump the value of the symbol by 1 since that is how other
10129 text symbols are handled. We don't bother to handle complex
10130 expressions, just `.' plus or minus a constant. */
10131 if (mips_opts
.mips16
10132 && ep
->X_op
== O_symbol
10133 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10134 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10135 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10136 && symbol_constant_p (ep
->X_add_symbol
)
10137 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10138 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10141 /* Turn a string in input_line_pointer into a floating point constant
10142 of type TYPE, and store the appropriate bytes in *LITP. The number
10143 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10144 returned, or NULL on OK. */
10147 md_atof (type
, litP
, sizeP
)
10153 LITTLENUM_TYPE words
[4];
10169 return _("bad call to md_atof");
10172 t
= atof_ieee (input_line_pointer
, type
, words
);
10174 input_line_pointer
= t
;
10178 if (! target_big_endian
)
10180 for (i
= prec
- 1; i
>= 0; i
--)
10182 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10188 for (i
= 0; i
< prec
; i
++)
10190 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10199 md_number_to_chars (buf
, val
, n
)
10204 if (target_big_endian
)
10205 number_to_chars_bigendian (buf
, val
, n
);
10207 number_to_chars_littleendian (buf
, val
, n
);
10211 static int support_64bit_objects(void)
10213 const char **list
, **l
;
10216 list
= bfd_target_list ();
10217 for (l
= list
; *l
!= NULL
; l
++)
10219 /* This is traditional mips */
10220 if (strcmp (*l
, "elf64-tradbigmips") == 0
10221 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10223 if (strcmp (*l
, "elf64-bigmips") == 0
10224 || strcmp (*l
, "elf64-littlemips") == 0)
10227 yes
= (*l
!= NULL
);
10231 #endif /* OBJ_ELF */
10233 const char *md_shortopts
= "nO::g::G:";
10235 struct option md_longopts
[] =
10237 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10238 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10239 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10240 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10241 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10242 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10243 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10244 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10245 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10246 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10247 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10248 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10249 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10250 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10251 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10252 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10253 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10254 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10255 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10256 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10257 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10258 {"break", no_argument
, NULL
, OPTION_BREAK
},
10259 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10260 #define OPTION_EB (OPTION_MD_BASE + 11)
10261 {"EB", no_argument
, NULL
, OPTION_EB
},
10262 #define OPTION_EL (OPTION_MD_BASE + 12)
10263 {"EL", no_argument
, NULL
, OPTION_EL
},
10264 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10265 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10266 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10267 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10268 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10269 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10270 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10271 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10272 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10273 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10274 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10275 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10276 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10277 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10278 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10279 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10280 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10281 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10282 {"march", required_argument
, NULL
, OPTION_MARCH
},
10283 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10284 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10285 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10286 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10287 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10288 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10289 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10290 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10291 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10292 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10293 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10294 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10295 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10296 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10297 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10298 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10299 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10300 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10301 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10302 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10303 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10304 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10305 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10306 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10307 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10308 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10309 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10310 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10311 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10312 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10313 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10314 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10315 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10316 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10317 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10318 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10319 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10320 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10321 #define OPTION_MIPS32R2 (OPTION_MD_BASE + 41)
10322 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10324 #define OPTION_ELF_BASE (OPTION_MD_BASE + 42)
10325 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10326 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10327 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10328 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10329 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10330 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10331 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10332 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10333 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10334 #define OPTION_32 (OPTION_ELF_BASE + 4)
10335 {"32", no_argument
, NULL
, OPTION_32
},
10336 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10337 {"n32", no_argument
, NULL
, OPTION_N32
},
10338 #define OPTION_64 (OPTION_ELF_BASE + 6)
10339 {"64", no_argument
, NULL
, OPTION_64
},
10340 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10341 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10342 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10343 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10344 #endif /* OBJ_ELF */
10345 {NULL
, no_argument
, NULL
, 0}
10347 size_t md_longopts_size
= sizeof (md_longopts
);
10349 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10350 NEW_VALUE. Warn if another value was already specified. Note:
10351 we have to defer parsing the -march and -mtune arguments in order
10352 to handle 'from-abi' correctly, since the ABI might be specified
10353 in a later argument. */
10356 mips_set_option_string (string_ptr
, new_value
)
10357 const char **string_ptr
, *new_value
;
10359 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10360 as_warn (_("A different %s was already specified, is now %s"),
10361 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10364 *string_ptr
= new_value
;
10368 md_parse_option (c
, arg
)
10374 case OPTION_CONSTRUCT_FLOATS
:
10375 mips_disable_float_construction
= 0;
10378 case OPTION_NO_CONSTRUCT_FLOATS
:
10379 mips_disable_float_construction
= 1;
10391 target_big_endian
= 1;
10395 target_big_endian
= 0;
10403 if (arg
&& arg
[1] == '0')
10413 mips_debug
= atoi (arg
);
10414 /* When the MIPS assembler sees -g or -g2, it does not do
10415 optimizations which limit full symbolic debugging. We take
10416 that to be equivalent to -O0. */
10417 if (mips_debug
== 2)
10422 file_mips_isa
= ISA_MIPS1
;
10426 file_mips_isa
= ISA_MIPS2
;
10430 file_mips_isa
= ISA_MIPS3
;
10434 file_mips_isa
= ISA_MIPS4
;
10438 file_mips_isa
= ISA_MIPS5
;
10441 case OPTION_MIPS32
:
10442 file_mips_isa
= ISA_MIPS32
;
10445 case OPTION_MIPS32R2
:
10446 file_mips_isa
= ISA_MIPS32R2
;
10449 case OPTION_MIPS64
:
10450 file_mips_isa
= ISA_MIPS64
;
10454 mips_set_option_string (&mips_tune_string
, arg
);
10458 mips_set_option_string (&mips_arch_string
, arg
);
10462 mips_set_option_string (&mips_arch_string
, "4650");
10463 mips_set_option_string (&mips_tune_string
, "4650");
10466 case OPTION_NO_M4650
:
10470 mips_set_option_string (&mips_arch_string
, "4010");
10471 mips_set_option_string (&mips_tune_string
, "4010");
10474 case OPTION_NO_M4010
:
10478 mips_set_option_string (&mips_arch_string
, "4100");
10479 mips_set_option_string (&mips_tune_string
, "4100");
10482 case OPTION_NO_M4100
:
10486 mips_set_option_string (&mips_arch_string
, "3900");
10487 mips_set_option_string (&mips_tune_string
, "3900");
10490 case OPTION_NO_M3900
:
10494 mips_opts
.ase_mdmx
= 1;
10497 case OPTION_NO_MDMX
:
10498 mips_opts
.ase_mdmx
= 0;
10501 case OPTION_MIPS16
:
10502 mips_opts
.mips16
= 1;
10503 mips_no_prev_insn (FALSE
);
10506 case OPTION_NO_MIPS16
:
10507 mips_opts
.mips16
= 0;
10508 mips_no_prev_insn (FALSE
);
10511 case OPTION_MIPS3D
:
10512 mips_opts
.ase_mips3d
= 1;
10515 case OPTION_NO_MIPS3D
:
10516 mips_opts
.ase_mips3d
= 0;
10519 case OPTION_MEMBEDDED_PIC
:
10520 mips_pic
= EMBEDDED_PIC
;
10521 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10523 as_bad (_("-G may not be used with embedded PIC code"));
10526 g_switch_value
= 0x7fffffff;
10529 case OPTION_FIX_VR4122
:
10530 mips_fix_4122_bugs
= 1;
10533 case OPTION_NO_FIX_VR4122
:
10534 mips_fix_4122_bugs
= 0;
10537 case OPTION_RELAX_BRANCH
:
10538 mips_relax_branch
= 1;
10541 case OPTION_NO_RELAX_BRANCH
:
10542 mips_relax_branch
= 0;
10546 /* When generating ELF code, we permit -KPIC and -call_shared to
10547 select SVR4_PIC, and -non_shared to select no PIC. This is
10548 intended to be compatible with Irix 5. */
10549 case OPTION_CALL_SHARED
:
10550 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10552 as_bad (_("-call_shared is supported only for ELF format"));
10555 mips_pic
= SVR4_PIC
;
10556 if (g_switch_seen
&& g_switch_value
!= 0)
10558 as_bad (_("-G may not be used with SVR4 PIC code"));
10561 g_switch_value
= 0;
10564 case OPTION_NON_SHARED
:
10565 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10567 as_bad (_("-non_shared is supported only for ELF format"));
10573 /* The -xgot option tells the assembler to use 32 offsets when
10574 accessing the got in SVR4_PIC mode. It is for Irix
10579 #endif /* OBJ_ELF */
10582 if (! USE_GLOBAL_POINTER_OPT
)
10584 as_bad (_("-G is not supported for this configuration"));
10587 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10589 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10593 g_switch_value
= atoi (arg
);
10598 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10601 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10603 as_bad (_("-32 is supported for ELF format only"));
10606 mips_abi
= O32_ABI
;
10610 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10612 as_bad (_("-n32 is supported for ELF format only"));
10615 mips_abi
= N32_ABI
;
10619 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10621 as_bad (_("-64 is supported for ELF format only"));
10624 mips_abi
= N64_ABI
;
10625 if (! support_64bit_objects())
10626 as_fatal (_("No compiled in support for 64 bit object file format"));
10628 #endif /* OBJ_ELF */
10631 file_mips_gp32
= 1;
10635 file_mips_gp32
= 0;
10639 file_mips_fp32
= 1;
10643 file_mips_fp32
= 0;
10648 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10650 as_bad (_("-mabi is supported for ELF format only"));
10653 if (strcmp (arg
, "32") == 0)
10654 mips_abi
= O32_ABI
;
10655 else if (strcmp (arg
, "o64") == 0)
10656 mips_abi
= O64_ABI
;
10657 else if (strcmp (arg
, "n32") == 0)
10658 mips_abi
= N32_ABI
;
10659 else if (strcmp (arg
, "64") == 0)
10661 mips_abi
= N64_ABI
;
10662 if (! support_64bit_objects())
10663 as_fatal (_("No compiled in support for 64 bit object file "
10666 else if (strcmp (arg
, "eabi") == 0)
10667 mips_abi
= EABI_ABI
;
10670 as_fatal (_("invalid abi -mabi=%s"), arg
);
10674 #endif /* OBJ_ELF */
10676 case OPTION_M7000_HILO_FIX
:
10677 mips_7000_hilo_fix
= TRUE
;
10680 case OPTION_MNO_7000_HILO_FIX
:
10681 mips_7000_hilo_fix
= FALSE
;
10685 case OPTION_MDEBUG
:
10686 mips_flag_mdebug
= TRUE
;
10689 case OPTION_NO_MDEBUG
:
10690 mips_flag_mdebug
= FALSE
;
10692 #endif /* OBJ_ELF */
10701 /* Set up globals to generate code for the ISA or processor
10702 described by INFO. */
10705 mips_set_architecture (info
)
10706 const struct mips_cpu_info
*info
;
10710 mips_arch_info
= info
;
10711 mips_arch
= info
->cpu
;
10712 mips_opts
.isa
= info
->isa
;
10717 /* Likewise for tuning. */
10720 mips_set_tune (info
)
10721 const struct mips_cpu_info
*info
;
10725 mips_tune_info
= info
;
10726 mips_tune
= info
->cpu
;
10732 mips_after_parse_args ()
10734 /* GP relative stuff not working for PE */
10735 if (strncmp (TARGET_OS
, "pe", 2) == 0
10736 && g_switch_value
!= 0)
10739 as_bad (_("-G not supported in this configuration."));
10740 g_switch_value
= 0;
10743 /* The following code determines the architecture and register size.
10744 Similar code was added to GCC 3.3 (see override_options() in
10745 config/mips/mips.c). The GAS and GCC code should be kept in sync
10746 as much as possible. */
10748 if (mips_arch_string
!= 0)
10749 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
10751 if (mips_tune_string
!= 0)
10752 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
10754 if (file_mips_isa
!= ISA_UNKNOWN
)
10756 /* Handle -mipsN. At this point, file_mips_isa contains the
10757 ISA level specified by -mipsN, while mips_opts.isa contains
10758 the -march selection (if any). */
10759 if (mips_arch_info
!= 0)
10761 /* -march takes precedence over -mipsN, since it is more descriptive.
10762 There's no harm in specifying both as long as the ISA levels
10764 if (file_mips_isa
!= mips_opts
.isa
)
10765 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10766 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10767 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10770 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
10773 if (mips_arch_info
== 0)
10774 mips_set_architecture (mips_parse_cpu ("default CPU",
10775 MIPS_CPU_STRING_DEFAULT
));
10777 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10778 as_bad ("-march=%s is not compatible with the selected ABI",
10779 mips_arch_info
->name
);
10781 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10782 if (mips_tune_info
== 0)
10783 mips_set_tune (mips_arch_info
);
10785 if (file_mips_gp32
>= 0)
10787 /* The user specified the size of the integer registers. Make sure
10788 it agrees with the ABI and ISA. */
10789 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10790 as_bad (_("-mgp64 used with a 32-bit processor"));
10791 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10792 as_bad (_("-mgp32 used with a 64-bit ABI"));
10793 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10794 as_bad (_("-mgp64 used with a 32-bit ABI"));
10798 /* Infer the integer register size from the ABI and processor.
10799 Restrict ourselves to 32-bit registers if that's all the
10800 processor has, or if the ABI cannot handle 64-bit registers. */
10801 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10802 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10805 /* ??? GAS treats single-float processors as though they had 64-bit
10806 float registers (although it complains when double-precision
10807 instructions are used). As things stand, saying they have 32-bit
10808 registers would lead to spurious "register must be even" messages.
10809 So here we assume float registers are always the same size as
10810 integer ones, unless the user says otherwise. */
10811 if (file_mips_fp32
< 0)
10812 file_mips_fp32
= file_mips_gp32
;
10814 /* End of GCC-shared inference code. */
10816 /* ??? When do we want this flag to be set? Who uses it? */
10817 if (file_mips_gp32
== 1
10818 && mips_abi
== NO_ABI
10819 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10820 mips_32bitmode
= 1;
10822 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10823 as_bad (_("trap exception not supported at ISA 1"));
10825 /* If the selected architecture includes support for ASEs, enable
10826 generation of code for them. */
10827 if (mips_opts
.mips16
== -1)
10828 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
10829 if (mips_opts
.ase_mips3d
== -1)
10830 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
10831 if (mips_opts
.ase_mdmx
== -1)
10832 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
10834 file_mips_isa
= mips_opts
.isa
;
10835 file_ase_mips16
= mips_opts
.mips16
;
10836 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10837 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10838 mips_opts
.gp32
= file_mips_gp32
;
10839 mips_opts
.fp32
= file_mips_fp32
;
10841 if (mips_flag_mdebug
< 0)
10843 #ifdef OBJ_MAYBE_ECOFF
10844 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10845 mips_flag_mdebug
= 1;
10847 #endif /* OBJ_MAYBE_ECOFF */
10848 mips_flag_mdebug
= 0;
10853 mips_init_after_args ()
10855 /* initialize opcodes */
10856 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10857 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10861 md_pcrel_from (fixP
)
10864 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10865 && fixP
->fx_addsy
!= (symbolS
*) NULL
10866 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10869 /* Return the address of the delay slot. */
10870 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10873 /* This is called before the symbol table is processed. In order to
10874 work with gcc when using mips-tfile, we must keep all local labels.
10875 However, in other cases, we want to discard them. If we were
10876 called with -g, but we didn't see any debugging information, it may
10877 mean that gcc is smuggling debugging information through to
10878 mips-tfile, in which case we must generate all local labels. */
10881 mips_frob_file_before_adjust ()
10883 #ifndef NO_ECOFF_DEBUGGING
10884 if (ECOFF_DEBUGGING
10886 && ! ecoff_debugging_seen
)
10887 flag_keep_locals
= 1;
10891 /* Sort any unmatched HI16_S relocs so that they immediately precede
10892 the corresponding LO reloc. This is called before md_apply_fix3 and
10893 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10894 explicit use of the %hi modifier. */
10899 struct mips_hi_fixup
*l
;
10901 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10903 segment_info_type
*seginfo
;
10906 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10908 /* If a GOT16 relocation turns out to be against a global symbol,
10909 there isn't supposed to be a matching LO. */
10910 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10911 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10914 /* Check quickly whether the next fixup happens to be a matching %lo. */
10915 if (fixup_has_matching_lo_p (l
->fixp
))
10918 /* Look through the fixups for this segment for a matching %lo.
10919 When we find one, move the %hi just in front of it. We do
10920 this in two passes. In the first pass, we try to find a
10921 unique %lo. In the second pass, we permit multiple %hi
10922 relocs for a single %lo (this is a GNU extension). */
10923 seginfo
= seg_info (l
->seg
);
10924 for (pass
= 0; pass
< 2; pass
++)
10929 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10931 /* Check whether this is a %lo fixup which matches l->fixp. */
10932 if (f
->fx_r_type
== BFD_RELOC_LO16
10933 && f
->fx_addsy
== l
->fixp
->fx_addsy
10934 && f
->fx_offset
== l
->fixp
->fx_offset
10937 || !reloc_needs_lo_p (prev
->fx_r_type
)
10938 || !fixup_has_matching_lo_p (prev
)))
10942 /* Move l->fixp before f. */
10943 for (pf
= &seginfo
->fix_root
;
10945 pf
= &(*pf
)->fx_next
)
10946 assert (*pf
!= NULL
);
10948 *pf
= l
->fixp
->fx_next
;
10950 l
->fixp
->fx_next
= f
;
10952 seginfo
->fix_root
= l
->fixp
;
10954 prev
->fx_next
= l
->fixp
;
10965 #if 0 /* GCC code motion plus incomplete dead code elimination
10966 can leave a %hi without a %lo. */
10968 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10969 _("Unmatched %%hi reloc"));
10975 /* When generating embedded PIC code we need to use a special
10976 relocation to represent the difference of two symbols in the .text
10977 section (switch tables use a difference of this sort). See
10978 include/coff/mips.h for details. This macro checks whether this
10979 fixup requires the special reloc. */
10980 #define SWITCH_TABLE(fixp) \
10981 ((fixp)->fx_r_type == BFD_RELOC_32 \
10982 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10983 && (fixp)->fx_addsy != NULL \
10984 && (fixp)->fx_subsy != NULL \
10985 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10986 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10988 /* When generating embedded PIC code we must keep all PC relative
10989 relocations, in case the linker has to relax a call. We also need
10990 to keep relocations for switch table entries.
10992 We may have combined relocations without symbols in the N32/N64 ABI.
10993 We have to prevent gas from dropping them. */
10996 mips_force_relocation (fixp
)
10999 if (generic_force_reloc (fixp
))
11003 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11004 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11005 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11006 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11009 return (mips_pic
== EMBEDDED_PIC
11011 || SWITCH_TABLE (fixp
)
11012 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
11013 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
11018 mips_need_elf_addend_fixup (fixP
)
11021 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
11023 if (mips_pic
== EMBEDDED_PIC
11024 && S_IS_WEAK (fixP
->fx_addsy
))
11026 if (mips_pic
!= EMBEDDED_PIC
11027 && (S_IS_WEAK (fixP
->fx_addsy
)
11028 || S_IS_EXTERNAL (fixP
->fx_addsy
))
11029 && !S_IS_COMMON (fixP
->fx_addsy
))
11031 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
11032 && (((bfd_get_section_flags (stdoutput
,
11033 S_GET_SEGMENT (fixP
->fx_addsy
))
11034 & (SEC_LINK_ONCE
| SEC_MERGE
)) != 0)
11035 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
11037 sizeof (".gnu.linkonce") - 1)))
11043 /* Apply a fixup to the object file. */
11046 md_apply_fix3 (fixP
, valP
, seg
)
11049 segT seg ATTRIBUTE_UNUSED
;
11054 static int previous_fx_r_type
= 0;
11056 /* FIXME: Maybe just return for all reloc types not listed below?
11057 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
11058 if (fixP
->fx_r_type
== BFD_RELOC_8
)
11061 assert (fixP
->fx_size
== 4
11062 || fixP
->fx_r_type
== BFD_RELOC_16
11063 || fixP
->fx_r_type
== BFD_RELOC_32
11064 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
11065 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
11066 || fixP
->fx_r_type
== BFD_RELOC_LO16
11067 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
11068 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
11069 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
11070 || fixP
->fx_r_type
== BFD_RELOC_64
11071 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11072 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11073 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
11074 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
11075 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
11076 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
11077 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
11078 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11079 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11080 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
11084 /* If we aren't adjusting this fixup to be against the section
11085 symbol, we need to adjust the value. */
11087 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11089 if (mips_need_elf_addend_fixup (fixP
))
11091 reloc_howto_type
*howto
;
11092 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
11096 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11097 if (value
!= 0 && howto
&& howto
->partial_inplace
11098 && (! fixP
->fx_pcrel
|| howto
->pcrel_offset
))
11100 /* In this case, the bfd_install_relocation routine will
11101 incorrectly add the symbol value back in. We just want
11102 the addend to appear in the object file.
11104 howto->pcrel_offset is added for R_MIPS_PC16, which is
11105 generated for code like
11116 /* Make sure the addend is still non-zero. If it became zero
11117 after the last operation, set it to a spurious value and
11118 subtract the same value from the object file's contents. */
11123 /* The in-place addends for LO16 relocations are signed;
11124 leave the matching HI16 in-place addends as zero. */
11125 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
11127 bfd_vma contents
, mask
, field
;
11129 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
11132 target_big_endian
);
11134 /* MASK has bits set where the relocation should go.
11135 FIELD is -value, shifted into the appropriate place
11136 for this relocation. */
11137 mask
= 1 << (howto
->bitsize
- 1);
11138 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
11139 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
11141 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
11142 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11144 target_big_endian
);
11150 /* This code was generated using trial and error and so is
11151 fragile and not trustworthy. If you change it, you should
11152 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11153 they still pass. */
11154 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
11156 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11158 /* BFD's REL handling, for MIPS, is _very_ weird.
11159 This gives the right results, but it can't possibly
11160 be the way things are supposed to work. */
11161 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11162 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
11163 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11168 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
11170 /* We are not done if this is a composite relocation to set up gp. */
11171 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11172 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11173 || (fixP
->fx_r_type
== BFD_RELOC_64
11174 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11175 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11176 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11177 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11178 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11180 previous_fx_r_type
= fixP
->fx_r_type
;
11182 switch (fixP
->fx_r_type
)
11184 case BFD_RELOC_MIPS_JMP
:
11185 case BFD_RELOC_MIPS_SHIFT5
:
11186 case BFD_RELOC_MIPS_SHIFT6
:
11187 case BFD_RELOC_MIPS_GOT_DISP
:
11188 case BFD_RELOC_MIPS_GOT_PAGE
:
11189 case BFD_RELOC_MIPS_GOT_OFST
:
11190 case BFD_RELOC_MIPS_SUB
:
11191 case BFD_RELOC_MIPS_INSERT_A
:
11192 case BFD_RELOC_MIPS_INSERT_B
:
11193 case BFD_RELOC_MIPS_DELETE
:
11194 case BFD_RELOC_MIPS_HIGHEST
:
11195 case BFD_RELOC_MIPS_HIGHER
:
11196 case BFD_RELOC_MIPS_SCN_DISP
:
11197 case BFD_RELOC_MIPS_REL16
:
11198 case BFD_RELOC_MIPS_RELGOT
:
11199 case BFD_RELOC_MIPS_JALR
:
11200 case BFD_RELOC_HI16
:
11201 case BFD_RELOC_HI16_S
:
11202 case BFD_RELOC_GPREL16
:
11203 case BFD_RELOC_MIPS_LITERAL
:
11204 case BFD_RELOC_MIPS_CALL16
:
11205 case BFD_RELOC_MIPS_GOT16
:
11206 case BFD_RELOC_GPREL32
:
11207 case BFD_RELOC_MIPS_GOT_HI16
:
11208 case BFD_RELOC_MIPS_GOT_LO16
:
11209 case BFD_RELOC_MIPS_CALL_HI16
:
11210 case BFD_RELOC_MIPS_CALL_LO16
:
11211 case BFD_RELOC_MIPS16_GPREL
:
11212 if (fixP
->fx_pcrel
)
11213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11214 _("Invalid PC relative reloc"));
11215 /* Nothing needed to do. The value comes from the reloc entry */
11218 case BFD_RELOC_MIPS16_JMP
:
11219 /* We currently always generate a reloc against a symbol, which
11220 means that we don't want an addend even if the symbol is
11222 fixP
->fx_addnumber
= 0;
11225 case BFD_RELOC_PCREL_HI16_S
:
11226 /* The addend for this is tricky if it is internal, so we just
11227 do everything here rather than in bfd_install_relocation. */
11228 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11233 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11235 /* For an external symbol adjust by the address to make it
11236 pcrel_offset. We use the address of the RELLO reloc
11237 which follows this one. */
11238 value
+= (fixP
->fx_next
->fx_frag
->fr_address
11239 + fixP
->fx_next
->fx_where
);
11241 value
= ((value
+ 0x8000) >> 16) & 0xffff;
11242 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11243 if (target_big_endian
)
11245 md_number_to_chars ((char *) buf
, value
, 2);
11248 case BFD_RELOC_PCREL_LO16
:
11249 /* The addend for this is tricky if it is internal, so we just
11250 do everything here rather than in bfd_install_relocation. */
11251 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11256 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11257 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11258 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11259 if (target_big_endian
)
11261 md_number_to_chars ((char *) buf
, value
, 2);
11265 /* This is handled like BFD_RELOC_32, but we output a sign
11266 extended value if we are only 32 bits. */
11268 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11270 if (8 <= sizeof (valueT
))
11271 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11278 w1
= w2
= fixP
->fx_where
;
11279 if (target_big_endian
)
11283 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
11284 if ((value
& 0x80000000) != 0)
11288 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
11293 case BFD_RELOC_RVA
:
11295 /* If we are deleting this reloc entry, we must fill in the
11296 value now. This can happen if we have a .word which is not
11297 resolved when it appears but is later defined. We also need
11298 to fill in the value if this is an embedded PIC switch table
11301 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11302 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11307 /* If we are deleting this reloc entry, we must fill in the
11309 assert (fixP
->fx_size
== 2);
11311 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11315 case BFD_RELOC_LO16
:
11316 /* When handling an embedded PIC switch statement, we can wind
11317 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11320 if (value
+ 0x8000 > 0xffff)
11321 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11322 _("relocation overflow"));
11323 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11324 if (target_big_endian
)
11326 md_number_to_chars ((char *) buf
, value
, 2);
11330 case BFD_RELOC_16_PCREL_S2
:
11331 if ((value
& 0x3) != 0)
11332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11333 _("Branch to odd address (%lx)"), (long) value
);
11336 * We need to save the bits in the instruction since fixup_segment()
11337 * might be deleting the relocation entry (i.e., a branch within
11338 * the current segment).
11340 if (!fixP
->fx_done
&& (value
!= 0 || HAVE_NEWABI
))
11342 /* If 'value' is zero, the remaining reloc code won't actually
11343 do the store, so it must be done here. This is probably
11344 a bug somewhere. */
11346 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11347 || fixP
->fx_addsy
== NULL
/* ??? */
11348 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
11349 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11351 value
= (offsetT
) value
>> 2;
11353 /* update old instruction data */
11354 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11355 if (target_big_endian
)
11356 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11358 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11360 if (value
+ 0x8000 <= 0xffff)
11361 insn
|= value
& 0xffff;
11364 /* The branch offset is too large. If this is an
11365 unconditional branch, and we are not generating PIC code,
11366 we can convert it to an absolute jump instruction. */
11367 if (mips_pic
== NO_PIC
11369 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11370 && (fixP
->fx_frag
->fr_address
11371 < text_section
->vma
+ text_section
->_raw_size
)
11372 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11373 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11374 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11376 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11377 insn
= 0x0c000000; /* jal */
11379 insn
= 0x08000000; /* j */
11380 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11382 fixP
->fx_addsy
= section_symbol (text_section
);
11383 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11387 /* If we got here, we have branch-relaxation disabled,
11388 and there's nothing we can do to fix this instruction
11389 without turning it into a longer sequence. */
11390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11391 _("Branch out of range"));
11395 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11398 case BFD_RELOC_VTABLE_INHERIT
:
11401 && !S_IS_DEFINED (fixP
->fx_addsy
)
11402 && !S_IS_WEAK (fixP
->fx_addsy
))
11403 S_SET_WEAK (fixP
->fx_addsy
);
11406 case BFD_RELOC_VTABLE_ENTRY
:
11420 const struct mips_opcode
*p
;
11421 int treg
, sreg
, dreg
, shamt
;
11426 for (i
= 0; i
< NUMOPCODES
; ++i
)
11428 p
= &mips_opcodes
[i
];
11429 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11431 printf ("%08lx %s\t", oc
, p
->name
);
11432 treg
= (oc
>> 16) & 0x1f;
11433 sreg
= (oc
>> 21) & 0x1f;
11434 dreg
= (oc
>> 11) & 0x1f;
11435 shamt
= (oc
>> 6) & 0x1f;
11437 for (args
= p
->args
;; ++args
)
11448 printf ("%c", *args
);
11452 assert (treg
== sreg
);
11453 printf ("$%d,$%d", treg
, sreg
);
11458 printf ("$%d", dreg
);
11463 printf ("$%d", treg
);
11467 printf ("0x%x", treg
);
11472 printf ("$%d", sreg
);
11476 printf ("0x%08lx", oc
& 0x1ffffff);
11483 printf ("%d", imm
);
11488 printf ("$%d", shamt
);
11499 printf (_("%08lx UNDEFINED\n"), oc
);
11510 name
= input_line_pointer
;
11511 c
= get_symbol_end ();
11512 p
= (symbolS
*) symbol_find_or_make (name
);
11513 *input_line_pointer
= c
;
11517 /* Align the current frag to a given power of two. The MIPS assembler
11518 also automatically adjusts any preceding label. */
11521 mips_align (to
, fill
, label
)
11526 mips_emit_delays (FALSE
);
11527 frag_align (to
, fill
, 0);
11528 record_alignment (now_seg
, to
);
11531 assert (S_GET_SEGMENT (label
) == now_seg
);
11532 symbol_set_frag (label
, frag_now
);
11533 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11537 /* Align to a given power of two. .align 0 turns off the automatic
11538 alignment used by the data creating pseudo-ops. */
11542 int x ATTRIBUTE_UNUSED
;
11545 register long temp_fill
;
11546 long max_alignment
= 15;
11550 o Note that the assembler pulls down any immediately preceeding label
11551 to the aligned address.
11552 o It's not documented but auto alignment is reinstated by
11553 a .align pseudo instruction.
11554 o Note also that after auto alignment is turned off the mips assembler
11555 issues an error on attempt to assemble an improperly aligned data item.
11560 temp
= get_absolute_expression ();
11561 if (temp
> max_alignment
)
11562 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11565 as_warn (_("Alignment negative: 0 assumed."));
11568 if (*input_line_pointer
== ',')
11570 ++input_line_pointer
;
11571 temp_fill
= get_absolute_expression ();
11578 mips_align (temp
, (int) temp_fill
,
11579 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11586 demand_empty_rest_of_line ();
11590 mips_flush_pending_output ()
11592 mips_emit_delays (FALSE
);
11593 mips_clear_insn_labels ();
11602 /* When generating embedded PIC code, we only use the .text, .lit8,
11603 .sdata and .sbss sections. We change the .data and .rdata
11604 pseudo-ops to use .sdata. */
11605 if (mips_pic
== EMBEDDED_PIC
11606 && (sec
== 'd' || sec
== 'r'))
11610 /* The ELF backend needs to know that we are changing sections, so
11611 that .previous works correctly. We could do something like check
11612 for an obj_section_change_hook macro, but that might be confusing
11613 as it would not be appropriate to use it in the section changing
11614 functions in read.c, since obj-elf.c intercepts those. FIXME:
11615 This should be cleaner, somehow. */
11616 obj_elf_section_change_hook ();
11619 mips_emit_delays (FALSE
);
11629 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11630 demand_empty_rest_of_line ();
11634 if (USE_GLOBAL_POINTER_OPT
)
11636 seg
= subseg_new (RDATA_SECTION_NAME
,
11637 (subsegT
) get_absolute_expression ());
11638 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11640 bfd_set_section_flags (stdoutput
, seg
,
11646 if (strcmp (TARGET_OS
, "elf") != 0)
11647 record_alignment (seg
, 4);
11649 demand_empty_rest_of_line ();
11653 as_bad (_("No read only data section in this object file format"));
11654 demand_empty_rest_of_line ();
11660 if (USE_GLOBAL_POINTER_OPT
)
11662 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11663 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11665 bfd_set_section_flags (stdoutput
, seg
,
11666 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11668 if (strcmp (TARGET_OS
, "elf") != 0)
11669 record_alignment (seg
, 4);
11671 demand_empty_rest_of_line ();
11676 as_bad (_("Global pointers not supported; recompile -G 0"));
11677 demand_empty_rest_of_line ();
11686 s_change_section (ignore
)
11687 int ignore ATTRIBUTE_UNUSED
;
11690 char *section_name
;
11695 int section_entry_size
;
11696 int section_alignment
;
11698 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11701 section_name
= input_line_pointer
;
11702 c
= get_symbol_end ();
11704 next_c
= *(input_line_pointer
+ 1);
11706 /* Do we have .section Name<,"flags">? */
11707 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11709 /* just after name is now '\0'. */
11710 *input_line_pointer
= c
;
11711 input_line_pointer
= section_name
;
11712 obj_elf_section (ignore
);
11715 input_line_pointer
++;
11717 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11719 section_type
= get_absolute_expression ();
11722 if (*input_line_pointer
++ == ',')
11723 section_flag
= get_absolute_expression ();
11726 if (*input_line_pointer
++ == ',')
11727 section_entry_size
= get_absolute_expression ();
11729 section_entry_size
= 0;
11730 if (*input_line_pointer
++ == ',')
11731 section_alignment
= get_absolute_expression ();
11733 section_alignment
= 0;
11735 section_name
= xstrdup (section_name
);
11737 obj_elf_change_section (section_name
, section_type
, section_flag
,
11738 section_entry_size
, 0, 0, 0);
11740 if (now_seg
->name
!= section_name
)
11741 free (section_name
);
11742 #endif /* OBJ_ELF */
11746 mips_enable_auto_align ()
11757 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11758 mips_emit_delays (FALSE
);
11759 if (log_size
> 0 && auto_align
)
11760 mips_align (log_size
, 0, label
);
11761 mips_clear_insn_labels ();
11762 cons (1 << log_size
);
11766 s_float_cons (type
)
11771 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11773 mips_emit_delays (FALSE
);
11778 mips_align (3, 0, label
);
11780 mips_align (2, 0, label
);
11783 mips_clear_insn_labels ();
11788 /* Handle .globl. We need to override it because on Irix 5 you are
11791 where foo is an undefined symbol, to mean that foo should be
11792 considered to be the address of a function. */
11796 int x ATTRIBUTE_UNUSED
;
11803 name
= input_line_pointer
;
11804 c
= get_symbol_end ();
11805 symbolP
= symbol_find_or_make (name
);
11806 *input_line_pointer
= c
;
11807 SKIP_WHITESPACE ();
11809 /* On Irix 5, every global symbol that is not explicitly labelled as
11810 being a function is apparently labelled as being an object. */
11813 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11818 secname
= input_line_pointer
;
11819 c
= get_symbol_end ();
11820 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11822 as_bad (_("%s: no such section"), secname
);
11823 *input_line_pointer
= c
;
11825 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11826 flag
= BSF_FUNCTION
;
11829 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11831 S_SET_EXTERNAL (symbolP
);
11832 demand_empty_rest_of_line ();
11837 int x ATTRIBUTE_UNUSED
;
11842 opt
= input_line_pointer
;
11843 c
= get_symbol_end ();
11847 /* FIXME: What does this mean? */
11849 else if (strncmp (opt
, "pic", 3) == 0)
11853 i
= atoi (opt
+ 3);
11857 mips_pic
= SVR4_PIC
;
11859 as_bad (_(".option pic%d not supported"), i
);
11861 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11863 if (g_switch_seen
&& g_switch_value
!= 0)
11864 as_warn (_("-G may not be used with SVR4 PIC code"));
11865 g_switch_value
= 0;
11866 bfd_set_gp_size (stdoutput
, 0);
11870 as_warn (_("Unrecognized option \"%s\""), opt
);
11872 *input_line_pointer
= c
;
11873 demand_empty_rest_of_line ();
11876 /* This structure is used to hold a stack of .set values. */
11878 struct mips_option_stack
11880 struct mips_option_stack
*next
;
11881 struct mips_set_options options
;
11884 static struct mips_option_stack
*mips_opts_stack
;
11886 /* Handle the .set pseudo-op. */
11890 int x ATTRIBUTE_UNUSED
;
11892 char *name
= input_line_pointer
, ch
;
11894 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11895 ++input_line_pointer
;
11896 ch
= *input_line_pointer
;
11897 *input_line_pointer
= '\0';
11899 if (strcmp (name
, "reorder") == 0)
11901 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11903 /* If we still have pending nops, we can discard them. The
11904 usual nop handling will insert any that are still
11906 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11907 * (mips_opts
.mips16
? 2 : 4));
11908 prev_nop_frag
= NULL
;
11910 mips_opts
.noreorder
= 0;
11912 else if (strcmp (name
, "noreorder") == 0)
11914 mips_emit_delays (TRUE
);
11915 mips_opts
.noreorder
= 1;
11916 mips_any_noreorder
= 1;
11918 else if (strcmp (name
, "at") == 0)
11920 mips_opts
.noat
= 0;
11922 else if (strcmp (name
, "noat") == 0)
11924 mips_opts
.noat
= 1;
11926 else if (strcmp (name
, "macro") == 0)
11928 mips_opts
.warn_about_macros
= 0;
11930 else if (strcmp (name
, "nomacro") == 0)
11932 if (mips_opts
.noreorder
== 0)
11933 as_bad (_("`noreorder' must be set before `nomacro'"));
11934 mips_opts
.warn_about_macros
= 1;
11936 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11938 mips_opts
.nomove
= 0;
11940 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11942 mips_opts
.nomove
= 1;
11944 else if (strcmp (name
, "bopt") == 0)
11946 mips_opts
.nobopt
= 0;
11948 else if (strcmp (name
, "nobopt") == 0)
11950 mips_opts
.nobopt
= 1;
11952 else if (strcmp (name
, "mips16") == 0
11953 || strcmp (name
, "MIPS-16") == 0)
11954 mips_opts
.mips16
= 1;
11955 else if (strcmp (name
, "nomips16") == 0
11956 || strcmp (name
, "noMIPS-16") == 0)
11957 mips_opts
.mips16
= 0;
11958 else if (strcmp (name
, "mips3d") == 0)
11959 mips_opts
.ase_mips3d
= 1;
11960 else if (strcmp (name
, "nomips3d") == 0)
11961 mips_opts
.ase_mips3d
= 0;
11962 else if (strcmp (name
, "mdmx") == 0)
11963 mips_opts
.ase_mdmx
= 1;
11964 else if (strcmp (name
, "nomdmx") == 0)
11965 mips_opts
.ase_mdmx
= 0;
11966 else if (strncmp (name
, "mips", 4) == 0)
11970 /* Permit the user to change the ISA on the fly. Needless to
11971 say, misuse can cause serious problems. */
11972 if (strcmp (name
, "mips0") == 0)
11975 mips_opts
.isa
= file_mips_isa
;
11977 else if (strcmp (name
, "mips1") == 0)
11978 mips_opts
.isa
= ISA_MIPS1
;
11979 else if (strcmp (name
, "mips2") == 0)
11980 mips_opts
.isa
= ISA_MIPS2
;
11981 else if (strcmp (name
, "mips3") == 0)
11982 mips_opts
.isa
= ISA_MIPS3
;
11983 else if (strcmp (name
, "mips4") == 0)
11984 mips_opts
.isa
= ISA_MIPS4
;
11985 else if (strcmp (name
, "mips5") == 0)
11986 mips_opts
.isa
= ISA_MIPS5
;
11987 else if (strcmp (name
, "mips32") == 0)
11988 mips_opts
.isa
= ISA_MIPS32
;
11989 else if (strcmp (name
, "mips32r2") == 0)
11990 mips_opts
.isa
= ISA_MIPS32R2
;
11991 else if (strcmp (name
, "mips64") == 0)
11992 mips_opts
.isa
= ISA_MIPS64
;
11994 as_bad (_("unknown ISA level %s"), name
+ 4);
11996 switch (mips_opts
.isa
)
12004 mips_opts
.gp32
= 1;
12005 mips_opts
.fp32
= 1;
12011 mips_opts
.gp32
= 0;
12012 mips_opts
.fp32
= 0;
12015 as_bad (_("unknown ISA level %s"), name
+ 4);
12020 mips_opts
.gp32
= file_mips_gp32
;
12021 mips_opts
.fp32
= file_mips_fp32
;
12024 else if (strcmp (name
, "autoextend") == 0)
12025 mips_opts
.noautoextend
= 0;
12026 else if (strcmp (name
, "noautoextend") == 0)
12027 mips_opts
.noautoextend
= 1;
12028 else if (strcmp (name
, "push") == 0)
12030 struct mips_option_stack
*s
;
12032 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12033 s
->next
= mips_opts_stack
;
12034 s
->options
= mips_opts
;
12035 mips_opts_stack
= s
;
12037 else if (strcmp (name
, "pop") == 0)
12039 struct mips_option_stack
*s
;
12041 s
= mips_opts_stack
;
12043 as_bad (_(".set pop with no .set push"));
12046 /* If we're changing the reorder mode we need to handle
12047 delay slots correctly. */
12048 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12049 mips_emit_delays (TRUE
);
12050 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12052 if (prev_nop_frag
!= NULL
)
12054 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12055 * (mips_opts
.mips16
? 2 : 4));
12056 prev_nop_frag
= NULL
;
12060 mips_opts
= s
->options
;
12061 mips_opts_stack
= s
->next
;
12067 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12069 *input_line_pointer
= ch
;
12070 demand_empty_rest_of_line ();
12073 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12074 .option pic2. It means to generate SVR4 PIC calls. */
12077 s_abicalls (ignore
)
12078 int ignore ATTRIBUTE_UNUSED
;
12080 mips_pic
= SVR4_PIC
;
12081 if (USE_GLOBAL_POINTER_OPT
)
12083 if (g_switch_seen
&& g_switch_value
!= 0)
12084 as_warn (_("-G may not be used with SVR4 PIC code"));
12085 g_switch_value
= 0;
12087 bfd_set_gp_size (stdoutput
, 0);
12088 demand_empty_rest_of_line ();
12091 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12092 PIC code. It sets the $gp register for the function based on the
12093 function address, which is in the register named in the argument.
12094 This uses a relocation against _gp_disp, which is handled specially
12095 by the linker. The result is:
12096 lui $gp,%hi(_gp_disp)
12097 addiu $gp,$gp,%lo(_gp_disp)
12098 addu $gp,$gp,.cpload argument
12099 The .cpload argument is normally $25 == $t9. */
12103 int ignore ATTRIBUTE_UNUSED
;
12108 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12109 .cpload is ignored. */
12110 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12116 /* .cpload should be in a .set noreorder section. */
12117 if (mips_opts
.noreorder
== 0)
12118 as_warn (_(".cpload not in noreorder section"));
12120 ex
.X_op
= O_symbol
;
12121 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12122 ex
.X_op_symbol
= NULL
;
12123 ex
.X_add_number
= 0;
12125 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12126 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12128 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12129 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
12130 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
12132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
12133 mips_gp_register
, mips_gp_register
, tc_get_register (0));
12135 demand_empty_rest_of_line ();
12138 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12139 .cpsetup $reg1, offset|$reg2, label
12141 If offset is given, this results in:
12142 sd $gp, offset($sp)
12143 lui $gp, %hi(%neg(%gp_rel(label)))
12144 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12145 daddu $gp, $gp, $reg1
12147 If $reg2 is given, this results in:
12148 daddu $reg2, $gp, $0
12149 lui $gp, %hi(%neg(%gp_rel(label)))
12150 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12151 daddu $gp, $gp, $reg1
12152 $reg1 is normally $25 == $t9. */
12155 int ignore ATTRIBUTE_UNUSED
;
12157 expressionS ex_off
;
12158 expressionS ex_sym
;
12163 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12164 We also need NewABI support. */
12165 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12171 reg1
= tc_get_register (0);
12172 SKIP_WHITESPACE ();
12173 if (*input_line_pointer
!= ',')
12175 as_bad (_("missing argument separator ',' for .cpsetup"));
12179 ++input_line_pointer
;
12180 SKIP_WHITESPACE ();
12181 if (*input_line_pointer
== '$')
12183 mips_cpreturn_register
= tc_get_register (0);
12184 mips_cpreturn_offset
= -1;
12188 mips_cpreturn_offset
= get_absolute_expression ();
12189 mips_cpreturn_register
= -1;
12191 SKIP_WHITESPACE ();
12192 if (*input_line_pointer
!= ',')
12194 as_bad (_("missing argument separator ',' for .cpsetup"));
12198 ++input_line_pointer
;
12199 SKIP_WHITESPACE ();
12200 expression (&ex_sym
);
12202 if (mips_cpreturn_register
== -1)
12204 ex_off
.X_op
= O_constant
;
12205 ex_off
.X_add_symbol
= NULL
;
12206 ex_off
.X_op_symbol
= NULL
;
12207 ex_off
.X_add_number
= mips_cpreturn_offset
;
12209 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
12210 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12213 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12214 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12216 /* Ensure there's room for the next two instructions, so that `f'
12217 doesn't end up with an address in the wrong frag. */
12220 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12221 (int) BFD_RELOC_GPREL16
);
12222 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12223 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12224 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12225 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12228 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12229 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12230 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12231 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12232 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12233 0, NULL
, 0, 0, BFD_RELOC_LO16
);
12235 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12236 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
12237 mips_gp_register
, mips_gp_register
, reg1
);
12239 demand_empty_rest_of_line ();
12244 int ignore ATTRIBUTE_UNUSED
;
12246 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12247 .cplocal is ignored. */
12248 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12254 mips_gp_register
= tc_get_register (0);
12255 demand_empty_rest_of_line ();
12258 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12259 offset from $sp. The offset is remembered, and after making a PIC
12260 call $gp is restored from that location. */
12263 s_cprestore (ignore
)
12264 int ignore ATTRIBUTE_UNUSED
;
12269 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12270 .cprestore is ignored. */
12271 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12277 mips_cprestore_offset
= get_absolute_expression ();
12278 mips_cprestore_valid
= 1;
12280 ex
.X_op
= O_constant
;
12281 ex
.X_add_symbol
= NULL
;
12282 ex
.X_op_symbol
= NULL
;
12283 ex
.X_add_number
= mips_cprestore_offset
;
12285 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
12286 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
12287 mips_gp_register
, SP
);
12289 demand_empty_rest_of_line ();
12292 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12293 was given in the preceeding .gpsetup, it results in:
12294 ld $gp, offset($sp)
12296 If a register $reg2 was given there, it results in:
12297 daddiu $gp, $gp, $reg2
12300 s_cpreturn (ignore
)
12301 int ignore ATTRIBUTE_UNUSED
;
12306 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12307 We also need NewABI support. */
12308 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12314 if (mips_cpreturn_register
== -1)
12316 ex
.X_op
= O_constant
;
12317 ex
.X_add_symbol
= NULL
;
12318 ex
.X_op_symbol
= NULL
;
12319 ex
.X_add_number
= mips_cpreturn_offset
;
12321 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12322 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12325 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12326 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12328 demand_empty_rest_of_line ();
12331 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12332 code. It sets the offset to use in gp_rel relocations. */
12336 int ignore ATTRIBUTE_UNUSED
;
12338 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12339 We also need NewABI support. */
12340 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12346 mips_gprel_offset
= get_absolute_expression ();
12348 demand_empty_rest_of_line ();
12351 /* Handle the .gpword pseudo-op. This is used when generating PIC
12352 code. It generates a 32 bit GP relative reloc. */
12356 int ignore ATTRIBUTE_UNUSED
;
12362 /* When not generating PIC code, this is treated as .word. */
12363 if (mips_pic
!= SVR4_PIC
)
12369 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12370 mips_emit_delays (TRUE
);
12372 mips_align (2, 0, label
);
12373 mips_clear_insn_labels ();
12377 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12379 as_bad (_("Unsupported use of .gpword"));
12380 ignore_rest_of_line ();
12384 md_number_to_chars (p
, (valueT
) 0, 4);
12385 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12386 BFD_RELOC_GPREL32
);
12388 demand_empty_rest_of_line ();
12393 int ignore ATTRIBUTE_UNUSED
;
12399 /* When not generating PIC code, this is treated as .dword. */
12400 if (mips_pic
!= SVR4_PIC
)
12406 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12407 mips_emit_delays (TRUE
);
12409 mips_align (3, 0, label
);
12410 mips_clear_insn_labels ();
12414 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12416 as_bad (_("Unsupported use of .gpdword"));
12417 ignore_rest_of_line ();
12421 md_number_to_chars (p
, (valueT
) 0, 8);
12422 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12423 BFD_RELOC_GPREL32
);
12425 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12426 ex
.X_op
= O_absent
;
12427 ex
.X_add_symbol
= 0;
12428 ex
.X_add_number
= 0;
12429 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12432 demand_empty_rest_of_line ();
12435 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12436 tables in SVR4 PIC code. */
12440 int ignore ATTRIBUTE_UNUSED
;
12445 /* This is ignored when not generating SVR4 PIC code. */
12446 if (mips_pic
!= SVR4_PIC
)
12452 /* Add $gp to the register named as an argument. */
12453 reg
= tc_get_register (0);
12454 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12455 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
12456 "d,v,t", reg
, reg
, mips_gp_register
);
12458 demand_empty_rest_of_line ();
12461 /* Handle the .insn pseudo-op. This marks instruction labels in
12462 mips16 mode. This permits the linker to handle them specially,
12463 such as generating jalx instructions when needed. We also make
12464 them odd for the duration of the assembly, in order to generate the
12465 right sort of code. We will make them even in the adjust_symtab
12466 routine, while leaving them marked. This is convenient for the
12467 debugger and the disassembler. The linker knows to make them odd
12472 int ignore ATTRIBUTE_UNUSED
;
12474 mips16_mark_labels ();
12476 demand_empty_rest_of_line ();
12479 /* Handle a .stabn directive. We need these in order to mark a label
12480 as being a mips16 text label correctly. Sometimes the compiler
12481 will emit a label, followed by a .stabn, and then switch sections.
12482 If the label and .stabn are in mips16 mode, then the label is
12483 really a mips16 text label. */
12490 mips16_mark_labels ();
12495 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12499 s_mips_weakext (ignore
)
12500 int ignore ATTRIBUTE_UNUSED
;
12507 name
= input_line_pointer
;
12508 c
= get_symbol_end ();
12509 symbolP
= symbol_find_or_make (name
);
12510 S_SET_WEAK (symbolP
);
12511 *input_line_pointer
= c
;
12513 SKIP_WHITESPACE ();
12515 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12517 if (S_IS_DEFINED (symbolP
))
12519 as_bad ("ignoring attempt to redefine symbol %s",
12520 S_GET_NAME (symbolP
));
12521 ignore_rest_of_line ();
12525 if (*input_line_pointer
== ',')
12527 ++input_line_pointer
;
12528 SKIP_WHITESPACE ();
12532 if (exp
.X_op
!= O_symbol
)
12534 as_bad ("bad .weakext directive");
12535 ignore_rest_of_line ();
12538 symbol_set_value_expression (symbolP
, &exp
);
12541 demand_empty_rest_of_line ();
12544 /* Parse a register string into a number. Called from the ECOFF code
12545 to parse .frame. The argument is non-zero if this is the frame
12546 register, so that we can record it in mips_frame_reg. */
12549 tc_get_register (frame
)
12554 SKIP_WHITESPACE ();
12555 if (*input_line_pointer
++ != '$')
12557 as_warn (_("expected `$'"));
12560 else if (ISDIGIT (*input_line_pointer
))
12562 reg
= get_absolute_expression ();
12563 if (reg
< 0 || reg
>= 32)
12565 as_warn (_("Bad register number"));
12571 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12574 input_line_pointer
+= 2;
12576 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12579 input_line_pointer
+= 2;
12581 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12584 input_line_pointer
+= 2;
12586 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12589 input_line_pointer
+= 2;
12591 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12594 input_line_pointer
+= 2;
12596 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12599 input_line_pointer
+= 3;
12601 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12604 input_line_pointer
+= 3;
12606 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12609 input_line_pointer
+= 4;
12613 as_warn (_("Unrecognized register name"));
12615 while (ISALNUM(*input_line_pointer
))
12616 input_line_pointer
++;
12621 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12622 mips_frame_reg_valid
= 1;
12623 mips_cprestore_valid
= 0;
12629 md_section_align (seg
, addr
)
12633 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12636 /* We don't need to align ELF sections to the full alignment.
12637 However, Irix 5 may prefer that we align them at least to a 16
12638 byte boundary. We don't bother to align the sections if we are
12639 targeted for an embedded system. */
12640 if (strcmp (TARGET_OS
, "elf") == 0)
12646 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12649 /* Utility routine, called from above as well. If called while the
12650 input file is still being read, it's only an approximation. (For
12651 example, a symbol may later become defined which appeared to be
12652 undefined earlier.) */
12655 nopic_need_relax (sym
, before_relaxing
)
12657 int before_relaxing
;
12662 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12664 const char *symname
;
12667 /* Find out whether this symbol can be referenced off the $gp
12668 register. It can be if it is smaller than the -G size or if
12669 it is in the .sdata or .sbss section. Certain symbols can
12670 not be referenced off the $gp, although it appears as though
12672 symname
= S_GET_NAME (sym
);
12673 if (symname
!= (const char *) NULL
12674 && (strcmp (symname
, "eprol") == 0
12675 || strcmp (symname
, "etext") == 0
12676 || strcmp (symname
, "_gp") == 0
12677 || strcmp (symname
, "edata") == 0
12678 || strcmp (symname
, "_fbss") == 0
12679 || strcmp (symname
, "_fdata") == 0
12680 || strcmp (symname
, "_ftext") == 0
12681 || strcmp (symname
, "end") == 0
12682 || strcmp (symname
, "_gp_disp") == 0))
12684 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12686 #ifndef NO_ECOFF_DEBUGGING
12687 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12688 && (symbol_get_obj (sym
)->ecoff_extern_size
12689 <= g_switch_value
))
12691 /* We must defer this decision until after the whole
12692 file has been read, since there might be a .extern
12693 after the first use of this symbol. */
12694 || (before_relaxing
12695 #ifndef NO_ECOFF_DEBUGGING
12696 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12698 && S_GET_VALUE (sym
) == 0)
12699 || (S_GET_VALUE (sym
) != 0
12700 && S_GET_VALUE (sym
) <= g_switch_value
)))
12704 const char *segname
;
12706 segname
= segment_name (S_GET_SEGMENT (sym
));
12707 assert (strcmp (segname
, ".lit8") != 0
12708 && strcmp (segname
, ".lit4") != 0);
12709 change
= (strcmp (segname
, ".sdata") != 0
12710 && strcmp (segname
, ".sbss") != 0
12711 && strncmp (segname
, ".sdata.", 7) != 0
12712 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12717 /* We are not optimizing for the $gp register. */
12722 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12725 pic_need_relax (sym
, segtype
)
12730 bfd_boolean linkonce
;
12732 /* Handle the case of a symbol equated to another symbol. */
12733 while (symbol_equated_reloc_p (sym
))
12737 /* It's possible to get a loop here in a badly written
12739 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12745 symsec
= S_GET_SEGMENT (sym
);
12747 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12749 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12751 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12755 /* The GNU toolchain uses an extension for ELF: a section
12756 beginning with the magic string .gnu.linkonce is a linkonce
12758 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12759 sizeof ".gnu.linkonce" - 1) == 0)
12763 /* This must duplicate the test in adjust_reloc_syms. */
12764 return (symsec
!= &bfd_und_section
12765 && symsec
!= &bfd_abs_section
12766 && ! bfd_is_com_section (symsec
)
12769 /* A global or weak symbol is treated as external. */
12770 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12771 || (! S_IS_WEAK (sym
)
12772 && (! S_IS_EXTERNAL (sym
)
12773 || mips_pic
== EMBEDDED_PIC
)))
12779 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12780 extended opcode. SEC is the section the frag is in. */
12783 mips16_extended_frag (fragp
, sec
, stretch
)
12789 register const struct mips16_immed_operand
*op
;
12791 int mintiny
, maxtiny
;
12795 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12797 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12800 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12801 op
= mips16_immed_operands
;
12802 while (op
->type
!= type
)
12805 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12810 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12813 maxtiny
= 1 << op
->nbits
;
12818 maxtiny
= (1 << op
->nbits
) - 1;
12823 mintiny
= - (1 << (op
->nbits
- 1));
12824 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12827 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12828 val
= S_GET_VALUE (fragp
->fr_symbol
);
12829 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12835 /* We won't have the section when we are called from
12836 mips_relax_frag. However, we will always have been called
12837 from md_estimate_size_before_relax first. If this is a
12838 branch to a different section, we mark it as such. If SEC is
12839 NULL, and the frag is not marked, then it must be a branch to
12840 the same section. */
12843 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12848 /* Must have been called from md_estimate_size_before_relax. */
12851 fragp
->fr_subtype
=
12852 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12854 /* FIXME: We should support this, and let the linker
12855 catch branches and loads that are out of range. */
12856 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12857 _("unsupported PC relative reference to different section"));
12861 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12862 /* Assume non-extended on the first relaxation pass.
12863 The address we have calculated will be bogus if this is
12864 a forward branch to another frag, as the forward frag
12865 will have fr_address == 0. */
12869 /* In this case, we know for sure that the symbol fragment is in
12870 the same section. If the relax_marker of the symbol fragment
12871 differs from the relax_marker of this fragment, we have not
12872 yet adjusted the symbol fragment fr_address. We want to add
12873 in STRETCH in order to get a better estimate of the address.
12874 This particularly matters because of the shift bits. */
12876 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12880 /* Adjust stretch for any alignment frag. Note that if have
12881 been expanding the earlier code, the symbol may be
12882 defined in what appears to be an earlier frag. FIXME:
12883 This doesn't handle the fr_subtype field, which specifies
12884 a maximum number of bytes to skip when doing an
12886 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12888 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12891 stretch
= - ((- stretch
)
12892 & ~ ((1 << (int) f
->fr_offset
) - 1));
12894 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12903 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12905 /* The base address rules are complicated. The base address of
12906 a branch is the following instruction. The base address of a
12907 PC relative load or add is the instruction itself, but if it
12908 is in a delay slot (in which case it can not be extended) use
12909 the address of the instruction whose delay slot it is in. */
12910 if (type
== 'p' || type
== 'q')
12914 /* If we are currently assuming that this frag should be
12915 extended, then, the current address is two bytes
12917 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12920 /* Ignore the low bit in the target, since it will be set
12921 for a text label. */
12922 if ((val
& 1) != 0)
12925 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12927 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12930 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12932 /* Branch offsets have an implicit 0 in the lowest bit. */
12933 if (type
== 'p' || type
== 'q')
12936 /* If any of the shifted bits are set, we must use an extended
12937 opcode. If the address depends on the size of this
12938 instruction, this can lead to a loop, so we arrange to always
12939 use an extended opcode. We only check this when we are in
12940 the main relaxation loop, when SEC is NULL. */
12941 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12943 fragp
->fr_subtype
=
12944 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12948 /* If we are about to mark a frag as extended because the value
12949 is precisely maxtiny + 1, then there is a chance of an
12950 infinite loop as in the following code:
12955 In this case when the la is extended, foo is 0x3fc bytes
12956 away, so the la can be shrunk, but then foo is 0x400 away, so
12957 the la must be extended. To avoid this loop, we mark the
12958 frag as extended if it was small, and is about to become
12959 extended with a value of maxtiny + 1. */
12960 if (val
== ((maxtiny
+ 1) << op
->shift
)
12961 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12964 fragp
->fr_subtype
=
12965 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12969 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12970 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12972 if ((val
& ((1 << op
->shift
) - 1)) != 0
12973 || val
< (mintiny
<< op
->shift
)
12974 || val
> (maxtiny
<< op
->shift
))
12980 /* Compute the length of a branch sequence, and adjust the
12981 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12982 worst-case length is computed, with UPDATE being used to indicate
12983 whether an unconditional (-1), branch-likely (+1) or regular (0)
12984 branch is to be computed. */
12986 relaxed_branch_length (fragp
, sec
, update
)
12991 bfd_boolean toofar
;
12995 && S_IS_DEFINED (fragp
->fr_symbol
)
12996 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13001 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13003 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13007 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13010 /* If the symbol is not defined or it's in a different segment,
13011 assume the user knows what's going on and emit a short
13017 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13019 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13020 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13021 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13027 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13030 if (mips_pic
!= NO_PIC
)
13032 /* Additional space for PIC loading of target address. */
13034 if (mips_opts
.isa
== ISA_MIPS1
)
13035 /* Additional space for $at-stabilizing nop. */
13039 /* If branch is conditional. */
13040 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13047 /* Estimate the size of a frag before relaxing. Unless this is the
13048 mips16, we are not really relaxing here, and the final size is
13049 encoded in the subtype information. For the mips16, we have to
13050 decide whether we are using an extended opcode or not. */
13053 md_estimate_size_before_relax (fragp
, segtype
)
13059 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13062 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13064 return fragp
->fr_var
;
13067 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13068 /* We don't want to modify the EXTENDED bit here; it might get us
13069 into infinite loops. We change it only in mips_relax_frag(). */
13070 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13072 if (mips_pic
== NO_PIC
)
13073 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13074 else if (mips_pic
== SVR4_PIC
)
13075 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13081 /* Record the offset to the first reloc in the fr_opcode field.
13082 This lets md_convert_frag and tc_gen_reloc know that the code
13083 must be expanded. */
13084 fragp
->fr_opcode
= (fragp
->fr_literal
13086 - RELAX_OLD (fragp
->fr_subtype
)
13087 + RELAX_RELOC1 (fragp
->fr_subtype
));
13088 /* FIXME: This really needs as_warn_where. */
13089 if (RELAX_WARN (fragp
->fr_subtype
))
13090 as_warn (_("AT used after \".set noat\" or macro used after "
13091 "\".set nomacro\""));
13093 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13099 /* This is called to see whether a reloc against a defined symbol
13100 should be converted into a reloc against a section. Don't adjust
13101 MIPS16 jump relocations, so we don't have to worry about the format
13102 of the offset in the .o file. Don't adjust relocations against
13103 mips16 symbols, so that the linker can find them if it needs to set
13107 mips_fix_adjustable (fixp
)
13110 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13113 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13114 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13117 if (fixp
->fx_addsy
== NULL
)
13121 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13122 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13123 && fixp
->fx_subsy
== NULL
)
13130 /* Translate internal representation of relocation info to BFD target
13134 tc_gen_reloc (section
, fixp
)
13135 asection
*section ATTRIBUTE_UNUSED
;
13138 static arelent
*retval
[4];
13140 bfd_reloc_code_real_type code
;
13142 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
13145 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13146 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13147 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13149 if (mips_pic
== EMBEDDED_PIC
13150 && SWITCH_TABLE (fixp
))
13152 /* For a switch table entry we use a special reloc. The addend
13153 is actually the difference between the reloc address and the
13155 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13156 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13157 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13158 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13160 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
13162 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13163 reloc
->addend
= fixp
->fx_addnumber
;
13166 /* We use a special addend for an internal RELLO reloc. */
13167 if (symbol_section_p (fixp
->fx_addsy
))
13168 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13170 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13173 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13175 assert (fixp
->fx_next
!= NULL
13176 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13178 /* The reloc is relative to the RELLO; adjust the addend
13180 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13181 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
13184 /* We use a special addend for an internal RELHI reloc. */
13185 if (symbol_section_p (fixp
->fx_addsy
))
13186 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
13187 + fixp
->fx_next
->fx_where
13188 - S_GET_VALUE (fixp
->fx_subsy
));
13190 reloc
->addend
= (fixp
->fx_addnumber
13191 + fixp
->fx_next
->fx_frag
->fr_address
13192 + fixp
->fx_next
->fx_where
);
13195 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13196 reloc
->addend
= fixp
->fx_addnumber
;
13199 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13200 /* A gruesome hack which is a result of the gruesome gas reloc
13202 reloc
->addend
= reloc
->address
;
13204 reloc
->addend
= -reloc
->address
;
13207 /* If this is a variant frag, we may need to adjust the existing
13208 reloc and generate a new one. */
13209 if (fixp
->fx_frag
->fr_opcode
!= NULL
13210 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13212 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13213 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13214 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13215 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13216 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13217 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13222 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13224 /* If this is not the last reloc in this frag, then we have two
13225 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13226 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13227 the second one handle all of them. */
13228 if (fixp
->fx_next
!= NULL
13229 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13231 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13232 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13233 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13234 && (fixp
->fx_next
->fx_r_type
13235 == BFD_RELOC_MIPS_GOT_LO16
))
13236 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13237 && (fixp
->fx_next
->fx_r_type
13238 == BFD_RELOC_MIPS_CALL_LO16
)));
13243 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13244 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13245 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13247 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13248 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13249 reloc2
->address
= (reloc
->address
13250 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13251 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13252 reloc2
->addend
= fixp
->fx_addnumber
;
13253 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13254 assert (reloc2
->howto
!= NULL
);
13256 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13260 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13263 reloc3
->address
+= 4;
13266 if (mips_pic
== NO_PIC
)
13268 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13269 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13271 else if (mips_pic
== SVR4_PIC
)
13273 switch (fixp
->fx_r_type
)
13277 case BFD_RELOC_MIPS_GOT16
:
13279 case BFD_RELOC_MIPS_GOT_LO16
:
13280 case BFD_RELOC_MIPS_CALL_LO16
:
13281 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13283 case BFD_RELOC_MIPS_CALL16
:
13286 /* BFD_RELOC_MIPS_GOT16;*/
13287 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13288 reloc2
->howto
= bfd_reloc_type_lookup
13289 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13292 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13299 /* newabi uses R_MIPS_GOT_DISP for local symbols */
13300 if (HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
)
13302 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13307 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13308 entry to be used in the relocation's section offset. */
13309 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13311 reloc
->address
= reloc
->addend
;
13315 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13316 fixup_segment converted a non-PC relative reloc into a PC
13317 relative reloc. In such a case, we need to convert the reloc
13319 code
= fixp
->fx_r_type
;
13320 if (fixp
->fx_pcrel
)
13325 code
= BFD_RELOC_8_PCREL
;
13328 code
= BFD_RELOC_16_PCREL
;
13331 code
= BFD_RELOC_32_PCREL
;
13334 code
= BFD_RELOC_64_PCREL
;
13336 case BFD_RELOC_8_PCREL
:
13337 case BFD_RELOC_16_PCREL
:
13338 case BFD_RELOC_32_PCREL
:
13339 case BFD_RELOC_64_PCREL
:
13340 case BFD_RELOC_16_PCREL_S2
:
13341 case BFD_RELOC_PCREL_HI16_S
:
13342 case BFD_RELOC_PCREL_LO16
:
13345 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13346 _("Cannot make %s relocation PC relative"),
13347 bfd_get_reloc_code_name (code
));
13352 /* md_apply_fix3 has a double-subtraction hack to get
13353 bfd_install_relocation to behave nicely. GPREL relocations are
13354 handled correctly without this hack, so undo it here. We can't
13355 stop md_apply_fix3 from subtracting twice in the first place since
13356 the fake addend is required for variant frags above. */
13357 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
13358 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
13359 && reloc
->addend
!= 0
13360 && mips_need_elf_addend_fixup (fixp
))
13361 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
13364 /* To support a PC relative reloc when generating embedded PIC code
13365 for ECOFF, we use a Cygnus extension. We check for that here to
13366 make sure that we don't let such a reloc escape normally. */
13367 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13368 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13369 && code
== BFD_RELOC_16_PCREL_S2
13370 && mips_pic
!= EMBEDDED_PIC
)
13371 reloc
->howto
= NULL
;
13373 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13375 if (reloc
->howto
== NULL
)
13377 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13378 _("Can not represent %s relocation in this object file format"),
13379 bfd_get_reloc_code_name (code
));
13386 /* Relax a machine dependent frag. This returns the amount by which
13387 the current size of the frag should change. */
13390 mips_relax_frag (sec
, fragp
, stretch
)
13395 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13397 offsetT old_var
= fragp
->fr_var
;
13399 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13401 return fragp
->fr_var
- old_var
;
13404 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13407 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13409 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13411 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13416 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13418 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13425 /* Convert a machine dependent frag. */
13428 md_convert_frag (abfd
, asec
, fragp
)
13429 bfd
*abfd ATTRIBUTE_UNUSED
;
13436 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13439 unsigned long insn
;
13443 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13445 if (target_big_endian
)
13446 insn
= bfd_getb32 (buf
);
13448 insn
= bfd_getl32 (buf
);
13450 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13452 /* We generate a fixup instead of applying it right now
13453 because, if there are linker relaxations, we're going to
13454 need the relocations. */
13455 exp
.X_op
= O_symbol
;
13456 exp
.X_add_symbol
= fragp
->fr_symbol
;
13457 exp
.X_add_number
= fragp
->fr_offset
;
13459 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13461 BFD_RELOC_16_PCREL_S2
);
13462 fixp
->fx_file
= fragp
->fr_file
;
13463 fixp
->fx_line
= fragp
->fr_line
;
13465 md_number_to_chars ((char *)buf
, insn
, 4);
13472 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13473 _("relaxed out-of-range branch into a jump"));
13475 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13478 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13480 /* Reverse the branch. */
13481 switch ((insn
>> 28) & 0xf)
13484 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13485 have the condition reversed by tweaking a single
13486 bit, and their opcodes all have 0x4???????. */
13487 assert ((insn
& 0xf1000000) == 0x41000000);
13488 insn
^= 0x00010000;
13492 /* bltz 0x04000000 bgez 0x04010000
13493 bltzal 0x04100000 bgezal 0x04110000 */
13494 assert ((insn
& 0xfc0e0000) == 0x04000000);
13495 insn
^= 0x00010000;
13499 /* beq 0x10000000 bne 0x14000000
13500 blez 0x18000000 bgtz 0x1c000000 */
13501 insn
^= 0x04000000;
13509 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13511 /* Clear the and-link bit. */
13512 assert ((insn
& 0xfc1c0000) == 0x04100000);
13514 /* bltzal 0x04100000 bgezal 0x04110000
13515 bltzall 0x04120000 bgezall 0x04130000 */
13516 insn
&= ~0x00100000;
13519 /* Branch over the branch (if the branch was likely) or the
13520 full jump (not likely case). Compute the offset from the
13521 current instruction to branch to. */
13522 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13526 /* How many bytes in instructions we've already emitted? */
13527 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13528 /* How many bytes in instructions from here to the end? */
13529 i
= fragp
->fr_var
- i
;
13531 /* Convert to instruction count. */
13533 /* Branch counts from the next instruction. */
13536 /* Branch over the jump. */
13537 md_number_to_chars ((char *)buf
, insn
, 4);
13541 md_number_to_chars ((char*)buf
, 0, 4);
13544 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13546 /* beql $0, $0, 2f */
13548 /* Compute the PC offset from the current instruction to
13549 the end of the variable frag. */
13550 /* How many bytes in instructions we've already emitted? */
13551 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13552 /* How many bytes in instructions from here to the end? */
13553 i
= fragp
->fr_var
- i
;
13554 /* Convert to instruction count. */
13556 /* Don't decrement i, because we want to branch over the
13560 md_number_to_chars ((char *)buf
, insn
, 4);
13563 md_number_to_chars ((char *)buf
, 0, 4);
13568 if (mips_pic
== NO_PIC
)
13571 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13572 ? 0x0c000000 : 0x08000000);
13573 exp
.X_op
= O_symbol
;
13574 exp
.X_add_symbol
= fragp
->fr_symbol
;
13575 exp
.X_add_number
= fragp
->fr_offset
;
13577 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13578 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13579 fixp
->fx_file
= fragp
->fr_file
;
13580 fixp
->fx_line
= fragp
->fr_line
;
13582 md_number_to_chars ((char*)buf
, insn
, 4);
13587 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13588 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13589 exp
.X_op
= O_symbol
;
13590 exp
.X_add_symbol
= fragp
->fr_symbol
;
13591 exp
.X_add_number
= fragp
->fr_offset
;
13593 if (fragp
->fr_offset
)
13595 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13596 exp
.X_add_number
= 0;
13599 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13600 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13601 fixp
->fx_file
= fragp
->fr_file
;
13602 fixp
->fx_line
= fragp
->fr_line
;
13604 md_number_to_chars ((char*)buf
, insn
, 4);
13607 if (mips_opts
.isa
== ISA_MIPS1
)
13610 md_number_to_chars ((char*)buf
, 0, 4);
13614 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13615 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13617 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13618 4, &exp
, 0, BFD_RELOC_LO16
);
13619 fixp
->fx_file
= fragp
->fr_file
;
13620 fixp
->fx_line
= fragp
->fr_line
;
13622 md_number_to_chars ((char*)buf
, insn
, 4);
13626 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13631 md_number_to_chars ((char*)buf
, insn
, 4);
13636 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13637 + fragp
->fr_fix
+ fragp
->fr_var
);
13639 fragp
->fr_fix
+= fragp
->fr_var
;
13644 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13647 register const struct mips16_immed_operand
*op
;
13648 bfd_boolean small
, ext
;
13651 unsigned long insn
;
13652 bfd_boolean use_extend
;
13653 unsigned short extend
;
13655 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13656 op
= mips16_immed_operands
;
13657 while (op
->type
!= type
)
13660 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13671 resolve_symbol_value (fragp
->fr_symbol
);
13672 val
= S_GET_VALUE (fragp
->fr_symbol
);
13677 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13679 /* The rules for the base address of a PC relative reloc are
13680 complicated; see mips16_extended_frag. */
13681 if (type
== 'p' || type
== 'q')
13686 /* Ignore the low bit in the target, since it will be
13687 set for a text label. */
13688 if ((val
& 1) != 0)
13691 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13693 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13696 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13699 /* Make sure the section winds up with the alignment we have
13702 record_alignment (asec
, op
->shift
);
13706 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13707 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13708 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13709 _("extended instruction in delay slot"));
13711 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13713 if (target_big_endian
)
13714 insn
= bfd_getb16 (buf
);
13716 insn
= bfd_getl16 (buf
);
13718 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13719 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13720 small
, ext
, &insn
, &use_extend
, &extend
);
13724 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13725 fragp
->fr_fix
+= 2;
13729 md_number_to_chars ((char *) buf
, insn
, 2);
13730 fragp
->fr_fix
+= 2;
13735 if (fragp
->fr_opcode
== NULL
)
13738 old
= RELAX_OLD (fragp
->fr_subtype
);
13739 new = RELAX_NEW (fragp
->fr_subtype
);
13740 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13743 memcpy (fixptr
- old
, fixptr
, new);
13745 fragp
->fr_fix
+= new - old
;
13751 /* This function is called after the relocs have been generated.
13752 We've been storing mips16 text labels as odd. Here we convert them
13753 back to even for the convenience of the debugger. */
13756 mips_frob_file_after_relocs ()
13759 unsigned int count
, i
;
13761 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13764 syms
= bfd_get_outsymbols (stdoutput
);
13765 count
= bfd_get_symcount (stdoutput
);
13766 for (i
= 0; i
< count
; i
++, syms
++)
13768 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13769 && ((*syms
)->value
& 1) != 0)
13771 (*syms
)->value
&= ~1;
13772 /* If the symbol has an odd size, it was probably computed
13773 incorrectly, so adjust that as well. */
13774 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13775 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13782 /* This function is called whenever a label is defined. It is used
13783 when handling branch delays; if a branch has a label, we assume we
13784 can not move it. */
13787 mips_define_label (sym
)
13790 struct insn_label_list
*l
;
13792 if (free_insn_labels
== NULL
)
13793 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13796 l
= free_insn_labels
;
13797 free_insn_labels
= l
->next
;
13801 l
->next
= insn_labels
;
13805 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13807 /* Some special processing for a MIPS ELF file. */
13810 mips_elf_final_processing ()
13812 /* Write out the register information. */
13813 if (mips_abi
!= N64_ABI
)
13817 s
.ri_gprmask
= mips_gprmask
;
13818 s
.ri_cprmask
[0] = mips_cprmask
[0];
13819 s
.ri_cprmask
[1] = mips_cprmask
[1];
13820 s
.ri_cprmask
[2] = mips_cprmask
[2];
13821 s
.ri_cprmask
[3] = mips_cprmask
[3];
13822 /* The gp_value field is set by the MIPS ELF backend. */
13824 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13825 ((Elf32_External_RegInfo
*)
13826 mips_regmask_frag
));
13830 Elf64_Internal_RegInfo s
;
13832 s
.ri_gprmask
= mips_gprmask
;
13834 s
.ri_cprmask
[0] = mips_cprmask
[0];
13835 s
.ri_cprmask
[1] = mips_cprmask
[1];
13836 s
.ri_cprmask
[2] = mips_cprmask
[2];
13837 s
.ri_cprmask
[3] = mips_cprmask
[3];
13838 /* The gp_value field is set by the MIPS ELF backend. */
13840 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13841 ((Elf64_External_RegInfo
*)
13842 mips_regmask_frag
));
13845 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13846 sort of BFD interface for this. */
13847 if (mips_any_noreorder
)
13848 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13849 if (mips_pic
!= NO_PIC
)
13850 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13852 /* Set MIPS ELF flags for ASEs. */
13853 if (file_ase_mips16
)
13854 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13855 #if 0 /* XXX FIXME */
13856 if (file_ase_mips3d
)
13857 elf_elfheader (stdoutput
)->e_flags
|= ???;
13860 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13862 /* Set the MIPS ELF ABI flags. */
13863 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13864 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13865 else if (mips_abi
== O64_ABI
)
13866 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13867 else if (mips_abi
== EABI_ABI
)
13869 if (!file_mips_gp32
)
13870 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13872 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13874 else if (mips_abi
== N32_ABI
)
13875 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13877 /* Nothing to do for N64_ABI. */
13879 if (mips_32bitmode
)
13880 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13883 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13885 typedef struct proc
{
13887 unsigned long reg_mask
;
13888 unsigned long reg_offset
;
13889 unsigned long fpreg_mask
;
13890 unsigned long fpreg_offset
;
13891 unsigned long frame_offset
;
13892 unsigned long frame_reg
;
13893 unsigned long pc_reg
;
13896 static procS cur_proc
;
13897 static procS
*cur_proc_ptr
;
13898 static int numprocs
;
13900 /* Fill in an rs_align_code fragment. */
13903 mips_handle_align (fragp
)
13906 if (fragp
->fr_type
!= rs_align_code
)
13909 if (mips_opts
.mips16
)
13911 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13912 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13917 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13918 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13926 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13930 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13941 /* check for premature end, nesting errors, etc */
13943 as_warn (_("missing .end at end of assembly"));
13952 if (*input_line_pointer
== '-')
13954 ++input_line_pointer
;
13957 if (!ISDIGIT (*input_line_pointer
))
13958 as_bad (_("expected simple number"));
13959 if (input_line_pointer
[0] == '0')
13961 if (input_line_pointer
[1] == 'x')
13963 input_line_pointer
+= 2;
13964 while (ISXDIGIT (*input_line_pointer
))
13967 val
|= hex_value (*input_line_pointer
++);
13969 return negative
? -val
: val
;
13973 ++input_line_pointer
;
13974 while (ISDIGIT (*input_line_pointer
))
13977 val
|= *input_line_pointer
++ - '0';
13979 return negative
? -val
: val
;
13982 if (!ISDIGIT (*input_line_pointer
))
13984 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13985 *input_line_pointer
, *input_line_pointer
);
13986 as_warn (_("invalid number"));
13989 while (ISDIGIT (*input_line_pointer
))
13992 val
+= *input_line_pointer
++ - '0';
13994 return negative
? -val
: val
;
13997 /* The .file directive; just like the usual .file directive, but there
13998 is an initial number which is the ECOFF file index. In the non-ECOFF
13999 case .file implies DWARF-2. */
14003 int x ATTRIBUTE_UNUSED
;
14005 static int first_file_directive
= 0;
14007 if (ECOFF_DEBUGGING
)
14016 filename
= dwarf2_directive_file (0);
14018 /* Versions of GCC up to 3.1 start files with a ".file"
14019 directive even for stabs output. Make sure that this
14020 ".file" is handled. Note that you need a version of GCC
14021 after 3.1 in order to support DWARF-2 on MIPS. */
14022 if (filename
!= NULL
&& ! first_file_directive
)
14024 (void) new_logical_line (filename
, -1);
14025 s_app_file_string (filename
);
14027 first_file_directive
= 1;
14031 /* The .loc directive, implying DWARF-2. */
14035 int x ATTRIBUTE_UNUSED
;
14037 if (!ECOFF_DEBUGGING
)
14038 dwarf2_directive_loc (0);
14041 /* The .end directive. */
14045 int x ATTRIBUTE_UNUSED
;
14050 /* Following functions need their own .frame and .cprestore directives. */
14051 mips_frame_reg_valid
= 0;
14052 mips_cprestore_valid
= 0;
14054 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14057 demand_empty_rest_of_line ();
14062 #ifdef BFD_ASSEMBLER
14063 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14068 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14075 as_warn (_(".end not in text section"));
14079 as_warn (_(".end directive without a preceding .ent directive."));
14080 demand_empty_rest_of_line ();
14086 assert (S_GET_NAME (p
));
14087 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14088 as_warn (_(".end symbol does not match .ent symbol."));
14090 if (debug_type
== DEBUG_STABS
)
14091 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14095 as_warn (_(".end directive missing or unknown symbol"));
14098 /* Generate a .pdr section. */
14099 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14101 segT saved_seg
= now_seg
;
14102 subsegT saved_subseg
= now_subseg
;
14107 dot
= frag_now_fix ();
14109 #ifdef md_flush_pending_output
14110 md_flush_pending_output ();
14114 subseg_set (pdr_seg
, 0);
14116 /* Write the symbol. */
14117 exp
.X_op
= O_symbol
;
14118 exp
.X_add_symbol
= p
;
14119 exp
.X_add_number
= 0;
14120 emit_expr (&exp
, 4);
14122 fragp
= frag_more (7 * 4);
14124 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
14125 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
14126 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
14127 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
14128 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
14129 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
14130 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
14132 subseg_set (saved_seg
, saved_subseg
);
14134 #endif /* OBJ_ELF */
14136 cur_proc_ptr
= NULL
;
14139 /* The .aent and .ent directives. */
14148 symbolP
= get_symbol ();
14149 if (*input_line_pointer
== ',')
14150 ++input_line_pointer
;
14151 SKIP_WHITESPACE ();
14152 if (ISDIGIT (*input_line_pointer
)
14153 || *input_line_pointer
== '-')
14156 #ifdef BFD_ASSEMBLER
14157 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14162 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14169 as_warn (_(".ent or .aent not in text section."));
14171 if (!aent
&& cur_proc_ptr
)
14172 as_warn (_("missing .end"));
14176 /* This function needs its own .frame and .cprestore directives. */
14177 mips_frame_reg_valid
= 0;
14178 mips_cprestore_valid
= 0;
14180 cur_proc_ptr
= &cur_proc
;
14181 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14183 cur_proc_ptr
->isym
= symbolP
;
14185 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14189 if (debug_type
== DEBUG_STABS
)
14190 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14191 S_GET_NAME (symbolP
));
14194 demand_empty_rest_of_line ();
14197 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14198 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14199 s_mips_frame is used so that we can set the PDR information correctly.
14200 We can't use the ecoff routines because they make reference to the ecoff
14201 symbol table (in the mdebug section). */
14204 s_mips_frame (ignore
)
14205 int ignore ATTRIBUTE_UNUSED
;
14208 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14212 if (cur_proc_ptr
== (procS
*) NULL
)
14214 as_warn (_(".frame outside of .ent"));
14215 demand_empty_rest_of_line ();
14219 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14221 SKIP_WHITESPACE ();
14222 if (*input_line_pointer
++ != ','
14223 || get_absolute_expression_and_terminator (&val
) != ',')
14225 as_warn (_("Bad .frame directive"));
14226 --input_line_pointer
;
14227 demand_empty_rest_of_line ();
14231 cur_proc_ptr
->frame_offset
= val
;
14232 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14234 demand_empty_rest_of_line ();
14237 #endif /* OBJ_ELF */
14241 /* The .fmask and .mask directives. If the mdebug section is present
14242 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14243 embedded targets, s_mips_mask is used so that we can set the PDR
14244 information correctly. We can't use the ecoff routines because they
14245 make reference to the ecoff symbol table (in the mdebug section). */
14248 s_mips_mask (reg_type
)
14252 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14256 if (cur_proc_ptr
== (procS
*) NULL
)
14258 as_warn (_(".mask/.fmask outside of .ent"));
14259 demand_empty_rest_of_line ();
14263 if (get_absolute_expression_and_terminator (&mask
) != ',')
14265 as_warn (_("Bad .mask/.fmask directive"));
14266 --input_line_pointer
;
14267 demand_empty_rest_of_line ();
14271 off
= get_absolute_expression ();
14273 if (reg_type
== 'F')
14275 cur_proc_ptr
->fpreg_mask
= mask
;
14276 cur_proc_ptr
->fpreg_offset
= off
;
14280 cur_proc_ptr
->reg_mask
= mask
;
14281 cur_proc_ptr
->reg_offset
= off
;
14284 demand_empty_rest_of_line ();
14287 #endif /* OBJ_ELF */
14288 s_ignore (reg_type
);
14291 /* The .loc directive. */
14302 assert (now_seg
== text_section
);
14304 lineno
= get_number ();
14305 addroff
= frag_now_fix ();
14307 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14308 S_SET_TYPE (symbolP
, N_SLINE
);
14309 S_SET_OTHER (symbolP
, 0);
14310 S_SET_DESC (symbolP
, lineno
);
14311 symbolP
->sy_segment
= now_seg
;
14315 /* A table describing all the processors gas knows about. Names are
14316 matched in the order listed.
14318 To ease comparison, please keep this table in the same order as
14319 gcc's mips_cpu_info_table[]. */
14320 static const struct mips_cpu_info mips_cpu_info_table
[] =
14322 /* Entries for generic ISAs */
14323 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14324 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14325 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14326 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14327 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14328 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14329 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14330 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14333 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14334 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14335 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14338 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14341 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14342 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14343 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14344 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14345 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14346 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14347 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14348 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14349 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14350 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14351 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14352 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14355 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14356 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14357 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14358 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14359 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14360 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14361 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14362 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14363 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14364 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14365 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14366 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
14369 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
14370 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14371 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14374 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14375 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14377 /* Broadcom SB-1 CPU core */
14378 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14385 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14386 with a final "000" replaced by "k". Ignore case.
14388 Note: this function is shared between GCC and GAS. */
14391 mips_strict_matching_cpu_name_p (canonical
, given
)
14392 const char *canonical
, *given
;
14394 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14395 given
++, canonical
++;
14397 return ((*given
== 0 && *canonical
== 0)
14398 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14402 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14403 CPU name. We've traditionally allowed a lot of variation here.
14405 Note: this function is shared between GCC and GAS. */
14408 mips_matching_cpu_name_p (canonical
, given
)
14409 const char *canonical
, *given
;
14411 /* First see if the name matches exactly, or with a final "000"
14412 turned into "k". */
14413 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14416 /* If not, try comparing based on numerical designation alone.
14417 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14418 if (TOLOWER (*given
) == 'r')
14420 if (!ISDIGIT (*given
))
14423 /* Skip over some well-known prefixes in the canonical name,
14424 hoping to find a number there too. */
14425 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14427 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14429 else if (TOLOWER (canonical
[0]) == 'r')
14432 return mips_strict_matching_cpu_name_p (canonical
, given
);
14436 /* Parse an option that takes the name of a processor as its argument.
14437 OPTION is the name of the option and CPU_STRING is the argument.
14438 Return the corresponding processor enumeration if the CPU_STRING is
14439 recognized, otherwise report an error and return null.
14441 A similar function exists in GCC. */
14443 static const struct mips_cpu_info
*
14444 mips_parse_cpu (option
, cpu_string
)
14445 const char *option
, *cpu_string
;
14447 const struct mips_cpu_info
*p
;
14449 /* 'from-abi' selects the most compatible architecture for the given
14450 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14451 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14452 version. Look first at the -mgp options, if given, otherwise base
14453 the choice on MIPS_DEFAULT_64BIT.
14455 Treat NO_ABI like the EABIs. One reason to do this is that the
14456 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14457 architecture. This code picks MIPS I for 'mips' and MIPS III for
14458 'mips64', just as we did in the days before 'from-abi'. */
14459 if (strcasecmp (cpu_string
, "from-abi") == 0)
14461 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14462 return mips_cpu_info_from_isa (ISA_MIPS1
);
14464 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14465 return mips_cpu_info_from_isa (ISA_MIPS3
);
14467 if (file_mips_gp32
>= 0)
14468 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14470 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14475 /* 'default' has traditionally been a no-op. Probably not very useful. */
14476 if (strcasecmp (cpu_string
, "default") == 0)
14479 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14480 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14483 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14487 /* Return the canonical processor information for ISA (a member of the
14488 ISA_MIPS* enumeration). */
14490 static const struct mips_cpu_info
*
14491 mips_cpu_info_from_isa (isa
)
14496 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14497 if (mips_cpu_info_table
[i
].is_isa
14498 && isa
== mips_cpu_info_table
[i
].isa
)
14499 return (&mips_cpu_info_table
[i
]);
14505 show (stream
, string
, col_p
, first_p
)
14507 const char *string
;
14513 fprintf (stream
, "%24s", "");
14518 fprintf (stream
, ", ");
14522 if (*col_p
+ strlen (string
) > 72)
14524 fprintf (stream
, "\n%24s", "");
14528 fprintf (stream
, "%s", string
);
14529 *col_p
+= strlen (string
);
14535 md_show_usage (stream
)
14541 fprintf (stream
, _("\
14543 -membedded-pic generate embedded position independent code\n\
14544 -EB generate big endian output\n\
14545 -EL generate little endian output\n\
14546 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14547 -G NUM allow referencing objects up to NUM bytes\n\
14548 implicitly with the gp register [default 8]\n"));
14549 fprintf (stream
, _("\
14550 -mips1 generate MIPS ISA I instructions\n\
14551 -mips2 generate MIPS ISA II instructions\n\
14552 -mips3 generate MIPS ISA III instructions\n\
14553 -mips4 generate MIPS ISA IV instructions\n\
14554 -mips5 generate MIPS ISA V instructions\n\
14555 -mips32 generate MIPS32 ISA instructions\n\
14556 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14557 -mips64 generate MIPS64 ISA instructions\n\
14558 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14562 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14563 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14564 show (stream
, "from-abi", &column
, &first
);
14565 fputc ('\n', stream
);
14567 fprintf (stream
, _("\
14568 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14569 -no-mCPU don't generate code specific to CPU.\n\
14570 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14574 show (stream
, "3900", &column
, &first
);
14575 show (stream
, "4010", &column
, &first
);
14576 show (stream
, "4100", &column
, &first
);
14577 show (stream
, "4650", &column
, &first
);
14578 fputc ('\n', stream
);
14580 fprintf (stream
, _("\
14581 -mips16 generate mips16 instructions\n\
14582 -no-mips16 do not generate mips16 instructions\n"));
14583 fprintf (stream
, _("\
14584 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14585 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14586 -O0 remove unneeded NOPs, do not swap branches\n\
14587 -O remove unneeded NOPs and swap branches\n\
14588 -n warn about NOPs generated from macros\n\
14589 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14590 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14591 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14593 fprintf (stream
, _("\
14594 -KPIC, -call_shared generate SVR4 position independent code\n\
14595 -non_shared do not generate position independent code\n\
14596 -xgot assume a 32 bit GOT\n\
14597 -mabi=ABI create ABI conformant object file for:\n"));
14601 show (stream
, "32", &column
, &first
);
14602 show (stream
, "o64", &column
, &first
);
14603 show (stream
, "n32", &column
, &first
);
14604 show (stream
, "64", &column
, &first
);
14605 show (stream
, "eabi", &column
, &first
);
14607 fputc ('\n', stream
);
14609 fprintf (stream
, _("\
14610 -32 create o32 ABI object file (default)\n\
14611 -n32 create n32 ABI object file\n\
14612 -64 create 64 ABI object file\n"));
14617 mips_dwarf2_format ()
14619 if (mips_abi
== N64_ABI
)
14622 return dwarf2_format_64bit_irix
;
14624 return dwarf2_format_64bit
;
14628 return dwarf2_format_32bit
;