1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode
*insn_mo
;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p
: 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p
: 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi
= NO_ABI
;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls
= FALSE
;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared
= TRUE
;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros
;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float
;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float
;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32
= -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32
= -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float
= 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float
= 0;
275 static struct mips_set_options mips_opts
=
277 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
278 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
279 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
280 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
281 /* soft_float */ FALSE
, /* single_float */ FALSE
284 /* The set of ASEs that were selected on the command line, either
285 explicitly via ASE options or implicitly through things like -march. */
286 static unsigned int file_ase
;
288 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
289 static unsigned int file_ase_explicit
;
291 /* These variables are filled in with the masks of registers used.
292 The object format code reads them and puts them in the appropriate
294 unsigned long mips_gprmask
;
295 unsigned long mips_cprmask
[4];
297 /* MIPS ISA we are using for this output file. */
298 static int file_mips_isa
= ISA_UNKNOWN
;
300 /* True if any MIPS16 code was produced. */
301 static int file_ase_mips16
;
303 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
304 || mips_opts.isa == ISA_MIPS32R2 \
305 || mips_opts.isa == ISA_MIPS64 \
306 || mips_opts.isa == ISA_MIPS64R2)
308 /* True if any microMIPS code was produced. */
309 static int file_ase_micromips
;
311 /* True if we want to create R_MIPS_JALR for jalr $25. */
313 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
315 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
316 because there's no place for any addend, the only acceptable
317 expression is a bare symbol. */
318 #define MIPS_JALR_HINT_P(EXPR) \
319 (!HAVE_IN_PLACE_ADDENDS \
320 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
323 /* The argument of the -march= flag. The architecture we are assembling. */
324 static int file_mips_arch
= CPU_UNKNOWN
;
325 static const char *mips_arch_string
;
327 /* The argument of the -mtune= flag. The architecture for which we
329 static int mips_tune
= CPU_UNKNOWN
;
330 static const char *mips_tune_string
;
332 /* True when generating 32-bit code for a 64-bit processor. */
333 static int mips_32bitmode
= 0;
335 /* True if the given ABI requires 32-bit registers. */
336 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
338 /* Likewise 64-bit registers. */
339 #define ABI_NEEDS_64BIT_REGS(ABI) \
341 || (ABI) == N64_ABI \
344 /* Return true if ISA supports 64 bit wide gp registers. */
345 #define ISA_HAS_64BIT_REGS(ISA) \
346 ((ISA) == ISA_MIPS3 \
347 || (ISA) == ISA_MIPS4 \
348 || (ISA) == ISA_MIPS5 \
349 || (ISA) == ISA_MIPS64 \
350 || (ISA) == ISA_MIPS64R2)
352 /* Return true if ISA supports 64 bit wide float registers. */
353 #define ISA_HAS_64BIT_FPRS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS32R2 \
358 || (ISA) == ISA_MIPS64 \
359 || (ISA) == ISA_MIPS64R2)
361 /* Return true if ISA supports 64-bit right rotate (dror et al.)
363 #define ISA_HAS_DROR(ISA) \
364 ((ISA) == ISA_MIPS64R2 \
365 || (mips_opts.micromips \
366 && ISA_HAS_64BIT_REGS (ISA)) \
369 /* Return true if ISA supports 32-bit right rotate (ror et al.)
371 #define ISA_HAS_ROR(ISA) \
372 ((ISA) == ISA_MIPS32R2 \
373 || (ISA) == ISA_MIPS64R2 \
374 || (mips_opts.ase & ASE_SMARTMIPS) \
375 || mips_opts.micromips \
378 /* Return true if ISA supports single-precision floats in odd registers. */
379 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
380 ((ISA) == ISA_MIPS32 \
381 || (ISA) == ISA_MIPS32R2 \
382 || (ISA) == ISA_MIPS64 \
383 || (ISA) == ISA_MIPS64R2)
385 /* Return true if ISA supports move to/from high part of a 64-bit
386 floating-point register. */
387 #define ISA_HAS_MXHC1(ISA) \
388 ((ISA) == ISA_MIPS32R2 \
389 || (ISA) == ISA_MIPS64R2)
391 #define HAVE_32BIT_GPRS \
392 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
394 #define HAVE_32BIT_FPRS \
395 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
397 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
398 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
400 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
402 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
404 /* True if relocations are stored in-place. */
405 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
407 /* The ABI-derived address size. */
408 #define HAVE_64BIT_ADDRESSES \
409 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
410 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
412 /* The size of symbolic constants (i.e., expressions of the form
413 "SYMBOL" or "SYMBOL + OFFSET"). */
414 #define HAVE_32BIT_SYMBOLS \
415 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
416 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
418 /* Addresses are loaded in different ways, depending on the address size
419 in use. The n32 ABI Documentation also mandates the use of additions
420 with overflow checking, but existing implementations don't follow it. */
421 #define ADDRESS_ADD_INSN \
422 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
424 #define ADDRESS_ADDI_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
427 #define ADDRESS_LOAD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
430 #define ADDRESS_STORE_INSN \
431 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
433 /* Return true if the given CPU supports the MIPS16 ASE. */
434 #define CPU_HAS_MIPS16(cpu) \
435 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
436 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
438 /* Return true if the given CPU supports the microMIPS ASE. */
439 #define CPU_HAS_MICROMIPS(cpu) 0
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU is in the Octeon family */
448 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
450 /* True if CPU has seq/sne and seqi/snei instructions. */
451 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
453 /* True, if CPU has support for ldc1 and sdc1. */
454 #define CPU_HAS_LDC1_SDC1(CPU) \
455 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
457 /* True if mflo and mfhi can be immediately followed by instructions
458 which write to the HI and LO registers.
460 According to MIPS specifications, MIPS ISAs I, II, and III need
461 (at least) two instructions between the reads of HI/LO and
462 instructions which write them, and later ISAs do not. Contradicting
463 the MIPS specifications, some MIPS IV processor user manuals (e.g.
464 the UM for the NEC Vr5000) document needing the instructions between
465 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
466 MIPS64 and later ISAs to have the interlocks, plus any specific
467 earlier-ISA CPUs for which CPU documentation declares that the
468 instructions are really interlocked. */
469 #define hilo_interlocks \
470 (mips_opts.isa == ISA_MIPS32 \
471 || mips_opts.isa == ISA_MIPS32R2 \
472 || mips_opts.isa == ISA_MIPS64 \
473 || mips_opts.isa == ISA_MIPS64R2 \
474 || mips_opts.arch == CPU_R4010 \
475 || mips_opts.arch == CPU_R5900 \
476 || mips_opts.arch == CPU_R10000 \
477 || mips_opts.arch == CPU_R12000 \
478 || mips_opts.arch == CPU_R14000 \
479 || mips_opts.arch == CPU_R16000 \
480 || mips_opts.arch == CPU_RM7000 \
481 || mips_opts.arch == CPU_VR5500 \
482 || mips_opts.micromips \
485 /* Whether the processor uses hardware interlocks to protect reads
486 from the GPRs after they are loaded from memory, and thus does not
487 require nops to be inserted. This applies to instructions marked
488 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
489 level I and microMIPS mode instructions are always interlocked. */
490 #define gpr_interlocks \
491 (mips_opts.isa != ISA_MIPS1 \
492 || mips_opts.arch == CPU_R3900 \
493 || mips_opts.arch == CPU_R5900 \
494 || mips_opts.micromips \
497 /* Whether the processor uses hardware interlocks to avoid delays
498 required by coprocessor instructions, and thus does not require
499 nops to be inserted. This applies to instructions marked
500 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
501 between instructions marked INSN_WRITE_COND_CODE and ones marked
502 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
503 levels I, II, and III and microMIPS mode instructions are always
505 /* Itbl support may require additional care here. */
506 #define cop_interlocks \
507 ((mips_opts.isa != ISA_MIPS1 \
508 && mips_opts.isa != ISA_MIPS2 \
509 && mips_opts.isa != ISA_MIPS3) \
510 || mips_opts.arch == CPU_R4300 \
511 || mips_opts.micromips \
514 /* Whether the processor uses hardware interlocks to protect reads
515 from coprocessor registers after they are loaded from memory, and
516 thus does not require nops to be inserted. This applies to
517 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
518 requires at MIPS ISA level I and microMIPS mode instructions are
519 always interlocked. */
520 #define cop_mem_interlocks \
521 (mips_opts.isa != ISA_MIPS1 \
522 || mips_opts.micromips \
525 /* Is this a mfhi or mflo instruction? */
526 #define MF_HILO_INSN(PINFO) \
527 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
529 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
530 has been selected. This implies, in particular, that addresses of text
531 labels have their LSB set. */
532 #define HAVE_CODE_COMPRESSION \
533 ((mips_opts.mips16 | mips_opts.micromips) != 0)
535 /* The minimum and maximum signed values that can be stored in a GPR. */
536 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
537 #define GPR_SMIN (-GPR_SMAX - 1)
539 /* MIPS PIC level. */
541 enum mips_pic_level mips_pic
;
543 /* 1 if we should generate 32 bit offsets from the $gp register in
544 SVR4_PIC mode. Currently has no meaning in other modes. */
545 static int mips_big_got
= 0;
547 /* 1 if trap instructions should used for overflow rather than break
549 static int mips_trap
= 0;
551 /* 1 if double width floating point constants should not be constructed
552 by assembling two single width halves into two single width floating
553 point registers which just happen to alias the double width destination
554 register. On some architectures this aliasing can be disabled by a bit
555 in the status register, and the setting of this bit cannot be determined
556 automatically at assemble time. */
557 static int mips_disable_float_construction
;
559 /* Non-zero if any .set noreorder directives were used. */
561 static int mips_any_noreorder
;
563 /* Non-zero if nops should be inserted when the register referenced in
564 an mfhi/mflo instruction is read in the next two instructions. */
565 static int mips_7000_hilo_fix
;
567 /* The size of objects in the small data section. */
568 static unsigned int g_switch_value
= 8;
569 /* Whether the -G option was used. */
570 static int g_switch_seen
= 0;
575 /* If we can determine in advance that GP optimization won't be
576 possible, we can skip the relaxation stuff that tries to produce
577 GP-relative references. This makes delay slot optimization work
580 This function can only provide a guess, but it seems to work for
581 gcc output. It needs to guess right for gcc, otherwise gcc
582 will put what it thinks is a GP-relative instruction in a branch
585 I don't know if a fix is needed for the SVR4_PIC mode. I've only
586 fixed it for the non-PIC mode. KR 95/04/07 */
587 static int nopic_need_relax (symbolS
*, int);
589 /* handle of the OPCODE hash table */
590 static struct hash_control
*op_hash
= NULL
;
592 /* The opcode hash table we use for the mips16. */
593 static struct hash_control
*mips16_op_hash
= NULL
;
595 /* The opcode hash table we use for the microMIPS ASE. */
596 static struct hash_control
*micromips_op_hash
= NULL
;
598 /* This array holds the chars that always start a comment. If the
599 pre-processor is disabled, these aren't very useful */
600 const char comment_chars
[] = "#";
602 /* This array holds the chars that only start a comment at the beginning of
603 a line. If the line seems to have the form '# 123 filename'
604 .line and .file directives will appear in the pre-processed output */
605 /* Note that input_file.c hand checks for '#' at the beginning of the
606 first line of the input file. This is because the compiler outputs
607 #NO_APP at the beginning of its output. */
608 /* Also note that C style comments are always supported. */
609 const char line_comment_chars
[] = "#";
611 /* This array holds machine specific line separator characters. */
612 const char line_separator_chars
[] = ";";
614 /* Chars that can be used to separate mant from exp in floating point nums */
615 const char EXP_CHARS
[] = "eE";
617 /* Chars that mean this number is a floating point constant */
620 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
622 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
623 changed in read.c . Ideally it shouldn't have to know about it at all,
624 but nothing is ideal around here.
627 static char *insn_error
;
629 static int auto_align
= 1;
631 /* When outputting SVR4 PIC code, the assembler needs to know the
632 offset in the stack frame from which to restore the $gp register.
633 This is set by the .cprestore pseudo-op, and saved in this
635 static offsetT mips_cprestore_offset
= -1;
637 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
638 more optimizations, it can use a register value instead of a memory-saved
639 offset and even an other register than $gp as global pointer. */
640 static offsetT mips_cpreturn_offset
= -1;
641 static int mips_cpreturn_register
= -1;
642 static int mips_gp_register
= GP
;
643 static int mips_gprel_offset
= 0;
645 /* Whether mips_cprestore_offset has been set in the current function
646 (or whether it has already been warned about, if not). */
647 static int mips_cprestore_valid
= 0;
649 /* This is the register which holds the stack frame, as set by the
650 .frame pseudo-op. This is needed to implement .cprestore. */
651 static int mips_frame_reg
= SP
;
653 /* Whether mips_frame_reg has been set in the current function
654 (or whether it has already been warned about, if not). */
655 static int mips_frame_reg_valid
= 0;
657 /* To output NOP instructions correctly, we need to keep information
658 about the previous two instructions. */
660 /* Whether we are optimizing. The default value of 2 means to remove
661 unneeded NOPs and swap branch instructions when possible. A value
662 of 1 means to not swap branches. A value of 0 means to always
664 static int mips_optimize
= 2;
666 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
667 equivalent to seeing no -g option at all. */
668 static int mips_debug
= 0;
670 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
671 #define MAX_VR4130_NOPS 4
673 /* The maximum number of NOPs needed to fill delay slots. */
674 #define MAX_DELAY_NOPS 2
676 /* The maximum number of NOPs needed for any purpose. */
679 /* A list of previous instructions, with index 0 being the most recent.
680 We need to look back MAX_NOPS instructions when filling delay slots
681 or working around processor errata. We need to look back one
682 instruction further if we're thinking about using history[0] to
683 fill a branch delay slot. */
684 static struct mips_cl_insn history
[1 + MAX_NOPS
];
686 /* Nop instructions used by emit_nop. */
687 static struct mips_cl_insn nop_insn
;
688 static struct mips_cl_insn mips16_nop_insn
;
689 static struct mips_cl_insn micromips_nop16_insn
;
690 static struct mips_cl_insn micromips_nop32_insn
;
692 /* The appropriate nop for the current mode. */
693 #define NOP_INSN (mips_opts.mips16 \
695 : (mips_opts.micromips \
696 ? (mips_opts.insn32 \
697 ? µmips_nop32_insn \
698 : µmips_nop16_insn) \
701 /* The size of NOP_INSN in bytes. */
702 #define NOP_INSN_SIZE ((mips_opts.mips16 \
703 || (mips_opts.micromips && !mips_opts.insn32)) \
706 /* If this is set, it points to a frag holding nop instructions which
707 were inserted before the start of a noreorder section. If those
708 nops turn out to be unnecessary, the size of the frag can be
710 static fragS
*prev_nop_frag
;
712 /* The number of nop instructions we created in prev_nop_frag. */
713 static int prev_nop_frag_holds
;
715 /* The number of nop instructions that we know we need in
717 static int prev_nop_frag_required
;
719 /* The number of instructions we've seen since prev_nop_frag. */
720 static int prev_nop_frag_since
;
722 /* Relocations against symbols are sometimes done in two parts, with a HI
723 relocation and a LO relocation. Each relocation has only 16 bits of
724 space to store an addend. This means that in order for the linker to
725 handle carries correctly, it must be able to locate both the HI and
726 the LO relocation. This means that the relocations must appear in
727 order in the relocation table.
729 In order to implement this, we keep track of each unmatched HI
730 relocation. We then sort them so that they immediately precede the
731 corresponding LO relocation. */
736 struct mips_hi_fixup
*next
;
739 /* The section this fixup is in. */
743 /* The list of unmatched HI relocs. */
745 static struct mips_hi_fixup
*mips_hi_fixup_list
;
747 /* The frag containing the last explicit relocation operator.
748 Null if explicit relocations have not been used. */
750 static fragS
*prev_reloc_op_frag
;
752 /* Map normal MIPS register numbers to mips16 register numbers. */
754 #define X ILLEGAL_REG
755 static const int mips32_to_16_reg_map
[] =
757 X
, X
, 2, 3, 4, 5, 6, 7,
758 X
, X
, X
, X
, X
, X
, X
, X
,
759 0, 1, X
, X
, X
, X
, X
, X
,
760 X
, X
, X
, X
, X
, X
, X
, X
764 /* Map mips16 register numbers to normal MIPS register numbers. */
766 static const unsigned int mips16_to_32_reg_map
[] =
768 16, 17, 2, 3, 4, 5, 6, 7
771 /* Map normal MIPS register numbers to microMIPS register numbers. */
773 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
774 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
775 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
776 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
781 #define X ILLEGAL_REG
782 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
783 static const int mips32_to_micromips_reg_m_map
[] =
785 0, X
, 2, 3, X
, X
, X
, X
,
786 X
, X
, X
, X
, X
, X
, X
, X
,
787 4, 1, 5, 6, 7, X
, X
, X
,
788 X
, X
, X
, X
, X
, X
, X
, X
791 /* reg type q: 0, 2-7. 17. */
792 static const int mips32_to_micromips_reg_q_map
[] =
794 0, X
, 2, 3, 4, 5, 6, 7,
795 X
, X
, X
, X
, X
, X
, X
, X
,
796 X
, 1, X
, X
, X
, X
, X
, X
,
797 X
, X
, X
, X
, X
, X
, X
, X
800 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
803 /* Map microMIPS register numbers to normal MIPS register numbers. */
805 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
806 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
807 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
808 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
809 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
810 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
812 /* The microMIPS registers with type h. */
813 static const unsigned int micromips_to_32_reg_h_map1
[] =
815 5, 5, 6, 4, 4, 4, 4, 4
817 static const unsigned int micromips_to_32_reg_h_map2
[] =
819 6, 7, 7, 21, 22, 5, 6, 7
822 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map
[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* The microMIPS registers with type q. */
833 static const unsigned int micromips_to_32_reg_q_map
[] =
835 0, 17, 2, 3, 4, 5, 6, 7
838 /* microMIPS imm type B. */
839 static const int micromips_imm_b_map
[] =
841 1, 4, 8, 12, 16, 20, 24, -1
844 /* microMIPS imm type C. */
845 static const int micromips_imm_c_map
[] =
847 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
850 /* Classifies the kind of instructions we're interested in when
851 implementing -mfix-vr4120. */
852 enum fix_vr4120_class
860 NUM_FIX_VR4120_CLASSES
863 /* ...likewise -mfix-loongson2f-jump. */
864 static bfd_boolean mips_fix_loongson2f_jump
;
866 /* ...likewise -mfix-loongson2f-nop. */
867 static bfd_boolean mips_fix_loongson2f_nop
;
869 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
870 static bfd_boolean mips_fix_loongson2f
;
872 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
873 there must be at least one other instruction between an instruction
874 of type X and an instruction of type Y. */
875 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
877 /* True if -mfix-vr4120 is in force. */
878 static int mips_fix_vr4120
;
880 /* ...likewise -mfix-vr4130. */
881 static int mips_fix_vr4130
;
883 /* ...likewise -mfix-24k. */
884 static int mips_fix_24k
;
886 /* ...likewise -mfix-cn63xxp1 */
887 static bfd_boolean mips_fix_cn63xxp1
;
889 /* We don't relax branches by default, since this causes us to expand
890 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
891 fail to compute the offset before expanding the macro to the most
892 efficient expansion. */
894 static int mips_relax_branch
;
896 /* The expansion of many macros depends on the type of symbol that
897 they refer to. For example, when generating position-dependent code,
898 a macro that refers to a symbol may have two different expansions,
899 one which uses GP-relative addresses and one which uses absolute
900 addresses. When generating SVR4-style PIC, a macro may have
901 different expansions for local and global symbols.
903 We handle these situations by generating both sequences and putting
904 them in variant frags. In position-dependent code, the first sequence
905 will be the GP-relative one and the second sequence will be the
906 absolute one. In SVR4 PIC, the first sequence will be for global
907 symbols and the second will be for local symbols.
909 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
910 SECOND are the lengths of the two sequences in bytes. These fields
911 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
912 the subtype has the following flags:
915 Set if it has been decided that we should use the second
916 sequence instead of the first.
919 Set in the first variant frag if the macro's second implementation
920 is longer than its first. This refers to the macro as a whole,
921 not an individual relaxation.
924 Set in the first variant frag if the macro appeared in a .set nomacro
925 block and if one alternative requires a warning but the other does not.
928 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
931 RELAX_DELAY_SLOT_16BIT
932 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
935 RELAX_DELAY_SLOT_SIZE_FIRST
936 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
937 the macro is of the wrong size for the branch delay slot.
939 RELAX_DELAY_SLOT_SIZE_SECOND
940 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
941 the macro is of the wrong size for the branch delay slot.
943 The frag's "opcode" points to the first fixup for relaxable code.
945 Relaxable macros are generated using a sequence such as:
947 relax_start (SYMBOL);
948 ... generate first expansion ...
950 ... generate second expansion ...
953 The code and fixups for the unwanted alternative are discarded
954 by md_convert_frag. */
955 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
957 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
958 #define RELAX_SECOND(X) ((X) & 0xff)
959 #define RELAX_USE_SECOND 0x10000
960 #define RELAX_SECOND_LONGER 0x20000
961 #define RELAX_NOMACRO 0x40000
962 #define RELAX_DELAY_SLOT 0x80000
963 #define RELAX_DELAY_SLOT_16BIT 0x100000
964 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
965 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
967 /* Branch without likely bit. If label is out of range, we turn:
969 beq reg1, reg2, label
979 with the following opcode replacements:
986 bltzal <-> bgezal (with jal label instead of j label)
988 Even though keeping the delay slot instruction in the delay slot of
989 the branch would be more efficient, it would be very tricky to do
990 correctly, because we'd have to introduce a variable frag *after*
991 the delay slot instruction, and expand that instead. Let's do it
992 the easy way for now, even if the branch-not-taken case now costs
993 one additional instruction. Out-of-range branches are not supposed
994 to be common, anyway.
996 Branch likely. If label is out of range, we turn:
998 beql reg1, reg2, label
999 delay slot (annulled if branch not taken)
1008 delay slot (executed only if branch taken)
1011 It would be possible to generate a shorter sequence by losing the
1012 likely bit, generating something like:
1017 delay slot (executed only if branch taken)
1029 bltzall -> bgezal (with jal label instead of j label)
1030 bgezall -> bltzal (ditto)
1033 but it's not clear that it would actually improve performance. */
1034 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1035 ((relax_substateT) \
1038 | ((toofar) ? 0x20 : 0) \
1039 | ((link) ? 0x40 : 0) \
1040 | ((likely) ? 0x80 : 0) \
1041 | ((uncond) ? 0x100 : 0)))
1042 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1043 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1044 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1045 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1046 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1047 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1049 /* For mips16 code, we use an entirely different form of relaxation.
1050 mips16 supports two versions of most instructions which take
1051 immediate values: a small one which takes some small value, and a
1052 larger one which takes a 16 bit value. Since branches also follow
1053 this pattern, relaxing these values is required.
1055 We can assemble both mips16 and normal MIPS code in a single
1056 object. Therefore, we need to support this type of relaxation at
1057 the same time that we support the relaxation described above. We
1058 use the high bit of the subtype field to distinguish these cases.
1060 The information we store for this type of relaxation is the
1061 argument code found in the opcode file for this relocation, whether
1062 the user explicitly requested a small or extended form, and whether
1063 the relocation is in a jump or jal delay slot. That tells us the
1064 size of the value, and how it should be stored. We also store
1065 whether the fragment is considered to be extended or not. We also
1066 store whether this is known to be a branch to a different section,
1067 whether we have tried to relax this frag yet, and whether we have
1068 ever extended a PC relative fragment because of a shift count. */
1069 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1072 | ((small) ? 0x100 : 0) \
1073 | ((ext) ? 0x200 : 0) \
1074 | ((dslot) ? 0x400 : 0) \
1075 | ((jal_dslot) ? 0x800 : 0))
1076 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1077 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1078 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1079 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1080 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1081 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1082 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1083 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1084 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1085 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1086 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1087 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1089 /* For microMIPS code, we use relaxation similar to one we use for
1090 MIPS16 code. Some instructions that take immediate values support
1091 two encodings: a small one which takes some small value, and a
1092 larger one which takes a 16 bit value. As some branches also follow
1093 this pattern, relaxing these values is required.
1095 We can assemble both microMIPS and normal MIPS code in a single
1096 object. Therefore, we need to support this type of relaxation at
1097 the same time that we support the relaxation described above. We
1098 use one of the high bits of the subtype field to distinguish these
1101 The information we store for this type of relaxation is the argument
1102 code found in the opcode file for this relocation, the register
1103 selected as the assembler temporary, whether the branch is
1104 unconditional, whether it is compact, whether it stores the link
1105 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1106 branches to a sequence of instructions is enabled, and whether the
1107 displacement of a branch is too large to fit as an immediate argument
1108 of a 16-bit and a 32-bit branch, respectively. */
1109 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1110 relax32, toofar16, toofar32) \
1113 | (((at) & 0x1f) << 8) \
1114 | ((uncond) ? 0x2000 : 0) \
1115 | ((compact) ? 0x4000 : 0) \
1116 | ((link) ? 0x8000 : 0) \
1117 | ((relax32) ? 0x10000 : 0) \
1118 | ((toofar16) ? 0x20000 : 0) \
1119 | ((toofar32) ? 0x40000 : 0))
1120 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1121 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1123 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1124 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1125 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1126 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1128 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1129 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1130 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1131 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1135 /* Sign-extend 16-bit value X. */
1136 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1138 /* Is the given value a sign-extended 32-bit value? */
1139 #define IS_SEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1141 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1143 /* Is the given value a sign-extended 16-bit value? */
1144 #define IS_SEXT_16BIT_NUM(x) \
1145 (((x) &~ (offsetT) 0x7fff) == 0 \
1146 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1148 /* Is the given value a sign-extended 12-bit value? */
1149 #define IS_SEXT_12BIT_NUM(x) \
1150 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1152 /* Is the given value a sign-extended 9-bit value? */
1153 #define IS_SEXT_9BIT_NUM(x) \
1154 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1156 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1157 #define IS_ZEXT_32BIT_NUM(x) \
1158 (((x) &~ (offsetT) 0xffffffff) == 0 \
1159 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1161 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1162 VALUE << SHIFT. VALUE is evaluated exactly once. */
1163 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1164 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1165 | (((VALUE) & (MASK)) << (SHIFT)))
1167 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1169 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1170 (((STRUCT) >> (SHIFT)) & (MASK))
1172 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1173 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1175 include/opcode/mips.h specifies operand fields using the macros
1176 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1177 with "MIPS16OP" instead of "OP". */
1178 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1181 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1182 OP_MASK_##FIELD, OP_SH_##FIELD); \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1187 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1188 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1189 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1191 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1192 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1194 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1195 : EXTRACT_BITS ((INSN).insn_opcode, \
1196 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1197 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1198 EXTRACT_BITS ((INSN).insn_opcode, \
1199 MIPS16OP_MASK_##FIELD, \
1200 MIPS16OP_SH_##FIELD)
1202 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1203 #define MIPS16_EXTEND (0xf000U << 16)
1205 /* Whether or not we are emitting a branch-likely macro. */
1206 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1208 /* Global variables used when generating relaxable macros. See the
1209 comment above RELAX_ENCODE for more details about how relaxation
1212 /* 0 if we're not emitting a relaxable macro.
1213 1 if we're emitting the first of the two relaxation alternatives.
1214 2 if we're emitting the second alternative. */
1217 /* The first relaxable fixup in the current frag. (In other words,
1218 the first fixup that refers to relaxable code.) */
1221 /* sizes[0] says how many bytes of the first alternative are stored in
1222 the current frag. Likewise sizes[1] for the second alternative. */
1223 unsigned int sizes
[2];
1225 /* The symbol on which the choice of sequence depends. */
1229 /* Global variables used to decide whether a macro needs a warning. */
1231 /* True if the macro is in a branch delay slot. */
1232 bfd_boolean delay_slot_p
;
1234 /* Set to the length in bytes required if the macro is in a delay slot
1235 that requires a specific length of instruction, otherwise zero. */
1236 unsigned int delay_slot_length
;
1238 /* For relaxable macros, sizes[0] is the length of the first alternative
1239 in bytes and sizes[1] is the length of the second alternative.
1240 For non-relaxable macros, both elements give the length of the
1242 unsigned int sizes
[2];
1244 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1245 instruction of the first alternative in bytes and first_insn_sizes[1]
1246 is the length of the first instruction of the second alternative.
1247 For non-relaxable macros, both elements give the length of the first
1248 instruction in bytes.
1250 Set to zero if we haven't yet seen the first instruction. */
1251 unsigned int first_insn_sizes
[2];
1253 /* For relaxable macros, insns[0] is the number of instructions for the
1254 first alternative and insns[1] is the number of instructions for the
1257 For non-relaxable macros, both elements give the number of
1258 instructions for the macro. */
1259 unsigned int insns
[2];
1261 /* The first variant frag for this macro. */
1263 } mips_macro_warning
;
1265 /* Prototypes for static functions. */
1267 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1269 static void append_insn
1270 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1271 bfd_boolean expansionp
);
1272 static void mips_no_prev_insn (void);
1273 static void macro_build (expressionS
*, const char *, const char *, ...);
1274 static void mips16_macro_build
1275 (expressionS
*, const char *, const char *, va_list *);
1276 static void load_register (int, expressionS
*, int);
1277 static void macro_start (void);
1278 static void macro_end (void);
1279 static void macro (struct mips_cl_insn
*ip
, char *str
);
1280 static void mips16_macro (struct mips_cl_insn
* ip
);
1281 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1282 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1283 static void mips16_immed
1284 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1285 unsigned int, unsigned long *);
1286 static size_t my_getSmallExpression
1287 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1288 static void my_getExpression (expressionS
*, char *);
1289 static void s_align (int);
1290 static void s_change_sec (int);
1291 static void s_change_section (int);
1292 static void s_cons (int);
1293 static void s_float_cons (int);
1294 static void s_mips_globl (int);
1295 static void s_option (int);
1296 static void s_mipsset (int);
1297 static void s_abicalls (int);
1298 static void s_cpload (int);
1299 static void s_cpsetup (int);
1300 static void s_cplocal (int);
1301 static void s_cprestore (int);
1302 static void s_cpreturn (int);
1303 static void s_dtprelword (int);
1304 static void s_dtpreldword (int);
1305 static void s_tprelword (int);
1306 static void s_tpreldword (int);
1307 static void s_gpvalue (int);
1308 static void s_gpword (int);
1309 static void s_gpdword (int);
1310 static void s_ehword (int);
1311 static void s_cpadd (int);
1312 static void s_insn (int);
1313 static void md_obj_begin (void);
1314 static void md_obj_end (void);
1315 static void s_mips_ent (int);
1316 static void s_mips_end (int);
1317 static void s_mips_frame (int);
1318 static void s_mips_mask (int reg_type
);
1319 static void s_mips_stab (int);
1320 static void s_mips_weakext (int);
1321 static void s_mips_file (int);
1322 static void s_mips_loc (int);
1323 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1324 static int relaxed_branch_length (fragS
*, asection
*, int);
1325 static int validate_mips_insn (const struct mips_opcode
*);
1326 static int validate_micromips_insn (const struct mips_opcode
*);
1327 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1328 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1330 /* Table and functions used to map between CPU/ISA names, and
1331 ISA levels, and CPU numbers. */
1333 struct mips_cpu_info
1335 const char *name
; /* CPU or ISA name. */
1336 int flags
; /* MIPS_CPU_* flags. */
1337 int ase
; /* Set of ASEs implemented by the CPU. */
1338 int isa
; /* ISA level. */
1339 int cpu
; /* CPU number (default CPU if ISA). */
1342 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1344 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1345 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1346 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1348 /* Command-line options. */
1349 const char *md_shortopts
= "O::g::G:";
1353 OPTION_MARCH
= OPTION_MD_BASE
,
1377 OPTION_NO_SMARTMIPS
,
1383 OPTION_NO_MICROMIPS
,
1386 OPTION_COMPAT_ARCH_BASE
,
1395 OPTION_M7000_HILO_FIX
,
1396 OPTION_MNO_7000_HILO_FIX
,
1399 OPTION_FIX_LOONGSON2F_JUMP
,
1400 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1401 OPTION_FIX_LOONGSON2F_NOP
,
1402 OPTION_NO_FIX_LOONGSON2F_NOP
,
1404 OPTION_NO_FIX_VR4120
,
1406 OPTION_NO_FIX_VR4130
,
1407 OPTION_FIX_CN63XXP1
,
1408 OPTION_NO_FIX_CN63XXP1
,
1415 OPTION_CONSTRUCT_FLOATS
,
1416 OPTION_NO_CONSTRUCT_FLOATS
,
1419 OPTION_RELAX_BRANCH
,
1420 OPTION_NO_RELAX_BRANCH
,
1429 OPTION_SINGLE_FLOAT
,
1430 OPTION_DOUBLE_FLOAT
,
1443 OPTION_MVXWORKS_PIC
,
1447 struct option md_longopts
[] =
1449 /* Options which specify architecture. */
1450 {"march", required_argument
, NULL
, OPTION_MARCH
},
1451 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1452 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1453 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1454 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1455 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1456 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1457 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1458 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1459 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1460 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1461 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1463 /* Options which specify Application Specific Extensions (ASEs). */
1464 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1465 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1466 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1467 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1468 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1469 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1470 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1471 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1472 {"mmt", no_argument
, NULL
, OPTION_MT
},
1473 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1474 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1475 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1476 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1477 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1478 {"meva", no_argument
, NULL
, OPTION_EVA
},
1479 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1480 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1481 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1482 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1483 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1484 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1485 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1487 /* Old-style architecture options. Don't add more of these. */
1488 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1489 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1490 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1491 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1492 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1493 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1494 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1495 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1497 /* Options which enable bug fixes. */
1498 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1499 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1500 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1501 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1502 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1503 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1504 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1505 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1506 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1507 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1508 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1509 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1510 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1511 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1512 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1514 /* Miscellaneous options. */
1515 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1516 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1517 {"break", no_argument
, NULL
, OPTION_BREAK
},
1518 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1519 {"EB", no_argument
, NULL
, OPTION_EB
},
1520 {"EL", no_argument
, NULL
, OPTION_EL
},
1521 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1522 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1523 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1524 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1525 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1526 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1527 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1528 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1529 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1530 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1531 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1532 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1533 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1534 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1535 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1536 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1537 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1538 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1540 /* Strictly speaking this next option is ELF specific,
1541 but we allow it for other ports as well in order to
1542 make testing easier. */
1543 {"32", no_argument
, NULL
, OPTION_32
},
1545 /* ELF-specific options. */
1546 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1547 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1548 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1549 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1550 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1551 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1552 {"n32", no_argument
, NULL
, OPTION_N32
},
1553 {"64", no_argument
, NULL
, OPTION_64
},
1554 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1555 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1556 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1557 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1558 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1560 {NULL
, no_argument
, NULL
, 0}
1562 size_t md_longopts_size
= sizeof (md_longopts
);
1564 /* Information about either an Application Specific Extension or an
1565 optional architecture feature that, for simplicity, we treat in the
1566 same way as an ASE. */
1569 /* The name of the ASE, used in both the command-line and .set options. */
1572 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1573 and 64-bit architectures, the flags here refer to the subset that
1574 is available on both. */
1577 /* The ASE_* flag used for instructions that are available on 64-bit
1578 architectures but that are not included in FLAGS. */
1579 unsigned int flags64
;
1581 /* The command-line options that turn the ASE on and off. */
1585 /* The minimum required architecture revisions for MIPS32, MIPS64,
1586 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1589 int micromips32_rev
;
1590 int micromips64_rev
;
1593 /* A table of all supported ASEs. */
1594 static const struct mips_ase mips_ases
[] = {
1595 { "dsp", ASE_DSP
, ASE_DSP64
,
1596 OPTION_DSP
, OPTION_NO_DSP
,
1599 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1600 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1603 { "eva", ASE_EVA
, 0,
1604 OPTION_EVA
, OPTION_NO_EVA
,
1607 { "mcu", ASE_MCU
, 0,
1608 OPTION_MCU
, OPTION_NO_MCU
,
1611 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1612 { "mdmx", ASE_MDMX
, 0,
1613 OPTION_MDMX
, OPTION_NO_MDMX
,
1616 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1617 { "mips3d", ASE_MIPS3D
, 0,
1618 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1622 OPTION_MT
, OPTION_NO_MT
,
1625 { "smartmips", ASE_SMARTMIPS
, 0,
1626 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1629 { "virt", ASE_VIRT
, ASE_VIRT64
,
1630 OPTION_VIRT
, OPTION_NO_VIRT
,
1634 /* The set of ASEs that require -mfp64. */
1635 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1637 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1638 static const unsigned int mips_ase_groups
[] = {
1644 The following pseudo-ops from the Kane and Heinrich MIPS book
1645 should be defined here, but are currently unsupported: .alias,
1646 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1648 The following pseudo-ops from the Kane and Heinrich MIPS book are
1649 specific to the type of debugging information being generated, and
1650 should be defined by the object format: .aent, .begin, .bend,
1651 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1654 The following pseudo-ops from the Kane and Heinrich MIPS book are
1655 not MIPS CPU specific, but are also not specific to the object file
1656 format. This file is probably the best place to define them, but
1657 they are not currently supported: .asm0, .endr, .lab, .struct. */
1659 static const pseudo_typeS mips_pseudo_table
[] =
1661 /* MIPS specific pseudo-ops. */
1662 {"option", s_option
, 0},
1663 {"set", s_mipsset
, 0},
1664 {"rdata", s_change_sec
, 'r'},
1665 {"sdata", s_change_sec
, 's'},
1666 {"livereg", s_ignore
, 0},
1667 {"abicalls", s_abicalls
, 0},
1668 {"cpload", s_cpload
, 0},
1669 {"cpsetup", s_cpsetup
, 0},
1670 {"cplocal", s_cplocal
, 0},
1671 {"cprestore", s_cprestore
, 0},
1672 {"cpreturn", s_cpreturn
, 0},
1673 {"dtprelword", s_dtprelword
, 0},
1674 {"dtpreldword", s_dtpreldword
, 0},
1675 {"tprelword", s_tprelword
, 0},
1676 {"tpreldword", s_tpreldword
, 0},
1677 {"gpvalue", s_gpvalue
, 0},
1678 {"gpword", s_gpword
, 0},
1679 {"gpdword", s_gpdword
, 0},
1680 {"ehword", s_ehword
, 0},
1681 {"cpadd", s_cpadd
, 0},
1682 {"insn", s_insn
, 0},
1684 /* Relatively generic pseudo-ops that happen to be used on MIPS
1686 {"asciiz", stringer
, 8 + 1},
1687 {"bss", s_change_sec
, 'b'},
1689 {"half", s_cons
, 1},
1690 {"dword", s_cons
, 3},
1691 {"weakext", s_mips_weakext
, 0},
1692 {"origin", s_org
, 0},
1693 {"repeat", s_rept
, 0},
1695 /* For MIPS this is non-standard, but we define it for consistency. */
1696 {"sbss", s_change_sec
, 'B'},
1698 /* These pseudo-ops are defined in read.c, but must be overridden
1699 here for one reason or another. */
1700 {"align", s_align
, 0},
1701 {"byte", s_cons
, 0},
1702 {"data", s_change_sec
, 'd'},
1703 {"double", s_float_cons
, 'd'},
1704 {"float", s_float_cons
, 'f'},
1705 {"globl", s_mips_globl
, 0},
1706 {"global", s_mips_globl
, 0},
1707 {"hword", s_cons
, 1},
1709 {"long", s_cons
, 2},
1710 {"octa", s_cons
, 4},
1711 {"quad", s_cons
, 3},
1712 {"section", s_change_section
, 0},
1713 {"short", s_cons
, 1},
1714 {"single", s_float_cons
, 'f'},
1715 {"stabd", s_mips_stab
, 'd'},
1716 {"stabn", s_mips_stab
, 'n'},
1717 {"stabs", s_mips_stab
, 's'},
1718 {"text", s_change_sec
, 't'},
1719 {"word", s_cons
, 2},
1721 { "extern", ecoff_directive_extern
, 0},
1726 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1728 /* These pseudo-ops should be defined by the object file format.
1729 However, a.out doesn't support them, so we have versions here. */
1730 {"aent", s_mips_ent
, 1},
1731 {"bgnb", s_ignore
, 0},
1732 {"end", s_mips_end
, 0},
1733 {"endb", s_ignore
, 0},
1734 {"ent", s_mips_ent
, 0},
1735 {"file", s_mips_file
, 0},
1736 {"fmask", s_mips_mask
, 'F'},
1737 {"frame", s_mips_frame
, 0},
1738 {"loc", s_mips_loc
, 0},
1739 {"mask", s_mips_mask
, 'R'},
1740 {"verstamp", s_ignore
, 0},
1744 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1745 purpose of the `.dc.a' internal pseudo-op. */
1748 mips_address_bytes (void)
1750 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1753 extern void pop_insert (const pseudo_typeS
*);
1756 mips_pop_insert (void)
1758 pop_insert (mips_pseudo_table
);
1759 if (! ECOFF_DEBUGGING
)
1760 pop_insert (mips_nonecoff_pseudo_table
);
1763 /* Symbols labelling the current insn. */
1765 struct insn_label_list
1767 struct insn_label_list
*next
;
1771 static struct insn_label_list
*free_insn_labels
;
1772 #define label_list tc_segment_info_data.labels
1774 static void mips_clear_insn_labels (void);
1775 static void mips_mark_labels (void);
1776 static void mips_compressed_mark_labels (void);
1779 mips_clear_insn_labels (void)
1781 register struct insn_label_list
**pl
;
1782 segment_info_type
*si
;
1786 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1789 si
= seg_info (now_seg
);
1790 *pl
= si
->label_list
;
1791 si
->label_list
= NULL
;
1795 /* Mark instruction labels in MIPS16/microMIPS mode. */
1798 mips_mark_labels (void)
1800 if (HAVE_CODE_COMPRESSION
)
1801 mips_compressed_mark_labels ();
1804 static char *expr_end
;
1806 /* Expressions which appear in instructions. These are set by
1809 static expressionS imm_expr
;
1810 static expressionS imm2_expr
;
1811 static expressionS offset_expr
;
1813 /* Relocs associated with imm_expr and offset_expr. */
1815 static bfd_reloc_code_real_type imm_reloc
[3]
1816 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1817 static bfd_reloc_code_real_type offset_reloc
[3]
1818 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1820 /* This is set to the resulting size of the instruction to be produced
1821 by mips16_ip if an explicit extension is used or by mips_ip if an
1822 explicit size is supplied. */
1824 static unsigned int forced_insn_length
;
1826 /* True if we are assembling an instruction. All dot symbols defined during
1827 this time should be treated as code labels. */
1829 static bfd_boolean mips_assembling_insn
;
1831 /* The pdr segment for per procedure frame/regmask info. Not used for
1834 static segT pdr_seg
;
1836 /* The default target format to use. */
1838 #if defined (TE_FreeBSD)
1839 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1840 #elif defined (TE_TMIPS)
1841 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1843 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1847 mips_target_format (void)
1849 switch (OUTPUT_FLAVOR
)
1851 case bfd_target_elf_flavour
:
1853 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1854 return (target_big_endian
1855 ? "elf32-bigmips-vxworks"
1856 : "elf32-littlemips-vxworks");
1858 return (target_big_endian
1859 ? (HAVE_64BIT_OBJECTS
1860 ? ELF_TARGET ("elf64-", "big")
1862 ? ELF_TARGET ("elf32-n", "big")
1863 : ELF_TARGET ("elf32-", "big")))
1864 : (HAVE_64BIT_OBJECTS
1865 ? ELF_TARGET ("elf64-", "little")
1867 ? ELF_TARGET ("elf32-n", "little")
1868 : ELF_TARGET ("elf32-", "little"))));
1875 /* Return the ISA revision that is currently in use, or 0 if we are
1876 generating code for MIPS V or below. */
1881 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1884 /* microMIPS implies revision 2 or above. */
1885 if (mips_opts
.micromips
)
1888 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1894 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1897 mips_ase_mask (unsigned int flags
)
1901 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1902 if (flags
& mips_ase_groups
[i
])
1903 flags
|= mips_ase_groups
[i
];
1907 /* Check whether the current ISA supports ASE. Issue a warning if
1911 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1915 static unsigned int warned_isa
;
1916 static unsigned int warned_fp32
;
1918 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1919 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1921 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1922 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1923 && (warned_isa
& ase
->flags
) != ase
->flags
)
1925 warned_isa
|= ase
->flags
;
1926 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1927 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1929 as_warn (_("The %d-bit %s architecture does not support the"
1930 " `%s' extension"), size
, base
, ase
->name
);
1932 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1933 ase
->name
, base
, size
, min_rev
);
1935 if ((ase
->flags
& FP64_ASES
)
1937 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1939 warned_fp32
|= ase
->flags
;
1940 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1944 /* Check all enabled ASEs to see whether they are supported by the
1945 chosen architecture. */
1948 mips_check_isa_supports_ases (void)
1950 unsigned int i
, mask
;
1952 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1954 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1955 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1956 mips_check_isa_supports_ase (&mips_ases
[i
]);
1960 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1961 that were affected. */
1964 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1968 mask
= mips_ase_mask (ase
->flags
);
1969 mips_opts
.ase
&= ~mask
;
1971 mips_opts
.ase
|= ase
->flags
;
1975 /* Return the ASE called NAME, or null if none. */
1977 static const struct mips_ase
*
1978 mips_lookup_ase (const char *name
)
1982 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1983 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1984 return &mips_ases
[i
];
1988 /* Return the length of a microMIPS instruction in bytes. If bits of
1989 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1990 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1991 major opcode) will require further modifications to the opcode
1994 static inline unsigned int
1995 micromips_insn_length (const struct mips_opcode
*mo
)
1997 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2000 /* Return the length of MIPS16 instruction OPCODE. */
2002 static inline unsigned int
2003 mips16_opcode_length (unsigned long opcode
)
2005 return (opcode
>> 16) == 0 ? 2 : 4;
2008 /* Return the length of instruction INSN. */
2010 static inline unsigned int
2011 insn_length (const struct mips_cl_insn
*insn
)
2013 if (mips_opts
.micromips
)
2014 return micromips_insn_length (insn
->insn_mo
);
2015 else if (mips_opts
.mips16
)
2016 return mips16_opcode_length (insn
->insn_opcode
);
2021 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2024 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2029 insn
->insn_opcode
= mo
->match
;
2032 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2033 insn
->fixp
[i
] = NULL
;
2034 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2035 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2036 insn
->mips16_absolute_jump_p
= 0;
2037 insn
->complete_p
= 0;
2038 insn
->cleared_p
= 0;
2041 /* Record the current MIPS16/microMIPS mode in now_seg. */
2044 mips_record_compressed_mode (void)
2046 segment_info_type
*si
;
2048 si
= seg_info (now_seg
);
2049 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2050 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2051 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2052 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2055 /* Read a standard MIPS instruction from BUF. */
2057 static unsigned long
2058 read_insn (char *buf
)
2060 if (target_big_endian
)
2061 return bfd_getb32 ((bfd_byte
*) buf
);
2063 return bfd_getl32 ((bfd_byte
*) buf
);
2066 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2070 write_insn (char *buf
, unsigned int insn
)
2072 md_number_to_chars (buf
, insn
, 4);
2076 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2077 has length LENGTH. */
2079 static unsigned long
2080 read_compressed_insn (char *buf
, unsigned int length
)
2086 for (i
= 0; i
< length
; i
+= 2)
2089 if (target_big_endian
)
2090 insn
|= bfd_getb16 ((char *) buf
);
2092 insn
|= bfd_getl16 ((char *) buf
);
2098 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2099 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2102 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2106 for (i
= 0; i
< length
; i
+= 2)
2107 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2108 return buf
+ length
;
2111 /* Install INSN at the location specified by its "frag" and "where" fields. */
2114 install_insn (const struct mips_cl_insn
*insn
)
2116 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2117 if (HAVE_CODE_COMPRESSION
)
2118 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2120 write_insn (f
, insn
->insn_opcode
);
2121 mips_record_compressed_mode ();
2124 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2125 and install the opcode in the new location. */
2128 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2133 insn
->where
= where
;
2134 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2135 if (insn
->fixp
[i
] != NULL
)
2137 insn
->fixp
[i
]->fx_frag
= frag
;
2138 insn
->fixp
[i
]->fx_where
= where
;
2140 install_insn (insn
);
2143 /* Add INSN to the end of the output. */
2146 add_fixed_insn (struct mips_cl_insn
*insn
)
2148 char *f
= frag_more (insn_length (insn
));
2149 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2152 /* Start a variant frag and move INSN to the start of the variant part,
2153 marking it as fixed. The other arguments are as for frag_var. */
2156 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2157 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2159 frag_grow (max_chars
);
2160 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2162 frag_var (rs_machine_dependent
, max_chars
, var
,
2163 subtype
, symbol
, offset
, NULL
);
2166 /* Insert N copies of INSN into the history buffer, starting at
2167 position FIRST. Neither FIRST nor N need to be clipped. */
2170 insert_into_history (unsigned int first
, unsigned int n
,
2171 const struct mips_cl_insn
*insn
)
2173 if (mips_relax
.sequence
!= 2)
2177 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2179 history
[i
] = history
[i
- n
];
2185 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2186 the idea is to make it obvious at a glance that each errata is
2190 init_vr4120_conflicts (void)
2192 #define CONFLICT(FIRST, SECOND) \
2193 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2195 /* Errata 21 - [D]DIV[U] after [D]MACC */
2196 CONFLICT (MACC
, DIV
);
2197 CONFLICT (DMACC
, DIV
);
2199 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2200 CONFLICT (DMULT
, DMULT
);
2201 CONFLICT (DMULT
, DMACC
);
2202 CONFLICT (DMACC
, DMULT
);
2203 CONFLICT (DMACC
, DMACC
);
2205 /* Errata 24 - MT{LO,HI} after [D]MACC */
2206 CONFLICT (MACC
, MTHILO
);
2207 CONFLICT (DMACC
, MTHILO
);
2209 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2210 instruction is executed immediately after a MACC or DMACC
2211 instruction, the result of [either instruction] is incorrect." */
2212 CONFLICT (MACC
, MULT
);
2213 CONFLICT (MACC
, DMULT
);
2214 CONFLICT (DMACC
, MULT
);
2215 CONFLICT (DMACC
, DMULT
);
2217 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2218 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2219 DDIV or DDIVU instruction, the result of the MACC or
2220 DMACC instruction is incorrect.". */
2221 CONFLICT (DMULT
, MACC
);
2222 CONFLICT (DMULT
, DMACC
);
2223 CONFLICT (DIV
, MACC
);
2224 CONFLICT (DIV
, DMACC
);
2234 #define RTYPE_MASK 0x1ff00
2235 #define RTYPE_NUM 0x00100
2236 #define RTYPE_FPU 0x00200
2237 #define RTYPE_FCC 0x00400
2238 #define RTYPE_VEC 0x00800
2239 #define RTYPE_GP 0x01000
2240 #define RTYPE_CP0 0x02000
2241 #define RTYPE_PC 0x04000
2242 #define RTYPE_ACC 0x08000
2243 #define RTYPE_CCC 0x10000
2244 #define RNUM_MASK 0x000ff
2245 #define RWARN 0x80000
2247 #define GENERIC_REGISTER_NUMBERS \
2248 {"$0", RTYPE_NUM | 0}, \
2249 {"$1", RTYPE_NUM | 1}, \
2250 {"$2", RTYPE_NUM | 2}, \
2251 {"$3", RTYPE_NUM | 3}, \
2252 {"$4", RTYPE_NUM | 4}, \
2253 {"$5", RTYPE_NUM | 5}, \
2254 {"$6", RTYPE_NUM | 6}, \
2255 {"$7", RTYPE_NUM | 7}, \
2256 {"$8", RTYPE_NUM | 8}, \
2257 {"$9", RTYPE_NUM | 9}, \
2258 {"$10", RTYPE_NUM | 10}, \
2259 {"$11", RTYPE_NUM | 11}, \
2260 {"$12", RTYPE_NUM | 12}, \
2261 {"$13", RTYPE_NUM | 13}, \
2262 {"$14", RTYPE_NUM | 14}, \
2263 {"$15", RTYPE_NUM | 15}, \
2264 {"$16", RTYPE_NUM | 16}, \
2265 {"$17", RTYPE_NUM | 17}, \
2266 {"$18", RTYPE_NUM | 18}, \
2267 {"$19", RTYPE_NUM | 19}, \
2268 {"$20", RTYPE_NUM | 20}, \
2269 {"$21", RTYPE_NUM | 21}, \
2270 {"$22", RTYPE_NUM | 22}, \
2271 {"$23", RTYPE_NUM | 23}, \
2272 {"$24", RTYPE_NUM | 24}, \
2273 {"$25", RTYPE_NUM | 25}, \
2274 {"$26", RTYPE_NUM | 26}, \
2275 {"$27", RTYPE_NUM | 27}, \
2276 {"$28", RTYPE_NUM | 28}, \
2277 {"$29", RTYPE_NUM | 29}, \
2278 {"$30", RTYPE_NUM | 30}, \
2279 {"$31", RTYPE_NUM | 31}
2281 #define FPU_REGISTER_NAMES \
2282 {"$f0", RTYPE_FPU | 0}, \
2283 {"$f1", RTYPE_FPU | 1}, \
2284 {"$f2", RTYPE_FPU | 2}, \
2285 {"$f3", RTYPE_FPU | 3}, \
2286 {"$f4", RTYPE_FPU | 4}, \
2287 {"$f5", RTYPE_FPU | 5}, \
2288 {"$f6", RTYPE_FPU | 6}, \
2289 {"$f7", RTYPE_FPU | 7}, \
2290 {"$f8", RTYPE_FPU | 8}, \
2291 {"$f9", RTYPE_FPU | 9}, \
2292 {"$f10", RTYPE_FPU | 10}, \
2293 {"$f11", RTYPE_FPU | 11}, \
2294 {"$f12", RTYPE_FPU | 12}, \
2295 {"$f13", RTYPE_FPU | 13}, \
2296 {"$f14", RTYPE_FPU | 14}, \
2297 {"$f15", RTYPE_FPU | 15}, \
2298 {"$f16", RTYPE_FPU | 16}, \
2299 {"$f17", RTYPE_FPU | 17}, \
2300 {"$f18", RTYPE_FPU | 18}, \
2301 {"$f19", RTYPE_FPU | 19}, \
2302 {"$f20", RTYPE_FPU | 20}, \
2303 {"$f21", RTYPE_FPU | 21}, \
2304 {"$f22", RTYPE_FPU | 22}, \
2305 {"$f23", RTYPE_FPU | 23}, \
2306 {"$f24", RTYPE_FPU | 24}, \
2307 {"$f25", RTYPE_FPU | 25}, \
2308 {"$f26", RTYPE_FPU | 26}, \
2309 {"$f27", RTYPE_FPU | 27}, \
2310 {"$f28", RTYPE_FPU | 28}, \
2311 {"$f29", RTYPE_FPU | 29}, \
2312 {"$f30", RTYPE_FPU | 30}, \
2313 {"$f31", RTYPE_FPU | 31}
2315 #define FPU_CONDITION_CODE_NAMES \
2316 {"$fcc0", RTYPE_FCC | 0}, \
2317 {"$fcc1", RTYPE_FCC | 1}, \
2318 {"$fcc2", RTYPE_FCC | 2}, \
2319 {"$fcc3", RTYPE_FCC | 3}, \
2320 {"$fcc4", RTYPE_FCC | 4}, \
2321 {"$fcc5", RTYPE_FCC | 5}, \
2322 {"$fcc6", RTYPE_FCC | 6}, \
2323 {"$fcc7", RTYPE_FCC | 7}
2325 #define COPROC_CONDITION_CODE_NAMES \
2326 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2327 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2328 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2329 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2330 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2331 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2332 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2333 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2335 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2336 {"$a4", RTYPE_GP | 8}, \
2337 {"$a5", RTYPE_GP | 9}, \
2338 {"$a6", RTYPE_GP | 10}, \
2339 {"$a7", RTYPE_GP | 11}, \
2340 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2341 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2342 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2343 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2344 {"$t0", RTYPE_GP | 12}, \
2345 {"$t1", RTYPE_GP | 13}, \
2346 {"$t2", RTYPE_GP | 14}, \
2347 {"$t3", RTYPE_GP | 15}
2349 #define O32_SYMBOLIC_REGISTER_NAMES \
2350 {"$t0", RTYPE_GP | 8}, \
2351 {"$t1", RTYPE_GP | 9}, \
2352 {"$t2", RTYPE_GP | 10}, \
2353 {"$t3", RTYPE_GP | 11}, \
2354 {"$t4", RTYPE_GP | 12}, \
2355 {"$t5", RTYPE_GP | 13}, \
2356 {"$t6", RTYPE_GP | 14}, \
2357 {"$t7", RTYPE_GP | 15}, \
2358 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2359 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2360 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2361 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2363 /* Remaining symbolic register names */
2364 #define SYMBOLIC_REGISTER_NAMES \
2365 {"$zero", RTYPE_GP | 0}, \
2366 {"$at", RTYPE_GP | 1}, \
2367 {"$AT", RTYPE_GP | 1}, \
2368 {"$v0", RTYPE_GP | 2}, \
2369 {"$v1", RTYPE_GP | 3}, \
2370 {"$a0", RTYPE_GP | 4}, \
2371 {"$a1", RTYPE_GP | 5}, \
2372 {"$a2", RTYPE_GP | 6}, \
2373 {"$a3", RTYPE_GP | 7}, \
2374 {"$s0", RTYPE_GP | 16}, \
2375 {"$s1", RTYPE_GP | 17}, \
2376 {"$s2", RTYPE_GP | 18}, \
2377 {"$s3", RTYPE_GP | 19}, \
2378 {"$s4", RTYPE_GP | 20}, \
2379 {"$s5", RTYPE_GP | 21}, \
2380 {"$s6", RTYPE_GP | 22}, \
2381 {"$s7", RTYPE_GP | 23}, \
2382 {"$t8", RTYPE_GP | 24}, \
2383 {"$t9", RTYPE_GP | 25}, \
2384 {"$k0", RTYPE_GP | 26}, \
2385 {"$kt0", RTYPE_GP | 26}, \
2386 {"$k1", RTYPE_GP | 27}, \
2387 {"$kt1", RTYPE_GP | 27}, \
2388 {"$gp", RTYPE_GP | 28}, \
2389 {"$sp", RTYPE_GP | 29}, \
2390 {"$s8", RTYPE_GP | 30}, \
2391 {"$fp", RTYPE_GP | 30}, \
2392 {"$ra", RTYPE_GP | 31}
2394 #define MIPS16_SPECIAL_REGISTER_NAMES \
2395 {"$pc", RTYPE_PC | 0}
2397 #define MDMX_VECTOR_REGISTER_NAMES \
2398 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2399 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2400 {"$v2", RTYPE_VEC | 2}, \
2401 {"$v3", RTYPE_VEC | 3}, \
2402 {"$v4", RTYPE_VEC | 4}, \
2403 {"$v5", RTYPE_VEC | 5}, \
2404 {"$v6", RTYPE_VEC | 6}, \
2405 {"$v7", RTYPE_VEC | 7}, \
2406 {"$v8", RTYPE_VEC | 8}, \
2407 {"$v9", RTYPE_VEC | 9}, \
2408 {"$v10", RTYPE_VEC | 10}, \
2409 {"$v11", RTYPE_VEC | 11}, \
2410 {"$v12", RTYPE_VEC | 12}, \
2411 {"$v13", RTYPE_VEC | 13}, \
2412 {"$v14", RTYPE_VEC | 14}, \
2413 {"$v15", RTYPE_VEC | 15}, \
2414 {"$v16", RTYPE_VEC | 16}, \
2415 {"$v17", RTYPE_VEC | 17}, \
2416 {"$v18", RTYPE_VEC | 18}, \
2417 {"$v19", RTYPE_VEC | 19}, \
2418 {"$v20", RTYPE_VEC | 20}, \
2419 {"$v21", RTYPE_VEC | 21}, \
2420 {"$v22", RTYPE_VEC | 22}, \
2421 {"$v23", RTYPE_VEC | 23}, \
2422 {"$v24", RTYPE_VEC | 24}, \
2423 {"$v25", RTYPE_VEC | 25}, \
2424 {"$v26", RTYPE_VEC | 26}, \
2425 {"$v27", RTYPE_VEC | 27}, \
2426 {"$v28", RTYPE_VEC | 28}, \
2427 {"$v29", RTYPE_VEC | 29}, \
2428 {"$v30", RTYPE_VEC | 30}, \
2429 {"$v31", RTYPE_VEC | 31}
2431 #define MIPS_DSP_ACCUMULATOR_NAMES \
2432 {"$ac0", RTYPE_ACC | 0}, \
2433 {"$ac1", RTYPE_ACC | 1}, \
2434 {"$ac2", RTYPE_ACC | 2}, \
2435 {"$ac3", RTYPE_ACC | 3}
2437 static const struct regname reg_names
[] = {
2438 GENERIC_REGISTER_NUMBERS
,
2440 FPU_CONDITION_CODE_NAMES
,
2441 COPROC_CONDITION_CODE_NAMES
,
2443 /* The $txx registers depends on the abi,
2444 these will be added later into the symbol table from
2445 one of the tables below once mips_abi is set after
2446 parsing of arguments from the command line. */
2447 SYMBOLIC_REGISTER_NAMES
,
2449 MIPS16_SPECIAL_REGISTER_NAMES
,
2450 MDMX_VECTOR_REGISTER_NAMES
,
2451 MIPS_DSP_ACCUMULATOR_NAMES
,
2455 static const struct regname reg_names_o32
[] = {
2456 O32_SYMBOLIC_REGISTER_NAMES
,
2460 static const struct regname reg_names_n32n64
[] = {
2461 N32N64_SYMBOLIC_REGISTER_NAMES
,
2465 /* Check if S points at a valid register specifier according to TYPES.
2466 If so, then return 1, advance S to consume the specifier and store
2467 the register's number in REGNOP, otherwise return 0. */
2470 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2477 /* Find end of name. */
2479 if (is_name_beginner (*e
))
2481 while (is_part_of_name (*e
))
2484 /* Terminate name. */
2488 /* Look for a register symbol. */
2489 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2491 int r
= S_GET_VALUE (symbolP
);
2493 reg
= r
& RNUM_MASK
;
2494 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2495 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2496 reg
= (r
& RNUM_MASK
) - 2;
2498 /* Else see if this is a register defined in an itbl entry. */
2499 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2506 if (itbl_get_reg_val (n
, &r
))
2507 reg
= r
& RNUM_MASK
;
2510 /* Advance to next token if a register was recognised. */
2513 else if (types
& RWARN
)
2514 as_warn (_("Unrecognized register name `%s'"), *s
);
2522 /* Check if S points at a valid register list according to TYPES.
2523 If so, then return 1, advance S to consume the list and store
2524 the registers present on the list as a bitmask of ones in REGLISTP,
2525 otherwise return 0. A valid list comprises a comma-separated
2526 enumeration of valid single registers and/or dash-separated
2527 contiguous register ranges as determined by their numbers.
2529 As a special exception if one of s0-s7 registers is specified as
2530 the range's lower delimiter and s8 (fp) is its upper one, then no
2531 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2532 are selected; they have to be listed separately if needed. */
2535 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2537 unsigned int reglist
= 0;
2538 unsigned int lastregno
;
2539 bfd_boolean ok
= TRUE
;
2540 unsigned int regmask
;
2541 char *s_endlist
= *s
;
2545 while (reg_lookup (s
, types
, ®no
))
2551 ok
= reg_lookup (s
, types
, &lastregno
);
2552 if (ok
&& lastregno
< regno
)
2558 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2563 regmask
= 1 << lastregno
;
2564 regmask
= (regmask
<< 1) - 1;
2565 regmask
^= (1 << regno
) - 1;
2579 *reglistp
= reglist
;
2580 return ok
&& reglist
!= 0;
2584 mips_lookup_reg_pair (unsigned int regno1
, unsigned int regno2
,
2585 const unsigned int *map1
, const unsigned int *map2
,
2590 for (i
= 0; i
< count
; i
++)
2591 if (map1
[i
] == regno1
&& map2
[i
] == regno2
)
2596 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2597 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2600 is_opcode_valid (const struct mips_opcode
*mo
)
2602 int isa
= mips_opts
.isa
;
2603 int ase
= mips_opts
.ase
;
2607 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2608 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2609 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2610 ase
|= mips_ases
[i
].flags64
;
2612 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2615 /* Check whether the instruction or macro requires single-precision or
2616 double-precision floating-point support. Note that this information is
2617 stored differently in the opcode table for insns and macros. */
2618 if (mo
->pinfo
== INSN_MACRO
)
2620 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2621 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2625 fp_s
= mo
->pinfo
& FP_S
;
2626 fp_d
= mo
->pinfo
& FP_D
;
2629 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2632 if (fp_s
&& mips_opts
.soft_float
)
2638 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2639 selected ISA and architecture. */
2642 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2644 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2647 /* Return TRUE if the size of the microMIPS opcode MO matches one
2648 explicitly requested. Always TRUE in the standard MIPS mode. */
2651 is_size_valid (const struct mips_opcode
*mo
)
2653 if (!mips_opts
.micromips
)
2656 if (mips_opts
.insn32
)
2658 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2660 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2663 if (!forced_insn_length
)
2665 if (mo
->pinfo
== INSN_MACRO
)
2667 return forced_insn_length
== micromips_insn_length (mo
);
2670 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2671 of the preceding instruction. Always TRUE in the standard MIPS mode.
2673 We don't accept macros in 16-bit delay slots to avoid a case where
2674 a macro expansion fails because it relies on a preceding 32-bit real
2675 instruction to have matched and does not handle the operands correctly.
2676 The only macros that may expand to 16-bit instructions are JAL that
2677 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2678 and BGT (that likewise cannot be placed in a delay slot) that decay to
2679 a NOP. In all these cases the macros precede any corresponding real
2680 instruction definitions in the opcode table, so they will match in the
2681 second pass where the size of the delay slot is ignored and therefore
2682 produce correct code. */
2685 is_delay_slot_valid (const struct mips_opcode
*mo
)
2687 if (!mips_opts
.micromips
)
2690 if (mo
->pinfo
== INSN_MACRO
)
2691 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2692 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2693 && micromips_insn_length (mo
) != 4)
2695 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2696 && micromips_insn_length (mo
) != 2)
2702 /* This function is called once, at assembler startup time. It should set up
2703 all the tables, etc. that the MD part of the assembler will need. */
2708 const char *retval
= NULL
;
2712 if (mips_pic
!= NO_PIC
)
2714 if (g_switch_seen
&& g_switch_value
!= 0)
2715 as_bad (_("-G may not be used in position-independent code"));
2719 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2720 as_warn (_("Could not set architecture and machine"));
2722 op_hash
= hash_new ();
2724 for (i
= 0; i
< NUMOPCODES
;)
2726 const char *name
= mips_opcodes
[i
].name
;
2728 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2731 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2732 mips_opcodes
[i
].name
, retval
);
2733 /* Probably a memory allocation problem? Give up now. */
2734 as_fatal (_("Broken assembler. No assembly attempted."));
2738 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2740 if (!validate_mips_insn (&mips_opcodes
[i
]))
2742 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2744 create_insn (&nop_insn
, mips_opcodes
+ i
);
2745 if (mips_fix_loongson2f_nop
)
2746 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2747 nop_insn
.fixed_p
= 1;
2752 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2755 mips16_op_hash
= hash_new ();
2758 while (i
< bfd_mips16_num_opcodes
)
2760 const char *name
= mips16_opcodes
[i
].name
;
2762 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2764 as_fatal (_("internal: can't hash `%s': %s"),
2765 mips16_opcodes
[i
].name
, retval
);
2768 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2769 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2770 != mips16_opcodes
[i
].match
))
2772 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2773 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2776 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2778 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2779 mips16_nop_insn
.fixed_p
= 1;
2783 while (i
< bfd_mips16_num_opcodes
2784 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2787 micromips_op_hash
= hash_new ();
2790 while (i
< bfd_micromips_num_opcodes
)
2792 const char *name
= micromips_opcodes
[i
].name
;
2794 retval
= hash_insert (micromips_op_hash
, name
,
2795 (void *) µmips_opcodes
[i
]);
2797 as_fatal (_("internal: can't hash `%s': %s"),
2798 micromips_opcodes
[i
].name
, retval
);
2800 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2802 struct mips_cl_insn
*micromips_nop_insn
;
2804 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2807 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2808 micromips_nop_insn
= µmips_nop16_insn
;
2809 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2810 micromips_nop_insn
= µmips_nop32_insn
;
2814 if (micromips_nop_insn
->insn_mo
== NULL
2815 && strcmp (name
, "nop") == 0)
2817 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2818 micromips_nop_insn
->fixed_p
= 1;
2821 while (++i
< bfd_micromips_num_opcodes
2822 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2826 as_fatal (_("Broken assembler. No assembly attempted."));
2828 /* We add all the general register names to the symbol table. This
2829 helps us detect invalid uses of them. */
2830 for (i
= 0; reg_names
[i
].name
; i
++)
2831 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2832 reg_names
[i
].num
, /* & RNUM_MASK, */
2833 &zero_address_frag
));
2835 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2836 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2837 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2838 &zero_address_frag
));
2840 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2841 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2842 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2843 &zero_address_frag
));
2845 mips_no_prev_insn ();
2848 mips_cprmask
[0] = 0;
2849 mips_cprmask
[1] = 0;
2850 mips_cprmask
[2] = 0;
2851 mips_cprmask
[3] = 0;
2853 /* set the default alignment for the text section (2**2) */
2854 record_alignment (text_section
, 2);
2856 bfd_set_gp_size (stdoutput
, g_switch_value
);
2858 /* On a native system other than VxWorks, sections must be aligned
2859 to 16 byte boundaries. When configured for an embedded ELF
2860 target, we don't bother. */
2861 if (strncmp (TARGET_OS
, "elf", 3) != 0
2862 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2864 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2865 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2866 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2869 /* Create a .reginfo section for register masks and a .mdebug
2870 section for debugging information. */
2878 subseg
= now_subseg
;
2880 /* The ABI says this section should be loaded so that the
2881 running program can access it. However, we don't load it
2882 if we are configured for an embedded target */
2883 flags
= SEC_READONLY
| SEC_DATA
;
2884 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2885 flags
|= SEC_ALLOC
| SEC_LOAD
;
2887 if (mips_abi
!= N64_ABI
)
2889 sec
= subseg_new (".reginfo", (subsegT
) 0);
2891 bfd_set_section_flags (stdoutput
, sec
, flags
);
2892 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2894 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2898 /* The 64-bit ABI uses a .MIPS.options section rather than
2899 .reginfo section. */
2900 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2901 bfd_set_section_flags (stdoutput
, sec
, flags
);
2902 bfd_set_section_alignment (stdoutput
, sec
, 3);
2904 /* Set up the option header. */
2906 Elf_Internal_Options opthdr
;
2909 opthdr
.kind
= ODK_REGINFO
;
2910 opthdr
.size
= (sizeof (Elf_External_Options
)
2911 + sizeof (Elf64_External_RegInfo
));
2914 f
= frag_more (sizeof (Elf_External_Options
));
2915 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2916 (Elf_External_Options
*) f
);
2918 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2922 if (ECOFF_DEBUGGING
)
2924 sec
= subseg_new (".mdebug", (subsegT
) 0);
2925 (void) bfd_set_section_flags (stdoutput
, sec
,
2926 SEC_HAS_CONTENTS
| SEC_READONLY
);
2927 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2929 else if (mips_flag_pdr
)
2931 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2932 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2933 SEC_READONLY
| SEC_RELOC
2935 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2938 subseg_set (seg
, subseg
);
2941 if (! ECOFF_DEBUGGING
)
2944 if (mips_fix_vr4120
)
2945 init_vr4120_conflicts ();
2951 mips_emit_delays ();
2952 if (! ECOFF_DEBUGGING
)
2957 md_assemble (char *str
)
2959 struct mips_cl_insn insn
;
2960 bfd_reloc_code_real_type unused_reloc
[3]
2961 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2963 imm_expr
.X_op
= O_absent
;
2964 imm2_expr
.X_op
= O_absent
;
2965 offset_expr
.X_op
= O_absent
;
2966 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2967 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2968 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2969 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2970 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2971 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2973 mips_mark_labels ();
2974 mips_assembling_insn
= TRUE
;
2976 if (mips_opts
.mips16
)
2977 mips16_ip (str
, &insn
);
2980 mips_ip (str
, &insn
);
2981 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2982 str
, insn
.insn_opcode
));
2986 as_bad ("%s `%s'", insn_error
, str
);
2987 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2990 if (mips_opts
.mips16
)
2991 mips16_macro (&insn
);
2998 if (imm_expr
.X_op
!= O_absent
)
2999 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
3000 else if (offset_expr
.X_op
!= O_absent
)
3001 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3003 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3006 mips_assembling_insn
= FALSE
;
3009 /* Convenience functions for abstracting away the differences between
3010 MIPS16 and non-MIPS16 relocations. */
3012 static inline bfd_boolean
3013 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3017 case BFD_RELOC_MIPS16_JMP
:
3018 case BFD_RELOC_MIPS16_GPREL
:
3019 case BFD_RELOC_MIPS16_GOT16
:
3020 case BFD_RELOC_MIPS16_CALL16
:
3021 case BFD_RELOC_MIPS16_HI16_S
:
3022 case BFD_RELOC_MIPS16_HI16
:
3023 case BFD_RELOC_MIPS16_LO16
:
3031 static inline bfd_boolean
3032 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3036 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3037 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3038 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3039 case BFD_RELOC_MICROMIPS_GPREL16
:
3040 case BFD_RELOC_MICROMIPS_JMP
:
3041 case BFD_RELOC_MICROMIPS_HI16
:
3042 case BFD_RELOC_MICROMIPS_HI16_S
:
3043 case BFD_RELOC_MICROMIPS_LO16
:
3044 case BFD_RELOC_MICROMIPS_LITERAL
:
3045 case BFD_RELOC_MICROMIPS_GOT16
:
3046 case BFD_RELOC_MICROMIPS_CALL16
:
3047 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3048 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3049 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3050 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3051 case BFD_RELOC_MICROMIPS_SUB
:
3052 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3053 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3054 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3055 case BFD_RELOC_MICROMIPS_HIGHEST
:
3056 case BFD_RELOC_MICROMIPS_HIGHER
:
3057 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3058 case BFD_RELOC_MICROMIPS_JALR
:
3066 static inline bfd_boolean
3067 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3069 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3072 static inline bfd_boolean
3073 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3075 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3076 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3079 static inline bfd_boolean
3080 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3082 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3083 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3086 static inline bfd_boolean
3087 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3089 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3090 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3093 static inline bfd_boolean
3094 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3096 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3099 /* Return true if RELOC is a PC-relative relocation that does not have
3100 full address range. */
3102 static inline bfd_boolean
3103 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3107 case BFD_RELOC_16_PCREL_S2
:
3108 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3109 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3110 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3113 case BFD_RELOC_32_PCREL
:
3114 return HAVE_64BIT_ADDRESSES
;
3121 /* Return true if the given relocation might need a matching %lo().
3122 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3123 need a matching %lo() when applied to local symbols. */
3125 static inline bfd_boolean
3126 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3128 return (HAVE_IN_PLACE_ADDENDS
3129 && (hi16_reloc_p (reloc
)
3130 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3131 all GOT16 relocations evaluate to "G". */
3132 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3135 /* Return the type of %lo() reloc needed by RELOC, given that
3136 reloc_needs_lo_p. */
3138 static inline bfd_reloc_code_real_type
3139 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3141 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3142 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3146 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3149 static inline bfd_boolean
3150 fixup_has_matching_lo_p (fixS
*fixp
)
3152 return (fixp
->fx_next
!= NULL
3153 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3154 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3155 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3158 /* This function returns true if modifying a register requires a
3162 reg_needs_delay (unsigned int reg
)
3164 unsigned long prev_pinfo
;
3166 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3167 if (! mips_opts
.noreorder
3168 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
3169 && ! gpr_interlocks
)
3170 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
3171 && ! cop_interlocks
)))
3173 /* A load from a coprocessor or from memory. All load delays
3174 delay the use of general register rt for one instruction. */
3175 /* Itbl support may require additional care here. */
3176 know (prev_pinfo
& INSN_WRITE_GPR_T
);
3177 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
3184 /* Move all labels in LABELS to the current insertion point. TEXT_P
3185 says whether the labels refer to text or data. */
3188 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3190 struct insn_label_list
*l
;
3193 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3195 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3196 symbol_set_frag (l
->label
, frag_now
);
3197 val
= (valueT
) frag_now_fix ();
3198 /* MIPS16/microMIPS text labels are stored as odd. */
3199 if (text_p
&& HAVE_CODE_COMPRESSION
)
3201 S_SET_VALUE (l
->label
, val
);
3205 /* Move all labels in insn_labels to the current insertion point
3206 and treat them as text labels. */
3209 mips_move_text_labels (void)
3211 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3215 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3217 bfd_boolean linkonce
= FALSE
;
3218 segT symseg
= S_GET_SEGMENT (sym
);
3220 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3222 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3224 /* The GNU toolchain uses an extension for ELF: a section
3225 beginning with the magic string .gnu.linkonce is a
3226 linkonce section. */
3227 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3228 sizeof ".gnu.linkonce" - 1) == 0)
3234 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3235 linker to handle them specially, such as generating jalx instructions
3236 when needed. We also make them odd for the duration of the assembly,
3237 in order to generate the right sort of code. We will make them even
3238 in the adjust_symtab routine, while leaving them marked. This is
3239 convenient for the debugger and the disassembler. The linker knows
3240 to make them odd again. */
3243 mips_compressed_mark_label (symbolS
*label
)
3245 gas_assert (HAVE_CODE_COMPRESSION
);
3247 if (mips_opts
.mips16
)
3248 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3250 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3251 if ((S_GET_VALUE (label
) & 1) == 0
3252 /* Don't adjust the address if the label is global or weak, or
3253 in a link-once section, since we'll be emitting symbol reloc
3254 references to it which will be patched up by the linker, and
3255 the final value of the symbol may or may not be MIPS16/microMIPS. */
3256 && !S_IS_WEAK (label
)
3257 && !S_IS_EXTERNAL (label
)
3258 && !s_is_linkonce (label
, now_seg
))
3259 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3262 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3265 mips_compressed_mark_labels (void)
3267 struct insn_label_list
*l
;
3269 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3270 mips_compressed_mark_label (l
->label
);
3273 /* End the current frag. Make it a variant frag and record the
3277 relax_close_frag (void)
3279 mips_macro_warning
.first_frag
= frag_now
;
3280 frag_var (rs_machine_dependent
, 0, 0,
3281 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3282 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3284 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3285 mips_relax
.first_fixup
= 0;
3288 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3289 See the comment above RELAX_ENCODE for more details. */
3292 relax_start (symbolS
*symbol
)
3294 gas_assert (mips_relax
.sequence
== 0);
3295 mips_relax
.sequence
= 1;
3296 mips_relax
.symbol
= symbol
;
3299 /* Start generating the second version of a relaxable sequence.
3300 See the comment above RELAX_ENCODE for more details. */
3305 gas_assert (mips_relax
.sequence
== 1);
3306 mips_relax
.sequence
= 2;
3309 /* End the current relaxable sequence. */
3314 gas_assert (mips_relax
.sequence
== 2);
3315 relax_close_frag ();
3316 mips_relax
.sequence
= 0;
3319 /* Return true if IP is a delayed branch or jump. */
3321 static inline bfd_boolean
3322 delayed_branch_p (const struct mips_cl_insn
*ip
)
3324 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3325 | INSN_COND_BRANCH_DELAY
3326 | INSN_COND_BRANCH_LIKELY
)) != 0;
3329 /* Return true if IP is a compact branch or jump. */
3331 static inline bfd_boolean
3332 compact_branch_p (const struct mips_cl_insn
*ip
)
3334 if (mips_opts
.mips16
)
3335 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3336 | MIPS16_INSN_COND_BRANCH
)) != 0;
3338 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3339 | INSN2_COND_BRANCH
)) != 0;
3342 /* Return true if IP is an unconditional branch or jump. */
3344 static inline bfd_boolean
3345 uncond_branch_p (const struct mips_cl_insn
*ip
)
3347 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3348 || (mips_opts
.mips16
3349 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3350 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3353 /* Return true if IP is a branch-likely instruction. */
3355 static inline bfd_boolean
3356 branch_likely_p (const struct mips_cl_insn
*ip
)
3358 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3361 /* Return the type of nop that should be used to fill the delay slot
3362 of delayed branch IP. */
3364 static struct mips_cl_insn
*
3365 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3367 if (mips_opts
.micromips
3368 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3369 return µmips_nop32_insn
;
3373 /* Return the mask of core registers that IP reads or writes. */
3376 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3378 unsigned long pinfo2
;
3382 pinfo2
= ip
->insn_mo
->pinfo2
;
3383 if (mips_opts
.micromips
)
3385 if (pinfo2
& INSN2_MOD_GPR_MD
)
3386 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3387 if (pinfo2
& INSN2_MOD_GPR_MF
)
3388 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3389 if (pinfo2
& INSN2_MOD_SP
)
3395 /* Return the mask of core registers that IP reads. */
3398 gpr_read_mask (const struct mips_cl_insn
*ip
)
3400 unsigned long pinfo
, pinfo2
;
3403 mask
= gpr_mod_mask (ip
);
3404 pinfo
= ip
->insn_mo
->pinfo
;
3405 pinfo2
= ip
->insn_mo
->pinfo2
;
3406 if (mips_opts
.mips16
)
3408 if (pinfo
& MIPS16_INSN_READ_X
)
3409 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3410 if (pinfo
& MIPS16_INSN_READ_Y
)
3411 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3412 if (pinfo
& MIPS16_INSN_READ_T
)
3414 if (pinfo
& MIPS16_INSN_READ_SP
)
3416 if (pinfo
& MIPS16_INSN_READ_31
)
3418 if (pinfo
& MIPS16_INSN_READ_Z
)
3419 mask
|= 1 << (mips16_to_32_reg_map
3420 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3421 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3422 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3426 if (pinfo2
& INSN2_READ_GPR_D
)
3427 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3428 if (pinfo
& INSN_READ_GPR_T
)
3429 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3430 if (pinfo
& INSN_READ_GPR_S
)
3431 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3432 if (pinfo2
& INSN2_READ_GP
)
3434 if (pinfo2
& INSN2_READ_GPR_31
)
3436 if (pinfo2
& INSN2_READ_GPR_Z
)
3437 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3439 if (mips_opts
.micromips
)
3441 if (pinfo2
& INSN2_READ_GPR_MC
)
3442 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3443 if (pinfo2
& INSN2_READ_GPR_ME
)
3444 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3445 if (pinfo2
& INSN2_READ_GPR_MG
)
3446 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3447 if (pinfo2
& INSN2_READ_GPR_MJ
)
3448 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3449 if (pinfo2
& INSN2_READ_GPR_MMN
)
3451 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3452 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3454 if (pinfo2
& INSN2_READ_GPR_MP
)
3455 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3456 if (pinfo2
& INSN2_READ_GPR_MQ
)
3457 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3459 /* Don't include register 0. */
3463 /* Return the mask of core registers that IP writes. */
3466 gpr_write_mask (const struct mips_cl_insn
*ip
)
3468 unsigned long pinfo
, pinfo2
;
3471 mask
= gpr_mod_mask (ip
);
3472 pinfo
= ip
->insn_mo
->pinfo
;
3473 pinfo2
= ip
->insn_mo
->pinfo2
;
3474 if (mips_opts
.mips16
)
3476 if (pinfo
& MIPS16_INSN_WRITE_X
)
3477 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3478 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3479 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3480 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3481 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3482 if (pinfo
& MIPS16_INSN_WRITE_T
)
3484 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3486 if (pinfo
& MIPS16_INSN_WRITE_31
)
3488 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3489 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3493 if (pinfo
& INSN_WRITE_GPR_D
)
3494 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3495 if (pinfo
& INSN_WRITE_GPR_T
)
3496 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3497 if (pinfo
& INSN_WRITE_GPR_S
)
3498 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3499 if (pinfo
& INSN_WRITE_GPR_31
)
3501 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3502 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3504 if (mips_opts
.micromips
)
3506 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3507 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3508 if (pinfo2
& INSN2_WRITE_GPR_MH
)
3510 mask
|= 1 << micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
3511 mask
|= 1 << micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
3513 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3514 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3515 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3516 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3518 /* Don't include register 0. */
3522 /* Return the mask of floating-point registers that IP reads. */
3525 fpr_read_mask (const struct mips_cl_insn
*ip
)
3527 unsigned long pinfo
, pinfo2
;
3531 pinfo
= ip
->insn_mo
->pinfo
;
3532 pinfo2
= ip
->insn_mo
->pinfo2
;
3533 if (!mips_opts
.mips16
)
3535 if (pinfo2
& INSN2_READ_FPR_D
)
3536 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3537 if (pinfo
& INSN_READ_FPR_S
)
3538 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3539 if (pinfo
& INSN_READ_FPR_T
)
3540 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3541 if (pinfo
& INSN_READ_FPR_R
)
3542 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3543 if (pinfo2
& INSN2_READ_FPR_Z
)
3544 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3546 /* Conservatively treat all operands to an FP_D instruction are doubles.
3547 (This is overly pessimistic for things like cvt.d.s.) */
3548 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3553 /* Return the mask of floating-point registers that IP writes. */
3556 fpr_write_mask (const struct mips_cl_insn
*ip
)
3558 unsigned long pinfo
, pinfo2
;
3562 pinfo
= ip
->insn_mo
->pinfo
;
3563 pinfo2
= ip
->insn_mo
->pinfo2
;
3564 if (!mips_opts
.mips16
)
3566 if (pinfo
& INSN_WRITE_FPR_D
)
3567 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3568 if (pinfo
& INSN_WRITE_FPR_S
)
3569 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3570 if (pinfo
& INSN_WRITE_FPR_T
)
3571 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3572 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3573 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3575 /* Conservatively treat all operands to an FP_D instruction are doubles.
3576 (This is overly pessimistic for things like cvt.s.d.) */
3577 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3582 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3583 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3584 by VR4120 errata. */
3587 classify_vr4120_insn (const char *name
)
3589 if (strncmp (name
, "macc", 4) == 0)
3590 return FIX_VR4120_MACC
;
3591 if (strncmp (name
, "dmacc", 5) == 0)
3592 return FIX_VR4120_DMACC
;
3593 if (strncmp (name
, "mult", 4) == 0)
3594 return FIX_VR4120_MULT
;
3595 if (strncmp (name
, "dmult", 5) == 0)
3596 return FIX_VR4120_DMULT
;
3597 if (strstr (name
, "div"))
3598 return FIX_VR4120_DIV
;
3599 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3600 return FIX_VR4120_MTHILO
;
3601 return NUM_FIX_VR4120_CLASSES
;
3604 #define INSN_ERET 0x42000018
3605 #define INSN_DERET 0x4200001f
3607 /* Return the number of instructions that must separate INSN1 and INSN2,
3608 where INSN1 is the earlier instruction. Return the worst-case value
3609 for any INSN2 if INSN2 is null. */
3612 insns_between (const struct mips_cl_insn
*insn1
,
3613 const struct mips_cl_insn
*insn2
)
3615 unsigned long pinfo1
, pinfo2
;
3618 /* This function needs to know which pinfo flags are set for INSN2
3619 and which registers INSN2 uses. The former is stored in PINFO2 and
3620 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3621 will have every flag set and INSN2_USES_GPR will always return true. */
3622 pinfo1
= insn1
->insn_mo
->pinfo
;
3623 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3625 #define INSN2_USES_GPR(REG) \
3626 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3628 /* For most targets, write-after-read dependencies on the HI and LO
3629 registers must be separated by at least two instructions. */
3630 if (!hilo_interlocks
)
3632 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3634 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3638 /* If we're working around r7000 errata, there must be two instructions
3639 between an mfhi or mflo and any instruction that uses the result. */
3640 if (mips_7000_hilo_fix
3641 && !mips_opts
.micromips
3642 && MF_HILO_INSN (pinfo1
)
3643 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3646 /* If we're working around 24K errata, one instruction is required
3647 if an ERET or DERET is followed by a branch instruction. */
3648 if (mips_fix_24k
&& !mips_opts
.micromips
)
3650 if (insn1
->insn_opcode
== INSN_ERET
3651 || insn1
->insn_opcode
== INSN_DERET
)
3654 || insn2
->insn_opcode
== INSN_ERET
3655 || insn2
->insn_opcode
== INSN_DERET
3656 || delayed_branch_p (insn2
))
3661 /* If working around VR4120 errata, check for combinations that need
3662 a single intervening instruction. */
3663 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3665 unsigned int class1
, class2
;
3667 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3668 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3672 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3673 if (vr4120_conflicts
[class1
] & (1 << class2
))
3678 if (!HAVE_CODE_COMPRESSION
)
3680 /* Check for GPR or coprocessor load delays. All such delays
3681 are on the RT register. */
3682 /* Itbl support may require additional care here. */
3683 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3684 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3686 know (pinfo1
& INSN_WRITE_GPR_T
);
3687 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3691 /* Check for generic coprocessor hazards.
3693 This case is not handled very well. There is no special
3694 knowledge of CP0 handling, and the coprocessors other than
3695 the floating point unit are not distinguished at all. */
3696 /* Itbl support may require additional care here. FIXME!
3697 Need to modify this to include knowledge about
3698 user specified delays! */
3699 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3700 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3702 /* Handle cases where INSN1 writes to a known general coprocessor
3703 register. There must be a one instruction delay before INSN2
3704 if INSN2 reads that register, otherwise no delay is needed. */
3705 mask
= fpr_write_mask (insn1
);
3708 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3713 /* Read-after-write dependencies on the control registers
3714 require a two-instruction gap. */
3715 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3716 && (pinfo2
& INSN_READ_COND_CODE
))
3719 /* We don't know exactly what INSN1 does. If INSN2 is
3720 also a coprocessor instruction, assume there must be
3721 a one instruction gap. */
3722 if (pinfo2
& INSN_COP
)
3727 /* Check for read-after-write dependencies on the coprocessor
3728 control registers in cases where INSN1 does not need a general
3729 coprocessor delay. This means that INSN1 is a floating point
3730 comparison instruction. */
3731 /* Itbl support may require additional care here. */
3732 else if (!cop_interlocks
3733 && (pinfo1
& INSN_WRITE_COND_CODE
)
3734 && (pinfo2
& INSN_READ_COND_CODE
))
3738 #undef INSN2_USES_GPR
3743 /* Return the number of nops that would be needed to work around the
3744 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3745 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3746 that are contained within the first IGNORE instructions of HIST. */
3749 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3750 const struct mips_cl_insn
*insn
)
3755 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3756 are not affected by the errata. */
3758 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3759 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3760 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3763 /* Search for the first MFLO or MFHI. */
3764 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3765 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3767 /* Extract the destination register. */
3768 mask
= gpr_write_mask (&hist
[i
]);
3770 /* No nops are needed if INSN reads that register. */
3771 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3774 /* ...or if any of the intervening instructions do. */
3775 for (j
= 0; j
< i
; j
++)
3776 if (gpr_read_mask (&hist
[j
]) & mask
)
3780 return MAX_VR4130_NOPS
- i
;
3785 #define BASE_REG_EQ(INSN1, INSN2) \
3786 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3787 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3789 /* Return the minimum alignment for this store instruction. */
3792 fix_24k_align_to (const struct mips_opcode
*mo
)
3794 if (strcmp (mo
->name
, "sh") == 0)
3797 if (strcmp (mo
->name
, "swc1") == 0
3798 || strcmp (mo
->name
, "swc2") == 0
3799 || strcmp (mo
->name
, "sw") == 0
3800 || strcmp (mo
->name
, "sc") == 0
3801 || strcmp (mo
->name
, "s.s") == 0)
3804 if (strcmp (mo
->name
, "sdc1") == 0
3805 || strcmp (mo
->name
, "sdc2") == 0
3806 || strcmp (mo
->name
, "s.d") == 0)
3813 struct fix_24k_store_info
3815 /* Immediate offset, if any, for this store instruction. */
3817 /* Alignment required by this store instruction. */
3819 /* True for register offsets. */
3820 int register_offset
;
3823 /* Comparison function used by qsort. */
3826 fix_24k_sort (const void *a
, const void *b
)
3828 const struct fix_24k_store_info
*pos1
= a
;
3829 const struct fix_24k_store_info
*pos2
= b
;
3831 return (pos1
->off
- pos2
->off
);
3834 /* INSN is a store instruction. Try to record the store information
3835 in STINFO. Return false if the information isn't known. */
3838 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3839 const struct mips_cl_insn
*insn
)
3841 /* The instruction must have a known offset. */
3842 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3845 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3846 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3850 /* Return the number of nops that would be needed to work around the 24k
3851 "lost data on stores during refill" errata if instruction INSN
3852 immediately followed the 2 instructions described by HIST.
3853 Ignore hazards that are contained within the first IGNORE
3854 instructions of HIST.
3856 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3857 for the data cache refills and store data. The following describes
3858 the scenario where the store data could be lost.
3860 * A data cache miss, due to either a load or a store, causing fill
3861 data to be supplied by the memory subsystem
3862 * The first three doublewords of fill data are returned and written
3864 * A sequence of four stores occurs in consecutive cycles around the
3865 final doubleword of the fill:
3869 * Zero, One or more instructions
3872 The four stores A-D must be to different doublewords of the line that
3873 is being filled. The fourth instruction in the sequence above permits
3874 the fill of the final doubleword to be transferred from the FSB into
3875 the cache. In the sequence above, the stores may be either integer
3876 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3877 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3878 different doublewords on the line. If the floating point unit is
3879 running in 1:2 mode, it is not possible to create the sequence above
3880 using only floating point store instructions.
3882 In this case, the cache line being filled is incorrectly marked
3883 invalid, thereby losing the data from any store to the line that
3884 occurs between the original miss and the completion of the five
3885 cycle sequence shown above.
3887 The workarounds are:
3889 * Run the data cache in write-through mode.
3890 * Insert a non-store instruction between
3891 Store A and Store B or Store B and Store C. */
3894 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3895 const struct mips_cl_insn
*insn
)
3897 struct fix_24k_store_info pos
[3];
3898 int align
, i
, base_offset
;
3903 /* If the previous instruction wasn't a store, there's nothing to
3905 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3908 /* If the instructions after the previous one are unknown, we have
3909 to assume the worst. */
3913 /* Check whether we are dealing with three consecutive stores. */
3914 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3915 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3918 /* If we don't know the relationship between the store addresses,
3919 assume the worst. */
3920 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3921 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3924 if (!fix_24k_record_store_info (&pos
[0], insn
)
3925 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3926 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3929 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3931 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3932 X bytes and such that the base register + X is known to be aligned
3935 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3939 align
= pos
[0].align_to
;
3940 base_offset
= pos
[0].off
;
3941 for (i
= 1; i
< 3; i
++)
3942 if (align
< pos
[i
].align_to
)
3944 align
= pos
[i
].align_to
;
3945 base_offset
= pos
[i
].off
;
3947 for (i
= 0; i
< 3; i
++)
3948 pos
[i
].off
-= base_offset
;
3951 pos
[0].off
&= ~align
+ 1;
3952 pos
[1].off
&= ~align
+ 1;
3953 pos
[2].off
&= ~align
+ 1;
3955 /* If any two stores write to the same chunk, they also write to the
3956 same doubleword. The offsets are still sorted at this point. */
3957 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3960 /* A range of at least 9 bytes is needed for the stores to be in
3961 non-overlapping doublewords. */
3962 if (pos
[2].off
- pos
[0].off
<= 8)
3965 if (pos
[2].off
- pos
[1].off
>= 24
3966 || pos
[1].off
- pos
[0].off
>= 24
3967 || pos
[2].off
- pos
[0].off
>= 32)
3973 /* Return the number of nops that would be needed if instruction INSN
3974 immediately followed the MAX_NOPS instructions given by HIST,
3975 where HIST[0] is the most recent instruction. Ignore hazards
3976 between INSN and the first IGNORE instructions in HIST.
3978 If INSN is null, return the worse-case number of nops for any
3982 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3983 const struct mips_cl_insn
*insn
)
3985 int i
, nops
, tmp_nops
;
3988 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3990 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3991 if (tmp_nops
> nops
)
3995 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3997 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3998 if (tmp_nops
> nops
)
4002 if (mips_fix_24k
&& !mips_opts
.micromips
)
4004 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
4005 if (tmp_nops
> nops
)
4012 /* The variable arguments provide NUM_INSNS extra instructions that
4013 might be added to HIST. Return the largest number of nops that
4014 would be needed after the extended sequence, ignoring hazards
4015 in the first IGNORE instructions. */
4018 nops_for_sequence (int num_insns
, int ignore
,
4019 const struct mips_cl_insn
*hist
, ...)
4022 struct mips_cl_insn buffer
[MAX_NOPS
];
4023 struct mips_cl_insn
*cursor
;
4026 va_start (args
, hist
);
4027 cursor
= buffer
+ num_insns
;
4028 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
4029 while (cursor
> buffer
)
4030 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
4032 nops
= nops_for_insn (ignore
, buffer
, NULL
);
4037 /* Like nops_for_insn, but if INSN is a branch, take into account the
4038 worst-case delay for the branch target. */
4041 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
4042 const struct mips_cl_insn
*insn
)
4046 nops
= nops_for_insn (ignore
, hist
, insn
);
4047 if (delayed_branch_p (insn
))
4049 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
4050 hist
, insn
, get_delay_slot_nop (insn
));
4051 if (tmp_nops
> nops
)
4054 else if (compact_branch_p (insn
))
4056 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
4057 if (tmp_nops
> nops
)
4063 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4066 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
4068 gas_assert (!HAVE_CODE_COMPRESSION
);
4069 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
4070 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
4073 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4074 jr target pc &= 'hffff_ffff_cfff_ffff. */
4077 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
4079 gas_assert (!HAVE_CODE_COMPRESSION
);
4080 if (strcmp (ip
->insn_mo
->name
, "j") == 0
4081 || strcmp (ip
->insn_mo
->name
, "jr") == 0
4082 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
4090 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
4091 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
4094 ep
.X_op
= O_constant
;
4095 ep
.X_add_number
= 0xcfff0000;
4096 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
4097 ep
.X_add_number
= 0xffff;
4098 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
4099 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
4104 fix_loongson2f (struct mips_cl_insn
* ip
)
4106 if (mips_fix_loongson2f_nop
)
4107 fix_loongson2f_nop (ip
);
4109 if (mips_fix_loongson2f_jump
)
4110 fix_loongson2f_jump (ip
);
4113 /* IP is a branch that has a delay slot, and we need to fill it
4114 automatically. Return true if we can do that by swapping IP
4115 with the previous instruction.
4116 ADDRESS_EXPR is an operand of the instruction to be used with
4120 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4121 bfd_reloc_code_real_type
*reloc_type
)
4123 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
4124 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
4126 /* -O2 and above is required for this optimization. */
4127 if (mips_optimize
< 2)
4130 /* If we have seen .set volatile or .set nomove, don't optimize. */
4131 if (mips_opts
.nomove
)
4134 /* We can't swap if the previous instruction's position is fixed. */
4135 if (history
[0].fixed_p
)
4138 /* If the previous previous insn was in a .set noreorder, we can't
4139 swap. Actually, the MIPS assembler will swap in this situation.
4140 However, gcc configured -with-gnu-as will generate code like
4148 in which we can not swap the bne and INSN. If gcc is not configured
4149 -with-gnu-as, it does not output the .set pseudo-ops. */
4150 if (history
[1].noreorder_p
)
4153 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4154 This means that the previous instruction was a 4-byte one anyhow. */
4155 if (mips_opts
.mips16
&& history
[0].fixp
[0])
4158 /* If the branch is itself the target of a branch, we can not swap.
4159 We cheat on this; all we check for is whether there is a label on
4160 this instruction. If there are any branches to anything other than
4161 a label, users must use .set noreorder. */
4162 if (seg_info (now_seg
)->label_list
)
4165 /* If the previous instruction is in a variant frag other than this
4166 branch's one, we cannot do the swap. This does not apply to
4167 MIPS16 code, which uses variant frags for different purposes. */
4168 if (!mips_opts
.mips16
4170 && history
[0].frag
->fr_type
== rs_machine_dependent
)
4173 /* We do not swap with instructions that cannot architecturally
4174 be placed in a branch delay slot, such as SYNC or ERET. We
4175 also refrain from swapping with a trap instruction, since it
4176 complicates trap handlers to have the trap instruction be in
4178 prev_pinfo
= history
[0].insn_mo
->pinfo
;
4179 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
4182 /* Check for conflicts between the branch and the instructions
4183 before the candidate delay slot. */
4184 if (nops_for_insn (0, history
+ 1, ip
) > 0)
4187 /* Check for conflicts between the swapped sequence and the
4188 target of the branch. */
4189 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
4192 /* If the branch reads a register that the previous
4193 instruction sets, we can not swap. */
4194 gpr_read
= gpr_read_mask (ip
);
4195 prev_gpr_write
= gpr_write_mask (&history
[0]);
4196 if (gpr_read
& prev_gpr_write
)
4199 /* If the branch writes a register that the previous
4200 instruction sets, we can not swap. */
4201 gpr_write
= gpr_write_mask (ip
);
4202 if (gpr_write
& prev_gpr_write
)
4205 /* If the branch writes a register that the previous
4206 instruction reads, we can not swap. */
4207 prev_gpr_read
= gpr_read_mask (&history
[0]);
4208 if (gpr_write
& prev_gpr_read
)
4211 /* If one instruction sets a condition code and the
4212 other one uses a condition code, we can not swap. */
4213 pinfo
= ip
->insn_mo
->pinfo
;
4214 if ((pinfo
& INSN_READ_COND_CODE
)
4215 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
4217 if ((pinfo
& INSN_WRITE_COND_CODE
)
4218 && (prev_pinfo
& INSN_READ_COND_CODE
))
4221 /* If the previous instruction uses the PC, we can not swap. */
4222 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4223 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
4225 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
4228 /* If the previous instruction has an incorrect size for a fixed
4229 branch delay slot in microMIPS mode, we cannot swap. */
4230 pinfo2
= ip
->insn_mo
->pinfo2
;
4231 if (mips_opts
.micromips
4232 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
4233 && insn_length (history
) != 2)
4235 if (mips_opts
.micromips
4236 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
4237 && insn_length (history
) != 4)
4240 /* On R5900 short loops need to be fixed by inserting a nop in
4241 the branch delay slots.
4242 A short loop can be terminated too early. */
4243 if (mips_opts
.arch
== CPU_R5900
4244 /* Check if instruction has a parameter, ignore "j $31". */
4245 && (address_expr
!= NULL
)
4246 /* Parameter must be 16 bit. */
4247 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
4248 /* Branch to same segment. */
4249 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
4250 /* Branch to same code fragment. */
4251 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
4252 /* Can only calculate branch offset if value is known. */
4253 && symbol_constant_p(address_expr
->X_add_symbol
)
4254 /* Check if branch is really conditional. */
4255 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
4256 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
4257 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
4260 /* Check if loop is shorter than 6 instructions including
4261 branch and delay slot. */
4262 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
4269 /* When the loop includes branches or jumps,
4270 it is not a short loop. */
4271 for (i
= 0; i
< (distance
/ 4); i
++)
4273 if ((history
[i
].cleared_p
)
4274 || delayed_branch_p(&history
[i
]))
4282 /* Insert nop after branch to fix short loop. */
4291 /* Decide how we should add IP to the instruction stream.
4292 ADDRESS_EXPR is an operand of the instruction to be used with
4295 static enum append_method
4296 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4297 bfd_reloc_code_real_type
*reloc_type
)
4299 unsigned long pinfo
;
4301 /* The relaxed version of a macro sequence must be inherently
4303 if (mips_relax
.sequence
== 2)
4306 /* We must not dabble with instructions in a ".set norerorder" block. */
4307 if (mips_opts
.noreorder
)
4310 /* Otherwise, it's our responsibility to fill branch delay slots. */
4311 if (delayed_branch_p (ip
))
4313 if (!branch_likely_p (ip
)
4314 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
4317 pinfo
= ip
->insn_mo
->pinfo
;
4318 if (mips_opts
.mips16
4319 && ISA_SUPPORTS_MIPS16E
4320 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
4321 return APPEND_ADD_COMPACT
;
4323 return APPEND_ADD_WITH_NOP
;
4329 /* IP is a MIPS16 instruction whose opcode we have just changed.
4330 Point IP->insn_mo to the new opcode's definition. */
4333 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
4335 const struct mips_opcode
*mo
, *end
;
4337 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
4338 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
4339 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
4347 /* For microMIPS macros, we need to generate a local number label
4348 as the target of branches. */
4349 #define MICROMIPS_LABEL_CHAR '\037'
4350 static unsigned long micromips_target_label
;
4351 static char micromips_target_name
[32];
4354 micromips_label_name (void)
4356 char *p
= micromips_target_name
;
4357 char symbol_name_temporary
[24];
4365 l
= micromips_target_label
;
4366 #ifdef LOCAL_LABEL_PREFIX
4367 *p
++ = LOCAL_LABEL_PREFIX
;
4370 *p
++ = MICROMIPS_LABEL_CHAR
;
4373 symbol_name_temporary
[i
++] = l
% 10 + '0';
4378 *p
++ = symbol_name_temporary
[--i
];
4381 return micromips_target_name
;
4385 micromips_label_expr (expressionS
*label_expr
)
4387 label_expr
->X_op
= O_symbol
;
4388 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4389 label_expr
->X_add_number
= 0;
4393 micromips_label_inc (void)
4395 micromips_target_label
++;
4396 *micromips_target_name
= '\0';
4400 micromips_add_label (void)
4404 s
= colon (micromips_label_name ());
4405 micromips_label_inc ();
4406 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4409 /* If assembling microMIPS code, then return the microMIPS reloc
4410 corresponding to the requested one if any. Otherwise return
4411 the reloc unchanged. */
4413 static bfd_reloc_code_real_type
4414 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4416 static const bfd_reloc_code_real_type relocs
[][2] =
4418 /* Keep sorted incrementally by the left-hand key. */
4419 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4420 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4421 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4422 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4423 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4424 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4425 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4426 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4427 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4428 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4429 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4430 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4431 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4432 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4433 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4434 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4435 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4436 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4437 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4438 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4439 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4440 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4441 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4442 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4443 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4444 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4445 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4447 bfd_reloc_code_real_type r
;
4450 if (!mips_opts
.micromips
)
4452 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4458 return relocs
[i
][1];
4463 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4464 Return true on success, storing the resolved value in RESULT. */
4467 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4472 case BFD_RELOC_MIPS_HIGHEST
:
4473 case BFD_RELOC_MICROMIPS_HIGHEST
:
4474 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4477 case BFD_RELOC_MIPS_HIGHER
:
4478 case BFD_RELOC_MICROMIPS_HIGHER
:
4479 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4482 case BFD_RELOC_HI16_S
:
4483 case BFD_RELOC_MICROMIPS_HI16_S
:
4484 case BFD_RELOC_MIPS16_HI16_S
:
4485 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4488 case BFD_RELOC_HI16
:
4489 case BFD_RELOC_MICROMIPS_HI16
:
4490 case BFD_RELOC_MIPS16_HI16
:
4491 *result
= (operand
>> 16) & 0xffff;
4494 case BFD_RELOC_LO16
:
4495 case BFD_RELOC_MICROMIPS_LO16
:
4496 case BFD_RELOC_MIPS16_LO16
:
4497 *result
= operand
& 0xffff;
4500 case BFD_RELOC_UNUSED
:
4509 /* Output an instruction. IP is the instruction information.
4510 ADDRESS_EXPR is an operand of the instruction to be used with
4511 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4512 a macro expansion. */
4515 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4516 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4518 unsigned long prev_pinfo2
, pinfo
;
4519 bfd_boolean relaxed_branch
= FALSE
;
4520 enum append_method method
;
4521 bfd_boolean relax32
;
4524 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4525 fix_loongson2f (ip
);
4527 file_ase_mips16
|= mips_opts
.mips16
;
4528 file_ase_micromips
|= mips_opts
.micromips
;
4530 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4531 pinfo
= ip
->insn_mo
->pinfo
;
4533 if (mips_opts
.micromips
4535 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4536 && micromips_insn_length (ip
->insn_mo
) != 2)
4537 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4538 && micromips_insn_length (ip
->insn_mo
) != 4)))
4539 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4540 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4542 if (address_expr
== NULL
)
4544 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4545 && reloc_type
[1] == BFD_RELOC_UNUSED
4546 && reloc_type
[2] == BFD_RELOC_UNUSED
4547 && address_expr
->X_op
== O_constant
)
4549 switch (*reloc_type
)
4551 case BFD_RELOC_MIPS_JMP
:
4555 shift
= mips_opts
.micromips
? 1 : 2;
4556 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4557 as_bad (_("jump to misaligned address (0x%lx)"),
4558 (unsigned long) address_expr
->X_add_number
);
4559 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4565 case BFD_RELOC_MIPS16_JMP
:
4566 if ((address_expr
->X_add_number
& 3) != 0)
4567 as_bad (_("jump to misaligned address (0x%lx)"),
4568 (unsigned long) address_expr
->X_add_number
);
4570 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4571 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4572 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4576 case BFD_RELOC_16_PCREL_S2
:
4580 shift
= mips_opts
.micromips
? 1 : 2;
4581 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4582 as_bad (_("branch to misaligned address (0x%lx)"),
4583 (unsigned long) address_expr
->X_add_number
);
4584 if (!mips_relax_branch
)
4586 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4587 & ~((1 << (shift
+ 16)) - 1))
4588 as_bad (_("branch address range overflow (0x%lx)"),
4589 (unsigned long) address_expr
->X_add_number
);
4590 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4600 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4603 ip
->insn_opcode
|= value
& 0xffff;
4611 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4613 /* There are a lot of optimizations we could do that we don't.
4614 In particular, we do not, in general, reorder instructions.
4615 If you use gcc with optimization, it will reorder
4616 instructions and generally do much more optimization then we
4617 do here; repeating all that work in the assembler would only
4618 benefit hand written assembly code, and does not seem worth
4620 int nops
= (mips_optimize
== 0
4621 ? nops_for_insn (0, history
, NULL
)
4622 : nops_for_insn_or_target (0, history
, ip
));
4626 unsigned long old_frag_offset
;
4629 old_frag
= frag_now
;
4630 old_frag_offset
= frag_now_fix ();
4632 for (i
= 0; i
< nops
; i
++)
4633 add_fixed_insn (NOP_INSN
);
4634 insert_into_history (0, nops
, NOP_INSN
);
4638 listing_prev_line ();
4639 /* We may be at the start of a variant frag. In case we
4640 are, make sure there is enough space for the frag
4641 after the frags created by listing_prev_line. The
4642 argument to frag_grow here must be at least as large
4643 as the argument to all other calls to frag_grow in
4644 this file. We don't have to worry about being in the
4645 middle of a variant frag, because the variants insert
4646 all needed nop instructions themselves. */
4650 mips_move_text_labels ();
4652 #ifndef NO_ECOFF_DEBUGGING
4653 if (ECOFF_DEBUGGING
)
4654 ecoff_fix_loc (old_frag
, old_frag_offset
);
4658 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4662 /* Work out how many nops in prev_nop_frag are needed by IP,
4663 ignoring hazards generated by the first prev_nop_frag_since
4665 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4666 gas_assert (nops
<= prev_nop_frag_holds
);
4668 /* Enforce NOPS as a minimum. */
4669 if (nops
> prev_nop_frag_required
)
4670 prev_nop_frag_required
= nops
;
4672 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4674 /* Settle for the current number of nops. Update the history
4675 accordingly (for the benefit of any future .set reorder code). */
4676 prev_nop_frag
= NULL
;
4677 insert_into_history (prev_nop_frag_since
,
4678 prev_nop_frag_holds
, NOP_INSN
);
4682 /* Allow this instruction to replace one of the nops that was
4683 tentatively added to prev_nop_frag. */
4684 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4685 prev_nop_frag_holds
--;
4686 prev_nop_frag_since
++;
4690 method
= get_append_method (ip
, address_expr
, reloc_type
);
4691 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4693 dwarf2_emit_insn (0);
4694 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4695 so "move" the instruction address accordingly.
4697 Also, it doesn't seem appropriate for the assembler to reorder .loc
4698 entries. If this instruction is a branch that we are going to swap
4699 with the previous instruction, the two instructions should be
4700 treated as a unit, and the debug information for both instructions
4701 should refer to the start of the branch sequence. Using the
4702 current position is certainly wrong when swapping a 32-bit branch
4703 and a 16-bit delay slot, since the current position would then be
4704 in the middle of a branch. */
4705 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
4707 relax32
= (mips_relax_branch
4708 /* Don't try branch relaxation within .set nomacro, or within
4709 .set noat if we use $at for PIC computations. If it turns
4710 out that the branch was out-of-range, we'll get an error. */
4711 && !mips_opts
.warn_about_macros
4712 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4713 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4714 as they have no complementing branches. */
4715 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
4717 if (!HAVE_CODE_COMPRESSION
4720 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4721 && delayed_branch_p (ip
))
4723 relaxed_branch
= TRUE
;
4724 add_relaxed_insn (ip
, (relaxed_branch_length
4726 uncond_branch_p (ip
) ? -1
4727 : branch_likely_p (ip
) ? 1
4731 uncond_branch_p (ip
),
4732 branch_likely_p (ip
),
4733 pinfo
& INSN_WRITE_GPR_31
,
4735 address_expr
->X_add_symbol
,
4736 address_expr
->X_add_number
);
4737 *reloc_type
= BFD_RELOC_UNUSED
;
4739 else if (mips_opts
.micromips
4741 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4742 || *reloc_type
> BFD_RELOC_UNUSED
)
4743 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4744 /* Don't try branch relaxation when users specify
4745 16-bit/32-bit instructions. */
4746 && !forced_insn_length
)
4748 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4749 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4750 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4751 int compact
= compact_branch_p (ip
);
4752 int al
= pinfo
& INSN_WRITE_GPR_31
;
4755 gas_assert (address_expr
!= NULL
);
4756 gas_assert (!mips_relax
.sequence
);
4758 relaxed_branch
= TRUE
;
4759 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4760 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4761 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4763 address_expr
->X_add_symbol
,
4764 address_expr
->X_add_number
);
4765 *reloc_type
= BFD_RELOC_UNUSED
;
4767 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4769 /* We need to set up a variant frag. */
4770 gas_assert (address_expr
!= NULL
);
4771 add_relaxed_insn (ip
, 4, 0,
4773 (*reloc_type
- BFD_RELOC_UNUSED
,
4774 forced_insn_length
== 2, forced_insn_length
== 4,
4775 delayed_branch_p (&history
[0]),
4776 history
[0].mips16_absolute_jump_p
),
4777 make_expr_symbol (address_expr
), 0);
4779 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4781 if (!delayed_branch_p (ip
))
4782 /* Make sure there is enough room to swap this instruction with
4783 a following jump instruction. */
4785 add_fixed_insn (ip
);
4789 if (mips_opts
.mips16
4790 && mips_opts
.noreorder
4791 && delayed_branch_p (&history
[0]))
4792 as_warn (_("extended instruction in delay slot"));
4794 if (mips_relax
.sequence
)
4796 /* If we've reached the end of this frag, turn it into a variant
4797 frag and record the information for the instructions we've
4799 if (frag_room () < 4)
4800 relax_close_frag ();
4801 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4804 if (mips_relax
.sequence
!= 2)
4806 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4807 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4808 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4809 mips_macro_warning
.insns
[0]++;
4811 if (mips_relax
.sequence
!= 1)
4813 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4814 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4815 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4816 mips_macro_warning
.insns
[1]++;
4819 if (mips_opts
.mips16
)
4822 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4824 add_fixed_insn (ip
);
4827 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4829 bfd_reloc_code_real_type final_type
[3];
4830 reloc_howto_type
*howto0
;
4831 reloc_howto_type
*howto
;
4834 /* Perform any necessary conversion to microMIPS relocations
4835 and find out how many relocations there actually are. */
4836 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4837 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4839 /* In a compound relocation, it is the final (outermost)
4840 operator that determines the relocated field. */
4841 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4846 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4847 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4848 bfd_get_reloc_size (howto
),
4850 howto0
&& howto0
->pc_relative
,
4853 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4854 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4855 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4857 /* These relocations can have an addend that won't fit in
4858 4 octets for 64bit assembly. */
4860 && ! howto
->partial_inplace
4861 && (reloc_type
[0] == BFD_RELOC_16
4862 || reloc_type
[0] == BFD_RELOC_32
4863 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4864 || reloc_type
[0] == BFD_RELOC_GPREL16
4865 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4866 || reloc_type
[0] == BFD_RELOC_GPREL32
4867 || reloc_type
[0] == BFD_RELOC_64
4868 || reloc_type
[0] == BFD_RELOC_CTOR
4869 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4870 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4871 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4872 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4873 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4874 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4875 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4876 || hi16_reloc_p (reloc_type
[0])
4877 || lo16_reloc_p (reloc_type
[0])))
4878 ip
->fixp
[0]->fx_no_overflow
= 1;
4880 /* These relocations can have an addend that won't fit in 2 octets. */
4881 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4882 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4883 ip
->fixp
[0]->fx_no_overflow
= 1;
4885 if (mips_relax
.sequence
)
4887 if (mips_relax
.first_fixup
== 0)
4888 mips_relax
.first_fixup
= ip
->fixp
[0];
4890 else if (reloc_needs_lo_p (*reloc_type
))
4892 struct mips_hi_fixup
*hi_fixup
;
4894 /* Reuse the last entry if it already has a matching %lo. */
4895 hi_fixup
= mips_hi_fixup_list
;
4897 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4899 hi_fixup
= ((struct mips_hi_fixup
*)
4900 xmalloc (sizeof (struct mips_hi_fixup
)));
4901 hi_fixup
->next
= mips_hi_fixup_list
;
4902 mips_hi_fixup_list
= hi_fixup
;
4904 hi_fixup
->fixp
= ip
->fixp
[0];
4905 hi_fixup
->seg
= now_seg
;
4908 /* Add fixups for the second and third relocations, if given.
4909 Note that the ABI allows the second relocation to be
4910 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4911 moment we only use RSS_UNDEF, but we could add support
4912 for the others if it ever becomes necessary. */
4913 for (i
= 1; i
< 3; i
++)
4914 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4916 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4917 ip
->fixp
[0]->fx_size
, NULL
, 0,
4918 FALSE
, final_type
[i
]);
4920 /* Use fx_tcbit to mark compound relocs. */
4921 ip
->fixp
[0]->fx_tcbit
= 1;
4922 ip
->fixp
[i
]->fx_tcbit
= 1;
4927 /* Update the register mask information. */
4928 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4929 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4934 insert_into_history (0, 1, ip
);
4937 case APPEND_ADD_WITH_NOP
:
4939 struct mips_cl_insn
*nop
;
4941 insert_into_history (0, 1, ip
);
4942 nop
= get_delay_slot_nop (ip
);
4943 add_fixed_insn (nop
);
4944 insert_into_history (0, 1, nop
);
4945 if (mips_relax
.sequence
)
4946 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4950 case APPEND_ADD_COMPACT
:
4951 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4952 gas_assert (mips_opts
.mips16
);
4953 ip
->insn_opcode
|= 0x0080;
4954 find_altered_mips16_opcode (ip
);
4956 insert_into_history (0, 1, ip
);
4961 struct mips_cl_insn delay
= history
[0];
4962 if (mips_opts
.mips16
)
4964 know (delay
.frag
== ip
->frag
);
4965 move_insn (ip
, delay
.frag
, delay
.where
);
4966 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4968 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4970 /* Add the delay slot instruction to the end of the
4971 current frag and shrink the fixed part of the
4972 original frag. If the branch occupies the tail of
4973 the latter, move it backwards to cover the gap. */
4974 delay
.frag
->fr_fix
-= branch_disp
;
4975 if (delay
.frag
== ip
->frag
)
4976 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4977 add_fixed_insn (&delay
);
4981 move_insn (&delay
, ip
->frag
,
4982 ip
->where
- branch_disp
+ insn_length (ip
));
4983 move_insn (ip
, history
[0].frag
, history
[0].where
);
4987 insert_into_history (0, 1, &delay
);
4992 /* If we have just completed an unconditional branch, clear the history. */
4993 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4994 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4998 mips_no_prev_insn ();
5000 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
5001 history
[i
].cleared_p
= 1;
5004 /* We need to emit a label at the end of branch-likely macros. */
5005 if (emit_branch_likely_macro
)
5007 emit_branch_likely_macro
= FALSE
;
5008 micromips_add_label ();
5011 /* We just output an insn, so the next one doesn't have a label. */
5012 mips_clear_insn_labels ();
5015 /* Forget that there was any previous instruction or label.
5016 When BRANCH is true, the branch history is also flushed. */
5019 mips_no_prev_insn (void)
5021 prev_nop_frag
= NULL
;
5022 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
5023 mips_clear_insn_labels ();
5026 /* This function must be called before we emit something other than
5027 instructions. It is like mips_no_prev_insn except that it inserts
5028 any NOPS that might be needed by previous instructions. */
5031 mips_emit_delays (void)
5033 if (! mips_opts
.noreorder
)
5035 int nops
= nops_for_insn (0, history
, NULL
);
5039 add_fixed_insn (NOP_INSN
);
5040 mips_move_text_labels ();
5043 mips_no_prev_insn ();
5046 /* Start a (possibly nested) noreorder block. */
5049 start_noreorder (void)
5051 if (mips_opts
.noreorder
== 0)
5056 /* None of the instructions before the .set noreorder can be moved. */
5057 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
5058 history
[i
].fixed_p
= 1;
5060 /* Insert any nops that might be needed between the .set noreorder
5061 block and the previous instructions. We will later remove any
5062 nops that turn out not to be needed. */
5063 nops
= nops_for_insn (0, history
, NULL
);
5066 if (mips_optimize
!= 0)
5068 /* Record the frag which holds the nop instructions, so
5069 that we can remove them if we don't need them. */
5070 frag_grow (nops
* NOP_INSN_SIZE
);
5071 prev_nop_frag
= frag_now
;
5072 prev_nop_frag_holds
= nops
;
5073 prev_nop_frag_required
= 0;
5074 prev_nop_frag_since
= 0;
5077 for (; nops
> 0; --nops
)
5078 add_fixed_insn (NOP_INSN
);
5080 /* Move on to a new frag, so that it is safe to simply
5081 decrease the size of prev_nop_frag. */
5082 frag_wane (frag_now
);
5084 mips_move_text_labels ();
5086 mips_mark_labels ();
5087 mips_clear_insn_labels ();
5089 mips_opts
.noreorder
++;
5090 mips_any_noreorder
= 1;
5093 /* End a nested noreorder block. */
5096 end_noreorder (void)
5098 mips_opts
.noreorder
--;
5099 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
5101 /* Commit to inserting prev_nop_frag_required nops and go back to
5102 handling nop insertion the .set reorder way. */
5103 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
5105 insert_into_history (prev_nop_frag_since
,
5106 prev_nop_frag_required
, NOP_INSN
);
5107 prev_nop_frag
= NULL
;
5111 /* Set up global variables for the start of a new macro. */
5116 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
5117 memset (&mips_macro_warning
.first_insn_sizes
, 0,
5118 sizeof (mips_macro_warning
.first_insn_sizes
));
5119 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
5120 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
5121 && delayed_branch_p (&history
[0]));
5122 switch (history
[0].insn_mo
->pinfo2
5123 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
5125 case INSN2_BRANCH_DELAY_32BIT
:
5126 mips_macro_warning
.delay_slot_length
= 4;
5128 case INSN2_BRANCH_DELAY_16BIT
:
5129 mips_macro_warning
.delay_slot_length
= 2;
5132 mips_macro_warning
.delay_slot_length
= 0;
5135 mips_macro_warning
.first_frag
= NULL
;
5138 /* Given that a macro is longer than one instruction or of the wrong size,
5139 return the appropriate warning for it. Return null if no warning is
5140 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5141 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5142 and RELAX_NOMACRO. */
5145 macro_warning (relax_substateT subtype
)
5147 if (subtype
& RELAX_DELAY_SLOT
)
5148 return _("Macro instruction expanded into multiple instructions"
5149 " in a branch delay slot");
5150 else if (subtype
& RELAX_NOMACRO
)
5151 return _("Macro instruction expanded into multiple instructions");
5152 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
5153 | RELAX_DELAY_SLOT_SIZE_SECOND
))
5154 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
5155 ? _("Macro instruction expanded into a wrong size instruction"
5156 " in a 16-bit branch delay slot")
5157 : _("Macro instruction expanded into a wrong size instruction"
5158 " in a 32-bit branch delay slot"));
5163 /* Finish up a macro. Emit warnings as appropriate. */
5168 /* Relaxation warning flags. */
5169 relax_substateT subtype
= 0;
5171 /* Check delay slot size requirements. */
5172 if (mips_macro_warning
.delay_slot_length
== 2)
5173 subtype
|= RELAX_DELAY_SLOT_16BIT
;
5174 if (mips_macro_warning
.delay_slot_length
!= 0)
5176 if (mips_macro_warning
.delay_slot_length
5177 != mips_macro_warning
.first_insn_sizes
[0])
5178 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
5179 if (mips_macro_warning
.delay_slot_length
5180 != mips_macro_warning
.first_insn_sizes
[1])
5181 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
5184 /* Check instruction count requirements. */
5185 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
5187 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
5188 subtype
|= RELAX_SECOND_LONGER
;
5189 if (mips_opts
.warn_about_macros
)
5190 subtype
|= RELAX_NOMACRO
;
5191 if (mips_macro_warning
.delay_slot_p
)
5192 subtype
|= RELAX_DELAY_SLOT
;
5195 /* If both alternatives fail to fill a delay slot correctly,
5196 emit the warning now. */
5197 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
5198 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
5203 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
5204 | RELAX_DELAY_SLOT_SIZE_FIRST
5205 | RELAX_DELAY_SLOT_SIZE_SECOND
);
5206 msg
= macro_warning (s
);
5208 as_warn ("%s", msg
);
5212 /* If both implementations are longer than 1 instruction, then emit the
5214 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
5219 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
5220 msg
= macro_warning (s
);
5222 as_warn ("%s", msg
);
5226 /* If any flags still set, then one implementation might need a warning
5227 and the other either will need one of a different kind or none at all.
5228 Pass any remaining flags over to relaxation. */
5229 if (mips_macro_warning
.first_frag
!= NULL
)
5230 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
5233 /* Instruction operand formats used in macros that vary between
5234 standard MIPS and microMIPS code. */
5236 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
5237 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
5238 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
5239 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
5240 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
5241 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
5242 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
5243 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
5245 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
5246 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5247 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5248 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5249 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5250 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
5251 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5252 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5254 /* Read a macro's relocation codes from *ARGS and store them in *R.
5255 The first argument in *ARGS will be either the code for a single
5256 relocation or -1 followed by the three codes that make up a
5257 composite relocation. */
5260 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
5264 next
= va_arg (*args
, int);
5266 r
[0] = (bfd_reloc_code_real_type
) next
;
5268 for (i
= 0; i
< 3; i
++)
5269 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
5272 /* Build an instruction created by a macro expansion. This is passed
5273 a pointer to the count of instructions created so far, an
5274 expression, the name of the instruction to build, an operand format
5275 string, and corresponding arguments. */
5278 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
5280 const struct mips_opcode
*mo
= NULL
;
5281 bfd_reloc_code_real_type r
[3];
5282 const struct mips_opcode
*amo
;
5283 struct hash_control
*hash
;
5284 struct mips_cl_insn insn
;
5287 va_start (args
, fmt
);
5289 if (mips_opts
.mips16
)
5291 mips16_macro_build (ep
, name
, fmt
, &args
);
5296 r
[0] = BFD_RELOC_UNUSED
;
5297 r
[1] = BFD_RELOC_UNUSED
;
5298 r
[2] = BFD_RELOC_UNUSED
;
5299 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
5300 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
5302 gas_assert (strcmp (name
, amo
->name
) == 0);
5306 /* Search until we get a match for NAME. It is assumed here that
5307 macros will never generate MDMX, MIPS-3D, or MT instructions.
5308 We try to match an instruction that fulfils the branch delay
5309 slot instruction length requirement (if any) of the previous
5310 instruction. While doing this we record the first instruction
5311 seen that matches all the other conditions and use it anyway
5312 if the requirement cannot be met; we will issue an appropriate
5313 warning later on. */
5314 if (strcmp (fmt
, amo
->args
) == 0
5315 && amo
->pinfo
!= INSN_MACRO
5316 && is_opcode_valid (amo
)
5317 && is_size_valid (amo
))
5319 if (is_delay_slot_valid (amo
))
5329 gas_assert (amo
->name
);
5331 while (strcmp (name
, amo
->name
) == 0);
5334 create_insn (&insn
, mo
);
5352 INSERT_OPERAND (mips_opts
.micromips
,
5353 EXTLSB
, insn
, va_arg (args
, int));
5358 /* Note that in the macro case, these arguments are already
5359 in MSB form. (When handling the instruction in the
5360 non-macro case, these arguments are sizes from which
5361 MSB values must be calculated.) */
5362 INSERT_OPERAND (mips_opts
.micromips
,
5363 INSMSB
, insn
, va_arg (args
, int));
5367 gas_assert (!mips_opts
.micromips
);
5368 INSERT_OPERAND (0, CODE10
, insn
, va_arg (args
, int));
5374 /* Note that in the macro case, these arguments are already
5375 in MSBD form. (When handling the instruction in the
5376 non-macro case, these arguments are sizes from which
5377 MSBD values must be calculated.) */
5378 INSERT_OPERAND (mips_opts
.micromips
,
5379 EXTMSBD
, insn
, va_arg (args
, int));
5383 gas_assert (!mips_opts
.micromips
);
5384 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5388 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, insn
, va_arg (args
, int));
5397 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5401 gas_assert (mips_opts
.micromips
);
5405 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5409 INSERT_OPERAND (mips_opts
.micromips
, CODE
, insn
, va_arg (args
, int));
5413 gas_assert (!mips_opts
.micromips
);
5415 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5419 if (mips_opts
.micromips
)
5420 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5422 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5426 gas_assert (!mips_opts
.micromips
);
5428 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5432 gas_assert (!mips_opts
.micromips
);
5434 int tmp
= va_arg (args
, int);
5436 INSERT_OPERAND (0, RT
, insn
, tmp
);
5437 INSERT_OPERAND (0, RD
, insn
, tmp
);
5443 gas_assert (!mips_opts
.micromips
);
5444 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5451 INSERT_OPERAND (mips_opts
.micromips
,
5452 SHAMT
, insn
, va_arg (args
, int));
5456 gas_assert (!mips_opts
.micromips
);
5457 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5461 gas_assert (!mips_opts
.micromips
);
5462 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5466 gas_assert (!mips_opts
.micromips
);
5467 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5471 gas_assert (!mips_opts
.micromips
);
5472 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5479 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5484 macro_read_relocs (&args
, r
);
5485 gas_assert (*r
== BFD_RELOC_GPREL16
5486 || *r
== BFD_RELOC_MIPS_HIGHER
5487 || *r
== BFD_RELOC_HI16_S
5488 || *r
== BFD_RELOC_LO16
5489 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5493 macro_read_relocs (&args
, r
);
5497 macro_read_relocs (&args
, r
);
5498 gas_assert (ep
!= NULL
5499 && (ep
->X_op
== O_constant
5500 || (ep
->X_op
== O_symbol
5501 && (*r
== BFD_RELOC_MIPS_HIGHEST
5502 || *r
== BFD_RELOC_HI16_S
5503 || *r
== BFD_RELOC_HI16
5504 || *r
== BFD_RELOC_GPREL16
5505 || *r
== BFD_RELOC_MIPS_GOT_HI16
5506 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5510 gas_assert (ep
!= NULL
);
5513 * This allows macro() to pass an immediate expression for
5514 * creating short branches without creating a symbol.
5516 * We don't allow branch relaxation for these branches, as
5517 * they should only appear in ".set nomacro" anyway.
5519 if (ep
->X_op
== O_constant
)
5521 /* For microMIPS we always use relocations for branches.
5522 So we should not resolve immediate values. */
5523 gas_assert (!mips_opts
.micromips
);
5525 if ((ep
->X_add_number
& 3) != 0)
5526 as_bad (_("branch to misaligned address (0x%lx)"),
5527 (unsigned long) ep
->X_add_number
);
5528 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5529 as_bad (_("branch address range overflow (0x%lx)"),
5530 (unsigned long) ep
->X_add_number
);
5531 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5535 *r
= BFD_RELOC_16_PCREL_S2
;
5539 gas_assert (ep
!= NULL
);
5540 *r
= BFD_RELOC_MIPS_JMP
;
5544 gas_assert (!mips_opts
.micromips
);
5545 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5549 INSERT_OPERAND (mips_opts
.micromips
,
5550 CACHE
, insn
, va_arg (args
, unsigned long));
5554 gas_assert (mips_opts
.micromips
);
5555 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5559 gas_assert (mips_opts
.micromips
);
5560 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5564 INSERT_OPERAND (mips_opts
.micromips
,
5565 3BITPOS
, insn
, va_arg (args
, unsigned int));
5569 INSERT_OPERAND (mips_opts
.micromips
,
5570 OFFSET12
, insn
, va_arg (args
, unsigned long));
5574 gas_assert (mips_opts
.micromips
);
5575 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5578 case 'm': /* Opcode extension character. */
5579 gas_assert (mips_opts
.micromips
);
5583 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5587 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5591 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5605 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5607 append_insn (&insn
, ep
, r
, TRUE
);
5611 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5614 struct mips_opcode
*mo
;
5615 struct mips_cl_insn insn
;
5616 bfd_reloc_code_real_type r
[3]
5617 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5619 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5621 gas_assert (strcmp (name
, mo
->name
) == 0);
5623 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5626 gas_assert (mo
->name
);
5627 gas_assert (strcmp (name
, mo
->name
) == 0);
5630 create_insn (&insn
, mo
);
5648 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5653 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5657 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5661 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5671 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5678 regno
= va_arg (*args
, int);
5679 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5680 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5703 gas_assert (ep
!= NULL
);
5705 if (ep
->X_op
!= O_constant
)
5706 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5707 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5709 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5711 *r
= BFD_RELOC_UNUSED
;
5717 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5724 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5726 append_insn (&insn
, ep
, r
, TRUE
);
5730 * Sign-extend 32-bit mode constants that have bit 31 set and all
5731 * higher bits unset.
5734 normalize_constant_expr (expressionS
*ex
)
5736 if (ex
->X_op
== O_constant
5737 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5738 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5743 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5744 * all higher bits unset.
5747 normalize_address_expr (expressionS
*ex
)
5749 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5750 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5751 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5752 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5757 * Generate a "jalr" instruction with a relocation hint to the called
5758 * function. This occurs in NewABI PIC code.
5761 macro_build_jalr (expressionS
*ep
, int cprestore
)
5763 static const bfd_reloc_code_real_type jalr_relocs
[2]
5764 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5765 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5769 if (MIPS_JALR_HINT_P (ep
))
5774 if (mips_opts
.micromips
)
5776 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
5777 ? "jalr" : "jalrs");
5778 if (MIPS_JALR_HINT_P (ep
)
5780 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5781 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5783 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5786 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5787 if (MIPS_JALR_HINT_P (ep
))
5788 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5792 * Generate a "lui" instruction.
5795 macro_build_lui (expressionS
*ep
, int regnum
)
5797 gas_assert (! mips_opts
.mips16
);
5799 if (ep
->X_op
!= O_constant
)
5801 gas_assert (ep
->X_op
== O_symbol
);
5802 /* _gp_disp is a special case, used from s_cpload.
5803 __gnu_local_gp is used if mips_no_shared. */
5804 gas_assert (mips_pic
== NO_PIC
5806 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5807 || (! mips_in_shared
5808 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5809 "__gnu_local_gp") == 0));
5812 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5815 /* Generate a sequence of instructions to do a load or store from a constant
5816 offset off of a base register (breg) into/from a target register (treg),
5817 using AT if necessary. */
5819 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5820 int treg
, int breg
, int dbl
)
5822 gas_assert (ep
->X_op
== O_constant
);
5824 /* Sign-extending 32-bit constants makes their handling easier. */
5826 normalize_constant_expr (ep
);
5828 /* Right now, this routine can only handle signed 32-bit constants. */
5829 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5830 as_warn (_("operand overflow"));
5832 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5834 /* Signed 16-bit offset will fit in the op. Easy! */
5835 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5839 /* 32-bit offset, need multiple instructions and AT, like:
5840 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5841 addu $tempreg,$tempreg,$breg
5842 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5843 to handle the complete offset. */
5844 macro_build_lui (ep
, AT
);
5845 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5846 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5849 as_bad (_("Macro used $at after \".set noat\""));
5854 * Generates code to set the $at register to true (one)
5855 * if reg is less than the immediate expression.
5858 set_at (int reg
, int unsignedp
)
5860 if (imm_expr
.X_op
== O_constant
5861 && imm_expr
.X_add_number
>= -0x8000
5862 && imm_expr
.X_add_number
< 0x8000)
5863 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5864 AT
, reg
, BFD_RELOC_LO16
);
5867 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5868 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5872 /* Warn if an expression is not a constant. */
5875 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5877 if (ex
->X_op
== O_big
)
5878 as_bad (_("unsupported large constant"));
5879 else if (ex
->X_op
!= O_constant
)
5880 as_bad (_("Instruction %s requires absolute expression"),
5883 if (HAVE_32BIT_GPRS
)
5884 normalize_constant_expr (ex
);
5887 /* Count the leading zeroes by performing a binary chop. This is a
5888 bulky bit of source, but performance is a LOT better for the
5889 majority of values than a simple loop to count the bits:
5890 for (lcnt = 0; (lcnt < 32); lcnt++)
5891 if ((v) & (1 << (31 - lcnt)))
5893 However it is not code size friendly, and the gain will drop a bit
5894 on certain cached systems.
5896 #define COUNT_TOP_ZEROES(v) \
5897 (((v) & ~0xffff) == 0 \
5898 ? ((v) & ~0xff) == 0 \
5899 ? ((v) & ~0xf) == 0 \
5900 ? ((v) & ~0x3) == 0 \
5901 ? ((v) & ~0x1) == 0 \
5906 : ((v) & ~0x7) == 0 \
5909 : ((v) & ~0x3f) == 0 \
5910 ? ((v) & ~0x1f) == 0 \
5913 : ((v) & ~0x7f) == 0 \
5916 : ((v) & ~0xfff) == 0 \
5917 ? ((v) & ~0x3ff) == 0 \
5918 ? ((v) & ~0x1ff) == 0 \
5921 : ((v) & ~0x7ff) == 0 \
5924 : ((v) & ~0x3fff) == 0 \
5925 ? ((v) & ~0x1fff) == 0 \
5928 : ((v) & ~0x7fff) == 0 \
5931 : ((v) & ~0xffffff) == 0 \
5932 ? ((v) & ~0xfffff) == 0 \
5933 ? ((v) & ~0x3ffff) == 0 \
5934 ? ((v) & ~0x1ffff) == 0 \
5937 : ((v) & ~0x7ffff) == 0 \
5940 : ((v) & ~0x3fffff) == 0 \
5941 ? ((v) & ~0x1fffff) == 0 \
5944 : ((v) & ~0x7fffff) == 0 \
5947 : ((v) & ~0xfffffff) == 0 \
5948 ? ((v) & ~0x3ffffff) == 0 \
5949 ? ((v) & ~0x1ffffff) == 0 \
5952 : ((v) & ~0x7ffffff) == 0 \
5955 : ((v) & ~0x3fffffff) == 0 \
5956 ? ((v) & ~0x1fffffff) == 0 \
5959 : ((v) & ~0x7fffffff) == 0 \
5964 * This routine generates the least number of instructions necessary to load
5965 * an absolute expression value into a register.
5968 load_register (int reg
, expressionS
*ep
, int dbl
)
5971 expressionS hi32
, lo32
;
5973 if (ep
->X_op
!= O_big
)
5975 gas_assert (ep
->X_op
== O_constant
);
5977 /* Sign-extending 32-bit constants makes their handling easier. */
5979 normalize_constant_expr (ep
);
5981 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5983 /* We can handle 16 bit signed values with an addiu to
5984 $zero. No need to ever use daddiu here, since $zero and
5985 the result are always correct in 32 bit mode. */
5986 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5989 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5991 /* We can handle 16 bit unsigned values with an ori to
5993 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5996 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5998 /* 32 bit values require an lui. */
5999 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6000 if ((ep
->X_add_number
& 0xffff) != 0)
6001 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6006 /* The value is larger than 32 bits. */
6008 if (!dbl
|| HAVE_32BIT_GPRS
)
6012 sprintf_vma (value
, ep
->X_add_number
);
6013 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6014 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6018 if (ep
->X_op
!= O_big
)
6021 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6022 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6023 hi32
.X_add_number
&= 0xffffffff;
6025 lo32
.X_add_number
&= 0xffffffff;
6029 gas_assert (ep
->X_add_number
> 2);
6030 if (ep
->X_add_number
== 3)
6031 generic_bignum
[3] = 0;
6032 else if (ep
->X_add_number
> 4)
6033 as_bad (_("Number larger than 64 bits"));
6034 lo32
.X_op
= O_constant
;
6035 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
6036 hi32
.X_op
= O_constant
;
6037 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
6040 if (hi32
.X_add_number
== 0)
6045 unsigned long hi
, lo
;
6047 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
6049 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
6051 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6054 if (lo32
.X_add_number
& 0x80000000)
6056 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6057 if (lo32
.X_add_number
& 0xffff)
6058 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6063 /* Check for 16bit shifted constant. We know that hi32 is
6064 non-zero, so start the mask on the first bit of the hi32
6069 unsigned long himask
, lomask
;
6073 himask
= 0xffff >> (32 - shift
);
6074 lomask
= (0xffff << shift
) & 0xffffffff;
6078 himask
= 0xffff << (shift
- 32);
6081 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
6082 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
6086 tmp
.X_op
= O_constant
;
6088 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
6089 | (lo32
.X_add_number
>> shift
));
6091 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
6092 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6093 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6094 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6099 while (shift
<= (64 - 16));
6101 /* Find the bit number of the lowest one bit, and store the
6102 shifted value in hi/lo. */
6103 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
6104 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
6108 while ((lo
& 1) == 0)
6113 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
6119 while ((hi
& 1) == 0)
6128 /* Optimize if the shifted value is a (power of 2) - 1. */
6129 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
6130 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
6132 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
6137 /* This instruction will set the register to be all
6139 tmp
.X_op
= O_constant
;
6140 tmp
.X_add_number
= (offsetT
) -1;
6141 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6145 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6146 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
6148 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
6149 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6154 /* Sign extend hi32 before calling load_register, because we can
6155 generally get better code when we load a sign extended value. */
6156 if ((hi32
.X_add_number
& 0x80000000) != 0)
6157 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
6158 load_register (reg
, &hi32
, 0);
6161 if ((lo32
.X_add_number
& 0xffff0000) == 0)
6165 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
6173 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
6175 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6176 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
6182 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
6186 mid16
.X_add_number
>>= 16;
6187 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6188 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6191 if ((lo32
.X_add_number
& 0xffff) != 0)
6192 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6196 load_delay_nop (void)
6198 if (!gpr_interlocks
)
6199 macro_build (NULL
, "nop", "");
6202 /* Load an address into a register. */
6205 load_address (int reg
, expressionS
*ep
, int *used_at
)
6207 if (ep
->X_op
!= O_constant
6208 && ep
->X_op
!= O_symbol
)
6210 as_bad (_("expression too complex"));
6211 ep
->X_op
= O_constant
;
6214 if (ep
->X_op
== O_constant
)
6216 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
6220 if (mips_pic
== NO_PIC
)
6222 /* If this is a reference to a GP relative symbol, we want
6223 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6225 lui $reg,<sym> (BFD_RELOC_HI16_S)
6226 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6227 If we have an addend, we always use the latter form.
6229 With 64bit address space and a usable $at we want
6230 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6231 lui $at,<sym> (BFD_RELOC_HI16_S)
6232 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6233 daddiu $at,<sym> (BFD_RELOC_LO16)
6237 If $at is already in use, we use a path which is suboptimal
6238 on superscalar processors.
6239 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6240 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6242 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6244 daddiu $reg,<sym> (BFD_RELOC_LO16)
6246 For GP relative symbols in 64bit address space we can use
6247 the same sequence as in 32bit address space. */
6248 if (HAVE_64BIT_SYMBOLS
)
6250 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
6251 && !nopic_need_relax (ep
->X_add_symbol
, 1))
6253 relax_start (ep
->X_add_symbol
);
6254 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
6255 mips_gp_register
, BFD_RELOC_GPREL16
);
6259 if (*used_at
== 0 && mips_opts
.at
)
6261 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
6262 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
6263 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
6264 BFD_RELOC_MIPS_HIGHER
);
6265 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
6266 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
6267 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
6272 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
6273 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
6274 BFD_RELOC_MIPS_HIGHER
);
6275 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6276 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
6277 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6278 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
6281 if (mips_relax
.sequence
)
6286 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
6287 && !nopic_need_relax (ep
->X_add_symbol
, 1))
6289 relax_start (ep
->X_add_symbol
);
6290 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
6291 mips_gp_register
, BFD_RELOC_GPREL16
);
6294 macro_build_lui (ep
, reg
);
6295 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
6296 reg
, reg
, BFD_RELOC_LO16
);
6297 if (mips_relax
.sequence
)
6301 else if (!mips_big_got
)
6305 /* If this is a reference to an external symbol, we want
6306 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6308 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6310 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6311 If there is a constant, it must be added in after.
6313 If we have NewABI, we want
6314 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6315 unless we're referencing a global symbol with a non-zero
6316 offset, in which case cst must be added separately. */
6319 if (ep
->X_add_number
)
6321 ex
.X_add_number
= ep
->X_add_number
;
6322 ep
->X_add_number
= 0;
6323 relax_start (ep
->X_add_symbol
);
6324 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6325 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6326 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6327 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6328 ex
.X_op
= O_constant
;
6329 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6330 reg
, reg
, BFD_RELOC_LO16
);
6331 ep
->X_add_number
= ex
.X_add_number
;
6334 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6335 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6336 if (mips_relax
.sequence
)
6341 ex
.X_add_number
= ep
->X_add_number
;
6342 ep
->X_add_number
= 0;
6343 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6344 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6346 relax_start (ep
->X_add_symbol
);
6348 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6352 if (ex
.X_add_number
!= 0)
6354 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6355 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6356 ex
.X_op
= O_constant
;
6357 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6358 reg
, reg
, BFD_RELOC_LO16
);
6362 else if (mips_big_got
)
6366 /* This is the large GOT case. If this is a reference to an
6367 external symbol, we want
6368 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6370 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6372 Otherwise, for a reference to a local symbol in old ABI, we want
6373 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6375 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6376 If there is a constant, it must be added in after.
6378 In the NewABI, for local symbols, with or without offsets, we want:
6379 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6380 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6384 ex
.X_add_number
= ep
->X_add_number
;
6385 ep
->X_add_number
= 0;
6386 relax_start (ep
->X_add_symbol
);
6387 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6388 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6389 reg
, reg
, mips_gp_register
);
6390 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6391 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6392 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6393 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6394 else if (ex
.X_add_number
)
6396 ex
.X_op
= O_constant
;
6397 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6401 ep
->X_add_number
= ex
.X_add_number
;
6403 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6404 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6405 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6406 BFD_RELOC_MIPS_GOT_OFST
);
6411 ex
.X_add_number
= ep
->X_add_number
;
6412 ep
->X_add_number
= 0;
6413 relax_start (ep
->X_add_symbol
);
6414 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6415 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6416 reg
, reg
, mips_gp_register
);
6417 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6418 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6420 if (reg_needs_delay (mips_gp_register
))
6422 /* We need a nop before loading from $gp. This special
6423 check is required because the lui which starts the main
6424 instruction stream does not refer to $gp, and so will not
6425 insert the nop which may be required. */
6426 macro_build (NULL
, "nop", "");
6428 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6429 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6431 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6435 if (ex
.X_add_number
!= 0)
6437 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6438 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6439 ex
.X_op
= O_constant
;
6440 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6448 if (!mips_opts
.at
&& *used_at
== 1)
6449 as_bad (_("Macro used $at after \".set noat\""));
6452 /* Move the contents of register SOURCE into register DEST. */
6455 move_register (int dest
, int source
)
6457 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6458 instruction specifically requires a 32-bit one. */
6459 if (mips_opts
.micromips
6460 && !mips_opts
.insn32
6461 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6462 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6464 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6468 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6469 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6470 The two alternatives are:
6472 Global symbol Local sybmol
6473 ------------- ------------
6474 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6476 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6478 load_got_offset emits the first instruction and add_got_offset
6479 emits the second for a 16-bit offset or add_got_offset_hilo emits
6480 a sequence to add a 32-bit offset using a scratch register. */
6483 load_got_offset (int dest
, expressionS
*local
)
6488 global
.X_add_number
= 0;
6490 relax_start (local
->X_add_symbol
);
6491 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6492 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6494 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6495 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6500 add_got_offset (int dest
, expressionS
*local
)
6504 global
.X_op
= O_constant
;
6505 global
.X_op_symbol
= NULL
;
6506 global
.X_add_symbol
= NULL
;
6507 global
.X_add_number
= local
->X_add_number
;
6509 relax_start (local
->X_add_symbol
);
6510 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6511 dest
, dest
, BFD_RELOC_LO16
);
6513 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6518 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6521 int hold_mips_optimize
;
6523 global
.X_op
= O_constant
;
6524 global
.X_op_symbol
= NULL
;
6525 global
.X_add_symbol
= NULL
;
6526 global
.X_add_number
= local
->X_add_number
;
6528 relax_start (local
->X_add_symbol
);
6529 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6531 /* Set mips_optimize around the lui instruction to avoid
6532 inserting an unnecessary nop after the lw. */
6533 hold_mips_optimize
= mips_optimize
;
6535 macro_build_lui (&global
, tmp
);
6536 mips_optimize
= hold_mips_optimize
;
6537 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6540 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6543 /* Emit a sequence of instructions to emulate a branch likely operation.
6544 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6545 is its complementing branch with the original condition negated.
6546 CALL is set if the original branch specified the link operation.
6547 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6549 Code like this is produced in the noreorder mode:
6554 delay slot (executed only if branch taken)
6562 delay slot (executed only if branch taken)
6565 In the reorder mode the delay slot would be filled with a nop anyway,
6566 so code produced is simply:
6571 This function is used when producing code for the microMIPS ASE that
6572 does not implement branch likely instructions in hardware. */
6575 macro_build_branch_likely (const char *br
, const char *brneg
,
6576 int call
, expressionS
*ep
, const char *fmt
,
6577 unsigned int sreg
, unsigned int treg
)
6579 int noreorder
= mips_opts
.noreorder
;
6582 gas_assert (mips_opts
.micromips
);
6586 micromips_label_expr (&expr1
);
6587 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6588 macro_build (NULL
, "nop", "");
6589 macro_build (ep
, call
? "bal" : "b", "p");
6591 /* Set to true so that append_insn adds a label. */
6592 emit_branch_likely_macro
= TRUE
;
6596 macro_build (ep
, br
, fmt
, sreg
, treg
);
6597 macro_build (NULL
, "nop", "");
6602 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6603 the condition code tested. EP specifies the branch target. */
6606 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6633 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6636 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6637 the register tested. EP specifies the branch target. */
6640 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6642 const char *brneg
= NULL
;
6652 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6656 gas_assert (mips_opts
.micromips
);
6657 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
6665 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6672 br
= mips_opts
.micromips
? "blez" : "blezl";
6679 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6683 gas_assert (mips_opts
.micromips
);
6684 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
6691 if (mips_opts
.micromips
&& brneg
)
6692 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6694 macro_build (ep
, br
, "s,p", sreg
);
6697 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6698 TREG as the registers tested. EP specifies the branch target. */
6701 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6702 unsigned int sreg
, unsigned int treg
)
6704 const char *brneg
= NULL
;
6716 br
= mips_opts
.micromips
? "beq" : "beql";
6725 br
= mips_opts
.micromips
? "bne" : "bnel";
6731 if (mips_opts
.micromips
&& brneg
)
6732 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6734 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6739 * This routine implements the seemingly endless macro or synthesized
6740 * instructions and addressing modes in the mips assembly language. Many
6741 * of these macros are simple and are similar to each other. These could
6742 * probably be handled by some kind of table or grammar approach instead of
6743 * this verbose method. Others are not simple macros but are more like
6744 * optimizing code generation.
6745 * One interesting optimization is when several store macros appear
6746 * consecutively that would load AT with the upper half of the same address.
6747 * The ensuing load upper instructions are ommited. This implies some kind
6748 * of global optimization. We currently only optimize within a single macro.
6749 * For many of the load and store macros if the address is specified as a
6750 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6751 * first load register 'at' with zero and use it as the base register. The
6752 * mips assembler simply uses register $zero. Just one tiny optimization
6756 macro (struct mips_cl_insn
*ip
, char *str
)
6758 unsigned int treg
, sreg
, dreg
, breg
;
6759 unsigned int tempreg
;
6762 expressionS label_expr
;
6779 bfd_reloc_code_real_type r
;
6780 int hold_mips_optimize
;
6782 gas_assert (! mips_opts
.mips16
);
6784 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6785 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6786 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6787 mask
= ip
->insn_mo
->mask
;
6789 label_expr
.X_op
= O_constant
;
6790 label_expr
.X_op_symbol
= NULL
;
6791 label_expr
.X_add_symbol
= NULL
;
6792 label_expr
.X_add_number
= 0;
6794 expr1
.X_op
= O_constant
;
6795 expr1
.X_op_symbol
= NULL
;
6796 expr1
.X_add_symbol
= NULL
;
6797 expr1
.X_add_number
= 1;
6812 if (mips_opts
.micromips
)
6813 micromips_label_expr (&label_expr
);
6815 label_expr
.X_add_number
= 8;
6816 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6818 macro_build (NULL
, "nop", "");
6820 move_register (dreg
, sreg
);
6821 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6822 if (mips_opts
.micromips
)
6823 micromips_add_label ();
6840 if (!mips_opts
.micromips
)
6842 if (imm_expr
.X_op
== O_constant
6843 && imm_expr
.X_add_number
>= -0x200
6844 && imm_expr
.X_add_number
< 0x200)
6846 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6855 if (imm_expr
.X_op
== O_constant
6856 && imm_expr
.X_add_number
>= -0x8000
6857 && imm_expr
.X_add_number
< 0x8000)
6859 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6864 load_register (AT
, &imm_expr
, dbl
);
6865 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6884 if (imm_expr
.X_op
== O_constant
6885 && imm_expr
.X_add_number
>= 0
6886 && imm_expr
.X_add_number
< 0x10000)
6888 if (mask
!= M_NOR_I
)
6889 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6892 macro_build (&imm_expr
, "ori", "t,r,i",
6893 treg
, sreg
, BFD_RELOC_LO16
);
6894 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6900 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6901 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6905 switch (imm_expr
.X_add_number
)
6908 macro_build (NULL
, "nop", "");
6911 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6915 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6916 (int) imm_expr
.X_add_number
);
6919 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6920 (unsigned long) imm_expr
.X_add_number
);
6929 gas_assert (mips_opts
.micromips
);
6930 macro_build_branch_ccl (mask
, &offset_expr
,
6931 EXTRACT_OPERAND (1, BCC
, *ip
));
6938 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6944 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6949 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6956 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6958 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6962 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6963 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6964 &offset_expr
, AT
, ZERO
);
6974 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6980 /* Check for > max integer. */
6981 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
6984 /* Result is always false. */
6986 macro_build (NULL
, "nop", "");
6988 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6991 if (imm_expr
.X_op
!= O_constant
)
6992 as_bad (_("Unsupported large constant"));
6993 ++imm_expr
.X_add_number
;
6997 if (mask
== M_BGEL_I
)
6999 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7001 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
7002 &offset_expr
, sreg
);
7005 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7007 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
7008 &offset_expr
, sreg
);
7011 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
7014 /* result is always true */
7015 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
7016 macro_build (&offset_expr
, "b", "p");
7021 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7022 &offset_expr
, AT
, ZERO
);
7031 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7032 &offset_expr
, ZERO
, treg
);
7036 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7037 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7038 &offset_expr
, AT
, ZERO
);
7047 && imm_expr
.X_op
== O_constant
7048 && imm_expr
.X_add_number
== -1))
7050 if (imm_expr
.X_op
!= O_constant
)
7051 as_bad (_("Unsupported large constant"));
7052 ++imm_expr
.X_add_number
;
7056 if (mask
== M_BGEUL_I
)
7058 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7060 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7061 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7062 &offset_expr
, sreg
, ZERO
);
7067 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7068 &offset_expr
, AT
, ZERO
);
7076 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
7078 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
7082 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7083 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7084 &offset_expr
, AT
, ZERO
);
7092 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7093 &offset_expr
, sreg
, ZERO
);
7099 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7100 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7101 &offset_expr
, AT
, ZERO
);
7109 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7111 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
7115 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7116 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7117 &offset_expr
, AT
, ZERO
);
7124 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
7126 if (imm_expr
.X_op
!= O_constant
)
7127 as_bad (_("Unsupported large constant"));
7128 ++imm_expr
.X_add_number
;
7132 if (mask
== M_BLTL_I
)
7134 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7135 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7136 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7137 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7142 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7143 &offset_expr
, AT
, ZERO
);
7151 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7152 &offset_expr
, sreg
, ZERO
);
7158 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7159 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7160 &offset_expr
, AT
, ZERO
);
7169 && imm_expr
.X_op
== O_constant
7170 && imm_expr
.X_add_number
== -1))
7172 if (imm_expr
.X_op
!= O_constant
)
7173 as_bad (_("Unsupported large constant"));
7174 ++imm_expr
.X_add_number
;
7178 if (mask
== M_BLTUL_I
)
7180 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7182 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7183 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7184 &offset_expr
, sreg
, ZERO
);
7189 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7190 &offset_expr
, AT
, ZERO
);
7198 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7200 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
7204 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
7205 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7206 &offset_expr
, AT
, ZERO
);
7216 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7217 &offset_expr
, ZERO
, treg
);
7221 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7222 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7223 &offset_expr
, AT
, ZERO
);
7229 /* Use unsigned arithmetic. */
7233 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7235 as_bad (_("Unsupported large constant"));
7240 pos
= imm_expr
.X_add_number
;
7241 size
= imm2_expr
.X_add_number
;
7246 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7249 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7251 as_bad (_("Improper extract size (%lu, position %lu)"),
7252 (unsigned long) size
, (unsigned long) pos
);
7256 if (size
<= 32 && pos
< 32)
7261 else if (size
<= 32)
7271 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7278 /* Use unsigned arithmetic. */
7282 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7284 as_bad (_("Unsupported large constant"));
7289 pos
= imm_expr
.X_add_number
;
7290 size
= imm2_expr
.X_add_number
;
7295 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7298 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7300 as_bad (_("Improper insert size (%lu, position %lu)"),
7301 (unsigned long) size
, (unsigned long) pos
);
7305 if (pos
< 32 && (pos
+ size
- 1) < 32)
7320 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7321 (int) (pos
+ size
- 1));
7337 as_warn (_("Divide by zero."));
7339 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7341 macro_build (NULL
, "break", BRK_FMT
, 7);
7348 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7349 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7353 if (mips_opts
.micromips
)
7354 micromips_label_expr (&label_expr
);
7356 label_expr
.X_add_number
= 8;
7357 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7358 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7359 macro_build (NULL
, "break", BRK_FMT
, 7);
7360 if (mips_opts
.micromips
)
7361 micromips_add_label ();
7363 expr1
.X_add_number
= -1;
7365 load_register (AT
, &expr1
, dbl
);
7366 if (mips_opts
.micromips
)
7367 micromips_label_expr (&label_expr
);
7369 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7370 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7373 expr1
.X_add_number
= 1;
7374 load_register (AT
, &expr1
, dbl
);
7375 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7379 expr1
.X_add_number
= 0x80000000;
7380 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7384 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7385 /* We want to close the noreorder block as soon as possible, so
7386 that later insns are available for delay slot filling. */
7391 if (mips_opts
.micromips
)
7392 micromips_label_expr (&label_expr
);
7394 label_expr
.X_add_number
= 8;
7395 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7396 macro_build (NULL
, "nop", "");
7398 /* We want to close the noreorder block as soon as possible, so
7399 that later insns are available for delay slot filling. */
7402 macro_build (NULL
, "break", BRK_FMT
, 6);
7404 if (mips_opts
.micromips
)
7405 micromips_add_label ();
7406 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7445 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7447 as_warn (_("Divide by zero."));
7449 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7451 macro_build (NULL
, "break", BRK_FMT
, 7);
7454 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7456 if (strcmp (s2
, "mflo") == 0)
7457 move_register (dreg
, sreg
);
7459 move_register (dreg
, ZERO
);
7462 if (imm_expr
.X_op
== O_constant
7463 && imm_expr
.X_add_number
== -1
7464 && s
[strlen (s
) - 1] != 'u')
7466 if (strcmp (s2
, "mflo") == 0)
7468 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7471 move_register (dreg
, ZERO
);
7476 load_register (AT
, &imm_expr
, dbl
);
7477 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7478 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7500 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7501 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7502 /* We want to close the noreorder block as soon as possible, so
7503 that later insns are available for delay slot filling. */
7508 if (mips_opts
.micromips
)
7509 micromips_label_expr (&label_expr
);
7511 label_expr
.X_add_number
= 8;
7512 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7513 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7515 /* We want to close the noreorder block as soon as possible, so
7516 that later insns are available for delay slot filling. */
7518 macro_build (NULL
, "break", BRK_FMT
, 7);
7519 if (mips_opts
.micromips
)
7520 micromips_add_label ();
7522 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7534 /* Load the address of a symbol into a register. If breg is not
7535 zero, we then add a base register to it. */
7537 if (dbl
&& HAVE_32BIT_GPRS
)
7538 as_warn (_("dla used to load 32-bit register"));
7540 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7541 as_warn (_("la used to load 64-bit address"));
7543 if (offset_expr
.X_op
== O_constant
7544 && offset_expr
.X_add_number
>= -0x8000
7545 && offset_expr
.X_add_number
< 0x8000)
7547 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7548 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7552 if (mips_opts
.at
&& (treg
== breg
))
7562 if (offset_expr
.X_op
!= O_symbol
7563 && offset_expr
.X_op
!= O_constant
)
7565 as_bad (_("Expression too complex"));
7566 offset_expr
.X_op
= O_constant
;
7569 if (offset_expr
.X_op
== O_constant
)
7570 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7571 else if (mips_pic
== NO_PIC
)
7573 /* If this is a reference to a GP relative symbol, we want
7574 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7576 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7577 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7578 If we have a constant, we need two instructions anyhow,
7579 so we may as well always use the latter form.
7581 With 64bit address space and a usable $at we want
7582 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7583 lui $at,<sym> (BFD_RELOC_HI16_S)
7584 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7585 daddiu $at,<sym> (BFD_RELOC_LO16)
7587 daddu $tempreg,$tempreg,$at
7589 If $at is already in use, we use a path which is suboptimal
7590 on superscalar processors.
7591 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7592 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7594 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7596 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7598 For GP relative symbols in 64bit address space we can use
7599 the same sequence as in 32bit address space. */
7600 if (HAVE_64BIT_SYMBOLS
)
7602 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7603 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7605 relax_start (offset_expr
.X_add_symbol
);
7606 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7607 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7611 if (used_at
== 0 && mips_opts
.at
)
7613 macro_build (&offset_expr
, "lui", LUI_FMT
,
7614 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7615 macro_build (&offset_expr
, "lui", LUI_FMT
,
7616 AT
, BFD_RELOC_HI16_S
);
7617 macro_build (&offset_expr
, "daddiu", "t,r,j",
7618 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7619 macro_build (&offset_expr
, "daddiu", "t,r,j",
7620 AT
, AT
, BFD_RELOC_LO16
);
7621 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7622 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7627 macro_build (&offset_expr
, "lui", LUI_FMT
,
7628 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7629 macro_build (&offset_expr
, "daddiu", "t,r,j",
7630 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7631 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7632 macro_build (&offset_expr
, "daddiu", "t,r,j",
7633 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7634 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7635 macro_build (&offset_expr
, "daddiu", "t,r,j",
7636 tempreg
, tempreg
, BFD_RELOC_LO16
);
7639 if (mips_relax
.sequence
)
7644 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7645 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7647 relax_start (offset_expr
.X_add_symbol
);
7648 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7649 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7652 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7653 as_bad (_("Offset too large"));
7654 macro_build_lui (&offset_expr
, tempreg
);
7655 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7656 tempreg
, tempreg
, BFD_RELOC_LO16
);
7657 if (mips_relax
.sequence
)
7661 else if (!mips_big_got
&& !HAVE_NEWABI
)
7663 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7665 /* If this is a reference to an external symbol, and there
7666 is no constant, we want
7667 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7668 or for lca or if tempreg is PIC_CALL_REG
7669 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7670 For a local symbol, we want
7671 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7673 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7675 If we have a small constant, and this is a reference to
7676 an external symbol, we want
7677 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7679 addiu $tempreg,$tempreg,<constant>
7680 For a local symbol, we want the same instruction
7681 sequence, but we output a BFD_RELOC_LO16 reloc on the
7684 If we have a large constant, and this is a reference to
7685 an external symbol, we want
7686 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7687 lui $at,<hiconstant>
7688 addiu $at,$at,<loconstant>
7689 addu $tempreg,$tempreg,$at
7690 For a local symbol, we want the same instruction
7691 sequence, but we output a BFD_RELOC_LO16 reloc on the
7695 if (offset_expr
.X_add_number
== 0)
7697 if (mips_pic
== SVR4_PIC
7699 && (call
|| tempreg
== PIC_CALL_REG
))
7700 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7702 relax_start (offset_expr
.X_add_symbol
);
7703 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7704 lw_reloc_type
, mips_gp_register
);
7707 /* We're going to put in an addu instruction using
7708 tempreg, so we may as well insert the nop right
7713 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7714 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7716 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7717 tempreg
, tempreg
, BFD_RELOC_LO16
);
7719 /* FIXME: If breg == 0, and the next instruction uses
7720 $tempreg, then if this variant case is used an extra
7721 nop will be generated. */
7723 else if (offset_expr
.X_add_number
>= -0x8000
7724 && offset_expr
.X_add_number
< 0x8000)
7726 load_got_offset (tempreg
, &offset_expr
);
7728 add_got_offset (tempreg
, &offset_expr
);
7732 expr1
.X_add_number
= offset_expr
.X_add_number
;
7733 offset_expr
.X_add_number
=
7734 SEXT_16BIT (offset_expr
.X_add_number
);
7735 load_got_offset (tempreg
, &offset_expr
);
7736 offset_expr
.X_add_number
= expr1
.X_add_number
;
7737 /* If we are going to add in a base register, and the
7738 target register and the base register are the same,
7739 then we are using AT as a temporary register. Since
7740 we want to load the constant into AT, we add our
7741 current AT (from the global offset table) and the
7742 register into the register now, and pretend we were
7743 not using a base register. */
7747 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7752 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7756 else if (!mips_big_got
&& HAVE_NEWABI
)
7758 int add_breg_early
= 0;
7760 /* If this is a reference to an external, and there is no
7761 constant, or local symbol (*), with or without a
7763 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7764 or for lca or if tempreg is PIC_CALL_REG
7765 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7767 If we have a small constant, and this is a reference to
7768 an external symbol, we want
7769 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7770 addiu $tempreg,$tempreg,<constant>
7772 If we have a large constant, and this is a reference to
7773 an external symbol, we want
7774 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7775 lui $at,<hiconstant>
7776 addiu $at,$at,<loconstant>
7777 addu $tempreg,$tempreg,$at
7779 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7780 local symbols, even though it introduces an additional
7783 if (offset_expr
.X_add_number
)
7785 expr1
.X_add_number
= offset_expr
.X_add_number
;
7786 offset_expr
.X_add_number
= 0;
7788 relax_start (offset_expr
.X_add_symbol
);
7789 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7790 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7792 if (expr1
.X_add_number
>= -0x8000
7793 && expr1
.X_add_number
< 0x8000)
7795 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7796 tempreg
, tempreg
, BFD_RELOC_LO16
);
7798 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7800 /* If we are going to add in a base register, and the
7801 target register and the base register are the same,
7802 then we are using AT as a temporary register. Since
7803 we want to load the constant into AT, we add our
7804 current AT (from the global offset table) and the
7805 register into the register now, and pretend we were
7806 not using a base register. */
7811 gas_assert (tempreg
== AT
);
7812 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7818 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7819 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7825 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7828 offset_expr
.X_add_number
= expr1
.X_add_number
;
7830 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7831 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7834 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7835 treg
, tempreg
, breg
);
7841 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7843 relax_start (offset_expr
.X_add_symbol
);
7844 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7845 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7847 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7848 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7853 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7854 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7857 else if (mips_big_got
&& !HAVE_NEWABI
)
7860 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7861 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7862 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7864 /* This is the large GOT case. If this is a reference to an
7865 external symbol, and there is no constant, we want
7866 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7867 addu $tempreg,$tempreg,$gp
7868 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7869 or for lca or if tempreg is PIC_CALL_REG
7870 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7871 addu $tempreg,$tempreg,$gp
7872 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7873 For a local symbol, we want
7874 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7876 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7878 If we have a small constant, and this is a reference to
7879 an external symbol, we want
7880 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7881 addu $tempreg,$tempreg,$gp
7882 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7884 addiu $tempreg,$tempreg,<constant>
7885 For a local symbol, we want
7886 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7888 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7890 If we have a large constant, and this is a reference to
7891 an external symbol, we want
7892 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7893 addu $tempreg,$tempreg,$gp
7894 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7895 lui $at,<hiconstant>
7896 addiu $at,$at,<loconstant>
7897 addu $tempreg,$tempreg,$at
7898 For a local symbol, we want
7899 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7900 lui $at,<hiconstant>
7901 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7902 addu $tempreg,$tempreg,$at
7905 expr1
.X_add_number
= offset_expr
.X_add_number
;
7906 offset_expr
.X_add_number
= 0;
7907 relax_start (offset_expr
.X_add_symbol
);
7908 gpdelay
= reg_needs_delay (mips_gp_register
);
7909 if (expr1
.X_add_number
== 0 && breg
== 0
7910 && (call
|| tempreg
== PIC_CALL_REG
))
7912 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7913 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7915 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7916 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7917 tempreg
, tempreg
, mips_gp_register
);
7918 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7919 tempreg
, lw_reloc_type
, tempreg
);
7920 if (expr1
.X_add_number
== 0)
7924 /* We're going to put in an addu instruction using
7925 tempreg, so we may as well insert the nop right
7930 else if (expr1
.X_add_number
>= -0x8000
7931 && expr1
.X_add_number
< 0x8000)
7934 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7935 tempreg
, tempreg
, BFD_RELOC_LO16
);
7939 /* If we are going to add in a base register, and the
7940 target register and the base register are the same,
7941 then we are using AT as a temporary register. Since
7942 we want to load the constant into AT, we add our
7943 current AT (from the global offset table) and the
7944 register into the register now, and pretend we were
7945 not using a base register. */
7950 gas_assert (tempreg
== AT
);
7952 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7957 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7958 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7962 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7967 /* This is needed because this instruction uses $gp, but
7968 the first instruction on the main stream does not. */
7969 macro_build (NULL
, "nop", "");
7972 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7973 local_reloc_type
, mips_gp_register
);
7974 if (expr1
.X_add_number
>= -0x8000
7975 && expr1
.X_add_number
< 0x8000)
7978 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7979 tempreg
, tempreg
, BFD_RELOC_LO16
);
7980 /* FIXME: If add_number is 0, and there was no base
7981 register, the external symbol case ended with a load,
7982 so if the symbol turns out to not be external, and
7983 the next instruction uses tempreg, an unnecessary nop
7984 will be inserted. */
7990 /* We must add in the base register now, as in the
7991 external symbol case. */
7992 gas_assert (tempreg
== AT
);
7994 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7997 /* We set breg to 0 because we have arranged to add
7998 it in in both cases. */
8002 macro_build_lui (&expr1
, AT
);
8003 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8004 AT
, AT
, BFD_RELOC_LO16
);
8005 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8006 tempreg
, tempreg
, AT
);
8011 else if (mips_big_got
&& HAVE_NEWABI
)
8013 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8014 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8015 int add_breg_early
= 0;
8017 /* This is the large GOT case. If this is a reference to an
8018 external symbol, and there is no constant, we want
8019 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8020 add $tempreg,$tempreg,$gp
8021 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8022 or for lca or if tempreg is PIC_CALL_REG
8023 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8024 add $tempreg,$tempreg,$gp
8025 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8027 If we have a small constant, and this is a reference to
8028 an external symbol, we want
8029 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8030 add $tempreg,$tempreg,$gp
8031 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8032 addi $tempreg,$tempreg,<constant>
8034 If we have a large constant, and this is a reference to
8035 an external symbol, we want
8036 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8037 addu $tempreg,$tempreg,$gp
8038 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8039 lui $at,<hiconstant>
8040 addi $at,$at,<loconstant>
8041 add $tempreg,$tempreg,$at
8043 If we have NewABI, and we know it's a local symbol, we want
8044 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8045 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8046 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8048 relax_start (offset_expr
.X_add_symbol
);
8050 expr1
.X_add_number
= offset_expr
.X_add_number
;
8051 offset_expr
.X_add_number
= 0;
8053 if (expr1
.X_add_number
== 0 && breg
== 0
8054 && (call
|| tempreg
== PIC_CALL_REG
))
8056 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8057 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8059 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8060 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8061 tempreg
, tempreg
, mips_gp_register
);
8062 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8063 tempreg
, lw_reloc_type
, tempreg
);
8065 if (expr1
.X_add_number
== 0)
8067 else if (expr1
.X_add_number
>= -0x8000
8068 && expr1
.X_add_number
< 0x8000)
8070 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8071 tempreg
, tempreg
, BFD_RELOC_LO16
);
8073 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
8075 /* If we are going to add in a base register, and the
8076 target register and the base register are the same,
8077 then we are using AT as a temporary register. Since
8078 we want to load the constant into AT, we add our
8079 current AT (from the global offset table) and the
8080 register into the register now, and pretend we were
8081 not using a base register. */
8086 gas_assert (tempreg
== AT
);
8087 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8093 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8094 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
8099 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8102 offset_expr
.X_add_number
= expr1
.X_add_number
;
8103 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8104 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8105 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8106 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
8109 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8110 treg
, tempreg
, breg
);
8120 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
8124 gas_assert (!mips_opts
.micromips
);
8126 unsigned long temp
= (treg
<< 16) | (0x01);
8127 macro_build (NULL
, "c2", "C", temp
);
8132 gas_assert (!mips_opts
.micromips
);
8134 unsigned long temp
= (0x02);
8135 macro_build (NULL
, "c2", "C", temp
);
8140 gas_assert (!mips_opts
.micromips
);
8142 unsigned long temp
= (treg
<< 16) | (0x02);
8143 macro_build (NULL
, "c2", "C", temp
);
8148 gas_assert (!mips_opts
.micromips
);
8149 macro_build (NULL
, "c2", "C", 3);
8153 gas_assert (!mips_opts
.micromips
);
8155 unsigned long temp
= (treg
<< 16) | 0x03;
8156 macro_build (NULL
, "c2", "C", temp
);
8161 /* The j instruction may not be used in PIC code, since it
8162 requires an absolute address. We convert it to a b
8164 if (mips_pic
== NO_PIC
)
8165 macro_build (&offset_expr
, "j", "a");
8167 macro_build (&offset_expr
, "b", "p");
8170 /* The jal instructions must be handled as macros because when
8171 generating PIC code they expand to multi-instruction
8172 sequences. Normally they are simple instructions. */
8177 gas_assert (mips_opts
.micromips
);
8178 if (mips_opts
.insn32
)
8180 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
8190 if (mips_pic
== NO_PIC
)
8192 s
= jals
? "jalrs" : "jalr";
8193 if (mips_opts
.micromips
8194 && !mips_opts
.insn32
8196 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8197 macro_build (NULL
, s
, "mj", sreg
);
8199 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8203 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
8204 && mips_cprestore_offset
>= 0);
8206 if (sreg
!= PIC_CALL_REG
)
8207 as_warn (_("MIPS PIC call to register other than $25"));
8209 s
= ((mips_opts
.micromips
8210 && !mips_opts
.insn32
8211 && (!mips_opts
.noreorder
|| cprestore
))
8212 ? "jalrs" : "jalr");
8213 if (mips_opts
.micromips
8214 && !mips_opts
.insn32
8216 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8217 macro_build (NULL
, s
, "mj", sreg
);
8219 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8220 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
8222 if (mips_cprestore_offset
< 0)
8223 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8226 if (!mips_frame_reg_valid
)
8228 as_warn (_("No .frame pseudo-op used in PIC code"));
8229 /* Quiet this warning. */
8230 mips_frame_reg_valid
= 1;
8232 if (!mips_cprestore_valid
)
8234 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8235 /* Quiet this warning. */
8236 mips_cprestore_valid
= 1;
8238 if (mips_opts
.noreorder
)
8239 macro_build (NULL
, "nop", "");
8240 expr1
.X_add_number
= mips_cprestore_offset
;
8241 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8244 HAVE_64BIT_ADDRESSES
);
8252 gas_assert (mips_opts
.micromips
);
8253 if (mips_opts
.insn32
)
8255 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
8261 if (mips_pic
== NO_PIC
)
8262 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
8263 else if (mips_pic
== SVR4_PIC
)
8265 /* If this is a reference to an external symbol, and we are
8266 using a small GOT, we want
8267 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8271 lw $gp,cprestore($sp)
8272 The cprestore value is set using the .cprestore
8273 pseudo-op. If we are using a big GOT, we want
8274 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8276 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8280 lw $gp,cprestore($sp)
8281 If the symbol is not external, we want
8282 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8284 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8287 lw $gp,cprestore($sp)
8289 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8290 sequences above, minus nops, unless the symbol is local,
8291 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8297 relax_start (offset_expr
.X_add_symbol
);
8298 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8299 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8302 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8303 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
8309 relax_start (offset_expr
.X_add_symbol
);
8310 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8311 BFD_RELOC_MIPS_CALL_HI16
);
8312 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8313 PIC_CALL_REG
, mips_gp_register
);
8314 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8315 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8318 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8319 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
8321 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8322 PIC_CALL_REG
, PIC_CALL_REG
,
8323 BFD_RELOC_MIPS_GOT_OFST
);
8327 macro_build_jalr (&offset_expr
, 0);
8331 relax_start (offset_expr
.X_add_symbol
);
8334 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8335 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8344 gpdelay
= reg_needs_delay (mips_gp_register
);
8345 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8346 BFD_RELOC_MIPS_CALL_HI16
);
8347 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8348 PIC_CALL_REG
, mips_gp_register
);
8349 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8350 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8355 macro_build (NULL
, "nop", "");
8357 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8358 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8361 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8362 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8364 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8366 if (mips_cprestore_offset
< 0)
8367 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8370 if (!mips_frame_reg_valid
)
8372 as_warn (_("No .frame pseudo-op used in PIC code"));
8373 /* Quiet this warning. */
8374 mips_frame_reg_valid
= 1;
8376 if (!mips_cprestore_valid
)
8378 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8379 /* Quiet this warning. */
8380 mips_cprestore_valid
= 1;
8382 if (mips_opts
.noreorder
)
8383 macro_build (NULL
, "nop", "");
8384 expr1
.X_add_number
= mips_cprestore_offset
;
8385 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8388 HAVE_64BIT_ADDRESSES
);
8392 else if (mips_pic
== VXWORKS_PIC
)
8393 as_bad (_("Non-PIC jump used in PIC library"));
8501 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8509 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8540 gas_assert (!mips_opts
.micromips
);
8543 /* Itbl support may require additional care here. */
8550 /* Itbl support may require additional care here. */
8558 offbits
= (mips_opts
.micromips
? 12 : 16);
8559 /* Itbl support may require additional care here. */
8564 gas_assert (!mips_opts
.micromips
);
8567 /* Itbl support may require additional care here. */
8575 offbits
= (mips_opts
.micromips
? 12 : 16);
8582 offbits
= (mips_opts
.micromips
? 12 : 16);
8588 /* Itbl support may require additional care here. */
8596 offbits
= (mips_opts
.micromips
? 12 : 16);
8597 /* Itbl support may require additional care here. */
8604 /* Itbl support may require additional care here. */
8611 /* Itbl support may require additional care here. */
8619 offbits
= (mips_opts
.micromips
? 12 : 16);
8626 offbits
= (mips_opts
.micromips
? 12 : 16);
8633 offbits
= (mips_opts
.micromips
? 12 : 16);
8640 offbits
= (mips_opts
.micromips
? 12 : 16);
8647 offbits
= (mips_opts
.micromips
? 12 : 16);
8652 gas_assert (mips_opts
.micromips
);
8661 gas_assert (mips_opts
.micromips
);
8670 gas_assert (mips_opts
.micromips
);
8678 gas_assert (mips_opts
.micromips
);
8685 /* We don't want to use $0 as tempreg. */
8686 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
8689 tempreg
= treg
+ lp
;
8709 gas_assert (!mips_opts
.micromips
);
8712 /* Itbl support may require additional care here. */
8719 /* Itbl support may require additional care here. */
8727 offbits
= (mips_opts
.micromips
? 12 : 16);
8728 /* Itbl support may require additional care here. */
8733 gas_assert (!mips_opts
.micromips
);
8736 /* Itbl support may require additional care here. */
8744 offbits
= (mips_opts
.micromips
? 12 : 16);
8751 offbits
= (mips_opts
.micromips
? 12 : 16);
8758 offbits
= (mips_opts
.micromips
? 12 : 16);
8765 offbits
= (mips_opts
.micromips
? 12 : 16);
8771 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8772 offbits
= (mips_opts
.micromips
? 12 : 16);
8785 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8786 offbits
= (mips_opts
.micromips
? 12 : 16);
8800 /* Itbl support may require additional care here. */
8807 offbits
= (mips_opts
.micromips
? 12 : 16);
8808 /* Itbl support may require additional care here. */
8815 /* Itbl support may require additional care here. */
8820 gas_assert (!mips_opts
.micromips
);
8823 /* Itbl support may require additional care here. */
8831 offbits
= (mips_opts
.micromips
? 12 : 16);
8838 offbits
= (mips_opts
.micromips
? 12 : 16);
8843 gas_assert (mips_opts
.micromips
);
8851 gas_assert (mips_opts
.micromips
);
8859 gas_assert (mips_opts
.micromips
);
8867 gas_assert (mips_opts
.micromips
);
8876 if (offset_expr
.X_op
!= O_constant
8877 && offset_expr
.X_op
!= O_symbol
)
8879 as_bad (_("Expression too complex"));
8880 offset_expr
.X_op
= O_constant
;
8883 if (HAVE_32BIT_ADDRESSES
8884 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8888 sprintf_vma (value
, offset_expr
.X_add_number
);
8889 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8892 /* A constant expression in PIC code can be handled just as it
8893 is in non PIC code. */
8894 if (offset_expr
.X_op
== O_constant
)
8898 expr1
.X_add_number
= offset_expr
.X_add_number
;
8899 normalize_address_expr (&expr1
);
8900 if ((offbits
== 0 || offbits
== 16)
8901 && !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8903 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8904 & ~(bfd_vma
) 0xffff);
8907 else if (offbits
== 12 && !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8909 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8910 & ~(bfd_vma
) 0xfff);
8913 else if (offbits
== 9 && !IS_SEXT_9BIT_NUM (expr1
.X_add_number
))
8915 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x100)
8916 & ~(bfd_vma
) 0x1ff);
8921 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8923 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8924 tempreg
, tempreg
, breg
);
8929 if (offset_expr
.X_add_number
== 0)
8932 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8933 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8934 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8936 else if (offbits
== 16)
8937 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8939 macro_build (NULL
, s
, fmt
,
8940 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8942 else if (offbits
!= 16)
8944 /* The offset field is too narrow to be used for a low-part
8945 relocation, so load the whole address into the auxillary
8946 register. In the case of "A(b)" addresses, we first load
8947 absolute address "A" into the register and then add base
8948 register "b". In the case of "o(b)" addresses, we simply
8949 need to add 16-bit offset "o" to base register "b", and
8950 offset_reloc already contains the relocations associated
8954 load_address (tempreg
, &offset_expr
, &used_at
);
8956 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8957 tempreg
, tempreg
, breg
);
8960 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8962 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8963 expr1
.X_add_number
= 0;
8965 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8967 macro_build (NULL
, s
, fmt
,
8968 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8970 else if (mips_pic
== NO_PIC
)
8972 /* If this is a reference to a GP relative symbol, and there
8973 is no base register, we want
8974 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8975 Otherwise, if there is no base register, we want
8976 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8977 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8978 If we have a constant, we need two instructions anyhow,
8979 so we always use the latter form.
8981 If we have a base register, and this is a reference to a
8982 GP relative symbol, we want
8983 addu $tempreg,$breg,$gp
8984 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8986 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8987 addu $tempreg,$tempreg,$breg
8988 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8989 With a constant we always use the latter case.
8991 With 64bit address space and no base register and $at usable,
8993 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8994 lui $at,<sym> (BFD_RELOC_HI16_S)
8995 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8998 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8999 If we have a base register, we want
9000 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9001 lui $at,<sym> (BFD_RELOC_HI16_S)
9002 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9006 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9008 Without $at we can't generate the optimal path for superscalar
9009 processors here since this would require two temporary registers.
9010 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9011 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9013 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9015 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9016 If we have a base register, we want
9017 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9018 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9020 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9022 daddu $tempreg,$tempreg,$breg
9023 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9025 For GP relative symbols in 64bit address space we can use
9026 the same sequence as in 32bit address space. */
9027 if (HAVE_64BIT_SYMBOLS
)
9029 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9030 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9032 relax_start (offset_expr
.X_add_symbol
);
9035 macro_build (&offset_expr
, s
, fmt
, treg
,
9036 BFD_RELOC_GPREL16
, mips_gp_register
);
9040 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9041 tempreg
, breg
, mips_gp_register
);
9042 macro_build (&offset_expr
, s
, fmt
, treg
,
9043 BFD_RELOC_GPREL16
, tempreg
);
9048 if (used_at
== 0 && mips_opts
.at
)
9050 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9051 BFD_RELOC_MIPS_HIGHEST
);
9052 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
9054 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9055 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9057 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
9058 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9059 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9060 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
9066 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9067 BFD_RELOC_MIPS_HIGHEST
);
9068 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9069 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9070 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9071 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9072 tempreg
, BFD_RELOC_HI16_S
);
9073 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9075 macro_build (NULL
, "daddu", "d,v,t",
9076 tempreg
, tempreg
, breg
);
9077 macro_build (&offset_expr
, s
, fmt
, treg
,
9078 BFD_RELOC_LO16
, tempreg
);
9081 if (mips_relax
.sequence
)
9088 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9089 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9091 relax_start (offset_expr
.X_add_symbol
);
9092 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
9096 macro_build_lui (&offset_expr
, tempreg
);
9097 macro_build (&offset_expr
, s
, fmt
, treg
,
9098 BFD_RELOC_LO16
, tempreg
);
9099 if (mips_relax
.sequence
)
9104 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9105 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9107 relax_start (offset_expr
.X_add_symbol
);
9108 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9109 tempreg
, breg
, mips_gp_register
);
9110 macro_build (&offset_expr
, s
, fmt
, treg
,
9111 BFD_RELOC_GPREL16
, tempreg
);
9114 macro_build_lui (&offset_expr
, tempreg
);
9115 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9116 tempreg
, tempreg
, breg
);
9117 macro_build (&offset_expr
, s
, fmt
, treg
,
9118 BFD_RELOC_LO16
, tempreg
);
9119 if (mips_relax
.sequence
)
9123 else if (!mips_big_got
)
9125 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9127 /* If this is a reference to an external symbol, we want
9128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9130 <op> $treg,0($tempreg)
9132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9134 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9135 <op> $treg,0($tempreg)
9138 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9139 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9141 If there is a base register, we add it to $tempreg before
9142 the <op>. If there is a constant, we stick it in the
9143 <op> instruction. We don't handle constants larger than
9144 16 bits, because we have no way to load the upper 16 bits
9145 (actually, we could handle them for the subset of cases
9146 in which we are not using $at). */
9147 gas_assert (offset_expr
.X_op
== O_symbol
);
9150 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9151 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9153 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9154 tempreg
, tempreg
, breg
);
9155 macro_build (&offset_expr
, s
, fmt
, treg
,
9156 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9159 expr1
.X_add_number
= offset_expr
.X_add_number
;
9160 offset_expr
.X_add_number
= 0;
9161 if (expr1
.X_add_number
< -0x8000
9162 || expr1
.X_add_number
>= 0x8000)
9163 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9164 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9165 lw_reloc_type
, mips_gp_register
);
9167 relax_start (offset_expr
.X_add_symbol
);
9169 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9170 tempreg
, BFD_RELOC_LO16
);
9173 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9174 tempreg
, tempreg
, breg
);
9175 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9177 else if (mips_big_got
&& !HAVE_NEWABI
)
9181 /* If this is a reference to an external symbol, we want
9182 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9183 addu $tempreg,$tempreg,$gp
9184 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9185 <op> $treg,0($tempreg)
9187 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9189 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9190 <op> $treg,0($tempreg)
9191 If there is a base register, we add it to $tempreg before
9192 the <op>. If there is a constant, we stick it in the
9193 <op> instruction. We don't handle constants larger than
9194 16 bits, because we have no way to load the upper 16 bits
9195 (actually, we could handle them for the subset of cases
9196 in which we are not using $at). */
9197 gas_assert (offset_expr
.X_op
== O_symbol
);
9198 expr1
.X_add_number
= offset_expr
.X_add_number
;
9199 offset_expr
.X_add_number
= 0;
9200 if (expr1
.X_add_number
< -0x8000
9201 || expr1
.X_add_number
>= 0x8000)
9202 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9203 gpdelay
= reg_needs_delay (mips_gp_register
);
9204 relax_start (offset_expr
.X_add_symbol
);
9205 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9206 BFD_RELOC_MIPS_GOT_HI16
);
9207 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9209 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9210 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9213 macro_build (NULL
, "nop", "");
9214 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9215 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9217 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9218 tempreg
, BFD_RELOC_LO16
);
9222 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9223 tempreg
, tempreg
, breg
);
9224 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9226 else if (mips_big_got
&& HAVE_NEWABI
)
9228 /* If this is a reference to an external symbol, we want
9229 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9230 add $tempreg,$tempreg,$gp
9231 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9232 <op> $treg,<ofst>($tempreg)
9233 Otherwise, for local symbols, we want:
9234 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9235 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9236 gas_assert (offset_expr
.X_op
== O_symbol
);
9237 expr1
.X_add_number
= offset_expr
.X_add_number
;
9238 offset_expr
.X_add_number
= 0;
9239 if (expr1
.X_add_number
< -0x8000
9240 || expr1
.X_add_number
>= 0x8000)
9241 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9242 relax_start (offset_expr
.X_add_symbol
);
9243 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9244 BFD_RELOC_MIPS_GOT_HI16
);
9245 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9247 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9248 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9250 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9251 tempreg
, tempreg
, breg
);
9252 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9255 offset_expr
.X_add_number
= expr1
.X_add_number
;
9256 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9257 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9259 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9260 tempreg
, tempreg
, breg
);
9261 macro_build (&offset_expr
, s
, fmt
, treg
,
9262 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9271 gas_assert (mips_opts
.micromips
);
9272 gas_assert (mips_opts
.insn32
);
9274 macro_build (NULL
, "jr", "s", RA
);
9275 expr1
.X_add_number
= EXTRACT_OPERAND (1, IMMP
, *ip
) << 2;
9276 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
9281 gas_assert (mips_opts
.micromips
);
9282 gas_assert (mips_opts
.insn32
);
9283 macro_build (NULL
, "jr", "s", sreg
);
9284 if (mips_opts
.noreorder
)
9285 macro_build (NULL
, "nop", "");
9290 load_register (treg
, &imm_expr
, 0);
9294 load_register (treg
, &imm_expr
, 1);
9298 if (imm_expr
.X_op
== O_constant
)
9301 load_register (AT
, &imm_expr
, 0);
9302 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9307 gas_assert (offset_expr
.X_op
== O_symbol
9308 && strcmp (segment_name (S_GET_SEGMENT
9309 (offset_expr
.X_add_symbol
)),
9311 && offset_expr
.X_add_number
== 0);
9312 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
9313 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9318 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9319 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9320 order 32 bits of the value and the low order 32 bits are either
9321 zero or in OFFSET_EXPR. */
9322 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9324 if (HAVE_64BIT_GPRS
)
9325 load_register (treg
, &imm_expr
, 1);
9330 if (target_big_endian
)
9342 load_register (hreg
, &imm_expr
, 0);
9345 if (offset_expr
.X_op
== O_absent
)
9346 move_register (lreg
, 0);
9349 gas_assert (offset_expr
.X_op
== O_constant
);
9350 load_register (lreg
, &offset_expr
, 0);
9357 /* We know that sym is in the .rdata section. First we get the
9358 upper 16 bits of the address. */
9359 if (mips_pic
== NO_PIC
)
9361 macro_build_lui (&offset_expr
, AT
);
9366 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9367 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9371 /* Now we load the register(s). */
9372 if (HAVE_64BIT_GPRS
)
9375 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9380 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9383 /* FIXME: How in the world do we deal with the possible
9385 offset_expr
.X_add_number
+= 4;
9386 macro_build (&offset_expr
, "lw", "t,o(b)",
9387 treg
+ 1, BFD_RELOC_LO16
, AT
);
9393 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9394 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9395 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9396 the value and the low order 32 bits are either zero or in
9398 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9401 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
9402 if (HAVE_64BIT_FPRS
)
9404 gas_assert (HAVE_64BIT_GPRS
);
9405 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
9409 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
9410 if (offset_expr
.X_op
== O_absent
)
9411 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
9414 gas_assert (offset_expr
.X_op
== O_constant
);
9415 load_register (AT
, &offset_expr
, 0);
9416 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9422 gas_assert (offset_expr
.X_op
== O_symbol
9423 && offset_expr
.X_add_number
== 0);
9424 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
9425 if (strcmp (s
, ".lit8") == 0)
9427 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9429 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
9430 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9433 breg
= mips_gp_register
;
9434 r
= BFD_RELOC_MIPS_LITERAL
;
9439 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
9441 if (mips_pic
!= NO_PIC
)
9442 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9443 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9446 /* FIXME: This won't work for a 64 bit address. */
9447 macro_build_lui (&offset_expr
, AT
);
9450 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9452 macro_build (&offset_expr
, "ldc1", "T,o(b)",
9453 treg
, BFD_RELOC_LO16
, AT
);
9462 /* Even on a big endian machine $fn comes before $fn+1. We have
9463 to adjust when loading from memory. */
9466 gas_assert (!mips_opts
.micromips
);
9467 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9468 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9469 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
9470 /* FIXME: A possible overflow which I don't know how to deal
9472 offset_expr
.X_add_number
+= 4;
9473 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9474 target_big_endian
? treg
: treg
+ 1, r
, breg
);
9478 gas_assert (!mips_opts
.micromips
);
9479 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9480 /* Even on a big endian machine $fn comes before $fn+1. We have
9481 to adjust when storing to memory. */
9482 macro_build (&offset_expr
, "swc1", "T,o(b)",
9483 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
9484 offset_expr
.X_add_number
+= 4;
9485 macro_build (&offset_expr
, "swc1", "T,o(b)",
9486 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
9490 gas_assert (!mips_opts
.micromips
);
9492 * The MIPS assembler seems to check for X_add_number not
9493 * being double aligned and generating:
9496 * addiu at,at,%lo(foo+1)
9499 * But, the resulting address is the same after relocation so why
9500 * generate the extra instruction?
9502 /* Itbl support may require additional care here. */
9505 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9514 gas_assert (!mips_opts
.micromips
);
9515 /* Itbl support may require additional care here. */
9518 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9538 if (HAVE_64BIT_GPRS
)
9548 if (HAVE_64BIT_GPRS
)
9556 if (offset_expr
.X_op
!= O_symbol
9557 && offset_expr
.X_op
!= O_constant
)
9559 as_bad (_("Expression too complex"));
9560 offset_expr
.X_op
= O_constant
;
9563 if (HAVE_32BIT_ADDRESSES
9564 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9568 sprintf_vma (value
, offset_expr
.X_add_number
);
9569 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9572 /* Even on a big endian machine $fn comes before $fn+1. We have
9573 to adjust when loading from memory. We set coproc if we must
9574 load $fn+1 first. */
9575 /* Itbl support may require additional care here. */
9576 if (!target_big_endian
)
9579 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9581 /* If this is a reference to a GP relative symbol, we want
9582 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9583 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9584 If we have a base register, we use this
9586 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9587 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9588 If this is not a GP relative symbol, we want
9589 lui $at,<sym> (BFD_RELOC_HI16_S)
9590 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9591 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9592 If there is a base register, we add it to $at after the
9593 lui instruction. If there is a constant, we always use
9595 if (offset_expr
.X_op
== O_symbol
9596 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9597 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9599 relax_start (offset_expr
.X_add_symbol
);
9602 tempreg
= mips_gp_register
;
9606 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9607 AT
, breg
, mips_gp_register
);
9612 /* Itbl support may require additional care here. */
9613 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9614 BFD_RELOC_GPREL16
, tempreg
);
9615 offset_expr
.X_add_number
+= 4;
9617 /* Set mips_optimize to 2 to avoid inserting an
9619 hold_mips_optimize
= mips_optimize
;
9621 /* Itbl support may require additional care here. */
9622 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9623 BFD_RELOC_GPREL16
, tempreg
);
9624 mips_optimize
= hold_mips_optimize
;
9628 offset_expr
.X_add_number
-= 4;
9631 macro_build_lui (&offset_expr
, AT
);
9633 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9634 /* Itbl support may require additional care here. */
9635 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9636 BFD_RELOC_LO16
, AT
);
9637 /* FIXME: How do we handle overflow here? */
9638 offset_expr
.X_add_number
+= 4;
9639 /* Itbl support may require additional care here. */
9640 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9641 BFD_RELOC_LO16
, AT
);
9642 if (mips_relax
.sequence
)
9645 else if (!mips_big_got
)
9647 /* If this is a reference to an external symbol, we want
9648 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9653 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9655 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9656 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9657 If there is a base register we add it to $at before the
9658 lwc1 instructions. If there is a constant we include it
9659 in the lwc1 instructions. */
9661 expr1
.X_add_number
= offset_expr
.X_add_number
;
9662 if (expr1
.X_add_number
< -0x8000
9663 || expr1
.X_add_number
>= 0x8000 - 4)
9664 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9665 load_got_offset (AT
, &offset_expr
);
9668 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9670 /* Set mips_optimize to 2 to avoid inserting an undesired
9672 hold_mips_optimize
= mips_optimize
;
9675 /* Itbl support may require additional care here. */
9676 relax_start (offset_expr
.X_add_symbol
);
9677 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9678 BFD_RELOC_LO16
, AT
);
9679 expr1
.X_add_number
+= 4;
9680 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9681 BFD_RELOC_LO16
, AT
);
9683 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9684 BFD_RELOC_LO16
, AT
);
9685 offset_expr
.X_add_number
+= 4;
9686 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9687 BFD_RELOC_LO16
, AT
);
9690 mips_optimize
= hold_mips_optimize
;
9692 else if (mips_big_got
)
9696 /* If this is a reference to an external symbol, we want
9697 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9699 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9704 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9706 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9707 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9708 If there is a base register we add it to $at before the
9709 lwc1 instructions. If there is a constant we include it
9710 in the lwc1 instructions. */
9712 expr1
.X_add_number
= offset_expr
.X_add_number
;
9713 offset_expr
.X_add_number
= 0;
9714 if (expr1
.X_add_number
< -0x8000
9715 || expr1
.X_add_number
>= 0x8000 - 4)
9716 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9717 gpdelay
= reg_needs_delay (mips_gp_register
);
9718 relax_start (offset_expr
.X_add_symbol
);
9719 macro_build (&offset_expr
, "lui", LUI_FMT
,
9720 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9721 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9722 AT
, AT
, mips_gp_register
);
9723 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9724 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9727 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9728 /* Itbl support may require additional care here. */
9729 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9730 BFD_RELOC_LO16
, AT
);
9731 expr1
.X_add_number
+= 4;
9733 /* Set mips_optimize to 2 to avoid inserting an undesired
9735 hold_mips_optimize
= mips_optimize
;
9737 /* Itbl support may require additional care here. */
9738 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9739 BFD_RELOC_LO16
, AT
);
9740 mips_optimize
= hold_mips_optimize
;
9741 expr1
.X_add_number
-= 4;
9744 offset_expr
.X_add_number
= expr1
.X_add_number
;
9746 macro_build (NULL
, "nop", "");
9747 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9748 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9751 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9752 /* Itbl support may require additional care here. */
9753 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9754 BFD_RELOC_LO16
, AT
);
9755 offset_expr
.X_add_number
+= 4;
9757 /* Set mips_optimize to 2 to avoid inserting an undesired
9759 hold_mips_optimize
= mips_optimize
;
9761 /* Itbl support may require additional care here. */
9762 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9763 BFD_RELOC_LO16
, AT
);
9764 mips_optimize
= hold_mips_optimize
;
9773 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9776 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9778 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9779 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9781 if (!HAVE_64BIT_GPRS
)
9783 offset_expr
.X_add_number
+= 4;
9784 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9785 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9806 /* New code added to support COPZ instructions.
9807 This code builds table entries out of the macros in mip_opcodes.
9808 R4000 uses interlocks to handle coproc delays.
9809 Other chips (like the R3000) require nops to be inserted for delays.
9811 FIXME: Currently, we require that the user handle delays.
9812 In order to fill delay slots for non-interlocked chips,
9813 we must have a way to specify delays based on the coprocessor.
9814 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9815 What are the side-effects of the cop instruction?
9816 What cache support might we have and what are its effects?
9817 Both coprocessor & memory require delays. how long???
9818 What registers are read/set/modified?
9820 If an itbl is provided to interpret cop instructions,
9821 this knowledge can be encoded in the itbl spec. */
9835 gas_assert (!mips_opts
.micromips
);
9836 /* For now we just do C (same as Cz). The parameter will be
9837 stored in insn_opcode by mips_ip. */
9838 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9842 move_register (dreg
, sreg
);
9846 gas_assert (mips_opts
.micromips
);
9847 gas_assert (mips_opts
.insn32
);
9848 dreg
= micromips_to_32_reg_h_map1
[EXTRACT_OPERAND (1, MH
, *ip
)];
9849 breg
= micromips_to_32_reg_h_map2
[EXTRACT_OPERAND (1, MH
, *ip
)];
9850 sreg
= micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
9851 treg
= micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
9852 move_register (dreg
, sreg
);
9853 move_register (breg
, treg
);
9859 if (mips_opts
.arch
== CPU_R5900
)
9861 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9865 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9866 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9873 /* The MIPS assembler some times generates shifts and adds. I'm
9874 not trying to be that fancy. GCC should do this for us
9877 load_register (AT
, &imm_expr
, dbl
);
9878 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9879 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9895 load_register (AT
, &imm_expr
, dbl
);
9896 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9897 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9898 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9899 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9901 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9904 if (mips_opts
.micromips
)
9905 micromips_label_expr (&label_expr
);
9907 label_expr
.X_add_number
= 8;
9908 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9909 macro_build (NULL
, "nop", "");
9910 macro_build (NULL
, "break", BRK_FMT
, 6);
9911 if (mips_opts
.micromips
)
9912 micromips_add_label ();
9915 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9931 load_register (AT
, &imm_expr
, dbl
);
9932 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9933 sreg
, imm
? AT
: treg
);
9934 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9935 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9937 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9940 if (mips_opts
.micromips
)
9941 micromips_label_expr (&label_expr
);
9943 label_expr
.X_add_number
= 8;
9944 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9945 macro_build (NULL
, "nop", "");
9946 macro_build (NULL
, "break", BRK_FMT
, 6);
9947 if (mips_opts
.micromips
)
9948 micromips_add_label ();
9954 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9965 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9966 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9970 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9971 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9972 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9973 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9977 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9988 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9989 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9993 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9994 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9995 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9996 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10005 if (imm_expr
.X_op
!= O_constant
)
10006 as_bad (_("Improper rotate count"));
10007 rot
= imm_expr
.X_add_number
& 0x3f;
10008 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10010 rot
= (64 - rot
) & 0x3f;
10012 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10014 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10019 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10022 l
= (rot
< 0x20) ? "dsll" : "dsll32";
10023 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
10026 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
10027 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10028 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10036 if (imm_expr
.X_op
!= O_constant
)
10037 as_bad (_("Improper rotate count"));
10038 rot
= imm_expr
.X_add_number
& 0x1f;
10039 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10041 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
10046 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10050 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
10051 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10052 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10057 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10059 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
10063 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
10064 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
10065 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
10066 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10070 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10072 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
10076 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10077 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
10078 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
10079 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10088 if (imm_expr
.X_op
!= O_constant
)
10089 as_bad (_("Improper rotate count"));
10090 rot
= imm_expr
.X_add_number
& 0x3f;
10091 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10094 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10096 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10101 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10104 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
10105 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
10108 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
10109 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10110 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10118 if (imm_expr
.X_op
!= O_constant
)
10119 as_bad (_("Improper rotate count"));
10120 rot
= imm_expr
.X_add_number
& 0x1f;
10121 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10123 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
10128 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10132 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
10133 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10134 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10140 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
10141 else if (treg
== 0)
10142 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10145 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10146 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10151 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10153 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10158 as_warn (_("Instruction %s: result is always false"),
10159 ip
->insn_mo
->name
);
10160 move_register (dreg
, 0);
10163 if (CPU_HAS_SEQ (mips_opts
.arch
)
10164 && -512 <= imm_expr
.X_add_number
10165 && imm_expr
.X_add_number
< 512)
10167 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
10168 (int) imm_expr
.X_add_number
);
10171 if (imm_expr
.X_op
== O_constant
10172 && imm_expr
.X_add_number
>= 0
10173 && imm_expr
.X_add_number
< 0x10000)
10175 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10177 else if (imm_expr
.X_op
== O_constant
10178 && imm_expr
.X_add_number
> -0x8000
10179 && imm_expr
.X_add_number
< 0)
10181 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10182 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10183 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10185 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10188 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10189 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
10194 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10195 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10198 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10201 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
10207 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
10208 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10211 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
10213 if (imm_expr
.X_op
== O_constant
10214 && imm_expr
.X_add_number
>= -0x8000
10215 && imm_expr
.X_add_number
< 0x8000)
10217 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
10218 dreg
, sreg
, BFD_RELOC_LO16
);
10222 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10223 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
10227 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10230 case M_SGT
: /* sreg > treg <==> treg < sreg */
10236 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10239 case M_SGT_I
: /* sreg > I <==> I < sreg */
10246 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10247 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10250 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10256 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10257 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10260 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10267 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10268 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10269 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10273 if (imm_expr
.X_op
== O_constant
10274 && imm_expr
.X_add_number
>= -0x8000
10275 && imm_expr
.X_add_number
< 0x8000)
10277 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10281 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10282 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
10286 if (imm_expr
.X_op
== O_constant
10287 && imm_expr
.X_add_number
>= -0x8000
10288 && imm_expr
.X_add_number
< 0x8000)
10290 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
10295 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10296 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
10301 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
10302 else if (treg
== 0)
10303 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10306 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10307 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10312 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10314 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10319 as_warn (_("Instruction %s: result is always true"),
10320 ip
->insn_mo
->name
);
10321 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
10322 dreg
, 0, BFD_RELOC_LO16
);
10325 if (CPU_HAS_SEQ (mips_opts
.arch
)
10326 && -512 <= imm_expr
.X_add_number
10327 && imm_expr
.X_add_number
< 512)
10329 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
10330 (int) imm_expr
.X_add_number
);
10333 if (imm_expr
.X_op
== O_constant
10334 && imm_expr
.X_add_number
>= 0
10335 && imm_expr
.X_add_number
< 0x10000)
10337 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10339 else if (imm_expr
.X_op
== O_constant
10340 && imm_expr
.X_add_number
> -0x8000
10341 && imm_expr
.X_add_number
< 0)
10343 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10344 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10345 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10347 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10350 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10351 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
10356 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10357 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10360 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10375 if (!mips_opts
.micromips
)
10377 if (imm_expr
.X_op
== O_constant
10378 && imm_expr
.X_add_number
> -0x200
10379 && imm_expr
.X_add_number
<= 0x200)
10381 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
10390 if (imm_expr
.X_op
== O_constant
10391 && imm_expr
.X_add_number
> -0x8000
10392 && imm_expr
.X_add_number
<= 0x8000)
10394 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10395 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10400 load_register (AT
, &imm_expr
, dbl
);
10401 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
10423 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10424 macro_build (NULL
, s
, "s,t", sreg
, AT
);
10429 gas_assert (!mips_opts
.micromips
);
10430 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
10432 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
10433 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
10436 * Is the double cfc1 instruction a bug in the mips assembler;
10437 * or is there a reason for it?
10439 start_noreorder ();
10440 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10441 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10442 macro_build (NULL
, "nop", "");
10443 expr1
.X_add_number
= 3;
10444 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
10445 expr1
.X_add_number
= 2;
10446 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
10447 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
10448 macro_build (NULL
, "nop", "");
10449 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
10451 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
10452 macro_build (NULL
, "nop", "");
10475 offbits
= (mips_opts
.micromips
? 12 : 16);
10483 offbits
= (mips_opts
.micromips
? 12 : 16);
10499 offbits
= (mips_opts
.micromips
? 12 : 16);
10508 offbits
= (mips_opts
.micromips
? 12 : 16);
10513 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
10514 as_bad (_("Operand overflow"));
10517 expr1
.X_add_number
= 0;
10522 load_address (tempreg
, ep
, &used_at
);
10524 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10525 tempreg
, tempreg
, breg
);
10530 else if (offbits
== 12
10531 && (offset_expr
.X_op
!= O_constant
10532 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
10533 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
10537 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
10538 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10543 else if (!ust
&& treg
== breg
)
10554 if (!target_big_endian
)
10555 ep
->X_add_number
+= off
;
10557 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10559 macro_build (NULL
, s
, "t,~(b)",
10560 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10562 if (!target_big_endian
)
10563 ep
->X_add_number
-= off
;
10565 ep
->X_add_number
+= off
;
10567 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10569 macro_build (NULL
, s2
, "t,~(b)",
10570 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10572 /* If necessary, move the result in tempreg to the final destination. */
10573 if (!ust
&& treg
!= tempreg
)
10575 /* Protect second load's delay slot. */
10577 move_register (treg
, tempreg
);
10583 if (target_big_endian
== ust
)
10584 ep
->X_add_number
+= off
;
10585 tempreg
= ust
|| ab
? treg
: AT
;
10586 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10588 /* For halfword transfers we need a temporary register to shuffle
10589 bytes. Unfortunately for M_USH_A we have none available before
10590 the next store as AT holds the base address. We deal with this
10591 case by clobbering TREG and then restoring it as with ULH. */
10592 tempreg
= ust
== ab
? treg
: AT
;
10594 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10596 if (target_big_endian
== ust
)
10597 ep
->X_add_number
-= off
;
10599 ep
->X_add_number
+= off
;
10600 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10602 /* For M_USH_A re-retrieve the LSB. */
10605 if (target_big_endian
)
10606 ep
->X_add_number
+= off
;
10608 ep
->X_add_number
-= off
;
10609 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
10611 /* For ULH and M_USH_A OR the LSB in. */
10614 tempreg
= !ab
? AT
: treg
;
10615 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10616 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10621 /* FIXME: Check if this is one of the itbl macros, since they
10622 are added dynamically. */
10623 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10626 if (!mips_opts
.at
&& used_at
)
10627 as_bad (_("Macro used $at after \".set noat\""));
10630 /* Implement macros in mips16 mode. */
10633 mips16_macro (struct mips_cl_insn
*ip
)
10636 int xreg
, yreg
, zreg
, tmp
;
10639 const char *s
, *s2
, *s3
;
10641 mask
= ip
->insn_mo
->mask
;
10643 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10644 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10645 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10647 expr1
.X_op
= O_constant
;
10648 expr1
.X_op_symbol
= NULL
;
10649 expr1
.X_add_symbol
= NULL
;
10650 expr1
.X_add_number
= 1;
10669 start_noreorder ();
10670 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10671 expr1
.X_add_number
= 2;
10672 macro_build (&expr1
, "bnez", "x,p", yreg
);
10673 macro_build (NULL
, "break", "6", 7);
10675 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10676 since that causes an overflow. We should do that as well,
10677 but I don't see how to do the comparisons without a temporary
10680 macro_build (NULL
, s
, "x", zreg
);
10699 start_noreorder ();
10700 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10701 expr1
.X_add_number
= 2;
10702 macro_build (&expr1
, "bnez", "x,p", yreg
);
10703 macro_build (NULL
, "break", "6", 7);
10705 macro_build (NULL
, s2
, "x", zreg
);
10711 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10712 macro_build (NULL
, "mflo", "x", zreg
);
10720 if (imm_expr
.X_op
!= O_constant
)
10721 as_bad (_("Unsupported large constant"));
10722 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10723 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10727 if (imm_expr
.X_op
!= O_constant
)
10728 as_bad (_("Unsupported large constant"));
10729 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10730 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10734 if (imm_expr
.X_op
!= O_constant
)
10735 as_bad (_("Unsupported large constant"));
10736 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10737 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10759 goto do_reverse_branch
;
10763 goto do_reverse_branch
;
10775 goto do_reverse_branch
;
10786 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10787 macro_build (&offset_expr
, s2
, "p");
10814 goto do_addone_branch_i
;
10819 goto do_addone_branch_i
;
10834 goto do_addone_branch_i
;
10840 do_addone_branch_i
:
10841 if (imm_expr
.X_op
!= O_constant
)
10842 as_bad (_("Unsupported large constant"));
10843 ++imm_expr
.X_add_number
;
10846 macro_build (&imm_expr
, s
, s3
, xreg
);
10847 macro_build (&offset_expr
, s2
, "p");
10851 expr1
.X_add_number
= 0;
10852 macro_build (&expr1
, "slti", "x,8", yreg
);
10854 move_register (xreg
, yreg
);
10855 expr1
.X_add_number
= 2;
10856 macro_build (&expr1
, "bteqz", "p");
10857 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10861 /* For consistency checking, verify that all bits are specified either
10862 by the match/mask part of the instruction definition, or by the
10865 validate_mips_insn (const struct mips_opcode
*opc
)
10867 const char *p
= opc
->args
;
10869 unsigned long used_bits
= opc
->mask
;
10871 if ((used_bits
& opc
->match
) != opc
->match
)
10873 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10874 opc
->name
, opc
->args
);
10877 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10887 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10888 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10889 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10890 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10891 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10892 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10893 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10894 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10895 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10896 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10897 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10899 case 'J': USE_BITS (OP_MASK_CODE10
, OP_SH_CODE10
); break;
10900 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10901 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10902 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10903 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10904 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10905 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10906 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10907 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10908 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10909 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10910 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10911 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10912 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10913 case 'i': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10914 case 'j': USE_BITS (OP_MASK_EVAOFFSET
, OP_SH_EVAOFFSET
); break;
10917 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10918 c
, opc
->name
, opc
->args
);
10922 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10923 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10925 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10926 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10927 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10928 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10930 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10931 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10933 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10934 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10936 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10937 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10938 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10939 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10940 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10941 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10942 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10943 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10944 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10945 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10946 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10947 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10948 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10949 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10950 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10951 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10952 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10954 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10955 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10956 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10957 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10959 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10960 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10961 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10962 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10963 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10964 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10965 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10966 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10967 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10970 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10971 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10972 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10973 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10974 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10975 case '1': USE_BITS (OP_MASK_STYPE
, OP_SH_STYPE
); break;
10976 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10977 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10978 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10979 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10980 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10981 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10982 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10983 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10984 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10985 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10986 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10987 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10988 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10989 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10990 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10991 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10992 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10993 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10994 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10996 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10997 c
, opc
->name
, opc
->args
);
11001 if (used_bits
!= 0xffffffff)
11003 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
11004 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
11010 /* For consistency checking, verify that the length implied matches the
11011 major opcode and that all bits are specified either by the match/mask
11012 part of the instruction definition, or by the operand list. */
11015 validate_micromips_insn (const struct mips_opcode
*opc
)
11017 unsigned long match
= opc
->match
;
11018 unsigned long mask
= opc
->mask
;
11019 const char *p
= opc
->args
;
11020 unsigned long insn_bits
;
11021 unsigned long used_bits
;
11022 unsigned long major
;
11023 unsigned int length
;
11027 if ((mask
& match
) != match
)
11029 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
11030 opc
->name
, opc
->args
);
11033 length
= micromips_insn_length (opc
);
11034 if (length
!= 2 && length
!= 4)
11036 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
11037 "%s %s"), length
, opc
->name
, opc
->args
);
11040 major
= match
>> (10 + 8 * (length
- 2));
11041 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
11042 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
11044 as_bad (_("Internal error: bad microMIPS opcode "
11045 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
11049 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
11050 insn_bits
= 1 << 4 * length
;
11051 insn_bits
<<= 4 * length
;
11054 #define USE_BITS(field) \
11055 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
11066 case 'A': USE_BITS (EXTLSB
); break;
11067 case 'B': USE_BITS (INSMSB
); break;
11068 case 'C': USE_BITS (EXTMSBD
); break;
11069 case 'E': USE_BITS (EXTLSB
); break;
11070 case 'F': USE_BITS (INSMSB
); break;
11071 case 'G': USE_BITS (EXTMSBD
); break;
11072 case 'H': USE_BITS (EXTMSBD
); break;
11073 case 'i': USE_BITS (TARGET
); break;
11074 case 'j': USE_BITS (EVAOFFSET
); break;
11076 as_bad (_("Internal error: bad mips opcode "
11077 "(unknown extension operand type `%c%c'): %s %s"),
11078 e
, c
, opc
->name
, opc
->args
);
11086 case 'A': USE_BITS (IMMA
); break;
11087 case 'B': USE_BITS (IMMB
); break;
11088 case 'C': USE_BITS (IMMC
); break;
11089 case 'D': USE_BITS (IMMD
); break;
11090 case 'E': USE_BITS (IMME
); break;
11091 case 'F': USE_BITS (IMMF
); break;
11092 case 'G': USE_BITS (IMMG
); break;
11093 case 'H': USE_BITS (IMMH
); break;
11094 case 'I': USE_BITS (IMMI
); break;
11095 case 'J': USE_BITS (IMMJ
); break;
11096 case 'L': USE_BITS (IMML
); break;
11097 case 'M': USE_BITS (IMMM
); break;
11098 case 'N': USE_BITS (IMMN
); break;
11099 case 'O': USE_BITS (IMMO
); break;
11100 case 'P': USE_BITS (IMMP
); break;
11101 case 'Q': USE_BITS (IMMQ
); break;
11102 case 'U': USE_BITS (IMMU
); break;
11103 case 'W': USE_BITS (IMMW
); break;
11104 case 'X': USE_BITS (IMMX
); break;
11105 case 'Y': USE_BITS (IMMY
); break;
11108 case 'b': USE_BITS (MB
); break;
11109 case 'c': USE_BITS (MC
); break;
11110 case 'd': USE_BITS (MD
); break;
11111 case 'e': USE_BITS (ME
); break;
11112 case 'f': USE_BITS (MF
); break;
11113 case 'g': USE_BITS (MG
); break;
11114 case 'h': USE_BITS (MH
); break;
11115 case 'j': USE_BITS (MJ
); break;
11116 case 'l': USE_BITS (ML
); break;
11117 case 'm': USE_BITS (MM
); break;
11118 case 'n': USE_BITS (MN
); break;
11119 case 'p': USE_BITS (MP
); break;
11120 case 'q': USE_BITS (MQ
); break;
11128 as_bad (_("Internal error: bad mips opcode "
11129 "(unknown extension operand type `%c%c'): %s %s"),
11130 e
, c
, opc
->name
, opc
->args
);
11134 case '.': USE_BITS (OFFSET10
); break;
11135 case '1': USE_BITS (STYPE
); break;
11136 case '2': USE_BITS (BP
); break;
11137 case '3': USE_BITS (SA3
); break;
11138 case '4': USE_BITS (SA4
); break;
11139 case '5': USE_BITS (IMM8
); break;
11140 case '6': USE_BITS (RS
); break;
11141 case '7': USE_BITS (DSPACC
); break;
11142 case '8': USE_BITS (WRDSP
); break;
11143 case '0': USE_BITS (DSPSFT
); break;
11144 case '<': USE_BITS (SHAMT
); break;
11145 case '>': USE_BITS (SHAMT
); break;
11146 case '@': USE_BITS (IMM10
); break;
11147 case 'B': USE_BITS (CODE10
); break;
11148 case 'C': USE_BITS (COPZ
); break;
11149 case 'D': USE_BITS (FD
); break;
11150 case 'E': USE_BITS (RT
); break;
11151 case 'G': USE_BITS (RS
); break;
11152 case 'H': USE_BITS (SEL
); break;
11153 case 'K': USE_BITS (RS
); break;
11154 case 'M': USE_BITS (CCC
); break;
11155 case 'N': USE_BITS (BCC
); break;
11156 case 'R': USE_BITS (FR
); break;
11157 case 'S': USE_BITS (FS
); break;
11158 case 'T': USE_BITS (FT
); break;
11159 case 'V': USE_BITS (FS
); break;
11160 case '\\': USE_BITS (3BITPOS
); break;
11161 case '^': USE_BITS (RD
); break;
11162 case 'a': USE_BITS (TARGET
); break;
11163 case 'b': USE_BITS (RS
); break;
11164 case 'c': USE_BITS (CODE
); break;
11165 case 'd': USE_BITS (RD
); break;
11166 case 'h': USE_BITS (PREFX
); break;
11167 case 'i': USE_BITS (IMMEDIATE
); break;
11168 case 'j': USE_BITS (DELTA
); break;
11169 case 'k': USE_BITS (CACHE
); break;
11170 case 'n': USE_BITS (RT
); break;
11171 case 'o': USE_BITS (DELTA
); break;
11172 case 'p': USE_BITS (DELTA
); break;
11173 case 'q': USE_BITS (CODE2
); break;
11174 case 'r': USE_BITS (RS
); break;
11175 case 's': USE_BITS (RS
); break;
11176 case 't': USE_BITS (RT
); break;
11177 case 'u': USE_BITS (IMMEDIATE
); break;
11178 case 'v': USE_BITS (RS
); break;
11179 case 'w': USE_BITS (RT
); break;
11180 case 'y': USE_BITS (RS3
); break;
11182 case '|': USE_BITS (TRAP
); break;
11183 case '~': USE_BITS (OFFSET12
); break;
11185 as_bad (_("Internal error: bad microMIPS opcode "
11186 "(unknown operand type `%c'): %s %s"),
11187 c
, opc
->name
, opc
->args
);
11191 if (used_bits
!= insn_bits
)
11193 if (~used_bits
& insn_bits
)
11194 as_bad (_("Internal error: bad microMIPS opcode "
11195 "(bits 0x%lx undefined): %s %s"),
11196 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
11197 if (used_bits
& ~insn_bits
)
11198 as_bad (_("Internal error: bad microMIPS opcode "
11199 "(bits 0x%lx defined): %s %s"),
11200 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
11206 /* UDI immediates. */
11207 struct mips_immed
{
11209 unsigned int shift
;
11210 unsigned long mask
;
11214 static const struct mips_immed mips_immed
[] = {
11215 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
11216 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
11217 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
11218 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
11222 /* Check whether an odd floating-point register is allowed. */
11224 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
11226 const char *s
= insn
->name
;
11228 if (insn
->pinfo
== INSN_MACRO
)
11229 /* Let a macro pass, we'll catch it later when it is expanded. */
11232 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
11234 /* Allow odd registers for single-precision ops. */
11235 switch (insn
->pinfo
& (FP_S
| FP_D
))
11239 return 1; /* both single precision - ok */
11241 return 0; /* both double precision - fail */
11246 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11247 s
= strchr (insn
->name
, '.');
11249 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
11250 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
11253 /* Single-precision coprocessor loads and moves are OK too. */
11254 if ((insn
->pinfo
& FP_S
)
11255 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
11256 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
11262 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11263 taking bits from BIT up. */
11265 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
11267 return (ep
->X_op
== O_constant
11268 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
11269 && ep
->X_add_number
>= min
<< bit
11270 && ep
->X_add_number
< max
<< bit
);
11273 /* This routine assembles an instruction into its binary format. As a
11274 side effect, it sets one of the global variables imm_reloc or
11275 offset_reloc to the type of relocation to do if one of the operands
11276 is an address expression. */
11279 mips_ip (char *str
, struct mips_cl_insn
*ip
)
11281 bfd_boolean wrong_delay_slot_insns
= FALSE
;
11282 bfd_boolean need_delay_slot_ok
= TRUE
;
11283 struct mips_opcode
*firstinsn
= NULL
;
11284 const struct mips_opcode
*past
;
11285 struct hash_control
*hash
;
11289 struct mips_opcode
*insn
;
11291 unsigned int regno
, regno2
;
11292 unsigned int lastregno
;
11293 unsigned int destregno
= 0;
11294 unsigned int lastpos
= 0;
11295 unsigned int limlo
, limhi
;
11298 offsetT min_range
, max_range
;
11302 unsigned int rtype
;
11308 if (mips_opts
.micromips
)
11310 hash
= micromips_op_hash
;
11311 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
11316 past
= &mips_opcodes
[NUMOPCODES
];
11318 forced_insn_length
= 0;
11321 /* We first try to match an instruction up to a space or to the end. */
11322 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
11325 /* Make a copy of the instruction so that we can fiddle with it. */
11326 name
= alloca (end
+ 1);
11327 memcpy (name
, str
, end
);
11332 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
11334 if (insn
!= NULL
|| !mips_opts
.micromips
)
11336 if (forced_insn_length
)
11339 /* See if there's an instruction size override suffix,
11340 either `16' or `32', at the end of the mnemonic proper,
11341 that defines the operation, i.e. before the first `.'
11342 character if any. Strip it and retry. */
11343 dot
= strchr (name
, '.');
11344 opend
= dot
!= NULL
? dot
- name
: end
;
11347 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
11348 forced_insn_length
= 2;
11349 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
11350 forced_insn_length
= 4;
11353 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
11357 insn_error
= _("Unrecognized opcode");
11361 /* For microMIPS instructions placed in a fixed-length branch delay slot
11362 we make up to two passes over the relevant fragment of the opcode
11363 table. First we try instructions that meet the delay slot's length
11364 requirement. If none matched, then we retry with the remaining ones
11365 and if one matches, then we use it and then issue an appropriate
11366 warning later on. */
11367 argsStart
= s
= str
+ end
;
11370 bfd_boolean delay_slot_ok
;
11371 bfd_boolean size_ok
;
11374 gas_assert (strcmp (insn
->name
, name
) == 0);
11376 ok
= is_opcode_valid (insn
);
11377 size_ok
= is_size_valid (insn
);
11378 delay_slot_ok
= is_delay_slot_valid (insn
);
11379 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
11382 wrong_delay_slot_insns
= TRUE
;
11384 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
11386 static char buf
[256];
11388 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
11393 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
11395 gas_assert (firstinsn
);
11396 need_delay_slot_ok
= FALSE
;
11406 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
11407 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
11408 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11409 else if (mips_opts
.insn32
)
11410 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
11412 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
11413 8 * forced_insn_length
);
11419 create_insn (ip
, insn
);
11422 lastregno
= 0xffffffff;
11423 for (args
= insn
->args
;; ++args
)
11427 s
+= strspn (s
, " \t");
11431 case '\0': /* end of args */
11437 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11438 code) or 14 (for microMIPS code). */
11439 my_getExpression (&imm_expr
, s
);
11440 check_absolute_expr (ip
, &imm_expr
);
11441 if ((unsigned long) imm_expr
.X_add_number
!= 1
11442 && (unsigned long) imm_expr
.X_add_number
!= 3)
11444 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11445 (unsigned long) imm_expr
.X_add_number
);
11447 INSERT_OPERAND (mips_opts
.micromips
,
11448 BP
, *ip
, imm_expr
.X_add_number
);
11449 imm_expr
.X_op
= O_absent
;
11454 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11455 code) or 13 (for microMIPS code). */
11457 unsigned long mask
= (mips_opts
.micromips
11458 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
11460 my_getExpression (&imm_expr
, s
);
11461 check_absolute_expr (ip
, &imm_expr
);
11462 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11463 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11464 mask
, (unsigned long) imm_expr
.X_add_number
);
11465 INSERT_OPERAND (mips_opts
.micromips
,
11466 SA3
, *ip
, imm_expr
.X_add_number
);
11467 imm_expr
.X_op
= O_absent
;
11473 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11474 code) or 12 (for microMIPS code). */
11476 unsigned long mask
= (mips_opts
.micromips
11477 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
11479 my_getExpression (&imm_expr
, s
);
11480 check_absolute_expr (ip
, &imm_expr
);
11481 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11482 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11483 mask
, (unsigned long) imm_expr
.X_add_number
);
11484 INSERT_OPERAND (mips_opts
.micromips
,
11485 SA4
, *ip
, imm_expr
.X_add_number
);
11486 imm_expr
.X_op
= O_absent
;
11492 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11493 code) or 13 (for microMIPS code). */
11495 unsigned long mask
= (mips_opts
.micromips
11496 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11498 my_getExpression (&imm_expr
, s
);
11499 check_absolute_expr (ip
, &imm_expr
);
11500 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11501 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11502 mask
, (unsigned long) imm_expr
.X_add_number
);
11503 INSERT_OPERAND (mips_opts
.micromips
,
11504 IMM8
, *ip
, imm_expr
.X_add_number
);
11505 imm_expr
.X_op
= O_absent
;
11511 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11512 code) or 16 (for microMIPS code). */
11514 unsigned long mask
= (mips_opts
.micromips
11515 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11517 my_getExpression (&imm_expr
, s
);
11518 check_absolute_expr (ip
, &imm_expr
);
11519 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11520 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11521 mask
, (unsigned long) imm_expr
.X_add_number
);
11522 INSERT_OPERAND (mips_opts
.micromips
,
11523 RS
, *ip
, imm_expr
.X_add_number
);
11524 imm_expr
.X_op
= O_absent
;
11530 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11531 or 14 (for microMIPS code). */
11532 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11533 && s
[3] >= '0' && s
[3] <= '3')
11535 regno
= s
[3] - '0';
11537 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11541 as_bad (_("Invalid dsp acc register"));
11545 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11546 code) or 14 (for microMIPS code). */
11548 unsigned long mask
= (mips_opts
.micromips
11549 ? MICROMIPSOP_MASK_WRDSP
11552 my_getExpression (&imm_expr
, s
);
11553 check_absolute_expr (ip
, &imm_expr
);
11554 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11555 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11556 mask
, (unsigned long) imm_expr
.X_add_number
);
11557 INSERT_OPERAND (mips_opts
.micromips
,
11558 WRDSP
, *ip
, imm_expr
.X_add_number
);
11559 imm_expr
.X_op
= O_absent
;
11564 case '9': /* Four DSP accumulators in bits 21,22. */
11565 gas_assert (!mips_opts
.micromips
);
11566 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11567 && s
[3] >= '0' && s
[3] <= '3')
11569 regno
= s
[3] - '0';
11571 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11575 as_bad (_("Invalid dsp acc register"));
11579 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11580 code) or 16 (for microMIPS code). */
11582 long mask
= (mips_opts
.micromips
11583 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11585 my_getExpression (&imm_expr
, s
);
11586 check_absolute_expr (ip
, &imm_expr
);
11587 min_range
= -((mask
+ 1) >> 1);
11588 max_range
= ((mask
+ 1) >> 1) - 1;
11589 if (imm_expr
.X_add_number
< min_range
11590 || imm_expr
.X_add_number
> max_range
)
11591 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11592 (long) min_range
, (long) max_range
,
11593 (long) imm_expr
.X_add_number
);
11594 INSERT_OPERAND (mips_opts
.micromips
,
11595 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11596 imm_expr
.X_op
= O_absent
;
11601 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11602 gas_assert (!mips_opts
.micromips
);
11603 my_getExpression (&imm_expr
, s
);
11604 check_absolute_expr (ip
, &imm_expr
);
11605 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11607 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11609 (unsigned long) imm_expr
.X_add_number
);
11611 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11612 imm_expr
.X_op
= O_absent
;
11616 case ':': /* DSP 7-bit signed immediate in bit 19. */
11617 gas_assert (!mips_opts
.micromips
);
11618 my_getExpression (&imm_expr
, s
);
11619 check_absolute_expr (ip
, &imm_expr
);
11620 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11621 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11622 if (imm_expr
.X_add_number
< min_range
||
11623 imm_expr
.X_add_number
> max_range
)
11625 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11626 (long) min_range
, (long) max_range
,
11627 (long) imm_expr
.X_add_number
);
11629 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11630 imm_expr
.X_op
= O_absent
;
11634 case '@': /* DSP 10-bit signed immediate in bit 16. */
11636 long mask
= (mips_opts
.micromips
11637 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11639 my_getExpression (&imm_expr
, s
);
11640 check_absolute_expr (ip
, &imm_expr
);
11641 min_range
= -((mask
+ 1) >> 1);
11642 max_range
= ((mask
+ 1) >> 1) - 1;
11643 if (imm_expr
.X_add_number
< min_range
11644 || imm_expr
.X_add_number
> max_range
)
11645 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11646 (long) min_range
, (long) max_range
,
11647 (long) imm_expr
.X_add_number
);
11648 INSERT_OPERAND (mips_opts
.micromips
,
11649 IMM10
, *ip
, imm_expr
.X_add_number
);
11650 imm_expr
.X_op
= O_absent
;
11655 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11656 gas_assert (mips_opts
.micromips
);
11657 my_getExpression (&imm_expr
, s
);
11658 check_absolute_expr (ip
, &imm_expr
);
11659 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11660 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11661 MICROMIPSOP_MASK_RD
,
11662 (unsigned long) imm_expr
.X_add_number
);
11663 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11664 imm_expr
.X_op
= O_absent
;
11668 case '!': /* MT usermode flag bit. */
11669 gas_assert (!mips_opts
.micromips
);
11670 my_getExpression (&imm_expr
, s
);
11671 check_absolute_expr (ip
, &imm_expr
);
11672 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11673 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11674 (unsigned long) imm_expr
.X_add_number
);
11675 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11676 imm_expr
.X_op
= O_absent
;
11680 case '$': /* MT load high flag bit. */
11681 gas_assert (!mips_opts
.micromips
);
11682 my_getExpression (&imm_expr
, s
);
11683 check_absolute_expr (ip
, &imm_expr
);
11684 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11685 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11686 (unsigned long) imm_expr
.X_add_number
);
11687 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11688 imm_expr
.X_op
= O_absent
;
11692 case '*': /* Four DSP accumulators in bits 18,19. */
11693 gas_assert (!mips_opts
.micromips
);
11694 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11695 s
[3] >= '0' && s
[3] <= '3')
11697 regno
= s
[3] - '0';
11699 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11703 as_bad (_("Invalid dsp/smartmips acc register"));
11706 case '&': /* Four DSP accumulators in bits 13,14. */
11707 gas_assert (!mips_opts
.micromips
);
11708 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11709 s
[3] >= '0' && s
[3] <= '3')
11711 regno
= s
[3] - '0';
11713 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11717 as_bad (_("Invalid dsp/smartmips acc register"));
11720 case '\\': /* 3-bit bit position. */
11722 unsigned long mask
= (mips_opts
.micromips
11723 ? MICROMIPSOP_MASK_3BITPOS
11724 : OP_MASK_3BITPOS
);
11726 my_getExpression (&imm_expr
, s
);
11727 check_absolute_expr (ip
, &imm_expr
);
11728 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11729 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11731 mask
, (unsigned long) imm_expr
.X_add_number
);
11732 INSERT_OPERAND (mips_opts
.micromips
,
11733 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11734 imm_expr
.X_op
= O_absent
;
11748 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11752 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11756 gas_assert (!mips_opts
.micromips
);
11757 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11761 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11767 /* Handle optional base register.
11768 Either the base register is omitted or
11769 we must have a left paren. */
11770 /* This is dependent on the next operand specifier
11771 is a base register specification. */
11772 gas_assert (args
[1] == 'b'
11773 || (mips_opts
.micromips
11775 && (args
[2] == 'l' || args
[2] == 'n'
11776 || args
[2] == 's' || args
[2] == 'a')));
11777 if (*s
== '\0' && args
[1] == 'b')
11779 /* Fall through. */
11781 case ')': /* These must match exactly. */
11786 case '+': /* Opcode extension character. */
11789 case '1': /* UDI immediates. */
11793 gas_assert (!mips_opts
.micromips
);
11795 const struct mips_immed
*imm
= mips_immed
;
11797 while (imm
->type
&& imm
->type
!= *args
)
11801 my_getExpression (&imm_expr
, s
);
11802 check_absolute_expr (ip
, &imm_expr
);
11803 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11805 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11806 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11807 (unsigned long) imm_expr
.X_add_number
,
11808 (unsigned long) imm_expr
.X_add_number
);
11809 imm_expr
.X_add_number
&= imm
->mask
;
11811 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11813 imm_expr
.X_op
= O_absent
;
11818 case 'J': /* 10-bit hypcall code. */
11819 gas_assert (!mips_opts
.micromips
);
11821 unsigned long mask
= OP_MASK_CODE10
;
11823 my_getExpression (&imm_expr
, s
);
11824 check_absolute_expr (ip
, &imm_expr
);
11825 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11826 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11828 mask
, (unsigned long) imm_expr
.X_add_number
);
11829 INSERT_OPERAND (0, CODE10
, *ip
, imm_expr
.X_add_number
);
11830 imm_expr
.X_op
= O_absent
;
11835 case 'A': /* ins/ext position, becomes LSB. */
11844 my_getExpression (&imm_expr
, s
);
11845 check_absolute_expr (ip
, &imm_expr
);
11846 if ((unsigned long) imm_expr
.X_add_number
< limlo
11847 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11849 as_bad (_("Improper position (%lu)"),
11850 (unsigned long) imm_expr
.X_add_number
);
11851 imm_expr
.X_add_number
= limlo
;
11853 lastpos
= imm_expr
.X_add_number
;
11854 INSERT_OPERAND (mips_opts
.micromips
,
11855 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11856 imm_expr
.X_op
= O_absent
;
11860 case 'B': /* ins size, becomes MSB. */
11869 my_getExpression (&imm_expr
, s
);
11870 check_absolute_expr (ip
, &imm_expr
);
11871 /* Check for negative input so that small negative numbers
11872 will not succeed incorrectly. The checks against
11873 (pos+size) transitively check "size" itself,
11874 assuming that "pos" is reasonable. */
11875 if ((long) imm_expr
.X_add_number
< 0
11876 || ((unsigned long) imm_expr
.X_add_number
11878 || ((unsigned long) imm_expr
.X_add_number
11879 + lastpos
) > limhi
)
11881 as_bad (_("Improper insert size (%lu, position %lu)"),
11882 (unsigned long) imm_expr
.X_add_number
,
11883 (unsigned long) lastpos
);
11884 imm_expr
.X_add_number
= limlo
- lastpos
;
11886 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11887 lastpos
+ imm_expr
.X_add_number
- 1);
11888 imm_expr
.X_op
= O_absent
;
11892 case 'C': /* ext size, becomes MSBD. */
11908 my_getExpression (&imm_expr
, s
);
11909 check_absolute_expr (ip
, &imm_expr
);
11910 /* The checks against (pos+size) don't transitively check
11911 "size" itself, assuming that "pos" is reasonable.
11912 We also need to check the lower bound of "size". */
11913 if ((long) imm_expr
.X_add_number
< sizelo
11914 || ((unsigned long) imm_expr
.X_add_number
11916 || ((unsigned long) imm_expr
.X_add_number
11917 + lastpos
) > limhi
)
11919 as_bad (_("Improper extract size (%lu, position %lu)"),
11920 (unsigned long) imm_expr
.X_add_number
,
11921 (unsigned long) lastpos
);
11922 imm_expr
.X_add_number
= limlo
- lastpos
;
11924 INSERT_OPERAND (mips_opts
.micromips
,
11925 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11926 imm_expr
.X_op
= O_absent
;
11931 /* "+I" is like "I", except that imm2_expr is used. */
11932 my_getExpression (&imm2_expr
, s
);
11933 if (imm2_expr
.X_op
!= O_big
11934 && imm2_expr
.X_op
!= O_constant
)
11935 insn_error
= _("absolute expression required");
11936 if (HAVE_32BIT_GPRS
)
11937 normalize_constant_expr (&imm2_expr
);
11941 case 't': /* Coprocessor register number. */
11942 gas_assert (!mips_opts
.micromips
);
11943 if (s
[0] == '$' && ISDIGIT (s
[1]))
11953 while (ISDIGIT (*s
));
11955 as_bad (_("Invalid register number (%d)"), regno
);
11958 INSERT_OPERAND (0, RT
, *ip
, regno
);
11963 as_bad (_("Invalid coprocessor 0 register number"));
11967 /* bbit[01] and bbit[01]32 bit index. Give error if index
11968 is not in the valid range. */
11969 gas_assert (!mips_opts
.micromips
);
11970 my_getExpression (&imm_expr
, s
);
11971 check_absolute_expr (ip
, &imm_expr
);
11972 if ((unsigned) imm_expr
.X_add_number
> 31)
11974 as_bad (_("Improper bit index (%lu)"),
11975 (unsigned long) imm_expr
.X_add_number
);
11976 imm_expr
.X_add_number
= 0;
11978 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11979 imm_expr
.X_op
= O_absent
;
11984 /* bbit[01] bit index when bbit is used but we generate
11985 bbit[01]32 because the index is over 32. Move to the
11986 next candidate if index is not in the valid range. */
11987 gas_assert (!mips_opts
.micromips
);
11988 my_getExpression (&imm_expr
, s
);
11989 check_absolute_expr (ip
, &imm_expr
);
11990 if ((unsigned) imm_expr
.X_add_number
< 32
11991 || (unsigned) imm_expr
.X_add_number
> 63)
11993 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11994 imm_expr
.X_op
= O_absent
;
11999 /* cins, cins32, exts and exts32 position field. Give error
12000 if it's not in the valid range. */
12001 gas_assert (!mips_opts
.micromips
);
12002 my_getExpression (&imm_expr
, s
);
12003 check_absolute_expr (ip
, &imm_expr
);
12004 if ((unsigned) imm_expr
.X_add_number
> 31)
12006 as_bad (_("Improper position (%lu)"),
12007 (unsigned long) imm_expr
.X_add_number
);
12008 imm_expr
.X_add_number
= 0;
12010 lastpos
= imm_expr
.X_add_number
;
12011 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
12012 imm_expr
.X_op
= O_absent
;
12017 /* cins, cins32, exts and exts32 position field. Move to
12018 the next candidate if it's not in the valid range. */
12019 gas_assert (!mips_opts
.micromips
);
12020 my_getExpression (&imm_expr
, s
);
12021 check_absolute_expr (ip
, &imm_expr
);
12022 if ((unsigned) imm_expr
.X_add_number
< 32
12023 || (unsigned) imm_expr
.X_add_number
> 63)
12025 lastpos
= imm_expr
.X_add_number
;
12026 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
12027 imm_expr
.X_op
= O_absent
;
12032 /* cins32 and exts32 length-minus-one field. */
12033 gas_assert (!mips_opts
.micromips
);
12034 my_getExpression (&imm_expr
, s
);
12035 check_absolute_expr (ip
, &imm_expr
);
12036 if ((unsigned long) imm_expr
.X_add_number
> 31
12037 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 31)
12039 as_bad (_("Improper size (%lu)"),
12040 (unsigned long) imm_expr
.X_add_number
);
12041 imm_expr
.X_add_number
= 0;
12043 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
12044 imm_expr
.X_op
= O_absent
;
12049 /* cins/exts length-minus-one field. */
12050 gas_assert (!mips_opts
.micromips
);
12051 my_getExpression (&imm_expr
, s
);
12052 check_absolute_expr (ip
, &imm_expr
);
12053 if ((unsigned long) imm_expr
.X_add_number
> 31
12054 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
12056 as_bad (_("Improper size (%lu)"),
12057 (unsigned long) imm_expr
.X_add_number
);
12058 imm_expr
.X_add_number
= 0;
12060 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
12061 imm_expr
.X_op
= O_absent
;
12066 /* seqi/snei immediate field. */
12067 gas_assert (!mips_opts
.micromips
);
12068 my_getExpression (&imm_expr
, s
);
12069 check_absolute_expr (ip
, &imm_expr
);
12070 if ((long) imm_expr
.X_add_number
< -512
12071 || (long) imm_expr
.X_add_number
>= 512)
12073 as_bad (_("Improper immediate (%ld)"),
12074 (long) imm_expr
.X_add_number
);
12075 imm_expr
.X_add_number
= 0;
12077 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
12078 imm_expr
.X_op
= O_absent
;
12082 case 'a': /* 8-bit signed offset in bit 6 */
12083 gas_assert (!mips_opts
.micromips
);
12084 my_getExpression (&imm_expr
, s
);
12085 check_absolute_expr (ip
, &imm_expr
);
12086 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
12087 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
12088 if (imm_expr
.X_add_number
< min_range
12089 || imm_expr
.X_add_number
> max_range
)
12091 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12092 (long) min_range
, (long) max_range
,
12093 (long) imm_expr
.X_add_number
);
12095 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
12096 imm_expr
.X_op
= O_absent
;
12100 case 'b': /* 8-bit signed offset in bit 3 */
12101 gas_assert (!mips_opts
.micromips
);
12102 my_getExpression (&imm_expr
, s
);
12103 check_absolute_expr (ip
, &imm_expr
);
12104 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
12105 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
12106 if (imm_expr
.X_add_number
< min_range
12107 || imm_expr
.X_add_number
> max_range
)
12109 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12110 (long) min_range
, (long) max_range
,
12111 (long) imm_expr
.X_add_number
);
12113 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
12114 imm_expr
.X_op
= O_absent
;
12118 case 'c': /* 9-bit signed offset in bit 6 */
12119 gas_assert (!mips_opts
.micromips
);
12120 my_getExpression (&imm_expr
, s
);
12121 check_absolute_expr (ip
, &imm_expr
);
12122 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
12123 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
12124 /* We check the offset range before adjusted. */
12127 if (imm_expr
.X_add_number
< min_range
12128 || imm_expr
.X_add_number
> max_range
)
12130 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12131 (long) min_range
, (long) max_range
,
12132 (long) imm_expr
.X_add_number
);
12134 if (imm_expr
.X_add_number
& 0xf)
12136 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12137 (long) imm_expr
.X_add_number
);
12139 /* Right shift 4 bits to adjust the offset operand. */
12140 INSERT_OPERAND (0, OFFSET_C
, *ip
,
12141 imm_expr
.X_add_number
>> 4);
12142 imm_expr
.X_op
= O_absent
;
12147 gas_assert (!mips_opts
.micromips
);
12148 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
12150 if (regno
== AT
&& mips_opts
.at
)
12152 if (mips_opts
.at
== ATREG
)
12153 as_warn (_("used $at without \".set noat\""));
12155 as_warn (_("used $%u with \".set at=$%u\""),
12156 regno
, mips_opts
.at
);
12158 INSERT_OPERAND (0, RZ
, *ip
, regno
);
12162 gas_assert (!mips_opts
.micromips
);
12163 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
12165 INSERT_OPERAND (0, FZ
, *ip
, regno
);
12175 /* Check whether there is only a single bracketed expression
12176 left. If so, it must be the base register and the
12177 constant must be zero. */
12178 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12181 /* If this value won't fit into the offset, then go find
12182 a macro that will generate a 16- or 32-bit offset code
12184 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
12185 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
12186 || imm_expr
.X_add_number
>= 1 << shift
12187 || imm_expr
.X_add_number
< -1 << shift
))
12190 imm_expr
.X_op
= O_absent
;
12193 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, *ip
,
12194 imm_expr
.X_add_number
);
12195 imm_expr
.X_op
= O_absent
;
12201 as_bad (_("Internal error: bad %s opcode "
12202 "(unknown extension operand type `+%c'): %s %s"),
12203 mips_opts
.micromips
? "microMIPS" : "MIPS",
12204 *args
, insn
->name
, insn
->args
);
12205 /* Further processing is fruitless. */
12210 case '.': /* 10-bit offset. */
12211 gas_assert (mips_opts
.micromips
);
12212 case '~': /* 12-bit offset. */
12214 int shift
= *args
== '.' ? 9 : 11;
12217 /* Check whether there is only a single bracketed expression
12218 left. If so, it must be the base register and the
12219 constant must be zero. */
12220 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12223 /* If this value won't fit into the offset, then go find
12224 a macro that will generate a 16- or 32-bit offset code
12226 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
12227 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
12228 || imm_expr
.X_add_number
>= 1 << shift
12229 || imm_expr
.X_add_number
< -1 << shift
))
12232 imm_expr
.X_op
= O_absent
;
12236 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
12238 INSERT_OPERAND (mips_opts
.micromips
,
12239 OFFSET12
, *ip
, imm_expr
.X_add_number
);
12240 imm_expr
.X_op
= O_absent
;
12245 case '<': /* must be at least one digit */
12247 * According to the manual, if the shift amount is greater
12248 * than 31 or less than 0, then the shift amount should be
12249 * mod 32. In reality the mips assembler issues an error.
12250 * We issue a warning and mask out all but the low 5 bits.
12252 my_getExpression (&imm_expr
, s
);
12253 check_absolute_expr (ip
, &imm_expr
);
12254 if ((unsigned long) imm_expr
.X_add_number
> 31)
12255 as_warn (_("Improper shift amount (%lu)"),
12256 (unsigned long) imm_expr
.X_add_number
);
12257 INSERT_OPERAND (mips_opts
.micromips
,
12258 SHAMT
, *ip
, imm_expr
.X_add_number
);
12259 imm_expr
.X_op
= O_absent
;
12263 case '>': /* shift amount minus 32 */
12264 my_getExpression (&imm_expr
, s
);
12265 check_absolute_expr (ip
, &imm_expr
);
12266 if ((unsigned long) imm_expr
.X_add_number
< 32
12267 || (unsigned long) imm_expr
.X_add_number
> 63)
12269 INSERT_OPERAND (mips_opts
.micromips
,
12270 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
12271 imm_expr
.X_op
= O_absent
;
12275 case 'k': /* CACHE code. */
12276 case 'h': /* PREFX code. */
12277 case '1': /* SYNC type. */
12278 my_getExpression (&imm_expr
, s
);
12279 check_absolute_expr (ip
, &imm_expr
);
12280 if ((unsigned long) imm_expr
.X_add_number
> 31)
12281 as_warn (_("Invalid value for `%s' (%lu)"),
12283 (unsigned long) imm_expr
.X_add_number
);
12287 if (mips_fix_cn63xxp1
12288 && !mips_opts
.micromips
12289 && strcmp ("pref", insn
->name
) == 0)
12290 switch (imm_expr
.X_add_number
)
12299 case 31: /* These are ok. */
12302 default: /* The rest must be changed to 28. */
12303 imm_expr
.X_add_number
= 28;
12306 INSERT_OPERAND (mips_opts
.micromips
,
12307 CACHE
, *ip
, imm_expr
.X_add_number
);
12310 INSERT_OPERAND (mips_opts
.micromips
,
12311 PREFX
, *ip
, imm_expr
.X_add_number
);
12314 INSERT_OPERAND (mips_opts
.micromips
,
12315 STYPE
, *ip
, imm_expr
.X_add_number
);
12318 imm_expr
.X_op
= O_absent
;
12322 case 'c': /* BREAK code. */
12324 unsigned long mask
= (mips_opts
.micromips
12325 ? MICROMIPSOP_MASK_CODE
12328 my_getExpression (&imm_expr
, s
);
12329 check_absolute_expr (ip
, &imm_expr
);
12330 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12331 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12333 mask
, (unsigned long) imm_expr
.X_add_number
);
12334 INSERT_OPERAND (mips_opts
.micromips
,
12335 CODE
, *ip
, imm_expr
.X_add_number
);
12336 imm_expr
.X_op
= O_absent
;
12341 case 'q': /* Lower BREAK code. */
12343 unsigned long mask
= (mips_opts
.micromips
12344 ? MICROMIPSOP_MASK_CODE2
12347 my_getExpression (&imm_expr
, s
);
12348 check_absolute_expr (ip
, &imm_expr
);
12349 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12350 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12352 mask
, (unsigned long) imm_expr
.X_add_number
);
12353 INSERT_OPERAND (mips_opts
.micromips
,
12354 CODE2
, *ip
, imm_expr
.X_add_number
);
12355 imm_expr
.X_op
= O_absent
;
12360 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12362 unsigned long mask
= (mips_opts
.micromips
12363 ? MICROMIPSOP_MASK_CODE10
12366 my_getExpression (&imm_expr
, s
);
12367 check_absolute_expr (ip
, &imm_expr
);
12368 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12369 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12371 mask
, (unsigned long) imm_expr
.X_add_number
);
12372 if (mips_opts
.micromips
)
12373 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
12375 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
12376 imm_expr
.X_op
= O_absent
;
12381 case 'C': /* 25- or 23-bit coprocessor code. */
12383 unsigned long mask
= (mips_opts
.micromips
12384 ? MICROMIPSOP_MASK_COPZ
12387 my_getExpression (&imm_expr
, s
);
12388 check_absolute_expr (ip
, &imm_expr
);
12389 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12390 as_warn (_("Coproccesor code > %u bits (%lu)"),
12391 mips_opts
.micromips
? 23U : 25U,
12392 (unsigned long) imm_expr
.X_add_number
);
12393 INSERT_OPERAND (mips_opts
.micromips
,
12394 COPZ
, *ip
, imm_expr
.X_add_number
);
12395 imm_expr
.X_op
= O_absent
;
12400 case 'J': /* 19-bit WAIT code. */
12401 gas_assert (!mips_opts
.micromips
);
12402 my_getExpression (&imm_expr
, s
);
12403 check_absolute_expr (ip
, &imm_expr
);
12404 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
12406 as_warn (_("Illegal 19-bit code (%lu)"),
12407 (unsigned long) imm_expr
.X_add_number
);
12408 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
12410 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
12411 imm_expr
.X_op
= O_absent
;
12415 case 'P': /* Performance register. */
12416 gas_assert (!mips_opts
.micromips
);
12417 my_getExpression (&imm_expr
, s
);
12418 check_absolute_expr (ip
, &imm_expr
);
12419 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
12420 as_warn (_("Invalid performance register (%lu)"),
12421 (unsigned long) imm_expr
.X_add_number
);
12422 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
12423 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
12424 as_warn (_("Invalid performance register (%lu)"),
12425 (unsigned long) imm_expr
.X_add_number
);
12426 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
12427 imm_expr
.X_op
= O_absent
;
12431 case 'G': /* Coprocessor destination register. */
12433 unsigned long opcode
= ip
->insn_opcode
;
12434 unsigned long mask
;
12435 unsigned int types
;
12438 if (mips_opts
.micromips
)
12440 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
12441 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
12442 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
12446 case 0x000000fc: /* mfc0 */
12447 case 0x000002fc: /* mtc0 */
12448 case 0x580000fc: /* dmfc0 */
12449 case 0x580002fc: /* dmtc0 */
12459 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
12460 cop0
= opcode
== OP_OP_COP0
;
12462 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
12463 ok
= reg_lookup (&s
, types
, ®no
);
12464 if (mips_opts
.micromips
)
12465 INSERT_OPERAND (1, RS
, *ip
, regno
);
12467 INSERT_OPERAND (0, RD
, *ip
, regno
);
12476 case 'y': /* ALNV.PS source register. */
12477 gas_assert (mips_opts
.micromips
);
12479 case 'x': /* Ignore register name. */
12480 case 'U': /* Destination register (CLO/CLZ). */
12481 case 'g': /* Coprocessor destination register. */
12482 gas_assert (!mips_opts
.micromips
);
12483 case 'b': /* Base register. */
12484 case 'd': /* Destination register. */
12485 case 's': /* Source register. */
12486 case 't': /* Target register. */
12487 case 'r': /* Both target and source. */
12488 case 'v': /* Both dest and source. */
12489 case 'w': /* Both dest and target. */
12490 case 'E': /* Coprocessor target register. */
12491 case 'K': /* RDHWR destination register. */
12492 case 'z': /* Must be zero register. */
12495 if (*args
== 'E' || *args
== 'K')
12496 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
12499 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12500 if (regno
== AT
&& mips_opts
.at
)
12502 if (mips_opts
.at
== ATREG
)
12503 as_warn (_("Used $at without \".set noat\""));
12505 as_warn (_("Used $%u with \".set at=$%u\""),
12506 regno
, mips_opts
.at
);
12516 if (c
== 'r' || c
== 'v' || c
== 'w')
12523 /* 'z' only matches $0. */
12524 if (c
== 'z' && regno
!= 0)
12527 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12529 if (regno
== lastregno
)
12532 = _("Source and destination must be different");
12535 if (regno
== 31 && lastregno
== 0xffffffff)
12538 = _("A destination register must be supplied");
12542 /* Now that we have assembled one operand, we use the args
12543 string to figure out where it goes in the instruction. */
12550 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12554 if (mips_opts
.micromips
)
12555 INSERT_OPERAND (1, RS
, *ip
, regno
);
12557 INSERT_OPERAND (0, RD
, *ip
, regno
);
12562 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12566 gas_assert (!mips_opts
.micromips
);
12567 INSERT_OPERAND (0, RD
, *ip
, regno
);
12568 INSERT_OPERAND (0, RT
, *ip
, regno
);
12574 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12578 gas_assert (mips_opts
.micromips
);
12579 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12583 /* This case exists because on the r3000 trunc
12584 expands into a macro which requires a gp
12585 register. On the r6000 or r4000 it is
12586 assembled into a single instruction which
12587 ignores the register. Thus the insn version
12588 is MIPS_ISA2 and uses 'x', and the macro
12589 version is MIPS_ISA1 and uses 't'. */
12593 /* This case is for the div instruction, which
12594 acts differently if the destination argument
12595 is $0. This only matches $0, and is checked
12596 outside the switch. */
12606 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12610 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12615 case 'O': /* MDMX alignment immediate constant. */
12616 gas_assert (!mips_opts
.micromips
);
12617 my_getExpression (&imm_expr
, s
);
12618 check_absolute_expr (ip
, &imm_expr
);
12619 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12620 as_warn (_("Improper align amount (%ld), using low bits"),
12621 (long) imm_expr
.X_add_number
);
12622 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12623 imm_expr
.X_op
= O_absent
;
12627 case 'Q': /* MDMX vector, element sel, or const. */
12630 /* MDMX Immediate. */
12631 gas_assert (!mips_opts
.micromips
);
12632 my_getExpression (&imm_expr
, s
);
12633 check_absolute_expr (ip
, &imm_expr
);
12634 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12635 as_warn (_("Invalid MDMX Immediate (%ld)"),
12636 (long) imm_expr
.X_add_number
);
12637 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12638 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12639 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12641 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12642 imm_expr
.X_op
= O_absent
;
12646 /* Not MDMX Immediate. Fall through. */
12647 case 'X': /* MDMX destination register. */
12648 case 'Y': /* MDMX source register. */
12649 case 'Z': /* MDMX target register. */
12650 is_mdmx
= !(insn
->membership
& INSN_5400
);
12652 gas_assert (!mips_opts
.micromips
);
12653 case 'D': /* Floating point destination register. */
12654 case 'S': /* Floating point source register. */
12655 case 'T': /* Floating point target register. */
12656 case 'R': /* Floating point source register. */
12660 || ((mips_opts
.ase
& ASE_MDMX
)
12661 && (ip
->insn_mo
->pinfo
& FP_D
)
12662 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12663 | INSN_COPROC_MEMORY_DELAY
12664 | INSN_LOAD_COPROC_DELAY
12665 | INSN_LOAD_MEMORY_DELAY
12666 | INSN_STORE_MEMORY
))))
12667 rtype
|= RTYPE_VEC
;
12669 if (reg_lookup (&s
, rtype
, ®no
))
12671 if ((regno
& 1) != 0
12673 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12674 as_warn (_("Float register should be even, was %d"),
12682 if (c
== 'V' || c
== 'W')
12693 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12699 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12703 /* This is like 'Z', but also needs to fix the MDMX
12704 vector/scalar select bits. Note that the
12705 scalar immediate case is handled above. */
12706 if ((ip
->insn_mo
->membership
& INSN_5400
)
12707 && strcmp (insn
->name
, "rzu.ob") == 0)
12708 as_bad (_("Operand %d of `%s' must be an immediate"),
12709 argnum
, ip
->insn_mo
->name
);
12713 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12714 int max_el
= (is_qh
? 3 : 7);
12716 my_getExpression(&imm_expr
, s
);
12717 check_absolute_expr (ip
, &imm_expr
);
12719 if (imm_expr
.X_add_number
> max_el
)
12720 as_bad (_("Bad element selector %ld"),
12721 (long) imm_expr
.X_add_number
);
12722 imm_expr
.X_add_number
&= max_el
;
12723 ip
->insn_opcode
|= (imm_expr
.X_add_number
12726 imm_expr
.X_op
= O_absent
;
12728 as_warn (_("Expecting ']' found '%s'"), s
);
12734 if ((ip
->insn_mo
->membership
& INSN_5400
)
12735 && (strcmp (insn
->name
, "sll.ob") == 0
12736 || strcmp (insn
->name
, "srl.ob") == 0))
12737 as_bad (_("Operand %d of `%s' must be scalar"),
12738 argnum
, ip
->insn_mo
->name
);
12740 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12741 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12744 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12747 /* Fall through. */
12751 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12755 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12765 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12769 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12775 my_getExpression (&imm_expr
, s
);
12776 if (imm_expr
.X_op
!= O_big
12777 && imm_expr
.X_op
!= O_constant
)
12778 insn_error
= _("absolute expression required");
12779 if (HAVE_32BIT_GPRS
)
12780 normalize_constant_expr (&imm_expr
);
12785 my_getExpression (&offset_expr
, s
);
12786 normalize_address_expr (&offset_expr
);
12787 *imm_reloc
= BFD_RELOC_32
;
12800 unsigned char temp
[8];
12802 unsigned int length
;
12807 /* These only appear as the last operand in an
12808 instruction, and every instruction that accepts
12809 them in any variant accepts them in all variants.
12810 This means we don't have to worry about backing out
12811 any changes if the instruction does not match.
12813 The difference between them is the size of the
12814 floating point constant and where it goes. For 'F'
12815 and 'L' the constant is 64 bits; for 'f' and 'l' it
12816 is 32 bits. Where the constant is placed is based
12817 on how the MIPS assembler does things:
12820 f -- immediate value
12823 The .lit4 and .lit8 sections are only used if
12824 permitted by the -G argument.
12826 The code below needs to know whether the target register
12827 is 32 or 64 bits wide. It relies on the fact 'f' and
12828 'F' are used with GPR-based instructions and 'l' and
12829 'L' are used with FPR-based instructions. */
12831 f64
= *args
== 'F' || *args
== 'L';
12832 using_gprs
= *args
== 'F' || *args
== 'f';
12834 save_in
= input_line_pointer
;
12835 input_line_pointer
= s
;
12836 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12838 s
= input_line_pointer
;
12839 input_line_pointer
= save_in
;
12840 if (err
!= NULL
&& *err
!= '\0')
12842 as_bad (_("Bad floating point constant: %s"), err
);
12843 memset (temp
, '\0', sizeof temp
);
12844 length
= f64
? 8 : 4;
12847 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12851 && (g_switch_value
< 4
12852 || (temp
[0] == 0 && temp
[1] == 0)
12853 || (temp
[2] == 0 && temp
[3] == 0))))
12855 imm_expr
.X_op
= O_constant
;
12856 if (!target_big_endian
)
12857 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12859 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12861 else if (length
> 4
12862 && !mips_disable_float_construction
12863 /* Constants can only be constructed in GPRs and
12864 copied to FPRs if the GPRs are at least as wide
12865 as the FPRs. Force the constant into memory if
12866 we are using 64-bit FPRs but the GPRs are only
12869 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12870 && ((temp
[0] == 0 && temp
[1] == 0)
12871 || (temp
[2] == 0 && temp
[3] == 0))
12872 && ((temp
[4] == 0 && temp
[5] == 0)
12873 || (temp
[6] == 0 && temp
[7] == 0)))
12875 /* The value is simple enough to load with a couple of
12876 instructions. If using 32-bit registers, set
12877 imm_expr to the high order 32 bits and offset_expr to
12878 the low order 32 bits. Otherwise, set imm_expr to
12879 the entire 64 bit constant. */
12880 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12882 imm_expr
.X_op
= O_constant
;
12883 offset_expr
.X_op
= O_constant
;
12884 if (!target_big_endian
)
12886 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12887 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12891 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12892 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12894 if (offset_expr
.X_add_number
== 0)
12895 offset_expr
.X_op
= O_absent
;
12899 imm_expr
.X_op
= O_constant
;
12900 if (!target_big_endian
)
12901 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12903 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12908 const char *newname
;
12911 /* Switch to the right section. */
12913 subseg
= now_subseg
;
12916 default: /* unused default case avoids warnings. */
12918 newname
= RDATA_SECTION_NAME
;
12919 if (g_switch_value
>= 8)
12923 newname
= RDATA_SECTION_NAME
;
12926 gas_assert (g_switch_value
>= 4);
12930 new_seg
= subseg_new (newname
, (subsegT
) 0);
12931 bfd_set_section_flags (stdoutput
, new_seg
,
12936 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12937 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12938 record_alignment (new_seg
, 4);
12940 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12941 if (seg
== now_seg
)
12942 as_bad (_("Can't use floating point insn in this section"));
12944 /* Set the argument to the current address in the
12946 offset_expr
.X_op
= O_symbol
;
12947 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12948 offset_expr
.X_add_number
= 0;
12950 /* Put the floating point number into the section. */
12951 p
= frag_more ((int) length
);
12952 memcpy (p
, temp
, length
);
12954 /* Switch back to the original section. */
12955 subseg_set (seg
, subseg
);
12960 case 'i': /* 16-bit unsigned immediate. */
12961 case 'j': /* 16-bit signed immediate. */
12962 *imm_reloc
= BFD_RELOC_LO16
;
12963 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12966 offsetT minval
, maxval
;
12968 more
= (insn
+ 1 < past
12969 && strcmp (insn
->name
, insn
[1].name
) == 0);
12971 /* For compatibility with older assemblers, we accept
12972 0x8000-0xffff as signed 16-bit numbers when only
12973 signed numbers are allowed. */
12975 minval
= 0, maxval
= 0xffff;
12977 minval
= -0x8000, maxval
= 0x7fff;
12979 minval
= -0x8000, maxval
= 0xffff;
12981 if (imm_expr
.X_op
!= O_constant
12982 || imm_expr
.X_add_number
< minval
12983 || imm_expr
.X_add_number
> maxval
)
12987 if (imm_expr
.X_op
== O_constant
12988 || imm_expr
.X_op
== O_big
)
12989 as_bad (_("Expression out of range"));
12995 case 'o': /* 16-bit offset. */
12996 offset_reloc
[0] = BFD_RELOC_LO16
;
12997 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12998 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13000 /* Check whether there is only a single bracketed expression
13001 left. If so, it must be the base register and the
13002 constant must be zero. */
13003 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13005 offset_expr
.X_op
= O_constant
;
13006 offset_expr
.X_add_number
= 0;
13010 /* If this value won't fit into a 16 bit offset, then go
13011 find a macro that will generate the 32 bit offset
13013 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
13014 && (offset_expr
.X_op
!= O_constant
13015 || offset_expr
.X_add_number
>= 0x8000
13016 || offset_expr
.X_add_number
< -0x8000))
13022 case 'p': /* PC-relative offset. */
13023 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
13024 my_getExpression (&offset_expr
, s
);
13028 case 'u': /* Upper 16 bits. */
13029 *imm_reloc
= BFD_RELOC_LO16
;
13030 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
13031 && imm_expr
.X_op
== O_constant
13032 && (imm_expr
.X_add_number
< 0
13033 || imm_expr
.X_add_number
>= 0x10000))
13034 as_bad (_("lui expression (%lu) not in range 0..65535"),
13035 (unsigned long) imm_expr
.X_add_number
);
13039 case 'a': /* 26-bit address. */
13041 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
13042 my_getExpression (&offset_expr
, s
);
13046 case 'N': /* 3-bit branch condition code. */
13047 case 'M': /* 3-bit compare condition code. */
13049 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
13050 rtype
|= RTYPE_FCC
;
13051 if (!reg_lookup (&s
, rtype
, ®no
))
13053 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
13054 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
13055 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
13056 && (regno
& 1) != 0)
13057 as_warn (_("Condition code register should be even for %s, "
13060 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
13061 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
13062 && (regno
& 3) != 0)
13063 as_warn (_("Condition code register should be 0 or 4 for %s, "
13067 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
13069 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
13073 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
13084 while (ISDIGIT (*s
));
13087 c
= 8; /* Invalid sel value. */
13090 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13091 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
13095 gas_assert (!mips_opts
.micromips
);
13096 /* Must be at least one digit. */
13097 my_getExpression (&imm_expr
, s
);
13098 check_absolute_expr (ip
, &imm_expr
);
13100 if ((unsigned long) imm_expr
.X_add_number
13101 > (unsigned long) OP_MASK_VECBYTE
)
13103 as_bad (_("bad byte vector index (%ld)"),
13104 (long) imm_expr
.X_add_number
);
13105 imm_expr
.X_add_number
= 0;
13108 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
13109 imm_expr
.X_op
= O_absent
;
13114 gas_assert (!mips_opts
.micromips
);
13115 my_getExpression (&imm_expr
, s
);
13116 check_absolute_expr (ip
, &imm_expr
);
13118 if ((unsigned long) imm_expr
.X_add_number
13119 > (unsigned long) OP_MASK_VECALIGN
)
13121 as_bad (_("bad byte vector index (%ld)"),
13122 (long) imm_expr
.X_add_number
);
13123 imm_expr
.X_add_number
= 0;
13126 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
13127 imm_expr
.X_op
= O_absent
;
13131 case 'm': /* Opcode extension character. */
13132 gas_assert (mips_opts
.micromips
);
13137 if (strncmp (s
, "$pc", 3) == 0)
13164 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
13165 if (regno
== AT
&& mips_opts
.at
)
13167 if (mips_opts
.at
== ATREG
)
13168 as_warn (_("Used $at without \".set noat\""));
13170 as_warn (_("Used $%u with \".set at=$%u\""),
13171 regno
, mips_opts
.at
);
13177 gas_assert (args
[1] == ',');
13183 gas_assert (args
[1] == ',');
13185 continue; /* Nothing to do. */
13191 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
13193 if (regno
== lastregno
)
13196 = _("Source and destination must be different");
13199 if (regno
== 31 && lastregno
== 0xffffffff)
13202 = _("A destination register must be supplied");
13213 gas_assert (args
[1] == ',');
13220 gas_assert (args
[1] == ',');
13223 continue; /* Nothing to do. */
13227 /* Make sure regno is the same as lastregno. */
13228 if (c
== 't' && regno
!= lastregno
)
13231 /* Make sure regno is the same as destregno. */
13232 if (c
== 'x' && regno
!= destregno
)
13235 /* We need to save regno, before regno maps to the
13236 microMIPS register encoding. */
13246 regno
= ILLEGAL_REG
;
13250 regno
= mips32_to_micromips_reg_b_map
[regno
];
13254 regno
= mips32_to_micromips_reg_c_map
[regno
];
13258 regno
= mips32_to_micromips_reg_d_map
[regno
];
13262 regno
= mips32_to_micromips_reg_e_map
[regno
];
13266 regno
= mips32_to_micromips_reg_f_map
[regno
];
13270 regno
= mips32_to_micromips_reg_g_map
[regno
];
13274 s
+= strspn (s
, " \t");
13277 regno
= ILLEGAL_REG
;
13281 s
+= strspn (s
, " \t");
13282 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no2
);
13285 regno
= ILLEGAL_REG
;
13288 if (regno2
== AT
&& mips_opts
.at
)
13290 if (mips_opts
.at
== ATREG
)
13291 as_warn (_("Used $at without \".set noat\""));
13293 as_warn (_("Used $%u with \".set at=$%u\""),
13294 regno2
, mips_opts
.at
);
13296 regno
= (mips_lookup_reg_pair
13298 micromips_to_32_reg_h_map1
,
13299 micromips_to_32_reg_h_map2
, 8));
13303 regno
= mips32_to_micromips_reg_l_map
[regno
];
13307 regno
= mips32_to_micromips_reg_m_map
[regno
];
13311 regno
= mips32_to_micromips_reg_n_map
[regno
];
13315 regno
= mips32_to_micromips_reg_q_map
[regno
];
13320 regno
= ILLEGAL_REG
;
13325 regno
= ILLEGAL_REG
;
13330 regno
= ILLEGAL_REG
;
13333 case 'j': /* Do nothing. */
13343 if (regno
== ILLEGAL_REG
)
13349 INSERT_OPERAND (1, MB
, *ip
, regno
);
13353 INSERT_OPERAND (1, MC
, *ip
, regno
);
13357 INSERT_OPERAND (1, MD
, *ip
, regno
);
13361 INSERT_OPERAND (1, ME
, *ip
, regno
);
13365 INSERT_OPERAND (1, MF
, *ip
, regno
);
13369 INSERT_OPERAND (1, MG
, *ip
, regno
);
13373 INSERT_OPERAND (1, MH
, *ip
, regno
);
13377 INSERT_OPERAND (1, MJ
, *ip
, regno
);
13381 INSERT_OPERAND (1, ML
, *ip
, regno
);
13385 INSERT_OPERAND (1, MM
, *ip
, regno
);
13389 INSERT_OPERAND (1, MN
, *ip
, regno
);
13393 INSERT_OPERAND (1, MP
, *ip
, regno
);
13397 INSERT_OPERAND (1, MQ
, *ip
, regno
);
13400 case 'a': /* Do nothing. */
13401 case 's': /* Do nothing. */
13402 case 't': /* Do nothing. */
13403 case 'x': /* Do nothing. */
13404 case 'y': /* Do nothing. */
13405 case 'z': /* Do nothing. */
13415 bfd_reloc_code_real_type r
[3];
13419 /* Check whether there is only a single bracketed
13420 expression left. If so, it must be the base register
13421 and the constant must be zero. */
13422 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13424 INSERT_OPERAND (1, IMMA
, *ip
, 0);
13428 if (my_getSmallExpression (&ep
, r
, s
) > 0
13429 || !expr_const_in_range (&ep
, -64, 64, 2))
13432 imm
= ep
.X_add_number
>> 2;
13433 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
13440 bfd_reloc_code_real_type r
[3];
13444 if (my_getSmallExpression (&ep
, r
, s
) > 0
13445 || ep
.X_op
!= O_constant
)
13448 for (imm
= 0; imm
< 8; imm
++)
13449 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
13454 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
13461 bfd_reloc_code_real_type r
[3];
13465 if (my_getSmallExpression (&ep
, r
, s
) > 0
13466 || ep
.X_op
!= O_constant
)
13469 for (imm
= 0; imm
< 16; imm
++)
13470 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
13475 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13480 case 'D': /* pc relative offset */
13481 case 'E': /* pc relative offset */
13482 my_getExpression (&offset_expr
, s
);
13483 if (offset_expr
.X_op
== O_register
)
13486 if (!forced_insn_length
)
13487 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13489 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13491 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13497 bfd_reloc_code_real_type r
[3];
13501 if (my_getSmallExpression (&ep
, r
, s
) > 0
13502 || !expr_const_in_range (&ep
, 0, 16, 0))
13505 imm
= ep
.X_add_number
;
13506 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13513 bfd_reloc_code_real_type r
[3];
13517 /* Check whether there is only a single bracketed
13518 expression left. If so, it must be the base register
13519 and the constant must be zero. */
13520 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13522 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13526 if (my_getSmallExpression (&ep
, r
, s
) > 0
13527 || !expr_const_in_range (&ep
, -1, 15, 0))
13530 imm
= ep
.X_add_number
& 15;
13531 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13538 bfd_reloc_code_real_type r
[3];
13542 /* Check whether there is only a single bracketed
13543 expression left. If so, it must be the base register
13544 and the constant must be zero. */
13545 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13547 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13551 if (my_getSmallExpression (&ep
, r
, s
) > 0
13552 || !expr_const_in_range (&ep
, 0, 16, 1))
13555 imm
= ep
.X_add_number
>> 1;
13556 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13563 bfd_reloc_code_real_type r
[3];
13567 if (my_getSmallExpression (&ep
, r
, s
) > 0
13568 || !expr_const_in_range (&ep
, -1, 127, 0))
13571 imm
= ep
.X_add_number
& 127;
13572 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13579 bfd_reloc_code_real_type r
[3];
13583 /* Check whether there is only a single bracketed
13584 expression left. If so, it must be the base register
13585 and the constant must be zero. */
13586 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13588 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13592 if (my_getSmallExpression (&ep
, r
, s
) > 0
13593 || !expr_const_in_range (&ep
, 0, 16, 2))
13596 imm
= ep
.X_add_number
>> 2;
13597 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13604 bfd_reloc_code_real_type r
[3];
13608 /* Check whether there is only a single bracketed
13609 expression left. If so, it must be the base register
13610 and the constant must be zero. */
13611 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13613 INSERT_OPERAND (1, IMML
, *ip
, 0);
13617 if (my_getSmallExpression (&ep
, r
, s
) > 0
13618 || !expr_const_in_range (&ep
, 0, 16, 0))
13621 imm
= ep
.X_add_number
;
13622 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13629 bfd_reloc_code_real_type r
[3];
13633 if (my_getSmallExpression (&ep
, r
, s
) > 0
13634 || !expr_const_in_range (&ep
, 1, 9, 0))
13637 imm
= ep
.X_add_number
& 7;
13638 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13643 case 'N': /* Register list for lwm and swm. */
13645 /* A comma-separated list of registers and/or
13646 dash-separated contiguous ranges including
13647 both ra and a set of one or more registers
13648 starting at s0 up to s3 which have to be
13655 and any permutations of these. */
13656 unsigned int reglist
;
13659 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13662 if ((reglist
& 0xfff1ffff) != 0x80010000)
13665 reglist
= (reglist
>> 17) & 7;
13667 if ((reglist
& -reglist
) != reglist
)
13670 imm
= ffs (reglist
) - 1;
13671 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13675 case 'O': /* sdbbp 4-bit code. */
13677 bfd_reloc_code_real_type r
[3];
13681 if (my_getSmallExpression (&ep
, r
, s
) > 0
13682 || !expr_const_in_range (&ep
, 0, 16, 0))
13685 imm
= ep
.X_add_number
;
13686 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13693 bfd_reloc_code_real_type r
[3];
13697 if (my_getSmallExpression (&ep
, r
, s
) > 0
13698 || !expr_const_in_range (&ep
, 0, 32, 2))
13701 imm
= ep
.X_add_number
>> 2;
13702 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13709 bfd_reloc_code_real_type r
[3];
13713 if (my_getSmallExpression (&ep
, r
, s
) > 0
13714 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13717 imm
= ep
.X_add_number
>> 2;
13718 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13725 bfd_reloc_code_real_type r
[3];
13729 /* Check whether there is only a single bracketed
13730 expression left. If so, it must be the base register
13731 and the constant must be zero. */
13732 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13734 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13738 if (my_getSmallExpression (&ep
, r
, s
) > 0
13739 || !expr_const_in_range (&ep
, 0, 32, 2))
13742 imm
= ep
.X_add_number
>> 2;
13743 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13750 bfd_reloc_code_real_type r
[3];
13754 if (my_getSmallExpression (&ep
, r
, s
) > 0
13755 || !expr_const_in_range (&ep
, 0, 64, 2))
13758 imm
= ep
.X_add_number
>> 2;
13759 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13766 bfd_reloc_code_real_type r
[3];
13770 if (my_getSmallExpression (&ep
, r
, s
) > 0
13771 || !expr_const_in_range (&ep
, -8, 8, 0))
13774 imm
= ep
.X_add_number
;
13775 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13782 bfd_reloc_code_real_type r
[3];
13786 if (my_getSmallExpression (&ep
, r
, s
) > 0
13787 || expr_const_in_range (&ep
, -2, 2, 2)
13788 || !expr_const_in_range (&ep
, -258, 258, 2))
13791 imm
= ep
.X_add_number
>> 2;
13792 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13793 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13800 bfd_reloc_code_real_type r
[3];
13803 if (my_getSmallExpression (&ep
, r
, s
) > 0
13804 || !expr_const_in_range (&ep
, 0, 1, 0))
13811 as_bad (_("Internal error: bad microMIPS opcode "
13812 "(unknown extension operand type `m%c'): %s %s"),
13813 *args
, insn
->name
, insn
->args
);
13814 /* Further processing is fruitless. */
13819 case 'n': /* Register list for 32-bit lwm and swm. */
13820 gas_assert (mips_opts
.micromips
);
13822 /* A comma-separated list of registers and/or
13823 dash-separated contiguous ranges including
13824 at least one of ra and a set of one or more
13825 registers starting at s0 up to s7 and then
13826 s8 which have to be consecutive, e.g.:
13834 and any permutations of these. */
13835 unsigned int reglist
;
13839 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13842 if ((reglist
& 0x3f00ffff) != 0)
13845 ra
= (reglist
>> 27) & 0x10;
13846 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13848 if ((reglist
& -reglist
) != reglist
)
13851 imm
= (ffs (reglist
) - 1) | ra
;
13852 INSERT_OPERAND (1, RT
, *ip
, imm
);
13853 imm_expr
.X_op
= O_absent
;
13857 case '|': /* 4-bit trap code. */
13858 gas_assert (mips_opts
.micromips
);
13859 my_getExpression (&imm_expr
, s
);
13860 check_absolute_expr (ip
, &imm_expr
);
13861 if ((unsigned long) imm_expr
.X_add_number
13862 > MICROMIPSOP_MASK_TRAP
)
13863 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13864 (unsigned long) imm_expr
.X_add_number
,
13865 ip
->insn_mo
->name
);
13866 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13867 imm_expr
.X_op
= O_absent
;
13872 as_bad (_("Bad char = '%c'\n"), *args
);
13877 /* Args don't match. */
13879 insn_error
= _("Illegal operands");
13880 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13885 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13887 gas_assert (firstinsn
);
13888 need_delay_slot_ok
= FALSE
;
13897 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13899 /* This routine assembles an instruction into its binary format when
13900 assembling for the mips16. As a side effect, it sets one of the
13901 global variables imm_reloc or offset_reloc to the type of relocation
13902 to do if one of the operands is an address expression. It also sets
13903 forced_insn_length to the resulting instruction size in bytes if the
13904 user explicitly requested a small or extended instruction. */
13907 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13911 struct mips_opcode
*insn
;
13913 unsigned int regno
;
13914 unsigned int lastregno
= 0;
13920 forced_insn_length
= 0;
13922 for (s
= str
; ISLOWER (*s
); ++s
)
13934 if (s
[1] == 't' && s
[2] == ' ')
13937 forced_insn_length
= 2;
13941 else if (s
[1] == 'e' && s
[2] == ' ')
13944 forced_insn_length
= 4;
13948 /* Fall through. */
13950 insn_error
= _("unknown opcode");
13954 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13955 forced_insn_length
= 2;
13957 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13959 insn_error
= _("unrecognized opcode");
13968 gas_assert (strcmp (insn
->name
, str
) == 0);
13970 ok
= is_opcode_valid_16 (insn
);
13973 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13974 && strcmp (insn
->name
, insn
[1].name
) == 0)
13983 static char buf
[100];
13985 _("Opcode not supported on this processor: %s (%s)"),
13986 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13987 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13994 create_insn (ip
, insn
);
13995 imm_expr
.X_op
= O_absent
;
13996 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13997 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13998 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13999 imm2_expr
.X_op
= O_absent
;
14000 offset_expr
.X_op
= O_absent
;
14001 offset_reloc
[0] = BFD_RELOC_UNUSED
;
14002 offset_reloc
[1] = BFD_RELOC_UNUSED
;
14003 offset_reloc
[2] = BFD_RELOC_UNUSED
;
14004 for (args
= insn
->args
; 1; ++args
)
14011 /* In this switch statement we call break if we did not find
14012 a match, continue if we did find a match, or return if we
14023 /* Stuff the immediate value in now, if we can. */
14024 if (imm_expr
.X_op
== O_constant
14025 && *imm_reloc
> BFD_RELOC_UNUSED
14026 && insn
->pinfo
!= INSN_MACRO
14027 && calculate_reloc (*offset_reloc
,
14028 imm_expr
.X_add_number
, &value
))
14030 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
14031 *offset_reloc
, value
, forced_insn_length
,
14033 imm_expr
.X_op
= O_absent
;
14034 *imm_reloc
= BFD_RELOC_UNUSED
;
14035 *offset_reloc
= BFD_RELOC_UNUSED
;
14049 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14052 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14068 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14070 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14074 /* Fall through. */
14085 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
14087 if (c
== 'v' || c
== 'w')
14090 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14092 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14103 if (c
== 'v' || c
== 'w')
14105 regno
= mips16_to_32_reg_map
[lastregno
];
14119 regno
= mips32_to_16_reg_map
[regno
];
14124 regno
= ILLEGAL_REG
;
14129 regno
= ILLEGAL_REG
;
14134 regno
= ILLEGAL_REG
;
14139 if (regno
== AT
&& mips_opts
.at
)
14141 if (mips_opts
.at
== ATREG
)
14142 as_warn (_("used $at without \".set noat\""));
14144 as_warn (_("used $%u with \".set at=$%u\""),
14145 regno
, mips_opts
.at
);
14153 if (regno
== ILLEGAL_REG
)
14160 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
14164 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
14167 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
14170 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
14176 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
14179 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
14180 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
14190 if (strncmp (s
, "$pc", 3) == 0)
14207 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
14210 if (imm_expr
.X_op
!= O_constant
)
14212 forced_insn_length
= 4;
14213 ip
->insn_opcode
|= MIPS16_EXTEND
;
14217 /* We need to relax this instruction. */
14218 *offset_reloc
= *imm_reloc
;
14219 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14224 *imm_reloc
= BFD_RELOC_UNUSED
;
14225 /* Fall through. */
14232 my_getExpression (&imm_expr
, s
);
14233 if (imm_expr
.X_op
== O_register
)
14235 /* What we thought was an expression turned out to
14238 if (s
[0] == '(' && args
[1] == '(')
14240 /* It looks like the expression was omitted
14241 before a register indirection, which means
14242 that the expression is implicitly zero. We
14243 still set up imm_expr, so that we handle
14244 explicit extensions correctly. */
14245 imm_expr
.X_op
= O_constant
;
14246 imm_expr
.X_add_number
= 0;
14247 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14254 /* We need to relax this instruction. */
14255 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14264 /* We use offset_reloc rather than imm_reloc for the PC
14265 relative operands. This lets macros with both
14266 immediate and address operands work correctly. */
14267 my_getExpression (&offset_expr
, s
);
14269 if (offset_expr
.X_op
== O_register
)
14272 /* We need to relax this instruction. */
14273 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14277 case '6': /* break code */
14278 my_getExpression (&imm_expr
, s
);
14279 check_absolute_expr (ip
, &imm_expr
);
14280 if ((unsigned long) imm_expr
.X_add_number
> 63)
14281 as_warn (_("Invalid value for `%s' (%lu)"),
14283 (unsigned long) imm_expr
.X_add_number
);
14284 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
14285 imm_expr
.X_op
= O_absent
;
14289 case 'a': /* 26 bit address */
14291 my_getExpression (&offset_expr
, s
);
14293 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
14294 ip
->insn_opcode
<<= 16;
14297 case 'l': /* register list for entry macro */
14298 case 'L': /* register list for exit macro */
14308 unsigned int freg
, reg1
, reg2
;
14310 while (*s
== ' ' || *s
== ',')
14312 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14314 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
14318 as_bad (_("can't parse register list"));
14328 if (!reg_lookup (&s
, freg
? RTYPE_FPU
14329 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
14331 as_bad (_("invalid register list"));
14335 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
14337 mask
&= ~ (7 << 3);
14340 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
14342 mask
&= ~ (7 << 3);
14345 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
14346 mask
|= (reg2
- 3) << 3;
14347 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
14348 mask
|= (reg2
- 15) << 1;
14349 else if (reg1
== RA
&& reg2
== RA
)
14353 as_bad (_("invalid register list"));
14357 /* The mask is filled in in the opcode table for the
14358 benefit of the disassembler. We remove it before
14359 applying the actual mask. */
14360 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
14361 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
14365 case 'm': /* Register list for save insn. */
14366 case 'M': /* Register list for restore insn. */
14368 int opcode
= ip
->insn_opcode
;
14369 int framesz
= 0, seen_framesz
= 0;
14370 int nargs
= 0, statics
= 0, sregs
= 0;
14374 unsigned int reg1
, reg2
;
14376 SKIP_SPACE_TABS (s
);
14379 SKIP_SPACE_TABS (s
);
14381 my_getExpression (&imm_expr
, s
);
14382 if (imm_expr
.X_op
== O_constant
)
14384 /* Handle the frame size. */
14387 as_bad (_("more than one frame size in list"));
14391 framesz
= imm_expr
.X_add_number
;
14392 imm_expr
.X_op
= O_absent
;
14397 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14399 as_bad (_("can't parse register list"));
14411 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
14414 as_bad (_("can't parse register list"));
14419 while (reg1
<= reg2
)
14421 if (reg1
>= 4 && reg1
<= 7)
14425 nargs
|= 1 << (reg1
- 4);
14427 /* statics $a0-$a3 */
14428 statics
|= 1 << (reg1
- 4);
14430 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
14433 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
14435 else if (reg1
== 31)
14437 /* Add $ra to insn. */
14442 as_bad (_("unexpected register in list"));
14450 /* Encode args/statics combination. */
14451 if (nargs
& statics
)
14452 as_bad (_("arg/static registers overlap"));
14453 else if (nargs
== 0xf)
14454 /* All $a0-$a3 are args. */
14455 opcode
|= MIPS16_ALL_ARGS
<< 16;
14456 else if (statics
== 0xf)
14457 /* All $a0-$a3 are statics. */
14458 opcode
|= MIPS16_ALL_STATICS
<< 16;
14461 int narg
= 0, nstat
= 0;
14463 /* Count arg registers. */
14464 while (nargs
& 0x1)
14470 as_bad (_("invalid arg register list"));
14472 /* Count static registers. */
14473 while (statics
& 0x8)
14475 statics
= (statics
<< 1) & 0xf;
14479 as_bad (_("invalid static register list"));
14481 /* Encode args/statics. */
14482 opcode
|= ((narg
<< 2) | nstat
) << 16;
14485 /* Encode $s0/$s1. */
14486 if (sregs
& (1 << 0)) /* $s0 */
14488 if (sregs
& (1 << 1)) /* $s1 */
14494 /* Count regs $s2-$s8. */
14502 as_bad (_("invalid static register list"));
14503 /* Encode $s2-$s8. */
14504 opcode
|= nsreg
<< 24;
14507 /* Encode frame size. */
14509 as_bad (_("missing frame size"));
14510 else if ((framesz
& 7) != 0 || framesz
< 0
14511 || framesz
> 0xff * 8)
14512 as_bad (_("invalid frame size"));
14513 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14516 opcode
|= (((framesz
& 0xf0) << 16)
14517 | (framesz
& 0x0f));
14520 /* Finally build the instruction. */
14521 if ((opcode
>> 16) != 0 || framesz
== 0)
14522 opcode
|= MIPS16_EXTEND
;
14523 ip
->insn_opcode
= opcode
;
14527 case 'e': /* extend code */
14528 my_getExpression (&imm_expr
, s
);
14529 check_absolute_expr (ip
, &imm_expr
);
14530 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14532 as_warn (_("Invalid value for `%s' (%lu)"),
14534 (unsigned long) imm_expr
.X_add_number
);
14535 imm_expr
.X_add_number
&= 0x7ff;
14537 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14538 imm_expr
.X_op
= O_absent
;
14548 /* Args don't match. */
14549 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14550 strcmp (insn
->name
, insn
[1].name
) == 0)
14557 insn_error
= _("illegal operands");
14563 /* This structure holds information we know about a mips16 immediate
14566 struct mips16_immed_operand
14568 /* The type code used in the argument string in the opcode table. */
14570 /* The number of bits in the short form of the opcode. */
14572 /* The number of bits in the extended form of the opcode. */
14574 /* The amount by which the short form is shifted when it is used;
14575 for example, the sw instruction has a shift count of 2. */
14577 /* The amount by which the short form is shifted when it is stored
14578 into the instruction code. */
14580 /* Non-zero if the short form is unsigned. */
14582 /* Non-zero if the extended form is unsigned. */
14584 /* Non-zero if the value is PC relative. */
14588 /* The mips16 immediate operand types. */
14590 static const struct mips16_immed_operand mips16_immed_operands
[] =
14592 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14593 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14594 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14595 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14596 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14597 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14598 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14599 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14600 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14601 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14602 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14603 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14604 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14605 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14606 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14607 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14608 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14609 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14610 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14611 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14612 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14615 #define MIPS16_NUM_IMMED \
14616 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14618 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14619 NBITS is the number of significant bits in VAL. */
14621 static unsigned long
14622 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14627 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14630 else if (nbits
== 15)
14632 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14637 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14640 return (extval
<< 16) | val
;
14643 /* Install immediate value VAL into MIPS16 instruction *INSN,
14644 extending it if necessary. The instruction in *INSN may
14645 already be extended.
14647 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14648 if none. In the former case, VAL is a 16-bit number with no
14649 defined signedness.
14651 TYPE is the type of the immediate field. USER_INSN_LENGTH
14652 is the length that the user requested, or 0 if none. */
14655 mips16_immed (char *file
, unsigned int line
, int type
,
14656 bfd_reloc_code_real_type reloc
, offsetT val
,
14657 unsigned int user_insn_length
, unsigned long *insn
)
14659 const struct mips16_immed_operand
*op
;
14660 int mintiny
, maxtiny
;
14662 op
= mips16_immed_operands
;
14663 while (op
->type
!= type
)
14666 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14671 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14674 maxtiny
= 1 << op
->nbits
;
14679 maxtiny
= (1 << op
->nbits
) - 1;
14681 if (reloc
!= BFD_RELOC_UNUSED
)
14686 mintiny
= - (1 << (op
->nbits
- 1));
14687 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14688 if (reloc
!= BFD_RELOC_UNUSED
)
14689 val
= SEXT_16BIT (val
);
14692 /* Branch offsets have an implicit 0 in the lowest bit. */
14693 if (type
== 'p' || type
== 'q')
14696 if ((val
& ((1 << op
->shift
) - 1)) != 0
14697 || val
< (mintiny
<< op
->shift
)
14698 || val
> (maxtiny
<< op
->shift
))
14700 /* We need an extended instruction. */
14701 if (user_insn_length
== 2)
14702 as_bad_where (file
, line
, _("invalid unextended operand value"));
14704 *insn
|= MIPS16_EXTEND
;
14706 else if (user_insn_length
== 4)
14708 /* The operand doesn't force an unextended instruction to be extended.
14709 Warn if the user wanted an extended instruction anyway. */
14710 *insn
|= MIPS16_EXTEND
;
14711 as_warn_where (file
, line
,
14712 _("extended operand requested but not required"));
14715 if (mips16_opcode_length (*insn
) == 2)
14719 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14720 insnval
<<= op
->op_shift
;
14725 long minext
, maxext
;
14727 if (reloc
== BFD_RELOC_UNUSED
)
14732 maxext
= (1 << op
->extbits
) - 1;
14736 minext
= - (1 << (op
->extbits
- 1));
14737 maxext
= (1 << (op
->extbits
- 1)) - 1;
14739 if (val
< minext
|| val
> maxext
)
14740 as_bad_where (file
, line
,
14741 _("operand value out of range for instruction"));
14744 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14748 struct percent_op_match
14751 bfd_reloc_code_real_type reloc
;
14754 static const struct percent_op_match mips_percent_op
[] =
14756 {"%lo", BFD_RELOC_LO16
},
14757 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14758 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14759 {"%call16", BFD_RELOC_MIPS_CALL16
},
14760 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14761 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14762 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14763 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14764 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14765 {"%got", BFD_RELOC_MIPS_GOT16
},
14766 {"%gp_rel", BFD_RELOC_GPREL16
},
14767 {"%half", BFD_RELOC_16
},
14768 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14769 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14770 {"%neg", BFD_RELOC_MIPS_SUB
},
14771 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14772 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14773 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14774 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14775 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14776 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14777 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14778 {"%hi", BFD_RELOC_HI16_S
}
14781 static const struct percent_op_match mips16_percent_op
[] =
14783 {"%lo", BFD_RELOC_MIPS16_LO16
},
14784 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14785 {"%got", BFD_RELOC_MIPS16_GOT16
},
14786 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14787 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14788 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14789 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14790 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14791 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14792 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14793 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14794 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14798 /* Return true if *STR points to a relocation operator. When returning true,
14799 move *STR over the operator and store its relocation code in *RELOC.
14800 Leave both *STR and *RELOC alone when returning false. */
14803 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14805 const struct percent_op_match
*percent_op
;
14808 if (mips_opts
.mips16
)
14810 percent_op
= mips16_percent_op
;
14811 limit
= ARRAY_SIZE (mips16_percent_op
);
14815 percent_op
= mips_percent_op
;
14816 limit
= ARRAY_SIZE (mips_percent_op
);
14819 for (i
= 0; i
< limit
; i
++)
14820 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14822 int len
= strlen (percent_op
[i
].str
);
14824 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14827 *str
+= strlen (percent_op
[i
].str
);
14828 *reloc
= percent_op
[i
].reloc
;
14830 /* Check whether the output BFD supports this relocation.
14831 If not, issue an error and fall back on something safe. */
14832 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14834 as_bad (_("relocation %s isn't supported by the current ABI"),
14835 percent_op
[i
].str
);
14836 *reloc
= BFD_RELOC_UNUSED
;
14844 /* Parse string STR as a 16-bit relocatable operand. Store the
14845 expression in *EP and the relocations in the array starting
14846 at RELOC. Return the number of relocation operators used.
14848 On exit, EXPR_END points to the first character after the expression. */
14851 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14854 bfd_reloc_code_real_type reversed_reloc
[3];
14855 size_t reloc_index
, i
;
14856 int crux_depth
, str_depth
;
14859 /* Search for the start of the main expression, recoding relocations
14860 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14861 of the main expression and with CRUX_DEPTH containing the number
14862 of open brackets at that point. */
14869 crux_depth
= str_depth
;
14871 /* Skip over whitespace and brackets, keeping count of the number
14873 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14878 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14879 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14881 my_getExpression (ep
, crux
);
14884 /* Match every open bracket. */
14885 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14889 if (crux_depth
> 0)
14890 as_bad (_("unclosed '('"));
14894 if (reloc_index
!= 0)
14896 prev_reloc_op_frag
= frag_now
;
14897 for (i
= 0; i
< reloc_index
; i
++)
14898 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14901 return reloc_index
;
14905 my_getExpression (expressionS
*ep
, char *str
)
14909 save_in
= input_line_pointer
;
14910 input_line_pointer
= str
;
14912 expr_end
= input_line_pointer
;
14913 input_line_pointer
= save_in
;
14917 md_atof (int type
, char *litP
, int *sizeP
)
14919 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14923 md_number_to_chars (char *buf
, valueT val
, int n
)
14925 if (target_big_endian
)
14926 number_to_chars_bigendian (buf
, val
, n
);
14928 number_to_chars_littleendian (buf
, val
, n
);
14931 static int support_64bit_objects(void)
14933 const char **list
, **l
;
14936 list
= bfd_target_list ();
14937 for (l
= list
; *l
!= NULL
; l
++)
14938 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14939 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14941 yes
= (*l
!= NULL
);
14946 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14947 NEW_VALUE. Warn if another value was already specified. Note:
14948 we have to defer parsing the -march and -mtune arguments in order
14949 to handle 'from-abi' correctly, since the ABI might be specified
14950 in a later argument. */
14953 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14955 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14956 as_warn (_("A different %s was already specified, is now %s"),
14957 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14960 *string_ptr
= new_value
;
14964 md_parse_option (int c
, char *arg
)
14968 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14969 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14971 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
14972 c
== mips_ases
[i
].option_on
);
14978 case OPTION_CONSTRUCT_FLOATS
:
14979 mips_disable_float_construction
= 0;
14982 case OPTION_NO_CONSTRUCT_FLOATS
:
14983 mips_disable_float_construction
= 1;
14995 target_big_endian
= 1;
14999 target_big_endian
= 0;
15005 else if (arg
[0] == '0')
15007 else if (arg
[0] == '1')
15017 mips_debug
= atoi (arg
);
15021 file_mips_isa
= ISA_MIPS1
;
15025 file_mips_isa
= ISA_MIPS2
;
15029 file_mips_isa
= ISA_MIPS3
;
15033 file_mips_isa
= ISA_MIPS4
;
15037 file_mips_isa
= ISA_MIPS5
;
15040 case OPTION_MIPS32
:
15041 file_mips_isa
= ISA_MIPS32
;
15044 case OPTION_MIPS32R2
:
15045 file_mips_isa
= ISA_MIPS32R2
;
15048 case OPTION_MIPS64R2
:
15049 file_mips_isa
= ISA_MIPS64R2
;
15052 case OPTION_MIPS64
:
15053 file_mips_isa
= ISA_MIPS64
;
15057 mips_set_option_string (&mips_tune_string
, arg
);
15061 mips_set_option_string (&mips_arch_string
, arg
);
15065 mips_set_option_string (&mips_arch_string
, "4650");
15066 mips_set_option_string (&mips_tune_string
, "4650");
15069 case OPTION_NO_M4650
:
15073 mips_set_option_string (&mips_arch_string
, "4010");
15074 mips_set_option_string (&mips_tune_string
, "4010");
15077 case OPTION_NO_M4010
:
15081 mips_set_option_string (&mips_arch_string
, "4100");
15082 mips_set_option_string (&mips_tune_string
, "4100");
15085 case OPTION_NO_M4100
:
15089 mips_set_option_string (&mips_arch_string
, "3900");
15090 mips_set_option_string (&mips_tune_string
, "3900");
15093 case OPTION_NO_M3900
:
15096 case OPTION_MICROMIPS
:
15097 if (mips_opts
.mips16
== 1)
15099 as_bad (_("-mmicromips cannot be used with -mips16"));
15102 mips_opts
.micromips
= 1;
15103 mips_no_prev_insn ();
15106 case OPTION_NO_MICROMIPS
:
15107 mips_opts
.micromips
= 0;
15108 mips_no_prev_insn ();
15111 case OPTION_MIPS16
:
15112 if (mips_opts
.micromips
== 1)
15114 as_bad (_("-mips16 cannot be used with -micromips"));
15117 mips_opts
.mips16
= 1;
15118 mips_no_prev_insn ();
15121 case OPTION_NO_MIPS16
:
15122 mips_opts
.mips16
= 0;
15123 mips_no_prev_insn ();
15126 case OPTION_FIX_24K
:
15130 case OPTION_NO_FIX_24K
:
15134 case OPTION_FIX_LOONGSON2F_JUMP
:
15135 mips_fix_loongson2f_jump
= TRUE
;
15138 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
15139 mips_fix_loongson2f_jump
= FALSE
;
15142 case OPTION_FIX_LOONGSON2F_NOP
:
15143 mips_fix_loongson2f_nop
= TRUE
;
15146 case OPTION_NO_FIX_LOONGSON2F_NOP
:
15147 mips_fix_loongson2f_nop
= FALSE
;
15150 case OPTION_FIX_VR4120
:
15151 mips_fix_vr4120
= 1;
15154 case OPTION_NO_FIX_VR4120
:
15155 mips_fix_vr4120
= 0;
15158 case OPTION_FIX_VR4130
:
15159 mips_fix_vr4130
= 1;
15162 case OPTION_NO_FIX_VR4130
:
15163 mips_fix_vr4130
= 0;
15166 case OPTION_FIX_CN63XXP1
:
15167 mips_fix_cn63xxp1
= TRUE
;
15170 case OPTION_NO_FIX_CN63XXP1
:
15171 mips_fix_cn63xxp1
= FALSE
;
15174 case OPTION_RELAX_BRANCH
:
15175 mips_relax_branch
= 1;
15178 case OPTION_NO_RELAX_BRANCH
:
15179 mips_relax_branch
= 0;
15182 case OPTION_INSN32
:
15183 mips_opts
.insn32
= TRUE
;
15186 case OPTION_NO_INSN32
:
15187 mips_opts
.insn32
= FALSE
;
15190 case OPTION_MSHARED
:
15191 mips_in_shared
= TRUE
;
15194 case OPTION_MNO_SHARED
:
15195 mips_in_shared
= FALSE
;
15198 case OPTION_MSYM32
:
15199 mips_opts
.sym32
= TRUE
;
15202 case OPTION_MNO_SYM32
:
15203 mips_opts
.sym32
= FALSE
;
15206 /* When generating ELF code, we permit -KPIC and -call_shared to
15207 select SVR4_PIC, and -non_shared to select no PIC. This is
15208 intended to be compatible with Irix 5. */
15209 case OPTION_CALL_SHARED
:
15210 mips_pic
= SVR4_PIC
;
15211 mips_abicalls
= TRUE
;
15214 case OPTION_CALL_NONPIC
:
15216 mips_abicalls
= TRUE
;
15219 case OPTION_NON_SHARED
:
15221 mips_abicalls
= FALSE
;
15224 /* The -xgot option tells the assembler to use 32 bit offsets
15225 when accessing the got in SVR4_PIC mode. It is for Irix
15232 g_switch_value
= atoi (arg
);
15236 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15239 mips_abi
= O32_ABI
;
15243 mips_abi
= N32_ABI
;
15247 mips_abi
= N64_ABI
;
15248 if (!support_64bit_objects())
15249 as_fatal (_("No compiled in support for 64 bit object file format"));
15253 file_mips_gp32
= 1;
15257 file_mips_gp32
= 0;
15261 file_mips_fp32
= 1;
15265 file_mips_fp32
= 0;
15268 case OPTION_SINGLE_FLOAT
:
15269 file_mips_single_float
= 1;
15272 case OPTION_DOUBLE_FLOAT
:
15273 file_mips_single_float
= 0;
15276 case OPTION_SOFT_FLOAT
:
15277 file_mips_soft_float
= 1;
15280 case OPTION_HARD_FLOAT
:
15281 file_mips_soft_float
= 0;
15285 if (strcmp (arg
, "32") == 0)
15286 mips_abi
= O32_ABI
;
15287 else if (strcmp (arg
, "o64") == 0)
15288 mips_abi
= O64_ABI
;
15289 else if (strcmp (arg
, "n32") == 0)
15290 mips_abi
= N32_ABI
;
15291 else if (strcmp (arg
, "64") == 0)
15293 mips_abi
= N64_ABI
;
15294 if (! support_64bit_objects())
15295 as_fatal (_("No compiled in support for 64 bit object file "
15298 else if (strcmp (arg
, "eabi") == 0)
15299 mips_abi
= EABI_ABI
;
15302 as_fatal (_("invalid abi -mabi=%s"), arg
);
15307 case OPTION_M7000_HILO_FIX
:
15308 mips_7000_hilo_fix
= TRUE
;
15311 case OPTION_MNO_7000_HILO_FIX
:
15312 mips_7000_hilo_fix
= FALSE
;
15315 case OPTION_MDEBUG
:
15316 mips_flag_mdebug
= TRUE
;
15319 case OPTION_NO_MDEBUG
:
15320 mips_flag_mdebug
= FALSE
;
15324 mips_flag_pdr
= TRUE
;
15327 case OPTION_NO_PDR
:
15328 mips_flag_pdr
= FALSE
;
15331 case OPTION_MVXWORKS_PIC
:
15332 mips_pic
= VXWORKS_PIC
;
15339 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15344 /* Set up globals to generate code for the ISA or processor
15345 described by INFO. */
15348 mips_set_architecture (const struct mips_cpu_info
*info
)
15352 file_mips_arch
= info
->cpu
;
15353 mips_opts
.arch
= info
->cpu
;
15354 mips_opts
.isa
= info
->isa
;
15359 /* Likewise for tuning. */
15362 mips_set_tune (const struct mips_cpu_info
*info
)
15365 mips_tune
= info
->cpu
;
15370 mips_after_parse_args (void)
15372 const struct mips_cpu_info
*arch_info
= 0;
15373 const struct mips_cpu_info
*tune_info
= 0;
15375 /* GP relative stuff not working for PE */
15376 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15378 if (g_switch_seen
&& g_switch_value
!= 0)
15379 as_bad (_("-G not supported in this configuration."));
15380 g_switch_value
= 0;
15383 if (mips_abi
== NO_ABI
)
15384 mips_abi
= MIPS_DEFAULT_ABI
;
15386 /* The following code determines the architecture and register size.
15387 Similar code was added to GCC 3.3 (see override_options() in
15388 config/mips/mips.c). The GAS and GCC code should be kept in sync
15389 as much as possible. */
15391 if (mips_arch_string
!= 0)
15392 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15394 if (file_mips_isa
!= ISA_UNKNOWN
)
15396 /* Handle -mipsN. At this point, file_mips_isa contains the
15397 ISA level specified by -mipsN, while arch_info->isa contains
15398 the -march selection (if any). */
15399 if (arch_info
!= 0)
15401 /* -march takes precedence over -mipsN, since it is more descriptive.
15402 There's no harm in specifying both as long as the ISA levels
15404 if (file_mips_isa
!= arch_info
->isa
)
15405 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15406 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15407 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15410 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15413 if (arch_info
== 0)
15415 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15416 gas_assert (arch_info
);
15419 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15420 as_bad (_("-march=%s is not compatible with the selected ABI"),
15423 mips_set_architecture (arch_info
);
15425 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15426 if (mips_tune_string
!= 0)
15427 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15429 if (tune_info
== 0)
15430 mips_set_tune (arch_info
);
15432 mips_set_tune (tune_info
);
15434 if (file_mips_gp32
>= 0)
15436 /* The user specified the size of the integer registers. Make sure
15437 it agrees with the ABI and ISA. */
15438 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15439 as_bad (_("-mgp64 used with a 32-bit processor"));
15440 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15441 as_bad (_("-mgp32 used with a 64-bit ABI"));
15442 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15443 as_bad (_("-mgp64 used with a 32-bit ABI"));
15447 /* Infer the integer register size from the ABI and processor.
15448 Restrict ourselves to 32-bit registers if that's all the
15449 processor has, or if the ABI cannot handle 64-bit registers. */
15450 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15451 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15454 switch (file_mips_fp32
)
15458 /* No user specified float register size.
15459 ??? GAS treats single-float processors as though they had 64-bit
15460 float registers (although it complains when double-precision
15461 instructions are used). As things stand, saying they have 32-bit
15462 registers would lead to spurious "register must be even" messages.
15463 So here we assume float registers are never smaller than the
15465 if (file_mips_gp32
== 0)
15466 /* 64-bit integer registers implies 64-bit float registers. */
15467 file_mips_fp32
= 0;
15468 else if ((mips_opts
.ase
& FP64_ASES
)
15469 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15470 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15471 file_mips_fp32
= 0;
15473 /* 32-bit float registers. */
15474 file_mips_fp32
= 1;
15477 /* The user specified the size of the float registers. Check if it
15478 agrees with the ABI and ISA. */
15480 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15481 as_bad (_("-mfp64 used with a 32-bit fpu"));
15482 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15483 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15484 as_warn (_("-mfp64 used with a 32-bit ABI"));
15487 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15488 as_warn (_("-mfp32 used with a 64-bit ABI"));
15492 /* End of GCC-shared inference code. */
15494 /* This flag is set when we have a 64-bit capable CPU but use only
15495 32-bit wide registers. Note that EABI does not use it. */
15496 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15497 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15498 || mips_abi
== O32_ABI
))
15499 mips_32bitmode
= 1;
15501 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15502 as_bad (_("trap exception not supported at ISA 1"));
15504 /* If the selected architecture includes support for ASEs, enable
15505 generation of code for them. */
15506 if (mips_opts
.mips16
== -1)
15507 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15508 if (mips_opts
.micromips
== -1)
15509 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15511 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15512 ASEs from being selected implicitly. */
15513 if (file_mips_fp32
== 1)
15514 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
15516 /* If the user didn't explicitly select or deselect a particular ASE,
15517 use the default setting for the CPU. */
15518 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
15520 file_mips_isa
= mips_opts
.isa
;
15521 file_ase
= mips_opts
.ase
;
15522 mips_opts
.gp32
= file_mips_gp32
;
15523 mips_opts
.fp32
= file_mips_fp32
;
15524 mips_opts
.soft_float
= file_mips_soft_float
;
15525 mips_opts
.single_float
= file_mips_single_float
;
15527 mips_check_isa_supports_ases ();
15529 if (mips_flag_mdebug
< 0)
15530 mips_flag_mdebug
= 0;
15534 mips_init_after_args (void)
15536 /* initialize opcodes */
15537 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15538 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15542 md_pcrel_from (fixS
*fixP
)
15544 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15545 switch (fixP
->fx_r_type
)
15547 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15548 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15549 /* Return the address of the delay slot. */
15552 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15553 case BFD_RELOC_MICROMIPS_JMP
:
15554 case BFD_RELOC_16_PCREL_S2
:
15555 case BFD_RELOC_MIPS_JMP
:
15556 /* Return the address of the delay slot. */
15559 case BFD_RELOC_32_PCREL
:
15563 /* We have no relocation type for PC relative MIPS16 instructions. */
15564 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15566 _("PC relative MIPS16 instruction references a different section"));
15571 /* This is called before the symbol table is processed. In order to
15572 work with gcc when using mips-tfile, we must keep all local labels.
15573 However, in other cases, we want to discard them. If we were
15574 called with -g, but we didn't see any debugging information, it may
15575 mean that gcc is smuggling debugging information through to
15576 mips-tfile, in which case we must generate all local labels. */
15579 mips_frob_file_before_adjust (void)
15581 #ifndef NO_ECOFF_DEBUGGING
15582 if (ECOFF_DEBUGGING
15584 && ! ecoff_debugging_seen
)
15585 flag_keep_locals
= 1;
15589 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15590 the corresponding LO16 reloc. This is called before md_apply_fix and
15591 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15592 relocation operators.
15594 For our purposes, a %lo() expression matches a %got() or %hi()
15597 (a) it refers to the same symbol; and
15598 (b) the offset applied in the %lo() expression is no lower than
15599 the offset applied in the %got() or %hi().
15601 (b) allows us to cope with code like:
15604 lh $4,%lo(foo+2)($4)
15606 ...which is legal on RELA targets, and has a well-defined behaviour
15607 if the user knows that adding 2 to "foo" will not induce a carry to
15610 When several %lo()s match a particular %got() or %hi(), we use the
15611 following rules to distinguish them:
15613 (1) %lo()s with smaller offsets are a better match than %lo()s with
15616 (2) %lo()s with no matching %got() or %hi() are better than those
15617 that already have a matching %got() or %hi().
15619 (3) later %lo()s are better than earlier %lo()s.
15621 These rules are applied in order.
15623 (1) means, among other things, that %lo()s with identical offsets are
15624 chosen if they exist.
15626 (2) means that we won't associate several high-part relocations with
15627 the same low-part relocation unless there's no alternative. Having
15628 several high parts for the same low part is a GNU extension; this rule
15629 allows careful users to avoid it.
15631 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15632 with the last high-part relocation being at the front of the list.
15633 It therefore makes sense to choose the last matching low-part
15634 relocation, all other things being equal. It's also easier
15635 to code that way. */
15638 mips_frob_file (void)
15640 struct mips_hi_fixup
*l
;
15641 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15643 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15645 segment_info_type
*seginfo
;
15646 bfd_boolean matched_lo_p
;
15647 fixS
**hi_pos
, **lo_pos
, **pos
;
15649 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15651 /* If a GOT16 relocation turns out to be against a global symbol,
15652 there isn't supposed to be a matching LO. Ignore %gots against
15653 constants; we'll report an error for those later. */
15654 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15655 && !(l
->fixp
->fx_addsy
15656 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15659 /* Check quickly whether the next fixup happens to be a matching %lo. */
15660 if (fixup_has_matching_lo_p (l
->fixp
))
15663 seginfo
= seg_info (l
->seg
);
15665 /* Set HI_POS to the position of this relocation in the chain.
15666 Set LO_POS to the position of the chosen low-part relocation.
15667 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15668 relocation that matches an immediately-preceding high-part
15672 matched_lo_p
= FALSE
;
15673 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15675 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15677 if (*pos
== l
->fixp
)
15680 if ((*pos
)->fx_r_type
== looking_for_rtype
15681 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15682 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15684 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15686 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15689 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15690 && fixup_has_matching_lo_p (*pos
));
15693 /* If we found a match, remove the high-part relocation from its
15694 current position and insert it before the low-part relocation.
15695 Make the offsets match so that fixup_has_matching_lo_p()
15698 We don't warn about unmatched high-part relocations since some
15699 versions of gcc have been known to emit dead "lui ...%hi(...)"
15701 if (lo_pos
!= NULL
)
15703 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15704 if (l
->fixp
->fx_next
!= *lo_pos
)
15706 *hi_pos
= l
->fixp
->fx_next
;
15707 l
->fixp
->fx_next
= *lo_pos
;
15715 mips_force_relocation (fixS
*fixp
)
15717 if (generic_force_reloc (fixp
))
15720 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15721 so that the linker relaxation can update targets. */
15722 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15723 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15724 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15730 /* Read the instruction associated with RELOC from BUF. */
15732 static unsigned int
15733 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15735 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15736 return read_compressed_insn (buf
, 4);
15738 return read_insn (buf
);
15741 /* Write instruction INSN to BUF, given that it has been relocated
15745 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15746 unsigned long insn
)
15748 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15749 write_compressed_insn (buf
, insn
, 4);
15751 write_insn (buf
, insn
);
15754 /* Apply a fixup to the object file. */
15757 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15760 unsigned long insn
;
15761 reloc_howto_type
*howto
;
15763 /* We ignore generic BFD relocations we don't know about. */
15764 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15768 gas_assert (fixP
->fx_size
== 2
15769 || fixP
->fx_size
== 4
15770 || fixP
->fx_r_type
== BFD_RELOC_16
15771 || fixP
->fx_r_type
== BFD_RELOC_64
15772 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15773 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15774 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15775 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15776 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15777 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15779 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15781 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15782 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15783 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15784 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
15785 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
15787 /* Don't treat parts of a composite relocation as done. There are two
15790 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15791 should nevertheless be emitted if the first part is.
15793 (2) In normal usage, composite relocations are never assembly-time
15794 constants. The easiest way of dealing with the pathological
15795 exceptions is to generate a relocation against STN_UNDEF and
15796 leave everything up to the linker. */
15797 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15800 switch (fixP
->fx_r_type
)
15802 case BFD_RELOC_MIPS_TLS_GD
:
15803 case BFD_RELOC_MIPS_TLS_LDM
:
15804 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15805 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15806 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15807 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15808 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15809 case BFD_RELOC_MIPS_TLS_TPREL32
:
15810 case BFD_RELOC_MIPS_TLS_TPREL64
:
15811 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15812 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15813 case BFD_RELOC_MICROMIPS_TLS_GD
:
15814 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15815 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15816 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15817 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15818 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15819 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15820 case BFD_RELOC_MIPS16_TLS_GD
:
15821 case BFD_RELOC_MIPS16_TLS_LDM
:
15822 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15823 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15824 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15825 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15826 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15827 if (!fixP
->fx_addsy
)
15829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15830 _("TLS relocation against a constant"));
15833 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15836 case BFD_RELOC_MIPS_JMP
:
15837 case BFD_RELOC_MIPS_SHIFT5
:
15838 case BFD_RELOC_MIPS_SHIFT6
:
15839 case BFD_RELOC_MIPS_GOT_DISP
:
15840 case BFD_RELOC_MIPS_GOT_PAGE
:
15841 case BFD_RELOC_MIPS_GOT_OFST
:
15842 case BFD_RELOC_MIPS_SUB
:
15843 case BFD_RELOC_MIPS_INSERT_A
:
15844 case BFD_RELOC_MIPS_INSERT_B
:
15845 case BFD_RELOC_MIPS_DELETE
:
15846 case BFD_RELOC_MIPS_HIGHEST
:
15847 case BFD_RELOC_MIPS_HIGHER
:
15848 case BFD_RELOC_MIPS_SCN_DISP
:
15849 case BFD_RELOC_MIPS_REL16
:
15850 case BFD_RELOC_MIPS_RELGOT
:
15851 case BFD_RELOC_MIPS_JALR
:
15852 case BFD_RELOC_HI16
:
15853 case BFD_RELOC_HI16_S
:
15854 case BFD_RELOC_LO16
:
15855 case BFD_RELOC_GPREL16
:
15856 case BFD_RELOC_MIPS_LITERAL
:
15857 case BFD_RELOC_MIPS_CALL16
:
15858 case BFD_RELOC_MIPS_GOT16
:
15859 case BFD_RELOC_GPREL32
:
15860 case BFD_RELOC_MIPS_GOT_HI16
:
15861 case BFD_RELOC_MIPS_GOT_LO16
:
15862 case BFD_RELOC_MIPS_CALL_HI16
:
15863 case BFD_RELOC_MIPS_CALL_LO16
:
15864 case BFD_RELOC_MIPS16_GPREL
:
15865 case BFD_RELOC_MIPS16_GOT16
:
15866 case BFD_RELOC_MIPS16_CALL16
:
15867 case BFD_RELOC_MIPS16_HI16
:
15868 case BFD_RELOC_MIPS16_HI16_S
:
15869 case BFD_RELOC_MIPS16_LO16
:
15870 case BFD_RELOC_MIPS16_JMP
:
15871 case BFD_RELOC_MICROMIPS_JMP
:
15872 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15873 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15874 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15875 case BFD_RELOC_MICROMIPS_SUB
:
15876 case BFD_RELOC_MICROMIPS_HIGHEST
:
15877 case BFD_RELOC_MICROMIPS_HIGHER
:
15878 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15879 case BFD_RELOC_MICROMIPS_JALR
:
15880 case BFD_RELOC_MICROMIPS_HI16
:
15881 case BFD_RELOC_MICROMIPS_HI16_S
:
15882 case BFD_RELOC_MICROMIPS_LO16
:
15883 case BFD_RELOC_MICROMIPS_GPREL16
:
15884 case BFD_RELOC_MICROMIPS_LITERAL
:
15885 case BFD_RELOC_MICROMIPS_CALL16
:
15886 case BFD_RELOC_MICROMIPS_GOT16
:
15887 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15888 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15889 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15890 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15891 case BFD_RELOC_MIPS_EH
:
15896 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15898 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15899 if (mips16_reloc_p (fixP
->fx_r_type
))
15900 insn
|= mips16_immed_extend (value
, 16);
15902 insn
|= (value
& 0xffff);
15903 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15907 _("Unsupported constant in relocation"));
15912 /* This is handled like BFD_RELOC_32, but we output a sign
15913 extended value if we are only 32 bits. */
15916 if (8 <= sizeof (valueT
))
15917 md_number_to_chars (buf
, *valP
, 8);
15922 if ((*valP
& 0x80000000) != 0)
15926 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15927 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15932 case BFD_RELOC_RVA
:
15934 case BFD_RELOC_32_PCREL
:
15936 /* If we are deleting this reloc entry, we must fill in the
15937 value now. This can happen if we have a .word which is not
15938 resolved when it appears but is later defined. */
15940 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15943 case BFD_RELOC_16_PCREL_S2
:
15944 if ((*valP
& 0x3) != 0)
15945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15946 _("Branch to misaligned address (%lx)"), (long) *valP
);
15948 /* We need to save the bits in the instruction since fixup_segment()
15949 might be deleting the relocation entry (i.e., a branch within
15950 the current segment). */
15951 if (! fixP
->fx_done
)
15954 /* Update old instruction data. */
15955 insn
= read_insn (buf
);
15957 if (*valP
+ 0x20000 <= 0x3ffff)
15959 insn
|= (*valP
>> 2) & 0xffff;
15960 write_insn (buf
, insn
);
15962 else if (mips_pic
== NO_PIC
15964 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15965 && (fixP
->fx_frag
->fr_address
15966 < text_section
->vma
+ bfd_get_section_size (text_section
))
15967 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15968 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15969 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15971 /* The branch offset is too large. If this is an
15972 unconditional branch, and we are not generating PIC code,
15973 we can convert it to an absolute jump instruction. */
15974 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15975 insn
= 0x0c000000; /* jal */
15977 insn
= 0x08000000; /* j */
15978 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15980 fixP
->fx_addsy
= section_symbol (text_section
);
15981 *valP
+= md_pcrel_from (fixP
);
15982 write_insn (buf
, insn
);
15986 /* If we got here, we have branch-relaxation disabled,
15987 and there's nothing we can do to fix this instruction
15988 without turning it into a longer sequence. */
15989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15990 _("Branch out of range"));
15994 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15995 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15996 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15997 /* We adjust the offset back to even. */
15998 if ((*valP
& 0x1) != 0)
16001 if (! fixP
->fx_done
)
16004 /* Should never visit here, because we keep the relocation. */
16008 case BFD_RELOC_VTABLE_INHERIT
:
16011 && !S_IS_DEFINED (fixP
->fx_addsy
)
16012 && !S_IS_WEAK (fixP
->fx_addsy
))
16013 S_SET_WEAK (fixP
->fx_addsy
);
16016 case BFD_RELOC_VTABLE_ENTRY
:
16024 /* Remember value for tc_gen_reloc. */
16025 fixP
->fx_addnumber
= *valP
;
16035 name
= input_line_pointer
;
16036 c
= get_symbol_end ();
16037 p
= (symbolS
*) symbol_find_or_make (name
);
16038 *input_line_pointer
= c
;
16042 /* Align the current frag to a given power of two. If a particular
16043 fill byte should be used, FILL points to an integer that contains
16044 that byte, otherwise FILL is null.
16046 This function used to have the comment:
16048 The MIPS assembler also automatically adjusts any preceding label.
16050 The implementation therefore applied the adjustment to a maximum of
16051 one label. However, other label adjustments are applied to batches
16052 of labels, and adjusting just one caused problems when new labels
16053 were added for the sake of debugging or unwind information.
16054 We therefore adjust all preceding labels (given as LABELS) instead. */
16057 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16059 mips_emit_delays ();
16060 mips_record_compressed_mode ();
16061 if (fill
== NULL
&& subseg_text_p (now_seg
))
16062 frag_align_code (to
, 0);
16064 frag_align (to
, fill
? *fill
: 0, 0);
16065 record_alignment (now_seg
, to
);
16066 mips_move_labels (labels
, FALSE
);
16069 /* Align to a given power of two. .align 0 turns off the automatic
16070 alignment used by the data creating pseudo-ops. */
16073 s_align (int x ATTRIBUTE_UNUSED
)
16075 int temp
, fill_value
, *fill_ptr
;
16076 long max_alignment
= 28;
16078 /* o Note that the assembler pulls down any immediately preceding label
16079 to the aligned address.
16080 o It's not documented but auto alignment is reinstated by
16081 a .align pseudo instruction.
16082 o Note also that after auto alignment is turned off the mips assembler
16083 issues an error on attempt to assemble an improperly aligned data item.
16086 temp
= get_absolute_expression ();
16087 if (temp
> max_alignment
)
16088 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
16091 as_warn (_("Alignment negative: 0 assumed."));
16094 if (*input_line_pointer
== ',')
16096 ++input_line_pointer
;
16097 fill_value
= get_absolute_expression ();
16098 fill_ptr
= &fill_value
;
16104 segment_info_type
*si
= seg_info (now_seg
);
16105 struct insn_label_list
*l
= si
->label_list
;
16106 /* Auto alignment should be switched on by next section change. */
16108 mips_align (temp
, fill_ptr
, l
);
16115 demand_empty_rest_of_line ();
16119 s_change_sec (int sec
)
16123 /* The ELF backend needs to know that we are changing sections, so
16124 that .previous works correctly. We could do something like check
16125 for an obj_section_change_hook macro, but that might be confusing
16126 as it would not be appropriate to use it in the section changing
16127 functions in read.c, since obj-elf.c intercepts those. FIXME:
16128 This should be cleaner, somehow. */
16129 obj_elf_section_change_hook ();
16131 mips_emit_delays ();
16142 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16143 demand_empty_rest_of_line ();
16147 seg
= subseg_new (RDATA_SECTION_NAME
,
16148 (subsegT
) get_absolute_expression ());
16149 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16150 | SEC_READONLY
| SEC_RELOC
16152 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16153 record_alignment (seg
, 4);
16154 demand_empty_rest_of_line ();
16158 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16159 bfd_set_section_flags (stdoutput
, seg
,
16160 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16161 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16162 record_alignment (seg
, 4);
16163 demand_empty_rest_of_line ();
16167 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16168 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16169 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16170 record_alignment (seg
, 4);
16171 demand_empty_rest_of_line ();
16179 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16181 char *section_name
;
16186 int section_entry_size
;
16187 int section_alignment
;
16189 section_name
= input_line_pointer
;
16190 c
= get_symbol_end ();
16192 next_c
= *(input_line_pointer
+ 1);
16194 /* Do we have .section Name<,"flags">? */
16195 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16197 /* just after name is now '\0'. */
16198 *input_line_pointer
= c
;
16199 input_line_pointer
= section_name
;
16200 obj_elf_section (ignore
);
16203 input_line_pointer
++;
16205 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16207 section_type
= get_absolute_expression ();
16210 if (*input_line_pointer
++ == ',')
16211 section_flag
= get_absolute_expression ();
16214 if (*input_line_pointer
++ == ',')
16215 section_entry_size
= get_absolute_expression ();
16217 section_entry_size
= 0;
16218 if (*input_line_pointer
++ == ',')
16219 section_alignment
= get_absolute_expression ();
16221 section_alignment
= 0;
16222 /* FIXME: really ignore? */
16223 (void) section_alignment
;
16225 section_name
= xstrdup (section_name
);
16227 /* When using the generic form of .section (as implemented by obj-elf.c),
16228 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16229 traditionally had to fall back on the more common @progbits instead.
16231 There's nothing really harmful in this, since bfd will correct
16232 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16233 means that, for backwards compatibility, the special_section entries
16234 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16236 Even so, we shouldn't force users of the MIPS .section syntax to
16237 incorrectly label the sections as SHT_PROGBITS. The best compromise
16238 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16239 generic type-checking code. */
16240 if (section_type
== SHT_MIPS_DWARF
)
16241 section_type
= SHT_PROGBITS
;
16243 obj_elf_change_section (section_name
, section_type
, section_flag
,
16244 section_entry_size
, 0, 0, 0);
16246 if (now_seg
->name
!= section_name
)
16247 free (section_name
);
16251 mips_enable_auto_align (void)
16257 s_cons (int log_size
)
16259 segment_info_type
*si
= seg_info (now_seg
);
16260 struct insn_label_list
*l
= si
->label_list
;
16262 mips_emit_delays ();
16263 if (log_size
> 0 && auto_align
)
16264 mips_align (log_size
, 0, l
);
16265 cons (1 << log_size
);
16266 mips_clear_insn_labels ();
16270 s_float_cons (int type
)
16272 segment_info_type
*si
= seg_info (now_seg
);
16273 struct insn_label_list
*l
= si
->label_list
;
16275 mips_emit_delays ();
16280 mips_align (3, 0, l
);
16282 mips_align (2, 0, l
);
16286 mips_clear_insn_labels ();
16289 /* Handle .globl. We need to override it because on Irix 5 you are
16292 where foo is an undefined symbol, to mean that foo should be
16293 considered to be the address of a function. */
16296 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16305 name
= input_line_pointer
;
16306 c
= get_symbol_end ();
16307 symbolP
= symbol_find_or_make (name
);
16308 S_SET_EXTERNAL (symbolP
);
16310 *input_line_pointer
= c
;
16311 SKIP_WHITESPACE ();
16313 /* On Irix 5, every global symbol that is not explicitly labelled as
16314 being a function is apparently labelled as being an object. */
16317 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16318 && (*input_line_pointer
!= ','))
16323 secname
= input_line_pointer
;
16324 c
= get_symbol_end ();
16325 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16327 as_bad (_("%s: no such section"), secname
);
16328 *input_line_pointer
= c
;
16330 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16331 flag
= BSF_FUNCTION
;
16334 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16336 c
= *input_line_pointer
;
16339 input_line_pointer
++;
16340 SKIP_WHITESPACE ();
16341 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16347 demand_empty_rest_of_line ();
16351 s_option (int x ATTRIBUTE_UNUSED
)
16356 opt
= input_line_pointer
;
16357 c
= get_symbol_end ();
16361 /* FIXME: What does this mean? */
16363 else if (strncmp (opt
, "pic", 3) == 0)
16367 i
= atoi (opt
+ 3);
16372 mips_pic
= SVR4_PIC
;
16373 mips_abicalls
= TRUE
;
16376 as_bad (_(".option pic%d not supported"), i
);
16378 if (mips_pic
== SVR4_PIC
)
16380 if (g_switch_seen
&& g_switch_value
!= 0)
16381 as_warn (_("-G may not be used with SVR4 PIC code"));
16382 g_switch_value
= 0;
16383 bfd_set_gp_size (stdoutput
, 0);
16387 as_warn (_("Unrecognized option \"%s\""), opt
);
16389 *input_line_pointer
= c
;
16390 demand_empty_rest_of_line ();
16393 /* This structure is used to hold a stack of .set values. */
16395 struct mips_option_stack
16397 struct mips_option_stack
*next
;
16398 struct mips_set_options options
;
16401 static struct mips_option_stack
*mips_opts_stack
;
16403 /* Handle the .set pseudo-op. */
16406 s_mipsset (int x ATTRIBUTE_UNUSED
)
16408 char *name
= input_line_pointer
, ch
;
16409 const struct mips_ase
*ase
;
16411 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16412 ++input_line_pointer
;
16413 ch
= *input_line_pointer
;
16414 *input_line_pointer
= '\0';
16416 if (strcmp (name
, "reorder") == 0)
16418 if (mips_opts
.noreorder
)
16421 else if (strcmp (name
, "noreorder") == 0)
16423 if (!mips_opts
.noreorder
)
16424 start_noreorder ();
16426 else if (strncmp (name
, "at=", 3) == 0)
16428 char *s
= name
+ 3;
16430 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16431 as_bad (_("Unrecognized register name `%s'"), s
);
16433 else if (strcmp (name
, "at") == 0)
16435 mips_opts
.at
= ATREG
;
16437 else if (strcmp (name
, "noat") == 0)
16439 mips_opts
.at
= ZERO
;
16441 else if (strcmp (name
, "macro") == 0)
16443 mips_opts
.warn_about_macros
= 0;
16445 else if (strcmp (name
, "nomacro") == 0)
16447 if (mips_opts
.noreorder
== 0)
16448 as_bad (_("`noreorder' must be set before `nomacro'"));
16449 mips_opts
.warn_about_macros
= 1;
16451 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16453 mips_opts
.nomove
= 0;
16455 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16457 mips_opts
.nomove
= 1;
16459 else if (strcmp (name
, "bopt") == 0)
16461 mips_opts
.nobopt
= 0;
16463 else if (strcmp (name
, "nobopt") == 0)
16465 mips_opts
.nobopt
= 1;
16467 else if (strcmp (name
, "gp=default") == 0)
16468 mips_opts
.gp32
= file_mips_gp32
;
16469 else if (strcmp (name
, "gp=32") == 0)
16470 mips_opts
.gp32
= 1;
16471 else if (strcmp (name
, "gp=64") == 0)
16473 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16474 as_warn (_("%s isa does not support 64-bit registers"),
16475 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16476 mips_opts
.gp32
= 0;
16478 else if (strcmp (name
, "fp=default") == 0)
16479 mips_opts
.fp32
= file_mips_fp32
;
16480 else if (strcmp (name
, "fp=32") == 0)
16481 mips_opts
.fp32
= 1;
16482 else if (strcmp (name
, "fp=64") == 0)
16484 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16485 as_warn (_("%s isa does not support 64-bit floating point registers"),
16486 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16487 mips_opts
.fp32
= 0;
16489 else if (strcmp (name
, "softfloat") == 0)
16490 mips_opts
.soft_float
= 1;
16491 else if (strcmp (name
, "hardfloat") == 0)
16492 mips_opts
.soft_float
= 0;
16493 else if (strcmp (name
, "singlefloat") == 0)
16494 mips_opts
.single_float
= 1;
16495 else if (strcmp (name
, "doublefloat") == 0)
16496 mips_opts
.single_float
= 0;
16497 else if (strcmp (name
, "mips16") == 0
16498 || strcmp (name
, "MIPS-16") == 0)
16500 if (mips_opts
.micromips
== 1)
16501 as_fatal (_("`mips16' cannot be used with `micromips'"));
16502 mips_opts
.mips16
= 1;
16504 else if (strcmp (name
, "nomips16") == 0
16505 || strcmp (name
, "noMIPS-16") == 0)
16506 mips_opts
.mips16
= 0;
16507 else if (strcmp (name
, "micromips") == 0)
16509 if (mips_opts
.mips16
== 1)
16510 as_fatal (_("`micromips' cannot be used with `mips16'"));
16511 mips_opts
.micromips
= 1;
16513 else if (strcmp (name
, "nomicromips") == 0)
16514 mips_opts
.micromips
= 0;
16515 else if (name
[0] == 'n'
16517 && (ase
= mips_lookup_ase (name
+ 2)))
16518 mips_set_ase (ase
, FALSE
);
16519 else if ((ase
= mips_lookup_ase (name
)))
16520 mips_set_ase (ase
, TRUE
);
16521 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16525 /* Permit the user to change the ISA and architecture on the fly.
16526 Needless to say, misuse can cause serious problems. */
16527 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16530 mips_opts
.isa
= file_mips_isa
;
16531 mips_opts
.arch
= file_mips_arch
;
16533 else if (strncmp (name
, "arch=", 5) == 0)
16535 const struct mips_cpu_info
*p
;
16537 p
= mips_parse_cpu("internal use", name
+ 5);
16539 as_bad (_("unknown architecture %s"), name
+ 5);
16542 mips_opts
.arch
= p
->cpu
;
16543 mips_opts
.isa
= p
->isa
;
16546 else if (strncmp (name
, "mips", 4) == 0)
16548 const struct mips_cpu_info
*p
;
16550 p
= mips_parse_cpu("internal use", name
);
16552 as_bad (_("unknown ISA level %s"), name
+ 4);
16555 mips_opts
.arch
= p
->cpu
;
16556 mips_opts
.isa
= p
->isa
;
16560 as_bad (_("unknown ISA or architecture %s"), name
);
16562 switch (mips_opts
.isa
)
16570 mips_opts
.gp32
= 1;
16571 mips_opts
.fp32
= 1;
16578 mips_opts
.gp32
= 0;
16579 if (mips_opts
.arch
== CPU_R5900
)
16581 mips_opts
.fp32
= 1;
16585 mips_opts
.fp32
= 0;
16589 as_bad (_("unknown ISA level %s"), name
+ 4);
16594 mips_opts
.gp32
= file_mips_gp32
;
16595 mips_opts
.fp32
= file_mips_fp32
;
16598 else if (strcmp (name
, "autoextend") == 0)
16599 mips_opts
.noautoextend
= 0;
16600 else if (strcmp (name
, "noautoextend") == 0)
16601 mips_opts
.noautoextend
= 1;
16602 else if (strcmp (name
, "insn32") == 0)
16603 mips_opts
.insn32
= TRUE
;
16604 else if (strcmp (name
, "noinsn32") == 0)
16605 mips_opts
.insn32
= FALSE
;
16606 else if (strcmp (name
, "push") == 0)
16608 struct mips_option_stack
*s
;
16610 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16611 s
->next
= mips_opts_stack
;
16612 s
->options
= mips_opts
;
16613 mips_opts_stack
= s
;
16615 else if (strcmp (name
, "pop") == 0)
16617 struct mips_option_stack
*s
;
16619 s
= mips_opts_stack
;
16621 as_bad (_(".set pop with no .set push"));
16624 /* If we're changing the reorder mode we need to handle
16625 delay slots correctly. */
16626 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16627 start_noreorder ();
16628 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16631 mips_opts
= s
->options
;
16632 mips_opts_stack
= s
->next
;
16636 else if (strcmp (name
, "sym32") == 0)
16637 mips_opts
.sym32
= TRUE
;
16638 else if (strcmp (name
, "nosym32") == 0)
16639 mips_opts
.sym32
= FALSE
;
16640 else if (strchr (name
, ','))
16642 /* Generic ".set" directive; use the generic handler. */
16643 *input_line_pointer
= ch
;
16644 input_line_pointer
= name
;
16650 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16652 mips_check_isa_supports_ases ();
16653 *input_line_pointer
= ch
;
16654 demand_empty_rest_of_line ();
16657 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16658 .option pic2. It means to generate SVR4 PIC calls. */
16661 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16663 mips_pic
= SVR4_PIC
;
16664 mips_abicalls
= TRUE
;
16666 if (g_switch_seen
&& g_switch_value
!= 0)
16667 as_warn (_("-G may not be used with SVR4 PIC code"));
16668 g_switch_value
= 0;
16670 bfd_set_gp_size (stdoutput
, 0);
16671 demand_empty_rest_of_line ();
16674 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16675 PIC code. It sets the $gp register for the function based on the
16676 function address, which is in the register named in the argument.
16677 This uses a relocation against _gp_disp, which is handled specially
16678 by the linker. The result is:
16679 lui $gp,%hi(_gp_disp)
16680 addiu $gp,$gp,%lo(_gp_disp)
16681 addu $gp,$gp,.cpload argument
16682 The .cpload argument is normally $25 == $t9.
16684 The -mno-shared option changes this to:
16685 lui $gp,%hi(__gnu_local_gp)
16686 addiu $gp,$gp,%lo(__gnu_local_gp)
16687 and the argument is ignored. This saves an instruction, but the
16688 resulting code is not position independent; it uses an absolute
16689 address for __gnu_local_gp. Thus code assembled with -mno-shared
16690 can go into an ordinary executable, but not into a shared library. */
16693 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16699 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16700 .cpload is ignored. */
16701 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16707 if (mips_opts
.mips16
)
16709 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16710 ignore_rest_of_line ();
16714 /* .cpload should be in a .set noreorder section. */
16715 if (mips_opts
.noreorder
== 0)
16716 as_warn (_(".cpload not in noreorder section"));
16718 reg
= tc_get_register (0);
16720 /* If we need to produce a 64-bit address, we are better off using
16721 the default instruction sequence. */
16722 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16724 ex
.X_op
= O_symbol
;
16725 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16727 ex
.X_op_symbol
= NULL
;
16728 ex
.X_add_number
= 0;
16730 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16731 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16733 mips_mark_labels ();
16734 mips_assembling_insn
= TRUE
;
16737 macro_build_lui (&ex
, mips_gp_register
);
16738 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16739 mips_gp_register
, BFD_RELOC_LO16
);
16741 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16742 mips_gp_register
, reg
);
16745 mips_assembling_insn
= FALSE
;
16746 demand_empty_rest_of_line ();
16749 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16750 .cpsetup $reg1, offset|$reg2, label
16752 If offset is given, this results in:
16753 sd $gp, offset($sp)
16754 lui $gp, %hi(%neg(%gp_rel(label)))
16755 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16756 daddu $gp, $gp, $reg1
16758 If $reg2 is given, this results in:
16759 daddu $reg2, $gp, $0
16760 lui $gp, %hi(%neg(%gp_rel(label)))
16761 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16762 daddu $gp, $gp, $reg1
16763 $reg1 is normally $25 == $t9.
16765 The -mno-shared option replaces the last three instructions with
16767 addiu $gp,$gp,%lo(_gp) */
16770 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16772 expressionS ex_off
;
16773 expressionS ex_sym
;
16776 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16777 We also need NewABI support. */
16778 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16784 if (mips_opts
.mips16
)
16786 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16787 ignore_rest_of_line ();
16791 reg1
= tc_get_register (0);
16792 SKIP_WHITESPACE ();
16793 if (*input_line_pointer
!= ',')
16795 as_bad (_("missing argument separator ',' for .cpsetup"));
16799 ++input_line_pointer
;
16800 SKIP_WHITESPACE ();
16801 if (*input_line_pointer
== '$')
16803 mips_cpreturn_register
= tc_get_register (0);
16804 mips_cpreturn_offset
= -1;
16808 mips_cpreturn_offset
= get_absolute_expression ();
16809 mips_cpreturn_register
= -1;
16811 SKIP_WHITESPACE ();
16812 if (*input_line_pointer
!= ',')
16814 as_bad (_("missing argument separator ',' for .cpsetup"));
16818 ++input_line_pointer
;
16819 SKIP_WHITESPACE ();
16820 expression (&ex_sym
);
16822 mips_mark_labels ();
16823 mips_assembling_insn
= TRUE
;
16826 if (mips_cpreturn_register
== -1)
16828 ex_off
.X_op
= O_constant
;
16829 ex_off
.X_add_symbol
= NULL
;
16830 ex_off
.X_op_symbol
= NULL
;
16831 ex_off
.X_add_number
= mips_cpreturn_offset
;
16833 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16834 BFD_RELOC_LO16
, SP
);
16837 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16838 mips_gp_register
, 0);
16840 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16842 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16843 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16846 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16847 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16848 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16850 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16851 mips_gp_register
, reg1
);
16857 ex
.X_op
= O_symbol
;
16858 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16859 ex
.X_op_symbol
= NULL
;
16860 ex
.X_add_number
= 0;
16862 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16863 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16865 macro_build_lui (&ex
, mips_gp_register
);
16866 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16867 mips_gp_register
, BFD_RELOC_LO16
);
16872 mips_assembling_insn
= FALSE
;
16873 demand_empty_rest_of_line ();
16877 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16879 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16880 .cplocal is ignored. */
16881 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16887 if (mips_opts
.mips16
)
16889 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16890 ignore_rest_of_line ();
16894 mips_gp_register
= tc_get_register (0);
16895 demand_empty_rest_of_line ();
16898 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16899 offset from $sp. The offset is remembered, and after making a PIC
16900 call $gp is restored from that location. */
16903 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16907 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16908 .cprestore is ignored. */
16909 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16915 if (mips_opts
.mips16
)
16917 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16918 ignore_rest_of_line ();
16922 mips_cprestore_offset
= get_absolute_expression ();
16923 mips_cprestore_valid
= 1;
16925 ex
.X_op
= O_constant
;
16926 ex
.X_add_symbol
= NULL
;
16927 ex
.X_op_symbol
= NULL
;
16928 ex
.X_add_number
= mips_cprestore_offset
;
16930 mips_mark_labels ();
16931 mips_assembling_insn
= TRUE
;
16934 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16935 SP
, HAVE_64BIT_ADDRESSES
);
16938 mips_assembling_insn
= FALSE
;
16939 demand_empty_rest_of_line ();
16942 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16943 was given in the preceding .cpsetup, it results in:
16944 ld $gp, offset($sp)
16946 If a register $reg2 was given there, it results in:
16947 daddu $gp, $reg2, $0 */
16950 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16954 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16955 We also need NewABI support. */
16956 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16962 if (mips_opts
.mips16
)
16964 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16965 ignore_rest_of_line ();
16969 mips_mark_labels ();
16970 mips_assembling_insn
= TRUE
;
16973 if (mips_cpreturn_register
== -1)
16975 ex
.X_op
= O_constant
;
16976 ex
.X_add_symbol
= NULL
;
16977 ex
.X_op_symbol
= NULL
;
16978 ex
.X_add_number
= mips_cpreturn_offset
;
16980 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16983 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16984 mips_cpreturn_register
, 0);
16987 mips_assembling_insn
= FALSE
;
16988 demand_empty_rest_of_line ();
16991 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16992 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16993 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16994 debug information or MIPS16 TLS. */
16997 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16998 bfd_reloc_code_real_type rtype
)
17005 if (ex
.X_op
!= O_symbol
)
17007 as_bad (_("Unsupported use of %s"), dirstr
);
17008 ignore_rest_of_line ();
17011 p
= frag_more (bytes
);
17012 md_number_to_chars (p
, 0, bytes
);
17013 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17014 demand_empty_rest_of_line ();
17015 mips_clear_insn_labels ();
17018 /* Handle .dtprelword. */
17021 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17023 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17026 /* Handle .dtpreldword. */
17029 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17031 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17034 /* Handle .tprelword. */
17037 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17039 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17042 /* Handle .tpreldword. */
17045 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17047 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17050 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17051 code. It sets the offset to use in gp_rel relocations. */
17054 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17056 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17057 We also need NewABI support. */
17058 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17064 mips_gprel_offset
= get_absolute_expression ();
17066 demand_empty_rest_of_line ();
17069 /* Handle the .gpword pseudo-op. This is used when generating PIC
17070 code. It generates a 32 bit GP relative reloc. */
17073 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17075 segment_info_type
*si
;
17076 struct insn_label_list
*l
;
17080 /* When not generating PIC code, this is treated as .word. */
17081 if (mips_pic
!= SVR4_PIC
)
17087 si
= seg_info (now_seg
);
17088 l
= si
->label_list
;
17089 mips_emit_delays ();
17091 mips_align (2, 0, l
);
17094 mips_clear_insn_labels ();
17096 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17098 as_bad (_("Unsupported use of .gpword"));
17099 ignore_rest_of_line ();
17103 md_number_to_chars (p
, 0, 4);
17104 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17105 BFD_RELOC_GPREL32
);
17107 demand_empty_rest_of_line ();
17111 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17113 segment_info_type
*si
;
17114 struct insn_label_list
*l
;
17118 /* When not generating PIC code, this is treated as .dword. */
17119 if (mips_pic
!= SVR4_PIC
)
17125 si
= seg_info (now_seg
);
17126 l
= si
->label_list
;
17127 mips_emit_delays ();
17129 mips_align (3, 0, l
);
17132 mips_clear_insn_labels ();
17134 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17136 as_bad (_("Unsupported use of .gpdword"));
17137 ignore_rest_of_line ();
17141 md_number_to_chars (p
, 0, 8);
17142 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17143 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17145 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17146 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17147 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17149 demand_empty_rest_of_line ();
17152 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17153 tables. It generates a R_MIPS_EH reloc. */
17156 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17161 mips_emit_delays ();
17164 mips_clear_insn_labels ();
17166 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17168 as_bad (_("Unsupported use of .ehword"));
17169 ignore_rest_of_line ();
17173 md_number_to_chars (p
, 0, 4);
17174 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17175 BFD_RELOC_MIPS_EH
);
17177 demand_empty_rest_of_line ();
17180 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17181 tables in SVR4 PIC code. */
17184 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17188 /* This is ignored when not generating SVR4 PIC code. */
17189 if (mips_pic
!= SVR4_PIC
)
17195 mips_mark_labels ();
17196 mips_assembling_insn
= TRUE
;
17198 /* Add $gp to the register named as an argument. */
17200 reg
= tc_get_register (0);
17201 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17204 mips_assembling_insn
= FALSE
;
17205 demand_empty_rest_of_line ();
17208 /* Handle the .insn pseudo-op. This marks instruction labels in
17209 mips16/micromips mode. This permits the linker to handle them specially,
17210 such as generating jalx instructions when needed. We also make
17211 them odd for the duration of the assembly, in order to generate the
17212 right sort of code. We will make them even in the adjust_symtab
17213 routine, while leaving them marked. This is convenient for the
17214 debugger and the disassembler. The linker knows to make them odd
17218 s_insn (int ignore ATTRIBUTE_UNUSED
)
17220 mips_mark_labels ();
17222 demand_empty_rest_of_line ();
17225 /* Handle a .stab[snd] directive. Ideally these directives would be
17226 implemented in a transparent way, so that removing them would not
17227 have any effect on the generated instructions. However, s_stab
17228 internally changes the section, so in practice we need to decide
17229 now whether the preceding label marks compressed code. We do not
17230 support changing the compression mode of a label after a .stab*
17231 directive, such as in:
17237 so the current mode wins. */
17240 s_mips_stab (int type
)
17242 mips_mark_labels ();
17246 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17249 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17256 name
= input_line_pointer
;
17257 c
= get_symbol_end ();
17258 symbolP
= symbol_find_or_make (name
);
17259 S_SET_WEAK (symbolP
);
17260 *input_line_pointer
= c
;
17262 SKIP_WHITESPACE ();
17264 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17266 if (S_IS_DEFINED (symbolP
))
17268 as_bad (_("ignoring attempt to redefine symbol %s"),
17269 S_GET_NAME (symbolP
));
17270 ignore_rest_of_line ();
17274 if (*input_line_pointer
== ',')
17276 ++input_line_pointer
;
17277 SKIP_WHITESPACE ();
17281 if (exp
.X_op
!= O_symbol
)
17283 as_bad (_("bad .weakext directive"));
17284 ignore_rest_of_line ();
17287 symbol_set_value_expression (symbolP
, &exp
);
17290 demand_empty_rest_of_line ();
17293 /* Parse a register string into a number. Called from the ECOFF code
17294 to parse .frame. The argument is non-zero if this is the frame
17295 register, so that we can record it in mips_frame_reg. */
17298 tc_get_register (int frame
)
17302 SKIP_WHITESPACE ();
17303 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17307 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17308 mips_frame_reg_valid
= 1;
17309 mips_cprestore_valid
= 0;
17315 md_section_align (asection
*seg
, valueT addr
)
17317 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17319 /* We don't need to align ELF sections to the full alignment.
17320 However, Irix 5 may prefer that we align them at least to a 16
17321 byte boundary. We don't bother to align the sections if we
17322 are targeted for an embedded system. */
17323 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17328 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17331 /* Utility routine, called from above as well. If called while the
17332 input file is still being read, it's only an approximation. (For
17333 example, a symbol may later become defined which appeared to be
17334 undefined earlier.) */
17337 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17342 if (g_switch_value
> 0)
17344 const char *symname
;
17347 /* Find out whether this symbol can be referenced off the $gp
17348 register. It can be if it is smaller than the -G size or if
17349 it is in the .sdata or .sbss section. Certain symbols can
17350 not be referenced off the $gp, although it appears as though
17352 symname
= S_GET_NAME (sym
);
17353 if (symname
!= (const char *) NULL
17354 && (strcmp (symname
, "eprol") == 0
17355 || strcmp (symname
, "etext") == 0
17356 || strcmp (symname
, "_gp") == 0
17357 || strcmp (symname
, "edata") == 0
17358 || strcmp (symname
, "_fbss") == 0
17359 || strcmp (symname
, "_fdata") == 0
17360 || strcmp (symname
, "_ftext") == 0
17361 || strcmp (symname
, "end") == 0
17362 || strcmp (symname
, "_gp_disp") == 0))
17364 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17366 #ifndef NO_ECOFF_DEBUGGING
17367 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17368 && (symbol_get_obj (sym
)->ecoff_extern_size
17369 <= g_switch_value
))
17371 /* We must defer this decision until after the whole
17372 file has been read, since there might be a .extern
17373 after the first use of this symbol. */
17374 || (before_relaxing
17375 #ifndef NO_ECOFF_DEBUGGING
17376 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17378 && S_GET_VALUE (sym
) == 0)
17379 || (S_GET_VALUE (sym
) != 0
17380 && S_GET_VALUE (sym
) <= g_switch_value
)))
17384 const char *segname
;
17386 segname
= segment_name (S_GET_SEGMENT (sym
));
17387 gas_assert (strcmp (segname
, ".lit8") != 0
17388 && strcmp (segname
, ".lit4") != 0);
17389 change
= (strcmp (segname
, ".sdata") != 0
17390 && strcmp (segname
, ".sbss") != 0
17391 && strncmp (segname
, ".sdata.", 7) != 0
17392 && strncmp (segname
, ".sbss.", 6) != 0
17393 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17394 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17399 /* We are not optimizing for the $gp register. */
17404 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17407 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17411 /* Handle the case of a symbol equated to another symbol. */
17412 while (symbol_equated_reloc_p (sym
))
17416 /* It's possible to get a loop here in a badly written program. */
17417 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17423 if (symbol_section_p (sym
))
17426 symsec
= S_GET_SEGMENT (sym
);
17428 /* This must duplicate the test in adjust_reloc_syms. */
17429 return (!bfd_is_und_section (symsec
)
17430 && !bfd_is_abs_section (symsec
)
17431 && !bfd_is_com_section (symsec
)
17432 && !s_is_linkonce (sym
, segtype
)
17433 /* A global or weak symbol is treated as external. */
17434 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17438 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17439 extended opcode. SEC is the section the frag is in. */
17442 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17445 const struct mips16_immed_operand
*op
;
17447 int mintiny
, maxtiny
;
17451 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17453 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17456 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17457 op
= mips16_immed_operands
;
17458 while (op
->type
!= type
)
17461 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17466 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17469 maxtiny
= 1 << op
->nbits
;
17474 maxtiny
= (1 << op
->nbits
) - 1;
17479 mintiny
= - (1 << (op
->nbits
- 1));
17480 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17483 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17484 val
= S_GET_VALUE (fragp
->fr_symbol
);
17485 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17491 /* We won't have the section when we are called from
17492 mips_relax_frag. However, we will always have been called
17493 from md_estimate_size_before_relax first. If this is a
17494 branch to a different section, we mark it as such. If SEC is
17495 NULL, and the frag is not marked, then it must be a branch to
17496 the same section. */
17499 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17504 /* Must have been called from md_estimate_size_before_relax. */
17507 fragp
->fr_subtype
=
17508 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17510 /* FIXME: We should support this, and let the linker
17511 catch branches and loads that are out of range. */
17512 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17513 _("unsupported PC relative reference to different section"));
17517 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17518 /* Assume non-extended on the first relaxation pass.
17519 The address we have calculated will be bogus if this is
17520 a forward branch to another frag, as the forward frag
17521 will have fr_address == 0. */
17525 /* In this case, we know for sure that the symbol fragment is in
17526 the same section. If the relax_marker of the symbol fragment
17527 differs from the relax_marker of this fragment, we have not
17528 yet adjusted the symbol fragment fr_address. We want to add
17529 in STRETCH in order to get a better estimate of the address.
17530 This particularly matters because of the shift bits. */
17532 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17536 /* Adjust stretch for any alignment frag. Note that if have
17537 been expanding the earlier code, the symbol may be
17538 defined in what appears to be an earlier frag. FIXME:
17539 This doesn't handle the fr_subtype field, which specifies
17540 a maximum number of bytes to skip when doing an
17542 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17544 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17547 stretch
= - ((- stretch
)
17548 & ~ ((1 << (int) f
->fr_offset
) - 1));
17550 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17559 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17561 /* The base address rules are complicated. The base address of
17562 a branch is the following instruction. The base address of a
17563 PC relative load or add is the instruction itself, but if it
17564 is in a delay slot (in which case it can not be extended) use
17565 the address of the instruction whose delay slot it is in. */
17566 if (type
== 'p' || type
== 'q')
17570 /* If we are currently assuming that this frag should be
17571 extended, then, the current address is two bytes
17573 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17576 /* Ignore the low bit in the target, since it will be set
17577 for a text label. */
17578 if ((val
& 1) != 0)
17581 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17583 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17586 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17588 /* Branch offsets have an implicit 0 in the lowest bit. */
17589 if (type
== 'p' || type
== 'q')
17592 /* If any of the shifted bits are set, we must use an extended
17593 opcode. If the address depends on the size of this
17594 instruction, this can lead to a loop, so we arrange to always
17595 use an extended opcode. We only check this when we are in
17596 the main relaxation loop, when SEC is NULL. */
17597 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17599 fragp
->fr_subtype
=
17600 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17604 /* If we are about to mark a frag as extended because the value
17605 is precisely maxtiny + 1, then there is a chance of an
17606 infinite loop as in the following code:
17611 In this case when the la is extended, foo is 0x3fc bytes
17612 away, so the la can be shrunk, but then foo is 0x400 away, so
17613 the la must be extended. To avoid this loop, we mark the
17614 frag as extended if it was small, and is about to become
17615 extended with a value of maxtiny + 1. */
17616 if (val
== ((maxtiny
+ 1) << op
->shift
)
17617 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17620 fragp
->fr_subtype
=
17621 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17625 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17626 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17628 if ((val
& ((1 << op
->shift
) - 1)) != 0
17629 || val
< (mintiny
<< op
->shift
)
17630 || val
> (maxtiny
<< op
->shift
))
17636 /* Compute the length of a branch sequence, and adjust the
17637 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17638 worst-case length is computed, with UPDATE being used to indicate
17639 whether an unconditional (-1), branch-likely (+1) or regular (0)
17640 branch is to be computed. */
17642 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17644 bfd_boolean toofar
;
17648 && S_IS_DEFINED (fragp
->fr_symbol
)
17649 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17654 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17656 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17660 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17663 /* If the symbol is not defined or it's in a different segment,
17664 assume the user knows what's going on and emit a short
17670 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17672 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17673 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17674 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17675 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17681 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17684 if (mips_pic
!= NO_PIC
)
17686 /* Additional space for PIC loading of target address. */
17688 if (mips_opts
.isa
== ISA_MIPS1
)
17689 /* Additional space for $at-stabilizing nop. */
17693 /* If branch is conditional. */
17694 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17701 /* Compute the length of a branch sequence, and adjust the
17702 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17703 worst-case length is computed, with UPDATE being used to indicate
17704 whether an unconditional (-1), or regular (0) branch is to be
17708 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17710 bfd_boolean toofar
;
17714 && S_IS_DEFINED (fragp
->fr_symbol
)
17715 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17720 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17721 /* Ignore the low bit in the target, since it will be set
17722 for a text label. */
17723 if ((val
& 1) != 0)
17726 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17730 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17733 /* If the symbol is not defined or it's in a different segment,
17734 assume the user knows what's going on and emit a short
17740 if (fragp
&& update
17741 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17742 fragp
->fr_subtype
= (toofar
17743 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17744 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17749 bfd_boolean compact_known
= fragp
!= NULL
;
17750 bfd_boolean compact
= FALSE
;
17751 bfd_boolean uncond
;
17754 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17756 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17758 uncond
= update
< 0;
17760 /* If label is out of range, we turn branch <br>:
17762 <br> label # 4 bytes
17768 nop # 2 bytes if compact && !PIC
17771 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17774 /* If assembling PIC code, we further turn:
17780 lw/ld at, %got(label)(gp) # 4 bytes
17781 d/addiu at, %lo(label) # 4 bytes
17784 if (mips_pic
!= NO_PIC
)
17787 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17789 <brneg> 0f # 4 bytes
17790 nop # 2 bytes if !compact
17793 length
+= (compact_known
&& compact
) ? 4 : 6;
17799 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17800 bit accordingly. */
17803 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17805 bfd_boolean toofar
;
17808 && S_IS_DEFINED (fragp
->fr_symbol
)
17809 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17815 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17816 /* Ignore the low bit in the target, since it will be set
17817 for a text label. */
17818 if ((val
& 1) != 0)
17821 /* Assume this is a 2-byte branch. */
17822 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17824 /* We try to avoid the infinite loop by not adding 2 more bytes for
17829 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17831 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17832 else if (type
== 'E')
17833 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17838 /* If the symbol is not defined or it's in a different segment,
17839 we emit a normal 32-bit branch. */
17842 if (fragp
&& update
17843 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17845 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17846 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17854 /* Estimate the size of a frag before relaxing. Unless this is the
17855 mips16, we are not really relaxing here, and the final size is
17856 encoded in the subtype information. For the mips16, we have to
17857 decide whether we are using an extended opcode or not. */
17860 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17864 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17867 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17869 return fragp
->fr_var
;
17872 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17873 /* We don't want to modify the EXTENDED bit here; it might get us
17874 into infinite loops. We change it only in mips_relax_frag(). */
17875 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17877 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17881 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17882 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17883 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17884 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17885 fragp
->fr_var
= length
;
17890 if (mips_pic
== NO_PIC
)
17891 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17892 else if (mips_pic
== SVR4_PIC
)
17893 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17894 else if (mips_pic
== VXWORKS_PIC
)
17895 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17902 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17903 return -RELAX_FIRST (fragp
->fr_subtype
);
17906 return -RELAX_SECOND (fragp
->fr_subtype
);
17909 /* This is called to see whether a reloc against a defined symbol
17910 should be converted into a reloc against a section. */
17913 mips_fix_adjustable (fixS
*fixp
)
17915 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17916 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17919 if (fixp
->fx_addsy
== NULL
)
17922 /* If symbol SYM is in a mergeable section, relocations of the form
17923 SYM + 0 can usually be made section-relative. The mergeable data
17924 is then identified by the section offset rather than by the symbol.
17926 However, if we're generating REL LO16 relocations, the offset is split
17927 between the LO16 and parterning high part relocation. The linker will
17928 need to recalculate the complete offset in order to correctly identify
17931 The linker has traditionally not looked for the parterning high part
17932 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17933 placed anywhere. Rather than break backwards compatibility by changing
17934 this, it seems better not to force the issue, and instead keep the
17935 original symbol. This will work with either linker behavior. */
17936 if ((lo16_reloc_p (fixp
->fx_r_type
)
17937 || reloc_needs_lo_p (fixp
->fx_r_type
))
17938 && HAVE_IN_PLACE_ADDENDS
17939 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17942 /* There is no place to store an in-place offset for JALR relocations.
17943 Likewise an in-range offset of limited PC-relative relocations may
17944 overflow the in-place relocatable field if recalculated against the
17945 start address of the symbol's containing section. */
17946 if (HAVE_IN_PLACE_ADDENDS
17947 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17948 || jalr_reloc_p (fixp
->fx_r_type
)))
17951 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17952 to a floating-point stub. The same is true for non-R_MIPS16_26
17953 relocations against MIPS16 functions; in this case, the stub becomes
17954 the function's canonical address.
17956 Floating-point stubs are stored in unique .mips16.call.* or
17957 .mips16.fn.* sections. If a stub T for function F is in section S,
17958 the first relocation in section S must be against F; this is how the
17959 linker determines the target function. All relocations that might
17960 resolve to T must also be against F. We therefore have the following
17961 restrictions, which are given in an intentionally-redundant way:
17963 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17966 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17967 if that stub might be used.
17969 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17972 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17973 that stub might be used.
17975 There is a further restriction:
17977 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17978 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17979 targets with in-place addends; the relocation field cannot
17980 encode the low bit.
17982 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17983 against a MIPS16 symbol. We deal with (5) by by not reducing any
17984 such relocations on REL targets.
17986 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17987 relocation against some symbol R, no relocation against R may be
17988 reduced. (Note that this deals with (2) as well as (1) because
17989 relocations against global symbols will never be reduced on ELF
17990 targets.) This approach is a little simpler than trying to detect
17991 stub sections, and gives the "all or nothing" per-symbol consistency
17992 that we have for MIPS16 symbols. */
17993 if (fixp
->fx_subsy
== NULL
17994 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17995 || *symbol_get_tc (fixp
->fx_addsy
)
17996 || (HAVE_IN_PLACE_ADDENDS
17997 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17998 && jmp_reloc_p (fixp
->fx_r_type
))))
18004 /* Translate internal representation of relocation info to BFD target
18008 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18010 static arelent
*retval
[4];
18012 bfd_reloc_code_real_type code
;
18014 memset (retval
, 0, sizeof(retval
));
18015 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
18016 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
18017 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18018 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18020 if (fixp
->fx_pcrel
)
18022 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18023 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18024 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18025 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18026 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
18028 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18029 Relocations want only the symbol offset. */
18030 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18033 reloc
->addend
= fixp
->fx_addnumber
;
18035 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18036 entry to be used in the relocation's section offset. */
18037 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18039 reloc
->address
= reloc
->addend
;
18043 code
= fixp
->fx_r_type
;
18045 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18046 if (reloc
->howto
== NULL
)
18048 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18049 _("Can not represent %s relocation in this object file format"),
18050 bfd_get_reloc_code_name (code
));
18057 /* Relax a machine dependent frag. This returns the amount by which
18058 the current size of the frag should change. */
18061 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18063 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18065 offsetT old_var
= fragp
->fr_var
;
18067 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18069 return fragp
->fr_var
- old_var
;
18072 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18074 offsetT old_var
= fragp
->fr_var
;
18075 offsetT new_var
= 4;
18077 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18078 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18079 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18080 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18081 fragp
->fr_var
= new_var
;
18083 return new_var
- old_var
;
18086 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18089 if (mips16_extended_frag (fragp
, NULL
, stretch
))
18091 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18093 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18098 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18100 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18107 /* Convert a machine dependent frag. */
18110 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18112 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18115 unsigned long insn
;
18119 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18120 insn
= read_insn (buf
);
18122 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18124 /* We generate a fixup instead of applying it right now
18125 because, if there are linker relaxations, we're going to
18126 need the relocations. */
18127 exp
.X_op
= O_symbol
;
18128 exp
.X_add_symbol
= fragp
->fr_symbol
;
18129 exp
.X_add_number
= fragp
->fr_offset
;
18131 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18132 BFD_RELOC_16_PCREL_S2
);
18133 fixp
->fx_file
= fragp
->fr_file
;
18134 fixp
->fx_line
= fragp
->fr_line
;
18136 buf
= write_insn (buf
, insn
);
18142 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18143 _("Relaxed out-of-range branch into a jump"));
18145 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18148 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18150 /* Reverse the branch. */
18151 switch ((insn
>> 28) & 0xf)
18154 /* bc[0-3][tf]l? instructions can have the condition
18155 reversed by tweaking a single TF bit, and their
18156 opcodes all have 0x4???????. */
18157 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18158 insn
^= 0x00010000;
18162 /* bltz 0x04000000 bgez 0x04010000
18163 bltzal 0x04100000 bgezal 0x04110000 */
18164 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18165 insn
^= 0x00010000;
18169 /* beq 0x10000000 bne 0x14000000
18170 blez 0x18000000 bgtz 0x1c000000 */
18171 insn
^= 0x04000000;
18179 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18181 /* Clear the and-link bit. */
18182 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18184 /* bltzal 0x04100000 bgezal 0x04110000
18185 bltzall 0x04120000 bgezall 0x04130000 */
18186 insn
&= ~0x00100000;
18189 /* Branch over the branch (if the branch was likely) or the
18190 full jump (not likely case). Compute the offset from the
18191 current instruction to branch to. */
18192 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18196 /* How many bytes in instructions we've already emitted? */
18197 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18198 /* How many bytes in instructions from here to the end? */
18199 i
= fragp
->fr_var
- i
;
18201 /* Convert to instruction count. */
18203 /* Branch counts from the next instruction. */
18206 /* Branch over the jump. */
18207 buf
= write_insn (buf
, insn
);
18210 buf
= write_insn (buf
, 0);
18212 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18214 /* beql $0, $0, 2f */
18216 /* Compute the PC offset from the current instruction to
18217 the end of the variable frag. */
18218 /* How many bytes in instructions we've already emitted? */
18219 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18220 /* How many bytes in instructions from here to the end? */
18221 i
= fragp
->fr_var
- i
;
18222 /* Convert to instruction count. */
18224 /* Don't decrement i, because we want to branch over the
18228 buf
= write_insn (buf
, insn
);
18229 buf
= write_insn (buf
, 0);
18233 if (mips_pic
== NO_PIC
)
18236 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18237 ? 0x0c000000 : 0x08000000);
18238 exp
.X_op
= O_symbol
;
18239 exp
.X_add_symbol
= fragp
->fr_symbol
;
18240 exp
.X_add_number
= fragp
->fr_offset
;
18242 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18243 FALSE
, BFD_RELOC_MIPS_JMP
);
18244 fixp
->fx_file
= fragp
->fr_file
;
18245 fixp
->fx_line
= fragp
->fr_line
;
18247 buf
= write_insn (buf
, insn
);
18251 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18253 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18254 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18255 insn
|= at
<< OP_SH_RT
;
18256 exp
.X_op
= O_symbol
;
18257 exp
.X_add_symbol
= fragp
->fr_symbol
;
18258 exp
.X_add_number
= fragp
->fr_offset
;
18260 if (fragp
->fr_offset
)
18262 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18263 exp
.X_add_number
= 0;
18266 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18267 FALSE
, BFD_RELOC_MIPS_GOT16
);
18268 fixp
->fx_file
= fragp
->fr_file
;
18269 fixp
->fx_line
= fragp
->fr_line
;
18271 buf
= write_insn (buf
, insn
);
18273 if (mips_opts
.isa
== ISA_MIPS1
)
18275 buf
= write_insn (buf
, 0);
18277 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18278 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18279 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18281 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18282 FALSE
, BFD_RELOC_LO16
);
18283 fixp
->fx_file
= fragp
->fr_file
;
18284 fixp
->fx_line
= fragp
->fr_line
;
18286 buf
= write_insn (buf
, insn
);
18289 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18293 insn
|= at
<< OP_SH_RS
;
18295 buf
= write_insn (buf
, insn
);
18299 fragp
->fr_fix
+= fragp
->fr_var
;
18300 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18304 /* Relax microMIPS branches. */
18305 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18307 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18308 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18309 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18310 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18311 bfd_boolean short_ds
;
18312 unsigned long insn
;
18316 exp
.X_op
= O_symbol
;
18317 exp
.X_add_symbol
= fragp
->fr_symbol
;
18318 exp
.X_add_number
= fragp
->fr_offset
;
18320 fragp
->fr_fix
+= fragp
->fr_var
;
18322 /* Handle 16-bit branches that fit or are forced to fit. */
18323 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18325 /* We generate a fixup instead of applying it right now,
18326 because if there is linker relaxation, we're going to
18327 need the relocations. */
18329 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18330 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18331 else if (type
== 'E')
18332 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18333 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18337 fixp
->fx_file
= fragp
->fr_file
;
18338 fixp
->fx_line
= fragp
->fr_line
;
18340 /* These relocations can have an addend that won't fit in
18342 fixp
->fx_no_overflow
= 1;
18347 /* Handle 32-bit branches that fit or are forced to fit. */
18348 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18349 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18351 /* We generate a fixup instead of applying it right now,
18352 because if there is linker relaxation, we're going to
18353 need the relocations. */
18354 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18355 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18356 fixp
->fx_file
= fragp
->fr_file
;
18357 fixp
->fx_line
= fragp
->fr_line
;
18363 /* Relax 16-bit branches to 32-bit branches. */
18366 insn
= read_compressed_insn (buf
, 2);
18368 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18369 insn
= 0x94000000; /* beq */
18370 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18372 unsigned long regno
;
18374 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18375 regno
= micromips_to_32_reg_d_map
[regno
];
18376 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18377 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18382 /* Nothing else to do, just write it out. */
18383 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18384 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18386 buf
= write_compressed_insn (buf
, insn
, 4);
18387 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18392 insn
= read_compressed_insn (buf
, 4);
18394 /* Relax 32-bit branches to a sequence of instructions. */
18395 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18396 _("Relaxed out-of-range branch into a jump"));
18398 /* Set the short-delay-slot bit. */
18399 short_ds
= al
&& (insn
& 0x02000000) != 0;
18401 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18405 /* Reverse the branch. */
18406 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18407 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18408 insn
^= 0x20000000;
18409 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18410 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18411 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18412 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18413 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18414 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18415 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18416 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18417 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18418 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18419 insn
^= 0x00400000;
18420 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18421 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18422 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18423 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18424 insn
^= 0x00200000;
18430 /* Clear the and-link and short-delay-slot bits. */
18431 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18433 /* bltzal 0x40200000 bgezal 0x40600000 */
18434 /* bltzals 0x42200000 bgezals 0x42600000 */
18435 insn
&= ~0x02200000;
18438 /* Make a label at the end for use with the branch. */
18439 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18440 micromips_label_inc ();
18441 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18444 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18445 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18446 fixp
->fx_file
= fragp
->fr_file
;
18447 fixp
->fx_line
= fragp
->fr_line
;
18449 /* Branch over the jump. */
18450 buf
= write_compressed_insn (buf
, insn
, 4);
18453 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18456 if (mips_pic
== NO_PIC
)
18458 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18460 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18461 insn
= al
? jal
: 0xd4000000;
18463 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18464 BFD_RELOC_MICROMIPS_JMP
);
18465 fixp
->fx_file
= fragp
->fr_file
;
18466 fixp
->fx_line
= fragp
->fr_line
;
18468 buf
= write_compressed_insn (buf
, insn
, 4);
18471 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18475 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18476 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18477 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18479 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18480 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18481 insn
|= at
<< MICROMIPSOP_SH_RT
;
18483 if (exp
.X_add_number
)
18485 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18486 exp
.X_add_number
= 0;
18489 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18490 BFD_RELOC_MICROMIPS_GOT16
);
18491 fixp
->fx_file
= fragp
->fr_file
;
18492 fixp
->fx_line
= fragp
->fr_line
;
18494 buf
= write_compressed_insn (buf
, insn
, 4);
18496 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18497 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18498 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18500 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18501 BFD_RELOC_MICROMIPS_LO16
);
18502 fixp
->fx_file
= fragp
->fr_file
;
18503 fixp
->fx_line
= fragp
->fr_line
;
18505 buf
= write_compressed_insn (buf
, insn
, 4);
18507 /* jr/jrc/jalr/jalrs $at */
18508 insn
= al
? jalr
: jr
;
18509 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18511 buf
= write_compressed_insn (buf
, insn
, 2);
18514 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18518 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18521 const struct mips16_immed_operand
*op
;
18524 unsigned int user_length
, length
;
18525 unsigned long insn
;
18528 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18529 op
= mips16_immed_operands
;
18530 while (op
->type
!= type
)
18533 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18534 val
= resolve_symbol_value (fragp
->fr_symbol
);
18539 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18541 /* The rules for the base address of a PC relative reloc are
18542 complicated; see mips16_extended_frag. */
18543 if (type
== 'p' || type
== 'q')
18548 /* Ignore the low bit in the target, since it will be
18549 set for a text label. */
18550 if ((val
& 1) != 0)
18553 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18555 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18558 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18561 /* Make sure the section winds up with the alignment we have
18564 record_alignment (asec
, op
->shift
);
18568 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18569 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18570 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18571 _("extended instruction in delay slot"));
18573 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18575 insn
= read_compressed_insn (buf
, 2);
18577 insn
|= MIPS16_EXTEND
;
18579 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18581 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18586 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18587 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18589 length
= (ext
? 4 : 2);
18590 gas_assert (mips16_opcode_length (insn
) == length
);
18591 write_compressed_insn (buf
, insn
, length
);
18592 fragp
->fr_fix
+= length
;
18596 relax_substateT subtype
= fragp
->fr_subtype
;
18597 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18598 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18602 first
= RELAX_FIRST (subtype
);
18603 second
= RELAX_SECOND (subtype
);
18604 fixp
= (fixS
*) fragp
->fr_opcode
;
18606 /* If the delay slot chosen does not match the size of the instruction,
18607 then emit a warning. */
18608 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18609 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18614 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18615 | RELAX_DELAY_SLOT_SIZE_FIRST
18616 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18617 msg
= macro_warning (s
);
18619 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18623 /* Possibly emit a warning if we've chosen the longer option. */
18624 if (use_second
== second_longer
)
18630 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18631 msg
= macro_warning (s
);
18633 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18637 /* Go through all the fixups for the first sequence. Disable them
18638 (by marking them as done) if we're going to use the second
18639 sequence instead. */
18641 && fixp
->fx_frag
== fragp
18642 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18644 if (subtype
& RELAX_USE_SECOND
)
18646 fixp
= fixp
->fx_next
;
18649 /* Go through the fixups for the second sequence. Disable them if
18650 we're going to use the first sequence, otherwise adjust their
18651 addresses to account for the relaxation. */
18652 while (fixp
&& fixp
->fx_frag
== fragp
)
18654 if (subtype
& RELAX_USE_SECOND
)
18655 fixp
->fx_where
-= first
;
18658 fixp
= fixp
->fx_next
;
18661 /* Now modify the frag contents. */
18662 if (subtype
& RELAX_USE_SECOND
)
18666 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18667 memmove (start
, start
+ first
, second
);
18668 fragp
->fr_fix
-= first
;
18671 fragp
->fr_fix
-= second
;
18675 /* This function is called after the relocs have been generated.
18676 We've been storing mips16 text labels as odd. Here we convert them
18677 back to even for the convenience of the debugger. */
18680 mips_frob_file_after_relocs (void)
18683 unsigned int count
, i
;
18685 syms
= bfd_get_outsymbols (stdoutput
);
18686 count
= bfd_get_symcount (stdoutput
);
18687 for (i
= 0; i
< count
; i
++, syms
++)
18688 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18689 && ((*syms
)->value
& 1) != 0)
18691 (*syms
)->value
&= ~1;
18692 /* If the symbol has an odd size, it was probably computed
18693 incorrectly, so adjust that as well. */
18694 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18695 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18699 /* This function is called whenever a label is defined, including fake
18700 labels instantiated off the dot special symbol. It is used when
18701 handling branch delays; if a branch has a label, we assume we cannot
18702 move it. This also bumps the value of the symbol by 1 in compressed
18706 mips_record_label (symbolS
*sym
)
18708 segment_info_type
*si
= seg_info (now_seg
);
18709 struct insn_label_list
*l
;
18711 if (free_insn_labels
== NULL
)
18712 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18715 l
= free_insn_labels
;
18716 free_insn_labels
= l
->next
;
18720 l
->next
= si
->label_list
;
18721 si
->label_list
= l
;
18724 /* This function is called as tc_frob_label() whenever a label is defined
18725 and adds a DWARF-2 record we only want for true labels. */
18728 mips_define_label (symbolS
*sym
)
18730 mips_record_label (sym
);
18731 dwarf2_emit_label (sym
);
18734 /* This function is called by tc_new_dot_label whenever a new dot symbol
18738 mips_add_dot_label (symbolS
*sym
)
18740 mips_record_label (sym
);
18741 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18742 mips_compressed_mark_label (sym
);
18745 /* Some special processing for a MIPS ELF file. */
18748 mips_elf_final_processing (void)
18750 /* Write out the register information. */
18751 if (mips_abi
!= N64_ABI
)
18755 s
.ri_gprmask
= mips_gprmask
;
18756 s
.ri_cprmask
[0] = mips_cprmask
[0];
18757 s
.ri_cprmask
[1] = mips_cprmask
[1];
18758 s
.ri_cprmask
[2] = mips_cprmask
[2];
18759 s
.ri_cprmask
[3] = mips_cprmask
[3];
18760 /* The gp_value field is set by the MIPS ELF backend. */
18762 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18763 ((Elf32_External_RegInfo
*)
18764 mips_regmask_frag
));
18768 Elf64_Internal_RegInfo s
;
18770 s
.ri_gprmask
= mips_gprmask
;
18772 s
.ri_cprmask
[0] = mips_cprmask
[0];
18773 s
.ri_cprmask
[1] = mips_cprmask
[1];
18774 s
.ri_cprmask
[2] = mips_cprmask
[2];
18775 s
.ri_cprmask
[3] = mips_cprmask
[3];
18776 /* The gp_value field is set by the MIPS ELF backend. */
18778 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18779 ((Elf64_External_RegInfo
*)
18780 mips_regmask_frag
));
18783 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18784 sort of BFD interface for this. */
18785 if (mips_any_noreorder
)
18786 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18787 if (mips_pic
!= NO_PIC
)
18789 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18790 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18793 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18795 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18796 defined at present; this might need to change in future. */
18797 if (file_ase_mips16
)
18798 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18799 if (file_ase_micromips
)
18800 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18801 if (file_ase
& ASE_MDMX
)
18802 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18804 /* Set the MIPS ELF ABI flags. */
18805 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18806 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18807 else if (mips_abi
== O64_ABI
)
18808 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18809 else if (mips_abi
== EABI_ABI
)
18811 if (!file_mips_gp32
)
18812 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18814 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18816 else if (mips_abi
== N32_ABI
)
18817 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18819 /* Nothing to do for N64_ABI. */
18821 if (mips_32bitmode
)
18822 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18824 #if 0 /* XXX FIXME */
18825 /* 32 bit code with 64 bit FP registers. */
18826 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18827 elf_elfheader (stdoutput
)->e_flags
|= ???;
18831 typedef struct proc
{
18833 symbolS
*func_end_sym
;
18834 unsigned long reg_mask
;
18835 unsigned long reg_offset
;
18836 unsigned long fpreg_mask
;
18837 unsigned long fpreg_offset
;
18838 unsigned long frame_offset
;
18839 unsigned long frame_reg
;
18840 unsigned long pc_reg
;
18843 static procS cur_proc
;
18844 static procS
*cur_proc_ptr
;
18845 static int numprocs
;
18847 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18848 as "2", and a normal nop as "0". */
18850 #define NOP_OPCODE_MIPS 0
18851 #define NOP_OPCODE_MIPS16 1
18852 #define NOP_OPCODE_MICROMIPS 2
18855 mips_nop_opcode (void)
18857 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18858 return NOP_OPCODE_MICROMIPS
;
18859 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18860 return NOP_OPCODE_MIPS16
;
18862 return NOP_OPCODE_MIPS
;
18865 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18866 32-bit microMIPS NOPs here (if applicable). */
18869 mips_handle_align (fragS
*fragp
)
18873 int bytes
, size
, excess
;
18876 if (fragp
->fr_type
!= rs_align_code
)
18879 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18881 switch (nop_opcode
)
18883 case NOP_OPCODE_MICROMIPS
:
18884 opcode
= micromips_nop32_insn
.insn_opcode
;
18887 case NOP_OPCODE_MIPS16
:
18888 opcode
= mips16_nop_insn
.insn_opcode
;
18891 case NOP_OPCODE_MIPS
:
18893 opcode
= nop_insn
.insn_opcode
;
18898 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18899 excess
= bytes
% size
;
18901 /* Handle the leading part if we're not inserting a whole number of
18902 instructions, and make it the end of the fixed part of the frag.
18903 Try to fit in a short microMIPS NOP if applicable and possible,
18904 and use zeroes otherwise. */
18905 gas_assert (excess
< 4);
18906 fragp
->fr_fix
+= excess
;
18911 /* Fall through. */
18913 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18915 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18919 /* Fall through. */
18922 /* Fall through. */
18927 md_number_to_chars (p
, opcode
, size
);
18928 fragp
->fr_var
= size
;
18932 md_obj_begin (void)
18939 /* Check for premature end, nesting errors, etc. */
18941 as_warn (_("missing .end at end of assembly"));
18950 if (*input_line_pointer
== '-')
18952 ++input_line_pointer
;
18955 if (!ISDIGIT (*input_line_pointer
))
18956 as_bad (_("expected simple number"));
18957 if (input_line_pointer
[0] == '0')
18959 if (input_line_pointer
[1] == 'x')
18961 input_line_pointer
+= 2;
18962 while (ISXDIGIT (*input_line_pointer
))
18965 val
|= hex_value (*input_line_pointer
++);
18967 return negative
? -val
: val
;
18971 ++input_line_pointer
;
18972 while (ISDIGIT (*input_line_pointer
))
18975 val
|= *input_line_pointer
++ - '0';
18977 return negative
? -val
: val
;
18980 if (!ISDIGIT (*input_line_pointer
))
18982 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18983 *input_line_pointer
, *input_line_pointer
);
18984 as_warn (_("invalid number"));
18987 while (ISDIGIT (*input_line_pointer
))
18990 val
+= *input_line_pointer
++ - '0';
18992 return negative
? -val
: val
;
18995 /* The .file directive; just like the usual .file directive, but there
18996 is an initial number which is the ECOFF file index. In the non-ECOFF
18997 case .file implies DWARF-2. */
19000 s_mips_file (int x ATTRIBUTE_UNUSED
)
19002 static int first_file_directive
= 0;
19004 if (ECOFF_DEBUGGING
)
19013 filename
= dwarf2_directive_file (0);
19015 /* Versions of GCC up to 3.1 start files with a ".file"
19016 directive even for stabs output. Make sure that this
19017 ".file" is handled. Note that you need a version of GCC
19018 after 3.1 in order to support DWARF-2 on MIPS. */
19019 if (filename
!= NULL
&& ! first_file_directive
)
19021 (void) new_logical_line (filename
, -1);
19022 s_app_file_string (filename
, 0);
19024 first_file_directive
= 1;
19028 /* The .loc directive, implying DWARF-2. */
19031 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19033 if (!ECOFF_DEBUGGING
)
19034 dwarf2_directive_loc (0);
19037 /* The .end directive. */
19040 s_mips_end (int x ATTRIBUTE_UNUSED
)
19044 /* Following functions need their own .frame and .cprestore directives. */
19045 mips_frame_reg_valid
= 0;
19046 mips_cprestore_valid
= 0;
19048 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19051 demand_empty_rest_of_line ();
19056 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19057 as_warn (_(".end not in text section"));
19061 as_warn (_(".end directive without a preceding .ent directive."));
19062 demand_empty_rest_of_line ();
19068 gas_assert (S_GET_NAME (p
));
19069 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19070 as_warn (_(".end symbol does not match .ent symbol."));
19072 if (debug_type
== DEBUG_STABS
)
19073 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19077 as_warn (_(".end directive missing or unknown symbol"));
19079 /* Create an expression to calculate the size of the function. */
19080 if (p
&& cur_proc_ptr
)
19082 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19083 expressionS
*exp
= xmalloc (sizeof (expressionS
));
19086 exp
->X_op
= O_subtract
;
19087 exp
->X_add_symbol
= symbol_temp_new_now ();
19088 exp
->X_op_symbol
= p
;
19089 exp
->X_add_number
= 0;
19091 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19094 /* Generate a .pdr section. */
19095 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19097 segT saved_seg
= now_seg
;
19098 subsegT saved_subseg
= now_subseg
;
19102 #ifdef md_flush_pending_output
19103 md_flush_pending_output ();
19106 gas_assert (pdr_seg
);
19107 subseg_set (pdr_seg
, 0);
19109 /* Write the symbol. */
19110 exp
.X_op
= O_symbol
;
19111 exp
.X_add_symbol
= p
;
19112 exp
.X_add_number
= 0;
19113 emit_expr (&exp
, 4);
19115 fragp
= frag_more (7 * 4);
19117 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19118 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19119 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19120 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19121 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19122 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19123 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19125 subseg_set (saved_seg
, saved_subseg
);
19128 cur_proc_ptr
= NULL
;
19131 /* The .aent and .ent directives. */
19134 s_mips_ent (int aent
)
19138 symbolP
= get_symbol ();
19139 if (*input_line_pointer
== ',')
19140 ++input_line_pointer
;
19141 SKIP_WHITESPACE ();
19142 if (ISDIGIT (*input_line_pointer
)
19143 || *input_line_pointer
== '-')
19146 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19147 as_warn (_(".ent or .aent not in text section."));
19149 if (!aent
&& cur_proc_ptr
)
19150 as_warn (_("missing .end"));
19154 /* This function needs its own .frame and .cprestore directives. */
19155 mips_frame_reg_valid
= 0;
19156 mips_cprestore_valid
= 0;
19158 cur_proc_ptr
= &cur_proc
;
19159 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19161 cur_proc_ptr
->func_sym
= symbolP
;
19165 if (debug_type
== DEBUG_STABS
)
19166 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19167 S_GET_NAME (symbolP
));
19170 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19172 demand_empty_rest_of_line ();
19175 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19176 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19177 s_mips_frame is used so that we can set the PDR information correctly.
19178 We can't use the ecoff routines because they make reference to the ecoff
19179 symbol table (in the mdebug section). */
19182 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19184 if (ECOFF_DEBUGGING
)
19190 if (cur_proc_ptr
== (procS
*) NULL
)
19192 as_warn (_(".frame outside of .ent"));
19193 demand_empty_rest_of_line ();
19197 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19199 SKIP_WHITESPACE ();
19200 if (*input_line_pointer
++ != ','
19201 || get_absolute_expression_and_terminator (&val
) != ',')
19203 as_warn (_("Bad .frame directive"));
19204 --input_line_pointer
;
19205 demand_empty_rest_of_line ();
19209 cur_proc_ptr
->frame_offset
= val
;
19210 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19212 demand_empty_rest_of_line ();
19216 /* The .fmask and .mask directives. If the mdebug section is present
19217 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19218 embedded targets, s_mips_mask is used so that we can set the PDR
19219 information correctly. We can't use the ecoff routines because they
19220 make reference to the ecoff symbol table (in the mdebug section). */
19223 s_mips_mask (int reg_type
)
19225 if (ECOFF_DEBUGGING
)
19226 s_ignore (reg_type
);
19231 if (cur_proc_ptr
== (procS
*) NULL
)
19233 as_warn (_(".mask/.fmask outside of .ent"));
19234 demand_empty_rest_of_line ();
19238 if (get_absolute_expression_and_terminator (&mask
) != ',')
19240 as_warn (_("Bad .mask/.fmask directive"));
19241 --input_line_pointer
;
19242 demand_empty_rest_of_line ();
19246 off
= get_absolute_expression ();
19248 if (reg_type
== 'F')
19250 cur_proc_ptr
->fpreg_mask
= mask
;
19251 cur_proc_ptr
->fpreg_offset
= off
;
19255 cur_proc_ptr
->reg_mask
= mask
;
19256 cur_proc_ptr
->reg_offset
= off
;
19259 demand_empty_rest_of_line ();
19263 /* A table describing all the processors gas knows about. Names are
19264 matched in the order listed.
19266 To ease comparison, please keep this table in the same order as
19267 gcc's mips_cpu_info_table[]. */
19268 static const struct mips_cpu_info mips_cpu_info_table
[] =
19270 /* Entries for generic ISAs */
19271 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19272 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19273 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19274 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19275 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19276 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19277 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19278 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19279 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19282 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19283 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19284 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19287 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19290 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19291 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19292 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19293 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19294 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19295 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19296 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19297 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19298 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19299 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19300 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19301 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19302 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19303 /* ST Microelectronics Loongson 2E and 2F cores */
19304 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19305 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19308 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19309 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19310 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19311 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19312 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19313 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19314 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19315 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19316 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19317 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19318 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19319 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19320 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19321 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19322 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19325 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19326 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19327 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19328 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19330 /* MIPS 32 Release 2 */
19331 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19332 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19333 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19334 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19335 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19336 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19337 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19338 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19339 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19340 ISA_MIPS32R2
, CPU_MIPS32R2
},
19341 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19342 ISA_MIPS32R2
, CPU_MIPS32R2
},
19343 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19344 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19345 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19346 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19347 /* Deprecated forms of the above. */
19348 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19349 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19350 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19351 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19352 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19353 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19354 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19355 /* Deprecated forms of the above. */
19356 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19357 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19358 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19359 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19360 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19361 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19362 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19363 /* Deprecated forms of the above. */
19364 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19365 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19366 /* 34Kn is a 34kc without DSP. */
19367 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19368 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19369 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19370 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19371 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19372 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19373 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19374 /* Deprecated forms of the above. */
19375 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19376 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19377 /* 1004K cores are multiprocessor versions of the 34K. */
19378 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19379 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19380 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19381 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19384 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19385 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19386 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19387 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19389 /* Broadcom SB-1 CPU core */
19390 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19391 /* Broadcom SB-1A CPU core */
19392 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19394 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19396 /* MIPS 64 Release 2 */
19398 /* Cavium Networks Octeon CPU core */
19399 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19400 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19401 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19404 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19407 XLP is mostly like XLR, with the prominent exception that it is
19408 MIPS64R2 rather than MIPS64. */
19409 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19412 { NULL
, 0, 0, 0, 0 }
19416 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19417 with a final "000" replaced by "k". Ignore case.
19419 Note: this function is shared between GCC and GAS. */
19422 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19424 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19425 given
++, canonical
++;
19427 return ((*given
== 0 && *canonical
== 0)
19428 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19432 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19433 CPU name. We've traditionally allowed a lot of variation here.
19435 Note: this function is shared between GCC and GAS. */
19438 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19440 /* First see if the name matches exactly, or with a final "000"
19441 turned into "k". */
19442 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19445 /* If not, try comparing based on numerical designation alone.
19446 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19447 if (TOLOWER (*given
) == 'r')
19449 if (!ISDIGIT (*given
))
19452 /* Skip over some well-known prefixes in the canonical name,
19453 hoping to find a number there too. */
19454 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19456 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19458 else if (TOLOWER (canonical
[0]) == 'r')
19461 return mips_strict_matching_cpu_name_p (canonical
, given
);
19465 /* Parse an option that takes the name of a processor as its argument.
19466 OPTION is the name of the option and CPU_STRING is the argument.
19467 Return the corresponding processor enumeration if the CPU_STRING is
19468 recognized, otherwise report an error and return null.
19470 A similar function exists in GCC. */
19472 static const struct mips_cpu_info
*
19473 mips_parse_cpu (const char *option
, const char *cpu_string
)
19475 const struct mips_cpu_info
*p
;
19477 /* 'from-abi' selects the most compatible architecture for the given
19478 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19479 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19480 version. Look first at the -mgp options, if given, otherwise base
19481 the choice on MIPS_DEFAULT_64BIT.
19483 Treat NO_ABI like the EABIs. One reason to do this is that the
19484 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19485 architecture. This code picks MIPS I for 'mips' and MIPS III for
19486 'mips64', just as we did in the days before 'from-abi'. */
19487 if (strcasecmp (cpu_string
, "from-abi") == 0)
19489 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19490 return mips_cpu_info_from_isa (ISA_MIPS1
);
19492 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19493 return mips_cpu_info_from_isa (ISA_MIPS3
);
19495 if (file_mips_gp32
>= 0)
19496 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19498 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19503 /* 'default' has traditionally been a no-op. Probably not very useful. */
19504 if (strcasecmp (cpu_string
, "default") == 0)
19507 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19508 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19511 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19515 /* Return the canonical processor information for ISA (a member of the
19516 ISA_MIPS* enumeration). */
19518 static const struct mips_cpu_info
*
19519 mips_cpu_info_from_isa (int isa
)
19523 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19524 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19525 && isa
== mips_cpu_info_table
[i
].isa
)
19526 return (&mips_cpu_info_table
[i
]);
19531 static const struct mips_cpu_info
*
19532 mips_cpu_info_from_arch (int arch
)
19536 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19537 if (arch
== mips_cpu_info_table
[i
].cpu
)
19538 return (&mips_cpu_info_table
[i
]);
19544 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19548 fprintf (stream
, "%24s", "");
19553 fprintf (stream
, ", ");
19557 if (*col_p
+ strlen (string
) > 72)
19559 fprintf (stream
, "\n%24s", "");
19563 fprintf (stream
, "%s", string
);
19564 *col_p
+= strlen (string
);
19570 md_show_usage (FILE *stream
)
19575 fprintf (stream
, _("\
19577 -EB generate big endian output\n\
19578 -EL generate little endian output\n\
19579 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19580 -G NUM allow referencing objects up to NUM bytes\n\
19581 implicitly with the gp register [default 8]\n"));
19582 fprintf (stream
, _("\
19583 -mips1 generate MIPS ISA I instructions\n\
19584 -mips2 generate MIPS ISA II instructions\n\
19585 -mips3 generate MIPS ISA III instructions\n\
19586 -mips4 generate MIPS ISA IV instructions\n\
19587 -mips5 generate MIPS ISA V instructions\n\
19588 -mips32 generate MIPS32 ISA instructions\n\
19589 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19590 -mips64 generate MIPS64 ISA instructions\n\
19591 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19592 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19596 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19597 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19598 show (stream
, "from-abi", &column
, &first
);
19599 fputc ('\n', stream
);
19601 fprintf (stream
, _("\
19602 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19603 -no-mCPU don't generate code specific to CPU.\n\
19604 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19608 show (stream
, "3900", &column
, &first
);
19609 show (stream
, "4010", &column
, &first
);
19610 show (stream
, "4100", &column
, &first
);
19611 show (stream
, "4650", &column
, &first
);
19612 fputc ('\n', stream
);
19614 fprintf (stream
, _("\
19615 -mips16 generate mips16 instructions\n\
19616 -no-mips16 do not generate mips16 instructions\n"));
19617 fprintf (stream
, _("\
19618 -mmicromips generate microMIPS instructions\n\
19619 -mno-micromips do not generate microMIPS instructions\n"));
19620 fprintf (stream
, _("\
19621 -msmartmips generate smartmips instructions\n\
19622 -mno-smartmips do not generate smartmips instructions\n"));
19623 fprintf (stream
, _("\
19624 -mdsp generate DSP instructions\n\
19625 -mno-dsp do not generate DSP instructions\n"));
19626 fprintf (stream
, _("\
19627 -mdspr2 generate DSP R2 instructions\n\
19628 -mno-dspr2 do not generate DSP R2 instructions\n"));
19629 fprintf (stream
, _("\
19630 -mmt generate MT instructions\n\
19631 -mno-mt do not generate MT instructions\n"));
19632 fprintf (stream
, _("\
19633 -mmcu generate MCU instructions\n\
19634 -mno-mcu do not generate MCU instructions\n"));
19635 fprintf (stream
, _("\
19636 -mvirt generate Virtualization instructions\n\
19637 -mno-virt do not generate Virtualization instructions\n"));
19638 fprintf (stream
, _("\
19639 -minsn32 only generate 32-bit microMIPS instructions\n\
19640 -mno-insn32 generate all microMIPS instructions\n"));
19641 fprintf (stream
, _("\
19642 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19643 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19644 -mfix-vr4120 work around certain VR4120 errata\n\
19645 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19646 -mfix-24k insert a nop after ERET and DERET instructions\n\
19647 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19648 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19649 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19650 -msym32 assume all symbols have 32-bit values\n\
19651 -O0 remove unneeded NOPs, do not swap branches\n\
19652 -O remove unneeded NOPs and swap branches\n\
19653 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19654 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19655 fprintf (stream
, _("\
19656 -mhard-float allow floating-point instructions\n\
19657 -msoft-float do not allow floating-point instructions\n\
19658 -msingle-float only allow 32-bit floating-point operations\n\
19659 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19660 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19661 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19663 fprintf (stream
, _("\
19664 -KPIC, -call_shared generate SVR4 position independent code\n\
19665 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19666 -mvxworks-pic generate VxWorks position independent code\n\
19667 -non_shared do not generate code that can operate with DSOs\n\
19668 -xgot assume a 32 bit GOT\n\
19669 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19670 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19671 position dependent (non shared) code\n\
19672 -mabi=ABI create ABI conformant object file for:\n"));
19676 show (stream
, "32", &column
, &first
);
19677 show (stream
, "o64", &column
, &first
);
19678 show (stream
, "n32", &column
, &first
);
19679 show (stream
, "64", &column
, &first
);
19680 show (stream
, "eabi", &column
, &first
);
19682 fputc ('\n', stream
);
19684 fprintf (stream
, _("\
19685 -32 create o32 ABI object file (default)\n\
19686 -n32 create n32 ABI object file\n\
19687 -64 create 64 ABI object file\n"));
19692 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19694 if (HAVE_64BIT_SYMBOLS
)
19695 return dwarf2_format_64bit_irix
;
19697 return dwarf2_format_32bit
;
19702 mips_dwarf2_addr_size (void)
19704 if (HAVE_64BIT_OBJECTS
)
19710 /* Standard calling conventions leave the CFA at SP on entry. */
19712 mips_cfi_frame_initial_instructions (void)
19714 cfi_add_CFA_def_cfa_register (SP
);
19718 tc_mips_regname_to_dw2regnum (char *regname
)
19720 unsigned int regnum
= -1;
19723 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))