1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
1171 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1174 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1179 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1186 /* Sign-extend 16-bit value X. */
1187 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1189 /* Is the given value a sign-extended 32-bit value? */
1190 #define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1194 /* Is the given value a sign-extended 16-bit value? */
1195 #define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1199 /* Is the given value a sign-extended 12-bit value? */
1200 #define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1203 /* Is the given value a sign-extended 9-bit value? */
1204 #define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1207 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208 #define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1212 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1214 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1217 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1218 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1223 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
1228 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229 #define MIPS16_EXTEND (0xf000U << 16)
1231 /* Whether or not we are emitting a branch-likely macro. */
1232 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1234 /* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes
[2];
1251 /* The symbol on which the choice of sequence depends. */
1255 /* Global variables used to decide whether a macro needs a warning. */
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p
;
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length
;
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1268 unsigned int sizes
[2];
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes
[2];
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns
[2];
1287 /* The first variant frag for this macro. */
1289 } mips_macro_warning
;
1291 /* Prototypes for static functions. */
1293 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1295 static void append_insn
1296 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1297 bfd_boolean expansionp
);
1298 static void mips_no_prev_insn (void);
1299 static void macro_build (expressionS
*, const char *, const char *, ...);
1300 static void mips16_macro_build
1301 (expressionS
*, const char *, const char *, va_list *);
1302 static void load_register (int, expressionS
*, int);
1303 static void macro_start (void);
1304 static void macro_end (void);
1305 static void macro (struct mips_cl_insn
*ip
, char *str
);
1306 static void mips16_macro (struct mips_cl_insn
* ip
);
1307 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1308 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1309 static void mips16_immed
1310 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1311 unsigned int, unsigned long *);
1312 static size_t my_getSmallExpression
1313 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1314 static void my_getExpression (expressionS
*, char *);
1315 static void s_align (int);
1316 static void s_change_sec (int);
1317 static void s_change_section (int);
1318 static void s_cons (int);
1319 static void s_float_cons (int);
1320 static void s_mips_globl (int);
1321 static void s_option (int);
1322 static void s_mipsset (int);
1323 static void s_abicalls (int);
1324 static void s_cpload (int);
1325 static void s_cpsetup (int);
1326 static void s_cplocal (int);
1327 static void s_cprestore (int);
1328 static void s_cpreturn (int);
1329 static void s_dtprelword (int);
1330 static void s_dtpreldword (int);
1331 static void s_tprelword (int);
1332 static void s_tpreldword (int);
1333 static void s_gpvalue (int);
1334 static void s_gpword (int);
1335 static void s_gpdword (int);
1336 static void s_ehword (int);
1337 static void s_cpadd (int);
1338 static void s_insn (int);
1339 static void s_nan (int);
1340 static void s_module (int);
1341 static void s_mips_ent (int);
1342 static void s_mips_end (int);
1343 static void s_mips_frame (int);
1344 static void s_mips_mask (int reg_type
);
1345 static void s_mips_stab (int);
1346 static void s_mips_weakext (int);
1347 static void s_mips_file (int);
1348 static void s_mips_loc (int);
1349 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1350 static int relaxed_branch_length (fragS
*, asection
*, int);
1351 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1352 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1353 static void file_mips_check_options (void);
1355 /* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1358 struct mips_cpu_info
1360 const char *name
; /* CPU or ISA name. */
1361 int flags
; /* MIPS_CPU_* flags. */
1362 int ase
; /* Set of ASEs implemented by the CPU. */
1363 int isa
; /* ISA level. */
1364 int cpu
; /* CPU number (default CPU if ISA). */
1367 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1369 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1370 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1371 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1373 /* Command-line options. */
1374 const char *md_shortopts
= "O::g::G:";
1378 OPTION_MARCH
= OPTION_MD_BASE
,
1410 OPTION_NO_SMARTMIPS
,
1418 OPTION_NO_MICROMIPS
,
1421 OPTION_COMPAT_ARCH_BASE
,
1430 OPTION_M7000_HILO_FIX
,
1431 OPTION_MNO_7000_HILO_FIX
,
1435 OPTION_NO_FIX_RM7000
,
1436 OPTION_FIX_LOONGSON2F_JUMP
,
1437 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1438 OPTION_FIX_LOONGSON2F_NOP
,
1439 OPTION_NO_FIX_LOONGSON2F_NOP
,
1441 OPTION_NO_FIX_VR4120
,
1443 OPTION_NO_FIX_VR4130
,
1444 OPTION_FIX_CN63XXP1
,
1445 OPTION_NO_FIX_CN63XXP1
,
1452 OPTION_CONSTRUCT_FLOATS
,
1453 OPTION_NO_CONSTRUCT_FLOATS
,
1457 OPTION_RELAX_BRANCH
,
1458 OPTION_NO_RELAX_BRANCH
,
1467 OPTION_SINGLE_FLOAT
,
1468 OPTION_DOUBLE_FLOAT
,
1481 OPTION_MVXWORKS_PIC
,
1484 OPTION_NO_ODD_SPREG
,
1488 struct option md_longopts
[] =
1490 /* Options which specify architecture. */
1491 {"march", required_argument
, NULL
, OPTION_MARCH
},
1492 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1493 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1494 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1495 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1496 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1497 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1498 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1499 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1500 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1501 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1502 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1503 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1504 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1505 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1506 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1507 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1508 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1510 /* Options which specify Application Specific Extensions (ASEs). */
1511 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1512 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1513 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1514 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1515 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1516 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1517 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1518 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1519 {"mmt", no_argument
, NULL
, OPTION_MT
},
1520 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1521 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1522 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1523 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1524 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1525 {"meva", no_argument
, NULL
, OPTION_EVA
},
1526 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1527 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1528 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1529 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1530 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1531 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1532 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1533 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1534 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1535 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1536 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1538 /* Old-style architecture options. Don't add more of these. */
1539 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1540 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1541 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1542 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1543 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1544 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1545 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1546 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1548 /* Options which enable bug fixes. */
1549 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1550 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1551 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1552 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1553 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1554 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1555 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1556 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1557 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1558 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1559 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1560 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1561 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1562 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1563 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1564 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1565 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1567 /* Miscellaneous options. */
1568 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1569 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1570 {"break", no_argument
, NULL
, OPTION_BREAK
},
1571 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1572 {"EB", no_argument
, NULL
, OPTION_EB
},
1573 {"EL", no_argument
, NULL
, OPTION_EL
},
1574 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1575 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1576 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1577 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1578 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1579 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1580 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1581 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1582 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1583 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1584 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1585 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1586 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1587 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1588 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1589 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1590 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1591 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1592 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1593 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1594 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1596 /* Strictly speaking this next option is ELF specific,
1597 but we allow it for other ports as well in order to
1598 make testing easier. */
1599 {"32", no_argument
, NULL
, OPTION_32
},
1601 /* ELF-specific options. */
1602 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1603 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1604 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1605 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1606 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1607 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1608 {"n32", no_argument
, NULL
, OPTION_N32
},
1609 {"64", no_argument
, NULL
, OPTION_64
},
1610 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1611 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1612 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1613 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1614 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1615 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1617 {NULL
, no_argument
, NULL
, 0}
1619 size_t md_longopts_size
= sizeof (md_longopts
);
1621 /* Information about either an Application Specific Extension or an
1622 optional architecture feature that, for simplicity, we treat in the
1623 same way as an ASE. */
1626 /* The name of the ASE, used in both the command-line and .set options. */
1629 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1630 and 64-bit architectures, the flags here refer to the subset that
1631 is available on both. */
1634 /* The ASE_* flag used for instructions that are available on 64-bit
1635 architectures but that are not included in FLAGS. */
1636 unsigned int flags64
;
1638 /* The command-line options that turn the ASE on and off. */
1642 /* The minimum required architecture revisions for MIPS32, MIPS64,
1643 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1646 int micromips32_rev
;
1647 int micromips64_rev
;
1649 /* The architecture where the ASE was removed or -1 if the extension has not
1654 /* A table of all supported ASEs. */
1655 static const struct mips_ase mips_ases
[] = {
1656 { "dsp", ASE_DSP
, ASE_DSP64
,
1657 OPTION_DSP
, OPTION_NO_DSP
,
1661 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1662 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1666 { "eva", ASE_EVA
, 0,
1667 OPTION_EVA
, OPTION_NO_EVA
,
1671 { "mcu", ASE_MCU
, 0,
1672 OPTION_MCU
, OPTION_NO_MCU
,
1676 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1677 { "mdmx", ASE_MDMX
, 0,
1678 OPTION_MDMX
, OPTION_NO_MDMX
,
1682 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1683 { "mips3d", ASE_MIPS3D
, 0,
1684 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1689 OPTION_MT
, OPTION_NO_MT
,
1693 { "smartmips", ASE_SMARTMIPS
, 0,
1694 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1698 { "virt", ASE_VIRT
, ASE_VIRT64
,
1699 OPTION_VIRT
, OPTION_NO_VIRT
,
1703 { "msa", ASE_MSA
, ASE_MSA64
,
1704 OPTION_MSA
, OPTION_NO_MSA
,
1708 { "xpa", ASE_XPA
, 0,
1709 OPTION_XPA
, OPTION_NO_XPA
,
1714 /* The set of ASEs that require -mfp64. */
1715 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1717 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1718 static const unsigned int mips_ase_groups
[] = {
1724 The following pseudo-ops from the Kane and Heinrich MIPS book
1725 should be defined here, but are currently unsupported: .alias,
1726 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1728 The following pseudo-ops from the Kane and Heinrich MIPS book are
1729 specific to the type of debugging information being generated, and
1730 should be defined by the object format: .aent, .begin, .bend,
1731 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1734 The following pseudo-ops from the Kane and Heinrich MIPS book are
1735 not MIPS CPU specific, but are also not specific to the object file
1736 format. This file is probably the best place to define them, but
1737 they are not currently supported: .asm0, .endr, .lab, .struct. */
1739 static const pseudo_typeS mips_pseudo_table
[] =
1741 /* MIPS specific pseudo-ops. */
1742 {"option", s_option
, 0},
1743 {"set", s_mipsset
, 0},
1744 {"rdata", s_change_sec
, 'r'},
1745 {"sdata", s_change_sec
, 's'},
1746 {"livereg", s_ignore
, 0},
1747 {"abicalls", s_abicalls
, 0},
1748 {"cpload", s_cpload
, 0},
1749 {"cpsetup", s_cpsetup
, 0},
1750 {"cplocal", s_cplocal
, 0},
1751 {"cprestore", s_cprestore
, 0},
1752 {"cpreturn", s_cpreturn
, 0},
1753 {"dtprelword", s_dtprelword
, 0},
1754 {"dtpreldword", s_dtpreldword
, 0},
1755 {"tprelword", s_tprelword
, 0},
1756 {"tpreldword", s_tpreldword
, 0},
1757 {"gpvalue", s_gpvalue
, 0},
1758 {"gpword", s_gpword
, 0},
1759 {"gpdword", s_gpdword
, 0},
1760 {"ehword", s_ehword
, 0},
1761 {"cpadd", s_cpadd
, 0},
1762 {"insn", s_insn
, 0},
1764 {"module", s_module
, 0},
1766 /* Relatively generic pseudo-ops that happen to be used on MIPS
1768 {"asciiz", stringer
, 8 + 1},
1769 {"bss", s_change_sec
, 'b'},
1771 {"half", s_cons
, 1},
1772 {"dword", s_cons
, 3},
1773 {"weakext", s_mips_weakext
, 0},
1774 {"origin", s_org
, 0},
1775 {"repeat", s_rept
, 0},
1777 /* For MIPS this is non-standard, but we define it for consistency. */
1778 {"sbss", s_change_sec
, 'B'},
1780 /* These pseudo-ops are defined in read.c, but must be overridden
1781 here for one reason or another. */
1782 {"align", s_align
, 0},
1783 {"byte", s_cons
, 0},
1784 {"data", s_change_sec
, 'd'},
1785 {"double", s_float_cons
, 'd'},
1786 {"float", s_float_cons
, 'f'},
1787 {"globl", s_mips_globl
, 0},
1788 {"global", s_mips_globl
, 0},
1789 {"hword", s_cons
, 1},
1791 {"long", s_cons
, 2},
1792 {"octa", s_cons
, 4},
1793 {"quad", s_cons
, 3},
1794 {"section", s_change_section
, 0},
1795 {"short", s_cons
, 1},
1796 {"single", s_float_cons
, 'f'},
1797 {"stabd", s_mips_stab
, 'd'},
1798 {"stabn", s_mips_stab
, 'n'},
1799 {"stabs", s_mips_stab
, 's'},
1800 {"text", s_change_sec
, 't'},
1801 {"word", s_cons
, 2},
1803 { "extern", ecoff_directive_extern
, 0},
1808 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1810 /* These pseudo-ops should be defined by the object file format.
1811 However, a.out doesn't support them, so we have versions here. */
1812 {"aent", s_mips_ent
, 1},
1813 {"bgnb", s_ignore
, 0},
1814 {"end", s_mips_end
, 0},
1815 {"endb", s_ignore
, 0},
1816 {"ent", s_mips_ent
, 0},
1817 {"file", s_mips_file
, 0},
1818 {"fmask", s_mips_mask
, 'F'},
1819 {"frame", s_mips_frame
, 0},
1820 {"loc", s_mips_loc
, 0},
1821 {"mask", s_mips_mask
, 'R'},
1822 {"verstamp", s_ignore
, 0},
1826 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1827 purpose of the `.dc.a' internal pseudo-op. */
1830 mips_address_bytes (void)
1832 file_mips_check_options ();
1833 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1836 extern void pop_insert (const pseudo_typeS
*);
1839 mips_pop_insert (void)
1841 pop_insert (mips_pseudo_table
);
1842 if (! ECOFF_DEBUGGING
)
1843 pop_insert (mips_nonecoff_pseudo_table
);
1846 /* Symbols labelling the current insn. */
1848 struct insn_label_list
1850 struct insn_label_list
*next
;
1854 static struct insn_label_list
*free_insn_labels
;
1855 #define label_list tc_segment_info_data.labels
1857 static void mips_clear_insn_labels (void);
1858 static void mips_mark_labels (void);
1859 static void mips_compressed_mark_labels (void);
1862 mips_clear_insn_labels (void)
1864 struct insn_label_list
**pl
;
1865 segment_info_type
*si
;
1869 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1872 si
= seg_info (now_seg
);
1873 *pl
= si
->label_list
;
1874 si
->label_list
= NULL
;
1878 /* Mark instruction labels in MIPS16/microMIPS mode. */
1881 mips_mark_labels (void)
1883 if (HAVE_CODE_COMPRESSION
)
1884 mips_compressed_mark_labels ();
1887 static char *expr_end
;
1889 /* An expression in a macro instruction. This is set by mips_ip and
1890 mips16_ip and when populated is always an O_constant. */
1892 static expressionS imm_expr
;
1894 /* The relocatable field in an instruction and the relocs associated
1895 with it. These variables are used for instructions like LUI and
1896 JAL as well as true offsets. They are also used for address
1897 operands in macros. */
1899 static expressionS offset_expr
;
1900 static bfd_reloc_code_real_type offset_reloc
[3]
1901 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1903 /* This is set to the resulting size of the instruction to be produced
1904 by mips16_ip if an explicit extension is used or by mips_ip if an
1905 explicit size is supplied. */
1907 static unsigned int forced_insn_length
;
1909 /* True if we are assembling an instruction. All dot symbols defined during
1910 this time should be treated as code labels. */
1912 static bfd_boolean mips_assembling_insn
;
1914 /* The pdr segment for per procedure frame/regmask info. Not used for
1917 static segT pdr_seg
;
1919 /* The default target format to use. */
1921 #if defined (TE_FreeBSD)
1922 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1923 #elif defined (TE_TMIPS)
1924 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1926 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1930 mips_target_format (void)
1932 switch (OUTPUT_FLAVOR
)
1934 case bfd_target_elf_flavour
:
1936 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1937 return (target_big_endian
1938 ? "elf32-bigmips-vxworks"
1939 : "elf32-littlemips-vxworks");
1941 return (target_big_endian
1942 ? (HAVE_64BIT_OBJECTS
1943 ? ELF_TARGET ("elf64-", "big")
1945 ? ELF_TARGET ("elf32-n", "big")
1946 : ELF_TARGET ("elf32-", "big")))
1947 : (HAVE_64BIT_OBJECTS
1948 ? ELF_TARGET ("elf64-", "little")
1950 ? ELF_TARGET ("elf32-n", "little")
1951 : ELF_TARGET ("elf32-", "little"))));
1958 /* Return the ISA revision that is currently in use, or 0 if we are
1959 generating code for MIPS V or below. */
1964 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1967 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
1970 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
1973 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
1976 /* microMIPS implies revision 2 or above. */
1977 if (mips_opts
.micromips
)
1980 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1986 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1989 mips_ase_mask (unsigned int flags
)
1993 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1994 if (flags
& mips_ase_groups
[i
])
1995 flags
|= mips_ase_groups
[i
];
1999 /* Check whether the current ISA supports ASE. Issue a warning if
2003 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2007 static unsigned int warned_isa
;
2008 static unsigned int warned_fp32
;
2010 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2011 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2013 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2014 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2015 && (warned_isa
& ase
->flags
) != ase
->flags
)
2017 warned_isa
|= ase
->flags
;
2018 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2019 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2021 as_warn (_("the %d-bit %s architecture does not support the"
2022 " `%s' extension"), size
, base
, ase
->name
);
2024 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2025 ase
->name
, base
, size
, min_rev
);
2027 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2028 && (warned_isa
& ase
->flags
) != ase
->flags
)
2030 warned_isa
|= ase
->flags
;
2031 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2032 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2033 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2034 ase
->name
, base
, size
, ase
->rem_rev
);
2037 if ((ase
->flags
& FP64_ASES
)
2038 && mips_opts
.fp
!= 64
2039 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2041 warned_fp32
|= ase
->flags
;
2042 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2046 /* Check all enabled ASEs to see whether they are supported by the
2047 chosen architecture. */
2050 mips_check_isa_supports_ases (void)
2052 unsigned int i
, mask
;
2054 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2056 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2057 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2058 mips_check_isa_supports_ase (&mips_ases
[i
]);
2062 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2063 that were affected. */
2066 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2067 bfd_boolean enabled_p
)
2071 mask
= mips_ase_mask (ase
->flags
);
2074 opts
->ase
|= ase
->flags
;
2078 /* Return the ASE called NAME, or null if none. */
2080 static const struct mips_ase
*
2081 mips_lookup_ase (const char *name
)
2085 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2086 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2087 return &mips_ases
[i
];
2091 /* Return the length of a microMIPS instruction in bytes. If bits of
2092 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2093 otherwise it is a 32-bit instruction. */
2095 static inline unsigned int
2096 micromips_insn_length (const struct mips_opcode
*mo
)
2098 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2101 /* Return the length of MIPS16 instruction OPCODE. */
2103 static inline unsigned int
2104 mips16_opcode_length (unsigned long opcode
)
2106 return (opcode
>> 16) == 0 ? 2 : 4;
2109 /* Return the length of instruction INSN. */
2111 static inline unsigned int
2112 insn_length (const struct mips_cl_insn
*insn
)
2114 if (mips_opts
.micromips
)
2115 return micromips_insn_length (insn
->insn_mo
);
2116 else if (mips_opts
.mips16
)
2117 return mips16_opcode_length (insn
->insn_opcode
);
2122 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2125 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2130 insn
->insn_opcode
= mo
->match
;
2133 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2134 insn
->fixp
[i
] = NULL
;
2135 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2136 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2137 insn
->mips16_absolute_jump_p
= 0;
2138 insn
->complete_p
= 0;
2139 insn
->cleared_p
= 0;
2142 /* Get a list of all the operands in INSN. */
2144 static const struct mips_operand_array
*
2145 insn_operands (const struct mips_cl_insn
*insn
)
2147 if (insn
->insn_mo
>= &mips_opcodes
[0]
2148 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2149 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2151 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2152 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2153 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2155 if (insn
->insn_mo
>= µmips_opcodes
[0]
2156 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2157 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2162 /* Get a description of operand OPNO of INSN. */
2164 static const struct mips_operand
*
2165 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2167 const struct mips_operand_array
*operands
;
2169 operands
= insn_operands (insn
);
2170 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2172 return operands
->operand
[opno
];
2175 /* Install UVAL as the value of OPERAND in INSN. */
2178 insn_insert_operand (struct mips_cl_insn
*insn
,
2179 const struct mips_operand
*operand
, unsigned int uval
)
2181 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2184 /* Extract the value of OPERAND from INSN. */
2186 static inline unsigned
2187 insn_extract_operand (const struct mips_cl_insn
*insn
,
2188 const struct mips_operand
*operand
)
2190 return mips_extract_operand (operand
, insn
->insn_opcode
);
2193 /* Record the current MIPS16/microMIPS mode in now_seg. */
2196 mips_record_compressed_mode (void)
2198 segment_info_type
*si
;
2200 si
= seg_info (now_seg
);
2201 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2202 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2203 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2204 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2207 /* Read a standard MIPS instruction from BUF. */
2209 static unsigned long
2210 read_insn (char *buf
)
2212 if (target_big_endian
)
2213 return bfd_getb32 ((bfd_byte
*) buf
);
2215 return bfd_getl32 ((bfd_byte
*) buf
);
2218 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2222 write_insn (char *buf
, unsigned int insn
)
2224 md_number_to_chars (buf
, insn
, 4);
2228 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2229 has length LENGTH. */
2231 static unsigned long
2232 read_compressed_insn (char *buf
, unsigned int length
)
2238 for (i
= 0; i
< length
; i
+= 2)
2241 if (target_big_endian
)
2242 insn
|= bfd_getb16 ((char *) buf
);
2244 insn
|= bfd_getl16 ((char *) buf
);
2250 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2251 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2254 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2258 for (i
= 0; i
< length
; i
+= 2)
2259 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2260 return buf
+ length
;
2263 /* Install INSN at the location specified by its "frag" and "where" fields. */
2266 install_insn (const struct mips_cl_insn
*insn
)
2268 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2269 if (HAVE_CODE_COMPRESSION
)
2270 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2272 write_insn (f
, insn
->insn_opcode
);
2273 mips_record_compressed_mode ();
2276 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2277 and install the opcode in the new location. */
2280 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2285 insn
->where
= where
;
2286 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2287 if (insn
->fixp
[i
] != NULL
)
2289 insn
->fixp
[i
]->fx_frag
= frag
;
2290 insn
->fixp
[i
]->fx_where
= where
;
2292 install_insn (insn
);
2295 /* Add INSN to the end of the output. */
2298 add_fixed_insn (struct mips_cl_insn
*insn
)
2300 char *f
= frag_more (insn_length (insn
));
2301 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2304 /* Start a variant frag and move INSN to the start of the variant part,
2305 marking it as fixed. The other arguments are as for frag_var. */
2308 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2309 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2311 frag_grow (max_chars
);
2312 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2314 frag_var (rs_machine_dependent
, max_chars
, var
,
2315 subtype
, symbol
, offset
, NULL
);
2318 /* Insert N copies of INSN into the history buffer, starting at
2319 position FIRST. Neither FIRST nor N need to be clipped. */
2322 insert_into_history (unsigned int first
, unsigned int n
,
2323 const struct mips_cl_insn
*insn
)
2325 if (mips_relax
.sequence
!= 2)
2329 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2331 history
[i
] = history
[i
- n
];
2337 /* Clear the error in insn_error. */
2340 clear_insn_error (void)
2342 memset (&insn_error
, 0, sizeof (insn_error
));
2345 /* Possibly record error message MSG for the current instruction.
2346 If the error is about a particular argument, ARGNUM is the 1-based
2347 number of that argument, otherwise it is 0. FORMAT is the format
2348 of MSG. Return true if MSG was used, false if the current message
2352 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2357 /* Give priority to errors against specific arguments, and to
2358 the first whole-instruction message. */
2364 /* Keep insn_error if it is against a later argument. */
2365 if (argnum
< insn_error
.min_argnum
)
2368 /* If both errors are against the same argument but are different,
2369 give up on reporting a specific error for this argument.
2370 See the comment about mips_insn_error for details. */
2371 if (argnum
== insn_error
.min_argnum
2373 && strcmp (insn_error
.msg
, msg
) != 0)
2376 insn_error
.min_argnum
+= 1;
2380 insn_error
.min_argnum
= argnum
;
2381 insn_error
.format
= format
;
2382 insn_error
.msg
= msg
;
2386 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2387 as for set_insn_error_format. */
2390 set_insn_error (int argnum
, const char *msg
)
2392 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2395 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2396 as for set_insn_error_format. */
2399 set_insn_error_i (int argnum
, const char *msg
, int i
)
2401 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2405 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2406 are as for set_insn_error_format. */
2409 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2411 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2413 insn_error
.u
.ss
[0] = s1
;
2414 insn_error
.u
.ss
[1] = s2
;
2418 /* Report the error in insn_error, which is against assembly code STR. */
2421 report_insn_error (const char *str
)
2423 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2425 switch (insn_error
.format
)
2432 as_bad (msg
, insn_error
.u
.i
, str
);
2436 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2440 free ((char *) msg
);
2443 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2444 the idea is to make it obvious at a glance that each errata is
2448 init_vr4120_conflicts (void)
2450 #define CONFLICT(FIRST, SECOND) \
2451 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2453 /* Errata 21 - [D]DIV[U] after [D]MACC */
2454 CONFLICT (MACC
, DIV
);
2455 CONFLICT (DMACC
, DIV
);
2457 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2458 CONFLICT (DMULT
, DMULT
);
2459 CONFLICT (DMULT
, DMACC
);
2460 CONFLICT (DMACC
, DMULT
);
2461 CONFLICT (DMACC
, DMACC
);
2463 /* Errata 24 - MT{LO,HI} after [D]MACC */
2464 CONFLICT (MACC
, MTHILO
);
2465 CONFLICT (DMACC
, MTHILO
);
2467 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2468 instruction is executed immediately after a MACC or DMACC
2469 instruction, the result of [either instruction] is incorrect." */
2470 CONFLICT (MACC
, MULT
);
2471 CONFLICT (MACC
, DMULT
);
2472 CONFLICT (DMACC
, MULT
);
2473 CONFLICT (DMACC
, DMULT
);
2475 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2476 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2477 DDIV or DDIVU instruction, the result of the MACC or
2478 DMACC instruction is incorrect.". */
2479 CONFLICT (DMULT
, MACC
);
2480 CONFLICT (DMULT
, DMACC
);
2481 CONFLICT (DIV
, MACC
);
2482 CONFLICT (DIV
, DMACC
);
2492 #define RNUM_MASK 0x00000ff
2493 #define RTYPE_MASK 0x0ffff00
2494 #define RTYPE_NUM 0x0000100
2495 #define RTYPE_FPU 0x0000200
2496 #define RTYPE_FCC 0x0000400
2497 #define RTYPE_VEC 0x0000800
2498 #define RTYPE_GP 0x0001000
2499 #define RTYPE_CP0 0x0002000
2500 #define RTYPE_PC 0x0004000
2501 #define RTYPE_ACC 0x0008000
2502 #define RTYPE_CCC 0x0010000
2503 #define RTYPE_VI 0x0020000
2504 #define RTYPE_VF 0x0040000
2505 #define RTYPE_R5900_I 0x0080000
2506 #define RTYPE_R5900_Q 0x0100000
2507 #define RTYPE_R5900_R 0x0200000
2508 #define RTYPE_R5900_ACC 0x0400000
2509 #define RTYPE_MSA 0x0800000
2510 #define RWARN 0x8000000
2512 #define GENERIC_REGISTER_NUMBERS \
2513 {"$0", RTYPE_NUM | 0}, \
2514 {"$1", RTYPE_NUM | 1}, \
2515 {"$2", RTYPE_NUM | 2}, \
2516 {"$3", RTYPE_NUM | 3}, \
2517 {"$4", RTYPE_NUM | 4}, \
2518 {"$5", RTYPE_NUM | 5}, \
2519 {"$6", RTYPE_NUM | 6}, \
2520 {"$7", RTYPE_NUM | 7}, \
2521 {"$8", RTYPE_NUM | 8}, \
2522 {"$9", RTYPE_NUM | 9}, \
2523 {"$10", RTYPE_NUM | 10}, \
2524 {"$11", RTYPE_NUM | 11}, \
2525 {"$12", RTYPE_NUM | 12}, \
2526 {"$13", RTYPE_NUM | 13}, \
2527 {"$14", RTYPE_NUM | 14}, \
2528 {"$15", RTYPE_NUM | 15}, \
2529 {"$16", RTYPE_NUM | 16}, \
2530 {"$17", RTYPE_NUM | 17}, \
2531 {"$18", RTYPE_NUM | 18}, \
2532 {"$19", RTYPE_NUM | 19}, \
2533 {"$20", RTYPE_NUM | 20}, \
2534 {"$21", RTYPE_NUM | 21}, \
2535 {"$22", RTYPE_NUM | 22}, \
2536 {"$23", RTYPE_NUM | 23}, \
2537 {"$24", RTYPE_NUM | 24}, \
2538 {"$25", RTYPE_NUM | 25}, \
2539 {"$26", RTYPE_NUM | 26}, \
2540 {"$27", RTYPE_NUM | 27}, \
2541 {"$28", RTYPE_NUM | 28}, \
2542 {"$29", RTYPE_NUM | 29}, \
2543 {"$30", RTYPE_NUM | 30}, \
2544 {"$31", RTYPE_NUM | 31}
2546 #define FPU_REGISTER_NAMES \
2547 {"$f0", RTYPE_FPU | 0}, \
2548 {"$f1", RTYPE_FPU | 1}, \
2549 {"$f2", RTYPE_FPU | 2}, \
2550 {"$f3", RTYPE_FPU | 3}, \
2551 {"$f4", RTYPE_FPU | 4}, \
2552 {"$f5", RTYPE_FPU | 5}, \
2553 {"$f6", RTYPE_FPU | 6}, \
2554 {"$f7", RTYPE_FPU | 7}, \
2555 {"$f8", RTYPE_FPU | 8}, \
2556 {"$f9", RTYPE_FPU | 9}, \
2557 {"$f10", RTYPE_FPU | 10}, \
2558 {"$f11", RTYPE_FPU | 11}, \
2559 {"$f12", RTYPE_FPU | 12}, \
2560 {"$f13", RTYPE_FPU | 13}, \
2561 {"$f14", RTYPE_FPU | 14}, \
2562 {"$f15", RTYPE_FPU | 15}, \
2563 {"$f16", RTYPE_FPU | 16}, \
2564 {"$f17", RTYPE_FPU | 17}, \
2565 {"$f18", RTYPE_FPU | 18}, \
2566 {"$f19", RTYPE_FPU | 19}, \
2567 {"$f20", RTYPE_FPU | 20}, \
2568 {"$f21", RTYPE_FPU | 21}, \
2569 {"$f22", RTYPE_FPU | 22}, \
2570 {"$f23", RTYPE_FPU | 23}, \
2571 {"$f24", RTYPE_FPU | 24}, \
2572 {"$f25", RTYPE_FPU | 25}, \
2573 {"$f26", RTYPE_FPU | 26}, \
2574 {"$f27", RTYPE_FPU | 27}, \
2575 {"$f28", RTYPE_FPU | 28}, \
2576 {"$f29", RTYPE_FPU | 29}, \
2577 {"$f30", RTYPE_FPU | 30}, \
2578 {"$f31", RTYPE_FPU | 31}
2580 #define FPU_CONDITION_CODE_NAMES \
2581 {"$fcc0", RTYPE_FCC | 0}, \
2582 {"$fcc1", RTYPE_FCC | 1}, \
2583 {"$fcc2", RTYPE_FCC | 2}, \
2584 {"$fcc3", RTYPE_FCC | 3}, \
2585 {"$fcc4", RTYPE_FCC | 4}, \
2586 {"$fcc5", RTYPE_FCC | 5}, \
2587 {"$fcc6", RTYPE_FCC | 6}, \
2588 {"$fcc7", RTYPE_FCC | 7}
2590 #define COPROC_CONDITION_CODE_NAMES \
2591 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2592 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2593 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2594 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2595 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2596 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2597 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2598 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2600 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2601 {"$a4", RTYPE_GP | 8}, \
2602 {"$a5", RTYPE_GP | 9}, \
2603 {"$a6", RTYPE_GP | 10}, \
2604 {"$a7", RTYPE_GP | 11}, \
2605 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2606 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2607 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2608 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2609 {"$t0", RTYPE_GP | 12}, \
2610 {"$t1", RTYPE_GP | 13}, \
2611 {"$t2", RTYPE_GP | 14}, \
2612 {"$t3", RTYPE_GP | 15}
2614 #define O32_SYMBOLIC_REGISTER_NAMES \
2615 {"$t0", RTYPE_GP | 8}, \
2616 {"$t1", RTYPE_GP | 9}, \
2617 {"$t2", RTYPE_GP | 10}, \
2618 {"$t3", RTYPE_GP | 11}, \
2619 {"$t4", RTYPE_GP | 12}, \
2620 {"$t5", RTYPE_GP | 13}, \
2621 {"$t6", RTYPE_GP | 14}, \
2622 {"$t7", RTYPE_GP | 15}, \
2623 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2624 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2625 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2626 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2628 /* Remaining symbolic register names */
2629 #define SYMBOLIC_REGISTER_NAMES \
2630 {"$zero", RTYPE_GP | 0}, \
2631 {"$at", RTYPE_GP | 1}, \
2632 {"$AT", RTYPE_GP | 1}, \
2633 {"$v0", RTYPE_GP | 2}, \
2634 {"$v1", RTYPE_GP | 3}, \
2635 {"$a0", RTYPE_GP | 4}, \
2636 {"$a1", RTYPE_GP | 5}, \
2637 {"$a2", RTYPE_GP | 6}, \
2638 {"$a3", RTYPE_GP | 7}, \
2639 {"$s0", RTYPE_GP | 16}, \
2640 {"$s1", RTYPE_GP | 17}, \
2641 {"$s2", RTYPE_GP | 18}, \
2642 {"$s3", RTYPE_GP | 19}, \
2643 {"$s4", RTYPE_GP | 20}, \
2644 {"$s5", RTYPE_GP | 21}, \
2645 {"$s6", RTYPE_GP | 22}, \
2646 {"$s7", RTYPE_GP | 23}, \
2647 {"$t8", RTYPE_GP | 24}, \
2648 {"$t9", RTYPE_GP | 25}, \
2649 {"$k0", RTYPE_GP | 26}, \
2650 {"$kt0", RTYPE_GP | 26}, \
2651 {"$k1", RTYPE_GP | 27}, \
2652 {"$kt1", RTYPE_GP | 27}, \
2653 {"$gp", RTYPE_GP | 28}, \
2654 {"$sp", RTYPE_GP | 29}, \
2655 {"$s8", RTYPE_GP | 30}, \
2656 {"$fp", RTYPE_GP | 30}, \
2657 {"$ra", RTYPE_GP | 31}
2659 #define MIPS16_SPECIAL_REGISTER_NAMES \
2660 {"$pc", RTYPE_PC | 0}
2662 #define MDMX_VECTOR_REGISTER_NAMES \
2663 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2664 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2665 {"$v2", RTYPE_VEC | 2}, \
2666 {"$v3", RTYPE_VEC | 3}, \
2667 {"$v4", RTYPE_VEC | 4}, \
2668 {"$v5", RTYPE_VEC | 5}, \
2669 {"$v6", RTYPE_VEC | 6}, \
2670 {"$v7", RTYPE_VEC | 7}, \
2671 {"$v8", RTYPE_VEC | 8}, \
2672 {"$v9", RTYPE_VEC | 9}, \
2673 {"$v10", RTYPE_VEC | 10}, \
2674 {"$v11", RTYPE_VEC | 11}, \
2675 {"$v12", RTYPE_VEC | 12}, \
2676 {"$v13", RTYPE_VEC | 13}, \
2677 {"$v14", RTYPE_VEC | 14}, \
2678 {"$v15", RTYPE_VEC | 15}, \
2679 {"$v16", RTYPE_VEC | 16}, \
2680 {"$v17", RTYPE_VEC | 17}, \
2681 {"$v18", RTYPE_VEC | 18}, \
2682 {"$v19", RTYPE_VEC | 19}, \
2683 {"$v20", RTYPE_VEC | 20}, \
2684 {"$v21", RTYPE_VEC | 21}, \
2685 {"$v22", RTYPE_VEC | 22}, \
2686 {"$v23", RTYPE_VEC | 23}, \
2687 {"$v24", RTYPE_VEC | 24}, \
2688 {"$v25", RTYPE_VEC | 25}, \
2689 {"$v26", RTYPE_VEC | 26}, \
2690 {"$v27", RTYPE_VEC | 27}, \
2691 {"$v28", RTYPE_VEC | 28}, \
2692 {"$v29", RTYPE_VEC | 29}, \
2693 {"$v30", RTYPE_VEC | 30}, \
2694 {"$v31", RTYPE_VEC | 31}
2696 #define R5900_I_NAMES \
2697 {"$I", RTYPE_R5900_I | 0}
2699 #define R5900_Q_NAMES \
2700 {"$Q", RTYPE_R5900_Q | 0}
2702 #define R5900_R_NAMES \
2703 {"$R", RTYPE_R5900_R | 0}
2705 #define R5900_ACC_NAMES \
2706 {"$ACC", RTYPE_R5900_ACC | 0 }
2708 #define MIPS_DSP_ACCUMULATOR_NAMES \
2709 {"$ac0", RTYPE_ACC | 0}, \
2710 {"$ac1", RTYPE_ACC | 1}, \
2711 {"$ac2", RTYPE_ACC | 2}, \
2712 {"$ac3", RTYPE_ACC | 3}
2714 static const struct regname reg_names
[] = {
2715 GENERIC_REGISTER_NUMBERS
,
2717 FPU_CONDITION_CODE_NAMES
,
2718 COPROC_CONDITION_CODE_NAMES
,
2720 /* The $txx registers depends on the abi,
2721 these will be added later into the symbol table from
2722 one of the tables below once mips_abi is set after
2723 parsing of arguments from the command line. */
2724 SYMBOLIC_REGISTER_NAMES
,
2726 MIPS16_SPECIAL_REGISTER_NAMES
,
2727 MDMX_VECTOR_REGISTER_NAMES
,
2732 MIPS_DSP_ACCUMULATOR_NAMES
,
2736 static const struct regname reg_names_o32
[] = {
2737 O32_SYMBOLIC_REGISTER_NAMES
,
2741 static const struct regname reg_names_n32n64
[] = {
2742 N32N64_SYMBOLIC_REGISTER_NAMES
,
2746 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2747 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2748 of these register symbols, return the associated vector register,
2749 otherwise return SYMVAL itself. */
2752 mips_prefer_vec_regno (unsigned int symval
)
2754 if ((symval
& -2) == (RTYPE_GP
| 2))
2755 return RTYPE_VEC
| (symval
& 1);
2759 /* Return true if string [S, E) is a valid register name, storing its
2760 symbol value in *SYMVAL_PTR if so. */
2763 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2768 /* Terminate name. */
2772 /* Look up the name. */
2773 symbol
= symbol_find (s
);
2776 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2779 *symval_ptr
= S_GET_VALUE (symbol
);
2783 /* Return true if the string at *SPTR is a valid register name. Allow it
2784 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2787 When returning true, move *SPTR past the register, store the
2788 register's symbol value in *SYMVAL_PTR and the channel mask in
2789 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2790 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2791 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2794 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2795 unsigned int *channels_ptr
)
2799 unsigned int channels
, symval
, bit
;
2801 /* Find end of name. */
2803 if (is_name_beginner (*e
))
2805 while (is_part_of_name (*e
))
2809 if (!mips_parse_register_1 (s
, e
, &symval
))
2814 /* Eat characters from the end of the string that are valid
2815 channel suffixes. The preceding register must be $ACC or
2816 end with a digit, so there is no ambiguity. */
2819 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2820 if (m
> s
&& m
[-1] == *q
)
2827 || !mips_parse_register_1 (s
, m
, &symval
)
2828 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2833 *symval_ptr
= symval
;
2835 *channels_ptr
= channels
;
2839 /* Check if SPTR points at a valid register specifier according to TYPES.
2840 If so, then return 1, advance S to consume the specifier and store
2841 the register's number in REGNOP, otherwise return 0. */
2844 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2848 if (mips_parse_register (s
, ®no
, NULL
))
2850 if (types
& RTYPE_VEC
)
2851 regno
= mips_prefer_vec_regno (regno
);
2860 as_warn (_("unrecognized register name `%s'"), *s
);
2865 return regno
<= RNUM_MASK
;
2868 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2869 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2872 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2877 for (i
= 0; i
< 4; i
++)
2878 if (*s
== "xyzw"[i
])
2880 *channels
|= 1 << (3 - i
);
2886 /* Token types for parsed operand lists. */
2887 enum mips_operand_token_type
{
2888 /* A plain register, e.g. $f2. */
2891 /* A 4-bit XYZW channel mask. */
2894 /* A constant vector index, e.g. [1]. */
2897 /* A register vector index, e.g. [$2]. */
2900 /* A continuous range of registers, e.g. $s0-$s4. */
2903 /* A (possibly relocated) expression. */
2906 /* A floating-point value. */
2909 /* A single character. This can be '(', ')' or ',', but '(' only appears
2913 /* A doubled character, either "--" or "++". */
2916 /* The end of the operand list. */
2920 /* A parsed operand token. */
2921 struct mips_operand_token
2923 /* The type of token. */
2924 enum mips_operand_token_type type
;
2927 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2930 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2931 unsigned int channels
;
2933 /* The integer value of an OT_INTEGER_INDEX. */
2936 /* The two register symbol values involved in an OT_REG_RANGE. */
2938 unsigned int regno1
;
2939 unsigned int regno2
;
2942 /* The value of an OT_INTEGER. The value is represented as an
2943 expression and the relocation operators that were applied to
2944 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2945 relocation operators were used. */
2948 bfd_reloc_code_real_type relocs
[3];
2951 /* The binary data for an OT_FLOAT constant, and the number of bytes
2954 unsigned char data
[8];
2958 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2963 /* An obstack used to construct lists of mips_operand_tokens. */
2964 static struct obstack mips_operand_tokens
;
2966 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2969 mips_add_token (struct mips_operand_token
*token
,
2970 enum mips_operand_token_type type
)
2973 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2976 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2977 and OT_REG tokens for them if so, and return a pointer to the first
2978 unconsumed character. Return null otherwise. */
2981 mips_parse_base_start (char *s
)
2983 struct mips_operand_token token
;
2984 unsigned int regno
, channels
;
2985 bfd_boolean decrement_p
;
2991 SKIP_SPACE_TABS (s
);
2993 /* Only match "--" as part of a base expression. In other contexts "--X"
2994 is a double negative. */
2995 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2999 SKIP_SPACE_TABS (s
);
3002 /* Allow a channel specifier because that leads to better error messages
3003 than treating something like "$vf0x++" as an expression. */
3004 if (!mips_parse_register (&s
, ®no
, &channels
))
3008 mips_add_token (&token
, OT_CHAR
);
3013 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3016 token
.u
.regno
= regno
;
3017 mips_add_token (&token
, OT_REG
);
3021 token
.u
.channels
= channels
;
3022 mips_add_token (&token
, OT_CHANNELS
);
3025 /* For consistency, only match "++" as part of base expressions too. */
3026 SKIP_SPACE_TABS (s
);
3027 if (s
[0] == '+' && s
[1] == '+')
3031 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3037 /* Parse one or more tokens from S. Return a pointer to the first
3038 unconsumed character on success. Return null if an error was found
3039 and store the error text in insn_error. FLOAT_FORMAT is as for
3040 mips_parse_arguments. */
3043 mips_parse_argument_token (char *s
, char float_format
)
3045 char *end
, *save_in
;
3047 unsigned int regno1
, regno2
, channels
;
3048 struct mips_operand_token token
;
3050 /* First look for "($reg", since we want to treat that as an
3051 OT_CHAR and OT_REG rather than an expression. */
3052 end
= mips_parse_base_start (s
);
3056 /* Handle other characters that end up as OT_CHARs. */
3057 if (*s
== ')' || *s
== ',')
3060 mips_add_token (&token
, OT_CHAR
);
3065 /* Handle tokens that start with a register. */
3066 if (mips_parse_register (&s
, ®no1
, &channels
))
3070 /* A register and a VU0 channel suffix. */
3071 token
.u
.regno
= regno1
;
3072 mips_add_token (&token
, OT_REG
);
3074 token
.u
.channels
= channels
;
3075 mips_add_token (&token
, OT_CHANNELS
);
3079 SKIP_SPACE_TABS (s
);
3082 /* A register range. */
3084 SKIP_SPACE_TABS (s
);
3085 if (!mips_parse_register (&s
, ®no2
, NULL
))
3087 set_insn_error (0, _("invalid register range"));
3091 token
.u
.reg_range
.regno1
= regno1
;
3092 token
.u
.reg_range
.regno2
= regno2
;
3093 mips_add_token (&token
, OT_REG_RANGE
);
3097 /* Add the register itself. */
3098 token
.u
.regno
= regno1
;
3099 mips_add_token (&token
, OT_REG
);
3101 /* Check for a vector index. */
3105 SKIP_SPACE_TABS (s
);
3106 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3107 mips_add_token (&token
, OT_REG_INDEX
);
3110 expressionS element
;
3112 my_getExpression (&element
, s
);
3113 if (element
.X_op
!= O_constant
)
3115 set_insn_error (0, _("vector element must be constant"));
3119 token
.u
.index
= element
.X_add_number
;
3120 mips_add_token (&token
, OT_INTEGER_INDEX
);
3122 SKIP_SPACE_TABS (s
);
3125 set_insn_error (0, _("missing `]'"));
3135 /* First try to treat expressions as floats. */
3136 save_in
= input_line_pointer
;
3137 input_line_pointer
= s
;
3138 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3139 &token
.u
.flt
.length
);
3140 end
= input_line_pointer
;
3141 input_line_pointer
= save_in
;
3144 set_insn_error (0, err
);
3149 mips_add_token (&token
, OT_FLOAT
);
3154 /* Treat everything else as an integer expression. */
3155 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3156 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3157 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3158 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3160 mips_add_token (&token
, OT_INTEGER
);
3164 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3165 if expressions should be treated as 32-bit floating-point constants,
3166 'd' if they should be treated as 64-bit floating-point constants,
3167 or 0 if they should be treated as integer expressions (the usual case).
3169 Return a list of tokens on success, otherwise return 0. The caller
3170 must obstack_free the list after use. */
3172 static struct mips_operand_token
*
3173 mips_parse_arguments (char *s
, char float_format
)
3175 struct mips_operand_token token
;
3177 SKIP_SPACE_TABS (s
);
3180 s
= mips_parse_argument_token (s
, float_format
);
3183 obstack_free (&mips_operand_tokens
,
3184 obstack_finish (&mips_operand_tokens
));
3187 SKIP_SPACE_TABS (s
);
3189 mips_add_token (&token
, OT_END
);
3190 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3193 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3194 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3197 is_opcode_valid (const struct mips_opcode
*mo
)
3199 int isa
= mips_opts
.isa
;
3200 int ase
= mips_opts
.ase
;
3204 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3205 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3206 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3207 ase
|= mips_ases
[i
].flags64
;
3209 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3212 /* Check whether the instruction or macro requires single-precision or
3213 double-precision floating-point support. Note that this information is
3214 stored differently in the opcode table for insns and macros. */
3215 if (mo
->pinfo
== INSN_MACRO
)
3217 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3218 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3222 fp_s
= mo
->pinfo
& FP_S
;
3223 fp_d
= mo
->pinfo
& FP_D
;
3226 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3229 if (fp_s
&& mips_opts
.soft_float
)
3235 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3236 selected ISA and architecture. */
3239 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3241 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3244 /* Return TRUE if the size of the microMIPS opcode MO matches one
3245 explicitly requested. Always TRUE in the standard MIPS mode. */
3248 is_size_valid (const struct mips_opcode
*mo
)
3250 if (!mips_opts
.micromips
)
3253 if (mips_opts
.insn32
)
3255 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3257 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3260 if (!forced_insn_length
)
3262 if (mo
->pinfo
== INSN_MACRO
)
3264 return forced_insn_length
== micromips_insn_length (mo
);
3267 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3268 of the preceding instruction. Always TRUE in the standard MIPS mode.
3270 We don't accept macros in 16-bit delay slots to avoid a case where
3271 a macro expansion fails because it relies on a preceding 32-bit real
3272 instruction to have matched and does not handle the operands correctly.
3273 The only macros that may expand to 16-bit instructions are JAL that
3274 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3275 and BGT (that likewise cannot be placed in a delay slot) that decay to
3276 a NOP. In all these cases the macros precede any corresponding real
3277 instruction definitions in the opcode table, so they will match in the
3278 second pass where the size of the delay slot is ignored and therefore
3279 produce correct code. */
3282 is_delay_slot_valid (const struct mips_opcode
*mo
)
3284 if (!mips_opts
.micromips
)
3287 if (mo
->pinfo
== INSN_MACRO
)
3288 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3289 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3290 && micromips_insn_length (mo
) != 4)
3292 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3293 && micromips_insn_length (mo
) != 2)
3299 /* For consistency checking, verify that all bits of OPCODE are specified
3300 either by the match/mask part of the instruction definition, or by the
3301 operand list. Also build up a list of operands in OPERANDS.
3303 INSN_BITS says which bits of the instruction are significant.
3304 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3305 provides the mips_operand description of each operand. DECODE_OPERAND
3306 is null for MIPS16 instructions. */
3309 validate_mips_insn (const struct mips_opcode
*opcode
,
3310 unsigned long insn_bits
,
3311 const struct mips_operand
*(*decode_operand
) (const char *),
3312 struct mips_operand_array
*operands
)
3315 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3316 const struct mips_operand
*operand
;
3318 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3319 if ((mask
& opcode
->match
) != opcode
->match
)
3321 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3322 opcode
->name
, opcode
->args
);
3327 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3328 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3329 for (s
= opcode
->args
; *s
; ++s
)
3342 if (!decode_operand
)
3343 operand
= decode_mips16_operand (*s
, FALSE
);
3345 operand
= decode_operand (s
);
3346 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3348 as_bad (_("internal: unknown operand type: %s %s"),
3349 opcode
->name
, opcode
->args
);
3352 gas_assert (opno
< MAX_OPERANDS
);
3353 operands
->operand
[opno
] = operand
;
3354 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3356 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3357 if (operand
->type
== OP_MDMX_IMM_REG
)
3358 /* Bit 5 is the format selector (OB vs QH). The opcode table
3359 has separate entries for each format. */
3360 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3361 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3362 used_bits
&= ~(mask
& 0x700);
3364 /* Skip prefix characters. */
3365 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3370 doubled
= used_bits
& mask
& insn_bits
;
3373 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3374 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3378 undefined
= ~used_bits
& insn_bits
;
3379 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3381 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3382 undefined
, opcode
->name
, opcode
->args
);
3385 used_bits
&= ~insn_bits
;
3388 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3389 used_bits
, opcode
->name
, opcode
->args
);
3395 /* The MIPS16 version of validate_mips_insn. */
3398 validate_mips16_insn (const struct mips_opcode
*opcode
,
3399 struct mips_operand_array
*operands
)
3401 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3403 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3404 instruction. Use TMP to describe the full instruction. */
3405 struct mips_opcode tmp
;
3410 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3412 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3415 /* The microMIPS version of validate_mips_insn. */
3418 validate_micromips_insn (const struct mips_opcode
*opc
,
3419 struct mips_operand_array
*operands
)
3421 unsigned long insn_bits
;
3422 unsigned long major
;
3423 unsigned int length
;
3425 if (opc
->pinfo
== INSN_MACRO
)
3426 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3429 length
= micromips_insn_length (opc
);
3430 if (length
!= 2 && length
!= 4)
3432 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3433 "%s %s"), length
, opc
->name
, opc
->args
);
3436 major
= opc
->match
>> (10 + 8 * (length
- 2));
3437 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3438 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3440 as_bad (_("internal error: bad microMIPS opcode "
3441 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3445 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3446 insn_bits
= 1 << 4 * length
;
3447 insn_bits
<<= 4 * length
;
3449 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3453 /* This function is called once, at assembler startup time. It should set up
3454 all the tables, etc. that the MD part of the assembler will need. */
3459 const char *retval
= NULL
;
3463 if (mips_pic
!= NO_PIC
)
3465 if (g_switch_seen
&& g_switch_value
!= 0)
3466 as_bad (_("-G may not be used in position-independent code"));
3469 else if (mips_abicalls
)
3471 if (g_switch_seen
&& g_switch_value
!= 0)
3472 as_bad (_("-G may not be used with abicalls"));
3476 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3477 as_warn (_("could not set architecture and machine"));
3479 op_hash
= hash_new ();
3481 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3482 for (i
= 0; i
< NUMOPCODES
;)
3484 const char *name
= mips_opcodes
[i
].name
;
3486 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3489 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3490 mips_opcodes
[i
].name
, retval
);
3491 /* Probably a memory allocation problem? Give up now. */
3492 as_fatal (_("broken assembler, no assembly attempted"));
3496 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3497 decode_mips_operand
, &mips_operands
[i
]))
3499 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3501 create_insn (&nop_insn
, mips_opcodes
+ i
);
3502 if (mips_fix_loongson2f_nop
)
3503 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3504 nop_insn
.fixed_p
= 1;
3508 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3511 mips16_op_hash
= hash_new ();
3512 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3513 bfd_mips16_num_opcodes
);
3516 while (i
< bfd_mips16_num_opcodes
)
3518 const char *name
= mips16_opcodes
[i
].name
;
3520 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3522 as_fatal (_("internal: can't hash `%s': %s"),
3523 mips16_opcodes
[i
].name
, retval
);
3526 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3528 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3530 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3531 mips16_nop_insn
.fixed_p
= 1;
3535 while (i
< bfd_mips16_num_opcodes
3536 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3539 micromips_op_hash
= hash_new ();
3540 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3541 bfd_micromips_num_opcodes
);
3544 while (i
< bfd_micromips_num_opcodes
)
3546 const char *name
= micromips_opcodes
[i
].name
;
3548 retval
= hash_insert (micromips_op_hash
, name
,
3549 (void *) µmips_opcodes
[i
]);
3551 as_fatal (_("internal: can't hash `%s': %s"),
3552 micromips_opcodes
[i
].name
, retval
);
3555 struct mips_cl_insn
*micromips_nop_insn
;
3557 if (!validate_micromips_insn (µmips_opcodes
[i
],
3558 µmips_operands
[i
]))
3561 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3563 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3564 micromips_nop_insn
= µmips_nop16_insn
;
3565 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3566 micromips_nop_insn
= µmips_nop32_insn
;
3570 if (micromips_nop_insn
->insn_mo
== NULL
3571 && strcmp (name
, "nop") == 0)
3573 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3574 micromips_nop_insn
->fixed_p
= 1;
3578 while (++i
< bfd_micromips_num_opcodes
3579 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3583 as_fatal (_("broken assembler, no assembly attempted"));
3585 /* We add all the general register names to the symbol table. This
3586 helps us detect invalid uses of them. */
3587 for (i
= 0; reg_names
[i
].name
; i
++)
3588 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3589 reg_names
[i
].num
, /* & RNUM_MASK, */
3590 &zero_address_frag
));
3592 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3593 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3594 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3595 &zero_address_frag
));
3597 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3598 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3599 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3600 &zero_address_frag
));
3602 for (i
= 0; i
< 32; i
++)
3606 /* R5900 VU0 floating-point register. */
3607 regname
[sizeof (rename
) - 1] = 0;
3608 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3609 symbol_table_insert (symbol_new (regname
, reg_section
,
3610 RTYPE_VF
| i
, &zero_address_frag
));
3612 /* R5900 VU0 integer register. */
3613 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3614 symbol_table_insert (symbol_new (regname
, reg_section
,
3615 RTYPE_VI
| i
, &zero_address_frag
));
3618 snprintf (regname
, sizeof (regname
) - 1, "$w%d", i
);
3619 symbol_table_insert (symbol_new (regname
, reg_section
,
3620 RTYPE_MSA
| i
, &zero_address_frag
));
3623 obstack_init (&mips_operand_tokens
);
3625 mips_no_prev_insn ();
3628 mips_cprmask
[0] = 0;
3629 mips_cprmask
[1] = 0;
3630 mips_cprmask
[2] = 0;
3631 mips_cprmask
[3] = 0;
3633 /* set the default alignment for the text section (2**2) */
3634 record_alignment (text_section
, 2);
3636 bfd_set_gp_size (stdoutput
, g_switch_value
);
3638 /* On a native system other than VxWorks, sections must be aligned
3639 to 16 byte boundaries. When configured for an embedded ELF
3640 target, we don't bother. */
3641 if (strncmp (TARGET_OS
, "elf", 3) != 0
3642 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3644 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3645 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3646 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3649 /* Create a .reginfo section for register masks and a .mdebug
3650 section for debugging information. */
3658 subseg
= now_subseg
;
3660 /* The ABI says this section should be loaded so that the
3661 running program can access it. However, we don't load it
3662 if we are configured for an embedded target */
3663 flags
= SEC_READONLY
| SEC_DATA
;
3664 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3665 flags
|= SEC_ALLOC
| SEC_LOAD
;
3667 if (mips_abi
!= N64_ABI
)
3669 sec
= subseg_new (".reginfo", (subsegT
) 0);
3671 bfd_set_section_flags (stdoutput
, sec
, flags
);
3672 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3674 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3678 /* The 64-bit ABI uses a .MIPS.options section rather than
3679 .reginfo section. */
3680 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3681 bfd_set_section_flags (stdoutput
, sec
, flags
);
3682 bfd_set_section_alignment (stdoutput
, sec
, 3);
3684 /* Set up the option header. */
3686 Elf_Internal_Options opthdr
;
3689 opthdr
.kind
= ODK_REGINFO
;
3690 opthdr
.size
= (sizeof (Elf_External_Options
)
3691 + sizeof (Elf64_External_RegInfo
));
3694 f
= frag_more (sizeof (Elf_External_Options
));
3695 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3696 (Elf_External_Options
*) f
);
3698 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3702 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3703 bfd_set_section_flags (stdoutput
, sec
,
3704 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3705 bfd_set_section_alignment (stdoutput
, sec
, 3);
3706 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3708 if (ECOFF_DEBUGGING
)
3710 sec
= subseg_new (".mdebug", (subsegT
) 0);
3711 (void) bfd_set_section_flags (stdoutput
, sec
,
3712 SEC_HAS_CONTENTS
| SEC_READONLY
);
3713 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3715 else if (mips_flag_pdr
)
3717 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3718 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3719 SEC_READONLY
| SEC_RELOC
3721 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3724 subseg_set (seg
, subseg
);
3727 if (mips_fix_vr4120
)
3728 init_vr4120_conflicts ();
3732 fpabi_incompatible_with (int fpabi
, const char *what
)
3734 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3735 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3739 fpabi_requires (int fpabi
, const char *what
)
3741 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3742 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3745 /* Check -mabi and register sizes against the specified FP ABI. */
3747 check_fpabi (int fpabi
)
3751 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3752 if (file_mips_opts
.soft_float
)
3753 fpabi_incompatible_with (fpabi
, "softfloat");
3754 else if (file_mips_opts
.single_float
)
3755 fpabi_incompatible_with (fpabi
, "singlefloat");
3756 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3757 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3758 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3759 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3762 case Val_GNU_MIPS_ABI_FP_XX
:
3763 if (mips_abi
!= O32_ABI
)
3764 fpabi_requires (fpabi
, "-mabi=32");
3765 else if (file_mips_opts
.soft_float
)
3766 fpabi_incompatible_with (fpabi
, "softfloat");
3767 else if (file_mips_opts
.single_float
)
3768 fpabi_incompatible_with (fpabi
, "singlefloat");
3769 else if (file_mips_opts
.fp
!= 0)
3770 fpabi_requires (fpabi
, "fp=xx");
3773 case Val_GNU_MIPS_ABI_FP_64A
:
3774 case Val_GNU_MIPS_ABI_FP_64
:
3775 if (mips_abi
!= O32_ABI
)
3776 fpabi_requires (fpabi
, "-mabi=32");
3777 else if (file_mips_opts
.soft_float
)
3778 fpabi_incompatible_with (fpabi
, "softfloat");
3779 else if (file_mips_opts
.single_float
)
3780 fpabi_incompatible_with (fpabi
, "singlefloat");
3781 else if (file_mips_opts
.fp
!= 64)
3782 fpabi_requires (fpabi
, "fp=64");
3783 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3784 fpabi_incompatible_with (fpabi
, "nooddspreg");
3785 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3786 fpabi_requires (fpabi
, "nooddspreg");
3789 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3790 if (file_mips_opts
.soft_float
)
3791 fpabi_incompatible_with (fpabi
, "softfloat");
3792 else if (!file_mips_opts
.single_float
)
3793 fpabi_requires (fpabi
, "singlefloat");
3796 case Val_GNU_MIPS_ABI_FP_SOFT
:
3797 if (!file_mips_opts
.soft_float
)
3798 fpabi_requires (fpabi
, "softfloat");
3801 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3802 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3803 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3806 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3807 /* Silently ignore compatibility value. */
3811 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3812 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3817 /* Perform consistency checks on the current options. */
3820 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3822 /* Check the size of integer registers agrees with the ABI and ISA. */
3823 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3824 as_bad (_("`gp=64' used with a 32-bit processor"));
3826 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3827 as_bad (_("`gp=32' used with a 64-bit ABI"));
3829 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3830 as_bad (_("`gp=64' used with a 32-bit ABI"));
3832 /* Check the size of the float registers agrees with the ABI and ISA. */
3836 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3837 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3838 else if (opts
->single_float
== 1)
3839 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3842 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3843 as_bad (_("`fp=64' used with a 32-bit fpu"));
3845 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3846 && !ISA_HAS_MXHC1 (opts
->isa
))
3847 as_warn (_("`fp=64' used with a 32-bit ABI"));
3851 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3852 as_warn (_("`fp=32' used with a 64-bit ABI"));
3853 if (ISA_IS_R6 (mips_opts
.isa
) && opts
->single_float
== 0)
3854 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3857 as_bad (_("Unknown size of floating point registers"));
3861 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3862 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3864 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3865 as_bad (_("`mips16' cannot be used with `micromips'"));
3866 else if (ISA_IS_R6 (mips_opts
.isa
)
3867 && (opts
->micromips
== 1
3868 || opts
->mips16
== 1))
3869 as_fatal (_("`%s' can not be used with `%s'"),
3870 opts
->micromips
? "micromips" : "mips16",
3871 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
3873 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3874 as_fatal (_("branch relaxation is not supported in `%s'"),
3875 mips_cpu_info_from_isa (opts
->isa
)->name
);
3878 /* Perform consistency checks on the module level options exactly once.
3879 This is a deferred check that happens:
3880 at the first .set directive
3881 or, at the first pseudo op that generates code (inc .dc.a)
3882 or, at the first instruction
3886 file_mips_check_options (void)
3888 const struct mips_cpu_info
*arch_info
= 0;
3890 if (file_mips_opts_checked
)
3893 /* The following code determines the register size.
3894 Similar code was added to GCC 3.3 (see override_options() in
3895 config/mips/mips.c). The GAS and GCC code should be kept in sync
3896 as much as possible. */
3898 if (file_mips_opts
.gp
< 0)
3900 /* Infer the integer register size from the ABI and processor.
3901 Restrict ourselves to 32-bit registers if that's all the
3902 processor has, or if the ABI cannot handle 64-bit registers. */
3903 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3904 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3908 if (file_mips_opts
.fp
< 0)
3910 /* No user specified float register size.
3911 ??? GAS treats single-float processors as though they had 64-bit
3912 float registers (although it complains when double-precision
3913 instructions are used). As things stand, saying they have 32-bit
3914 registers would lead to spurious "register must be even" messages.
3915 So here we assume float registers are never smaller than the
3917 if (file_mips_opts
.gp
== 64)
3918 /* 64-bit integer registers implies 64-bit float registers. */
3919 file_mips_opts
.fp
= 64;
3920 else if ((file_mips_opts
.ase
& FP64_ASES
)
3921 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3922 /* Handle ASEs that require 64-bit float registers, if possible. */
3923 file_mips_opts
.fp
= 64;
3924 else if (ISA_IS_R6 (mips_opts
.isa
))
3925 /* R6 implies 64-bit float registers. */
3926 file_mips_opts
.fp
= 64;
3928 /* 32-bit float registers. */
3929 file_mips_opts
.fp
= 32;
3932 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3934 /* Disable operations on odd-numbered floating-point registers by default
3935 when using the FPXX ABI. */
3936 if (file_mips_opts
.oddspreg
< 0)
3938 if (file_mips_opts
.fp
== 0)
3939 file_mips_opts
.oddspreg
= 0;
3941 file_mips_opts
.oddspreg
= 1;
3944 /* End of GCC-shared inference code. */
3946 /* This flag is set when we have a 64-bit capable CPU but use only
3947 32-bit wide registers. Note that EABI does not use it. */
3948 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
3949 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
3950 || mips_abi
== O32_ABI
))
3953 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
3954 as_bad (_("trap exception not supported at ISA 1"));
3956 /* If the selected architecture includes support for ASEs, enable
3957 generation of code for them. */
3958 if (file_mips_opts
.mips16
== -1)
3959 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
3960 if (file_mips_opts
.micromips
== -1)
3961 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
3964 if (mips_nan2008
== -1)
3965 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
3966 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
3967 as_fatal (_("`%s' does not support legacy NaN"),
3968 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
3970 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3971 being selected implicitly. */
3972 if (file_mips_opts
.fp
!= 64)
3973 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
3975 /* If the user didn't explicitly select or deselect a particular ASE,
3976 use the default setting for the CPU. */
3977 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
3979 /* Set up the current options. These may change throughout assembly. */
3980 mips_opts
= file_mips_opts
;
3982 mips_check_isa_supports_ases ();
3983 mips_check_options (&file_mips_opts
, TRUE
);
3984 file_mips_opts_checked
= TRUE
;
3986 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3987 as_warn (_("could not set architecture and machine"));
3991 md_assemble (char *str
)
3993 struct mips_cl_insn insn
;
3994 bfd_reloc_code_real_type unused_reloc
[3]
3995 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3997 file_mips_check_options ();
3999 imm_expr
.X_op
= O_absent
;
4000 offset_expr
.X_op
= O_absent
;
4001 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4002 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4003 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4005 mips_mark_labels ();
4006 mips_assembling_insn
= TRUE
;
4007 clear_insn_error ();
4009 if (mips_opts
.mips16
)
4010 mips16_ip (str
, &insn
);
4013 mips_ip (str
, &insn
);
4014 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4015 str
, insn
.insn_opcode
));
4019 report_insn_error (str
);
4020 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4023 if (mips_opts
.mips16
)
4024 mips16_macro (&insn
);
4031 if (offset_expr
.X_op
!= O_absent
)
4032 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4034 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4037 mips_assembling_insn
= FALSE
;
4040 /* Convenience functions for abstracting away the differences between
4041 MIPS16 and non-MIPS16 relocations. */
4043 static inline bfd_boolean
4044 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4048 case BFD_RELOC_MIPS16_JMP
:
4049 case BFD_RELOC_MIPS16_GPREL
:
4050 case BFD_RELOC_MIPS16_GOT16
:
4051 case BFD_RELOC_MIPS16_CALL16
:
4052 case BFD_RELOC_MIPS16_HI16_S
:
4053 case BFD_RELOC_MIPS16_HI16
:
4054 case BFD_RELOC_MIPS16_LO16
:
4062 static inline bfd_boolean
4063 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4067 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4068 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4069 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4070 case BFD_RELOC_MICROMIPS_GPREL16
:
4071 case BFD_RELOC_MICROMIPS_JMP
:
4072 case BFD_RELOC_MICROMIPS_HI16
:
4073 case BFD_RELOC_MICROMIPS_HI16_S
:
4074 case BFD_RELOC_MICROMIPS_LO16
:
4075 case BFD_RELOC_MICROMIPS_LITERAL
:
4076 case BFD_RELOC_MICROMIPS_GOT16
:
4077 case BFD_RELOC_MICROMIPS_CALL16
:
4078 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4079 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4080 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4081 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4082 case BFD_RELOC_MICROMIPS_SUB
:
4083 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4084 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4085 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4086 case BFD_RELOC_MICROMIPS_HIGHEST
:
4087 case BFD_RELOC_MICROMIPS_HIGHER
:
4088 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4089 case BFD_RELOC_MICROMIPS_JALR
:
4097 static inline bfd_boolean
4098 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4100 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4103 static inline bfd_boolean
4104 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4106 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4107 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4110 static inline bfd_boolean
4111 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4113 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4114 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4117 static inline bfd_boolean
4118 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4120 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4121 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4124 static inline bfd_boolean
4125 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4127 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4130 static inline bfd_boolean
4131 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4133 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4134 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4137 /* Return true if RELOC is a PC-relative relocation that does not have
4138 full address range. */
4140 static inline bfd_boolean
4141 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4145 case BFD_RELOC_16_PCREL_S2
:
4146 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4147 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4148 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4149 case BFD_RELOC_MIPS_21_PCREL_S2
:
4150 case BFD_RELOC_MIPS_26_PCREL_S2
:
4151 case BFD_RELOC_MIPS_18_PCREL_S3
:
4152 case BFD_RELOC_MIPS_19_PCREL_S2
:
4155 case BFD_RELOC_32_PCREL
:
4156 case BFD_RELOC_HI16_S_PCREL
:
4157 case BFD_RELOC_LO16_PCREL
:
4158 return HAVE_64BIT_ADDRESSES
;
4165 /* Return true if the given relocation might need a matching %lo().
4166 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4167 need a matching %lo() when applied to local symbols. */
4169 static inline bfd_boolean
4170 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4172 return (HAVE_IN_PLACE_ADDENDS
4173 && (hi16_reloc_p (reloc
)
4174 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4175 all GOT16 relocations evaluate to "G". */
4176 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4179 /* Return the type of %lo() reloc needed by RELOC, given that
4180 reloc_needs_lo_p. */
4182 static inline bfd_reloc_code_real_type
4183 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4185 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4186 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4190 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4193 static inline bfd_boolean
4194 fixup_has_matching_lo_p (fixS
*fixp
)
4196 return (fixp
->fx_next
!= NULL
4197 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4198 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4199 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4202 /* Move all labels in LABELS to the current insertion point. TEXT_P
4203 says whether the labels refer to text or data. */
4206 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4208 struct insn_label_list
*l
;
4211 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4213 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4214 symbol_set_frag (l
->label
, frag_now
);
4215 val
= (valueT
) frag_now_fix ();
4216 /* MIPS16/microMIPS text labels are stored as odd. */
4217 if (text_p
&& HAVE_CODE_COMPRESSION
)
4219 S_SET_VALUE (l
->label
, val
);
4223 /* Move all labels in insn_labels to the current insertion point
4224 and treat them as text labels. */
4227 mips_move_text_labels (void)
4229 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4233 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4235 bfd_boolean linkonce
= FALSE
;
4236 segT symseg
= S_GET_SEGMENT (sym
);
4238 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4240 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4242 /* The GNU toolchain uses an extension for ELF: a section
4243 beginning with the magic string .gnu.linkonce is a
4244 linkonce section. */
4245 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4246 sizeof ".gnu.linkonce" - 1) == 0)
4252 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4253 linker to handle them specially, such as generating jalx instructions
4254 when needed. We also make them odd for the duration of the assembly,
4255 in order to generate the right sort of code. We will make them even
4256 in the adjust_symtab routine, while leaving them marked. This is
4257 convenient for the debugger and the disassembler. The linker knows
4258 to make them odd again. */
4261 mips_compressed_mark_label (symbolS
*label
)
4263 gas_assert (HAVE_CODE_COMPRESSION
);
4265 if (mips_opts
.mips16
)
4266 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4268 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4269 if ((S_GET_VALUE (label
) & 1) == 0
4270 /* Don't adjust the address if the label is global or weak, or
4271 in a link-once section, since we'll be emitting symbol reloc
4272 references to it which will be patched up by the linker, and
4273 the final value of the symbol may or may not be MIPS16/microMIPS. */
4274 && !S_IS_WEAK (label
)
4275 && !S_IS_EXTERNAL (label
)
4276 && !s_is_linkonce (label
, now_seg
))
4277 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4280 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4283 mips_compressed_mark_labels (void)
4285 struct insn_label_list
*l
;
4287 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4288 mips_compressed_mark_label (l
->label
);
4291 /* End the current frag. Make it a variant frag and record the
4295 relax_close_frag (void)
4297 mips_macro_warning
.first_frag
= frag_now
;
4298 frag_var (rs_machine_dependent
, 0, 0,
4299 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
4300 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4302 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4303 mips_relax
.first_fixup
= 0;
4306 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4307 See the comment above RELAX_ENCODE for more details. */
4310 relax_start (symbolS
*symbol
)
4312 gas_assert (mips_relax
.sequence
== 0);
4313 mips_relax
.sequence
= 1;
4314 mips_relax
.symbol
= symbol
;
4317 /* Start generating the second version of a relaxable sequence.
4318 See the comment above RELAX_ENCODE for more details. */
4323 gas_assert (mips_relax
.sequence
== 1);
4324 mips_relax
.sequence
= 2;
4327 /* End the current relaxable sequence. */
4332 gas_assert (mips_relax
.sequence
== 2);
4333 relax_close_frag ();
4334 mips_relax
.sequence
= 0;
4337 /* Return true if IP is a delayed branch or jump. */
4339 static inline bfd_boolean
4340 delayed_branch_p (const struct mips_cl_insn
*ip
)
4342 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4343 | INSN_COND_BRANCH_DELAY
4344 | INSN_COND_BRANCH_LIKELY
)) != 0;
4347 /* Return true if IP is a compact branch or jump. */
4349 static inline bfd_boolean
4350 compact_branch_p (const struct mips_cl_insn
*ip
)
4352 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4353 | INSN2_COND_BRANCH
)) != 0;
4356 /* Return true if IP is an unconditional branch or jump. */
4358 static inline bfd_boolean
4359 uncond_branch_p (const struct mips_cl_insn
*ip
)
4361 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4362 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4365 /* Return true if IP is a branch-likely instruction. */
4367 static inline bfd_boolean
4368 branch_likely_p (const struct mips_cl_insn
*ip
)
4370 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4373 /* Return the type of nop that should be used to fill the delay slot
4374 of delayed branch IP. */
4376 static struct mips_cl_insn
*
4377 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4379 if (mips_opts
.micromips
4380 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4381 return µmips_nop32_insn
;
4385 /* Return a mask that has bit N set if OPCODE reads the register(s)
4389 insn_read_mask (const struct mips_opcode
*opcode
)
4391 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4394 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4398 insn_write_mask (const struct mips_opcode
*opcode
)
4400 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4403 /* Return a mask of the registers specified by operand OPERAND of INSN.
4404 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4408 operand_reg_mask (const struct mips_cl_insn
*insn
,
4409 const struct mips_operand
*operand
,
4410 unsigned int type_mask
)
4412 unsigned int uval
, vsel
;
4414 switch (operand
->type
)
4421 case OP_ADDIUSP_INT
:
4422 case OP_ENTRY_EXIT_LIST
:
4423 case OP_REPEAT_DEST_REG
:
4424 case OP_REPEAT_PREV_REG
:
4427 case OP_VU0_MATCH_SUFFIX
:
4432 case OP_OPTIONAL_REG
:
4434 const struct mips_reg_operand
*reg_op
;
4436 reg_op
= (const struct mips_reg_operand
*) operand
;
4437 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4439 uval
= insn_extract_operand (insn
, operand
);
4440 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4445 const struct mips_reg_pair_operand
*pair_op
;
4447 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4448 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4450 uval
= insn_extract_operand (insn
, operand
);
4451 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4454 case OP_CLO_CLZ_DEST
:
4455 if (!(type_mask
& (1 << OP_REG_GP
)))
4457 uval
= insn_extract_operand (insn
, operand
);
4458 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4461 if (!(type_mask
& (1 << OP_REG_GP
)))
4463 uval
= insn_extract_operand (insn
, operand
);
4464 gas_assert ((uval
& 31) == (uval
>> 5));
4465 return 1 << (uval
& 31);
4468 case OP_NON_ZERO_REG
:
4469 if (!(type_mask
& (1 << OP_REG_GP
)))
4471 uval
= insn_extract_operand (insn
, operand
);
4472 return 1 << (uval
& 31);
4474 case OP_LWM_SWM_LIST
:
4477 case OP_SAVE_RESTORE_LIST
:
4480 case OP_MDMX_IMM_REG
:
4481 if (!(type_mask
& (1 << OP_REG_VEC
)))
4483 uval
= insn_extract_operand (insn
, operand
);
4485 if ((vsel
& 0x18) == 0x18)
4487 return 1 << (uval
& 31);
4490 if (!(type_mask
& (1 << OP_REG_GP
)))
4492 return 1 << insn_extract_operand (insn
, operand
);
4497 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4498 where bit N of OPNO_MASK is set if operand N should be included.
4499 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4503 insn_reg_mask (const struct mips_cl_insn
*insn
,
4504 unsigned int type_mask
, unsigned int opno_mask
)
4506 unsigned int opno
, reg_mask
;
4510 while (opno_mask
!= 0)
4513 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4520 /* Return the mask of core registers that IP reads. */
4523 gpr_read_mask (const struct mips_cl_insn
*ip
)
4525 unsigned long pinfo
, pinfo2
;
4528 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4529 pinfo
= ip
->insn_mo
->pinfo
;
4530 pinfo2
= ip
->insn_mo
->pinfo2
;
4531 if (pinfo
& INSN_UDI
)
4533 /* UDI instructions have traditionally been assumed to read RS
4535 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4536 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4538 if (pinfo
& INSN_READ_GPR_24
)
4540 if (pinfo2
& INSN2_READ_GPR_16
)
4542 if (pinfo2
& INSN2_READ_SP
)
4544 if (pinfo2
& INSN2_READ_GPR_31
)
4546 /* Don't include register 0. */
4550 /* Return the mask of core registers that IP writes. */
4553 gpr_write_mask (const struct mips_cl_insn
*ip
)
4555 unsigned long pinfo
, pinfo2
;
4558 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4559 pinfo
= ip
->insn_mo
->pinfo
;
4560 pinfo2
= ip
->insn_mo
->pinfo2
;
4561 if (pinfo
& INSN_WRITE_GPR_24
)
4563 if (pinfo
& INSN_WRITE_GPR_31
)
4565 if (pinfo
& INSN_UDI
)
4566 /* UDI instructions have traditionally been assumed to write to RD. */
4567 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4568 if (pinfo2
& INSN2_WRITE_SP
)
4570 /* Don't include register 0. */
4574 /* Return the mask of floating-point registers that IP reads. */
4577 fpr_read_mask (const struct mips_cl_insn
*ip
)
4579 unsigned long pinfo
;
4582 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4583 | (1 << OP_REG_MSA
)),
4584 insn_read_mask (ip
->insn_mo
));
4585 pinfo
= ip
->insn_mo
->pinfo
;
4586 /* Conservatively treat all operands to an FP_D instruction are doubles.
4587 (This is overly pessimistic for things like cvt.d.s.) */
4588 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4593 /* Return the mask of floating-point registers that IP writes. */
4596 fpr_write_mask (const struct mips_cl_insn
*ip
)
4598 unsigned long pinfo
;
4601 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4602 | (1 << OP_REG_MSA
)),
4603 insn_write_mask (ip
->insn_mo
));
4604 pinfo
= ip
->insn_mo
->pinfo
;
4605 /* Conservatively treat all operands to an FP_D instruction are doubles.
4606 (This is overly pessimistic for things like cvt.s.d.) */
4607 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4612 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4613 Check whether that is allowed. */
4616 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4618 const char *s
= insn
->name
;
4619 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4621 && mips_opts
.oddspreg
;
4623 if (insn
->pinfo
== INSN_MACRO
)
4624 /* Let a macro pass, we'll catch it later when it is expanded. */
4627 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4628 otherwise it depends on oddspreg. */
4629 if ((insn
->pinfo
& FP_S
)
4630 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4631 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4632 return FPR_SIZE
== 32 || oddspreg
;
4634 /* Allow odd registers for single-precision ops and double-precision if the
4635 floating-point registers are 64-bit wide. */
4636 switch (insn
->pinfo
& (FP_S
| FP_D
))
4642 return FPR_SIZE
== 64;
4647 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4648 s
= strchr (insn
->name
, '.');
4649 if (s
!= NULL
&& opnum
== 2)
4650 s
= strchr (s
+ 1, '.');
4651 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4654 return FPR_SIZE
== 64;
4657 /* Information about an instruction argument that we're trying to match. */
4658 struct mips_arg_info
4660 /* The instruction so far. */
4661 struct mips_cl_insn
*insn
;
4663 /* The first unconsumed operand token. */
4664 struct mips_operand_token
*token
;
4666 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4669 /* The 1-based argument number, for error reporting. This does not
4670 count elided optional registers, etc.. */
4673 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4674 unsigned int last_regno
;
4676 /* If the first operand was an OP_REG, this is the register that it
4677 specified, otherwise it is ILLEGAL_REG. */
4678 unsigned int dest_regno
;
4680 /* The value of the last OP_INT operand. Only used for OP_MSB,
4681 where it gives the lsb position. */
4682 unsigned int last_op_int
;
4684 /* If true, match routines should assume that no later instruction
4685 alternative matches and should therefore be as accomodating as
4686 possible. Match routines should not report errors if something
4687 is only invalid for !LAX_MATCH. */
4688 bfd_boolean lax_match
;
4690 /* True if a reference to the current AT register was seen. */
4691 bfd_boolean seen_at
;
4694 /* Record that the argument is out of range. */
4697 match_out_of_range (struct mips_arg_info
*arg
)
4699 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4702 /* Record that the argument isn't constant but needs to be. */
4705 match_not_constant (struct mips_arg_info
*arg
)
4707 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4711 /* Try to match an OT_CHAR token for character CH. Consume the token
4712 and return true on success, otherwise return false. */
4715 match_char (struct mips_arg_info
*arg
, char ch
)
4717 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4727 /* Try to get an expression from the next tokens in ARG. Consume the
4728 tokens and return true on success, storing the expression value in
4729 VALUE and relocation types in R. */
4732 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4733 bfd_reloc_code_real_type
*r
)
4735 /* If the next token is a '(' that was parsed as being part of a base
4736 expression, assume we have an elided offset. The later match will fail
4737 if this turns out to be wrong. */
4738 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4740 value
->X_op
= O_constant
;
4741 value
->X_add_number
= 0;
4742 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4746 /* Reject register-based expressions such as "0+$2" and "(($2))".
4747 For plain registers the default error seems more appropriate. */
4748 if (arg
->token
->type
== OT_INTEGER
4749 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4751 set_insn_error (arg
->argnum
, _("register value used as expression"));
4755 if (arg
->token
->type
== OT_INTEGER
)
4757 *value
= arg
->token
->u
.integer
.value
;
4758 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4764 (arg
->argnum
, _("operand %d must be an immediate expression"),
4769 /* Try to get a constant expression from the next tokens in ARG. Consume
4770 the tokens and return return true on success, storing the constant value
4771 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4775 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4778 bfd_reloc_code_real_type r
[3];
4780 if (!match_expression (arg
, &ex
, r
))
4783 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4784 *value
= ex
.X_add_number
;
4787 match_not_constant (arg
);
4793 /* Return the RTYPE_* flags for a register operand of type TYPE that
4794 appears in instruction OPCODE. */
4797 convert_reg_type (const struct mips_opcode
*opcode
,
4798 enum mips_reg_operand_type type
)
4803 return RTYPE_NUM
| RTYPE_GP
;
4806 /* Allow vector register names for MDMX if the instruction is a 64-bit
4807 FPR load, store or move (including moves to and from GPRs). */
4808 if ((mips_opts
.ase
& ASE_MDMX
)
4809 && (opcode
->pinfo
& FP_D
)
4810 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4811 | INSN_COPROC_MEMORY_DELAY
4814 | INSN_STORE_MEMORY
)))
4815 return RTYPE_FPU
| RTYPE_VEC
;
4819 if (opcode
->pinfo
& (FP_D
| FP_S
))
4820 return RTYPE_CCC
| RTYPE_FCC
;
4824 if (opcode
->membership
& INSN_5400
)
4826 return RTYPE_FPU
| RTYPE_VEC
;
4832 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4833 return RTYPE_NUM
| RTYPE_CP0
;
4840 return RTYPE_NUM
| RTYPE_VI
;
4843 return RTYPE_NUM
| RTYPE_VF
;
4845 case OP_REG_R5900_I
:
4846 return RTYPE_R5900_I
;
4848 case OP_REG_R5900_Q
:
4849 return RTYPE_R5900_Q
;
4851 case OP_REG_R5900_R
:
4852 return RTYPE_R5900_R
;
4854 case OP_REG_R5900_ACC
:
4855 return RTYPE_R5900_ACC
;
4860 case OP_REG_MSA_CTRL
:
4866 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4869 check_regno (struct mips_arg_info
*arg
,
4870 enum mips_reg_operand_type type
, unsigned int regno
)
4872 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4873 arg
->seen_at
= TRUE
;
4875 if (type
== OP_REG_FP
4877 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4879 /* This was a warning prior to introducing O32 FPXX and FP64 support
4880 so maintain a warning for FP32 but raise an error for the new
4883 as_warn (_("float register should be even, was %d"), regno
);
4885 as_bad (_("float register should be even, was %d"), regno
);
4888 if (type
== OP_REG_CCC
)
4893 name
= arg
->insn
->insn_mo
->name
;
4894 length
= strlen (name
);
4895 if ((regno
& 1) != 0
4896 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4897 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4898 as_warn (_("condition code register should be even for %s, was %d"),
4901 if ((regno
& 3) != 0
4902 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4903 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4908 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4909 a register of type TYPE. Return true on success, storing the register
4910 number in *REGNO and warning about any dubious uses. */
4913 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4914 unsigned int symval
, unsigned int *regno
)
4916 if (type
== OP_REG_VEC
)
4917 symval
= mips_prefer_vec_regno (symval
);
4918 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4921 *regno
= symval
& RNUM_MASK
;
4922 check_regno (arg
, type
, *regno
);
4926 /* Try to interpret the next token in ARG as a register of type TYPE.
4927 Consume the token and return true on success, storing the register
4928 number in *REGNO. Return false on failure. */
4931 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4932 unsigned int *regno
)
4934 if (arg
->token
->type
== OT_REG
4935 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4943 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4944 Consume the token and return true on success, storing the register numbers
4945 in *REGNO1 and *REGNO2. Return false on failure. */
4948 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4949 unsigned int *regno1
, unsigned int *regno2
)
4951 if (match_reg (arg
, type
, regno1
))
4956 if (arg
->token
->type
== OT_REG_RANGE
4957 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4958 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4959 && *regno1
<= *regno2
)
4967 /* OP_INT matcher. */
4970 match_int_operand (struct mips_arg_info
*arg
,
4971 const struct mips_operand
*operand_base
)
4973 const struct mips_int_operand
*operand
;
4975 int min_val
, max_val
, factor
;
4978 operand
= (const struct mips_int_operand
*) operand_base
;
4979 factor
= 1 << operand
->shift
;
4980 min_val
= mips_int_operand_min (operand
);
4981 max_val
= mips_int_operand_max (operand
);
4983 if (operand_base
->lsb
== 0
4984 && operand_base
->size
== 16
4985 && operand
->shift
== 0
4986 && operand
->bias
== 0
4987 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4989 /* The operand can be relocated. */
4990 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4993 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4994 /* Relocation operators were used. Accept the arguent and
4995 leave the relocation value in offset_expr and offset_relocs
4996 for the caller to process. */
4999 if (offset_expr
.X_op
!= O_constant
)
5001 /* Accept non-constant operands if no later alternative matches,
5002 leaving it for the caller to process. */
5003 if (!arg
->lax_match
)
5005 offset_reloc
[0] = BFD_RELOC_LO16
;
5009 /* Clear the global state; we're going to install the operand
5011 sval
= offset_expr
.X_add_number
;
5012 offset_expr
.X_op
= O_absent
;
5014 /* For compatibility with older assemblers, we accept
5015 0x8000-0xffff as signed 16-bit numbers when only
5016 signed numbers are allowed. */
5019 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5020 if (!arg
->lax_match
&& sval
<= max_val
)
5026 if (!match_const_int (arg
, &sval
))
5030 arg
->last_op_int
= sval
;
5032 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5034 match_out_of_range (arg
);
5038 uval
= (unsigned int) sval
>> operand
->shift
;
5039 uval
-= operand
->bias
;
5041 /* Handle -mfix-cn63xxp1. */
5043 && mips_fix_cn63xxp1
5044 && !mips_opts
.micromips
5045 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5060 /* The rest must be changed to 28. */
5065 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5069 /* OP_MAPPED_INT matcher. */
5072 match_mapped_int_operand (struct mips_arg_info
*arg
,
5073 const struct mips_operand
*operand_base
)
5075 const struct mips_mapped_int_operand
*operand
;
5076 unsigned int uval
, num_vals
;
5079 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5080 if (!match_const_int (arg
, &sval
))
5083 num_vals
= 1 << operand_base
->size
;
5084 for (uval
= 0; uval
< num_vals
; uval
++)
5085 if (operand
->int_map
[uval
] == sval
)
5087 if (uval
== num_vals
)
5089 match_out_of_range (arg
);
5093 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5097 /* OP_MSB matcher. */
5100 match_msb_operand (struct mips_arg_info
*arg
,
5101 const struct mips_operand
*operand_base
)
5103 const struct mips_msb_operand
*operand
;
5104 int min_val
, max_val
, max_high
;
5105 offsetT size
, sval
, high
;
5107 operand
= (const struct mips_msb_operand
*) operand_base
;
5108 min_val
= operand
->bias
;
5109 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5110 max_high
= operand
->opsize
;
5112 if (!match_const_int (arg
, &size
))
5115 high
= size
+ arg
->last_op_int
;
5116 sval
= operand
->add_lsb
? high
: size
;
5118 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5120 match_out_of_range (arg
);
5123 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5127 /* OP_REG matcher. */
5130 match_reg_operand (struct mips_arg_info
*arg
,
5131 const struct mips_operand
*operand_base
)
5133 const struct mips_reg_operand
*operand
;
5134 unsigned int regno
, uval
, num_vals
;
5136 operand
= (const struct mips_reg_operand
*) operand_base
;
5137 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5140 if (operand
->reg_map
)
5142 num_vals
= 1 << operand
->root
.size
;
5143 for (uval
= 0; uval
< num_vals
; uval
++)
5144 if (operand
->reg_map
[uval
] == regno
)
5146 if (num_vals
== uval
)
5152 arg
->last_regno
= regno
;
5153 if (arg
->opnum
== 1)
5154 arg
->dest_regno
= regno
;
5155 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5159 /* OP_REG_PAIR matcher. */
5162 match_reg_pair_operand (struct mips_arg_info
*arg
,
5163 const struct mips_operand
*operand_base
)
5165 const struct mips_reg_pair_operand
*operand
;
5166 unsigned int regno1
, regno2
, uval
, num_vals
;
5168 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5169 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5170 || !match_char (arg
, ',')
5171 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5174 num_vals
= 1 << operand_base
->size
;
5175 for (uval
= 0; uval
< num_vals
; uval
++)
5176 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5178 if (uval
== num_vals
)
5181 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5185 /* OP_PCREL matcher. The caller chooses the relocation type. */
5188 match_pcrel_operand (struct mips_arg_info
*arg
)
5190 bfd_reloc_code_real_type r
[3];
5192 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5195 /* OP_PERF_REG matcher. */
5198 match_perf_reg_operand (struct mips_arg_info
*arg
,
5199 const struct mips_operand
*operand
)
5203 if (!match_const_int (arg
, &sval
))
5208 || (mips_opts
.arch
== CPU_R5900
5209 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5210 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5212 set_insn_error (arg
->argnum
, _("invalid performance register"));
5216 insn_insert_operand (arg
->insn
, operand
, sval
);
5220 /* OP_ADDIUSP matcher. */
5223 match_addiusp_operand (struct mips_arg_info
*arg
,
5224 const struct mips_operand
*operand
)
5229 if (!match_const_int (arg
, &sval
))
5234 match_out_of_range (arg
);
5239 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5241 match_out_of_range (arg
);
5245 uval
= (unsigned int) sval
;
5246 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5247 insn_insert_operand (arg
->insn
, operand
, uval
);
5251 /* OP_CLO_CLZ_DEST matcher. */
5254 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5255 const struct mips_operand
*operand
)
5259 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5262 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5266 /* OP_CHECK_PREV matcher. */
5269 match_check_prev_operand (struct mips_arg_info
*arg
,
5270 const struct mips_operand
*operand_base
)
5272 const struct mips_check_prev_operand
*operand
;
5275 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5277 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5280 if (!operand
->zero_ok
&& regno
== 0)
5283 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5284 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5285 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5287 arg
->last_regno
= regno
;
5288 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5295 /* OP_SAME_RS_RT matcher. */
5298 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5299 const struct mips_operand
*operand
)
5303 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5308 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5312 arg
->last_regno
= regno
;
5314 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5318 /* OP_LWM_SWM_LIST matcher. */
5321 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5322 const struct mips_operand
*operand
)
5324 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5325 struct mips_arg_info reset
;
5328 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5332 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5337 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5340 while (match_char (arg
, ',')
5341 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5344 if (operand
->size
== 2)
5346 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5352 and any permutations of these. */
5353 if ((reglist
& 0xfff1ffff) != 0x80010000)
5356 sregs
= (reglist
>> 17) & 7;
5361 /* The list must include at least one of ra and s0-sN,
5362 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5363 which are $23 and $30 respectively.) E.g.:
5371 and any permutations of these. */
5372 if ((reglist
& 0x3f00ffff) != 0)
5375 ra
= (reglist
>> 27) & 0x10;
5376 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5379 if ((sregs
& -sregs
) != sregs
)
5382 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5386 /* OP_ENTRY_EXIT_LIST matcher. */
5389 match_entry_exit_operand (struct mips_arg_info
*arg
,
5390 const struct mips_operand
*operand
)
5393 bfd_boolean is_exit
;
5395 /* The format is the same for both ENTRY and EXIT, but the constraints
5397 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5398 mask
= (is_exit
? 7 << 3 : 0);
5401 unsigned int regno1
, regno2
;
5402 bfd_boolean is_freg
;
5404 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5406 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5411 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5414 mask
|= (5 + regno2
) << 3;
5416 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5417 mask
|= (regno2
- 3) << 3;
5418 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5419 mask
|= (regno2
- 15) << 1;
5420 else if (regno1
== RA
&& regno2
== RA
)
5425 while (match_char (arg
, ','));
5427 insn_insert_operand (arg
->insn
, operand
, mask
);
5431 /* OP_SAVE_RESTORE_LIST matcher. */
5434 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5436 unsigned int opcode
, args
, statics
, sregs
;
5437 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5440 opcode
= arg
->insn
->insn_opcode
;
5442 num_frame_sizes
= 0;
5448 unsigned int regno1
, regno2
;
5450 if (arg
->token
->type
== OT_INTEGER
)
5452 /* Handle the frame size. */
5453 if (!match_const_int (arg
, &frame_size
))
5455 num_frame_sizes
+= 1;
5459 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5462 while (regno1
<= regno2
)
5464 if (regno1
>= 4 && regno1
<= 7)
5466 if (num_frame_sizes
== 0)
5468 args
|= 1 << (regno1
- 4);
5470 /* statics $a0-$a3 */
5471 statics
|= 1 << (regno1
- 4);
5473 else if (regno1
>= 16 && regno1
<= 23)
5475 sregs
|= 1 << (regno1
- 16);
5476 else if (regno1
== 30)
5479 else if (regno1
== 31)
5480 /* Add $ra to insn. */
5490 while (match_char (arg
, ','));
5492 /* Encode args/statics combination. */
5495 else if (args
== 0xf)
5496 /* All $a0-$a3 are args. */
5497 opcode
|= MIPS16_ALL_ARGS
<< 16;
5498 else if (statics
== 0xf)
5499 /* All $a0-$a3 are statics. */
5500 opcode
|= MIPS16_ALL_STATICS
<< 16;
5503 /* Count arg registers. */
5513 /* Count static registers. */
5515 while (statics
& 0x8)
5517 statics
= (statics
<< 1) & 0xf;
5523 /* Encode args/statics. */
5524 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5527 /* Encode $s0/$s1. */
5528 if (sregs
& (1 << 0)) /* $s0 */
5530 if (sregs
& (1 << 1)) /* $s1 */
5534 /* Encode $s2-$s8. */
5543 opcode
|= num_sregs
<< 24;
5545 /* Encode frame size. */
5546 if (num_frame_sizes
== 0)
5548 set_insn_error (arg
->argnum
, _("missing frame size"));
5551 if (num_frame_sizes
> 1)
5553 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5556 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5558 set_insn_error (arg
->argnum
, _("invalid frame size"));
5561 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5564 opcode
|= (((frame_size
& 0xf0) << 16)
5565 | (frame_size
& 0x0f));
5568 /* Finally build the instruction. */
5569 if ((opcode
>> 16) != 0 || frame_size
== 0)
5570 opcode
|= MIPS16_EXTEND
;
5571 arg
->insn
->insn_opcode
= opcode
;
5575 /* OP_MDMX_IMM_REG matcher. */
5578 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5579 const struct mips_operand
*operand
)
5581 unsigned int regno
, uval
;
5583 const struct mips_opcode
*opcode
;
5585 /* The mips_opcode records whether this is an octobyte or quadhalf
5586 instruction. Start out with that bit in place. */
5587 opcode
= arg
->insn
->insn_mo
;
5588 uval
= mips_extract_operand (operand
, opcode
->match
);
5589 is_qh
= (uval
!= 0);
5591 if (arg
->token
->type
== OT_REG
)
5593 if ((opcode
->membership
& INSN_5400
)
5594 && strcmp (opcode
->name
, "rzu.ob") == 0)
5596 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5601 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5605 /* Check whether this is a vector register or a broadcast of
5606 a single element. */
5607 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5609 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5611 set_insn_error (arg
->argnum
, _("invalid element selector"));
5614 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5619 /* A full vector. */
5620 if ((opcode
->membership
& INSN_5400
)
5621 && (strcmp (opcode
->name
, "sll.ob") == 0
5622 || strcmp (opcode
->name
, "srl.ob") == 0))
5624 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5630 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5632 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5640 if (!match_const_int (arg
, &sval
))
5642 if (sval
< 0 || sval
> 31)
5644 match_out_of_range (arg
);
5647 uval
|= (sval
& 31);
5649 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5651 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5653 insn_insert_operand (arg
->insn
, operand
, uval
);
5657 /* OP_IMM_INDEX matcher. */
5660 match_imm_index_operand (struct mips_arg_info
*arg
,
5661 const struct mips_operand
*operand
)
5663 unsigned int max_val
;
5665 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5668 max_val
= (1 << operand
->size
) - 1;
5669 if (arg
->token
->u
.index
> max_val
)
5671 match_out_of_range (arg
);
5674 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5679 /* OP_REG_INDEX matcher. */
5682 match_reg_index_operand (struct mips_arg_info
*arg
,
5683 const struct mips_operand
*operand
)
5687 if (arg
->token
->type
!= OT_REG_INDEX
)
5690 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5693 insn_insert_operand (arg
->insn
, operand
, regno
);
5698 /* OP_PC matcher. */
5701 match_pc_operand (struct mips_arg_info
*arg
)
5703 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5711 /* OP_NON_ZERO_REG matcher. */
5714 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5715 const struct mips_operand
*operand
)
5719 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5725 arg
->last_regno
= regno
;
5726 insn_insert_operand (arg
->insn
, operand
, regno
);
5730 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5731 register that we need to match. */
5734 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5738 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5741 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5742 the length of the value in bytes (4 for float, 8 for double) and
5743 USING_GPRS says whether the destination is a GPR rather than an FPR.
5745 Return the constant in IMM and OFFSET as follows:
5747 - If the constant should be loaded via memory, set IMM to O_absent and
5748 OFFSET to the memory address.
5750 - Otherwise, if the constant should be loaded into two 32-bit registers,
5751 set IMM to the O_constant to load into the high register and OFFSET
5752 to the corresponding value for the low register.
5754 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5756 These constants only appear as the last operand in an instruction,
5757 and every instruction that accepts them in any variant accepts them
5758 in all variants. This means we don't have to worry about backing out
5759 any changes if the instruction does not match. We just match
5760 unconditionally and report an error if the constant is invalid. */
5763 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5764 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5769 const char *newname
;
5770 unsigned char *data
;
5772 /* Where the constant is placed is based on how the MIPS assembler
5775 length == 4 && using_gprs -- immediate value only
5776 length == 8 && using_gprs -- .rdata or immediate value
5777 length == 4 && !using_gprs -- .lit4 or immediate value
5778 length == 8 && !using_gprs -- .lit8 or immediate value
5780 The .lit4 and .lit8 sections are only used if permitted by the
5782 if (arg
->token
->type
!= OT_FLOAT
)
5784 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5788 gas_assert (arg
->token
->u
.flt
.length
== length
);
5789 data
= arg
->token
->u
.flt
.data
;
5792 /* Handle 32-bit constants for which an immediate value is best. */
5795 || g_switch_value
< 4
5796 || (data
[0] == 0 && data
[1] == 0)
5797 || (data
[2] == 0 && data
[3] == 0)))
5799 imm
->X_op
= O_constant
;
5800 if (!target_big_endian
)
5801 imm
->X_add_number
= bfd_getl32 (data
);
5803 imm
->X_add_number
= bfd_getb32 (data
);
5804 offset
->X_op
= O_absent
;
5808 /* Handle 64-bit constants for which an immediate value is best. */
5810 && !mips_disable_float_construction
5811 /* Constants can only be constructed in GPRs and copied to FPRs if the
5812 GPRs are at least as wide as the FPRs or MTHC1 is available.
5813 Unlike most tests for 32-bit floating-point registers this check
5814 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5815 permit 64-bit moves without MXHC1.
5816 Force the constant into memory otherwise. */
5819 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5821 && ((data
[0] == 0 && data
[1] == 0)
5822 || (data
[2] == 0 && data
[3] == 0))
5823 && ((data
[4] == 0 && data
[5] == 0)
5824 || (data
[6] == 0 && data
[7] == 0)))
5826 /* The value is simple enough to load with a couple of instructions.
5827 If using 32-bit registers, set IMM to the high order 32 bits and
5828 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5830 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5832 imm
->X_op
= O_constant
;
5833 offset
->X_op
= O_constant
;
5834 if (!target_big_endian
)
5836 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5837 offset
->X_add_number
= bfd_getl32 (data
);
5841 imm
->X_add_number
= bfd_getb32 (data
);
5842 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5844 if (offset
->X_add_number
== 0)
5845 offset
->X_op
= O_absent
;
5849 imm
->X_op
= O_constant
;
5850 if (!target_big_endian
)
5851 imm
->X_add_number
= bfd_getl64 (data
);
5853 imm
->X_add_number
= bfd_getb64 (data
);
5854 offset
->X_op
= O_absent
;
5859 /* Switch to the right section. */
5861 subseg
= now_subseg
;
5864 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5869 if (using_gprs
|| g_switch_value
< 8)
5870 newname
= RDATA_SECTION_NAME
;
5875 new_seg
= subseg_new (newname
, (subsegT
) 0);
5876 bfd_set_section_flags (stdoutput
, new_seg
,
5877 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5878 frag_align (length
== 4 ? 2 : 3, 0, 0);
5879 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5880 record_alignment (new_seg
, 4);
5882 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5884 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5886 /* Set the argument to the current address in the section. */
5887 imm
->X_op
= O_absent
;
5888 offset
->X_op
= O_symbol
;
5889 offset
->X_add_symbol
= symbol_temp_new_now ();
5890 offset
->X_add_number
= 0;
5892 /* Put the floating point number into the section. */
5893 p
= frag_more (length
);
5894 memcpy (p
, data
, length
);
5896 /* Switch back to the original section. */
5897 subseg_set (seg
, subseg
);
5901 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5905 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5906 const struct mips_operand
*operand
,
5907 bfd_boolean match_p
)
5911 /* The operand can be an XYZW mask or a single 2-bit channel index
5912 (with X being 0). */
5913 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5915 /* The suffix can be omitted when it is already part of the opcode. */
5916 if (arg
->token
->type
!= OT_CHANNELS
)
5919 uval
= arg
->token
->u
.channels
;
5920 if (operand
->size
== 2)
5922 /* Check that a single bit is set and convert it into a 2-bit index. */
5923 if ((uval
& -uval
) != uval
)
5925 uval
= 4 - ffs (uval
);
5928 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5933 insn_insert_operand (arg
->insn
, operand
, uval
);
5937 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5938 of the argument text if the match is successful, otherwise return null. */
5941 match_operand (struct mips_arg_info
*arg
,
5942 const struct mips_operand
*operand
)
5944 switch (operand
->type
)
5947 return match_int_operand (arg
, operand
);
5950 return match_mapped_int_operand (arg
, operand
);
5953 return match_msb_operand (arg
, operand
);
5956 case OP_OPTIONAL_REG
:
5957 return match_reg_operand (arg
, operand
);
5960 return match_reg_pair_operand (arg
, operand
);
5963 return match_pcrel_operand (arg
);
5966 return match_perf_reg_operand (arg
, operand
);
5968 case OP_ADDIUSP_INT
:
5969 return match_addiusp_operand (arg
, operand
);
5971 case OP_CLO_CLZ_DEST
:
5972 return match_clo_clz_dest_operand (arg
, operand
);
5974 case OP_LWM_SWM_LIST
:
5975 return match_lwm_swm_list_operand (arg
, operand
);
5977 case OP_ENTRY_EXIT_LIST
:
5978 return match_entry_exit_operand (arg
, operand
);
5980 case OP_SAVE_RESTORE_LIST
:
5981 return match_save_restore_list_operand (arg
);
5983 case OP_MDMX_IMM_REG
:
5984 return match_mdmx_imm_reg_operand (arg
, operand
);
5986 case OP_REPEAT_DEST_REG
:
5987 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5989 case OP_REPEAT_PREV_REG
:
5990 return match_tied_reg_operand (arg
, arg
->last_regno
);
5993 return match_pc_operand (arg
);
5996 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5998 case OP_VU0_MATCH_SUFFIX
:
5999 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6002 return match_imm_index_operand (arg
, operand
);
6005 return match_reg_index_operand (arg
, operand
);
6008 return match_same_rs_rt_operand (arg
, operand
);
6011 return match_check_prev_operand (arg
, operand
);
6013 case OP_NON_ZERO_REG
:
6014 return match_non_zero_reg_operand (arg
, operand
);
6019 /* ARG is the state after successfully matching an instruction.
6020 Issue any queued-up warnings. */
6023 check_completed_insn (struct mips_arg_info
*arg
)
6028 as_warn (_("used $at without \".set noat\""));
6030 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6034 /* Return true if modifying general-purpose register REG needs a delay. */
6037 reg_needs_delay (unsigned int reg
)
6039 unsigned long prev_pinfo
;
6041 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6042 if (!mips_opts
.noreorder
6043 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6044 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6045 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6051 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6052 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6053 by VR4120 errata. */
6056 classify_vr4120_insn (const char *name
)
6058 if (strncmp (name
, "macc", 4) == 0)
6059 return FIX_VR4120_MACC
;
6060 if (strncmp (name
, "dmacc", 5) == 0)
6061 return FIX_VR4120_DMACC
;
6062 if (strncmp (name
, "mult", 4) == 0)
6063 return FIX_VR4120_MULT
;
6064 if (strncmp (name
, "dmult", 5) == 0)
6065 return FIX_VR4120_DMULT
;
6066 if (strstr (name
, "div"))
6067 return FIX_VR4120_DIV
;
6068 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6069 return FIX_VR4120_MTHILO
;
6070 return NUM_FIX_VR4120_CLASSES
;
6073 #define INSN_ERET 0x42000018
6074 #define INSN_DERET 0x4200001f
6075 #define INSN_DMULT 0x1c
6076 #define INSN_DMULTU 0x1d
6078 /* Return the number of instructions that must separate INSN1 and INSN2,
6079 where INSN1 is the earlier instruction. Return the worst-case value
6080 for any INSN2 if INSN2 is null. */
6083 insns_between (const struct mips_cl_insn
*insn1
,
6084 const struct mips_cl_insn
*insn2
)
6086 unsigned long pinfo1
, pinfo2
;
6089 /* If INFO2 is null, pessimistically assume that all flags are set for
6090 the second instruction. */
6091 pinfo1
= insn1
->insn_mo
->pinfo
;
6092 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6094 /* For most targets, write-after-read dependencies on the HI and LO
6095 registers must be separated by at least two instructions. */
6096 if (!hilo_interlocks
)
6098 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6100 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6104 /* If we're working around r7000 errata, there must be two instructions
6105 between an mfhi or mflo and any instruction that uses the result. */
6106 if (mips_7000_hilo_fix
6107 && !mips_opts
.micromips
6108 && MF_HILO_INSN (pinfo1
)
6109 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6112 /* If we're working around 24K errata, one instruction is required
6113 if an ERET or DERET is followed by a branch instruction. */
6114 if (mips_fix_24k
&& !mips_opts
.micromips
)
6116 if (insn1
->insn_opcode
== INSN_ERET
6117 || insn1
->insn_opcode
== INSN_DERET
)
6120 || insn2
->insn_opcode
== INSN_ERET
6121 || insn2
->insn_opcode
== INSN_DERET
6122 || delayed_branch_p (insn2
))
6127 /* If we're working around PMC RM7000 errata, there must be three
6128 nops between a dmult and a load instruction. */
6129 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6131 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6132 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6134 if (pinfo2
& INSN_LOAD_MEMORY
)
6139 /* If working around VR4120 errata, check for combinations that need
6140 a single intervening instruction. */
6141 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6143 unsigned int class1
, class2
;
6145 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6146 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6150 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6151 if (vr4120_conflicts
[class1
] & (1 << class2
))
6156 if (!HAVE_CODE_COMPRESSION
)
6158 /* Check for GPR or coprocessor load delays. All such delays
6159 are on the RT register. */
6160 /* Itbl support may require additional care here. */
6161 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6162 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6164 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6168 /* Check for generic coprocessor hazards.
6170 This case is not handled very well. There is no special
6171 knowledge of CP0 handling, and the coprocessors other than
6172 the floating point unit are not distinguished at all. */
6173 /* Itbl support may require additional care here. FIXME!
6174 Need to modify this to include knowledge about
6175 user specified delays! */
6176 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6177 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6179 /* Handle cases where INSN1 writes to a known general coprocessor
6180 register. There must be a one instruction delay before INSN2
6181 if INSN2 reads that register, otherwise no delay is needed. */
6182 mask
= fpr_write_mask (insn1
);
6185 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6190 /* Read-after-write dependencies on the control registers
6191 require a two-instruction gap. */
6192 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6193 && (pinfo2
& INSN_READ_COND_CODE
))
6196 /* We don't know exactly what INSN1 does. If INSN2 is
6197 also a coprocessor instruction, assume there must be
6198 a one instruction gap. */
6199 if (pinfo2
& INSN_COP
)
6204 /* Check for read-after-write dependencies on the coprocessor
6205 control registers in cases where INSN1 does not need a general
6206 coprocessor delay. This means that INSN1 is a floating point
6207 comparison instruction. */
6208 /* Itbl support may require additional care here. */
6209 else if (!cop_interlocks
6210 && (pinfo1
& INSN_WRITE_COND_CODE
)
6211 && (pinfo2
& INSN_READ_COND_CODE
))
6215 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6216 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6218 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6219 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6220 || (insn2
&& delayed_branch_p (insn2
))))
6226 /* Return the number of nops that would be needed to work around the
6227 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6228 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6229 that are contained within the first IGNORE instructions of HIST. */
6232 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6233 const struct mips_cl_insn
*insn
)
6238 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6239 are not affected by the errata. */
6241 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6242 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6243 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6246 /* Search for the first MFLO or MFHI. */
6247 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6248 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6250 /* Extract the destination register. */
6251 mask
= gpr_write_mask (&hist
[i
]);
6253 /* No nops are needed if INSN reads that register. */
6254 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6257 /* ...or if any of the intervening instructions do. */
6258 for (j
= 0; j
< i
; j
++)
6259 if (gpr_read_mask (&hist
[j
]) & mask
)
6263 return MAX_VR4130_NOPS
- i
;
6268 #define BASE_REG_EQ(INSN1, INSN2) \
6269 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6270 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6272 /* Return the minimum alignment for this store instruction. */
6275 fix_24k_align_to (const struct mips_opcode
*mo
)
6277 if (strcmp (mo
->name
, "sh") == 0)
6280 if (strcmp (mo
->name
, "swc1") == 0
6281 || strcmp (mo
->name
, "swc2") == 0
6282 || strcmp (mo
->name
, "sw") == 0
6283 || strcmp (mo
->name
, "sc") == 0
6284 || strcmp (mo
->name
, "s.s") == 0)
6287 if (strcmp (mo
->name
, "sdc1") == 0
6288 || strcmp (mo
->name
, "sdc2") == 0
6289 || strcmp (mo
->name
, "s.d") == 0)
6296 struct fix_24k_store_info
6298 /* Immediate offset, if any, for this store instruction. */
6300 /* Alignment required by this store instruction. */
6302 /* True for register offsets. */
6303 int register_offset
;
6306 /* Comparison function used by qsort. */
6309 fix_24k_sort (const void *a
, const void *b
)
6311 const struct fix_24k_store_info
*pos1
= a
;
6312 const struct fix_24k_store_info
*pos2
= b
;
6314 return (pos1
->off
- pos2
->off
);
6317 /* INSN is a store instruction. Try to record the store information
6318 in STINFO. Return false if the information isn't known. */
6321 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6322 const struct mips_cl_insn
*insn
)
6324 /* The instruction must have a known offset. */
6325 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6328 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6329 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6333 /* Return the number of nops that would be needed to work around the 24k
6334 "lost data on stores during refill" errata if instruction INSN
6335 immediately followed the 2 instructions described by HIST.
6336 Ignore hazards that are contained within the first IGNORE
6337 instructions of HIST.
6339 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6340 for the data cache refills and store data. The following describes
6341 the scenario where the store data could be lost.
6343 * A data cache miss, due to either a load or a store, causing fill
6344 data to be supplied by the memory subsystem
6345 * The first three doublewords of fill data are returned and written
6347 * A sequence of four stores occurs in consecutive cycles around the
6348 final doubleword of the fill:
6352 * Zero, One or more instructions
6355 The four stores A-D must be to different doublewords of the line that
6356 is being filled. The fourth instruction in the sequence above permits
6357 the fill of the final doubleword to be transferred from the FSB into
6358 the cache. In the sequence above, the stores may be either integer
6359 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6360 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6361 different doublewords on the line. If the floating point unit is
6362 running in 1:2 mode, it is not possible to create the sequence above
6363 using only floating point store instructions.
6365 In this case, the cache line being filled is incorrectly marked
6366 invalid, thereby losing the data from any store to the line that
6367 occurs between the original miss and the completion of the five
6368 cycle sequence shown above.
6370 The workarounds are:
6372 * Run the data cache in write-through mode.
6373 * Insert a non-store instruction between
6374 Store A and Store B or Store B and Store C. */
6377 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6378 const struct mips_cl_insn
*insn
)
6380 struct fix_24k_store_info pos
[3];
6381 int align
, i
, base_offset
;
6386 /* If the previous instruction wasn't a store, there's nothing to
6388 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6391 /* If the instructions after the previous one are unknown, we have
6392 to assume the worst. */
6396 /* Check whether we are dealing with three consecutive stores. */
6397 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6398 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6401 /* If we don't know the relationship between the store addresses,
6402 assume the worst. */
6403 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6404 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6407 if (!fix_24k_record_store_info (&pos
[0], insn
)
6408 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6409 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6412 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6414 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6415 X bytes and such that the base register + X is known to be aligned
6418 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6422 align
= pos
[0].align_to
;
6423 base_offset
= pos
[0].off
;
6424 for (i
= 1; i
< 3; i
++)
6425 if (align
< pos
[i
].align_to
)
6427 align
= pos
[i
].align_to
;
6428 base_offset
= pos
[i
].off
;
6430 for (i
= 0; i
< 3; i
++)
6431 pos
[i
].off
-= base_offset
;
6434 pos
[0].off
&= ~align
+ 1;
6435 pos
[1].off
&= ~align
+ 1;
6436 pos
[2].off
&= ~align
+ 1;
6438 /* If any two stores write to the same chunk, they also write to the
6439 same doubleword. The offsets are still sorted at this point. */
6440 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6443 /* A range of at least 9 bytes is needed for the stores to be in
6444 non-overlapping doublewords. */
6445 if (pos
[2].off
- pos
[0].off
<= 8)
6448 if (pos
[2].off
- pos
[1].off
>= 24
6449 || pos
[1].off
- pos
[0].off
>= 24
6450 || pos
[2].off
- pos
[0].off
>= 32)
6456 /* Return the number of nops that would be needed if instruction INSN
6457 immediately followed the MAX_NOPS instructions given by HIST,
6458 where HIST[0] is the most recent instruction. Ignore hazards
6459 between INSN and the first IGNORE instructions in HIST.
6461 If INSN is null, return the worse-case number of nops for any
6465 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6466 const struct mips_cl_insn
*insn
)
6468 int i
, nops
, tmp_nops
;
6471 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6473 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6474 if (tmp_nops
> nops
)
6478 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6480 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6481 if (tmp_nops
> nops
)
6485 if (mips_fix_24k
&& !mips_opts
.micromips
)
6487 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6488 if (tmp_nops
> nops
)
6495 /* The variable arguments provide NUM_INSNS extra instructions that
6496 might be added to HIST. Return the largest number of nops that
6497 would be needed after the extended sequence, ignoring hazards
6498 in the first IGNORE instructions. */
6501 nops_for_sequence (int num_insns
, int ignore
,
6502 const struct mips_cl_insn
*hist
, ...)
6505 struct mips_cl_insn buffer
[MAX_NOPS
];
6506 struct mips_cl_insn
*cursor
;
6509 va_start (args
, hist
);
6510 cursor
= buffer
+ num_insns
;
6511 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6512 while (cursor
> buffer
)
6513 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6515 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6520 /* Like nops_for_insn, but if INSN is a branch, take into account the
6521 worst-case delay for the branch target. */
6524 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6525 const struct mips_cl_insn
*insn
)
6529 nops
= nops_for_insn (ignore
, hist
, insn
);
6530 if (delayed_branch_p (insn
))
6532 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6533 hist
, insn
, get_delay_slot_nop (insn
));
6534 if (tmp_nops
> nops
)
6537 else if (compact_branch_p (insn
))
6539 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6540 if (tmp_nops
> nops
)
6546 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6549 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6551 gas_assert (!HAVE_CODE_COMPRESSION
);
6552 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6553 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6556 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6557 jr target pc &= 'hffff_ffff_cfff_ffff. */
6560 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6562 gas_assert (!HAVE_CODE_COMPRESSION
);
6563 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6564 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6565 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6573 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6574 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6577 ep
.X_op
= O_constant
;
6578 ep
.X_add_number
= 0xcfff0000;
6579 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6580 ep
.X_add_number
= 0xffff;
6581 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6582 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6587 fix_loongson2f (struct mips_cl_insn
* ip
)
6589 if (mips_fix_loongson2f_nop
)
6590 fix_loongson2f_nop (ip
);
6592 if (mips_fix_loongson2f_jump
)
6593 fix_loongson2f_jump (ip
);
6596 /* IP is a branch that has a delay slot, and we need to fill it
6597 automatically. Return true if we can do that by swapping IP
6598 with the previous instruction.
6599 ADDRESS_EXPR is an operand of the instruction to be used with
6603 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6604 bfd_reloc_code_real_type
*reloc_type
)
6606 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6607 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6608 unsigned int fpr_read
, prev_fpr_write
;
6610 /* -O2 and above is required for this optimization. */
6611 if (mips_optimize
< 2)
6614 /* If we have seen .set volatile or .set nomove, don't optimize. */
6615 if (mips_opts
.nomove
)
6618 /* We can't swap if the previous instruction's position is fixed. */
6619 if (history
[0].fixed_p
)
6622 /* If the previous previous insn was in a .set noreorder, we can't
6623 swap. Actually, the MIPS assembler will swap in this situation.
6624 However, gcc configured -with-gnu-as will generate code like
6632 in which we can not swap the bne and INSN. If gcc is not configured
6633 -with-gnu-as, it does not output the .set pseudo-ops. */
6634 if (history
[1].noreorder_p
)
6637 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6638 This means that the previous instruction was a 4-byte one anyhow. */
6639 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6642 /* If the branch is itself the target of a branch, we can not swap.
6643 We cheat on this; all we check for is whether there is a label on
6644 this instruction. If there are any branches to anything other than
6645 a label, users must use .set noreorder. */
6646 if (seg_info (now_seg
)->label_list
)
6649 /* If the previous instruction is in a variant frag other than this
6650 branch's one, we cannot do the swap. This does not apply to
6651 MIPS16 code, which uses variant frags for different purposes. */
6652 if (!mips_opts
.mips16
6654 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6657 /* We do not swap with instructions that cannot architecturally
6658 be placed in a branch delay slot, such as SYNC or ERET. We
6659 also refrain from swapping with a trap instruction, since it
6660 complicates trap handlers to have the trap instruction be in
6662 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6663 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6666 /* Check for conflicts between the branch and the instructions
6667 before the candidate delay slot. */
6668 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6671 /* Check for conflicts between the swapped sequence and the
6672 target of the branch. */
6673 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6676 /* If the branch reads a register that the previous
6677 instruction sets, we can not swap. */
6678 gpr_read
= gpr_read_mask (ip
);
6679 prev_gpr_write
= gpr_write_mask (&history
[0]);
6680 if (gpr_read
& prev_gpr_write
)
6683 fpr_read
= fpr_read_mask (ip
);
6684 prev_fpr_write
= fpr_write_mask (&history
[0]);
6685 if (fpr_read
& prev_fpr_write
)
6688 /* If the branch writes a register that the previous
6689 instruction sets, we can not swap. */
6690 gpr_write
= gpr_write_mask (ip
);
6691 if (gpr_write
& prev_gpr_write
)
6694 /* If the branch writes a register that the previous
6695 instruction reads, we can not swap. */
6696 prev_gpr_read
= gpr_read_mask (&history
[0]);
6697 if (gpr_write
& prev_gpr_read
)
6700 /* If one instruction sets a condition code and the
6701 other one uses a condition code, we can not swap. */
6702 pinfo
= ip
->insn_mo
->pinfo
;
6703 if ((pinfo
& INSN_READ_COND_CODE
)
6704 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6706 if ((pinfo
& INSN_WRITE_COND_CODE
)
6707 && (prev_pinfo
& INSN_READ_COND_CODE
))
6710 /* If the previous instruction uses the PC, we can not swap. */
6711 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6712 if (prev_pinfo2
& INSN2_READ_PC
)
6715 /* If the previous instruction has an incorrect size for a fixed
6716 branch delay slot in microMIPS mode, we cannot swap. */
6717 pinfo2
= ip
->insn_mo
->pinfo2
;
6718 if (mips_opts
.micromips
6719 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6720 && insn_length (history
) != 2)
6722 if (mips_opts
.micromips
6723 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6724 && insn_length (history
) != 4)
6727 /* On R5900 short loops need to be fixed by inserting a nop in
6728 the branch delay slots.
6729 A short loop can be terminated too early. */
6730 if (mips_opts
.arch
== CPU_R5900
6731 /* Check if instruction has a parameter, ignore "j $31". */
6732 && (address_expr
!= NULL
)
6733 /* Parameter must be 16 bit. */
6734 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6735 /* Branch to same segment. */
6736 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6737 /* Branch to same code fragment. */
6738 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6739 /* Can only calculate branch offset if value is known. */
6740 && symbol_constant_p(address_expr
->X_add_symbol
)
6741 /* Check if branch is really conditional. */
6742 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6743 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6744 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6747 /* Check if loop is shorter than 6 instructions including
6748 branch and delay slot. */
6749 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6756 /* When the loop includes branches or jumps,
6757 it is not a short loop. */
6758 for (i
= 0; i
< (distance
/ 4); i
++)
6760 if ((history
[i
].cleared_p
)
6761 || delayed_branch_p(&history
[i
]))
6769 /* Insert nop after branch to fix short loop. */
6778 /* Decide how we should add IP to the instruction stream.
6779 ADDRESS_EXPR is an operand of the instruction to be used with
6782 static enum append_method
6783 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6784 bfd_reloc_code_real_type
*reloc_type
)
6786 /* The relaxed version of a macro sequence must be inherently
6788 if (mips_relax
.sequence
== 2)
6791 /* We must not dabble with instructions in a ".set norerorder" block. */
6792 if (mips_opts
.noreorder
)
6795 /* Otherwise, it's our responsibility to fill branch delay slots. */
6796 if (delayed_branch_p (ip
))
6798 if (!branch_likely_p (ip
)
6799 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6802 if (mips_opts
.mips16
6803 && ISA_SUPPORTS_MIPS16E
6804 && gpr_read_mask (ip
) != 0)
6805 return APPEND_ADD_COMPACT
;
6807 return APPEND_ADD_WITH_NOP
;
6813 /* IP is a MIPS16 instruction whose opcode we have just changed.
6814 Point IP->insn_mo to the new opcode's definition. */
6817 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6819 const struct mips_opcode
*mo
, *end
;
6821 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6822 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6823 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6831 /* For microMIPS macros, we need to generate a local number label
6832 as the target of branches. */
6833 #define MICROMIPS_LABEL_CHAR '\037'
6834 static unsigned long micromips_target_label
;
6835 static char micromips_target_name
[32];
6838 micromips_label_name (void)
6840 char *p
= micromips_target_name
;
6841 char symbol_name_temporary
[24];
6849 l
= micromips_target_label
;
6850 #ifdef LOCAL_LABEL_PREFIX
6851 *p
++ = LOCAL_LABEL_PREFIX
;
6854 *p
++ = MICROMIPS_LABEL_CHAR
;
6857 symbol_name_temporary
[i
++] = l
% 10 + '0';
6862 *p
++ = symbol_name_temporary
[--i
];
6865 return micromips_target_name
;
6869 micromips_label_expr (expressionS
*label_expr
)
6871 label_expr
->X_op
= O_symbol
;
6872 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6873 label_expr
->X_add_number
= 0;
6877 micromips_label_inc (void)
6879 micromips_target_label
++;
6880 *micromips_target_name
= '\0';
6884 micromips_add_label (void)
6888 s
= colon (micromips_label_name ());
6889 micromips_label_inc ();
6890 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6893 /* If assembling microMIPS code, then return the microMIPS reloc
6894 corresponding to the requested one if any. Otherwise return
6895 the reloc unchanged. */
6897 static bfd_reloc_code_real_type
6898 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6900 static const bfd_reloc_code_real_type relocs
[][2] =
6902 /* Keep sorted incrementally by the left-hand key. */
6903 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6904 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6905 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6906 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6907 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6908 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6909 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6910 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6911 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6912 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6913 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6914 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6915 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6916 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6917 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6918 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6919 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6920 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6921 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6922 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6923 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6924 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6925 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6926 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6927 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6928 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6929 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6931 bfd_reloc_code_real_type r
;
6934 if (!mips_opts
.micromips
)
6936 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6942 return relocs
[i
][1];
6947 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6948 Return true on success, storing the resolved value in RESULT. */
6951 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6956 case BFD_RELOC_MIPS_HIGHEST
:
6957 case BFD_RELOC_MICROMIPS_HIGHEST
:
6958 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6961 case BFD_RELOC_MIPS_HIGHER
:
6962 case BFD_RELOC_MICROMIPS_HIGHER
:
6963 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6966 case BFD_RELOC_HI16_S
:
6967 case BFD_RELOC_MICROMIPS_HI16_S
:
6968 case BFD_RELOC_MIPS16_HI16_S
:
6969 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6972 case BFD_RELOC_HI16
:
6973 case BFD_RELOC_MICROMIPS_HI16
:
6974 case BFD_RELOC_MIPS16_HI16
:
6975 *result
= (operand
>> 16) & 0xffff;
6978 case BFD_RELOC_LO16
:
6979 case BFD_RELOC_MICROMIPS_LO16
:
6980 case BFD_RELOC_MIPS16_LO16
:
6981 *result
= operand
& 0xffff;
6984 case BFD_RELOC_UNUSED
:
6993 /* Output an instruction. IP is the instruction information.
6994 ADDRESS_EXPR is an operand of the instruction to be used with
6995 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6996 a macro expansion. */
6999 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7000 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7002 unsigned long prev_pinfo2
, pinfo
;
7003 bfd_boolean relaxed_branch
= FALSE
;
7004 enum append_method method
;
7005 bfd_boolean relax32
;
7008 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7009 fix_loongson2f (ip
);
7011 file_ase_mips16
|= mips_opts
.mips16
;
7012 file_ase_micromips
|= mips_opts
.micromips
;
7014 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7015 pinfo
= ip
->insn_mo
->pinfo
;
7017 if (mips_opts
.micromips
7019 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7020 && micromips_insn_length (ip
->insn_mo
) != 2)
7021 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7022 && micromips_insn_length (ip
->insn_mo
) != 4)))
7023 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7024 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7026 if (address_expr
== NULL
)
7028 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7029 && reloc_type
[1] == BFD_RELOC_UNUSED
7030 && reloc_type
[2] == BFD_RELOC_UNUSED
7031 && address_expr
->X_op
== O_constant
)
7033 switch (*reloc_type
)
7035 case BFD_RELOC_MIPS_JMP
:
7039 shift
= mips_opts
.micromips
? 1 : 2;
7040 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7041 as_bad (_("jump to misaligned address (0x%lx)"),
7042 (unsigned long) address_expr
->X_add_number
);
7043 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7049 case BFD_RELOC_MIPS16_JMP
:
7050 if ((address_expr
->X_add_number
& 3) != 0)
7051 as_bad (_("jump to misaligned address (0x%lx)"),
7052 (unsigned long) address_expr
->X_add_number
);
7054 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7055 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7056 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7060 case BFD_RELOC_16_PCREL_S2
:
7064 shift
= mips_opts
.micromips
? 1 : 2;
7065 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7066 as_bad (_("branch to misaligned address (0x%lx)"),
7067 (unsigned long) address_expr
->X_add_number
);
7068 if (!mips_relax_branch
)
7070 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7071 & ~((1 << (shift
+ 16)) - 1))
7072 as_bad (_("branch address range overflow (0x%lx)"),
7073 (unsigned long) address_expr
->X_add_number
);
7074 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7080 case BFD_RELOC_MIPS_21_PCREL_S2
:
7085 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7086 as_bad (_("branch to misaligned address (0x%lx)"),
7087 (unsigned long) address_expr
->X_add_number
);
7088 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7089 & ~((1 << (shift
+ 21)) - 1))
7090 as_bad (_("branch address range overflow (0x%lx)"),
7091 (unsigned long) address_expr
->X_add_number
);
7092 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7097 case BFD_RELOC_MIPS_26_PCREL_S2
:
7102 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7103 as_bad (_("branch to misaligned address (0x%lx)"),
7104 (unsigned long) address_expr
->X_add_number
);
7105 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7106 & ~((1 << (shift
+ 26)) - 1))
7107 as_bad (_("branch address range overflow (0x%lx)"),
7108 (unsigned long) address_expr
->X_add_number
);
7109 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7118 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7121 ip
->insn_opcode
|= value
& 0xffff;
7129 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7131 /* There are a lot of optimizations we could do that we don't.
7132 In particular, we do not, in general, reorder instructions.
7133 If you use gcc with optimization, it will reorder
7134 instructions and generally do much more optimization then we
7135 do here; repeating all that work in the assembler would only
7136 benefit hand written assembly code, and does not seem worth
7138 int nops
= (mips_optimize
== 0
7139 ? nops_for_insn (0, history
, NULL
)
7140 : nops_for_insn_or_target (0, history
, ip
));
7144 unsigned long old_frag_offset
;
7147 old_frag
= frag_now
;
7148 old_frag_offset
= frag_now_fix ();
7150 for (i
= 0; i
< nops
; i
++)
7151 add_fixed_insn (NOP_INSN
);
7152 insert_into_history (0, nops
, NOP_INSN
);
7156 listing_prev_line ();
7157 /* We may be at the start of a variant frag. In case we
7158 are, make sure there is enough space for the frag
7159 after the frags created by listing_prev_line. The
7160 argument to frag_grow here must be at least as large
7161 as the argument to all other calls to frag_grow in
7162 this file. We don't have to worry about being in the
7163 middle of a variant frag, because the variants insert
7164 all needed nop instructions themselves. */
7168 mips_move_text_labels ();
7170 #ifndef NO_ECOFF_DEBUGGING
7171 if (ECOFF_DEBUGGING
)
7172 ecoff_fix_loc (old_frag
, old_frag_offset
);
7176 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7180 /* Work out how many nops in prev_nop_frag are needed by IP,
7181 ignoring hazards generated by the first prev_nop_frag_since
7183 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7184 gas_assert (nops
<= prev_nop_frag_holds
);
7186 /* Enforce NOPS as a minimum. */
7187 if (nops
> prev_nop_frag_required
)
7188 prev_nop_frag_required
= nops
;
7190 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7192 /* Settle for the current number of nops. Update the history
7193 accordingly (for the benefit of any future .set reorder code). */
7194 prev_nop_frag
= NULL
;
7195 insert_into_history (prev_nop_frag_since
,
7196 prev_nop_frag_holds
, NOP_INSN
);
7200 /* Allow this instruction to replace one of the nops that was
7201 tentatively added to prev_nop_frag. */
7202 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7203 prev_nop_frag_holds
--;
7204 prev_nop_frag_since
++;
7208 method
= get_append_method (ip
, address_expr
, reloc_type
);
7209 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7211 dwarf2_emit_insn (0);
7212 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7213 so "move" the instruction address accordingly.
7215 Also, it doesn't seem appropriate for the assembler to reorder .loc
7216 entries. If this instruction is a branch that we are going to swap
7217 with the previous instruction, the two instructions should be
7218 treated as a unit, and the debug information for both instructions
7219 should refer to the start of the branch sequence. Using the
7220 current position is certainly wrong when swapping a 32-bit branch
7221 and a 16-bit delay slot, since the current position would then be
7222 in the middle of a branch. */
7223 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7225 relax32
= (mips_relax_branch
7226 /* Don't try branch relaxation within .set nomacro, or within
7227 .set noat if we use $at for PIC computations. If it turns
7228 out that the branch was out-of-range, we'll get an error. */
7229 && !mips_opts
.warn_about_macros
7230 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7231 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7232 as they have no complementing branches. */
7233 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7235 if (!HAVE_CODE_COMPRESSION
7238 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7239 && delayed_branch_p (ip
))
7241 relaxed_branch
= TRUE
;
7242 add_relaxed_insn (ip
, (relaxed_branch_length
7244 uncond_branch_p (ip
) ? -1
7245 : branch_likely_p (ip
) ? 1
7249 uncond_branch_p (ip
),
7250 branch_likely_p (ip
),
7251 pinfo
& INSN_WRITE_GPR_31
,
7253 address_expr
->X_add_symbol
,
7254 address_expr
->X_add_number
);
7255 *reloc_type
= BFD_RELOC_UNUSED
;
7257 else if (mips_opts
.micromips
7259 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7260 || *reloc_type
> BFD_RELOC_UNUSED
)
7261 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7262 /* Don't try branch relaxation when users specify
7263 16-bit/32-bit instructions. */
7264 && !forced_insn_length
)
7266 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
7267 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7268 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7269 int compact
= compact_branch_p (ip
);
7270 int al
= pinfo
& INSN_WRITE_GPR_31
;
7273 gas_assert (address_expr
!= NULL
);
7274 gas_assert (!mips_relax
.sequence
);
7276 relaxed_branch
= TRUE
;
7277 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7278 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
7279 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
7281 address_expr
->X_add_symbol
,
7282 address_expr
->X_add_number
);
7283 *reloc_type
= BFD_RELOC_UNUSED
;
7285 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7287 /* We need to set up a variant frag. */
7288 gas_assert (address_expr
!= NULL
);
7289 add_relaxed_insn (ip
, 4, 0,
7291 (*reloc_type
- BFD_RELOC_UNUSED
,
7292 forced_insn_length
== 2, forced_insn_length
== 4,
7293 delayed_branch_p (&history
[0]),
7294 history
[0].mips16_absolute_jump_p
),
7295 make_expr_symbol (address_expr
), 0);
7297 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7299 if (!delayed_branch_p (ip
))
7300 /* Make sure there is enough room to swap this instruction with
7301 a following jump instruction. */
7303 add_fixed_insn (ip
);
7307 if (mips_opts
.mips16
7308 && mips_opts
.noreorder
7309 && delayed_branch_p (&history
[0]))
7310 as_warn (_("extended instruction in delay slot"));
7312 if (mips_relax
.sequence
)
7314 /* If we've reached the end of this frag, turn it into a variant
7315 frag and record the information for the instructions we've
7317 if (frag_room () < 4)
7318 relax_close_frag ();
7319 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7322 if (mips_relax
.sequence
!= 2)
7324 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7325 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7326 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7327 mips_macro_warning
.insns
[0]++;
7329 if (mips_relax
.sequence
!= 1)
7331 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7332 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7333 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7334 mips_macro_warning
.insns
[1]++;
7337 if (mips_opts
.mips16
)
7340 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7342 add_fixed_insn (ip
);
7345 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7347 bfd_reloc_code_real_type final_type
[3];
7348 reloc_howto_type
*howto0
;
7349 reloc_howto_type
*howto
;
7352 /* Perform any necessary conversion to microMIPS relocations
7353 and find out how many relocations there actually are. */
7354 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7355 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7357 /* In a compound relocation, it is the final (outermost)
7358 operator that determines the relocated field. */
7359 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7364 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7365 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7366 bfd_get_reloc_size (howto
),
7368 howto0
&& howto0
->pc_relative
,
7371 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7372 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7373 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7375 /* These relocations can have an addend that won't fit in
7376 4 octets for 64bit assembly. */
7378 && ! howto
->partial_inplace
7379 && (reloc_type
[0] == BFD_RELOC_16
7380 || reloc_type
[0] == BFD_RELOC_32
7381 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7382 || reloc_type
[0] == BFD_RELOC_GPREL16
7383 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7384 || reloc_type
[0] == BFD_RELOC_GPREL32
7385 || reloc_type
[0] == BFD_RELOC_64
7386 || reloc_type
[0] == BFD_RELOC_CTOR
7387 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7388 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7389 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7390 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7391 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7392 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7393 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7394 || hi16_reloc_p (reloc_type
[0])
7395 || lo16_reloc_p (reloc_type
[0])))
7396 ip
->fixp
[0]->fx_no_overflow
= 1;
7398 /* These relocations can have an addend that won't fit in 2 octets. */
7399 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7400 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7401 ip
->fixp
[0]->fx_no_overflow
= 1;
7403 if (mips_relax
.sequence
)
7405 if (mips_relax
.first_fixup
== 0)
7406 mips_relax
.first_fixup
= ip
->fixp
[0];
7408 else if (reloc_needs_lo_p (*reloc_type
))
7410 struct mips_hi_fixup
*hi_fixup
;
7412 /* Reuse the last entry if it already has a matching %lo. */
7413 hi_fixup
= mips_hi_fixup_list
;
7415 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7417 hi_fixup
= ((struct mips_hi_fixup
*)
7418 xmalloc (sizeof (struct mips_hi_fixup
)));
7419 hi_fixup
->next
= mips_hi_fixup_list
;
7420 mips_hi_fixup_list
= hi_fixup
;
7422 hi_fixup
->fixp
= ip
->fixp
[0];
7423 hi_fixup
->seg
= now_seg
;
7426 /* Add fixups for the second and third relocations, if given.
7427 Note that the ABI allows the second relocation to be
7428 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7429 moment we only use RSS_UNDEF, but we could add support
7430 for the others if it ever becomes necessary. */
7431 for (i
= 1; i
< 3; i
++)
7432 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7434 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7435 ip
->fixp
[0]->fx_size
, NULL
, 0,
7436 FALSE
, final_type
[i
]);
7438 /* Use fx_tcbit to mark compound relocs. */
7439 ip
->fixp
[0]->fx_tcbit
= 1;
7440 ip
->fixp
[i
]->fx_tcbit
= 1;
7445 /* Update the register mask information. */
7446 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7447 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7452 insert_into_history (0, 1, ip
);
7455 case APPEND_ADD_WITH_NOP
:
7457 struct mips_cl_insn
*nop
;
7459 insert_into_history (0, 1, ip
);
7460 nop
= get_delay_slot_nop (ip
);
7461 add_fixed_insn (nop
);
7462 insert_into_history (0, 1, nop
);
7463 if (mips_relax
.sequence
)
7464 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7468 case APPEND_ADD_COMPACT
:
7469 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7470 gas_assert (mips_opts
.mips16
);
7471 ip
->insn_opcode
|= 0x0080;
7472 find_altered_mips16_opcode (ip
);
7474 insert_into_history (0, 1, ip
);
7479 struct mips_cl_insn delay
= history
[0];
7480 if (mips_opts
.mips16
)
7482 know (delay
.frag
== ip
->frag
);
7483 move_insn (ip
, delay
.frag
, delay
.where
);
7484 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7486 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7488 /* Add the delay slot instruction to the end of the
7489 current frag and shrink the fixed part of the
7490 original frag. If the branch occupies the tail of
7491 the latter, move it backwards to cover the gap. */
7492 delay
.frag
->fr_fix
-= branch_disp
;
7493 if (delay
.frag
== ip
->frag
)
7494 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7495 add_fixed_insn (&delay
);
7499 move_insn (&delay
, ip
->frag
,
7500 ip
->where
- branch_disp
+ insn_length (ip
));
7501 move_insn (ip
, history
[0].frag
, history
[0].where
);
7505 insert_into_history (0, 1, &delay
);
7510 /* If we have just completed an unconditional branch, clear the history. */
7511 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7512 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7516 mips_no_prev_insn ();
7518 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7519 history
[i
].cleared_p
= 1;
7522 /* We need to emit a label at the end of branch-likely macros. */
7523 if (emit_branch_likely_macro
)
7525 emit_branch_likely_macro
= FALSE
;
7526 micromips_add_label ();
7529 /* We just output an insn, so the next one doesn't have a label. */
7530 mips_clear_insn_labels ();
7533 /* Forget that there was any previous instruction or label.
7534 When BRANCH is true, the branch history is also flushed. */
7537 mips_no_prev_insn (void)
7539 prev_nop_frag
= NULL
;
7540 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7541 mips_clear_insn_labels ();
7544 /* This function must be called before we emit something other than
7545 instructions. It is like mips_no_prev_insn except that it inserts
7546 any NOPS that might be needed by previous instructions. */
7549 mips_emit_delays (void)
7551 if (! mips_opts
.noreorder
)
7553 int nops
= nops_for_insn (0, history
, NULL
);
7557 add_fixed_insn (NOP_INSN
);
7558 mips_move_text_labels ();
7561 mips_no_prev_insn ();
7564 /* Start a (possibly nested) noreorder block. */
7567 start_noreorder (void)
7569 if (mips_opts
.noreorder
== 0)
7574 /* None of the instructions before the .set noreorder can be moved. */
7575 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7576 history
[i
].fixed_p
= 1;
7578 /* Insert any nops that might be needed between the .set noreorder
7579 block and the previous instructions. We will later remove any
7580 nops that turn out not to be needed. */
7581 nops
= nops_for_insn (0, history
, NULL
);
7584 if (mips_optimize
!= 0)
7586 /* Record the frag which holds the nop instructions, so
7587 that we can remove them if we don't need them. */
7588 frag_grow (nops
* NOP_INSN_SIZE
);
7589 prev_nop_frag
= frag_now
;
7590 prev_nop_frag_holds
= nops
;
7591 prev_nop_frag_required
= 0;
7592 prev_nop_frag_since
= 0;
7595 for (; nops
> 0; --nops
)
7596 add_fixed_insn (NOP_INSN
);
7598 /* Move on to a new frag, so that it is safe to simply
7599 decrease the size of prev_nop_frag. */
7600 frag_wane (frag_now
);
7602 mips_move_text_labels ();
7604 mips_mark_labels ();
7605 mips_clear_insn_labels ();
7607 mips_opts
.noreorder
++;
7608 mips_any_noreorder
= 1;
7611 /* End a nested noreorder block. */
7614 end_noreorder (void)
7616 mips_opts
.noreorder
--;
7617 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7619 /* Commit to inserting prev_nop_frag_required nops and go back to
7620 handling nop insertion the .set reorder way. */
7621 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7623 insert_into_history (prev_nop_frag_since
,
7624 prev_nop_frag_required
, NOP_INSN
);
7625 prev_nop_frag
= NULL
;
7629 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7630 higher bits unset. */
7633 normalize_constant_expr (expressionS
*ex
)
7635 if (ex
->X_op
== O_constant
7636 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7637 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7641 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7642 all higher bits unset. */
7645 normalize_address_expr (expressionS
*ex
)
7647 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7648 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7649 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7650 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7654 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7655 Return true if the match was successful.
7657 OPCODE_EXTRA is a value that should be ORed into the opcode
7658 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7659 there are more alternatives after OPCODE and SOFT_MATCH is
7660 as for mips_arg_info. */
7663 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7664 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7665 bfd_boolean lax_match
, bfd_boolean complete_p
)
7668 struct mips_arg_info arg
;
7669 const struct mips_operand
*operand
;
7672 imm_expr
.X_op
= O_absent
;
7673 offset_expr
.X_op
= O_absent
;
7674 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7675 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7676 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7678 create_insn (insn
, opcode
);
7679 /* When no opcode suffix is specified, assume ".xyzw". */
7680 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7681 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7683 insn
->insn_opcode
|= opcode_extra
;
7684 memset (&arg
, 0, sizeof (arg
));
7688 arg
.last_regno
= ILLEGAL_REG
;
7689 arg
.dest_regno
= ILLEGAL_REG
;
7690 arg
.lax_match
= lax_match
;
7691 for (args
= opcode
->args
;; ++args
)
7693 if (arg
.token
->type
== OT_END
)
7695 /* Handle unary instructions in which only one operand is given.
7696 The source is then the same as the destination. */
7697 if (arg
.opnum
== 1 && *args
== ',')
7699 operand
= (mips_opts
.micromips
7700 ? decode_micromips_operand (args
+ 1)
7701 : decode_mips_operand (args
+ 1));
7702 if (operand
&& mips_optional_operand_p (operand
))
7710 /* Treat elided base registers as $0. */
7711 if (strcmp (args
, "(b)") == 0)
7719 /* The register suffix is optional. */
7724 /* Fail the match if there were too few operands. */
7728 /* Successful match. */
7731 clear_insn_error ();
7732 if (arg
.dest_regno
== arg
.last_regno
7733 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7737 (0, _("source and destination must be different"));
7738 else if (arg
.last_regno
== 31)
7740 (0, _("a destination register must be supplied"));
7742 else if (arg
.last_regno
== 31
7743 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7744 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7745 set_insn_error (0, _("the source register must not be $31"));
7746 check_completed_insn (&arg
);
7750 /* Fail the match if the line has too many operands. */
7754 /* Handle characters that need to match exactly. */
7755 if (*args
== '(' || *args
== ')' || *args
== ',')
7757 if (match_char (&arg
, *args
))
7764 if (arg
.token
->type
== OT_DOUBLE_CHAR
7765 && arg
.token
->u
.ch
== *args
)
7773 /* Handle special macro operands. Work out the properties of
7782 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7786 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7795 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7799 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
7803 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
7809 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7811 imm_expr
.X_op
= O_constant
;
7813 normalize_constant_expr (&imm_expr
);
7817 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7819 /* Assume that the offset has been elided and that what
7820 we saw was a base register. The match will fail later
7821 if that assumption turns out to be wrong. */
7822 offset_expr
.X_op
= O_constant
;
7823 offset_expr
.X_add_number
= 0;
7827 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7829 normalize_address_expr (&offset_expr
);
7834 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7840 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7846 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7852 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7858 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7862 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7866 gas_assert (mips_opts
.micromips
);
7872 if (!forced_insn_length
)
7873 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7875 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7877 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7883 operand
= (mips_opts
.micromips
7884 ? decode_micromips_operand (args
)
7885 : decode_mips_operand (args
));
7889 /* Skip prefixes. */
7890 if (*args
== '+' || *args
== 'm' || *args
== '-')
7893 if (mips_optional_operand_p (operand
)
7895 && (arg
.token
[0].type
!= OT_REG
7896 || arg
.token
[1].type
== OT_END
))
7898 /* Assume that the register has been elided and is the
7899 same as the first operand. */
7904 if (!match_operand (&arg
, operand
))
7909 /* Like match_insn, but for MIPS16. */
7912 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7913 struct mips_operand_token
*tokens
)
7916 const struct mips_operand
*operand
;
7917 const struct mips_operand
*ext_operand
;
7918 struct mips_arg_info arg
;
7921 create_insn (insn
, opcode
);
7922 imm_expr
.X_op
= O_absent
;
7923 offset_expr
.X_op
= O_absent
;
7924 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7925 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7926 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7929 memset (&arg
, 0, sizeof (arg
));
7933 arg
.last_regno
= ILLEGAL_REG
;
7934 arg
.dest_regno
= ILLEGAL_REG
;
7936 for (args
= opcode
->args
;; ++args
)
7940 if (arg
.token
->type
== OT_END
)
7944 /* Handle unary instructions in which only one operand is given.
7945 The source is then the same as the destination. */
7946 if (arg
.opnum
== 1 && *args
== ',')
7948 operand
= decode_mips16_operand (args
[1], FALSE
);
7949 if (operand
&& mips_optional_operand_p (operand
))
7957 /* Fail the match if there were too few operands. */
7961 /* Successful match. Stuff the immediate value in now, if
7963 clear_insn_error ();
7964 if (opcode
->pinfo
== INSN_MACRO
)
7966 gas_assert (relax_char
== 0 || relax_char
== 'p');
7967 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7970 && offset_expr
.X_op
== O_constant
7971 && calculate_reloc (*offset_reloc
,
7972 offset_expr
.X_add_number
,
7975 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7976 forced_insn_length
, &insn
->insn_opcode
);
7977 offset_expr
.X_op
= O_absent
;
7978 *offset_reloc
= BFD_RELOC_UNUSED
;
7980 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7982 if (forced_insn_length
== 2)
7983 set_insn_error (0, _("invalid unextended operand value"));
7984 forced_insn_length
= 4;
7985 insn
->insn_opcode
|= MIPS16_EXTEND
;
7987 else if (relax_char
)
7988 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7990 check_completed_insn (&arg
);
7994 /* Fail the match if the line has too many operands. */
7998 /* Handle characters that need to match exactly. */
7999 if (*args
== '(' || *args
== ')' || *args
== ',')
8001 if (match_char (&arg
, *args
))
8019 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8021 imm_expr
.X_op
= O_constant
;
8023 normalize_constant_expr (&imm_expr
);
8028 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8029 insn
->insn_opcode
<<= 16;
8033 operand
= decode_mips16_operand (c
, FALSE
);
8037 /* '6' is a special case. It is used for BREAK and SDBBP,
8038 whose operands are only meaningful to the software that decodes
8039 them. This means that there is no architectural reason why
8040 they cannot be prefixed by EXTEND, but in practice,
8041 exception handlers will only look at the instruction
8042 itself. We therefore allow '6' to be extended when
8043 disassembling but not when assembling. */
8044 if (operand
->type
!= OP_PCREL
&& c
!= '6')
8046 ext_operand
= decode_mips16_operand (c
, TRUE
);
8047 if (operand
!= ext_operand
)
8049 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8051 offset_expr
.X_op
= O_constant
;
8052 offset_expr
.X_add_number
= 0;
8057 /* We need the OT_INTEGER check because some MIPS16
8058 immediate variants are listed before the register ones. */
8059 if (arg
.token
->type
!= OT_INTEGER
8060 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
8063 /* '8' is used for SLTI(U) and has traditionally not
8064 been allowed to take relocation operators. */
8065 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8066 && (ext_operand
->size
!= 16 || c
== '8'))
8074 if (mips_optional_operand_p (operand
)
8076 && (arg
.token
[0].type
!= OT_REG
8077 || arg
.token
[1].type
== OT_END
))
8079 /* Assume that the register has been elided and is the
8080 same as the first operand. */
8085 if (!match_operand (&arg
, operand
))
8090 /* Record that the current instruction is invalid for the current ISA. */
8093 match_invalid_for_isa (void)
8096 (0, _("opcode not supported on this processor: %s (%s)"),
8097 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8098 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8101 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8102 Return true if a definite match or failure was found, storing any match
8103 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8104 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8105 tried and failed to match under normal conditions and now want to try a
8106 more relaxed match. */
8109 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8110 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8111 int opcode_extra
, bfd_boolean lax_match
)
8113 const struct mips_opcode
*opcode
;
8114 const struct mips_opcode
*invalid_delay_slot
;
8115 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8117 /* Search for a match, ignoring alternatives that don't satisfy the
8118 current ISA or forced_length. */
8119 invalid_delay_slot
= 0;
8120 seen_valid_for_isa
= FALSE
;
8121 seen_valid_for_size
= FALSE
;
8125 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8126 if (is_opcode_valid (opcode
))
8128 seen_valid_for_isa
= TRUE
;
8129 if (is_size_valid (opcode
))
8131 bfd_boolean delay_slot_ok
;
8133 seen_valid_for_size
= TRUE
;
8134 delay_slot_ok
= is_delay_slot_valid (opcode
);
8135 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8136 lax_match
, delay_slot_ok
))
8140 if (!invalid_delay_slot
)
8141 invalid_delay_slot
= opcode
;
8150 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8152 /* If the only matches we found had the wrong length for the delay slot,
8153 pick the first such match. We'll issue an appropriate warning later. */
8154 if (invalid_delay_slot
)
8156 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8162 /* Handle the case where we didn't try to match an instruction because
8163 all the alternatives were incompatible with the current ISA. */
8164 if (!seen_valid_for_isa
)
8166 match_invalid_for_isa ();
8170 /* Handle the case where we didn't try to match an instruction because
8171 all the alternatives were of the wrong size. */
8172 if (!seen_valid_for_size
)
8174 if (mips_opts
.insn32
)
8175 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8178 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8179 8 * forced_insn_length
);
8186 /* Like match_insns, but for MIPS16. */
8189 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8190 struct mips_operand_token
*tokens
)
8192 const struct mips_opcode
*opcode
;
8193 bfd_boolean seen_valid_for_isa
;
8195 /* Search for a match, ignoring alternatives that don't satisfy the
8196 current ISA. There are no separate entries for extended forms so
8197 we deal with forced_length later. */
8198 seen_valid_for_isa
= FALSE
;
8202 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8203 if (is_opcode_valid_16 (opcode
))
8205 seen_valid_for_isa
= TRUE
;
8206 if (match_mips16_insn (insn
, opcode
, tokens
))
8211 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8212 && strcmp (opcode
->name
, first
->name
) == 0);
8214 /* Handle the case where we didn't try to match an instruction because
8215 all the alternatives were incompatible with the current ISA. */
8216 if (!seen_valid_for_isa
)
8218 match_invalid_for_isa ();
8225 /* Set up global variables for the start of a new macro. */
8230 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8231 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8232 sizeof (mips_macro_warning
.first_insn_sizes
));
8233 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8234 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8235 && delayed_branch_p (&history
[0]));
8236 switch (history
[0].insn_mo
->pinfo2
8237 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8239 case INSN2_BRANCH_DELAY_32BIT
:
8240 mips_macro_warning
.delay_slot_length
= 4;
8242 case INSN2_BRANCH_DELAY_16BIT
:
8243 mips_macro_warning
.delay_slot_length
= 2;
8246 mips_macro_warning
.delay_slot_length
= 0;
8249 mips_macro_warning
.first_frag
= NULL
;
8252 /* Given that a macro is longer than one instruction or of the wrong size,
8253 return the appropriate warning for it. Return null if no warning is
8254 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8255 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8256 and RELAX_NOMACRO. */
8259 macro_warning (relax_substateT subtype
)
8261 if (subtype
& RELAX_DELAY_SLOT
)
8262 return _("macro instruction expanded into multiple instructions"
8263 " in a branch delay slot");
8264 else if (subtype
& RELAX_NOMACRO
)
8265 return _("macro instruction expanded into multiple instructions");
8266 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8267 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8268 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8269 ? _("macro instruction expanded into a wrong size instruction"
8270 " in a 16-bit branch delay slot")
8271 : _("macro instruction expanded into a wrong size instruction"
8272 " in a 32-bit branch delay slot"));
8277 /* Finish up a macro. Emit warnings as appropriate. */
8282 /* Relaxation warning flags. */
8283 relax_substateT subtype
= 0;
8285 /* Check delay slot size requirements. */
8286 if (mips_macro_warning
.delay_slot_length
== 2)
8287 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8288 if (mips_macro_warning
.delay_slot_length
!= 0)
8290 if (mips_macro_warning
.delay_slot_length
8291 != mips_macro_warning
.first_insn_sizes
[0])
8292 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8293 if (mips_macro_warning
.delay_slot_length
8294 != mips_macro_warning
.first_insn_sizes
[1])
8295 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8298 /* Check instruction count requirements. */
8299 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8301 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8302 subtype
|= RELAX_SECOND_LONGER
;
8303 if (mips_opts
.warn_about_macros
)
8304 subtype
|= RELAX_NOMACRO
;
8305 if (mips_macro_warning
.delay_slot_p
)
8306 subtype
|= RELAX_DELAY_SLOT
;
8309 /* If both alternatives fail to fill a delay slot correctly,
8310 emit the warning now. */
8311 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8312 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8317 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8318 | RELAX_DELAY_SLOT_SIZE_FIRST
8319 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8320 msg
= macro_warning (s
);
8322 as_warn ("%s", msg
);
8326 /* If both implementations are longer than 1 instruction, then emit the
8328 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8333 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8334 msg
= macro_warning (s
);
8336 as_warn ("%s", msg
);
8340 /* If any flags still set, then one implementation might need a warning
8341 and the other either will need one of a different kind or none at all.
8342 Pass any remaining flags over to relaxation. */
8343 if (mips_macro_warning
.first_frag
!= NULL
)
8344 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8347 /* Instruction operand formats used in macros that vary between
8348 standard MIPS and microMIPS code. */
8350 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8351 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8352 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8353 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8354 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8355 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8356 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8357 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8359 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8360 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8361 : cop12_fmt[mips_opts.micromips])
8362 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8363 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8364 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8365 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8366 : mem12_fmt[mips_opts.micromips])
8367 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8368 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8369 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8371 /* Read a macro's relocation codes from *ARGS and store them in *R.
8372 The first argument in *ARGS will be either the code for a single
8373 relocation or -1 followed by the three codes that make up a
8374 composite relocation. */
8377 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8381 next
= va_arg (*args
, int);
8383 r
[0] = (bfd_reloc_code_real_type
) next
;
8386 for (i
= 0; i
< 3; i
++)
8387 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8388 /* This function is only used for 16-bit relocation fields.
8389 To make the macro code simpler, treat an unrelocated value
8390 in the same way as BFD_RELOC_LO16. */
8391 if (r
[0] == BFD_RELOC_UNUSED
)
8392 r
[0] = BFD_RELOC_LO16
;
8396 /* Build an instruction created by a macro expansion. This is passed
8397 a pointer to the count of instructions created so far, an
8398 expression, the name of the instruction to build, an operand format
8399 string, and corresponding arguments. */
8402 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8404 const struct mips_opcode
*mo
= NULL
;
8405 bfd_reloc_code_real_type r
[3];
8406 const struct mips_opcode
*amo
;
8407 const struct mips_operand
*operand
;
8408 struct hash_control
*hash
;
8409 struct mips_cl_insn insn
;
8413 va_start (args
, fmt
);
8415 if (mips_opts
.mips16
)
8417 mips16_macro_build (ep
, name
, fmt
, &args
);
8422 r
[0] = BFD_RELOC_UNUSED
;
8423 r
[1] = BFD_RELOC_UNUSED
;
8424 r
[2] = BFD_RELOC_UNUSED
;
8425 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8426 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8428 gas_assert (strcmp (name
, amo
->name
) == 0);
8432 /* Search until we get a match for NAME. It is assumed here that
8433 macros will never generate MDMX, MIPS-3D, or MT instructions.
8434 We try to match an instruction that fulfils the branch delay
8435 slot instruction length requirement (if any) of the previous
8436 instruction. While doing this we record the first instruction
8437 seen that matches all the other conditions and use it anyway
8438 if the requirement cannot be met; we will issue an appropriate
8439 warning later on. */
8440 if (strcmp (fmt
, amo
->args
) == 0
8441 && amo
->pinfo
!= INSN_MACRO
8442 && is_opcode_valid (amo
)
8443 && is_size_valid (amo
))
8445 if (is_delay_slot_valid (amo
))
8455 gas_assert (amo
->name
);
8457 while (strcmp (name
, amo
->name
) == 0);
8460 create_insn (&insn
, mo
);
8473 macro_read_relocs (&args
, r
);
8474 gas_assert (*r
== BFD_RELOC_GPREL16
8475 || *r
== BFD_RELOC_MIPS_HIGHER
8476 || *r
== BFD_RELOC_HI16_S
8477 || *r
== BFD_RELOC_LO16
8478 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8482 macro_read_relocs (&args
, r
);
8486 macro_read_relocs (&args
, r
);
8487 gas_assert (ep
!= NULL
8488 && (ep
->X_op
== O_constant
8489 || (ep
->X_op
== O_symbol
8490 && (*r
== BFD_RELOC_MIPS_HIGHEST
8491 || *r
== BFD_RELOC_HI16_S
8492 || *r
== BFD_RELOC_HI16
8493 || *r
== BFD_RELOC_GPREL16
8494 || *r
== BFD_RELOC_MIPS_GOT_HI16
8495 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8499 gas_assert (ep
!= NULL
);
8502 * This allows macro() to pass an immediate expression for
8503 * creating short branches without creating a symbol.
8505 * We don't allow branch relaxation for these branches, as
8506 * they should only appear in ".set nomacro" anyway.
8508 if (ep
->X_op
== O_constant
)
8510 /* For microMIPS we always use relocations for branches.
8511 So we should not resolve immediate values. */
8512 gas_assert (!mips_opts
.micromips
);
8514 if ((ep
->X_add_number
& 3) != 0)
8515 as_bad (_("branch to misaligned address (0x%lx)"),
8516 (unsigned long) ep
->X_add_number
);
8517 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8518 as_bad (_("branch address range overflow (0x%lx)"),
8519 (unsigned long) ep
->X_add_number
);
8520 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8524 *r
= BFD_RELOC_16_PCREL_S2
;
8528 gas_assert (ep
!= NULL
);
8529 *r
= BFD_RELOC_MIPS_JMP
;
8533 operand
= (mips_opts
.micromips
8534 ? decode_micromips_operand (fmt
)
8535 : decode_mips_operand (fmt
));
8539 uval
= va_arg (args
, int);
8540 if (operand
->type
== OP_CLO_CLZ_DEST
)
8541 uval
|= (uval
<< 5);
8542 insn_insert_operand (&insn
, operand
, uval
);
8544 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8550 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8552 append_insn (&insn
, ep
, r
, TRUE
);
8556 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8559 struct mips_opcode
*mo
;
8560 struct mips_cl_insn insn
;
8561 const struct mips_operand
*operand
;
8562 bfd_reloc_code_real_type r
[3]
8563 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8565 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8567 gas_assert (strcmp (name
, mo
->name
) == 0);
8569 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8572 gas_assert (mo
->name
);
8573 gas_assert (strcmp (name
, mo
->name
) == 0);
8576 create_insn (&insn
, mo
);
8614 gas_assert (ep
!= NULL
);
8616 if (ep
->X_op
!= O_constant
)
8617 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8618 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8620 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8622 *r
= BFD_RELOC_UNUSED
;
8628 operand
= decode_mips16_operand (c
, FALSE
);
8632 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8637 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8639 append_insn (&insn
, ep
, r
, TRUE
);
8643 * Generate a "jalr" instruction with a relocation hint to the called
8644 * function. This occurs in NewABI PIC code.
8647 macro_build_jalr (expressionS
*ep
, int cprestore
)
8649 static const bfd_reloc_code_real_type jalr_relocs
[2]
8650 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8651 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8655 if (MIPS_JALR_HINT_P (ep
))
8660 if (mips_opts
.micromips
)
8662 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8663 ? "jalr" : "jalrs");
8664 if (MIPS_JALR_HINT_P (ep
)
8666 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8667 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8669 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8672 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8673 if (MIPS_JALR_HINT_P (ep
))
8674 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8678 * Generate a "lui" instruction.
8681 macro_build_lui (expressionS
*ep
, int regnum
)
8683 gas_assert (! mips_opts
.mips16
);
8685 if (ep
->X_op
!= O_constant
)
8687 gas_assert (ep
->X_op
== O_symbol
);
8688 /* _gp_disp is a special case, used from s_cpload.
8689 __gnu_local_gp is used if mips_no_shared. */
8690 gas_assert (mips_pic
== NO_PIC
8692 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8693 || (! mips_in_shared
8694 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8695 "__gnu_local_gp") == 0));
8698 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8701 /* Generate a sequence of instructions to do a load or store from a constant
8702 offset off of a base register (breg) into/from a target register (treg),
8703 using AT if necessary. */
8705 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8706 int treg
, int breg
, int dbl
)
8708 gas_assert (ep
->X_op
== O_constant
);
8710 /* Sign-extending 32-bit constants makes their handling easier. */
8712 normalize_constant_expr (ep
);
8714 /* Right now, this routine can only handle signed 32-bit constants. */
8715 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8716 as_warn (_("operand overflow"));
8718 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8720 /* Signed 16-bit offset will fit in the op. Easy! */
8721 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8725 /* 32-bit offset, need multiple instructions and AT, like:
8726 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8727 addu $tempreg,$tempreg,$breg
8728 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8729 to handle the complete offset. */
8730 macro_build_lui (ep
, AT
);
8731 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8732 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8735 as_bad (_("macro used $at after \".set noat\""));
8740 * Generates code to set the $at register to true (one)
8741 * if reg is less than the immediate expression.
8744 set_at (int reg
, int unsignedp
)
8746 if (imm_expr
.X_add_number
>= -0x8000
8747 && imm_expr
.X_add_number
< 0x8000)
8748 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8749 AT
, reg
, BFD_RELOC_LO16
);
8752 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8753 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8757 /* Count the leading zeroes by performing a binary chop. This is a
8758 bulky bit of source, but performance is a LOT better for the
8759 majority of values than a simple loop to count the bits:
8760 for (lcnt = 0; (lcnt < 32); lcnt++)
8761 if ((v) & (1 << (31 - lcnt)))
8763 However it is not code size friendly, and the gain will drop a bit
8764 on certain cached systems.
8766 #define COUNT_TOP_ZEROES(v) \
8767 (((v) & ~0xffff) == 0 \
8768 ? ((v) & ~0xff) == 0 \
8769 ? ((v) & ~0xf) == 0 \
8770 ? ((v) & ~0x3) == 0 \
8771 ? ((v) & ~0x1) == 0 \
8776 : ((v) & ~0x7) == 0 \
8779 : ((v) & ~0x3f) == 0 \
8780 ? ((v) & ~0x1f) == 0 \
8783 : ((v) & ~0x7f) == 0 \
8786 : ((v) & ~0xfff) == 0 \
8787 ? ((v) & ~0x3ff) == 0 \
8788 ? ((v) & ~0x1ff) == 0 \
8791 : ((v) & ~0x7ff) == 0 \
8794 : ((v) & ~0x3fff) == 0 \
8795 ? ((v) & ~0x1fff) == 0 \
8798 : ((v) & ~0x7fff) == 0 \
8801 : ((v) & ~0xffffff) == 0 \
8802 ? ((v) & ~0xfffff) == 0 \
8803 ? ((v) & ~0x3ffff) == 0 \
8804 ? ((v) & ~0x1ffff) == 0 \
8807 : ((v) & ~0x7ffff) == 0 \
8810 : ((v) & ~0x3fffff) == 0 \
8811 ? ((v) & ~0x1fffff) == 0 \
8814 : ((v) & ~0x7fffff) == 0 \
8817 : ((v) & ~0xfffffff) == 0 \
8818 ? ((v) & ~0x3ffffff) == 0 \
8819 ? ((v) & ~0x1ffffff) == 0 \
8822 : ((v) & ~0x7ffffff) == 0 \
8825 : ((v) & ~0x3fffffff) == 0 \
8826 ? ((v) & ~0x1fffffff) == 0 \
8829 : ((v) & ~0x7fffffff) == 0 \
8834 * This routine generates the least number of instructions necessary to load
8835 * an absolute expression value into a register.
8838 load_register (int reg
, expressionS
*ep
, int dbl
)
8841 expressionS hi32
, lo32
;
8843 if (ep
->X_op
!= O_big
)
8845 gas_assert (ep
->X_op
== O_constant
);
8847 /* Sign-extending 32-bit constants makes their handling easier. */
8849 normalize_constant_expr (ep
);
8851 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8853 /* We can handle 16 bit signed values with an addiu to
8854 $zero. No need to ever use daddiu here, since $zero and
8855 the result are always correct in 32 bit mode. */
8856 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8859 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8861 /* We can handle 16 bit unsigned values with an ori to
8863 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8866 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8868 /* 32 bit values require an lui. */
8869 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8870 if ((ep
->X_add_number
& 0xffff) != 0)
8871 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8876 /* The value is larger than 32 bits. */
8878 if (!dbl
|| GPR_SIZE
== 32)
8882 sprintf_vma (value
, ep
->X_add_number
);
8883 as_bad (_("number (0x%s) larger than 32 bits"), value
);
8884 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8888 if (ep
->X_op
!= O_big
)
8891 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8892 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8893 hi32
.X_add_number
&= 0xffffffff;
8895 lo32
.X_add_number
&= 0xffffffff;
8899 gas_assert (ep
->X_add_number
> 2);
8900 if (ep
->X_add_number
== 3)
8901 generic_bignum
[3] = 0;
8902 else if (ep
->X_add_number
> 4)
8903 as_bad (_("number larger than 64 bits"));
8904 lo32
.X_op
= O_constant
;
8905 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8906 hi32
.X_op
= O_constant
;
8907 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8910 if (hi32
.X_add_number
== 0)
8915 unsigned long hi
, lo
;
8917 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8919 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8921 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8924 if (lo32
.X_add_number
& 0x80000000)
8926 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8927 if (lo32
.X_add_number
& 0xffff)
8928 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8933 /* Check for 16bit shifted constant. We know that hi32 is
8934 non-zero, so start the mask on the first bit of the hi32
8939 unsigned long himask
, lomask
;
8943 himask
= 0xffff >> (32 - shift
);
8944 lomask
= (0xffff << shift
) & 0xffffffff;
8948 himask
= 0xffff << (shift
- 32);
8951 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8952 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8956 tmp
.X_op
= O_constant
;
8958 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8959 | (lo32
.X_add_number
>> shift
));
8961 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8962 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8963 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8964 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8969 while (shift
<= (64 - 16));
8971 /* Find the bit number of the lowest one bit, and store the
8972 shifted value in hi/lo. */
8973 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8974 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8978 while ((lo
& 1) == 0)
8983 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8989 while ((hi
& 1) == 0)
8998 /* Optimize if the shifted value is a (power of 2) - 1. */
8999 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9000 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9002 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9007 /* This instruction will set the register to be all
9009 tmp
.X_op
= O_constant
;
9010 tmp
.X_add_number
= (offsetT
) -1;
9011 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9015 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9016 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9018 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9019 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9024 /* Sign extend hi32 before calling load_register, because we can
9025 generally get better code when we load a sign extended value. */
9026 if ((hi32
.X_add_number
& 0x80000000) != 0)
9027 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9028 load_register (reg
, &hi32
, 0);
9031 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9035 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9043 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9045 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9046 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9052 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9056 mid16
.X_add_number
>>= 16;
9057 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9058 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9061 if ((lo32
.X_add_number
& 0xffff) != 0)
9062 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9066 load_delay_nop (void)
9068 if (!gpr_interlocks
)
9069 macro_build (NULL
, "nop", "");
9072 /* Load an address into a register. */
9075 load_address (int reg
, expressionS
*ep
, int *used_at
)
9077 if (ep
->X_op
!= O_constant
9078 && ep
->X_op
!= O_symbol
)
9080 as_bad (_("expression too complex"));
9081 ep
->X_op
= O_constant
;
9084 if (ep
->X_op
== O_constant
)
9086 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9090 if (mips_pic
== NO_PIC
)
9092 /* If this is a reference to a GP relative symbol, we want
9093 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9095 lui $reg,<sym> (BFD_RELOC_HI16_S)
9096 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9097 If we have an addend, we always use the latter form.
9099 With 64bit address space and a usable $at we want
9100 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9101 lui $at,<sym> (BFD_RELOC_HI16_S)
9102 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9103 daddiu $at,<sym> (BFD_RELOC_LO16)
9107 If $at is already in use, we use a path which is suboptimal
9108 on superscalar processors.
9109 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9110 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9112 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9114 daddiu $reg,<sym> (BFD_RELOC_LO16)
9116 For GP relative symbols in 64bit address space we can use
9117 the same sequence as in 32bit address space. */
9118 if (HAVE_64BIT_SYMBOLS
)
9120 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9121 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9123 relax_start (ep
->X_add_symbol
);
9124 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9125 mips_gp_register
, BFD_RELOC_GPREL16
);
9129 if (*used_at
== 0 && mips_opts
.at
)
9131 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9132 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9133 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9134 BFD_RELOC_MIPS_HIGHER
);
9135 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9136 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9137 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9142 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9143 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9144 BFD_RELOC_MIPS_HIGHER
);
9145 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9146 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9147 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9148 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9151 if (mips_relax
.sequence
)
9156 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9157 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9159 relax_start (ep
->X_add_symbol
);
9160 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9161 mips_gp_register
, BFD_RELOC_GPREL16
);
9164 macro_build_lui (ep
, reg
);
9165 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9166 reg
, reg
, BFD_RELOC_LO16
);
9167 if (mips_relax
.sequence
)
9171 else if (!mips_big_got
)
9175 /* If this is a reference to an external symbol, we want
9176 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9178 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9180 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9181 If there is a constant, it must be added in after.
9183 If we have NewABI, we want
9184 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9185 unless we're referencing a global symbol with a non-zero
9186 offset, in which case cst must be added separately. */
9189 if (ep
->X_add_number
)
9191 ex
.X_add_number
= ep
->X_add_number
;
9192 ep
->X_add_number
= 0;
9193 relax_start (ep
->X_add_symbol
);
9194 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9195 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9196 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9197 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9198 ex
.X_op
= O_constant
;
9199 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9200 reg
, reg
, BFD_RELOC_LO16
);
9201 ep
->X_add_number
= ex
.X_add_number
;
9204 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9205 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9206 if (mips_relax
.sequence
)
9211 ex
.X_add_number
= ep
->X_add_number
;
9212 ep
->X_add_number
= 0;
9213 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9214 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9216 relax_start (ep
->X_add_symbol
);
9218 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9222 if (ex
.X_add_number
!= 0)
9224 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9225 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9226 ex
.X_op
= O_constant
;
9227 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9228 reg
, reg
, BFD_RELOC_LO16
);
9232 else if (mips_big_got
)
9236 /* This is the large GOT case. If this is a reference to an
9237 external symbol, we want
9238 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9240 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9242 Otherwise, for a reference to a local symbol in old ABI, we want
9243 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9245 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9246 If there is a constant, it must be added in after.
9248 In the NewABI, for local symbols, with or without offsets, we want:
9249 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9250 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9254 ex
.X_add_number
= ep
->X_add_number
;
9255 ep
->X_add_number
= 0;
9256 relax_start (ep
->X_add_symbol
);
9257 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9258 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9259 reg
, reg
, mips_gp_register
);
9260 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9261 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9262 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9263 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9264 else if (ex
.X_add_number
)
9266 ex
.X_op
= O_constant
;
9267 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9271 ep
->X_add_number
= ex
.X_add_number
;
9273 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9274 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9275 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9276 BFD_RELOC_MIPS_GOT_OFST
);
9281 ex
.X_add_number
= ep
->X_add_number
;
9282 ep
->X_add_number
= 0;
9283 relax_start (ep
->X_add_symbol
);
9284 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9285 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9286 reg
, reg
, mips_gp_register
);
9287 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9288 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9290 if (reg_needs_delay (mips_gp_register
))
9292 /* We need a nop before loading from $gp. This special
9293 check is required because the lui which starts the main
9294 instruction stream does not refer to $gp, and so will not
9295 insert the nop which may be required. */
9296 macro_build (NULL
, "nop", "");
9298 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9299 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9301 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9305 if (ex
.X_add_number
!= 0)
9307 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9308 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9309 ex
.X_op
= O_constant
;
9310 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9318 if (!mips_opts
.at
&& *used_at
== 1)
9319 as_bad (_("macro used $at after \".set noat\""));
9322 /* Move the contents of register SOURCE into register DEST. */
9325 move_register (int dest
, int source
)
9327 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9328 instruction specifically requires a 32-bit one. */
9329 if (mips_opts
.micromips
9330 && !mips_opts
.insn32
9331 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9332 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9334 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9337 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9338 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9339 The two alternatives are:
9341 Global symbol Local sybmol
9342 ------------- ------------
9343 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9345 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9347 load_got_offset emits the first instruction and add_got_offset
9348 emits the second for a 16-bit offset or add_got_offset_hilo emits
9349 a sequence to add a 32-bit offset using a scratch register. */
9352 load_got_offset (int dest
, expressionS
*local
)
9357 global
.X_add_number
= 0;
9359 relax_start (local
->X_add_symbol
);
9360 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9361 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9363 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9364 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9369 add_got_offset (int dest
, expressionS
*local
)
9373 global
.X_op
= O_constant
;
9374 global
.X_op_symbol
= NULL
;
9375 global
.X_add_symbol
= NULL
;
9376 global
.X_add_number
= local
->X_add_number
;
9378 relax_start (local
->X_add_symbol
);
9379 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9380 dest
, dest
, BFD_RELOC_LO16
);
9382 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9387 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9390 int hold_mips_optimize
;
9392 global
.X_op
= O_constant
;
9393 global
.X_op_symbol
= NULL
;
9394 global
.X_add_symbol
= NULL
;
9395 global
.X_add_number
= local
->X_add_number
;
9397 relax_start (local
->X_add_symbol
);
9398 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9400 /* Set mips_optimize around the lui instruction to avoid
9401 inserting an unnecessary nop after the lw. */
9402 hold_mips_optimize
= mips_optimize
;
9404 macro_build_lui (&global
, tmp
);
9405 mips_optimize
= hold_mips_optimize
;
9406 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9412 /* Emit a sequence of instructions to emulate a branch likely operation.
9413 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9414 is its complementing branch with the original condition negated.
9415 CALL is set if the original branch specified the link operation.
9416 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9418 Code like this is produced in the noreorder mode:
9423 delay slot (executed only if branch taken)
9431 delay slot (executed only if branch taken)
9434 In the reorder mode the delay slot would be filled with a nop anyway,
9435 so code produced is simply:
9440 This function is used when producing code for the microMIPS ASE that
9441 does not implement branch likely instructions in hardware. */
9444 macro_build_branch_likely (const char *br
, const char *brneg
,
9445 int call
, expressionS
*ep
, const char *fmt
,
9446 unsigned int sreg
, unsigned int treg
)
9448 int noreorder
= mips_opts
.noreorder
;
9451 gas_assert (mips_opts
.micromips
);
9455 micromips_label_expr (&expr1
);
9456 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9457 macro_build (NULL
, "nop", "");
9458 macro_build (ep
, call
? "bal" : "b", "p");
9460 /* Set to true so that append_insn adds a label. */
9461 emit_branch_likely_macro
= TRUE
;
9465 macro_build (ep
, br
, fmt
, sreg
, treg
);
9466 macro_build (NULL
, "nop", "");
9471 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9472 the condition code tested. EP specifies the branch target. */
9475 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9502 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9505 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9506 the register tested. EP specifies the branch target. */
9509 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9511 const char *brneg
= NULL
;
9521 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9525 gas_assert (mips_opts
.micromips
);
9526 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9534 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9541 br
= mips_opts
.micromips
? "blez" : "blezl";
9548 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9552 gas_assert (mips_opts
.micromips
);
9553 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9560 if (mips_opts
.micromips
&& brneg
)
9561 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9563 macro_build (ep
, br
, "s,p", sreg
);
9566 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9567 TREG as the registers tested. EP specifies the branch target. */
9570 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9571 unsigned int sreg
, unsigned int treg
)
9573 const char *brneg
= NULL
;
9585 br
= mips_opts
.micromips
? "beq" : "beql";
9594 br
= mips_opts
.micromips
? "bne" : "bnel";
9600 if (mips_opts
.micromips
&& brneg
)
9601 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9603 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9606 /* Return the high part that should be loaded in order to make the low
9607 part of VALUE accessible using an offset of OFFBITS bits. */
9610 offset_high_part (offsetT value
, unsigned int offbits
)
9617 bias
= 1 << (offbits
- 1);
9618 low_mask
= bias
* 2 - 1;
9619 return (value
+ bias
) & ~low_mask
;
9622 /* Return true if the value stored in offset_expr and offset_reloc
9623 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9624 amount that the caller wants to add without inducing overflow
9625 and ALIGN is the known alignment of the value in bytes. */
9628 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9632 /* Accept any relocation operator if overflow isn't a concern. */
9633 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9636 /* These relocations are guaranteed not to overflow in correct links. */
9637 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9638 || gprel16_reloc_p (*offset_reloc
))
9641 if (offset_expr
.X_op
== O_constant
9642 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9643 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9650 * This routine implements the seemingly endless macro or synthesized
9651 * instructions and addressing modes in the mips assembly language. Many
9652 * of these macros are simple and are similar to each other. These could
9653 * probably be handled by some kind of table or grammar approach instead of
9654 * this verbose method. Others are not simple macros but are more like
9655 * optimizing code generation.
9656 * One interesting optimization is when several store macros appear
9657 * consecutively that would load AT with the upper half of the same address.
9658 * The ensuing load upper instructions are ommited. This implies some kind
9659 * of global optimization. We currently only optimize within a single macro.
9660 * For many of the load and store macros if the address is specified as a
9661 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9662 * first load register 'at' with zero and use it as the base register. The
9663 * mips assembler simply uses register $zero. Just one tiny optimization
9667 macro (struct mips_cl_insn
*ip
, char *str
)
9669 const struct mips_operand_array
*operands
;
9670 unsigned int breg
, i
;
9671 unsigned int tempreg
;
9674 expressionS label_expr
;
9689 bfd_boolean large_offset
;
9691 int hold_mips_optimize
;
9693 unsigned int op
[MAX_OPERANDS
];
9695 gas_assert (! mips_opts
.mips16
);
9697 operands
= insn_operands (ip
);
9698 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9699 if (operands
->operand
[i
])
9700 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9704 mask
= ip
->insn_mo
->mask
;
9706 label_expr
.X_op
= O_constant
;
9707 label_expr
.X_op_symbol
= NULL
;
9708 label_expr
.X_add_symbol
= NULL
;
9709 label_expr
.X_add_number
= 0;
9711 expr1
.X_op
= O_constant
;
9712 expr1
.X_op_symbol
= NULL
;
9713 expr1
.X_add_symbol
= NULL
;
9714 expr1
.X_add_number
= 1;
9730 if (mips_opts
.micromips
)
9731 micromips_label_expr (&label_expr
);
9733 label_expr
.X_add_number
= 8;
9734 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9736 macro_build (NULL
, "nop", "");
9738 move_register (op
[0], op
[1]);
9739 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9740 if (mips_opts
.micromips
)
9741 micromips_add_label ();
9758 if (!mips_opts
.micromips
)
9760 if (imm_expr
.X_add_number
>= -0x200
9761 && imm_expr
.X_add_number
< 0x200)
9763 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9764 (int) imm_expr
.X_add_number
);
9773 if (imm_expr
.X_add_number
>= -0x8000
9774 && imm_expr
.X_add_number
< 0x8000)
9776 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9781 load_register (AT
, &imm_expr
, dbl
);
9782 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9801 if (imm_expr
.X_add_number
>= 0
9802 && imm_expr
.X_add_number
< 0x10000)
9804 if (mask
!= M_NOR_I
)
9805 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9808 macro_build (&imm_expr
, "ori", "t,r,i",
9809 op
[0], op
[1], BFD_RELOC_LO16
);
9810 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9816 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9817 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9821 switch (imm_expr
.X_add_number
)
9824 macro_build (NULL
, "nop", "");
9827 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9831 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9832 (int) imm_expr
.X_add_number
);
9835 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9836 (unsigned long) imm_expr
.X_add_number
);
9845 gas_assert (mips_opts
.micromips
);
9846 macro_build_branch_ccl (mask
, &offset_expr
,
9847 EXTRACT_OPERAND (1, BCC
, *ip
));
9854 if (imm_expr
.X_add_number
== 0)
9860 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
9865 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9872 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9873 else if (op
[0] == 0)
9874 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9878 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9879 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9880 &offset_expr
, AT
, ZERO
);
9890 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9896 /* Check for > max integer. */
9897 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9900 /* Result is always false. */
9902 macro_build (NULL
, "nop", "");
9904 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9907 ++imm_expr
.X_add_number
;
9911 if (mask
== M_BGEL_I
)
9913 if (imm_expr
.X_add_number
== 0)
9915 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9916 &offset_expr
, op
[0]);
9919 if (imm_expr
.X_add_number
== 1)
9921 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9922 &offset_expr
, op
[0]);
9925 if (imm_expr
.X_add_number
<= GPR_SMIN
)
9928 /* result is always true */
9929 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
9930 macro_build (&offset_expr
, "b", "p");
9935 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9936 &offset_expr
, AT
, ZERO
);
9944 else if (op
[0] == 0)
9945 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9946 &offset_expr
, ZERO
, op
[1]);
9950 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9951 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9952 &offset_expr
, AT
, ZERO
);
9961 && imm_expr
.X_add_number
== -1))
9963 ++imm_expr
.X_add_number
;
9967 if (mask
== M_BGEUL_I
)
9969 if (imm_expr
.X_add_number
== 0)
9971 else if (imm_expr
.X_add_number
== 1)
9972 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9973 &offset_expr
, op
[0], ZERO
);
9978 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9979 &offset_expr
, AT
, ZERO
);
9987 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9988 else if (op
[0] == 0)
9989 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9993 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9994 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9995 &offset_expr
, AT
, ZERO
);
10003 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10004 &offset_expr
, op
[0], ZERO
);
10005 else if (op
[0] == 0)
10010 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10011 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10012 &offset_expr
, AT
, ZERO
);
10020 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10021 else if (op
[0] == 0)
10022 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10026 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10027 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10028 &offset_expr
, AT
, ZERO
);
10035 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10037 ++imm_expr
.X_add_number
;
10041 if (mask
== M_BLTL_I
)
10043 if (imm_expr
.X_add_number
== 0)
10044 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10045 else if (imm_expr
.X_add_number
== 1)
10046 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10051 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10052 &offset_expr
, AT
, ZERO
);
10060 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10061 &offset_expr
, op
[0], ZERO
);
10062 else if (op
[0] == 0)
10067 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10068 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10069 &offset_expr
, AT
, ZERO
);
10078 && imm_expr
.X_add_number
== -1))
10080 ++imm_expr
.X_add_number
;
10084 if (mask
== M_BLTUL_I
)
10086 if (imm_expr
.X_add_number
== 0)
10088 else if (imm_expr
.X_add_number
== 1)
10089 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10090 &offset_expr
, op
[0], ZERO
);
10095 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10096 &offset_expr
, AT
, ZERO
);
10104 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10105 else if (op
[0] == 0)
10106 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10110 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10111 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10112 &offset_expr
, AT
, ZERO
);
10121 else if (op
[0] == 0)
10122 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10123 &offset_expr
, ZERO
, op
[1]);
10127 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10128 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10129 &offset_expr
, AT
, ZERO
);
10145 as_warn (_("divide by zero"));
10147 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10149 macro_build (NULL
, "break", BRK_FMT
, 7);
10153 start_noreorder ();
10156 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10157 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10161 if (mips_opts
.micromips
)
10162 micromips_label_expr (&label_expr
);
10164 label_expr
.X_add_number
= 8;
10165 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10166 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10167 macro_build (NULL
, "break", BRK_FMT
, 7);
10168 if (mips_opts
.micromips
)
10169 micromips_add_label ();
10171 expr1
.X_add_number
= -1;
10173 load_register (AT
, &expr1
, dbl
);
10174 if (mips_opts
.micromips
)
10175 micromips_label_expr (&label_expr
);
10177 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10178 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10181 expr1
.X_add_number
= 1;
10182 load_register (AT
, &expr1
, dbl
);
10183 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10187 expr1
.X_add_number
= 0x80000000;
10188 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10192 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10193 /* We want to close the noreorder block as soon as possible, so
10194 that later insns are available for delay slot filling. */
10199 if (mips_opts
.micromips
)
10200 micromips_label_expr (&label_expr
);
10202 label_expr
.X_add_number
= 8;
10203 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10204 macro_build (NULL
, "nop", "");
10206 /* We want to close the noreorder block as soon as possible, so
10207 that later insns are available for delay slot filling. */
10210 macro_build (NULL
, "break", BRK_FMT
, 6);
10212 if (mips_opts
.micromips
)
10213 micromips_add_label ();
10214 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10253 if (imm_expr
.X_add_number
== 0)
10255 as_warn (_("divide by zero"));
10257 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10259 macro_build (NULL
, "break", BRK_FMT
, 7);
10262 if (imm_expr
.X_add_number
== 1)
10264 if (strcmp (s2
, "mflo") == 0)
10265 move_register (op
[0], op
[1]);
10267 move_register (op
[0], ZERO
);
10270 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10272 if (strcmp (s2
, "mflo") == 0)
10273 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10275 move_register (op
[0], ZERO
);
10280 load_register (AT
, &imm_expr
, dbl
);
10281 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10282 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10301 start_noreorder ();
10304 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10305 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10306 /* We want to close the noreorder block as soon as possible, so
10307 that later insns are available for delay slot filling. */
10312 if (mips_opts
.micromips
)
10313 micromips_label_expr (&label_expr
);
10315 label_expr
.X_add_number
= 8;
10316 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10317 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10319 /* We want to close the noreorder block as soon as possible, so
10320 that later insns are available for delay slot filling. */
10322 macro_build (NULL
, "break", BRK_FMT
, 7);
10323 if (mips_opts
.micromips
)
10324 micromips_add_label ();
10326 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10338 /* Load the address of a symbol into a register. If breg is not
10339 zero, we then add a base register to it. */
10342 if (dbl
&& GPR_SIZE
== 32)
10343 as_warn (_("dla used to load 32-bit register; recommend using la "
10346 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10347 as_warn (_("la used to load 64-bit address; recommend using dla "
10350 if (small_offset_p (0, align
, 16))
10352 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10353 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10357 if (mips_opts
.at
&& (op
[0] == breg
))
10365 if (offset_expr
.X_op
!= O_symbol
10366 && offset_expr
.X_op
!= O_constant
)
10368 as_bad (_("expression too complex"));
10369 offset_expr
.X_op
= O_constant
;
10372 if (offset_expr
.X_op
== O_constant
)
10373 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10374 else if (mips_pic
== NO_PIC
)
10376 /* If this is a reference to a GP relative symbol, we want
10377 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10379 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10380 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10381 If we have a constant, we need two instructions anyhow,
10382 so we may as well always use the latter form.
10384 With 64bit address space and a usable $at we want
10385 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10386 lui $at,<sym> (BFD_RELOC_HI16_S)
10387 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10388 daddiu $at,<sym> (BFD_RELOC_LO16)
10390 daddu $tempreg,$tempreg,$at
10392 If $at is already in use, we use a path which is suboptimal
10393 on superscalar processors.
10394 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10395 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10397 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10399 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10401 For GP relative symbols in 64bit address space we can use
10402 the same sequence as in 32bit address space. */
10403 if (HAVE_64BIT_SYMBOLS
)
10405 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10406 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10408 relax_start (offset_expr
.X_add_symbol
);
10409 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10410 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10414 if (used_at
== 0 && mips_opts
.at
)
10416 macro_build (&offset_expr
, "lui", LUI_FMT
,
10417 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10418 macro_build (&offset_expr
, "lui", LUI_FMT
,
10419 AT
, BFD_RELOC_HI16_S
);
10420 macro_build (&offset_expr
, "daddiu", "t,r,j",
10421 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10422 macro_build (&offset_expr
, "daddiu", "t,r,j",
10423 AT
, AT
, BFD_RELOC_LO16
);
10424 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10425 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10430 macro_build (&offset_expr
, "lui", LUI_FMT
,
10431 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10432 macro_build (&offset_expr
, "daddiu", "t,r,j",
10433 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10434 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10435 macro_build (&offset_expr
, "daddiu", "t,r,j",
10436 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10437 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10438 macro_build (&offset_expr
, "daddiu", "t,r,j",
10439 tempreg
, tempreg
, BFD_RELOC_LO16
);
10442 if (mips_relax
.sequence
)
10447 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10448 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10450 relax_start (offset_expr
.X_add_symbol
);
10451 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10452 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10455 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10456 as_bad (_("offset too large"));
10457 macro_build_lui (&offset_expr
, tempreg
);
10458 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10459 tempreg
, tempreg
, BFD_RELOC_LO16
);
10460 if (mips_relax
.sequence
)
10464 else if (!mips_big_got
&& !HAVE_NEWABI
)
10466 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10468 /* If this is a reference to an external symbol, and there
10469 is no constant, we want
10470 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10471 or for lca or if tempreg is PIC_CALL_REG
10472 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10473 For a local symbol, we want
10474 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10476 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10478 If we have a small constant, and this is a reference to
10479 an external symbol, we want
10480 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10482 addiu $tempreg,$tempreg,<constant>
10483 For a local symbol, we want the same instruction
10484 sequence, but we output a BFD_RELOC_LO16 reloc on the
10487 If we have a large constant, and this is a reference to
10488 an external symbol, we want
10489 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10490 lui $at,<hiconstant>
10491 addiu $at,$at,<loconstant>
10492 addu $tempreg,$tempreg,$at
10493 For a local symbol, we want the same instruction
10494 sequence, but we output a BFD_RELOC_LO16 reloc on the
10498 if (offset_expr
.X_add_number
== 0)
10500 if (mips_pic
== SVR4_PIC
10502 && (call
|| tempreg
== PIC_CALL_REG
))
10503 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10505 relax_start (offset_expr
.X_add_symbol
);
10506 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10507 lw_reloc_type
, mips_gp_register
);
10510 /* We're going to put in an addu instruction using
10511 tempreg, so we may as well insert the nop right
10516 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10517 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10519 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10520 tempreg
, tempreg
, BFD_RELOC_LO16
);
10522 /* FIXME: If breg == 0, and the next instruction uses
10523 $tempreg, then if this variant case is used an extra
10524 nop will be generated. */
10526 else if (offset_expr
.X_add_number
>= -0x8000
10527 && offset_expr
.X_add_number
< 0x8000)
10529 load_got_offset (tempreg
, &offset_expr
);
10531 add_got_offset (tempreg
, &offset_expr
);
10535 expr1
.X_add_number
= offset_expr
.X_add_number
;
10536 offset_expr
.X_add_number
=
10537 SEXT_16BIT (offset_expr
.X_add_number
);
10538 load_got_offset (tempreg
, &offset_expr
);
10539 offset_expr
.X_add_number
= expr1
.X_add_number
;
10540 /* If we are going to add in a base register, and the
10541 target register and the base register are the same,
10542 then we are using AT as a temporary register. Since
10543 we want to load the constant into AT, we add our
10544 current AT (from the global offset table) and the
10545 register into the register now, and pretend we were
10546 not using a base register. */
10550 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10555 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10559 else if (!mips_big_got
&& HAVE_NEWABI
)
10561 int add_breg_early
= 0;
10563 /* If this is a reference to an external, and there is no
10564 constant, or local symbol (*), with or without a
10566 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10567 or for lca or if tempreg is PIC_CALL_REG
10568 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10570 If we have a small constant, and this is a reference to
10571 an external symbol, we want
10572 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10573 addiu $tempreg,$tempreg,<constant>
10575 If we have a large constant, and this is a reference to
10576 an external symbol, we want
10577 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10578 lui $at,<hiconstant>
10579 addiu $at,$at,<loconstant>
10580 addu $tempreg,$tempreg,$at
10582 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10583 local symbols, even though it introduces an additional
10586 if (offset_expr
.X_add_number
)
10588 expr1
.X_add_number
= offset_expr
.X_add_number
;
10589 offset_expr
.X_add_number
= 0;
10591 relax_start (offset_expr
.X_add_symbol
);
10592 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10593 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10595 if (expr1
.X_add_number
>= -0x8000
10596 && expr1
.X_add_number
< 0x8000)
10598 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10599 tempreg
, tempreg
, BFD_RELOC_LO16
);
10601 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10605 /* If we are going to add in a base register, and the
10606 target register and the base register are the same,
10607 then we are using AT as a temporary register. Since
10608 we want to load the constant into AT, we add our
10609 current AT (from the global offset table) and the
10610 register into the register now, and pretend we were
10611 not using a base register. */
10616 gas_assert (tempreg
== AT
);
10617 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10620 add_breg_early
= 1;
10623 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10624 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10630 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10633 offset_expr
.X_add_number
= expr1
.X_add_number
;
10635 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10636 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10637 if (add_breg_early
)
10639 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10640 op
[0], tempreg
, breg
);
10646 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10648 relax_start (offset_expr
.X_add_symbol
);
10649 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10650 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10652 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10653 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10658 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10659 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10662 else if (mips_big_got
&& !HAVE_NEWABI
)
10665 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10666 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10667 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10669 /* This is the large GOT case. If this is a reference to an
10670 external symbol, and there is no constant, we want
10671 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10672 addu $tempreg,$tempreg,$gp
10673 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10674 or for lca or if tempreg is PIC_CALL_REG
10675 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10676 addu $tempreg,$tempreg,$gp
10677 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10678 For a local symbol, we want
10679 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10681 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10683 If we have a small constant, and this is a reference to
10684 an external symbol, we want
10685 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10686 addu $tempreg,$tempreg,$gp
10687 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10689 addiu $tempreg,$tempreg,<constant>
10690 For a local symbol, we want
10691 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10693 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10695 If we have a large constant, and this is a reference to
10696 an external symbol, we want
10697 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10698 addu $tempreg,$tempreg,$gp
10699 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10700 lui $at,<hiconstant>
10701 addiu $at,$at,<loconstant>
10702 addu $tempreg,$tempreg,$at
10703 For a local symbol, we want
10704 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10705 lui $at,<hiconstant>
10706 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10707 addu $tempreg,$tempreg,$at
10710 expr1
.X_add_number
= offset_expr
.X_add_number
;
10711 offset_expr
.X_add_number
= 0;
10712 relax_start (offset_expr
.X_add_symbol
);
10713 gpdelay
= reg_needs_delay (mips_gp_register
);
10714 if (expr1
.X_add_number
== 0 && breg
== 0
10715 && (call
|| tempreg
== PIC_CALL_REG
))
10717 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10718 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10720 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10721 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10722 tempreg
, tempreg
, mips_gp_register
);
10723 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10724 tempreg
, lw_reloc_type
, tempreg
);
10725 if (expr1
.X_add_number
== 0)
10729 /* We're going to put in an addu instruction using
10730 tempreg, so we may as well insert the nop right
10735 else if (expr1
.X_add_number
>= -0x8000
10736 && expr1
.X_add_number
< 0x8000)
10739 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10740 tempreg
, tempreg
, BFD_RELOC_LO16
);
10746 /* If we are going to add in a base register, and the
10747 target register and the base register are the same,
10748 then we are using AT as a temporary register. Since
10749 we want to load the constant into AT, we add our
10750 current AT (from the global offset table) and the
10751 register into the register now, and pretend we were
10752 not using a base register. */
10757 gas_assert (tempreg
== AT
);
10759 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10764 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10765 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10769 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10774 /* This is needed because this instruction uses $gp, but
10775 the first instruction on the main stream does not. */
10776 macro_build (NULL
, "nop", "");
10779 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10780 local_reloc_type
, mips_gp_register
);
10781 if (expr1
.X_add_number
>= -0x8000
10782 && expr1
.X_add_number
< 0x8000)
10785 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10786 tempreg
, tempreg
, BFD_RELOC_LO16
);
10787 /* FIXME: If add_number is 0, and there was no base
10788 register, the external symbol case ended with a load,
10789 so if the symbol turns out to not be external, and
10790 the next instruction uses tempreg, an unnecessary nop
10791 will be inserted. */
10797 /* We must add in the base register now, as in the
10798 external symbol case. */
10799 gas_assert (tempreg
== AT
);
10801 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10804 /* We set breg to 0 because we have arranged to add
10805 it in in both cases. */
10809 macro_build_lui (&expr1
, AT
);
10810 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10811 AT
, AT
, BFD_RELOC_LO16
);
10812 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10813 tempreg
, tempreg
, AT
);
10818 else if (mips_big_got
&& HAVE_NEWABI
)
10820 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10821 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10822 int add_breg_early
= 0;
10824 /* This is the large GOT case. If this is a reference to an
10825 external symbol, and there is no constant, we want
10826 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10827 add $tempreg,$tempreg,$gp
10828 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10829 or for lca or if tempreg is PIC_CALL_REG
10830 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10831 add $tempreg,$tempreg,$gp
10832 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10834 If we have a small constant, and this is a reference to
10835 an external symbol, we want
10836 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10837 add $tempreg,$tempreg,$gp
10838 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10839 addi $tempreg,$tempreg,<constant>
10841 If we have a large constant, and this is a reference to
10842 an external symbol, we want
10843 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10844 addu $tempreg,$tempreg,$gp
10845 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10846 lui $at,<hiconstant>
10847 addi $at,$at,<loconstant>
10848 add $tempreg,$tempreg,$at
10850 If we have NewABI, and we know it's a local symbol, we want
10851 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10852 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10853 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10855 relax_start (offset_expr
.X_add_symbol
);
10857 expr1
.X_add_number
= offset_expr
.X_add_number
;
10858 offset_expr
.X_add_number
= 0;
10860 if (expr1
.X_add_number
== 0 && breg
== 0
10861 && (call
|| tempreg
== PIC_CALL_REG
))
10863 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10864 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10866 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10867 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10868 tempreg
, tempreg
, mips_gp_register
);
10869 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10870 tempreg
, lw_reloc_type
, tempreg
);
10872 if (expr1
.X_add_number
== 0)
10874 else if (expr1
.X_add_number
>= -0x8000
10875 && expr1
.X_add_number
< 0x8000)
10877 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10878 tempreg
, tempreg
, BFD_RELOC_LO16
);
10880 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10884 /* If we are going to add in a base register, and the
10885 target register and the base register are the same,
10886 then we are using AT as a temporary register. Since
10887 we want to load the constant into AT, we add our
10888 current AT (from the global offset table) and the
10889 register into the register now, and pretend we were
10890 not using a base register. */
10895 gas_assert (tempreg
== AT
);
10896 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10899 add_breg_early
= 1;
10902 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10903 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10908 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10911 offset_expr
.X_add_number
= expr1
.X_add_number
;
10912 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10913 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10914 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10915 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10916 if (add_breg_early
)
10918 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10919 op
[0], tempreg
, breg
);
10929 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10933 gas_assert (!mips_opts
.micromips
);
10934 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10938 gas_assert (!mips_opts
.micromips
);
10939 macro_build (NULL
, "c2", "C", 0x02);
10943 gas_assert (!mips_opts
.micromips
);
10944 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10948 gas_assert (!mips_opts
.micromips
);
10949 macro_build (NULL
, "c2", "C", 3);
10953 gas_assert (!mips_opts
.micromips
);
10954 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10958 /* The j instruction may not be used in PIC code, since it
10959 requires an absolute address. We convert it to a b
10961 if (mips_pic
== NO_PIC
)
10962 macro_build (&offset_expr
, "j", "a");
10964 macro_build (&offset_expr
, "b", "p");
10967 /* The jal instructions must be handled as macros because when
10968 generating PIC code they expand to multi-instruction
10969 sequences. Normally they are simple instructions. */
10973 /* Fall through. */
10975 gas_assert (mips_opts
.micromips
);
10976 if (mips_opts
.insn32
)
10978 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10986 /* Fall through. */
10989 if (mips_pic
== NO_PIC
)
10991 s
= jals
? "jalrs" : "jalr";
10992 if (mips_opts
.micromips
10993 && !mips_opts
.insn32
10995 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10996 macro_build (NULL
, s
, "mj", op
[1]);
10998 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11002 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11003 && mips_cprestore_offset
>= 0);
11005 if (op
[1] != PIC_CALL_REG
)
11006 as_warn (_("MIPS PIC call to register other than $25"));
11008 s
= ((mips_opts
.micromips
11009 && !mips_opts
.insn32
11010 && (!mips_opts
.noreorder
|| cprestore
))
11011 ? "jalrs" : "jalr");
11012 if (mips_opts
.micromips
11013 && !mips_opts
.insn32
11015 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11016 macro_build (NULL
, s
, "mj", op
[1]);
11018 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11019 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11021 if (mips_cprestore_offset
< 0)
11022 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11025 if (!mips_frame_reg_valid
)
11027 as_warn (_("no .frame pseudo-op used in PIC code"));
11028 /* Quiet this warning. */
11029 mips_frame_reg_valid
= 1;
11031 if (!mips_cprestore_valid
)
11033 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11034 /* Quiet this warning. */
11035 mips_cprestore_valid
= 1;
11037 if (mips_opts
.noreorder
)
11038 macro_build (NULL
, "nop", "");
11039 expr1
.X_add_number
= mips_cprestore_offset
;
11040 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11043 HAVE_64BIT_ADDRESSES
);
11051 gas_assert (mips_opts
.micromips
);
11052 if (mips_opts
.insn32
)
11054 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11058 /* Fall through. */
11060 if (mips_pic
== NO_PIC
)
11061 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11062 else if (mips_pic
== SVR4_PIC
)
11064 /* If this is a reference to an external symbol, and we are
11065 using a small GOT, we want
11066 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11070 lw $gp,cprestore($sp)
11071 The cprestore value is set using the .cprestore
11072 pseudo-op. If we are using a big GOT, we want
11073 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11075 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11079 lw $gp,cprestore($sp)
11080 If the symbol is not external, we want
11081 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11083 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11086 lw $gp,cprestore($sp)
11088 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11089 sequences above, minus nops, unless the symbol is local,
11090 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11096 relax_start (offset_expr
.X_add_symbol
);
11097 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11098 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11101 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11102 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11108 relax_start (offset_expr
.X_add_symbol
);
11109 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11110 BFD_RELOC_MIPS_CALL_HI16
);
11111 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11112 PIC_CALL_REG
, mips_gp_register
);
11113 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11114 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11117 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11118 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11120 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11121 PIC_CALL_REG
, PIC_CALL_REG
,
11122 BFD_RELOC_MIPS_GOT_OFST
);
11126 macro_build_jalr (&offset_expr
, 0);
11130 relax_start (offset_expr
.X_add_symbol
);
11133 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11134 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11143 gpdelay
= reg_needs_delay (mips_gp_register
);
11144 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11145 BFD_RELOC_MIPS_CALL_HI16
);
11146 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11147 PIC_CALL_REG
, mips_gp_register
);
11148 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11149 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11154 macro_build (NULL
, "nop", "");
11156 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11157 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11160 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11161 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11163 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11165 if (mips_cprestore_offset
< 0)
11166 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11169 if (!mips_frame_reg_valid
)
11171 as_warn (_("no .frame pseudo-op used in PIC code"));
11172 /* Quiet this warning. */
11173 mips_frame_reg_valid
= 1;
11175 if (!mips_cprestore_valid
)
11177 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11178 /* Quiet this warning. */
11179 mips_cprestore_valid
= 1;
11181 if (mips_opts
.noreorder
)
11182 macro_build (NULL
, "nop", "");
11183 expr1
.X_add_number
= mips_cprestore_offset
;
11184 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11187 HAVE_64BIT_ADDRESSES
);
11191 else if (mips_pic
== VXWORKS_PIC
)
11192 as_bad (_("non-PIC jump used in PIC library"));
11299 gas_assert (!mips_opts
.micromips
);
11302 /* Itbl support may require additional care here. */
11308 /* Itbl support may require additional care here. */
11314 offbits
= (mips_opts
.micromips
? 12
11315 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11317 /* Itbl support may require additional care here. */
11321 gas_assert (!mips_opts
.micromips
);
11324 /* Itbl support may require additional care here. */
11330 offbits
= (mips_opts
.micromips
? 12 : 16);
11335 offbits
= (mips_opts
.micromips
? 12 : 16);
11340 /* Itbl support may require additional care here. */
11346 offbits
= (mips_opts
.micromips
? 12
11347 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11349 /* Itbl support may require additional care here. */
11355 /* Itbl support may require additional care here. */
11361 /* Itbl support may require additional care here. */
11367 offbits
= (mips_opts
.micromips
? 12 : 16);
11372 offbits
= (mips_opts
.micromips
? 12 : 16);
11377 offbits
= (mips_opts
.micromips
? 12
11378 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11384 offbits
= (mips_opts
.micromips
? 12
11385 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11391 offbits
= (mips_opts
.micromips
? 12 : 16);
11394 gas_assert (mips_opts
.micromips
);
11401 gas_assert (mips_opts
.micromips
);
11408 gas_assert (mips_opts
.micromips
);
11414 gas_assert (mips_opts
.micromips
);
11421 /* We don't want to use $0 as tempreg. */
11422 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11425 tempreg
= op
[0] + lp
;
11441 gas_assert (!mips_opts
.micromips
);
11444 /* Itbl support may require additional care here. */
11450 /* Itbl support may require additional care here. */
11456 offbits
= (mips_opts
.micromips
? 12
11457 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11459 /* Itbl support may require additional care here. */
11463 gas_assert (!mips_opts
.micromips
);
11466 /* Itbl support may require additional care here. */
11472 offbits
= (mips_opts
.micromips
? 12 : 16);
11477 offbits
= (mips_opts
.micromips
? 12 : 16);
11482 offbits
= (mips_opts
.micromips
? 12
11483 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11489 offbits
= (mips_opts
.micromips
? 12
11490 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11495 fmt
= (mips_opts
.micromips
? "k,~(b)"
11496 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11498 offbits
= (mips_opts
.micromips
? 12
11499 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11509 fmt
= (mips_opts
.micromips
? "k,~(b)"
11510 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11512 offbits
= (mips_opts
.micromips
? 12
11513 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11525 /* Itbl support may require additional care here. */
11530 offbits
= (mips_opts
.micromips
? 12
11531 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11533 /* Itbl support may require additional care here. */
11539 /* Itbl support may require additional care here. */
11543 gas_assert (!mips_opts
.micromips
);
11546 /* Itbl support may require additional care here. */
11552 offbits
= (mips_opts
.micromips
? 12 : 16);
11557 offbits
= (mips_opts
.micromips
? 12 : 16);
11560 gas_assert (mips_opts
.micromips
);
11566 gas_assert (mips_opts
.micromips
);
11572 gas_assert (mips_opts
.micromips
);
11578 gas_assert (mips_opts
.micromips
);
11587 if (small_offset_p (0, align
, 16))
11589 /* The first case exists for M_LD_AB and M_SD_AB, which are
11590 macros for o32 but which should act like normal instructions
11593 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11594 offset_reloc
[1], offset_reloc
[2], breg
);
11595 else if (small_offset_p (0, align
, offbits
))
11598 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11600 macro_build (NULL
, s
, fmt
, op
[0],
11601 (int) offset_expr
.X_add_number
, breg
);
11607 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11608 tempreg
, breg
, -1, offset_reloc
[0],
11609 offset_reloc
[1], offset_reloc
[2]);
11611 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11613 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11621 if (offset_expr
.X_op
!= O_constant
11622 && offset_expr
.X_op
!= O_symbol
)
11624 as_bad (_("expression too complex"));
11625 offset_expr
.X_op
= O_constant
;
11628 if (HAVE_32BIT_ADDRESSES
11629 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11633 sprintf_vma (value
, offset_expr
.X_add_number
);
11634 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11637 /* A constant expression in PIC code can be handled just as it
11638 is in non PIC code. */
11639 if (offset_expr
.X_op
== O_constant
)
11641 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11642 offbits
== 0 ? 16 : offbits
);
11643 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11645 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11647 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11648 tempreg
, tempreg
, breg
);
11651 if (offset_expr
.X_add_number
!= 0)
11652 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11653 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11654 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11656 else if (offbits
== 16)
11657 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11659 macro_build (NULL
, s
, fmt
, op
[0],
11660 (int) offset_expr
.X_add_number
, tempreg
);
11662 else if (offbits
!= 16)
11664 /* The offset field is too narrow to be used for a low-part
11665 relocation, so load the whole address into the auxillary
11667 load_address (tempreg
, &offset_expr
, &used_at
);
11669 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11670 tempreg
, tempreg
, breg
);
11672 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11674 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11676 else if (mips_pic
== NO_PIC
)
11678 /* If this is a reference to a GP relative symbol, and there
11679 is no base register, we want
11680 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11681 Otherwise, if there is no base register, we want
11682 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11683 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11684 If we have a constant, we need two instructions anyhow,
11685 so we always use the latter form.
11687 If we have a base register, and this is a reference to a
11688 GP relative symbol, we want
11689 addu $tempreg,$breg,$gp
11690 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11692 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11693 addu $tempreg,$tempreg,$breg
11694 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11695 With a constant we always use the latter case.
11697 With 64bit address space and no base register and $at usable,
11699 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11700 lui $at,<sym> (BFD_RELOC_HI16_S)
11701 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11704 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11705 If we have a base register, we want
11706 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11707 lui $at,<sym> (BFD_RELOC_HI16_S)
11708 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11712 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11714 Without $at we can't generate the optimal path for superscalar
11715 processors here since this would require two temporary registers.
11716 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11717 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11719 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11721 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11722 If we have a base register, we want
11723 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11724 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11726 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11728 daddu $tempreg,$tempreg,$breg
11729 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11731 For GP relative symbols in 64bit address space we can use
11732 the same sequence as in 32bit address space. */
11733 if (HAVE_64BIT_SYMBOLS
)
11735 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11736 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11738 relax_start (offset_expr
.X_add_symbol
);
11741 macro_build (&offset_expr
, s
, fmt
, op
[0],
11742 BFD_RELOC_GPREL16
, mips_gp_register
);
11746 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11747 tempreg
, breg
, mips_gp_register
);
11748 macro_build (&offset_expr
, s
, fmt
, op
[0],
11749 BFD_RELOC_GPREL16
, tempreg
);
11754 if (used_at
== 0 && mips_opts
.at
)
11756 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11757 BFD_RELOC_MIPS_HIGHEST
);
11758 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11760 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11761 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11763 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11764 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11765 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11766 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11772 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11773 BFD_RELOC_MIPS_HIGHEST
);
11774 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11775 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11776 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11777 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11778 tempreg
, BFD_RELOC_HI16_S
);
11779 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11781 macro_build (NULL
, "daddu", "d,v,t",
11782 tempreg
, tempreg
, breg
);
11783 macro_build (&offset_expr
, s
, fmt
, op
[0],
11784 BFD_RELOC_LO16
, tempreg
);
11787 if (mips_relax
.sequence
)
11794 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11795 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11797 relax_start (offset_expr
.X_add_symbol
);
11798 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11802 macro_build_lui (&offset_expr
, tempreg
);
11803 macro_build (&offset_expr
, s
, fmt
, op
[0],
11804 BFD_RELOC_LO16
, tempreg
);
11805 if (mips_relax
.sequence
)
11810 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11811 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11813 relax_start (offset_expr
.X_add_symbol
);
11814 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11815 tempreg
, breg
, mips_gp_register
);
11816 macro_build (&offset_expr
, s
, fmt
, op
[0],
11817 BFD_RELOC_GPREL16
, tempreg
);
11820 macro_build_lui (&offset_expr
, tempreg
);
11821 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11822 tempreg
, tempreg
, breg
);
11823 macro_build (&offset_expr
, s
, fmt
, op
[0],
11824 BFD_RELOC_LO16
, tempreg
);
11825 if (mips_relax
.sequence
)
11829 else if (!mips_big_got
)
11831 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11833 /* If this is a reference to an external symbol, we want
11834 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11836 <op> op[0],0($tempreg)
11838 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11840 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11841 <op> op[0],0($tempreg)
11843 For NewABI, we want
11844 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11845 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11847 If there is a base register, we add it to $tempreg before
11848 the <op>. If there is a constant, we stick it in the
11849 <op> instruction. We don't handle constants larger than
11850 16 bits, because we have no way to load the upper 16 bits
11851 (actually, we could handle them for the subset of cases
11852 in which we are not using $at). */
11853 gas_assert (offset_expr
.X_op
== O_symbol
);
11856 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11857 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11859 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11860 tempreg
, tempreg
, breg
);
11861 macro_build (&offset_expr
, s
, fmt
, op
[0],
11862 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11865 expr1
.X_add_number
= offset_expr
.X_add_number
;
11866 offset_expr
.X_add_number
= 0;
11867 if (expr1
.X_add_number
< -0x8000
11868 || expr1
.X_add_number
>= 0x8000)
11869 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11870 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11871 lw_reloc_type
, mips_gp_register
);
11873 relax_start (offset_expr
.X_add_symbol
);
11875 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11876 tempreg
, BFD_RELOC_LO16
);
11879 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11880 tempreg
, tempreg
, breg
);
11881 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11883 else if (mips_big_got
&& !HAVE_NEWABI
)
11887 /* If this is a reference to an external symbol, we want
11888 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11889 addu $tempreg,$tempreg,$gp
11890 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11891 <op> op[0],0($tempreg)
11893 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11895 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11896 <op> op[0],0($tempreg)
11897 If there is a base register, we add it to $tempreg before
11898 the <op>. If there is a constant, we stick it in the
11899 <op> instruction. We don't handle constants larger than
11900 16 bits, because we have no way to load the upper 16 bits
11901 (actually, we could handle them for the subset of cases
11902 in which we are not using $at). */
11903 gas_assert (offset_expr
.X_op
== O_symbol
);
11904 expr1
.X_add_number
= offset_expr
.X_add_number
;
11905 offset_expr
.X_add_number
= 0;
11906 if (expr1
.X_add_number
< -0x8000
11907 || expr1
.X_add_number
>= 0x8000)
11908 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11909 gpdelay
= reg_needs_delay (mips_gp_register
);
11910 relax_start (offset_expr
.X_add_symbol
);
11911 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11912 BFD_RELOC_MIPS_GOT_HI16
);
11913 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11915 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11916 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11919 macro_build (NULL
, "nop", "");
11920 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11921 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11923 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11924 tempreg
, BFD_RELOC_LO16
);
11928 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11929 tempreg
, tempreg
, breg
);
11930 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11932 else if (mips_big_got
&& HAVE_NEWABI
)
11934 /* If this is a reference to an external symbol, we want
11935 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11936 add $tempreg,$tempreg,$gp
11937 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11938 <op> op[0],<ofst>($tempreg)
11939 Otherwise, for local symbols, we want:
11940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11941 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11942 gas_assert (offset_expr
.X_op
== O_symbol
);
11943 expr1
.X_add_number
= offset_expr
.X_add_number
;
11944 offset_expr
.X_add_number
= 0;
11945 if (expr1
.X_add_number
< -0x8000
11946 || expr1
.X_add_number
>= 0x8000)
11947 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11948 relax_start (offset_expr
.X_add_symbol
);
11949 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11950 BFD_RELOC_MIPS_GOT_HI16
);
11951 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11953 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11954 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11956 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11957 tempreg
, tempreg
, breg
);
11958 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11961 offset_expr
.X_add_number
= expr1
.X_add_number
;
11962 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11963 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11965 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11966 tempreg
, tempreg
, breg
);
11967 macro_build (&offset_expr
, s
, fmt
, op
[0],
11968 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11977 gas_assert (mips_opts
.micromips
);
11978 gas_assert (mips_opts
.insn32
);
11979 start_noreorder ();
11980 macro_build (NULL
, "jr", "s", RA
);
11981 expr1
.X_add_number
= op
[0] << 2;
11982 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11987 gas_assert (mips_opts
.micromips
);
11988 gas_assert (mips_opts
.insn32
);
11989 macro_build (NULL
, "jr", "s", op
[0]);
11990 if (mips_opts
.noreorder
)
11991 macro_build (NULL
, "nop", "");
11996 load_register (op
[0], &imm_expr
, 0);
12000 load_register (op
[0], &imm_expr
, 1);
12004 if (imm_expr
.X_op
== O_constant
)
12007 load_register (AT
, &imm_expr
, 0);
12008 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12013 gas_assert (imm_expr
.X_op
== O_absent
12014 && offset_expr
.X_op
== O_symbol
12015 && strcmp (segment_name (S_GET_SEGMENT
12016 (offset_expr
.X_add_symbol
)),
12018 && offset_expr
.X_add_number
== 0);
12019 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12020 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12025 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12026 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12027 order 32 bits of the value and the low order 32 bits are either
12028 zero or in OFFSET_EXPR. */
12029 if (imm_expr
.X_op
== O_constant
)
12031 if (GPR_SIZE
== 64)
12032 load_register (op
[0], &imm_expr
, 1);
12037 if (target_big_endian
)
12049 load_register (hreg
, &imm_expr
, 0);
12052 if (offset_expr
.X_op
== O_absent
)
12053 move_register (lreg
, 0);
12056 gas_assert (offset_expr
.X_op
== O_constant
);
12057 load_register (lreg
, &offset_expr
, 0);
12063 gas_assert (imm_expr
.X_op
== O_absent
);
12065 /* We know that sym is in the .rdata section. First we get the
12066 upper 16 bits of the address. */
12067 if (mips_pic
== NO_PIC
)
12069 macro_build_lui (&offset_expr
, AT
);
12074 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12075 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12079 /* Now we load the register(s). */
12080 if (GPR_SIZE
== 64)
12083 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12084 BFD_RELOC_LO16
, AT
);
12089 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12090 BFD_RELOC_LO16
, AT
);
12093 /* FIXME: How in the world do we deal with the possible
12095 offset_expr
.X_add_number
+= 4;
12096 macro_build (&offset_expr
, "lw", "t,o(b)",
12097 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12103 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12104 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12105 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12106 the value and the low order 32 bits are either zero or in
12108 if (imm_expr
.X_op
== O_constant
)
12111 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12112 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12113 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12116 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12117 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12118 else if (FPR_SIZE
!= 32)
12119 as_bad (_("Unable to generate `%s' compliant code "
12121 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12123 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12124 if (offset_expr
.X_op
== O_absent
)
12125 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12128 gas_assert (offset_expr
.X_op
== O_constant
);
12129 load_register (AT
, &offset_expr
, 0);
12130 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12136 gas_assert (imm_expr
.X_op
== O_absent
12137 && offset_expr
.X_op
== O_symbol
12138 && offset_expr
.X_add_number
== 0);
12139 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12140 if (strcmp (s
, ".lit8") == 0)
12142 op
[2] = mips_gp_register
;
12143 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12144 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12145 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12149 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12151 if (mips_pic
!= NO_PIC
)
12152 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12153 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12156 /* FIXME: This won't work for a 64 bit address. */
12157 macro_build_lui (&offset_expr
, AT
);
12161 offset_reloc
[0] = BFD_RELOC_LO16
;
12162 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12163 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12170 * The MIPS assembler seems to check for X_add_number not
12171 * being double aligned and generating:
12172 * lui at,%hi(foo+1)
12174 * addiu at,at,%lo(foo+1)
12177 * But, the resulting address is the same after relocation so why
12178 * generate the extra instruction?
12180 /* Itbl support may require additional care here. */
12183 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12192 gas_assert (!mips_opts
.micromips
);
12193 /* Itbl support may require additional care here. */
12196 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12216 if (GPR_SIZE
== 64)
12226 if (GPR_SIZE
== 64)
12234 /* Even on a big endian machine $fn comes before $fn+1. We have
12235 to adjust when loading from memory. We set coproc if we must
12236 load $fn+1 first. */
12237 /* Itbl support may require additional care here. */
12238 if (!target_big_endian
)
12242 if (small_offset_p (0, align
, 16))
12245 if (!small_offset_p (4, align
, 16))
12247 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12248 -1, offset_reloc
[0], offset_reloc
[1],
12250 expr1
.X_add_number
= 0;
12254 offset_reloc
[0] = BFD_RELOC_LO16
;
12255 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12256 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12258 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12260 ep
->X_add_number
+= 4;
12261 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12262 offset_reloc
[1], offset_reloc
[2], breg
);
12263 ep
->X_add_number
-= 4;
12264 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12265 offset_reloc
[1], offset_reloc
[2], breg
);
12269 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12270 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12272 ep
->X_add_number
+= 4;
12273 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12274 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12280 if (offset_expr
.X_op
!= O_symbol
12281 && offset_expr
.X_op
!= O_constant
)
12283 as_bad (_("expression too complex"));
12284 offset_expr
.X_op
= O_constant
;
12287 if (HAVE_32BIT_ADDRESSES
12288 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12292 sprintf_vma (value
, offset_expr
.X_add_number
);
12293 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12296 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12298 /* If this is a reference to a GP relative symbol, we want
12299 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12300 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12301 If we have a base register, we use this
12303 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12304 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12305 If this is not a GP relative symbol, we want
12306 lui $at,<sym> (BFD_RELOC_HI16_S)
12307 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12308 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12309 If there is a base register, we add it to $at after the
12310 lui instruction. If there is a constant, we always use
12312 if (offset_expr
.X_op
== O_symbol
12313 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12314 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12316 relax_start (offset_expr
.X_add_symbol
);
12319 tempreg
= mips_gp_register
;
12323 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12324 AT
, breg
, mips_gp_register
);
12329 /* Itbl support may require additional care here. */
12330 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12331 BFD_RELOC_GPREL16
, tempreg
);
12332 offset_expr
.X_add_number
+= 4;
12334 /* Set mips_optimize to 2 to avoid inserting an
12336 hold_mips_optimize
= mips_optimize
;
12338 /* Itbl support may require additional care here. */
12339 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12340 BFD_RELOC_GPREL16
, tempreg
);
12341 mips_optimize
= hold_mips_optimize
;
12345 offset_expr
.X_add_number
-= 4;
12348 if (offset_high_part (offset_expr
.X_add_number
, 16)
12349 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12351 load_address (AT
, &offset_expr
, &used_at
);
12352 offset_expr
.X_op
= O_constant
;
12353 offset_expr
.X_add_number
= 0;
12356 macro_build_lui (&offset_expr
, AT
);
12358 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12359 /* Itbl support may require additional care here. */
12360 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12361 BFD_RELOC_LO16
, AT
);
12362 /* FIXME: How do we handle overflow here? */
12363 offset_expr
.X_add_number
+= 4;
12364 /* Itbl support may require additional care here. */
12365 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12366 BFD_RELOC_LO16
, AT
);
12367 if (mips_relax
.sequence
)
12370 else if (!mips_big_got
)
12372 /* If this is a reference to an external symbol, we want
12373 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12376 <op> op[0]+1,4($at)
12378 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12380 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12381 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12382 If there is a base register we add it to $at before the
12383 lwc1 instructions. If there is a constant we include it
12384 in the lwc1 instructions. */
12386 expr1
.X_add_number
= offset_expr
.X_add_number
;
12387 if (expr1
.X_add_number
< -0x8000
12388 || expr1
.X_add_number
>= 0x8000 - 4)
12389 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12390 load_got_offset (AT
, &offset_expr
);
12393 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12395 /* Set mips_optimize to 2 to avoid inserting an undesired
12397 hold_mips_optimize
= mips_optimize
;
12400 /* Itbl support may require additional care here. */
12401 relax_start (offset_expr
.X_add_symbol
);
12402 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12403 BFD_RELOC_LO16
, AT
);
12404 expr1
.X_add_number
+= 4;
12405 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12406 BFD_RELOC_LO16
, AT
);
12408 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12409 BFD_RELOC_LO16
, AT
);
12410 offset_expr
.X_add_number
+= 4;
12411 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12412 BFD_RELOC_LO16
, AT
);
12415 mips_optimize
= hold_mips_optimize
;
12417 else if (mips_big_got
)
12421 /* If this is a reference to an external symbol, we want
12422 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12424 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12427 <op> op[0]+1,4($at)
12429 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12431 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12432 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12433 If there is a base register we add it to $at before the
12434 lwc1 instructions. If there is a constant we include it
12435 in the lwc1 instructions. */
12437 expr1
.X_add_number
= offset_expr
.X_add_number
;
12438 offset_expr
.X_add_number
= 0;
12439 if (expr1
.X_add_number
< -0x8000
12440 || expr1
.X_add_number
>= 0x8000 - 4)
12441 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12442 gpdelay
= reg_needs_delay (mips_gp_register
);
12443 relax_start (offset_expr
.X_add_symbol
);
12444 macro_build (&offset_expr
, "lui", LUI_FMT
,
12445 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12446 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12447 AT
, AT
, mips_gp_register
);
12448 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12449 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12452 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12453 /* Itbl support may require additional care here. */
12454 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12455 BFD_RELOC_LO16
, AT
);
12456 expr1
.X_add_number
+= 4;
12458 /* Set mips_optimize to 2 to avoid inserting an undesired
12460 hold_mips_optimize
= mips_optimize
;
12462 /* Itbl support may require additional care here. */
12463 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12464 BFD_RELOC_LO16
, AT
);
12465 mips_optimize
= hold_mips_optimize
;
12466 expr1
.X_add_number
-= 4;
12469 offset_expr
.X_add_number
= expr1
.X_add_number
;
12471 macro_build (NULL
, "nop", "");
12472 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12473 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12476 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12477 /* Itbl support may require additional care here. */
12478 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12479 BFD_RELOC_LO16
, AT
);
12480 offset_expr
.X_add_number
+= 4;
12482 /* Set mips_optimize to 2 to avoid inserting an undesired
12484 hold_mips_optimize
= mips_optimize
;
12486 /* Itbl support may require additional care here. */
12487 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12488 BFD_RELOC_LO16
, AT
);
12489 mips_optimize
= hold_mips_optimize
;
12503 gas_assert (!mips_opts
.micromips
);
12508 /* New code added to support COPZ instructions.
12509 This code builds table entries out of the macros in mip_opcodes.
12510 R4000 uses interlocks to handle coproc delays.
12511 Other chips (like the R3000) require nops to be inserted for delays.
12513 FIXME: Currently, we require that the user handle delays.
12514 In order to fill delay slots for non-interlocked chips,
12515 we must have a way to specify delays based on the coprocessor.
12516 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12517 What are the side-effects of the cop instruction?
12518 What cache support might we have and what are its effects?
12519 Both coprocessor & memory require delays. how long???
12520 What registers are read/set/modified?
12522 If an itbl is provided to interpret cop instructions,
12523 this knowledge can be encoded in the itbl spec. */
12537 gas_assert (!mips_opts
.micromips
);
12538 /* For now we just do C (same as Cz). The parameter will be
12539 stored in insn_opcode by mips_ip. */
12540 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12544 move_register (op
[0], op
[1]);
12548 gas_assert (mips_opts
.micromips
);
12549 gas_assert (mips_opts
.insn32
);
12550 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12551 micromips_to_32_reg_m_map
[op
[1]]);
12552 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12553 micromips_to_32_reg_n_map
[op
[2]]);
12559 if (mips_opts
.arch
== CPU_R5900
)
12560 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12564 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12565 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12572 /* The MIPS assembler some times generates shifts and adds. I'm
12573 not trying to be that fancy. GCC should do this for us
12576 load_register (AT
, &imm_expr
, dbl
);
12577 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12578 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12591 start_noreorder ();
12594 load_register (AT
, &imm_expr
, dbl
);
12595 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12596 op
[1], imm
? AT
: op
[2]);
12597 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12598 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12599 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12601 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12604 if (mips_opts
.micromips
)
12605 micromips_label_expr (&label_expr
);
12607 label_expr
.X_add_number
= 8;
12608 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12609 macro_build (NULL
, "nop", "");
12610 macro_build (NULL
, "break", BRK_FMT
, 6);
12611 if (mips_opts
.micromips
)
12612 micromips_add_label ();
12615 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12628 start_noreorder ();
12631 load_register (AT
, &imm_expr
, dbl
);
12632 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12633 op
[1], imm
? AT
: op
[2]);
12634 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12635 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12637 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12640 if (mips_opts
.micromips
)
12641 micromips_label_expr (&label_expr
);
12643 label_expr
.X_add_number
= 8;
12644 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12645 macro_build (NULL
, "nop", "");
12646 macro_build (NULL
, "break", BRK_FMT
, 6);
12647 if (mips_opts
.micromips
)
12648 micromips_add_label ();
12654 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12656 if (op
[0] == op
[1])
12663 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12664 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12668 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12669 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12670 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12671 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12675 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12677 if (op
[0] == op
[1])
12684 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12685 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12689 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12690 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12691 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12692 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12701 rot
= imm_expr
.X_add_number
& 0x3f;
12702 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12704 rot
= (64 - rot
) & 0x3f;
12706 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12708 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12713 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12716 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12717 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12720 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12721 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12722 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12730 rot
= imm_expr
.X_add_number
& 0x1f;
12731 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12733 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12734 (32 - rot
) & 0x1f);
12739 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12743 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12744 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12745 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12750 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12752 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12756 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12757 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12758 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12759 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12763 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12765 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12769 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12770 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12771 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12772 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12781 rot
= imm_expr
.X_add_number
& 0x3f;
12782 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12785 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12787 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12792 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12795 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12796 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12799 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12800 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12801 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12809 rot
= imm_expr
.X_add_number
& 0x1f;
12810 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12812 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12817 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12821 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12822 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12823 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12829 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12830 else if (op
[2] == 0)
12831 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12834 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12835 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12840 if (imm_expr
.X_add_number
== 0)
12842 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12847 as_warn (_("instruction %s: result is always false"),
12848 ip
->insn_mo
->name
);
12849 move_register (op
[0], 0);
12852 if (CPU_HAS_SEQ (mips_opts
.arch
)
12853 && -512 <= imm_expr
.X_add_number
12854 && imm_expr
.X_add_number
< 512)
12856 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12857 (int) imm_expr
.X_add_number
);
12860 if (imm_expr
.X_add_number
>= 0
12861 && imm_expr
.X_add_number
< 0x10000)
12862 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12863 else if (imm_expr
.X_add_number
> -0x8000
12864 && imm_expr
.X_add_number
< 0)
12866 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12867 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
12868 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12870 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12873 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12874 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12879 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12880 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12883 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12886 case M_SGE
: /* X >= Y <==> not (X < Y) */
12892 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12893 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12896 case M_SGE_I
: /* X >= I <==> not (X < I) */
12898 if (imm_expr
.X_add_number
>= -0x8000
12899 && imm_expr
.X_add_number
< 0x8000)
12900 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12901 op
[0], op
[1], BFD_RELOC_LO16
);
12904 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12905 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12909 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12912 case M_SGT
: /* X > Y <==> Y < X */
12918 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12921 case M_SGT_I
: /* X > I <==> I < X */
12928 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12929 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12932 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12938 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12939 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12942 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12949 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12950 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12951 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12955 if (imm_expr
.X_add_number
>= -0x8000
12956 && imm_expr
.X_add_number
< 0x8000)
12958 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12963 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12964 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12968 if (imm_expr
.X_add_number
>= -0x8000
12969 && imm_expr
.X_add_number
< 0x8000)
12971 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12976 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12977 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12982 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12983 else if (op
[2] == 0)
12984 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12987 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12988 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12993 if (imm_expr
.X_add_number
== 0)
12995 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13000 as_warn (_("instruction %s: result is always true"),
13001 ip
->insn_mo
->name
);
13002 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13003 op
[0], 0, BFD_RELOC_LO16
);
13006 if (CPU_HAS_SEQ (mips_opts
.arch
)
13007 && -512 <= imm_expr
.X_add_number
13008 && imm_expr
.X_add_number
< 512)
13010 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13011 (int) imm_expr
.X_add_number
);
13014 if (imm_expr
.X_add_number
>= 0
13015 && imm_expr
.X_add_number
< 0x10000)
13017 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13020 else if (imm_expr
.X_add_number
> -0x8000
13021 && imm_expr
.X_add_number
< 0)
13023 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13024 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13025 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13027 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13030 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13031 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13036 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13037 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13040 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13055 if (!mips_opts
.micromips
)
13057 if (imm_expr
.X_add_number
> -0x200
13058 && imm_expr
.X_add_number
<= 0x200)
13060 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13061 (int) -imm_expr
.X_add_number
);
13070 if (imm_expr
.X_add_number
> -0x8000
13071 && imm_expr
.X_add_number
<= 0x8000)
13073 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13074 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13079 load_register (AT
, &imm_expr
, dbl
);
13080 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13102 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13103 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13108 gas_assert (!mips_opts
.micromips
);
13109 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13113 * Is the double cfc1 instruction a bug in the mips assembler;
13114 * or is there a reason for it?
13116 start_noreorder ();
13117 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13118 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13119 macro_build (NULL
, "nop", "");
13120 expr1
.X_add_number
= 3;
13121 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13122 expr1
.X_add_number
= 2;
13123 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13124 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13125 macro_build (NULL
, "nop", "");
13126 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13128 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13129 macro_build (NULL
, "nop", "");
13146 offbits
= (mips_opts
.micromips
? 12 : 16);
13152 offbits
= (mips_opts
.micromips
? 12 : 16);
13164 offbits
= (mips_opts
.micromips
? 12 : 16);
13171 offbits
= (mips_opts
.micromips
? 12 : 16);
13177 large_offset
= !small_offset_p (off
, align
, offbits
);
13179 expr1
.X_add_number
= 0;
13184 if (small_offset_p (0, align
, 16))
13185 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13186 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13189 load_address (tempreg
, ep
, &used_at
);
13191 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13192 tempreg
, tempreg
, breg
);
13194 offset_reloc
[0] = BFD_RELOC_LO16
;
13195 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13196 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13201 else if (!ust
&& op
[0] == breg
)
13212 if (!target_big_endian
)
13213 ep
->X_add_number
+= off
;
13215 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13217 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13218 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13220 if (!target_big_endian
)
13221 ep
->X_add_number
-= off
;
13223 ep
->X_add_number
+= off
;
13225 macro_build (NULL
, s2
, "t,~(b)",
13226 tempreg
, (int) ep
->X_add_number
, breg
);
13228 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13229 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13231 /* If necessary, move the result in tempreg to the final destination. */
13232 if (!ust
&& op
[0] != tempreg
)
13234 /* Protect second load's delay slot. */
13236 move_register (op
[0], tempreg
);
13242 if (target_big_endian
== ust
)
13243 ep
->X_add_number
+= off
;
13244 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13245 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13246 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13248 /* For halfword transfers we need a temporary register to shuffle
13249 bytes. Unfortunately for M_USH_A we have none available before
13250 the next store as AT holds the base address. We deal with this
13251 case by clobbering TREG and then restoring it as with ULH. */
13252 tempreg
= ust
== large_offset
? op
[0] : AT
;
13254 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13256 if (target_big_endian
== ust
)
13257 ep
->X_add_number
-= off
;
13259 ep
->X_add_number
+= off
;
13260 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13261 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13263 /* For M_USH_A re-retrieve the LSB. */
13264 if (ust
&& large_offset
)
13266 if (target_big_endian
)
13267 ep
->X_add_number
+= off
;
13269 ep
->X_add_number
-= off
;
13270 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13271 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13273 /* For ULH and M_USH_A OR the LSB in. */
13274 if (!ust
|| large_offset
)
13276 tempreg
= !large_offset
? AT
: op
[0];
13277 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13278 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13283 /* FIXME: Check if this is one of the itbl macros, since they
13284 are added dynamically. */
13285 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13288 if (!mips_opts
.at
&& used_at
)
13289 as_bad (_("macro used $at after \".set noat\""));
13292 /* Implement macros in mips16 mode. */
13295 mips16_macro (struct mips_cl_insn
*ip
)
13297 const struct mips_operand_array
*operands
;
13302 const char *s
, *s2
, *s3
;
13303 unsigned int op
[MAX_OPERANDS
];
13306 mask
= ip
->insn_mo
->mask
;
13308 operands
= insn_operands (ip
);
13309 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13310 if (operands
->operand
[i
])
13311 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13315 expr1
.X_op
= O_constant
;
13316 expr1
.X_op_symbol
= NULL
;
13317 expr1
.X_add_symbol
= NULL
;
13318 expr1
.X_add_number
= 1;
13337 start_noreorder ();
13338 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
13339 expr1
.X_add_number
= 2;
13340 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13341 macro_build (NULL
, "break", "6", 7);
13343 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13344 since that causes an overflow. We should do that as well,
13345 but I don't see how to do the comparisons without a temporary
13348 macro_build (NULL
, s
, "x", op
[0]);
13367 start_noreorder ();
13368 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
13369 expr1
.X_add_number
= 2;
13370 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13371 macro_build (NULL
, "break", "6", 7);
13373 macro_build (NULL
, s2
, "x", op
[0]);
13379 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13380 macro_build (NULL
, "mflo", "x", op
[0]);
13388 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13389 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
13393 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13394 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13398 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13399 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13421 goto do_reverse_branch
;
13425 goto do_reverse_branch
;
13437 goto do_reverse_branch
;
13448 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13449 macro_build (&offset_expr
, s2
, "p");
13476 goto do_addone_branch_i
;
13481 goto do_addone_branch_i
;
13496 goto do_addone_branch_i
;
13502 do_addone_branch_i
:
13503 ++imm_expr
.X_add_number
;
13506 macro_build (&imm_expr
, s
, s3
, op
[0]);
13507 macro_build (&offset_expr
, s2
, "p");
13511 expr1
.X_add_number
= 0;
13512 macro_build (&expr1
, "slti", "x,8", op
[1]);
13513 if (op
[0] != op
[1])
13514 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13515 expr1
.X_add_number
= 2;
13516 macro_build (&expr1
, "bteqz", "p");
13517 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13522 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13523 opcode bits in *OPCODE_EXTRA. */
13525 static struct mips_opcode
*
13526 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13527 ssize_t length
, unsigned int *opcode_extra
)
13529 char *name
, *dot
, *p
;
13530 unsigned int mask
, suffix
;
13532 struct mips_opcode
*insn
;
13534 /* Make a copy of the instruction so that we can fiddle with it. */
13535 name
= xstrndup (start
, length
);
13537 /* Look up the instruction as-is. */
13538 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13542 dot
= strchr (name
, '.');
13545 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13546 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13547 if (*p
== 0 && mask
!= 0)
13550 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13552 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13554 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13560 if (mips_opts
.micromips
)
13562 /* See if there's an instruction size override suffix,
13563 either `16' or `32', at the end of the mnemonic proper,
13564 that defines the operation, i.e. before the first `.'
13565 character if any. Strip it and retry. */
13566 opend
= dot
!= NULL
? dot
- name
: length
;
13567 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13569 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13575 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13576 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13579 forced_insn_length
= suffix
;
13591 /* Assemble an instruction into its binary format. If the instruction
13592 is a macro, set imm_expr and offset_expr to the values associated
13593 with "I" and "A" operands respectively. Otherwise store the value
13594 of the relocatable field (if any) in offset_expr. In both cases
13595 set offset_reloc to the relocation operators applied to offset_expr. */
13598 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13600 const struct mips_opcode
*first
, *past
;
13601 struct hash_control
*hash
;
13604 struct mips_operand_token
*tokens
;
13605 unsigned int opcode_extra
;
13607 if (mips_opts
.micromips
)
13609 hash
= micromips_op_hash
;
13610 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13615 past
= &mips_opcodes
[NUMOPCODES
];
13617 forced_insn_length
= 0;
13620 /* We first try to match an instruction up to a space or to the end. */
13621 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13624 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13627 set_insn_error (0, _("unrecognized opcode"));
13631 if (strcmp (first
->name
, "li.s") == 0)
13633 else if (strcmp (first
->name
, "li.d") == 0)
13637 tokens
= mips_parse_arguments (str
+ end
, format
);
13641 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13642 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13643 set_insn_error (0, _("invalid operands"));
13645 obstack_free (&mips_operand_tokens
, tokens
);
13648 /* As for mips_ip, but used when assembling MIPS16 code.
13649 Also set forced_insn_length to the resulting instruction size in
13650 bytes if the user explicitly requested a small or extended instruction. */
13653 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13656 struct mips_opcode
*first
;
13657 struct mips_operand_token
*tokens
;
13659 forced_insn_length
= 0;
13661 for (s
= str
; ISLOWER (*s
); ++s
)
13675 if (s
[1] == 't' && s
[2] == ' ')
13677 forced_insn_length
= 2;
13681 else if (s
[1] == 'e' && s
[2] == ' ')
13683 forced_insn_length
= 4;
13687 /* Fall through. */
13689 set_insn_error (0, _("unrecognized opcode"));
13693 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13694 forced_insn_length
= 2;
13697 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13702 set_insn_error (0, _("unrecognized opcode"));
13706 tokens
= mips_parse_arguments (s
, 0);
13710 if (!match_mips16_insns (insn
, first
, tokens
))
13711 set_insn_error (0, _("invalid operands"));
13713 obstack_free (&mips_operand_tokens
, tokens
);
13716 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13717 NBITS is the number of significant bits in VAL. */
13719 static unsigned long
13720 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13725 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13728 else if (nbits
== 15)
13730 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13735 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13738 return (extval
<< 16) | val
;
13741 /* Like decode_mips16_operand, but require the operand to be defined and
13742 require it to be an integer. */
13744 static const struct mips_int_operand
*
13745 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13747 const struct mips_operand
*operand
;
13749 operand
= decode_mips16_operand (type
, extended_p
);
13750 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13752 return (const struct mips_int_operand
*) operand
;
13755 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13758 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13759 bfd_reloc_code_real_type reloc
, offsetT sval
)
13761 int min_val
, max_val
;
13763 min_val
= mips_int_operand_min (operand
);
13764 max_val
= mips_int_operand_max (operand
);
13765 if (reloc
!= BFD_RELOC_UNUSED
)
13768 sval
= SEXT_16BIT (sval
);
13773 return (sval
>= min_val
13775 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13778 /* Install immediate value VAL into MIPS16 instruction *INSN,
13779 extending it if necessary. The instruction in *INSN may
13780 already be extended.
13782 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13783 if none. In the former case, VAL is a 16-bit number with no
13784 defined signedness.
13786 TYPE is the type of the immediate field. USER_INSN_LENGTH
13787 is the length that the user requested, or 0 if none. */
13790 mips16_immed (const char *file
, unsigned int line
, int type
,
13791 bfd_reloc_code_real_type reloc
, offsetT val
,
13792 unsigned int user_insn_length
, unsigned long *insn
)
13794 const struct mips_int_operand
*operand
;
13795 unsigned int uval
, length
;
13797 operand
= mips16_immed_operand (type
, FALSE
);
13798 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13800 /* We need an extended instruction. */
13801 if (user_insn_length
== 2)
13802 as_bad_where (file
, line
, _("invalid unextended operand value"));
13804 *insn
|= MIPS16_EXTEND
;
13806 else if (user_insn_length
== 4)
13808 /* The operand doesn't force an unextended instruction to be extended.
13809 Warn if the user wanted an extended instruction anyway. */
13810 *insn
|= MIPS16_EXTEND
;
13811 as_warn_where (file
, line
,
13812 _("extended operand requested but not required"));
13815 length
= mips16_opcode_length (*insn
);
13818 operand
= mips16_immed_operand (type
, TRUE
);
13819 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13820 as_bad_where (file
, line
,
13821 _("operand value out of range for instruction"));
13823 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13825 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13827 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13830 struct percent_op_match
13833 bfd_reloc_code_real_type reloc
;
13836 static const struct percent_op_match mips_percent_op
[] =
13838 {"%lo", BFD_RELOC_LO16
},
13839 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13840 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13841 {"%call16", BFD_RELOC_MIPS_CALL16
},
13842 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13843 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13844 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13845 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13846 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13847 {"%got", BFD_RELOC_MIPS_GOT16
},
13848 {"%gp_rel", BFD_RELOC_GPREL16
},
13849 {"%half", BFD_RELOC_16
},
13850 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13851 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13852 {"%neg", BFD_RELOC_MIPS_SUB
},
13853 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13854 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13855 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13856 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13857 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13858 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13859 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13860 {"%hi", BFD_RELOC_HI16_S
},
13861 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
13862 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
13865 static const struct percent_op_match mips16_percent_op
[] =
13867 {"%lo", BFD_RELOC_MIPS16_LO16
},
13868 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13869 {"%got", BFD_RELOC_MIPS16_GOT16
},
13870 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13871 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13872 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13873 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13874 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13875 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13876 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13877 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13878 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13882 /* Return true if *STR points to a relocation operator. When returning true,
13883 move *STR over the operator and store its relocation code in *RELOC.
13884 Leave both *STR and *RELOC alone when returning false. */
13887 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13889 const struct percent_op_match
*percent_op
;
13892 if (mips_opts
.mips16
)
13894 percent_op
= mips16_percent_op
;
13895 limit
= ARRAY_SIZE (mips16_percent_op
);
13899 percent_op
= mips_percent_op
;
13900 limit
= ARRAY_SIZE (mips_percent_op
);
13903 for (i
= 0; i
< limit
; i
++)
13904 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13906 int len
= strlen (percent_op
[i
].str
);
13908 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13911 *str
+= strlen (percent_op
[i
].str
);
13912 *reloc
= percent_op
[i
].reloc
;
13914 /* Check whether the output BFD supports this relocation.
13915 If not, issue an error and fall back on something safe. */
13916 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13918 as_bad (_("relocation %s isn't supported by the current ABI"),
13919 percent_op
[i
].str
);
13920 *reloc
= BFD_RELOC_UNUSED
;
13928 /* Parse string STR as a 16-bit relocatable operand. Store the
13929 expression in *EP and the relocations in the array starting
13930 at RELOC. Return the number of relocation operators used.
13932 On exit, EXPR_END points to the first character after the expression. */
13935 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13938 bfd_reloc_code_real_type reversed_reloc
[3];
13939 size_t reloc_index
, i
;
13940 int crux_depth
, str_depth
;
13943 /* Search for the start of the main expression, recoding relocations
13944 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13945 of the main expression and with CRUX_DEPTH containing the number
13946 of open brackets at that point. */
13953 crux_depth
= str_depth
;
13955 /* Skip over whitespace and brackets, keeping count of the number
13957 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13962 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13963 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13965 my_getExpression (ep
, crux
);
13968 /* Match every open bracket. */
13969 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13973 if (crux_depth
> 0)
13974 as_bad (_("unclosed '('"));
13978 if (reloc_index
!= 0)
13980 prev_reloc_op_frag
= frag_now
;
13981 for (i
= 0; i
< reloc_index
; i
++)
13982 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13985 return reloc_index
;
13989 my_getExpression (expressionS
*ep
, char *str
)
13993 save_in
= input_line_pointer
;
13994 input_line_pointer
= str
;
13996 expr_end
= input_line_pointer
;
13997 input_line_pointer
= save_in
;
14001 md_atof (int type
, char *litP
, int *sizeP
)
14003 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14007 md_number_to_chars (char *buf
, valueT val
, int n
)
14009 if (target_big_endian
)
14010 number_to_chars_bigendian (buf
, val
, n
);
14012 number_to_chars_littleendian (buf
, val
, n
);
14015 static int support_64bit_objects(void)
14017 const char **list
, **l
;
14020 list
= bfd_target_list ();
14021 for (l
= list
; *l
!= NULL
; l
++)
14022 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14023 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14025 yes
= (*l
!= NULL
);
14030 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14031 NEW_VALUE. Warn if another value was already specified. Note:
14032 we have to defer parsing the -march and -mtune arguments in order
14033 to handle 'from-abi' correctly, since the ABI might be specified
14034 in a later argument. */
14037 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14039 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14040 as_warn (_("a different %s was already specified, is now %s"),
14041 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14044 *string_ptr
= new_value
;
14048 md_parse_option (int c
, const char *arg
)
14052 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14053 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14055 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14056 c
== mips_ases
[i
].option_on
);
14062 case OPTION_CONSTRUCT_FLOATS
:
14063 mips_disable_float_construction
= 0;
14066 case OPTION_NO_CONSTRUCT_FLOATS
:
14067 mips_disable_float_construction
= 1;
14079 target_big_endian
= 1;
14083 target_big_endian
= 0;
14089 else if (arg
[0] == '0')
14091 else if (arg
[0] == '1')
14101 mips_debug
= atoi (arg
);
14105 file_mips_opts
.isa
= ISA_MIPS1
;
14109 file_mips_opts
.isa
= ISA_MIPS2
;
14113 file_mips_opts
.isa
= ISA_MIPS3
;
14117 file_mips_opts
.isa
= ISA_MIPS4
;
14121 file_mips_opts
.isa
= ISA_MIPS5
;
14124 case OPTION_MIPS32
:
14125 file_mips_opts
.isa
= ISA_MIPS32
;
14128 case OPTION_MIPS32R2
:
14129 file_mips_opts
.isa
= ISA_MIPS32R2
;
14132 case OPTION_MIPS32R3
:
14133 file_mips_opts
.isa
= ISA_MIPS32R3
;
14136 case OPTION_MIPS32R5
:
14137 file_mips_opts
.isa
= ISA_MIPS32R5
;
14140 case OPTION_MIPS32R6
:
14141 file_mips_opts
.isa
= ISA_MIPS32R6
;
14144 case OPTION_MIPS64R2
:
14145 file_mips_opts
.isa
= ISA_MIPS64R2
;
14148 case OPTION_MIPS64R3
:
14149 file_mips_opts
.isa
= ISA_MIPS64R3
;
14152 case OPTION_MIPS64R5
:
14153 file_mips_opts
.isa
= ISA_MIPS64R5
;
14156 case OPTION_MIPS64R6
:
14157 file_mips_opts
.isa
= ISA_MIPS64R6
;
14160 case OPTION_MIPS64
:
14161 file_mips_opts
.isa
= ISA_MIPS64
;
14165 mips_set_option_string (&mips_tune_string
, arg
);
14169 mips_set_option_string (&mips_arch_string
, arg
);
14173 mips_set_option_string (&mips_arch_string
, "4650");
14174 mips_set_option_string (&mips_tune_string
, "4650");
14177 case OPTION_NO_M4650
:
14181 mips_set_option_string (&mips_arch_string
, "4010");
14182 mips_set_option_string (&mips_tune_string
, "4010");
14185 case OPTION_NO_M4010
:
14189 mips_set_option_string (&mips_arch_string
, "4100");
14190 mips_set_option_string (&mips_tune_string
, "4100");
14193 case OPTION_NO_M4100
:
14197 mips_set_option_string (&mips_arch_string
, "3900");
14198 mips_set_option_string (&mips_tune_string
, "3900");
14201 case OPTION_NO_M3900
:
14204 case OPTION_MICROMIPS
:
14205 if (file_mips_opts
.mips16
== 1)
14207 as_bad (_("-mmicromips cannot be used with -mips16"));
14210 file_mips_opts
.micromips
= 1;
14211 mips_no_prev_insn ();
14214 case OPTION_NO_MICROMIPS
:
14215 file_mips_opts
.micromips
= 0;
14216 mips_no_prev_insn ();
14219 case OPTION_MIPS16
:
14220 if (file_mips_opts
.micromips
== 1)
14222 as_bad (_("-mips16 cannot be used with -micromips"));
14225 file_mips_opts
.mips16
= 1;
14226 mips_no_prev_insn ();
14229 case OPTION_NO_MIPS16
:
14230 file_mips_opts
.mips16
= 0;
14231 mips_no_prev_insn ();
14234 case OPTION_FIX_24K
:
14238 case OPTION_NO_FIX_24K
:
14242 case OPTION_FIX_RM7000
:
14243 mips_fix_rm7000
= 1;
14246 case OPTION_NO_FIX_RM7000
:
14247 mips_fix_rm7000
= 0;
14250 case OPTION_FIX_LOONGSON2F_JUMP
:
14251 mips_fix_loongson2f_jump
= TRUE
;
14254 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14255 mips_fix_loongson2f_jump
= FALSE
;
14258 case OPTION_FIX_LOONGSON2F_NOP
:
14259 mips_fix_loongson2f_nop
= TRUE
;
14262 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14263 mips_fix_loongson2f_nop
= FALSE
;
14266 case OPTION_FIX_VR4120
:
14267 mips_fix_vr4120
= 1;
14270 case OPTION_NO_FIX_VR4120
:
14271 mips_fix_vr4120
= 0;
14274 case OPTION_FIX_VR4130
:
14275 mips_fix_vr4130
= 1;
14278 case OPTION_NO_FIX_VR4130
:
14279 mips_fix_vr4130
= 0;
14282 case OPTION_FIX_CN63XXP1
:
14283 mips_fix_cn63xxp1
= TRUE
;
14286 case OPTION_NO_FIX_CN63XXP1
:
14287 mips_fix_cn63xxp1
= FALSE
;
14290 case OPTION_RELAX_BRANCH
:
14291 mips_relax_branch
= 1;
14294 case OPTION_NO_RELAX_BRANCH
:
14295 mips_relax_branch
= 0;
14298 case OPTION_INSN32
:
14299 file_mips_opts
.insn32
= TRUE
;
14302 case OPTION_NO_INSN32
:
14303 file_mips_opts
.insn32
= FALSE
;
14306 case OPTION_MSHARED
:
14307 mips_in_shared
= TRUE
;
14310 case OPTION_MNO_SHARED
:
14311 mips_in_shared
= FALSE
;
14314 case OPTION_MSYM32
:
14315 file_mips_opts
.sym32
= TRUE
;
14318 case OPTION_MNO_SYM32
:
14319 file_mips_opts
.sym32
= FALSE
;
14322 /* When generating ELF code, we permit -KPIC and -call_shared to
14323 select SVR4_PIC, and -non_shared to select no PIC. This is
14324 intended to be compatible with Irix 5. */
14325 case OPTION_CALL_SHARED
:
14326 mips_pic
= SVR4_PIC
;
14327 mips_abicalls
= TRUE
;
14330 case OPTION_CALL_NONPIC
:
14332 mips_abicalls
= TRUE
;
14335 case OPTION_NON_SHARED
:
14337 mips_abicalls
= FALSE
;
14340 /* The -xgot option tells the assembler to use 32 bit offsets
14341 when accessing the got in SVR4_PIC mode. It is for Irix
14348 g_switch_value
= atoi (arg
);
14352 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14355 mips_abi
= O32_ABI
;
14359 mips_abi
= N32_ABI
;
14363 mips_abi
= N64_ABI
;
14364 if (!support_64bit_objects())
14365 as_fatal (_("no compiled in support for 64 bit object file format"));
14369 file_mips_opts
.gp
= 32;
14373 file_mips_opts
.gp
= 64;
14377 file_mips_opts
.fp
= 32;
14381 file_mips_opts
.fp
= 0;
14385 file_mips_opts
.fp
= 64;
14388 case OPTION_ODD_SPREG
:
14389 file_mips_opts
.oddspreg
= 1;
14392 case OPTION_NO_ODD_SPREG
:
14393 file_mips_opts
.oddspreg
= 0;
14396 case OPTION_SINGLE_FLOAT
:
14397 file_mips_opts
.single_float
= 1;
14400 case OPTION_DOUBLE_FLOAT
:
14401 file_mips_opts
.single_float
= 0;
14404 case OPTION_SOFT_FLOAT
:
14405 file_mips_opts
.soft_float
= 1;
14408 case OPTION_HARD_FLOAT
:
14409 file_mips_opts
.soft_float
= 0;
14413 if (strcmp (arg
, "32") == 0)
14414 mips_abi
= O32_ABI
;
14415 else if (strcmp (arg
, "o64") == 0)
14416 mips_abi
= O64_ABI
;
14417 else if (strcmp (arg
, "n32") == 0)
14418 mips_abi
= N32_ABI
;
14419 else if (strcmp (arg
, "64") == 0)
14421 mips_abi
= N64_ABI
;
14422 if (! support_64bit_objects())
14423 as_fatal (_("no compiled in support for 64 bit object file "
14426 else if (strcmp (arg
, "eabi") == 0)
14427 mips_abi
= EABI_ABI
;
14430 as_fatal (_("invalid abi -mabi=%s"), arg
);
14435 case OPTION_M7000_HILO_FIX
:
14436 mips_7000_hilo_fix
= TRUE
;
14439 case OPTION_MNO_7000_HILO_FIX
:
14440 mips_7000_hilo_fix
= FALSE
;
14443 case OPTION_MDEBUG
:
14444 mips_flag_mdebug
= TRUE
;
14447 case OPTION_NO_MDEBUG
:
14448 mips_flag_mdebug
= FALSE
;
14452 mips_flag_pdr
= TRUE
;
14455 case OPTION_NO_PDR
:
14456 mips_flag_pdr
= FALSE
;
14459 case OPTION_MVXWORKS_PIC
:
14460 mips_pic
= VXWORKS_PIC
;
14464 if (strcmp (arg
, "2008") == 0)
14466 else if (strcmp (arg
, "legacy") == 0)
14470 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14479 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14484 /* Set up globals to tune for the ISA or processor described by INFO. */
14487 mips_set_tune (const struct mips_cpu_info
*info
)
14490 mips_tune
= info
->cpu
;
14495 mips_after_parse_args (void)
14497 const struct mips_cpu_info
*arch_info
= 0;
14498 const struct mips_cpu_info
*tune_info
= 0;
14500 /* GP relative stuff not working for PE */
14501 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14503 if (g_switch_seen
&& g_switch_value
!= 0)
14504 as_bad (_("-G not supported in this configuration"));
14505 g_switch_value
= 0;
14508 if (mips_abi
== NO_ABI
)
14509 mips_abi
= MIPS_DEFAULT_ABI
;
14511 /* The following code determines the architecture.
14512 Similar code was added to GCC 3.3 (see override_options() in
14513 config/mips/mips.c). The GAS and GCC code should be kept in sync
14514 as much as possible. */
14516 if (mips_arch_string
!= 0)
14517 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14519 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14521 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14522 ISA level specified by -mipsN, while arch_info->isa contains
14523 the -march selection (if any). */
14524 if (arch_info
!= 0)
14526 /* -march takes precedence over -mipsN, since it is more descriptive.
14527 There's no harm in specifying both as long as the ISA levels
14529 if (file_mips_opts
.isa
!= arch_info
->isa
)
14530 as_bad (_("-%s conflicts with the other architecture options,"
14531 " which imply -%s"),
14532 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14533 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14536 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14539 if (arch_info
== 0)
14541 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14542 gas_assert (arch_info
);
14545 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14546 as_bad (_("-march=%s is not compatible with the selected ABI"),
14549 file_mips_opts
.arch
= arch_info
->cpu
;
14550 file_mips_opts
.isa
= arch_info
->isa
;
14552 /* Set up initial mips_opts state. */
14553 mips_opts
= file_mips_opts
;
14555 /* The register size inference code is now placed in
14556 file_mips_check_options. */
14558 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14560 if (mips_tune_string
!= 0)
14561 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14563 if (tune_info
== 0)
14564 mips_set_tune (arch_info
);
14566 mips_set_tune (tune_info
);
14568 if (mips_flag_mdebug
< 0)
14569 mips_flag_mdebug
= 0;
14573 mips_init_after_args (void)
14575 /* initialize opcodes */
14576 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14577 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14581 md_pcrel_from (fixS
*fixP
)
14583 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14584 switch (fixP
->fx_r_type
)
14586 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14587 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14588 /* Return the address of the delay slot. */
14591 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14592 case BFD_RELOC_MICROMIPS_JMP
:
14593 case BFD_RELOC_16_PCREL_S2
:
14594 case BFD_RELOC_MIPS_21_PCREL_S2
:
14595 case BFD_RELOC_MIPS_26_PCREL_S2
:
14596 case BFD_RELOC_MIPS_JMP
:
14597 /* Return the address of the delay slot. */
14605 /* This is called before the symbol table is processed. In order to
14606 work with gcc when using mips-tfile, we must keep all local labels.
14607 However, in other cases, we want to discard them. If we were
14608 called with -g, but we didn't see any debugging information, it may
14609 mean that gcc is smuggling debugging information through to
14610 mips-tfile, in which case we must generate all local labels. */
14613 mips_frob_file_before_adjust (void)
14615 #ifndef NO_ECOFF_DEBUGGING
14616 if (ECOFF_DEBUGGING
14618 && ! ecoff_debugging_seen
)
14619 flag_keep_locals
= 1;
14623 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14624 the corresponding LO16 reloc. This is called before md_apply_fix and
14625 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14626 relocation operators.
14628 For our purposes, a %lo() expression matches a %got() or %hi()
14631 (a) it refers to the same symbol; and
14632 (b) the offset applied in the %lo() expression is no lower than
14633 the offset applied in the %got() or %hi().
14635 (b) allows us to cope with code like:
14638 lh $4,%lo(foo+2)($4)
14640 ...which is legal on RELA targets, and has a well-defined behaviour
14641 if the user knows that adding 2 to "foo" will not induce a carry to
14644 When several %lo()s match a particular %got() or %hi(), we use the
14645 following rules to distinguish them:
14647 (1) %lo()s with smaller offsets are a better match than %lo()s with
14650 (2) %lo()s with no matching %got() or %hi() are better than those
14651 that already have a matching %got() or %hi().
14653 (3) later %lo()s are better than earlier %lo()s.
14655 These rules are applied in order.
14657 (1) means, among other things, that %lo()s with identical offsets are
14658 chosen if they exist.
14660 (2) means that we won't associate several high-part relocations with
14661 the same low-part relocation unless there's no alternative. Having
14662 several high parts for the same low part is a GNU extension; this rule
14663 allows careful users to avoid it.
14665 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14666 with the last high-part relocation being at the front of the list.
14667 It therefore makes sense to choose the last matching low-part
14668 relocation, all other things being equal. It's also easier
14669 to code that way. */
14672 mips_frob_file (void)
14674 struct mips_hi_fixup
*l
;
14675 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14677 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14679 segment_info_type
*seginfo
;
14680 bfd_boolean matched_lo_p
;
14681 fixS
**hi_pos
, **lo_pos
, **pos
;
14683 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14685 /* If a GOT16 relocation turns out to be against a global symbol,
14686 there isn't supposed to be a matching LO. Ignore %gots against
14687 constants; we'll report an error for those later. */
14688 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14689 && !(l
->fixp
->fx_addsy
14690 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14693 /* Check quickly whether the next fixup happens to be a matching %lo. */
14694 if (fixup_has_matching_lo_p (l
->fixp
))
14697 seginfo
= seg_info (l
->seg
);
14699 /* Set HI_POS to the position of this relocation in the chain.
14700 Set LO_POS to the position of the chosen low-part relocation.
14701 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14702 relocation that matches an immediately-preceding high-part
14706 matched_lo_p
= FALSE
;
14707 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14709 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14711 if (*pos
== l
->fixp
)
14714 if ((*pos
)->fx_r_type
== looking_for_rtype
14715 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14716 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14718 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14720 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14723 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14724 && fixup_has_matching_lo_p (*pos
));
14727 /* If we found a match, remove the high-part relocation from its
14728 current position and insert it before the low-part relocation.
14729 Make the offsets match so that fixup_has_matching_lo_p()
14732 We don't warn about unmatched high-part relocations since some
14733 versions of gcc have been known to emit dead "lui ...%hi(...)"
14735 if (lo_pos
!= NULL
)
14737 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14738 if (l
->fixp
->fx_next
!= *lo_pos
)
14740 *hi_pos
= l
->fixp
->fx_next
;
14741 l
->fixp
->fx_next
= *lo_pos
;
14749 mips_force_relocation (fixS
*fixp
)
14751 if (generic_force_reloc (fixp
))
14754 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14755 so that the linker relaxation can update targets. */
14756 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14757 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14758 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14761 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14762 if (ISA_IS_R6 (mips_opts
.isa
)
14763 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14764 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
14765 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
14766 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
14767 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
14768 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
14769 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
14775 /* Read the instruction associated with RELOC from BUF. */
14777 static unsigned int
14778 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14780 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14781 return read_compressed_insn (buf
, 4);
14783 return read_insn (buf
);
14786 /* Write instruction INSN to BUF, given that it has been relocated
14790 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14791 unsigned long insn
)
14793 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14794 write_compressed_insn (buf
, insn
, 4);
14796 write_insn (buf
, insn
);
14799 /* Apply a fixup to the object file. */
14802 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14805 unsigned long insn
;
14806 reloc_howto_type
*howto
;
14808 if (fixP
->fx_pcrel
)
14809 switch (fixP
->fx_r_type
)
14811 case BFD_RELOC_16_PCREL_S2
:
14812 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14813 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14814 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14815 case BFD_RELOC_32_PCREL
:
14816 case BFD_RELOC_MIPS_21_PCREL_S2
:
14817 case BFD_RELOC_MIPS_26_PCREL_S2
:
14818 case BFD_RELOC_MIPS_18_PCREL_S3
:
14819 case BFD_RELOC_MIPS_19_PCREL_S2
:
14820 case BFD_RELOC_HI16_S_PCREL
:
14821 case BFD_RELOC_LO16_PCREL
:
14825 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
14829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14830 _("PC-relative reference to a different section"));
14834 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14835 that have no MIPS ELF equivalent. */
14836 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
14838 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14843 gas_assert (fixP
->fx_size
== 2
14844 || fixP
->fx_size
== 4
14845 || fixP
->fx_r_type
== BFD_RELOC_8
14846 || fixP
->fx_r_type
== BFD_RELOC_16
14847 || fixP
->fx_r_type
== BFD_RELOC_64
14848 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14849 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14850 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14851 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14852 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14853 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
14854 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
14856 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14858 /* Don't treat parts of a composite relocation as done. There are two
14861 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14862 should nevertheless be emitted if the first part is.
14864 (2) In normal usage, composite relocations are never assembly-time
14865 constants. The easiest way of dealing with the pathological
14866 exceptions is to generate a relocation against STN_UNDEF and
14867 leave everything up to the linker. */
14868 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14871 switch (fixP
->fx_r_type
)
14873 case BFD_RELOC_MIPS_TLS_GD
:
14874 case BFD_RELOC_MIPS_TLS_LDM
:
14875 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14876 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14877 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14878 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14879 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14880 case BFD_RELOC_MIPS_TLS_TPREL32
:
14881 case BFD_RELOC_MIPS_TLS_TPREL64
:
14882 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14883 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14884 case BFD_RELOC_MICROMIPS_TLS_GD
:
14885 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14886 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14887 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14888 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14889 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14890 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14891 case BFD_RELOC_MIPS16_TLS_GD
:
14892 case BFD_RELOC_MIPS16_TLS_LDM
:
14893 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14894 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14895 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14896 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14897 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14898 if (!fixP
->fx_addsy
)
14900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14901 _("TLS relocation against a constant"));
14904 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14907 case BFD_RELOC_MIPS_JMP
:
14908 case BFD_RELOC_MIPS_SHIFT5
:
14909 case BFD_RELOC_MIPS_SHIFT6
:
14910 case BFD_RELOC_MIPS_GOT_DISP
:
14911 case BFD_RELOC_MIPS_GOT_PAGE
:
14912 case BFD_RELOC_MIPS_GOT_OFST
:
14913 case BFD_RELOC_MIPS_SUB
:
14914 case BFD_RELOC_MIPS_INSERT_A
:
14915 case BFD_RELOC_MIPS_INSERT_B
:
14916 case BFD_RELOC_MIPS_DELETE
:
14917 case BFD_RELOC_MIPS_HIGHEST
:
14918 case BFD_RELOC_MIPS_HIGHER
:
14919 case BFD_RELOC_MIPS_SCN_DISP
:
14920 case BFD_RELOC_MIPS_REL16
:
14921 case BFD_RELOC_MIPS_RELGOT
:
14922 case BFD_RELOC_MIPS_JALR
:
14923 case BFD_RELOC_HI16
:
14924 case BFD_RELOC_HI16_S
:
14925 case BFD_RELOC_LO16
:
14926 case BFD_RELOC_GPREL16
:
14927 case BFD_RELOC_MIPS_LITERAL
:
14928 case BFD_RELOC_MIPS_CALL16
:
14929 case BFD_RELOC_MIPS_GOT16
:
14930 case BFD_RELOC_GPREL32
:
14931 case BFD_RELOC_MIPS_GOT_HI16
:
14932 case BFD_RELOC_MIPS_GOT_LO16
:
14933 case BFD_RELOC_MIPS_CALL_HI16
:
14934 case BFD_RELOC_MIPS_CALL_LO16
:
14935 case BFD_RELOC_MIPS16_GPREL
:
14936 case BFD_RELOC_MIPS16_GOT16
:
14937 case BFD_RELOC_MIPS16_CALL16
:
14938 case BFD_RELOC_MIPS16_HI16
:
14939 case BFD_RELOC_MIPS16_HI16_S
:
14940 case BFD_RELOC_MIPS16_LO16
:
14941 case BFD_RELOC_MIPS16_JMP
:
14942 case BFD_RELOC_MICROMIPS_JMP
:
14943 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14944 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14945 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14946 case BFD_RELOC_MICROMIPS_SUB
:
14947 case BFD_RELOC_MICROMIPS_HIGHEST
:
14948 case BFD_RELOC_MICROMIPS_HIGHER
:
14949 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14950 case BFD_RELOC_MICROMIPS_JALR
:
14951 case BFD_RELOC_MICROMIPS_HI16
:
14952 case BFD_RELOC_MICROMIPS_HI16_S
:
14953 case BFD_RELOC_MICROMIPS_LO16
:
14954 case BFD_RELOC_MICROMIPS_GPREL16
:
14955 case BFD_RELOC_MICROMIPS_LITERAL
:
14956 case BFD_RELOC_MICROMIPS_CALL16
:
14957 case BFD_RELOC_MICROMIPS_GOT16
:
14958 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14959 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14960 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14961 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14962 case BFD_RELOC_MIPS_EH
:
14967 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14969 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14970 if (mips16_reloc_p (fixP
->fx_r_type
))
14971 insn
|= mips16_immed_extend (value
, 16);
14973 insn
|= (value
& 0xffff);
14974 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14978 _("unsupported constant in relocation"));
14983 /* This is handled like BFD_RELOC_32, but we output a sign
14984 extended value if we are only 32 bits. */
14987 if (8 <= sizeof (valueT
))
14988 md_number_to_chars (buf
, *valP
, 8);
14993 if ((*valP
& 0x80000000) != 0)
14997 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14998 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15003 case BFD_RELOC_RVA
:
15005 case BFD_RELOC_32_PCREL
:
15008 /* If we are deleting this reloc entry, we must fill in the
15009 value now. This can happen if we have a .word which is not
15010 resolved when it appears but is later defined. */
15012 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15015 case BFD_RELOC_MIPS_21_PCREL_S2
:
15016 case BFD_RELOC_MIPS_26_PCREL_S2
:
15017 if ((*valP
& 0x3) != 0)
15018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15019 _("branch to misaligned address (%lx)"), (long) *valP
);
15021 gas_assert (!fixP
->fx_done
);
15024 case BFD_RELOC_MIPS_18_PCREL_S3
:
15025 if ((S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15027 _("PC-relative access using misaligned symbol (%lx)"),
15028 (long) S_GET_VALUE (fixP
->fx_addsy
));
15029 if ((fixP
->fx_offset
& 0x7) != 0)
15030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15031 _("PC-relative access using misaligned offset (%lx)"),
15032 (long) fixP
->fx_offset
);
15034 gas_assert (!fixP
->fx_done
);
15037 case BFD_RELOC_MIPS_19_PCREL_S2
:
15038 if ((*valP
& 0x3) != 0)
15039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15040 _("PC-relative access to misaligned address (%lx)"),
15041 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15043 gas_assert (!fixP
->fx_done
);
15046 case BFD_RELOC_HI16_S_PCREL
:
15047 case BFD_RELOC_LO16_PCREL
:
15048 gas_assert (!fixP
->fx_done
);
15051 case BFD_RELOC_16_PCREL_S2
:
15052 if ((*valP
& 0x3) != 0)
15053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15054 _("branch to misaligned address (%lx)"), (long) *valP
);
15056 /* We need to save the bits in the instruction since fixup_segment()
15057 might be deleting the relocation entry (i.e., a branch within
15058 the current segment). */
15059 if (! fixP
->fx_done
)
15062 /* Update old instruction data. */
15063 insn
= read_insn (buf
);
15065 if (*valP
+ 0x20000 <= 0x3ffff)
15067 insn
|= (*valP
>> 2) & 0xffff;
15068 write_insn (buf
, insn
);
15070 else if (mips_pic
== NO_PIC
15072 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15073 && (fixP
->fx_frag
->fr_address
15074 < text_section
->vma
+ bfd_get_section_size (text_section
))
15075 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15076 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15077 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15079 /* The branch offset is too large. If this is an
15080 unconditional branch, and we are not generating PIC code,
15081 we can convert it to an absolute jump instruction. */
15082 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15083 insn
= 0x0c000000; /* jal */
15085 insn
= 0x08000000; /* j */
15086 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15088 fixP
->fx_addsy
= section_symbol (text_section
);
15089 *valP
+= md_pcrel_from (fixP
);
15090 write_insn (buf
, insn
);
15094 /* If we got here, we have branch-relaxation disabled,
15095 and there's nothing we can do to fix this instruction
15096 without turning it into a longer sequence. */
15097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15098 _("branch out of range"));
15102 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15103 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15104 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15105 /* We adjust the offset back to even. */
15106 if ((*valP
& 0x1) != 0)
15109 if (! fixP
->fx_done
)
15112 /* Should never visit here, because we keep the relocation. */
15116 case BFD_RELOC_VTABLE_INHERIT
:
15119 && !S_IS_DEFINED (fixP
->fx_addsy
)
15120 && !S_IS_WEAK (fixP
->fx_addsy
))
15121 S_SET_WEAK (fixP
->fx_addsy
);
15124 case BFD_RELOC_NONE
:
15125 case BFD_RELOC_VTABLE_ENTRY
:
15133 /* Remember value for tc_gen_reloc. */
15134 fixP
->fx_addnumber
= *valP
;
15144 c
= get_symbol_name (&name
);
15145 p
= (symbolS
*) symbol_find_or_make (name
);
15146 (void) restore_line_pointer (c
);
15150 /* Align the current frag to a given power of two. If a particular
15151 fill byte should be used, FILL points to an integer that contains
15152 that byte, otherwise FILL is null.
15154 This function used to have the comment:
15156 The MIPS assembler also automatically adjusts any preceding label.
15158 The implementation therefore applied the adjustment to a maximum of
15159 one label. However, other label adjustments are applied to batches
15160 of labels, and adjusting just one caused problems when new labels
15161 were added for the sake of debugging or unwind information.
15162 We therefore adjust all preceding labels (given as LABELS) instead. */
15165 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15167 mips_emit_delays ();
15168 mips_record_compressed_mode ();
15169 if (fill
== NULL
&& subseg_text_p (now_seg
))
15170 frag_align_code (to
, 0);
15172 frag_align (to
, fill
? *fill
: 0, 0);
15173 record_alignment (now_seg
, to
);
15174 mips_move_labels (labels
, FALSE
);
15177 /* Align to a given power of two. .align 0 turns off the automatic
15178 alignment used by the data creating pseudo-ops. */
15181 s_align (int x ATTRIBUTE_UNUSED
)
15183 int temp
, fill_value
, *fill_ptr
;
15184 long max_alignment
= 28;
15186 /* o Note that the assembler pulls down any immediately preceding label
15187 to the aligned address.
15188 o It's not documented but auto alignment is reinstated by
15189 a .align pseudo instruction.
15190 o Note also that after auto alignment is turned off the mips assembler
15191 issues an error on attempt to assemble an improperly aligned data item.
15194 temp
= get_absolute_expression ();
15195 if (temp
> max_alignment
)
15196 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15199 as_warn (_("alignment negative, 0 assumed"));
15202 if (*input_line_pointer
== ',')
15204 ++input_line_pointer
;
15205 fill_value
= get_absolute_expression ();
15206 fill_ptr
= &fill_value
;
15212 segment_info_type
*si
= seg_info (now_seg
);
15213 struct insn_label_list
*l
= si
->label_list
;
15214 /* Auto alignment should be switched on by next section change. */
15216 mips_align (temp
, fill_ptr
, l
);
15223 demand_empty_rest_of_line ();
15227 s_change_sec (int sec
)
15231 /* The ELF backend needs to know that we are changing sections, so
15232 that .previous works correctly. We could do something like check
15233 for an obj_section_change_hook macro, but that might be confusing
15234 as it would not be appropriate to use it in the section changing
15235 functions in read.c, since obj-elf.c intercepts those. FIXME:
15236 This should be cleaner, somehow. */
15237 obj_elf_section_change_hook ();
15239 mips_emit_delays ();
15250 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15251 demand_empty_rest_of_line ();
15255 seg
= subseg_new (RDATA_SECTION_NAME
,
15256 (subsegT
) get_absolute_expression ());
15257 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15258 | SEC_READONLY
| SEC_RELOC
15260 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15261 record_alignment (seg
, 4);
15262 demand_empty_rest_of_line ();
15266 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15267 bfd_set_section_flags (stdoutput
, seg
,
15268 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15269 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15270 record_alignment (seg
, 4);
15271 demand_empty_rest_of_line ();
15275 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15276 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15277 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15278 record_alignment (seg
, 4);
15279 demand_empty_rest_of_line ();
15287 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15290 char *section_name
;
15295 int section_entry_size
;
15296 int section_alignment
;
15298 saved_ilp
= input_line_pointer
;
15299 endc
= get_symbol_name (§ion_name
);
15300 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
15302 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
15304 /* Do we have .section Name<,"flags">? */
15305 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15307 /* Just after name is now '\0'. */
15308 (void) restore_line_pointer (endc
);
15309 input_line_pointer
= saved_ilp
;
15310 obj_elf_section (ignore
);
15314 section_name
= xstrdup (section_name
);
15315 c
= restore_line_pointer (endc
);
15317 input_line_pointer
++;
15319 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15321 section_type
= get_absolute_expression ();
15325 if (*input_line_pointer
++ == ',')
15326 section_flag
= get_absolute_expression ();
15330 if (*input_line_pointer
++ == ',')
15331 section_entry_size
= get_absolute_expression ();
15333 section_entry_size
= 0;
15335 if (*input_line_pointer
++ == ',')
15336 section_alignment
= get_absolute_expression ();
15338 section_alignment
= 0;
15340 /* FIXME: really ignore? */
15341 (void) section_alignment
;
15343 /* When using the generic form of .section (as implemented by obj-elf.c),
15344 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15345 traditionally had to fall back on the more common @progbits instead.
15347 There's nothing really harmful in this, since bfd will correct
15348 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15349 means that, for backwards compatibility, the special_section entries
15350 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15352 Even so, we shouldn't force users of the MIPS .section syntax to
15353 incorrectly label the sections as SHT_PROGBITS. The best compromise
15354 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15355 generic type-checking code. */
15356 if (section_type
== SHT_MIPS_DWARF
)
15357 section_type
= SHT_PROGBITS
;
15359 obj_elf_change_section (section_name
, section_type
, section_flag
,
15360 section_entry_size
, 0, 0, 0);
15362 if (now_seg
->name
!= section_name
)
15363 free (section_name
);
15367 mips_enable_auto_align (void)
15373 s_cons (int log_size
)
15375 segment_info_type
*si
= seg_info (now_seg
);
15376 struct insn_label_list
*l
= si
->label_list
;
15378 mips_emit_delays ();
15379 if (log_size
> 0 && auto_align
)
15380 mips_align (log_size
, 0, l
);
15381 cons (1 << log_size
);
15382 mips_clear_insn_labels ();
15386 s_float_cons (int type
)
15388 segment_info_type
*si
= seg_info (now_seg
);
15389 struct insn_label_list
*l
= si
->label_list
;
15391 mips_emit_delays ();
15396 mips_align (3, 0, l
);
15398 mips_align (2, 0, l
);
15402 mips_clear_insn_labels ();
15405 /* Handle .globl. We need to override it because on Irix 5 you are
15408 where foo is an undefined symbol, to mean that foo should be
15409 considered to be the address of a function. */
15412 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15421 c
= get_symbol_name (&name
);
15422 symbolP
= symbol_find_or_make (name
);
15423 S_SET_EXTERNAL (symbolP
);
15425 *input_line_pointer
= c
;
15426 SKIP_WHITESPACE_AFTER_NAME ();
15428 /* On Irix 5, every global symbol that is not explicitly labelled as
15429 being a function is apparently labelled as being an object. */
15432 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15433 && (*input_line_pointer
!= ','))
15438 c
= get_symbol_name (&secname
);
15439 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15441 as_bad (_("%s: no such section"), secname
);
15442 (void) restore_line_pointer (c
);
15444 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15445 flag
= BSF_FUNCTION
;
15448 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15450 c
= *input_line_pointer
;
15453 input_line_pointer
++;
15454 SKIP_WHITESPACE ();
15455 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
15461 demand_empty_rest_of_line ();
15465 s_option (int x ATTRIBUTE_UNUSED
)
15470 c
= get_symbol_name (&opt
);
15474 /* FIXME: What does this mean? */
15476 else if (strncmp (opt
, "pic", 3) == 0)
15480 i
= atoi (opt
+ 3);
15485 mips_pic
= SVR4_PIC
;
15486 mips_abicalls
= TRUE
;
15489 as_bad (_(".option pic%d not supported"), i
);
15491 if (mips_pic
== SVR4_PIC
)
15493 if (g_switch_seen
&& g_switch_value
!= 0)
15494 as_warn (_("-G may not be used with SVR4 PIC code"));
15495 g_switch_value
= 0;
15496 bfd_set_gp_size (stdoutput
, 0);
15500 as_warn (_("unrecognized option \"%s\""), opt
);
15502 (void) restore_line_pointer (c
);
15503 demand_empty_rest_of_line ();
15506 /* This structure is used to hold a stack of .set values. */
15508 struct mips_option_stack
15510 struct mips_option_stack
*next
;
15511 struct mips_set_options options
;
15514 static struct mips_option_stack
*mips_opts_stack
;
15517 parse_code_option (char * name
)
15519 const struct mips_ase
*ase
;
15520 if (strncmp (name
, "at=", 3) == 0)
15522 char *s
= name
+ 3;
15524 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15525 as_bad (_("unrecognized register name `%s'"), s
);
15527 else if (strcmp (name
, "at") == 0)
15528 mips_opts
.at
= ATREG
;
15529 else if (strcmp (name
, "noat") == 0)
15530 mips_opts
.at
= ZERO
;
15531 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15532 mips_opts
.nomove
= 0;
15533 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15534 mips_opts
.nomove
= 1;
15535 else if (strcmp (name
, "bopt") == 0)
15536 mips_opts
.nobopt
= 0;
15537 else if (strcmp (name
, "nobopt") == 0)
15538 mips_opts
.nobopt
= 1;
15539 else if (strcmp (name
, "gp=32") == 0)
15541 else if (strcmp (name
, "gp=64") == 0)
15543 else if (strcmp (name
, "fp=32") == 0)
15545 else if (strcmp (name
, "fp=xx") == 0)
15547 else if (strcmp (name
, "fp=64") == 0)
15549 else if (strcmp (name
, "softfloat") == 0)
15550 mips_opts
.soft_float
= 1;
15551 else if (strcmp (name
, "hardfloat") == 0)
15552 mips_opts
.soft_float
= 0;
15553 else if (strcmp (name
, "singlefloat") == 0)
15554 mips_opts
.single_float
= 1;
15555 else if (strcmp (name
, "doublefloat") == 0)
15556 mips_opts
.single_float
= 0;
15557 else if (strcmp (name
, "nooddspreg") == 0)
15558 mips_opts
.oddspreg
= 0;
15559 else if (strcmp (name
, "oddspreg") == 0)
15560 mips_opts
.oddspreg
= 1;
15561 else if (strcmp (name
, "mips16") == 0
15562 || strcmp (name
, "MIPS-16") == 0)
15563 mips_opts
.mips16
= 1;
15564 else if (strcmp (name
, "nomips16") == 0
15565 || strcmp (name
, "noMIPS-16") == 0)
15566 mips_opts
.mips16
= 0;
15567 else if (strcmp (name
, "micromips") == 0)
15568 mips_opts
.micromips
= 1;
15569 else if (strcmp (name
, "nomicromips") == 0)
15570 mips_opts
.micromips
= 0;
15571 else if (name
[0] == 'n'
15573 && (ase
= mips_lookup_ase (name
+ 2)))
15574 mips_set_ase (ase
, &mips_opts
, FALSE
);
15575 else if ((ase
= mips_lookup_ase (name
)))
15576 mips_set_ase (ase
, &mips_opts
, TRUE
);
15577 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15579 /* Permit the user to change the ISA and architecture on the fly.
15580 Needless to say, misuse can cause serious problems. */
15581 if (strncmp (name
, "arch=", 5) == 0)
15583 const struct mips_cpu_info
*p
;
15585 p
= mips_parse_cpu ("internal use", name
+ 5);
15587 as_bad (_("unknown architecture %s"), name
+ 5);
15590 mips_opts
.arch
= p
->cpu
;
15591 mips_opts
.isa
= p
->isa
;
15594 else if (strncmp (name
, "mips", 4) == 0)
15596 const struct mips_cpu_info
*p
;
15598 p
= mips_parse_cpu ("internal use", name
);
15600 as_bad (_("unknown ISA level %s"), name
+ 4);
15603 mips_opts
.arch
= p
->cpu
;
15604 mips_opts
.isa
= p
->isa
;
15608 as_bad (_("unknown ISA or architecture %s"), name
);
15610 else if (strcmp (name
, "autoextend") == 0)
15611 mips_opts
.noautoextend
= 0;
15612 else if (strcmp (name
, "noautoextend") == 0)
15613 mips_opts
.noautoextend
= 1;
15614 else if (strcmp (name
, "insn32") == 0)
15615 mips_opts
.insn32
= TRUE
;
15616 else if (strcmp (name
, "noinsn32") == 0)
15617 mips_opts
.insn32
= FALSE
;
15618 else if (strcmp (name
, "sym32") == 0)
15619 mips_opts
.sym32
= TRUE
;
15620 else if (strcmp (name
, "nosym32") == 0)
15621 mips_opts
.sym32
= FALSE
;
15627 /* Handle the .set pseudo-op. */
15630 s_mipsset (int x ATTRIBUTE_UNUSED
)
15632 char *name
= input_line_pointer
, ch
;
15633 int prev_isa
= mips_opts
.isa
;
15635 file_mips_check_options ();
15637 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15638 ++input_line_pointer
;
15639 ch
= *input_line_pointer
;
15640 *input_line_pointer
= '\0';
15642 if (strchr (name
, ','))
15644 /* Generic ".set" directive; use the generic handler. */
15645 *input_line_pointer
= ch
;
15646 input_line_pointer
= name
;
15651 if (strcmp (name
, "reorder") == 0)
15653 if (mips_opts
.noreorder
)
15656 else if (strcmp (name
, "noreorder") == 0)
15658 if (!mips_opts
.noreorder
)
15659 start_noreorder ();
15661 else if (strcmp (name
, "macro") == 0)
15662 mips_opts
.warn_about_macros
= 0;
15663 else if (strcmp (name
, "nomacro") == 0)
15665 if (mips_opts
.noreorder
== 0)
15666 as_bad (_("`noreorder' must be set before `nomacro'"));
15667 mips_opts
.warn_about_macros
= 1;
15669 else if (strcmp (name
, "gp=default") == 0)
15670 mips_opts
.gp
= file_mips_opts
.gp
;
15671 else if (strcmp (name
, "fp=default") == 0)
15672 mips_opts
.fp
= file_mips_opts
.fp
;
15673 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15675 mips_opts
.isa
= file_mips_opts
.isa
;
15676 mips_opts
.arch
= file_mips_opts
.arch
;
15677 mips_opts
.gp
= file_mips_opts
.gp
;
15678 mips_opts
.fp
= file_mips_opts
.fp
;
15680 else if (strcmp (name
, "push") == 0)
15682 struct mips_option_stack
*s
;
15684 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15685 s
->next
= mips_opts_stack
;
15686 s
->options
= mips_opts
;
15687 mips_opts_stack
= s
;
15689 else if (strcmp (name
, "pop") == 0)
15691 struct mips_option_stack
*s
;
15693 s
= mips_opts_stack
;
15695 as_bad (_(".set pop with no .set push"));
15698 /* If we're changing the reorder mode we need to handle
15699 delay slots correctly. */
15700 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15701 start_noreorder ();
15702 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15705 mips_opts
= s
->options
;
15706 mips_opts_stack
= s
->next
;
15710 else if (!parse_code_option (name
))
15711 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
15713 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15714 registers based on what is supported by the arch/cpu. */
15715 if (mips_opts
.isa
!= prev_isa
)
15717 switch (mips_opts
.isa
)
15722 /* MIPS I cannot support FPXX. */
15724 /* fall-through. */
15731 if (mips_opts
.fp
!= 0)
15747 if (mips_opts
.fp
!= 0)
15749 if (mips_opts
.arch
== CPU_R5900
)
15756 as_bad (_("unknown ISA level %s"), name
+ 4);
15761 mips_check_options (&mips_opts
, FALSE
);
15763 mips_check_isa_supports_ases ();
15764 *input_line_pointer
= ch
;
15765 demand_empty_rest_of_line ();
15768 /* Handle the .module pseudo-op. */
15771 s_module (int ignore ATTRIBUTE_UNUSED
)
15773 char *name
= input_line_pointer
, ch
;
15775 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15776 ++input_line_pointer
;
15777 ch
= *input_line_pointer
;
15778 *input_line_pointer
= '\0';
15780 if (!file_mips_opts_checked
)
15782 if (!parse_code_option (name
))
15783 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
15785 /* Update module level settings from mips_opts. */
15786 file_mips_opts
= mips_opts
;
15789 as_bad (_(".module is not permitted after generating code"));
15791 *input_line_pointer
= ch
;
15792 demand_empty_rest_of_line ();
15795 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15796 .option pic2. It means to generate SVR4 PIC calls. */
15799 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15801 mips_pic
= SVR4_PIC
;
15802 mips_abicalls
= TRUE
;
15804 if (g_switch_seen
&& g_switch_value
!= 0)
15805 as_warn (_("-G may not be used with SVR4 PIC code"));
15806 g_switch_value
= 0;
15808 bfd_set_gp_size (stdoutput
, 0);
15809 demand_empty_rest_of_line ();
15812 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15813 PIC code. It sets the $gp register for the function based on the
15814 function address, which is in the register named in the argument.
15815 This uses a relocation against _gp_disp, which is handled specially
15816 by the linker. The result is:
15817 lui $gp,%hi(_gp_disp)
15818 addiu $gp,$gp,%lo(_gp_disp)
15819 addu $gp,$gp,.cpload argument
15820 The .cpload argument is normally $25 == $t9.
15822 The -mno-shared option changes this to:
15823 lui $gp,%hi(__gnu_local_gp)
15824 addiu $gp,$gp,%lo(__gnu_local_gp)
15825 and the argument is ignored. This saves an instruction, but the
15826 resulting code is not position independent; it uses an absolute
15827 address for __gnu_local_gp. Thus code assembled with -mno-shared
15828 can go into an ordinary executable, but not into a shared library. */
15831 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15837 file_mips_check_options ();
15839 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15840 .cpload is ignored. */
15841 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15847 if (mips_opts
.mips16
)
15849 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15850 ignore_rest_of_line ();
15854 /* .cpload should be in a .set noreorder section. */
15855 if (mips_opts
.noreorder
== 0)
15856 as_warn (_(".cpload not in noreorder section"));
15858 reg
= tc_get_register (0);
15860 /* If we need to produce a 64-bit address, we are better off using
15861 the default instruction sequence. */
15862 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15864 ex
.X_op
= O_symbol
;
15865 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15867 ex
.X_op_symbol
= NULL
;
15868 ex
.X_add_number
= 0;
15870 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15871 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15873 mips_mark_labels ();
15874 mips_assembling_insn
= TRUE
;
15877 macro_build_lui (&ex
, mips_gp_register
);
15878 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15879 mips_gp_register
, BFD_RELOC_LO16
);
15881 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15882 mips_gp_register
, reg
);
15885 mips_assembling_insn
= FALSE
;
15886 demand_empty_rest_of_line ();
15889 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15890 .cpsetup $reg1, offset|$reg2, label
15892 If offset is given, this results in:
15893 sd $gp, offset($sp)
15894 lui $gp, %hi(%neg(%gp_rel(label)))
15895 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15896 daddu $gp, $gp, $reg1
15898 If $reg2 is given, this results in:
15900 lui $gp, %hi(%neg(%gp_rel(label)))
15901 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15902 daddu $gp, $gp, $reg1
15903 $reg1 is normally $25 == $t9.
15905 The -mno-shared option replaces the last three instructions with
15907 addiu $gp,$gp,%lo(_gp) */
15910 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15912 expressionS ex_off
;
15913 expressionS ex_sym
;
15916 file_mips_check_options ();
15918 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15919 We also need NewABI support. */
15920 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15926 if (mips_opts
.mips16
)
15928 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15929 ignore_rest_of_line ();
15933 reg1
= tc_get_register (0);
15934 SKIP_WHITESPACE ();
15935 if (*input_line_pointer
!= ',')
15937 as_bad (_("missing argument separator ',' for .cpsetup"));
15941 ++input_line_pointer
;
15942 SKIP_WHITESPACE ();
15943 if (*input_line_pointer
== '$')
15945 mips_cpreturn_register
= tc_get_register (0);
15946 mips_cpreturn_offset
= -1;
15950 mips_cpreturn_offset
= get_absolute_expression ();
15951 mips_cpreturn_register
= -1;
15953 SKIP_WHITESPACE ();
15954 if (*input_line_pointer
!= ',')
15956 as_bad (_("missing argument separator ',' for .cpsetup"));
15960 ++input_line_pointer
;
15961 SKIP_WHITESPACE ();
15962 expression (&ex_sym
);
15964 mips_mark_labels ();
15965 mips_assembling_insn
= TRUE
;
15968 if (mips_cpreturn_register
== -1)
15970 ex_off
.X_op
= O_constant
;
15971 ex_off
.X_add_symbol
= NULL
;
15972 ex_off
.X_op_symbol
= NULL
;
15973 ex_off
.X_add_number
= mips_cpreturn_offset
;
15975 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15976 BFD_RELOC_LO16
, SP
);
15979 move_register (mips_cpreturn_register
, mips_gp_register
);
15981 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15983 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15984 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15987 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15988 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15989 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15991 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15992 mips_gp_register
, reg1
);
15998 ex
.X_op
= O_symbol
;
15999 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16000 ex
.X_op_symbol
= NULL
;
16001 ex
.X_add_number
= 0;
16003 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16004 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16006 macro_build_lui (&ex
, mips_gp_register
);
16007 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16008 mips_gp_register
, BFD_RELOC_LO16
);
16013 mips_assembling_insn
= FALSE
;
16014 demand_empty_rest_of_line ();
16018 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16020 file_mips_check_options ();
16022 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16023 .cplocal is ignored. */
16024 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16030 if (mips_opts
.mips16
)
16032 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16033 ignore_rest_of_line ();
16037 mips_gp_register
= tc_get_register (0);
16038 demand_empty_rest_of_line ();
16041 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16042 offset from $sp. The offset is remembered, and after making a PIC
16043 call $gp is restored from that location. */
16046 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16050 file_mips_check_options ();
16052 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16053 .cprestore is ignored. */
16054 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16060 if (mips_opts
.mips16
)
16062 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16063 ignore_rest_of_line ();
16067 mips_cprestore_offset
= get_absolute_expression ();
16068 mips_cprestore_valid
= 1;
16070 ex
.X_op
= O_constant
;
16071 ex
.X_add_symbol
= NULL
;
16072 ex
.X_op_symbol
= NULL
;
16073 ex
.X_add_number
= mips_cprestore_offset
;
16075 mips_mark_labels ();
16076 mips_assembling_insn
= TRUE
;
16079 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16080 SP
, HAVE_64BIT_ADDRESSES
);
16083 mips_assembling_insn
= FALSE
;
16084 demand_empty_rest_of_line ();
16087 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16088 was given in the preceding .cpsetup, it results in:
16089 ld $gp, offset($sp)
16091 If a register $reg2 was given there, it results in:
16092 or $gp, $reg2, $0 */
16095 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16099 file_mips_check_options ();
16101 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16102 We also need NewABI support. */
16103 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16109 if (mips_opts
.mips16
)
16111 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16112 ignore_rest_of_line ();
16116 mips_mark_labels ();
16117 mips_assembling_insn
= TRUE
;
16120 if (mips_cpreturn_register
== -1)
16122 ex
.X_op
= O_constant
;
16123 ex
.X_add_symbol
= NULL
;
16124 ex
.X_op_symbol
= NULL
;
16125 ex
.X_add_number
= mips_cpreturn_offset
;
16127 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16130 move_register (mips_gp_register
, mips_cpreturn_register
);
16134 mips_assembling_insn
= FALSE
;
16135 demand_empty_rest_of_line ();
16138 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16139 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16140 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16141 debug information or MIPS16 TLS. */
16144 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16145 bfd_reloc_code_real_type rtype
)
16152 if (ex
.X_op
!= O_symbol
)
16154 as_bad (_("unsupported use of %s"), dirstr
);
16155 ignore_rest_of_line ();
16158 p
= frag_more (bytes
);
16159 md_number_to_chars (p
, 0, bytes
);
16160 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16161 demand_empty_rest_of_line ();
16162 mips_clear_insn_labels ();
16165 /* Handle .dtprelword. */
16168 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16170 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16173 /* Handle .dtpreldword. */
16176 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16178 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16181 /* Handle .tprelword. */
16184 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16186 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16189 /* Handle .tpreldword. */
16192 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16194 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16197 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16198 code. It sets the offset to use in gp_rel relocations. */
16201 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16203 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16204 We also need NewABI support. */
16205 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16211 mips_gprel_offset
= get_absolute_expression ();
16213 demand_empty_rest_of_line ();
16216 /* Handle the .gpword pseudo-op. This is used when generating PIC
16217 code. It generates a 32 bit GP relative reloc. */
16220 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16222 segment_info_type
*si
;
16223 struct insn_label_list
*l
;
16227 /* When not generating PIC code, this is treated as .word. */
16228 if (mips_pic
!= SVR4_PIC
)
16234 si
= seg_info (now_seg
);
16235 l
= si
->label_list
;
16236 mips_emit_delays ();
16238 mips_align (2, 0, l
);
16241 mips_clear_insn_labels ();
16243 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16245 as_bad (_("unsupported use of .gpword"));
16246 ignore_rest_of_line ();
16250 md_number_to_chars (p
, 0, 4);
16251 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16252 BFD_RELOC_GPREL32
);
16254 demand_empty_rest_of_line ();
16258 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16260 segment_info_type
*si
;
16261 struct insn_label_list
*l
;
16265 /* When not generating PIC code, this is treated as .dword. */
16266 if (mips_pic
!= SVR4_PIC
)
16272 si
= seg_info (now_seg
);
16273 l
= si
->label_list
;
16274 mips_emit_delays ();
16276 mips_align (3, 0, l
);
16279 mips_clear_insn_labels ();
16281 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16283 as_bad (_("unsupported use of .gpdword"));
16284 ignore_rest_of_line ();
16288 md_number_to_chars (p
, 0, 8);
16289 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16290 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16292 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16293 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16294 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16296 demand_empty_rest_of_line ();
16299 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16300 tables. It generates a R_MIPS_EH reloc. */
16303 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16308 mips_emit_delays ();
16311 mips_clear_insn_labels ();
16313 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16315 as_bad (_("unsupported use of .ehword"));
16316 ignore_rest_of_line ();
16320 md_number_to_chars (p
, 0, 4);
16321 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16322 BFD_RELOC_32_PCREL
);
16324 demand_empty_rest_of_line ();
16327 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16328 tables in SVR4 PIC code. */
16331 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16335 file_mips_check_options ();
16337 /* This is ignored when not generating SVR4 PIC code. */
16338 if (mips_pic
!= SVR4_PIC
)
16344 mips_mark_labels ();
16345 mips_assembling_insn
= TRUE
;
16347 /* Add $gp to the register named as an argument. */
16349 reg
= tc_get_register (0);
16350 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16353 mips_assembling_insn
= FALSE
;
16354 demand_empty_rest_of_line ();
16357 /* Handle the .insn pseudo-op. This marks instruction labels in
16358 mips16/micromips mode. This permits the linker to handle them specially,
16359 such as generating jalx instructions when needed. We also make
16360 them odd for the duration of the assembly, in order to generate the
16361 right sort of code. We will make them even in the adjust_symtab
16362 routine, while leaving them marked. This is convenient for the
16363 debugger and the disassembler. The linker knows to make them odd
16367 s_insn (int ignore ATTRIBUTE_UNUSED
)
16369 file_mips_check_options ();
16370 file_ase_mips16
|= mips_opts
.mips16
;
16371 file_ase_micromips
|= mips_opts
.micromips
;
16373 mips_mark_labels ();
16375 demand_empty_rest_of_line ();
16378 /* Handle the .nan pseudo-op. */
16381 s_nan (int ignore ATTRIBUTE_UNUSED
)
16383 static const char str_legacy
[] = "legacy";
16384 static const char str_2008
[] = "2008";
16387 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16389 if (i
== sizeof (str_2008
) - 1
16390 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16392 else if (i
== sizeof (str_legacy
) - 1
16393 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16395 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
16398 as_bad (_("`%s' does not support legacy NaN"),
16399 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
16402 as_bad (_("bad .nan directive"));
16404 input_line_pointer
+= i
;
16405 demand_empty_rest_of_line ();
16408 /* Handle a .stab[snd] directive. Ideally these directives would be
16409 implemented in a transparent way, so that removing them would not
16410 have any effect on the generated instructions. However, s_stab
16411 internally changes the section, so in practice we need to decide
16412 now whether the preceding label marks compressed code. We do not
16413 support changing the compression mode of a label after a .stab*
16414 directive, such as in:
16420 so the current mode wins. */
16423 s_mips_stab (int type
)
16425 mips_mark_labels ();
16429 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16432 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16439 c
= get_symbol_name (&name
);
16440 symbolP
= symbol_find_or_make (name
);
16441 S_SET_WEAK (symbolP
);
16442 *input_line_pointer
= c
;
16444 SKIP_WHITESPACE_AFTER_NAME ();
16446 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16448 if (S_IS_DEFINED (symbolP
))
16450 as_bad (_("ignoring attempt to redefine symbol %s"),
16451 S_GET_NAME (symbolP
));
16452 ignore_rest_of_line ();
16456 if (*input_line_pointer
== ',')
16458 ++input_line_pointer
;
16459 SKIP_WHITESPACE ();
16463 if (exp
.X_op
!= O_symbol
)
16465 as_bad (_("bad .weakext directive"));
16466 ignore_rest_of_line ();
16469 symbol_set_value_expression (symbolP
, &exp
);
16472 demand_empty_rest_of_line ();
16475 /* Parse a register string into a number. Called from the ECOFF code
16476 to parse .frame. The argument is non-zero if this is the frame
16477 register, so that we can record it in mips_frame_reg. */
16480 tc_get_register (int frame
)
16484 SKIP_WHITESPACE ();
16485 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16489 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16490 mips_frame_reg_valid
= 1;
16491 mips_cprestore_valid
= 0;
16497 md_section_align (asection
*seg
, valueT addr
)
16499 int align
= bfd_get_section_alignment (stdoutput
, seg
);
16501 /* We don't need to align ELF sections to the full alignment.
16502 However, Irix 5 may prefer that we align them at least to a 16
16503 byte boundary. We don't bother to align the sections if we
16504 are targeted for an embedded system. */
16505 if (strncmp (TARGET_OS
, "elf", 3) == 0)
16510 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
16513 /* Utility routine, called from above as well. If called while the
16514 input file is still being read, it's only an approximation. (For
16515 example, a symbol may later become defined which appeared to be
16516 undefined earlier.) */
16519 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
16524 if (g_switch_value
> 0)
16526 const char *symname
;
16529 /* Find out whether this symbol can be referenced off the $gp
16530 register. It can be if it is smaller than the -G size or if
16531 it is in the .sdata or .sbss section. Certain symbols can
16532 not be referenced off the $gp, although it appears as though
16534 symname
= S_GET_NAME (sym
);
16535 if (symname
!= (const char *) NULL
16536 && (strcmp (symname
, "eprol") == 0
16537 || strcmp (symname
, "etext") == 0
16538 || strcmp (symname
, "_gp") == 0
16539 || strcmp (symname
, "edata") == 0
16540 || strcmp (symname
, "_fbss") == 0
16541 || strcmp (symname
, "_fdata") == 0
16542 || strcmp (symname
, "_ftext") == 0
16543 || strcmp (symname
, "end") == 0
16544 || strcmp (symname
, "_gp_disp") == 0))
16546 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
16548 #ifndef NO_ECOFF_DEBUGGING
16549 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
16550 && (symbol_get_obj (sym
)->ecoff_extern_size
16551 <= g_switch_value
))
16553 /* We must defer this decision until after the whole
16554 file has been read, since there might be a .extern
16555 after the first use of this symbol. */
16556 || (before_relaxing
16557 #ifndef NO_ECOFF_DEBUGGING
16558 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
16560 && S_GET_VALUE (sym
) == 0)
16561 || (S_GET_VALUE (sym
) != 0
16562 && S_GET_VALUE (sym
) <= g_switch_value
)))
16566 const char *segname
;
16568 segname
= segment_name (S_GET_SEGMENT (sym
));
16569 gas_assert (strcmp (segname
, ".lit8") != 0
16570 && strcmp (segname
, ".lit4") != 0);
16571 change
= (strcmp (segname
, ".sdata") != 0
16572 && strcmp (segname
, ".sbss") != 0
16573 && strncmp (segname
, ".sdata.", 7) != 0
16574 && strncmp (segname
, ".sbss.", 6) != 0
16575 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16576 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16581 /* We are not optimizing for the $gp register. */
16586 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16589 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16593 /* Handle the case of a symbol equated to another symbol. */
16594 while (symbol_equated_reloc_p (sym
))
16598 /* It's possible to get a loop here in a badly written program. */
16599 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16605 if (symbol_section_p (sym
))
16608 symsec
= S_GET_SEGMENT (sym
);
16610 /* This must duplicate the test in adjust_reloc_syms. */
16611 return (!bfd_is_und_section (symsec
)
16612 && !bfd_is_abs_section (symsec
)
16613 && !bfd_is_com_section (symsec
)
16614 && !s_is_linkonce (sym
, segtype
)
16615 /* A global or weak symbol is treated as external. */
16616 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16620 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16621 extended opcode. SEC is the section the frag is in. */
16624 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16627 const struct mips_int_operand
*operand
;
16632 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16634 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16637 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16638 operand
= mips16_immed_operand (type
, FALSE
);
16640 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16641 val
= S_GET_VALUE (fragp
->fr_symbol
);
16642 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16644 if (operand
->root
.type
== OP_PCREL
)
16646 const struct mips_pcrel_operand
*pcrel_op
;
16650 /* We won't have the section when we are called from
16651 mips_relax_frag. However, we will always have been called
16652 from md_estimate_size_before_relax first. If this is a
16653 branch to a different section, we mark it as such. If SEC is
16654 NULL, and the frag is not marked, then it must be a branch to
16655 the same section. */
16656 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16659 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16664 /* Must have been called from md_estimate_size_before_relax. */
16667 fragp
->fr_subtype
=
16668 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16670 /* FIXME: We should support this, and let the linker
16671 catch branches and loads that are out of range. */
16672 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16673 _("unsupported PC relative reference to different section"));
16677 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16678 /* Assume non-extended on the first relaxation pass.
16679 The address we have calculated will be bogus if this is
16680 a forward branch to another frag, as the forward frag
16681 will have fr_address == 0. */
16685 /* In this case, we know for sure that the symbol fragment is in
16686 the same section. If the relax_marker of the symbol fragment
16687 differs from the relax_marker of this fragment, we have not
16688 yet adjusted the symbol fragment fr_address. We want to add
16689 in STRETCH in order to get a better estimate of the address.
16690 This particularly matters because of the shift bits. */
16692 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16696 /* Adjust stretch for any alignment frag. Note that if have
16697 been expanding the earlier code, the symbol may be
16698 defined in what appears to be an earlier frag. FIXME:
16699 This doesn't handle the fr_subtype field, which specifies
16700 a maximum number of bytes to skip when doing an
16702 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16704 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16707 stretch
= - ((- stretch
)
16708 & ~ ((1 << (int) f
->fr_offset
) - 1));
16710 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16719 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16721 /* The base address rules are complicated. The base address of
16722 a branch is the following instruction. The base address of a
16723 PC relative load or add is the instruction itself, but if it
16724 is in a delay slot (in which case it can not be extended) use
16725 the address of the instruction whose delay slot it is in. */
16726 if (pcrel_op
->include_isa_bit
)
16730 /* If we are currently assuming that this frag should be
16731 extended, then, the current address is two bytes
16733 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16736 /* Ignore the low bit in the target, since it will be set
16737 for a text label. */
16740 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16742 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16745 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16747 /* If any of the shifted bits are set, we must use an extended
16748 opcode. If the address depends on the size of this
16749 instruction, this can lead to a loop, so we arrange to always
16750 use an extended opcode. We only check this when we are in
16751 the main relaxation loop, when SEC is NULL. */
16752 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16754 fragp
->fr_subtype
=
16755 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16759 /* If we are about to mark a frag as extended because the value
16760 is precisely the next value above maxtiny, then there is a
16761 chance of an infinite loop as in the following code:
16766 In this case when the la is extended, foo is 0x3fc bytes
16767 away, so the la can be shrunk, but then foo is 0x400 away, so
16768 the la must be extended. To avoid this loop, we mark the
16769 frag as extended if it was small, and is about to become
16770 extended with the next value above maxtiny. */
16771 maxtiny
= mips_int_operand_max (operand
);
16772 if (val
== maxtiny
+ (1 << operand
->shift
)
16773 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16776 fragp
->fr_subtype
=
16777 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16781 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16782 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16784 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16787 /* Compute the length of a branch sequence, and adjust the
16788 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16789 worst-case length is computed, with UPDATE being used to indicate
16790 whether an unconditional (-1), branch-likely (+1) or regular (0)
16791 branch is to be computed. */
16793 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16795 bfd_boolean toofar
;
16799 && S_IS_DEFINED (fragp
->fr_symbol
)
16800 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16805 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16807 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16811 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16814 /* If the symbol is not defined or it's in a different segment,
16815 assume the user knows what's going on and emit a short
16821 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16823 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16824 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16825 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16826 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16832 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16835 if (mips_pic
!= NO_PIC
)
16837 /* Additional space for PIC loading of target address. */
16839 if (mips_opts
.isa
== ISA_MIPS1
)
16840 /* Additional space for $at-stabilizing nop. */
16844 /* If branch is conditional. */
16845 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16852 /* Compute the length of a branch sequence, and adjust the
16853 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16854 worst-case length is computed, with UPDATE being used to indicate
16855 whether an unconditional (-1), or regular (0) branch is to be
16859 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16861 bfd_boolean toofar
;
16865 && S_IS_DEFINED (fragp
->fr_symbol
)
16866 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16871 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16872 /* Ignore the low bit in the target, since it will be set
16873 for a text label. */
16874 if ((val
& 1) != 0)
16877 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16881 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16884 /* If the symbol is not defined or it's in a different segment,
16885 assume the user knows what's going on and emit a short
16891 if (fragp
&& update
16892 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16893 fragp
->fr_subtype
= (toofar
16894 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16895 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16900 bfd_boolean compact_known
= fragp
!= NULL
;
16901 bfd_boolean compact
= FALSE
;
16902 bfd_boolean uncond
;
16905 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16907 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16909 uncond
= update
< 0;
16911 /* If label is out of range, we turn branch <br>:
16913 <br> label # 4 bytes
16919 nop # 2 bytes if compact && !PIC
16922 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16925 /* If assembling PIC code, we further turn:
16931 lw/ld at, %got(label)(gp) # 4 bytes
16932 d/addiu at, %lo(label) # 4 bytes
16935 if (mips_pic
!= NO_PIC
)
16938 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16940 <brneg> 0f # 4 bytes
16941 nop # 2 bytes if !compact
16944 length
+= (compact_known
&& compact
) ? 4 : 6;
16950 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16951 bit accordingly. */
16954 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16956 bfd_boolean toofar
;
16959 && S_IS_DEFINED (fragp
->fr_symbol
)
16960 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16966 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16967 /* Ignore the low bit in the target, since it will be set
16968 for a text label. */
16969 if ((val
& 1) != 0)
16972 /* Assume this is a 2-byte branch. */
16973 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16975 /* We try to avoid the infinite loop by not adding 2 more bytes for
16980 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16982 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16983 else if (type
== 'E')
16984 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16989 /* If the symbol is not defined or it's in a different segment,
16990 we emit a normal 32-bit branch. */
16993 if (fragp
&& update
16994 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16996 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16997 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17005 /* Estimate the size of a frag before relaxing. Unless this is the
17006 mips16, we are not really relaxing here, and the final size is
17007 encoded in the subtype information. For the mips16, we have to
17008 decide whether we are using an extended opcode or not. */
17011 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17015 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17018 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17020 return fragp
->fr_var
;
17023 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17024 /* We don't want to modify the EXTENDED bit here; it might get us
17025 into infinite loops. We change it only in mips_relax_frag(). */
17026 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17028 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17032 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17033 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17034 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17035 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17036 fragp
->fr_var
= length
;
17041 if (mips_pic
== NO_PIC
)
17042 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17043 else if (mips_pic
== SVR4_PIC
)
17044 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17045 else if (mips_pic
== VXWORKS_PIC
)
17046 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17053 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17054 return -RELAX_FIRST (fragp
->fr_subtype
);
17057 return -RELAX_SECOND (fragp
->fr_subtype
);
17060 /* This is called to see whether a reloc against a defined symbol
17061 should be converted into a reloc against a section. */
17064 mips_fix_adjustable (fixS
*fixp
)
17066 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17067 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17070 if (fixp
->fx_addsy
== NULL
)
17073 /* Allow relocs used for EH tables. */
17074 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17077 /* If symbol SYM is in a mergeable section, relocations of the form
17078 SYM + 0 can usually be made section-relative. The mergeable data
17079 is then identified by the section offset rather than by the symbol.
17081 However, if we're generating REL LO16 relocations, the offset is split
17082 between the LO16 and parterning high part relocation. The linker will
17083 need to recalculate the complete offset in order to correctly identify
17086 The linker has traditionally not looked for the parterning high part
17087 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17088 placed anywhere. Rather than break backwards compatibility by changing
17089 this, it seems better not to force the issue, and instead keep the
17090 original symbol. This will work with either linker behavior. */
17091 if ((lo16_reloc_p (fixp
->fx_r_type
)
17092 || reloc_needs_lo_p (fixp
->fx_r_type
))
17093 && HAVE_IN_PLACE_ADDENDS
17094 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17097 /* There is no place to store an in-place offset for JALR relocations.
17098 Likewise an in-range offset of limited PC-relative relocations may
17099 overflow the in-place relocatable field if recalculated against the
17100 start address of the symbol's containing section.
17102 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17103 section relative to allow linker relaxations to be performed later on. */
17104 if ((HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (mips_opts
.isa
))
17105 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17106 || jalr_reloc_p (fixp
->fx_r_type
)))
17109 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17110 to a floating-point stub. The same is true for non-R_MIPS16_26
17111 relocations against MIPS16 functions; in this case, the stub becomes
17112 the function's canonical address.
17114 Floating-point stubs are stored in unique .mips16.call.* or
17115 .mips16.fn.* sections. If a stub T for function F is in section S,
17116 the first relocation in section S must be against F; this is how the
17117 linker determines the target function. All relocations that might
17118 resolve to T must also be against F. We therefore have the following
17119 restrictions, which are given in an intentionally-redundant way:
17121 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17124 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17125 if that stub might be used.
17127 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17130 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17131 that stub might be used.
17133 There is a further restriction:
17135 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17136 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17137 targets with in-place addends; the relocation field cannot
17138 encode the low bit.
17140 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17141 against a MIPS16 symbol. We deal with (5) by by not reducing any
17142 such relocations on REL targets.
17144 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17145 relocation against some symbol R, no relocation against R may be
17146 reduced. (Note that this deals with (2) as well as (1) because
17147 relocations against global symbols will never be reduced on ELF
17148 targets.) This approach is a little simpler than trying to detect
17149 stub sections, and gives the "all or nothing" per-symbol consistency
17150 that we have for MIPS16 symbols. */
17151 if (fixp
->fx_subsy
== NULL
17152 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17153 || *symbol_get_tc (fixp
->fx_addsy
)
17154 || (HAVE_IN_PLACE_ADDENDS
17155 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17156 && jmp_reloc_p (fixp
->fx_r_type
))))
17162 /* Translate internal representation of relocation info to BFD target
17166 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17168 static arelent
*retval
[4];
17170 bfd_reloc_code_real_type code
;
17172 memset (retval
, 0, sizeof(retval
));
17173 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17174 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17175 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17176 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17178 if (fixp
->fx_pcrel
)
17180 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17181 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17182 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17183 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17184 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17185 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17186 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17187 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17188 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17189 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17190 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17192 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17193 Relocations want only the symbol offset. */
17194 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17197 reloc
->addend
= fixp
->fx_addnumber
;
17199 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17200 entry to be used in the relocation's section offset. */
17201 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17203 reloc
->address
= reloc
->addend
;
17207 code
= fixp
->fx_r_type
;
17209 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17210 if (reloc
->howto
== NULL
)
17212 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17213 _("cannot represent %s relocation in this object file"
17215 bfd_get_reloc_code_name (code
));
17222 /* Relax a machine dependent frag. This returns the amount by which
17223 the current size of the frag should change. */
17226 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17228 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17230 offsetT old_var
= fragp
->fr_var
;
17232 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17234 return fragp
->fr_var
- old_var
;
17237 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17239 offsetT old_var
= fragp
->fr_var
;
17240 offsetT new_var
= 4;
17242 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17243 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17244 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17245 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17246 fragp
->fr_var
= new_var
;
17248 return new_var
- old_var
;
17251 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17254 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17256 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17258 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17263 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17265 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17272 /* Convert a machine dependent frag. */
17275 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17277 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17280 unsigned long insn
;
17284 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17285 insn
= read_insn (buf
);
17287 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17289 /* We generate a fixup instead of applying it right now
17290 because, if there are linker relaxations, we're going to
17291 need the relocations. */
17292 exp
.X_op
= O_symbol
;
17293 exp
.X_add_symbol
= fragp
->fr_symbol
;
17294 exp
.X_add_number
= fragp
->fr_offset
;
17296 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17297 BFD_RELOC_16_PCREL_S2
);
17298 fixp
->fx_file
= fragp
->fr_file
;
17299 fixp
->fx_line
= fragp
->fr_line
;
17301 buf
= write_insn (buf
, insn
);
17307 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17308 _("relaxed out-of-range branch into a jump"));
17310 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17313 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17315 /* Reverse the branch. */
17316 switch ((insn
>> 28) & 0xf)
17319 if ((insn
& 0xff000000) == 0x47000000
17320 || (insn
& 0xff600000) == 0x45600000)
17322 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17323 reversed by tweaking bit 23. */
17324 insn
^= 0x00800000;
17328 /* bc[0-3][tf]l? instructions can have the condition
17329 reversed by tweaking a single TF bit, and their
17330 opcodes all have 0x4???????. */
17331 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
17332 insn
^= 0x00010000;
17337 /* bltz 0x04000000 bgez 0x04010000
17338 bltzal 0x04100000 bgezal 0x04110000 */
17339 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17340 insn
^= 0x00010000;
17344 /* beq 0x10000000 bne 0x14000000
17345 blez 0x18000000 bgtz 0x1c000000 */
17346 insn
^= 0x04000000;
17354 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17356 /* Clear the and-link bit. */
17357 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17359 /* bltzal 0x04100000 bgezal 0x04110000
17360 bltzall 0x04120000 bgezall 0x04130000 */
17361 insn
&= ~0x00100000;
17364 /* Branch over the branch (if the branch was likely) or the
17365 full jump (not likely case). Compute the offset from the
17366 current instruction to branch to. */
17367 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17371 /* How many bytes in instructions we've already emitted? */
17372 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17373 /* How many bytes in instructions from here to the end? */
17374 i
= fragp
->fr_var
- i
;
17376 /* Convert to instruction count. */
17378 /* Branch counts from the next instruction. */
17381 /* Branch over the jump. */
17382 buf
= write_insn (buf
, insn
);
17385 buf
= write_insn (buf
, 0);
17387 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17389 /* beql $0, $0, 2f */
17391 /* Compute the PC offset from the current instruction to
17392 the end of the variable frag. */
17393 /* How many bytes in instructions we've already emitted? */
17394 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17395 /* How many bytes in instructions from here to the end? */
17396 i
= fragp
->fr_var
- i
;
17397 /* Convert to instruction count. */
17399 /* Don't decrement i, because we want to branch over the
17403 buf
= write_insn (buf
, insn
);
17404 buf
= write_insn (buf
, 0);
17408 if (mips_pic
== NO_PIC
)
17411 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17412 ? 0x0c000000 : 0x08000000);
17413 exp
.X_op
= O_symbol
;
17414 exp
.X_add_symbol
= fragp
->fr_symbol
;
17415 exp
.X_add_number
= fragp
->fr_offset
;
17417 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17418 FALSE
, BFD_RELOC_MIPS_JMP
);
17419 fixp
->fx_file
= fragp
->fr_file
;
17420 fixp
->fx_line
= fragp
->fr_line
;
17422 buf
= write_insn (buf
, insn
);
17426 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17428 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17429 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17430 insn
|= at
<< OP_SH_RT
;
17431 exp
.X_op
= O_symbol
;
17432 exp
.X_add_symbol
= fragp
->fr_symbol
;
17433 exp
.X_add_number
= fragp
->fr_offset
;
17435 if (fragp
->fr_offset
)
17437 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17438 exp
.X_add_number
= 0;
17441 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17442 FALSE
, BFD_RELOC_MIPS_GOT16
);
17443 fixp
->fx_file
= fragp
->fr_file
;
17444 fixp
->fx_line
= fragp
->fr_line
;
17446 buf
= write_insn (buf
, insn
);
17448 if (mips_opts
.isa
== ISA_MIPS1
)
17450 buf
= write_insn (buf
, 0);
17452 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17453 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17454 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17456 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17457 FALSE
, BFD_RELOC_LO16
);
17458 fixp
->fx_file
= fragp
->fr_file
;
17459 fixp
->fx_line
= fragp
->fr_line
;
17461 buf
= write_insn (buf
, insn
);
17464 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17468 insn
|= at
<< OP_SH_RS
;
17470 buf
= write_insn (buf
, insn
);
17474 fragp
->fr_fix
+= fragp
->fr_var
;
17475 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17479 /* Relax microMIPS branches. */
17480 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17482 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17483 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17484 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17485 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17486 bfd_boolean short_ds
;
17487 unsigned long insn
;
17491 exp
.X_op
= O_symbol
;
17492 exp
.X_add_symbol
= fragp
->fr_symbol
;
17493 exp
.X_add_number
= fragp
->fr_offset
;
17495 fragp
->fr_fix
+= fragp
->fr_var
;
17497 /* Handle 16-bit branches that fit or are forced to fit. */
17498 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17500 /* We generate a fixup instead of applying it right now,
17501 because if there is linker relaxation, we're going to
17502 need the relocations. */
17504 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
17505 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
17506 else if (type
== 'E')
17507 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
17508 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
17512 fixp
->fx_file
= fragp
->fr_file
;
17513 fixp
->fx_line
= fragp
->fr_line
;
17515 /* These relocations can have an addend that won't fit in
17517 fixp
->fx_no_overflow
= 1;
17522 /* Handle 32-bit branches that fit or are forced to fit. */
17523 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17524 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17526 /* We generate a fixup instead of applying it right now,
17527 because if there is linker relaxation, we're going to
17528 need the relocations. */
17529 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17530 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17531 fixp
->fx_file
= fragp
->fr_file
;
17532 fixp
->fx_line
= fragp
->fr_line
;
17538 /* Relax 16-bit branches to 32-bit branches. */
17541 insn
= read_compressed_insn (buf
, 2);
17543 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
17544 insn
= 0x94000000; /* beq */
17545 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17547 unsigned long regno
;
17549 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
17550 regno
= micromips_to_32_reg_d_map
[regno
];
17551 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
17552 insn
|= regno
<< MICROMIPSOP_SH_RS
;
17557 /* Nothing else to do, just write it out. */
17558 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17559 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17561 buf
= write_compressed_insn (buf
, insn
, 4);
17562 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17567 insn
= read_compressed_insn (buf
, 4);
17569 /* Relax 32-bit branches to a sequence of instructions. */
17570 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17571 _("relaxed out-of-range branch into a jump"));
17573 /* Set the short-delay-slot bit. */
17574 short_ds
= al
&& (insn
& 0x02000000) != 0;
17576 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
17580 /* Reverse the branch. */
17581 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
17582 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
17583 insn
^= 0x20000000;
17584 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
17585 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
17586 || (insn
& 0xffe00000) == 0x40800000 /* blez */
17587 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17588 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17589 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17590 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17591 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17592 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17593 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17594 insn
^= 0x00400000;
17595 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17596 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17597 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17598 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17599 insn
^= 0x00200000;
17600 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
17602 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
17604 insn
^= 0x00800000;
17610 /* Clear the and-link and short-delay-slot bits. */
17611 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17613 /* bltzal 0x40200000 bgezal 0x40600000 */
17614 /* bltzals 0x42200000 bgezals 0x42600000 */
17615 insn
&= ~0x02200000;
17618 /* Make a label at the end for use with the branch. */
17619 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17620 micromips_label_inc ();
17621 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17624 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17625 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17626 fixp
->fx_file
= fragp
->fr_file
;
17627 fixp
->fx_line
= fragp
->fr_line
;
17629 /* Branch over the jump. */
17630 buf
= write_compressed_insn (buf
, insn
, 4);
17633 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17636 if (mips_pic
== NO_PIC
)
17638 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17640 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17641 insn
= al
? jal
: 0xd4000000;
17643 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17644 BFD_RELOC_MICROMIPS_JMP
);
17645 fixp
->fx_file
= fragp
->fr_file
;
17646 fixp
->fx_line
= fragp
->fr_line
;
17648 buf
= write_compressed_insn (buf
, insn
, 4);
17651 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17655 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17656 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17657 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17659 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17660 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17661 insn
|= at
<< MICROMIPSOP_SH_RT
;
17663 if (exp
.X_add_number
)
17665 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17666 exp
.X_add_number
= 0;
17669 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17670 BFD_RELOC_MICROMIPS_GOT16
);
17671 fixp
->fx_file
= fragp
->fr_file
;
17672 fixp
->fx_line
= fragp
->fr_line
;
17674 buf
= write_compressed_insn (buf
, insn
, 4);
17676 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17677 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17678 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17680 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17681 BFD_RELOC_MICROMIPS_LO16
);
17682 fixp
->fx_file
= fragp
->fr_file
;
17683 fixp
->fx_line
= fragp
->fr_line
;
17685 buf
= write_compressed_insn (buf
, insn
, 4);
17687 /* jr/jrc/jalr/jalrs $at */
17688 insn
= al
? jalr
: jr
;
17689 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17691 buf
= write_compressed_insn (buf
, insn
, 2);
17694 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17698 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17701 const struct mips_int_operand
*operand
;
17704 unsigned int user_length
, length
;
17705 unsigned long insn
;
17708 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17709 operand
= mips16_immed_operand (type
, FALSE
);
17711 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17712 val
= resolve_symbol_value (fragp
->fr_symbol
);
17713 if (operand
->root
.type
== OP_PCREL
)
17715 const struct mips_pcrel_operand
*pcrel_op
;
17718 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17719 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17721 /* The rules for the base address of a PC relative reloc are
17722 complicated; see mips16_extended_frag. */
17723 if (pcrel_op
->include_isa_bit
)
17728 /* Ignore the low bit in the target, since it will be
17729 set for a text label. */
17732 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17734 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17737 addr
&= -(1 << pcrel_op
->align_log2
);
17740 /* Make sure the section winds up with the alignment we have
17742 if (operand
->shift
> 0)
17743 record_alignment (asec
, operand
->shift
);
17747 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17748 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17749 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17750 _("extended instruction in delay slot"));
17752 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17754 insn
= read_compressed_insn (buf
, 2);
17756 insn
|= MIPS16_EXTEND
;
17758 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17760 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17765 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17766 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17768 length
= (ext
? 4 : 2);
17769 gas_assert (mips16_opcode_length (insn
) == length
);
17770 write_compressed_insn (buf
, insn
, length
);
17771 fragp
->fr_fix
+= length
;
17775 relax_substateT subtype
= fragp
->fr_subtype
;
17776 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17777 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17781 first
= RELAX_FIRST (subtype
);
17782 second
= RELAX_SECOND (subtype
);
17783 fixp
= (fixS
*) fragp
->fr_opcode
;
17785 /* If the delay slot chosen does not match the size of the instruction,
17786 then emit a warning. */
17787 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17788 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17793 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17794 | RELAX_DELAY_SLOT_SIZE_FIRST
17795 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17796 msg
= macro_warning (s
);
17798 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17802 /* Possibly emit a warning if we've chosen the longer option. */
17803 if (use_second
== second_longer
)
17809 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17810 msg
= macro_warning (s
);
17812 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17816 /* Go through all the fixups for the first sequence. Disable them
17817 (by marking them as done) if we're going to use the second
17818 sequence instead. */
17820 && fixp
->fx_frag
== fragp
17821 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17823 if (subtype
& RELAX_USE_SECOND
)
17825 fixp
= fixp
->fx_next
;
17828 /* Go through the fixups for the second sequence. Disable them if
17829 we're going to use the first sequence, otherwise adjust their
17830 addresses to account for the relaxation. */
17831 while (fixp
&& fixp
->fx_frag
== fragp
)
17833 if (subtype
& RELAX_USE_SECOND
)
17834 fixp
->fx_where
-= first
;
17837 fixp
= fixp
->fx_next
;
17840 /* Now modify the frag contents. */
17841 if (subtype
& RELAX_USE_SECOND
)
17845 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17846 memmove (start
, start
+ first
, second
);
17847 fragp
->fr_fix
-= first
;
17850 fragp
->fr_fix
-= second
;
17854 /* This function is called after the relocs have been generated.
17855 We've been storing mips16 text labels as odd. Here we convert them
17856 back to even for the convenience of the debugger. */
17859 mips_frob_file_after_relocs (void)
17862 unsigned int count
, i
;
17864 syms
= bfd_get_outsymbols (stdoutput
);
17865 count
= bfd_get_symcount (stdoutput
);
17866 for (i
= 0; i
< count
; i
++, syms
++)
17867 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17868 && ((*syms
)->value
& 1) != 0)
17870 (*syms
)->value
&= ~1;
17871 /* If the symbol has an odd size, it was probably computed
17872 incorrectly, so adjust that as well. */
17873 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17874 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17878 /* This function is called whenever a label is defined, including fake
17879 labels instantiated off the dot special symbol. It is used when
17880 handling branch delays; if a branch has a label, we assume we cannot
17881 move it. This also bumps the value of the symbol by 1 in compressed
17885 mips_record_label (symbolS
*sym
)
17887 segment_info_type
*si
= seg_info (now_seg
);
17888 struct insn_label_list
*l
;
17890 if (free_insn_labels
== NULL
)
17891 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17894 l
= free_insn_labels
;
17895 free_insn_labels
= l
->next
;
17899 l
->next
= si
->label_list
;
17900 si
->label_list
= l
;
17903 /* This function is called as tc_frob_label() whenever a label is defined
17904 and adds a DWARF-2 record we only want for true labels. */
17907 mips_define_label (symbolS
*sym
)
17909 mips_record_label (sym
);
17910 dwarf2_emit_label (sym
);
17913 /* This function is called by tc_new_dot_label whenever a new dot symbol
17917 mips_add_dot_label (symbolS
*sym
)
17919 mips_record_label (sym
);
17920 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17921 mips_compressed_mark_label (sym
);
17924 /* Converting ASE flags from internal to .MIPS.abiflags values. */
17925 static unsigned int
17926 mips_convert_ase_flags (int ase
)
17928 unsigned int ext_ases
= 0;
17931 ext_ases
|= AFL_ASE_DSP
;
17932 if (ase
& ASE_DSPR2
)
17933 ext_ases
|= AFL_ASE_DSPR2
;
17935 ext_ases
|= AFL_ASE_EVA
;
17937 ext_ases
|= AFL_ASE_MCU
;
17938 if (ase
& ASE_MDMX
)
17939 ext_ases
|= AFL_ASE_MDMX
;
17940 if (ase
& ASE_MIPS3D
)
17941 ext_ases
|= AFL_ASE_MIPS3D
;
17943 ext_ases
|= AFL_ASE_MT
;
17944 if (ase
& ASE_SMARTMIPS
)
17945 ext_ases
|= AFL_ASE_SMARTMIPS
;
17946 if (ase
& ASE_VIRT
)
17947 ext_ases
|= AFL_ASE_VIRT
;
17949 ext_ases
|= AFL_ASE_MSA
;
17951 ext_ases
|= AFL_ASE_XPA
;
17955 /* Some special processing for a MIPS ELF file. */
17958 mips_elf_final_processing (void)
17961 Elf_Internal_ABIFlags_v0 flags
;
17965 switch (file_mips_opts
.isa
)
17968 flags
.isa_level
= 1;
17971 flags
.isa_level
= 2;
17974 flags
.isa_level
= 3;
17977 flags
.isa_level
= 4;
17980 flags
.isa_level
= 5;
17983 flags
.isa_level
= 32;
17987 flags
.isa_level
= 32;
17991 flags
.isa_level
= 32;
17995 flags
.isa_level
= 32;
17999 flags
.isa_level
= 32;
18003 flags
.isa_level
= 64;
18007 flags
.isa_level
= 64;
18011 flags
.isa_level
= 64;
18015 flags
.isa_level
= 64;
18019 flags
.isa_level
= 64;
18024 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18025 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18026 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18027 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18029 flags
.cpr2_size
= AFL_REG_NONE
;
18030 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18031 Tag_GNU_MIPS_ABI_FP
);
18032 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18033 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18034 if (file_ase_mips16
)
18035 flags
.ases
|= AFL_ASE_MIPS16
;
18036 if (file_ase_micromips
)
18037 flags
.ases
|= AFL_ASE_MICROMIPS
;
18039 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18040 || file_mips_opts
.fp
== 64)
18041 && file_mips_opts
.oddspreg
)
18042 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18045 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18046 ((Elf_External_ABIFlags_v0
*)
18049 /* Write out the register information. */
18050 if (mips_abi
!= N64_ABI
)
18054 s
.ri_gprmask
= mips_gprmask
;
18055 s
.ri_cprmask
[0] = mips_cprmask
[0];
18056 s
.ri_cprmask
[1] = mips_cprmask
[1];
18057 s
.ri_cprmask
[2] = mips_cprmask
[2];
18058 s
.ri_cprmask
[3] = mips_cprmask
[3];
18059 /* The gp_value field is set by the MIPS ELF backend. */
18061 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18062 ((Elf32_External_RegInfo
*)
18063 mips_regmask_frag
));
18067 Elf64_Internal_RegInfo s
;
18069 s
.ri_gprmask
= mips_gprmask
;
18071 s
.ri_cprmask
[0] = mips_cprmask
[0];
18072 s
.ri_cprmask
[1] = mips_cprmask
[1];
18073 s
.ri_cprmask
[2] = mips_cprmask
[2];
18074 s
.ri_cprmask
[3] = mips_cprmask
[3];
18075 /* The gp_value field is set by the MIPS ELF backend. */
18077 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18078 ((Elf64_External_RegInfo
*)
18079 mips_regmask_frag
));
18082 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18083 sort of BFD interface for this. */
18084 if (mips_any_noreorder
)
18085 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18086 if (mips_pic
!= NO_PIC
)
18088 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18089 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18092 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18094 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18095 defined at present; this might need to change in future. */
18096 if (file_ase_mips16
)
18097 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18098 if (file_ase_micromips
)
18099 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18100 if (file_mips_opts
.ase
& ASE_MDMX
)
18101 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18103 /* Set the MIPS ELF ABI flags. */
18104 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18105 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18106 else if (mips_abi
== O64_ABI
)
18107 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18108 else if (mips_abi
== EABI_ABI
)
18110 if (file_mips_opts
.gp
== 64)
18111 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18113 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18115 else if (mips_abi
== N32_ABI
)
18116 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18118 /* Nothing to do for N64_ABI. */
18120 if (mips_32bitmode
)
18121 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18123 if (mips_nan2008
== 1)
18124 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
18126 /* 32 bit code with 64 bit FP registers. */
18127 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18128 Tag_GNU_MIPS_ABI_FP
);
18129 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
18130 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
18133 typedef struct proc
{
18135 symbolS
*func_end_sym
;
18136 unsigned long reg_mask
;
18137 unsigned long reg_offset
;
18138 unsigned long fpreg_mask
;
18139 unsigned long fpreg_offset
;
18140 unsigned long frame_offset
;
18141 unsigned long frame_reg
;
18142 unsigned long pc_reg
;
18145 static procS cur_proc
;
18146 static procS
*cur_proc_ptr
;
18147 static int numprocs
;
18149 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18150 as "2", and a normal nop as "0". */
18152 #define NOP_OPCODE_MIPS 0
18153 #define NOP_OPCODE_MIPS16 1
18154 #define NOP_OPCODE_MICROMIPS 2
18157 mips_nop_opcode (void)
18159 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18160 return NOP_OPCODE_MICROMIPS
;
18161 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18162 return NOP_OPCODE_MIPS16
;
18164 return NOP_OPCODE_MIPS
;
18167 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18168 32-bit microMIPS NOPs here (if applicable). */
18171 mips_handle_align (fragS
*fragp
)
18175 int bytes
, size
, excess
;
18178 if (fragp
->fr_type
!= rs_align_code
)
18181 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18183 switch (nop_opcode
)
18185 case NOP_OPCODE_MICROMIPS
:
18186 opcode
= micromips_nop32_insn
.insn_opcode
;
18189 case NOP_OPCODE_MIPS16
:
18190 opcode
= mips16_nop_insn
.insn_opcode
;
18193 case NOP_OPCODE_MIPS
:
18195 opcode
= nop_insn
.insn_opcode
;
18200 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18201 excess
= bytes
% size
;
18203 /* Handle the leading part if we're not inserting a whole number of
18204 instructions, and make it the end of the fixed part of the frag.
18205 Try to fit in a short microMIPS NOP if applicable and possible,
18206 and use zeroes otherwise. */
18207 gas_assert (excess
< 4);
18208 fragp
->fr_fix
+= excess
;
18213 /* Fall through. */
18215 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18217 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18221 /* Fall through. */
18224 /* Fall through. */
18229 md_number_to_chars (p
, opcode
, size
);
18230 fragp
->fr_var
= size
;
18239 if (*input_line_pointer
== '-')
18241 ++input_line_pointer
;
18244 if (!ISDIGIT (*input_line_pointer
))
18245 as_bad (_("expected simple number"));
18246 if (input_line_pointer
[0] == '0')
18248 if (input_line_pointer
[1] == 'x')
18250 input_line_pointer
+= 2;
18251 while (ISXDIGIT (*input_line_pointer
))
18254 val
|= hex_value (*input_line_pointer
++);
18256 return negative
? -val
: val
;
18260 ++input_line_pointer
;
18261 while (ISDIGIT (*input_line_pointer
))
18264 val
|= *input_line_pointer
++ - '0';
18266 return negative
? -val
: val
;
18269 if (!ISDIGIT (*input_line_pointer
))
18271 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18272 *input_line_pointer
, *input_line_pointer
);
18273 as_warn (_("invalid number"));
18276 while (ISDIGIT (*input_line_pointer
))
18279 val
+= *input_line_pointer
++ - '0';
18281 return negative
? -val
: val
;
18284 /* The .file directive; just like the usual .file directive, but there
18285 is an initial number which is the ECOFF file index. In the non-ECOFF
18286 case .file implies DWARF-2. */
18289 s_mips_file (int x ATTRIBUTE_UNUSED
)
18291 static int first_file_directive
= 0;
18293 if (ECOFF_DEBUGGING
)
18302 filename
= dwarf2_directive_file (0);
18304 /* Versions of GCC up to 3.1 start files with a ".file"
18305 directive even for stabs output. Make sure that this
18306 ".file" is handled. Note that you need a version of GCC
18307 after 3.1 in order to support DWARF-2 on MIPS. */
18308 if (filename
!= NULL
&& ! first_file_directive
)
18310 (void) new_logical_line (filename
, -1);
18311 s_app_file_string (filename
, 0);
18313 first_file_directive
= 1;
18317 /* The .loc directive, implying DWARF-2. */
18320 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18322 if (!ECOFF_DEBUGGING
)
18323 dwarf2_directive_loc (0);
18326 /* The .end directive. */
18329 s_mips_end (int x ATTRIBUTE_UNUSED
)
18333 /* Following functions need their own .frame and .cprestore directives. */
18334 mips_frame_reg_valid
= 0;
18335 mips_cprestore_valid
= 0;
18337 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18340 demand_empty_rest_of_line ();
18345 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18346 as_warn (_(".end not in text section"));
18350 as_warn (_(".end directive without a preceding .ent directive"));
18351 demand_empty_rest_of_line ();
18357 gas_assert (S_GET_NAME (p
));
18358 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18359 as_warn (_(".end symbol does not match .ent symbol"));
18361 if (debug_type
== DEBUG_STABS
)
18362 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18366 as_warn (_(".end directive missing or unknown symbol"));
18368 /* Create an expression to calculate the size of the function. */
18369 if (p
&& cur_proc_ptr
)
18371 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18372 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18375 exp
->X_op
= O_subtract
;
18376 exp
->X_add_symbol
= symbol_temp_new_now ();
18377 exp
->X_op_symbol
= p
;
18378 exp
->X_add_number
= 0;
18380 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18383 /* Generate a .pdr section. */
18384 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
18386 segT saved_seg
= now_seg
;
18387 subsegT saved_subseg
= now_subseg
;
18391 #ifdef md_flush_pending_output
18392 md_flush_pending_output ();
18395 gas_assert (pdr_seg
);
18396 subseg_set (pdr_seg
, 0);
18398 /* Write the symbol. */
18399 exp
.X_op
= O_symbol
;
18400 exp
.X_add_symbol
= p
;
18401 exp
.X_add_number
= 0;
18402 emit_expr (&exp
, 4);
18404 fragp
= frag_more (7 * 4);
18406 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18407 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18408 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18409 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18410 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18411 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18412 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18414 subseg_set (saved_seg
, saved_subseg
);
18417 cur_proc_ptr
= NULL
;
18420 /* The .aent and .ent directives. */
18423 s_mips_ent (int aent
)
18427 symbolP
= get_symbol ();
18428 if (*input_line_pointer
== ',')
18429 ++input_line_pointer
;
18430 SKIP_WHITESPACE ();
18431 if (ISDIGIT (*input_line_pointer
)
18432 || *input_line_pointer
== '-')
18435 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18436 as_warn (_(".ent or .aent not in text section"));
18438 if (!aent
&& cur_proc_ptr
)
18439 as_warn (_("missing .end"));
18443 /* This function needs its own .frame and .cprestore directives. */
18444 mips_frame_reg_valid
= 0;
18445 mips_cprestore_valid
= 0;
18447 cur_proc_ptr
= &cur_proc
;
18448 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18450 cur_proc_ptr
->func_sym
= symbolP
;
18454 if (debug_type
== DEBUG_STABS
)
18455 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18456 S_GET_NAME (symbolP
));
18459 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18461 demand_empty_rest_of_line ();
18464 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18465 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18466 s_mips_frame is used so that we can set the PDR information correctly.
18467 We can't use the ecoff routines because they make reference to the ecoff
18468 symbol table (in the mdebug section). */
18471 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18473 if (ECOFF_DEBUGGING
)
18479 if (cur_proc_ptr
== (procS
*) NULL
)
18481 as_warn (_(".frame outside of .ent"));
18482 demand_empty_rest_of_line ();
18486 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18488 SKIP_WHITESPACE ();
18489 if (*input_line_pointer
++ != ','
18490 || get_absolute_expression_and_terminator (&val
) != ',')
18492 as_warn (_("bad .frame directive"));
18493 --input_line_pointer
;
18494 demand_empty_rest_of_line ();
18498 cur_proc_ptr
->frame_offset
= val
;
18499 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18501 demand_empty_rest_of_line ();
18505 /* The .fmask and .mask directives. If the mdebug section is present
18506 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18507 embedded targets, s_mips_mask is used so that we can set the PDR
18508 information correctly. We can't use the ecoff routines because they
18509 make reference to the ecoff symbol table (in the mdebug section). */
18512 s_mips_mask (int reg_type
)
18514 if (ECOFF_DEBUGGING
)
18515 s_ignore (reg_type
);
18520 if (cur_proc_ptr
== (procS
*) NULL
)
18522 as_warn (_(".mask/.fmask outside of .ent"));
18523 demand_empty_rest_of_line ();
18527 if (get_absolute_expression_and_terminator (&mask
) != ',')
18529 as_warn (_("bad .mask/.fmask directive"));
18530 --input_line_pointer
;
18531 demand_empty_rest_of_line ();
18535 off
= get_absolute_expression ();
18537 if (reg_type
== 'F')
18539 cur_proc_ptr
->fpreg_mask
= mask
;
18540 cur_proc_ptr
->fpreg_offset
= off
;
18544 cur_proc_ptr
->reg_mask
= mask
;
18545 cur_proc_ptr
->reg_offset
= off
;
18548 demand_empty_rest_of_line ();
18552 /* A table describing all the processors gas knows about. Names are
18553 matched in the order listed.
18555 To ease comparison, please keep this table in the same order as
18556 gcc's mips_cpu_info_table[]. */
18557 static const struct mips_cpu_info mips_cpu_info_table
[] =
18559 /* Entries for generic ISAs */
18560 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
18561 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
18562 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
18563 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
18564 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
18565 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
18566 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18567 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
18568 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
18569 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
18570 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
18571 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
18572 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
18573 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
18574 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
18577 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
18578 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
18579 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
18582 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
18585 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
18586 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
18587 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
18588 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
18589 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
18590 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
18591 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
18592 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
18593 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
18594 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
18595 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
18596 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
18597 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
18598 /* ST Microelectronics Loongson 2E and 2F cores */
18599 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
18600 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
18603 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
18604 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
18605 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
18606 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
18607 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
18608 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
18609 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
18610 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
18611 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
18612 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
18613 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
18614 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
18615 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
18616 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
18617 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
18620 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18621 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18622 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18623 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
18625 /* MIPS 32 Release 2 */
18626 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18627 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18628 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18629 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18630 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18631 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18632 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18633 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18634 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
18635 ISA_MIPS32R2
, CPU_MIPS32R2
},
18636 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
18637 ISA_MIPS32R2
, CPU_MIPS32R2
},
18638 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18639 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18640 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18641 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18642 /* Deprecated forms of the above. */
18643 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18644 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18645 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18646 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18647 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18648 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18649 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18650 /* Deprecated forms of the above. */
18651 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18652 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18653 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18654 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18655 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18656 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18657 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18658 /* Deprecated forms of the above. */
18659 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18660 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18661 /* 34Kn is a 34kc without DSP. */
18662 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18663 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18664 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18665 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18666 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18667 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18668 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18669 /* Deprecated forms of the above. */
18670 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18671 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18672 /* 1004K cores are multiprocessor versions of the 34K. */
18673 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18674 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18675 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18676 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18677 /* interaptiv is the new name for 1004kf */
18678 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18680 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
18681 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
18682 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18683 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
18686 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18687 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18688 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18689 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18691 /* Broadcom SB-1 CPU core */
18692 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18693 /* Broadcom SB-1A CPU core */
18694 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18696 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
18698 /* MIPS 64 Release 2 */
18700 /* Cavium Networks Octeon CPU core */
18701 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
18702 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
18703 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
18704 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
18707 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
18710 XLP is mostly like XLR, with the prominent exception that it is
18711 MIPS64R2 rather than MIPS64. */
18712 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
18715 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
18718 { NULL
, 0, 0, 0, 0 }
18722 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18723 with a final "000" replaced by "k". Ignore case.
18725 Note: this function is shared between GCC and GAS. */
18728 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18730 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18731 given
++, canonical
++;
18733 return ((*given
== 0 && *canonical
== 0)
18734 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18738 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18739 CPU name. We've traditionally allowed a lot of variation here.
18741 Note: this function is shared between GCC and GAS. */
18744 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18746 /* First see if the name matches exactly, or with a final "000"
18747 turned into "k". */
18748 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18751 /* If not, try comparing based on numerical designation alone.
18752 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18753 if (TOLOWER (*given
) == 'r')
18755 if (!ISDIGIT (*given
))
18758 /* Skip over some well-known prefixes in the canonical name,
18759 hoping to find a number there too. */
18760 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18762 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18764 else if (TOLOWER (canonical
[0]) == 'r')
18767 return mips_strict_matching_cpu_name_p (canonical
, given
);
18771 /* Parse an option that takes the name of a processor as its argument.
18772 OPTION is the name of the option and CPU_STRING is the argument.
18773 Return the corresponding processor enumeration if the CPU_STRING is
18774 recognized, otherwise report an error and return null.
18776 A similar function exists in GCC. */
18778 static const struct mips_cpu_info
*
18779 mips_parse_cpu (const char *option
, const char *cpu_string
)
18781 const struct mips_cpu_info
*p
;
18783 /* 'from-abi' selects the most compatible architecture for the given
18784 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18785 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18786 version. Look first at the -mgp options, if given, otherwise base
18787 the choice on MIPS_DEFAULT_64BIT.
18789 Treat NO_ABI like the EABIs. One reason to do this is that the
18790 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18791 architecture. This code picks MIPS I for 'mips' and MIPS III for
18792 'mips64', just as we did in the days before 'from-abi'. */
18793 if (strcasecmp (cpu_string
, "from-abi") == 0)
18795 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18796 return mips_cpu_info_from_isa (ISA_MIPS1
);
18798 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18799 return mips_cpu_info_from_isa (ISA_MIPS3
);
18801 if (file_mips_opts
.gp
>= 0)
18802 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
18803 ? ISA_MIPS1
: ISA_MIPS3
);
18805 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18810 /* 'default' has traditionally been a no-op. Probably not very useful. */
18811 if (strcasecmp (cpu_string
, "default") == 0)
18814 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18815 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18818 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
18822 /* Return the canonical processor information for ISA (a member of the
18823 ISA_MIPS* enumeration). */
18825 static const struct mips_cpu_info
*
18826 mips_cpu_info_from_isa (int isa
)
18830 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18831 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18832 && isa
== mips_cpu_info_table
[i
].isa
)
18833 return (&mips_cpu_info_table
[i
]);
18838 static const struct mips_cpu_info
*
18839 mips_cpu_info_from_arch (int arch
)
18843 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18844 if (arch
== mips_cpu_info_table
[i
].cpu
)
18845 return (&mips_cpu_info_table
[i
]);
18851 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18855 fprintf (stream
, "%24s", "");
18860 fprintf (stream
, ", ");
18864 if (*col_p
+ strlen (string
) > 72)
18866 fprintf (stream
, "\n%24s", "");
18870 fprintf (stream
, "%s", string
);
18871 *col_p
+= strlen (string
);
18877 md_show_usage (FILE *stream
)
18882 fprintf (stream
, _("\
18884 -EB generate big endian output\n\
18885 -EL generate little endian output\n\
18886 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18887 -G NUM allow referencing objects up to NUM bytes\n\
18888 implicitly with the gp register [default 8]\n"));
18889 fprintf (stream
, _("\
18890 -mips1 generate MIPS ISA I instructions\n\
18891 -mips2 generate MIPS ISA II instructions\n\
18892 -mips3 generate MIPS ISA III instructions\n\
18893 -mips4 generate MIPS ISA IV instructions\n\
18894 -mips5 generate MIPS ISA V instructions\n\
18895 -mips32 generate MIPS32 ISA instructions\n\
18896 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18897 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18898 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18899 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
18900 -mips64 generate MIPS64 ISA instructions\n\
18901 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18902 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18903 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18904 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
18905 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18909 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18910 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18911 show (stream
, "from-abi", &column
, &first
);
18912 fputc ('\n', stream
);
18914 fprintf (stream
, _("\
18915 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18916 -no-mCPU don't generate code specific to CPU.\n\
18917 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18921 show (stream
, "3900", &column
, &first
);
18922 show (stream
, "4010", &column
, &first
);
18923 show (stream
, "4100", &column
, &first
);
18924 show (stream
, "4650", &column
, &first
);
18925 fputc ('\n', stream
);
18927 fprintf (stream
, _("\
18928 -mips16 generate mips16 instructions\n\
18929 -no-mips16 do not generate mips16 instructions\n"));
18930 fprintf (stream
, _("\
18931 -mmicromips generate microMIPS instructions\n\
18932 -mno-micromips do not generate microMIPS instructions\n"));
18933 fprintf (stream
, _("\
18934 -msmartmips generate smartmips instructions\n\
18935 -mno-smartmips do not generate smartmips instructions\n"));
18936 fprintf (stream
, _("\
18937 -mdsp generate DSP instructions\n\
18938 -mno-dsp do not generate DSP instructions\n"));
18939 fprintf (stream
, _("\
18940 -mdspr2 generate DSP R2 instructions\n\
18941 -mno-dspr2 do not generate DSP R2 instructions\n"));
18942 fprintf (stream
, _("\
18943 -mmt generate MT instructions\n\
18944 -mno-mt do not generate MT instructions\n"));
18945 fprintf (stream
, _("\
18946 -mmcu generate MCU instructions\n\
18947 -mno-mcu do not generate MCU instructions\n"));
18948 fprintf (stream
, _("\
18949 -mmsa generate MSA instructions\n\
18950 -mno-msa do not generate MSA instructions\n"));
18951 fprintf (stream
, _("\
18952 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18953 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18954 fprintf (stream
, _("\
18955 -mvirt generate Virtualization instructions\n\
18956 -mno-virt do not generate Virtualization instructions\n"));
18957 fprintf (stream
, _("\
18958 -minsn32 only generate 32-bit microMIPS instructions\n\
18959 -mno-insn32 generate all microMIPS instructions\n"));
18960 fprintf (stream
, _("\
18961 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18962 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18963 -mfix-vr4120 work around certain VR4120 errata\n\
18964 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18965 -mfix-24k insert a nop after ERET and DERET instructions\n\
18966 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18967 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18968 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18969 -msym32 assume all symbols have 32-bit values\n\
18970 -O0 remove unneeded NOPs, do not swap branches\n\
18971 -O remove unneeded NOPs and swap branches\n\
18972 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18973 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18974 fprintf (stream
, _("\
18975 -mhard-float allow floating-point instructions\n\
18976 -msoft-float do not allow floating-point instructions\n\
18977 -msingle-float only allow 32-bit floating-point operations\n\
18978 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18979 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18980 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18981 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18985 show (stream
, "legacy", &column
, &first
);
18986 show (stream
, "2008", &column
, &first
);
18988 fputc ('\n', stream
);
18990 fprintf (stream
, _("\
18991 -KPIC, -call_shared generate SVR4 position independent code\n\
18992 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18993 -mvxworks-pic generate VxWorks position independent code\n\
18994 -non_shared do not generate code that can operate with DSOs\n\
18995 -xgot assume a 32 bit GOT\n\
18996 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18997 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18998 position dependent (non shared) code\n\
18999 -mabi=ABI create ABI conformant object file for:\n"));
19003 show (stream
, "32", &column
, &first
);
19004 show (stream
, "o64", &column
, &first
);
19005 show (stream
, "n32", &column
, &first
);
19006 show (stream
, "64", &column
, &first
);
19007 show (stream
, "eabi", &column
, &first
);
19009 fputc ('\n', stream
);
19011 fprintf (stream
, _("\
19012 -32 create o32 ABI object file (default)\n\
19013 -n32 create n32 ABI object file\n\
19014 -64 create 64 ABI object file\n"));
19019 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19021 if (HAVE_64BIT_SYMBOLS
)
19022 return dwarf2_format_64bit_irix
;
19024 return dwarf2_format_32bit
;
19029 mips_dwarf2_addr_size (void)
19031 if (HAVE_64BIT_OBJECTS
)
19037 /* Standard calling conventions leave the CFA at SP on entry. */
19039 mips_cfi_frame_initial_instructions (void)
19041 cfi_add_CFA_def_cfa_register (SP
);
19045 tc_mips_regname_to_dw2regnum (char *regname
)
19047 unsigned int regnum
= -1;
19050 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19056 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19057 Given a symbolic attribute NAME, return the proper integer value.
19058 Returns -1 if the attribute is not known. */
19061 mips_convert_symbolic_attribute (const char *name
)
19063 static const struct
19068 attribute_table
[] =
19070 #define T(tag) {#tag, tag}
19071 T (Tag_GNU_MIPS_ABI_FP
),
19072 T (Tag_GNU_MIPS_ABI_MSA
),
19080 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
19081 if (streq (name
, attribute_table
[i
].name
))
19082 return attribute_table
[i
].tag
;
19090 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
19092 mips_emit_delays ();
19094 as_warn (_("missing .end at end of assembly"));
19096 /* Just in case no code was emitted, do the consistency check. */
19097 file_mips_check_options ();
19099 /* Set a floating-point ABI if the user did not. */
19100 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
19102 /* Perform consistency checks on the floating-point ABI. */
19103 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19104 Tag_GNU_MIPS_ABI_FP
);
19105 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
19106 check_fpabi (fpabi
);
19110 /* Soft-float gets precedence over single-float, the two options should
19111 not be used together so this should not matter. */
19112 if (file_mips_opts
.soft_float
== 1)
19113 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
19114 /* Single-float gets precedence over all double_float cases. */
19115 else if (file_mips_opts
.single_float
== 1)
19116 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
19119 switch (file_mips_opts
.fp
)
19122 if (file_mips_opts
.gp
== 32)
19123 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19126 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
19129 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
19130 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
19131 else if (file_mips_opts
.gp
== 32)
19132 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
19134 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19139 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19140 Tag_GNU_MIPS_ABI_FP
, fpabi
);
19144 /* Returns the relocation type required for a particular CFI encoding. */
19146 bfd_reloc_code_real_type
19147 mips_cfi_reloc_for_encoding (int encoding
)
19149 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
19150 return BFD_RELOC_32_PCREL
;
19151 else return BFD_RELOC_NONE
;