1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* This is the set of options which may be modified by the .set
140 pseudo-op. We use a struct so that .set push and .set pop are more
143 struct mips_set_options
145 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
146 if it has not been initialized. Changed by `.set mipsN', and the
147 -mipsN command line option, and the default CPU. */
149 /* Enabled Application Specific Extensions (ASEs). These are set to -1
150 if they have not been initialized. Changed by `.set <asename>', by
151 command line options, and based on the default architecture. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros
;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
180 /* Restrict general purpose registers and floating point registers
181 to 32 bit. This is initially determined when -mgp32 or -mfp32
182 is passed but can changed if the assembler code uses .set mipsN. */
185 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
186 command line option, and the default CPU. */
190 /* True if -mgp32 was passed. */
191 static int file_mips_gp32
= -1;
193 /* True if -mfp32 was passed. */
194 static int file_mips_fp32
= -1;
196 /* This is the struct we use to hold the current set of options. Note
197 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
198 -1 to indicate that they have not been initialized. */
200 static struct mips_set_options mips_opts
=
202 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
205 /* These variables are filled in with the masks of registers used.
206 The object format code reads them and puts them in the appropriate
208 unsigned long mips_gprmask
;
209 unsigned long mips_cprmask
[4];
211 /* MIPS ISA we are using for this output file. */
212 static int file_mips_isa
= ISA_UNKNOWN
;
214 /* True if -mips16 was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mips16
;
218 /* True if -mips3d was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips3d
;
222 /* True if -mdmx was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mdmx
;
226 /* The argument of the -march= flag. The architecture we are assembling. */
227 static int file_mips_arch
= CPU_UNKNOWN
;
228 static const char *mips_arch_string
;
230 /* The argument of the -mtune= flag. The architecture for which we
232 static int mips_tune
= CPU_UNKNOWN
;
233 static const char *mips_tune_string
;
235 /* True when generating 32-bit code for a 64-bit processor. */
236 static int mips_32bitmode
= 0;
238 /* True if the given ABI requires 32-bit registers. */
239 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
241 /* Likewise 64-bit registers. */
242 #define ABI_NEEDS_64BIT_REGS(ABI) \
244 || (ABI) == N64_ABI \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
253 || (ISA) == ISA_MIPS64R2 \
256 /* Return true if ISA supports 64-bit right rotate (dror et al.)
258 #define ISA_HAS_DROR(ISA) ( \
259 (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 32-bit right rotate (ror et al.)
264 #define ISA_HAS_ROR(ISA) ( \
265 (ISA) == ISA_MIPS32R2 \
266 || (ISA) == ISA_MIPS64R2 \
269 #define HAVE_32BIT_GPRS \
270 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
272 #define HAVE_32BIT_FPRS \
273 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
275 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
276 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
278 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
280 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
282 /* True if relocations are stored in-place. */
283 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
285 /* We can only have 64bit addresses if the object file format supports it. */
286 #define HAVE_32BIT_ADDRESSES \
288 || (bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS)) \
291 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
293 /* Addresses are loaded in different ways, depending on the address size
294 in use. The n32 ABI Documentation also mandates the use of additions
295 with overflow checking, but existing implementations don't follow it. */
296 #define ADDRESS_ADD_INSN \
297 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
299 #define ADDRESS_ADDI_INSN \
300 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
302 #define ADDRESS_LOAD_INSN \
303 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
305 #define ADDRESS_STORE_INSN \
306 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
308 /* Return true if the given CPU supports the MIPS16 ASE. */
309 #define CPU_HAS_MIPS16(cpu) \
310 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
311 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
313 /* Return true if the given CPU supports the MIPS3D ASE. */
314 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
317 /* Return true if the given CPU supports the MDMX ASE. */
318 #define CPU_HAS_MDMX(cpu) (FALSE \
321 /* True if CPU has a dror instruction. */
322 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
324 /* True if CPU has a ror instruction. */
325 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
327 /* True if mflo and mfhi can be immediately followed by instructions
328 which write to the HI and LO registers.
330 According to MIPS specifications, MIPS ISAs I, II, and III need
331 (at least) two instructions between the reads of HI/LO and
332 instructions which write them, and later ISAs do not. Contradicting
333 the MIPS specifications, some MIPS IV processor user manuals (e.g.
334 the UM for the NEC Vr5000) document needing the instructions between
335 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
336 MIPS64 and later ISAs to have the interlocks, plus any specific
337 earlier-ISA CPUs for which CPU documentation declares that the
338 instructions are really interlocked. */
339 #define hilo_interlocks \
340 (mips_opts.isa == ISA_MIPS32 \
341 || mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64 \
343 || mips_opts.isa == ISA_MIPS64R2 \
344 || mips_opts.arch == CPU_R4010 \
345 || mips_opts.arch == CPU_R10000 \
346 || mips_opts.arch == CPU_R12000 \
347 || mips_opts.arch == CPU_RM7000 \
348 || mips_opts.arch == CPU_VR5500 \
351 /* Whether the processor uses hardware interlocks to protect reads
352 from the GPRs after they are loaded from memory, and thus does not
353 require nops to be inserted. This applies to instructions marked
354 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
356 #define gpr_interlocks \
357 (mips_opts.isa != ISA_MIPS1 \
358 || mips_opts.arch == CPU_R3900)
360 /* Whether the processor uses hardware interlocks to avoid delays
361 required by coprocessor instructions, and thus does not require
362 nops to be inserted. This applies to instructions marked
363 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
364 between instructions marked INSN_WRITE_COND_CODE and ones marked
365 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
366 levels I, II, and III. */
367 /* Itbl support may require additional care here. */
368 #define cop_interlocks \
369 ((mips_opts.isa != ISA_MIPS1 \
370 && mips_opts.isa != ISA_MIPS2 \
371 && mips_opts.isa != ISA_MIPS3) \
372 || mips_opts.arch == CPU_R4300 \
375 /* Whether the processor uses hardware interlocks to protect reads
376 from coprocessor registers after they are loaded from memory, and
377 thus does not require nops to be inserted. This applies to
378 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
379 requires at MIPS ISA level I. */
380 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
382 /* Is this a mfhi or mflo instruction? */
383 #define MF_HILO_INSN(PINFO) \
384 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
386 /* MIPS PIC level. */
388 enum mips_pic_level mips_pic
;
390 /* 1 if we should generate 32 bit offsets from the $gp register in
391 SVR4_PIC mode. Currently has no meaning in other modes. */
392 static int mips_big_got
= 0;
394 /* 1 if trap instructions should used for overflow rather than break
396 static int mips_trap
= 0;
398 /* 1 if double width floating point constants should not be constructed
399 by assembling two single width halves into two single width floating
400 point registers which just happen to alias the double width destination
401 register. On some architectures this aliasing can be disabled by a bit
402 in the status register, and the setting of this bit cannot be determined
403 automatically at assemble time. */
404 static int mips_disable_float_construction
;
406 /* Non-zero if any .set noreorder directives were used. */
408 static int mips_any_noreorder
;
410 /* Non-zero if nops should be inserted when the register referenced in
411 an mfhi/mflo instruction is read in the next two instructions. */
412 static int mips_7000_hilo_fix
;
414 /* The size of the small data section. */
415 static unsigned int g_switch_value
= 8;
416 /* Whether the -G option was used. */
417 static int g_switch_seen
= 0;
422 /* If we can determine in advance that GP optimization won't be
423 possible, we can skip the relaxation stuff that tries to produce
424 GP-relative references. This makes delay slot optimization work
427 This function can only provide a guess, but it seems to work for
428 gcc output. It needs to guess right for gcc, otherwise gcc
429 will put what it thinks is a GP-relative instruction in a branch
432 I don't know if a fix is needed for the SVR4_PIC mode. I've only
433 fixed it for the non-PIC mode. KR 95/04/07 */
434 static int nopic_need_relax (symbolS
*, int);
436 /* handle of the OPCODE hash table */
437 static struct hash_control
*op_hash
= NULL
;
439 /* The opcode hash table we use for the mips16. */
440 static struct hash_control
*mips16_op_hash
= NULL
;
442 /* This array holds the chars that always start a comment. If the
443 pre-processor is disabled, these aren't very useful */
444 const char comment_chars
[] = "#";
446 /* This array holds the chars that only start a comment at the beginning of
447 a line. If the line seems to have the form '# 123 filename'
448 .line and .file directives will appear in the pre-processed output */
449 /* Note that input_file.c hand checks for '#' at the beginning of the
450 first line of the input file. This is because the compiler outputs
451 #NO_APP at the beginning of its output. */
452 /* Also note that C style comments are always supported. */
453 const char line_comment_chars
[] = "#";
455 /* This array holds machine specific line separator characters. */
456 const char line_separator_chars
[] = ";";
458 /* Chars that can be used to separate mant from exp in floating point nums */
459 const char EXP_CHARS
[] = "eE";
461 /* Chars that mean this number is a floating point constant */
464 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
466 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
467 changed in read.c . Ideally it shouldn't have to know about it at all,
468 but nothing is ideal around here.
471 static char *insn_error
;
473 static int auto_align
= 1;
475 /* When outputting SVR4 PIC code, the assembler needs to know the
476 offset in the stack frame from which to restore the $gp register.
477 This is set by the .cprestore pseudo-op, and saved in this
479 static offsetT mips_cprestore_offset
= -1;
481 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
482 more optimizations, it can use a register value instead of a memory-saved
483 offset and even an other register than $gp as global pointer. */
484 static offsetT mips_cpreturn_offset
= -1;
485 static int mips_cpreturn_register
= -1;
486 static int mips_gp_register
= GP
;
487 static int mips_gprel_offset
= 0;
489 /* Whether mips_cprestore_offset has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_cprestore_valid
= 0;
493 /* This is the register which holds the stack frame, as set by the
494 .frame pseudo-op. This is needed to implement .cprestore. */
495 static int mips_frame_reg
= SP
;
497 /* Whether mips_frame_reg has been set in the current function
498 (or whether it has already been warned about, if not). */
499 static int mips_frame_reg_valid
= 0;
501 /* To output NOP instructions correctly, we need to keep information
502 about the previous two instructions. */
504 /* Whether we are optimizing. The default value of 2 means to remove
505 unneeded NOPs and swap branch instructions when possible. A value
506 of 1 means to not swap branches. A value of 0 means to always
508 static int mips_optimize
= 2;
510 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
511 equivalent to seeing no -g option at all. */
512 static int mips_debug
= 0;
514 /* The previous instruction. */
515 static struct mips_cl_insn prev_insn
;
517 /* The instruction before prev_insn. */
518 static struct mips_cl_insn prev_prev_insn
;
520 /* If we don't want information for prev_insn or prev_prev_insn, we
521 point the insn_mo field at this dummy integer. */
522 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
524 /* Non-zero if prev_insn is valid. */
525 static int prev_insn_valid
;
527 /* The frag for the previous instruction. */
528 static struct frag
*prev_insn_frag
;
530 /* The offset into prev_insn_frag for the previous instruction. */
531 static long prev_insn_where
;
533 /* The reloc type for the previous instruction, if any. */
534 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
536 /* The reloc for the previous instruction, if any. */
537 static fixS
*prev_insn_fixp
[3];
539 /* Non-zero if the previous instruction was in a delay slot. */
540 static int prev_insn_is_delay_slot
;
542 /* Non-zero if the previous instruction was in a .set noreorder. */
543 static int prev_insn_unreordered
;
545 /* Non-zero if the previous instruction uses an extend opcode (if
547 static int prev_insn_extended
;
549 /* Non-zero if the previous previous instruction was in a .set
551 static int prev_prev_insn_unreordered
;
553 /* If this is set, it points to a frag holding nop instructions which
554 were inserted before the start of a noreorder section. If those
555 nops turn out to be unnecessary, the size of the frag can be
557 static fragS
*prev_nop_frag
;
559 /* The number of nop instructions we created in prev_nop_frag. */
560 static int prev_nop_frag_holds
;
562 /* The number of nop instructions that we know we need in
564 static int prev_nop_frag_required
;
566 /* The number of instructions we've seen since prev_nop_frag. */
567 static int prev_nop_frag_since
;
569 /* For ECOFF and ELF, relocations against symbols are done in two
570 parts, with a HI relocation and a LO relocation. Each relocation
571 has only 16 bits of space to store an addend. This means that in
572 order for the linker to handle carries correctly, it must be able
573 to locate both the HI and the LO relocation. This means that the
574 relocations must appear in order in the relocation table.
576 In order to implement this, we keep track of each unmatched HI
577 relocation. We then sort them so that they immediately precede the
578 corresponding LO relocation. */
583 struct mips_hi_fixup
*next
;
586 /* The section this fixup is in. */
590 /* The list of unmatched HI relocs. */
592 static struct mips_hi_fixup
*mips_hi_fixup_list
;
594 /* The frag containing the last explicit relocation operator.
595 Null if explicit relocations have not been used. */
597 static fragS
*prev_reloc_op_frag
;
599 /* Map normal MIPS register numbers to mips16 register numbers. */
601 #define X ILLEGAL_REG
602 static const int mips32_to_16_reg_map
[] =
604 X
, X
, 2, 3, 4, 5, 6, 7,
605 X
, X
, X
, X
, X
, X
, X
, X
,
606 0, 1, X
, X
, X
, X
, X
, X
,
607 X
, X
, X
, X
, X
, X
, X
, X
611 /* Map mips16 register numbers to normal MIPS register numbers. */
613 static const unsigned int mips16_to_32_reg_map
[] =
615 16, 17, 2, 3, 4, 5, 6, 7
618 static int mips_fix_vr4120
;
620 /* We don't relax branches by default, since this causes us to expand
621 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
622 fail to compute the offset before expanding the macro to the most
623 efficient expansion. */
625 static int mips_relax_branch
;
627 /* The expansion of many macros depends on the type of symbol that
628 they refer to. For example, when generating position-dependent code,
629 a macro that refers to a symbol may have two different expansions,
630 one which uses GP-relative addresses and one which uses absolute
631 addresses. When generating SVR4-style PIC, a macro may have
632 different expansions for local and global symbols.
634 We handle these situations by generating both sequences and putting
635 them in variant frags. In position-dependent code, the first sequence
636 will be the GP-relative one and the second sequence will be the
637 absolute one. In SVR4 PIC, the first sequence will be for global
638 symbols and the second will be for local symbols.
640 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
641 SECOND are the lengths of the two sequences in bytes. These fields
642 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
643 the subtype has the following flags:
646 Set if it has been decided that we should use the second
647 sequence instead of the first.
650 Set in the first variant frag if the macro's second implementation
651 is longer than its first. This refers to the macro as a whole,
652 not an individual relaxation.
655 Set in the first variant frag if the macro appeared in a .set nomacro
656 block and if one alternative requires a warning but the other does not.
659 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
662 The frag's "opcode" points to the first fixup for relaxable code.
664 Relaxable macros are generated using a sequence such as:
666 relax_start (SYMBOL);
667 ... generate first expansion ...
669 ... generate second expansion ...
672 The code and fixups for the unwanted alternative are discarded
673 by md_convert_frag. */
674 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
676 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
677 #define RELAX_SECOND(X) ((X) & 0xff)
678 #define RELAX_USE_SECOND 0x10000
679 #define RELAX_SECOND_LONGER 0x20000
680 #define RELAX_NOMACRO 0x40000
681 #define RELAX_DELAY_SLOT 0x80000
683 /* Branch without likely bit. If label is out of range, we turn:
685 beq reg1, reg2, label
695 with the following opcode replacements:
702 bltzal <-> bgezal (with jal label instead of j label)
704 Even though keeping the delay slot instruction in the delay slot of
705 the branch would be more efficient, it would be very tricky to do
706 correctly, because we'd have to introduce a variable frag *after*
707 the delay slot instruction, and expand that instead. Let's do it
708 the easy way for now, even if the branch-not-taken case now costs
709 one additional instruction. Out-of-range branches are not supposed
710 to be common, anyway.
712 Branch likely. If label is out of range, we turn:
714 beql reg1, reg2, label
715 delay slot (annulled if branch not taken)
724 delay slot (executed only if branch taken)
727 It would be possible to generate a shorter sequence by losing the
728 likely bit, generating something like:
733 delay slot (executed only if branch taken)
745 bltzall -> bgezal (with jal label instead of j label)
746 bgezall -> bltzal (ditto)
749 but it's not clear that it would actually improve performance. */
750 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
753 | ((toofar) ? 1 : 0) \
755 | ((likely) ? 4 : 0) \
756 | ((uncond) ? 8 : 0)))
757 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
758 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
759 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
760 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
761 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
763 /* For mips16 code, we use an entirely different form of relaxation.
764 mips16 supports two versions of most instructions which take
765 immediate values: a small one which takes some small value, and a
766 larger one which takes a 16 bit value. Since branches also follow
767 this pattern, relaxing these values is required.
769 We can assemble both mips16 and normal MIPS code in a single
770 object. Therefore, we need to support this type of relaxation at
771 the same time that we support the relaxation described above. We
772 use the high bit of the subtype field to distinguish these cases.
774 The information we store for this type of relaxation is the
775 argument code found in the opcode file for this relocation, whether
776 the user explicitly requested a small or extended form, and whether
777 the relocation is in a jump or jal delay slot. That tells us the
778 size of the value, and how it should be stored. We also store
779 whether the fragment is considered to be extended or not. We also
780 store whether this is known to be a branch to a different section,
781 whether we have tried to relax this frag yet, and whether we have
782 ever extended a PC relative fragment because of a shift count. */
783 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
786 | ((small) ? 0x100 : 0) \
787 | ((ext) ? 0x200 : 0) \
788 | ((dslot) ? 0x400 : 0) \
789 | ((jal_dslot) ? 0x800 : 0))
790 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
791 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
792 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
793 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
794 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
795 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
796 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
797 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
798 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
799 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
800 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
801 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
803 /* Is the given value a sign-extended 32-bit value? */
804 #define IS_SEXT_32BIT_NUM(x) \
805 (((x) &~ (offsetT) 0x7fffffff) == 0 \
806 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
808 /* Is the given value a sign-extended 16-bit value? */
809 #define IS_SEXT_16BIT_NUM(x) \
810 (((x) &~ (offsetT) 0x7fff) == 0 \
811 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
814 /* Global variables used when generating relaxable macros. See the
815 comment above RELAX_ENCODE for more details about how relaxation
818 /* 0 if we're not emitting a relaxable macro.
819 1 if we're emitting the first of the two relaxation alternatives.
820 2 if we're emitting the second alternative. */
823 /* The first relaxable fixup in the current frag. (In other words,
824 the first fixup that refers to relaxable code.) */
827 /* sizes[0] says how many bytes of the first alternative are stored in
828 the current frag. Likewise sizes[1] for the second alternative. */
829 unsigned int sizes
[2];
831 /* The symbol on which the choice of sequence depends. */
835 /* Global variables used to decide whether a macro needs a warning. */
837 /* True if the macro is in a branch delay slot. */
838 bfd_boolean delay_slot_p
;
840 /* For relaxable macros, sizes[0] is the length of the first alternative
841 in bytes and sizes[1] is the length of the second alternative.
842 For non-relaxable macros, both elements give the length of the
844 unsigned int sizes
[2];
846 /* The first variant frag for this macro. */
848 } mips_macro_warning
;
850 /* Prototypes for static functions. */
852 #define internalError() \
853 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
855 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
857 static void append_insn
858 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
859 static void mips_no_prev_insn (int);
860 static void mips16_macro_build
861 (expressionS
*, const char *, const char *, va_list);
862 static void load_register (int, expressionS
*, int);
863 static void macro_start (void);
864 static void macro_end (void);
865 static void macro (struct mips_cl_insn
* ip
);
866 static void mips16_macro (struct mips_cl_insn
* ip
);
867 #ifdef LOSING_COMPILER
868 static void macro2 (struct mips_cl_insn
* ip
);
870 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
871 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
872 static void mips16_immed
873 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
874 unsigned long *, bfd_boolean
*, unsigned short *);
875 static size_t my_getSmallExpression
876 (expressionS
*, bfd_reloc_code_real_type
*, char *);
877 static void my_getExpression (expressionS
*, char *);
878 static void s_align (int);
879 static void s_change_sec (int);
880 static void s_change_section (int);
881 static void s_cons (int);
882 static void s_float_cons (int);
883 static void s_mips_globl (int);
884 static void s_option (int);
885 static void s_mipsset (int);
886 static void s_abicalls (int);
887 static void s_cpload (int);
888 static void s_cpsetup (int);
889 static void s_cplocal (int);
890 static void s_cprestore (int);
891 static void s_cpreturn (int);
892 static void s_gpvalue (int);
893 static void s_gpword (int);
894 static void s_gpdword (int);
895 static void s_cpadd (int);
896 static void s_insn (int);
897 static void md_obj_begin (void);
898 static void md_obj_end (void);
899 static void s_mips_ent (int);
900 static void s_mips_end (int);
901 static void s_mips_frame (int);
902 static void s_mips_mask (int reg_type
);
903 static void s_mips_stab (int);
904 static void s_mips_weakext (int);
905 static void s_mips_file (int);
906 static void s_mips_loc (int);
907 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
908 static int relaxed_branch_length (fragS
*, asection
*, int);
909 static int validate_mips_insn (const struct mips_opcode
*);
911 /* Table and functions used to map between CPU/ISA names, and
912 ISA levels, and CPU numbers. */
916 const char *name
; /* CPU or ISA name. */
917 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
918 int isa
; /* ISA level. */
919 int cpu
; /* CPU number (default CPU if ISA). */
922 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
923 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
924 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
928 The following pseudo-ops from the Kane and Heinrich MIPS book
929 should be defined here, but are currently unsupported: .alias,
930 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
932 The following pseudo-ops from the Kane and Heinrich MIPS book are
933 specific to the type of debugging information being generated, and
934 should be defined by the object format: .aent, .begin, .bend,
935 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
938 The following pseudo-ops from the Kane and Heinrich MIPS book are
939 not MIPS CPU specific, but are also not specific to the object file
940 format. This file is probably the best place to define them, but
941 they are not currently supported: .asm0, .endr, .lab, .repeat,
944 static const pseudo_typeS mips_pseudo_table
[] =
946 /* MIPS specific pseudo-ops. */
947 {"option", s_option
, 0},
948 {"set", s_mipsset
, 0},
949 {"rdata", s_change_sec
, 'r'},
950 {"sdata", s_change_sec
, 's'},
951 {"livereg", s_ignore
, 0},
952 {"abicalls", s_abicalls
, 0},
953 {"cpload", s_cpload
, 0},
954 {"cpsetup", s_cpsetup
, 0},
955 {"cplocal", s_cplocal
, 0},
956 {"cprestore", s_cprestore
, 0},
957 {"cpreturn", s_cpreturn
, 0},
958 {"gpvalue", s_gpvalue
, 0},
959 {"gpword", s_gpword
, 0},
960 {"gpdword", s_gpdword
, 0},
961 {"cpadd", s_cpadd
, 0},
964 /* Relatively generic pseudo-ops that happen to be used on MIPS
966 {"asciiz", stringer
, 1},
967 {"bss", s_change_sec
, 'b'},
970 {"dword", s_cons
, 3},
971 {"weakext", s_mips_weakext
, 0},
973 /* These pseudo-ops are defined in read.c, but must be overridden
974 here for one reason or another. */
975 {"align", s_align
, 0},
977 {"data", s_change_sec
, 'd'},
978 {"double", s_float_cons
, 'd'},
979 {"float", s_float_cons
, 'f'},
980 {"globl", s_mips_globl
, 0},
981 {"global", s_mips_globl
, 0},
982 {"hword", s_cons
, 1},
987 {"section", s_change_section
, 0},
988 {"short", s_cons
, 1},
989 {"single", s_float_cons
, 'f'},
990 {"stabn", s_mips_stab
, 'n'},
991 {"text", s_change_sec
, 't'},
994 { "extern", ecoff_directive_extern
, 0},
999 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1001 /* These pseudo-ops should be defined by the object file format.
1002 However, a.out doesn't support them, so we have versions here. */
1003 {"aent", s_mips_ent
, 1},
1004 {"bgnb", s_ignore
, 0},
1005 {"end", s_mips_end
, 0},
1006 {"endb", s_ignore
, 0},
1007 {"ent", s_mips_ent
, 0},
1008 {"file", s_mips_file
, 0},
1009 {"fmask", s_mips_mask
, 'F'},
1010 {"frame", s_mips_frame
, 0},
1011 {"loc", s_mips_loc
, 0},
1012 {"mask", s_mips_mask
, 'R'},
1013 {"verstamp", s_ignore
, 0},
1017 extern void pop_insert (const pseudo_typeS
*);
1020 mips_pop_insert (void)
1022 pop_insert (mips_pseudo_table
);
1023 if (! ECOFF_DEBUGGING
)
1024 pop_insert (mips_nonecoff_pseudo_table
);
1027 /* Symbols labelling the current insn. */
1029 struct insn_label_list
1031 struct insn_label_list
*next
;
1035 static struct insn_label_list
*insn_labels
;
1036 static struct insn_label_list
*free_insn_labels
;
1038 static void mips_clear_insn_labels (void);
1041 mips_clear_insn_labels (void)
1043 register struct insn_label_list
**pl
;
1045 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1051 static char *expr_end
;
1053 /* Expressions which appear in instructions. These are set by
1056 static expressionS imm_expr
;
1057 static expressionS imm2_expr
;
1058 static expressionS offset_expr
;
1060 /* Relocs associated with imm_expr and offset_expr. */
1062 static bfd_reloc_code_real_type imm_reloc
[3]
1063 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1064 static bfd_reloc_code_real_type offset_reloc
[3]
1065 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1067 /* These are set by mips16_ip if an explicit extension is used. */
1069 static bfd_boolean mips16_small
, mips16_ext
;
1072 /* The pdr segment for per procedure frame/regmask info. Not used for
1075 static segT pdr_seg
;
1078 /* The default target format to use. */
1081 mips_target_format (void)
1083 switch (OUTPUT_FLAVOR
)
1085 case bfd_target_ecoff_flavour
:
1086 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1087 case bfd_target_coff_flavour
:
1089 case bfd_target_elf_flavour
:
1091 /* This is traditional mips. */
1092 return (target_big_endian
1093 ? (HAVE_64BIT_OBJECTS
1094 ? "elf64-tradbigmips"
1096 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1097 : (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradlittlemips"
1100 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1102 return (target_big_endian
1103 ? (HAVE_64BIT_OBJECTS
1106 ? "elf32-nbigmips" : "elf32-bigmips"))
1107 : (HAVE_64BIT_OBJECTS
1108 ? "elf64-littlemips"
1110 ? "elf32-nlittlemips" : "elf32-littlemips")));
1118 /* This function is called once, at assembler startup time. It should
1119 set up all the tables, etc. that the MD part of the assembler will need. */
1124 register const char *retval
= NULL
;
1128 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1129 as_warn (_("Could not set architecture and machine"));
1131 op_hash
= hash_new ();
1133 for (i
= 0; i
< NUMOPCODES
;)
1135 const char *name
= mips_opcodes
[i
].name
;
1137 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1140 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1141 mips_opcodes
[i
].name
, retval
);
1142 /* Probably a memory allocation problem? Give up now. */
1143 as_fatal (_("Broken assembler. No assembly attempted."));
1147 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1149 if (!validate_mips_insn (&mips_opcodes
[i
]))
1154 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1157 mips16_op_hash
= hash_new ();
1160 while (i
< bfd_mips16_num_opcodes
)
1162 const char *name
= mips16_opcodes
[i
].name
;
1164 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1166 as_fatal (_("internal: can't hash `%s': %s"),
1167 mips16_opcodes
[i
].name
, retval
);
1170 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1171 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1172 != mips16_opcodes
[i
].match
))
1174 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1175 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1180 while (i
< bfd_mips16_num_opcodes
1181 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1185 as_fatal (_("Broken assembler. No assembly attempted."));
1187 /* We add all the general register names to the symbol table. This
1188 helps us detect invalid uses of them. */
1189 for (i
= 0; i
< 32; i
++)
1193 sprintf (buf
, "$%d", i
);
1194 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1195 &zero_address_frag
));
1197 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1198 &zero_address_frag
));
1199 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1200 &zero_address_frag
));
1201 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1202 &zero_address_frag
));
1203 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1204 &zero_address_frag
));
1205 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1206 &zero_address_frag
));
1207 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1208 &zero_address_frag
));
1209 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1210 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1214 &zero_address_frag
));
1216 /* If we don't add these register names to the symbol table, they
1217 may end up being added as regular symbols by operand(), and then
1218 make it to the object file as undefined in case they're not
1219 regarded as local symbols. They're local in o32, since `$' is a
1220 local symbol prefix, but not in n32 or n64. */
1221 for (i
= 0; i
< 8; i
++)
1225 sprintf (buf
, "$fcc%i", i
);
1226 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1227 &zero_address_frag
));
1230 mips_no_prev_insn (FALSE
);
1233 mips_cprmask
[0] = 0;
1234 mips_cprmask
[1] = 0;
1235 mips_cprmask
[2] = 0;
1236 mips_cprmask
[3] = 0;
1238 /* set the default alignment for the text section (2**2) */
1239 record_alignment (text_section
, 2);
1241 bfd_set_gp_size (stdoutput
, g_switch_value
);
1243 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1245 /* On a native system, sections must be aligned to 16 byte
1246 boundaries. When configured for an embedded ELF target, we
1248 if (strcmp (TARGET_OS
, "elf") != 0)
1250 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1251 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1252 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1255 /* Create a .reginfo section for register masks and a .mdebug
1256 section for debugging information. */
1264 subseg
= now_subseg
;
1266 /* The ABI says this section should be loaded so that the
1267 running program can access it. However, we don't load it
1268 if we are configured for an embedded target */
1269 flags
= SEC_READONLY
| SEC_DATA
;
1270 if (strcmp (TARGET_OS
, "elf") != 0)
1271 flags
|= SEC_ALLOC
| SEC_LOAD
;
1273 if (mips_abi
!= N64_ABI
)
1275 sec
= subseg_new (".reginfo", (subsegT
) 0);
1277 bfd_set_section_flags (stdoutput
, sec
, flags
);
1278 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1281 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1286 /* The 64-bit ABI uses a .MIPS.options section rather than
1287 .reginfo section. */
1288 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1289 bfd_set_section_flags (stdoutput
, sec
, flags
);
1290 bfd_set_section_alignment (stdoutput
, sec
, 3);
1293 /* Set up the option header. */
1295 Elf_Internal_Options opthdr
;
1298 opthdr
.kind
= ODK_REGINFO
;
1299 opthdr
.size
= (sizeof (Elf_External_Options
)
1300 + sizeof (Elf64_External_RegInfo
));
1303 f
= frag_more (sizeof (Elf_External_Options
));
1304 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1305 (Elf_External_Options
*) f
);
1307 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1312 if (ECOFF_DEBUGGING
)
1314 sec
= subseg_new (".mdebug", (subsegT
) 0);
1315 (void) bfd_set_section_flags (stdoutput
, sec
,
1316 SEC_HAS_CONTENTS
| SEC_READONLY
);
1317 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1320 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1322 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1323 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1324 SEC_READONLY
| SEC_RELOC
1326 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1330 subseg_set (seg
, subseg
);
1334 if (! ECOFF_DEBUGGING
)
1341 if (! ECOFF_DEBUGGING
)
1346 md_assemble (char *str
)
1348 struct mips_cl_insn insn
;
1349 bfd_reloc_code_real_type unused_reloc
[3]
1350 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1352 imm_expr
.X_op
= O_absent
;
1353 imm2_expr
.X_op
= O_absent
;
1354 offset_expr
.X_op
= O_absent
;
1355 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1356 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1357 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1358 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1359 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1360 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1362 if (mips_opts
.mips16
)
1363 mips16_ip (str
, &insn
);
1366 mips_ip (str
, &insn
);
1367 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1368 str
, insn
.insn_opcode
));
1373 as_bad ("%s `%s'", insn_error
, str
);
1377 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1380 if (mips_opts
.mips16
)
1381 mips16_macro (&insn
);
1388 if (imm_expr
.X_op
!= O_absent
)
1389 append_insn (&insn
, &imm_expr
, imm_reloc
);
1390 else if (offset_expr
.X_op
!= O_absent
)
1391 append_insn (&insn
, &offset_expr
, offset_reloc
);
1393 append_insn (&insn
, NULL
, unused_reloc
);
1397 /* Return true if the given relocation might need a matching %lo().
1398 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1399 applied to local symbols. */
1401 static inline bfd_boolean
1402 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1404 return (HAVE_IN_PLACE_ADDENDS
1405 && (reloc
== BFD_RELOC_HI16_S
1406 || reloc
== BFD_RELOC_MIPS_GOT16
));
1409 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1412 static inline bfd_boolean
1413 fixup_has_matching_lo_p (fixS
*fixp
)
1415 return (fixp
->fx_next
!= NULL
1416 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1417 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1418 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1421 /* See whether instruction IP reads register REG. CLASS is the type
1425 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1426 enum mips_regclass
class)
1428 if (class == MIPS16_REG
)
1430 assert (mips_opts
.mips16
);
1431 reg
= mips16_to_32_reg_map
[reg
];
1432 class = MIPS_GR_REG
;
1435 /* Don't report on general register ZERO, since it never changes. */
1436 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1439 if (class == MIPS_FP_REG
)
1441 assert (! mips_opts
.mips16
);
1442 /* If we are called with either $f0 or $f1, we must check $f0.
1443 This is not optimal, because it will introduce an unnecessary
1444 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1445 need to distinguish reading both $f0 and $f1 or just one of
1446 them. Note that we don't have to check the other way,
1447 because there is no instruction that sets both $f0 and $f1
1448 and requires a delay. */
1449 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1450 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1451 == (reg
&~ (unsigned) 1)))
1453 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1454 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1455 == (reg
&~ (unsigned) 1)))
1458 else if (! mips_opts
.mips16
)
1460 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1461 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1463 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1464 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1469 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1470 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1471 & MIPS16OP_MASK_RX
)]
1474 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1475 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1476 & MIPS16OP_MASK_RY
)]
1479 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1480 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1481 & MIPS16OP_MASK_MOVE32Z
)]
1484 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1486 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1488 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1490 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1491 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1492 & MIPS16OP_MASK_REGR32
) == reg
)
1499 /* This function returns true if modifying a register requires a
1503 reg_needs_delay (unsigned int reg
)
1505 unsigned long prev_pinfo
;
1507 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1508 if (! mips_opts
.noreorder
1509 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1510 && ! gpr_interlocks
)
1511 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1512 && ! cop_interlocks
)))
1514 /* A load from a coprocessor or from memory. All load delays
1515 delay the use of general register rt for one instruction. */
1516 /* Itbl support may require additional care here. */
1517 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1518 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1525 /* Mark instruction labels in mips16 mode. This permits the linker to
1526 handle them specially, such as generating jalx instructions when
1527 needed. We also make them odd for the duration of the assembly, in
1528 order to generate the right sort of code. We will make them even
1529 in the adjust_symtab routine, while leaving them marked. This is
1530 convenient for the debugger and the disassembler. The linker knows
1531 to make them odd again. */
1534 mips16_mark_labels (void)
1536 if (mips_opts
.mips16
)
1538 struct insn_label_list
*l
;
1541 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1544 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1545 S_SET_OTHER (l
->label
, STO_MIPS16
);
1547 val
= S_GET_VALUE (l
->label
);
1549 S_SET_VALUE (l
->label
, val
+ 1);
1554 /* End the current frag. Make it a variant frag and record the
1558 relax_close_frag (void)
1560 mips_macro_warning
.first_frag
= frag_now
;
1561 frag_var (rs_machine_dependent
, 0, 0,
1562 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1563 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1565 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1566 mips_relax
.first_fixup
= 0;
1569 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1570 See the comment above RELAX_ENCODE for more details. */
1573 relax_start (symbolS
*symbol
)
1575 assert (mips_relax
.sequence
== 0);
1576 mips_relax
.sequence
= 1;
1577 mips_relax
.symbol
= symbol
;
1580 /* Start generating the second version of a relaxable sequence.
1581 See the comment above RELAX_ENCODE for more details. */
1586 assert (mips_relax
.sequence
== 1);
1587 mips_relax
.sequence
= 2;
1590 /* End the current relaxable sequence. */
1595 assert (mips_relax
.sequence
== 2);
1596 relax_close_frag ();
1597 mips_relax
.sequence
= 0;
1600 /* Output an instruction. IP is the instruction information.
1601 ADDRESS_EXPR is an operand of the instruction to be used with
1605 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1606 bfd_reloc_code_real_type
*reloc_type
)
1608 register unsigned long prev_pinfo
, pinfo
;
1612 relax_stateT prev_insn_frag_type
= 0;
1613 bfd_boolean relaxed_branch
= FALSE
;
1614 bfd_boolean force_new_frag
= FALSE
;
1616 /* Mark instruction labels in mips16 mode. */
1617 mips16_mark_labels ();
1619 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1620 pinfo
= ip
->insn_mo
->pinfo
;
1622 if (mips_relax
.sequence
!= 2
1623 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1627 /* If the previous insn required any delay slots, see if we need
1628 to insert a NOP or two. There are eight kinds of possible
1629 hazards, of which an instruction can have at most one type.
1630 (1) a load from memory delay
1631 (2) a load from a coprocessor delay
1632 (3) an unconditional branch delay
1633 (4) a conditional branch delay
1634 (5) a move to coprocessor register delay
1635 (6) a load coprocessor register from memory delay
1636 (7) a coprocessor condition code delay
1637 (8) a HI/LO special register delay
1639 There are a lot of optimizations we could do that we don't.
1640 In particular, we do not, in general, reorder instructions.
1641 If you use gcc with optimization, it will reorder
1642 instructions and generally do much more optimization then we
1643 do here; repeating all that work in the assembler would only
1644 benefit hand written assembly code, and does not seem worth
1647 /* This is how a NOP is emitted. */
1648 #define emit_nop() \
1650 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1651 : md_number_to_chars (frag_more (4), 0, 4))
1653 /* The previous insn might require a delay slot, depending upon
1654 the contents of the current insn. */
1655 if (! mips_opts
.mips16
1656 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1657 && ! gpr_interlocks
)
1658 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1659 && ! cop_interlocks
)))
1661 /* A load from a coprocessor or from memory. All load
1662 delays delay the use of general register rt for one
1664 /* Itbl support may require additional care here. */
1665 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1666 if (mips_optimize
== 0
1667 || insn_uses_reg (ip
,
1668 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1673 else if (! mips_opts
.mips16
1674 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1675 && ! cop_interlocks
)
1676 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1677 && ! cop_mem_interlocks
)))
1679 /* A generic coprocessor delay. The previous instruction
1680 modified a coprocessor general or control register. If
1681 it modified a control register, we need to avoid any
1682 coprocessor instruction (this is probably not always
1683 required, but it sometimes is). If it modified a general
1684 register, we avoid using that register.
1686 This case is not handled very well. There is no special
1687 knowledge of CP0 handling, and the coprocessors other
1688 than the floating point unit are not distinguished at
1690 /* Itbl support may require additional care here. FIXME!
1691 Need to modify this to include knowledge about
1692 user specified delays! */
1693 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1695 if (mips_optimize
== 0
1696 || insn_uses_reg (ip
,
1697 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1702 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1704 if (mips_optimize
== 0
1705 || insn_uses_reg (ip
,
1706 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1713 /* We don't know exactly what the previous instruction
1714 does. If the current instruction uses a coprocessor
1715 register, we must insert a NOP. If previous
1716 instruction may set the condition codes, and the
1717 current instruction uses them, we must insert two
1719 /* Itbl support may require additional care here. */
1720 if (mips_optimize
== 0
1721 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1722 && (pinfo
& INSN_READ_COND_CODE
)))
1724 else if (pinfo
& INSN_COP
)
1728 else if (! mips_opts
.mips16
1729 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1730 && ! cop_interlocks
)
1732 /* The previous instruction sets the coprocessor condition
1733 codes, but does not require a general coprocessor delay
1734 (this means it is a floating point comparison
1735 instruction). If this instruction uses the condition
1736 codes, we need to insert a single NOP. */
1737 /* Itbl support may require additional care here. */
1738 if (mips_optimize
== 0
1739 || (pinfo
& INSN_READ_COND_CODE
))
1743 /* If we're fixing up mfhi/mflo for the r7000 and the
1744 previous insn was an mfhi/mflo and the current insn
1745 reads the register that the mfhi/mflo wrote to, then
1748 else if (mips_7000_hilo_fix
1749 && MF_HILO_INSN (prev_pinfo
)
1750 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1757 /* If we're fixing up mfhi/mflo for the r7000 and the
1758 2nd previous insn was an mfhi/mflo and the current insn
1759 reads the register that the mfhi/mflo wrote to, then
1762 else if (mips_7000_hilo_fix
1763 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1764 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1772 else if (prev_pinfo
& INSN_READ_LO
)
1774 /* The previous instruction reads the LO register; if the
1775 current instruction writes to the LO register, we must
1776 insert two NOPS. Some newer processors have interlocks.
1777 Also the tx39's multiply instructions can be executed
1778 immediately after a read from HI/LO (without the delay),
1779 though the tx39's divide insns still do require the
1781 if (! (hilo_interlocks
1782 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1783 && (mips_optimize
== 0
1784 || (pinfo
& INSN_WRITE_LO
)))
1786 /* Most mips16 branch insns don't have a delay slot.
1787 If a read from LO is immediately followed by a branch
1788 to a write to LO we have a read followed by a write
1789 less than 2 insns away. We assume the target of
1790 a branch might be a write to LO, and insert a nop
1791 between a read and an immediately following branch. */
1792 else if (mips_opts
.mips16
1793 && (mips_optimize
== 0
1794 || (pinfo
& MIPS16_INSN_BRANCH
)))
1797 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1799 /* The previous instruction reads the HI register; if the
1800 current instruction writes to the HI register, we must
1801 insert a NOP. Some newer processors have interlocks.
1802 Also the note tx39's multiply above. */
1803 if (! (hilo_interlocks
1804 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1805 && (mips_optimize
== 0
1806 || (pinfo
& INSN_WRITE_HI
)))
1808 /* Most mips16 branch insns don't have a delay slot.
1809 If a read from HI is immediately followed by a branch
1810 to a write to HI we have a read followed by a write
1811 less than 2 insns away. We assume the target of
1812 a branch might be a write to HI, and insert a nop
1813 between a read and an immediately following branch. */
1814 else if (mips_opts
.mips16
1815 && (mips_optimize
== 0
1816 || (pinfo
& MIPS16_INSN_BRANCH
)))
1820 /* If the previous instruction was in a noreorder section, then
1821 we don't want to insert the nop after all. */
1822 /* Itbl support may require additional care here. */
1823 if (prev_insn_unreordered
)
1826 /* There are two cases which require two intervening
1827 instructions: 1) setting the condition codes using a move to
1828 coprocessor instruction which requires a general coprocessor
1829 delay and then reading the condition codes 2) reading the HI
1830 or LO register and then writing to it (except on processors
1831 which have interlocks). If we are not already emitting a NOP
1832 instruction, we must check for these cases compared to the
1833 instruction previous to the previous instruction. */
1834 if ((! mips_opts
.mips16
1835 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1836 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1837 && (pinfo
& INSN_READ_COND_CODE
)
1838 && ! cop_interlocks
)
1839 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1840 && (pinfo
& INSN_WRITE_LO
)
1841 && ! (hilo_interlocks
1842 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1843 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1844 && (pinfo
& INSN_WRITE_HI
)
1845 && ! (hilo_interlocks
1846 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1851 if (prev_prev_insn_unreordered
)
1854 if (prev_prev_nop
&& nops
== 0)
1857 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1859 /* We're out of bits in pinfo, so we must resort to string
1860 ops here. Shortcuts are selected based on opcodes being
1861 limited to the VR4120 instruction set. */
1863 const char *pn
= prev_insn
.insn_mo
->name
;
1864 const char *tn
= ip
->insn_mo
->name
;
1865 if (strncmp (pn
, "macc", 4) == 0
1866 || strncmp (pn
, "dmacc", 5) == 0)
1868 /* Errata 21 - [D]DIV[U] after [D]MACC */
1869 if (strstr (tn
, "div"))
1872 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1873 instruction is executed immediately after a MACC or
1874 DMACC instruction, the result of [either instruction]
1876 if (strncmp (tn
, "mult", 4) == 0
1877 || strncmp (tn
, "dmult", 5) == 0)
1880 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1881 Applies on top of VR4181A MD(1) errata. */
1882 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1885 /* Errata 24 - MT{LO,HI} after [D]MACC */
1886 if (strcmp (tn
, "mtlo") == 0
1887 || strcmp (tn
, "mthi") == 0)
1890 else if (strncmp (pn
, "dmult", 5) == 0
1891 && (strncmp (tn
, "dmult", 5) == 0
1892 || strncmp (tn
, "dmacc", 5) == 0))
1894 /* Here is the rest of errata 23. */
1897 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1898 && (strncmp (tn
, "macc", 4) == 0
1899 || strncmp (tn
, "dmacc", 5) == 0))
1901 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1902 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1903 DDIV or DDIVU instruction, the result of the MACC or
1904 DMACC instruction is incorrect.". This partly overlaps
1905 the workaround for errata 23. */
1908 if (nops
< min_nops
)
1912 /* If we are being given a nop instruction, don't bother with
1913 one of the nops we would otherwise output. This will only
1914 happen when a nop instruction is used with mips_optimize set
1917 && ! mips_opts
.noreorder
1918 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1921 /* Now emit the right number of NOP instructions. */
1922 if (nops
> 0 && ! mips_opts
.noreorder
)
1925 unsigned long old_frag_offset
;
1927 struct insn_label_list
*l
;
1929 old_frag
= frag_now
;
1930 old_frag_offset
= frag_now_fix ();
1932 for (i
= 0; i
< nops
; i
++)
1937 listing_prev_line ();
1938 /* We may be at the start of a variant frag. In case we
1939 are, make sure there is enough space for the frag
1940 after the frags created by listing_prev_line. The
1941 argument to frag_grow here must be at least as large
1942 as the argument to all other calls to frag_grow in
1943 this file. We don't have to worry about being in the
1944 middle of a variant frag, because the variants insert
1945 all needed nop instructions themselves. */
1949 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1953 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1954 symbol_set_frag (l
->label
, frag_now
);
1955 val
= (valueT
) frag_now_fix ();
1956 /* mips16 text labels are stored as odd. */
1957 if (mips_opts
.mips16
)
1959 S_SET_VALUE (l
->label
, val
);
1962 #ifndef NO_ECOFF_DEBUGGING
1963 if (ECOFF_DEBUGGING
)
1964 ecoff_fix_loc (old_frag
, old_frag_offset
);
1967 else if (prev_nop_frag
!= NULL
)
1969 /* We have a frag holding nops we may be able to remove. If
1970 we don't need any nops, we can decrease the size of
1971 prev_nop_frag by the size of one instruction. If we do
1972 need some nops, we count them in prev_nops_required. */
1973 if (prev_nop_frag_since
== 0)
1977 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1978 --prev_nop_frag_holds
;
1981 prev_nop_frag_required
+= nops
;
1985 if (prev_prev_nop
== 0)
1987 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1988 --prev_nop_frag_holds
;
1991 ++prev_nop_frag_required
;
1994 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1995 prev_nop_frag
= NULL
;
1997 ++prev_nop_frag_since
;
1999 /* Sanity check: by the time we reach the second instruction
2000 after prev_nop_frag, we should have used up all the nops
2001 one way or another. */
2002 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2006 /* Record the frag type before frag_var. */
2008 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
2011 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2012 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2013 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2014 && mips_relax_branch
2015 /* Don't try branch relaxation within .set nomacro, or within
2016 .set noat if we use $at for PIC computations. If it turns
2017 out that the branch was out-of-range, we'll get an error. */
2018 && !mips_opts
.warn_about_macros
2019 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2020 && !mips_opts
.mips16
)
2022 relaxed_branch
= TRUE
;
2023 f
= frag_var (rs_machine_dependent
,
2024 relaxed_branch_length
2026 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2027 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2029 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2030 pinfo
& INSN_COND_BRANCH_LIKELY
,
2031 pinfo
& INSN_WRITE_GPR_31
,
2033 address_expr
->X_add_symbol
,
2034 address_expr
->X_add_number
,
2036 *reloc_type
= BFD_RELOC_UNUSED
;
2038 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2040 /* We need to set up a variant frag. */
2041 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2042 f
= frag_var (rs_machine_dependent
, 4, 0,
2043 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2044 mips16_small
, mips16_ext
,
2046 & INSN_UNCOND_BRANCH_DELAY
),
2047 (*prev_insn_reloc_type
2048 == BFD_RELOC_MIPS16_JMP
)),
2049 make_expr_symbol (address_expr
), 0, NULL
);
2051 else if (mips_opts
.mips16
2053 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2055 /* Make sure there is enough room to swap this instruction with
2056 a following jump instruction. */
2062 if (mips_opts
.mips16
2063 && mips_opts
.noreorder
2064 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2065 as_warn (_("extended instruction in delay slot"));
2067 if (mips_relax
.sequence
)
2069 /* If we've reached the end of this frag, turn it into a variant
2070 frag and record the information for the instructions we've
2072 if (frag_room () < 4)
2073 relax_close_frag ();
2074 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2077 if (mips_relax
.sequence
!= 2)
2078 mips_macro_warning
.sizes
[0] += 4;
2079 if (mips_relax
.sequence
!= 1)
2080 mips_macro_warning
.sizes
[1] += 4;
2085 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2086 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2088 if (address_expr
->X_op
== O_constant
)
2092 switch (*reloc_type
)
2095 ip
->insn_opcode
|= address_expr
->X_add_number
;
2098 case BFD_RELOC_MIPS_HIGHEST
:
2099 tmp
= (address_expr
->X_add_number
2100 + ((valueT
) 0x8000 << 32) + 0x80008000) >> 16;
2102 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2105 case BFD_RELOC_MIPS_HIGHER
:
2106 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2107 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2110 case BFD_RELOC_HI16_S
:
2111 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2115 case BFD_RELOC_HI16
:
2116 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2119 case BFD_RELOC_UNUSED
:
2120 case BFD_RELOC_LO16
:
2121 case BFD_RELOC_MIPS_GOT_DISP
:
2122 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2125 case BFD_RELOC_MIPS_JMP
:
2126 if ((address_expr
->X_add_number
& 3) != 0)
2127 as_bad (_("jump to misaligned address (0x%lx)"),
2128 (unsigned long) address_expr
->X_add_number
);
2129 if (address_expr
->X_add_number
& ~0xfffffff)
2130 as_bad (_("jump address range overflow (0x%lx)"),
2131 (unsigned long) address_expr
->X_add_number
);
2132 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2135 case BFD_RELOC_MIPS16_JMP
:
2136 if ((address_expr
->X_add_number
& 3) != 0)
2137 as_bad (_("jump to misaligned address (0x%lx)"),
2138 (unsigned long) address_expr
->X_add_number
);
2139 if (address_expr
->X_add_number
& ~0xfffffff)
2140 as_bad (_("jump address range overflow (0x%lx)"),
2141 (unsigned long) address_expr
->X_add_number
);
2143 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2144 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2145 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2148 case BFD_RELOC_16_PCREL_S2
:
2155 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2158 reloc_howto_type
*howto
;
2161 /* In a compound relocation, it is the final (outermost)
2162 operator that determines the relocated field. */
2163 for (i
= 1; i
< 3; i
++)
2164 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2167 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2168 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2169 bfd_get_reloc_size(howto
),
2171 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2174 /* These relocations can have an addend that won't fit in
2175 4 octets for 64bit assembly. */
2177 && ! howto
->partial_inplace
2178 && (reloc_type
[0] == BFD_RELOC_16
2179 || reloc_type
[0] == BFD_RELOC_32
2180 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2181 || reloc_type
[0] == BFD_RELOC_HI16_S
2182 || reloc_type
[0] == BFD_RELOC_LO16
2183 || reloc_type
[0] == BFD_RELOC_GPREL16
2184 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2185 || reloc_type
[0] == BFD_RELOC_GPREL32
2186 || reloc_type
[0] == BFD_RELOC_64
2187 || reloc_type
[0] == BFD_RELOC_CTOR
2188 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2189 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2190 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2191 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2192 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2193 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2194 fixp
[0]->fx_no_overflow
= 1;
2196 if (mips_relax
.sequence
)
2198 if (mips_relax
.first_fixup
== 0)
2199 mips_relax
.first_fixup
= fixp
[0];
2201 else if (reloc_needs_lo_p (*reloc_type
))
2203 struct mips_hi_fixup
*hi_fixup
;
2205 /* Reuse the last entry if it already has a matching %lo. */
2206 hi_fixup
= mips_hi_fixup_list
;
2208 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2210 hi_fixup
= ((struct mips_hi_fixup
*)
2211 xmalloc (sizeof (struct mips_hi_fixup
)));
2212 hi_fixup
->next
= mips_hi_fixup_list
;
2213 mips_hi_fixup_list
= hi_fixup
;
2215 hi_fixup
->fixp
= fixp
[0];
2216 hi_fixup
->seg
= now_seg
;
2219 /* Add fixups for the second and third relocations, if given.
2220 Note that the ABI allows the second relocation to be
2221 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2222 moment we only use RSS_UNDEF, but we could add support
2223 for the others if it ever becomes necessary. */
2224 for (i
= 1; i
< 3; i
++)
2225 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2227 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2228 fixp
[0]->fx_size
, NULL
, 0,
2229 FALSE
, reloc_type
[i
]);
2231 /* Use fx_tcbit to mark compound relocs. */
2232 fixp
[0]->fx_tcbit
= 1;
2233 fixp
[i
]->fx_tcbit
= 1;
2238 if (! mips_opts
.mips16
)
2240 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2242 dwarf2_emit_insn (4);
2245 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2247 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2248 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2250 /* The value passed to dwarf2_emit_insn is the distance between
2251 the end of the current instruction and the address that should
2252 be recorded in the debug tables. Since we want to use ISA-encoded
2253 addresses in MIPS16 debug info, the value is one byte less than
2254 the real instruction length. */
2255 dwarf2_emit_insn (3);
2262 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2265 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2267 dwarf2_emit_insn (ip
->use_extend
? 3 : 1);
2271 /* Update the register mask information. */
2272 if (! mips_opts
.mips16
)
2274 if (pinfo
& INSN_WRITE_GPR_D
)
2275 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2276 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2277 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2278 if (pinfo
& INSN_READ_GPR_S
)
2279 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2280 if (pinfo
& INSN_WRITE_GPR_31
)
2281 mips_gprmask
|= 1 << RA
;
2282 if (pinfo
& INSN_WRITE_FPR_D
)
2283 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2284 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2285 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2286 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2287 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2288 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2289 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2290 if (pinfo
& INSN_COP
)
2292 /* We don't keep enough information to sort these cases out.
2293 The itbl support does keep this information however, although
2294 we currently don't support itbl fprmats as part of the cop
2295 instruction. May want to add this support in the future. */
2297 /* Never set the bit for $0, which is always zero. */
2298 mips_gprmask
&= ~1 << 0;
2302 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2303 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2304 & MIPS16OP_MASK_RX
);
2305 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2306 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2307 & MIPS16OP_MASK_RY
);
2308 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2309 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2310 & MIPS16OP_MASK_RZ
);
2311 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2312 mips_gprmask
|= 1 << TREG
;
2313 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2314 mips_gprmask
|= 1 << SP
;
2315 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2316 mips_gprmask
|= 1 << RA
;
2317 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2318 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2319 if (pinfo
& MIPS16_INSN_READ_Z
)
2320 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2321 & MIPS16OP_MASK_MOVE32Z
);
2322 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2323 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2324 & MIPS16OP_MASK_REGR32
);
2327 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2329 /* Filling the branch delay slot is more complex. We try to
2330 switch the branch with the previous instruction, which we can
2331 do if the previous instruction does not set up a condition
2332 that the branch tests and if the branch is not itself the
2333 target of any branch. */
2334 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2335 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2337 if (mips_optimize
< 2
2338 /* If we have seen .set volatile or .set nomove, don't
2340 || mips_opts
.nomove
!= 0
2341 /* If we had to emit any NOP instructions, then we
2342 already know we can not swap. */
2344 /* If we don't even know the previous insn, we can not
2346 || ! prev_insn_valid
2347 /* If the previous insn is already in a branch delay
2348 slot, then we can not swap. */
2349 || prev_insn_is_delay_slot
2350 /* If the previous previous insn was in a .set
2351 noreorder, we can't swap. Actually, the MIPS
2352 assembler will swap in this situation. However, gcc
2353 configured -with-gnu-as will generate code like
2359 in which we can not swap the bne and INSN. If gcc is
2360 not configured -with-gnu-as, it does not output the
2361 .set pseudo-ops. We don't have to check
2362 prev_insn_unreordered, because prev_insn_valid will
2363 be 0 in that case. We don't want to use
2364 prev_prev_insn_valid, because we do want to be able
2365 to swap at the start of a function. */
2366 || prev_prev_insn_unreordered
2367 /* If the branch is itself the target of a branch, we
2368 can not swap. We cheat on this; all we check for is
2369 whether there is a label on this instruction. If
2370 there are any branches to anything other than a
2371 label, users must use .set noreorder. */
2372 || insn_labels
!= NULL
2373 /* If the previous instruction is in a variant frag
2374 other than this branch's one, we cannot do the swap.
2375 This does not apply to the mips16, which uses variant
2376 frags for different purposes. */
2377 || (! mips_opts
.mips16
2378 && prev_insn_frag_type
== rs_machine_dependent
)
2379 /* If the branch reads the condition codes, we don't
2380 even try to swap, because in the sequence
2385 we can not swap, and I don't feel like handling that
2387 || (! mips_opts
.mips16
2388 && (pinfo
& INSN_READ_COND_CODE
)
2389 && ! cop_interlocks
)
2390 /* We can not swap with an instruction that requires a
2391 delay slot, because the target of the branch might
2392 interfere with that instruction. */
2393 || (! mips_opts
.mips16
2395 /* Itbl support may require additional care here. */
2396 & (INSN_LOAD_COPROC_DELAY
2397 | INSN_COPROC_MOVE_DELAY
2398 | INSN_WRITE_COND_CODE
))
2399 && ! cop_interlocks
)
2400 || (! (hilo_interlocks
2401 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2405 || (! mips_opts
.mips16
2406 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2407 && ! gpr_interlocks
)
2408 || (! mips_opts
.mips16
2409 /* Itbl support may require additional care here. */
2410 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2411 && ! cop_mem_interlocks
)
2412 /* We can not swap with a branch instruction. */
2414 & (INSN_UNCOND_BRANCH_DELAY
2415 | INSN_COND_BRANCH_DELAY
2416 | INSN_COND_BRANCH_LIKELY
))
2417 /* We do not swap with a trap instruction, since it
2418 complicates trap handlers to have the trap
2419 instruction be in a delay slot. */
2420 || (prev_pinfo
& INSN_TRAP
)
2421 /* If the branch reads a register that the previous
2422 instruction sets, we can not swap. */
2423 || (! mips_opts
.mips16
2424 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2425 && insn_uses_reg (ip
,
2426 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2429 || (! mips_opts
.mips16
2430 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2431 && insn_uses_reg (ip
,
2432 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2435 || (mips_opts
.mips16
2436 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2437 && insn_uses_reg (ip
,
2438 ((prev_insn
.insn_opcode
2440 & MIPS16OP_MASK_RX
),
2442 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2443 && insn_uses_reg (ip
,
2444 ((prev_insn
.insn_opcode
2446 & MIPS16OP_MASK_RY
),
2448 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2449 && insn_uses_reg (ip
,
2450 ((prev_insn
.insn_opcode
2452 & MIPS16OP_MASK_RZ
),
2454 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2455 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2456 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2457 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2458 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2459 && insn_uses_reg (ip
,
2460 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2463 /* If the branch writes a register that the previous
2464 instruction sets, we can not swap (we know that
2465 branches write only to RD or to $31). */
2466 || (! mips_opts
.mips16
2467 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2468 && (((pinfo
& INSN_WRITE_GPR_D
)
2469 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2470 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2471 || ((pinfo
& INSN_WRITE_GPR_31
)
2472 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2475 || (! mips_opts
.mips16
2476 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2477 && (((pinfo
& INSN_WRITE_GPR_D
)
2478 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2479 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2480 || ((pinfo
& INSN_WRITE_GPR_31
)
2481 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2484 || (mips_opts
.mips16
2485 && (pinfo
& MIPS16_INSN_WRITE_31
)
2486 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2487 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2488 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2490 /* If the branch writes a register that the previous
2491 instruction reads, we can not swap (we know that
2492 branches only write to RD or to $31). */
2493 || (! mips_opts
.mips16
2494 && (pinfo
& INSN_WRITE_GPR_D
)
2495 && insn_uses_reg (&prev_insn
,
2496 ((ip
->insn_opcode
>> OP_SH_RD
)
2499 || (! mips_opts
.mips16
2500 && (pinfo
& INSN_WRITE_GPR_31
)
2501 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2502 || (mips_opts
.mips16
2503 && (pinfo
& MIPS16_INSN_WRITE_31
)
2504 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2505 /* If the previous previous instruction has a load
2506 delay, and sets a register that the branch reads, we
2508 || (! mips_opts
.mips16
2509 /* Itbl support may require additional care here. */
2510 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2511 && ! cop_interlocks
)
2512 || ((prev_prev_insn
.insn_mo
->pinfo
2513 & INSN_LOAD_MEMORY_DELAY
)
2514 && ! gpr_interlocks
))
2515 && insn_uses_reg (ip
,
2516 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2519 /* If one instruction sets a condition code and the
2520 other one uses a condition code, we can not swap. */
2521 || ((pinfo
& INSN_READ_COND_CODE
)
2522 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2523 || ((pinfo
& INSN_WRITE_COND_CODE
)
2524 && (prev_pinfo
& INSN_READ_COND_CODE
))
2525 /* If the previous instruction uses the PC, we can not
2527 || (mips_opts
.mips16
2528 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2529 /* If the previous instruction was extended, we can not
2531 || (mips_opts
.mips16
&& prev_insn_extended
)
2532 /* If the previous instruction had a fixup in mips16
2533 mode, we can not swap. This normally means that the
2534 previous instruction was a 4 byte branch anyhow. */
2535 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2536 /* If the previous instruction is a sync, sync.l, or
2537 sync.p, we can not swap. */
2538 || (prev_pinfo
& INSN_SYNC
))
2540 /* We could do even better for unconditional branches to
2541 portions of this object file; we could pick up the
2542 instruction at the destination, put it in the delay
2543 slot, and bump the destination address. */
2545 /* Update the previous insn information. */
2546 prev_prev_insn
= *ip
;
2547 prev_insn
.insn_mo
= &dummy_opcode
;
2551 /* It looks like we can actually do the swap. */
2552 if (! mips_opts
.mips16
)
2557 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2558 if (!relaxed_branch
)
2560 /* If this is not a relaxed branch, then just
2561 swap the instructions. */
2562 memcpy (temp
, prev_f
, 4);
2563 memcpy (prev_f
, f
, 4);
2564 memcpy (f
, temp
, 4);
2568 /* If this is a relaxed branch, then we move the
2569 instruction to be placed in the delay slot to
2570 the current frag, shrinking the fixed part of
2571 the originating frag. If the branch occupies
2572 the tail of the latter, we move it backwards,
2573 into the space freed by the moved instruction. */
2575 memcpy (f
, prev_f
, 4);
2576 prev_insn_frag
->fr_fix
-= 4;
2577 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2578 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2581 if (prev_insn_fixp
[0])
2583 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2584 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2586 if (prev_insn_fixp
[1])
2588 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2589 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2591 if (prev_insn_fixp
[2])
2593 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2594 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2596 if (prev_insn_fixp
[0] && HAVE_NEWABI
2597 && prev_insn_frag
!= frag_now
2598 && (prev_insn_fixp
[0]->fx_r_type
2599 == BFD_RELOC_MIPS_GOT_DISP
2600 || (prev_insn_fixp
[0]->fx_r_type
2601 == BFD_RELOC_MIPS_CALL16
)))
2603 /* To avoid confusion in tc_gen_reloc, we must
2604 ensure that this does not become a variant
2606 force_new_frag
= TRUE
;
2609 if (!relaxed_branch
)
2613 fixp
[0]->fx_frag
= prev_insn_frag
;
2614 fixp
[0]->fx_where
= prev_insn_where
;
2618 fixp
[1]->fx_frag
= prev_insn_frag
;
2619 fixp
[1]->fx_where
= prev_insn_where
;
2623 fixp
[2]->fx_frag
= prev_insn_frag
;
2624 fixp
[2]->fx_where
= prev_insn_where
;
2627 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2630 fixp
[0]->fx_where
-= 4;
2632 fixp
[1]->fx_where
-= 4;
2634 fixp
[2]->fx_where
-= 4;
2642 assert (prev_insn_fixp
[0] == NULL
);
2643 assert (prev_insn_fixp
[1] == NULL
);
2644 assert (prev_insn_fixp
[2] == NULL
);
2645 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2646 memcpy (temp
, prev_f
, 2);
2647 memcpy (prev_f
, f
, 2);
2648 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2650 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2651 memcpy (f
, temp
, 2);
2655 memcpy (f
, f
+ 2, 2);
2656 memcpy (f
+ 2, temp
, 2);
2660 fixp
[0]->fx_frag
= prev_insn_frag
;
2661 fixp
[0]->fx_where
= prev_insn_where
;
2665 fixp
[1]->fx_frag
= prev_insn_frag
;
2666 fixp
[1]->fx_where
= prev_insn_where
;
2670 fixp
[2]->fx_frag
= prev_insn_frag
;
2671 fixp
[2]->fx_where
= prev_insn_where
;
2675 /* Update the previous insn information; leave prev_insn
2677 prev_prev_insn
= *ip
;
2679 prev_insn_is_delay_slot
= 1;
2681 /* If that was an unconditional branch, forget the previous
2682 insn information. */
2683 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2685 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2686 prev_insn
.insn_mo
= &dummy_opcode
;
2689 prev_insn_fixp
[0] = NULL
;
2690 prev_insn_fixp
[1] = NULL
;
2691 prev_insn_fixp
[2] = NULL
;
2692 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2693 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2694 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2695 prev_insn_extended
= 0;
2697 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2699 /* We don't yet optimize a branch likely. What we should do
2700 is look at the target, copy the instruction found there
2701 into the delay slot, and increment the branch to jump to
2702 the next instruction. */
2704 /* Update the previous insn information. */
2705 prev_prev_insn
= *ip
;
2706 prev_insn
.insn_mo
= &dummy_opcode
;
2707 prev_insn_fixp
[0] = NULL
;
2708 prev_insn_fixp
[1] = NULL
;
2709 prev_insn_fixp
[2] = NULL
;
2710 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2711 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2712 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2713 prev_insn_extended
= 0;
2714 prev_insn_is_delay_slot
= 1;
2718 /* Update the previous insn information. */
2720 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2722 prev_prev_insn
= prev_insn
;
2725 /* Any time we see a branch, we always fill the delay slot
2726 immediately; since this insn is not a branch, we know it
2727 is not in a delay slot. */
2728 prev_insn_is_delay_slot
= 0;
2730 prev_insn_fixp
[0] = fixp
[0];
2731 prev_insn_fixp
[1] = fixp
[1];
2732 prev_insn_fixp
[2] = fixp
[2];
2733 prev_insn_reloc_type
[0] = reloc_type
[0];
2734 prev_insn_reloc_type
[1] = reloc_type
[1];
2735 prev_insn_reloc_type
[2] = reloc_type
[2];
2736 if (mips_opts
.mips16
)
2737 prev_insn_extended
= (ip
->use_extend
2738 || *reloc_type
> BFD_RELOC_UNUSED
);
2741 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2742 prev_insn_unreordered
= 0;
2743 prev_insn_frag
= frag_now
;
2744 prev_insn_where
= f
- frag_now
->fr_literal
;
2745 prev_insn_valid
= 1;
2747 else if (mips_relax
.sequence
!= 2)
2749 /* We need to record a bit of information even when we are not
2750 reordering, in order to determine the base address for mips16
2751 PC relative relocs. */
2752 prev_prev_insn
= prev_insn
;
2754 prev_insn_reloc_type
[0] = reloc_type
[0];
2755 prev_insn_reloc_type
[1] = reloc_type
[1];
2756 prev_insn_reloc_type
[2] = reloc_type
[2];
2757 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2758 prev_insn_unreordered
= 1;
2761 /* We just output an insn, so the next one doesn't have a label. */
2762 mips_clear_insn_labels ();
2765 /* This function forgets that there was any previous instruction or
2766 label. If PRESERVE is non-zero, it remembers enough information to
2767 know whether nops are needed before a noreorder section. */
2770 mips_no_prev_insn (int preserve
)
2774 prev_insn
.insn_mo
= &dummy_opcode
;
2775 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2776 prev_nop_frag
= NULL
;
2777 prev_nop_frag_holds
= 0;
2778 prev_nop_frag_required
= 0;
2779 prev_nop_frag_since
= 0;
2781 prev_insn_valid
= 0;
2782 prev_insn_is_delay_slot
= 0;
2783 prev_insn_unreordered
= 0;
2784 prev_insn_extended
= 0;
2785 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2786 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2787 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2788 prev_prev_insn_unreordered
= 0;
2789 mips_clear_insn_labels ();
2792 /* This function must be called whenever we turn on noreorder or emit
2793 something other than instructions. It inserts any NOPS which might
2794 be needed by the previous instruction, and clears the information
2795 kept for the previous instructions. The INSNS parameter is true if
2796 instructions are to follow. */
2799 mips_emit_delays (bfd_boolean insns
)
2801 if (! mips_opts
.noreorder
)
2806 if ((! mips_opts
.mips16
2807 && ((prev_insn
.insn_mo
->pinfo
2808 & (INSN_LOAD_COPROC_DELAY
2809 | INSN_COPROC_MOVE_DELAY
2810 | INSN_WRITE_COND_CODE
))
2811 && ! cop_interlocks
))
2812 || (! hilo_interlocks
2813 && (prev_insn
.insn_mo
->pinfo
2816 || (! mips_opts
.mips16
2817 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2818 && ! gpr_interlocks
)
2819 || (! mips_opts
.mips16
2820 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2821 && ! cop_mem_interlocks
))
2823 /* Itbl support may require additional care here. */
2825 if ((! mips_opts
.mips16
2826 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2827 && ! cop_interlocks
))
2828 || (! hilo_interlocks
2829 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2830 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2833 if (prev_insn_unreordered
)
2836 else if ((! mips_opts
.mips16
2837 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2838 && ! cop_interlocks
))
2839 || (! hilo_interlocks
2840 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2841 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2843 /* Itbl support may require additional care here. */
2844 if (! prev_prev_insn_unreordered
)
2848 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2851 const char *pn
= prev_insn
.insn_mo
->name
;
2852 if (strncmp (pn
, "macc", 4) == 0
2853 || strncmp (pn
, "dmacc", 5) == 0
2854 || strncmp (pn
, "dmult", 5) == 0
2855 || strstr (pn
, "div"))
2857 if (nops
< min_nops
)
2863 struct insn_label_list
*l
;
2867 /* Record the frag which holds the nop instructions, so
2868 that we can remove them if we don't need them. */
2869 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2870 prev_nop_frag
= frag_now
;
2871 prev_nop_frag_holds
= nops
;
2872 prev_nop_frag_required
= 0;
2873 prev_nop_frag_since
= 0;
2876 for (; nops
> 0; --nops
)
2881 /* Move on to a new frag, so that it is safe to simply
2882 decrease the size of prev_nop_frag. */
2883 frag_wane (frag_now
);
2887 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2891 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2892 symbol_set_frag (l
->label
, frag_now
);
2893 val
= (valueT
) frag_now_fix ();
2894 /* mips16 text labels are stored as odd. */
2895 if (mips_opts
.mips16
)
2897 S_SET_VALUE (l
->label
, val
);
2902 /* Mark instruction labels in mips16 mode. */
2904 mips16_mark_labels ();
2906 mips_no_prev_insn (insns
);
2909 /* Set up global variables for the start of a new macro. */
2914 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2915 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2916 && (prev_insn
.insn_mo
->pinfo
2917 & (INSN_UNCOND_BRANCH_DELAY
2918 | INSN_COND_BRANCH_DELAY
2919 | INSN_COND_BRANCH_LIKELY
)) != 0);
2922 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2923 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2924 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2927 macro_warning (relax_substateT subtype
)
2929 if (subtype
& RELAX_DELAY_SLOT
)
2930 return _("Macro instruction expanded into multiple instructions"
2931 " in a branch delay slot");
2932 else if (subtype
& RELAX_NOMACRO
)
2933 return _("Macro instruction expanded into multiple instructions");
2938 /* Finish up a macro. Emit warnings as appropriate. */
2943 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2945 relax_substateT subtype
;
2947 /* Set up the relaxation warning flags. */
2949 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2950 subtype
|= RELAX_SECOND_LONGER
;
2951 if (mips_opts
.warn_about_macros
)
2952 subtype
|= RELAX_NOMACRO
;
2953 if (mips_macro_warning
.delay_slot_p
)
2954 subtype
|= RELAX_DELAY_SLOT
;
2956 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2958 /* Either the macro has a single implementation or both
2959 implementations are longer than 4 bytes. Emit the
2961 const char *msg
= macro_warning (subtype
);
2967 /* One implementation might need a warning but the other
2968 definitely doesn't. */
2969 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2974 /* Read a macro's relocation codes from *ARGS and store them in *R.
2975 The first argument in *ARGS will be either the code for a single
2976 relocation or -1 followed by the three codes that make up a
2977 composite relocation. */
2980 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2984 next
= va_arg (*args
, int);
2986 r
[0] = (bfd_reloc_code_real_type
) next
;
2988 for (i
= 0; i
< 3; i
++)
2989 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2992 /* Build an instruction created by a macro expansion. This is passed
2993 a pointer to the count of instructions created so far, an
2994 expression, the name of the instruction to build, an operand format
2995 string, and corresponding arguments. */
2998 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3000 struct mips_cl_insn insn
;
3001 bfd_reloc_code_real_type r
[3];
3004 va_start (args
, fmt
);
3006 if (mips_opts
.mips16
)
3008 mips16_macro_build (ep
, name
, fmt
, args
);
3013 r
[0] = BFD_RELOC_UNUSED
;
3014 r
[1] = BFD_RELOC_UNUSED
;
3015 r
[2] = BFD_RELOC_UNUSED
;
3016 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3017 assert (insn
.insn_mo
);
3018 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3020 /* Search until we get a match for NAME. */
3023 /* It is assumed here that macros will never generate
3024 MDMX or MIPS-3D instructions. */
3025 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3026 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3027 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3029 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3031 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3035 assert (insn
.insn_mo
->name
);
3036 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3039 insn
.insn_opcode
= insn
.insn_mo
->match
;
3057 insn
.insn_opcode
|= (va_arg (args
, int)
3058 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3063 /* Note that in the macro case, these arguments are already
3064 in MSB form. (When handling the instruction in the
3065 non-macro case, these arguments are sizes from which
3066 MSB values must be calculated.) */
3067 insn
.insn_opcode
|= (va_arg (args
, int)
3068 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3074 /* Note that in the macro case, these arguments are already
3075 in MSBD form. (When handling the instruction in the
3076 non-macro case, these arguments are sizes from which
3077 MSBD values must be calculated.) */
3078 insn
.insn_opcode
|= (va_arg (args
, int)
3079 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3090 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3094 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3099 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3105 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3110 int tmp
= va_arg (args
, int);
3112 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3113 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3119 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3126 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3130 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3134 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3138 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3142 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3149 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3155 macro_read_relocs (&args
, r
);
3156 assert (*r
== BFD_RELOC_GPREL16
3157 || *r
== BFD_RELOC_MIPS_LITERAL
3158 || *r
== BFD_RELOC_MIPS_HIGHER
3159 || *r
== BFD_RELOC_HI16_S
3160 || *r
== BFD_RELOC_LO16
3161 || *r
== BFD_RELOC_MIPS_GOT16
3162 || *r
== BFD_RELOC_MIPS_CALL16
3163 || *r
== BFD_RELOC_MIPS_GOT_DISP
3164 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3165 || *r
== BFD_RELOC_MIPS_GOT_OFST
3166 || *r
== BFD_RELOC_MIPS_GOT_LO16
3167 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3171 macro_read_relocs (&args
, r
);
3173 && (ep
->X_op
== O_constant
3174 || (ep
->X_op
== O_symbol
3175 && (*r
== BFD_RELOC_MIPS_HIGHEST
3176 || *r
== BFD_RELOC_HI16_S
3177 || *r
== BFD_RELOC_HI16
3178 || *r
== BFD_RELOC_GPREL16
3179 || *r
== BFD_RELOC_MIPS_GOT_HI16
3180 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3184 assert (ep
!= NULL
);
3186 * This allows macro() to pass an immediate expression for
3187 * creating short branches without creating a symbol.
3188 * Note that the expression still might come from the assembly
3189 * input, in which case the value is not checked for range nor
3190 * is a relocation entry generated (yuck).
3192 if (ep
->X_op
== O_constant
)
3194 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3198 *r
= BFD_RELOC_16_PCREL_S2
;
3202 assert (ep
!= NULL
);
3203 *r
= BFD_RELOC_MIPS_JMP
;
3207 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3216 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3218 append_insn (&insn
, ep
, r
);
3222 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3225 struct mips_cl_insn insn
;
3226 bfd_reloc_code_real_type r
[3]
3227 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3229 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3230 assert (insn
.insn_mo
);
3231 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3233 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3234 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3237 assert (insn
.insn_mo
->name
);
3238 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3241 insn
.insn_opcode
= insn
.insn_mo
->match
;
3242 insn
.use_extend
= FALSE
;
3261 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3266 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3270 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3274 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3284 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3291 regno
= va_arg (args
, int);
3292 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3293 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3314 assert (ep
!= NULL
);
3316 if (ep
->X_op
!= O_constant
)
3317 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3320 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3321 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3324 *r
= BFD_RELOC_UNUSED
;
3330 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3337 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3339 append_insn (&insn
, ep
, r
);
3343 * Generate a "jalr" instruction with a relocation hint to the called
3344 * function. This occurs in NewABI PIC code.
3347 macro_build_jalr (expressionS
*ep
)
3356 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3358 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3359 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3363 * Generate a "lui" instruction.
3366 macro_build_lui (expressionS
*ep
, int regnum
)
3368 expressionS high_expr
;
3369 struct mips_cl_insn insn
;
3370 bfd_reloc_code_real_type r
[3]
3371 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3372 const char *name
= "lui";
3373 const char *fmt
= "t,u";
3375 assert (! mips_opts
.mips16
);
3379 if (high_expr
.X_op
== O_constant
)
3381 /* we can compute the instruction now without a relocation entry */
3382 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3384 *r
= BFD_RELOC_UNUSED
;
3388 assert (ep
->X_op
== O_symbol
);
3389 /* _gp_disp is a special case, used from s_cpload. */
3390 assert (mips_pic
== NO_PIC
3392 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3393 *r
= BFD_RELOC_HI16_S
;
3396 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3397 assert (insn
.insn_mo
);
3398 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3399 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3401 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3402 if (*r
== BFD_RELOC_UNUSED
)
3404 insn
.insn_opcode
|= high_expr
.X_add_number
;
3405 append_insn (&insn
, NULL
, r
);
3408 append_insn (&insn
, &high_expr
, r
);
3411 /* Generate a sequence of instructions to do a load or store from a constant
3412 offset off of a base register (breg) into/from a target register (treg),
3413 using AT if necessary. */
3415 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3416 int treg
, int breg
, int dbl
)
3418 assert (ep
->X_op
== O_constant
);
3420 /* Sign-extending 32-bit constants makes their handling easier. */
3421 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3422 == ~((bfd_vma
) 0x7fffffff)))
3424 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3425 as_bad (_("constant too large"));
3427 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3431 /* Right now, this routine can only handle signed 32-bit constants. */
3432 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3433 as_warn (_("operand overflow"));
3435 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3437 /* Signed 16-bit offset will fit in the op. Easy! */
3438 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3442 /* 32-bit offset, need multiple instructions and AT, like:
3443 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3444 addu $tempreg,$tempreg,$breg
3445 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3446 to handle the complete offset. */
3447 macro_build_lui (ep
, AT
);
3448 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3449 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3452 as_warn (_("Macro used $at after \".set noat\""));
3457 * Generates code to set the $at register to true (one)
3458 * if reg is less than the immediate expression.
3461 set_at (int reg
, int unsignedp
)
3463 if (imm_expr
.X_op
== O_constant
3464 && imm_expr
.X_add_number
>= -0x8000
3465 && imm_expr
.X_add_number
< 0x8000)
3466 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3467 AT
, reg
, BFD_RELOC_LO16
);
3470 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3471 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3476 normalize_constant_expr (expressionS
*ex
)
3478 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3479 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3483 /* Warn if an expression is not a constant. */
3486 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3488 if (ex
->X_op
== O_big
)
3489 as_bad (_("unsupported large constant"));
3490 else if (ex
->X_op
!= O_constant
)
3491 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3493 normalize_constant_expr (ex
);
3496 /* Count the leading zeroes by performing a binary chop. This is a
3497 bulky bit of source, but performance is a LOT better for the
3498 majority of values than a simple loop to count the bits:
3499 for (lcnt = 0; (lcnt < 32); lcnt++)
3500 if ((v) & (1 << (31 - lcnt)))
3502 However it is not code size friendly, and the gain will drop a bit
3503 on certain cached systems.
3505 #define COUNT_TOP_ZEROES(v) \
3506 (((v) & ~0xffff) == 0 \
3507 ? ((v) & ~0xff) == 0 \
3508 ? ((v) & ~0xf) == 0 \
3509 ? ((v) & ~0x3) == 0 \
3510 ? ((v) & ~0x1) == 0 \
3515 : ((v) & ~0x7) == 0 \
3518 : ((v) & ~0x3f) == 0 \
3519 ? ((v) & ~0x1f) == 0 \
3522 : ((v) & ~0x7f) == 0 \
3525 : ((v) & ~0xfff) == 0 \
3526 ? ((v) & ~0x3ff) == 0 \
3527 ? ((v) & ~0x1ff) == 0 \
3530 : ((v) & ~0x7ff) == 0 \
3533 : ((v) & ~0x3fff) == 0 \
3534 ? ((v) & ~0x1fff) == 0 \
3537 : ((v) & ~0x7fff) == 0 \
3540 : ((v) & ~0xffffff) == 0 \
3541 ? ((v) & ~0xfffff) == 0 \
3542 ? ((v) & ~0x3ffff) == 0 \
3543 ? ((v) & ~0x1ffff) == 0 \
3546 : ((v) & ~0x7ffff) == 0 \
3549 : ((v) & ~0x3fffff) == 0 \
3550 ? ((v) & ~0x1fffff) == 0 \
3553 : ((v) & ~0x7fffff) == 0 \
3556 : ((v) & ~0xfffffff) == 0 \
3557 ? ((v) & ~0x3ffffff) == 0 \
3558 ? ((v) & ~0x1ffffff) == 0 \
3561 : ((v) & ~0x7ffffff) == 0 \
3564 : ((v) & ~0x3fffffff) == 0 \
3565 ? ((v) & ~0x1fffffff) == 0 \
3568 : ((v) & ~0x7fffffff) == 0 \
3573 * This routine generates the least number of instructions necessary to load
3574 * an absolute expression value into a register.
3577 load_register (int reg
, expressionS
*ep
, int dbl
)
3580 expressionS hi32
, lo32
;
3582 if (ep
->X_op
!= O_big
)
3584 assert (ep
->X_op
== O_constant
);
3586 /* Sign-extending 32-bit constants makes their handling easier. */
3587 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3588 == ~((bfd_vma
) 0x7fffffff)))
3590 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3591 as_bad (_("constant too large"));
3593 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3597 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3599 /* We can handle 16 bit signed values with an addiu to
3600 $zero. No need to ever use daddiu here, since $zero and
3601 the result are always correct in 32 bit mode. */
3602 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3605 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3607 /* We can handle 16 bit unsigned values with an ori to
3609 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3612 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3614 /* 32 bit values require an lui. */
3615 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3616 if ((ep
->X_add_number
& 0xffff) != 0)
3617 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3622 /* The value is larger than 32 bits. */
3624 if (HAVE_32BIT_GPRS
)
3626 as_bad (_("Number (0x%lx) larger than 32 bits"),
3627 (unsigned long) ep
->X_add_number
);
3628 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3632 if (ep
->X_op
!= O_big
)
3635 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3636 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3637 hi32
.X_add_number
&= 0xffffffff;
3639 lo32
.X_add_number
&= 0xffffffff;
3643 assert (ep
->X_add_number
> 2);
3644 if (ep
->X_add_number
== 3)
3645 generic_bignum
[3] = 0;
3646 else if (ep
->X_add_number
> 4)
3647 as_bad (_("Number larger than 64 bits"));
3648 lo32
.X_op
= O_constant
;
3649 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3650 hi32
.X_op
= O_constant
;
3651 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3654 if (hi32
.X_add_number
== 0)
3659 unsigned long hi
, lo
;
3661 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3663 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3665 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3668 if (lo32
.X_add_number
& 0x80000000)
3670 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3671 if (lo32
.X_add_number
& 0xffff)
3672 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3677 /* Check for 16bit shifted constant. We know that hi32 is
3678 non-zero, so start the mask on the first bit of the hi32
3683 unsigned long himask
, lomask
;
3687 himask
= 0xffff >> (32 - shift
);
3688 lomask
= (0xffff << shift
) & 0xffffffff;
3692 himask
= 0xffff << (shift
- 32);
3695 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3696 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3700 tmp
.X_op
= O_constant
;
3702 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3703 | (lo32
.X_add_number
>> shift
));
3705 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3706 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3707 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3708 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3713 while (shift
<= (64 - 16));
3715 /* Find the bit number of the lowest one bit, and store the
3716 shifted value in hi/lo. */
3717 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3718 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3722 while ((lo
& 1) == 0)
3727 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3733 while ((hi
& 1) == 0)
3742 /* Optimize if the shifted value is a (power of 2) - 1. */
3743 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3744 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3746 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3751 /* This instruction will set the register to be all
3753 tmp
.X_op
= O_constant
;
3754 tmp
.X_add_number
= (offsetT
) -1;
3755 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3759 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3760 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3762 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3763 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3768 /* Sign extend hi32 before calling load_register, because we can
3769 generally get better code when we load a sign extended value. */
3770 if ((hi32
.X_add_number
& 0x80000000) != 0)
3771 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3772 load_register (reg
, &hi32
, 0);
3775 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3779 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3787 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3789 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3790 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3796 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3800 mid16
.X_add_number
>>= 16;
3801 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3802 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3805 if ((lo32
.X_add_number
& 0xffff) != 0)
3806 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3810 load_delay_nop (void)
3812 if (!gpr_interlocks
)
3813 macro_build (NULL
, "nop", "");
3816 /* Load an address into a register. */
3819 load_address (int reg
, expressionS
*ep
, int *used_at
)
3821 if (ep
->X_op
!= O_constant
3822 && ep
->X_op
!= O_symbol
)
3824 as_bad (_("expression too complex"));
3825 ep
->X_op
= O_constant
;
3828 if (ep
->X_op
== O_constant
)
3830 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3834 if (mips_pic
== NO_PIC
)
3836 /* If this is a reference to a GP relative symbol, we want
3837 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3839 lui $reg,<sym> (BFD_RELOC_HI16_S)
3840 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3841 If we have an addend, we always use the latter form.
3843 With 64bit address space and a usable $at we want
3844 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3845 lui $at,<sym> (BFD_RELOC_HI16_S)
3846 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3847 daddiu $at,<sym> (BFD_RELOC_LO16)
3851 If $at is already in use, we use a path which is suboptimal
3852 on superscalar processors.
3853 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3854 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3856 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3858 daddiu $reg,<sym> (BFD_RELOC_LO16)
3860 if (HAVE_64BIT_ADDRESSES
)
3862 /* ??? We don't provide a GP-relative alternative for these macros.
3863 It used not to be possible with the original relaxation code,
3864 but it could be done now. */
3866 if (*used_at
== 0 && ! mips_opts
.noat
)
3868 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3869 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3870 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3871 BFD_RELOC_MIPS_HIGHER
);
3872 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3873 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3874 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3879 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3880 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3881 BFD_RELOC_MIPS_HIGHER
);
3882 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3883 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3884 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3885 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3890 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3891 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3893 relax_start (ep
->X_add_symbol
);
3894 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3895 mips_gp_register
, BFD_RELOC_GPREL16
);
3898 macro_build_lui (ep
, reg
);
3899 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3900 reg
, reg
, BFD_RELOC_LO16
);
3901 if (mips_relax
.sequence
)
3905 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3909 /* If this is a reference to an external symbol, we want
3910 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3912 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3914 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3915 If there is a constant, it must be added in after.
3917 If we have NewABI, we want
3918 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3919 unless we're referencing a global symbol with a non-zero
3920 offset, in which case cst must be added separately. */
3923 if (ep
->X_add_number
)
3925 ex
.X_add_number
= ep
->X_add_number
;
3926 ep
->X_add_number
= 0;
3927 relax_start (ep
->X_add_symbol
);
3928 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3929 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3930 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3931 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3932 ex
.X_op
= O_constant
;
3933 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3934 reg
, reg
, BFD_RELOC_LO16
);
3935 ep
->X_add_number
= ex
.X_add_number
;
3938 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3939 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3940 if (mips_relax
.sequence
)
3945 ex
.X_add_number
= ep
->X_add_number
;
3946 ep
->X_add_number
= 0;
3947 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3948 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3950 relax_start (ep
->X_add_symbol
);
3952 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3956 if (ex
.X_add_number
!= 0)
3958 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3959 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3960 ex
.X_op
= O_constant
;
3961 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3962 reg
, reg
, BFD_RELOC_LO16
);
3966 else if (mips_pic
== SVR4_PIC
)
3970 /* This is the large GOT case. If this is a reference to an
3971 external symbol, we want
3972 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3974 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3976 Otherwise, for a reference to a local symbol in old ABI, we want
3977 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3979 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3980 If there is a constant, it must be added in after.
3982 In the NewABI, for local symbols, with or without offsets, we want:
3983 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3984 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3988 ex
.X_add_number
= ep
->X_add_number
;
3989 ep
->X_add_number
= 0;
3990 relax_start (ep
->X_add_symbol
);
3991 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3992 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3993 reg
, reg
, mips_gp_register
);
3994 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3995 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3996 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3997 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3998 else if (ex
.X_add_number
)
4000 ex
.X_op
= O_constant
;
4001 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4005 ep
->X_add_number
= ex
.X_add_number
;
4007 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4008 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4009 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4010 BFD_RELOC_MIPS_GOT_OFST
);
4015 ex
.X_add_number
= ep
->X_add_number
;
4016 ep
->X_add_number
= 0;
4017 relax_start (ep
->X_add_symbol
);
4018 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4019 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4020 reg
, reg
, mips_gp_register
);
4021 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4022 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4024 if (reg_needs_delay (mips_gp_register
))
4026 /* We need a nop before loading from $gp. This special
4027 check is required because the lui which starts the main
4028 instruction stream does not refer to $gp, and so will not
4029 insert the nop which may be required. */
4030 macro_build (NULL
, "nop", "");
4032 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4033 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4035 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4039 if (ex
.X_add_number
!= 0)
4041 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4042 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4043 ex
.X_op
= O_constant
;
4044 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4053 /* Move the contents of register SOURCE into register DEST. */
4056 move_register (int dest
, int source
)
4058 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4062 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4063 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4064 The two alternatives are:
4066 Global symbol Local sybmol
4067 ------------- ------------
4068 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4070 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4072 load_got_offset emits the first instruction and add_got_offset
4073 emits the second for a 16-bit offset or add_got_offset_hilo emits
4074 a sequence to add a 32-bit offset using a scratch register. */
4077 load_got_offset (int dest
, expressionS
*local
)
4082 global
.X_add_number
= 0;
4084 relax_start (local
->X_add_symbol
);
4085 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4086 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4088 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4089 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4094 add_got_offset (int dest
, expressionS
*local
)
4098 global
.X_op
= O_constant
;
4099 global
.X_op_symbol
= NULL
;
4100 global
.X_add_symbol
= NULL
;
4101 global
.X_add_number
= local
->X_add_number
;
4103 relax_start (local
->X_add_symbol
);
4104 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4105 dest
, dest
, BFD_RELOC_LO16
);
4107 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4112 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4115 int hold_mips_optimize
;
4117 global
.X_op
= O_constant
;
4118 global
.X_op_symbol
= NULL
;
4119 global
.X_add_symbol
= NULL
;
4120 global
.X_add_number
= local
->X_add_number
;
4122 relax_start (local
->X_add_symbol
);
4123 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4125 /* Set mips_optimize around the lui instruction to avoid
4126 inserting an unnecessary nop after the lw. */
4127 hold_mips_optimize
= mips_optimize
;
4129 macro_build_lui (&global
, tmp
);
4130 mips_optimize
= hold_mips_optimize
;
4131 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4134 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4139 * This routine implements the seemingly endless macro or synthesized
4140 * instructions and addressing modes in the mips assembly language. Many
4141 * of these macros are simple and are similar to each other. These could
4142 * probably be handled by some kind of table or grammar approach instead of
4143 * this verbose method. Others are not simple macros but are more like
4144 * optimizing code generation.
4145 * One interesting optimization is when several store macros appear
4146 * consecutively that would load AT with the upper half of the same address.
4147 * The ensuing load upper instructions are ommited. This implies some kind
4148 * of global optimization. We currently only optimize within a single macro.
4149 * For many of the load and store macros if the address is specified as a
4150 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4151 * first load register 'at' with zero and use it as the base register. The
4152 * mips assembler simply uses register $zero. Just one tiny optimization
4156 macro (struct mips_cl_insn
*ip
)
4158 register int treg
, sreg
, dreg
, breg
;
4174 bfd_reloc_code_real_type r
;
4175 int hold_mips_optimize
;
4177 assert (! mips_opts
.mips16
);
4179 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4180 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4181 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4182 mask
= ip
->insn_mo
->mask
;
4184 expr1
.X_op
= O_constant
;
4185 expr1
.X_op_symbol
= NULL
;
4186 expr1
.X_add_symbol
= NULL
;
4187 expr1
.X_add_number
= 1;
4199 mips_emit_delays (TRUE
);
4200 ++mips_opts
.noreorder
;
4201 mips_any_noreorder
= 1;
4203 expr1
.X_add_number
= 8;
4204 macro_build (&expr1
, "bgez", "s,p", sreg
);
4206 macro_build (NULL
, "nop", "", 0);
4208 move_register (dreg
, sreg
);
4209 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4211 --mips_opts
.noreorder
;
4232 if (imm_expr
.X_op
== O_constant
4233 && imm_expr
.X_add_number
>= -0x8000
4234 && imm_expr
.X_add_number
< 0x8000)
4236 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4239 load_register (AT
, &imm_expr
, dbl
);
4240 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4259 if (imm_expr
.X_op
== O_constant
4260 && imm_expr
.X_add_number
>= 0
4261 && imm_expr
.X_add_number
< 0x10000)
4263 if (mask
!= M_NOR_I
)
4264 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4267 macro_build (&imm_expr
, "ori", "t,r,i",
4268 treg
, sreg
, BFD_RELOC_LO16
);
4269 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4274 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4275 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4292 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4294 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4297 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4298 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4306 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4311 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4314 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4315 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4321 /* check for > max integer */
4322 maxnum
= 0x7fffffff;
4323 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4330 if (imm_expr
.X_op
== O_constant
4331 && imm_expr
.X_add_number
>= maxnum
4332 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4335 /* result is always false */
4337 macro_build (NULL
, "nop", "", 0);
4339 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4342 if (imm_expr
.X_op
!= O_constant
)
4343 as_bad (_("Unsupported large constant"));
4344 ++imm_expr
.X_add_number
;
4348 if (mask
== M_BGEL_I
)
4350 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4352 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4355 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4357 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4360 maxnum
= 0x7fffffff;
4361 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4368 maxnum
= - maxnum
- 1;
4369 if (imm_expr
.X_op
== O_constant
4370 && imm_expr
.X_add_number
<= maxnum
4371 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4374 /* result is always true */
4375 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4376 macro_build (&offset_expr
, "b", "p");
4380 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4390 macro_build (&offset_expr
, likely
? "beql" : "beq",
4394 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4395 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4403 && imm_expr
.X_op
== O_constant
4404 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4406 if (imm_expr
.X_op
!= O_constant
)
4407 as_bad (_("Unsupported large constant"));
4408 ++imm_expr
.X_add_number
;
4412 if (mask
== M_BGEUL_I
)
4414 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4416 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4418 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4423 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4431 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4436 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4439 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4440 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4448 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4454 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4455 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4463 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4468 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4471 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4472 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4478 maxnum
= 0x7fffffff;
4479 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4486 if (imm_expr
.X_op
== O_constant
4487 && imm_expr
.X_add_number
>= maxnum
4488 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4490 if (imm_expr
.X_op
!= O_constant
)
4491 as_bad (_("Unsupported large constant"));
4492 ++imm_expr
.X_add_number
;
4496 if (mask
== M_BLTL_I
)
4498 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4500 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4503 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4505 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4509 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4517 macro_build (&offset_expr
, likely
? "beql" : "beq",
4523 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4524 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4532 && imm_expr
.X_op
== O_constant
4533 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4535 if (imm_expr
.X_op
!= O_constant
)
4536 as_bad (_("Unsupported large constant"));
4537 ++imm_expr
.X_add_number
;
4541 if (mask
== M_BLTUL_I
)
4543 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4545 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4547 macro_build (&offset_expr
, likely
? "beql" : "beq",
4552 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4560 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4565 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4568 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4569 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4579 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4583 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4584 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4592 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4594 as_bad (_("Unsupported large constant"));
4599 pos
= (unsigned long) imm_expr
.X_add_number
;
4600 size
= (unsigned long) imm2_expr
.X_add_number
;
4605 as_bad (_("Improper position (%lu)"), pos
);
4608 if (size
== 0 || size
> 64
4609 || (pos
+ size
- 1) > 63)
4611 as_bad (_("Improper extract size (%lu, position %lu)"),
4616 if (size
<= 32 && pos
< 32)
4621 else if (size
<= 32)
4631 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4640 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4642 as_bad (_("Unsupported large constant"));
4647 pos
= (unsigned long) imm_expr
.X_add_number
;
4648 size
= (unsigned long) imm2_expr
.X_add_number
;
4653 as_bad (_("Improper position (%lu)"), pos
);
4656 if (size
== 0 || size
> 64
4657 || (pos
+ size
- 1) > 63)
4659 as_bad (_("Improper insert size (%lu, position %lu)"),
4664 if (pos
< 32 && (pos
+ size
- 1) < 32)
4679 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4696 as_warn (_("Divide by zero."));
4698 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4700 macro_build (NULL
, "break", "c", 7);
4704 mips_emit_delays (TRUE
);
4705 ++mips_opts
.noreorder
;
4706 mips_any_noreorder
= 1;
4709 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4710 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4714 expr1
.X_add_number
= 8;
4715 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4716 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4717 macro_build (NULL
, "break", "c", 7);
4719 expr1
.X_add_number
= -1;
4720 load_register (AT
, &expr1
, dbl
);
4721 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4722 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4725 expr1
.X_add_number
= 1;
4726 load_register (AT
, &expr1
, dbl
);
4727 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4731 expr1
.X_add_number
= 0x80000000;
4732 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4736 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4737 /* We want to close the noreorder block as soon as possible, so
4738 that later insns are available for delay slot filling. */
4739 --mips_opts
.noreorder
;
4743 expr1
.X_add_number
= 8;
4744 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4745 macro_build (NULL
, "nop", "", 0);
4747 /* We want to close the noreorder block as soon as possible, so
4748 that later insns are available for delay slot filling. */
4749 --mips_opts
.noreorder
;
4751 macro_build (NULL
, "break", "c", 6);
4753 macro_build (NULL
, s
, "d", dreg
);
4792 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4794 as_warn (_("Divide by zero."));
4796 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4798 macro_build (NULL
, "break", "c", 7);
4801 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4803 if (strcmp (s2
, "mflo") == 0)
4804 move_register (dreg
, sreg
);
4806 move_register (dreg
, 0);
4809 if (imm_expr
.X_op
== O_constant
4810 && imm_expr
.X_add_number
== -1
4811 && s
[strlen (s
) - 1] != 'u')
4813 if (strcmp (s2
, "mflo") == 0)
4815 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4818 move_register (dreg
, 0);
4822 load_register (AT
, &imm_expr
, dbl
);
4823 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4824 macro_build (NULL
, s2
, "d", dreg
);
4843 mips_emit_delays (TRUE
);
4844 ++mips_opts
.noreorder
;
4845 mips_any_noreorder
= 1;
4848 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4849 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4850 /* We want to close the noreorder block as soon as possible, so
4851 that later insns are available for delay slot filling. */
4852 --mips_opts
.noreorder
;
4856 expr1
.X_add_number
= 8;
4857 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4858 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4860 /* We want to close the noreorder block as soon as possible, so
4861 that later insns are available for delay slot filling. */
4862 --mips_opts
.noreorder
;
4863 macro_build (NULL
, "break", "c", 7);
4865 macro_build (NULL
, s2
, "d", dreg
);
4877 /* Load the address of a symbol into a register. If breg is not
4878 zero, we then add a base register to it. */
4880 if (dbl
&& HAVE_32BIT_GPRS
)
4881 as_warn (_("dla used to load 32-bit register"));
4883 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4884 as_warn (_("la used to load 64-bit address"));
4886 if (offset_expr
.X_op
== O_constant
4887 && offset_expr
.X_add_number
>= -0x8000
4888 && offset_expr
.X_add_number
< 0x8000)
4890 macro_build (&offset_expr
,
4891 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4892 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4907 if (offset_expr
.X_op
!= O_symbol
4908 && offset_expr
.X_op
!= O_constant
)
4910 as_bad (_("expression too complex"));
4911 offset_expr
.X_op
= O_constant
;
4914 if (offset_expr
.X_op
== O_constant
)
4915 load_register (tempreg
, &offset_expr
,
4917 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4918 : HAVE_64BIT_ADDRESSES
));
4919 else if (mips_pic
== NO_PIC
)
4921 /* If this is a reference to a GP relative symbol, we want
4922 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4924 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4925 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4926 If we have a constant, we need two instructions anyhow,
4927 so we may as well always use the latter form.
4929 With 64bit address space and a usable $at we want
4930 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4931 lui $at,<sym> (BFD_RELOC_HI16_S)
4932 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4933 daddiu $at,<sym> (BFD_RELOC_LO16)
4935 daddu $tempreg,$tempreg,$at
4937 If $at is already in use, we use a path which is suboptimal
4938 on superscalar processors.
4939 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4940 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4942 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4944 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4946 if (HAVE_64BIT_ADDRESSES
)
4948 /* ??? We don't provide a GP-relative alternative for
4949 these macros. It used not to be possible with the
4950 original relaxation code, but it could be done now. */
4952 if (used_at
== 0 && ! mips_opts
.noat
)
4954 macro_build (&offset_expr
, "lui", "t,u",
4955 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4956 macro_build (&offset_expr
, "lui", "t,u",
4957 AT
, BFD_RELOC_HI16_S
);
4958 macro_build (&offset_expr
, "daddiu", "t,r,j",
4959 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4960 macro_build (&offset_expr
, "daddiu", "t,r,j",
4961 AT
, AT
, BFD_RELOC_LO16
);
4962 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4963 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4968 macro_build (&offset_expr
, "lui", "t,u",
4969 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4970 macro_build (&offset_expr
, "daddiu", "t,r,j",
4971 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4972 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4973 macro_build (&offset_expr
, "daddiu", "t,r,j",
4974 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4975 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4976 macro_build (&offset_expr
, "daddiu", "t,r,j",
4977 tempreg
, tempreg
, BFD_RELOC_LO16
);
4982 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4983 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4985 relax_start (offset_expr
.X_add_symbol
);
4986 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4987 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4990 macro_build_lui (&offset_expr
, tempreg
);
4991 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4992 tempreg
, tempreg
, BFD_RELOC_LO16
);
4993 if (mips_relax
.sequence
)
4997 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4999 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5001 /* If this is a reference to an external symbol, and there
5002 is no constant, we want
5003 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5004 or for lca or if tempreg is PIC_CALL_REG
5005 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5006 For a local symbol, we want
5007 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5009 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5011 If we have a small constant, and this is a reference to
5012 an external symbol, we want
5013 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5015 addiu $tempreg,$tempreg,<constant>
5016 For a local symbol, we want the same instruction
5017 sequence, but we output a BFD_RELOC_LO16 reloc on the
5020 If we have a large constant, and this is a reference to
5021 an external symbol, we want
5022 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5023 lui $at,<hiconstant>
5024 addiu $at,$at,<loconstant>
5025 addu $tempreg,$tempreg,$at
5026 For a local symbol, we want the same instruction
5027 sequence, but we output a BFD_RELOC_LO16 reloc on the
5031 if (offset_expr
.X_add_number
== 0)
5033 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5034 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5036 relax_start (offset_expr
.X_add_symbol
);
5037 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5038 lw_reloc_type
, mips_gp_register
);
5041 /* We're going to put in an addu instruction using
5042 tempreg, so we may as well insert the nop right
5047 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5048 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5050 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5051 tempreg
, tempreg
, BFD_RELOC_LO16
);
5053 /* FIXME: If breg == 0, and the next instruction uses
5054 $tempreg, then if this variant case is used an extra
5055 nop will be generated. */
5057 else if (offset_expr
.X_add_number
>= -0x8000
5058 && offset_expr
.X_add_number
< 0x8000)
5060 load_got_offset (tempreg
, &offset_expr
);
5062 add_got_offset (tempreg
, &offset_expr
);
5066 expr1
.X_add_number
= offset_expr
.X_add_number
;
5067 offset_expr
.X_add_number
=
5068 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5069 load_got_offset (tempreg
, &offset_expr
);
5070 offset_expr
.X_add_number
= expr1
.X_add_number
;
5071 /* If we are going to add in a base register, and the
5072 target register and the base register are the same,
5073 then we are using AT as a temporary register. Since
5074 we want to load the constant into AT, we add our
5075 current AT (from the global offset table) and the
5076 register into the register now, and pretend we were
5077 not using a base register. */
5081 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5086 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5090 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5092 int add_breg_early
= 0;
5094 /* If this is a reference to an external, and there is no
5095 constant, or local symbol (*), with or without a
5097 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5098 or for lca or if tempreg is PIC_CALL_REG
5099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5101 If we have a small constant, and this is a reference to
5102 an external symbol, we want
5103 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5104 addiu $tempreg,$tempreg,<constant>
5106 If we have a large constant, and this is a reference to
5107 an external symbol, we want
5108 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5109 lui $at,<hiconstant>
5110 addiu $at,$at,<loconstant>
5111 addu $tempreg,$tempreg,$at
5113 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5114 local symbols, even though it introduces an additional
5117 if (offset_expr
.X_add_number
)
5119 expr1
.X_add_number
= offset_expr
.X_add_number
;
5120 offset_expr
.X_add_number
= 0;
5122 relax_start (offset_expr
.X_add_symbol
);
5123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5124 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5126 if (expr1
.X_add_number
>= -0x8000
5127 && expr1
.X_add_number
< 0x8000)
5129 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5130 tempreg
, tempreg
, BFD_RELOC_LO16
);
5132 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5136 /* If we are going to add in a base register, and the
5137 target register and the base register are the same,
5138 then we are using AT as a temporary register. Since
5139 we want to load the constant into AT, we add our
5140 current AT (from the global offset table) and the
5141 register into the register now, and pretend we were
5142 not using a base register. */
5147 assert (tempreg
== AT
);
5148 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5154 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5155 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5161 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5164 offset_expr
.X_add_number
= expr1
.X_add_number
;
5166 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5167 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5170 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5171 treg
, tempreg
, breg
);
5177 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5179 relax_start (offset_expr
.X_add_symbol
);
5180 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5181 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5183 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5184 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5189 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5190 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5193 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5196 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5197 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5198 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5200 /* This is the large GOT case. If this is a reference to an
5201 external symbol, and there is no constant, we want
5202 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5203 addu $tempreg,$tempreg,$gp
5204 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5205 or for lca or if tempreg is PIC_CALL_REG
5206 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5207 addu $tempreg,$tempreg,$gp
5208 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5209 For a local symbol, we want
5210 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5212 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5214 If we have a small constant, and this is a reference to
5215 an external symbol, we want
5216 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5217 addu $tempreg,$tempreg,$gp
5218 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5220 addiu $tempreg,$tempreg,<constant>
5221 For a local symbol, we want
5222 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5224 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5226 If we have a large constant, and this is a reference to
5227 an external symbol, we want
5228 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5229 addu $tempreg,$tempreg,$gp
5230 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5231 lui $at,<hiconstant>
5232 addiu $at,$at,<loconstant>
5233 addu $tempreg,$tempreg,$at
5234 For a local symbol, we want
5235 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5236 lui $at,<hiconstant>
5237 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5238 addu $tempreg,$tempreg,$at
5241 expr1
.X_add_number
= offset_expr
.X_add_number
;
5242 offset_expr
.X_add_number
= 0;
5243 relax_start (offset_expr
.X_add_symbol
);
5244 gpdelay
= reg_needs_delay (mips_gp_register
);
5245 if (expr1
.X_add_number
== 0 && breg
== 0
5246 && (call
|| tempreg
== PIC_CALL_REG
))
5248 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5249 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5251 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5252 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5253 tempreg
, tempreg
, mips_gp_register
);
5254 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5255 tempreg
, lw_reloc_type
, tempreg
);
5256 if (expr1
.X_add_number
== 0)
5260 /* We're going to put in an addu instruction using
5261 tempreg, so we may as well insert the nop right
5266 else if (expr1
.X_add_number
>= -0x8000
5267 && expr1
.X_add_number
< 0x8000)
5270 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5271 tempreg
, tempreg
, BFD_RELOC_LO16
);
5277 /* If we are going to add in a base register, and the
5278 target register and the base register are the same,
5279 then we are using AT as a temporary register. Since
5280 we want to load the constant into AT, we add our
5281 current AT (from the global offset table) and the
5282 register into the register now, and pretend we were
5283 not using a base register. */
5288 assert (tempreg
== AT
);
5290 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5295 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5296 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5300 offset_expr
.X_add_number
=
5301 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5306 /* This is needed because this instruction uses $gp, but
5307 the first instruction on the main stream does not. */
5308 macro_build (NULL
, "nop", "");
5311 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5312 local_reloc_type
, mips_gp_register
);
5313 if (expr1
.X_add_number
>= -0x8000
5314 && expr1
.X_add_number
< 0x8000)
5317 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5318 tempreg
, tempreg
, BFD_RELOC_LO16
);
5319 /* FIXME: If add_number is 0, and there was no base
5320 register, the external symbol case ended with a load,
5321 so if the symbol turns out to not be external, and
5322 the next instruction uses tempreg, an unnecessary nop
5323 will be inserted. */
5329 /* We must add in the base register now, as in the
5330 external symbol case. */
5331 assert (tempreg
== AT
);
5333 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5336 /* We set breg to 0 because we have arranged to add
5337 it in in both cases. */
5341 macro_build_lui (&expr1
, AT
);
5342 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5343 AT
, AT
, BFD_RELOC_LO16
);
5344 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5345 tempreg
, tempreg
, AT
);
5349 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5351 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5352 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5353 int add_breg_early
= 0;
5355 /* This is the large GOT case. If this is a reference to an
5356 external symbol, and there is no constant, we want
5357 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5358 add $tempreg,$tempreg,$gp
5359 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5360 or for lca or if tempreg is PIC_CALL_REG
5361 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5362 add $tempreg,$tempreg,$gp
5363 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5365 If we have a small constant, and this is a reference to
5366 an external symbol, we want
5367 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5368 add $tempreg,$tempreg,$gp
5369 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5370 addi $tempreg,$tempreg,<constant>
5372 If we have a large constant, and this is a reference to
5373 an external symbol, we want
5374 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5375 addu $tempreg,$tempreg,$gp
5376 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5377 lui $at,<hiconstant>
5378 addi $at,$at,<loconstant>
5379 add $tempreg,$tempreg,$at
5381 If we have NewABI, and we know it's a local symbol, we want
5382 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5383 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5384 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5386 relax_start (offset_expr
.X_add_symbol
);
5388 expr1
.X_add_number
= offset_expr
.X_add_number
;
5389 offset_expr
.X_add_number
= 0;
5391 if (expr1
.X_add_number
== 0 && breg
== 0
5392 && (call
|| tempreg
== PIC_CALL_REG
))
5394 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5395 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5397 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5398 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5399 tempreg
, tempreg
, mips_gp_register
);
5400 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5401 tempreg
, lw_reloc_type
, tempreg
);
5403 if (expr1
.X_add_number
== 0)
5405 else if (expr1
.X_add_number
>= -0x8000
5406 && expr1
.X_add_number
< 0x8000)
5408 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5409 tempreg
, tempreg
, BFD_RELOC_LO16
);
5411 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5415 /* If we are going to add in a base register, and the
5416 target register and the base register are the same,
5417 then we are using AT as a temporary register. Since
5418 we want to load the constant into AT, we add our
5419 current AT (from the global offset table) and the
5420 register into the register now, and pretend we were
5421 not using a base register. */
5426 assert (tempreg
== AT
);
5427 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5433 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5439 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5442 offset_expr
.X_add_number
= expr1
.X_add_number
;
5443 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5444 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5445 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5446 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5449 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5450 treg
, tempreg
, breg
);
5463 if (mips_pic
== NO_PIC
)
5464 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5466 s
= ADDRESS_ADD_INSN
;
5468 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5477 /* The j instruction may not be used in PIC code, since it
5478 requires an absolute address. We convert it to a b
5480 if (mips_pic
== NO_PIC
)
5481 macro_build (&offset_expr
, "j", "a");
5483 macro_build (&offset_expr
, "b", "p");
5486 /* The jal instructions must be handled as macros because when
5487 generating PIC code they expand to multi-instruction
5488 sequences. Normally they are simple instructions. */
5493 if (mips_pic
== NO_PIC
)
5494 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5495 else if (mips_pic
== SVR4_PIC
)
5497 if (sreg
!= PIC_CALL_REG
)
5498 as_warn (_("MIPS PIC call to register other than $25"));
5500 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5503 if (mips_cprestore_offset
< 0)
5504 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5507 if (! mips_frame_reg_valid
)
5509 as_warn (_("No .frame pseudo-op used in PIC code"));
5510 /* Quiet this warning. */
5511 mips_frame_reg_valid
= 1;
5513 if (! mips_cprestore_valid
)
5515 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5516 /* Quiet this warning. */
5517 mips_cprestore_valid
= 1;
5519 expr1
.X_add_number
= mips_cprestore_offset
;
5520 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5523 HAVE_64BIT_ADDRESSES
);
5533 if (mips_pic
== NO_PIC
)
5534 macro_build (&offset_expr
, "jal", "a");
5535 else if (mips_pic
== SVR4_PIC
)
5537 /* If this is a reference to an external symbol, and we are
5538 using a small GOT, we want
5539 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5543 lw $gp,cprestore($sp)
5544 The cprestore value is set using the .cprestore
5545 pseudo-op. If we are using a big GOT, we want
5546 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5548 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5552 lw $gp,cprestore($sp)
5553 If the symbol is not external, we want
5554 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5556 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5559 lw $gp,cprestore($sp)
5561 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5562 sequences above, minus nops, unless the symbol is local,
5563 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5569 relax_start (offset_expr
.X_add_symbol
);
5570 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5571 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5574 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5575 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5581 relax_start (offset_expr
.X_add_symbol
);
5582 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5583 BFD_RELOC_MIPS_CALL_HI16
);
5584 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5585 PIC_CALL_REG
, mips_gp_register
);
5586 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5587 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5590 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5591 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5593 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5594 PIC_CALL_REG
, PIC_CALL_REG
,
5595 BFD_RELOC_MIPS_GOT_OFST
);
5599 macro_build_jalr (&offset_expr
);
5603 relax_start (offset_expr
.X_add_symbol
);
5606 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5607 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5616 gpdelay
= reg_needs_delay (mips_gp_register
);
5617 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5618 BFD_RELOC_MIPS_CALL_HI16
);
5619 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5620 PIC_CALL_REG
, mips_gp_register
);
5621 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5622 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5627 macro_build (NULL
, "nop", "");
5629 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5630 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5633 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5634 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5636 macro_build_jalr (&offset_expr
);
5638 if (mips_cprestore_offset
< 0)
5639 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5642 if (! mips_frame_reg_valid
)
5644 as_warn (_("No .frame pseudo-op used in PIC code"));
5645 /* Quiet this warning. */
5646 mips_frame_reg_valid
= 1;
5648 if (! mips_cprestore_valid
)
5650 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5651 /* Quiet this warning. */
5652 mips_cprestore_valid
= 1;
5654 if (mips_opts
.noreorder
)
5655 macro_build (NULL
, "nop", "");
5656 expr1
.X_add_number
= mips_cprestore_offset
;
5657 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5660 HAVE_64BIT_ADDRESSES
);
5686 /* Itbl support may require additional care here. */
5691 /* Itbl support may require additional care here. */
5696 /* Itbl support may require additional care here. */
5701 /* Itbl support may require additional care here. */
5713 if (mips_opts
.arch
== CPU_R4650
)
5715 as_bad (_("opcode not supported on this processor"));
5719 /* Itbl support may require additional care here. */
5724 /* Itbl support may require additional care here. */
5729 /* Itbl support may require additional care here. */
5749 if (breg
== treg
|| coproc
|| lr
)
5771 /* Itbl support may require additional care here. */
5776 /* Itbl support may require additional care here. */
5781 /* Itbl support may require additional care here. */
5786 /* Itbl support may require additional care here. */
5802 if (mips_opts
.arch
== CPU_R4650
)
5804 as_bad (_("opcode not supported on this processor"));
5809 /* Itbl support may require additional care here. */
5813 /* Itbl support may require additional care here. */
5818 /* Itbl support may require additional care here. */
5830 /* Itbl support may require additional care here. */
5831 if (mask
== M_LWC1_AB
5832 || mask
== M_SWC1_AB
5833 || mask
== M_LDC1_AB
5834 || mask
== M_SDC1_AB
5843 /* Sign-extending 32-bit constants makes their handling easier.
5844 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5846 if ((! HAVE_64BIT_ADDRESSES
5847 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5848 && (offset_expr
.X_op
== O_constant
)
5849 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5850 == ~((bfd_vma
) 0x7fffffff)))
5852 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5853 as_bad (_("constant too large"));
5855 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5856 ^ 0x80000000) - 0x80000000);
5859 if (offset_expr
.X_op
!= O_constant
5860 && offset_expr
.X_op
!= O_symbol
)
5862 as_bad (_("expression too complex"));
5863 offset_expr
.X_op
= O_constant
;
5866 /* A constant expression in PIC code can be handled just as it
5867 is in non PIC code. */
5868 if (mips_pic
== NO_PIC
5869 || offset_expr
.X_op
== O_constant
)
5871 /* If this is a reference to a GP relative symbol, and there
5872 is no base register, we want
5873 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5874 Otherwise, if there is no base register, we want
5875 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5876 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5877 If we have a constant, we need two instructions anyhow,
5878 so we always use the latter form.
5880 If we have a base register, and this is a reference to a
5881 GP relative symbol, we want
5882 addu $tempreg,$breg,$gp
5883 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5885 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5886 addu $tempreg,$tempreg,$breg
5887 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5888 With a constant we always use the latter case.
5890 With 64bit address space and no base register and $at usable,
5892 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5893 lui $at,<sym> (BFD_RELOC_HI16_S)
5894 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5897 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5898 If we have a base register, we want
5899 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5900 lui $at,<sym> (BFD_RELOC_HI16_S)
5901 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5905 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5907 Without $at we can't generate the optimal path for superscalar
5908 processors here since this would require two temporary registers.
5909 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5910 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5912 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5914 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5915 If we have a base register, we want
5916 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5917 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5919 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5921 daddu $tempreg,$tempreg,$breg
5922 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5924 If we have 64-bit addresses, as an optimization, for
5925 addresses which are 32-bit constants (e.g. kseg0/kseg1
5926 addresses) we fall back to the 32-bit address generation
5927 mechanism since it is more efficient. Note that due to
5928 the signed offset used by memory operations, the 32-bit
5929 range is shifted down by 32768 here. This code should
5930 probably attempt to generate 64-bit constants more
5931 efficiently in general.
5933 As an extension for architectures with 64-bit registers,
5934 we don't truncate 64-bit addresses given as literal
5935 constants down to 32 bits, to support existing practice
5936 in the mips64 Linux (the kernel), that compiles source
5937 files with -mabi=64, assembling them as o32 or n32 (with
5938 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5939 the whole kernel is loaded into a memory region that is
5940 addressable with sign-extended 32-bit addresses, it is
5941 wasteful to compute the upper 32 bits of every
5942 non-literal address, that takes more space and time.
5943 Some day this should probably be implemented as an
5944 assembler option, such that the kernel doesn't have to
5945 use such ugly hacks, even though it will still have to
5946 end up converting the binary to ELF32 for a number of
5947 platforms whose boot loaders don't support ELF64
5949 if ((HAVE_64BIT_ADDRESSES
5950 && ! (offset_expr
.X_op
== O_constant
5951 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5953 && offset_expr
.X_op
== O_constant
5954 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5956 /* ??? We don't provide a GP-relative alternative for
5957 these macros. It used not to be possible with the
5958 original relaxation code, but it could be done now. */
5960 if (used_at
== 0 && ! mips_opts
.noat
)
5962 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5963 BFD_RELOC_MIPS_HIGHEST
);
5964 macro_build (&offset_expr
, "lui", "t,u", AT
,
5966 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5967 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5969 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5970 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5971 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5972 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5978 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5979 BFD_RELOC_MIPS_HIGHEST
);
5980 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5981 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5982 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5983 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5984 tempreg
, BFD_RELOC_HI16_S
);
5985 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5987 macro_build (NULL
, "daddu", "d,v,t",
5988 tempreg
, tempreg
, breg
);
5989 macro_build (&offset_expr
, s
, fmt
, treg
,
5990 BFD_RELOC_LO16
, tempreg
);
5996 if (offset_expr
.X_op
== O_constant
5997 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
5998 as_bad (_("load/store address overflow (max 32 bits)"));
6002 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6003 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6005 relax_start (offset_expr
.X_add_symbol
);
6006 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6011 macro_build_lui (&offset_expr
, tempreg
);
6012 macro_build (&offset_expr
, s
, fmt
, treg
,
6013 BFD_RELOC_LO16
, tempreg
);
6014 if (mips_relax
.sequence
)
6019 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6020 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6022 relax_start (offset_expr
.X_add_symbol
);
6023 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6024 tempreg
, breg
, mips_gp_register
);
6025 macro_build (&offset_expr
, s
, fmt
, treg
,
6026 BFD_RELOC_GPREL16
, tempreg
);
6029 macro_build_lui (&offset_expr
, tempreg
);
6030 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6031 tempreg
, tempreg
, breg
);
6032 macro_build (&offset_expr
, s
, fmt
, treg
,
6033 BFD_RELOC_LO16
, tempreg
);
6034 if (mips_relax
.sequence
)
6038 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6040 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6042 /* If this is a reference to an external symbol, we want
6043 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6045 <op> $treg,0($tempreg)
6047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6049 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6050 <op> $treg,0($tempreg)
6053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6054 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6056 If there is a base register, we add it to $tempreg before
6057 the <op>. If there is a constant, we stick it in the
6058 <op> instruction. We don't handle constants larger than
6059 16 bits, because we have no way to load the upper 16 bits
6060 (actually, we could handle them for the subset of cases
6061 in which we are not using $at). */
6062 assert (offset_expr
.X_op
== O_symbol
);
6065 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6066 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6068 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6069 tempreg
, tempreg
, breg
);
6070 macro_build (&offset_expr
, s
, fmt
, treg
,
6071 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6078 expr1
.X_add_number
= offset_expr
.X_add_number
;
6079 offset_expr
.X_add_number
= 0;
6080 if (expr1
.X_add_number
< -0x8000
6081 || expr1
.X_add_number
>= 0x8000)
6082 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6083 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6084 lw_reloc_type
, mips_gp_register
);
6086 relax_start (offset_expr
.X_add_symbol
);
6088 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6089 tempreg
, BFD_RELOC_LO16
);
6092 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6093 tempreg
, tempreg
, breg
);
6094 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6096 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6100 /* If this is a reference to an external symbol, we want
6101 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6102 addu $tempreg,$tempreg,$gp
6103 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6104 <op> $treg,0($tempreg)
6106 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6108 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6109 <op> $treg,0($tempreg)
6110 If there is a base register, we add it to $tempreg before
6111 the <op>. If there is a constant, we stick it in the
6112 <op> instruction. We don't handle constants larger than
6113 16 bits, because we have no way to load the upper 16 bits
6114 (actually, we could handle them for the subset of cases
6115 in which we are not using $at). */
6116 assert (offset_expr
.X_op
== O_symbol
);
6117 expr1
.X_add_number
= offset_expr
.X_add_number
;
6118 offset_expr
.X_add_number
= 0;
6119 if (expr1
.X_add_number
< -0x8000
6120 || expr1
.X_add_number
>= 0x8000)
6121 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6122 gpdelay
= reg_needs_delay (mips_gp_register
);
6123 relax_start (offset_expr
.X_add_symbol
);
6124 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6125 BFD_RELOC_MIPS_GOT_HI16
);
6126 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6128 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6129 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6132 macro_build (NULL
, "nop", "");
6133 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6134 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6136 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6137 tempreg
, BFD_RELOC_LO16
);
6141 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6142 tempreg
, tempreg
, breg
);
6143 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6145 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6147 /* If this is a reference to an external symbol, we want
6148 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6149 add $tempreg,$tempreg,$gp
6150 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6151 <op> $treg,<ofst>($tempreg)
6152 Otherwise, for local symbols, we want:
6153 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6154 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6155 assert (offset_expr
.X_op
== O_symbol
);
6156 expr1
.X_add_number
= offset_expr
.X_add_number
;
6157 offset_expr
.X_add_number
= 0;
6158 if (expr1
.X_add_number
< -0x8000
6159 || expr1
.X_add_number
>= 0x8000)
6160 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6161 relax_start (offset_expr
.X_add_symbol
);
6162 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6163 BFD_RELOC_MIPS_GOT_HI16
);
6164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6166 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6167 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6169 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6170 tempreg
, tempreg
, breg
);
6171 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6174 offset_expr
.X_add_number
= expr1
.X_add_number
;
6175 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6176 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6178 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6179 tempreg
, tempreg
, breg
);
6180 macro_build (&offset_expr
, s
, fmt
, treg
,
6181 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6194 load_register (treg
, &imm_expr
, 0);
6198 load_register (treg
, &imm_expr
, 1);
6202 if (imm_expr
.X_op
== O_constant
)
6204 load_register (AT
, &imm_expr
, 0);
6205 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6210 assert (offset_expr
.X_op
== O_symbol
6211 && strcmp (segment_name (S_GET_SEGMENT
6212 (offset_expr
.X_add_symbol
)),
6214 && offset_expr
.X_add_number
== 0);
6215 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6216 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6221 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6222 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6223 order 32 bits of the value and the low order 32 bits are either
6224 zero or in OFFSET_EXPR. */
6225 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6227 if (HAVE_64BIT_GPRS
)
6228 load_register (treg
, &imm_expr
, 1);
6233 if (target_big_endian
)
6245 load_register (hreg
, &imm_expr
, 0);
6248 if (offset_expr
.X_op
== O_absent
)
6249 move_register (lreg
, 0);
6252 assert (offset_expr
.X_op
== O_constant
);
6253 load_register (lreg
, &offset_expr
, 0);
6260 /* We know that sym is in the .rdata section. First we get the
6261 upper 16 bits of the address. */
6262 if (mips_pic
== NO_PIC
)
6264 macro_build_lui (&offset_expr
, AT
);
6266 else if (mips_pic
== SVR4_PIC
)
6268 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6269 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6274 /* Now we load the register(s). */
6275 if (HAVE_64BIT_GPRS
)
6276 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6279 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6282 /* FIXME: How in the world do we deal with the possible
6284 offset_expr
.X_add_number
+= 4;
6285 macro_build (&offset_expr
, "lw", "t,o(b)",
6286 treg
+ 1, BFD_RELOC_LO16
, AT
);
6292 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6293 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6294 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6295 the value and the low order 32 bits are either zero or in
6297 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6299 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6300 if (HAVE_64BIT_FPRS
)
6302 assert (HAVE_64BIT_GPRS
);
6303 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6307 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6308 if (offset_expr
.X_op
== O_absent
)
6309 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6312 assert (offset_expr
.X_op
== O_constant
);
6313 load_register (AT
, &offset_expr
, 0);
6314 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6320 assert (offset_expr
.X_op
== O_symbol
6321 && offset_expr
.X_add_number
== 0);
6322 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6323 if (strcmp (s
, ".lit8") == 0)
6325 if (mips_opts
.isa
!= ISA_MIPS1
)
6327 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6328 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6331 breg
= mips_gp_register
;
6332 r
= BFD_RELOC_MIPS_LITERAL
;
6337 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6338 if (mips_pic
== SVR4_PIC
)
6339 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6340 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6343 /* FIXME: This won't work for a 64 bit address. */
6344 macro_build_lui (&offset_expr
, AT
);
6347 if (mips_opts
.isa
!= ISA_MIPS1
)
6349 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6350 treg
, BFD_RELOC_LO16
, AT
);
6359 if (mips_opts
.arch
== CPU_R4650
)
6361 as_bad (_("opcode not supported on this processor"));
6364 /* Even on a big endian machine $fn comes before $fn+1. We have
6365 to adjust when loading from memory. */
6368 assert (mips_opts
.isa
== ISA_MIPS1
);
6369 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6370 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6371 /* FIXME: A possible overflow which I don't know how to deal
6373 offset_expr
.X_add_number
+= 4;
6374 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6375 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6383 * The MIPS assembler seems to check for X_add_number not
6384 * being double aligned and generating:
6387 * addiu at,at,%lo(foo+1)
6390 * But, the resulting address is the same after relocation so why
6391 * generate the extra instruction?
6393 if (mips_opts
.arch
== CPU_R4650
)
6395 as_bad (_("opcode not supported on this processor"));
6398 /* Itbl support may require additional care here. */
6400 if (mips_opts
.isa
!= ISA_MIPS1
)
6411 if (mips_opts
.arch
== CPU_R4650
)
6413 as_bad (_("opcode not supported on this processor"));
6417 if (mips_opts
.isa
!= ISA_MIPS1
)
6425 /* Itbl support may require additional care here. */
6430 if (HAVE_64BIT_GPRS
)
6441 if (HAVE_64BIT_GPRS
)
6451 if (offset_expr
.X_op
!= O_symbol
6452 && offset_expr
.X_op
!= O_constant
)
6454 as_bad (_("expression too complex"));
6455 offset_expr
.X_op
= O_constant
;
6458 /* Even on a big endian machine $fn comes before $fn+1. We have
6459 to adjust when loading from memory. We set coproc if we must
6460 load $fn+1 first. */
6461 /* Itbl support may require additional care here. */
6462 if (! target_big_endian
)
6465 if (mips_pic
== NO_PIC
6466 || offset_expr
.X_op
== O_constant
)
6468 /* If this is a reference to a GP relative symbol, we want
6469 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6470 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6471 If we have a base register, we use this
6473 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6474 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6475 If this is not a GP relative symbol, we want
6476 lui $at,<sym> (BFD_RELOC_HI16_S)
6477 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6478 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6479 If there is a base register, we add it to $at after the
6480 lui instruction. If there is a constant, we always use
6482 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6483 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6487 relax_start (offset_expr
.X_add_symbol
);
6490 tempreg
= mips_gp_register
;
6495 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6496 AT
, breg
, mips_gp_register
);
6501 /* Itbl support may require additional care here. */
6502 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6503 BFD_RELOC_GPREL16
, tempreg
);
6504 offset_expr
.X_add_number
+= 4;
6506 /* Set mips_optimize to 2 to avoid inserting an
6508 hold_mips_optimize
= mips_optimize
;
6510 /* Itbl support may require additional care here. */
6511 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6512 BFD_RELOC_GPREL16
, tempreg
);
6513 mips_optimize
= hold_mips_optimize
;
6517 /* We just generated two relocs. When tc_gen_reloc
6518 handles this case, it will skip the first reloc and
6519 handle the second. The second reloc already has an
6520 extra addend of 4, which we added above. We must
6521 subtract it out, and then subtract another 4 to make
6522 the first reloc come out right. The second reloc
6523 will come out right because we are going to add 4 to
6524 offset_expr when we build its instruction below.
6526 If we have a symbol, then we don't want to include
6527 the offset, because it will wind up being included
6528 when we generate the reloc. */
6530 if (offset_expr
.X_op
== O_constant
)
6531 offset_expr
.X_add_number
-= 8;
6534 offset_expr
.X_add_number
= -4;
6535 offset_expr
.X_op
= O_constant
;
6538 macro_build_lui (&offset_expr
, AT
);
6540 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6541 /* Itbl support may require additional care here. */
6542 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6543 BFD_RELOC_LO16
, AT
);
6544 /* FIXME: How do we handle overflow here? */
6545 offset_expr
.X_add_number
+= 4;
6546 /* Itbl support may require additional care here. */
6547 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6548 BFD_RELOC_LO16
, AT
);
6549 if (mips_relax
.sequence
)
6552 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6554 /* If this is a reference to an external symbol, we want
6555 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6560 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6562 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6563 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6564 If there is a base register we add it to $at before the
6565 lwc1 instructions. If there is a constant we include it
6566 in the lwc1 instructions. */
6568 expr1
.X_add_number
= offset_expr
.X_add_number
;
6569 if (expr1
.X_add_number
< -0x8000
6570 || expr1
.X_add_number
>= 0x8000 - 4)
6571 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6572 load_got_offset (AT
, &offset_expr
);
6575 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6577 /* Set mips_optimize to 2 to avoid inserting an undesired
6579 hold_mips_optimize
= mips_optimize
;
6582 /* Itbl support may require additional care here. */
6583 relax_start (offset_expr
.X_add_symbol
);
6584 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6585 BFD_RELOC_LO16
, AT
);
6586 expr1
.X_add_number
+= 4;
6587 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6588 BFD_RELOC_LO16
, AT
);
6590 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6591 BFD_RELOC_LO16
, AT
);
6592 offset_expr
.X_add_number
+= 4;
6593 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6594 BFD_RELOC_LO16
, AT
);
6597 mips_optimize
= hold_mips_optimize
;
6599 else if (mips_pic
== SVR4_PIC
)
6603 /* If this is a reference to an external symbol, we want
6604 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6606 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6611 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6613 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6614 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6615 If there is a base register we add it to $at before the
6616 lwc1 instructions. If there is a constant we include it
6617 in the lwc1 instructions. */
6619 expr1
.X_add_number
= offset_expr
.X_add_number
;
6620 offset_expr
.X_add_number
= 0;
6621 if (expr1
.X_add_number
< -0x8000
6622 || expr1
.X_add_number
>= 0x8000 - 4)
6623 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6624 gpdelay
= reg_needs_delay (mips_gp_register
);
6625 relax_start (offset_expr
.X_add_symbol
);
6626 macro_build (&offset_expr
, "lui", "t,u",
6627 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6628 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6629 AT
, AT
, mips_gp_register
);
6630 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6631 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6634 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6635 /* Itbl support may require additional care here. */
6636 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6637 BFD_RELOC_LO16
, AT
);
6638 expr1
.X_add_number
+= 4;
6640 /* Set mips_optimize to 2 to avoid inserting an undesired
6642 hold_mips_optimize
= mips_optimize
;
6644 /* Itbl support may require additional care here. */
6645 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6646 BFD_RELOC_LO16
, AT
);
6647 mips_optimize
= hold_mips_optimize
;
6648 expr1
.X_add_number
-= 4;
6651 offset_expr
.X_add_number
= expr1
.X_add_number
;
6653 macro_build (NULL
, "nop", "");
6654 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6655 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6658 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6659 /* Itbl support may require additional care here. */
6660 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6661 BFD_RELOC_LO16
, AT
);
6662 offset_expr
.X_add_number
+= 4;
6664 /* Set mips_optimize to 2 to avoid inserting an undesired
6666 hold_mips_optimize
= mips_optimize
;
6668 /* Itbl support may require additional care here. */
6669 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6670 BFD_RELOC_LO16
, AT
);
6671 mips_optimize
= hold_mips_optimize
;
6688 assert (HAVE_32BIT_ADDRESSES
);
6689 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6690 offset_expr
.X_add_number
+= 4;
6691 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6694 /* New code added to support COPZ instructions.
6695 This code builds table entries out of the macros in mip_opcodes.
6696 R4000 uses interlocks to handle coproc delays.
6697 Other chips (like the R3000) require nops to be inserted for delays.
6699 FIXME: Currently, we require that the user handle delays.
6700 In order to fill delay slots for non-interlocked chips,
6701 we must have a way to specify delays based on the coprocessor.
6702 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6703 What are the side-effects of the cop instruction?
6704 What cache support might we have and what are its effects?
6705 Both coprocessor & memory require delays. how long???
6706 What registers are read/set/modified?
6708 If an itbl is provided to interpret cop instructions,
6709 this knowledge can be encoded in the itbl spec. */
6723 /* For now we just do C (same as Cz). The parameter will be
6724 stored in insn_opcode by mips_ip. */
6725 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6729 move_register (dreg
, sreg
);
6732 #ifdef LOSING_COMPILER
6734 /* Try and see if this is a new itbl instruction.
6735 This code builds table entries out of the macros in mip_opcodes.
6736 FIXME: For now we just assemble the expression and pass it's
6737 value along as a 32-bit immediate.
6738 We may want to have the assembler assemble this value,
6739 so that we gain the assembler's knowledge of delay slots,
6741 Would it be more efficient to use mask (id) here? */
6742 if (itbl_have_entries
6743 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6745 s
= ip
->insn_mo
->name
;
6747 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6748 macro_build (&immed_expr
, s
, "C");
6755 as_warn (_("Macro used $at after \".set noat\""));
6759 macro2 (struct mips_cl_insn
*ip
)
6761 register int treg
, sreg
, dreg
, breg
;
6776 bfd_reloc_code_real_type r
;
6778 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6779 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6780 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6781 mask
= ip
->insn_mo
->mask
;
6783 expr1
.X_op
= O_constant
;
6784 expr1
.X_op_symbol
= NULL
;
6785 expr1
.X_add_symbol
= NULL
;
6786 expr1
.X_add_number
= 1;
6790 #endif /* LOSING_COMPILER */
6795 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6796 macro_build (NULL
, "mflo", "d", dreg
);
6802 /* The MIPS assembler some times generates shifts and adds. I'm
6803 not trying to be that fancy. GCC should do this for us
6805 load_register (AT
, &imm_expr
, dbl
);
6806 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6807 macro_build (NULL
, "mflo", "d", dreg
);
6820 mips_emit_delays (TRUE
);
6821 ++mips_opts
.noreorder
;
6822 mips_any_noreorder
= 1;
6824 load_register (AT
, &imm_expr
, dbl
);
6825 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6826 macro_build (NULL
, "mflo", "d", dreg
);
6827 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6828 macro_build (NULL
, "mfhi", "d", AT
);
6830 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6833 expr1
.X_add_number
= 8;
6834 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6835 macro_build (NULL
, "nop", "", 0);
6836 macro_build (NULL
, "break", "c", 6);
6838 --mips_opts
.noreorder
;
6839 macro_build (NULL
, "mflo", "d", dreg
);
6852 mips_emit_delays (TRUE
);
6853 ++mips_opts
.noreorder
;
6854 mips_any_noreorder
= 1;
6856 load_register (AT
, &imm_expr
, dbl
);
6857 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6858 sreg
, imm
? AT
: treg
);
6859 macro_build (NULL
, "mfhi", "d", AT
);
6860 macro_build (NULL
, "mflo", "d", dreg
);
6862 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6865 expr1
.X_add_number
= 8;
6866 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6867 macro_build (NULL
, "nop", "", 0);
6868 macro_build (NULL
, "break", "c", 6);
6870 --mips_opts
.noreorder
;
6874 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6886 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6887 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6892 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6893 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6894 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6895 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6899 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6911 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6912 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6917 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6918 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6919 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6920 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6928 if (imm_expr
.X_op
!= O_constant
)
6929 as_bad (_("Improper rotate count"));
6930 rot
= imm_expr
.X_add_number
& 0x3f;
6931 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6933 rot
= (64 - rot
) & 0x3f;
6935 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6937 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6942 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6945 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6946 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6948 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6949 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6950 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6958 if (imm_expr
.X_op
!= O_constant
)
6959 as_bad (_("Improper rotate count"));
6960 rot
= imm_expr
.X_add_number
& 0x1f;
6961 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6963 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6968 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6971 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6972 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6973 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6978 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6980 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6983 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6984 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6985 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6986 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6990 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6992 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6995 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6996 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6997 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6998 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7006 if (imm_expr
.X_op
!= O_constant
)
7007 as_bad (_("Improper rotate count"));
7008 rot
= imm_expr
.X_add_number
& 0x3f;
7009 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7012 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7014 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7019 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7022 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7023 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7025 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7026 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7027 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7035 if (imm_expr
.X_op
!= O_constant
)
7036 as_bad (_("Improper rotate count"));
7037 rot
= imm_expr
.X_add_number
& 0x1f;
7038 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7040 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7045 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7048 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7049 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7050 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7055 if (mips_opts
.arch
== CPU_R4650
)
7057 as_bad (_("opcode not supported on this processor"));
7060 assert (mips_opts
.isa
== ISA_MIPS1
);
7061 /* Even on a big endian machine $fn comes before $fn+1. We have
7062 to adjust when storing to memory. */
7063 macro_build (&offset_expr
, "swc1", "T,o(b)",
7064 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7065 offset_expr
.X_add_number
+= 4;
7066 macro_build (&offset_expr
, "swc1", "T,o(b)",
7067 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7072 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7074 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7077 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7078 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7083 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7085 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7090 as_warn (_("Instruction %s: result is always false"),
7092 move_register (dreg
, 0);
7095 if (imm_expr
.X_op
== O_constant
7096 && imm_expr
.X_add_number
>= 0
7097 && imm_expr
.X_add_number
< 0x10000)
7099 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7102 else if (imm_expr
.X_op
== O_constant
7103 && imm_expr
.X_add_number
> -0x8000
7104 && imm_expr
.X_add_number
< 0)
7106 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7107 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7108 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7113 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7114 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7117 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7122 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7128 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7129 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7132 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7134 if (imm_expr
.X_op
== O_constant
7135 && imm_expr
.X_add_number
>= -0x8000
7136 && imm_expr
.X_add_number
< 0x8000)
7138 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7139 dreg
, sreg
, BFD_RELOC_LO16
);
7144 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7145 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7149 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7154 case M_SGT
: /* sreg > treg <==> treg < sreg */
7160 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7163 case M_SGT_I
: /* sreg > I <==> I < sreg */
7169 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7170 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7173 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7179 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7180 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7183 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7189 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7190 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7191 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7195 if (imm_expr
.X_op
== O_constant
7196 && imm_expr
.X_add_number
>= -0x8000
7197 && imm_expr
.X_add_number
< 0x8000)
7199 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7202 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7203 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7207 if (imm_expr
.X_op
== O_constant
7208 && imm_expr
.X_add_number
>= -0x8000
7209 && imm_expr
.X_add_number
< 0x8000)
7211 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7215 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7216 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7221 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7223 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7226 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7227 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7232 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7234 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7239 as_warn (_("Instruction %s: result is always true"),
7241 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7242 dreg
, 0, BFD_RELOC_LO16
);
7245 if (imm_expr
.X_op
== O_constant
7246 && imm_expr
.X_add_number
>= 0
7247 && imm_expr
.X_add_number
< 0x10000)
7249 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7252 else if (imm_expr
.X_op
== O_constant
7253 && imm_expr
.X_add_number
> -0x8000
7254 && imm_expr
.X_add_number
< 0)
7256 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7257 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7258 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7263 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7264 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7267 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7275 if (imm_expr
.X_op
== O_constant
7276 && imm_expr
.X_add_number
> -0x8000
7277 && imm_expr
.X_add_number
<= 0x8000)
7279 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7280 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7281 dreg
, sreg
, BFD_RELOC_LO16
);
7284 load_register (AT
, &imm_expr
, dbl
);
7285 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7291 if (imm_expr
.X_op
== O_constant
7292 && imm_expr
.X_add_number
> -0x8000
7293 && imm_expr
.X_add_number
<= 0x8000)
7295 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7296 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7297 dreg
, sreg
, BFD_RELOC_LO16
);
7300 load_register (AT
, &imm_expr
, dbl
);
7301 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7322 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7323 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7328 assert (mips_opts
.isa
== ISA_MIPS1
);
7329 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7330 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7333 * Is the double cfc1 instruction a bug in the mips assembler;
7334 * or is there a reason for it?
7336 mips_emit_delays (TRUE
);
7337 ++mips_opts
.noreorder
;
7338 mips_any_noreorder
= 1;
7339 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7340 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7341 macro_build (NULL
, "nop", "");
7342 expr1
.X_add_number
= 3;
7343 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7344 expr1
.X_add_number
= 2;
7345 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7346 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7347 macro_build (NULL
, "nop", "");
7348 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7350 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7351 macro_build (NULL
, "nop", "");
7352 --mips_opts
.noreorder
;
7361 if (offset_expr
.X_add_number
>= 0x7fff)
7362 as_bad (_("operand overflow"));
7363 if (! target_big_endian
)
7364 ++offset_expr
.X_add_number
;
7365 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7366 if (! target_big_endian
)
7367 --offset_expr
.X_add_number
;
7369 ++offset_expr
.X_add_number
;
7370 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7371 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7372 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7385 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7386 as_bad (_("operand overflow"));
7391 if (! target_big_endian
)
7392 offset_expr
.X_add_number
+= off
;
7393 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7394 if (! target_big_endian
)
7395 offset_expr
.X_add_number
-= off
;
7397 offset_expr
.X_add_number
+= off
;
7398 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7400 /* If necessary, move the result in tempreg the final destination. */
7401 if (treg
== tempreg
)
7403 /* Protect second load's delay slot. */
7405 move_register (treg
, tempreg
);
7419 load_address (AT
, &offset_expr
, &used_at
);
7421 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7422 if (! target_big_endian
)
7423 expr1
.X_add_number
= off
;
7425 expr1
.X_add_number
= 0;
7426 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7427 if (! target_big_endian
)
7428 expr1
.X_add_number
= 0;
7430 expr1
.X_add_number
= off
;
7431 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7437 load_address (AT
, &offset_expr
, &used_at
);
7439 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7440 if (target_big_endian
)
7441 expr1
.X_add_number
= 0;
7442 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7443 treg
, BFD_RELOC_LO16
, AT
);
7444 if (target_big_endian
)
7445 expr1
.X_add_number
= 1;
7447 expr1
.X_add_number
= 0;
7448 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7449 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7450 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7454 if (offset_expr
.X_add_number
>= 0x7fff)
7455 as_bad (_("operand overflow"));
7456 if (target_big_endian
)
7457 ++offset_expr
.X_add_number
;
7458 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7459 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7460 if (target_big_endian
)
7461 --offset_expr
.X_add_number
;
7463 ++offset_expr
.X_add_number
;
7464 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7477 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7478 as_bad (_("operand overflow"));
7479 if (! target_big_endian
)
7480 offset_expr
.X_add_number
+= off
;
7481 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7482 if (! target_big_endian
)
7483 offset_expr
.X_add_number
-= off
;
7485 offset_expr
.X_add_number
+= off
;
7486 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7500 load_address (AT
, &offset_expr
, &used_at
);
7502 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7503 if (! target_big_endian
)
7504 expr1
.X_add_number
= off
;
7506 expr1
.X_add_number
= 0;
7507 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7508 if (! target_big_endian
)
7509 expr1
.X_add_number
= 0;
7511 expr1
.X_add_number
= off
;
7512 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7517 load_address (AT
, &offset_expr
, &used_at
);
7519 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7520 if (! target_big_endian
)
7521 expr1
.X_add_number
= 0;
7522 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7523 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7524 if (! target_big_endian
)
7525 expr1
.X_add_number
= 1;
7527 expr1
.X_add_number
= 0;
7528 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7529 if (! target_big_endian
)
7530 expr1
.X_add_number
= 0;
7532 expr1
.X_add_number
= 1;
7533 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7534 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7535 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7539 /* FIXME: Check if this is one of the itbl macros, since they
7540 are added dynamically. */
7541 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7545 as_warn (_("Macro used $at after \".set noat\""));
7548 /* Implement macros in mips16 mode. */
7551 mips16_macro (struct mips_cl_insn
*ip
)
7554 int xreg
, yreg
, zreg
, tmp
;
7557 const char *s
, *s2
, *s3
;
7559 mask
= ip
->insn_mo
->mask
;
7561 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7562 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7563 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7565 expr1
.X_op
= O_constant
;
7566 expr1
.X_op_symbol
= NULL
;
7567 expr1
.X_add_symbol
= NULL
;
7568 expr1
.X_add_number
= 1;
7587 mips_emit_delays (TRUE
);
7588 ++mips_opts
.noreorder
;
7589 mips_any_noreorder
= 1;
7590 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7591 expr1
.X_add_number
= 2;
7592 macro_build (&expr1
, "bnez", "x,p", yreg
);
7593 macro_build (NULL
, "break", "6", 7);
7595 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7596 since that causes an overflow. We should do that as well,
7597 but I don't see how to do the comparisons without a temporary
7599 --mips_opts
.noreorder
;
7600 macro_build (NULL
, s
, "x", zreg
);
7619 mips_emit_delays (TRUE
);
7620 ++mips_opts
.noreorder
;
7621 mips_any_noreorder
= 1;
7622 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7623 expr1
.X_add_number
= 2;
7624 macro_build (&expr1
, "bnez", "x,p", yreg
);
7625 macro_build (NULL
, "break", "6", 7);
7626 --mips_opts
.noreorder
;
7627 macro_build (NULL
, s2
, "x", zreg
);
7633 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7634 macro_build (NULL
, "mflo", "x", zreg
);
7642 if (imm_expr
.X_op
!= O_constant
)
7643 as_bad (_("Unsupported large constant"));
7644 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7645 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7649 if (imm_expr
.X_op
!= O_constant
)
7650 as_bad (_("Unsupported large constant"));
7651 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7652 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7656 if (imm_expr
.X_op
!= O_constant
)
7657 as_bad (_("Unsupported large constant"));
7658 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7659 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7681 goto do_reverse_branch
;
7685 goto do_reverse_branch
;
7697 goto do_reverse_branch
;
7708 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7709 macro_build (&offset_expr
, s2
, "p");
7736 goto do_addone_branch_i
;
7741 goto do_addone_branch_i
;
7756 goto do_addone_branch_i
;
7763 if (imm_expr
.X_op
!= O_constant
)
7764 as_bad (_("Unsupported large constant"));
7765 ++imm_expr
.X_add_number
;
7768 macro_build (&imm_expr
, s
, s3
, xreg
);
7769 macro_build (&offset_expr
, s2
, "p");
7773 expr1
.X_add_number
= 0;
7774 macro_build (&expr1
, "slti", "x,8", yreg
);
7776 move_register (xreg
, yreg
);
7777 expr1
.X_add_number
= 2;
7778 macro_build (&expr1
, "bteqz", "p");
7779 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7783 /* For consistency checking, verify that all bits are specified either
7784 by the match/mask part of the instruction definition, or by the
7787 validate_mips_insn (const struct mips_opcode
*opc
)
7789 const char *p
= opc
->args
;
7791 unsigned long used_bits
= opc
->mask
;
7793 if ((used_bits
& opc
->match
) != opc
->match
)
7795 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7796 opc
->name
, opc
->args
);
7799 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7809 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7810 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7811 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7812 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7813 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7814 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7815 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7816 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7817 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7820 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7821 c
, opc
->name
, opc
->args
);
7825 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7826 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7828 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7829 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7830 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7831 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7833 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7834 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7836 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7837 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7839 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7840 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7841 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7842 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7843 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7844 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7845 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7846 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7847 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7848 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7849 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7850 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7851 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7852 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7853 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7854 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7855 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7857 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7858 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7859 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7860 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7862 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7863 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7864 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7865 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7866 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7867 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7868 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7869 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7870 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7873 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7874 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7875 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7876 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7877 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7881 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7882 c
, opc
->name
, opc
->args
);
7886 if (used_bits
!= 0xffffffff)
7888 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7889 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7895 /* This routine assembles an instruction into its binary format. As a
7896 side effect, it sets one of the global variables imm_reloc or
7897 offset_reloc to the type of relocation to do if one of the operands
7898 is an address expression. */
7901 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7906 struct mips_opcode
*insn
;
7909 unsigned int lastregno
= 0;
7910 unsigned int lastpos
= 0;
7911 unsigned int limlo
, limhi
;
7917 /* If the instruction contains a '.', we first try to match an instruction
7918 including the '.'. Then we try again without the '.'. */
7920 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7923 /* If we stopped on whitespace, then replace the whitespace with null for
7924 the call to hash_find. Save the character we replaced just in case we
7925 have to re-parse the instruction. */
7932 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7934 /* If we didn't find the instruction in the opcode table, try again, but
7935 this time with just the instruction up to, but not including the
7939 /* Restore the character we overwrite above (if any). */
7943 /* Scan up to the first '.' or whitespace. */
7945 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7949 /* If we did not find a '.', then we can quit now. */
7952 insn_error
= "unrecognized opcode";
7956 /* Lookup the instruction in the hash table. */
7958 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7960 insn_error
= "unrecognized opcode";
7970 assert (strcmp (insn
->name
, str
) == 0);
7972 if (OPCODE_IS_MEMBER (insn
,
7974 | (file_ase_mips16
? INSN_MIPS16
: 0)
7975 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7976 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7982 if (insn
->pinfo
!= INSN_MACRO
)
7984 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7990 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7991 && strcmp (insn
->name
, insn
[1].name
) == 0)
8000 static char buf
[100];
8002 _("opcode not supported on this processor: %s (%s)"),
8003 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8004 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8014 ip
->insn_opcode
= insn
->match
;
8016 for (args
= insn
->args
;; ++args
)
8020 s
+= strspn (s
, " \t");
8024 case '\0': /* end of args */
8037 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8041 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8045 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8049 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8055 /* Handle optional base register.
8056 Either the base register is omitted or
8057 we must have a left paren. */
8058 /* This is dependent on the next operand specifier
8059 is a base register specification. */
8060 assert (args
[1] == 'b' || args
[1] == '5'
8061 || args
[1] == '-' || args
[1] == '4');
8065 case ')': /* these must match exactly */
8072 case '+': /* Opcode extension character. */
8075 case 'A': /* ins/ext position, becomes LSB. */
8084 my_getExpression (&imm_expr
, s
);
8085 check_absolute_expr (ip
, &imm_expr
);
8086 if ((unsigned long) imm_expr
.X_add_number
< limlo
8087 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8089 as_bad (_("Improper position (%lu)"),
8090 (unsigned long) imm_expr
.X_add_number
);
8091 imm_expr
.X_add_number
= limlo
;
8093 lastpos
= imm_expr
.X_add_number
;
8094 ip
->insn_opcode
|= (imm_expr
.X_add_number
8095 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8096 imm_expr
.X_op
= O_absent
;
8100 case 'B': /* ins size, becomes MSB. */
8109 my_getExpression (&imm_expr
, s
);
8110 check_absolute_expr (ip
, &imm_expr
);
8111 /* Check for negative input so that small negative numbers
8112 will not succeed incorrectly. The checks against
8113 (pos+size) transitively check "size" itself,
8114 assuming that "pos" is reasonable. */
8115 if ((long) imm_expr
.X_add_number
< 0
8116 || ((unsigned long) imm_expr
.X_add_number
8118 || ((unsigned long) imm_expr
.X_add_number
8121 as_bad (_("Improper insert size (%lu, position %lu)"),
8122 (unsigned long) imm_expr
.X_add_number
,
8123 (unsigned long) lastpos
);
8124 imm_expr
.X_add_number
= limlo
- lastpos
;
8126 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8127 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8128 imm_expr
.X_op
= O_absent
;
8132 case 'C': /* ext size, becomes MSBD. */
8145 my_getExpression (&imm_expr
, s
);
8146 check_absolute_expr (ip
, &imm_expr
);
8147 /* Check for negative input so that small negative numbers
8148 will not succeed incorrectly. The checks against
8149 (pos+size) transitively check "size" itself,
8150 assuming that "pos" is reasonable. */
8151 if ((long) imm_expr
.X_add_number
< 0
8152 || ((unsigned long) imm_expr
.X_add_number
8154 || ((unsigned long) imm_expr
.X_add_number
8157 as_bad (_("Improper extract size (%lu, position %lu)"),
8158 (unsigned long) imm_expr
.X_add_number
,
8159 (unsigned long) lastpos
);
8160 imm_expr
.X_add_number
= limlo
- lastpos
;
8162 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8163 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8164 imm_expr
.X_op
= O_absent
;
8169 /* +D is for disassembly only; never match. */
8173 /* "+I" is like "I", except that imm2_expr is used. */
8174 my_getExpression (&imm2_expr
, s
);
8175 if (imm2_expr
.X_op
!= O_big
8176 && imm2_expr
.X_op
!= O_constant
)
8177 insn_error
= _("absolute expression required");
8178 normalize_constant_expr (&imm2_expr
);
8183 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8184 *args
, insn
->name
, insn
->args
);
8185 /* Further processing is fruitless. */
8190 case '<': /* must be at least one digit */
8192 * According to the manual, if the shift amount is greater
8193 * than 31 or less than 0, then the shift amount should be
8194 * mod 32. In reality the mips assembler issues an error.
8195 * We issue a warning and mask out all but the low 5 bits.
8197 my_getExpression (&imm_expr
, s
);
8198 check_absolute_expr (ip
, &imm_expr
);
8199 if ((unsigned long) imm_expr
.X_add_number
> 31)
8201 as_warn (_("Improper shift amount (%lu)"),
8202 (unsigned long) imm_expr
.X_add_number
);
8203 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8205 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8206 imm_expr
.X_op
= O_absent
;
8210 case '>': /* shift amount minus 32 */
8211 my_getExpression (&imm_expr
, s
);
8212 check_absolute_expr (ip
, &imm_expr
);
8213 if ((unsigned long) imm_expr
.X_add_number
< 32
8214 || (unsigned long) imm_expr
.X_add_number
> 63)
8216 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8217 imm_expr
.X_op
= O_absent
;
8221 case 'k': /* cache code */
8222 case 'h': /* prefx code */
8223 my_getExpression (&imm_expr
, s
);
8224 check_absolute_expr (ip
, &imm_expr
);
8225 if ((unsigned long) imm_expr
.X_add_number
> 31)
8227 as_warn (_("Invalid value for `%s' (%lu)"),
8229 (unsigned long) imm_expr
.X_add_number
);
8230 imm_expr
.X_add_number
&= 0x1f;
8233 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8235 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8236 imm_expr
.X_op
= O_absent
;
8240 case 'c': /* break code */
8241 my_getExpression (&imm_expr
, s
);
8242 check_absolute_expr (ip
, &imm_expr
);
8243 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8245 as_warn (_("Illegal break code (%lu)"),
8246 (unsigned long) imm_expr
.X_add_number
);
8247 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8249 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8250 imm_expr
.X_op
= O_absent
;
8254 case 'q': /* lower break code */
8255 my_getExpression (&imm_expr
, s
);
8256 check_absolute_expr (ip
, &imm_expr
);
8257 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8259 as_warn (_("Illegal lower break code (%lu)"),
8260 (unsigned long) imm_expr
.X_add_number
);
8261 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8263 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8264 imm_expr
.X_op
= O_absent
;
8268 case 'B': /* 20-bit syscall/break code. */
8269 my_getExpression (&imm_expr
, s
);
8270 check_absolute_expr (ip
, &imm_expr
);
8271 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8272 as_warn (_("Illegal 20-bit code (%lu)"),
8273 (unsigned long) imm_expr
.X_add_number
);
8274 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8275 imm_expr
.X_op
= O_absent
;
8279 case 'C': /* Coprocessor code */
8280 my_getExpression (&imm_expr
, s
);
8281 check_absolute_expr (ip
, &imm_expr
);
8282 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8284 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8285 (unsigned long) imm_expr
.X_add_number
);
8286 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8288 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8289 imm_expr
.X_op
= O_absent
;
8293 case 'J': /* 19-bit wait code. */
8294 my_getExpression (&imm_expr
, s
);
8295 check_absolute_expr (ip
, &imm_expr
);
8296 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8297 as_warn (_("Illegal 19-bit code (%lu)"),
8298 (unsigned long) imm_expr
.X_add_number
);
8299 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8300 imm_expr
.X_op
= O_absent
;
8304 case 'P': /* Performance register */
8305 my_getExpression (&imm_expr
, s
);
8306 check_absolute_expr (ip
, &imm_expr
);
8307 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8309 as_warn (_("Invalid performance register (%lu)"),
8310 (unsigned long) imm_expr
.X_add_number
);
8311 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8313 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8314 imm_expr
.X_op
= O_absent
;
8318 case 'b': /* base register */
8319 case 'd': /* destination register */
8320 case 's': /* source register */
8321 case 't': /* target register */
8322 case 'r': /* both target and source */
8323 case 'v': /* both dest and source */
8324 case 'w': /* both dest and target */
8325 case 'E': /* coprocessor target register */
8326 case 'G': /* coprocessor destination register */
8327 case 'K': /* 'rdhwr' destination register */
8328 case 'x': /* ignore register name */
8329 case 'z': /* must be zero register */
8330 case 'U': /* destination register (clo/clz). */
8345 while (ISDIGIT (*s
));
8347 as_bad (_("Invalid register number (%d)"), regno
);
8349 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8353 if (s
[1] == 'r' && s
[2] == 'a')
8358 else if (s
[1] == 'f' && s
[2] == 'p')
8363 else if (s
[1] == 's' && s
[2] == 'p')
8368 else if (s
[1] == 'g' && s
[2] == 'p')
8373 else if (s
[1] == 'a' && s
[2] == 't')
8378 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8383 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8388 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8393 else if (itbl_have_entries
)
8398 p
= s
+ 1; /* advance past '$' */
8399 n
= itbl_get_field (&p
); /* n is name */
8401 /* See if this is a register defined in an
8403 if (itbl_get_reg_val (n
, &r
))
8405 /* Get_field advances to the start of
8406 the next field, so we need to back
8407 rack to the end of the last field. */
8411 s
= strchr (s
, '\0');
8425 as_warn (_("Used $at without \".set noat\""));
8431 if (c
== 'r' || c
== 'v' || c
== 'w')
8438 /* 'z' only matches $0. */
8439 if (c
== 'z' && regno
!= 0)
8442 /* Now that we have assembled one operand, we use the args string
8443 * to figure out where it goes in the instruction. */
8450 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8455 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8458 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8459 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8464 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8467 /* This case exists because on the r3000 trunc
8468 expands into a macro which requires a gp
8469 register. On the r6000 or r4000 it is
8470 assembled into a single instruction which
8471 ignores the register. Thus the insn version
8472 is MIPS_ISA2 and uses 'x', and the macro
8473 version is MIPS_ISA1 and uses 't'. */
8476 /* This case is for the div instruction, which
8477 acts differently if the destination argument
8478 is $0. This only matches $0, and is checked
8479 outside the switch. */
8482 /* Itbl operand; not yet implemented. FIXME ?? */
8484 /* What about all other operands like 'i', which
8485 can be specified in the opcode table? */
8495 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8498 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8503 case 'O': /* MDMX alignment immediate constant. */
8504 my_getExpression (&imm_expr
, s
);
8505 check_absolute_expr (ip
, &imm_expr
);
8506 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8508 as_warn ("Improper align amount (%ld), using low bits",
8509 (long) imm_expr
.X_add_number
);
8510 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8512 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8513 imm_expr
.X_op
= O_absent
;
8517 case 'Q': /* MDMX vector, element sel, or const. */
8520 /* MDMX Immediate. */
8521 my_getExpression (&imm_expr
, s
);
8522 check_absolute_expr (ip
, &imm_expr
);
8523 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8525 as_warn (_("Invalid MDMX Immediate (%ld)"),
8526 (long) imm_expr
.X_add_number
);
8527 imm_expr
.X_add_number
&= OP_MASK_FT
;
8529 imm_expr
.X_add_number
&= OP_MASK_FT
;
8530 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8531 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8533 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8534 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8535 imm_expr
.X_op
= O_absent
;
8539 /* Not MDMX Immediate. Fall through. */
8540 case 'X': /* MDMX destination register. */
8541 case 'Y': /* MDMX source register. */
8542 case 'Z': /* MDMX target register. */
8544 case 'D': /* floating point destination register */
8545 case 'S': /* floating point source register */
8546 case 'T': /* floating point target register */
8547 case 'R': /* floating point source register */
8551 /* Accept $fN for FP and MDMX register numbers, and in
8552 addition accept $vN for MDMX register numbers. */
8553 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8554 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8565 while (ISDIGIT (*s
));
8568 as_bad (_("Invalid float register number (%d)"), regno
);
8570 if ((regno
& 1) != 0
8572 && ! (strcmp (str
, "mtc1") == 0
8573 || strcmp (str
, "mfc1") == 0
8574 || strcmp (str
, "lwc1") == 0
8575 || strcmp (str
, "swc1") == 0
8576 || strcmp (str
, "l.s") == 0
8577 || strcmp (str
, "s.s") == 0))
8578 as_warn (_("Float register should be even, was %d"),
8586 if (c
== 'V' || c
== 'W')
8597 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8602 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8605 /* This is like 'Z', but also needs to fix the MDMX
8606 vector/scalar select bits. Note that the
8607 scalar immediate case is handled above. */
8610 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8611 int max_el
= (is_qh
? 3 : 7);
8613 my_getExpression(&imm_expr
, s
);
8614 check_absolute_expr (ip
, &imm_expr
);
8616 if (imm_expr
.X_add_number
> max_el
)
8617 as_bad(_("Bad element selector %ld"),
8618 (long) imm_expr
.X_add_number
);
8619 imm_expr
.X_add_number
&= max_el
;
8620 ip
->insn_opcode
|= (imm_expr
.X_add_number
8623 imm_expr
.X_op
= O_absent
;
8625 as_warn(_("Expecting ']' found '%s'"), s
);
8631 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8632 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8635 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8642 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8645 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8655 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8658 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8664 my_getExpression (&imm_expr
, s
);
8665 if (imm_expr
.X_op
!= O_big
8666 && imm_expr
.X_op
!= O_constant
)
8667 insn_error
= _("absolute expression required");
8668 normalize_constant_expr (&imm_expr
);
8673 my_getExpression (&offset_expr
, s
);
8674 *imm_reloc
= BFD_RELOC_32
;
8687 unsigned char temp
[8];
8689 unsigned int length
;
8694 /* These only appear as the last operand in an
8695 instruction, and every instruction that accepts
8696 them in any variant accepts them in all variants.
8697 This means we don't have to worry about backing out
8698 any changes if the instruction does not match.
8700 The difference between them is the size of the
8701 floating point constant and where it goes. For 'F'
8702 and 'L' the constant is 64 bits; for 'f' and 'l' it
8703 is 32 bits. Where the constant is placed is based
8704 on how the MIPS assembler does things:
8707 f -- immediate value
8710 The .lit4 and .lit8 sections are only used if
8711 permitted by the -G argument.
8713 The code below needs to know whether the target register
8714 is 32 or 64 bits wide. It relies on the fact 'f' and
8715 'F' are used with GPR-based instructions and 'l' and
8716 'L' are used with FPR-based instructions. */
8718 f64
= *args
== 'F' || *args
== 'L';
8719 using_gprs
= *args
== 'F' || *args
== 'f';
8721 save_in
= input_line_pointer
;
8722 input_line_pointer
= s
;
8723 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8725 s
= input_line_pointer
;
8726 input_line_pointer
= save_in
;
8727 if (err
!= NULL
&& *err
!= '\0')
8729 as_bad (_("Bad floating point constant: %s"), err
);
8730 memset (temp
, '\0', sizeof temp
);
8731 length
= f64
? 8 : 4;
8734 assert (length
== (unsigned) (f64
? 8 : 4));
8738 && (g_switch_value
< 4
8739 || (temp
[0] == 0 && temp
[1] == 0)
8740 || (temp
[2] == 0 && temp
[3] == 0))))
8742 imm_expr
.X_op
= O_constant
;
8743 if (! target_big_endian
)
8744 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8746 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8749 && ! mips_disable_float_construction
8750 /* Constants can only be constructed in GPRs and
8751 copied to FPRs if the GPRs are at least as wide
8752 as the FPRs. Force the constant into memory if
8753 we are using 64-bit FPRs but the GPRs are only
8756 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8757 && ((temp
[0] == 0 && temp
[1] == 0)
8758 || (temp
[2] == 0 && temp
[3] == 0))
8759 && ((temp
[4] == 0 && temp
[5] == 0)
8760 || (temp
[6] == 0 && temp
[7] == 0)))
8762 /* The value is simple enough to load with a couple of
8763 instructions. If using 32-bit registers, set
8764 imm_expr to the high order 32 bits and offset_expr to
8765 the low order 32 bits. Otherwise, set imm_expr to
8766 the entire 64 bit constant. */
8767 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8769 imm_expr
.X_op
= O_constant
;
8770 offset_expr
.X_op
= O_constant
;
8771 if (! target_big_endian
)
8773 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8774 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8778 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8779 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8781 if (offset_expr
.X_add_number
== 0)
8782 offset_expr
.X_op
= O_absent
;
8784 else if (sizeof (imm_expr
.X_add_number
) > 4)
8786 imm_expr
.X_op
= O_constant
;
8787 if (! target_big_endian
)
8788 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8790 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8794 imm_expr
.X_op
= O_big
;
8795 imm_expr
.X_add_number
= 4;
8796 if (! target_big_endian
)
8798 generic_bignum
[0] = bfd_getl16 (temp
);
8799 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8800 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8801 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8805 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8806 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8807 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8808 generic_bignum
[3] = bfd_getb16 (temp
);
8814 const char *newname
;
8817 /* Switch to the right section. */
8819 subseg
= now_subseg
;
8822 default: /* unused default case avoids warnings. */
8824 newname
= RDATA_SECTION_NAME
;
8825 if (g_switch_value
>= 8)
8829 newname
= RDATA_SECTION_NAME
;
8832 assert (g_switch_value
>= 4);
8836 new_seg
= subseg_new (newname
, (subsegT
) 0);
8837 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8838 bfd_set_section_flags (stdoutput
, new_seg
,
8843 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8844 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8845 && strcmp (TARGET_OS
, "elf") != 0)
8846 record_alignment (new_seg
, 4);
8848 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8850 as_bad (_("Can't use floating point insn in this section"));
8852 /* Set the argument to the current address in the
8854 offset_expr
.X_op
= O_symbol
;
8855 offset_expr
.X_add_symbol
=
8856 symbol_new ("L0\001", now_seg
,
8857 (valueT
) frag_now_fix (), frag_now
);
8858 offset_expr
.X_add_number
= 0;
8860 /* Put the floating point number into the section. */
8861 p
= frag_more ((int) length
);
8862 memcpy (p
, temp
, length
);
8864 /* Switch back to the original section. */
8865 subseg_set (seg
, subseg
);
8870 case 'i': /* 16 bit unsigned immediate */
8871 case 'j': /* 16 bit signed immediate */
8872 *imm_reloc
= BFD_RELOC_LO16
;
8873 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8876 offsetT minval
, maxval
;
8878 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8879 && strcmp (insn
->name
, insn
[1].name
) == 0);
8881 /* If the expression was written as an unsigned number,
8882 only treat it as signed if there are no more
8886 && sizeof (imm_expr
.X_add_number
) <= 4
8887 && imm_expr
.X_op
== O_constant
8888 && imm_expr
.X_add_number
< 0
8889 && imm_expr
.X_unsigned
8893 /* For compatibility with older assemblers, we accept
8894 0x8000-0xffff as signed 16-bit numbers when only
8895 signed numbers are allowed. */
8897 minval
= 0, maxval
= 0xffff;
8899 minval
= -0x8000, maxval
= 0x7fff;
8901 minval
= -0x8000, maxval
= 0xffff;
8903 if (imm_expr
.X_op
!= O_constant
8904 || imm_expr
.X_add_number
< minval
8905 || imm_expr
.X_add_number
> maxval
)
8909 if (imm_expr
.X_op
== O_constant
8910 || imm_expr
.X_op
== O_big
)
8911 as_bad (_("expression out of range"));
8917 case 'o': /* 16 bit offset */
8918 /* Check whether there is only a single bracketed expression
8919 left. If so, it must be the base register and the
8920 constant must be zero. */
8921 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8923 offset_expr
.X_op
= O_constant
;
8924 offset_expr
.X_add_number
= 0;
8928 /* If this value won't fit into a 16 bit offset, then go
8929 find a macro that will generate the 32 bit offset
8931 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8932 && (offset_expr
.X_op
!= O_constant
8933 || offset_expr
.X_add_number
>= 0x8000
8934 || offset_expr
.X_add_number
< -0x8000))
8940 case 'p': /* pc relative offset */
8941 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8942 my_getExpression (&offset_expr
, s
);
8946 case 'u': /* upper 16 bits */
8947 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8948 && imm_expr
.X_op
== O_constant
8949 && (imm_expr
.X_add_number
< 0
8950 || imm_expr
.X_add_number
>= 0x10000))
8951 as_bad (_("lui expression not in range 0..65535"));
8955 case 'a': /* 26 bit address */
8956 my_getExpression (&offset_expr
, s
);
8958 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8961 case 'N': /* 3 bit branch condition code */
8962 case 'M': /* 3 bit compare condition code */
8963 if (strncmp (s
, "$fcc", 4) != 0)
8973 while (ISDIGIT (*s
));
8975 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8976 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8977 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8978 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8979 && (regno
& 1) != 0)
8980 as_warn(_("Condition code register should be even for %s, was %d"),
8982 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8983 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8984 && (regno
& 3) != 0)
8985 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8988 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8990 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8994 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9005 while (ISDIGIT (*s
));
9008 c
= 8; /* Invalid sel value. */
9011 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9012 ip
->insn_opcode
|= c
;
9016 /* Must be at least one digit. */
9017 my_getExpression (&imm_expr
, s
);
9018 check_absolute_expr (ip
, &imm_expr
);
9020 if ((unsigned long) imm_expr
.X_add_number
9021 > (unsigned long) OP_MASK_VECBYTE
)
9023 as_bad (_("bad byte vector index (%ld)"),
9024 (long) imm_expr
.X_add_number
);
9025 imm_expr
.X_add_number
= 0;
9028 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9029 imm_expr
.X_op
= O_absent
;
9034 my_getExpression (&imm_expr
, s
);
9035 check_absolute_expr (ip
, &imm_expr
);
9037 if ((unsigned long) imm_expr
.X_add_number
9038 > (unsigned long) OP_MASK_VECALIGN
)
9040 as_bad (_("bad byte vector index (%ld)"),
9041 (long) imm_expr
.X_add_number
);
9042 imm_expr
.X_add_number
= 0;
9045 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9046 imm_expr
.X_op
= O_absent
;
9051 as_bad (_("bad char = '%c'\n"), *args
);
9056 /* Args don't match. */
9057 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9058 !strcmp (insn
->name
, insn
[1].name
))
9062 insn_error
= _("illegal operands");
9067 insn_error
= _("illegal operands");
9072 /* This routine assembles an instruction into its binary format when
9073 assembling for the mips16. As a side effect, it sets one of the
9074 global variables imm_reloc or offset_reloc to the type of
9075 relocation to do if one of the operands is an address expression.
9076 It also sets mips16_small and mips16_ext if the user explicitly
9077 requested a small or extended instruction. */
9080 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9084 struct mips_opcode
*insn
;
9087 unsigned int lastregno
= 0;
9092 mips16_small
= FALSE
;
9095 for (s
= str
; ISLOWER (*s
); ++s
)
9107 if (s
[1] == 't' && s
[2] == ' ')
9110 mips16_small
= TRUE
;
9114 else if (s
[1] == 'e' && s
[2] == ' ')
9123 insn_error
= _("unknown opcode");
9127 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9128 mips16_small
= TRUE
;
9130 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9132 insn_error
= _("unrecognized opcode");
9139 assert (strcmp (insn
->name
, str
) == 0);
9142 ip
->insn_opcode
= insn
->match
;
9143 ip
->use_extend
= FALSE
;
9144 imm_expr
.X_op
= O_absent
;
9145 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9146 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9147 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9148 imm2_expr
.X_op
= O_absent
;
9149 offset_expr
.X_op
= O_absent
;
9150 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9151 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9152 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9153 for (args
= insn
->args
; 1; ++args
)
9160 /* In this switch statement we call break if we did not find
9161 a match, continue if we did find a match, or return if we
9170 /* Stuff the immediate value in now, if we can. */
9171 if (imm_expr
.X_op
== O_constant
9172 && *imm_reloc
> BFD_RELOC_UNUSED
9173 && insn
->pinfo
!= INSN_MACRO
)
9175 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9176 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9177 mips16_ext
, &ip
->insn_opcode
,
9178 &ip
->use_extend
, &ip
->extend
);
9179 imm_expr
.X_op
= O_absent
;
9180 *imm_reloc
= BFD_RELOC_UNUSED
;
9194 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9197 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9213 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9215 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9242 while (ISDIGIT (*s
));
9245 as_bad (_("invalid register number (%d)"), regno
);
9251 if (s
[1] == 'r' && s
[2] == 'a')
9256 else if (s
[1] == 'f' && s
[2] == 'p')
9261 else if (s
[1] == 's' && s
[2] == 'p')
9266 else if (s
[1] == 'g' && s
[2] == 'p')
9271 else if (s
[1] == 'a' && s
[2] == 't')
9276 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9281 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9286 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9299 if (c
== 'v' || c
== 'w')
9301 regno
= mips16_to_32_reg_map
[lastregno
];
9315 regno
= mips32_to_16_reg_map
[regno
];
9320 regno
= ILLEGAL_REG
;
9325 regno
= ILLEGAL_REG
;
9330 regno
= ILLEGAL_REG
;
9335 if (regno
== AT
&& ! mips_opts
.noat
)
9336 as_warn (_("used $at without \".set noat\""));
9343 if (regno
== ILLEGAL_REG
)
9350 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9354 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9357 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9360 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9366 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9369 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9370 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9380 if (strncmp (s
, "$pc", 3) == 0)
9404 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9406 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9407 and generate the appropriate reloc. If the text
9408 inside %gprel is not a symbol name with an
9409 optional offset, then we generate a normal reloc
9410 and will probably fail later. */
9411 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9412 if (imm_expr
.X_op
== O_symbol
)
9415 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9417 ip
->use_extend
= TRUE
;
9424 /* Just pick up a normal expression. */
9425 my_getExpression (&imm_expr
, s
);
9428 if (imm_expr
.X_op
== O_register
)
9430 /* What we thought was an expression turned out to
9433 if (s
[0] == '(' && args
[1] == '(')
9435 /* It looks like the expression was omitted
9436 before a register indirection, which means
9437 that the expression is implicitly zero. We
9438 still set up imm_expr, so that we handle
9439 explicit extensions correctly. */
9440 imm_expr
.X_op
= O_constant
;
9441 imm_expr
.X_add_number
= 0;
9442 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9449 /* We need to relax this instruction. */
9450 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9459 /* We use offset_reloc rather than imm_reloc for the PC
9460 relative operands. This lets macros with both
9461 immediate and address operands work correctly. */
9462 my_getExpression (&offset_expr
, s
);
9464 if (offset_expr
.X_op
== O_register
)
9467 /* We need to relax this instruction. */
9468 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9472 case '6': /* break code */
9473 my_getExpression (&imm_expr
, s
);
9474 check_absolute_expr (ip
, &imm_expr
);
9475 if ((unsigned long) imm_expr
.X_add_number
> 63)
9477 as_warn (_("Invalid value for `%s' (%lu)"),
9479 (unsigned long) imm_expr
.X_add_number
);
9480 imm_expr
.X_add_number
&= 0x3f;
9482 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9483 imm_expr
.X_op
= O_absent
;
9487 case 'a': /* 26 bit address */
9488 my_getExpression (&offset_expr
, s
);
9490 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9491 ip
->insn_opcode
<<= 16;
9494 case 'l': /* register list for entry macro */
9495 case 'L': /* register list for exit macro */
9505 int freg
, reg1
, reg2
;
9507 while (*s
== ' ' || *s
== ',')
9511 as_bad (_("can't parse register list"));
9523 while (ISDIGIT (*s
))
9545 as_bad (_("invalid register list"));
9550 while (ISDIGIT (*s
))
9557 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9562 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9567 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9568 mask
|= (reg2
- 3) << 3;
9569 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9570 mask
|= (reg2
- 15) << 1;
9571 else if (reg1
== RA
&& reg2
== RA
)
9575 as_bad (_("invalid register list"));
9579 /* The mask is filled in in the opcode table for the
9580 benefit of the disassembler. We remove it before
9581 applying the actual mask. */
9582 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9583 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9587 case 'e': /* extend code */
9588 my_getExpression (&imm_expr
, s
);
9589 check_absolute_expr (ip
, &imm_expr
);
9590 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9592 as_warn (_("Invalid value for `%s' (%lu)"),
9594 (unsigned long) imm_expr
.X_add_number
);
9595 imm_expr
.X_add_number
&= 0x7ff;
9597 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9598 imm_expr
.X_op
= O_absent
;
9608 /* Args don't match. */
9609 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9610 strcmp (insn
->name
, insn
[1].name
) == 0)
9617 insn_error
= _("illegal operands");
9623 /* This structure holds information we know about a mips16 immediate
9626 struct mips16_immed_operand
9628 /* The type code used in the argument string in the opcode table. */
9630 /* The number of bits in the short form of the opcode. */
9632 /* The number of bits in the extended form of the opcode. */
9634 /* The amount by which the short form is shifted when it is used;
9635 for example, the sw instruction has a shift count of 2. */
9637 /* The amount by which the short form is shifted when it is stored
9638 into the instruction code. */
9640 /* Non-zero if the short form is unsigned. */
9642 /* Non-zero if the extended form is unsigned. */
9644 /* Non-zero if the value is PC relative. */
9648 /* The mips16 immediate operand types. */
9650 static const struct mips16_immed_operand mips16_immed_operands
[] =
9652 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9653 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9654 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9655 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9656 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9657 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9658 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9659 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9660 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9661 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9662 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9663 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9664 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9665 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9666 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9667 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9668 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9669 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9670 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9671 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9672 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9675 #define MIPS16_NUM_IMMED \
9676 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9678 /* Handle a mips16 instruction with an immediate value. This or's the
9679 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9680 whether an extended value is needed; if one is needed, it sets
9681 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9682 If SMALL is true, an unextended opcode was explicitly requested.
9683 If EXT is true, an extended opcode was explicitly requested. If
9684 WARN is true, warn if EXT does not match reality. */
9687 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9688 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9689 unsigned long *insn
, bfd_boolean
*use_extend
,
9690 unsigned short *extend
)
9692 register const struct mips16_immed_operand
*op
;
9693 int mintiny
, maxtiny
;
9694 bfd_boolean needext
;
9696 op
= mips16_immed_operands
;
9697 while (op
->type
!= type
)
9700 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9705 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9708 maxtiny
= 1 << op
->nbits
;
9713 maxtiny
= (1 << op
->nbits
) - 1;
9718 mintiny
= - (1 << (op
->nbits
- 1));
9719 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9722 /* Branch offsets have an implicit 0 in the lowest bit. */
9723 if (type
== 'p' || type
== 'q')
9726 if ((val
& ((1 << op
->shift
) - 1)) != 0
9727 || val
< (mintiny
<< op
->shift
)
9728 || val
> (maxtiny
<< op
->shift
))
9733 if (warn
&& ext
&& ! needext
)
9734 as_warn_where (file
, line
,
9735 _("extended operand requested but not required"));
9736 if (small
&& needext
)
9737 as_bad_where (file
, line
, _("invalid unextended operand value"));
9739 if (small
|| (! ext
&& ! needext
))
9743 *use_extend
= FALSE
;
9744 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9745 insnval
<<= op
->op_shift
;
9750 long minext
, maxext
;
9756 maxext
= (1 << op
->extbits
) - 1;
9760 minext
= - (1 << (op
->extbits
- 1));
9761 maxext
= (1 << (op
->extbits
- 1)) - 1;
9763 if (val
< minext
|| val
> maxext
)
9764 as_bad_where (file
, line
,
9765 _("operand value out of range for instruction"));
9768 if (op
->extbits
== 16)
9770 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9773 else if (op
->extbits
== 15)
9775 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9780 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9784 *extend
= (unsigned short) extval
;
9789 static const struct percent_op_match
9792 bfd_reloc_code_real_type reloc
;
9795 {"%lo", BFD_RELOC_LO16
},
9797 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9798 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9799 {"%call16", BFD_RELOC_MIPS_CALL16
},
9800 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9801 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9802 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9803 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9804 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9805 {"%got", BFD_RELOC_MIPS_GOT16
},
9806 {"%gp_rel", BFD_RELOC_GPREL16
},
9807 {"%half", BFD_RELOC_16
},
9808 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9809 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9810 {"%neg", BFD_RELOC_MIPS_SUB
},
9812 {"%hi", BFD_RELOC_HI16_S
}
9816 /* Return true if *STR points to a relocation operator. When returning true,
9817 move *STR over the operator and store its relocation code in *RELOC.
9818 Leave both *STR and *RELOC alone when returning false. */
9821 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9825 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
9826 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9828 *str
+= strlen (percent_op
[i
].str
);
9829 *reloc
= percent_op
[i
].reloc
;
9831 /* Check whether the output BFD supports this relocation.
9832 If not, issue an error and fall back on something safe. */
9833 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9835 as_bad ("relocation %s isn't supported by the current ABI",
9837 *reloc
= BFD_RELOC_UNUSED
;
9845 /* Parse string STR as a 16-bit relocatable operand. Store the
9846 expression in *EP and the relocations in the array starting
9847 at RELOC. Return the number of relocation operators used.
9849 On exit, EXPR_END points to the first character after the expression. */
9852 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9855 bfd_reloc_code_real_type reversed_reloc
[3];
9856 size_t reloc_index
, i
;
9857 int crux_depth
, str_depth
;
9860 /* Search for the start of the main expression, recoding relocations
9861 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9862 of the main expression and with CRUX_DEPTH containing the number
9863 of open brackets at that point. */
9870 crux_depth
= str_depth
;
9872 /* Skip over whitespace and brackets, keeping count of the number
9874 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9879 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9880 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9882 my_getExpression (ep
, crux
);
9885 /* Match every open bracket. */
9886 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9891 as_bad ("unclosed '('");
9895 if (reloc_index
!= 0)
9897 prev_reloc_op_frag
= frag_now
;
9898 for (i
= 0; i
< reloc_index
; i
++)
9899 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9906 my_getExpression (expressionS
*ep
, char *str
)
9911 save_in
= input_line_pointer
;
9912 input_line_pointer
= str
;
9914 expr_end
= input_line_pointer
;
9915 input_line_pointer
= save_in
;
9917 /* If we are in mips16 mode, and this is an expression based on `.',
9918 then we bump the value of the symbol by 1 since that is how other
9919 text symbols are handled. We don't bother to handle complex
9920 expressions, just `.' plus or minus a constant. */
9921 if (mips_opts
.mips16
9922 && ep
->X_op
== O_symbol
9923 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9924 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9925 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9926 && symbol_constant_p (ep
->X_add_symbol
)
9927 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9928 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9931 /* Turn a string in input_line_pointer into a floating point constant
9932 of type TYPE, and store the appropriate bytes in *LITP. The number
9933 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9934 returned, or NULL on OK. */
9937 md_atof (int type
, char *litP
, int *sizeP
)
9940 LITTLENUM_TYPE words
[4];
9956 return _("bad call to md_atof");
9959 t
= atof_ieee (input_line_pointer
, type
, words
);
9961 input_line_pointer
= t
;
9965 if (! target_big_endian
)
9967 for (i
= prec
- 1; i
>= 0; i
--)
9969 md_number_to_chars (litP
, words
[i
], 2);
9975 for (i
= 0; i
< prec
; i
++)
9977 md_number_to_chars (litP
, words
[i
], 2);
9986 md_number_to_chars (char *buf
, valueT val
, int n
)
9988 if (target_big_endian
)
9989 number_to_chars_bigendian (buf
, val
, n
);
9991 number_to_chars_littleendian (buf
, val
, n
);
9995 static int support_64bit_objects(void)
9997 const char **list
, **l
;
10000 list
= bfd_target_list ();
10001 for (l
= list
; *l
!= NULL
; l
++)
10003 /* This is traditional mips */
10004 if (strcmp (*l
, "elf64-tradbigmips") == 0
10005 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10007 if (strcmp (*l
, "elf64-bigmips") == 0
10008 || strcmp (*l
, "elf64-littlemips") == 0)
10011 yes
= (*l
!= NULL
);
10015 #endif /* OBJ_ELF */
10017 const char *md_shortopts
= "O::g::G:";
10019 struct option md_longopts
[] =
10021 /* Options which specify architecture. */
10022 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10023 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10024 {"march", required_argument
, NULL
, OPTION_MARCH
},
10025 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10026 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10027 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10028 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10029 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10030 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10031 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10032 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10033 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10034 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10035 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10036 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10037 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10038 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10039 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10040 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10041 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10042 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10043 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10044 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10045 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10047 /* Options which specify Application Specific Extensions (ASEs). */
10048 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10049 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10050 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10051 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10052 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10053 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10054 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10055 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10056 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10057 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10058 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10059 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10060 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10062 /* Old-style architecture options. Don't add more of these. */
10063 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10064 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10065 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10066 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10067 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10068 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10069 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10070 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10071 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10072 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10073 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10074 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10075 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10076 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10077 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10078 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10079 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10081 /* Options which enable bug fixes. */
10082 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10083 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10084 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10085 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10086 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10087 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10088 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10089 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10090 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10091 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10093 /* Miscellaneous options. */
10094 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10095 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10096 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10097 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10098 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10099 {"break", no_argument
, NULL
, OPTION_BREAK
},
10100 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10101 #define OPTION_EB (OPTION_MISC_BASE + 2)
10102 {"EB", no_argument
, NULL
, OPTION_EB
},
10103 #define OPTION_EL (OPTION_MISC_BASE + 3)
10104 {"EL", no_argument
, NULL
, OPTION_EL
},
10105 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10106 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10107 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10108 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10109 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10110 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10111 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10112 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10113 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10114 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10115 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10116 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10117 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10118 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10119 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10120 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10122 /* ELF-specific options. */
10124 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
10125 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10126 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10127 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10128 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10129 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10130 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10131 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10132 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10133 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10134 #define OPTION_32 (OPTION_ELF_BASE + 4)
10135 {"32", no_argument
, NULL
, OPTION_32
},
10136 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10137 {"n32", no_argument
, NULL
, OPTION_N32
},
10138 #define OPTION_64 (OPTION_ELF_BASE + 6)
10139 {"64", no_argument
, NULL
, OPTION_64
},
10140 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10141 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10142 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10143 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10144 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10145 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10146 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10147 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10148 #endif /* OBJ_ELF */
10150 {NULL
, no_argument
, NULL
, 0}
10152 size_t md_longopts_size
= sizeof (md_longopts
);
10154 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10155 NEW_VALUE. Warn if another value was already specified. Note:
10156 we have to defer parsing the -march and -mtune arguments in order
10157 to handle 'from-abi' correctly, since the ABI might be specified
10158 in a later argument. */
10161 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10163 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10164 as_warn (_("A different %s was already specified, is now %s"),
10165 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10168 *string_ptr
= new_value
;
10172 md_parse_option (int c
, char *arg
)
10176 case OPTION_CONSTRUCT_FLOATS
:
10177 mips_disable_float_construction
= 0;
10180 case OPTION_NO_CONSTRUCT_FLOATS
:
10181 mips_disable_float_construction
= 1;
10193 target_big_endian
= 1;
10197 target_big_endian
= 0;
10201 if (arg
&& arg
[1] == '0')
10211 mips_debug
= atoi (arg
);
10212 /* When the MIPS assembler sees -g or -g2, it does not do
10213 optimizations which limit full symbolic debugging. We take
10214 that to be equivalent to -O0. */
10215 if (mips_debug
== 2)
10220 file_mips_isa
= ISA_MIPS1
;
10224 file_mips_isa
= ISA_MIPS2
;
10228 file_mips_isa
= ISA_MIPS3
;
10232 file_mips_isa
= ISA_MIPS4
;
10236 file_mips_isa
= ISA_MIPS5
;
10239 case OPTION_MIPS32
:
10240 file_mips_isa
= ISA_MIPS32
;
10243 case OPTION_MIPS32R2
:
10244 file_mips_isa
= ISA_MIPS32R2
;
10247 case OPTION_MIPS64R2
:
10248 file_mips_isa
= ISA_MIPS64R2
;
10251 case OPTION_MIPS64
:
10252 file_mips_isa
= ISA_MIPS64
;
10256 mips_set_option_string (&mips_tune_string
, arg
);
10260 mips_set_option_string (&mips_arch_string
, arg
);
10264 mips_set_option_string (&mips_arch_string
, "4650");
10265 mips_set_option_string (&mips_tune_string
, "4650");
10268 case OPTION_NO_M4650
:
10272 mips_set_option_string (&mips_arch_string
, "4010");
10273 mips_set_option_string (&mips_tune_string
, "4010");
10276 case OPTION_NO_M4010
:
10280 mips_set_option_string (&mips_arch_string
, "4100");
10281 mips_set_option_string (&mips_tune_string
, "4100");
10284 case OPTION_NO_M4100
:
10288 mips_set_option_string (&mips_arch_string
, "3900");
10289 mips_set_option_string (&mips_tune_string
, "3900");
10292 case OPTION_NO_M3900
:
10296 mips_opts
.ase_mdmx
= 1;
10299 case OPTION_NO_MDMX
:
10300 mips_opts
.ase_mdmx
= 0;
10303 case OPTION_MIPS16
:
10304 mips_opts
.mips16
= 1;
10305 mips_no_prev_insn (FALSE
);
10308 case OPTION_NO_MIPS16
:
10309 mips_opts
.mips16
= 0;
10310 mips_no_prev_insn (FALSE
);
10313 case OPTION_MIPS3D
:
10314 mips_opts
.ase_mips3d
= 1;
10317 case OPTION_NO_MIPS3D
:
10318 mips_opts
.ase_mips3d
= 0;
10321 case OPTION_FIX_VR4120
:
10322 mips_fix_vr4120
= 1;
10325 case OPTION_NO_FIX_VR4120
:
10326 mips_fix_vr4120
= 0;
10329 case OPTION_RELAX_BRANCH
:
10330 mips_relax_branch
= 1;
10333 case OPTION_NO_RELAX_BRANCH
:
10334 mips_relax_branch
= 0;
10338 /* When generating ELF code, we permit -KPIC and -call_shared to
10339 select SVR4_PIC, and -non_shared to select no PIC. This is
10340 intended to be compatible with Irix 5. */
10341 case OPTION_CALL_SHARED
:
10342 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10344 as_bad (_("-call_shared is supported only for ELF format"));
10347 mips_pic
= SVR4_PIC
;
10348 mips_abicalls
= TRUE
;
10349 if (g_switch_seen
&& g_switch_value
!= 0)
10351 as_bad (_("-G may not be used with SVR4 PIC code"));
10354 g_switch_value
= 0;
10357 case OPTION_NON_SHARED
:
10358 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10360 as_bad (_("-non_shared is supported only for ELF format"));
10364 mips_abicalls
= FALSE
;
10367 /* The -xgot option tells the assembler to use 32 offsets when
10368 accessing the got in SVR4_PIC mode. It is for Irix
10373 #endif /* OBJ_ELF */
10376 if (mips_pic
== SVR4_PIC
)
10378 as_bad (_("-G may not be used with SVR4 PIC code"));
10382 g_switch_value
= atoi (arg
);
10387 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10390 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10392 as_bad (_("-32 is supported for ELF format only"));
10395 mips_abi
= O32_ABI
;
10399 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10401 as_bad (_("-n32 is supported for ELF format only"));
10404 mips_abi
= N32_ABI
;
10408 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10410 as_bad (_("-64 is supported for ELF format only"));
10413 mips_abi
= N64_ABI
;
10414 if (! support_64bit_objects())
10415 as_fatal (_("No compiled in support for 64 bit object file format"));
10417 #endif /* OBJ_ELF */
10420 file_mips_gp32
= 1;
10424 file_mips_gp32
= 0;
10428 file_mips_fp32
= 1;
10432 file_mips_fp32
= 0;
10437 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10439 as_bad (_("-mabi is supported for ELF format only"));
10442 if (strcmp (arg
, "32") == 0)
10443 mips_abi
= O32_ABI
;
10444 else if (strcmp (arg
, "o64") == 0)
10445 mips_abi
= O64_ABI
;
10446 else if (strcmp (arg
, "n32") == 0)
10447 mips_abi
= N32_ABI
;
10448 else if (strcmp (arg
, "64") == 0)
10450 mips_abi
= N64_ABI
;
10451 if (! support_64bit_objects())
10452 as_fatal (_("No compiled in support for 64 bit object file "
10455 else if (strcmp (arg
, "eabi") == 0)
10456 mips_abi
= EABI_ABI
;
10459 as_fatal (_("invalid abi -mabi=%s"), arg
);
10463 #endif /* OBJ_ELF */
10465 case OPTION_M7000_HILO_FIX
:
10466 mips_7000_hilo_fix
= TRUE
;
10469 case OPTION_MNO_7000_HILO_FIX
:
10470 mips_7000_hilo_fix
= FALSE
;
10474 case OPTION_MDEBUG
:
10475 mips_flag_mdebug
= TRUE
;
10478 case OPTION_NO_MDEBUG
:
10479 mips_flag_mdebug
= FALSE
;
10483 mips_flag_pdr
= TRUE
;
10486 case OPTION_NO_PDR
:
10487 mips_flag_pdr
= FALSE
;
10489 #endif /* OBJ_ELF */
10498 /* Set up globals to generate code for the ISA or processor
10499 described by INFO. */
10502 mips_set_architecture (const struct mips_cpu_info
*info
)
10506 file_mips_arch
= info
->cpu
;
10507 mips_opts
.arch
= info
->cpu
;
10508 mips_opts
.isa
= info
->isa
;
10513 /* Likewise for tuning. */
10516 mips_set_tune (const struct mips_cpu_info
*info
)
10519 mips_tune
= info
->cpu
;
10524 mips_after_parse_args (void)
10526 const struct mips_cpu_info
*arch_info
= 0;
10527 const struct mips_cpu_info
*tune_info
= 0;
10529 /* GP relative stuff not working for PE */
10530 if (strncmp (TARGET_OS
, "pe", 2) == 0
10531 && g_switch_value
!= 0)
10534 as_bad (_("-G not supported in this configuration."));
10535 g_switch_value
= 0;
10538 if (mips_abi
== NO_ABI
)
10539 mips_abi
= MIPS_DEFAULT_ABI
;
10541 /* The following code determines the architecture and register size.
10542 Similar code was added to GCC 3.3 (see override_options() in
10543 config/mips/mips.c). The GAS and GCC code should be kept in sync
10544 as much as possible. */
10546 if (mips_arch_string
!= 0)
10547 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10549 if (file_mips_isa
!= ISA_UNKNOWN
)
10551 /* Handle -mipsN. At this point, file_mips_isa contains the
10552 ISA level specified by -mipsN, while arch_info->isa contains
10553 the -march selection (if any). */
10554 if (arch_info
!= 0)
10556 /* -march takes precedence over -mipsN, since it is more descriptive.
10557 There's no harm in specifying both as long as the ISA levels
10559 if (file_mips_isa
!= arch_info
->isa
)
10560 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10561 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10562 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10565 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10568 if (arch_info
== 0)
10569 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10571 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10572 as_bad ("-march=%s is not compatible with the selected ABI",
10575 mips_set_architecture (arch_info
);
10577 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10578 if (mips_tune_string
!= 0)
10579 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10581 if (tune_info
== 0)
10582 mips_set_tune (arch_info
);
10584 mips_set_tune (tune_info
);
10586 if (file_mips_gp32
>= 0)
10588 /* The user specified the size of the integer registers. Make sure
10589 it agrees with the ABI and ISA. */
10590 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10591 as_bad (_("-mgp64 used with a 32-bit processor"));
10592 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10593 as_bad (_("-mgp32 used with a 64-bit ABI"));
10594 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10595 as_bad (_("-mgp64 used with a 32-bit ABI"));
10599 /* Infer the integer register size from the ABI and processor.
10600 Restrict ourselves to 32-bit registers if that's all the
10601 processor has, or if the ABI cannot handle 64-bit registers. */
10602 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10603 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10606 /* ??? GAS treats single-float processors as though they had 64-bit
10607 float registers (although it complains when double-precision
10608 instructions are used). As things stand, saying they have 32-bit
10609 registers would lead to spurious "register must be even" messages.
10610 So here we assume float registers are always the same size as
10611 integer ones, unless the user says otherwise. */
10612 if (file_mips_fp32
< 0)
10613 file_mips_fp32
= file_mips_gp32
;
10615 /* End of GCC-shared inference code. */
10617 /* This flag is set when we have a 64-bit capable CPU but use only
10618 32-bit wide registers. Note that EABI does not use it. */
10619 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10620 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10621 || mips_abi
== O32_ABI
))
10622 mips_32bitmode
= 1;
10624 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10625 as_bad (_("trap exception not supported at ISA 1"));
10627 /* If the selected architecture includes support for ASEs, enable
10628 generation of code for them. */
10629 if (mips_opts
.mips16
== -1)
10630 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10631 if (mips_opts
.ase_mips3d
== -1)
10632 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10633 if (mips_opts
.ase_mdmx
== -1)
10634 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10636 file_mips_isa
= mips_opts
.isa
;
10637 file_ase_mips16
= mips_opts
.mips16
;
10638 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10639 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10640 mips_opts
.gp32
= file_mips_gp32
;
10641 mips_opts
.fp32
= file_mips_fp32
;
10643 if (mips_flag_mdebug
< 0)
10645 #ifdef OBJ_MAYBE_ECOFF
10646 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10647 mips_flag_mdebug
= 1;
10649 #endif /* OBJ_MAYBE_ECOFF */
10650 mips_flag_mdebug
= 0;
10655 mips_init_after_args (void)
10657 /* initialize opcodes */
10658 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10659 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10663 md_pcrel_from (fixS
*fixP
)
10665 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10666 switch (fixP
->fx_r_type
)
10668 case BFD_RELOC_16_PCREL_S2
:
10669 case BFD_RELOC_MIPS_JMP
:
10670 /* Return the address of the delay slot. */
10677 /* This is called before the symbol table is processed. In order to
10678 work with gcc when using mips-tfile, we must keep all local labels.
10679 However, in other cases, we want to discard them. If we were
10680 called with -g, but we didn't see any debugging information, it may
10681 mean that gcc is smuggling debugging information through to
10682 mips-tfile, in which case we must generate all local labels. */
10685 mips_frob_file_before_adjust (void)
10687 #ifndef NO_ECOFF_DEBUGGING
10688 if (ECOFF_DEBUGGING
10690 && ! ecoff_debugging_seen
)
10691 flag_keep_locals
= 1;
10695 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10696 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10697 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10698 relocation operators.
10700 For our purposes, a %lo() expression matches a %got() or %hi()
10703 (a) it refers to the same symbol; and
10704 (b) the offset applied in the %lo() expression is no lower than
10705 the offset applied in the %got() or %hi().
10707 (b) allows us to cope with code like:
10710 lh $4,%lo(foo+2)($4)
10712 ...which is legal on RELA targets, and has a well-defined behaviour
10713 if the user knows that adding 2 to "foo" will not induce a carry to
10716 When several %lo()s match a particular %got() or %hi(), we use the
10717 following rules to distinguish them:
10719 (1) %lo()s with smaller offsets are a better match than %lo()s with
10722 (2) %lo()s with no matching %got() or %hi() are better than those
10723 that already have a matching %got() or %hi().
10725 (3) later %lo()s are better than earlier %lo()s.
10727 These rules are applied in order.
10729 (1) means, among other things, that %lo()s with identical offsets are
10730 chosen if they exist.
10732 (2) means that we won't associate several high-part relocations with
10733 the same low-part relocation unless there's no alternative. Having
10734 several high parts for the same low part is a GNU extension; this rule
10735 allows careful users to avoid it.
10737 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10738 with the last high-part relocation being at the front of the list.
10739 It therefore makes sense to choose the last matching low-part
10740 relocation, all other things being equal. It's also easier
10741 to code that way. */
10744 mips_frob_file (void)
10746 struct mips_hi_fixup
*l
;
10748 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10750 segment_info_type
*seginfo
;
10751 bfd_boolean matched_lo_p
;
10752 fixS
**hi_pos
, **lo_pos
, **pos
;
10754 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10756 /* If a GOT16 relocation turns out to be against a global symbol,
10757 there isn't supposed to be a matching LO. */
10758 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10759 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10762 /* Check quickly whether the next fixup happens to be a matching %lo. */
10763 if (fixup_has_matching_lo_p (l
->fixp
))
10766 seginfo
= seg_info (l
->seg
);
10768 /* Set HI_POS to the position of this relocation in the chain.
10769 Set LO_POS to the position of the chosen low-part relocation.
10770 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10771 relocation that matches an immediately-preceding high-part
10775 matched_lo_p
= FALSE
;
10776 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10778 if (*pos
== l
->fixp
)
10781 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10782 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10783 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10785 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10787 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10790 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10791 && fixup_has_matching_lo_p (*pos
));
10794 /* If we found a match, remove the high-part relocation from its
10795 current position and insert it before the low-part relocation.
10796 Make the offsets match so that fixup_has_matching_lo_p()
10799 We don't warn about unmatched high-part relocations since some
10800 versions of gcc have been known to emit dead "lui ...%hi(...)"
10802 if (lo_pos
!= NULL
)
10804 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10805 if (l
->fixp
->fx_next
!= *lo_pos
)
10807 *hi_pos
= l
->fixp
->fx_next
;
10808 l
->fixp
->fx_next
= *lo_pos
;
10815 /* We may have combined relocations without symbols in the N32/N64 ABI.
10816 We have to prevent gas from dropping them. */
10819 mips_force_relocation (fixS
*fixp
)
10821 if (generic_force_reloc (fixp
))
10825 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10826 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10827 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10828 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10834 /* This hook is called before a fix is simplified. We don't really
10835 decide whether to skip a fix here. Rather, we turn global symbols
10836 used as branch targets into local symbols, such that they undergo
10837 simplification. We can only do this if the symbol is defined and
10838 it is in the same section as the branch. If this doesn't hold, we
10839 emit a better error message than just saying the relocation is not
10840 valid for the selected object format.
10842 FIXP is the fix-up we're going to try to simplify, SEG is the
10843 segment in which the fix up occurs. The return value should be
10844 non-zero to indicate the fix-up is valid for further
10845 simplifications. */
10848 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10850 /* There's a lot of discussion on whether it should be possible to
10851 use R_MIPS_PC16 to represent branch relocations. The outcome
10852 seems to be that it can, but gas/bfd are very broken in creating
10853 RELA relocations for this, so for now we only accept branches to
10854 symbols in the same section. Anything else is of dubious value,
10855 since there's no guarantee that at link time the symbol would be
10856 in range. Even for branches to local symbols this is arguably
10857 wrong, since it we assume the symbol is not going to be
10858 overridden, which should be possible per ELF library semantics,
10859 but then, there isn't a dynamic relocation that could be used to
10860 this effect, and the target would likely be out of range as well.
10862 Unfortunately, it seems that there is too much code out there
10863 that relies on branches to symbols that are global to be resolved
10864 as if they were local, like the IRIX tools do, so we do it as
10865 well, but with a warning so that people are reminded to fix their
10866 code. If we ever get back to using R_MIPS_PC16 for branch
10867 targets, this entire block should go away (and probably the
10868 whole function). */
10870 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10871 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10872 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10873 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10876 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10878 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10879 _("Cannot branch to undefined symbol."));
10880 /* Avoid any further errors about this fixup. */
10883 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10886 _("Cannot branch to symbol in another section."));
10889 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10891 symbolS
*sym
= fixP
->fx_addsy
;
10893 if (mips_pic
== SVR4_PIC
)
10894 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10895 _("Pretending global symbol used as branch target is local."));
10897 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10898 S_GET_SEGMENT (sym
),
10900 symbol_get_frag (sym
));
10901 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10902 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10903 assert (symbol_resolved_p (sym
));
10904 symbol_mark_resolved (fixP
->fx_addsy
);
10911 /* Apply a fixup to the object file. */
10914 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10918 reloc_howto_type
*howto
;
10920 /* We ignore generic BFD relocations we don't know about. */
10921 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10925 assert (fixP
->fx_size
== 4
10926 || fixP
->fx_r_type
== BFD_RELOC_16
10927 || fixP
->fx_r_type
== BFD_RELOC_64
10928 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10929 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10930 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10931 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10933 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10935 assert (! fixP
->fx_pcrel
);
10937 /* Don't treat parts of a composite relocation as done. There are two
10940 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10941 should nevertheless be emitted if the first part is.
10943 (2) In normal usage, composite relocations are never assembly-time
10944 constants. The easiest way of dealing with the pathological
10945 exceptions is to generate a relocation against STN_UNDEF and
10946 leave everything up to the linker. */
10947 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10950 switch (fixP
->fx_r_type
)
10952 case BFD_RELOC_MIPS_JMP
:
10953 case BFD_RELOC_MIPS_SHIFT5
:
10954 case BFD_RELOC_MIPS_SHIFT6
:
10955 case BFD_RELOC_MIPS_GOT_DISP
:
10956 case BFD_RELOC_MIPS_GOT_PAGE
:
10957 case BFD_RELOC_MIPS_GOT_OFST
:
10958 case BFD_RELOC_MIPS_SUB
:
10959 case BFD_RELOC_MIPS_INSERT_A
:
10960 case BFD_RELOC_MIPS_INSERT_B
:
10961 case BFD_RELOC_MIPS_DELETE
:
10962 case BFD_RELOC_MIPS_HIGHEST
:
10963 case BFD_RELOC_MIPS_HIGHER
:
10964 case BFD_RELOC_MIPS_SCN_DISP
:
10965 case BFD_RELOC_MIPS_REL16
:
10966 case BFD_RELOC_MIPS_RELGOT
:
10967 case BFD_RELOC_MIPS_JALR
:
10968 case BFD_RELOC_HI16
:
10969 case BFD_RELOC_HI16_S
:
10970 case BFD_RELOC_GPREL16
:
10971 case BFD_RELOC_MIPS_LITERAL
:
10972 case BFD_RELOC_MIPS_CALL16
:
10973 case BFD_RELOC_MIPS_GOT16
:
10974 case BFD_RELOC_GPREL32
:
10975 case BFD_RELOC_MIPS_GOT_HI16
:
10976 case BFD_RELOC_MIPS_GOT_LO16
:
10977 case BFD_RELOC_MIPS_CALL_HI16
:
10978 case BFD_RELOC_MIPS_CALL_LO16
:
10979 case BFD_RELOC_MIPS16_GPREL
:
10980 assert (! fixP
->fx_pcrel
);
10981 /* Nothing needed to do. The value comes from the reloc entry */
10984 case BFD_RELOC_MIPS16_JMP
:
10985 /* We currently always generate a reloc against a symbol, which
10986 means that we don't want an addend even if the symbol is
10992 /* This is handled like BFD_RELOC_32, but we output a sign
10993 extended value if we are only 32 bits. */
10996 if (8 <= sizeof (valueT
))
10997 md_number_to_chars (buf
, *valP
, 8);
11002 if ((*valP
& 0x80000000) != 0)
11006 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11008 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11014 case BFD_RELOC_RVA
:
11016 /* If we are deleting this reloc entry, we must fill in the
11017 value now. This can happen if we have a .word which is not
11018 resolved when it appears but is later defined. */
11020 md_number_to_chars (buf
, *valP
, 4);
11024 /* If we are deleting this reloc entry, we must fill in the
11027 md_number_to_chars (buf
, *valP
, 2);
11030 case BFD_RELOC_LO16
:
11031 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11032 may be safe to remove, but if so it's not obvious. */
11033 /* When handling an embedded PIC switch statement, we can wind
11034 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11037 if (*valP
+ 0x8000 > 0xffff)
11038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11039 _("relocation overflow"));
11040 if (target_big_endian
)
11042 md_number_to_chars (buf
, *valP
, 2);
11046 case BFD_RELOC_16_PCREL_S2
:
11047 if ((*valP
& 0x3) != 0)
11048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11049 _("Branch to odd address (%lx)"), (long) *valP
);
11052 * We need to save the bits in the instruction since fixup_segment()
11053 * might be deleting the relocation entry (i.e., a branch within
11054 * the current segment).
11056 if (! fixP
->fx_done
)
11059 /* update old instruction data */
11060 if (target_big_endian
)
11061 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11063 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11065 if (*valP
+ 0x20000 <= 0x3ffff)
11067 insn
|= (*valP
>> 2) & 0xffff;
11068 md_number_to_chars (buf
, insn
, 4);
11070 else if (mips_pic
== NO_PIC
11072 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11073 && (fixP
->fx_frag
->fr_address
11074 < text_section
->vma
+ bfd_get_section_size (text_section
))
11075 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11076 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11077 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11079 /* The branch offset is too large. If this is an
11080 unconditional branch, and we are not generating PIC code,
11081 we can convert it to an absolute jump instruction. */
11082 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11083 insn
= 0x0c000000; /* jal */
11085 insn
= 0x08000000; /* j */
11086 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11088 fixP
->fx_addsy
= section_symbol (text_section
);
11089 *valP
+= md_pcrel_from (fixP
);
11090 md_number_to_chars (buf
, insn
, 4);
11094 /* If we got here, we have branch-relaxation disabled,
11095 and there's nothing we can do to fix this instruction
11096 without turning it into a longer sequence. */
11097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11098 _("Branch out of range"));
11102 case BFD_RELOC_VTABLE_INHERIT
:
11105 && !S_IS_DEFINED (fixP
->fx_addsy
)
11106 && !S_IS_WEAK (fixP
->fx_addsy
))
11107 S_SET_WEAK (fixP
->fx_addsy
);
11110 case BFD_RELOC_VTABLE_ENTRY
:
11118 /* Remember value for tc_gen_reloc. */
11119 fixP
->fx_addnumber
= *valP
;
11124 printInsn (unsigned long oc
)
11126 const struct mips_opcode
*p
;
11127 int treg
, sreg
, dreg
, shamt
;
11132 for (i
= 0; i
< NUMOPCODES
; ++i
)
11134 p
= &mips_opcodes
[i
];
11135 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11137 printf ("%08lx %s\t", oc
, p
->name
);
11138 treg
= (oc
>> 16) & 0x1f;
11139 sreg
= (oc
>> 21) & 0x1f;
11140 dreg
= (oc
>> 11) & 0x1f;
11141 shamt
= (oc
>> 6) & 0x1f;
11143 for (args
= p
->args
;; ++args
)
11154 printf ("%c", *args
);
11158 assert (treg
== sreg
);
11159 printf ("$%d,$%d", treg
, sreg
);
11164 printf ("$%d", dreg
);
11169 printf ("$%d", treg
);
11173 printf ("0x%x", treg
);
11178 printf ("$%d", sreg
);
11182 printf ("0x%08lx", oc
& 0x1ffffff);
11189 printf ("%d", imm
);
11194 printf ("$%d", shamt
);
11205 printf (_("%08lx UNDEFINED\n"), oc
);
11216 name
= input_line_pointer
;
11217 c
= get_symbol_end ();
11218 p
= (symbolS
*) symbol_find_or_make (name
);
11219 *input_line_pointer
= c
;
11223 /* Align the current frag to a given power of two. The MIPS assembler
11224 also automatically adjusts any preceding label. */
11227 mips_align (int to
, int fill
, symbolS
*label
)
11229 mips_emit_delays (FALSE
);
11230 frag_align (to
, fill
, 0);
11231 record_alignment (now_seg
, to
);
11234 assert (S_GET_SEGMENT (label
) == now_seg
);
11235 symbol_set_frag (label
, frag_now
);
11236 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11240 /* Align to a given power of two. .align 0 turns off the automatic
11241 alignment used by the data creating pseudo-ops. */
11244 s_align (int x ATTRIBUTE_UNUSED
)
11247 register long temp_fill
;
11248 long max_alignment
= 15;
11252 o Note that the assembler pulls down any immediately preceding label
11253 to the aligned address.
11254 o It's not documented but auto alignment is reinstated by
11255 a .align pseudo instruction.
11256 o Note also that after auto alignment is turned off the mips assembler
11257 issues an error on attempt to assemble an improperly aligned data item.
11262 temp
= get_absolute_expression ();
11263 if (temp
> max_alignment
)
11264 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11267 as_warn (_("Alignment negative: 0 assumed."));
11270 if (*input_line_pointer
== ',')
11272 ++input_line_pointer
;
11273 temp_fill
= get_absolute_expression ();
11280 mips_align (temp
, (int) temp_fill
,
11281 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11288 demand_empty_rest_of_line ();
11292 mips_flush_pending_output (void)
11294 mips_emit_delays (FALSE
);
11295 mips_clear_insn_labels ();
11299 s_change_sec (int sec
)
11304 /* The ELF backend needs to know that we are changing sections, so
11305 that .previous works correctly. We could do something like check
11306 for an obj_section_change_hook macro, but that might be confusing
11307 as it would not be appropriate to use it in the section changing
11308 functions in read.c, since obj-elf.c intercepts those. FIXME:
11309 This should be cleaner, somehow. */
11310 obj_elf_section_change_hook ();
11313 mips_emit_delays (FALSE
);
11323 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11324 demand_empty_rest_of_line ();
11328 seg
= subseg_new (RDATA_SECTION_NAME
,
11329 (subsegT
) get_absolute_expression ());
11330 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11332 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11333 | SEC_READONLY
| SEC_RELOC
11335 if (strcmp (TARGET_OS
, "elf") != 0)
11336 record_alignment (seg
, 4);
11338 demand_empty_rest_of_line ();
11342 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11343 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11345 bfd_set_section_flags (stdoutput
, seg
,
11346 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11347 if (strcmp (TARGET_OS
, "elf") != 0)
11348 record_alignment (seg
, 4);
11350 demand_empty_rest_of_line ();
11358 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11361 char *section_name
;
11366 int section_entry_size
;
11367 int section_alignment
;
11369 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11372 section_name
= input_line_pointer
;
11373 c
= get_symbol_end ();
11375 next_c
= *(input_line_pointer
+ 1);
11377 /* Do we have .section Name<,"flags">? */
11378 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11380 /* just after name is now '\0'. */
11381 *input_line_pointer
= c
;
11382 input_line_pointer
= section_name
;
11383 obj_elf_section (ignore
);
11386 input_line_pointer
++;
11388 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11390 section_type
= get_absolute_expression ();
11393 if (*input_line_pointer
++ == ',')
11394 section_flag
= get_absolute_expression ();
11397 if (*input_line_pointer
++ == ',')
11398 section_entry_size
= get_absolute_expression ();
11400 section_entry_size
= 0;
11401 if (*input_line_pointer
++ == ',')
11402 section_alignment
= get_absolute_expression ();
11404 section_alignment
= 0;
11406 section_name
= xstrdup (section_name
);
11408 /* When using the generic form of .section (as implemented by obj-elf.c),
11409 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11410 traditionally had to fall back on the more common @progbits instead.
11412 There's nothing really harmful in this, since bfd will correct
11413 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11414 means that, for backwards compatibiltiy, the special_section entries
11415 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11417 Even so, we shouldn't force users of the MIPS .section syntax to
11418 incorrectly label the sections as SHT_PROGBITS. The best compromise
11419 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11420 generic type-checking code. */
11421 if (section_type
== SHT_MIPS_DWARF
)
11422 section_type
= SHT_PROGBITS
;
11424 obj_elf_change_section (section_name
, section_type
, section_flag
,
11425 section_entry_size
, 0, 0, 0);
11427 if (now_seg
->name
!= section_name
)
11428 free (section_name
);
11429 #endif /* OBJ_ELF */
11433 mips_enable_auto_align (void)
11439 s_cons (int log_size
)
11443 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11444 mips_emit_delays (FALSE
);
11445 if (log_size
> 0 && auto_align
)
11446 mips_align (log_size
, 0, label
);
11447 mips_clear_insn_labels ();
11448 cons (1 << log_size
);
11452 s_float_cons (int type
)
11456 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11458 mips_emit_delays (FALSE
);
11463 mips_align (3, 0, label
);
11465 mips_align (2, 0, label
);
11468 mips_clear_insn_labels ();
11473 /* Handle .globl. We need to override it because on Irix 5 you are
11476 where foo is an undefined symbol, to mean that foo should be
11477 considered to be the address of a function. */
11480 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11487 name
= input_line_pointer
;
11488 c
= get_symbol_end ();
11489 symbolP
= symbol_find_or_make (name
);
11490 *input_line_pointer
= c
;
11491 SKIP_WHITESPACE ();
11493 /* On Irix 5, every global symbol that is not explicitly labelled as
11494 being a function is apparently labelled as being an object. */
11497 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11502 secname
= input_line_pointer
;
11503 c
= get_symbol_end ();
11504 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11506 as_bad (_("%s: no such section"), secname
);
11507 *input_line_pointer
= c
;
11509 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11510 flag
= BSF_FUNCTION
;
11513 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11515 S_SET_EXTERNAL (symbolP
);
11516 demand_empty_rest_of_line ();
11520 s_option (int x ATTRIBUTE_UNUSED
)
11525 opt
= input_line_pointer
;
11526 c
= get_symbol_end ();
11530 /* FIXME: What does this mean? */
11532 else if (strncmp (opt
, "pic", 3) == 0)
11536 i
= atoi (opt
+ 3);
11541 mips_pic
= SVR4_PIC
;
11542 mips_abicalls
= TRUE
;
11545 as_bad (_(".option pic%d not supported"), i
);
11547 if (mips_pic
== SVR4_PIC
)
11549 if (g_switch_seen
&& g_switch_value
!= 0)
11550 as_warn (_("-G may not be used with SVR4 PIC code"));
11551 g_switch_value
= 0;
11552 bfd_set_gp_size (stdoutput
, 0);
11556 as_warn (_("Unrecognized option \"%s\""), opt
);
11558 *input_line_pointer
= c
;
11559 demand_empty_rest_of_line ();
11562 /* This structure is used to hold a stack of .set values. */
11564 struct mips_option_stack
11566 struct mips_option_stack
*next
;
11567 struct mips_set_options options
;
11570 static struct mips_option_stack
*mips_opts_stack
;
11572 /* Handle the .set pseudo-op. */
11575 s_mipsset (int x ATTRIBUTE_UNUSED
)
11577 char *name
= input_line_pointer
, ch
;
11579 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11580 ++input_line_pointer
;
11581 ch
= *input_line_pointer
;
11582 *input_line_pointer
= '\0';
11584 if (strcmp (name
, "reorder") == 0)
11586 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11588 /* If we still have pending nops, we can discard them. The
11589 usual nop handling will insert any that are still
11591 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11592 * (mips_opts
.mips16
? 2 : 4));
11593 prev_nop_frag
= NULL
;
11595 mips_opts
.noreorder
= 0;
11597 else if (strcmp (name
, "noreorder") == 0)
11599 mips_emit_delays (TRUE
);
11600 mips_opts
.noreorder
= 1;
11601 mips_any_noreorder
= 1;
11603 else if (strcmp (name
, "at") == 0)
11605 mips_opts
.noat
= 0;
11607 else if (strcmp (name
, "noat") == 0)
11609 mips_opts
.noat
= 1;
11611 else if (strcmp (name
, "macro") == 0)
11613 mips_opts
.warn_about_macros
= 0;
11615 else if (strcmp (name
, "nomacro") == 0)
11617 if (mips_opts
.noreorder
== 0)
11618 as_bad (_("`noreorder' must be set before `nomacro'"));
11619 mips_opts
.warn_about_macros
= 1;
11621 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11623 mips_opts
.nomove
= 0;
11625 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11627 mips_opts
.nomove
= 1;
11629 else if (strcmp (name
, "bopt") == 0)
11631 mips_opts
.nobopt
= 0;
11633 else if (strcmp (name
, "nobopt") == 0)
11635 mips_opts
.nobopt
= 1;
11637 else if (strcmp (name
, "mips16") == 0
11638 || strcmp (name
, "MIPS-16") == 0)
11639 mips_opts
.mips16
= 1;
11640 else if (strcmp (name
, "nomips16") == 0
11641 || strcmp (name
, "noMIPS-16") == 0)
11642 mips_opts
.mips16
= 0;
11643 else if (strcmp (name
, "mips3d") == 0)
11644 mips_opts
.ase_mips3d
= 1;
11645 else if (strcmp (name
, "nomips3d") == 0)
11646 mips_opts
.ase_mips3d
= 0;
11647 else if (strcmp (name
, "mdmx") == 0)
11648 mips_opts
.ase_mdmx
= 1;
11649 else if (strcmp (name
, "nomdmx") == 0)
11650 mips_opts
.ase_mdmx
= 0;
11651 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11655 /* Permit the user to change the ISA and architecture on the fly.
11656 Needless to say, misuse can cause serious problems. */
11657 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11660 mips_opts
.isa
= file_mips_isa
;
11661 mips_opts
.arch
= file_mips_arch
;
11663 else if (strncmp (name
, "arch=", 5) == 0)
11665 const struct mips_cpu_info
*p
;
11667 p
= mips_parse_cpu("internal use", name
+ 5);
11669 as_bad (_("unknown architecture %s"), name
+ 5);
11672 mips_opts
.arch
= p
->cpu
;
11673 mips_opts
.isa
= p
->isa
;
11676 else if (strncmp (name
, "mips", 4) == 0)
11678 const struct mips_cpu_info
*p
;
11680 p
= mips_parse_cpu("internal use", name
);
11682 as_bad (_("unknown ISA level %s"), name
+ 4);
11685 mips_opts
.arch
= p
->cpu
;
11686 mips_opts
.isa
= p
->isa
;
11690 as_bad (_("unknown ISA or architecture %s"), name
);
11692 switch (mips_opts
.isa
)
11700 mips_opts
.gp32
= 1;
11701 mips_opts
.fp32
= 1;
11708 mips_opts
.gp32
= 0;
11709 mips_opts
.fp32
= 0;
11712 as_bad (_("unknown ISA level %s"), name
+ 4);
11717 mips_opts
.gp32
= file_mips_gp32
;
11718 mips_opts
.fp32
= file_mips_fp32
;
11721 else if (strcmp (name
, "autoextend") == 0)
11722 mips_opts
.noautoextend
= 0;
11723 else if (strcmp (name
, "noautoextend") == 0)
11724 mips_opts
.noautoextend
= 1;
11725 else if (strcmp (name
, "push") == 0)
11727 struct mips_option_stack
*s
;
11729 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11730 s
->next
= mips_opts_stack
;
11731 s
->options
= mips_opts
;
11732 mips_opts_stack
= s
;
11734 else if (strcmp (name
, "pop") == 0)
11736 struct mips_option_stack
*s
;
11738 s
= mips_opts_stack
;
11740 as_bad (_(".set pop with no .set push"));
11743 /* If we're changing the reorder mode we need to handle
11744 delay slots correctly. */
11745 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11746 mips_emit_delays (TRUE
);
11747 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11749 if (prev_nop_frag
!= NULL
)
11751 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11752 * (mips_opts
.mips16
? 2 : 4));
11753 prev_nop_frag
= NULL
;
11757 mips_opts
= s
->options
;
11758 mips_opts_stack
= s
->next
;
11764 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11766 *input_line_pointer
= ch
;
11767 demand_empty_rest_of_line ();
11770 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11771 .option pic2. It means to generate SVR4 PIC calls. */
11774 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11776 mips_pic
= SVR4_PIC
;
11777 mips_abicalls
= TRUE
;
11779 if (g_switch_seen
&& g_switch_value
!= 0)
11780 as_warn (_("-G may not be used with SVR4 PIC code"));
11781 g_switch_value
= 0;
11783 bfd_set_gp_size (stdoutput
, 0);
11784 demand_empty_rest_of_line ();
11787 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11788 PIC code. It sets the $gp register for the function based on the
11789 function address, which is in the register named in the argument.
11790 This uses a relocation against _gp_disp, which is handled specially
11791 by the linker. The result is:
11792 lui $gp,%hi(_gp_disp)
11793 addiu $gp,$gp,%lo(_gp_disp)
11794 addu $gp,$gp,.cpload argument
11795 The .cpload argument is normally $25 == $t9. */
11798 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11802 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11803 .cpload is ignored. */
11804 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11810 /* .cpload should be in a .set noreorder section. */
11811 if (mips_opts
.noreorder
== 0)
11812 as_warn (_(".cpload not in noreorder section"));
11814 ex
.X_op
= O_symbol
;
11815 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11816 ex
.X_op_symbol
= NULL
;
11817 ex
.X_add_number
= 0;
11819 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11820 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11823 macro_build_lui (&ex
, mips_gp_register
);
11824 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11825 mips_gp_register
, BFD_RELOC_LO16
);
11826 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11827 mips_gp_register
, tc_get_register (0));
11830 demand_empty_rest_of_line ();
11833 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11834 .cpsetup $reg1, offset|$reg2, label
11836 If offset is given, this results in:
11837 sd $gp, offset($sp)
11838 lui $gp, %hi(%neg(%gp_rel(label)))
11839 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11840 daddu $gp, $gp, $reg1
11842 If $reg2 is given, this results in:
11843 daddu $reg2, $gp, $0
11844 lui $gp, %hi(%neg(%gp_rel(label)))
11845 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11846 daddu $gp, $gp, $reg1
11847 $reg1 is normally $25 == $t9. */
11849 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11851 expressionS ex_off
;
11852 expressionS ex_sym
;
11855 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11856 We also need NewABI support. */
11857 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11863 reg1
= tc_get_register (0);
11864 SKIP_WHITESPACE ();
11865 if (*input_line_pointer
!= ',')
11867 as_bad (_("missing argument separator ',' for .cpsetup"));
11871 ++input_line_pointer
;
11872 SKIP_WHITESPACE ();
11873 if (*input_line_pointer
== '$')
11875 mips_cpreturn_register
= tc_get_register (0);
11876 mips_cpreturn_offset
= -1;
11880 mips_cpreturn_offset
= get_absolute_expression ();
11881 mips_cpreturn_register
= -1;
11883 SKIP_WHITESPACE ();
11884 if (*input_line_pointer
!= ',')
11886 as_bad (_("missing argument separator ',' for .cpsetup"));
11890 ++input_line_pointer
;
11891 SKIP_WHITESPACE ();
11892 expression (&ex_sym
);
11895 if (mips_cpreturn_register
== -1)
11897 ex_off
.X_op
= O_constant
;
11898 ex_off
.X_add_symbol
= NULL
;
11899 ex_off
.X_op_symbol
= NULL
;
11900 ex_off
.X_add_number
= mips_cpreturn_offset
;
11902 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11903 BFD_RELOC_LO16
, SP
);
11906 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11907 mips_gp_register
, 0);
11909 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11910 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
, BFD_RELOC_HI16_S
);
11912 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11913 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11914 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11916 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11917 mips_gp_register
, reg1
);
11920 demand_empty_rest_of_line ();
11924 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11926 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11927 .cplocal is ignored. */
11928 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11934 mips_gp_register
= tc_get_register (0);
11935 demand_empty_rest_of_line ();
11938 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11939 offset from $sp. The offset is remembered, and after making a PIC
11940 call $gp is restored from that location. */
11943 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11947 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11948 .cprestore is ignored. */
11949 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11955 mips_cprestore_offset
= get_absolute_expression ();
11956 mips_cprestore_valid
= 1;
11958 ex
.X_op
= O_constant
;
11959 ex
.X_add_symbol
= NULL
;
11960 ex
.X_op_symbol
= NULL
;
11961 ex
.X_add_number
= mips_cprestore_offset
;
11964 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11965 SP
, HAVE_64BIT_ADDRESSES
);
11968 demand_empty_rest_of_line ();
11971 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11972 was given in the preceding .cpsetup, it results in:
11973 ld $gp, offset($sp)
11975 If a register $reg2 was given there, it results in:
11976 daddu $gp, $reg2, $0
11979 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11983 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11984 We also need NewABI support. */
11985 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11992 if (mips_cpreturn_register
== -1)
11994 ex
.X_op
= O_constant
;
11995 ex
.X_add_symbol
= NULL
;
11996 ex
.X_op_symbol
= NULL
;
11997 ex
.X_add_number
= mips_cpreturn_offset
;
11999 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12002 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12003 mips_cpreturn_register
, 0);
12006 demand_empty_rest_of_line ();
12009 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12010 code. It sets the offset to use in gp_rel relocations. */
12013 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12015 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12016 We also need NewABI support. */
12017 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12023 mips_gprel_offset
= get_absolute_expression ();
12025 demand_empty_rest_of_line ();
12028 /* Handle the .gpword pseudo-op. This is used when generating PIC
12029 code. It generates a 32 bit GP relative reloc. */
12032 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12038 /* When not generating PIC code, this is treated as .word. */
12039 if (mips_pic
!= SVR4_PIC
)
12045 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12046 mips_emit_delays (TRUE
);
12048 mips_align (2, 0, label
);
12049 mips_clear_insn_labels ();
12053 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12055 as_bad (_("Unsupported use of .gpword"));
12056 ignore_rest_of_line ();
12060 md_number_to_chars (p
, 0, 4);
12061 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12062 BFD_RELOC_GPREL32
);
12064 demand_empty_rest_of_line ();
12068 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12074 /* When not generating PIC code, this is treated as .dword. */
12075 if (mips_pic
!= SVR4_PIC
)
12081 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12082 mips_emit_delays (TRUE
);
12084 mips_align (3, 0, label
);
12085 mips_clear_insn_labels ();
12089 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12091 as_bad (_("Unsupported use of .gpdword"));
12092 ignore_rest_of_line ();
12096 md_number_to_chars (p
, 0, 8);
12097 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12098 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12100 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12101 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12102 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12104 demand_empty_rest_of_line ();
12107 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12108 tables in SVR4 PIC code. */
12111 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12115 /* This is ignored when not generating SVR4 PIC code. */
12116 if (mips_pic
!= SVR4_PIC
)
12122 /* Add $gp to the register named as an argument. */
12124 reg
= tc_get_register (0);
12125 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12128 demand_empty_rest_of_line ();
12131 /* Handle the .insn pseudo-op. This marks instruction labels in
12132 mips16 mode. This permits the linker to handle them specially,
12133 such as generating jalx instructions when needed. We also make
12134 them odd for the duration of the assembly, in order to generate the
12135 right sort of code. We will make them even in the adjust_symtab
12136 routine, while leaving them marked. This is convenient for the
12137 debugger and the disassembler. The linker knows to make them odd
12141 s_insn (int ignore ATTRIBUTE_UNUSED
)
12143 mips16_mark_labels ();
12145 demand_empty_rest_of_line ();
12148 /* Handle a .stabn directive. We need these in order to mark a label
12149 as being a mips16 text label correctly. Sometimes the compiler
12150 will emit a label, followed by a .stabn, and then switch sections.
12151 If the label and .stabn are in mips16 mode, then the label is
12152 really a mips16 text label. */
12155 s_mips_stab (int type
)
12158 mips16_mark_labels ();
12163 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12167 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12174 name
= input_line_pointer
;
12175 c
= get_symbol_end ();
12176 symbolP
= symbol_find_or_make (name
);
12177 S_SET_WEAK (symbolP
);
12178 *input_line_pointer
= c
;
12180 SKIP_WHITESPACE ();
12182 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12184 if (S_IS_DEFINED (symbolP
))
12186 as_bad ("ignoring attempt to redefine symbol %s",
12187 S_GET_NAME (symbolP
));
12188 ignore_rest_of_line ();
12192 if (*input_line_pointer
== ',')
12194 ++input_line_pointer
;
12195 SKIP_WHITESPACE ();
12199 if (exp
.X_op
!= O_symbol
)
12201 as_bad ("bad .weakext directive");
12202 ignore_rest_of_line ();
12205 symbol_set_value_expression (symbolP
, &exp
);
12208 demand_empty_rest_of_line ();
12211 /* Parse a register string into a number. Called from the ECOFF code
12212 to parse .frame. The argument is non-zero if this is the frame
12213 register, so that we can record it in mips_frame_reg. */
12216 tc_get_register (int frame
)
12220 SKIP_WHITESPACE ();
12221 if (*input_line_pointer
++ != '$')
12223 as_warn (_("expected `$'"));
12226 else if (ISDIGIT (*input_line_pointer
))
12228 reg
= get_absolute_expression ();
12229 if (reg
< 0 || reg
>= 32)
12231 as_warn (_("Bad register number"));
12237 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12240 input_line_pointer
+= 2;
12242 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12245 input_line_pointer
+= 2;
12247 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12250 input_line_pointer
+= 2;
12252 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12255 input_line_pointer
+= 2;
12257 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12260 input_line_pointer
+= 2;
12262 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12265 input_line_pointer
+= 3;
12267 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12270 input_line_pointer
+= 3;
12272 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12275 input_line_pointer
+= 4;
12279 as_warn (_("Unrecognized register name"));
12281 while (ISALNUM(*input_line_pointer
))
12282 input_line_pointer
++;
12287 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12288 mips_frame_reg_valid
= 1;
12289 mips_cprestore_valid
= 0;
12295 md_section_align (asection
*seg
, valueT addr
)
12297 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12300 /* We don't need to align ELF sections to the full alignment.
12301 However, Irix 5 may prefer that we align them at least to a 16
12302 byte boundary. We don't bother to align the sections if we are
12303 targeted for an embedded system. */
12304 if (strcmp (TARGET_OS
, "elf") == 0)
12310 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12313 /* Utility routine, called from above as well. If called while the
12314 input file is still being read, it's only an approximation. (For
12315 example, a symbol may later become defined which appeared to be
12316 undefined earlier.) */
12319 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12324 if (g_switch_value
> 0)
12326 const char *symname
;
12329 /* Find out whether this symbol can be referenced off the $gp
12330 register. It can be if it is smaller than the -G size or if
12331 it is in the .sdata or .sbss section. Certain symbols can
12332 not be referenced off the $gp, although it appears as though
12334 symname
= S_GET_NAME (sym
);
12335 if (symname
!= (const char *) NULL
12336 && (strcmp (symname
, "eprol") == 0
12337 || strcmp (symname
, "etext") == 0
12338 || strcmp (symname
, "_gp") == 0
12339 || strcmp (symname
, "edata") == 0
12340 || strcmp (symname
, "_fbss") == 0
12341 || strcmp (symname
, "_fdata") == 0
12342 || strcmp (symname
, "_ftext") == 0
12343 || strcmp (symname
, "end") == 0
12344 || strcmp (symname
, "_gp_disp") == 0))
12346 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12348 #ifndef NO_ECOFF_DEBUGGING
12349 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12350 && (symbol_get_obj (sym
)->ecoff_extern_size
12351 <= g_switch_value
))
12353 /* We must defer this decision until after the whole
12354 file has been read, since there might be a .extern
12355 after the first use of this symbol. */
12356 || (before_relaxing
12357 #ifndef NO_ECOFF_DEBUGGING
12358 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12360 && S_GET_VALUE (sym
) == 0)
12361 || (S_GET_VALUE (sym
) != 0
12362 && S_GET_VALUE (sym
) <= g_switch_value
)))
12366 const char *segname
;
12368 segname
= segment_name (S_GET_SEGMENT (sym
));
12369 assert (strcmp (segname
, ".lit8") != 0
12370 && strcmp (segname
, ".lit4") != 0);
12371 change
= (strcmp (segname
, ".sdata") != 0
12372 && strcmp (segname
, ".sbss") != 0
12373 && strncmp (segname
, ".sdata.", 7) != 0
12374 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12379 /* We are not optimizing for the $gp register. */
12384 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12387 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12390 bfd_boolean linkonce
;
12392 /* Handle the case of a symbol equated to another symbol. */
12393 while (symbol_equated_reloc_p (sym
))
12397 /* It's possible to get a loop here in a badly written
12399 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12405 symsec
= S_GET_SEGMENT (sym
);
12407 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12409 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12411 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12415 /* The GNU toolchain uses an extension for ELF: a section
12416 beginning with the magic string .gnu.linkonce is a linkonce
12418 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12419 sizeof ".gnu.linkonce" - 1) == 0)
12423 /* This must duplicate the test in adjust_reloc_syms. */
12424 return (symsec
!= &bfd_und_section
12425 && symsec
!= &bfd_abs_section
12426 && ! bfd_is_com_section (symsec
)
12429 /* A global or weak symbol is treated as external. */
12430 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12431 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12437 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12438 extended opcode. SEC is the section the frag is in. */
12441 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12444 register const struct mips16_immed_operand
*op
;
12446 int mintiny
, maxtiny
;
12450 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12452 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12455 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12456 op
= mips16_immed_operands
;
12457 while (op
->type
!= type
)
12460 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12465 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12468 maxtiny
= 1 << op
->nbits
;
12473 maxtiny
= (1 << op
->nbits
) - 1;
12478 mintiny
= - (1 << (op
->nbits
- 1));
12479 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12482 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12483 val
= S_GET_VALUE (fragp
->fr_symbol
);
12484 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12490 /* We won't have the section when we are called from
12491 mips_relax_frag. However, we will always have been called
12492 from md_estimate_size_before_relax first. If this is a
12493 branch to a different section, we mark it as such. If SEC is
12494 NULL, and the frag is not marked, then it must be a branch to
12495 the same section. */
12498 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12503 /* Must have been called from md_estimate_size_before_relax. */
12506 fragp
->fr_subtype
=
12507 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12509 /* FIXME: We should support this, and let the linker
12510 catch branches and loads that are out of range. */
12511 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12512 _("unsupported PC relative reference to different section"));
12516 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12517 /* Assume non-extended on the first relaxation pass.
12518 The address we have calculated will be bogus if this is
12519 a forward branch to another frag, as the forward frag
12520 will have fr_address == 0. */
12524 /* In this case, we know for sure that the symbol fragment is in
12525 the same section. If the relax_marker of the symbol fragment
12526 differs from the relax_marker of this fragment, we have not
12527 yet adjusted the symbol fragment fr_address. We want to add
12528 in STRETCH in order to get a better estimate of the address.
12529 This particularly matters because of the shift bits. */
12531 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12535 /* Adjust stretch for any alignment frag. Note that if have
12536 been expanding the earlier code, the symbol may be
12537 defined in what appears to be an earlier frag. FIXME:
12538 This doesn't handle the fr_subtype field, which specifies
12539 a maximum number of bytes to skip when doing an
12541 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12543 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12546 stretch
= - ((- stretch
)
12547 & ~ ((1 << (int) f
->fr_offset
) - 1));
12549 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12558 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12560 /* The base address rules are complicated. The base address of
12561 a branch is the following instruction. The base address of a
12562 PC relative load or add is the instruction itself, but if it
12563 is in a delay slot (in which case it can not be extended) use
12564 the address of the instruction whose delay slot it is in. */
12565 if (type
== 'p' || type
== 'q')
12569 /* If we are currently assuming that this frag should be
12570 extended, then, the current address is two bytes
12572 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12575 /* Ignore the low bit in the target, since it will be set
12576 for a text label. */
12577 if ((val
& 1) != 0)
12580 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12582 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12585 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12587 /* Branch offsets have an implicit 0 in the lowest bit. */
12588 if (type
== 'p' || type
== 'q')
12591 /* If any of the shifted bits are set, we must use an extended
12592 opcode. If the address depends on the size of this
12593 instruction, this can lead to a loop, so we arrange to always
12594 use an extended opcode. We only check this when we are in
12595 the main relaxation loop, when SEC is NULL. */
12596 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12598 fragp
->fr_subtype
=
12599 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12603 /* If we are about to mark a frag as extended because the value
12604 is precisely maxtiny + 1, then there is a chance of an
12605 infinite loop as in the following code:
12610 In this case when the la is extended, foo is 0x3fc bytes
12611 away, so the la can be shrunk, but then foo is 0x400 away, so
12612 the la must be extended. To avoid this loop, we mark the
12613 frag as extended if it was small, and is about to become
12614 extended with a value of maxtiny + 1. */
12615 if (val
== ((maxtiny
+ 1) << op
->shift
)
12616 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12619 fragp
->fr_subtype
=
12620 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12624 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12625 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12627 if ((val
& ((1 << op
->shift
) - 1)) != 0
12628 || val
< (mintiny
<< op
->shift
)
12629 || val
> (maxtiny
<< op
->shift
))
12635 /* Compute the length of a branch sequence, and adjust the
12636 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12637 worst-case length is computed, with UPDATE being used to indicate
12638 whether an unconditional (-1), branch-likely (+1) or regular (0)
12639 branch is to be computed. */
12641 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12643 bfd_boolean toofar
;
12647 && S_IS_DEFINED (fragp
->fr_symbol
)
12648 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12653 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12655 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12659 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12662 /* If the symbol is not defined or it's in a different segment,
12663 assume the user knows what's going on and emit a short
12669 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12671 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12672 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12673 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12679 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12682 if (mips_pic
!= NO_PIC
)
12684 /* Additional space for PIC loading of target address. */
12686 if (mips_opts
.isa
== ISA_MIPS1
)
12687 /* Additional space for $at-stabilizing nop. */
12691 /* If branch is conditional. */
12692 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12699 /* Estimate the size of a frag before relaxing. Unless this is the
12700 mips16, we are not really relaxing here, and the final size is
12701 encoded in the subtype information. For the mips16, we have to
12702 decide whether we are using an extended opcode or not. */
12705 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12709 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12712 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12714 return fragp
->fr_var
;
12717 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12718 /* We don't want to modify the EXTENDED bit here; it might get us
12719 into infinite loops. We change it only in mips_relax_frag(). */
12720 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12722 if (mips_pic
== NO_PIC
)
12723 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12724 else if (mips_pic
== SVR4_PIC
)
12725 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12731 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12732 return -RELAX_FIRST (fragp
->fr_subtype
);
12735 return -RELAX_SECOND (fragp
->fr_subtype
);
12738 /* This is called to see whether a reloc against a defined symbol
12739 should be converted into a reloc against a section. */
12742 mips_fix_adjustable (fixS
*fixp
)
12744 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12745 about the format of the offset in the .o file. */
12746 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12749 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12750 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12753 if (fixp
->fx_addsy
== NULL
)
12756 /* If symbol SYM is in a mergeable section, relocations of the form
12757 SYM + 0 can usually be made section-relative. The mergeable data
12758 is then identified by the section offset rather than by the symbol.
12760 However, if we're generating REL LO16 relocations, the offset is split
12761 between the LO16 and parterning high part relocation. The linker will
12762 need to recalculate the complete offset in order to correctly identify
12765 The linker has traditionally not looked for the parterning high part
12766 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12767 placed anywhere. Rather than break backwards compatibility by changing
12768 this, it seems better not to force the issue, and instead keep the
12769 original symbol. This will work with either linker behavior. */
12770 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12771 && HAVE_IN_PLACE_ADDENDS
12772 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12776 /* Don't adjust relocations against mips16 symbols, so that the linker
12777 can find them if it needs to set up a stub. */
12778 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12779 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12780 && fixp
->fx_subsy
== NULL
)
12787 /* Translate internal representation of relocation info to BFD target
12791 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12793 static arelent
*retval
[4];
12795 bfd_reloc_code_real_type code
;
12797 memset (retval
, 0, sizeof(retval
));
12798 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12799 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12800 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12801 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12803 assert (! fixp
->fx_pcrel
);
12804 reloc
->addend
= fixp
->fx_addnumber
;
12806 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12807 entry to be used in the relocation's section offset. */
12808 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12810 reloc
->address
= reloc
->addend
;
12814 code
= fixp
->fx_r_type
;
12816 /* To support a PC relative reloc, we used a Cygnus extension.
12817 We check for that here to make sure that we don't let such a
12818 reloc escape normally. (FIXME: This was formerly used by
12819 embedded-PIC support, but is now used by branch handling in
12820 general. That probably should be fixed.) */
12821 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12822 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12823 && code
== BFD_RELOC_16_PCREL_S2
)
12824 reloc
->howto
= NULL
;
12826 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12828 if (reloc
->howto
== NULL
)
12830 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12831 _("Can not represent %s relocation in this object file format"),
12832 bfd_get_reloc_code_name (code
));
12839 /* Relax a machine dependent frag. This returns the amount by which
12840 the current size of the frag should change. */
12843 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12845 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12847 offsetT old_var
= fragp
->fr_var
;
12849 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12851 return fragp
->fr_var
- old_var
;
12854 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12857 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12859 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12861 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12866 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12868 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12875 /* Convert a machine dependent frag. */
12878 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12880 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12883 unsigned long insn
;
12887 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12889 if (target_big_endian
)
12890 insn
= bfd_getb32 (buf
);
12892 insn
= bfd_getl32 (buf
);
12894 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12896 /* We generate a fixup instead of applying it right now
12897 because, if there are linker relaxations, we're going to
12898 need the relocations. */
12899 exp
.X_op
= O_symbol
;
12900 exp
.X_add_symbol
= fragp
->fr_symbol
;
12901 exp
.X_add_number
= fragp
->fr_offset
;
12903 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12905 BFD_RELOC_16_PCREL_S2
);
12906 fixp
->fx_file
= fragp
->fr_file
;
12907 fixp
->fx_line
= fragp
->fr_line
;
12909 md_number_to_chars (buf
, insn
, 4);
12916 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12917 _("relaxed out-of-range branch into a jump"));
12919 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12922 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12924 /* Reverse the branch. */
12925 switch ((insn
>> 28) & 0xf)
12928 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12929 have the condition reversed by tweaking a single
12930 bit, and their opcodes all have 0x4???????. */
12931 assert ((insn
& 0xf1000000) == 0x41000000);
12932 insn
^= 0x00010000;
12936 /* bltz 0x04000000 bgez 0x04010000
12937 bltzal 0x04100000 bgezal 0x04110000 */
12938 assert ((insn
& 0xfc0e0000) == 0x04000000);
12939 insn
^= 0x00010000;
12943 /* beq 0x10000000 bne 0x14000000
12944 blez 0x18000000 bgtz 0x1c000000 */
12945 insn
^= 0x04000000;
12953 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12955 /* Clear the and-link bit. */
12956 assert ((insn
& 0xfc1c0000) == 0x04100000);
12958 /* bltzal 0x04100000 bgezal 0x04110000
12959 bltzall 0x04120000 bgezall 0x04130000 */
12960 insn
&= ~0x00100000;
12963 /* Branch over the branch (if the branch was likely) or the
12964 full jump (not likely case). Compute the offset from the
12965 current instruction to branch to. */
12966 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12970 /* How many bytes in instructions we've already emitted? */
12971 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12972 /* How many bytes in instructions from here to the end? */
12973 i
= fragp
->fr_var
- i
;
12975 /* Convert to instruction count. */
12977 /* Branch counts from the next instruction. */
12980 /* Branch over the jump. */
12981 md_number_to_chars (buf
, insn
, 4);
12985 md_number_to_chars (buf
, 0, 4);
12988 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12990 /* beql $0, $0, 2f */
12992 /* Compute the PC offset from the current instruction to
12993 the end of the variable frag. */
12994 /* How many bytes in instructions we've already emitted? */
12995 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12996 /* How many bytes in instructions from here to the end? */
12997 i
= fragp
->fr_var
- i
;
12998 /* Convert to instruction count. */
13000 /* Don't decrement i, because we want to branch over the
13004 md_number_to_chars (buf
, insn
, 4);
13007 md_number_to_chars (buf
, 0, 4);
13012 if (mips_pic
== NO_PIC
)
13015 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13016 ? 0x0c000000 : 0x08000000);
13017 exp
.X_op
= O_symbol
;
13018 exp
.X_add_symbol
= fragp
->fr_symbol
;
13019 exp
.X_add_number
= fragp
->fr_offset
;
13021 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13022 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13023 fixp
->fx_file
= fragp
->fr_file
;
13024 fixp
->fx_line
= fragp
->fr_line
;
13026 md_number_to_chars (buf
, insn
, 4);
13031 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13032 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13033 exp
.X_op
= O_symbol
;
13034 exp
.X_add_symbol
= fragp
->fr_symbol
;
13035 exp
.X_add_number
= fragp
->fr_offset
;
13037 if (fragp
->fr_offset
)
13039 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13040 exp
.X_add_number
= 0;
13043 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13044 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13045 fixp
->fx_file
= fragp
->fr_file
;
13046 fixp
->fx_line
= fragp
->fr_line
;
13048 md_number_to_chars (buf
, insn
, 4);
13051 if (mips_opts
.isa
== ISA_MIPS1
)
13054 md_number_to_chars (buf
, 0, 4);
13058 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13059 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13061 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13062 4, &exp
, 0, BFD_RELOC_LO16
);
13063 fixp
->fx_file
= fragp
->fr_file
;
13064 fixp
->fx_line
= fragp
->fr_line
;
13066 md_number_to_chars (buf
, insn
, 4);
13070 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13075 md_number_to_chars (buf
, insn
, 4);
13080 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13081 + fragp
->fr_fix
+ fragp
->fr_var
);
13083 fragp
->fr_fix
+= fragp
->fr_var
;
13088 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13091 register const struct mips16_immed_operand
*op
;
13092 bfd_boolean small
, ext
;
13095 unsigned long insn
;
13096 bfd_boolean use_extend
;
13097 unsigned short extend
;
13099 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13100 op
= mips16_immed_operands
;
13101 while (op
->type
!= type
)
13104 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13115 resolve_symbol_value (fragp
->fr_symbol
);
13116 val
= S_GET_VALUE (fragp
->fr_symbol
);
13121 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13123 /* The rules for the base address of a PC relative reloc are
13124 complicated; see mips16_extended_frag. */
13125 if (type
== 'p' || type
== 'q')
13130 /* Ignore the low bit in the target, since it will be
13131 set for a text label. */
13132 if ((val
& 1) != 0)
13135 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13137 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13140 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13143 /* Make sure the section winds up with the alignment we have
13146 record_alignment (asec
, op
->shift
);
13150 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13151 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13152 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13153 _("extended instruction in delay slot"));
13155 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13157 if (target_big_endian
)
13158 insn
= bfd_getb16 (buf
);
13160 insn
= bfd_getl16 (buf
);
13162 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13163 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13164 small
, ext
, &insn
, &use_extend
, &extend
);
13168 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13169 fragp
->fr_fix
+= 2;
13173 md_number_to_chars (buf
, insn
, 2);
13174 fragp
->fr_fix
+= 2;
13182 first
= RELAX_FIRST (fragp
->fr_subtype
);
13183 second
= RELAX_SECOND (fragp
->fr_subtype
);
13184 fixp
= (fixS
*) fragp
->fr_opcode
;
13186 /* Possibly emit a warning if we've chosen the longer option. */
13187 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13188 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13190 const char *msg
= macro_warning (fragp
->fr_subtype
);
13192 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13195 /* Go through all the fixups for the first sequence. Disable them
13196 (by marking them as done) if we're going to use the second
13197 sequence instead. */
13199 && fixp
->fx_frag
== fragp
13200 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13202 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13204 fixp
= fixp
->fx_next
;
13207 /* Go through the fixups for the second sequence. Disable them if
13208 we're going to use the first sequence, otherwise adjust their
13209 addresses to account for the relaxation. */
13210 while (fixp
&& fixp
->fx_frag
== fragp
)
13212 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13213 fixp
->fx_where
-= first
;
13216 fixp
= fixp
->fx_next
;
13219 /* Now modify the frag contents. */
13220 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13224 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13225 memmove (start
, start
+ first
, second
);
13226 fragp
->fr_fix
-= first
;
13229 fragp
->fr_fix
-= second
;
13235 /* This function is called after the relocs have been generated.
13236 We've been storing mips16 text labels as odd. Here we convert them
13237 back to even for the convenience of the debugger. */
13240 mips_frob_file_after_relocs (void)
13243 unsigned int count
, i
;
13245 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13248 syms
= bfd_get_outsymbols (stdoutput
);
13249 count
= bfd_get_symcount (stdoutput
);
13250 for (i
= 0; i
< count
; i
++, syms
++)
13252 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13253 && ((*syms
)->value
& 1) != 0)
13255 (*syms
)->value
&= ~1;
13256 /* If the symbol has an odd size, it was probably computed
13257 incorrectly, so adjust that as well. */
13258 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13259 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13266 /* This function is called whenever a label is defined. It is used
13267 when handling branch delays; if a branch has a label, we assume we
13268 can not move it. */
13271 mips_define_label (symbolS
*sym
)
13273 struct insn_label_list
*l
;
13275 if (free_insn_labels
== NULL
)
13276 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13279 l
= free_insn_labels
;
13280 free_insn_labels
= l
->next
;
13284 l
->next
= insn_labels
;
13288 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13290 /* Some special processing for a MIPS ELF file. */
13293 mips_elf_final_processing (void)
13295 /* Write out the register information. */
13296 if (mips_abi
!= N64_ABI
)
13300 s
.ri_gprmask
= mips_gprmask
;
13301 s
.ri_cprmask
[0] = mips_cprmask
[0];
13302 s
.ri_cprmask
[1] = mips_cprmask
[1];
13303 s
.ri_cprmask
[2] = mips_cprmask
[2];
13304 s
.ri_cprmask
[3] = mips_cprmask
[3];
13305 /* The gp_value field is set by the MIPS ELF backend. */
13307 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13308 ((Elf32_External_RegInfo
*)
13309 mips_regmask_frag
));
13313 Elf64_Internal_RegInfo s
;
13315 s
.ri_gprmask
= mips_gprmask
;
13317 s
.ri_cprmask
[0] = mips_cprmask
[0];
13318 s
.ri_cprmask
[1] = mips_cprmask
[1];
13319 s
.ri_cprmask
[2] = mips_cprmask
[2];
13320 s
.ri_cprmask
[3] = mips_cprmask
[3];
13321 /* The gp_value field is set by the MIPS ELF backend. */
13323 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13324 ((Elf64_External_RegInfo
*)
13325 mips_regmask_frag
));
13328 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13329 sort of BFD interface for this. */
13330 if (mips_any_noreorder
)
13331 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13332 if (mips_pic
!= NO_PIC
)
13334 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13335 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13338 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13340 /* Set MIPS ELF flags for ASEs. */
13341 if (file_ase_mips16
)
13342 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13343 #if 0 /* XXX FIXME */
13344 if (file_ase_mips3d
)
13345 elf_elfheader (stdoutput
)->e_flags
|= ???;
13348 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13350 /* Set the MIPS ELF ABI flags. */
13351 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13352 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13353 else if (mips_abi
== O64_ABI
)
13354 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13355 else if (mips_abi
== EABI_ABI
)
13357 if (!file_mips_gp32
)
13358 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13360 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13362 else if (mips_abi
== N32_ABI
)
13363 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13365 /* Nothing to do for N64_ABI. */
13367 if (mips_32bitmode
)
13368 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13371 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13373 typedef struct proc
{
13375 unsigned long reg_mask
;
13376 unsigned long reg_offset
;
13377 unsigned long fpreg_mask
;
13378 unsigned long fpreg_offset
;
13379 unsigned long frame_offset
;
13380 unsigned long frame_reg
;
13381 unsigned long pc_reg
;
13384 static procS cur_proc
;
13385 static procS
*cur_proc_ptr
;
13386 static int numprocs
;
13388 /* Fill in an rs_align_code fragment. */
13391 mips_handle_align (fragS
*fragp
)
13393 if (fragp
->fr_type
!= rs_align_code
)
13396 if (mips_opts
.mips16
)
13398 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13399 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13404 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13405 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13413 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13417 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13421 md_obj_begin (void)
13428 /* check for premature end, nesting errors, etc */
13430 as_warn (_("missing .end at end of assembly"));
13439 if (*input_line_pointer
== '-')
13441 ++input_line_pointer
;
13444 if (!ISDIGIT (*input_line_pointer
))
13445 as_bad (_("expected simple number"));
13446 if (input_line_pointer
[0] == '0')
13448 if (input_line_pointer
[1] == 'x')
13450 input_line_pointer
+= 2;
13451 while (ISXDIGIT (*input_line_pointer
))
13454 val
|= hex_value (*input_line_pointer
++);
13456 return negative
? -val
: val
;
13460 ++input_line_pointer
;
13461 while (ISDIGIT (*input_line_pointer
))
13464 val
|= *input_line_pointer
++ - '0';
13466 return negative
? -val
: val
;
13469 if (!ISDIGIT (*input_line_pointer
))
13471 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13472 *input_line_pointer
, *input_line_pointer
);
13473 as_warn (_("invalid number"));
13476 while (ISDIGIT (*input_line_pointer
))
13479 val
+= *input_line_pointer
++ - '0';
13481 return negative
? -val
: val
;
13484 /* The .file directive; just like the usual .file directive, but there
13485 is an initial number which is the ECOFF file index. In the non-ECOFF
13486 case .file implies DWARF-2. */
13489 s_mips_file (int x ATTRIBUTE_UNUSED
)
13491 static int first_file_directive
= 0;
13493 if (ECOFF_DEBUGGING
)
13502 filename
= dwarf2_directive_file (0);
13504 /* Versions of GCC up to 3.1 start files with a ".file"
13505 directive even for stabs output. Make sure that this
13506 ".file" is handled. Note that you need a version of GCC
13507 after 3.1 in order to support DWARF-2 on MIPS. */
13508 if (filename
!= NULL
&& ! first_file_directive
)
13510 (void) new_logical_line (filename
, -1);
13511 s_app_file_string (filename
);
13513 first_file_directive
= 1;
13517 /* The .loc directive, implying DWARF-2. */
13520 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13522 if (!ECOFF_DEBUGGING
)
13523 dwarf2_directive_loc (0);
13526 /* The .end directive. */
13529 s_mips_end (int x ATTRIBUTE_UNUSED
)
13533 /* Following functions need their own .frame and .cprestore directives. */
13534 mips_frame_reg_valid
= 0;
13535 mips_cprestore_valid
= 0;
13537 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13540 demand_empty_rest_of_line ();
13545 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13546 as_warn (_(".end not in text section"));
13550 as_warn (_(".end directive without a preceding .ent directive."));
13551 demand_empty_rest_of_line ();
13557 assert (S_GET_NAME (p
));
13558 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13559 as_warn (_(".end symbol does not match .ent symbol."));
13561 if (debug_type
== DEBUG_STABS
)
13562 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13566 as_warn (_(".end directive missing or unknown symbol"));
13569 /* Generate a .pdr section. */
13570 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13573 segT saved_seg
= now_seg
;
13574 subsegT saved_subseg
= now_subseg
;
13579 dot
= frag_now_fix ();
13581 #ifdef md_flush_pending_output
13582 md_flush_pending_output ();
13586 subseg_set (pdr_seg
, 0);
13588 /* Write the symbol. */
13589 exp
.X_op
= O_symbol
;
13590 exp
.X_add_symbol
= p
;
13591 exp
.X_add_number
= 0;
13592 emit_expr (&exp
, 4);
13594 fragp
= frag_more (7 * 4);
13596 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13597 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13598 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13599 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13600 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13601 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13602 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13604 subseg_set (saved_seg
, saved_subseg
);
13606 #endif /* OBJ_ELF */
13608 cur_proc_ptr
= NULL
;
13611 /* The .aent and .ent directives. */
13614 s_mips_ent (int aent
)
13618 symbolP
= get_symbol ();
13619 if (*input_line_pointer
== ',')
13620 ++input_line_pointer
;
13621 SKIP_WHITESPACE ();
13622 if (ISDIGIT (*input_line_pointer
)
13623 || *input_line_pointer
== '-')
13626 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13627 as_warn (_(".ent or .aent not in text section."));
13629 if (!aent
&& cur_proc_ptr
)
13630 as_warn (_("missing .end"));
13634 /* This function needs its own .frame and .cprestore directives. */
13635 mips_frame_reg_valid
= 0;
13636 mips_cprestore_valid
= 0;
13638 cur_proc_ptr
= &cur_proc
;
13639 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13641 cur_proc_ptr
->isym
= symbolP
;
13643 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13647 if (debug_type
== DEBUG_STABS
)
13648 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13649 S_GET_NAME (symbolP
));
13652 demand_empty_rest_of_line ();
13655 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13656 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13657 s_mips_frame is used so that we can set the PDR information correctly.
13658 We can't use the ecoff routines because they make reference to the ecoff
13659 symbol table (in the mdebug section). */
13662 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13665 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13669 if (cur_proc_ptr
== (procS
*) NULL
)
13671 as_warn (_(".frame outside of .ent"));
13672 demand_empty_rest_of_line ();
13676 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13678 SKIP_WHITESPACE ();
13679 if (*input_line_pointer
++ != ','
13680 || get_absolute_expression_and_terminator (&val
) != ',')
13682 as_warn (_("Bad .frame directive"));
13683 --input_line_pointer
;
13684 demand_empty_rest_of_line ();
13688 cur_proc_ptr
->frame_offset
= val
;
13689 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13691 demand_empty_rest_of_line ();
13694 #endif /* OBJ_ELF */
13698 /* The .fmask and .mask directives. If the mdebug section is present
13699 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13700 embedded targets, s_mips_mask is used so that we can set the PDR
13701 information correctly. We can't use the ecoff routines because they
13702 make reference to the ecoff symbol table (in the mdebug section). */
13705 s_mips_mask (int reg_type
)
13708 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13712 if (cur_proc_ptr
== (procS
*) NULL
)
13714 as_warn (_(".mask/.fmask outside of .ent"));
13715 demand_empty_rest_of_line ();
13719 if (get_absolute_expression_and_terminator (&mask
) != ',')
13721 as_warn (_("Bad .mask/.fmask directive"));
13722 --input_line_pointer
;
13723 demand_empty_rest_of_line ();
13727 off
= get_absolute_expression ();
13729 if (reg_type
== 'F')
13731 cur_proc_ptr
->fpreg_mask
= mask
;
13732 cur_proc_ptr
->fpreg_offset
= off
;
13736 cur_proc_ptr
->reg_mask
= mask
;
13737 cur_proc_ptr
->reg_offset
= off
;
13740 demand_empty_rest_of_line ();
13743 #endif /* OBJ_ELF */
13744 s_ignore (reg_type
);
13747 /* The .loc directive. */
13757 assert (now_seg
== text_section
);
13759 lineno
= get_number ();
13760 addroff
= frag_now_fix ();
13762 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13763 S_SET_TYPE (symbolP
, N_SLINE
);
13764 S_SET_OTHER (symbolP
, 0);
13765 S_SET_DESC (symbolP
, lineno
);
13766 symbolP
->sy_segment
= now_seg
;
13770 /* A table describing all the processors gas knows about. Names are
13771 matched in the order listed.
13773 To ease comparison, please keep this table in the same order as
13774 gcc's mips_cpu_info_table[]. */
13775 static const struct mips_cpu_info mips_cpu_info_table
[] =
13777 /* Entries for generic ISAs */
13778 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13779 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13780 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13781 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13782 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13783 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13784 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13785 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13786 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13789 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13790 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13791 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13794 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13797 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13798 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13799 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13800 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13801 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13802 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13803 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13804 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13805 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13806 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13807 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13808 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13811 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13812 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13813 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13814 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13815 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13816 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13817 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13818 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13819 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13820 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13821 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13822 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13823 { "rm9000", 0, ISA_MIPS4
, CPU_RM7000
},
13826 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13827 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13828 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13831 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13832 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13834 /* Broadcom SB-1 CPU core */
13835 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13842 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13843 with a final "000" replaced by "k". Ignore case.
13845 Note: this function is shared between GCC and GAS. */
13848 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13850 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13851 given
++, canonical
++;
13853 return ((*given
== 0 && *canonical
== 0)
13854 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13858 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13859 CPU name. We've traditionally allowed a lot of variation here.
13861 Note: this function is shared between GCC and GAS. */
13864 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13866 /* First see if the name matches exactly, or with a final "000"
13867 turned into "k". */
13868 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13871 /* If not, try comparing based on numerical designation alone.
13872 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13873 if (TOLOWER (*given
) == 'r')
13875 if (!ISDIGIT (*given
))
13878 /* Skip over some well-known prefixes in the canonical name,
13879 hoping to find a number there too. */
13880 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13882 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13884 else if (TOLOWER (canonical
[0]) == 'r')
13887 return mips_strict_matching_cpu_name_p (canonical
, given
);
13891 /* Parse an option that takes the name of a processor as its argument.
13892 OPTION is the name of the option and CPU_STRING is the argument.
13893 Return the corresponding processor enumeration if the CPU_STRING is
13894 recognized, otherwise report an error and return null.
13896 A similar function exists in GCC. */
13898 static const struct mips_cpu_info
*
13899 mips_parse_cpu (const char *option
, const char *cpu_string
)
13901 const struct mips_cpu_info
*p
;
13903 /* 'from-abi' selects the most compatible architecture for the given
13904 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13905 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13906 version. Look first at the -mgp options, if given, otherwise base
13907 the choice on MIPS_DEFAULT_64BIT.
13909 Treat NO_ABI like the EABIs. One reason to do this is that the
13910 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13911 architecture. This code picks MIPS I for 'mips' and MIPS III for
13912 'mips64', just as we did in the days before 'from-abi'. */
13913 if (strcasecmp (cpu_string
, "from-abi") == 0)
13915 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13916 return mips_cpu_info_from_isa (ISA_MIPS1
);
13918 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13919 return mips_cpu_info_from_isa (ISA_MIPS3
);
13921 if (file_mips_gp32
>= 0)
13922 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13924 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13929 /* 'default' has traditionally been a no-op. Probably not very useful. */
13930 if (strcasecmp (cpu_string
, "default") == 0)
13933 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13934 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13937 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13941 /* Return the canonical processor information for ISA (a member of the
13942 ISA_MIPS* enumeration). */
13944 static const struct mips_cpu_info
*
13945 mips_cpu_info_from_isa (int isa
)
13949 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13950 if (mips_cpu_info_table
[i
].is_isa
13951 && isa
== mips_cpu_info_table
[i
].isa
)
13952 return (&mips_cpu_info_table
[i
]);
13957 static const struct mips_cpu_info
*
13958 mips_cpu_info_from_arch (int arch
)
13962 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13963 if (arch
== mips_cpu_info_table
[i
].cpu
)
13964 return (&mips_cpu_info_table
[i
]);
13970 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13974 fprintf (stream
, "%24s", "");
13979 fprintf (stream
, ", ");
13983 if (*col_p
+ strlen (string
) > 72)
13985 fprintf (stream
, "\n%24s", "");
13989 fprintf (stream
, "%s", string
);
13990 *col_p
+= strlen (string
);
13996 md_show_usage (FILE *stream
)
14001 fprintf (stream
, _("\
14003 -EB generate big endian output\n\
14004 -EL generate little endian output\n\
14005 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14006 -G NUM allow referencing objects up to NUM bytes\n\
14007 implicitly with the gp register [default 8]\n"));
14008 fprintf (stream
, _("\
14009 -mips1 generate MIPS ISA I instructions\n\
14010 -mips2 generate MIPS ISA II instructions\n\
14011 -mips3 generate MIPS ISA III instructions\n\
14012 -mips4 generate MIPS ISA IV instructions\n\
14013 -mips5 generate MIPS ISA V instructions\n\
14014 -mips32 generate MIPS32 ISA instructions\n\
14015 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14016 -mips64 generate MIPS64 ISA instructions\n\
14017 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14018 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14022 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14023 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14024 show (stream
, "from-abi", &column
, &first
);
14025 fputc ('\n', stream
);
14027 fprintf (stream
, _("\
14028 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14029 -no-mCPU don't generate code specific to CPU.\n\
14030 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14034 show (stream
, "3900", &column
, &first
);
14035 show (stream
, "4010", &column
, &first
);
14036 show (stream
, "4100", &column
, &first
);
14037 show (stream
, "4650", &column
, &first
);
14038 fputc ('\n', stream
);
14040 fprintf (stream
, _("\
14041 -mips16 generate mips16 instructions\n\
14042 -no-mips16 do not generate mips16 instructions\n"));
14043 fprintf (stream
, _("\
14044 -mfix-vr4120 work around certain VR4120 errata\n\
14045 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14046 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14047 -O0 remove unneeded NOPs, do not swap branches\n\
14048 -O remove unneeded NOPs and swap branches\n\
14049 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14050 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14051 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14053 fprintf (stream
, _("\
14054 -KPIC, -call_shared generate SVR4 position independent code\n\
14055 -non_shared do not generate position independent code\n\
14056 -xgot assume a 32 bit GOT\n\
14057 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14058 -mabi=ABI create ABI conformant object file for:\n"));
14062 show (stream
, "32", &column
, &first
);
14063 show (stream
, "o64", &column
, &first
);
14064 show (stream
, "n32", &column
, &first
);
14065 show (stream
, "64", &column
, &first
);
14066 show (stream
, "eabi", &column
, &first
);
14068 fputc ('\n', stream
);
14070 fprintf (stream
, _("\
14071 -32 create o32 ABI object file (default)\n\
14072 -n32 create n32 ABI object file\n\
14073 -64 create 64 ABI object file\n"));
14078 mips_dwarf2_format (void)
14080 if (mips_abi
== N64_ABI
)
14083 return dwarf2_format_64bit_irix
;
14085 return dwarf2_format_64bit
;
14089 return dwarf2_format_32bit
;
14093 mips_dwarf2_addr_size (void)
14095 if (mips_abi
== N64_ABI
)