1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
515 /* True if CPU has seq/sne and seqi/snei instructions. */
516 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
518 /* True, if CPU has support for ldc1 and sdc1. */
519 #define CPU_HAS_LDC1_SDC1(CPU) \
520 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
522 /* True if mflo and mfhi can be immediately followed by instructions
523 which write to the HI and LO registers.
525 According to MIPS specifications, MIPS ISAs I, II, and III need
526 (at least) two instructions between the reads of HI/LO and
527 instructions which write them, and later ISAs do not. Contradicting
528 the MIPS specifications, some MIPS IV processor user manuals (e.g.
529 the UM for the NEC Vr5000) document needing the instructions between
530 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
531 MIPS64 and later ISAs to have the interlocks, plus any specific
532 earlier-ISA CPUs for which CPU documentation declares that the
533 instructions are really interlocked. */
534 #define hilo_interlocks \
535 (mips_opts.isa == ISA_MIPS32 \
536 || mips_opts.isa == ISA_MIPS32R2 \
537 || mips_opts.isa == ISA_MIPS32R3 \
538 || mips_opts.isa == ISA_MIPS32R5 \
539 || mips_opts.isa == ISA_MIPS32R6 \
540 || mips_opts.isa == ISA_MIPS64 \
541 || mips_opts.isa == ISA_MIPS64R2 \
542 || mips_opts.isa == ISA_MIPS64R3 \
543 || mips_opts.isa == ISA_MIPS64R5 \
544 || mips_opts.isa == ISA_MIPS64R6 \
545 || mips_opts.arch == CPU_R4010 \
546 || mips_opts.arch == CPU_R5900 \
547 || mips_opts.arch == CPU_R10000 \
548 || mips_opts.arch == CPU_R12000 \
549 || mips_opts.arch == CPU_R14000 \
550 || mips_opts.arch == CPU_R16000 \
551 || mips_opts.arch == CPU_RM7000 \
552 || mips_opts.arch == CPU_VR5500 \
553 || mips_opts.micromips \
556 /* Whether the processor uses hardware interlocks to protect reads
557 from the GPRs after they are loaded from memory, and thus does not
558 require nops to be inserted. This applies to instructions marked
559 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
560 level I and microMIPS mode instructions are always interlocked. */
561 #define gpr_interlocks \
562 (mips_opts.isa != ISA_MIPS1 \
563 || mips_opts.arch == CPU_R3900 \
564 || mips_opts.arch == CPU_R5900 \
565 || mips_opts.micromips \
568 /* Whether the processor uses hardware interlocks to avoid delays
569 required by coprocessor instructions, and thus does not require
570 nops to be inserted. This applies to instructions marked
571 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
572 instructions marked INSN_WRITE_COND_CODE and ones marked
573 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
574 levels I, II, and III and microMIPS mode instructions are always
576 /* Itbl support may require additional care here. */
577 #define cop_interlocks \
578 ((mips_opts.isa != ISA_MIPS1 \
579 && mips_opts.isa != ISA_MIPS2 \
580 && mips_opts.isa != ISA_MIPS3) \
581 || mips_opts.arch == CPU_R4300 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to protect reads
586 from coprocessor registers after they are loaded from memory, and
587 thus does not require nops to be inserted. This applies to
588 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
589 requires at MIPS ISA level I and microMIPS mode instructions are
590 always interlocked. */
591 #define cop_mem_interlocks \
592 (mips_opts.isa != ISA_MIPS1 \
593 || mips_opts.micromips \
596 /* Is this a mfhi or mflo instruction? */
597 #define MF_HILO_INSN(PINFO) \
598 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
600 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
601 has been selected. This implies, in particular, that addresses of text
602 labels have their LSB set. */
603 #define HAVE_CODE_COMPRESSION \
604 ((mips_opts.mips16 | mips_opts.micromips) != 0)
606 /* The minimum and maximum signed values that can be stored in a GPR. */
607 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
608 #define GPR_SMIN (-GPR_SMAX - 1)
610 /* MIPS PIC level. */
612 enum mips_pic_level mips_pic
;
614 /* 1 if we should generate 32 bit offsets from the $gp register in
615 SVR4_PIC mode. Currently has no meaning in other modes. */
616 static int mips_big_got
= 0;
618 /* 1 if trap instructions should used for overflow rather than break
620 static int mips_trap
= 0;
622 /* 1 if double width floating point constants should not be constructed
623 by assembling two single width halves into two single width floating
624 point registers which just happen to alias the double width destination
625 register. On some architectures this aliasing can be disabled by a bit
626 in the status register, and the setting of this bit cannot be determined
627 automatically at assemble time. */
628 static int mips_disable_float_construction
;
630 /* Non-zero if any .set noreorder directives were used. */
632 static int mips_any_noreorder
;
634 /* Non-zero if nops should be inserted when the register referenced in
635 an mfhi/mflo instruction is read in the next two instructions. */
636 static int mips_7000_hilo_fix
;
638 /* The size of objects in the small data section. */
639 static unsigned int g_switch_value
= 8;
640 /* Whether the -G option was used. */
641 static int g_switch_seen
= 0;
646 /* If we can determine in advance that GP optimization won't be
647 possible, we can skip the relaxation stuff that tries to produce
648 GP-relative references. This makes delay slot optimization work
651 This function can only provide a guess, but it seems to work for
652 gcc output. It needs to guess right for gcc, otherwise gcc
653 will put what it thinks is a GP-relative instruction in a branch
656 I don't know if a fix is needed for the SVR4_PIC mode. I've only
657 fixed it for the non-PIC mode. KR 95/04/07 */
658 static int nopic_need_relax (symbolS
*, int);
660 /* handle of the OPCODE hash table */
661 static struct hash_control
*op_hash
= NULL
;
663 /* The opcode hash table we use for the mips16. */
664 static struct hash_control
*mips16_op_hash
= NULL
;
666 /* The opcode hash table we use for the microMIPS ASE. */
667 static struct hash_control
*micromips_op_hash
= NULL
;
669 /* This array holds the chars that always start a comment. If the
670 pre-processor is disabled, these aren't very useful */
671 const char comment_chars
[] = "#";
673 /* This array holds the chars that only start a comment at the beginning of
674 a line. If the line seems to have the form '# 123 filename'
675 .line and .file directives will appear in the pre-processed output */
676 /* Note that input_file.c hand checks for '#' at the beginning of the
677 first line of the input file. This is because the compiler outputs
678 #NO_APP at the beginning of its output. */
679 /* Also note that C style comments are always supported. */
680 const char line_comment_chars
[] = "#";
682 /* This array holds machine specific line separator characters. */
683 const char line_separator_chars
[] = ";";
685 /* Chars that can be used to separate mant from exp in floating point nums */
686 const char EXP_CHARS
[] = "eE";
688 /* Chars that mean this number is a floating point constant */
691 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
693 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
694 changed in read.c . Ideally it shouldn't have to know about it at all,
695 but nothing is ideal around here.
698 /* Types of printf format used for instruction-related error messages.
699 "I" means int ("%d") and "S" means string ("%s"). */
700 enum mips_insn_error_format
{
706 /* Information about an error that was found while assembling the current
708 struct mips_insn_error
{
709 /* We sometimes need to match an instruction against more than one
710 opcode table entry. Errors found during this matching are reported
711 against a particular syntactic argument rather than against the
712 instruction as a whole. We grade these messages so that errors
713 against argument N have a greater priority than an error against
714 any argument < N, since the former implies that arguments up to N
715 were acceptable and that the opcode entry was therefore a closer match.
716 If several matches report an error against the same argument,
717 we only use that error if it is the same in all cases.
719 min_argnum is the minimum argument number for which an error message
720 should be accepted. It is 0 if MSG is against the instruction as
724 /* The printf()-style message, including its format and arguments. */
725 enum mips_insn_error_format format
;
733 /* The error that should be reported for the current instruction. */
734 static struct mips_insn_error insn_error
;
736 static int auto_align
= 1;
738 /* When outputting SVR4 PIC code, the assembler needs to know the
739 offset in the stack frame from which to restore the $gp register.
740 This is set by the .cprestore pseudo-op, and saved in this
742 static offsetT mips_cprestore_offset
= -1;
744 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
745 more optimizations, it can use a register value instead of a memory-saved
746 offset and even an other register than $gp as global pointer. */
747 static offsetT mips_cpreturn_offset
= -1;
748 static int mips_cpreturn_register
= -1;
749 static int mips_gp_register
= GP
;
750 static int mips_gprel_offset
= 0;
752 /* Whether mips_cprestore_offset has been set in the current function
753 (or whether it has already been warned about, if not). */
754 static int mips_cprestore_valid
= 0;
756 /* This is the register which holds the stack frame, as set by the
757 .frame pseudo-op. This is needed to implement .cprestore. */
758 static int mips_frame_reg
= SP
;
760 /* Whether mips_frame_reg has been set in the current function
761 (or whether it has already been warned about, if not). */
762 static int mips_frame_reg_valid
= 0;
764 /* To output NOP instructions correctly, we need to keep information
765 about the previous two instructions. */
767 /* Whether we are optimizing. The default value of 2 means to remove
768 unneeded NOPs and swap branch instructions when possible. A value
769 of 1 means to not swap branches. A value of 0 means to always
771 static int mips_optimize
= 2;
773 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
774 equivalent to seeing no -g option at all. */
775 static int mips_debug
= 0;
777 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
778 #define MAX_VR4130_NOPS 4
780 /* The maximum number of NOPs needed to fill delay slots. */
781 #define MAX_DELAY_NOPS 2
783 /* The maximum number of NOPs needed for any purpose. */
786 /* A list of previous instructions, with index 0 being the most recent.
787 We need to look back MAX_NOPS instructions when filling delay slots
788 or working around processor errata. We need to look back one
789 instruction further if we're thinking about using history[0] to
790 fill a branch delay slot. */
791 static struct mips_cl_insn history
[1 + MAX_NOPS
];
793 /* Arrays of operands for each instruction. */
794 #define MAX_OPERANDS 6
795 struct mips_operand_array
{
796 const struct mips_operand
*operand
[MAX_OPERANDS
];
798 static struct mips_operand_array
*mips_operands
;
799 static struct mips_operand_array
*mips16_operands
;
800 static struct mips_operand_array
*micromips_operands
;
802 /* Nop instructions used by emit_nop. */
803 static struct mips_cl_insn nop_insn
;
804 static struct mips_cl_insn mips16_nop_insn
;
805 static struct mips_cl_insn micromips_nop16_insn
;
806 static struct mips_cl_insn micromips_nop32_insn
;
808 /* The appropriate nop for the current mode. */
809 #define NOP_INSN (mips_opts.mips16 \
811 : (mips_opts.micromips \
812 ? (mips_opts.insn32 \
813 ? µmips_nop32_insn \
814 : µmips_nop16_insn) \
817 /* The size of NOP_INSN in bytes. */
818 #define NOP_INSN_SIZE ((mips_opts.mips16 \
819 || (mips_opts.micromips && !mips_opts.insn32)) \
822 /* If this is set, it points to a frag holding nop instructions which
823 were inserted before the start of a noreorder section. If those
824 nops turn out to be unnecessary, the size of the frag can be
826 static fragS
*prev_nop_frag
;
828 /* The number of nop instructions we created in prev_nop_frag. */
829 static int prev_nop_frag_holds
;
831 /* The number of nop instructions that we know we need in
833 static int prev_nop_frag_required
;
835 /* The number of instructions we've seen since prev_nop_frag. */
836 static int prev_nop_frag_since
;
838 /* Relocations against symbols are sometimes done in two parts, with a HI
839 relocation and a LO relocation. Each relocation has only 16 bits of
840 space to store an addend. This means that in order for the linker to
841 handle carries correctly, it must be able to locate both the HI and
842 the LO relocation. This means that the relocations must appear in
843 order in the relocation table.
845 In order to implement this, we keep track of each unmatched HI
846 relocation. We then sort them so that they immediately precede the
847 corresponding LO relocation. */
852 struct mips_hi_fixup
*next
;
855 /* The section this fixup is in. */
859 /* The list of unmatched HI relocs. */
861 static struct mips_hi_fixup
*mips_hi_fixup_list
;
863 /* The frag containing the last explicit relocation operator.
864 Null if explicit relocations have not been used. */
866 static fragS
*prev_reloc_op_frag
;
868 /* Map mips16 register numbers to normal MIPS register numbers. */
870 static const unsigned int mips16_to_32_reg_map
[] =
872 16, 17, 2, 3, 4, 5, 6, 7
875 /* Map microMIPS register numbers to normal MIPS register numbers. */
877 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
879 /* The microMIPS registers with type h. */
880 static const unsigned int micromips_to_32_reg_h_map1
[] =
882 5, 5, 6, 4, 4, 4, 4, 4
884 static const unsigned int micromips_to_32_reg_h_map2
[] =
886 6, 7, 7, 21, 22, 5, 6, 7
889 /* The microMIPS registers with type m. */
890 static const unsigned int micromips_to_32_reg_m_map
[] =
892 0, 17, 2, 3, 16, 18, 19, 20
895 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
897 /* Classifies the kind of instructions we're interested in when
898 implementing -mfix-vr4120. */
899 enum fix_vr4120_class
907 NUM_FIX_VR4120_CLASSES
910 /* ...likewise -mfix-loongson2f-jump. */
911 static bfd_boolean mips_fix_loongson2f_jump
;
913 /* ...likewise -mfix-loongson2f-nop. */
914 static bfd_boolean mips_fix_loongson2f_nop
;
916 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
917 static bfd_boolean mips_fix_loongson2f
;
919 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
920 there must be at least one other instruction between an instruction
921 of type X and an instruction of type Y. */
922 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
924 /* True if -mfix-vr4120 is in force. */
925 static int mips_fix_vr4120
;
927 /* ...likewise -mfix-vr4130. */
928 static int mips_fix_vr4130
;
930 /* ...likewise -mfix-24k. */
931 static int mips_fix_24k
;
933 /* ...likewise -mfix-rm7000 */
934 static int mips_fix_rm7000
;
936 /* ...likewise -mfix-cn63xxp1 */
937 static bfd_boolean mips_fix_cn63xxp1
;
939 /* We don't relax branches by default, since this causes us to expand
940 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
941 fail to compute the offset before expanding the macro to the most
942 efficient expansion. */
944 static int mips_relax_branch
;
946 /* The expansion of many macros depends on the type of symbol that
947 they refer to. For example, when generating position-dependent code,
948 a macro that refers to a symbol may have two different expansions,
949 one which uses GP-relative addresses and one which uses absolute
950 addresses. When generating SVR4-style PIC, a macro may have
951 different expansions for local and global symbols.
953 We handle these situations by generating both sequences and putting
954 them in variant frags. In position-dependent code, the first sequence
955 will be the GP-relative one and the second sequence will be the
956 absolute one. In SVR4 PIC, the first sequence will be for global
957 symbols and the second will be for local symbols.
959 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
960 SECOND are the lengths of the two sequences in bytes. These fields
961 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
962 the subtype has the following flags:
965 Set if it has been decided that we should use the second
966 sequence instead of the first.
969 Set in the first variant frag if the macro's second implementation
970 is longer than its first. This refers to the macro as a whole,
971 not an individual relaxation.
974 Set in the first variant frag if the macro appeared in a .set nomacro
975 block and if one alternative requires a warning but the other does not.
978 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
981 RELAX_DELAY_SLOT_16BIT
982 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
985 RELAX_DELAY_SLOT_SIZE_FIRST
986 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
987 the macro is of the wrong size for the branch delay slot.
989 RELAX_DELAY_SLOT_SIZE_SECOND
990 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
991 the macro is of the wrong size for the branch delay slot.
993 The frag's "opcode" points to the first fixup for relaxable code.
995 Relaxable macros are generated using a sequence such as:
997 relax_start (SYMBOL);
998 ... generate first expansion ...
1000 ... generate second expansion ...
1003 The code and fixups for the unwanted alternative are discarded
1004 by md_convert_frag. */
1005 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1007 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1008 #define RELAX_SECOND(X) ((X) & 0xff)
1009 #define RELAX_USE_SECOND 0x10000
1010 #define RELAX_SECOND_LONGER 0x20000
1011 #define RELAX_NOMACRO 0x40000
1012 #define RELAX_DELAY_SLOT 0x80000
1013 #define RELAX_DELAY_SLOT_16BIT 0x100000
1014 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1015 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1017 /* Branch without likely bit. If label is out of range, we turn:
1019 beq reg1, reg2, label
1029 with the following opcode replacements:
1036 bltzal <-> bgezal (with jal label instead of j label)
1038 Even though keeping the delay slot instruction in the delay slot of
1039 the branch would be more efficient, it would be very tricky to do
1040 correctly, because we'd have to introduce a variable frag *after*
1041 the delay slot instruction, and expand that instead. Let's do it
1042 the easy way for now, even if the branch-not-taken case now costs
1043 one additional instruction. Out-of-range branches are not supposed
1044 to be common, anyway.
1046 Branch likely. If label is out of range, we turn:
1048 beql reg1, reg2, label
1049 delay slot (annulled if branch not taken)
1058 delay slot (executed only if branch taken)
1061 It would be possible to generate a shorter sequence by losing the
1062 likely bit, generating something like:
1067 delay slot (executed only if branch taken)
1079 bltzall -> bgezal (with jal label instead of j label)
1080 bgezall -> bltzal (ditto)
1083 but it's not clear that it would actually improve performance. */
1084 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1085 ((relax_substateT) \
1088 | ((toofar) ? 0x20 : 0) \
1089 | ((link) ? 0x40 : 0) \
1090 | ((likely) ? 0x80 : 0) \
1091 | ((uncond) ? 0x100 : 0)))
1092 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1093 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1094 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1095 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1096 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1097 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1099 /* For mips16 code, we use an entirely different form of relaxation.
1100 mips16 supports two versions of most instructions which take
1101 immediate values: a small one which takes some small value, and a
1102 larger one which takes a 16 bit value. Since branches also follow
1103 this pattern, relaxing these values is required.
1105 We can assemble both mips16 and normal MIPS code in a single
1106 object. Therefore, we need to support this type of relaxation at
1107 the same time that we support the relaxation described above. We
1108 use the high bit of the subtype field to distinguish these cases.
1110 The information we store for this type of relaxation is the
1111 argument code found in the opcode file for this relocation, whether
1112 the user explicitly requested a small or extended form, and whether
1113 the relocation is in a jump or jal delay slot. That tells us the
1114 size of the value, and how it should be stored. We also store
1115 whether the fragment is considered to be extended or not. We also
1116 store whether this is known to be a branch to a different section,
1117 whether we have tried to relax this frag yet, and whether we have
1118 ever extended a PC relative fragment because of a shift count. */
1119 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1122 | ((small) ? 0x100 : 0) \
1123 | ((ext) ? 0x200 : 0) \
1124 | ((dslot) ? 0x400 : 0) \
1125 | ((jal_dslot) ? 0x800 : 0))
1126 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1127 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1128 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1129 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1130 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1131 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1132 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1133 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1134 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1135 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1136 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1137 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1139 /* For microMIPS code, we use relaxation similar to one we use for
1140 MIPS16 code. Some instructions that take immediate values support
1141 two encodings: a small one which takes some small value, and a
1142 larger one which takes a 16 bit value. As some branches also follow
1143 this pattern, relaxing these values is required.
1145 We can assemble both microMIPS and normal MIPS code in a single
1146 object. Therefore, we need to support this type of relaxation at
1147 the same time that we support the relaxation described above. We
1148 use one of the high bits of the subtype field to distinguish these
1151 The information we store for this type of relaxation is the argument
1152 code found in the opcode file for this relocation, the register
1153 selected as the assembler temporary, whether the branch is
1154 unconditional, whether it is compact, whether it stores the link
1155 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1156 branches to a sequence of instructions is enabled, and whether the
1157 displacement of a branch is too large to fit as an immediate argument
1158 of a 16-bit and a 32-bit branch, respectively. */
1159 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1160 relax32, toofar16, toofar32) \
1163 | (((at) & 0x1f) << 8) \
1164 | ((uncond) ? 0x2000 : 0) \
1165 | ((compact) ? 0x4000 : 0) \
1166 | ((link) ? 0x8000 : 0) \
1167 | ((relax32) ? 0x10000 : 0) \
1168 | ((toofar16) ? 0x20000 : 0) \
1169 | ((toofar32) ? 0x40000 : 0))
1170 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1171 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1172 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1173 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1174 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1175 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1176 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1178 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1179 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1180 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1181 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1182 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1183 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1185 /* Sign-extend 16-bit value X. */
1186 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1188 /* Is the given value a sign-extended 32-bit value? */
1189 #define IS_SEXT_32BIT_NUM(x) \
1190 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1191 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1193 /* Is the given value a sign-extended 16-bit value? */
1194 #define IS_SEXT_16BIT_NUM(x) \
1195 (((x) &~ (offsetT) 0x7fff) == 0 \
1196 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1198 /* Is the given value a sign-extended 12-bit value? */
1199 #define IS_SEXT_12BIT_NUM(x) \
1200 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1202 /* Is the given value a sign-extended 9-bit value? */
1203 #define IS_SEXT_9BIT_NUM(x) \
1204 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1206 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1207 #define IS_ZEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0xffffffff) == 0 \
1209 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1211 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1213 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1214 (((STRUCT) >> (SHIFT)) & (MASK))
1216 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1217 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1219 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1220 : EXTRACT_BITS ((INSN).insn_opcode, \
1221 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1222 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1223 EXTRACT_BITS ((INSN).insn_opcode, \
1224 MIPS16OP_MASK_##FIELD, \
1225 MIPS16OP_SH_##FIELD)
1227 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1228 #define MIPS16_EXTEND (0xf000U << 16)
1230 /* Whether or not we are emitting a branch-likely macro. */
1231 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1233 /* Global variables used when generating relaxable macros. See the
1234 comment above RELAX_ENCODE for more details about how relaxation
1237 /* 0 if we're not emitting a relaxable macro.
1238 1 if we're emitting the first of the two relaxation alternatives.
1239 2 if we're emitting the second alternative. */
1242 /* The first relaxable fixup in the current frag. (In other words,
1243 the first fixup that refers to relaxable code.) */
1246 /* sizes[0] says how many bytes of the first alternative are stored in
1247 the current frag. Likewise sizes[1] for the second alternative. */
1248 unsigned int sizes
[2];
1250 /* The symbol on which the choice of sequence depends. */
1254 /* Global variables used to decide whether a macro needs a warning. */
1256 /* True if the macro is in a branch delay slot. */
1257 bfd_boolean delay_slot_p
;
1259 /* Set to the length in bytes required if the macro is in a delay slot
1260 that requires a specific length of instruction, otherwise zero. */
1261 unsigned int delay_slot_length
;
1263 /* For relaxable macros, sizes[0] is the length of the first alternative
1264 in bytes and sizes[1] is the length of the second alternative.
1265 For non-relaxable macros, both elements give the length of the
1267 unsigned int sizes
[2];
1269 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1270 instruction of the first alternative in bytes and first_insn_sizes[1]
1271 is the length of the first instruction of the second alternative.
1272 For non-relaxable macros, both elements give the length of the first
1273 instruction in bytes.
1275 Set to zero if we haven't yet seen the first instruction. */
1276 unsigned int first_insn_sizes
[2];
1278 /* For relaxable macros, insns[0] is the number of instructions for the
1279 first alternative and insns[1] is the number of instructions for the
1282 For non-relaxable macros, both elements give the number of
1283 instructions for the macro. */
1284 unsigned int insns
[2];
1286 /* The first variant frag for this macro. */
1288 } mips_macro_warning
;
1290 /* Prototypes for static functions. */
1292 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1294 static void append_insn
1295 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1296 bfd_boolean expansionp
);
1297 static void mips_no_prev_insn (void);
1298 static void macro_build (expressionS
*, const char *, const char *, ...);
1299 static void mips16_macro_build
1300 (expressionS
*, const char *, const char *, va_list *);
1301 static void load_register (int, expressionS
*, int);
1302 static void macro_start (void);
1303 static void macro_end (void);
1304 static void macro (struct mips_cl_insn
*ip
, char *str
);
1305 static void mips16_macro (struct mips_cl_insn
* ip
);
1306 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1307 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1308 static void mips16_immed
1309 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1310 unsigned int, unsigned long *);
1311 static size_t my_getSmallExpression
1312 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1313 static void my_getExpression (expressionS
*, char *);
1314 static void s_align (int);
1315 static void s_change_sec (int);
1316 static void s_change_section (int);
1317 static void s_cons (int);
1318 static void s_float_cons (int);
1319 static void s_mips_globl (int);
1320 static void s_option (int);
1321 static void s_mipsset (int);
1322 static void s_abicalls (int);
1323 static void s_cpload (int);
1324 static void s_cpsetup (int);
1325 static void s_cplocal (int);
1326 static void s_cprestore (int);
1327 static void s_cpreturn (int);
1328 static void s_dtprelword (int);
1329 static void s_dtpreldword (int);
1330 static void s_tprelword (int);
1331 static void s_tpreldword (int);
1332 static void s_gpvalue (int);
1333 static void s_gpword (int);
1334 static void s_gpdword (int);
1335 static void s_ehword (int);
1336 static void s_cpadd (int);
1337 static void s_insn (int);
1338 static void s_nan (int);
1339 static void s_module (int);
1340 static void s_mips_ent (int);
1341 static void s_mips_end (int);
1342 static void s_mips_frame (int);
1343 static void s_mips_mask (int reg_type
);
1344 static void s_mips_stab (int);
1345 static void s_mips_weakext (int);
1346 static void s_mips_file (int);
1347 static void s_mips_loc (int);
1348 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1349 static int relaxed_branch_length (fragS
*, asection
*, int);
1350 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1351 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1352 static void file_mips_check_options (void);
1354 /* Table and functions used to map between CPU/ISA names, and
1355 ISA levels, and CPU numbers. */
1357 struct mips_cpu_info
1359 const char *name
; /* CPU or ISA name. */
1360 int flags
; /* MIPS_CPU_* flags. */
1361 int ase
; /* Set of ASEs implemented by the CPU. */
1362 int isa
; /* ISA level. */
1363 int cpu
; /* CPU number (default CPU if ISA). */
1366 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1368 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1369 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1370 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1372 /* Command-line options. */
1373 const char *md_shortopts
= "O::g::G:";
1377 OPTION_MARCH
= OPTION_MD_BASE
,
1409 OPTION_NO_SMARTMIPS
,
1417 OPTION_NO_MICROMIPS
,
1420 OPTION_COMPAT_ARCH_BASE
,
1429 OPTION_M7000_HILO_FIX
,
1430 OPTION_MNO_7000_HILO_FIX
,
1434 OPTION_NO_FIX_RM7000
,
1435 OPTION_FIX_LOONGSON2F_JUMP
,
1436 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1437 OPTION_FIX_LOONGSON2F_NOP
,
1438 OPTION_NO_FIX_LOONGSON2F_NOP
,
1440 OPTION_NO_FIX_VR4120
,
1442 OPTION_NO_FIX_VR4130
,
1443 OPTION_FIX_CN63XXP1
,
1444 OPTION_NO_FIX_CN63XXP1
,
1451 OPTION_CONSTRUCT_FLOATS
,
1452 OPTION_NO_CONSTRUCT_FLOATS
,
1456 OPTION_RELAX_BRANCH
,
1457 OPTION_NO_RELAX_BRANCH
,
1466 OPTION_SINGLE_FLOAT
,
1467 OPTION_DOUBLE_FLOAT
,
1480 OPTION_MVXWORKS_PIC
,
1483 OPTION_NO_ODD_SPREG
,
1487 struct option md_longopts
[] =
1489 /* Options which specify architecture. */
1490 {"march", required_argument
, NULL
, OPTION_MARCH
},
1491 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1492 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1493 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1494 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1495 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1496 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1497 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1498 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1499 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1500 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1501 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1502 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1503 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1504 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1505 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1506 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1507 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1509 /* Options which specify Application Specific Extensions (ASEs). */
1510 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1511 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1512 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1513 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1514 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1515 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1516 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1517 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1518 {"mmt", no_argument
, NULL
, OPTION_MT
},
1519 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1520 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1521 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1522 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1523 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1524 {"meva", no_argument
, NULL
, OPTION_EVA
},
1525 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1526 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1527 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1528 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1529 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1530 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1531 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1532 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1533 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1534 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1535 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1537 /* Old-style architecture options. Don't add more of these. */
1538 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1539 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1540 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1541 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1542 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1543 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1544 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1545 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1547 /* Options which enable bug fixes. */
1548 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1549 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1550 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1551 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1552 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1553 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1554 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1555 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1556 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1557 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1558 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1559 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1560 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1561 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1562 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1563 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1564 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1566 /* Miscellaneous options. */
1567 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1568 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1569 {"break", no_argument
, NULL
, OPTION_BREAK
},
1570 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1571 {"EB", no_argument
, NULL
, OPTION_EB
},
1572 {"EL", no_argument
, NULL
, OPTION_EL
},
1573 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1574 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1575 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1576 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1577 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1578 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1579 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1580 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1581 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1582 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1583 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1584 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1585 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1586 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1587 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1588 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1589 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1590 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1591 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1592 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1593 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1595 /* Strictly speaking this next option is ELF specific,
1596 but we allow it for other ports as well in order to
1597 make testing easier. */
1598 {"32", no_argument
, NULL
, OPTION_32
},
1600 /* ELF-specific options. */
1601 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1602 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1603 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1604 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1605 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1606 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1607 {"n32", no_argument
, NULL
, OPTION_N32
},
1608 {"64", no_argument
, NULL
, OPTION_64
},
1609 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1610 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1611 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1612 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1613 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1614 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1616 {NULL
, no_argument
, NULL
, 0}
1618 size_t md_longopts_size
= sizeof (md_longopts
);
1620 /* Information about either an Application Specific Extension or an
1621 optional architecture feature that, for simplicity, we treat in the
1622 same way as an ASE. */
1625 /* The name of the ASE, used in both the command-line and .set options. */
1628 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1629 and 64-bit architectures, the flags here refer to the subset that
1630 is available on both. */
1633 /* The ASE_* flag used for instructions that are available on 64-bit
1634 architectures but that are not included in FLAGS. */
1635 unsigned int flags64
;
1637 /* The command-line options that turn the ASE on and off. */
1641 /* The minimum required architecture revisions for MIPS32, MIPS64,
1642 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1645 int micromips32_rev
;
1646 int micromips64_rev
;
1648 /* The architecture where the ASE was removed or -1 if the extension has not
1653 /* A table of all supported ASEs. */
1654 static const struct mips_ase mips_ases
[] = {
1655 { "dsp", ASE_DSP
, ASE_DSP64
,
1656 OPTION_DSP
, OPTION_NO_DSP
,
1660 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1661 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1665 { "eva", ASE_EVA
, 0,
1666 OPTION_EVA
, OPTION_NO_EVA
,
1670 { "mcu", ASE_MCU
, 0,
1671 OPTION_MCU
, OPTION_NO_MCU
,
1675 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1676 { "mdmx", ASE_MDMX
, 0,
1677 OPTION_MDMX
, OPTION_NO_MDMX
,
1681 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1682 { "mips3d", ASE_MIPS3D
, 0,
1683 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1688 OPTION_MT
, OPTION_NO_MT
,
1692 { "smartmips", ASE_SMARTMIPS
, 0,
1693 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1697 { "virt", ASE_VIRT
, ASE_VIRT64
,
1698 OPTION_VIRT
, OPTION_NO_VIRT
,
1702 { "msa", ASE_MSA
, ASE_MSA64
,
1703 OPTION_MSA
, OPTION_NO_MSA
,
1707 { "xpa", ASE_XPA
, 0,
1708 OPTION_XPA
, OPTION_NO_XPA
,
1713 /* The set of ASEs that require -mfp64. */
1714 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1716 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1717 static const unsigned int mips_ase_groups
[] = {
1723 The following pseudo-ops from the Kane and Heinrich MIPS book
1724 should be defined here, but are currently unsupported: .alias,
1725 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1727 The following pseudo-ops from the Kane and Heinrich MIPS book are
1728 specific to the type of debugging information being generated, and
1729 should be defined by the object format: .aent, .begin, .bend,
1730 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1733 The following pseudo-ops from the Kane and Heinrich MIPS book are
1734 not MIPS CPU specific, but are also not specific to the object file
1735 format. This file is probably the best place to define them, but
1736 they are not currently supported: .asm0, .endr, .lab, .struct. */
1738 static const pseudo_typeS mips_pseudo_table
[] =
1740 /* MIPS specific pseudo-ops. */
1741 {"option", s_option
, 0},
1742 {"set", s_mipsset
, 0},
1743 {"rdata", s_change_sec
, 'r'},
1744 {"sdata", s_change_sec
, 's'},
1745 {"livereg", s_ignore
, 0},
1746 {"abicalls", s_abicalls
, 0},
1747 {"cpload", s_cpload
, 0},
1748 {"cpsetup", s_cpsetup
, 0},
1749 {"cplocal", s_cplocal
, 0},
1750 {"cprestore", s_cprestore
, 0},
1751 {"cpreturn", s_cpreturn
, 0},
1752 {"dtprelword", s_dtprelword
, 0},
1753 {"dtpreldword", s_dtpreldword
, 0},
1754 {"tprelword", s_tprelword
, 0},
1755 {"tpreldword", s_tpreldword
, 0},
1756 {"gpvalue", s_gpvalue
, 0},
1757 {"gpword", s_gpword
, 0},
1758 {"gpdword", s_gpdword
, 0},
1759 {"ehword", s_ehword
, 0},
1760 {"cpadd", s_cpadd
, 0},
1761 {"insn", s_insn
, 0},
1763 {"module", s_module
, 0},
1765 /* Relatively generic pseudo-ops that happen to be used on MIPS
1767 {"asciiz", stringer
, 8 + 1},
1768 {"bss", s_change_sec
, 'b'},
1770 {"half", s_cons
, 1},
1771 {"dword", s_cons
, 3},
1772 {"weakext", s_mips_weakext
, 0},
1773 {"origin", s_org
, 0},
1774 {"repeat", s_rept
, 0},
1776 /* For MIPS this is non-standard, but we define it for consistency. */
1777 {"sbss", s_change_sec
, 'B'},
1779 /* These pseudo-ops are defined in read.c, but must be overridden
1780 here for one reason or another. */
1781 {"align", s_align
, 0},
1782 {"byte", s_cons
, 0},
1783 {"data", s_change_sec
, 'd'},
1784 {"double", s_float_cons
, 'd'},
1785 {"float", s_float_cons
, 'f'},
1786 {"globl", s_mips_globl
, 0},
1787 {"global", s_mips_globl
, 0},
1788 {"hword", s_cons
, 1},
1790 {"long", s_cons
, 2},
1791 {"octa", s_cons
, 4},
1792 {"quad", s_cons
, 3},
1793 {"section", s_change_section
, 0},
1794 {"short", s_cons
, 1},
1795 {"single", s_float_cons
, 'f'},
1796 {"stabd", s_mips_stab
, 'd'},
1797 {"stabn", s_mips_stab
, 'n'},
1798 {"stabs", s_mips_stab
, 's'},
1799 {"text", s_change_sec
, 't'},
1800 {"word", s_cons
, 2},
1802 { "extern", ecoff_directive_extern
, 0},
1807 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1809 /* These pseudo-ops should be defined by the object file format.
1810 However, a.out doesn't support them, so we have versions here. */
1811 {"aent", s_mips_ent
, 1},
1812 {"bgnb", s_ignore
, 0},
1813 {"end", s_mips_end
, 0},
1814 {"endb", s_ignore
, 0},
1815 {"ent", s_mips_ent
, 0},
1816 {"file", s_mips_file
, 0},
1817 {"fmask", s_mips_mask
, 'F'},
1818 {"frame", s_mips_frame
, 0},
1819 {"loc", s_mips_loc
, 0},
1820 {"mask", s_mips_mask
, 'R'},
1821 {"verstamp", s_ignore
, 0},
1825 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1826 purpose of the `.dc.a' internal pseudo-op. */
1829 mips_address_bytes (void)
1831 file_mips_check_options ();
1832 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1835 extern void pop_insert (const pseudo_typeS
*);
1838 mips_pop_insert (void)
1840 pop_insert (mips_pseudo_table
);
1841 if (! ECOFF_DEBUGGING
)
1842 pop_insert (mips_nonecoff_pseudo_table
);
1845 /* Symbols labelling the current insn. */
1847 struct insn_label_list
1849 struct insn_label_list
*next
;
1853 static struct insn_label_list
*free_insn_labels
;
1854 #define label_list tc_segment_info_data.labels
1856 static void mips_clear_insn_labels (void);
1857 static void mips_mark_labels (void);
1858 static void mips_compressed_mark_labels (void);
1861 mips_clear_insn_labels (void)
1863 register struct insn_label_list
**pl
;
1864 segment_info_type
*si
;
1868 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1871 si
= seg_info (now_seg
);
1872 *pl
= si
->label_list
;
1873 si
->label_list
= NULL
;
1877 /* Mark instruction labels in MIPS16/microMIPS mode. */
1880 mips_mark_labels (void)
1882 if (HAVE_CODE_COMPRESSION
)
1883 mips_compressed_mark_labels ();
1886 static char *expr_end
;
1888 /* An expression in a macro instruction. This is set by mips_ip and
1889 mips16_ip and when populated is always an O_constant. */
1891 static expressionS imm_expr
;
1893 /* The relocatable field in an instruction and the relocs associated
1894 with it. These variables are used for instructions like LUI and
1895 JAL as well as true offsets. They are also used for address
1896 operands in macros. */
1898 static expressionS offset_expr
;
1899 static bfd_reloc_code_real_type offset_reloc
[3]
1900 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1902 /* This is set to the resulting size of the instruction to be produced
1903 by mips16_ip if an explicit extension is used or by mips_ip if an
1904 explicit size is supplied. */
1906 static unsigned int forced_insn_length
;
1908 /* True if we are assembling an instruction. All dot symbols defined during
1909 this time should be treated as code labels. */
1911 static bfd_boolean mips_assembling_insn
;
1913 /* The pdr segment for per procedure frame/regmask info. Not used for
1916 static segT pdr_seg
;
1918 /* The default target format to use. */
1920 #if defined (TE_FreeBSD)
1921 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1922 #elif defined (TE_TMIPS)
1923 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1925 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1929 mips_target_format (void)
1931 switch (OUTPUT_FLAVOR
)
1933 case bfd_target_elf_flavour
:
1935 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1936 return (target_big_endian
1937 ? "elf32-bigmips-vxworks"
1938 : "elf32-littlemips-vxworks");
1940 return (target_big_endian
1941 ? (HAVE_64BIT_OBJECTS
1942 ? ELF_TARGET ("elf64-", "big")
1944 ? ELF_TARGET ("elf32-n", "big")
1945 : ELF_TARGET ("elf32-", "big")))
1946 : (HAVE_64BIT_OBJECTS
1947 ? ELF_TARGET ("elf64-", "little")
1949 ? ELF_TARGET ("elf32-n", "little")
1950 : ELF_TARGET ("elf32-", "little"))));
1957 /* Return the ISA revision that is currently in use, or 0 if we are
1958 generating code for MIPS V or below. */
1963 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1966 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
1969 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
1972 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
1975 /* microMIPS implies revision 2 or above. */
1976 if (mips_opts
.micromips
)
1979 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1985 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1988 mips_ase_mask (unsigned int flags
)
1992 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1993 if (flags
& mips_ase_groups
[i
])
1994 flags
|= mips_ase_groups
[i
];
1998 /* Check whether the current ISA supports ASE. Issue a warning if
2002 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2006 static unsigned int warned_isa
;
2007 static unsigned int warned_fp32
;
2009 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2010 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2012 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2013 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2014 && (warned_isa
& ase
->flags
) != ase
->flags
)
2016 warned_isa
|= ase
->flags
;
2017 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2018 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2020 as_warn (_("the %d-bit %s architecture does not support the"
2021 " `%s' extension"), size
, base
, ase
->name
);
2023 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2024 ase
->name
, base
, size
, min_rev
);
2026 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2027 && (warned_isa
& ase
->flags
) != ase
->flags
)
2029 warned_isa
|= ase
->flags
;
2030 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2031 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2032 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2033 ase
->name
, base
, size
, ase
->rem_rev
);
2036 if ((ase
->flags
& FP64_ASES
)
2037 && mips_opts
.fp
!= 64
2038 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2040 warned_fp32
|= ase
->flags
;
2041 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2045 /* Check all enabled ASEs to see whether they are supported by the
2046 chosen architecture. */
2049 mips_check_isa_supports_ases (void)
2051 unsigned int i
, mask
;
2053 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2055 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2056 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2057 mips_check_isa_supports_ase (&mips_ases
[i
]);
2061 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2062 that were affected. */
2065 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2066 bfd_boolean enabled_p
)
2070 mask
= mips_ase_mask (ase
->flags
);
2073 opts
->ase
|= ase
->flags
;
2077 /* Return the ASE called NAME, or null if none. */
2079 static const struct mips_ase
*
2080 mips_lookup_ase (const char *name
)
2084 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2085 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2086 return &mips_ases
[i
];
2090 /* Return the length of a microMIPS instruction in bytes. If bits of
2091 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
2092 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
2093 major opcode) will require further modifications to the opcode
2096 static inline unsigned int
2097 micromips_insn_length (const struct mips_opcode
*mo
)
2099 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2102 /* Return the length of MIPS16 instruction OPCODE. */
2104 static inline unsigned int
2105 mips16_opcode_length (unsigned long opcode
)
2107 return (opcode
>> 16) == 0 ? 2 : 4;
2110 /* Return the length of instruction INSN. */
2112 static inline unsigned int
2113 insn_length (const struct mips_cl_insn
*insn
)
2115 if (mips_opts
.micromips
)
2116 return micromips_insn_length (insn
->insn_mo
);
2117 else if (mips_opts
.mips16
)
2118 return mips16_opcode_length (insn
->insn_opcode
);
2123 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2126 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2131 insn
->insn_opcode
= mo
->match
;
2134 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2135 insn
->fixp
[i
] = NULL
;
2136 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2137 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2138 insn
->mips16_absolute_jump_p
= 0;
2139 insn
->complete_p
= 0;
2140 insn
->cleared_p
= 0;
2143 /* Get a list of all the operands in INSN. */
2145 static const struct mips_operand_array
*
2146 insn_operands (const struct mips_cl_insn
*insn
)
2148 if (insn
->insn_mo
>= &mips_opcodes
[0]
2149 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2150 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2152 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2153 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2154 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2156 if (insn
->insn_mo
>= µmips_opcodes
[0]
2157 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2158 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2163 /* Get a description of operand OPNO of INSN. */
2165 static const struct mips_operand
*
2166 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2168 const struct mips_operand_array
*operands
;
2170 operands
= insn_operands (insn
);
2171 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2173 return operands
->operand
[opno
];
2176 /* Install UVAL as the value of OPERAND in INSN. */
2179 insn_insert_operand (struct mips_cl_insn
*insn
,
2180 const struct mips_operand
*operand
, unsigned int uval
)
2182 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2185 /* Extract the value of OPERAND from INSN. */
2187 static inline unsigned
2188 insn_extract_operand (const struct mips_cl_insn
*insn
,
2189 const struct mips_operand
*operand
)
2191 return mips_extract_operand (operand
, insn
->insn_opcode
);
2194 /* Record the current MIPS16/microMIPS mode in now_seg. */
2197 mips_record_compressed_mode (void)
2199 segment_info_type
*si
;
2201 si
= seg_info (now_seg
);
2202 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2203 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2204 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2205 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2208 /* Read a standard MIPS instruction from BUF. */
2210 static unsigned long
2211 read_insn (char *buf
)
2213 if (target_big_endian
)
2214 return bfd_getb32 ((bfd_byte
*) buf
);
2216 return bfd_getl32 ((bfd_byte
*) buf
);
2219 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2223 write_insn (char *buf
, unsigned int insn
)
2225 md_number_to_chars (buf
, insn
, 4);
2229 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2230 has length LENGTH. */
2232 static unsigned long
2233 read_compressed_insn (char *buf
, unsigned int length
)
2239 for (i
= 0; i
< length
; i
+= 2)
2242 if (target_big_endian
)
2243 insn
|= bfd_getb16 ((char *) buf
);
2245 insn
|= bfd_getl16 ((char *) buf
);
2251 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2252 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2255 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2259 for (i
= 0; i
< length
; i
+= 2)
2260 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2261 return buf
+ length
;
2264 /* Install INSN at the location specified by its "frag" and "where" fields. */
2267 install_insn (const struct mips_cl_insn
*insn
)
2269 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2270 if (HAVE_CODE_COMPRESSION
)
2271 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2273 write_insn (f
, insn
->insn_opcode
);
2274 mips_record_compressed_mode ();
2277 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2278 and install the opcode in the new location. */
2281 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2286 insn
->where
= where
;
2287 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2288 if (insn
->fixp
[i
] != NULL
)
2290 insn
->fixp
[i
]->fx_frag
= frag
;
2291 insn
->fixp
[i
]->fx_where
= where
;
2293 install_insn (insn
);
2296 /* Add INSN to the end of the output. */
2299 add_fixed_insn (struct mips_cl_insn
*insn
)
2301 char *f
= frag_more (insn_length (insn
));
2302 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2305 /* Start a variant frag and move INSN to the start of the variant part,
2306 marking it as fixed. The other arguments are as for frag_var. */
2309 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2310 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2312 frag_grow (max_chars
);
2313 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2315 frag_var (rs_machine_dependent
, max_chars
, var
,
2316 subtype
, symbol
, offset
, NULL
);
2319 /* Insert N copies of INSN into the history buffer, starting at
2320 position FIRST. Neither FIRST nor N need to be clipped. */
2323 insert_into_history (unsigned int first
, unsigned int n
,
2324 const struct mips_cl_insn
*insn
)
2326 if (mips_relax
.sequence
!= 2)
2330 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2332 history
[i
] = history
[i
- n
];
2338 /* Clear the error in insn_error. */
2341 clear_insn_error (void)
2343 memset (&insn_error
, 0, sizeof (insn_error
));
2346 /* Possibly record error message MSG for the current instruction.
2347 If the error is about a particular argument, ARGNUM is the 1-based
2348 number of that argument, otherwise it is 0. FORMAT is the format
2349 of MSG. Return true if MSG was used, false if the current message
2353 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2358 /* Give priority to errors against specific arguments, and to
2359 the first whole-instruction message. */
2365 /* Keep insn_error if it is against a later argument. */
2366 if (argnum
< insn_error
.min_argnum
)
2369 /* If both errors are against the same argument but are different,
2370 give up on reporting a specific error for this argument.
2371 See the comment about mips_insn_error for details. */
2372 if (argnum
== insn_error
.min_argnum
2374 && strcmp (insn_error
.msg
, msg
) != 0)
2377 insn_error
.min_argnum
+= 1;
2381 insn_error
.min_argnum
= argnum
;
2382 insn_error
.format
= format
;
2383 insn_error
.msg
= msg
;
2387 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2388 as for set_insn_error_format. */
2391 set_insn_error (int argnum
, const char *msg
)
2393 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2396 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2397 as for set_insn_error_format. */
2400 set_insn_error_i (int argnum
, const char *msg
, int i
)
2402 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2406 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2407 are as for set_insn_error_format. */
2410 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2412 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2414 insn_error
.u
.ss
[0] = s1
;
2415 insn_error
.u
.ss
[1] = s2
;
2419 /* Report the error in insn_error, which is against assembly code STR. */
2422 report_insn_error (const char *str
)
2426 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2427 switch (insn_error
.format
)
2434 as_bad (msg
, insn_error
.u
.i
, str
);
2438 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2443 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2444 the idea is to make it obvious at a glance that each errata is
2448 init_vr4120_conflicts (void)
2450 #define CONFLICT(FIRST, SECOND) \
2451 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2453 /* Errata 21 - [D]DIV[U] after [D]MACC */
2454 CONFLICT (MACC
, DIV
);
2455 CONFLICT (DMACC
, DIV
);
2457 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2458 CONFLICT (DMULT
, DMULT
);
2459 CONFLICT (DMULT
, DMACC
);
2460 CONFLICT (DMACC
, DMULT
);
2461 CONFLICT (DMACC
, DMACC
);
2463 /* Errata 24 - MT{LO,HI} after [D]MACC */
2464 CONFLICT (MACC
, MTHILO
);
2465 CONFLICT (DMACC
, MTHILO
);
2467 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2468 instruction is executed immediately after a MACC or DMACC
2469 instruction, the result of [either instruction] is incorrect." */
2470 CONFLICT (MACC
, MULT
);
2471 CONFLICT (MACC
, DMULT
);
2472 CONFLICT (DMACC
, MULT
);
2473 CONFLICT (DMACC
, DMULT
);
2475 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2476 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2477 DDIV or DDIVU instruction, the result of the MACC or
2478 DMACC instruction is incorrect.". */
2479 CONFLICT (DMULT
, MACC
);
2480 CONFLICT (DMULT
, DMACC
);
2481 CONFLICT (DIV
, MACC
);
2482 CONFLICT (DIV
, DMACC
);
2492 #define RNUM_MASK 0x00000ff
2493 #define RTYPE_MASK 0x0ffff00
2494 #define RTYPE_NUM 0x0000100
2495 #define RTYPE_FPU 0x0000200
2496 #define RTYPE_FCC 0x0000400
2497 #define RTYPE_VEC 0x0000800
2498 #define RTYPE_GP 0x0001000
2499 #define RTYPE_CP0 0x0002000
2500 #define RTYPE_PC 0x0004000
2501 #define RTYPE_ACC 0x0008000
2502 #define RTYPE_CCC 0x0010000
2503 #define RTYPE_VI 0x0020000
2504 #define RTYPE_VF 0x0040000
2505 #define RTYPE_R5900_I 0x0080000
2506 #define RTYPE_R5900_Q 0x0100000
2507 #define RTYPE_R5900_R 0x0200000
2508 #define RTYPE_R5900_ACC 0x0400000
2509 #define RTYPE_MSA 0x0800000
2510 #define RWARN 0x8000000
2512 #define GENERIC_REGISTER_NUMBERS \
2513 {"$0", RTYPE_NUM | 0}, \
2514 {"$1", RTYPE_NUM | 1}, \
2515 {"$2", RTYPE_NUM | 2}, \
2516 {"$3", RTYPE_NUM | 3}, \
2517 {"$4", RTYPE_NUM | 4}, \
2518 {"$5", RTYPE_NUM | 5}, \
2519 {"$6", RTYPE_NUM | 6}, \
2520 {"$7", RTYPE_NUM | 7}, \
2521 {"$8", RTYPE_NUM | 8}, \
2522 {"$9", RTYPE_NUM | 9}, \
2523 {"$10", RTYPE_NUM | 10}, \
2524 {"$11", RTYPE_NUM | 11}, \
2525 {"$12", RTYPE_NUM | 12}, \
2526 {"$13", RTYPE_NUM | 13}, \
2527 {"$14", RTYPE_NUM | 14}, \
2528 {"$15", RTYPE_NUM | 15}, \
2529 {"$16", RTYPE_NUM | 16}, \
2530 {"$17", RTYPE_NUM | 17}, \
2531 {"$18", RTYPE_NUM | 18}, \
2532 {"$19", RTYPE_NUM | 19}, \
2533 {"$20", RTYPE_NUM | 20}, \
2534 {"$21", RTYPE_NUM | 21}, \
2535 {"$22", RTYPE_NUM | 22}, \
2536 {"$23", RTYPE_NUM | 23}, \
2537 {"$24", RTYPE_NUM | 24}, \
2538 {"$25", RTYPE_NUM | 25}, \
2539 {"$26", RTYPE_NUM | 26}, \
2540 {"$27", RTYPE_NUM | 27}, \
2541 {"$28", RTYPE_NUM | 28}, \
2542 {"$29", RTYPE_NUM | 29}, \
2543 {"$30", RTYPE_NUM | 30}, \
2544 {"$31", RTYPE_NUM | 31}
2546 #define FPU_REGISTER_NAMES \
2547 {"$f0", RTYPE_FPU | 0}, \
2548 {"$f1", RTYPE_FPU | 1}, \
2549 {"$f2", RTYPE_FPU | 2}, \
2550 {"$f3", RTYPE_FPU | 3}, \
2551 {"$f4", RTYPE_FPU | 4}, \
2552 {"$f5", RTYPE_FPU | 5}, \
2553 {"$f6", RTYPE_FPU | 6}, \
2554 {"$f7", RTYPE_FPU | 7}, \
2555 {"$f8", RTYPE_FPU | 8}, \
2556 {"$f9", RTYPE_FPU | 9}, \
2557 {"$f10", RTYPE_FPU | 10}, \
2558 {"$f11", RTYPE_FPU | 11}, \
2559 {"$f12", RTYPE_FPU | 12}, \
2560 {"$f13", RTYPE_FPU | 13}, \
2561 {"$f14", RTYPE_FPU | 14}, \
2562 {"$f15", RTYPE_FPU | 15}, \
2563 {"$f16", RTYPE_FPU | 16}, \
2564 {"$f17", RTYPE_FPU | 17}, \
2565 {"$f18", RTYPE_FPU | 18}, \
2566 {"$f19", RTYPE_FPU | 19}, \
2567 {"$f20", RTYPE_FPU | 20}, \
2568 {"$f21", RTYPE_FPU | 21}, \
2569 {"$f22", RTYPE_FPU | 22}, \
2570 {"$f23", RTYPE_FPU | 23}, \
2571 {"$f24", RTYPE_FPU | 24}, \
2572 {"$f25", RTYPE_FPU | 25}, \
2573 {"$f26", RTYPE_FPU | 26}, \
2574 {"$f27", RTYPE_FPU | 27}, \
2575 {"$f28", RTYPE_FPU | 28}, \
2576 {"$f29", RTYPE_FPU | 29}, \
2577 {"$f30", RTYPE_FPU | 30}, \
2578 {"$f31", RTYPE_FPU | 31}
2580 #define FPU_CONDITION_CODE_NAMES \
2581 {"$fcc0", RTYPE_FCC | 0}, \
2582 {"$fcc1", RTYPE_FCC | 1}, \
2583 {"$fcc2", RTYPE_FCC | 2}, \
2584 {"$fcc3", RTYPE_FCC | 3}, \
2585 {"$fcc4", RTYPE_FCC | 4}, \
2586 {"$fcc5", RTYPE_FCC | 5}, \
2587 {"$fcc6", RTYPE_FCC | 6}, \
2588 {"$fcc7", RTYPE_FCC | 7}
2590 #define COPROC_CONDITION_CODE_NAMES \
2591 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2592 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2593 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2594 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2595 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2596 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2597 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2598 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2600 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2601 {"$a4", RTYPE_GP | 8}, \
2602 {"$a5", RTYPE_GP | 9}, \
2603 {"$a6", RTYPE_GP | 10}, \
2604 {"$a7", RTYPE_GP | 11}, \
2605 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2606 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2607 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2608 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2609 {"$t0", RTYPE_GP | 12}, \
2610 {"$t1", RTYPE_GP | 13}, \
2611 {"$t2", RTYPE_GP | 14}, \
2612 {"$t3", RTYPE_GP | 15}
2614 #define O32_SYMBOLIC_REGISTER_NAMES \
2615 {"$t0", RTYPE_GP | 8}, \
2616 {"$t1", RTYPE_GP | 9}, \
2617 {"$t2", RTYPE_GP | 10}, \
2618 {"$t3", RTYPE_GP | 11}, \
2619 {"$t4", RTYPE_GP | 12}, \
2620 {"$t5", RTYPE_GP | 13}, \
2621 {"$t6", RTYPE_GP | 14}, \
2622 {"$t7", RTYPE_GP | 15}, \
2623 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2624 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2625 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2626 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2628 /* Remaining symbolic register names */
2629 #define SYMBOLIC_REGISTER_NAMES \
2630 {"$zero", RTYPE_GP | 0}, \
2631 {"$at", RTYPE_GP | 1}, \
2632 {"$AT", RTYPE_GP | 1}, \
2633 {"$v0", RTYPE_GP | 2}, \
2634 {"$v1", RTYPE_GP | 3}, \
2635 {"$a0", RTYPE_GP | 4}, \
2636 {"$a1", RTYPE_GP | 5}, \
2637 {"$a2", RTYPE_GP | 6}, \
2638 {"$a3", RTYPE_GP | 7}, \
2639 {"$s0", RTYPE_GP | 16}, \
2640 {"$s1", RTYPE_GP | 17}, \
2641 {"$s2", RTYPE_GP | 18}, \
2642 {"$s3", RTYPE_GP | 19}, \
2643 {"$s4", RTYPE_GP | 20}, \
2644 {"$s5", RTYPE_GP | 21}, \
2645 {"$s6", RTYPE_GP | 22}, \
2646 {"$s7", RTYPE_GP | 23}, \
2647 {"$t8", RTYPE_GP | 24}, \
2648 {"$t9", RTYPE_GP | 25}, \
2649 {"$k0", RTYPE_GP | 26}, \
2650 {"$kt0", RTYPE_GP | 26}, \
2651 {"$k1", RTYPE_GP | 27}, \
2652 {"$kt1", RTYPE_GP | 27}, \
2653 {"$gp", RTYPE_GP | 28}, \
2654 {"$sp", RTYPE_GP | 29}, \
2655 {"$s8", RTYPE_GP | 30}, \
2656 {"$fp", RTYPE_GP | 30}, \
2657 {"$ra", RTYPE_GP | 31}
2659 #define MIPS16_SPECIAL_REGISTER_NAMES \
2660 {"$pc", RTYPE_PC | 0}
2662 #define MDMX_VECTOR_REGISTER_NAMES \
2663 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2664 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2665 {"$v2", RTYPE_VEC | 2}, \
2666 {"$v3", RTYPE_VEC | 3}, \
2667 {"$v4", RTYPE_VEC | 4}, \
2668 {"$v5", RTYPE_VEC | 5}, \
2669 {"$v6", RTYPE_VEC | 6}, \
2670 {"$v7", RTYPE_VEC | 7}, \
2671 {"$v8", RTYPE_VEC | 8}, \
2672 {"$v9", RTYPE_VEC | 9}, \
2673 {"$v10", RTYPE_VEC | 10}, \
2674 {"$v11", RTYPE_VEC | 11}, \
2675 {"$v12", RTYPE_VEC | 12}, \
2676 {"$v13", RTYPE_VEC | 13}, \
2677 {"$v14", RTYPE_VEC | 14}, \
2678 {"$v15", RTYPE_VEC | 15}, \
2679 {"$v16", RTYPE_VEC | 16}, \
2680 {"$v17", RTYPE_VEC | 17}, \
2681 {"$v18", RTYPE_VEC | 18}, \
2682 {"$v19", RTYPE_VEC | 19}, \
2683 {"$v20", RTYPE_VEC | 20}, \
2684 {"$v21", RTYPE_VEC | 21}, \
2685 {"$v22", RTYPE_VEC | 22}, \
2686 {"$v23", RTYPE_VEC | 23}, \
2687 {"$v24", RTYPE_VEC | 24}, \
2688 {"$v25", RTYPE_VEC | 25}, \
2689 {"$v26", RTYPE_VEC | 26}, \
2690 {"$v27", RTYPE_VEC | 27}, \
2691 {"$v28", RTYPE_VEC | 28}, \
2692 {"$v29", RTYPE_VEC | 29}, \
2693 {"$v30", RTYPE_VEC | 30}, \
2694 {"$v31", RTYPE_VEC | 31}
2696 #define R5900_I_NAMES \
2697 {"$I", RTYPE_R5900_I | 0}
2699 #define R5900_Q_NAMES \
2700 {"$Q", RTYPE_R5900_Q | 0}
2702 #define R5900_R_NAMES \
2703 {"$R", RTYPE_R5900_R | 0}
2705 #define R5900_ACC_NAMES \
2706 {"$ACC", RTYPE_R5900_ACC | 0 }
2708 #define MIPS_DSP_ACCUMULATOR_NAMES \
2709 {"$ac0", RTYPE_ACC | 0}, \
2710 {"$ac1", RTYPE_ACC | 1}, \
2711 {"$ac2", RTYPE_ACC | 2}, \
2712 {"$ac3", RTYPE_ACC | 3}
2714 static const struct regname reg_names
[] = {
2715 GENERIC_REGISTER_NUMBERS
,
2717 FPU_CONDITION_CODE_NAMES
,
2718 COPROC_CONDITION_CODE_NAMES
,
2720 /* The $txx registers depends on the abi,
2721 these will be added later into the symbol table from
2722 one of the tables below once mips_abi is set after
2723 parsing of arguments from the command line. */
2724 SYMBOLIC_REGISTER_NAMES
,
2726 MIPS16_SPECIAL_REGISTER_NAMES
,
2727 MDMX_VECTOR_REGISTER_NAMES
,
2732 MIPS_DSP_ACCUMULATOR_NAMES
,
2736 static const struct regname reg_names_o32
[] = {
2737 O32_SYMBOLIC_REGISTER_NAMES
,
2741 static const struct regname reg_names_n32n64
[] = {
2742 N32N64_SYMBOLIC_REGISTER_NAMES
,
2746 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2747 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2748 of these register symbols, return the associated vector register,
2749 otherwise return SYMVAL itself. */
2752 mips_prefer_vec_regno (unsigned int symval
)
2754 if ((symval
& -2) == (RTYPE_GP
| 2))
2755 return RTYPE_VEC
| (symval
& 1);
2759 /* Return true if string [S, E) is a valid register name, storing its
2760 symbol value in *SYMVAL_PTR if so. */
2763 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2768 /* Terminate name. */
2772 /* Look up the name. */
2773 symbol
= symbol_find (s
);
2776 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2779 *symval_ptr
= S_GET_VALUE (symbol
);
2783 /* Return true if the string at *SPTR is a valid register name. Allow it
2784 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2787 When returning true, move *SPTR past the register, store the
2788 register's symbol value in *SYMVAL_PTR and the channel mask in
2789 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2790 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2791 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2794 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2795 unsigned int *channels_ptr
)
2799 unsigned int channels
, symval
, bit
;
2801 /* Find end of name. */
2803 if (is_name_beginner (*e
))
2805 while (is_part_of_name (*e
))
2809 if (!mips_parse_register_1 (s
, e
, &symval
))
2814 /* Eat characters from the end of the string that are valid
2815 channel suffixes. The preceding register must be $ACC or
2816 end with a digit, so there is no ambiguity. */
2819 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2820 if (m
> s
&& m
[-1] == *q
)
2827 || !mips_parse_register_1 (s
, m
, &symval
)
2828 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2833 *symval_ptr
= symval
;
2835 *channels_ptr
= channels
;
2839 /* Check if SPTR points at a valid register specifier according to TYPES.
2840 If so, then return 1, advance S to consume the specifier and store
2841 the register's number in REGNOP, otherwise return 0. */
2844 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2848 if (mips_parse_register (s
, ®no
, NULL
))
2850 if (types
& RTYPE_VEC
)
2851 regno
= mips_prefer_vec_regno (regno
);
2860 as_warn (_("unrecognized register name `%s'"), *s
);
2865 return regno
<= RNUM_MASK
;
2868 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2869 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2872 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2877 for (i
= 0; i
< 4; i
++)
2878 if (*s
== "xyzw"[i
])
2880 *channels
|= 1 << (3 - i
);
2886 /* Token types for parsed operand lists. */
2887 enum mips_operand_token_type
{
2888 /* A plain register, e.g. $f2. */
2891 /* A 4-bit XYZW channel mask. */
2894 /* A constant vector index, e.g. [1]. */
2897 /* A register vector index, e.g. [$2]. */
2900 /* A continuous range of registers, e.g. $s0-$s4. */
2903 /* A (possibly relocated) expression. */
2906 /* A floating-point value. */
2909 /* A single character. This can be '(', ')' or ',', but '(' only appears
2913 /* A doubled character, either "--" or "++". */
2916 /* The end of the operand list. */
2920 /* A parsed operand token. */
2921 struct mips_operand_token
2923 /* The type of token. */
2924 enum mips_operand_token_type type
;
2927 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2930 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2931 unsigned int channels
;
2933 /* The integer value of an OT_INTEGER_INDEX. */
2936 /* The two register symbol values involved in an OT_REG_RANGE. */
2938 unsigned int regno1
;
2939 unsigned int regno2
;
2942 /* The value of an OT_INTEGER. The value is represented as an
2943 expression and the relocation operators that were applied to
2944 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2945 relocation operators were used. */
2948 bfd_reloc_code_real_type relocs
[3];
2951 /* The binary data for an OT_FLOAT constant, and the number of bytes
2954 unsigned char data
[8];
2958 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2963 /* An obstack used to construct lists of mips_operand_tokens. */
2964 static struct obstack mips_operand_tokens
;
2966 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2969 mips_add_token (struct mips_operand_token
*token
,
2970 enum mips_operand_token_type type
)
2973 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2976 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2977 and OT_REG tokens for them if so, and return a pointer to the first
2978 unconsumed character. Return null otherwise. */
2981 mips_parse_base_start (char *s
)
2983 struct mips_operand_token token
;
2984 unsigned int regno
, channels
;
2985 bfd_boolean decrement_p
;
2991 SKIP_SPACE_TABS (s
);
2993 /* Only match "--" as part of a base expression. In other contexts "--X"
2994 is a double negative. */
2995 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2999 SKIP_SPACE_TABS (s
);
3002 /* Allow a channel specifier because that leads to better error messages
3003 than treating something like "$vf0x++" as an expression. */
3004 if (!mips_parse_register (&s
, ®no
, &channels
))
3008 mips_add_token (&token
, OT_CHAR
);
3013 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3016 token
.u
.regno
= regno
;
3017 mips_add_token (&token
, OT_REG
);
3021 token
.u
.channels
= channels
;
3022 mips_add_token (&token
, OT_CHANNELS
);
3025 /* For consistency, only match "++" as part of base expressions too. */
3026 SKIP_SPACE_TABS (s
);
3027 if (s
[0] == '+' && s
[1] == '+')
3031 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3037 /* Parse one or more tokens from S. Return a pointer to the first
3038 unconsumed character on success. Return null if an error was found
3039 and store the error text in insn_error. FLOAT_FORMAT is as for
3040 mips_parse_arguments. */
3043 mips_parse_argument_token (char *s
, char float_format
)
3045 char *end
, *save_in
, *err
;
3046 unsigned int regno1
, regno2
, channels
;
3047 struct mips_operand_token token
;
3049 /* First look for "($reg", since we want to treat that as an
3050 OT_CHAR and OT_REG rather than an expression. */
3051 end
= mips_parse_base_start (s
);
3055 /* Handle other characters that end up as OT_CHARs. */
3056 if (*s
== ')' || *s
== ',')
3059 mips_add_token (&token
, OT_CHAR
);
3064 /* Handle tokens that start with a register. */
3065 if (mips_parse_register (&s
, ®no1
, &channels
))
3069 /* A register and a VU0 channel suffix. */
3070 token
.u
.regno
= regno1
;
3071 mips_add_token (&token
, OT_REG
);
3073 token
.u
.channels
= channels
;
3074 mips_add_token (&token
, OT_CHANNELS
);
3078 SKIP_SPACE_TABS (s
);
3081 /* A register range. */
3083 SKIP_SPACE_TABS (s
);
3084 if (!mips_parse_register (&s
, ®no2
, NULL
))
3086 set_insn_error (0, _("invalid register range"));
3090 token
.u
.reg_range
.regno1
= regno1
;
3091 token
.u
.reg_range
.regno2
= regno2
;
3092 mips_add_token (&token
, OT_REG_RANGE
);
3096 /* Add the register itself. */
3097 token
.u
.regno
= regno1
;
3098 mips_add_token (&token
, OT_REG
);
3100 /* Check for a vector index. */
3104 SKIP_SPACE_TABS (s
);
3105 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3106 mips_add_token (&token
, OT_REG_INDEX
);
3109 expressionS element
;
3111 my_getExpression (&element
, s
);
3112 if (element
.X_op
!= O_constant
)
3114 set_insn_error (0, _("vector element must be constant"));
3118 token
.u
.index
= element
.X_add_number
;
3119 mips_add_token (&token
, OT_INTEGER_INDEX
);
3121 SKIP_SPACE_TABS (s
);
3124 set_insn_error (0, _("missing `]'"));
3134 /* First try to treat expressions as floats. */
3135 save_in
= input_line_pointer
;
3136 input_line_pointer
= s
;
3137 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3138 &token
.u
.flt
.length
);
3139 end
= input_line_pointer
;
3140 input_line_pointer
= save_in
;
3143 set_insn_error (0, err
);
3148 mips_add_token (&token
, OT_FLOAT
);
3153 /* Treat everything else as an integer expression. */
3154 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3155 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3156 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3157 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3159 mips_add_token (&token
, OT_INTEGER
);
3163 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3164 if expressions should be treated as 32-bit floating-point constants,
3165 'd' if they should be treated as 64-bit floating-point constants,
3166 or 0 if they should be treated as integer expressions (the usual case).
3168 Return a list of tokens on success, otherwise return 0. The caller
3169 must obstack_free the list after use. */
3171 static struct mips_operand_token
*
3172 mips_parse_arguments (char *s
, char float_format
)
3174 struct mips_operand_token token
;
3176 SKIP_SPACE_TABS (s
);
3179 s
= mips_parse_argument_token (s
, float_format
);
3182 obstack_free (&mips_operand_tokens
,
3183 obstack_finish (&mips_operand_tokens
));
3186 SKIP_SPACE_TABS (s
);
3188 mips_add_token (&token
, OT_END
);
3189 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3192 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3193 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3196 is_opcode_valid (const struct mips_opcode
*mo
)
3198 int isa
= mips_opts
.isa
;
3199 int ase
= mips_opts
.ase
;
3203 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3204 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3205 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3206 ase
|= mips_ases
[i
].flags64
;
3208 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3211 /* Check whether the instruction or macro requires single-precision or
3212 double-precision floating-point support. Note that this information is
3213 stored differently in the opcode table for insns and macros. */
3214 if (mo
->pinfo
== INSN_MACRO
)
3216 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3217 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3221 fp_s
= mo
->pinfo
& FP_S
;
3222 fp_d
= mo
->pinfo
& FP_D
;
3225 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3228 if (fp_s
&& mips_opts
.soft_float
)
3234 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3235 selected ISA and architecture. */
3238 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3240 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3243 /* Return TRUE if the size of the microMIPS opcode MO matches one
3244 explicitly requested. Always TRUE in the standard MIPS mode. */
3247 is_size_valid (const struct mips_opcode
*mo
)
3249 if (!mips_opts
.micromips
)
3252 if (mips_opts
.insn32
)
3254 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3256 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3259 if (!forced_insn_length
)
3261 if (mo
->pinfo
== INSN_MACRO
)
3263 return forced_insn_length
== micromips_insn_length (mo
);
3266 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3267 of the preceding instruction. Always TRUE in the standard MIPS mode.
3269 We don't accept macros in 16-bit delay slots to avoid a case where
3270 a macro expansion fails because it relies on a preceding 32-bit real
3271 instruction to have matched and does not handle the operands correctly.
3272 The only macros that may expand to 16-bit instructions are JAL that
3273 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3274 and BGT (that likewise cannot be placed in a delay slot) that decay to
3275 a NOP. In all these cases the macros precede any corresponding real
3276 instruction definitions in the opcode table, so they will match in the
3277 second pass where the size of the delay slot is ignored and therefore
3278 produce correct code. */
3281 is_delay_slot_valid (const struct mips_opcode
*mo
)
3283 if (!mips_opts
.micromips
)
3286 if (mo
->pinfo
== INSN_MACRO
)
3287 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3288 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3289 && micromips_insn_length (mo
) != 4)
3291 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3292 && micromips_insn_length (mo
) != 2)
3298 /* For consistency checking, verify that all bits of OPCODE are specified
3299 either by the match/mask part of the instruction definition, or by the
3300 operand list. Also build up a list of operands in OPERANDS.
3302 INSN_BITS says which bits of the instruction are significant.
3303 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3304 provides the mips_operand description of each operand. DECODE_OPERAND
3305 is null for MIPS16 instructions. */
3308 validate_mips_insn (const struct mips_opcode
*opcode
,
3309 unsigned long insn_bits
,
3310 const struct mips_operand
*(*decode_operand
) (const char *),
3311 struct mips_operand_array
*operands
)
3314 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3315 const struct mips_operand
*operand
;
3317 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3318 if ((mask
& opcode
->match
) != opcode
->match
)
3320 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3321 opcode
->name
, opcode
->args
);
3326 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3327 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3328 for (s
= opcode
->args
; *s
; ++s
)
3341 if (!decode_operand
)
3342 operand
= decode_mips16_operand (*s
, FALSE
);
3344 operand
= decode_operand (s
);
3345 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3347 as_bad (_("internal: unknown operand type: %s %s"),
3348 opcode
->name
, opcode
->args
);
3351 gas_assert (opno
< MAX_OPERANDS
);
3352 operands
->operand
[opno
] = operand
;
3353 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3355 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3356 if (operand
->type
== OP_MDMX_IMM_REG
)
3357 /* Bit 5 is the format selector (OB vs QH). The opcode table
3358 has separate entries for each format. */
3359 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3360 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3361 used_bits
&= ~(mask
& 0x700);
3363 /* Skip prefix characters. */
3364 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3369 doubled
= used_bits
& mask
& insn_bits
;
3372 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3373 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3377 undefined
= ~used_bits
& insn_bits
;
3378 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3380 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3381 undefined
, opcode
->name
, opcode
->args
);
3384 used_bits
&= ~insn_bits
;
3387 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3388 used_bits
, opcode
->name
, opcode
->args
);
3394 /* The MIPS16 version of validate_mips_insn. */
3397 validate_mips16_insn (const struct mips_opcode
*opcode
,
3398 struct mips_operand_array
*operands
)
3400 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3402 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3403 instruction. Use TMP to describe the full instruction. */
3404 struct mips_opcode tmp
;
3409 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3411 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3414 /* The microMIPS version of validate_mips_insn. */
3417 validate_micromips_insn (const struct mips_opcode
*opc
,
3418 struct mips_operand_array
*operands
)
3420 unsigned long insn_bits
;
3421 unsigned long major
;
3422 unsigned int length
;
3424 if (opc
->pinfo
== INSN_MACRO
)
3425 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3428 length
= micromips_insn_length (opc
);
3429 if (length
!= 2 && length
!= 4)
3431 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3432 "%s %s"), length
, opc
->name
, opc
->args
);
3435 major
= opc
->match
>> (10 + 8 * (length
- 2));
3436 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3437 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3439 as_bad (_("internal error: bad microMIPS opcode "
3440 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3444 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3445 insn_bits
= 1 << 4 * length
;
3446 insn_bits
<<= 4 * length
;
3448 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3452 /* This function is called once, at assembler startup time. It should set up
3453 all the tables, etc. that the MD part of the assembler will need. */
3458 const char *retval
= NULL
;
3462 if (mips_pic
!= NO_PIC
)
3464 if (g_switch_seen
&& g_switch_value
!= 0)
3465 as_bad (_("-G may not be used in position-independent code"));
3469 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3470 as_warn (_("could not set architecture and machine"));
3472 op_hash
= hash_new ();
3474 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3475 for (i
= 0; i
< NUMOPCODES
;)
3477 const char *name
= mips_opcodes
[i
].name
;
3479 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3482 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3483 mips_opcodes
[i
].name
, retval
);
3484 /* Probably a memory allocation problem? Give up now. */
3485 as_fatal (_("broken assembler, no assembly attempted"));
3489 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3490 decode_mips_operand
, &mips_operands
[i
]))
3492 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3494 create_insn (&nop_insn
, mips_opcodes
+ i
);
3495 if (mips_fix_loongson2f_nop
)
3496 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3497 nop_insn
.fixed_p
= 1;
3501 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3504 mips16_op_hash
= hash_new ();
3505 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3506 bfd_mips16_num_opcodes
);
3509 while (i
< bfd_mips16_num_opcodes
)
3511 const char *name
= mips16_opcodes
[i
].name
;
3513 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3515 as_fatal (_("internal: can't hash `%s': %s"),
3516 mips16_opcodes
[i
].name
, retval
);
3519 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3521 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3523 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3524 mips16_nop_insn
.fixed_p
= 1;
3528 while (i
< bfd_mips16_num_opcodes
3529 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3532 micromips_op_hash
= hash_new ();
3533 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3534 bfd_micromips_num_opcodes
);
3537 while (i
< bfd_micromips_num_opcodes
)
3539 const char *name
= micromips_opcodes
[i
].name
;
3541 retval
= hash_insert (micromips_op_hash
, name
,
3542 (void *) µmips_opcodes
[i
]);
3544 as_fatal (_("internal: can't hash `%s': %s"),
3545 micromips_opcodes
[i
].name
, retval
);
3548 struct mips_cl_insn
*micromips_nop_insn
;
3550 if (!validate_micromips_insn (µmips_opcodes
[i
],
3551 µmips_operands
[i
]))
3554 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3556 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3557 micromips_nop_insn
= µmips_nop16_insn
;
3558 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3559 micromips_nop_insn
= µmips_nop32_insn
;
3563 if (micromips_nop_insn
->insn_mo
== NULL
3564 && strcmp (name
, "nop") == 0)
3566 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3567 micromips_nop_insn
->fixed_p
= 1;
3571 while (++i
< bfd_micromips_num_opcodes
3572 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3576 as_fatal (_("broken assembler, no assembly attempted"));
3578 /* We add all the general register names to the symbol table. This
3579 helps us detect invalid uses of them. */
3580 for (i
= 0; reg_names
[i
].name
; i
++)
3581 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3582 reg_names
[i
].num
, /* & RNUM_MASK, */
3583 &zero_address_frag
));
3585 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3586 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3587 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3588 &zero_address_frag
));
3590 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3591 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3592 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3593 &zero_address_frag
));
3595 for (i
= 0; i
< 32; i
++)
3599 /* R5900 VU0 floating-point register. */
3600 regname
[sizeof (rename
) - 1] = 0;
3601 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3602 symbol_table_insert (symbol_new (regname
, reg_section
,
3603 RTYPE_VF
| i
, &zero_address_frag
));
3605 /* R5900 VU0 integer register. */
3606 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3607 symbol_table_insert (symbol_new (regname
, reg_section
,
3608 RTYPE_VI
| i
, &zero_address_frag
));
3611 snprintf (regname
, sizeof (regname
) - 1, "$w%d", i
);
3612 symbol_table_insert (symbol_new (regname
, reg_section
,
3613 RTYPE_MSA
| i
, &zero_address_frag
));
3616 obstack_init (&mips_operand_tokens
);
3618 mips_no_prev_insn ();
3621 mips_cprmask
[0] = 0;
3622 mips_cprmask
[1] = 0;
3623 mips_cprmask
[2] = 0;
3624 mips_cprmask
[3] = 0;
3626 /* set the default alignment for the text section (2**2) */
3627 record_alignment (text_section
, 2);
3629 bfd_set_gp_size (stdoutput
, g_switch_value
);
3631 /* On a native system other than VxWorks, sections must be aligned
3632 to 16 byte boundaries. When configured for an embedded ELF
3633 target, we don't bother. */
3634 if (strncmp (TARGET_OS
, "elf", 3) != 0
3635 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3637 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3638 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3639 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3642 /* Create a .reginfo section for register masks and a .mdebug
3643 section for debugging information. */
3651 subseg
= now_subseg
;
3653 /* The ABI says this section should be loaded so that the
3654 running program can access it. However, we don't load it
3655 if we are configured for an embedded target */
3656 flags
= SEC_READONLY
| SEC_DATA
;
3657 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3658 flags
|= SEC_ALLOC
| SEC_LOAD
;
3660 if (mips_abi
!= N64_ABI
)
3662 sec
= subseg_new (".reginfo", (subsegT
) 0);
3664 bfd_set_section_flags (stdoutput
, sec
, flags
);
3665 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3667 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3671 /* The 64-bit ABI uses a .MIPS.options section rather than
3672 .reginfo section. */
3673 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3674 bfd_set_section_flags (stdoutput
, sec
, flags
);
3675 bfd_set_section_alignment (stdoutput
, sec
, 3);
3677 /* Set up the option header. */
3679 Elf_Internal_Options opthdr
;
3682 opthdr
.kind
= ODK_REGINFO
;
3683 opthdr
.size
= (sizeof (Elf_External_Options
)
3684 + sizeof (Elf64_External_RegInfo
));
3687 f
= frag_more (sizeof (Elf_External_Options
));
3688 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3689 (Elf_External_Options
*) f
);
3691 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3695 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3696 bfd_set_section_flags (stdoutput
, sec
,
3697 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3698 bfd_set_section_alignment (stdoutput
, sec
, 3);
3699 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3701 if (ECOFF_DEBUGGING
)
3703 sec
= subseg_new (".mdebug", (subsegT
) 0);
3704 (void) bfd_set_section_flags (stdoutput
, sec
,
3705 SEC_HAS_CONTENTS
| SEC_READONLY
);
3706 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3708 else if (mips_flag_pdr
)
3710 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3711 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3712 SEC_READONLY
| SEC_RELOC
3714 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3717 subseg_set (seg
, subseg
);
3720 if (mips_fix_vr4120
)
3721 init_vr4120_conflicts ();
3725 fpabi_incompatible_with (int fpabi
, const char *what
)
3727 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3728 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3732 fpabi_requires (int fpabi
, const char *what
)
3734 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3735 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3738 /* Check -mabi and register sizes against the specified FP ABI. */
3740 check_fpabi (int fpabi
)
3744 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3745 if (file_mips_opts
.soft_float
)
3746 fpabi_incompatible_with (fpabi
, "softfloat");
3747 else if (file_mips_opts
.single_float
)
3748 fpabi_incompatible_with (fpabi
, "singlefloat");
3749 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3750 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3751 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3752 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3755 case Val_GNU_MIPS_ABI_FP_XX
:
3756 if (mips_abi
!= O32_ABI
)
3757 fpabi_requires (fpabi
, "-mabi=32");
3758 else if (file_mips_opts
.soft_float
)
3759 fpabi_incompatible_with (fpabi
, "softfloat");
3760 else if (file_mips_opts
.single_float
)
3761 fpabi_incompatible_with (fpabi
, "singlefloat");
3762 else if (file_mips_opts
.fp
!= 0)
3763 fpabi_requires (fpabi
, "fp=xx");
3766 case Val_GNU_MIPS_ABI_FP_64A
:
3767 case Val_GNU_MIPS_ABI_FP_64
:
3768 if (mips_abi
!= O32_ABI
)
3769 fpabi_requires (fpabi
, "-mabi=32");
3770 else if (file_mips_opts
.soft_float
)
3771 fpabi_incompatible_with (fpabi
, "softfloat");
3772 else if (file_mips_opts
.single_float
)
3773 fpabi_incompatible_with (fpabi
, "singlefloat");
3774 else if (file_mips_opts
.fp
!= 64)
3775 fpabi_requires (fpabi
, "fp=64");
3776 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3777 fpabi_incompatible_with (fpabi
, "nooddspreg");
3778 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3779 fpabi_requires (fpabi
, "nooddspreg");
3782 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3783 if (file_mips_opts
.soft_float
)
3784 fpabi_incompatible_with (fpabi
, "softfloat");
3785 else if (!file_mips_opts
.single_float
)
3786 fpabi_requires (fpabi
, "singlefloat");
3789 case Val_GNU_MIPS_ABI_FP_SOFT
:
3790 if (!file_mips_opts
.soft_float
)
3791 fpabi_requires (fpabi
, "softfloat");
3794 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3795 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3796 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3800 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3801 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3806 /* Perform consistency checks on the current options. */
3809 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3811 /* Check the size of integer registers agrees with the ABI and ISA. */
3812 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3813 as_bad (_("`gp=64' used with a 32-bit processor"));
3815 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3816 as_bad (_("`gp=32' used with a 64-bit ABI"));
3818 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3819 as_bad (_("`gp=64' used with a 32-bit ABI"));
3821 /* Check the size of the float registers agrees with the ABI and ISA. */
3825 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3826 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3827 else if (opts
->single_float
== 1)
3828 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3831 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3832 as_bad (_("`fp=64' used with a 32-bit fpu"));
3834 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3835 && !ISA_HAS_MXHC1 (opts
->isa
))
3836 as_warn (_("`fp=64' used with a 32-bit ABI"));
3840 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3841 as_warn (_("`fp=32' used with a 64-bit ABI"));
3842 if (ISA_IS_R6 (mips_opts
.isa
) && opts
->single_float
== 0)
3843 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3846 as_bad (_("Unknown size of floating point registers"));
3850 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3851 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3853 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3854 as_bad (_("`mips16' cannot be used with `micromips'"));
3855 else if (ISA_IS_R6 (mips_opts
.isa
)
3856 && (opts
->micromips
== 1
3857 || opts
->mips16
== 1))
3858 as_fatal (_("`%s' can not be used with `%s'"),
3859 opts
->micromips
? "micromips" : "mips16",
3860 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
3862 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3863 as_fatal (_("branch relaxation is not supported in `%s'"),
3864 mips_cpu_info_from_isa (opts
->isa
)->name
);
3867 /* Perform consistency checks on the module level options exactly once.
3868 This is a deferred check that happens:
3869 at the first .set directive
3870 or, at the first pseudo op that generates code (inc .dc.a)
3871 or, at the first instruction
3875 file_mips_check_options (void)
3877 const struct mips_cpu_info
*arch_info
= 0;
3879 if (file_mips_opts_checked
)
3882 /* The following code determines the register size.
3883 Similar code was added to GCC 3.3 (see override_options() in
3884 config/mips/mips.c). The GAS and GCC code should be kept in sync
3885 as much as possible. */
3887 if (file_mips_opts
.gp
< 0)
3889 /* Infer the integer register size from the ABI and processor.
3890 Restrict ourselves to 32-bit registers if that's all the
3891 processor has, or if the ABI cannot handle 64-bit registers. */
3892 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3893 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3897 if (file_mips_opts
.fp
< 0)
3899 /* No user specified float register size.
3900 ??? GAS treats single-float processors as though they had 64-bit
3901 float registers (although it complains when double-precision
3902 instructions are used). As things stand, saying they have 32-bit
3903 registers would lead to spurious "register must be even" messages.
3904 So here we assume float registers are never smaller than the
3906 if (file_mips_opts
.gp
== 64)
3907 /* 64-bit integer registers implies 64-bit float registers. */
3908 file_mips_opts
.fp
= 64;
3909 else if ((file_mips_opts
.ase
& FP64_ASES
)
3910 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3911 /* Handle ASEs that require 64-bit float registers, if possible. */
3912 file_mips_opts
.fp
= 64;
3913 else if (ISA_IS_R6 (mips_opts
.isa
))
3914 /* R6 implies 64-bit float registers. */
3915 file_mips_opts
.fp
= 64;
3917 /* 32-bit float registers. */
3918 file_mips_opts
.fp
= 32;
3921 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3923 /* Disable operations on odd-numbered floating-point registers by default
3924 when using the FPXX ABI. */
3925 if (file_mips_opts
.oddspreg
< 0)
3927 if (file_mips_opts
.fp
== 0)
3928 file_mips_opts
.oddspreg
= 0;
3930 file_mips_opts
.oddspreg
= 1;
3933 /* End of GCC-shared inference code. */
3935 /* This flag is set when we have a 64-bit capable CPU but use only
3936 32-bit wide registers. Note that EABI does not use it. */
3937 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
3938 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
3939 || mips_abi
== O32_ABI
))
3942 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
3943 as_bad (_("trap exception not supported at ISA 1"));
3945 /* If the selected architecture includes support for ASEs, enable
3946 generation of code for them. */
3947 if (file_mips_opts
.mips16
== -1)
3948 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
3949 if (file_mips_opts
.micromips
== -1)
3950 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
3953 if (mips_nan2008
== -1)
3954 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
3955 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
3956 as_fatal (_("`%s' does not support legacy NaN"),
3957 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
3959 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3960 being selected implicitly. */
3961 if (file_mips_opts
.fp
!= 64)
3962 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
3964 /* If the user didn't explicitly select or deselect a particular ASE,
3965 use the default setting for the CPU. */
3966 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
3968 /* Set up the current options. These may change throughout assembly. */
3969 mips_opts
= file_mips_opts
;
3971 mips_check_isa_supports_ases ();
3972 mips_check_options (&file_mips_opts
, TRUE
);
3973 file_mips_opts_checked
= TRUE
;
3975 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3976 as_warn (_("could not set architecture and machine"));
3980 md_assemble (char *str
)
3982 struct mips_cl_insn insn
;
3983 bfd_reloc_code_real_type unused_reloc
[3]
3984 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3986 file_mips_check_options ();
3988 imm_expr
.X_op
= O_absent
;
3989 offset_expr
.X_op
= O_absent
;
3990 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3991 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3992 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3994 mips_mark_labels ();
3995 mips_assembling_insn
= TRUE
;
3996 clear_insn_error ();
3998 if (mips_opts
.mips16
)
3999 mips16_ip (str
, &insn
);
4002 mips_ip (str
, &insn
);
4003 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4004 str
, insn
.insn_opcode
));
4008 report_insn_error (str
);
4009 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4012 if (mips_opts
.mips16
)
4013 mips16_macro (&insn
);
4020 if (offset_expr
.X_op
!= O_absent
)
4021 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4023 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4026 mips_assembling_insn
= FALSE
;
4029 /* Convenience functions for abstracting away the differences between
4030 MIPS16 and non-MIPS16 relocations. */
4032 static inline bfd_boolean
4033 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4037 case BFD_RELOC_MIPS16_JMP
:
4038 case BFD_RELOC_MIPS16_GPREL
:
4039 case BFD_RELOC_MIPS16_GOT16
:
4040 case BFD_RELOC_MIPS16_CALL16
:
4041 case BFD_RELOC_MIPS16_HI16_S
:
4042 case BFD_RELOC_MIPS16_HI16
:
4043 case BFD_RELOC_MIPS16_LO16
:
4051 static inline bfd_boolean
4052 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4056 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4057 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4058 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4059 case BFD_RELOC_MICROMIPS_GPREL16
:
4060 case BFD_RELOC_MICROMIPS_JMP
:
4061 case BFD_RELOC_MICROMIPS_HI16
:
4062 case BFD_RELOC_MICROMIPS_HI16_S
:
4063 case BFD_RELOC_MICROMIPS_LO16
:
4064 case BFD_RELOC_MICROMIPS_LITERAL
:
4065 case BFD_RELOC_MICROMIPS_GOT16
:
4066 case BFD_RELOC_MICROMIPS_CALL16
:
4067 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4068 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4069 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4070 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4071 case BFD_RELOC_MICROMIPS_SUB
:
4072 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4073 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4074 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4075 case BFD_RELOC_MICROMIPS_HIGHEST
:
4076 case BFD_RELOC_MICROMIPS_HIGHER
:
4077 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4078 case BFD_RELOC_MICROMIPS_JALR
:
4086 static inline bfd_boolean
4087 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4089 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4092 static inline bfd_boolean
4093 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4095 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4096 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4099 static inline bfd_boolean
4100 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4102 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4103 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4106 static inline bfd_boolean
4107 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4109 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4110 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4113 static inline bfd_boolean
4114 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4116 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4119 static inline bfd_boolean
4120 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4122 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4123 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4126 /* Return true if RELOC is a PC-relative relocation that does not have
4127 full address range. */
4129 static inline bfd_boolean
4130 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4134 case BFD_RELOC_16_PCREL_S2
:
4135 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4136 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4137 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4138 case BFD_RELOC_MIPS_21_PCREL_S2
:
4139 case BFD_RELOC_MIPS_26_PCREL_S2
:
4140 case BFD_RELOC_MIPS_18_PCREL_S3
:
4141 case BFD_RELOC_MIPS_19_PCREL_S2
:
4144 case BFD_RELOC_32_PCREL
:
4145 case BFD_RELOC_HI16_S_PCREL
:
4146 case BFD_RELOC_LO16_PCREL
:
4147 return HAVE_64BIT_ADDRESSES
;
4154 /* Return true if the given relocation might need a matching %lo().
4155 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4156 need a matching %lo() when applied to local symbols. */
4158 static inline bfd_boolean
4159 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4161 return (HAVE_IN_PLACE_ADDENDS
4162 && (hi16_reloc_p (reloc
)
4163 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4164 all GOT16 relocations evaluate to "G". */
4165 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4168 /* Return the type of %lo() reloc needed by RELOC, given that
4169 reloc_needs_lo_p. */
4171 static inline bfd_reloc_code_real_type
4172 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4174 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4175 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4179 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4182 static inline bfd_boolean
4183 fixup_has_matching_lo_p (fixS
*fixp
)
4185 return (fixp
->fx_next
!= NULL
4186 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4187 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4188 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4191 /* Move all labels in LABELS to the current insertion point. TEXT_P
4192 says whether the labels refer to text or data. */
4195 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4197 struct insn_label_list
*l
;
4200 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4202 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4203 symbol_set_frag (l
->label
, frag_now
);
4204 val
= (valueT
) frag_now_fix ();
4205 /* MIPS16/microMIPS text labels are stored as odd. */
4206 if (text_p
&& HAVE_CODE_COMPRESSION
)
4208 S_SET_VALUE (l
->label
, val
);
4212 /* Move all labels in insn_labels to the current insertion point
4213 and treat them as text labels. */
4216 mips_move_text_labels (void)
4218 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4222 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4224 bfd_boolean linkonce
= FALSE
;
4225 segT symseg
= S_GET_SEGMENT (sym
);
4227 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4229 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4231 /* The GNU toolchain uses an extension for ELF: a section
4232 beginning with the magic string .gnu.linkonce is a
4233 linkonce section. */
4234 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4235 sizeof ".gnu.linkonce" - 1) == 0)
4241 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4242 linker to handle them specially, such as generating jalx instructions
4243 when needed. We also make them odd for the duration of the assembly,
4244 in order to generate the right sort of code. We will make them even
4245 in the adjust_symtab routine, while leaving them marked. This is
4246 convenient for the debugger and the disassembler. The linker knows
4247 to make them odd again. */
4250 mips_compressed_mark_label (symbolS
*label
)
4252 gas_assert (HAVE_CODE_COMPRESSION
);
4254 if (mips_opts
.mips16
)
4255 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4257 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4258 if ((S_GET_VALUE (label
) & 1) == 0
4259 /* Don't adjust the address if the label is global or weak, or
4260 in a link-once section, since we'll be emitting symbol reloc
4261 references to it which will be patched up by the linker, and
4262 the final value of the symbol may or may not be MIPS16/microMIPS. */
4263 && !S_IS_WEAK (label
)
4264 && !S_IS_EXTERNAL (label
)
4265 && !s_is_linkonce (label
, now_seg
))
4266 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4269 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4272 mips_compressed_mark_labels (void)
4274 struct insn_label_list
*l
;
4276 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4277 mips_compressed_mark_label (l
->label
);
4280 /* End the current frag. Make it a variant frag and record the
4284 relax_close_frag (void)
4286 mips_macro_warning
.first_frag
= frag_now
;
4287 frag_var (rs_machine_dependent
, 0, 0,
4288 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
4289 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4291 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4292 mips_relax
.first_fixup
= 0;
4295 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4296 See the comment above RELAX_ENCODE for more details. */
4299 relax_start (symbolS
*symbol
)
4301 gas_assert (mips_relax
.sequence
== 0);
4302 mips_relax
.sequence
= 1;
4303 mips_relax
.symbol
= symbol
;
4306 /* Start generating the second version of a relaxable sequence.
4307 See the comment above RELAX_ENCODE for more details. */
4312 gas_assert (mips_relax
.sequence
== 1);
4313 mips_relax
.sequence
= 2;
4316 /* End the current relaxable sequence. */
4321 gas_assert (mips_relax
.sequence
== 2);
4322 relax_close_frag ();
4323 mips_relax
.sequence
= 0;
4326 /* Return true if IP is a delayed branch or jump. */
4328 static inline bfd_boolean
4329 delayed_branch_p (const struct mips_cl_insn
*ip
)
4331 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4332 | INSN_COND_BRANCH_DELAY
4333 | INSN_COND_BRANCH_LIKELY
)) != 0;
4336 /* Return true if IP is a compact branch or jump. */
4338 static inline bfd_boolean
4339 compact_branch_p (const struct mips_cl_insn
*ip
)
4341 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4342 | INSN2_COND_BRANCH
)) != 0;
4345 /* Return true if IP is an unconditional branch or jump. */
4347 static inline bfd_boolean
4348 uncond_branch_p (const struct mips_cl_insn
*ip
)
4350 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4351 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4354 /* Return true if IP is a branch-likely instruction. */
4356 static inline bfd_boolean
4357 branch_likely_p (const struct mips_cl_insn
*ip
)
4359 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4362 /* Return the type of nop that should be used to fill the delay slot
4363 of delayed branch IP. */
4365 static struct mips_cl_insn
*
4366 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4368 if (mips_opts
.micromips
4369 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4370 return µmips_nop32_insn
;
4374 /* Return a mask that has bit N set if OPCODE reads the register(s)
4378 insn_read_mask (const struct mips_opcode
*opcode
)
4380 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4383 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4387 insn_write_mask (const struct mips_opcode
*opcode
)
4389 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4392 /* Return a mask of the registers specified by operand OPERAND of INSN.
4393 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4397 operand_reg_mask (const struct mips_cl_insn
*insn
,
4398 const struct mips_operand
*operand
,
4399 unsigned int type_mask
)
4401 unsigned int uval
, vsel
;
4403 switch (operand
->type
)
4410 case OP_ADDIUSP_INT
:
4411 case OP_ENTRY_EXIT_LIST
:
4412 case OP_REPEAT_DEST_REG
:
4413 case OP_REPEAT_PREV_REG
:
4416 case OP_VU0_MATCH_SUFFIX
:
4421 case OP_OPTIONAL_REG
:
4423 const struct mips_reg_operand
*reg_op
;
4425 reg_op
= (const struct mips_reg_operand
*) operand
;
4426 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4428 uval
= insn_extract_operand (insn
, operand
);
4429 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4434 const struct mips_reg_pair_operand
*pair_op
;
4436 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4437 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4439 uval
= insn_extract_operand (insn
, operand
);
4440 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4443 case OP_CLO_CLZ_DEST
:
4444 if (!(type_mask
& (1 << OP_REG_GP
)))
4446 uval
= insn_extract_operand (insn
, operand
);
4447 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4450 if (!(type_mask
& (1 << OP_REG_GP
)))
4452 uval
= insn_extract_operand (insn
, operand
);
4453 gas_assert ((uval
& 31) == (uval
>> 5));
4454 return 1 << (uval
& 31);
4457 case OP_NON_ZERO_REG
:
4458 if (!(type_mask
& (1 << OP_REG_GP
)))
4460 uval
= insn_extract_operand (insn
, operand
);
4461 return 1 << (uval
& 31);
4463 case OP_LWM_SWM_LIST
:
4466 case OP_SAVE_RESTORE_LIST
:
4469 case OP_MDMX_IMM_REG
:
4470 if (!(type_mask
& (1 << OP_REG_VEC
)))
4472 uval
= insn_extract_operand (insn
, operand
);
4474 if ((vsel
& 0x18) == 0x18)
4476 return 1 << (uval
& 31);
4479 if (!(type_mask
& (1 << OP_REG_GP
)))
4481 return 1 << insn_extract_operand (insn
, operand
);
4486 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4487 where bit N of OPNO_MASK is set if operand N should be included.
4488 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4492 insn_reg_mask (const struct mips_cl_insn
*insn
,
4493 unsigned int type_mask
, unsigned int opno_mask
)
4495 unsigned int opno
, reg_mask
;
4499 while (opno_mask
!= 0)
4502 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4509 /* Return the mask of core registers that IP reads. */
4512 gpr_read_mask (const struct mips_cl_insn
*ip
)
4514 unsigned long pinfo
, pinfo2
;
4517 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4518 pinfo
= ip
->insn_mo
->pinfo
;
4519 pinfo2
= ip
->insn_mo
->pinfo2
;
4520 if (pinfo
& INSN_UDI
)
4522 /* UDI instructions have traditionally been assumed to read RS
4524 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4525 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4527 if (pinfo
& INSN_READ_GPR_24
)
4529 if (pinfo2
& INSN2_READ_GPR_16
)
4531 if (pinfo2
& INSN2_READ_SP
)
4533 if (pinfo2
& INSN2_READ_GPR_31
)
4535 /* Don't include register 0. */
4539 /* Return the mask of core registers that IP writes. */
4542 gpr_write_mask (const struct mips_cl_insn
*ip
)
4544 unsigned long pinfo
, pinfo2
;
4547 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4548 pinfo
= ip
->insn_mo
->pinfo
;
4549 pinfo2
= ip
->insn_mo
->pinfo2
;
4550 if (pinfo
& INSN_WRITE_GPR_24
)
4552 if (pinfo
& INSN_WRITE_GPR_31
)
4554 if (pinfo
& INSN_UDI
)
4555 /* UDI instructions have traditionally been assumed to write to RD. */
4556 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4557 if (pinfo2
& INSN2_WRITE_SP
)
4559 /* Don't include register 0. */
4563 /* Return the mask of floating-point registers that IP reads. */
4566 fpr_read_mask (const struct mips_cl_insn
*ip
)
4568 unsigned long pinfo
;
4571 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4572 | (1 << OP_REG_MSA
)),
4573 insn_read_mask (ip
->insn_mo
));
4574 pinfo
= ip
->insn_mo
->pinfo
;
4575 /* Conservatively treat all operands to an FP_D instruction are doubles.
4576 (This is overly pessimistic for things like cvt.d.s.) */
4577 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4582 /* Return the mask of floating-point registers that IP writes. */
4585 fpr_write_mask (const struct mips_cl_insn
*ip
)
4587 unsigned long pinfo
;
4590 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4591 | (1 << OP_REG_MSA
)),
4592 insn_write_mask (ip
->insn_mo
));
4593 pinfo
= ip
->insn_mo
->pinfo
;
4594 /* Conservatively treat all operands to an FP_D instruction are doubles.
4595 (This is overly pessimistic for things like cvt.s.d.) */
4596 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4601 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4602 Check whether that is allowed. */
4605 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4607 const char *s
= insn
->name
;
4608 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4610 && mips_opts
.oddspreg
;
4612 if (insn
->pinfo
== INSN_MACRO
)
4613 /* Let a macro pass, we'll catch it later when it is expanded. */
4616 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4617 otherwise it depends on oddspreg. */
4618 if ((insn
->pinfo
& FP_S
)
4619 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4620 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4621 return FPR_SIZE
== 32 || oddspreg
;
4623 /* Allow odd registers for single-precision ops and double-precision if the
4624 floating-point registers are 64-bit wide. */
4625 switch (insn
->pinfo
& (FP_S
| FP_D
))
4631 return FPR_SIZE
== 64;
4636 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4637 s
= strchr (insn
->name
, '.');
4638 if (s
!= NULL
&& opnum
== 2)
4639 s
= strchr (s
+ 1, '.');
4640 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4643 return FPR_SIZE
== 64;
4646 /* Information about an instruction argument that we're trying to match. */
4647 struct mips_arg_info
4649 /* The instruction so far. */
4650 struct mips_cl_insn
*insn
;
4652 /* The first unconsumed operand token. */
4653 struct mips_operand_token
*token
;
4655 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4658 /* The 1-based argument number, for error reporting. This does not
4659 count elided optional registers, etc.. */
4662 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4663 unsigned int last_regno
;
4665 /* If the first operand was an OP_REG, this is the register that it
4666 specified, otherwise it is ILLEGAL_REG. */
4667 unsigned int dest_regno
;
4669 /* The value of the last OP_INT operand. Only used for OP_MSB,
4670 where it gives the lsb position. */
4671 unsigned int last_op_int
;
4673 /* If true, match routines should assume that no later instruction
4674 alternative matches and should therefore be as accomodating as
4675 possible. Match routines should not report errors if something
4676 is only invalid for !LAX_MATCH. */
4677 bfd_boolean lax_match
;
4679 /* True if a reference to the current AT register was seen. */
4680 bfd_boolean seen_at
;
4683 /* Record that the argument is out of range. */
4686 match_out_of_range (struct mips_arg_info
*arg
)
4688 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4691 /* Record that the argument isn't constant but needs to be. */
4694 match_not_constant (struct mips_arg_info
*arg
)
4696 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4700 /* Try to match an OT_CHAR token for character CH. Consume the token
4701 and return true on success, otherwise return false. */
4704 match_char (struct mips_arg_info
*arg
, char ch
)
4706 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4716 /* Try to get an expression from the next tokens in ARG. Consume the
4717 tokens and return true on success, storing the expression value in
4718 VALUE and relocation types in R. */
4721 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4722 bfd_reloc_code_real_type
*r
)
4724 /* If the next token is a '(' that was parsed as being part of a base
4725 expression, assume we have an elided offset. The later match will fail
4726 if this turns out to be wrong. */
4727 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4729 value
->X_op
= O_constant
;
4730 value
->X_add_number
= 0;
4731 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4735 /* Reject register-based expressions such as "0+$2" and "(($2))".
4736 For plain registers the default error seems more appropriate. */
4737 if (arg
->token
->type
== OT_INTEGER
4738 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4740 set_insn_error (arg
->argnum
, _("register value used as expression"));
4744 if (arg
->token
->type
== OT_INTEGER
)
4746 *value
= arg
->token
->u
.integer
.value
;
4747 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4753 (arg
->argnum
, _("operand %d must be an immediate expression"),
4758 /* Try to get a constant expression from the next tokens in ARG. Consume
4759 the tokens and return return true on success, storing the constant value
4760 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4764 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4767 bfd_reloc_code_real_type r
[3];
4769 if (!match_expression (arg
, &ex
, r
))
4772 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4773 *value
= ex
.X_add_number
;
4776 match_not_constant (arg
);
4782 /* Return the RTYPE_* flags for a register operand of type TYPE that
4783 appears in instruction OPCODE. */
4786 convert_reg_type (const struct mips_opcode
*opcode
,
4787 enum mips_reg_operand_type type
)
4792 return RTYPE_NUM
| RTYPE_GP
;
4795 /* Allow vector register names for MDMX if the instruction is a 64-bit
4796 FPR load, store or move (including moves to and from GPRs). */
4797 if ((mips_opts
.ase
& ASE_MDMX
)
4798 && (opcode
->pinfo
& FP_D
)
4799 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4800 | INSN_COPROC_MEMORY_DELAY
4803 | INSN_STORE_MEMORY
)))
4804 return RTYPE_FPU
| RTYPE_VEC
;
4808 if (opcode
->pinfo
& (FP_D
| FP_S
))
4809 return RTYPE_CCC
| RTYPE_FCC
;
4813 if (opcode
->membership
& INSN_5400
)
4815 return RTYPE_FPU
| RTYPE_VEC
;
4821 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4822 return RTYPE_NUM
| RTYPE_CP0
;
4829 return RTYPE_NUM
| RTYPE_VI
;
4832 return RTYPE_NUM
| RTYPE_VF
;
4834 case OP_REG_R5900_I
:
4835 return RTYPE_R5900_I
;
4837 case OP_REG_R5900_Q
:
4838 return RTYPE_R5900_Q
;
4840 case OP_REG_R5900_R
:
4841 return RTYPE_R5900_R
;
4843 case OP_REG_R5900_ACC
:
4844 return RTYPE_R5900_ACC
;
4849 case OP_REG_MSA_CTRL
:
4855 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4858 check_regno (struct mips_arg_info
*arg
,
4859 enum mips_reg_operand_type type
, unsigned int regno
)
4861 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4862 arg
->seen_at
= TRUE
;
4864 if (type
== OP_REG_FP
4866 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4868 /* This was a warning prior to introducing O32 FPXX and FP64 support
4869 so maintain a warning for FP32 but raise an error for the new
4872 as_warn (_("float register should be even, was %d"), regno
);
4874 as_bad (_("float register should be even, was %d"), regno
);
4877 if (type
== OP_REG_CCC
)
4882 name
= arg
->insn
->insn_mo
->name
;
4883 length
= strlen (name
);
4884 if ((regno
& 1) != 0
4885 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4886 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4887 as_warn (_("condition code register should be even for %s, was %d"),
4890 if ((regno
& 3) != 0
4891 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4892 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4897 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4898 a register of type TYPE. Return true on success, storing the register
4899 number in *REGNO and warning about any dubious uses. */
4902 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4903 unsigned int symval
, unsigned int *regno
)
4905 if (type
== OP_REG_VEC
)
4906 symval
= mips_prefer_vec_regno (symval
);
4907 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4910 *regno
= symval
& RNUM_MASK
;
4911 check_regno (arg
, type
, *regno
);
4915 /* Try to interpret the next token in ARG as a register of type TYPE.
4916 Consume the token and return true on success, storing the register
4917 number in *REGNO. Return false on failure. */
4920 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4921 unsigned int *regno
)
4923 if (arg
->token
->type
== OT_REG
4924 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4932 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4933 Consume the token and return true on success, storing the register numbers
4934 in *REGNO1 and *REGNO2. Return false on failure. */
4937 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4938 unsigned int *regno1
, unsigned int *regno2
)
4940 if (match_reg (arg
, type
, regno1
))
4945 if (arg
->token
->type
== OT_REG_RANGE
4946 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4947 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4948 && *regno1
<= *regno2
)
4956 /* OP_INT matcher. */
4959 match_int_operand (struct mips_arg_info
*arg
,
4960 const struct mips_operand
*operand_base
)
4962 const struct mips_int_operand
*operand
;
4964 int min_val
, max_val
, factor
;
4967 operand
= (const struct mips_int_operand
*) operand_base
;
4968 factor
= 1 << operand
->shift
;
4969 min_val
= mips_int_operand_min (operand
);
4970 max_val
= mips_int_operand_max (operand
);
4972 if (operand_base
->lsb
== 0
4973 && operand_base
->size
== 16
4974 && operand
->shift
== 0
4975 && operand
->bias
== 0
4976 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4978 /* The operand can be relocated. */
4979 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4982 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4983 /* Relocation operators were used. Accept the arguent and
4984 leave the relocation value in offset_expr and offset_relocs
4985 for the caller to process. */
4988 if (offset_expr
.X_op
!= O_constant
)
4990 /* Accept non-constant operands if no later alternative matches,
4991 leaving it for the caller to process. */
4992 if (!arg
->lax_match
)
4994 offset_reloc
[0] = BFD_RELOC_LO16
;
4998 /* Clear the global state; we're going to install the operand
5000 sval
= offset_expr
.X_add_number
;
5001 offset_expr
.X_op
= O_absent
;
5003 /* For compatibility with older assemblers, we accept
5004 0x8000-0xffff as signed 16-bit numbers when only
5005 signed numbers are allowed. */
5008 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5009 if (!arg
->lax_match
&& sval
<= max_val
)
5015 if (!match_const_int (arg
, &sval
))
5019 arg
->last_op_int
= sval
;
5021 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5023 match_out_of_range (arg
);
5027 uval
= (unsigned int) sval
>> operand
->shift
;
5028 uval
-= operand
->bias
;
5030 /* Handle -mfix-cn63xxp1. */
5032 && mips_fix_cn63xxp1
5033 && !mips_opts
.micromips
5034 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5049 /* The rest must be changed to 28. */
5054 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5058 /* OP_MAPPED_INT matcher. */
5061 match_mapped_int_operand (struct mips_arg_info
*arg
,
5062 const struct mips_operand
*operand_base
)
5064 const struct mips_mapped_int_operand
*operand
;
5065 unsigned int uval
, num_vals
;
5068 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5069 if (!match_const_int (arg
, &sval
))
5072 num_vals
= 1 << operand_base
->size
;
5073 for (uval
= 0; uval
< num_vals
; uval
++)
5074 if (operand
->int_map
[uval
] == sval
)
5076 if (uval
== num_vals
)
5078 match_out_of_range (arg
);
5082 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5086 /* OP_MSB matcher. */
5089 match_msb_operand (struct mips_arg_info
*arg
,
5090 const struct mips_operand
*operand_base
)
5092 const struct mips_msb_operand
*operand
;
5093 int min_val
, max_val
, max_high
;
5094 offsetT size
, sval
, high
;
5096 operand
= (const struct mips_msb_operand
*) operand_base
;
5097 min_val
= operand
->bias
;
5098 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5099 max_high
= operand
->opsize
;
5101 if (!match_const_int (arg
, &size
))
5104 high
= size
+ arg
->last_op_int
;
5105 sval
= operand
->add_lsb
? high
: size
;
5107 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5109 match_out_of_range (arg
);
5112 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5116 /* OP_REG matcher. */
5119 match_reg_operand (struct mips_arg_info
*arg
,
5120 const struct mips_operand
*operand_base
)
5122 const struct mips_reg_operand
*operand
;
5123 unsigned int regno
, uval
, num_vals
;
5125 operand
= (const struct mips_reg_operand
*) operand_base
;
5126 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5129 if (operand
->reg_map
)
5131 num_vals
= 1 << operand
->root
.size
;
5132 for (uval
= 0; uval
< num_vals
; uval
++)
5133 if (operand
->reg_map
[uval
] == regno
)
5135 if (num_vals
== uval
)
5141 arg
->last_regno
= regno
;
5142 if (arg
->opnum
== 1)
5143 arg
->dest_regno
= regno
;
5144 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5148 /* OP_REG_PAIR matcher. */
5151 match_reg_pair_operand (struct mips_arg_info
*arg
,
5152 const struct mips_operand
*operand_base
)
5154 const struct mips_reg_pair_operand
*operand
;
5155 unsigned int regno1
, regno2
, uval
, num_vals
;
5157 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5158 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5159 || !match_char (arg
, ',')
5160 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5163 num_vals
= 1 << operand_base
->size
;
5164 for (uval
= 0; uval
< num_vals
; uval
++)
5165 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5167 if (uval
== num_vals
)
5170 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5174 /* OP_PCREL matcher. The caller chooses the relocation type. */
5177 match_pcrel_operand (struct mips_arg_info
*arg
)
5179 bfd_reloc_code_real_type r
[3];
5181 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5184 /* OP_PERF_REG matcher. */
5187 match_perf_reg_operand (struct mips_arg_info
*arg
,
5188 const struct mips_operand
*operand
)
5192 if (!match_const_int (arg
, &sval
))
5197 || (mips_opts
.arch
== CPU_R5900
5198 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5199 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5201 set_insn_error (arg
->argnum
, _("invalid performance register"));
5205 insn_insert_operand (arg
->insn
, operand
, sval
);
5209 /* OP_ADDIUSP matcher. */
5212 match_addiusp_operand (struct mips_arg_info
*arg
,
5213 const struct mips_operand
*operand
)
5218 if (!match_const_int (arg
, &sval
))
5223 match_out_of_range (arg
);
5228 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5230 match_out_of_range (arg
);
5234 uval
= (unsigned int) sval
;
5235 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5236 insn_insert_operand (arg
->insn
, operand
, uval
);
5240 /* OP_CLO_CLZ_DEST matcher. */
5243 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5244 const struct mips_operand
*operand
)
5248 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5251 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5255 /* OP_CHECK_PREV matcher. */
5258 match_check_prev_operand (struct mips_arg_info
*arg
,
5259 const struct mips_operand
*operand_base
)
5261 const struct mips_check_prev_operand
*operand
;
5264 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5266 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5269 if (!operand
->zero_ok
&& regno
== 0)
5272 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5273 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5274 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5276 arg
->last_regno
= regno
;
5277 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5284 /* OP_SAME_RS_RT matcher. */
5287 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5288 const struct mips_operand
*operand
)
5292 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5297 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5301 arg
->last_regno
= regno
;
5303 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5307 /* OP_LWM_SWM_LIST matcher. */
5310 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5311 const struct mips_operand
*operand
)
5313 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5314 struct mips_arg_info reset
;
5317 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5321 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5326 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5329 while (match_char (arg
, ',')
5330 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5333 if (operand
->size
== 2)
5335 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5341 and any permutations of these. */
5342 if ((reglist
& 0xfff1ffff) != 0x80010000)
5345 sregs
= (reglist
>> 17) & 7;
5350 /* The list must include at least one of ra and s0-sN,
5351 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5352 which are $23 and $30 respectively.) E.g.:
5360 and any permutations of these. */
5361 if ((reglist
& 0x3f00ffff) != 0)
5364 ra
= (reglist
>> 27) & 0x10;
5365 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5368 if ((sregs
& -sregs
) != sregs
)
5371 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5375 /* OP_ENTRY_EXIT_LIST matcher. */
5378 match_entry_exit_operand (struct mips_arg_info
*arg
,
5379 const struct mips_operand
*operand
)
5382 bfd_boolean is_exit
;
5384 /* The format is the same for both ENTRY and EXIT, but the constraints
5386 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5387 mask
= (is_exit
? 7 << 3 : 0);
5390 unsigned int regno1
, regno2
;
5391 bfd_boolean is_freg
;
5393 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5395 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5400 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5403 mask
|= (5 + regno2
) << 3;
5405 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5406 mask
|= (regno2
- 3) << 3;
5407 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5408 mask
|= (regno2
- 15) << 1;
5409 else if (regno1
== RA
&& regno2
== RA
)
5414 while (match_char (arg
, ','));
5416 insn_insert_operand (arg
->insn
, operand
, mask
);
5420 /* OP_SAVE_RESTORE_LIST matcher. */
5423 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5425 unsigned int opcode
, args
, statics
, sregs
;
5426 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5429 opcode
= arg
->insn
->insn_opcode
;
5431 num_frame_sizes
= 0;
5437 unsigned int regno1
, regno2
;
5439 if (arg
->token
->type
== OT_INTEGER
)
5441 /* Handle the frame size. */
5442 if (!match_const_int (arg
, &frame_size
))
5444 num_frame_sizes
+= 1;
5448 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5451 while (regno1
<= regno2
)
5453 if (regno1
>= 4 && regno1
<= 7)
5455 if (num_frame_sizes
== 0)
5457 args
|= 1 << (regno1
- 4);
5459 /* statics $a0-$a3 */
5460 statics
|= 1 << (regno1
- 4);
5462 else if (regno1
>= 16 && regno1
<= 23)
5464 sregs
|= 1 << (regno1
- 16);
5465 else if (regno1
== 30)
5468 else if (regno1
== 31)
5469 /* Add $ra to insn. */
5479 while (match_char (arg
, ','));
5481 /* Encode args/statics combination. */
5484 else if (args
== 0xf)
5485 /* All $a0-$a3 are args. */
5486 opcode
|= MIPS16_ALL_ARGS
<< 16;
5487 else if (statics
== 0xf)
5488 /* All $a0-$a3 are statics. */
5489 opcode
|= MIPS16_ALL_STATICS
<< 16;
5492 /* Count arg registers. */
5502 /* Count static registers. */
5504 while (statics
& 0x8)
5506 statics
= (statics
<< 1) & 0xf;
5512 /* Encode args/statics. */
5513 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5516 /* Encode $s0/$s1. */
5517 if (sregs
& (1 << 0)) /* $s0 */
5519 if (sregs
& (1 << 1)) /* $s1 */
5523 /* Encode $s2-$s8. */
5532 opcode
|= num_sregs
<< 24;
5534 /* Encode frame size. */
5535 if (num_frame_sizes
== 0)
5537 set_insn_error (arg
->argnum
, _("missing frame size"));
5540 if (num_frame_sizes
> 1)
5542 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5545 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5547 set_insn_error (arg
->argnum
, _("invalid frame size"));
5550 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5553 opcode
|= (((frame_size
& 0xf0) << 16)
5554 | (frame_size
& 0x0f));
5557 /* Finally build the instruction. */
5558 if ((opcode
>> 16) != 0 || frame_size
== 0)
5559 opcode
|= MIPS16_EXTEND
;
5560 arg
->insn
->insn_opcode
= opcode
;
5564 /* OP_MDMX_IMM_REG matcher. */
5567 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5568 const struct mips_operand
*operand
)
5570 unsigned int regno
, uval
;
5572 const struct mips_opcode
*opcode
;
5574 /* The mips_opcode records whether this is an octobyte or quadhalf
5575 instruction. Start out with that bit in place. */
5576 opcode
= arg
->insn
->insn_mo
;
5577 uval
= mips_extract_operand (operand
, opcode
->match
);
5578 is_qh
= (uval
!= 0);
5580 if (arg
->token
->type
== OT_REG
)
5582 if ((opcode
->membership
& INSN_5400
)
5583 && strcmp (opcode
->name
, "rzu.ob") == 0)
5585 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5590 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5594 /* Check whether this is a vector register or a broadcast of
5595 a single element. */
5596 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5598 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5600 set_insn_error (arg
->argnum
, _("invalid element selector"));
5603 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5608 /* A full vector. */
5609 if ((opcode
->membership
& INSN_5400
)
5610 && (strcmp (opcode
->name
, "sll.ob") == 0
5611 || strcmp (opcode
->name
, "srl.ob") == 0))
5613 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5619 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5621 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5629 if (!match_const_int (arg
, &sval
))
5631 if (sval
< 0 || sval
> 31)
5633 match_out_of_range (arg
);
5636 uval
|= (sval
& 31);
5638 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5640 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5642 insn_insert_operand (arg
->insn
, operand
, uval
);
5646 /* OP_IMM_INDEX matcher. */
5649 match_imm_index_operand (struct mips_arg_info
*arg
,
5650 const struct mips_operand
*operand
)
5652 unsigned int max_val
;
5654 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5657 max_val
= (1 << operand
->size
) - 1;
5658 if (arg
->token
->u
.index
> max_val
)
5660 match_out_of_range (arg
);
5663 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5668 /* OP_REG_INDEX matcher. */
5671 match_reg_index_operand (struct mips_arg_info
*arg
,
5672 const struct mips_operand
*operand
)
5676 if (arg
->token
->type
!= OT_REG_INDEX
)
5679 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5682 insn_insert_operand (arg
->insn
, operand
, regno
);
5687 /* OP_PC matcher. */
5690 match_pc_operand (struct mips_arg_info
*arg
)
5692 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5700 /* OP_NON_ZERO_REG matcher. */
5703 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5704 const struct mips_operand
*operand
)
5708 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5714 arg
->last_regno
= regno
;
5715 insn_insert_operand (arg
->insn
, operand
, regno
);
5719 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5720 register that we need to match. */
5723 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5727 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5730 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5731 the length of the value in bytes (4 for float, 8 for double) and
5732 USING_GPRS says whether the destination is a GPR rather than an FPR.
5734 Return the constant in IMM and OFFSET as follows:
5736 - If the constant should be loaded via memory, set IMM to O_absent and
5737 OFFSET to the memory address.
5739 - Otherwise, if the constant should be loaded into two 32-bit registers,
5740 set IMM to the O_constant to load into the high register and OFFSET
5741 to the corresponding value for the low register.
5743 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5745 These constants only appear as the last operand in an instruction,
5746 and every instruction that accepts them in any variant accepts them
5747 in all variants. This means we don't have to worry about backing out
5748 any changes if the instruction does not match. We just match
5749 unconditionally and report an error if the constant is invalid. */
5752 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5753 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5758 const char *newname
;
5759 unsigned char *data
;
5761 /* Where the constant is placed is based on how the MIPS assembler
5764 length == 4 && using_gprs -- immediate value only
5765 length == 8 && using_gprs -- .rdata or immediate value
5766 length == 4 && !using_gprs -- .lit4 or immediate value
5767 length == 8 && !using_gprs -- .lit8 or immediate value
5769 The .lit4 and .lit8 sections are only used if permitted by the
5771 if (arg
->token
->type
!= OT_FLOAT
)
5773 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5777 gas_assert (arg
->token
->u
.flt
.length
== length
);
5778 data
= arg
->token
->u
.flt
.data
;
5781 /* Handle 32-bit constants for which an immediate value is best. */
5784 || g_switch_value
< 4
5785 || (data
[0] == 0 && data
[1] == 0)
5786 || (data
[2] == 0 && data
[3] == 0)))
5788 imm
->X_op
= O_constant
;
5789 if (!target_big_endian
)
5790 imm
->X_add_number
= bfd_getl32 (data
);
5792 imm
->X_add_number
= bfd_getb32 (data
);
5793 offset
->X_op
= O_absent
;
5797 /* Handle 64-bit constants for which an immediate value is best. */
5799 && !mips_disable_float_construction
5800 /* Constants can only be constructed in GPRs and copied to FPRs if the
5801 GPRs are at least as wide as the FPRs or MTHC1 is available.
5802 Unlike most tests for 32-bit floating-point registers this check
5803 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5804 permit 64-bit moves without MXHC1.
5805 Force the constant into memory otherwise. */
5808 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5810 && ((data
[0] == 0 && data
[1] == 0)
5811 || (data
[2] == 0 && data
[3] == 0))
5812 && ((data
[4] == 0 && data
[5] == 0)
5813 || (data
[6] == 0 && data
[7] == 0)))
5815 /* The value is simple enough to load with a couple of instructions.
5816 If using 32-bit registers, set IMM to the high order 32 bits and
5817 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5819 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5821 imm
->X_op
= O_constant
;
5822 offset
->X_op
= O_constant
;
5823 if (!target_big_endian
)
5825 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5826 offset
->X_add_number
= bfd_getl32 (data
);
5830 imm
->X_add_number
= bfd_getb32 (data
);
5831 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5833 if (offset
->X_add_number
== 0)
5834 offset
->X_op
= O_absent
;
5838 imm
->X_op
= O_constant
;
5839 if (!target_big_endian
)
5840 imm
->X_add_number
= bfd_getl64 (data
);
5842 imm
->X_add_number
= bfd_getb64 (data
);
5843 offset
->X_op
= O_absent
;
5848 /* Switch to the right section. */
5850 subseg
= now_subseg
;
5853 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5858 if (using_gprs
|| g_switch_value
< 8)
5859 newname
= RDATA_SECTION_NAME
;
5864 new_seg
= subseg_new (newname
, (subsegT
) 0);
5865 bfd_set_section_flags (stdoutput
, new_seg
,
5866 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5867 frag_align (length
== 4 ? 2 : 3, 0, 0);
5868 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5869 record_alignment (new_seg
, 4);
5871 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5873 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5875 /* Set the argument to the current address in the section. */
5876 imm
->X_op
= O_absent
;
5877 offset
->X_op
= O_symbol
;
5878 offset
->X_add_symbol
= symbol_temp_new_now ();
5879 offset
->X_add_number
= 0;
5881 /* Put the floating point number into the section. */
5882 p
= frag_more (length
);
5883 memcpy (p
, data
, length
);
5885 /* Switch back to the original section. */
5886 subseg_set (seg
, subseg
);
5890 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5894 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5895 const struct mips_operand
*operand
,
5896 bfd_boolean match_p
)
5900 /* The operand can be an XYZW mask or a single 2-bit channel index
5901 (with X being 0). */
5902 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5904 /* The suffix can be omitted when it is already part of the opcode. */
5905 if (arg
->token
->type
!= OT_CHANNELS
)
5908 uval
= arg
->token
->u
.channels
;
5909 if (operand
->size
== 2)
5911 /* Check that a single bit is set and convert it into a 2-bit index. */
5912 if ((uval
& -uval
) != uval
)
5914 uval
= 4 - ffs (uval
);
5917 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5922 insn_insert_operand (arg
->insn
, operand
, uval
);
5926 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5927 of the argument text if the match is successful, otherwise return null. */
5930 match_operand (struct mips_arg_info
*arg
,
5931 const struct mips_operand
*operand
)
5933 switch (operand
->type
)
5936 return match_int_operand (arg
, operand
);
5939 return match_mapped_int_operand (arg
, operand
);
5942 return match_msb_operand (arg
, operand
);
5945 case OP_OPTIONAL_REG
:
5946 return match_reg_operand (arg
, operand
);
5949 return match_reg_pair_operand (arg
, operand
);
5952 return match_pcrel_operand (arg
);
5955 return match_perf_reg_operand (arg
, operand
);
5957 case OP_ADDIUSP_INT
:
5958 return match_addiusp_operand (arg
, operand
);
5960 case OP_CLO_CLZ_DEST
:
5961 return match_clo_clz_dest_operand (arg
, operand
);
5963 case OP_LWM_SWM_LIST
:
5964 return match_lwm_swm_list_operand (arg
, operand
);
5966 case OP_ENTRY_EXIT_LIST
:
5967 return match_entry_exit_operand (arg
, operand
);
5969 case OP_SAVE_RESTORE_LIST
:
5970 return match_save_restore_list_operand (arg
);
5972 case OP_MDMX_IMM_REG
:
5973 return match_mdmx_imm_reg_operand (arg
, operand
);
5975 case OP_REPEAT_DEST_REG
:
5976 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5978 case OP_REPEAT_PREV_REG
:
5979 return match_tied_reg_operand (arg
, arg
->last_regno
);
5982 return match_pc_operand (arg
);
5985 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5987 case OP_VU0_MATCH_SUFFIX
:
5988 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5991 return match_imm_index_operand (arg
, operand
);
5994 return match_reg_index_operand (arg
, operand
);
5997 return match_same_rs_rt_operand (arg
, operand
);
6000 return match_check_prev_operand (arg
, operand
);
6002 case OP_NON_ZERO_REG
:
6003 return match_non_zero_reg_operand (arg
, operand
);
6008 /* ARG is the state after successfully matching an instruction.
6009 Issue any queued-up warnings. */
6012 check_completed_insn (struct mips_arg_info
*arg
)
6017 as_warn (_("used $at without \".set noat\""));
6019 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6023 /* Return true if modifying general-purpose register REG needs a delay. */
6026 reg_needs_delay (unsigned int reg
)
6028 unsigned long prev_pinfo
;
6030 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6031 if (!mips_opts
.noreorder
6032 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6033 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6034 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6040 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6041 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6042 by VR4120 errata. */
6045 classify_vr4120_insn (const char *name
)
6047 if (strncmp (name
, "macc", 4) == 0)
6048 return FIX_VR4120_MACC
;
6049 if (strncmp (name
, "dmacc", 5) == 0)
6050 return FIX_VR4120_DMACC
;
6051 if (strncmp (name
, "mult", 4) == 0)
6052 return FIX_VR4120_MULT
;
6053 if (strncmp (name
, "dmult", 5) == 0)
6054 return FIX_VR4120_DMULT
;
6055 if (strstr (name
, "div"))
6056 return FIX_VR4120_DIV
;
6057 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6058 return FIX_VR4120_MTHILO
;
6059 return NUM_FIX_VR4120_CLASSES
;
6062 #define INSN_ERET 0x42000018
6063 #define INSN_DERET 0x4200001f
6064 #define INSN_DMULT 0x1c
6065 #define INSN_DMULTU 0x1d
6067 /* Return the number of instructions that must separate INSN1 and INSN2,
6068 where INSN1 is the earlier instruction. Return the worst-case value
6069 for any INSN2 if INSN2 is null. */
6072 insns_between (const struct mips_cl_insn
*insn1
,
6073 const struct mips_cl_insn
*insn2
)
6075 unsigned long pinfo1
, pinfo2
;
6078 /* If INFO2 is null, pessimistically assume that all flags are set for
6079 the second instruction. */
6080 pinfo1
= insn1
->insn_mo
->pinfo
;
6081 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6083 /* For most targets, write-after-read dependencies on the HI and LO
6084 registers must be separated by at least two instructions. */
6085 if (!hilo_interlocks
)
6087 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6089 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6093 /* If we're working around r7000 errata, there must be two instructions
6094 between an mfhi or mflo and any instruction that uses the result. */
6095 if (mips_7000_hilo_fix
6096 && !mips_opts
.micromips
6097 && MF_HILO_INSN (pinfo1
)
6098 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6101 /* If we're working around 24K errata, one instruction is required
6102 if an ERET or DERET is followed by a branch instruction. */
6103 if (mips_fix_24k
&& !mips_opts
.micromips
)
6105 if (insn1
->insn_opcode
== INSN_ERET
6106 || insn1
->insn_opcode
== INSN_DERET
)
6109 || insn2
->insn_opcode
== INSN_ERET
6110 || insn2
->insn_opcode
== INSN_DERET
6111 || delayed_branch_p (insn2
))
6116 /* If we're working around PMC RM7000 errata, there must be three
6117 nops between a dmult and a load instruction. */
6118 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6120 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6121 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6123 if (pinfo2
& INSN_LOAD_MEMORY
)
6128 /* If working around VR4120 errata, check for combinations that need
6129 a single intervening instruction. */
6130 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6132 unsigned int class1
, class2
;
6134 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6135 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6139 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6140 if (vr4120_conflicts
[class1
] & (1 << class2
))
6145 if (!HAVE_CODE_COMPRESSION
)
6147 /* Check for GPR or coprocessor load delays. All such delays
6148 are on the RT register. */
6149 /* Itbl support may require additional care here. */
6150 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6151 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6153 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6157 /* Check for generic coprocessor hazards.
6159 This case is not handled very well. There is no special
6160 knowledge of CP0 handling, and the coprocessors other than
6161 the floating point unit are not distinguished at all. */
6162 /* Itbl support may require additional care here. FIXME!
6163 Need to modify this to include knowledge about
6164 user specified delays! */
6165 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6166 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6168 /* Handle cases where INSN1 writes to a known general coprocessor
6169 register. There must be a one instruction delay before INSN2
6170 if INSN2 reads that register, otherwise no delay is needed. */
6171 mask
= fpr_write_mask (insn1
);
6174 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6179 /* Read-after-write dependencies on the control registers
6180 require a two-instruction gap. */
6181 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6182 && (pinfo2
& INSN_READ_COND_CODE
))
6185 /* We don't know exactly what INSN1 does. If INSN2 is
6186 also a coprocessor instruction, assume there must be
6187 a one instruction gap. */
6188 if (pinfo2
& INSN_COP
)
6193 /* Check for read-after-write dependencies on the coprocessor
6194 control registers in cases where INSN1 does not need a general
6195 coprocessor delay. This means that INSN1 is a floating point
6196 comparison instruction. */
6197 /* Itbl support may require additional care here. */
6198 else if (!cop_interlocks
6199 && (pinfo1
& INSN_WRITE_COND_CODE
)
6200 && (pinfo2
& INSN_READ_COND_CODE
))
6204 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6205 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6207 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6208 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6209 || (insn2
&& delayed_branch_p (insn2
))))
6215 /* Return the number of nops that would be needed to work around the
6216 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6217 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6218 that are contained within the first IGNORE instructions of HIST. */
6221 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6222 const struct mips_cl_insn
*insn
)
6227 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6228 are not affected by the errata. */
6230 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6231 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6232 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6235 /* Search for the first MFLO or MFHI. */
6236 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6237 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6239 /* Extract the destination register. */
6240 mask
= gpr_write_mask (&hist
[i
]);
6242 /* No nops are needed if INSN reads that register. */
6243 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6246 /* ...or if any of the intervening instructions do. */
6247 for (j
= 0; j
< i
; j
++)
6248 if (gpr_read_mask (&hist
[j
]) & mask
)
6252 return MAX_VR4130_NOPS
- i
;
6257 #define BASE_REG_EQ(INSN1, INSN2) \
6258 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6259 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6261 /* Return the minimum alignment for this store instruction. */
6264 fix_24k_align_to (const struct mips_opcode
*mo
)
6266 if (strcmp (mo
->name
, "sh") == 0)
6269 if (strcmp (mo
->name
, "swc1") == 0
6270 || strcmp (mo
->name
, "swc2") == 0
6271 || strcmp (mo
->name
, "sw") == 0
6272 || strcmp (mo
->name
, "sc") == 0
6273 || strcmp (mo
->name
, "s.s") == 0)
6276 if (strcmp (mo
->name
, "sdc1") == 0
6277 || strcmp (mo
->name
, "sdc2") == 0
6278 || strcmp (mo
->name
, "s.d") == 0)
6285 struct fix_24k_store_info
6287 /* Immediate offset, if any, for this store instruction. */
6289 /* Alignment required by this store instruction. */
6291 /* True for register offsets. */
6292 int register_offset
;
6295 /* Comparison function used by qsort. */
6298 fix_24k_sort (const void *a
, const void *b
)
6300 const struct fix_24k_store_info
*pos1
= a
;
6301 const struct fix_24k_store_info
*pos2
= b
;
6303 return (pos1
->off
- pos2
->off
);
6306 /* INSN is a store instruction. Try to record the store information
6307 in STINFO. Return false if the information isn't known. */
6310 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6311 const struct mips_cl_insn
*insn
)
6313 /* The instruction must have a known offset. */
6314 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6317 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6318 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6322 /* Return the number of nops that would be needed to work around the 24k
6323 "lost data on stores during refill" errata if instruction INSN
6324 immediately followed the 2 instructions described by HIST.
6325 Ignore hazards that are contained within the first IGNORE
6326 instructions of HIST.
6328 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6329 for the data cache refills and store data. The following describes
6330 the scenario where the store data could be lost.
6332 * A data cache miss, due to either a load or a store, causing fill
6333 data to be supplied by the memory subsystem
6334 * The first three doublewords of fill data are returned and written
6336 * A sequence of four stores occurs in consecutive cycles around the
6337 final doubleword of the fill:
6341 * Zero, One or more instructions
6344 The four stores A-D must be to different doublewords of the line that
6345 is being filled. The fourth instruction in the sequence above permits
6346 the fill of the final doubleword to be transferred from the FSB into
6347 the cache. In the sequence above, the stores may be either integer
6348 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6349 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6350 different doublewords on the line. If the floating point unit is
6351 running in 1:2 mode, it is not possible to create the sequence above
6352 using only floating point store instructions.
6354 In this case, the cache line being filled is incorrectly marked
6355 invalid, thereby losing the data from any store to the line that
6356 occurs between the original miss and the completion of the five
6357 cycle sequence shown above.
6359 The workarounds are:
6361 * Run the data cache in write-through mode.
6362 * Insert a non-store instruction between
6363 Store A and Store B or Store B and Store C. */
6366 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6367 const struct mips_cl_insn
*insn
)
6369 struct fix_24k_store_info pos
[3];
6370 int align
, i
, base_offset
;
6375 /* If the previous instruction wasn't a store, there's nothing to
6377 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6380 /* If the instructions after the previous one are unknown, we have
6381 to assume the worst. */
6385 /* Check whether we are dealing with three consecutive stores. */
6386 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6387 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6390 /* If we don't know the relationship between the store addresses,
6391 assume the worst. */
6392 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6393 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6396 if (!fix_24k_record_store_info (&pos
[0], insn
)
6397 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6398 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6401 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6403 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6404 X bytes and such that the base register + X is known to be aligned
6407 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6411 align
= pos
[0].align_to
;
6412 base_offset
= pos
[0].off
;
6413 for (i
= 1; i
< 3; i
++)
6414 if (align
< pos
[i
].align_to
)
6416 align
= pos
[i
].align_to
;
6417 base_offset
= pos
[i
].off
;
6419 for (i
= 0; i
< 3; i
++)
6420 pos
[i
].off
-= base_offset
;
6423 pos
[0].off
&= ~align
+ 1;
6424 pos
[1].off
&= ~align
+ 1;
6425 pos
[2].off
&= ~align
+ 1;
6427 /* If any two stores write to the same chunk, they also write to the
6428 same doubleword. The offsets are still sorted at this point. */
6429 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6432 /* A range of at least 9 bytes is needed for the stores to be in
6433 non-overlapping doublewords. */
6434 if (pos
[2].off
- pos
[0].off
<= 8)
6437 if (pos
[2].off
- pos
[1].off
>= 24
6438 || pos
[1].off
- pos
[0].off
>= 24
6439 || pos
[2].off
- pos
[0].off
>= 32)
6445 /* Return the number of nops that would be needed if instruction INSN
6446 immediately followed the MAX_NOPS instructions given by HIST,
6447 where HIST[0] is the most recent instruction. Ignore hazards
6448 between INSN and the first IGNORE instructions in HIST.
6450 If INSN is null, return the worse-case number of nops for any
6454 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6455 const struct mips_cl_insn
*insn
)
6457 int i
, nops
, tmp_nops
;
6460 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6462 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6463 if (tmp_nops
> nops
)
6467 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6469 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6470 if (tmp_nops
> nops
)
6474 if (mips_fix_24k
&& !mips_opts
.micromips
)
6476 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6477 if (tmp_nops
> nops
)
6484 /* The variable arguments provide NUM_INSNS extra instructions that
6485 might be added to HIST. Return the largest number of nops that
6486 would be needed after the extended sequence, ignoring hazards
6487 in the first IGNORE instructions. */
6490 nops_for_sequence (int num_insns
, int ignore
,
6491 const struct mips_cl_insn
*hist
, ...)
6494 struct mips_cl_insn buffer
[MAX_NOPS
];
6495 struct mips_cl_insn
*cursor
;
6498 va_start (args
, hist
);
6499 cursor
= buffer
+ num_insns
;
6500 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6501 while (cursor
> buffer
)
6502 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6504 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6509 /* Like nops_for_insn, but if INSN is a branch, take into account the
6510 worst-case delay for the branch target. */
6513 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6514 const struct mips_cl_insn
*insn
)
6518 nops
= nops_for_insn (ignore
, hist
, insn
);
6519 if (delayed_branch_p (insn
))
6521 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6522 hist
, insn
, get_delay_slot_nop (insn
));
6523 if (tmp_nops
> nops
)
6526 else if (compact_branch_p (insn
))
6528 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6529 if (tmp_nops
> nops
)
6535 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6538 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6540 gas_assert (!HAVE_CODE_COMPRESSION
);
6541 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6542 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6545 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6546 jr target pc &= 'hffff_ffff_cfff_ffff. */
6549 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6551 gas_assert (!HAVE_CODE_COMPRESSION
);
6552 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6553 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6554 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6562 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6563 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6566 ep
.X_op
= O_constant
;
6567 ep
.X_add_number
= 0xcfff0000;
6568 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6569 ep
.X_add_number
= 0xffff;
6570 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6571 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6576 fix_loongson2f (struct mips_cl_insn
* ip
)
6578 if (mips_fix_loongson2f_nop
)
6579 fix_loongson2f_nop (ip
);
6581 if (mips_fix_loongson2f_jump
)
6582 fix_loongson2f_jump (ip
);
6585 /* IP is a branch that has a delay slot, and we need to fill it
6586 automatically. Return true if we can do that by swapping IP
6587 with the previous instruction.
6588 ADDRESS_EXPR is an operand of the instruction to be used with
6592 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6593 bfd_reloc_code_real_type
*reloc_type
)
6595 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6596 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6597 unsigned int fpr_read
, prev_fpr_write
;
6599 /* -O2 and above is required for this optimization. */
6600 if (mips_optimize
< 2)
6603 /* If we have seen .set volatile or .set nomove, don't optimize. */
6604 if (mips_opts
.nomove
)
6607 /* We can't swap if the previous instruction's position is fixed. */
6608 if (history
[0].fixed_p
)
6611 /* If the previous previous insn was in a .set noreorder, we can't
6612 swap. Actually, the MIPS assembler will swap in this situation.
6613 However, gcc configured -with-gnu-as will generate code like
6621 in which we can not swap the bne and INSN. If gcc is not configured
6622 -with-gnu-as, it does not output the .set pseudo-ops. */
6623 if (history
[1].noreorder_p
)
6626 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6627 This means that the previous instruction was a 4-byte one anyhow. */
6628 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6631 /* If the branch is itself the target of a branch, we can not swap.
6632 We cheat on this; all we check for is whether there is a label on
6633 this instruction. If there are any branches to anything other than
6634 a label, users must use .set noreorder. */
6635 if (seg_info (now_seg
)->label_list
)
6638 /* If the previous instruction is in a variant frag other than this
6639 branch's one, we cannot do the swap. This does not apply to
6640 MIPS16 code, which uses variant frags for different purposes. */
6641 if (!mips_opts
.mips16
6643 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6646 /* We do not swap with instructions that cannot architecturally
6647 be placed in a branch delay slot, such as SYNC or ERET. We
6648 also refrain from swapping with a trap instruction, since it
6649 complicates trap handlers to have the trap instruction be in
6651 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6652 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6655 /* Check for conflicts between the branch and the instructions
6656 before the candidate delay slot. */
6657 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6660 /* Check for conflicts between the swapped sequence and the
6661 target of the branch. */
6662 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6665 /* If the branch reads a register that the previous
6666 instruction sets, we can not swap. */
6667 gpr_read
= gpr_read_mask (ip
);
6668 prev_gpr_write
= gpr_write_mask (&history
[0]);
6669 if (gpr_read
& prev_gpr_write
)
6672 fpr_read
= fpr_read_mask (ip
);
6673 prev_fpr_write
= fpr_write_mask (&history
[0]);
6674 if (fpr_read
& prev_fpr_write
)
6677 /* If the branch writes a register that the previous
6678 instruction sets, we can not swap. */
6679 gpr_write
= gpr_write_mask (ip
);
6680 if (gpr_write
& prev_gpr_write
)
6683 /* If the branch writes a register that the previous
6684 instruction reads, we can not swap. */
6685 prev_gpr_read
= gpr_read_mask (&history
[0]);
6686 if (gpr_write
& prev_gpr_read
)
6689 /* If one instruction sets a condition code and the
6690 other one uses a condition code, we can not swap. */
6691 pinfo
= ip
->insn_mo
->pinfo
;
6692 if ((pinfo
& INSN_READ_COND_CODE
)
6693 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6695 if ((pinfo
& INSN_WRITE_COND_CODE
)
6696 && (prev_pinfo
& INSN_READ_COND_CODE
))
6699 /* If the previous instruction uses the PC, we can not swap. */
6700 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6701 if (prev_pinfo2
& INSN2_READ_PC
)
6704 /* If the previous instruction has an incorrect size for a fixed
6705 branch delay slot in microMIPS mode, we cannot swap. */
6706 pinfo2
= ip
->insn_mo
->pinfo2
;
6707 if (mips_opts
.micromips
6708 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6709 && insn_length (history
) != 2)
6711 if (mips_opts
.micromips
6712 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6713 && insn_length (history
) != 4)
6716 /* On R5900 short loops need to be fixed by inserting a nop in
6717 the branch delay slots.
6718 A short loop can be terminated too early. */
6719 if (mips_opts
.arch
== CPU_R5900
6720 /* Check if instruction has a parameter, ignore "j $31". */
6721 && (address_expr
!= NULL
)
6722 /* Parameter must be 16 bit. */
6723 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6724 /* Branch to same segment. */
6725 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6726 /* Branch to same code fragment. */
6727 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6728 /* Can only calculate branch offset if value is known. */
6729 && symbol_constant_p(address_expr
->X_add_symbol
)
6730 /* Check if branch is really conditional. */
6731 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6732 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6733 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6736 /* Check if loop is shorter than 6 instructions including
6737 branch and delay slot. */
6738 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6745 /* When the loop includes branches or jumps,
6746 it is not a short loop. */
6747 for (i
= 0; i
< (distance
/ 4); i
++)
6749 if ((history
[i
].cleared_p
)
6750 || delayed_branch_p(&history
[i
]))
6758 /* Insert nop after branch to fix short loop. */
6767 /* Decide how we should add IP to the instruction stream.
6768 ADDRESS_EXPR is an operand of the instruction to be used with
6771 static enum append_method
6772 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6773 bfd_reloc_code_real_type
*reloc_type
)
6775 /* The relaxed version of a macro sequence must be inherently
6777 if (mips_relax
.sequence
== 2)
6780 /* We must not dabble with instructions in a ".set norerorder" block. */
6781 if (mips_opts
.noreorder
)
6784 /* Otherwise, it's our responsibility to fill branch delay slots. */
6785 if (delayed_branch_p (ip
))
6787 if (!branch_likely_p (ip
)
6788 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6791 if (mips_opts
.mips16
6792 && ISA_SUPPORTS_MIPS16E
6793 && gpr_read_mask (ip
) != 0)
6794 return APPEND_ADD_COMPACT
;
6796 return APPEND_ADD_WITH_NOP
;
6802 /* IP is a MIPS16 instruction whose opcode we have just changed.
6803 Point IP->insn_mo to the new opcode's definition. */
6806 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6808 const struct mips_opcode
*mo
, *end
;
6810 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6811 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6812 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6820 /* For microMIPS macros, we need to generate a local number label
6821 as the target of branches. */
6822 #define MICROMIPS_LABEL_CHAR '\037'
6823 static unsigned long micromips_target_label
;
6824 static char micromips_target_name
[32];
6827 micromips_label_name (void)
6829 char *p
= micromips_target_name
;
6830 char symbol_name_temporary
[24];
6838 l
= micromips_target_label
;
6839 #ifdef LOCAL_LABEL_PREFIX
6840 *p
++ = LOCAL_LABEL_PREFIX
;
6843 *p
++ = MICROMIPS_LABEL_CHAR
;
6846 symbol_name_temporary
[i
++] = l
% 10 + '0';
6851 *p
++ = symbol_name_temporary
[--i
];
6854 return micromips_target_name
;
6858 micromips_label_expr (expressionS
*label_expr
)
6860 label_expr
->X_op
= O_symbol
;
6861 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6862 label_expr
->X_add_number
= 0;
6866 micromips_label_inc (void)
6868 micromips_target_label
++;
6869 *micromips_target_name
= '\0';
6873 micromips_add_label (void)
6877 s
= colon (micromips_label_name ());
6878 micromips_label_inc ();
6879 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6882 /* If assembling microMIPS code, then return the microMIPS reloc
6883 corresponding to the requested one if any. Otherwise return
6884 the reloc unchanged. */
6886 static bfd_reloc_code_real_type
6887 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6889 static const bfd_reloc_code_real_type relocs
[][2] =
6891 /* Keep sorted incrementally by the left-hand key. */
6892 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6893 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6894 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6895 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6896 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6897 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6898 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6899 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6900 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6901 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6902 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6903 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6904 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6905 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6906 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6907 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6908 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6909 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6910 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6911 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6912 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6913 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6914 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6915 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6916 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6917 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6918 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6920 bfd_reloc_code_real_type r
;
6923 if (!mips_opts
.micromips
)
6925 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6931 return relocs
[i
][1];
6936 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6937 Return true on success, storing the resolved value in RESULT. */
6940 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6945 case BFD_RELOC_MIPS_HIGHEST
:
6946 case BFD_RELOC_MICROMIPS_HIGHEST
:
6947 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6950 case BFD_RELOC_MIPS_HIGHER
:
6951 case BFD_RELOC_MICROMIPS_HIGHER
:
6952 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6955 case BFD_RELOC_HI16_S
:
6956 case BFD_RELOC_MICROMIPS_HI16_S
:
6957 case BFD_RELOC_MIPS16_HI16_S
:
6958 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6961 case BFD_RELOC_HI16
:
6962 case BFD_RELOC_MICROMIPS_HI16
:
6963 case BFD_RELOC_MIPS16_HI16
:
6964 *result
= (operand
>> 16) & 0xffff;
6967 case BFD_RELOC_LO16
:
6968 case BFD_RELOC_MICROMIPS_LO16
:
6969 case BFD_RELOC_MIPS16_LO16
:
6970 *result
= operand
& 0xffff;
6973 case BFD_RELOC_UNUSED
:
6982 /* Output an instruction. IP is the instruction information.
6983 ADDRESS_EXPR is an operand of the instruction to be used with
6984 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6985 a macro expansion. */
6988 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6989 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6991 unsigned long prev_pinfo2
, pinfo
;
6992 bfd_boolean relaxed_branch
= FALSE
;
6993 enum append_method method
;
6994 bfd_boolean relax32
;
6997 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6998 fix_loongson2f (ip
);
7000 file_ase_mips16
|= mips_opts
.mips16
;
7001 file_ase_micromips
|= mips_opts
.micromips
;
7003 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7004 pinfo
= ip
->insn_mo
->pinfo
;
7006 if (mips_opts
.micromips
7008 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7009 && micromips_insn_length (ip
->insn_mo
) != 2)
7010 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7011 && micromips_insn_length (ip
->insn_mo
) != 4)))
7012 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7013 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7015 if (address_expr
== NULL
)
7017 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7018 && reloc_type
[1] == BFD_RELOC_UNUSED
7019 && reloc_type
[2] == BFD_RELOC_UNUSED
7020 && address_expr
->X_op
== O_constant
)
7022 switch (*reloc_type
)
7024 case BFD_RELOC_MIPS_JMP
:
7028 shift
= mips_opts
.micromips
? 1 : 2;
7029 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7030 as_bad (_("jump to misaligned address (0x%lx)"),
7031 (unsigned long) address_expr
->X_add_number
);
7032 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7038 case BFD_RELOC_MIPS16_JMP
:
7039 if ((address_expr
->X_add_number
& 3) != 0)
7040 as_bad (_("jump to misaligned address (0x%lx)"),
7041 (unsigned long) address_expr
->X_add_number
);
7043 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7044 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7045 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7049 case BFD_RELOC_16_PCREL_S2
:
7053 shift
= mips_opts
.micromips
? 1 : 2;
7054 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7055 as_bad (_("branch to misaligned address (0x%lx)"),
7056 (unsigned long) address_expr
->X_add_number
);
7057 if (!mips_relax_branch
)
7059 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7060 & ~((1 << (shift
+ 16)) - 1))
7061 as_bad (_("branch address range overflow (0x%lx)"),
7062 (unsigned long) address_expr
->X_add_number
);
7063 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7069 case BFD_RELOC_MIPS_21_PCREL_S2
:
7074 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7075 as_bad (_("branch to misaligned address (0x%lx)"),
7076 (unsigned long) address_expr
->X_add_number
);
7077 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7078 & ~((1 << (shift
+ 21)) - 1))
7079 as_bad (_("branch address range overflow (0x%lx)"),
7080 (unsigned long) address_expr
->X_add_number
);
7081 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7086 case BFD_RELOC_MIPS_26_PCREL_S2
:
7091 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7092 as_bad (_("branch to misaligned address (0x%lx)"),
7093 (unsigned long) address_expr
->X_add_number
);
7094 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7095 & ~((1 << (shift
+ 26)) - 1))
7096 as_bad (_("branch address range overflow (0x%lx)"),
7097 (unsigned long) address_expr
->X_add_number
);
7098 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7107 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7110 ip
->insn_opcode
|= value
& 0xffff;
7118 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7120 /* There are a lot of optimizations we could do that we don't.
7121 In particular, we do not, in general, reorder instructions.
7122 If you use gcc with optimization, it will reorder
7123 instructions and generally do much more optimization then we
7124 do here; repeating all that work in the assembler would only
7125 benefit hand written assembly code, and does not seem worth
7127 int nops
= (mips_optimize
== 0
7128 ? nops_for_insn (0, history
, NULL
)
7129 : nops_for_insn_or_target (0, history
, ip
));
7133 unsigned long old_frag_offset
;
7136 old_frag
= frag_now
;
7137 old_frag_offset
= frag_now_fix ();
7139 for (i
= 0; i
< nops
; i
++)
7140 add_fixed_insn (NOP_INSN
);
7141 insert_into_history (0, nops
, NOP_INSN
);
7145 listing_prev_line ();
7146 /* We may be at the start of a variant frag. In case we
7147 are, make sure there is enough space for the frag
7148 after the frags created by listing_prev_line. The
7149 argument to frag_grow here must be at least as large
7150 as the argument to all other calls to frag_grow in
7151 this file. We don't have to worry about being in the
7152 middle of a variant frag, because the variants insert
7153 all needed nop instructions themselves. */
7157 mips_move_text_labels ();
7159 #ifndef NO_ECOFF_DEBUGGING
7160 if (ECOFF_DEBUGGING
)
7161 ecoff_fix_loc (old_frag
, old_frag_offset
);
7165 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7169 /* Work out how many nops in prev_nop_frag are needed by IP,
7170 ignoring hazards generated by the first prev_nop_frag_since
7172 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7173 gas_assert (nops
<= prev_nop_frag_holds
);
7175 /* Enforce NOPS as a minimum. */
7176 if (nops
> prev_nop_frag_required
)
7177 prev_nop_frag_required
= nops
;
7179 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7181 /* Settle for the current number of nops. Update the history
7182 accordingly (for the benefit of any future .set reorder code). */
7183 prev_nop_frag
= NULL
;
7184 insert_into_history (prev_nop_frag_since
,
7185 prev_nop_frag_holds
, NOP_INSN
);
7189 /* Allow this instruction to replace one of the nops that was
7190 tentatively added to prev_nop_frag. */
7191 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7192 prev_nop_frag_holds
--;
7193 prev_nop_frag_since
++;
7197 method
= get_append_method (ip
, address_expr
, reloc_type
);
7198 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7200 dwarf2_emit_insn (0);
7201 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7202 so "move" the instruction address accordingly.
7204 Also, it doesn't seem appropriate for the assembler to reorder .loc
7205 entries. If this instruction is a branch that we are going to swap
7206 with the previous instruction, the two instructions should be
7207 treated as a unit, and the debug information for both instructions
7208 should refer to the start of the branch sequence. Using the
7209 current position is certainly wrong when swapping a 32-bit branch
7210 and a 16-bit delay slot, since the current position would then be
7211 in the middle of a branch. */
7212 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7214 relax32
= (mips_relax_branch
7215 /* Don't try branch relaxation within .set nomacro, or within
7216 .set noat if we use $at for PIC computations. If it turns
7217 out that the branch was out-of-range, we'll get an error. */
7218 && !mips_opts
.warn_about_macros
7219 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7220 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7221 as they have no complementing branches. */
7222 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7224 if (!HAVE_CODE_COMPRESSION
7227 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7228 && delayed_branch_p (ip
))
7230 relaxed_branch
= TRUE
;
7231 add_relaxed_insn (ip
, (relaxed_branch_length
7233 uncond_branch_p (ip
) ? -1
7234 : branch_likely_p (ip
) ? 1
7238 uncond_branch_p (ip
),
7239 branch_likely_p (ip
),
7240 pinfo
& INSN_WRITE_GPR_31
,
7242 address_expr
->X_add_symbol
,
7243 address_expr
->X_add_number
);
7244 *reloc_type
= BFD_RELOC_UNUSED
;
7246 else if (mips_opts
.micromips
7248 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7249 || *reloc_type
> BFD_RELOC_UNUSED
)
7250 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7251 /* Don't try branch relaxation when users specify
7252 16-bit/32-bit instructions. */
7253 && !forced_insn_length
)
7255 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
7256 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7257 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7258 int compact
= compact_branch_p (ip
);
7259 int al
= pinfo
& INSN_WRITE_GPR_31
;
7262 gas_assert (address_expr
!= NULL
);
7263 gas_assert (!mips_relax
.sequence
);
7265 relaxed_branch
= TRUE
;
7266 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7267 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
7268 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
7270 address_expr
->X_add_symbol
,
7271 address_expr
->X_add_number
);
7272 *reloc_type
= BFD_RELOC_UNUSED
;
7274 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7276 /* We need to set up a variant frag. */
7277 gas_assert (address_expr
!= NULL
);
7278 add_relaxed_insn (ip
, 4, 0,
7280 (*reloc_type
- BFD_RELOC_UNUSED
,
7281 forced_insn_length
== 2, forced_insn_length
== 4,
7282 delayed_branch_p (&history
[0]),
7283 history
[0].mips16_absolute_jump_p
),
7284 make_expr_symbol (address_expr
), 0);
7286 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7288 if (!delayed_branch_p (ip
))
7289 /* Make sure there is enough room to swap this instruction with
7290 a following jump instruction. */
7292 add_fixed_insn (ip
);
7296 if (mips_opts
.mips16
7297 && mips_opts
.noreorder
7298 && delayed_branch_p (&history
[0]))
7299 as_warn (_("extended instruction in delay slot"));
7301 if (mips_relax
.sequence
)
7303 /* If we've reached the end of this frag, turn it into a variant
7304 frag and record the information for the instructions we've
7306 if (frag_room () < 4)
7307 relax_close_frag ();
7308 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7311 if (mips_relax
.sequence
!= 2)
7313 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7314 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7315 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7316 mips_macro_warning
.insns
[0]++;
7318 if (mips_relax
.sequence
!= 1)
7320 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7321 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7322 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7323 mips_macro_warning
.insns
[1]++;
7326 if (mips_opts
.mips16
)
7329 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7331 add_fixed_insn (ip
);
7334 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7336 bfd_reloc_code_real_type final_type
[3];
7337 reloc_howto_type
*howto0
;
7338 reloc_howto_type
*howto
;
7341 /* Perform any necessary conversion to microMIPS relocations
7342 and find out how many relocations there actually are. */
7343 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7344 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7346 /* In a compound relocation, it is the final (outermost)
7347 operator that determines the relocated field. */
7348 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7353 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7354 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7355 bfd_get_reloc_size (howto
),
7357 howto0
&& howto0
->pc_relative
,
7360 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7361 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7362 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7364 /* These relocations can have an addend that won't fit in
7365 4 octets for 64bit assembly. */
7367 && ! howto
->partial_inplace
7368 && (reloc_type
[0] == BFD_RELOC_16
7369 || reloc_type
[0] == BFD_RELOC_32
7370 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7371 || reloc_type
[0] == BFD_RELOC_GPREL16
7372 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7373 || reloc_type
[0] == BFD_RELOC_GPREL32
7374 || reloc_type
[0] == BFD_RELOC_64
7375 || reloc_type
[0] == BFD_RELOC_CTOR
7376 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7377 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7378 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7379 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7380 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7381 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7382 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7383 || hi16_reloc_p (reloc_type
[0])
7384 || lo16_reloc_p (reloc_type
[0])))
7385 ip
->fixp
[0]->fx_no_overflow
= 1;
7387 /* These relocations can have an addend that won't fit in 2 octets. */
7388 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7389 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7390 ip
->fixp
[0]->fx_no_overflow
= 1;
7392 if (mips_relax
.sequence
)
7394 if (mips_relax
.first_fixup
== 0)
7395 mips_relax
.first_fixup
= ip
->fixp
[0];
7397 else if (reloc_needs_lo_p (*reloc_type
))
7399 struct mips_hi_fixup
*hi_fixup
;
7401 /* Reuse the last entry if it already has a matching %lo. */
7402 hi_fixup
= mips_hi_fixup_list
;
7404 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7406 hi_fixup
= ((struct mips_hi_fixup
*)
7407 xmalloc (sizeof (struct mips_hi_fixup
)));
7408 hi_fixup
->next
= mips_hi_fixup_list
;
7409 mips_hi_fixup_list
= hi_fixup
;
7411 hi_fixup
->fixp
= ip
->fixp
[0];
7412 hi_fixup
->seg
= now_seg
;
7415 /* Add fixups for the second and third relocations, if given.
7416 Note that the ABI allows the second relocation to be
7417 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7418 moment we only use RSS_UNDEF, but we could add support
7419 for the others if it ever becomes necessary. */
7420 for (i
= 1; i
< 3; i
++)
7421 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7423 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7424 ip
->fixp
[0]->fx_size
, NULL
, 0,
7425 FALSE
, final_type
[i
]);
7427 /* Use fx_tcbit to mark compound relocs. */
7428 ip
->fixp
[0]->fx_tcbit
= 1;
7429 ip
->fixp
[i
]->fx_tcbit
= 1;
7434 /* Update the register mask information. */
7435 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7436 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7441 insert_into_history (0, 1, ip
);
7444 case APPEND_ADD_WITH_NOP
:
7446 struct mips_cl_insn
*nop
;
7448 insert_into_history (0, 1, ip
);
7449 nop
= get_delay_slot_nop (ip
);
7450 add_fixed_insn (nop
);
7451 insert_into_history (0, 1, nop
);
7452 if (mips_relax
.sequence
)
7453 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7457 case APPEND_ADD_COMPACT
:
7458 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7459 gas_assert (mips_opts
.mips16
);
7460 ip
->insn_opcode
|= 0x0080;
7461 find_altered_mips16_opcode (ip
);
7463 insert_into_history (0, 1, ip
);
7468 struct mips_cl_insn delay
= history
[0];
7469 if (mips_opts
.mips16
)
7471 know (delay
.frag
== ip
->frag
);
7472 move_insn (ip
, delay
.frag
, delay
.where
);
7473 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7475 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7477 /* Add the delay slot instruction to the end of the
7478 current frag and shrink the fixed part of the
7479 original frag. If the branch occupies the tail of
7480 the latter, move it backwards to cover the gap. */
7481 delay
.frag
->fr_fix
-= branch_disp
;
7482 if (delay
.frag
== ip
->frag
)
7483 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7484 add_fixed_insn (&delay
);
7488 move_insn (&delay
, ip
->frag
,
7489 ip
->where
- branch_disp
+ insn_length (ip
));
7490 move_insn (ip
, history
[0].frag
, history
[0].where
);
7494 insert_into_history (0, 1, &delay
);
7499 /* If we have just completed an unconditional branch, clear the history. */
7500 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7501 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7505 mips_no_prev_insn ();
7507 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7508 history
[i
].cleared_p
= 1;
7511 /* We need to emit a label at the end of branch-likely macros. */
7512 if (emit_branch_likely_macro
)
7514 emit_branch_likely_macro
= FALSE
;
7515 micromips_add_label ();
7518 /* We just output an insn, so the next one doesn't have a label. */
7519 mips_clear_insn_labels ();
7522 /* Forget that there was any previous instruction or label.
7523 When BRANCH is true, the branch history is also flushed. */
7526 mips_no_prev_insn (void)
7528 prev_nop_frag
= NULL
;
7529 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7530 mips_clear_insn_labels ();
7533 /* This function must be called before we emit something other than
7534 instructions. It is like mips_no_prev_insn except that it inserts
7535 any NOPS that might be needed by previous instructions. */
7538 mips_emit_delays (void)
7540 if (! mips_opts
.noreorder
)
7542 int nops
= nops_for_insn (0, history
, NULL
);
7546 add_fixed_insn (NOP_INSN
);
7547 mips_move_text_labels ();
7550 mips_no_prev_insn ();
7553 /* Start a (possibly nested) noreorder block. */
7556 start_noreorder (void)
7558 if (mips_opts
.noreorder
== 0)
7563 /* None of the instructions before the .set noreorder can be moved. */
7564 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7565 history
[i
].fixed_p
= 1;
7567 /* Insert any nops that might be needed between the .set noreorder
7568 block and the previous instructions. We will later remove any
7569 nops that turn out not to be needed. */
7570 nops
= nops_for_insn (0, history
, NULL
);
7573 if (mips_optimize
!= 0)
7575 /* Record the frag which holds the nop instructions, so
7576 that we can remove them if we don't need them. */
7577 frag_grow (nops
* NOP_INSN_SIZE
);
7578 prev_nop_frag
= frag_now
;
7579 prev_nop_frag_holds
= nops
;
7580 prev_nop_frag_required
= 0;
7581 prev_nop_frag_since
= 0;
7584 for (; nops
> 0; --nops
)
7585 add_fixed_insn (NOP_INSN
);
7587 /* Move on to a new frag, so that it is safe to simply
7588 decrease the size of prev_nop_frag. */
7589 frag_wane (frag_now
);
7591 mips_move_text_labels ();
7593 mips_mark_labels ();
7594 mips_clear_insn_labels ();
7596 mips_opts
.noreorder
++;
7597 mips_any_noreorder
= 1;
7600 /* End a nested noreorder block. */
7603 end_noreorder (void)
7605 mips_opts
.noreorder
--;
7606 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7608 /* Commit to inserting prev_nop_frag_required nops and go back to
7609 handling nop insertion the .set reorder way. */
7610 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7612 insert_into_history (prev_nop_frag_since
,
7613 prev_nop_frag_required
, NOP_INSN
);
7614 prev_nop_frag
= NULL
;
7618 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7619 higher bits unset. */
7622 normalize_constant_expr (expressionS
*ex
)
7624 if (ex
->X_op
== O_constant
7625 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7626 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7630 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7631 all higher bits unset. */
7634 normalize_address_expr (expressionS
*ex
)
7636 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7637 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7638 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7639 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7643 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7644 Return true if the match was successful.
7646 OPCODE_EXTRA is a value that should be ORed into the opcode
7647 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7648 there are more alternatives after OPCODE and SOFT_MATCH is
7649 as for mips_arg_info. */
7652 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7653 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7654 bfd_boolean lax_match
, bfd_boolean complete_p
)
7657 struct mips_arg_info arg
;
7658 const struct mips_operand
*operand
;
7661 imm_expr
.X_op
= O_absent
;
7662 offset_expr
.X_op
= O_absent
;
7663 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7664 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7665 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7667 create_insn (insn
, opcode
);
7668 /* When no opcode suffix is specified, assume ".xyzw". */
7669 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7670 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7672 insn
->insn_opcode
|= opcode_extra
;
7673 memset (&arg
, 0, sizeof (arg
));
7677 arg
.last_regno
= ILLEGAL_REG
;
7678 arg
.dest_regno
= ILLEGAL_REG
;
7679 arg
.lax_match
= lax_match
;
7680 for (args
= opcode
->args
;; ++args
)
7682 if (arg
.token
->type
== OT_END
)
7684 /* Handle unary instructions in which only one operand is given.
7685 The source is then the same as the destination. */
7686 if (arg
.opnum
== 1 && *args
== ',')
7688 operand
= (mips_opts
.micromips
7689 ? decode_micromips_operand (args
+ 1)
7690 : decode_mips_operand (args
+ 1));
7691 if (operand
&& mips_optional_operand_p (operand
))
7699 /* Treat elided base registers as $0. */
7700 if (strcmp (args
, "(b)") == 0)
7708 /* The register suffix is optional. */
7713 /* Fail the match if there were too few operands. */
7717 /* Successful match. */
7720 clear_insn_error ();
7721 if (arg
.dest_regno
== arg
.last_regno
7722 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7726 (0, _("source and destination must be different"));
7727 else if (arg
.last_regno
== 31)
7729 (0, _("a destination register must be supplied"));
7731 else if (arg
.last_regno
== 31
7732 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7733 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7734 set_insn_error (0, _("the source register must not be $31"));
7735 check_completed_insn (&arg
);
7739 /* Fail the match if the line has too many operands. */
7743 /* Handle characters that need to match exactly. */
7744 if (*args
== '(' || *args
== ')' || *args
== ',')
7746 if (match_char (&arg
, *args
))
7753 if (arg
.token
->type
== OT_DOUBLE_CHAR
7754 && arg
.token
->u
.ch
== *args
)
7762 /* Handle special macro operands. Work out the properties of
7771 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7775 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7784 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7788 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
7792 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
7798 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7800 imm_expr
.X_op
= O_constant
;
7802 normalize_constant_expr (&imm_expr
);
7806 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7808 /* Assume that the offset has been elided and that what
7809 we saw was a base register. The match will fail later
7810 if that assumption turns out to be wrong. */
7811 offset_expr
.X_op
= O_constant
;
7812 offset_expr
.X_add_number
= 0;
7816 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7818 normalize_address_expr (&offset_expr
);
7823 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7829 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7835 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7841 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7847 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7851 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7855 gas_assert (mips_opts
.micromips
);
7861 if (!forced_insn_length
)
7862 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7864 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7866 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7872 operand
= (mips_opts
.micromips
7873 ? decode_micromips_operand (args
)
7874 : decode_mips_operand (args
));
7878 /* Skip prefixes. */
7879 if (*args
== '+' || *args
== 'm' || *args
== '-')
7882 if (mips_optional_operand_p (operand
)
7884 && (arg
.token
[0].type
!= OT_REG
7885 || arg
.token
[1].type
== OT_END
))
7887 /* Assume that the register has been elided and is the
7888 same as the first operand. */
7893 if (!match_operand (&arg
, operand
))
7898 /* Like match_insn, but for MIPS16. */
7901 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7902 struct mips_operand_token
*tokens
)
7905 const struct mips_operand
*operand
;
7906 const struct mips_operand
*ext_operand
;
7907 struct mips_arg_info arg
;
7910 create_insn (insn
, opcode
);
7911 imm_expr
.X_op
= O_absent
;
7912 offset_expr
.X_op
= O_absent
;
7913 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7914 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7915 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7918 memset (&arg
, 0, sizeof (arg
));
7922 arg
.last_regno
= ILLEGAL_REG
;
7923 arg
.dest_regno
= ILLEGAL_REG
;
7925 for (args
= opcode
->args
;; ++args
)
7929 if (arg
.token
->type
== OT_END
)
7933 /* Handle unary instructions in which only one operand is given.
7934 The source is then the same as the destination. */
7935 if (arg
.opnum
== 1 && *args
== ',')
7937 operand
= decode_mips16_operand (args
[1], FALSE
);
7938 if (operand
&& mips_optional_operand_p (operand
))
7946 /* Fail the match if there were too few operands. */
7950 /* Successful match. Stuff the immediate value in now, if
7952 clear_insn_error ();
7953 if (opcode
->pinfo
== INSN_MACRO
)
7955 gas_assert (relax_char
== 0 || relax_char
== 'p');
7956 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7959 && offset_expr
.X_op
== O_constant
7960 && calculate_reloc (*offset_reloc
,
7961 offset_expr
.X_add_number
,
7964 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7965 forced_insn_length
, &insn
->insn_opcode
);
7966 offset_expr
.X_op
= O_absent
;
7967 *offset_reloc
= BFD_RELOC_UNUSED
;
7969 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7971 if (forced_insn_length
== 2)
7972 set_insn_error (0, _("invalid unextended operand value"));
7973 forced_insn_length
= 4;
7974 insn
->insn_opcode
|= MIPS16_EXTEND
;
7976 else if (relax_char
)
7977 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7979 check_completed_insn (&arg
);
7983 /* Fail the match if the line has too many operands. */
7987 /* Handle characters that need to match exactly. */
7988 if (*args
== '(' || *args
== ')' || *args
== ',')
7990 if (match_char (&arg
, *args
))
8008 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8010 imm_expr
.X_op
= O_constant
;
8012 normalize_constant_expr (&imm_expr
);
8017 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8018 insn
->insn_opcode
<<= 16;
8022 operand
= decode_mips16_operand (c
, FALSE
);
8026 /* '6' is a special case. It is used for BREAK and SDBBP,
8027 whose operands are only meaningful to the software that decodes
8028 them. This means that there is no architectural reason why
8029 they cannot be prefixed by EXTEND, but in practice,
8030 exception handlers will only look at the instruction
8031 itself. We therefore allow '6' to be extended when
8032 disassembling but not when assembling. */
8033 if (operand
->type
!= OP_PCREL
&& c
!= '6')
8035 ext_operand
= decode_mips16_operand (c
, TRUE
);
8036 if (operand
!= ext_operand
)
8038 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8040 offset_expr
.X_op
= O_constant
;
8041 offset_expr
.X_add_number
= 0;
8046 /* We need the OT_INTEGER check because some MIPS16
8047 immediate variants are listed before the register ones. */
8048 if (arg
.token
->type
!= OT_INTEGER
8049 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
8052 /* '8' is used for SLTI(U) and has traditionally not
8053 been allowed to take relocation operators. */
8054 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8055 && (ext_operand
->size
!= 16 || c
== '8'))
8063 if (mips_optional_operand_p (operand
)
8065 && (arg
.token
[0].type
!= OT_REG
8066 || arg
.token
[1].type
== OT_END
))
8068 /* Assume that the register has been elided and is the
8069 same as the first operand. */
8074 if (!match_operand (&arg
, operand
))
8079 /* Record that the current instruction is invalid for the current ISA. */
8082 match_invalid_for_isa (void)
8085 (0, _("opcode not supported on this processor: %s (%s)"),
8086 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8087 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8090 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8091 Return true if a definite match or failure was found, storing any match
8092 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8093 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8094 tried and failed to match under normal conditions and now want to try a
8095 more relaxed match. */
8098 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8099 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8100 int opcode_extra
, bfd_boolean lax_match
)
8102 const struct mips_opcode
*opcode
;
8103 const struct mips_opcode
*invalid_delay_slot
;
8104 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8106 /* Search for a match, ignoring alternatives that don't satisfy the
8107 current ISA or forced_length. */
8108 invalid_delay_slot
= 0;
8109 seen_valid_for_isa
= FALSE
;
8110 seen_valid_for_size
= FALSE
;
8114 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8115 if (is_opcode_valid (opcode
))
8117 seen_valid_for_isa
= TRUE
;
8118 if (is_size_valid (opcode
))
8120 bfd_boolean delay_slot_ok
;
8122 seen_valid_for_size
= TRUE
;
8123 delay_slot_ok
= is_delay_slot_valid (opcode
);
8124 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8125 lax_match
, delay_slot_ok
))
8129 if (!invalid_delay_slot
)
8130 invalid_delay_slot
= opcode
;
8139 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8141 /* If the only matches we found had the wrong length for the delay slot,
8142 pick the first such match. We'll issue an appropriate warning later. */
8143 if (invalid_delay_slot
)
8145 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8151 /* Handle the case where we didn't try to match an instruction because
8152 all the alternatives were incompatible with the current ISA. */
8153 if (!seen_valid_for_isa
)
8155 match_invalid_for_isa ();
8159 /* Handle the case where we didn't try to match an instruction because
8160 all the alternatives were of the wrong size. */
8161 if (!seen_valid_for_size
)
8163 if (mips_opts
.insn32
)
8164 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8167 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8168 8 * forced_insn_length
);
8175 /* Like match_insns, but for MIPS16. */
8178 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8179 struct mips_operand_token
*tokens
)
8181 const struct mips_opcode
*opcode
;
8182 bfd_boolean seen_valid_for_isa
;
8184 /* Search for a match, ignoring alternatives that don't satisfy the
8185 current ISA. There are no separate entries for extended forms so
8186 we deal with forced_length later. */
8187 seen_valid_for_isa
= FALSE
;
8191 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8192 if (is_opcode_valid_16 (opcode
))
8194 seen_valid_for_isa
= TRUE
;
8195 if (match_mips16_insn (insn
, opcode
, tokens
))
8200 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8201 && strcmp (opcode
->name
, first
->name
) == 0);
8203 /* Handle the case where we didn't try to match an instruction because
8204 all the alternatives were incompatible with the current ISA. */
8205 if (!seen_valid_for_isa
)
8207 match_invalid_for_isa ();
8214 /* Set up global variables for the start of a new macro. */
8219 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8220 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8221 sizeof (mips_macro_warning
.first_insn_sizes
));
8222 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8223 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8224 && delayed_branch_p (&history
[0]));
8225 switch (history
[0].insn_mo
->pinfo2
8226 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8228 case INSN2_BRANCH_DELAY_32BIT
:
8229 mips_macro_warning
.delay_slot_length
= 4;
8231 case INSN2_BRANCH_DELAY_16BIT
:
8232 mips_macro_warning
.delay_slot_length
= 2;
8235 mips_macro_warning
.delay_slot_length
= 0;
8238 mips_macro_warning
.first_frag
= NULL
;
8241 /* Given that a macro is longer than one instruction or of the wrong size,
8242 return the appropriate warning for it. Return null if no warning is
8243 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8244 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8245 and RELAX_NOMACRO. */
8248 macro_warning (relax_substateT subtype
)
8250 if (subtype
& RELAX_DELAY_SLOT
)
8251 return _("macro instruction expanded into multiple instructions"
8252 " in a branch delay slot");
8253 else if (subtype
& RELAX_NOMACRO
)
8254 return _("macro instruction expanded into multiple instructions");
8255 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8256 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8257 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8258 ? _("macro instruction expanded into a wrong size instruction"
8259 " in a 16-bit branch delay slot")
8260 : _("macro instruction expanded into a wrong size instruction"
8261 " in a 32-bit branch delay slot"));
8266 /* Finish up a macro. Emit warnings as appropriate. */
8271 /* Relaxation warning flags. */
8272 relax_substateT subtype
= 0;
8274 /* Check delay slot size requirements. */
8275 if (mips_macro_warning
.delay_slot_length
== 2)
8276 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8277 if (mips_macro_warning
.delay_slot_length
!= 0)
8279 if (mips_macro_warning
.delay_slot_length
8280 != mips_macro_warning
.first_insn_sizes
[0])
8281 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8282 if (mips_macro_warning
.delay_slot_length
8283 != mips_macro_warning
.first_insn_sizes
[1])
8284 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8287 /* Check instruction count requirements. */
8288 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8290 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8291 subtype
|= RELAX_SECOND_LONGER
;
8292 if (mips_opts
.warn_about_macros
)
8293 subtype
|= RELAX_NOMACRO
;
8294 if (mips_macro_warning
.delay_slot_p
)
8295 subtype
|= RELAX_DELAY_SLOT
;
8298 /* If both alternatives fail to fill a delay slot correctly,
8299 emit the warning now. */
8300 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8301 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8306 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8307 | RELAX_DELAY_SLOT_SIZE_FIRST
8308 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8309 msg
= macro_warning (s
);
8311 as_warn ("%s", msg
);
8315 /* If both implementations are longer than 1 instruction, then emit the
8317 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8322 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8323 msg
= macro_warning (s
);
8325 as_warn ("%s", msg
);
8329 /* If any flags still set, then one implementation might need a warning
8330 and the other either will need one of a different kind or none at all.
8331 Pass any remaining flags over to relaxation. */
8332 if (mips_macro_warning
.first_frag
!= NULL
)
8333 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8336 /* Instruction operand formats used in macros that vary between
8337 standard MIPS and microMIPS code. */
8339 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8340 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8341 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8342 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8343 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8344 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8345 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8346 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8348 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8349 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8350 : cop12_fmt[mips_opts.micromips])
8351 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8352 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8353 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8354 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8355 : mem12_fmt[mips_opts.micromips])
8356 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8357 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8358 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8360 /* Read a macro's relocation codes from *ARGS and store them in *R.
8361 The first argument in *ARGS will be either the code for a single
8362 relocation or -1 followed by the three codes that make up a
8363 composite relocation. */
8366 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8370 next
= va_arg (*args
, int);
8372 r
[0] = (bfd_reloc_code_real_type
) next
;
8375 for (i
= 0; i
< 3; i
++)
8376 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8377 /* This function is only used for 16-bit relocation fields.
8378 To make the macro code simpler, treat an unrelocated value
8379 in the same way as BFD_RELOC_LO16. */
8380 if (r
[0] == BFD_RELOC_UNUSED
)
8381 r
[0] = BFD_RELOC_LO16
;
8385 /* Build an instruction created by a macro expansion. This is passed
8386 a pointer to the count of instructions created so far, an
8387 expression, the name of the instruction to build, an operand format
8388 string, and corresponding arguments. */
8391 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8393 const struct mips_opcode
*mo
= NULL
;
8394 bfd_reloc_code_real_type r
[3];
8395 const struct mips_opcode
*amo
;
8396 const struct mips_operand
*operand
;
8397 struct hash_control
*hash
;
8398 struct mips_cl_insn insn
;
8402 va_start (args
, fmt
);
8404 if (mips_opts
.mips16
)
8406 mips16_macro_build (ep
, name
, fmt
, &args
);
8411 r
[0] = BFD_RELOC_UNUSED
;
8412 r
[1] = BFD_RELOC_UNUSED
;
8413 r
[2] = BFD_RELOC_UNUSED
;
8414 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8415 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8417 gas_assert (strcmp (name
, amo
->name
) == 0);
8421 /* Search until we get a match for NAME. It is assumed here that
8422 macros will never generate MDMX, MIPS-3D, or MT instructions.
8423 We try to match an instruction that fulfils the branch delay
8424 slot instruction length requirement (if any) of the previous
8425 instruction. While doing this we record the first instruction
8426 seen that matches all the other conditions and use it anyway
8427 if the requirement cannot be met; we will issue an appropriate
8428 warning later on. */
8429 if (strcmp (fmt
, amo
->args
) == 0
8430 && amo
->pinfo
!= INSN_MACRO
8431 && is_opcode_valid (amo
)
8432 && is_size_valid (amo
))
8434 if (is_delay_slot_valid (amo
))
8444 gas_assert (amo
->name
);
8446 while (strcmp (name
, amo
->name
) == 0);
8449 create_insn (&insn
, mo
);
8462 macro_read_relocs (&args
, r
);
8463 gas_assert (*r
== BFD_RELOC_GPREL16
8464 || *r
== BFD_RELOC_MIPS_HIGHER
8465 || *r
== BFD_RELOC_HI16_S
8466 || *r
== BFD_RELOC_LO16
8467 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8471 macro_read_relocs (&args
, r
);
8475 macro_read_relocs (&args
, r
);
8476 gas_assert (ep
!= NULL
8477 && (ep
->X_op
== O_constant
8478 || (ep
->X_op
== O_symbol
8479 && (*r
== BFD_RELOC_MIPS_HIGHEST
8480 || *r
== BFD_RELOC_HI16_S
8481 || *r
== BFD_RELOC_HI16
8482 || *r
== BFD_RELOC_GPREL16
8483 || *r
== BFD_RELOC_MIPS_GOT_HI16
8484 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8488 gas_assert (ep
!= NULL
);
8491 * This allows macro() to pass an immediate expression for
8492 * creating short branches without creating a symbol.
8494 * We don't allow branch relaxation for these branches, as
8495 * they should only appear in ".set nomacro" anyway.
8497 if (ep
->X_op
== O_constant
)
8499 /* For microMIPS we always use relocations for branches.
8500 So we should not resolve immediate values. */
8501 gas_assert (!mips_opts
.micromips
);
8503 if ((ep
->X_add_number
& 3) != 0)
8504 as_bad (_("branch to misaligned address (0x%lx)"),
8505 (unsigned long) ep
->X_add_number
);
8506 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8507 as_bad (_("branch address range overflow (0x%lx)"),
8508 (unsigned long) ep
->X_add_number
);
8509 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8513 *r
= BFD_RELOC_16_PCREL_S2
;
8517 gas_assert (ep
!= NULL
);
8518 *r
= BFD_RELOC_MIPS_JMP
;
8522 operand
= (mips_opts
.micromips
8523 ? decode_micromips_operand (fmt
)
8524 : decode_mips_operand (fmt
));
8528 uval
= va_arg (args
, int);
8529 if (operand
->type
== OP_CLO_CLZ_DEST
)
8530 uval
|= (uval
<< 5);
8531 insn_insert_operand (&insn
, operand
, uval
);
8533 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8539 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8541 append_insn (&insn
, ep
, r
, TRUE
);
8545 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8548 struct mips_opcode
*mo
;
8549 struct mips_cl_insn insn
;
8550 const struct mips_operand
*operand
;
8551 bfd_reloc_code_real_type r
[3]
8552 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8554 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8556 gas_assert (strcmp (name
, mo
->name
) == 0);
8558 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8561 gas_assert (mo
->name
);
8562 gas_assert (strcmp (name
, mo
->name
) == 0);
8565 create_insn (&insn
, mo
);
8603 gas_assert (ep
!= NULL
);
8605 if (ep
->X_op
!= O_constant
)
8606 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8607 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8609 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8611 *r
= BFD_RELOC_UNUSED
;
8617 operand
= decode_mips16_operand (c
, FALSE
);
8621 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8626 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8628 append_insn (&insn
, ep
, r
, TRUE
);
8632 * Generate a "jalr" instruction with a relocation hint to the called
8633 * function. This occurs in NewABI PIC code.
8636 macro_build_jalr (expressionS
*ep
, int cprestore
)
8638 static const bfd_reloc_code_real_type jalr_relocs
[2]
8639 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8640 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8644 if (MIPS_JALR_HINT_P (ep
))
8649 if (mips_opts
.micromips
)
8651 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8652 ? "jalr" : "jalrs");
8653 if (MIPS_JALR_HINT_P (ep
)
8655 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8656 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8658 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8661 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8662 if (MIPS_JALR_HINT_P (ep
))
8663 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8667 * Generate a "lui" instruction.
8670 macro_build_lui (expressionS
*ep
, int regnum
)
8672 gas_assert (! mips_opts
.mips16
);
8674 if (ep
->X_op
!= O_constant
)
8676 gas_assert (ep
->X_op
== O_symbol
);
8677 /* _gp_disp is a special case, used from s_cpload.
8678 __gnu_local_gp is used if mips_no_shared. */
8679 gas_assert (mips_pic
== NO_PIC
8681 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8682 || (! mips_in_shared
8683 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8684 "__gnu_local_gp") == 0));
8687 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8690 /* Generate a sequence of instructions to do a load or store from a constant
8691 offset off of a base register (breg) into/from a target register (treg),
8692 using AT if necessary. */
8694 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8695 int treg
, int breg
, int dbl
)
8697 gas_assert (ep
->X_op
== O_constant
);
8699 /* Sign-extending 32-bit constants makes their handling easier. */
8701 normalize_constant_expr (ep
);
8703 /* Right now, this routine can only handle signed 32-bit constants. */
8704 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8705 as_warn (_("operand overflow"));
8707 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8709 /* Signed 16-bit offset will fit in the op. Easy! */
8710 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8714 /* 32-bit offset, need multiple instructions and AT, like:
8715 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8716 addu $tempreg,$tempreg,$breg
8717 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8718 to handle the complete offset. */
8719 macro_build_lui (ep
, AT
);
8720 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8721 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8724 as_bad (_("macro used $at after \".set noat\""));
8729 * Generates code to set the $at register to true (one)
8730 * if reg is less than the immediate expression.
8733 set_at (int reg
, int unsignedp
)
8735 if (imm_expr
.X_add_number
>= -0x8000
8736 && imm_expr
.X_add_number
< 0x8000)
8737 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8738 AT
, reg
, BFD_RELOC_LO16
);
8741 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8742 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8746 /* Count the leading zeroes by performing a binary chop. This is a
8747 bulky bit of source, but performance is a LOT better for the
8748 majority of values than a simple loop to count the bits:
8749 for (lcnt = 0; (lcnt < 32); lcnt++)
8750 if ((v) & (1 << (31 - lcnt)))
8752 However it is not code size friendly, and the gain will drop a bit
8753 on certain cached systems.
8755 #define COUNT_TOP_ZEROES(v) \
8756 (((v) & ~0xffff) == 0 \
8757 ? ((v) & ~0xff) == 0 \
8758 ? ((v) & ~0xf) == 0 \
8759 ? ((v) & ~0x3) == 0 \
8760 ? ((v) & ~0x1) == 0 \
8765 : ((v) & ~0x7) == 0 \
8768 : ((v) & ~0x3f) == 0 \
8769 ? ((v) & ~0x1f) == 0 \
8772 : ((v) & ~0x7f) == 0 \
8775 : ((v) & ~0xfff) == 0 \
8776 ? ((v) & ~0x3ff) == 0 \
8777 ? ((v) & ~0x1ff) == 0 \
8780 : ((v) & ~0x7ff) == 0 \
8783 : ((v) & ~0x3fff) == 0 \
8784 ? ((v) & ~0x1fff) == 0 \
8787 : ((v) & ~0x7fff) == 0 \
8790 : ((v) & ~0xffffff) == 0 \
8791 ? ((v) & ~0xfffff) == 0 \
8792 ? ((v) & ~0x3ffff) == 0 \
8793 ? ((v) & ~0x1ffff) == 0 \
8796 : ((v) & ~0x7ffff) == 0 \
8799 : ((v) & ~0x3fffff) == 0 \
8800 ? ((v) & ~0x1fffff) == 0 \
8803 : ((v) & ~0x7fffff) == 0 \
8806 : ((v) & ~0xfffffff) == 0 \
8807 ? ((v) & ~0x3ffffff) == 0 \
8808 ? ((v) & ~0x1ffffff) == 0 \
8811 : ((v) & ~0x7ffffff) == 0 \
8814 : ((v) & ~0x3fffffff) == 0 \
8815 ? ((v) & ~0x1fffffff) == 0 \
8818 : ((v) & ~0x7fffffff) == 0 \
8823 * This routine generates the least number of instructions necessary to load
8824 * an absolute expression value into a register.
8827 load_register (int reg
, expressionS
*ep
, int dbl
)
8830 expressionS hi32
, lo32
;
8832 if (ep
->X_op
!= O_big
)
8834 gas_assert (ep
->X_op
== O_constant
);
8836 /* Sign-extending 32-bit constants makes their handling easier. */
8838 normalize_constant_expr (ep
);
8840 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8842 /* We can handle 16 bit signed values with an addiu to
8843 $zero. No need to ever use daddiu here, since $zero and
8844 the result are always correct in 32 bit mode. */
8845 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8848 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8850 /* We can handle 16 bit unsigned values with an ori to
8852 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8855 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8857 /* 32 bit values require an lui. */
8858 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8859 if ((ep
->X_add_number
& 0xffff) != 0)
8860 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8865 /* The value is larger than 32 bits. */
8867 if (!dbl
|| GPR_SIZE
== 32)
8871 sprintf_vma (value
, ep
->X_add_number
);
8872 as_bad (_("number (0x%s) larger than 32 bits"), value
);
8873 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8877 if (ep
->X_op
!= O_big
)
8880 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8881 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8882 hi32
.X_add_number
&= 0xffffffff;
8884 lo32
.X_add_number
&= 0xffffffff;
8888 gas_assert (ep
->X_add_number
> 2);
8889 if (ep
->X_add_number
== 3)
8890 generic_bignum
[3] = 0;
8891 else if (ep
->X_add_number
> 4)
8892 as_bad (_("number larger than 64 bits"));
8893 lo32
.X_op
= O_constant
;
8894 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8895 hi32
.X_op
= O_constant
;
8896 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8899 if (hi32
.X_add_number
== 0)
8904 unsigned long hi
, lo
;
8906 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8908 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8910 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8913 if (lo32
.X_add_number
& 0x80000000)
8915 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8916 if (lo32
.X_add_number
& 0xffff)
8917 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8922 /* Check for 16bit shifted constant. We know that hi32 is
8923 non-zero, so start the mask on the first bit of the hi32
8928 unsigned long himask
, lomask
;
8932 himask
= 0xffff >> (32 - shift
);
8933 lomask
= (0xffff << shift
) & 0xffffffff;
8937 himask
= 0xffff << (shift
- 32);
8940 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8941 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8945 tmp
.X_op
= O_constant
;
8947 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8948 | (lo32
.X_add_number
>> shift
));
8950 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8951 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8952 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8953 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8958 while (shift
<= (64 - 16));
8960 /* Find the bit number of the lowest one bit, and store the
8961 shifted value in hi/lo. */
8962 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8963 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8967 while ((lo
& 1) == 0)
8972 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8978 while ((hi
& 1) == 0)
8987 /* Optimize if the shifted value is a (power of 2) - 1. */
8988 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8989 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8991 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8996 /* This instruction will set the register to be all
8998 tmp
.X_op
= O_constant
;
8999 tmp
.X_add_number
= (offsetT
) -1;
9000 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9004 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9005 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9007 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9008 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9013 /* Sign extend hi32 before calling load_register, because we can
9014 generally get better code when we load a sign extended value. */
9015 if ((hi32
.X_add_number
& 0x80000000) != 0)
9016 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9017 load_register (reg
, &hi32
, 0);
9020 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9024 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9032 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9034 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9035 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9041 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9045 mid16
.X_add_number
>>= 16;
9046 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9047 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9050 if ((lo32
.X_add_number
& 0xffff) != 0)
9051 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9055 load_delay_nop (void)
9057 if (!gpr_interlocks
)
9058 macro_build (NULL
, "nop", "");
9061 /* Load an address into a register. */
9064 load_address (int reg
, expressionS
*ep
, int *used_at
)
9066 if (ep
->X_op
!= O_constant
9067 && ep
->X_op
!= O_symbol
)
9069 as_bad (_("expression too complex"));
9070 ep
->X_op
= O_constant
;
9073 if (ep
->X_op
== O_constant
)
9075 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9079 if (mips_pic
== NO_PIC
)
9081 /* If this is a reference to a GP relative symbol, we want
9082 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9084 lui $reg,<sym> (BFD_RELOC_HI16_S)
9085 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9086 If we have an addend, we always use the latter form.
9088 With 64bit address space and a usable $at we want
9089 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9090 lui $at,<sym> (BFD_RELOC_HI16_S)
9091 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9092 daddiu $at,<sym> (BFD_RELOC_LO16)
9096 If $at is already in use, we use a path which is suboptimal
9097 on superscalar processors.
9098 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9099 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9101 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9103 daddiu $reg,<sym> (BFD_RELOC_LO16)
9105 For GP relative symbols in 64bit address space we can use
9106 the same sequence as in 32bit address space. */
9107 if (HAVE_64BIT_SYMBOLS
)
9109 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9110 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9112 relax_start (ep
->X_add_symbol
);
9113 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9114 mips_gp_register
, BFD_RELOC_GPREL16
);
9118 if (*used_at
== 0 && mips_opts
.at
)
9120 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9121 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9122 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9123 BFD_RELOC_MIPS_HIGHER
);
9124 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9125 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9126 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9131 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9132 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9133 BFD_RELOC_MIPS_HIGHER
);
9134 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9135 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9136 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9137 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9140 if (mips_relax
.sequence
)
9145 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9146 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9148 relax_start (ep
->X_add_symbol
);
9149 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9150 mips_gp_register
, BFD_RELOC_GPREL16
);
9153 macro_build_lui (ep
, reg
);
9154 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9155 reg
, reg
, BFD_RELOC_LO16
);
9156 if (mips_relax
.sequence
)
9160 else if (!mips_big_got
)
9164 /* If this is a reference to an external symbol, we want
9165 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9167 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9169 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9170 If there is a constant, it must be added in after.
9172 If we have NewABI, we want
9173 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9174 unless we're referencing a global symbol with a non-zero
9175 offset, in which case cst must be added separately. */
9178 if (ep
->X_add_number
)
9180 ex
.X_add_number
= ep
->X_add_number
;
9181 ep
->X_add_number
= 0;
9182 relax_start (ep
->X_add_symbol
);
9183 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9184 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9185 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9186 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9187 ex
.X_op
= O_constant
;
9188 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9189 reg
, reg
, BFD_RELOC_LO16
);
9190 ep
->X_add_number
= ex
.X_add_number
;
9193 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9194 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9195 if (mips_relax
.sequence
)
9200 ex
.X_add_number
= ep
->X_add_number
;
9201 ep
->X_add_number
= 0;
9202 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9203 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9205 relax_start (ep
->X_add_symbol
);
9207 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9211 if (ex
.X_add_number
!= 0)
9213 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9214 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9215 ex
.X_op
= O_constant
;
9216 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9217 reg
, reg
, BFD_RELOC_LO16
);
9221 else if (mips_big_got
)
9225 /* This is the large GOT case. If this is a reference to an
9226 external symbol, we want
9227 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9229 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9231 Otherwise, for a reference to a local symbol in old ABI, we want
9232 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9234 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9235 If there is a constant, it must be added in after.
9237 In the NewABI, for local symbols, with or without offsets, we want:
9238 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9239 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9243 ex
.X_add_number
= ep
->X_add_number
;
9244 ep
->X_add_number
= 0;
9245 relax_start (ep
->X_add_symbol
);
9246 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9247 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9248 reg
, reg
, mips_gp_register
);
9249 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9250 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9251 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9252 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9253 else if (ex
.X_add_number
)
9255 ex
.X_op
= O_constant
;
9256 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9260 ep
->X_add_number
= ex
.X_add_number
;
9262 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9263 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9264 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9265 BFD_RELOC_MIPS_GOT_OFST
);
9270 ex
.X_add_number
= ep
->X_add_number
;
9271 ep
->X_add_number
= 0;
9272 relax_start (ep
->X_add_symbol
);
9273 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9274 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9275 reg
, reg
, mips_gp_register
);
9276 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9277 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9279 if (reg_needs_delay (mips_gp_register
))
9281 /* We need a nop before loading from $gp. This special
9282 check is required because the lui which starts the main
9283 instruction stream does not refer to $gp, and so will not
9284 insert the nop which may be required. */
9285 macro_build (NULL
, "nop", "");
9287 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9288 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9290 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9294 if (ex
.X_add_number
!= 0)
9296 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9297 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9298 ex
.X_op
= O_constant
;
9299 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9307 if (!mips_opts
.at
&& *used_at
== 1)
9308 as_bad (_("macro used $at after \".set noat\""));
9311 /* Move the contents of register SOURCE into register DEST. */
9314 move_register (int dest
, int source
)
9316 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9317 instruction specifically requires a 32-bit one. */
9318 if (mips_opts
.micromips
9319 && !mips_opts
.insn32
9320 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9321 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9323 macro_build (NULL
, GPR_SIZE
== 32 ? "addu" : "daddu", "d,v,t",
9327 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9328 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9329 The two alternatives are:
9331 Global symbol Local sybmol
9332 ------------- ------------
9333 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9335 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9337 load_got_offset emits the first instruction and add_got_offset
9338 emits the second for a 16-bit offset or add_got_offset_hilo emits
9339 a sequence to add a 32-bit offset using a scratch register. */
9342 load_got_offset (int dest
, expressionS
*local
)
9347 global
.X_add_number
= 0;
9349 relax_start (local
->X_add_symbol
);
9350 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9351 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9353 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9354 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9359 add_got_offset (int dest
, expressionS
*local
)
9363 global
.X_op
= O_constant
;
9364 global
.X_op_symbol
= NULL
;
9365 global
.X_add_symbol
= NULL
;
9366 global
.X_add_number
= local
->X_add_number
;
9368 relax_start (local
->X_add_symbol
);
9369 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9370 dest
, dest
, BFD_RELOC_LO16
);
9372 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9377 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9380 int hold_mips_optimize
;
9382 global
.X_op
= O_constant
;
9383 global
.X_op_symbol
= NULL
;
9384 global
.X_add_symbol
= NULL
;
9385 global
.X_add_number
= local
->X_add_number
;
9387 relax_start (local
->X_add_symbol
);
9388 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9390 /* Set mips_optimize around the lui instruction to avoid
9391 inserting an unnecessary nop after the lw. */
9392 hold_mips_optimize
= mips_optimize
;
9394 macro_build_lui (&global
, tmp
);
9395 mips_optimize
= hold_mips_optimize
;
9396 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9399 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9402 /* Emit a sequence of instructions to emulate a branch likely operation.
9403 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9404 is its complementing branch with the original condition negated.
9405 CALL is set if the original branch specified the link operation.
9406 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9408 Code like this is produced in the noreorder mode:
9413 delay slot (executed only if branch taken)
9421 delay slot (executed only if branch taken)
9424 In the reorder mode the delay slot would be filled with a nop anyway,
9425 so code produced is simply:
9430 This function is used when producing code for the microMIPS ASE that
9431 does not implement branch likely instructions in hardware. */
9434 macro_build_branch_likely (const char *br
, const char *brneg
,
9435 int call
, expressionS
*ep
, const char *fmt
,
9436 unsigned int sreg
, unsigned int treg
)
9438 int noreorder
= mips_opts
.noreorder
;
9441 gas_assert (mips_opts
.micromips
);
9445 micromips_label_expr (&expr1
);
9446 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9447 macro_build (NULL
, "nop", "");
9448 macro_build (ep
, call
? "bal" : "b", "p");
9450 /* Set to true so that append_insn adds a label. */
9451 emit_branch_likely_macro
= TRUE
;
9455 macro_build (ep
, br
, fmt
, sreg
, treg
);
9456 macro_build (NULL
, "nop", "");
9461 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9462 the condition code tested. EP specifies the branch target. */
9465 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9492 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9495 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9496 the register tested. EP specifies the branch target. */
9499 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9501 const char *brneg
= NULL
;
9511 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9515 gas_assert (mips_opts
.micromips
);
9516 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9524 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9531 br
= mips_opts
.micromips
? "blez" : "blezl";
9538 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9542 gas_assert (mips_opts
.micromips
);
9543 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9550 if (mips_opts
.micromips
&& brneg
)
9551 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9553 macro_build (ep
, br
, "s,p", sreg
);
9556 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9557 TREG as the registers tested. EP specifies the branch target. */
9560 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9561 unsigned int sreg
, unsigned int treg
)
9563 const char *brneg
= NULL
;
9575 br
= mips_opts
.micromips
? "beq" : "beql";
9584 br
= mips_opts
.micromips
? "bne" : "bnel";
9590 if (mips_opts
.micromips
&& brneg
)
9591 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9593 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9596 /* Return the high part that should be loaded in order to make the low
9597 part of VALUE accessible using an offset of OFFBITS bits. */
9600 offset_high_part (offsetT value
, unsigned int offbits
)
9607 bias
= 1 << (offbits
- 1);
9608 low_mask
= bias
* 2 - 1;
9609 return (value
+ bias
) & ~low_mask
;
9612 /* Return true if the value stored in offset_expr and offset_reloc
9613 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9614 amount that the caller wants to add without inducing overflow
9615 and ALIGN is the known alignment of the value in bytes. */
9618 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9622 /* Accept any relocation operator if overflow isn't a concern. */
9623 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9626 /* These relocations are guaranteed not to overflow in correct links. */
9627 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9628 || gprel16_reloc_p (*offset_reloc
))
9631 if (offset_expr
.X_op
== O_constant
9632 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9633 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9640 * This routine implements the seemingly endless macro or synthesized
9641 * instructions and addressing modes in the mips assembly language. Many
9642 * of these macros are simple and are similar to each other. These could
9643 * probably be handled by some kind of table or grammar approach instead of
9644 * this verbose method. Others are not simple macros but are more like
9645 * optimizing code generation.
9646 * One interesting optimization is when several store macros appear
9647 * consecutively that would load AT with the upper half of the same address.
9648 * The ensuing load upper instructions are ommited. This implies some kind
9649 * of global optimization. We currently only optimize within a single macro.
9650 * For many of the load and store macros if the address is specified as a
9651 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9652 * first load register 'at' with zero and use it as the base register. The
9653 * mips assembler simply uses register $zero. Just one tiny optimization
9657 macro (struct mips_cl_insn
*ip
, char *str
)
9659 const struct mips_operand_array
*operands
;
9660 unsigned int breg
, i
;
9661 unsigned int tempreg
;
9664 expressionS label_expr
;
9679 bfd_boolean large_offset
;
9681 int hold_mips_optimize
;
9683 unsigned int op
[MAX_OPERANDS
];
9685 gas_assert (! mips_opts
.mips16
);
9687 operands
= insn_operands (ip
);
9688 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9689 if (operands
->operand
[i
])
9690 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9694 mask
= ip
->insn_mo
->mask
;
9696 label_expr
.X_op
= O_constant
;
9697 label_expr
.X_op_symbol
= NULL
;
9698 label_expr
.X_add_symbol
= NULL
;
9699 label_expr
.X_add_number
= 0;
9701 expr1
.X_op
= O_constant
;
9702 expr1
.X_op_symbol
= NULL
;
9703 expr1
.X_add_symbol
= NULL
;
9704 expr1
.X_add_number
= 1;
9720 if (mips_opts
.micromips
)
9721 micromips_label_expr (&label_expr
);
9723 label_expr
.X_add_number
= 8;
9724 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9726 macro_build (NULL
, "nop", "");
9728 move_register (op
[0], op
[1]);
9729 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9730 if (mips_opts
.micromips
)
9731 micromips_add_label ();
9748 if (!mips_opts
.micromips
)
9750 if (imm_expr
.X_add_number
>= -0x200
9751 && imm_expr
.X_add_number
< 0x200)
9753 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9754 (int) imm_expr
.X_add_number
);
9763 if (imm_expr
.X_add_number
>= -0x8000
9764 && imm_expr
.X_add_number
< 0x8000)
9766 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9771 load_register (AT
, &imm_expr
, dbl
);
9772 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9791 if (imm_expr
.X_add_number
>= 0
9792 && imm_expr
.X_add_number
< 0x10000)
9794 if (mask
!= M_NOR_I
)
9795 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9798 macro_build (&imm_expr
, "ori", "t,r,i",
9799 op
[0], op
[1], BFD_RELOC_LO16
);
9800 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9806 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9807 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9811 switch (imm_expr
.X_add_number
)
9814 macro_build (NULL
, "nop", "");
9817 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9821 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9822 (int) imm_expr
.X_add_number
);
9825 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9826 (unsigned long) imm_expr
.X_add_number
);
9835 gas_assert (mips_opts
.micromips
);
9836 macro_build_branch_ccl (mask
, &offset_expr
,
9837 EXTRACT_OPERAND (1, BCC
, *ip
));
9844 if (imm_expr
.X_add_number
== 0)
9850 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
9855 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9862 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9863 else if (op
[0] == 0)
9864 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9868 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9869 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9870 &offset_expr
, AT
, ZERO
);
9880 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9886 /* Check for > max integer. */
9887 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9890 /* Result is always false. */
9892 macro_build (NULL
, "nop", "");
9894 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9897 ++imm_expr
.X_add_number
;
9901 if (mask
== M_BGEL_I
)
9903 if (imm_expr
.X_add_number
== 0)
9905 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9906 &offset_expr
, op
[0]);
9909 if (imm_expr
.X_add_number
== 1)
9911 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9912 &offset_expr
, op
[0]);
9915 if (imm_expr
.X_add_number
<= GPR_SMIN
)
9918 /* result is always true */
9919 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
9920 macro_build (&offset_expr
, "b", "p");
9925 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9926 &offset_expr
, AT
, ZERO
);
9934 else if (op
[0] == 0)
9935 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9936 &offset_expr
, ZERO
, op
[1]);
9940 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9941 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9942 &offset_expr
, AT
, ZERO
);
9951 && imm_expr
.X_add_number
== -1))
9953 ++imm_expr
.X_add_number
;
9957 if (mask
== M_BGEUL_I
)
9959 if (imm_expr
.X_add_number
== 0)
9961 else if (imm_expr
.X_add_number
== 1)
9962 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9963 &offset_expr
, op
[0], ZERO
);
9968 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9969 &offset_expr
, AT
, ZERO
);
9977 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9978 else if (op
[0] == 0)
9979 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9983 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9984 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9985 &offset_expr
, AT
, ZERO
);
9993 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9994 &offset_expr
, op
[0], ZERO
);
9995 else if (op
[0] == 0)
10000 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10001 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10002 &offset_expr
, AT
, ZERO
);
10010 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10011 else if (op
[0] == 0)
10012 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10016 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10017 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10018 &offset_expr
, AT
, ZERO
);
10025 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10027 ++imm_expr
.X_add_number
;
10031 if (mask
== M_BLTL_I
)
10033 if (imm_expr
.X_add_number
== 0)
10034 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10035 else if (imm_expr
.X_add_number
== 1)
10036 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10041 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10042 &offset_expr
, AT
, ZERO
);
10050 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10051 &offset_expr
, op
[0], ZERO
);
10052 else if (op
[0] == 0)
10057 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10058 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10059 &offset_expr
, AT
, ZERO
);
10068 && imm_expr
.X_add_number
== -1))
10070 ++imm_expr
.X_add_number
;
10074 if (mask
== M_BLTUL_I
)
10076 if (imm_expr
.X_add_number
== 0)
10078 else if (imm_expr
.X_add_number
== 1)
10079 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10080 &offset_expr
, op
[0], ZERO
);
10085 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10086 &offset_expr
, AT
, ZERO
);
10094 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10095 else if (op
[0] == 0)
10096 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10100 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10101 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10102 &offset_expr
, AT
, ZERO
);
10111 else if (op
[0] == 0)
10112 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10113 &offset_expr
, ZERO
, op
[1]);
10117 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10118 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10119 &offset_expr
, AT
, ZERO
);
10135 as_warn (_("divide by zero"));
10137 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10139 macro_build (NULL
, "break", BRK_FMT
, 7);
10143 start_noreorder ();
10146 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10147 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10151 if (mips_opts
.micromips
)
10152 micromips_label_expr (&label_expr
);
10154 label_expr
.X_add_number
= 8;
10155 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10156 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10157 macro_build (NULL
, "break", BRK_FMT
, 7);
10158 if (mips_opts
.micromips
)
10159 micromips_add_label ();
10161 expr1
.X_add_number
= -1;
10163 load_register (AT
, &expr1
, dbl
);
10164 if (mips_opts
.micromips
)
10165 micromips_label_expr (&label_expr
);
10167 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10168 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10171 expr1
.X_add_number
= 1;
10172 load_register (AT
, &expr1
, dbl
);
10173 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10177 expr1
.X_add_number
= 0x80000000;
10178 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10182 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10183 /* We want to close the noreorder block as soon as possible, so
10184 that later insns are available for delay slot filling. */
10189 if (mips_opts
.micromips
)
10190 micromips_label_expr (&label_expr
);
10192 label_expr
.X_add_number
= 8;
10193 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10194 macro_build (NULL
, "nop", "");
10196 /* We want to close the noreorder block as soon as possible, so
10197 that later insns are available for delay slot filling. */
10200 macro_build (NULL
, "break", BRK_FMT
, 6);
10202 if (mips_opts
.micromips
)
10203 micromips_add_label ();
10204 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10243 if (imm_expr
.X_add_number
== 0)
10245 as_warn (_("divide by zero"));
10247 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10249 macro_build (NULL
, "break", BRK_FMT
, 7);
10252 if (imm_expr
.X_add_number
== 1)
10254 if (strcmp (s2
, "mflo") == 0)
10255 move_register (op
[0], op
[1]);
10257 move_register (op
[0], ZERO
);
10260 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10262 if (strcmp (s2
, "mflo") == 0)
10263 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10265 move_register (op
[0], ZERO
);
10270 load_register (AT
, &imm_expr
, dbl
);
10271 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10272 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10291 start_noreorder ();
10294 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10295 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10296 /* We want to close the noreorder block as soon as possible, so
10297 that later insns are available for delay slot filling. */
10302 if (mips_opts
.micromips
)
10303 micromips_label_expr (&label_expr
);
10305 label_expr
.X_add_number
= 8;
10306 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10307 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10309 /* We want to close the noreorder block as soon as possible, so
10310 that later insns are available for delay slot filling. */
10312 macro_build (NULL
, "break", BRK_FMT
, 7);
10313 if (mips_opts
.micromips
)
10314 micromips_add_label ();
10316 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10328 /* Load the address of a symbol into a register. If breg is not
10329 zero, we then add a base register to it. */
10332 if (dbl
&& GPR_SIZE
== 32)
10333 as_warn (_("dla used to load 32-bit register"));
10335 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10336 as_warn (_("la used to load 64-bit address"));
10338 if (small_offset_p (0, align
, 16))
10340 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10341 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10345 if (mips_opts
.at
&& (op
[0] == breg
))
10353 if (offset_expr
.X_op
!= O_symbol
10354 && offset_expr
.X_op
!= O_constant
)
10356 as_bad (_("expression too complex"));
10357 offset_expr
.X_op
= O_constant
;
10360 if (offset_expr
.X_op
== O_constant
)
10361 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10362 else if (mips_pic
== NO_PIC
)
10364 /* If this is a reference to a GP relative symbol, we want
10365 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10367 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10368 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10369 If we have a constant, we need two instructions anyhow,
10370 so we may as well always use the latter form.
10372 With 64bit address space and a usable $at we want
10373 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10374 lui $at,<sym> (BFD_RELOC_HI16_S)
10375 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10376 daddiu $at,<sym> (BFD_RELOC_LO16)
10378 daddu $tempreg,$tempreg,$at
10380 If $at is already in use, we use a path which is suboptimal
10381 on superscalar processors.
10382 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10383 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10385 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10387 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10389 For GP relative symbols in 64bit address space we can use
10390 the same sequence as in 32bit address space. */
10391 if (HAVE_64BIT_SYMBOLS
)
10393 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10394 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10396 relax_start (offset_expr
.X_add_symbol
);
10397 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10398 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10402 if (used_at
== 0 && mips_opts
.at
)
10404 macro_build (&offset_expr
, "lui", LUI_FMT
,
10405 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10406 macro_build (&offset_expr
, "lui", LUI_FMT
,
10407 AT
, BFD_RELOC_HI16_S
);
10408 macro_build (&offset_expr
, "daddiu", "t,r,j",
10409 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10410 macro_build (&offset_expr
, "daddiu", "t,r,j",
10411 AT
, AT
, BFD_RELOC_LO16
);
10412 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10413 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10418 macro_build (&offset_expr
, "lui", LUI_FMT
,
10419 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10420 macro_build (&offset_expr
, "daddiu", "t,r,j",
10421 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10422 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10423 macro_build (&offset_expr
, "daddiu", "t,r,j",
10424 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10425 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10426 macro_build (&offset_expr
, "daddiu", "t,r,j",
10427 tempreg
, tempreg
, BFD_RELOC_LO16
);
10430 if (mips_relax
.sequence
)
10435 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10436 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10438 relax_start (offset_expr
.X_add_symbol
);
10439 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10440 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10443 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10444 as_bad (_("offset too large"));
10445 macro_build_lui (&offset_expr
, tempreg
);
10446 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10447 tempreg
, tempreg
, BFD_RELOC_LO16
);
10448 if (mips_relax
.sequence
)
10452 else if (!mips_big_got
&& !HAVE_NEWABI
)
10454 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10456 /* If this is a reference to an external symbol, and there
10457 is no constant, we want
10458 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10459 or for lca or if tempreg is PIC_CALL_REG
10460 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10461 For a local symbol, we want
10462 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10464 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10466 If we have a small constant, and this is a reference to
10467 an external symbol, we want
10468 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10470 addiu $tempreg,$tempreg,<constant>
10471 For a local symbol, we want the same instruction
10472 sequence, but we output a BFD_RELOC_LO16 reloc on the
10475 If we have a large constant, and this is a reference to
10476 an external symbol, we want
10477 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10478 lui $at,<hiconstant>
10479 addiu $at,$at,<loconstant>
10480 addu $tempreg,$tempreg,$at
10481 For a local symbol, we want the same instruction
10482 sequence, but we output a BFD_RELOC_LO16 reloc on the
10486 if (offset_expr
.X_add_number
== 0)
10488 if (mips_pic
== SVR4_PIC
10490 && (call
|| tempreg
== PIC_CALL_REG
))
10491 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10493 relax_start (offset_expr
.X_add_symbol
);
10494 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10495 lw_reloc_type
, mips_gp_register
);
10498 /* We're going to put in an addu instruction using
10499 tempreg, so we may as well insert the nop right
10504 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10505 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10507 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10508 tempreg
, tempreg
, BFD_RELOC_LO16
);
10510 /* FIXME: If breg == 0, and the next instruction uses
10511 $tempreg, then if this variant case is used an extra
10512 nop will be generated. */
10514 else if (offset_expr
.X_add_number
>= -0x8000
10515 && offset_expr
.X_add_number
< 0x8000)
10517 load_got_offset (tempreg
, &offset_expr
);
10519 add_got_offset (tempreg
, &offset_expr
);
10523 expr1
.X_add_number
= offset_expr
.X_add_number
;
10524 offset_expr
.X_add_number
=
10525 SEXT_16BIT (offset_expr
.X_add_number
);
10526 load_got_offset (tempreg
, &offset_expr
);
10527 offset_expr
.X_add_number
= expr1
.X_add_number
;
10528 /* If we are going to add in a base register, and the
10529 target register and the base register are the same,
10530 then we are using AT as a temporary register. Since
10531 we want to load the constant into AT, we add our
10532 current AT (from the global offset table) and the
10533 register into the register now, and pretend we were
10534 not using a base register. */
10538 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10543 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10547 else if (!mips_big_got
&& HAVE_NEWABI
)
10549 int add_breg_early
= 0;
10551 /* If this is a reference to an external, and there is no
10552 constant, or local symbol (*), with or without a
10554 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10555 or for lca or if tempreg is PIC_CALL_REG
10556 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10558 If we have a small constant, and this is a reference to
10559 an external symbol, we want
10560 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10561 addiu $tempreg,$tempreg,<constant>
10563 If we have a large constant, and this is a reference to
10564 an external symbol, we want
10565 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10566 lui $at,<hiconstant>
10567 addiu $at,$at,<loconstant>
10568 addu $tempreg,$tempreg,$at
10570 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10571 local symbols, even though it introduces an additional
10574 if (offset_expr
.X_add_number
)
10576 expr1
.X_add_number
= offset_expr
.X_add_number
;
10577 offset_expr
.X_add_number
= 0;
10579 relax_start (offset_expr
.X_add_symbol
);
10580 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10581 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10583 if (expr1
.X_add_number
>= -0x8000
10584 && expr1
.X_add_number
< 0x8000)
10586 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10587 tempreg
, tempreg
, BFD_RELOC_LO16
);
10589 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10593 /* If we are going to add in a base register, and the
10594 target register and the base register are the same,
10595 then we are using AT as a temporary register. Since
10596 we want to load the constant into AT, we add our
10597 current AT (from the global offset table) and the
10598 register into the register now, and pretend we were
10599 not using a base register. */
10604 gas_assert (tempreg
== AT
);
10605 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10608 add_breg_early
= 1;
10611 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10612 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10618 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10621 offset_expr
.X_add_number
= expr1
.X_add_number
;
10623 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10624 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10625 if (add_breg_early
)
10627 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10628 op
[0], tempreg
, breg
);
10634 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10636 relax_start (offset_expr
.X_add_symbol
);
10637 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10638 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10640 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10641 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10646 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10647 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10650 else if (mips_big_got
&& !HAVE_NEWABI
)
10653 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10654 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10655 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10657 /* This is the large GOT case. If this is a reference to an
10658 external symbol, and there is no constant, we want
10659 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10660 addu $tempreg,$tempreg,$gp
10661 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10662 or for lca or if tempreg is PIC_CALL_REG
10663 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10664 addu $tempreg,$tempreg,$gp
10665 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10666 For a local symbol, we want
10667 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10669 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10671 If we have a small constant, and this is a reference to
10672 an external symbol, we want
10673 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10674 addu $tempreg,$tempreg,$gp
10675 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10677 addiu $tempreg,$tempreg,<constant>
10678 For a local symbol, we want
10679 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10681 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10683 If we have a large constant, and this is a reference to
10684 an external symbol, we want
10685 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10686 addu $tempreg,$tempreg,$gp
10687 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10688 lui $at,<hiconstant>
10689 addiu $at,$at,<loconstant>
10690 addu $tempreg,$tempreg,$at
10691 For a local symbol, we want
10692 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10693 lui $at,<hiconstant>
10694 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10695 addu $tempreg,$tempreg,$at
10698 expr1
.X_add_number
= offset_expr
.X_add_number
;
10699 offset_expr
.X_add_number
= 0;
10700 relax_start (offset_expr
.X_add_symbol
);
10701 gpdelay
= reg_needs_delay (mips_gp_register
);
10702 if (expr1
.X_add_number
== 0 && breg
== 0
10703 && (call
|| tempreg
== PIC_CALL_REG
))
10705 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10706 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10708 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10709 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10710 tempreg
, tempreg
, mips_gp_register
);
10711 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10712 tempreg
, lw_reloc_type
, tempreg
);
10713 if (expr1
.X_add_number
== 0)
10717 /* We're going to put in an addu instruction using
10718 tempreg, so we may as well insert the nop right
10723 else if (expr1
.X_add_number
>= -0x8000
10724 && expr1
.X_add_number
< 0x8000)
10727 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10728 tempreg
, tempreg
, BFD_RELOC_LO16
);
10734 /* If we are going to add in a base register, and the
10735 target register and the base register are the same,
10736 then we are using AT as a temporary register. Since
10737 we want to load the constant into AT, we add our
10738 current AT (from the global offset table) and the
10739 register into the register now, and pretend we were
10740 not using a base register. */
10745 gas_assert (tempreg
== AT
);
10747 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10752 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10753 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10757 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10762 /* This is needed because this instruction uses $gp, but
10763 the first instruction on the main stream does not. */
10764 macro_build (NULL
, "nop", "");
10767 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10768 local_reloc_type
, mips_gp_register
);
10769 if (expr1
.X_add_number
>= -0x8000
10770 && expr1
.X_add_number
< 0x8000)
10773 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10774 tempreg
, tempreg
, BFD_RELOC_LO16
);
10775 /* FIXME: If add_number is 0, and there was no base
10776 register, the external symbol case ended with a load,
10777 so if the symbol turns out to not be external, and
10778 the next instruction uses tempreg, an unnecessary nop
10779 will be inserted. */
10785 /* We must add in the base register now, as in the
10786 external symbol case. */
10787 gas_assert (tempreg
== AT
);
10789 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10792 /* We set breg to 0 because we have arranged to add
10793 it in in both cases. */
10797 macro_build_lui (&expr1
, AT
);
10798 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10799 AT
, AT
, BFD_RELOC_LO16
);
10800 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10801 tempreg
, tempreg
, AT
);
10806 else if (mips_big_got
&& HAVE_NEWABI
)
10808 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10809 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10810 int add_breg_early
= 0;
10812 /* This is the large GOT case. If this is a reference to an
10813 external symbol, and there is no constant, we want
10814 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10815 add $tempreg,$tempreg,$gp
10816 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10817 or for lca or if tempreg is PIC_CALL_REG
10818 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10819 add $tempreg,$tempreg,$gp
10820 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10822 If we have a small constant, and this is a reference to
10823 an external symbol, we want
10824 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10825 add $tempreg,$tempreg,$gp
10826 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10827 addi $tempreg,$tempreg,<constant>
10829 If we have a large constant, and this is a reference to
10830 an external symbol, we want
10831 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10832 addu $tempreg,$tempreg,$gp
10833 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10834 lui $at,<hiconstant>
10835 addi $at,$at,<loconstant>
10836 add $tempreg,$tempreg,$at
10838 If we have NewABI, and we know it's a local symbol, we want
10839 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10840 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10841 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10843 relax_start (offset_expr
.X_add_symbol
);
10845 expr1
.X_add_number
= offset_expr
.X_add_number
;
10846 offset_expr
.X_add_number
= 0;
10848 if (expr1
.X_add_number
== 0 && breg
== 0
10849 && (call
|| tempreg
== PIC_CALL_REG
))
10851 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10852 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10854 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10855 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10856 tempreg
, tempreg
, mips_gp_register
);
10857 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10858 tempreg
, lw_reloc_type
, tempreg
);
10860 if (expr1
.X_add_number
== 0)
10862 else if (expr1
.X_add_number
>= -0x8000
10863 && expr1
.X_add_number
< 0x8000)
10865 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10866 tempreg
, tempreg
, BFD_RELOC_LO16
);
10868 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10872 /* If we are going to add in a base register, and the
10873 target register and the base register are the same,
10874 then we are using AT as a temporary register. Since
10875 we want to load the constant into AT, we add our
10876 current AT (from the global offset table) and the
10877 register into the register now, and pretend we were
10878 not using a base register. */
10883 gas_assert (tempreg
== AT
);
10884 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10887 add_breg_early
= 1;
10890 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10891 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10896 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10899 offset_expr
.X_add_number
= expr1
.X_add_number
;
10900 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10901 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10902 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10903 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10904 if (add_breg_early
)
10906 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10907 op
[0], tempreg
, breg
);
10917 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10921 gas_assert (!mips_opts
.micromips
);
10922 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10926 gas_assert (!mips_opts
.micromips
);
10927 macro_build (NULL
, "c2", "C", 0x02);
10931 gas_assert (!mips_opts
.micromips
);
10932 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10936 gas_assert (!mips_opts
.micromips
);
10937 macro_build (NULL
, "c2", "C", 3);
10941 gas_assert (!mips_opts
.micromips
);
10942 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10946 /* The j instruction may not be used in PIC code, since it
10947 requires an absolute address. We convert it to a b
10949 if (mips_pic
== NO_PIC
)
10950 macro_build (&offset_expr
, "j", "a");
10952 macro_build (&offset_expr
, "b", "p");
10955 /* The jal instructions must be handled as macros because when
10956 generating PIC code they expand to multi-instruction
10957 sequences. Normally they are simple instructions. */
10961 /* Fall through. */
10963 gas_assert (mips_opts
.micromips
);
10964 if (mips_opts
.insn32
)
10966 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10974 /* Fall through. */
10977 if (mips_pic
== NO_PIC
)
10979 s
= jals
? "jalrs" : "jalr";
10980 if (mips_opts
.micromips
10981 && !mips_opts
.insn32
10983 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10984 macro_build (NULL
, s
, "mj", op
[1]);
10986 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10990 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10991 && mips_cprestore_offset
>= 0);
10993 if (op
[1] != PIC_CALL_REG
)
10994 as_warn (_("MIPS PIC call to register other than $25"));
10996 s
= ((mips_opts
.micromips
10997 && !mips_opts
.insn32
10998 && (!mips_opts
.noreorder
|| cprestore
))
10999 ? "jalrs" : "jalr");
11000 if (mips_opts
.micromips
11001 && !mips_opts
.insn32
11003 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11004 macro_build (NULL
, s
, "mj", op
[1]);
11006 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11007 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11009 if (mips_cprestore_offset
< 0)
11010 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11013 if (!mips_frame_reg_valid
)
11015 as_warn (_("no .frame pseudo-op used in PIC code"));
11016 /* Quiet this warning. */
11017 mips_frame_reg_valid
= 1;
11019 if (!mips_cprestore_valid
)
11021 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11022 /* Quiet this warning. */
11023 mips_cprestore_valid
= 1;
11025 if (mips_opts
.noreorder
)
11026 macro_build (NULL
, "nop", "");
11027 expr1
.X_add_number
= mips_cprestore_offset
;
11028 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11031 HAVE_64BIT_ADDRESSES
);
11039 gas_assert (mips_opts
.micromips
);
11040 if (mips_opts
.insn32
)
11042 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11046 /* Fall through. */
11048 if (mips_pic
== NO_PIC
)
11049 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11050 else if (mips_pic
== SVR4_PIC
)
11052 /* If this is a reference to an external symbol, and we are
11053 using a small GOT, we want
11054 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11058 lw $gp,cprestore($sp)
11059 The cprestore value is set using the .cprestore
11060 pseudo-op. If we are using a big GOT, we want
11061 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11063 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11067 lw $gp,cprestore($sp)
11068 If the symbol is not external, we want
11069 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11071 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11074 lw $gp,cprestore($sp)
11076 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11077 sequences above, minus nops, unless the symbol is local,
11078 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11084 relax_start (offset_expr
.X_add_symbol
);
11085 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11086 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11089 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11090 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11096 relax_start (offset_expr
.X_add_symbol
);
11097 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11098 BFD_RELOC_MIPS_CALL_HI16
);
11099 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11100 PIC_CALL_REG
, mips_gp_register
);
11101 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11102 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11105 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11106 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11108 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11109 PIC_CALL_REG
, PIC_CALL_REG
,
11110 BFD_RELOC_MIPS_GOT_OFST
);
11114 macro_build_jalr (&offset_expr
, 0);
11118 relax_start (offset_expr
.X_add_symbol
);
11121 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11122 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11131 gpdelay
= reg_needs_delay (mips_gp_register
);
11132 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11133 BFD_RELOC_MIPS_CALL_HI16
);
11134 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11135 PIC_CALL_REG
, mips_gp_register
);
11136 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11137 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11142 macro_build (NULL
, "nop", "");
11144 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11145 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11148 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11149 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11151 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11153 if (mips_cprestore_offset
< 0)
11154 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11157 if (!mips_frame_reg_valid
)
11159 as_warn (_("no .frame pseudo-op used in PIC code"));
11160 /* Quiet this warning. */
11161 mips_frame_reg_valid
= 1;
11163 if (!mips_cprestore_valid
)
11165 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11166 /* Quiet this warning. */
11167 mips_cprestore_valid
= 1;
11169 if (mips_opts
.noreorder
)
11170 macro_build (NULL
, "nop", "");
11171 expr1
.X_add_number
= mips_cprestore_offset
;
11172 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11175 HAVE_64BIT_ADDRESSES
);
11179 else if (mips_pic
== VXWORKS_PIC
)
11180 as_bad (_("non-PIC jump used in PIC library"));
11287 gas_assert (!mips_opts
.micromips
);
11290 /* Itbl support may require additional care here. */
11296 /* Itbl support may require additional care here. */
11302 offbits
= (mips_opts
.micromips
? 12
11303 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11305 /* Itbl support may require additional care here. */
11309 gas_assert (!mips_opts
.micromips
);
11312 /* Itbl support may require additional care here. */
11318 offbits
= (mips_opts
.micromips
? 12 : 16);
11323 offbits
= (mips_opts
.micromips
? 12 : 16);
11328 /* Itbl support may require additional care here. */
11334 offbits
= (mips_opts
.micromips
? 12
11335 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11337 /* Itbl support may require additional care here. */
11343 /* Itbl support may require additional care here. */
11349 /* Itbl support may require additional care here. */
11355 offbits
= (mips_opts
.micromips
? 12 : 16);
11360 offbits
= (mips_opts
.micromips
? 12 : 16);
11365 offbits
= (mips_opts
.micromips
? 12
11366 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11372 offbits
= (mips_opts
.micromips
? 12
11373 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11379 offbits
= (mips_opts
.micromips
? 12 : 16);
11382 gas_assert (mips_opts
.micromips
);
11389 gas_assert (mips_opts
.micromips
);
11396 gas_assert (mips_opts
.micromips
);
11402 gas_assert (mips_opts
.micromips
);
11409 /* We don't want to use $0 as tempreg. */
11410 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11413 tempreg
= op
[0] + lp
;
11429 gas_assert (!mips_opts
.micromips
);
11432 /* Itbl support may require additional care here. */
11438 /* Itbl support may require additional care here. */
11444 offbits
= (mips_opts
.micromips
? 12
11445 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11447 /* Itbl support may require additional care here. */
11451 gas_assert (!mips_opts
.micromips
);
11454 /* Itbl support may require additional care here. */
11460 offbits
= (mips_opts
.micromips
? 12 : 16);
11465 offbits
= (mips_opts
.micromips
? 12 : 16);
11470 offbits
= (mips_opts
.micromips
? 12
11471 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11477 offbits
= (mips_opts
.micromips
? 12
11478 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11483 fmt
= (mips_opts
.micromips
? "k,~(b)"
11484 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11486 offbits
= (mips_opts
.micromips
? 12
11487 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11497 fmt
= (mips_opts
.micromips
? "k,~(b)"
11498 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11500 offbits
= (mips_opts
.micromips
? 12
11501 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11513 /* Itbl support may require additional care here. */
11518 offbits
= (mips_opts
.micromips
? 12
11519 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11521 /* Itbl support may require additional care here. */
11527 /* Itbl support may require additional care here. */
11531 gas_assert (!mips_opts
.micromips
);
11534 /* Itbl support may require additional care here. */
11540 offbits
= (mips_opts
.micromips
? 12 : 16);
11545 offbits
= (mips_opts
.micromips
? 12 : 16);
11548 gas_assert (mips_opts
.micromips
);
11554 gas_assert (mips_opts
.micromips
);
11560 gas_assert (mips_opts
.micromips
);
11566 gas_assert (mips_opts
.micromips
);
11575 if (small_offset_p (0, align
, 16))
11577 /* The first case exists for M_LD_AB and M_SD_AB, which are
11578 macros for o32 but which should act like normal instructions
11581 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11582 offset_reloc
[1], offset_reloc
[2], breg
);
11583 else if (small_offset_p (0, align
, offbits
))
11586 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11588 macro_build (NULL
, s
, fmt
, op
[0],
11589 (int) offset_expr
.X_add_number
, breg
);
11595 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11596 tempreg
, breg
, -1, offset_reloc
[0],
11597 offset_reloc
[1], offset_reloc
[2]);
11599 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11601 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11609 if (offset_expr
.X_op
!= O_constant
11610 && offset_expr
.X_op
!= O_symbol
)
11612 as_bad (_("expression too complex"));
11613 offset_expr
.X_op
= O_constant
;
11616 if (HAVE_32BIT_ADDRESSES
11617 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11621 sprintf_vma (value
, offset_expr
.X_add_number
);
11622 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11625 /* A constant expression in PIC code can be handled just as it
11626 is in non PIC code. */
11627 if (offset_expr
.X_op
== O_constant
)
11629 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11630 offbits
== 0 ? 16 : offbits
);
11631 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11633 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11635 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11636 tempreg
, tempreg
, breg
);
11639 if (offset_expr
.X_add_number
!= 0)
11640 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11641 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11642 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11644 else if (offbits
== 16)
11645 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11647 macro_build (NULL
, s
, fmt
, op
[0],
11648 (int) offset_expr
.X_add_number
, tempreg
);
11650 else if (offbits
!= 16)
11652 /* The offset field is too narrow to be used for a low-part
11653 relocation, so load the whole address into the auxillary
11655 load_address (tempreg
, &offset_expr
, &used_at
);
11657 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11658 tempreg
, tempreg
, breg
);
11660 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11662 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11664 else if (mips_pic
== NO_PIC
)
11666 /* If this is a reference to a GP relative symbol, and there
11667 is no base register, we want
11668 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11669 Otherwise, if there is no base register, we want
11670 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11671 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11672 If we have a constant, we need two instructions anyhow,
11673 so we always use the latter form.
11675 If we have a base register, and this is a reference to a
11676 GP relative symbol, we want
11677 addu $tempreg,$breg,$gp
11678 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11680 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11681 addu $tempreg,$tempreg,$breg
11682 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11683 With a constant we always use the latter case.
11685 With 64bit address space and no base register and $at usable,
11687 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11688 lui $at,<sym> (BFD_RELOC_HI16_S)
11689 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11692 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11693 If we have a base register, we want
11694 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11695 lui $at,<sym> (BFD_RELOC_HI16_S)
11696 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11700 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11702 Without $at we can't generate the optimal path for superscalar
11703 processors here since this would require two temporary registers.
11704 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11705 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11707 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11709 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11710 If we have a base register, we want
11711 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11712 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11714 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11716 daddu $tempreg,$tempreg,$breg
11717 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11719 For GP relative symbols in 64bit address space we can use
11720 the same sequence as in 32bit address space. */
11721 if (HAVE_64BIT_SYMBOLS
)
11723 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11724 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11726 relax_start (offset_expr
.X_add_symbol
);
11729 macro_build (&offset_expr
, s
, fmt
, op
[0],
11730 BFD_RELOC_GPREL16
, mips_gp_register
);
11734 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11735 tempreg
, breg
, mips_gp_register
);
11736 macro_build (&offset_expr
, s
, fmt
, op
[0],
11737 BFD_RELOC_GPREL16
, tempreg
);
11742 if (used_at
== 0 && mips_opts
.at
)
11744 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11745 BFD_RELOC_MIPS_HIGHEST
);
11746 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11748 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11749 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11751 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11752 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11753 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11754 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11760 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11761 BFD_RELOC_MIPS_HIGHEST
);
11762 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11763 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11764 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11765 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11766 tempreg
, BFD_RELOC_HI16_S
);
11767 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11769 macro_build (NULL
, "daddu", "d,v,t",
11770 tempreg
, tempreg
, breg
);
11771 macro_build (&offset_expr
, s
, fmt
, op
[0],
11772 BFD_RELOC_LO16
, tempreg
);
11775 if (mips_relax
.sequence
)
11782 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11783 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11785 relax_start (offset_expr
.X_add_symbol
);
11786 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11790 macro_build_lui (&offset_expr
, tempreg
);
11791 macro_build (&offset_expr
, s
, fmt
, op
[0],
11792 BFD_RELOC_LO16
, tempreg
);
11793 if (mips_relax
.sequence
)
11798 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11799 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11801 relax_start (offset_expr
.X_add_symbol
);
11802 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11803 tempreg
, breg
, mips_gp_register
);
11804 macro_build (&offset_expr
, s
, fmt
, op
[0],
11805 BFD_RELOC_GPREL16
, tempreg
);
11808 macro_build_lui (&offset_expr
, tempreg
);
11809 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11810 tempreg
, tempreg
, breg
);
11811 macro_build (&offset_expr
, s
, fmt
, op
[0],
11812 BFD_RELOC_LO16
, tempreg
);
11813 if (mips_relax
.sequence
)
11817 else if (!mips_big_got
)
11819 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11821 /* If this is a reference to an external symbol, we want
11822 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11824 <op> op[0],0($tempreg)
11826 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11828 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11829 <op> op[0],0($tempreg)
11831 For NewABI, we want
11832 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11833 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11835 If there is a base register, we add it to $tempreg before
11836 the <op>. If there is a constant, we stick it in the
11837 <op> instruction. We don't handle constants larger than
11838 16 bits, because we have no way to load the upper 16 bits
11839 (actually, we could handle them for the subset of cases
11840 in which we are not using $at). */
11841 gas_assert (offset_expr
.X_op
== O_symbol
);
11844 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11845 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11847 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11848 tempreg
, tempreg
, breg
);
11849 macro_build (&offset_expr
, s
, fmt
, op
[0],
11850 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11853 expr1
.X_add_number
= offset_expr
.X_add_number
;
11854 offset_expr
.X_add_number
= 0;
11855 if (expr1
.X_add_number
< -0x8000
11856 || expr1
.X_add_number
>= 0x8000)
11857 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11858 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11859 lw_reloc_type
, mips_gp_register
);
11861 relax_start (offset_expr
.X_add_symbol
);
11863 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11864 tempreg
, BFD_RELOC_LO16
);
11867 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11868 tempreg
, tempreg
, breg
);
11869 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11871 else if (mips_big_got
&& !HAVE_NEWABI
)
11875 /* If this is a reference to an external symbol, we want
11876 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11877 addu $tempreg,$tempreg,$gp
11878 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11879 <op> op[0],0($tempreg)
11881 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11883 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11884 <op> op[0],0($tempreg)
11885 If there is a base register, we add it to $tempreg before
11886 the <op>. If there is a constant, we stick it in the
11887 <op> instruction. We don't handle constants larger than
11888 16 bits, because we have no way to load the upper 16 bits
11889 (actually, we could handle them for the subset of cases
11890 in which we are not using $at). */
11891 gas_assert (offset_expr
.X_op
== O_symbol
);
11892 expr1
.X_add_number
= offset_expr
.X_add_number
;
11893 offset_expr
.X_add_number
= 0;
11894 if (expr1
.X_add_number
< -0x8000
11895 || expr1
.X_add_number
>= 0x8000)
11896 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11897 gpdelay
= reg_needs_delay (mips_gp_register
);
11898 relax_start (offset_expr
.X_add_symbol
);
11899 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11900 BFD_RELOC_MIPS_GOT_HI16
);
11901 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11903 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11904 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11907 macro_build (NULL
, "nop", "");
11908 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11909 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11911 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11912 tempreg
, BFD_RELOC_LO16
);
11916 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11917 tempreg
, tempreg
, breg
);
11918 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11920 else if (mips_big_got
&& HAVE_NEWABI
)
11922 /* If this is a reference to an external symbol, we want
11923 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11924 add $tempreg,$tempreg,$gp
11925 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11926 <op> op[0],<ofst>($tempreg)
11927 Otherwise, for local symbols, we want:
11928 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11929 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11930 gas_assert (offset_expr
.X_op
== O_symbol
);
11931 expr1
.X_add_number
= offset_expr
.X_add_number
;
11932 offset_expr
.X_add_number
= 0;
11933 if (expr1
.X_add_number
< -0x8000
11934 || expr1
.X_add_number
>= 0x8000)
11935 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11936 relax_start (offset_expr
.X_add_symbol
);
11937 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11938 BFD_RELOC_MIPS_GOT_HI16
);
11939 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11941 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11942 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11944 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11945 tempreg
, tempreg
, breg
);
11946 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11949 offset_expr
.X_add_number
= expr1
.X_add_number
;
11950 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11951 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11953 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11954 tempreg
, tempreg
, breg
);
11955 macro_build (&offset_expr
, s
, fmt
, op
[0],
11956 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11965 gas_assert (mips_opts
.micromips
);
11966 gas_assert (mips_opts
.insn32
);
11967 start_noreorder ();
11968 macro_build (NULL
, "jr", "s", RA
);
11969 expr1
.X_add_number
= op
[0] << 2;
11970 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11975 gas_assert (mips_opts
.micromips
);
11976 gas_assert (mips_opts
.insn32
);
11977 macro_build (NULL
, "jr", "s", op
[0]);
11978 if (mips_opts
.noreorder
)
11979 macro_build (NULL
, "nop", "");
11984 load_register (op
[0], &imm_expr
, 0);
11988 load_register (op
[0], &imm_expr
, 1);
11992 if (imm_expr
.X_op
== O_constant
)
11995 load_register (AT
, &imm_expr
, 0);
11996 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12001 gas_assert (imm_expr
.X_op
== O_absent
12002 && offset_expr
.X_op
== O_symbol
12003 && strcmp (segment_name (S_GET_SEGMENT
12004 (offset_expr
.X_add_symbol
)),
12006 && offset_expr
.X_add_number
== 0);
12007 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12008 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12013 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12014 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12015 order 32 bits of the value and the low order 32 bits are either
12016 zero or in OFFSET_EXPR. */
12017 if (imm_expr
.X_op
== O_constant
)
12019 if (GPR_SIZE
== 64)
12020 load_register (op
[0], &imm_expr
, 1);
12025 if (target_big_endian
)
12037 load_register (hreg
, &imm_expr
, 0);
12040 if (offset_expr
.X_op
== O_absent
)
12041 move_register (lreg
, 0);
12044 gas_assert (offset_expr
.X_op
== O_constant
);
12045 load_register (lreg
, &offset_expr
, 0);
12051 gas_assert (imm_expr
.X_op
== O_absent
);
12053 /* We know that sym is in the .rdata section. First we get the
12054 upper 16 bits of the address. */
12055 if (mips_pic
== NO_PIC
)
12057 macro_build_lui (&offset_expr
, AT
);
12062 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12063 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12067 /* Now we load the register(s). */
12068 if (GPR_SIZE
== 64)
12071 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12072 BFD_RELOC_LO16
, AT
);
12077 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12078 BFD_RELOC_LO16
, AT
);
12081 /* FIXME: How in the world do we deal with the possible
12083 offset_expr
.X_add_number
+= 4;
12084 macro_build (&offset_expr
, "lw", "t,o(b)",
12085 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12091 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12092 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12093 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12094 the value and the low order 32 bits are either zero or in
12096 if (imm_expr
.X_op
== O_constant
)
12099 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12100 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12101 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12104 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12105 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12106 else if (FPR_SIZE
!= 32)
12107 as_bad (_("Unable to generate `%s' compliant code "
12109 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12111 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12112 if (offset_expr
.X_op
== O_absent
)
12113 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12116 gas_assert (offset_expr
.X_op
== O_constant
);
12117 load_register (AT
, &offset_expr
, 0);
12118 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12124 gas_assert (imm_expr
.X_op
== O_absent
12125 && offset_expr
.X_op
== O_symbol
12126 && offset_expr
.X_add_number
== 0);
12127 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12128 if (strcmp (s
, ".lit8") == 0)
12130 op
[2] = mips_gp_register
;
12131 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12132 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12133 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12137 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12139 if (mips_pic
!= NO_PIC
)
12140 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12141 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12144 /* FIXME: This won't work for a 64 bit address. */
12145 macro_build_lui (&offset_expr
, AT
);
12149 offset_reloc
[0] = BFD_RELOC_LO16
;
12150 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12151 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12158 * The MIPS assembler seems to check for X_add_number not
12159 * being double aligned and generating:
12160 * lui at,%hi(foo+1)
12162 * addiu at,at,%lo(foo+1)
12165 * But, the resulting address is the same after relocation so why
12166 * generate the extra instruction?
12168 /* Itbl support may require additional care here. */
12171 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12180 gas_assert (!mips_opts
.micromips
);
12181 /* Itbl support may require additional care here. */
12184 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12204 if (GPR_SIZE
== 64)
12214 if (GPR_SIZE
== 64)
12222 /* Even on a big endian machine $fn comes before $fn+1. We have
12223 to adjust when loading from memory. We set coproc if we must
12224 load $fn+1 first. */
12225 /* Itbl support may require additional care here. */
12226 if (!target_big_endian
)
12230 if (small_offset_p (0, align
, 16))
12233 if (!small_offset_p (4, align
, 16))
12235 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12236 -1, offset_reloc
[0], offset_reloc
[1],
12238 expr1
.X_add_number
= 0;
12242 offset_reloc
[0] = BFD_RELOC_LO16
;
12243 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12244 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12246 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12248 ep
->X_add_number
+= 4;
12249 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12250 offset_reloc
[1], offset_reloc
[2], breg
);
12251 ep
->X_add_number
-= 4;
12252 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12253 offset_reloc
[1], offset_reloc
[2], breg
);
12257 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12258 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12260 ep
->X_add_number
+= 4;
12261 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12262 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12268 if (offset_expr
.X_op
!= O_symbol
12269 && offset_expr
.X_op
!= O_constant
)
12271 as_bad (_("expression too complex"));
12272 offset_expr
.X_op
= O_constant
;
12275 if (HAVE_32BIT_ADDRESSES
12276 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12280 sprintf_vma (value
, offset_expr
.X_add_number
);
12281 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12284 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12286 /* If this is a reference to a GP relative symbol, we want
12287 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12288 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12289 If we have a base register, we use this
12291 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12292 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12293 If this is not a GP relative symbol, we want
12294 lui $at,<sym> (BFD_RELOC_HI16_S)
12295 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12296 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12297 If there is a base register, we add it to $at after the
12298 lui instruction. If there is a constant, we always use
12300 if (offset_expr
.X_op
== O_symbol
12301 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12302 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12304 relax_start (offset_expr
.X_add_symbol
);
12307 tempreg
= mips_gp_register
;
12311 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12312 AT
, breg
, mips_gp_register
);
12317 /* Itbl support may require additional care here. */
12318 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12319 BFD_RELOC_GPREL16
, tempreg
);
12320 offset_expr
.X_add_number
+= 4;
12322 /* Set mips_optimize to 2 to avoid inserting an
12324 hold_mips_optimize
= mips_optimize
;
12326 /* Itbl support may require additional care here. */
12327 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12328 BFD_RELOC_GPREL16
, tempreg
);
12329 mips_optimize
= hold_mips_optimize
;
12333 offset_expr
.X_add_number
-= 4;
12336 if (offset_high_part (offset_expr
.X_add_number
, 16)
12337 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12339 load_address (AT
, &offset_expr
, &used_at
);
12340 offset_expr
.X_op
= O_constant
;
12341 offset_expr
.X_add_number
= 0;
12344 macro_build_lui (&offset_expr
, AT
);
12346 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12347 /* Itbl support may require additional care here. */
12348 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12349 BFD_RELOC_LO16
, AT
);
12350 /* FIXME: How do we handle overflow here? */
12351 offset_expr
.X_add_number
+= 4;
12352 /* Itbl support may require additional care here. */
12353 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12354 BFD_RELOC_LO16
, AT
);
12355 if (mips_relax
.sequence
)
12358 else if (!mips_big_got
)
12360 /* If this is a reference to an external symbol, we want
12361 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12364 <op> op[0]+1,4($at)
12366 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12368 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12369 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12370 If there is a base register we add it to $at before the
12371 lwc1 instructions. If there is a constant we include it
12372 in the lwc1 instructions. */
12374 expr1
.X_add_number
= offset_expr
.X_add_number
;
12375 if (expr1
.X_add_number
< -0x8000
12376 || expr1
.X_add_number
>= 0x8000 - 4)
12377 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12378 load_got_offset (AT
, &offset_expr
);
12381 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12383 /* Set mips_optimize to 2 to avoid inserting an undesired
12385 hold_mips_optimize
= mips_optimize
;
12388 /* Itbl support may require additional care here. */
12389 relax_start (offset_expr
.X_add_symbol
);
12390 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12391 BFD_RELOC_LO16
, AT
);
12392 expr1
.X_add_number
+= 4;
12393 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12394 BFD_RELOC_LO16
, AT
);
12396 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12397 BFD_RELOC_LO16
, AT
);
12398 offset_expr
.X_add_number
+= 4;
12399 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12400 BFD_RELOC_LO16
, AT
);
12403 mips_optimize
= hold_mips_optimize
;
12405 else if (mips_big_got
)
12409 /* If this is a reference to an external symbol, we want
12410 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12412 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12415 <op> op[0]+1,4($at)
12417 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12419 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12420 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12421 If there is a base register we add it to $at before the
12422 lwc1 instructions. If there is a constant we include it
12423 in the lwc1 instructions. */
12425 expr1
.X_add_number
= offset_expr
.X_add_number
;
12426 offset_expr
.X_add_number
= 0;
12427 if (expr1
.X_add_number
< -0x8000
12428 || expr1
.X_add_number
>= 0x8000 - 4)
12429 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12430 gpdelay
= reg_needs_delay (mips_gp_register
);
12431 relax_start (offset_expr
.X_add_symbol
);
12432 macro_build (&offset_expr
, "lui", LUI_FMT
,
12433 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12435 AT
, AT
, mips_gp_register
);
12436 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12437 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12440 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12441 /* Itbl support may require additional care here. */
12442 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12443 BFD_RELOC_LO16
, AT
);
12444 expr1
.X_add_number
+= 4;
12446 /* Set mips_optimize to 2 to avoid inserting an undesired
12448 hold_mips_optimize
= mips_optimize
;
12450 /* Itbl support may require additional care here. */
12451 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12452 BFD_RELOC_LO16
, AT
);
12453 mips_optimize
= hold_mips_optimize
;
12454 expr1
.X_add_number
-= 4;
12457 offset_expr
.X_add_number
= expr1
.X_add_number
;
12459 macro_build (NULL
, "nop", "");
12460 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12461 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12464 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12465 /* Itbl support may require additional care here. */
12466 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12467 BFD_RELOC_LO16
, AT
);
12468 offset_expr
.X_add_number
+= 4;
12470 /* Set mips_optimize to 2 to avoid inserting an undesired
12472 hold_mips_optimize
= mips_optimize
;
12474 /* Itbl support may require additional care here. */
12475 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12476 BFD_RELOC_LO16
, AT
);
12477 mips_optimize
= hold_mips_optimize
;
12491 gas_assert (!mips_opts
.micromips
);
12496 /* New code added to support COPZ instructions.
12497 This code builds table entries out of the macros in mip_opcodes.
12498 R4000 uses interlocks to handle coproc delays.
12499 Other chips (like the R3000) require nops to be inserted for delays.
12501 FIXME: Currently, we require that the user handle delays.
12502 In order to fill delay slots for non-interlocked chips,
12503 we must have a way to specify delays based on the coprocessor.
12504 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12505 What are the side-effects of the cop instruction?
12506 What cache support might we have and what are its effects?
12507 Both coprocessor & memory require delays. how long???
12508 What registers are read/set/modified?
12510 If an itbl is provided to interpret cop instructions,
12511 this knowledge can be encoded in the itbl spec. */
12525 gas_assert (!mips_opts
.micromips
);
12526 /* For now we just do C (same as Cz). The parameter will be
12527 stored in insn_opcode by mips_ip. */
12528 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12532 move_register (op
[0], op
[1]);
12536 gas_assert (mips_opts
.micromips
);
12537 gas_assert (mips_opts
.insn32
);
12538 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12539 micromips_to_32_reg_m_map
[op
[1]]);
12540 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12541 micromips_to_32_reg_n_map
[op
[2]]);
12547 if (mips_opts
.arch
== CPU_R5900
)
12548 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12552 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12553 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12560 /* The MIPS assembler some times generates shifts and adds. I'm
12561 not trying to be that fancy. GCC should do this for us
12564 load_register (AT
, &imm_expr
, dbl
);
12565 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12566 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12579 start_noreorder ();
12582 load_register (AT
, &imm_expr
, dbl
);
12583 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12584 op
[1], imm
? AT
: op
[2]);
12585 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12586 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12587 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12589 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12592 if (mips_opts
.micromips
)
12593 micromips_label_expr (&label_expr
);
12595 label_expr
.X_add_number
= 8;
12596 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12597 macro_build (NULL
, "nop", "");
12598 macro_build (NULL
, "break", BRK_FMT
, 6);
12599 if (mips_opts
.micromips
)
12600 micromips_add_label ();
12603 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12616 start_noreorder ();
12619 load_register (AT
, &imm_expr
, dbl
);
12620 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12621 op
[1], imm
? AT
: op
[2]);
12622 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12623 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12625 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12628 if (mips_opts
.micromips
)
12629 micromips_label_expr (&label_expr
);
12631 label_expr
.X_add_number
= 8;
12632 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12633 macro_build (NULL
, "nop", "");
12634 macro_build (NULL
, "break", BRK_FMT
, 6);
12635 if (mips_opts
.micromips
)
12636 micromips_add_label ();
12642 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12644 if (op
[0] == op
[1])
12651 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12652 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12656 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12657 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12658 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12659 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12663 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12665 if (op
[0] == op
[1])
12672 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12673 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12677 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12678 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12679 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12680 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12689 rot
= imm_expr
.X_add_number
& 0x3f;
12690 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12692 rot
= (64 - rot
) & 0x3f;
12694 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12696 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12701 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12704 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12705 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12708 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12709 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12710 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12718 rot
= imm_expr
.X_add_number
& 0x1f;
12719 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12721 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12722 (32 - rot
) & 0x1f);
12727 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12731 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12732 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12733 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12738 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12740 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12744 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12745 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12746 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12747 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12751 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12753 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12757 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12758 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12759 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12760 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12769 rot
= imm_expr
.X_add_number
& 0x3f;
12770 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12773 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12775 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12780 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12783 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12784 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12787 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12788 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12789 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12797 rot
= imm_expr
.X_add_number
& 0x1f;
12798 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12800 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12805 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12809 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12810 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12811 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12817 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12818 else if (op
[2] == 0)
12819 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12822 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12823 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12828 if (imm_expr
.X_add_number
== 0)
12830 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12835 as_warn (_("instruction %s: result is always false"),
12836 ip
->insn_mo
->name
);
12837 move_register (op
[0], 0);
12840 if (CPU_HAS_SEQ (mips_opts
.arch
)
12841 && -512 <= imm_expr
.X_add_number
12842 && imm_expr
.X_add_number
< 512)
12844 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12845 (int) imm_expr
.X_add_number
);
12848 if (imm_expr
.X_add_number
>= 0
12849 && imm_expr
.X_add_number
< 0x10000)
12850 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12851 else if (imm_expr
.X_add_number
> -0x8000
12852 && imm_expr
.X_add_number
< 0)
12854 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12855 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
12856 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12858 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12861 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12862 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12867 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12868 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12871 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12874 case M_SGE
: /* X >= Y <==> not (X < Y) */
12880 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12881 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12884 case M_SGE_I
: /* X >= I <==> not (X < I) */
12886 if (imm_expr
.X_add_number
>= -0x8000
12887 && imm_expr
.X_add_number
< 0x8000)
12888 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12889 op
[0], op
[1], BFD_RELOC_LO16
);
12892 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12893 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12897 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12900 case M_SGT
: /* X > Y <==> Y < X */
12906 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12909 case M_SGT_I
: /* X > I <==> I < X */
12916 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12917 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12920 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12926 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12927 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12930 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12937 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12938 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12939 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12943 if (imm_expr
.X_add_number
>= -0x8000
12944 && imm_expr
.X_add_number
< 0x8000)
12946 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12951 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12952 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12956 if (imm_expr
.X_add_number
>= -0x8000
12957 && imm_expr
.X_add_number
< 0x8000)
12959 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12964 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
12965 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12970 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12971 else if (op
[2] == 0)
12972 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12975 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12976 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12981 if (imm_expr
.X_add_number
== 0)
12983 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12988 as_warn (_("instruction %s: result is always true"),
12989 ip
->insn_mo
->name
);
12990 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
12991 op
[0], 0, BFD_RELOC_LO16
);
12994 if (CPU_HAS_SEQ (mips_opts
.arch
)
12995 && -512 <= imm_expr
.X_add_number
12996 && imm_expr
.X_add_number
< 512)
12998 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
12999 (int) imm_expr
.X_add_number
);
13002 if (imm_expr
.X_add_number
>= 0
13003 && imm_expr
.X_add_number
< 0x10000)
13005 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13008 else if (imm_expr
.X_add_number
> -0x8000
13009 && imm_expr
.X_add_number
< 0)
13011 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13012 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13013 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13015 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13018 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13019 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13024 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13025 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13028 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13043 if (!mips_opts
.micromips
)
13045 if (imm_expr
.X_add_number
> -0x200
13046 && imm_expr
.X_add_number
<= 0x200)
13048 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13049 (int) -imm_expr
.X_add_number
);
13058 if (imm_expr
.X_add_number
> -0x8000
13059 && imm_expr
.X_add_number
<= 0x8000)
13061 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13062 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13067 load_register (AT
, &imm_expr
, dbl
);
13068 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13090 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13091 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13096 gas_assert (!mips_opts
.micromips
);
13097 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13101 * Is the double cfc1 instruction a bug in the mips assembler;
13102 * or is there a reason for it?
13104 start_noreorder ();
13105 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13106 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13107 macro_build (NULL
, "nop", "");
13108 expr1
.X_add_number
= 3;
13109 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13110 expr1
.X_add_number
= 2;
13111 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13112 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13113 macro_build (NULL
, "nop", "");
13114 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13116 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13117 macro_build (NULL
, "nop", "");
13134 offbits
= (mips_opts
.micromips
? 12 : 16);
13140 offbits
= (mips_opts
.micromips
? 12 : 16);
13152 offbits
= (mips_opts
.micromips
? 12 : 16);
13159 offbits
= (mips_opts
.micromips
? 12 : 16);
13165 large_offset
= !small_offset_p (off
, align
, offbits
);
13167 expr1
.X_add_number
= 0;
13172 if (small_offset_p (0, align
, 16))
13173 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13174 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13177 load_address (tempreg
, ep
, &used_at
);
13179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13180 tempreg
, tempreg
, breg
);
13182 offset_reloc
[0] = BFD_RELOC_LO16
;
13183 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13184 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13189 else if (!ust
&& op
[0] == breg
)
13200 if (!target_big_endian
)
13201 ep
->X_add_number
+= off
;
13203 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13205 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13206 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13208 if (!target_big_endian
)
13209 ep
->X_add_number
-= off
;
13211 ep
->X_add_number
+= off
;
13213 macro_build (NULL
, s2
, "t,~(b)",
13214 tempreg
, (int) ep
->X_add_number
, breg
);
13216 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13217 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13219 /* If necessary, move the result in tempreg to the final destination. */
13220 if (!ust
&& op
[0] != tempreg
)
13222 /* Protect second load's delay slot. */
13224 move_register (op
[0], tempreg
);
13230 if (target_big_endian
== ust
)
13231 ep
->X_add_number
+= off
;
13232 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13233 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13234 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13236 /* For halfword transfers we need a temporary register to shuffle
13237 bytes. Unfortunately for M_USH_A we have none available before
13238 the next store as AT holds the base address. We deal with this
13239 case by clobbering TREG and then restoring it as with ULH. */
13240 tempreg
= ust
== large_offset
? op
[0] : AT
;
13242 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13244 if (target_big_endian
== ust
)
13245 ep
->X_add_number
-= off
;
13247 ep
->X_add_number
+= off
;
13248 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13249 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13251 /* For M_USH_A re-retrieve the LSB. */
13252 if (ust
&& large_offset
)
13254 if (target_big_endian
)
13255 ep
->X_add_number
+= off
;
13257 ep
->X_add_number
-= off
;
13258 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13259 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13261 /* For ULH and M_USH_A OR the LSB in. */
13262 if (!ust
|| large_offset
)
13264 tempreg
= !large_offset
? AT
: op
[0];
13265 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13266 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13271 /* FIXME: Check if this is one of the itbl macros, since they
13272 are added dynamically. */
13273 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13276 if (!mips_opts
.at
&& used_at
)
13277 as_bad (_("macro used $at after \".set noat\""));
13280 /* Implement macros in mips16 mode. */
13283 mips16_macro (struct mips_cl_insn
*ip
)
13285 const struct mips_operand_array
*operands
;
13290 const char *s
, *s2
, *s3
;
13291 unsigned int op
[MAX_OPERANDS
];
13294 mask
= ip
->insn_mo
->mask
;
13296 operands
= insn_operands (ip
);
13297 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13298 if (operands
->operand
[i
])
13299 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13303 expr1
.X_op
= O_constant
;
13304 expr1
.X_op_symbol
= NULL
;
13305 expr1
.X_add_symbol
= NULL
;
13306 expr1
.X_add_number
= 1;
13325 start_noreorder ();
13326 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
13327 expr1
.X_add_number
= 2;
13328 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13329 macro_build (NULL
, "break", "6", 7);
13331 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13332 since that causes an overflow. We should do that as well,
13333 but I don't see how to do the comparisons without a temporary
13336 macro_build (NULL
, s
, "x", op
[0]);
13355 start_noreorder ();
13356 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
13357 expr1
.X_add_number
= 2;
13358 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13359 macro_build (NULL
, "break", "6", 7);
13361 macro_build (NULL
, s2
, "x", op
[0]);
13367 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13368 macro_build (NULL
, "mflo", "x", op
[0]);
13376 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13377 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
13381 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13382 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13386 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13387 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13409 goto do_reverse_branch
;
13413 goto do_reverse_branch
;
13425 goto do_reverse_branch
;
13436 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13437 macro_build (&offset_expr
, s2
, "p");
13464 goto do_addone_branch_i
;
13469 goto do_addone_branch_i
;
13484 goto do_addone_branch_i
;
13490 do_addone_branch_i
:
13491 ++imm_expr
.X_add_number
;
13494 macro_build (&imm_expr
, s
, s3
, op
[0]);
13495 macro_build (&offset_expr
, s2
, "p");
13499 expr1
.X_add_number
= 0;
13500 macro_build (&expr1
, "slti", "x,8", op
[1]);
13501 if (op
[0] != op
[1])
13502 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13503 expr1
.X_add_number
= 2;
13504 macro_build (&expr1
, "bteqz", "p");
13505 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13510 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13511 opcode bits in *OPCODE_EXTRA. */
13513 static struct mips_opcode
*
13514 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13515 ssize_t length
, unsigned int *opcode_extra
)
13517 char *name
, *dot
, *p
;
13518 unsigned int mask
, suffix
;
13520 struct mips_opcode
*insn
;
13522 /* Make a copy of the instruction so that we can fiddle with it. */
13523 name
= alloca (length
+ 1);
13524 memcpy (name
, start
, length
);
13525 name
[length
] = '\0';
13527 /* Look up the instruction as-is. */
13528 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13532 dot
= strchr (name
, '.');
13535 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13536 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13537 if (*p
== 0 && mask
!= 0)
13540 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13542 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13544 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13550 if (mips_opts
.micromips
)
13552 /* See if there's an instruction size override suffix,
13553 either `16' or `32', at the end of the mnemonic proper,
13554 that defines the operation, i.e. before the first `.'
13555 character if any. Strip it and retry. */
13556 opend
= dot
!= NULL
? dot
- name
: length
;
13557 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13559 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13565 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13566 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13569 forced_insn_length
= suffix
;
13578 /* Assemble an instruction into its binary format. If the instruction
13579 is a macro, set imm_expr and offset_expr to the values associated
13580 with "I" and "A" operands respectively. Otherwise store the value
13581 of the relocatable field (if any) in offset_expr. In both cases
13582 set offset_reloc to the relocation operators applied to offset_expr. */
13585 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13587 const struct mips_opcode
*first
, *past
;
13588 struct hash_control
*hash
;
13591 struct mips_operand_token
*tokens
;
13592 unsigned int opcode_extra
;
13594 if (mips_opts
.micromips
)
13596 hash
= micromips_op_hash
;
13597 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13602 past
= &mips_opcodes
[NUMOPCODES
];
13604 forced_insn_length
= 0;
13607 /* We first try to match an instruction up to a space or to the end. */
13608 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13611 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13614 set_insn_error (0, _("unrecognized opcode"));
13618 if (strcmp (first
->name
, "li.s") == 0)
13620 else if (strcmp (first
->name
, "li.d") == 0)
13624 tokens
= mips_parse_arguments (str
+ end
, format
);
13628 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13629 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13630 set_insn_error (0, _("invalid operands"));
13632 obstack_free (&mips_operand_tokens
, tokens
);
13635 /* As for mips_ip, but used when assembling MIPS16 code.
13636 Also set forced_insn_length to the resulting instruction size in
13637 bytes if the user explicitly requested a small or extended instruction. */
13640 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13643 struct mips_opcode
*first
;
13644 struct mips_operand_token
*tokens
;
13646 forced_insn_length
= 0;
13648 for (s
= str
; ISLOWER (*s
); ++s
)
13662 if (s
[1] == 't' && s
[2] == ' ')
13664 forced_insn_length
= 2;
13668 else if (s
[1] == 'e' && s
[2] == ' ')
13670 forced_insn_length
= 4;
13674 /* Fall through. */
13676 set_insn_error (0, _("unrecognized opcode"));
13680 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13681 forced_insn_length
= 2;
13684 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13689 set_insn_error (0, _("unrecognized opcode"));
13693 tokens
= mips_parse_arguments (s
, 0);
13697 if (!match_mips16_insns (insn
, first
, tokens
))
13698 set_insn_error (0, _("invalid operands"));
13700 obstack_free (&mips_operand_tokens
, tokens
);
13703 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13704 NBITS is the number of significant bits in VAL. */
13706 static unsigned long
13707 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13712 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13715 else if (nbits
== 15)
13717 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13722 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13725 return (extval
<< 16) | val
;
13728 /* Like decode_mips16_operand, but require the operand to be defined and
13729 require it to be an integer. */
13731 static const struct mips_int_operand
*
13732 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13734 const struct mips_operand
*operand
;
13736 operand
= decode_mips16_operand (type
, extended_p
);
13737 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13739 return (const struct mips_int_operand
*) operand
;
13742 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13745 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13746 bfd_reloc_code_real_type reloc
, offsetT sval
)
13748 int min_val
, max_val
;
13750 min_val
= mips_int_operand_min (operand
);
13751 max_val
= mips_int_operand_max (operand
);
13752 if (reloc
!= BFD_RELOC_UNUSED
)
13755 sval
= SEXT_16BIT (sval
);
13760 return (sval
>= min_val
13762 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13765 /* Install immediate value VAL into MIPS16 instruction *INSN,
13766 extending it if necessary. The instruction in *INSN may
13767 already be extended.
13769 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13770 if none. In the former case, VAL is a 16-bit number with no
13771 defined signedness.
13773 TYPE is the type of the immediate field. USER_INSN_LENGTH
13774 is the length that the user requested, or 0 if none. */
13777 mips16_immed (char *file
, unsigned int line
, int type
,
13778 bfd_reloc_code_real_type reloc
, offsetT val
,
13779 unsigned int user_insn_length
, unsigned long *insn
)
13781 const struct mips_int_operand
*operand
;
13782 unsigned int uval
, length
;
13784 operand
= mips16_immed_operand (type
, FALSE
);
13785 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13787 /* We need an extended instruction. */
13788 if (user_insn_length
== 2)
13789 as_bad_where (file
, line
, _("invalid unextended operand value"));
13791 *insn
|= MIPS16_EXTEND
;
13793 else if (user_insn_length
== 4)
13795 /* The operand doesn't force an unextended instruction to be extended.
13796 Warn if the user wanted an extended instruction anyway. */
13797 *insn
|= MIPS16_EXTEND
;
13798 as_warn_where (file
, line
,
13799 _("extended operand requested but not required"));
13802 length
= mips16_opcode_length (*insn
);
13805 operand
= mips16_immed_operand (type
, TRUE
);
13806 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13807 as_bad_where (file
, line
,
13808 _("operand value out of range for instruction"));
13810 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13812 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13814 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13817 struct percent_op_match
13820 bfd_reloc_code_real_type reloc
;
13823 static const struct percent_op_match mips_percent_op
[] =
13825 {"%lo", BFD_RELOC_LO16
},
13826 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13827 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13828 {"%call16", BFD_RELOC_MIPS_CALL16
},
13829 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13830 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13831 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13832 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13833 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13834 {"%got", BFD_RELOC_MIPS_GOT16
},
13835 {"%gp_rel", BFD_RELOC_GPREL16
},
13836 {"%half", BFD_RELOC_16
},
13837 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13838 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13839 {"%neg", BFD_RELOC_MIPS_SUB
},
13840 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13841 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13842 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13843 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13844 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13845 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13846 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13847 {"%hi", BFD_RELOC_HI16_S
},
13848 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
13849 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
13852 static const struct percent_op_match mips16_percent_op
[] =
13854 {"%lo", BFD_RELOC_MIPS16_LO16
},
13855 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13856 {"%got", BFD_RELOC_MIPS16_GOT16
},
13857 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13858 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13859 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13860 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13861 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13862 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13863 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13864 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13865 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13869 /* Return true if *STR points to a relocation operator. When returning true,
13870 move *STR over the operator and store its relocation code in *RELOC.
13871 Leave both *STR and *RELOC alone when returning false. */
13874 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13876 const struct percent_op_match
*percent_op
;
13879 if (mips_opts
.mips16
)
13881 percent_op
= mips16_percent_op
;
13882 limit
= ARRAY_SIZE (mips16_percent_op
);
13886 percent_op
= mips_percent_op
;
13887 limit
= ARRAY_SIZE (mips_percent_op
);
13890 for (i
= 0; i
< limit
; i
++)
13891 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13893 int len
= strlen (percent_op
[i
].str
);
13895 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13898 *str
+= strlen (percent_op
[i
].str
);
13899 *reloc
= percent_op
[i
].reloc
;
13901 /* Check whether the output BFD supports this relocation.
13902 If not, issue an error and fall back on something safe. */
13903 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13905 as_bad (_("relocation %s isn't supported by the current ABI"),
13906 percent_op
[i
].str
);
13907 *reloc
= BFD_RELOC_UNUSED
;
13915 /* Parse string STR as a 16-bit relocatable operand. Store the
13916 expression in *EP and the relocations in the array starting
13917 at RELOC. Return the number of relocation operators used.
13919 On exit, EXPR_END points to the first character after the expression. */
13922 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13925 bfd_reloc_code_real_type reversed_reloc
[3];
13926 size_t reloc_index
, i
;
13927 int crux_depth
, str_depth
;
13930 /* Search for the start of the main expression, recoding relocations
13931 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13932 of the main expression and with CRUX_DEPTH containing the number
13933 of open brackets at that point. */
13940 crux_depth
= str_depth
;
13942 /* Skip over whitespace and brackets, keeping count of the number
13944 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13949 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13950 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13952 my_getExpression (ep
, crux
);
13955 /* Match every open bracket. */
13956 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13960 if (crux_depth
> 0)
13961 as_bad (_("unclosed '('"));
13965 if (reloc_index
!= 0)
13967 prev_reloc_op_frag
= frag_now
;
13968 for (i
= 0; i
< reloc_index
; i
++)
13969 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13972 return reloc_index
;
13976 my_getExpression (expressionS
*ep
, char *str
)
13980 save_in
= input_line_pointer
;
13981 input_line_pointer
= str
;
13983 expr_end
= input_line_pointer
;
13984 input_line_pointer
= save_in
;
13988 md_atof (int type
, char *litP
, int *sizeP
)
13990 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13994 md_number_to_chars (char *buf
, valueT val
, int n
)
13996 if (target_big_endian
)
13997 number_to_chars_bigendian (buf
, val
, n
);
13999 number_to_chars_littleendian (buf
, val
, n
);
14002 static int support_64bit_objects(void)
14004 const char **list
, **l
;
14007 list
= bfd_target_list ();
14008 for (l
= list
; *l
!= NULL
; l
++)
14009 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14010 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14012 yes
= (*l
!= NULL
);
14017 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14018 NEW_VALUE. Warn if another value was already specified. Note:
14019 we have to defer parsing the -march and -mtune arguments in order
14020 to handle 'from-abi' correctly, since the ABI might be specified
14021 in a later argument. */
14024 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14026 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14027 as_warn (_("a different %s was already specified, is now %s"),
14028 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14031 *string_ptr
= new_value
;
14035 md_parse_option (int c
, char *arg
)
14039 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14040 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14042 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14043 c
== mips_ases
[i
].option_on
);
14049 case OPTION_CONSTRUCT_FLOATS
:
14050 mips_disable_float_construction
= 0;
14053 case OPTION_NO_CONSTRUCT_FLOATS
:
14054 mips_disable_float_construction
= 1;
14066 target_big_endian
= 1;
14070 target_big_endian
= 0;
14076 else if (arg
[0] == '0')
14078 else if (arg
[0] == '1')
14088 mips_debug
= atoi (arg
);
14092 file_mips_opts
.isa
= ISA_MIPS1
;
14096 file_mips_opts
.isa
= ISA_MIPS2
;
14100 file_mips_opts
.isa
= ISA_MIPS3
;
14104 file_mips_opts
.isa
= ISA_MIPS4
;
14108 file_mips_opts
.isa
= ISA_MIPS5
;
14111 case OPTION_MIPS32
:
14112 file_mips_opts
.isa
= ISA_MIPS32
;
14115 case OPTION_MIPS32R2
:
14116 file_mips_opts
.isa
= ISA_MIPS32R2
;
14119 case OPTION_MIPS32R3
:
14120 file_mips_opts
.isa
= ISA_MIPS32R3
;
14123 case OPTION_MIPS32R5
:
14124 file_mips_opts
.isa
= ISA_MIPS32R5
;
14127 case OPTION_MIPS32R6
:
14128 file_mips_opts
.isa
= ISA_MIPS32R6
;
14131 case OPTION_MIPS64R2
:
14132 file_mips_opts
.isa
= ISA_MIPS64R2
;
14135 case OPTION_MIPS64R3
:
14136 file_mips_opts
.isa
= ISA_MIPS64R3
;
14139 case OPTION_MIPS64R5
:
14140 file_mips_opts
.isa
= ISA_MIPS64R5
;
14143 case OPTION_MIPS64R6
:
14144 file_mips_opts
.isa
= ISA_MIPS64R6
;
14147 case OPTION_MIPS64
:
14148 file_mips_opts
.isa
= ISA_MIPS64
;
14152 mips_set_option_string (&mips_tune_string
, arg
);
14156 mips_set_option_string (&mips_arch_string
, arg
);
14160 mips_set_option_string (&mips_arch_string
, "4650");
14161 mips_set_option_string (&mips_tune_string
, "4650");
14164 case OPTION_NO_M4650
:
14168 mips_set_option_string (&mips_arch_string
, "4010");
14169 mips_set_option_string (&mips_tune_string
, "4010");
14172 case OPTION_NO_M4010
:
14176 mips_set_option_string (&mips_arch_string
, "4100");
14177 mips_set_option_string (&mips_tune_string
, "4100");
14180 case OPTION_NO_M4100
:
14184 mips_set_option_string (&mips_arch_string
, "3900");
14185 mips_set_option_string (&mips_tune_string
, "3900");
14188 case OPTION_NO_M3900
:
14191 case OPTION_MICROMIPS
:
14192 if (file_mips_opts
.mips16
== 1)
14194 as_bad (_("-mmicromips cannot be used with -mips16"));
14197 file_mips_opts
.micromips
= 1;
14198 mips_no_prev_insn ();
14201 case OPTION_NO_MICROMIPS
:
14202 file_mips_opts
.micromips
= 0;
14203 mips_no_prev_insn ();
14206 case OPTION_MIPS16
:
14207 if (file_mips_opts
.micromips
== 1)
14209 as_bad (_("-mips16 cannot be used with -micromips"));
14212 file_mips_opts
.mips16
= 1;
14213 mips_no_prev_insn ();
14216 case OPTION_NO_MIPS16
:
14217 file_mips_opts
.mips16
= 0;
14218 mips_no_prev_insn ();
14221 case OPTION_FIX_24K
:
14225 case OPTION_NO_FIX_24K
:
14229 case OPTION_FIX_RM7000
:
14230 mips_fix_rm7000
= 1;
14233 case OPTION_NO_FIX_RM7000
:
14234 mips_fix_rm7000
= 0;
14237 case OPTION_FIX_LOONGSON2F_JUMP
:
14238 mips_fix_loongson2f_jump
= TRUE
;
14241 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14242 mips_fix_loongson2f_jump
= FALSE
;
14245 case OPTION_FIX_LOONGSON2F_NOP
:
14246 mips_fix_loongson2f_nop
= TRUE
;
14249 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14250 mips_fix_loongson2f_nop
= FALSE
;
14253 case OPTION_FIX_VR4120
:
14254 mips_fix_vr4120
= 1;
14257 case OPTION_NO_FIX_VR4120
:
14258 mips_fix_vr4120
= 0;
14261 case OPTION_FIX_VR4130
:
14262 mips_fix_vr4130
= 1;
14265 case OPTION_NO_FIX_VR4130
:
14266 mips_fix_vr4130
= 0;
14269 case OPTION_FIX_CN63XXP1
:
14270 mips_fix_cn63xxp1
= TRUE
;
14273 case OPTION_NO_FIX_CN63XXP1
:
14274 mips_fix_cn63xxp1
= FALSE
;
14277 case OPTION_RELAX_BRANCH
:
14278 mips_relax_branch
= 1;
14281 case OPTION_NO_RELAX_BRANCH
:
14282 mips_relax_branch
= 0;
14285 case OPTION_INSN32
:
14286 file_mips_opts
.insn32
= TRUE
;
14289 case OPTION_NO_INSN32
:
14290 file_mips_opts
.insn32
= FALSE
;
14293 case OPTION_MSHARED
:
14294 mips_in_shared
= TRUE
;
14297 case OPTION_MNO_SHARED
:
14298 mips_in_shared
= FALSE
;
14301 case OPTION_MSYM32
:
14302 file_mips_opts
.sym32
= TRUE
;
14305 case OPTION_MNO_SYM32
:
14306 file_mips_opts
.sym32
= FALSE
;
14309 /* When generating ELF code, we permit -KPIC and -call_shared to
14310 select SVR4_PIC, and -non_shared to select no PIC. This is
14311 intended to be compatible with Irix 5. */
14312 case OPTION_CALL_SHARED
:
14313 mips_pic
= SVR4_PIC
;
14314 mips_abicalls
= TRUE
;
14317 case OPTION_CALL_NONPIC
:
14319 mips_abicalls
= TRUE
;
14322 case OPTION_NON_SHARED
:
14324 mips_abicalls
= FALSE
;
14327 /* The -xgot option tells the assembler to use 32 bit offsets
14328 when accessing the got in SVR4_PIC mode. It is for Irix
14335 g_switch_value
= atoi (arg
);
14339 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14342 mips_abi
= O32_ABI
;
14346 mips_abi
= N32_ABI
;
14350 mips_abi
= N64_ABI
;
14351 if (!support_64bit_objects())
14352 as_fatal (_("no compiled in support for 64 bit object file format"));
14356 file_mips_opts
.gp
= 32;
14360 file_mips_opts
.gp
= 64;
14364 file_mips_opts
.fp
= 32;
14368 file_mips_opts
.fp
= 0;
14372 file_mips_opts
.fp
= 64;
14375 case OPTION_ODD_SPREG
:
14376 file_mips_opts
.oddspreg
= 1;
14379 case OPTION_NO_ODD_SPREG
:
14380 file_mips_opts
.oddspreg
= 0;
14383 case OPTION_SINGLE_FLOAT
:
14384 file_mips_opts
.single_float
= 1;
14387 case OPTION_DOUBLE_FLOAT
:
14388 file_mips_opts
.single_float
= 0;
14391 case OPTION_SOFT_FLOAT
:
14392 file_mips_opts
.soft_float
= 1;
14395 case OPTION_HARD_FLOAT
:
14396 file_mips_opts
.soft_float
= 0;
14400 if (strcmp (arg
, "32") == 0)
14401 mips_abi
= O32_ABI
;
14402 else if (strcmp (arg
, "o64") == 0)
14403 mips_abi
= O64_ABI
;
14404 else if (strcmp (arg
, "n32") == 0)
14405 mips_abi
= N32_ABI
;
14406 else if (strcmp (arg
, "64") == 0)
14408 mips_abi
= N64_ABI
;
14409 if (! support_64bit_objects())
14410 as_fatal (_("no compiled in support for 64 bit object file "
14413 else if (strcmp (arg
, "eabi") == 0)
14414 mips_abi
= EABI_ABI
;
14417 as_fatal (_("invalid abi -mabi=%s"), arg
);
14422 case OPTION_M7000_HILO_FIX
:
14423 mips_7000_hilo_fix
= TRUE
;
14426 case OPTION_MNO_7000_HILO_FIX
:
14427 mips_7000_hilo_fix
= FALSE
;
14430 case OPTION_MDEBUG
:
14431 mips_flag_mdebug
= TRUE
;
14434 case OPTION_NO_MDEBUG
:
14435 mips_flag_mdebug
= FALSE
;
14439 mips_flag_pdr
= TRUE
;
14442 case OPTION_NO_PDR
:
14443 mips_flag_pdr
= FALSE
;
14446 case OPTION_MVXWORKS_PIC
:
14447 mips_pic
= VXWORKS_PIC
;
14451 if (strcmp (arg
, "2008") == 0)
14453 else if (strcmp (arg
, "legacy") == 0)
14457 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14466 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14471 /* Set up globals to tune for the ISA or processor described by INFO. */
14474 mips_set_tune (const struct mips_cpu_info
*info
)
14477 mips_tune
= info
->cpu
;
14482 mips_after_parse_args (void)
14484 const struct mips_cpu_info
*arch_info
= 0;
14485 const struct mips_cpu_info
*tune_info
= 0;
14487 /* GP relative stuff not working for PE */
14488 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14490 if (g_switch_seen
&& g_switch_value
!= 0)
14491 as_bad (_("-G not supported in this configuration"));
14492 g_switch_value
= 0;
14495 if (mips_abi
== NO_ABI
)
14496 mips_abi
= MIPS_DEFAULT_ABI
;
14498 /* The following code determines the architecture.
14499 Similar code was added to GCC 3.3 (see override_options() in
14500 config/mips/mips.c). The GAS and GCC code should be kept in sync
14501 as much as possible. */
14503 if (mips_arch_string
!= 0)
14504 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14506 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14508 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14509 ISA level specified by -mipsN, while arch_info->isa contains
14510 the -march selection (if any). */
14511 if (arch_info
!= 0)
14513 /* -march takes precedence over -mipsN, since it is more descriptive.
14514 There's no harm in specifying both as long as the ISA levels
14516 if (file_mips_opts
.isa
!= arch_info
->isa
)
14517 as_bad (_("-%s conflicts with the other architecture options,"
14518 " which imply -%s"),
14519 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14520 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14523 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14526 if (arch_info
== 0)
14528 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14529 gas_assert (arch_info
);
14532 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14533 as_bad (_("-march=%s is not compatible with the selected ABI"),
14536 file_mips_opts
.arch
= arch_info
->cpu
;
14537 file_mips_opts
.isa
= arch_info
->isa
;
14539 /* Set up initial mips_opts state. */
14540 mips_opts
= file_mips_opts
;
14542 /* The register size inference code is now placed in
14543 file_mips_check_options. */
14545 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14547 if (mips_tune_string
!= 0)
14548 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14550 if (tune_info
== 0)
14551 mips_set_tune (arch_info
);
14553 mips_set_tune (tune_info
);
14555 if (mips_flag_mdebug
< 0)
14556 mips_flag_mdebug
= 0;
14560 mips_init_after_args (void)
14562 /* initialize opcodes */
14563 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14564 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14568 md_pcrel_from (fixS
*fixP
)
14570 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14571 switch (fixP
->fx_r_type
)
14573 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14574 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14575 /* Return the address of the delay slot. */
14578 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14579 case BFD_RELOC_MICROMIPS_JMP
:
14580 case BFD_RELOC_16_PCREL_S2
:
14581 case BFD_RELOC_MIPS_21_PCREL_S2
:
14582 case BFD_RELOC_MIPS_26_PCREL_S2
:
14583 case BFD_RELOC_MIPS_JMP
:
14584 /* Return the address of the delay slot. */
14592 /* This is called before the symbol table is processed. In order to
14593 work with gcc when using mips-tfile, we must keep all local labels.
14594 However, in other cases, we want to discard them. If we were
14595 called with -g, but we didn't see any debugging information, it may
14596 mean that gcc is smuggling debugging information through to
14597 mips-tfile, in which case we must generate all local labels. */
14600 mips_frob_file_before_adjust (void)
14602 #ifndef NO_ECOFF_DEBUGGING
14603 if (ECOFF_DEBUGGING
14605 && ! ecoff_debugging_seen
)
14606 flag_keep_locals
= 1;
14610 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14611 the corresponding LO16 reloc. This is called before md_apply_fix and
14612 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14613 relocation operators.
14615 For our purposes, a %lo() expression matches a %got() or %hi()
14618 (a) it refers to the same symbol; and
14619 (b) the offset applied in the %lo() expression is no lower than
14620 the offset applied in the %got() or %hi().
14622 (b) allows us to cope with code like:
14625 lh $4,%lo(foo+2)($4)
14627 ...which is legal on RELA targets, and has a well-defined behaviour
14628 if the user knows that adding 2 to "foo" will not induce a carry to
14631 When several %lo()s match a particular %got() or %hi(), we use the
14632 following rules to distinguish them:
14634 (1) %lo()s with smaller offsets are a better match than %lo()s with
14637 (2) %lo()s with no matching %got() or %hi() are better than those
14638 that already have a matching %got() or %hi().
14640 (3) later %lo()s are better than earlier %lo()s.
14642 These rules are applied in order.
14644 (1) means, among other things, that %lo()s with identical offsets are
14645 chosen if they exist.
14647 (2) means that we won't associate several high-part relocations with
14648 the same low-part relocation unless there's no alternative. Having
14649 several high parts for the same low part is a GNU extension; this rule
14650 allows careful users to avoid it.
14652 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14653 with the last high-part relocation being at the front of the list.
14654 It therefore makes sense to choose the last matching low-part
14655 relocation, all other things being equal. It's also easier
14656 to code that way. */
14659 mips_frob_file (void)
14661 struct mips_hi_fixup
*l
;
14662 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14664 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14666 segment_info_type
*seginfo
;
14667 bfd_boolean matched_lo_p
;
14668 fixS
**hi_pos
, **lo_pos
, **pos
;
14670 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14672 /* If a GOT16 relocation turns out to be against a global symbol,
14673 there isn't supposed to be a matching LO. Ignore %gots against
14674 constants; we'll report an error for those later. */
14675 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14676 && !(l
->fixp
->fx_addsy
14677 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14680 /* Check quickly whether the next fixup happens to be a matching %lo. */
14681 if (fixup_has_matching_lo_p (l
->fixp
))
14684 seginfo
= seg_info (l
->seg
);
14686 /* Set HI_POS to the position of this relocation in the chain.
14687 Set LO_POS to the position of the chosen low-part relocation.
14688 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14689 relocation that matches an immediately-preceding high-part
14693 matched_lo_p
= FALSE
;
14694 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14696 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14698 if (*pos
== l
->fixp
)
14701 if ((*pos
)->fx_r_type
== looking_for_rtype
14702 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14703 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14705 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14707 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14710 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14711 && fixup_has_matching_lo_p (*pos
));
14714 /* If we found a match, remove the high-part relocation from its
14715 current position and insert it before the low-part relocation.
14716 Make the offsets match so that fixup_has_matching_lo_p()
14719 We don't warn about unmatched high-part relocations since some
14720 versions of gcc have been known to emit dead "lui ...%hi(...)"
14722 if (lo_pos
!= NULL
)
14724 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14725 if (l
->fixp
->fx_next
!= *lo_pos
)
14727 *hi_pos
= l
->fixp
->fx_next
;
14728 l
->fixp
->fx_next
= *lo_pos
;
14736 mips_force_relocation (fixS
*fixp
)
14738 if (generic_force_reloc (fixp
))
14741 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14742 so that the linker relaxation can update targets. */
14743 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14744 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14745 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14748 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14749 if (ISA_IS_R6 (mips_opts
.isa
)
14750 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14751 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
14752 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
14753 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
14754 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
14755 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
14756 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
14762 /* Read the instruction associated with RELOC from BUF. */
14764 static unsigned int
14765 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14767 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14768 return read_compressed_insn (buf
, 4);
14770 return read_insn (buf
);
14773 /* Write instruction INSN to BUF, given that it has been relocated
14777 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14778 unsigned long insn
)
14780 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14781 write_compressed_insn (buf
, insn
, 4);
14783 write_insn (buf
, insn
);
14786 /* Apply a fixup to the object file. */
14789 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14792 unsigned long insn
;
14793 reloc_howto_type
*howto
;
14795 if (fixP
->fx_pcrel
)
14796 switch (fixP
->fx_r_type
)
14798 case BFD_RELOC_16_PCREL_S2
:
14799 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14800 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14801 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14802 case BFD_RELOC_32_PCREL
:
14803 case BFD_RELOC_MIPS_21_PCREL_S2
:
14804 case BFD_RELOC_MIPS_26_PCREL_S2
:
14805 case BFD_RELOC_MIPS_18_PCREL_S3
:
14806 case BFD_RELOC_MIPS_19_PCREL_S2
:
14807 case BFD_RELOC_HI16_S_PCREL
:
14808 case BFD_RELOC_LO16_PCREL
:
14812 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
14816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14817 _("PC-relative reference to a different section"));
14821 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14822 that have no MIPS ELF equivalent. */
14823 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
14825 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14830 gas_assert (fixP
->fx_size
== 2
14831 || fixP
->fx_size
== 4
14832 || fixP
->fx_r_type
== BFD_RELOC_8
14833 || fixP
->fx_r_type
== BFD_RELOC_16
14834 || fixP
->fx_r_type
== BFD_RELOC_64
14835 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14836 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14837 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14838 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14839 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14840 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14842 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14844 /* Don't treat parts of a composite relocation as done. There are two
14847 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14848 should nevertheless be emitted if the first part is.
14850 (2) In normal usage, composite relocations are never assembly-time
14851 constants. The easiest way of dealing with the pathological
14852 exceptions is to generate a relocation against STN_UNDEF and
14853 leave everything up to the linker. */
14854 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14857 switch (fixP
->fx_r_type
)
14859 case BFD_RELOC_MIPS_TLS_GD
:
14860 case BFD_RELOC_MIPS_TLS_LDM
:
14861 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14862 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14863 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14864 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14865 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14866 case BFD_RELOC_MIPS_TLS_TPREL32
:
14867 case BFD_RELOC_MIPS_TLS_TPREL64
:
14868 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14869 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14870 case BFD_RELOC_MICROMIPS_TLS_GD
:
14871 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14872 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14873 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14874 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14875 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14876 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14877 case BFD_RELOC_MIPS16_TLS_GD
:
14878 case BFD_RELOC_MIPS16_TLS_LDM
:
14879 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14880 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14881 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14882 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14883 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14884 if (!fixP
->fx_addsy
)
14886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14887 _("TLS relocation against a constant"));
14890 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14893 case BFD_RELOC_MIPS_JMP
:
14894 case BFD_RELOC_MIPS_SHIFT5
:
14895 case BFD_RELOC_MIPS_SHIFT6
:
14896 case BFD_RELOC_MIPS_GOT_DISP
:
14897 case BFD_RELOC_MIPS_GOT_PAGE
:
14898 case BFD_RELOC_MIPS_GOT_OFST
:
14899 case BFD_RELOC_MIPS_SUB
:
14900 case BFD_RELOC_MIPS_INSERT_A
:
14901 case BFD_RELOC_MIPS_INSERT_B
:
14902 case BFD_RELOC_MIPS_DELETE
:
14903 case BFD_RELOC_MIPS_HIGHEST
:
14904 case BFD_RELOC_MIPS_HIGHER
:
14905 case BFD_RELOC_MIPS_SCN_DISP
:
14906 case BFD_RELOC_MIPS_REL16
:
14907 case BFD_RELOC_MIPS_RELGOT
:
14908 case BFD_RELOC_MIPS_JALR
:
14909 case BFD_RELOC_HI16
:
14910 case BFD_RELOC_HI16_S
:
14911 case BFD_RELOC_LO16
:
14912 case BFD_RELOC_GPREL16
:
14913 case BFD_RELOC_MIPS_LITERAL
:
14914 case BFD_RELOC_MIPS_CALL16
:
14915 case BFD_RELOC_MIPS_GOT16
:
14916 case BFD_RELOC_GPREL32
:
14917 case BFD_RELOC_MIPS_GOT_HI16
:
14918 case BFD_RELOC_MIPS_GOT_LO16
:
14919 case BFD_RELOC_MIPS_CALL_HI16
:
14920 case BFD_RELOC_MIPS_CALL_LO16
:
14921 case BFD_RELOC_MIPS16_GPREL
:
14922 case BFD_RELOC_MIPS16_GOT16
:
14923 case BFD_RELOC_MIPS16_CALL16
:
14924 case BFD_RELOC_MIPS16_HI16
:
14925 case BFD_RELOC_MIPS16_HI16_S
:
14926 case BFD_RELOC_MIPS16_LO16
:
14927 case BFD_RELOC_MIPS16_JMP
:
14928 case BFD_RELOC_MICROMIPS_JMP
:
14929 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14930 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14931 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14932 case BFD_RELOC_MICROMIPS_SUB
:
14933 case BFD_RELOC_MICROMIPS_HIGHEST
:
14934 case BFD_RELOC_MICROMIPS_HIGHER
:
14935 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14936 case BFD_RELOC_MICROMIPS_JALR
:
14937 case BFD_RELOC_MICROMIPS_HI16
:
14938 case BFD_RELOC_MICROMIPS_HI16_S
:
14939 case BFD_RELOC_MICROMIPS_LO16
:
14940 case BFD_RELOC_MICROMIPS_GPREL16
:
14941 case BFD_RELOC_MICROMIPS_LITERAL
:
14942 case BFD_RELOC_MICROMIPS_CALL16
:
14943 case BFD_RELOC_MICROMIPS_GOT16
:
14944 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14945 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14946 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14947 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14948 case BFD_RELOC_MIPS_EH
:
14953 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14955 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14956 if (mips16_reloc_p (fixP
->fx_r_type
))
14957 insn
|= mips16_immed_extend (value
, 16);
14959 insn
|= (value
& 0xffff);
14960 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14964 _("unsupported constant in relocation"));
14969 /* This is handled like BFD_RELOC_32, but we output a sign
14970 extended value if we are only 32 bits. */
14973 if (8 <= sizeof (valueT
))
14974 md_number_to_chars (buf
, *valP
, 8);
14979 if ((*valP
& 0x80000000) != 0)
14983 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14984 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14989 case BFD_RELOC_RVA
:
14991 case BFD_RELOC_32_PCREL
:
14994 /* If we are deleting this reloc entry, we must fill in the
14995 value now. This can happen if we have a .word which is not
14996 resolved when it appears but is later defined. */
14998 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15001 case BFD_RELOC_MIPS_21_PCREL_S2
:
15002 case BFD_RELOC_MIPS_26_PCREL_S2
:
15003 if ((*valP
& 0x3) != 0)
15004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15005 _("branch to misaligned address (%lx)"), (long) *valP
);
15007 gas_assert (!fixP
->fx_done
);
15010 case BFD_RELOC_MIPS_18_PCREL_S3
:
15011 if ((*valP
& 0x7) != 0)
15012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15013 _("PC-relative access to misaligned address (%lx)"),
15016 gas_assert (!fixP
->fx_done
);
15019 case BFD_RELOC_MIPS_19_PCREL_S2
:
15020 if ((*valP
& 0x3) != 0)
15021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15022 _("PC-relative access to misaligned address (%lx)"),
15025 gas_assert (!fixP
->fx_done
);
15028 case BFD_RELOC_HI16_S_PCREL
:
15029 case BFD_RELOC_LO16_PCREL
:
15030 gas_assert (!fixP
->fx_done
);
15033 case BFD_RELOC_16_PCREL_S2
:
15034 if ((*valP
& 0x3) != 0)
15035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15036 _("branch to misaligned address (%lx)"), (long) *valP
);
15038 /* We need to save the bits in the instruction since fixup_segment()
15039 might be deleting the relocation entry (i.e., a branch within
15040 the current segment). */
15041 if (! fixP
->fx_done
)
15044 /* Update old instruction data. */
15045 insn
= read_insn (buf
);
15047 if (*valP
+ 0x20000 <= 0x3ffff)
15049 insn
|= (*valP
>> 2) & 0xffff;
15050 write_insn (buf
, insn
);
15052 else if (mips_pic
== NO_PIC
15054 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15055 && (fixP
->fx_frag
->fr_address
15056 < text_section
->vma
+ bfd_get_section_size (text_section
))
15057 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15058 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15059 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15061 /* The branch offset is too large. If this is an
15062 unconditional branch, and we are not generating PIC code,
15063 we can convert it to an absolute jump instruction. */
15064 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15065 insn
= 0x0c000000; /* jal */
15067 insn
= 0x08000000; /* j */
15068 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15070 fixP
->fx_addsy
= section_symbol (text_section
);
15071 *valP
+= md_pcrel_from (fixP
);
15072 write_insn (buf
, insn
);
15076 /* If we got here, we have branch-relaxation disabled,
15077 and there's nothing we can do to fix this instruction
15078 without turning it into a longer sequence. */
15079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15080 _("branch out of range"));
15084 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15085 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15086 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15087 /* We adjust the offset back to even. */
15088 if ((*valP
& 0x1) != 0)
15091 if (! fixP
->fx_done
)
15094 /* Should never visit here, because we keep the relocation. */
15098 case BFD_RELOC_VTABLE_INHERIT
:
15101 && !S_IS_DEFINED (fixP
->fx_addsy
)
15102 && !S_IS_WEAK (fixP
->fx_addsy
))
15103 S_SET_WEAK (fixP
->fx_addsy
);
15106 case BFD_RELOC_VTABLE_ENTRY
:
15114 /* Remember value for tc_gen_reloc. */
15115 fixP
->fx_addnumber
= *valP
;
15125 name
= input_line_pointer
;
15126 c
= get_symbol_end ();
15127 p
= (symbolS
*) symbol_find_or_make (name
);
15128 *input_line_pointer
= c
;
15132 /* Align the current frag to a given power of two. If a particular
15133 fill byte should be used, FILL points to an integer that contains
15134 that byte, otherwise FILL is null.
15136 This function used to have the comment:
15138 The MIPS assembler also automatically adjusts any preceding label.
15140 The implementation therefore applied the adjustment to a maximum of
15141 one label. However, other label adjustments are applied to batches
15142 of labels, and adjusting just one caused problems when new labels
15143 were added for the sake of debugging or unwind information.
15144 We therefore adjust all preceding labels (given as LABELS) instead. */
15147 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15149 mips_emit_delays ();
15150 mips_record_compressed_mode ();
15151 if (fill
== NULL
&& subseg_text_p (now_seg
))
15152 frag_align_code (to
, 0);
15154 frag_align (to
, fill
? *fill
: 0, 0);
15155 record_alignment (now_seg
, to
);
15156 mips_move_labels (labels
, FALSE
);
15159 /* Align to a given power of two. .align 0 turns off the automatic
15160 alignment used by the data creating pseudo-ops. */
15163 s_align (int x ATTRIBUTE_UNUSED
)
15165 int temp
, fill_value
, *fill_ptr
;
15166 long max_alignment
= 28;
15168 /* o Note that the assembler pulls down any immediately preceding label
15169 to the aligned address.
15170 o It's not documented but auto alignment is reinstated by
15171 a .align pseudo instruction.
15172 o Note also that after auto alignment is turned off the mips assembler
15173 issues an error on attempt to assemble an improperly aligned data item.
15176 temp
= get_absolute_expression ();
15177 if (temp
> max_alignment
)
15178 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15181 as_warn (_("alignment negative, 0 assumed"));
15184 if (*input_line_pointer
== ',')
15186 ++input_line_pointer
;
15187 fill_value
= get_absolute_expression ();
15188 fill_ptr
= &fill_value
;
15194 segment_info_type
*si
= seg_info (now_seg
);
15195 struct insn_label_list
*l
= si
->label_list
;
15196 /* Auto alignment should be switched on by next section change. */
15198 mips_align (temp
, fill_ptr
, l
);
15205 demand_empty_rest_of_line ();
15209 s_change_sec (int sec
)
15213 /* The ELF backend needs to know that we are changing sections, so
15214 that .previous works correctly. We could do something like check
15215 for an obj_section_change_hook macro, but that might be confusing
15216 as it would not be appropriate to use it in the section changing
15217 functions in read.c, since obj-elf.c intercepts those. FIXME:
15218 This should be cleaner, somehow. */
15219 obj_elf_section_change_hook ();
15221 mips_emit_delays ();
15232 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15233 demand_empty_rest_of_line ();
15237 seg
= subseg_new (RDATA_SECTION_NAME
,
15238 (subsegT
) get_absolute_expression ());
15239 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15240 | SEC_READONLY
| SEC_RELOC
15242 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15243 record_alignment (seg
, 4);
15244 demand_empty_rest_of_line ();
15248 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15249 bfd_set_section_flags (stdoutput
, seg
,
15250 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15251 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15252 record_alignment (seg
, 4);
15253 demand_empty_rest_of_line ();
15257 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15258 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15259 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15260 record_alignment (seg
, 4);
15261 demand_empty_rest_of_line ();
15269 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15271 char *section_name
;
15276 int section_entry_size
;
15277 int section_alignment
;
15279 section_name
= input_line_pointer
;
15280 c
= get_symbol_end ();
15282 next_c
= *(input_line_pointer
+ 1);
15284 /* Do we have .section Name<,"flags">? */
15285 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15287 /* just after name is now '\0'. */
15288 *input_line_pointer
= c
;
15289 input_line_pointer
= section_name
;
15290 obj_elf_section (ignore
);
15293 input_line_pointer
++;
15295 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15297 section_type
= get_absolute_expression ();
15300 if (*input_line_pointer
++ == ',')
15301 section_flag
= get_absolute_expression ();
15304 if (*input_line_pointer
++ == ',')
15305 section_entry_size
= get_absolute_expression ();
15307 section_entry_size
= 0;
15308 if (*input_line_pointer
++ == ',')
15309 section_alignment
= get_absolute_expression ();
15311 section_alignment
= 0;
15312 /* FIXME: really ignore? */
15313 (void) section_alignment
;
15315 section_name
= xstrdup (section_name
);
15317 /* When using the generic form of .section (as implemented by obj-elf.c),
15318 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15319 traditionally had to fall back on the more common @progbits instead.
15321 There's nothing really harmful in this, since bfd will correct
15322 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15323 means that, for backwards compatibility, the special_section entries
15324 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15326 Even so, we shouldn't force users of the MIPS .section syntax to
15327 incorrectly label the sections as SHT_PROGBITS. The best compromise
15328 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15329 generic type-checking code. */
15330 if (section_type
== SHT_MIPS_DWARF
)
15331 section_type
= SHT_PROGBITS
;
15333 obj_elf_change_section (section_name
, section_type
, section_flag
,
15334 section_entry_size
, 0, 0, 0);
15336 if (now_seg
->name
!= section_name
)
15337 free (section_name
);
15341 mips_enable_auto_align (void)
15347 s_cons (int log_size
)
15349 segment_info_type
*si
= seg_info (now_seg
);
15350 struct insn_label_list
*l
= si
->label_list
;
15352 mips_emit_delays ();
15353 if (log_size
> 0 && auto_align
)
15354 mips_align (log_size
, 0, l
);
15355 cons (1 << log_size
);
15356 mips_clear_insn_labels ();
15360 s_float_cons (int type
)
15362 segment_info_type
*si
= seg_info (now_seg
);
15363 struct insn_label_list
*l
= si
->label_list
;
15365 mips_emit_delays ();
15370 mips_align (3, 0, l
);
15372 mips_align (2, 0, l
);
15376 mips_clear_insn_labels ();
15379 /* Handle .globl. We need to override it because on Irix 5 you are
15382 where foo is an undefined symbol, to mean that foo should be
15383 considered to be the address of a function. */
15386 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15395 name
= input_line_pointer
;
15396 c
= get_symbol_end ();
15397 symbolP
= symbol_find_or_make (name
);
15398 S_SET_EXTERNAL (symbolP
);
15400 *input_line_pointer
= c
;
15401 SKIP_WHITESPACE ();
15403 /* On Irix 5, every global symbol that is not explicitly labelled as
15404 being a function is apparently labelled as being an object. */
15407 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15408 && (*input_line_pointer
!= ','))
15413 secname
= input_line_pointer
;
15414 c
= get_symbol_end ();
15415 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15417 as_bad (_("%s: no such section"), secname
);
15418 *input_line_pointer
= c
;
15420 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15421 flag
= BSF_FUNCTION
;
15424 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15426 c
= *input_line_pointer
;
15429 input_line_pointer
++;
15430 SKIP_WHITESPACE ();
15431 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
15437 demand_empty_rest_of_line ();
15441 s_option (int x ATTRIBUTE_UNUSED
)
15446 opt
= input_line_pointer
;
15447 c
= get_symbol_end ();
15451 /* FIXME: What does this mean? */
15453 else if (strncmp (opt
, "pic", 3) == 0)
15457 i
= atoi (opt
+ 3);
15462 mips_pic
= SVR4_PIC
;
15463 mips_abicalls
= TRUE
;
15466 as_bad (_(".option pic%d not supported"), i
);
15468 if (mips_pic
== SVR4_PIC
)
15470 if (g_switch_seen
&& g_switch_value
!= 0)
15471 as_warn (_("-G may not be used with SVR4 PIC code"));
15472 g_switch_value
= 0;
15473 bfd_set_gp_size (stdoutput
, 0);
15477 as_warn (_("unrecognized option \"%s\""), opt
);
15479 *input_line_pointer
= c
;
15480 demand_empty_rest_of_line ();
15483 /* This structure is used to hold a stack of .set values. */
15485 struct mips_option_stack
15487 struct mips_option_stack
*next
;
15488 struct mips_set_options options
;
15491 static struct mips_option_stack
*mips_opts_stack
;
15494 parse_code_option (char * name
)
15496 const struct mips_ase
*ase
;
15497 if (strncmp (name
, "at=", 3) == 0)
15499 char *s
= name
+ 3;
15501 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15502 as_bad (_("unrecognized register name `%s'"), s
);
15504 else if (strcmp (name
, "at") == 0)
15505 mips_opts
.at
= ATREG
;
15506 else if (strcmp (name
, "noat") == 0)
15507 mips_opts
.at
= ZERO
;
15508 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15509 mips_opts
.nomove
= 0;
15510 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15511 mips_opts
.nomove
= 1;
15512 else if (strcmp (name
, "bopt") == 0)
15513 mips_opts
.nobopt
= 0;
15514 else if (strcmp (name
, "nobopt") == 0)
15515 mips_opts
.nobopt
= 1;
15516 else if (strcmp (name
, "gp=32") == 0)
15518 else if (strcmp (name
, "gp=64") == 0)
15520 else if (strcmp (name
, "fp=32") == 0)
15522 else if (strcmp (name
, "fp=xx") == 0)
15524 else if (strcmp (name
, "fp=64") == 0)
15526 else if (strcmp (name
, "softfloat") == 0)
15527 mips_opts
.soft_float
= 1;
15528 else if (strcmp (name
, "hardfloat") == 0)
15529 mips_opts
.soft_float
= 0;
15530 else if (strcmp (name
, "singlefloat") == 0)
15531 mips_opts
.single_float
= 1;
15532 else if (strcmp (name
, "doublefloat") == 0)
15533 mips_opts
.single_float
= 0;
15534 else if (strcmp (name
, "nooddspreg") == 0)
15535 mips_opts
.oddspreg
= 0;
15536 else if (strcmp (name
, "oddspreg") == 0)
15537 mips_opts
.oddspreg
= 1;
15538 else if (strcmp (name
, "mips16") == 0
15539 || strcmp (name
, "MIPS-16") == 0)
15540 mips_opts
.mips16
= 1;
15541 else if (strcmp (name
, "nomips16") == 0
15542 || strcmp (name
, "noMIPS-16") == 0)
15543 mips_opts
.mips16
= 0;
15544 else if (strcmp (name
, "micromips") == 0)
15545 mips_opts
.micromips
= 1;
15546 else if (strcmp (name
, "nomicromips") == 0)
15547 mips_opts
.micromips
= 0;
15548 else if (name
[0] == 'n'
15550 && (ase
= mips_lookup_ase (name
+ 2)))
15551 mips_set_ase (ase
, &mips_opts
, FALSE
);
15552 else if ((ase
= mips_lookup_ase (name
)))
15553 mips_set_ase (ase
, &mips_opts
, TRUE
);
15554 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15556 /* Permit the user to change the ISA and architecture on the fly.
15557 Needless to say, misuse can cause serious problems. */
15558 if (strncmp (name
, "arch=", 5) == 0)
15560 const struct mips_cpu_info
*p
;
15562 p
= mips_parse_cpu ("internal use", name
+ 5);
15564 as_bad (_("unknown architecture %s"), name
+ 5);
15567 mips_opts
.arch
= p
->cpu
;
15568 mips_opts
.isa
= p
->isa
;
15571 else if (strncmp (name
, "mips", 4) == 0)
15573 const struct mips_cpu_info
*p
;
15575 p
= mips_parse_cpu ("internal use", name
);
15577 as_bad (_("unknown ISA level %s"), name
+ 4);
15580 mips_opts
.arch
= p
->cpu
;
15581 mips_opts
.isa
= p
->isa
;
15585 as_bad (_("unknown ISA or architecture %s"), name
);
15587 else if (strcmp (name
, "autoextend") == 0)
15588 mips_opts
.noautoextend
= 0;
15589 else if (strcmp (name
, "noautoextend") == 0)
15590 mips_opts
.noautoextend
= 1;
15591 else if (strcmp (name
, "insn32") == 0)
15592 mips_opts
.insn32
= TRUE
;
15593 else if (strcmp (name
, "noinsn32") == 0)
15594 mips_opts
.insn32
= FALSE
;
15595 else if (strcmp (name
, "sym32") == 0)
15596 mips_opts
.sym32
= TRUE
;
15597 else if (strcmp (name
, "nosym32") == 0)
15598 mips_opts
.sym32
= FALSE
;
15604 /* Handle the .set pseudo-op. */
15607 s_mipsset (int x ATTRIBUTE_UNUSED
)
15609 char *name
= input_line_pointer
, ch
;
15610 int prev_isa
= mips_opts
.isa
;
15612 file_mips_check_options ();
15614 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15615 ++input_line_pointer
;
15616 ch
= *input_line_pointer
;
15617 *input_line_pointer
= '\0';
15619 if (strchr (name
, ','))
15621 /* Generic ".set" directive; use the generic handler. */
15622 *input_line_pointer
= ch
;
15623 input_line_pointer
= name
;
15628 if (strcmp (name
, "reorder") == 0)
15630 if (mips_opts
.noreorder
)
15633 else if (strcmp (name
, "noreorder") == 0)
15635 if (!mips_opts
.noreorder
)
15636 start_noreorder ();
15638 else if (strcmp (name
, "macro") == 0)
15639 mips_opts
.warn_about_macros
= 0;
15640 else if (strcmp (name
, "nomacro") == 0)
15642 if (mips_opts
.noreorder
== 0)
15643 as_bad (_("`noreorder' must be set before `nomacro'"));
15644 mips_opts
.warn_about_macros
= 1;
15646 else if (strcmp (name
, "gp=default") == 0)
15647 mips_opts
.gp
= file_mips_opts
.gp
;
15648 else if (strcmp (name
, "fp=default") == 0)
15649 mips_opts
.fp
= file_mips_opts
.fp
;
15650 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15652 mips_opts
.isa
= file_mips_opts
.isa
;
15653 mips_opts
.arch
= file_mips_opts
.arch
;
15654 mips_opts
.gp
= file_mips_opts
.gp
;
15655 mips_opts
.fp
= file_mips_opts
.fp
;
15657 else if (strcmp (name
, "push") == 0)
15659 struct mips_option_stack
*s
;
15661 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15662 s
->next
= mips_opts_stack
;
15663 s
->options
= mips_opts
;
15664 mips_opts_stack
= s
;
15666 else if (strcmp (name
, "pop") == 0)
15668 struct mips_option_stack
*s
;
15670 s
= mips_opts_stack
;
15672 as_bad (_(".set pop with no .set push"));
15675 /* If we're changing the reorder mode we need to handle
15676 delay slots correctly. */
15677 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15678 start_noreorder ();
15679 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15682 mips_opts
= s
->options
;
15683 mips_opts_stack
= s
->next
;
15687 else if (!parse_code_option (name
))
15688 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
15690 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15691 registers based on what is supported by the arch/cpu. */
15692 if (mips_opts
.isa
!= prev_isa
)
15694 switch (mips_opts
.isa
)
15699 /* MIPS I cannot support FPXX. */
15701 /* fall-through. */
15708 if (mips_opts
.fp
!= 0)
15724 if (mips_opts
.fp
!= 0)
15726 if (mips_opts
.arch
== CPU_R5900
)
15733 as_bad (_("unknown ISA level %s"), name
+ 4);
15738 mips_check_options (&mips_opts
, FALSE
);
15740 mips_check_isa_supports_ases ();
15741 *input_line_pointer
= ch
;
15742 demand_empty_rest_of_line ();
15745 /* Handle the .module pseudo-op. */
15748 s_module (int ignore ATTRIBUTE_UNUSED
)
15750 char *name
= input_line_pointer
, ch
;
15752 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15753 ++input_line_pointer
;
15754 ch
= *input_line_pointer
;
15755 *input_line_pointer
= '\0';
15757 if (!file_mips_opts_checked
)
15759 if (!parse_code_option (name
))
15760 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
15762 /* Update module level settings from mips_opts. */
15763 file_mips_opts
= mips_opts
;
15766 as_bad (_(".module is not permitted after generating code"));
15768 *input_line_pointer
= ch
;
15769 demand_empty_rest_of_line ();
15772 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15773 .option pic2. It means to generate SVR4 PIC calls. */
15776 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15778 mips_pic
= SVR4_PIC
;
15779 mips_abicalls
= TRUE
;
15781 if (g_switch_seen
&& g_switch_value
!= 0)
15782 as_warn (_("-G may not be used with SVR4 PIC code"));
15783 g_switch_value
= 0;
15785 bfd_set_gp_size (stdoutput
, 0);
15786 demand_empty_rest_of_line ();
15789 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15790 PIC code. It sets the $gp register for the function based on the
15791 function address, which is in the register named in the argument.
15792 This uses a relocation against _gp_disp, which is handled specially
15793 by the linker. The result is:
15794 lui $gp,%hi(_gp_disp)
15795 addiu $gp,$gp,%lo(_gp_disp)
15796 addu $gp,$gp,.cpload argument
15797 The .cpload argument is normally $25 == $t9.
15799 The -mno-shared option changes this to:
15800 lui $gp,%hi(__gnu_local_gp)
15801 addiu $gp,$gp,%lo(__gnu_local_gp)
15802 and the argument is ignored. This saves an instruction, but the
15803 resulting code is not position independent; it uses an absolute
15804 address for __gnu_local_gp. Thus code assembled with -mno-shared
15805 can go into an ordinary executable, but not into a shared library. */
15808 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15814 file_mips_check_options ();
15816 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15817 .cpload is ignored. */
15818 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15824 if (mips_opts
.mips16
)
15826 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15827 ignore_rest_of_line ();
15831 /* .cpload should be in a .set noreorder section. */
15832 if (mips_opts
.noreorder
== 0)
15833 as_warn (_(".cpload not in noreorder section"));
15835 reg
= tc_get_register (0);
15837 /* If we need to produce a 64-bit address, we are better off using
15838 the default instruction sequence. */
15839 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15841 ex
.X_op
= O_symbol
;
15842 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15844 ex
.X_op_symbol
= NULL
;
15845 ex
.X_add_number
= 0;
15847 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15848 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15850 mips_mark_labels ();
15851 mips_assembling_insn
= TRUE
;
15854 macro_build_lui (&ex
, mips_gp_register
);
15855 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15856 mips_gp_register
, BFD_RELOC_LO16
);
15858 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15859 mips_gp_register
, reg
);
15862 mips_assembling_insn
= FALSE
;
15863 demand_empty_rest_of_line ();
15866 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15867 .cpsetup $reg1, offset|$reg2, label
15869 If offset is given, this results in:
15870 sd $gp, offset($sp)
15871 lui $gp, %hi(%neg(%gp_rel(label)))
15872 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15873 daddu $gp, $gp, $reg1
15875 If $reg2 is given, this results in:
15876 daddu $reg2, $gp, $0
15877 lui $gp, %hi(%neg(%gp_rel(label)))
15878 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15879 daddu $gp, $gp, $reg1
15880 $reg1 is normally $25 == $t9.
15882 The -mno-shared option replaces the last three instructions with
15884 addiu $gp,$gp,%lo(_gp) */
15887 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15889 expressionS ex_off
;
15890 expressionS ex_sym
;
15893 file_mips_check_options ();
15895 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15896 We also need NewABI support. */
15897 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15903 if (mips_opts
.mips16
)
15905 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15906 ignore_rest_of_line ();
15910 reg1
= tc_get_register (0);
15911 SKIP_WHITESPACE ();
15912 if (*input_line_pointer
!= ',')
15914 as_bad (_("missing argument separator ',' for .cpsetup"));
15918 ++input_line_pointer
;
15919 SKIP_WHITESPACE ();
15920 if (*input_line_pointer
== '$')
15922 mips_cpreturn_register
= tc_get_register (0);
15923 mips_cpreturn_offset
= -1;
15927 mips_cpreturn_offset
= get_absolute_expression ();
15928 mips_cpreturn_register
= -1;
15930 SKIP_WHITESPACE ();
15931 if (*input_line_pointer
!= ',')
15933 as_bad (_("missing argument separator ',' for .cpsetup"));
15937 ++input_line_pointer
;
15938 SKIP_WHITESPACE ();
15939 expression (&ex_sym
);
15941 mips_mark_labels ();
15942 mips_assembling_insn
= TRUE
;
15945 if (mips_cpreturn_register
== -1)
15947 ex_off
.X_op
= O_constant
;
15948 ex_off
.X_add_symbol
= NULL
;
15949 ex_off
.X_op_symbol
= NULL
;
15950 ex_off
.X_add_number
= mips_cpreturn_offset
;
15952 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15953 BFD_RELOC_LO16
, SP
);
15956 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15957 mips_gp_register
, 0);
15959 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15961 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15962 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15965 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15966 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15967 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15969 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15970 mips_gp_register
, reg1
);
15976 ex
.X_op
= O_symbol
;
15977 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15978 ex
.X_op_symbol
= NULL
;
15979 ex
.X_add_number
= 0;
15981 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15982 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15984 macro_build_lui (&ex
, mips_gp_register
);
15985 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15986 mips_gp_register
, BFD_RELOC_LO16
);
15991 mips_assembling_insn
= FALSE
;
15992 demand_empty_rest_of_line ();
15996 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15998 file_mips_check_options ();
16000 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16001 .cplocal is ignored. */
16002 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16008 if (mips_opts
.mips16
)
16010 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16011 ignore_rest_of_line ();
16015 mips_gp_register
= tc_get_register (0);
16016 demand_empty_rest_of_line ();
16019 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16020 offset from $sp. The offset is remembered, and after making a PIC
16021 call $gp is restored from that location. */
16024 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16028 file_mips_check_options ();
16030 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16031 .cprestore is ignored. */
16032 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16038 if (mips_opts
.mips16
)
16040 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16041 ignore_rest_of_line ();
16045 mips_cprestore_offset
= get_absolute_expression ();
16046 mips_cprestore_valid
= 1;
16048 ex
.X_op
= O_constant
;
16049 ex
.X_add_symbol
= NULL
;
16050 ex
.X_op_symbol
= NULL
;
16051 ex
.X_add_number
= mips_cprestore_offset
;
16053 mips_mark_labels ();
16054 mips_assembling_insn
= TRUE
;
16057 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16058 SP
, HAVE_64BIT_ADDRESSES
);
16061 mips_assembling_insn
= FALSE
;
16062 demand_empty_rest_of_line ();
16065 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16066 was given in the preceding .cpsetup, it results in:
16067 ld $gp, offset($sp)
16069 If a register $reg2 was given there, it results in:
16070 daddu $gp, $reg2, $0 */
16073 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16077 file_mips_check_options ();
16079 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16080 We also need NewABI support. */
16081 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16087 if (mips_opts
.mips16
)
16089 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16090 ignore_rest_of_line ();
16094 mips_mark_labels ();
16095 mips_assembling_insn
= TRUE
;
16098 if (mips_cpreturn_register
== -1)
16100 ex
.X_op
= O_constant
;
16101 ex
.X_add_symbol
= NULL
;
16102 ex
.X_op_symbol
= NULL
;
16103 ex
.X_add_number
= mips_cpreturn_offset
;
16105 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16108 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16109 mips_cpreturn_register
, 0);
16112 mips_assembling_insn
= FALSE
;
16113 demand_empty_rest_of_line ();
16116 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16117 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16118 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16119 debug information or MIPS16 TLS. */
16122 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16123 bfd_reloc_code_real_type rtype
)
16130 if (ex
.X_op
!= O_symbol
)
16132 as_bad (_("unsupported use of %s"), dirstr
);
16133 ignore_rest_of_line ();
16136 p
= frag_more (bytes
);
16137 md_number_to_chars (p
, 0, bytes
);
16138 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16139 demand_empty_rest_of_line ();
16140 mips_clear_insn_labels ();
16143 /* Handle .dtprelword. */
16146 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16148 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16151 /* Handle .dtpreldword. */
16154 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16156 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16159 /* Handle .tprelword. */
16162 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16164 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16167 /* Handle .tpreldword. */
16170 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16172 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16175 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16176 code. It sets the offset to use in gp_rel relocations. */
16179 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16181 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16182 We also need NewABI support. */
16183 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16189 mips_gprel_offset
= get_absolute_expression ();
16191 demand_empty_rest_of_line ();
16194 /* Handle the .gpword pseudo-op. This is used when generating PIC
16195 code. It generates a 32 bit GP relative reloc. */
16198 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16200 segment_info_type
*si
;
16201 struct insn_label_list
*l
;
16205 /* When not generating PIC code, this is treated as .word. */
16206 if (mips_pic
!= SVR4_PIC
)
16212 si
= seg_info (now_seg
);
16213 l
= si
->label_list
;
16214 mips_emit_delays ();
16216 mips_align (2, 0, l
);
16219 mips_clear_insn_labels ();
16221 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16223 as_bad (_("unsupported use of .gpword"));
16224 ignore_rest_of_line ();
16228 md_number_to_chars (p
, 0, 4);
16229 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16230 BFD_RELOC_GPREL32
);
16232 demand_empty_rest_of_line ();
16236 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16238 segment_info_type
*si
;
16239 struct insn_label_list
*l
;
16243 /* When not generating PIC code, this is treated as .dword. */
16244 if (mips_pic
!= SVR4_PIC
)
16250 si
= seg_info (now_seg
);
16251 l
= si
->label_list
;
16252 mips_emit_delays ();
16254 mips_align (3, 0, l
);
16257 mips_clear_insn_labels ();
16259 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16261 as_bad (_("unsupported use of .gpdword"));
16262 ignore_rest_of_line ();
16266 md_number_to_chars (p
, 0, 8);
16267 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16268 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16270 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16271 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16272 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16274 demand_empty_rest_of_line ();
16277 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16278 tables. It generates a R_MIPS_EH reloc. */
16281 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16286 mips_emit_delays ();
16289 mips_clear_insn_labels ();
16291 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16293 as_bad (_("unsupported use of .ehword"));
16294 ignore_rest_of_line ();
16298 md_number_to_chars (p
, 0, 4);
16299 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16300 BFD_RELOC_MIPS_EH
);
16302 demand_empty_rest_of_line ();
16305 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16306 tables in SVR4 PIC code. */
16309 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16313 file_mips_check_options ();
16315 /* This is ignored when not generating SVR4 PIC code. */
16316 if (mips_pic
!= SVR4_PIC
)
16322 mips_mark_labels ();
16323 mips_assembling_insn
= TRUE
;
16325 /* Add $gp to the register named as an argument. */
16327 reg
= tc_get_register (0);
16328 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16331 mips_assembling_insn
= FALSE
;
16332 demand_empty_rest_of_line ();
16335 /* Handle the .insn pseudo-op. This marks instruction labels in
16336 mips16/micromips mode. This permits the linker to handle them specially,
16337 such as generating jalx instructions when needed. We also make
16338 them odd for the duration of the assembly, in order to generate the
16339 right sort of code. We will make them even in the adjust_symtab
16340 routine, while leaving them marked. This is convenient for the
16341 debugger and the disassembler. The linker knows to make them odd
16345 s_insn (int ignore ATTRIBUTE_UNUSED
)
16347 mips_mark_labels ();
16349 demand_empty_rest_of_line ();
16352 /* Handle the .nan pseudo-op. */
16355 s_nan (int ignore ATTRIBUTE_UNUSED
)
16357 static const char str_legacy
[] = "legacy";
16358 static const char str_2008
[] = "2008";
16361 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16363 if (i
== sizeof (str_2008
) - 1
16364 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16366 else if (i
== sizeof (str_legacy
) - 1
16367 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16369 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
16372 as_bad (_("`%s' does not support legacy NaN"),
16373 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
16376 as_bad (_("bad .nan directive"));
16378 input_line_pointer
+= i
;
16379 demand_empty_rest_of_line ();
16382 /* Handle a .stab[snd] directive. Ideally these directives would be
16383 implemented in a transparent way, so that removing them would not
16384 have any effect on the generated instructions. However, s_stab
16385 internally changes the section, so in practice we need to decide
16386 now whether the preceding label marks compressed code. We do not
16387 support changing the compression mode of a label after a .stab*
16388 directive, such as in:
16394 so the current mode wins. */
16397 s_mips_stab (int type
)
16399 mips_mark_labels ();
16403 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16406 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16413 name
= input_line_pointer
;
16414 c
= get_symbol_end ();
16415 symbolP
= symbol_find_or_make (name
);
16416 S_SET_WEAK (symbolP
);
16417 *input_line_pointer
= c
;
16419 SKIP_WHITESPACE ();
16421 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16423 if (S_IS_DEFINED (symbolP
))
16425 as_bad (_("ignoring attempt to redefine symbol %s"),
16426 S_GET_NAME (symbolP
));
16427 ignore_rest_of_line ();
16431 if (*input_line_pointer
== ',')
16433 ++input_line_pointer
;
16434 SKIP_WHITESPACE ();
16438 if (exp
.X_op
!= O_symbol
)
16440 as_bad (_("bad .weakext directive"));
16441 ignore_rest_of_line ();
16444 symbol_set_value_expression (symbolP
, &exp
);
16447 demand_empty_rest_of_line ();
16450 /* Parse a register string into a number. Called from the ECOFF code
16451 to parse .frame. The argument is non-zero if this is the frame
16452 register, so that we can record it in mips_frame_reg. */
16455 tc_get_register (int frame
)
16459 SKIP_WHITESPACE ();
16460 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16464 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16465 mips_frame_reg_valid
= 1;
16466 mips_cprestore_valid
= 0;
16472 md_section_align (asection
*seg
, valueT addr
)
16474 int align
= bfd_get_section_alignment (stdoutput
, seg
);
16476 /* We don't need to align ELF sections to the full alignment.
16477 However, Irix 5 may prefer that we align them at least to a 16
16478 byte boundary. We don't bother to align the sections if we
16479 are targeted for an embedded system. */
16480 if (strncmp (TARGET_OS
, "elf", 3) == 0)
16485 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
16488 /* Utility routine, called from above as well. If called while the
16489 input file is still being read, it's only an approximation. (For
16490 example, a symbol may later become defined which appeared to be
16491 undefined earlier.) */
16494 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
16499 if (g_switch_value
> 0)
16501 const char *symname
;
16504 /* Find out whether this symbol can be referenced off the $gp
16505 register. It can be if it is smaller than the -G size or if
16506 it is in the .sdata or .sbss section. Certain symbols can
16507 not be referenced off the $gp, although it appears as though
16509 symname
= S_GET_NAME (sym
);
16510 if (symname
!= (const char *) NULL
16511 && (strcmp (symname
, "eprol") == 0
16512 || strcmp (symname
, "etext") == 0
16513 || strcmp (symname
, "_gp") == 0
16514 || strcmp (symname
, "edata") == 0
16515 || strcmp (symname
, "_fbss") == 0
16516 || strcmp (symname
, "_fdata") == 0
16517 || strcmp (symname
, "_ftext") == 0
16518 || strcmp (symname
, "end") == 0
16519 || strcmp (symname
, "_gp_disp") == 0))
16521 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
16523 #ifndef NO_ECOFF_DEBUGGING
16524 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
16525 && (symbol_get_obj (sym
)->ecoff_extern_size
16526 <= g_switch_value
))
16528 /* We must defer this decision until after the whole
16529 file has been read, since there might be a .extern
16530 after the first use of this symbol. */
16531 || (before_relaxing
16532 #ifndef NO_ECOFF_DEBUGGING
16533 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
16535 && S_GET_VALUE (sym
) == 0)
16536 || (S_GET_VALUE (sym
) != 0
16537 && S_GET_VALUE (sym
) <= g_switch_value
)))
16541 const char *segname
;
16543 segname
= segment_name (S_GET_SEGMENT (sym
));
16544 gas_assert (strcmp (segname
, ".lit8") != 0
16545 && strcmp (segname
, ".lit4") != 0);
16546 change
= (strcmp (segname
, ".sdata") != 0
16547 && strcmp (segname
, ".sbss") != 0
16548 && strncmp (segname
, ".sdata.", 7) != 0
16549 && strncmp (segname
, ".sbss.", 6) != 0
16550 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16551 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16556 /* We are not optimizing for the $gp register. */
16561 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16564 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16568 /* Handle the case of a symbol equated to another symbol. */
16569 while (symbol_equated_reloc_p (sym
))
16573 /* It's possible to get a loop here in a badly written program. */
16574 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16580 if (symbol_section_p (sym
))
16583 symsec
= S_GET_SEGMENT (sym
);
16585 /* This must duplicate the test in adjust_reloc_syms. */
16586 return (!bfd_is_und_section (symsec
)
16587 && !bfd_is_abs_section (symsec
)
16588 && !bfd_is_com_section (symsec
)
16589 && !s_is_linkonce (sym
, segtype
)
16590 /* A global or weak symbol is treated as external. */
16591 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16595 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16596 extended opcode. SEC is the section the frag is in. */
16599 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16602 const struct mips_int_operand
*operand
;
16607 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16609 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16612 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16613 operand
= mips16_immed_operand (type
, FALSE
);
16615 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16616 val
= S_GET_VALUE (fragp
->fr_symbol
);
16617 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16619 if (operand
->root
.type
== OP_PCREL
)
16621 const struct mips_pcrel_operand
*pcrel_op
;
16625 /* We won't have the section when we are called from
16626 mips_relax_frag. However, we will always have been called
16627 from md_estimate_size_before_relax first. If this is a
16628 branch to a different section, we mark it as such. If SEC is
16629 NULL, and the frag is not marked, then it must be a branch to
16630 the same section. */
16631 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16634 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16639 /* Must have been called from md_estimate_size_before_relax. */
16642 fragp
->fr_subtype
=
16643 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16645 /* FIXME: We should support this, and let the linker
16646 catch branches and loads that are out of range. */
16647 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16648 _("unsupported PC relative reference to different section"));
16652 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16653 /* Assume non-extended on the first relaxation pass.
16654 The address we have calculated will be bogus if this is
16655 a forward branch to another frag, as the forward frag
16656 will have fr_address == 0. */
16660 /* In this case, we know for sure that the symbol fragment is in
16661 the same section. If the relax_marker of the symbol fragment
16662 differs from the relax_marker of this fragment, we have not
16663 yet adjusted the symbol fragment fr_address. We want to add
16664 in STRETCH in order to get a better estimate of the address.
16665 This particularly matters because of the shift bits. */
16667 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16671 /* Adjust stretch for any alignment frag. Note that if have
16672 been expanding the earlier code, the symbol may be
16673 defined in what appears to be an earlier frag. FIXME:
16674 This doesn't handle the fr_subtype field, which specifies
16675 a maximum number of bytes to skip when doing an
16677 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16679 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16682 stretch
= - ((- stretch
)
16683 & ~ ((1 << (int) f
->fr_offset
) - 1));
16685 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16694 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16696 /* The base address rules are complicated. The base address of
16697 a branch is the following instruction. The base address of a
16698 PC relative load or add is the instruction itself, but if it
16699 is in a delay slot (in which case it can not be extended) use
16700 the address of the instruction whose delay slot it is in. */
16701 if (pcrel_op
->include_isa_bit
)
16705 /* If we are currently assuming that this frag should be
16706 extended, then, the current address is two bytes
16708 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16711 /* Ignore the low bit in the target, since it will be set
16712 for a text label. */
16715 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16717 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16720 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16722 /* If any of the shifted bits are set, we must use an extended
16723 opcode. If the address depends on the size of this
16724 instruction, this can lead to a loop, so we arrange to always
16725 use an extended opcode. We only check this when we are in
16726 the main relaxation loop, when SEC is NULL. */
16727 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16729 fragp
->fr_subtype
=
16730 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16734 /* If we are about to mark a frag as extended because the value
16735 is precisely the next value above maxtiny, then there is a
16736 chance of an infinite loop as in the following code:
16741 In this case when the la is extended, foo is 0x3fc bytes
16742 away, so the la can be shrunk, but then foo is 0x400 away, so
16743 the la must be extended. To avoid this loop, we mark the
16744 frag as extended if it was small, and is about to become
16745 extended with the next value above maxtiny. */
16746 maxtiny
= mips_int_operand_max (operand
);
16747 if (val
== maxtiny
+ (1 << operand
->shift
)
16748 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16751 fragp
->fr_subtype
=
16752 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16756 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16757 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16759 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16762 /* Compute the length of a branch sequence, and adjust the
16763 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16764 worst-case length is computed, with UPDATE being used to indicate
16765 whether an unconditional (-1), branch-likely (+1) or regular (0)
16766 branch is to be computed. */
16768 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16770 bfd_boolean toofar
;
16774 && S_IS_DEFINED (fragp
->fr_symbol
)
16775 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16780 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16782 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16786 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16789 /* If the symbol is not defined or it's in a different segment,
16790 assume the user knows what's going on and emit a short
16796 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16798 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16799 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16800 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16801 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16807 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16810 if (mips_pic
!= NO_PIC
)
16812 /* Additional space for PIC loading of target address. */
16814 if (mips_opts
.isa
== ISA_MIPS1
)
16815 /* Additional space for $at-stabilizing nop. */
16819 /* If branch is conditional. */
16820 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16827 /* Compute the length of a branch sequence, and adjust the
16828 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16829 worst-case length is computed, with UPDATE being used to indicate
16830 whether an unconditional (-1), or regular (0) branch is to be
16834 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16836 bfd_boolean toofar
;
16840 && S_IS_DEFINED (fragp
->fr_symbol
)
16841 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16846 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16847 /* Ignore the low bit in the target, since it will be set
16848 for a text label. */
16849 if ((val
& 1) != 0)
16852 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16856 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16859 /* If the symbol is not defined or it's in a different segment,
16860 assume the user knows what's going on and emit a short
16866 if (fragp
&& update
16867 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16868 fragp
->fr_subtype
= (toofar
16869 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16870 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16875 bfd_boolean compact_known
= fragp
!= NULL
;
16876 bfd_boolean compact
= FALSE
;
16877 bfd_boolean uncond
;
16880 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16882 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16884 uncond
= update
< 0;
16886 /* If label is out of range, we turn branch <br>:
16888 <br> label # 4 bytes
16894 nop # 2 bytes if compact && !PIC
16897 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16900 /* If assembling PIC code, we further turn:
16906 lw/ld at, %got(label)(gp) # 4 bytes
16907 d/addiu at, %lo(label) # 4 bytes
16910 if (mips_pic
!= NO_PIC
)
16913 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16915 <brneg> 0f # 4 bytes
16916 nop # 2 bytes if !compact
16919 length
+= (compact_known
&& compact
) ? 4 : 6;
16925 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16926 bit accordingly. */
16929 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16931 bfd_boolean toofar
;
16934 && S_IS_DEFINED (fragp
->fr_symbol
)
16935 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16941 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16942 /* Ignore the low bit in the target, since it will be set
16943 for a text label. */
16944 if ((val
& 1) != 0)
16947 /* Assume this is a 2-byte branch. */
16948 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16950 /* We try to avoid the infinite loop by not adding 2 more bytes for
16955 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16957 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16958 else if (type
== 'E')
16959 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16964 /* If the symbol is not defined or it's in a different segment,
16965 we emit a normal 32-bit branch. */
16968 if (fragp
&& update
16969 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16971 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16972 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16980 /* Estimate the size of a frag before relaxing. Unless this is the
16981 mips16, we are not really relaxing here, and the final size is
16982 encoded in the subtype information. For the mips16, we have to
16983 decide whether we are using an extended opcode or not. */
16986 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16990 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16993 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16995 return fragp
->fr_var
;
16998 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16999 /* We don't want to modify the EXTENDED bit here; it might get us
17000 into infinite loops. We change it only in mips_relax_frag(). */
17001 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17003 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17007 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17008 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17009 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17010 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17011 fragp
->fr_var
= length
;
17016 if (mips_pic
== NO_PIC
)
17017 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17018 else if (mips_pic
== SVR4_PIC
)
17019 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17020 else if (mips_pic
== VXWORKS_PIC
)
17021 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17028 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17029 return -RELAX_FIRST (fragp
->fr_subtype
);
17032 return -RELAX_SECOND (fragp
->fr_subtype
);
17035 /* This is called to see whether a reloc against a defined symbol
17036 should be converted into a reloc against a section. */
17039 mips_fix_adjustable (fixS
*fixp
)
17041 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17042 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17045 if (fixp
->fx_addsy
== NULL
)
17048 /* If symbol SYM is in a mergeable section, relocations of the form
17049 SYM + 0 can usually be made section-relative. The mergeable data
17050 is then identified by the section offset rather than by the symbol.
17052 However, if we're generating REL LO16 relocations, the offset is split
17053 between the LO16 and parterning high part relocation. The linker will
17054 need to recalculate the complete offset in order to correctly identify
17057 The linker has traditionally not looked for the parterning high part
17058 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17059 placed anywhere. Rather than break backwards compatibility by changing
17060 this, it seems better not to force the issue, and instead keep the
17061 original symbol. This will work with either linker behavior. */
17062 if ((lo16_reloc_p (fixp
->fx_r_type
)
17063 || reloc_needs_lo_p (fixp
->fx_r_type
))
17064 && HAVE_IN_PLACE_ADDENDS
17065 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17068 /* There is no place to store an in-place offset for JALR relocations.
17069 Likewise an in-range offset of limited PC-relative relocations may
17070 overflow the in-place relocatable field if recalculated against the
17071 start address of the symbol's containing section.
17073 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17074 section relative to allow linker relaxations to be performed later on. */
17075 if ((HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (mips_opts
.isa
))
17076 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17077 || jalr_reloc_p (fixp
->fx_r_type
)))
17080 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17081 to a floating-point stub. The same is true for non-R_MIPS16_26
17082 relocations against MIPS16 functions; in this case, the stub becomes
17083 the function's canonical address.
17085 Floating-point stubs are stored in unique .mips16.call.* or
17086 .mips16.fn.* sections. If a stub T for function F is in section S,
17087 the first relocation in section S must be against F; this is how the
17088 linker determines the target function. All relocations that might
17089 resolve to T must also be against F. We therefore have the following
17090 restrictions, which are given in an intentionally-redundant way:
17092 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17095 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17096 if that stub might be used.
17098 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17101 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17102 that stub might be used.
17104 There is a further restriction:
17106 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17107 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17108 targets with in-place addends; the relocation field cannot
17109 encode the low bit.
17111 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17112 against a MIPS16 symbol. We deal with (5) by by not reducing any
17113 such relocations on REL targets.
17115 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17116 relocation against some symbol R, no relocation against R may be
17117 reduced. (Note that this deals with (2) as well as (1) because
17118 relocations against global symbols will never be reduced on ELF
17119 targets.) This approach is a little simpler than trying to detect
17120 stub sections, and gives the "all or nothing" per-symbol consistency
17121 that we have for MIPS16 symbols. */
17122 if (fixp
->fx_subsy
== NULL
17123 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17124 || *symbol_get_tc (fixp
->fx_addsy
)
17125 || (HAVE_IN_PLACE_ADDENDS
17126 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17127 && jmp_reloc_p (fixp
->fx_r_type
))))
17133 /* Translate internal representation of relocation info to BFD target
17137 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17139 static arelent
*retval
[4];
17141 bfd_reloc_code_real_type code
;
17143 memset (retval
, 0, sizeof(retval
));
17144 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17145 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17146 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17147 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17149 if (fixp
->fx_pcrel
)
17151 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17152 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17153 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17154 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17155 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17156 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17157 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17158 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17159 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17160 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17161 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17163 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17164 Relocations want only the symbol offset. */
17165 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17168 reloc
->addend
= fixp
->fx_addnumber
;
17170 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17171 entry to be used in the relocation's section offset. */
17172 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17174 reloc
->address
= reloc
->addend
;
17178 code
= fixp
->fx_r_type
;
17180 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17181 if (reloc
->howto
== NULL
)
17183 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17184 _("cannot represent %s relocation in this object file"
17186 bfd_get_reloc_code_name (code
));
17193 /* Relax a machine dependent frag. This returns the amount by which
17194 the current size of the frag should change. */
17197 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17199 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17201 offsetT old_var
= fragp
->fr_var
;
17203 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17205 return fragp
->fr_var
- old_var
;
17208 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17210 offsetT old_var
= fragp
->fr_var
;
17211 offsetT new_var
= 4;
17213 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17214 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17215 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17216 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17217 fragp
->fr_var
= new_var
;
17219 return new_var
- old_var
;
17222 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17225 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17227 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17229 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17234 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17236 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17243 /* Convert a machine dependent frag. */
17246 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17248 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17251 unsigned long insn
;
17255 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17256 insn
= read_insn (buf
);
17258 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17260 /* We generate a fixup instead of applying it right now
17261 because, if there are linker relaxations, we're going to
17262 need the relocations. */
17263 exp
.X_op
= O_symbol
;
17264 exp
.X_add_symbol
= fragp
->fr_symbol
;
17265 exp
.X_add_number
= fragp
->fr_offset
;
17267 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17268 BFD_RELOC_16_PCREL_S2
);
17269 fixp
->fx_file
= fragp
->fr_file
;
17270 fixp
->fx_line
= fragp
->fr_line
;
17272 buf
= write_insn (buf
, insn
);
17278 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17279 _("relaxed out-of-range branch into a jump"));
17281 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17284 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17286 /* Reverse the branch. */
17287 switch ((insn
>> 28) & 0xf)
17290 if ((insn
& 0xff000000) == 0x47000000
17291 || (insn
& 0xff600000) == 0x45600000)
17293 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17294 reversed by tweaking bit 23. */
17295 insn
^= 0x00800000;
17299 /* bc[0-3][tf]l? instructions can have the condition
17300 reversed by tweaking a single TF bit, and their
17301 opcodes all have 0x4???????. */
17302 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
17303 insn
^= 0x00010000;
17308 /* bltz 0x04000000 bgez 0x04010000
17309 bltzal 0x04100000 bgezal 0x04110000 */
17310 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17311 insn
^= 0x00010000;
17315 /* beq 0x10000000 bne 0x14000000
17316 blez 0x18000000 bgtz 0x1c000000 */
17317 insn
^= 0x04000000;
17325 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17327 /* Clear the and-link bit. */
17328 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17330 /* bltzal 0x04100000 bgezal 0x04110000
17331 bltzall 0x04120000 bgezall 0x04130000 */
17332 insn
&= ~0x00100000;
17335 /* Branch over the branch (if the branch was likely) or the
17336 full jump (not likely case). Compute the offset from the
17337 current instruction to branch to. */
17338 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17342 /* How many bytes in instructions we've already emitted? */
17343 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17344 /* How many bytes in instructions from here to the end? */
17345 i
= fragp
->fr_var
- i
;
17347 /* Convert to instruction count. */
17349 /* Branch counts from the next instruction. */
17352 /* Branch over the jump. */
17353 buf
= write_insn (buf
, insn
);
17356 buf
= write_insn (buf
, 0);
17358 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17360 /* beql $0, $0, 2f */
17362 /* Compute the PC offset from the current instruction to
17363 the end of the variable frag. */
17364 /* How many bytes in instructions we've already emitted? */
17365 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17366 /* How many bytes in instructions from here to the end? */
17367 i
= fragp
->fr_var
- i
;
17368 /* Convert to instruction count. */
17370 /* Don't decrement i, because we want to branch over the
17374 buf
= write_insn (buf
, insn
);
17375 buf
= write_insn (buf
, 0);
17379 if (mips_pic
== NO_PIC
)
17382 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17383 ? 0x0c000000 : 0x08000000);
17384 exp
.X_op
= O_symbol
;
17385 exp
.X_add_symbol
= fragp
->fr_symbol
;
17386 exp
.X_add_number
= fragp
->fr_offset
;
17388 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17389 FALSE
, BFD_RELOC_MIPS_JMP
);
17390 fixp
->fx_file
= fragp
->fr_file
;
17391 fixp
->fx_line
= fragp
->fr_line
;
17393 buf
= write_insn (buf
, insn
);
17397 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17399 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17400 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17401 insn
|= at
<< OP_SH_RT
;
17402 exp
.X_op
= O_symbol
;
17403 exp
.X_add_symbol
= fragp
->fr_symbol
;
17404 exp
.X_add_number
= fragp
->fr_offset
;
17406 if (fragp
->fr_offset
)
17408 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17409 exp
.X_add_number
= 0;
17412 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17413 FALSE
, BFD_RELOC_MIPS_GOT16
);
17414 fixp
->fx_file
= fragp
->fr_file
;
17415 fixp
->fx_line
= fragp
->fr_line
;
17417 buf
= write_insn (buf
, insn
);
17419 if (mips_opts
.isa
== ISA_MIPS1
)
17421 buf
= write_insn (buf
, 0);
17423 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17424 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17425 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17427 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17428 FALSE
, BFD_RELOC_LO16
);
17429 fixp
->fx_file
= fragp
->fr_file
;
17430 fixp
->fx_line
= fragp
->fr_line
;
17432 buf
= write_insn (buf
, insn
);
17435 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17439 insn
|= at
<< OP_SH_RS
;
17441 buf
= write_insn (buf
, insn
);
17445 fragp
->fr_fix
+= fragp
->fr_var
;
17446 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17450 /* Relax microMIPS branches. */
17451 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17453 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17454 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17455 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17456 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17457 bfd_boolean short_ds
;
17458 unsigned long insn
;
17462 exp
.X_op
= O_symbol
;
17463 exp
.X_add_symbol
= fragp
->fr_symbol
;
17464 exp
.X_add_number
= fragp
->fr_offset
;
17466 fragp
->fr_fix
+= fragp
->fr_var
;
17468 /* Handle 16-bit branches that fit or are forced to fit. */
17469 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17471 /* We generate a fixup instead of applying it right now,
17472 because if there is linker relaxation, we're going to
17473 need the relocations. */
17475 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
17476 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
17477 else if (type
== 'E')
17478 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
17479 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
17483 fixp
->fx_file
= fragp
->fr_file
;
17484 fixp
->fx_line
= fragp
->fr_line
;
17486 /* These relocations can have an addend that won't fit in
17488 fixp
->fx_no_overflow
= 1;
17493 /* Handle 32-bit branches that fit or are forced to fit. */
17494 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17495 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17497 /* We generate a fixup instead of applying it right now,
17498 because if there is linker relaxation, we're going to
17499 need the relocations. */
17500 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17501 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17502 fixp
->fx_file
= fragp
->fr_file
;
17503 fixp
->fx_line
= fragp
->fr_line
;
17509 /* Relax 16-bit branches to 32-bit branches. */
17512 insn
= read_compressed_insn (buf
, 2);
17514 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
17515 insn
= 0x94000000; /* beq */
17516 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17518 unsigned long regno
;
17520 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
17521 regno
= micromips_to_32_reg_d_map
[regno
];
17522 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
17523 insn
|= regno
<< MICROMIPSOP_SH_RS
;
17528 /* Nothing else to do, just write it out. */
17529 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
17530 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17532 buf
= write_compressed_insn (buf
, insn
, 4);
17533 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17538 insn
= read_compressed_insn (buf
, 4);
17540 /* Relax 32-bit branches to a sequence of instructions. */
17541 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17542 _("relaxed out-of-range branch into a jump"));
17544 /* Set the short-delay-slot bit. */
17545 short_ds
= al
&& (insn
& 0x02000000) != 0;
17547 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
17551 /* Reverse the branch. */
17552 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
17553 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
17554 insn
^= 0x20000000;
17555 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
17556 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
17557 || (insn
& 0xffe00000) == 0x40800000 /* blez */
17558 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17559 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17560 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17561 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17562 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17563 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17564 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17565 insn
^= 0x00400000;
17566 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17567 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17568 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17569 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17570 insn
^= 0x00200000;
17571 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
17573 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
17575 insn
^= 0x00800000;
17581 /* Clear the and-link and short-delay-slot bits. */
17582 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17584 /* bltzal 0x40200000 bgezal 0x40600000 */
17585 /* bltzals 0x42200000 bgezals 0x42600000 */
17586 insn
&= ~0x02200000;
17589 /* Make a label at the end for use with the branch. */
17590 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17591 micromips_label_inc ();
17592 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17595 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17596 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17597 fixp
->fx_file
= fragp
->fr_file
;
17598 fixp
->fx_line
= fragp
->fr_line
;
17600 /* Branch over the jump. */
17601 buf
= write_compressed_insn (buf
, insn
, 4);
17604 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17607 if (mips_pic
== NO_PIC
)
17609 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17611 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17612 insn
= al
? jal
: 0xd4000000;
17614 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17615 BFD_RELOC_MICROMIPS_JMP
);
17616 fixp
->fx_file
= fragp
->fr_file
;
17617 fixp
->fx_line
= fragp
->fr_line
;
17619 buf
= write_compressed_insn (buf
, insn
, 4);
17622 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17626 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17627 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17628 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17630 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17631 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17632 insn
|= at
<< MICROMIPSOP_SH_RT
;
17634 if (exp
.X_add_number
)
17636 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17637 exp
.X_add_number
= 0;
17640 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17641 BFD_RELOC_MICROMIPS_GOT16
);
17642 fixp
->fx_file
= fragp
->fr_file
;
17643 fixp
->fx_line
= fragp
->fr_line
;
17645 buf
= write_compressed_insn (buf
, insn
, 4);
17647 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17648 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17649 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17651 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17652 BFD_RELOC_MICROMIPS_LO16
);
17653 fixp
->fx_file
= fragp
->fr_file
;
17654 fixp
->fx_line
= fragp
->fr_line
;
17656 buf
= write_compressed_insn (buf
, insn
, 4);
17658 /* jr/jrc/jalr/jalrs $at */
17659 insn
= al
? jalr
: jr
;
17660 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17662 buf
= write_compressed_insn (buf
, insn
, 2);
17665 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17669 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17672 const struct mips_int_operand
*operand
;
17675 unsigned int user_length
, length
;
17676 unsigned long insn
;
17679 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17680 operand
= mips16_immed_operand (type
, FALSE
);
17682 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17683 val
= resolve_symbol_value (fragp
->fr_symbol
);
17684 if (operand
->root
.type
== OP_PCREL
)
17686 const struct mips_pcrel_operand
*pcrel_op
;
17689 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17690 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17692 /* The rules for the base address of a PC relative reloc are
17693 complicated; see mips16_extended_frag. */
17694 if (pcrel_op
->include_isa_bit
)
17699 /* Ignore the low bit in the target, since it will be
17700 set for a text label. */
17703 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17705 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17708 addr
&= -(1 << pcrel_op
->align_log2
);
17711 /* Make sure the section winds up with the alignment we have
17713 if (operand
->shift
> 0)
17714 record_alignment (asec
, operand
->shift
);
17718 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17719 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17720 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17721 _("extended instruction in delay slot"));
17723 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17725 insn
= read_compressed_insn (buf
, 2);
17727 insn
|= MIPS16_EXTEND
;
17729 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17731 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17736 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17737 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17739 length
= (ext
? 4 : 2);
17740 gas_assert (mips16_opcode_length (insn
) == length
);
17741 write_compressed_insn (buf
, insn
, length
);
17742 fragp
->fr_fix
+= length
;
17746 relax_substateT subtype
= fragp
->fr_subtype
;
17747 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17748 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17752 first
= RELAX_FIRST (subtype
);
17753 second
= RELAX_SECOND (subtype
);
17754 fixp
= (fixS
*) fragp
->fr_opcode
;
17756 /* If the delay slot chosen does not match the size of the instruction,
17757 then emit a warning. */
17758 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17759 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17764 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17765 | RELAX_DELAY_SLOT_SIZE_FIRST
17766 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17767 msg
= macro_warning (s
);
17769 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17773 /* Possibly emit a warning if we've chosen the longer option. */
17774 if (use_second
== second_longer
)
17780 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17781 msg
= macro_warning (s
);
17783 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17787 /* Go through all the fixups for the first sequence. Disable them
17788 (by marking them as done) if we're going to use the second
17789 sequence instead. */
17791 && fixp
->fx_frag
== fragp
17792 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17794 if (subtype
& RELAX_USE_SECOND
)
17796 fixp
= fixp
->fx_next
;
17799 /* Go through the fixups for the second sequence. Disable them if
17800 we're going to use the first sequence, otherwise adjust their
17801 addresses to account for the relaxation. */
17802 while (fixp
&& fixp
->fx_frag
== fragp
)
17804 if (subtype
& RELAX_USE_SECOND
)
17805 fixp
->fx_where
-= first
;
17808 fixp
= fixp
->fx_next
;
17811 /* Now modify the frag contents. */
17812 if (subtype
& RELAX_USE_SECOND
)
17816 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17817 memmove (start
, start
+ first
, second
);
17818 fragp
->fr_fix
-= first
;
17821 fragp
->fr_fix
-= second
;
17825 /* This function is called after the relocs have been generated.
17826 We've been storing mips16 text labels as odd. Here we convert them
17827 back to even for the convenience of the debugger. */
17830 mips_frob_file_after_relocs (void)
17833 unsigned int count
, i
;
17835 syms
= bfd_get_outsymbols (stdoutput
);
17836 count
= bfd_get_symcount (stdoutput
);
17837 for (i
= 0; i
< count
; i
++, syms
++)
17838 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17839 && ((*syms
)->value
& 1) != 0)
17841 (*syms
)->value
&= ~1;
17842 /* If the symbol has an odd size, it was probably computed
17843 incorrectly, so adjust that as well. */
17844 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17845 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17849 /* This function is called whenever a label is defined, including fake
17850 labels instantiated off the dot special symbol. It is used when
17851 handling branch delays; if a branch has a label, we assume we cannot
17852 move it. This also bumps the value of the symbol by 1 in compressed
17856 mips_record_label (symbolS
*sym
)
17858 segment_info_type
*si
= seg_info (now_seg
);
17859 struct insn_label_list
*l
;
17861 if (free_insn_labels
== NULL
)
17862 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17865 l
= free_insn_labels
;
17866 free_insn_labels
= l
->next
;
17870 l
->next
= si
->label_list
;
17871 si
->label_list
= l
;
17874 /* This function is called as tc_frob_label() whenever a label is defined
17875 and adds a DWARF-2 record we only want for true labels. */
17878 mips_define_label (symbolS
*sym
)
17880 mips_record_label (sym
);
17881 dwarf2_emit_label (sym
);
17884 /* This function is called by tc_new_dot_label whenever a new dot symbol
17888 mips_add_dot_label (symbolS
*sym
)
17890 mips_record_label (sym
);
17891 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17892 mips_compressed_mark_label (sym
);
17895 /* Converting ASE flags from internal to .MIPS.abiflags values. */
17896 static unsigned int
17897 mips_convert_ase_flags (int ase
)
17899 unsigned int ext_ases
= 0;
17902 ext_ases
|= AFL_ASE_DSP
;
17903 if (ase
& ASE_DSPR2
)
17904 ext_ases
|= AFL_ASE_DSPR2
;
17906 ext_ases
|= AFL_ASE_EVA
;
17908 ext_ases
|= AFL_ASE_MCU
;
17909 if (ase
& ASE_MDMX
)
17910 ext_ases
|= AFL_ASE_MDMX
;
17911 if (ase
& ASE_MIPS3D
)
17912 ext_ases
|= AFL_ASE_MIPS3D
;
17914 ext_ases
|= AFL_ASE_MT
;
17915 if (ase
& ASE_SMARTMIPS
)
17916 ext_ases
|= AFL_ASE_SMARTMIPS
;
17917 if (ase
& ASE_VIRT
)
17918 ext_ases
|= AFL_ASE_VIRT
;
17920 ext_ases
|= AFL_ASE_MSA
;
17922 ext_ases
|= AFL_ASE_XPA
;
17926 /* Some special processing for a MIPS ELF file. */
17929 mips_elf_final_processing (void)
17932 Elf_Internal_ABIFlags_v0 flags
;
17936 switch (file_mips_opts
.isa
)
17939 flags
.isa_level
= 1;
17942 flags
.isa_level
= 2;
17945 flags
.isa_level
= 3;
17948 flags
.isa_level
= 4;
17951 flags
.isa_level
= 5;
17954 flags
.isa_level
= 32;
17958 flags
.isa_level
= 32;
17962 flags
.isa_level
= 32;
17966 flags
.isa_level
= 32;
17970 flags
.isa_level
= 64;
17974 flags
.isa_level
= 64;
17978 flags
.isa_level
= 64;
17982 flags
.isa_level
= 64;
17987 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
17988 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
17989 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
17990 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
17992 flags
.cpr2_size
= AFL_REG_NONE
;
17993 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
17994 Tag_GNU_MIPS_ABI_FP
);
17995 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
17996 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
17997 if (file_ase_mips16
)
17998 flags
.ases
|= AFL_ASE_MIPS16
;
17999 if (file_ase_micromips
)
18000 flags
.ases
|= AFL_ASE_MICROMIPS
;
18002 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18003 || file_mips_opts
.fp
== 64)
18004 && file_mips_opts
.oddspreg
)
18005 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18008 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18009 ((Elf_External_ABIFlags_v0
*)
18012 /* Write out the register information. */
18013 if (mips_abi
!= N64_ABI
)
18017 s
.ri_gprmask
= mips_gprmask
;
18018 s
.ri_cprmask
[0] = mips_cprmask
[0];
18019 s
.ri_cprmask
[1] = mips_cprmask
[1];
18020 s
.ri_cprmask
[2] = mips_cprmask
[2];
18021 s
.ri_cprmask
[3] = mips_cprmask
[3];
18022 /* The gp_value field is set by the MIPS ELF backend. */
18024 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18025 ((Elf32_External_RegInfo
*)
18026 mips_regmask_frag
));
18030 Elf64_Internal_RegInfo s
;
18032 s
.ri_gprmask
= mips_gprmask
;
18034 s
.ri_cprmask
[0] = mips_cprmask
[0];
18035 s
.ri_cprmask
[1] = mips_cprmask
[1];
18036 s
.ri_cprmask
[2] = mips_cprmask
[2];
18037 s
.ri_cprmask
[3] = mips_cprmask
[3];
18038 /* The gp_value field is set by the MIPS ELF backend. */
18040 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18041 ((Elf64_External_RegInfo
*)
18042 mips_regmask_frag
));
18045 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18046 sort of BFD interface for this. */
18047 if (mips_any_noreorder
)
18048 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18049 if (mips_pic
!= NO_PIC
)
18051 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18052 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18055 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18057 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18058 defined at present; this might need to change in future. */
18059 if (file_ase_mips16
)
18060 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18061 if (file_ase_micromips
)
18062 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18063 if (file_mips_opts
.ase
& ASE_MDMX
)
18064 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18066 /* Set the MIPS ELF ABI flags. */
18067 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18068 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18069 else if (mips_abi
== O64_ABI
)
18070 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18071 else if (mips_abi
== EABI_ABI
)
18073 if (file_mips_opts
.gp
== 64)
18074 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18076 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18078 else if (mips_abi
== N32_ABI
)
18079 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18081 /* Nothing to do for N64_ABI. */
18083 if (mips_32bitmode
)
18084 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18086 if (mips_nan2008
== 1)
18087 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
18089 /* 32 bit code with 64 bit FP registers. */
18090 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18091 Tag_GNU_MIPS_ABI_FP
);
18092 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
18093 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
18096 typedef struct proc
{
18098 symbolS
*func_end_sym
;
18099 unsigned long reg_mask
;
18100 unsigned long reg_offset
;
18101 unsigned long fpreg_mask
;
18102 unsigned long fpreg_offset
;
18103 unsigned long frame_offset
;
18104 unsigned long frame_reg
;
18105 unsigned long pc_reg
;
18108 static procS cur_proc
;
18109 static procS
*cur_proc_ptr
;
18110 static int numprocs
;
18112 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18113 as "2", and a normal nop as "0". */
18115 #define NOP_OPCODE_MIPS 0
18116 #define NOP_OPCODE_MIPS16 1
18117 #define NOP_OPCODE_MICROMIPS 2
18120 mips_nop_opcode (void)
18122 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18123 return NOP_OPCODE_MICROMIPS
;
18124 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18125 return NOP_OPCODE_MIPS16
;
18127 return NOP_OPCODE_MIPS
;
18130 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18131 32-bit microMIPS NOPs here (if applicable). */
18134 mips_handle_align (fragS
*fragp
)
18138 int bytes
, size
, excess
;
18141 if (fragp
->fr_type
!= rs_align_code
)
18144 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18146 switch (nop_opcode
)
18148 case NOP_OPCODE_MICROMIPS
:
18149 opcode
= micromips_nop32_insn
.insn_opcode
;
18152 case NOP_OPCODE_MIPS16
:
18153 opcode
= mips16_nop_insn
.insn_opcode
;
18156 case NOP_OPCODE_MIPS
:
18158 opcode
= nop_insn
.insn_opcode
;
18163 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18164 excess
= bytes
% size
;
18166 /* Handle the leading part if we're not inserting a whole number of
18167 instructions, and make it the end of the fixed part of the frag.
18168 Try to fit in a short microMIPS NOP if applicable and possible,
18169 and use zeroes otherwise. */
18170 gas_assert (excess
< 4);
18171 fragp
->fr_fix
+= excess
;
18176 /* Fall through. */
18178 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18180 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18184 /* Fall through. */
18187 /* Fall through. */
18192 md_number_to_chars (p
, opcode
, size
);
18193 fragp
->fr_var
= size
;
18202 if (*input_line_pointer
== '-')
18204 ++input_line_pointer
;
18207 if (!ISDIGIT (*input_line_pointer
))
18208 as_bad (_("expected simple number"));
18209 if (input_line_pointer
[0] == '0')
18211 if (input_line_pointer
[1] == 'x')
18213 input_line_pointer
+= 2;
18214 while (ISXDIGIT (*input_line_pointer
))
18217 val
|= hex_value (*input_line_pointer
++);
18219 return negative
? -val
: val
;
18223 ++input_line_pointer
;
18224 while (ISDIGIT (*input_line_pointer
))
18227 val
|= *input_line_pointer
++ - '0';
18229 return negative
? -val
: val
;
18232 if (!ISDIGIT (*input_line_pointer
))
18234 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18235 *input_line_pointer
, *input_line_pointer
);
18236 as_warn (_("invalid number"));
18239 while (ISDIGIT (*input_line_pointer
))
18242 val
+= *input_line_pointer
++ - '0';
18244 return negative
? -val
: val
;
18247 /* The .file directive; just like the usual .file directive, but there
18248 is an initial number which is the ECOFF file index. In the non-ECOFF
18249 case .file implies DWARF-2. */
18252 s_mips_file (int x ATTRIBUTE_UNUSED
)
18254 static int first_file_directive
= 0;
18256 if (ECOFF_DEBUGGING
)
18265 filename
= dwarf2_directive_file (0);
18267 /* Versions of GCC up to 3.1 start files with a ".file"
18268 directive even for stabs output. Make sure that this
18269 ".file" is handled. Note that you need a version of GCC
18270 after 3.1 in order to support DWARF-2 on MIPS. */
18271 if (filename
!= NULL
&& ! first_file_directive
)
18273 (void) new_logical_line (filename
, -1);
18274 s_app_file_string (filename
, 0);
18276 first_file_directive
= 1;
18280 /* The .loc directive, implying DWARF-2. */
18283 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18285 if (!ECOFF_DEBUGGING
)
18286 dwarf2_directive_loc (0);
18289 /* The .end directive. */
18292 s_mips_end (int x ATTRIBUTE_UNUSED
)
18296 /* Following functions need their own .frame and .cprestore directives. */
18297 mips_frame_reg_valid
= 0;
18298 mips_cprestore_valid
= 0;
18300 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18303 demand_empty_rest_of_line ();
18308 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18309 as_warn (_(".end not in text section"));
18313 as_warn (_(".end directive without a preceding .ent directive"));
18314 demand_empty_rest_of_line ();
18320 gas_assert (S_GET_NAME (p
));
18321 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18322 as_warn (_(".end symbol does not match .ent symbol"));
18324 if (debug_type
== DEBUG_STABS
)
18325 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18329 as_warn (_(".end directive missing or unknown symbol"));
18331 /* Create an expression to calculate the size of the function. */
18332 if (p
&& cur_proc_ptr
)
18334 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18335 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18338 exp
->X_op
= O_subtract
;
18339 exp
->X_add_symbol
= symbol_temp_new_now ();
18340 exp
->X_op_symbol
= p
;
18341 exp
->X_add_number
= 0;
18343 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18346 /* Generate a .pdr section. */
18347 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
18349 segT saved_seg
= now_seg
;
18350 subsegT saved_subseg
= now_subseg
;
18354 #ifdef md_flush_pending_output
18355 md_flush_pending_output ();
18358 gas_assert (pdr_seg
);
18359 subseg_set (pdr_seg
, 0);
18361 /* Write the symbol. */
18362 exp
.X_op
= O_symbol
;
18363 exp
.X_add_symbol
= p
;
18364 exp
.X_add_number
= 0;
18365 emit_expr (&exp
, 4);
18367 fragp
= frag_more (7 * 4);
18369 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18370 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18371 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18372 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18373 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18374 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18375 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18377 subseg_set (saved_seg
, saved_subseg
);
18380 cur_proc_ptr
= NULL
;
18383 /* The .aent and .ent directives. */
18386 s_mips_ent (int aent
)
18390 symbolP
= get_symbol ();
18391 if (*input_line_pointer
== ',')
18392 ++input_line_pointer
;
18393 SKIP_WHITESPACE ();
18394 if (ISDIGIT (*input_line_pointer
)
18395 || *input_line_pointer
== '-')
18398 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18399 as_warn (_(".ent or .aent not in text section"));
18401 if (!aent
&& cur_proc_ptr
)
18402 as_warn (_("missing .end"));
18406 /* This function needs its own .frame and .cprestore directives. */
18407 mips_frame_reg_valid
= 0;
18408 mips_cprestore_valid
= 0;
18410 cur_proc_ptr
= &cur_proc
;
18411 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18413 cur_proc_ptr
->func_sym
= symbolP
;
18417 if (debug_type
== DEBUG_STABS
)
18418 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18419 S_GET_NAME (symbolP
));
18422 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18424 demand_empty_rest_of_line ();
18427 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18428 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18429 s_mips_frame is used so that we can set the PDR information correctly.
18430 We can't use the ecoff routines because they make reference to the ecoff
18431 symbol table (in the mdebug section). */
18434 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18436 if (ECOFF_DEBUGGING
)
18442 if (cur_proc_ptr
== (procS
*) NULL
)
18444 as_warn (_(".frame outside of .ent"));
18445 demand_empty_rest_of_line ();
18449 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18451 SKIP_WHITESPACE ();
18452 if (*input_line_pointer
++ != ','
18453 || get_absolute_expression_and_terminator (&val
) != ',')
18455 as_warn (_("bad .frame directive"));
18456 --input_line_pointer
;
18457 demand_empty_rest_of_line ();
18461 cur_proc_ptr
->frame_offset
= val
;
18462 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18464 demand_empty_rest_of_line ();
18468 /* The .fmask and .mask directives. If the mdebug section is present
18469 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18470 embedded targets, s_mips_mask is used so that we can set the PDR
18471 information correctly. We can't use the ecoff routines because they
18472 make reference to the ecoff symbol table (in the mdebug section). */
18475 s_mips_mask (int reg_type
)
18477 if (ECOFF_DEBUGGING
)
18478 s_ignore (reg_type
);
18483 if (cur_proc_ptr
== (procS
*) NULL
)
18485 as_warn (_(".mask/.fmask outside of .ent"));
18486 demand_empty_rest_of_line ();
18490 if (get_absolute_expression_and_terminator (&mask
) != ',')
18492 as_warn (_("bad .mask/.fmask directive"));
18493 --input_line_pointer
;
18494 demand_empty_rest_of_line ();
18498 off
= get_absolute_expression ();
18500 if (reg_type
== 'F')
18502 cur_proc_ptr
->fpreg_mask
= mask
;
18503 cur_proc_ptr
->fpreg_offset
= off
;
18507 cur_proc_ptr
->reg_mask
= mask
;
18508 cur_proc_ptr
->reg_offset
= off
;
18511 demand_empty_rest_of_line ();
18515 /* A table describing all the processors gas knows about. Names are
18516 matched in the order listed.
18518 To ease comparison, please keep this table in the same order as
18519 gcc's mips_cpu_info_table[]. */
18520 static const struct mips_cpu_info mips_cpu_info_table
[] =
18522 /* Entries for generic ISAs */
18523 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
18524 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
18525 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
18526 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
18527 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
18528 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
18529 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18530 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
18531 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
18532 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
18533 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
18534 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
18535 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
18536 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
18537 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
18540 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
18541 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
18542 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
18545 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
18548 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
18549 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
18550 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
18551 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
18552 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
18553 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
18554 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
18555 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
18556 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
18557 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
18558 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
18559 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
18560 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
18561 /* ST Microelectronics Loongson 2E and 2F cores */
18562 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
18563 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
18566 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
18567 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
18568 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
18569 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
18570 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
18571 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
18572 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
18573 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
18574 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
18575 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
18576 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
18577 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
18578 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
18579 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
18580 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
18583 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18584 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18585 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
18586 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
18588 /* MIPS 32 Release 2 */
18589 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18590 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18591 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18592 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18593 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18594 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18595 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18596 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18597 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
18598 ISA_MIPS32R2
, CPU_MIPS32R2
},
18599 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
18600 ISA_MIPS32R2
, CPU_MIPS32R2
},
18601 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18602 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18603 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18604 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18605 /* Deprecated forms of the above. */
18606 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18607 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
18608 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18609 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18610 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18611 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18612 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18613 /* Deprecated forms of the above. */
18614 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18615 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18616 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18617 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18618 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18619 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18620 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18621 /* Deprecated forms of the above. */
18622 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18623 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18624 /* 34Kn is a 34kc without DSP. */
18625 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18626 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18627 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18628 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18629 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18630 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18631 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18632 /* Deprecated forms of the above. */
18633 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18634 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18635 /* 1004K cores are multiprocessor versions of the 34K. */
18636 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18637 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18638 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18639 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18640 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18641 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
18644 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18645 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
18646 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18647 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
18649 /* Broadcom SB-1 CPU core */
18650 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18651 /* Broadcom SB-1A CPU core */
18652 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
18654 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
18656 /* MIPS 64 Release 2 */
18658 /* Cavium Networks Octeon CPU core */
18659 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
18660 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
18661 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
18664 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
18667 XLP is mostly like XLR, with the prominent exception that it is
18668 MIPS64R2 rather than MIPS64. */
18669 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
18672 { NULL
, 0, 0, 0, 0 }
18676 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18677 with a final "000" replaced by "k". Ignore case.
18679 Note: this function is shared between GCC and GAS. */
18682 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18684 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18685 given
++, canonical
++;
18687 return ((*given
== 0 && *canonical
== 0)
18688 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18692 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18693 CPU name. We've traditionally allowed a lot of variation here.
18695 Note: this function is shared between GCC and GAS. */
18698 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18700 /* First see if the name matches exactly, or with a final "000"
18701 turned into "k". */
18702 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18705 /* If not, try comparing based on numerical designation alone.
18706 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18707 if (TOLOWER (*given
) == 'r')
18709 if (!ISDIGIT (*given
))
18712 /* Skip over some well-known prefixes in the canonical name,
18713 hoping to find a number there too. */
18714 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18716 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18718 else if (TOLOWER (canonical
[0]) == 'r')
18721 return mips_strict_matching_cpu_name_p (canonical
, given
);
18725 /* Parse an option that takes the name of a processor as its argument.
18726 OPTION is the name of the option and CPU_STRING is the argument.
18727 Return the corresponding processor enumeration if the CPU_STRING is
18728 recognized, otherwise report an error and return null.
18730 A similar function exists in GCC. */
18732 static const struct mips_cpu_info
*
18733 mips_parse_cpu (const char *option
, const char *cpu_string
)
18735 const struct mips_cpu_info
*p
;
18737 /* 'from-abi' selects the most compatible architecture for the given
18738 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18739 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18740 version. Look first at the -mgp options, if given, otherwise base
18741 the choice on MIPS_DEFAULT_64BIT.
18743 Treat NO_ABI like the EABIs. One reason to do this is that the
18744 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18745 architecture. This code picks MIPS I for 'mips' and MIPS III for
18746 'mips64', just as we did in the days before 'from-abi'. */
18747 if (strcasecmp (cpu_string
, "from-abi") == 0)
18749 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18750 return mips_cpu_info_from_isa (ISA_MIPS1
);
18752 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18753 return mips_cpu_info_from_isa (ISA_MIPS3
);
18755 if (file_mips_opts
.gp
>= 0)
18756 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
18757 ? ISA_MIPS1
: ISA_MIPS3
);
18759 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18764 /* 'default' has traditionally been a no-op. Probably not very useful. */
18765 if (strcasecmp (cpu_string
, "default") == 0)
18768 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18769 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18772 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
18776 /* Return the canonical processor information for ISA (a member of the
18777 ISA_MIPS* enumeration). */
18779 static const struct mips_cpu_info
*
18780 mips_cpu_info_from_isa (int isa
)
18784 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18785 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18786 && isa
== mips_cpu_info_table
[i
].isa
)
18787 return (&mips_cpu_info_table
[i
]);
18792 static const struct mips_cpu_info
*
18793 mips_cpu_info_from_arch (int arch
)
18797 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18798 if (arch
== mips_cpu_info_table
[i
].cpu
)
18799 return (&mips_cpu_info_table
[i
]);
18805 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18809 fprintf (stream
, "%24s", "");
18814 fprintf (stream
, ", ");
18818 if (*col_p
+ strlen (string
) > 72)
18820 fprintf (stream
, "\n%24s", "");
18824 fprintf (stream
, "%s", string
);
18825 *col_p
+= strlen (string
);
18831 md_show_usage (FILE *stream
)
18836 fprintf (stream
, _("\
18838 -EB generate big endian output\n\
18839 -EL generate little endian output\n\
18840 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18841 -G NUM allow referencing objects up to NUM bytes\n\
18842 implicitly with the gp register [default 8]\n"));
18843 fprintf (stream
, _("\
18844 -mips1 generate MIPS ISA I instructions\n\
18845 -mips2 generate MIPS ISA II instructions\n\
18846 -mips3 generate MIPS ISA III instructions\n\
18847 -mips4 generate MIPS ISA IV instructions\n\
18848 -mips5 generate MIPS ISA V instructions\n\
18849 -mips32 generate MIPS32 ISA instructions\n\
18850 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18851 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18852 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18853 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
18854 -mips64 generate MIPS64 ISA instructions\n\
18855 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18856 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18857 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18858 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
18859 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18863 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18864 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18865 show (stream
, "from-abi", &column
, &first
);
18866 fputc ('\n', stream
);
18868 fprintf (stream
, _("\
18869 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18870 -no-mCPU don't generate code specific to CPU.\n\
18871 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18875 show (stream
, "3900", &column
, &first
);
18876 show (stream
, "4010", &column
, &first
);
18877 show (stream
, "4100", &column
, &first
);
18878 show (stream
, "4650", &column
, &first
);
18879 fputc ('\n', stream
);
18881 fprintf (stream
, _("\
18882 -mips16 generate mips16 instructions\n\
18883 -no-mips16 do not generate mips16 instructions\n"));
18884 fprintf (stream
, _("\
18885 -mmicromips generate microMIPS instructions\n\
18886 -mno-micromips do not generate microMIPS instructions\n"));
18887 fprintf (stream
, _("\
18888 -msmartmips generate smartmips instructions\n\
18889 -mno-smartmips do not generate smartmips instructions\n"));
18890 fprintf (stream
, _("\
18891 -mdsp generate DSP instructions\n\
18892 -mno-dsp do not generate DSP instructions\n"));
18893 fprintf (stream
, _("\
18894 -mdspr2 generate DSP R2 instructions\n\
18895 -mno-dspr2 do not generate DSP R2 instructions\n"));
18896 fprintf (stream
, _("\
18897 -mmt generate MT instructions\n\
18898 -mno-mt do not generate MT instructions\n"));
18899 fprintf (stream
, _("\
18900 -mmcu generate MCU instructions\n\
18901 -mno-mcu do not generate MCU instructions\n"));
18902 fprintf (stream
, _("\
18903 -mmsa generate MSA instructions\n\
18904 -mno-msa do not generate MSA instructions\n"));
18905 fprintf (stream
, _("\
18906 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18907 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18908 fprintf (stream
, _("\
18909 -mvirt generate Virtualization instructions\n\
18910 -mno-virt do not generate Virtualization instructions\n"));
18911 fprintf (stream
, _("\
18912 -minsn32 only generate 32-bit microMIPS instructions\n\
18913 -mno-insn32 generate all microMIPS instructions\n"));
18914 fprintf (stream
, _("\
18915 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18916 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18917 -mfix-vr4120 work around certain VR4120 errata\n\
18918 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18919 -mfix-24k insert a nop after ERET and DERET instructions\n\
18920 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18921 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18922 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18923 -msym32 assume all symbols have 32-bit values\n\
18924 -O0 remove unneeded NOPs, do not swap branches\n\
18925 -O remove unneeded NOPs and swap branches\n\
18926 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18927 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18928 fprintf (stream
, _("\
18929 -mhard-float allow floating-point instructions\n\
18930 -msoft-float do not allow floating-point instructions\n\
18931 -msingle-float only allow 32-bit floating-point operations\n\
18932 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18933 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18934 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18935 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18939 show (stream
, "legacy", &column
, &first
);
18940 show (stream
, "2008", &column
, &first
);
18942 fputc ('\n', stream
);
18944 fprintf (stream
, _("\
18945 -KPIC, -call_shared generate SVR4 position independent code\n\
18946 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18947 -mvxworks-pic generate VxWorks position independent code\n\
18948 -non_shared do not generate code that can operate with DSOs\n\
18949 -xgot assume a 32 bit GOT\n\
18950 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18951 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18952 position dependent (non shared) code\n\
18953 -mabi=ABI create ABI conformant object file for:\n"));
18957 show (stream
, "32", &column
, &first
);
18958 show (stream
, "o64", &column
, &first
);
18959 show (stream
, "n32", &column
, &first
);
18960 show (stream
, "64", &column
, &first
);
18961 show (stream
, "eabi", &column
, &first
);
18963 fputc ('\n', stream
);
18965 fprintf (stream
, _("\
18966 -32 create o32 ABI object file (default)\n\
18967 -n32 create n32 ABI object file\n\
18968 -64 create 64 ABI object file\n"));
18973 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18975 if (HAVE_64BIT_SYMBOLS
)
18976 return dwarf2_format_64bit_irix
;
18978 return dwarf2_format_32bit
;
18983 mips_dwarf2_addr_size (void)
18985 if (HAVE_64BIT_OBJECTS
)
18991 /* Standard calling conventions leave the CFA at SP on entry. */
18993 mips_cfi_frame_initial_instructions (void)
18995 cfi_add_CFA_def_cfa_register (SP
);
18999 tc_mips_regname_to_dw2regnum (char *regname
)
19001 unsigned int regnum
= -1;
19004 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19010 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19011 Given a symbolic attribute NAME, return the proper integer value.
19012 Returns -1 if the attribute is not known. */
19015 mips_convert_symbolic_attribute (const char *name
)
19017 static const struct
19022 attribute_table
[] =
19024 #define T(tag) {#tag, tag}
19025 T (Tag_GNU_MIPS_ABI_FP
),
19026 T (Tag_GNU_MIPS_ABI_MSA
),
19034 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
19035 if (streq (name
, attribute_table
[i
].name
))
19036 return attribute_table
[i
].tag
;
19044 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
19046 mips_emit_delays ();
19048 as_warn (_("missing .end at end of assembly"));
19050 /* Just in case no code was emitted, do the consistency check. */
19051 file_mips_check_options ();
19053 /* Set a floating-point ABI if the user did not. */
19054 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
19056 /* Perform consistency checks on the floating-point ABI. */
19057 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19058 Tag_GNU_MIPS_ABI_FP
);
19059 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
19060 check_fpabi (fpabi
);
19064 /* Soft-float gets precedence over single-float, the two options should
19065 not be used together so this should not matter. */
19066 if (file_mips_opts
.soft_float
== 1)
19067 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
19068 /* Single-float gets precedence over all double_float cases. */
19069 else if (file_mips_opts
.single_float
== 1)
19070 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
19073 switch (file_mips_opts
.fp
)
19076 if (file_mips_opts
.gp
== 32)
19077 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19080 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
19083 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
19084 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
19085 else if (file_mips_opts
.gp
== 32)
19086 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
19088 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19093 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19094 Tag_GNU_MIPS_ABI_FP
, fpabi
);