1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
159 /* The ABI to use. */
170 /* MIPS ABI we are using for this output file. */
171 static enum mips_abi_level mips_abi
= NO_ABI
;
173 /* Whether or not we have code that can call pic code. */
174 int mips_abicalls
= FALSE
;
176 /* Whether or not we have code which can be put into a shared
178 static bfd_boolean mips_in_shared
= TRUE
;
180 /* This is the set of options which may be modified by the .set
181 pseudo-op. We use a struct so that .set push and .set pop are more
184 struct mips_set_options
186 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
187 if it has not been initialized. Changed by `.set mipsN', and the
188 -mipsN command line option, and the default CPU. */
190 /* Enabled Application Specific Extensions (ASEs). These are set to -1
191 if they have not been initialized. Changed by `.set <asename>', by
192 command line options, and based on the default architecture. */
195 /* Whether we are assembling for the mips16 processor. 0 if we are
196 not, 1 if we are, and -1 if the value has not been initialized.
197 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
198 -nomips16 command line options, and the default CPU. */
200 /* Non-zero if we should not reorder instructions. Changed by `.set
201 reorder' and `.set noreorder'. */
203 /* Non-zero if we should not permit the $at ($1) register to be used
204 in instructions. Changed by `.set at' and `.set noat'. */
206 /* Non-zero if we should warn when a macro instruction expands into
207 more than one machine instruction. Changed by `.set nomacro' and
209 int warn_about_macros
;
210 /* Non-zero if we should not move instructions. Changed by `.set
211 move', `.set volatile', `.set nomove', and `.set novolatile'. */
213 /* Non-zero if we should not optimize branches by moving the target
214 of the branch into the delay slot. Actually, we don't perform
215 this optimization anyhow. Changed by `.set bopt' and `.set
218 /* Non-zero if we should not autoextend mips16 instructions.
219 Changed by `.set autoextend' and `.set noautoextend'. */
221 /* Restrict general purpose registers and floating point registers
222 to 32 bit. This is initially determined when -mgp32 or -mfp32
223 is passed but can changed if the assembler code uses .set mipsN. */
226 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
227 command line option, and the default CPU. */
229 /* True if ".set sym32" is in effect. */
233 /* True if -mgp32 was passed. */
234 static int file_mips_gp32
= -1;
236 /* True if -mfp32 was passed. */
237 static int file_mips_fp32
= -1;
239 /* This is the struct we use to hold the current set of options. Note
240 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
241 -1 to indicate that they have not been initialized. */
243 static struct mips_set_options mips_opts
=
245 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
248 /* These variables are filled in with the masks of registers used.
249 The object format code reads them and puts them in the appropriate
251 unsigned long mips_gprmask
;
252 unsigned long mips_cprmask
[4];
254 /* MIPS ISA we are using for this output file. */
255 static int file_mips_isa
= ISA_UNKNOWN
;
257 /* True if -mips16 was passed or implied by arguments passed on the
258 command line (e.g., by -march). */
259 static int file_ase_mips16
;
261 /* True if -mips3d was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips3d
;
265 /* True if -mdmx was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mdmx
;
269 /* The argument of the -march= flag. The architecture we are assembling. */
270 static int file_mips_arch
= CPU_UNKNOWN
;
271 static const char *mips_arch_string
;
273 /* The argument of the -mtune= flag. The architecture for which we
275 static int mips_tune
= CPU_UNKNOWN
;
276 static const char *mips_tune_string
;
278 /* True when generating 32-bit code for a 64-bit processor. */
279 static int mips_32bitmode
= 0;
281 /* True if the given ABI requires 32-bit registers. */
282 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
284 /* Likewise 64-bit registers. */
285 #define ABI_NEEDS_64BIT_REGS(ABI) \
287 || (ABI) == N64_ABI \
290 /* Return true if ISA supports 64 bit gp register instructions. */
291 #define ISA_HAS_64BIT_REGS(ISA) ( \
293 || (ISA) == ISA_MIPS4 \
294 || (ISA) == ISA_MIPS5 \
295 || (ISA) == ISA_MIPS64 \
296 || (ISA) == ISA_MIPS64R2 \
299 /* Return true if ISA supports 64-bit right rotate (dror et al.)
301 #define ISA_HAS_DROR(ISA) ( \
302 (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 32-bit right rotate (ror et al.)
307 #define ISA_HAS_ROR(ISA) ( \
308 (ISA) == ISA_MIPS32R2 \
309 || (ISA) == ISA_MIPS64R2 \
312 #define HAVE_32BIT_GPRS \
313 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
315 #define HAVE_32BIT_FPRS \
316 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
318 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
319 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
321 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
323 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
325 /* True if relocations are stored in-place. */
326 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
328 /* The ABI-derived address size. */
329 #define HAVE_64BIT_ADDRESSES \
330 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
331 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
333 /* The size of symbolic constants (i.e., expressions of the form
334 "SYMBOL" or "SYMBOL + OFFSET"). */
335 #define HAVE_32BIT_SYMBOLS \
336 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
337 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
339 /* Addresses are loaded in different ways, depending on the address size
340 in use. The n32 ABI Documentation also mandates the use of additions
341 with overflow checking, but existing implementations don't follow it. */
342 #define ADDRESS_ADD_INSN \
343 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
345 #define ADDRESS_ADDI_INSN \
346 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
348 #define ADDRESS_LOAD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
351 #define ADDRESS_STORE_INSN \
352 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
354 /* Return true if the given CPU supports the MIPS16 ASE. */
355 #define CPU_HAS_MIPS16(cpu) \
356 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
357 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
359 /* Return true if the given CPU supports the MIPS3D ASE. */
360 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
363 /* Return true if the given CPU supports the MDMX ASE. */
364 #define CPU_HAS_MDMX(cpu) (FALSE \
367 /* True if CPU has a dror instruction. */
368 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
370 /* True if CPU has a ror instruction. */
371 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
373 /* True if mflo and mfhi can be immediately followed by instructions
374 which write to the HI and LO registers.
376 According to MIPS specifications, MIPS ISAs I, II, and III need
377 (at least) two instructions between the reads of HI/LO and
378 instructions which write them, and later ISAs do not. Contradicting
379 the MIPS specifications, some MIPS IV processor user manuals (e.g.
380 the UM for the NEC Vr5000) document needing the instructions between
381 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
382 MIPS64 and later ISAs to have the interlocks, plus any specific
383 earlier-ISA CPUs for which CPU documentation declares that the
384 instructions are really interlocked. */
385 #define hilo_interlocks \
386 (mips_opts.isa == ISA_MIPS32 \
387 || mips_opts.isa == ISA_MIPS32R2 \
388 || mips_opts.isa == ISA_MIPS64 \
389 || mips_opts.isa == ISA_MIPS64R2 \
390 || mips_opts.arch == CPU_R4010 \
391 || mips_opts.arch == CPU_R10000 \
392 || mips_opts.arch == CPU_R12000 \
393 || mips_opts.arch == CPU_RM7000 \
394 || mips_opts.arch == CPU_VR5500 \
397 /* Whether the processor uses hardware interlocks to protect reads
398 from the GPRs after they are loaded from memory, and thus does not
399 require nops to be inserted. This applies to instructions marked
400 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
402 #define gpr_interlocks \
403 (mips_opts.isa != ISA_MIPS1 \
404 || mips_opts.arch == CPU_R3900)
406 /* Whether the processor uses hardware interlocks to avoid delays
407 required by coprocessor instructions, and thus does not require
408 nops to be inserted. This applies to instructions marked
409 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
410 between instructions marked INSN_WRITE_COND_CODE and ones marked
411 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
412 levels I, II, and III. */
413 /* Itbl support may require additional care here. */
414 #define cop_interlocks \
415 ((mips_opts.isa != ISA_MIPS1 \
416 && mips_opts.isa != ISA_MIPS2 \
417 && mips_opts.isa != ISA_MIPS3) \
418 || mips_opts.arch == CPU_R4300 \
421 /* Whether the processor uses hardware interlocks to protect reads
422 from coprocessor registers after they are loaded from memory, and
423 thus does not require nops to be inserted. This applies to
424 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
425 requires at MIPS ISA level I. */
426 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
428 /* Is this a mfhi or mflo instruction? */
429 #define MF_HILO_INSN(PINFO) \
430 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
432 /* MIPS PIC level. */
434 enum mips_pic_level mips_pic
;
436 /* 1 if we should generate 32 bit offsets from the $gp register in
437 SVR4_PIC mode. Currently has no meaning in other modes. */
438 static int mips_big_got
= 0;
440 /* 1 if trap instructions should used for overflow rather than break
442 static int mips_trap
= 0;
444 /* 1 if double width floating point constants should not be constructed
445 by assembling two single width halves into two single width floating
446 point registers which just happen to alias the double width destination
447 register. On some architectures this aliasing can be disabled by a bit
448 in the status register, and the setting of this bit cannot be determined
449 automatically at assemble time. */
450 static int mips_disable_float_construction
;
452 /* Non-zero if any .set noreorder directives were used. */
454 static int mips_any_noreorder
;
456 /* Non-zero if nops should be inserted when the register referenced in
457 an mfhi/mflo instruction is read in the next two instructions. */
458 static int mips_7000_hilo_fix
;
460 /* The size of the small data section. */
461 static unsigned int g_switch_value
= 8;
462 /* Whether the -G option was used. */
463 static int g_switch_seen
= 0;
468 /* If we can determine in advance that GP optimization won't be
469 possible, we can skip the relaxation stuff that tries to produce
470 GP-relative references. This makes delay slot optimization work
473 This function can only provide a guess, but it seems to work for
474 gcc output. It needs to guess right for gcc, otherwise gcc
475 will put what it thinks is a GP-relative instruction in a branch
478 I don't know if a fix is needed for the SVR4_PIC mode. I've only
479 fixed it for the non-PIC mode. KR 95/04/07 */
480 static int nopic_need_relax (symbolS
*, int);
482 /* handle of the OPCODE hash table */
483 static struct hash_control
*op_hash
= NULL
;
485 /* The opcode hash table we use for the mips16. */
486 static struct hash_control
*mips16_op_hash
= NULL
;
488 /* This array holds the chars that always start a comment. If the
489 pre-processor is disabled, these aren't very useful */
490 const char comment_chars
[] = "#";
492 /* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
494 .line and .file directives will appear in the pre-processed output */
495 /* Note that input_file.c hand checks for '#' at the beginning of the
496 first line of the input file. This is because the compiler outputs
497 #NO_APP at the beginning of its output. */
498 /* Also note that C style comments are always supported. */
499 const char line_comment_chars
[] = "#";
501 /* This array holds machine specific line separator characters. */
502 const char line_separator_chars
[] = ";";
504 /* Chars that can be used to separate mant from exp in floating point nums */
505 const char EXP_CHARS
[] = "eE";
507 /* Chars that mean this number is a floating point constant */
510 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
512 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
513 changed in read.c . Ideally it shouldn't have to know about it at all,
514 but nothing is ideal around here.
517 static char *insn_error
;
519 static int auto_align
= 1;
521 /* When outputting SVR4 PIC code, the assembler needs to know the
522 offset in the stack frame from which to restore the $gp register.
523 This is set by the .cprestore pseudo-op, and saved in this
525 static offsetT mips_cprestore_offset
= -1;
527 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
528 more optimizations, it can use a register value instead of a memory-saved
529 offset and even an other register than $gp as global pointer. */
530 static offsetT mips_cpreturn_offset
= -1;
531 static int mips_cpreturn_register
= -1;
532 static int mips_gp_register
= GP
;
533 static int mips_gprel_offset
= 0;
535 /* Whether mips_cprestore_offset has been set in the current function
536 (or whether it has already been warned about, if not). */
537 static int mips_cprestore_valid
= 0;
539 /* This is the register which holds the stack frame, as set by the
540 .frame pseudo-op. This is needed to implement .cprestore. */
541 static int mips_frame_reg
= SP
;
543 /* Whether mips_frame_reg has been set in the current function
544 (or whether it has already been warned about, if not). */
545 static int mips_frame_reg_valid
= 0;
547 /* To output NOP instructions correctly, we need to keep information
548 about the previous two instructions. */
550 /* Whether we are optimizing. The default value of 2 means to remove
551 unneeded NOPs and swap branch instructions when possible. A value
552 of 1 means to not swap branches. A value of 0 means to always
554 static int mips_optimize
= 2;
556 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
557 equivalent to seeing no -g option at all. */
558 static int mips_debug
= 0;
560 /* The maximum number of NOPs needed to satisfy a hardware hazard
561 or processor errata. */
564 /* A list of previous instructions, with index 0 being the most recent.
565 We need to look back MAX_NOPS instructions when filling delay slots
566 or working around processor errata. We need to look back one
567 instruction further if we're thinking about using history[0] to
568 fill a branch delay slot. */
569 static struct mips_cl_insn history
[1 + MAX_NOPS
];
571 /* Nop instructions used by emit_nop. */
572 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
574 /* The appropriate nop for the current mode. */
575 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
577 /* If this is set, it points to a frag holding nop instructions which
578 were inserted before the start of a noreorder section. If those
579 nops turn out to be unnecessary, the size of the frag can be
581 static fragS
*prev_nop_frag
;
583 /* The number of nop instructions we created in prev_nop_frag. */
584 static int prev_nop_frag_holds
;
586 /* The number of nop instructions that we know we need in
588 static int prev_nop_frag_required
;
590 /* The number of instructions we've seen since prev_nop_frag. */
591 static int prev_nop_frag_since
;
593 /* For ECOFF and ELF, relocations against symbols are done in two
594 parts, with a HI relocation and a LO relocation. Each relocation
595 has only 16 bits of space to store an addend. This means that in
596 order for the linker to handle carries correctly, it must be able
597 to locate both the HI and the LO relocation. This means that the
598 relocations must appear in order in the relocation table.
600 In order to implement this, we keep track of each unmatched HI
601 relocation. We then sort them so that they immediately precede the
602 corresponding LO relocation. */
607 struct mips_hi_fixup
*next
;
610 /* The section this fixup is in. */
614 /* The list of unmatched HI relocs. */
616 static struct mips_hi_fixup
*mips_hi_fixup_list
;
618 /* The frag containing the last explicit relocation operator.
619 Null if explicit relocations have not been used. */
621 static fragS
*prev_reloc_op_frag
;
623 /* Map normal MIPS register numbers to mips16 register numbers. */
625 #define X ILLEGAL_REG
626 static const int mips32_to_16_reg_map
[] =
628 X
, X
, 2, 3, 4, 5, 6, 7,
629 X
, X
, X
, X
, X
, X
, X
, X
,
630 0, 1, X
, X
, X
, X
, X
, X
,
631 X
, X
, X
, X
, X
, X
, X
, X
635 /* Map mips16 register numbers to normal MIPS register numbers. */
637 static const unsigned int mips16_to_32_reg_map
[] =
639 16, 17, 2, 3, 4, 5, 6, 7
642 /* Classifies the kind of instructions we're interested in when
643 implementing -mfix-vr4120. */
644 enum fix_vr4120_class
{
651 NUM_FIX_VR4120_CLASSES
654 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
655 there must be at least one other instruction between an instruction
656 of type X and an instruction of type Y. */
657 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
659 /* True if -mfix-vr4120 is in force. */
660 static int mips_fix_vr4120
;
662 /* We don't relax branches by default, since this causes us to expand
663 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
664 fail to compute the offset before expanding the macro to the most
665 efficient expansion. */
667 static int mips_relax_branch
;
669 /* The expansion of many macros depends on the type of symbol that
670 they refer to. For example, when generating position-dependent code,
671 a macro that refers to a symbol may have two different expansions,
672 one which uses GP-relative addresses and one which uses absolute
673 addresses. When generating SVR4-style PIC, a macro may have
674 different expansions for local and global symbols.
676 We handle these situations by generating both sequences and putting
677 them in variant frags. In position-dependent code, the first sequence
678 will be the GP-relative one and the second sequence will be the
679 absolute one. In SVR4 PIC, the first sequence will be for global
680 symbols and the second will be for local symbols.
682 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
683 SECOND are the lengths of the two sequences in bytes. These fields
684 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
685 the subtype has the following flags:
688 Set if it has been decided that we should use the second
689 sequence instead of the first.
692 Set in the first variant frag if the macro's second implementation
693 is longer than its first. This refers to the macro as a whole,
694 not an individual relaxation.
697 Set in the first variant frag if the macro appeared in a .set nomacro
698 block and if one alternative requires a warning but the other does not.
701 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
704 The frag's "opcode" points to the first fixup for relaxable code.
706 Relaxable macros are generated using a sequence such as:
708 relax_start (SYMBOL);
709 ... generate first expansion ...
711 ... generate second expansion ...
714 The code and fixups for the unwanted alternative are discarded
715 by md_convert_frag. */
716 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
718 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
719 #define RELAX_SECOND(X) ((X) & 0xff)
720 #define RELAX_USE_SECOND 0x10000
721 #define RELAX_SECOND_LONGER 0x20000
722 #define RELAX_NOMACRO 0x40000
723 #define RELAX_DELAY_SLOT 0x80000
725 /* Branch without likely bit. If label is out of range, we turn:
727 beq reg1, reg2, label
737 with the following opcode replacements:
744 bltzal <-> bgezal (with jal label instead of j label)
746 Even though keeping the delay slot instruction in the delay slot of
747 the branch would be more efficient, it would be very tricky to do
748 correctly, because we'd have to introduce a variable frag *after*
749 the delay slot instruction, and expand that instead. Let's do it
750 the easy way for now, even if the branch-not-taken case now costs
751 one additional instruction. Out-of-range branches are not supposed
752 to be common, anyway.
754 Branch likely. If label is out of range, we turn:
756 beql reg1, reg2, label
757 delay slot (annulled if branch not taken)
766 delay slot (executed only if branch taken)
769 It would be possible to generate a shorter sequence by losing the
770 likely bit, generating something like:
775 delay slot (executed only if branch taken)
787 bltzall -> bgezal (with jal label instead of j label)
788 bgezall -> bltzal (ditto)
791 but it's not clear that it would actually improve performance. */
792 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
795 | ((toofar) ? 1 : 0) \
797 | ((likely) ? 4 : 0) \
798 | ((uncond) ? 8 : 0)))
799 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
800 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
801 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
802 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
803 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
805 /* For mips16 code, we use an entirely different form of relaxation.
806 mips16 supports two versions of most instructions which take
807 immediate values: a small one which takes some small value, and a
808 larger one which takes a 16 bit value. Since branches also follow
809 this pattern, relaxing these values is required.
811 We can assemble both mips16 and normal MIPS code in a single
812 object. Therefore, we need to support this type of relaxation at
813 the same time that we support the relaxation described above. We
814 use the high bit of the subtype field to distinguish these cases.
816 The information we store for this type of relaxation is the
817 argument code found in the opcode file for this relocation, whether
818 the user explicitly requested a small or extended form, and whether
819 the relocation is in a jump or jal delay slot. That tells us the
820 size of the value, and how it should be stored. We also store
821 whether the fragment is considered to be extended or not. We also
822 store whether this is known to be a branch to a different section,
823 whether we have tried to relax this frag yet, and whether we have
824 ever extended a PC relative fragment because of a shift count. */
825 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
828 | ((small) ? 0x100 : 0) \
829 | ((ext) ? 0x200 : 0) \
830 | ((dslot) ? 0x400 : 0) \
831 | ((jal_dslot) ? 0x800 : 0))
832 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
833 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
834 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
835 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
836 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
837 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
838 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
839 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
840 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
841 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
842 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
843 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
845 /* Is the given value a sign-extended 32-bit value? */
846 #define IS_SEXT_32BIT_NUM(x) \
847 (((x) &~ (offsetT) 0x7fffffff) == 0 \
848 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
850 /* Is the given value a sign-extended 16-bit value? */
851 #define IS_SEXT_16BIT_NUM(x) \
852 (((x) &~ (offsetT) 0x7fff) == 0 \
853 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
855 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
856 VALUE << SHIFT. VALUE is evaluated exactly once. */
857 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
858 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
859 | (((VALUE) & (MASK)) << (SHIFT)))
861 /* Extract bits MASK << SHIFT from STRUCT and shift them right
863 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
864 (((STRUCT) >> (SHIFT)) & (MASK))
866 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
867 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
869 include/opcode/mips.h specifies operand fields using the macros
870 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
871 with "MIPS16OP" instead of "OP". */
872 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
873 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
874 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
875 INSERT_BITS ((INSN).insn_opcode, VALUE, \
876 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
878 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
879 #define EXTRACT_OPERAND(FIELD, INSN) \
880 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
881 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
882 EXTRACT_BITS ((INSN).insn_opcode, \
883 MIPS16OP_MASK_##FIELD, \
886 /* Global variables used when generating relaxable macros. See the
887 comment above RELAX_ENCODE for more details about how relaxation
890 /* 0 if we're not emitting a relaxable macro.
891 1 if we're emitting the first of the two relaxation alternatives.
892 2 if we're emitting the second alternative. */
895 /* The first relaxable fixup in the current frag. (In other words,
896 the first fixup that refers to relaxable code.) */
899 /* sizes[0] says how many bytes of the first alternative are stored in
900 the current frag. Likewise sizes[1] for the second alternative. */
901 unsigned int sizes
[2];
903 /* The symbol on which the choice of sequence depends. */
907 /* Global variables used to decide whether a macro needs a warning. */
909 /* True if the macro is in a branch delay slot. */
910 bfd_boolean delay_slot_p
;
912 /* For relaxable macros, sizes[0] is the length of the first alternative
913 in bytes and sizes[1] is the length of the second alternative.
914 For non-relaxable macros, both elements give the length of the
916 unsigned int sizes
[2];
918 /* The first variant frag for this macro. */
920 } mips_macro_warning
;
922 /* Prototypes for static functions. */
924 #define internalError() \
925 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
927 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
929 static void append_insn
930 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
931 static void mips_no_prev_insn (void);
932 static void mips16_macro_build
933 (expressionS
*, const char *, const char *, va_list);
934 static void load_register (int, expressionS
*, int);
935 static void macro_start (void);
936 static void macro_end (void);
937 static void macro (struct mips_cl_insn
* ip
);
938 static void mips16_macro (struct mips_cl_insn
* ip
);
939 #ifdef LOSING_COMPILER
940 static void macro2 (struct mips_cl_insn
* ip
);
942 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
943 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
944 static void mips16_immed
945 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
946 unsigned long *, bfd_boolean
*, unsigned short *);
947 static size_t my_getSmallExpression
948 (expressionS
*, bfd_reloc_code_real_type
*, char *);
949 static void my_getExpression (expressionS
*, char *);
950 static void s_align (int);
951 static void s_change_sec (int);
952 static void s_change_section (int);
953 static void s_cons (int);
954 static void s_float_cons (int);
955 static void s_mips_globl (int);
956 static void s_option (int);
957 static void s_mipsset (int);
958 static void s_abicalls (int);
959 static void s_cpload (int);
960 static void s_cpsetup (int);
961 static void s_cplocal (int);
962 static void s_cprestore (int);
963 static void s_cpreturn (int);
964 static void s_gpvalue (int);
965 static void s_gpword (int);
966 static void s_gpdword (int);
967 static void s_cpadd (int);
968 static void s_insn (int);
969 static void md_obj_begin (void);
970 static void md_obj_end (void);
971 static void s_mips_ent (int);
972 static void s_mips_end (int);
973 static void s_mips_frame (int);
974 static void s_mips_mask (int reg_type
);
975 static void s_mips_stab (int);
976 static void s_mips_weakext (int);
977 static void s_mips_file (int);
978 static void s_mips_loc (int);
979 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
980 static int relaxed_branch_length (fragS
*, asection
*, int);
981 static int validate_mips_insn (const struct mips_opcode
*);
983 /* Table and functions used to map between CPU/ISA names, and
984 ISA levels, and CPU numbers. */
988 const char *name
; /* CPU or ISA name. */
989 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
990 int isa
; /* ISA level. */
991 int cpu
; /* CPU number (default CPU if ISA). */
994 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
995 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
996 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1000 The following pseudo-ops from the Kane and Heinrich MIPS book
1001 should be defined here, but are currently unsupported: .alias,
1002 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1004 The following pseudo-ops from the Kane and Heinrich MIPS book are
1005 specific to the type of debugging information being generated, and
1006 should be defined by the object format: .aent, .begin, .bend,
1007 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1010 The following pseudo-ops from the Kane and Heinrich MIPS book are
1011 not MIPS CPU specific, but are also not specific to the object file
1012 format. This file is probably the best place to define them, but
1013 they are not currently supported: .asm0, .endr, .lab, .repeat,
1016 static const pseudo_typeS mips_pseudo_table
[] =
1018 /* MIPS specific pseudo-ops. */
1019 {"option", s_option
, 0},
1020 {"set", s_mipsset
, 0},
1021 {"rdata", s_change_sec
, 'r'},
1022 {"sdata", s_change_sec
, 's'},
1023 {"livereg", s_ignore
, 0},
1024 {"abicalls", s_abicalls
, 0},
1025 {"cpload", s_cpload
, 0},
1026 {"cpsetup", s_cpsetup
, 0},
1027 {"cplocal", s_cplocal
, 0},
1028 {"cprestore", s_cprestore
, 0},
1029 {"cpreturn", s_cpreturn
, 0},
1030 {"gpvalue", s_gpvalue
, 0},
1031 {"gpword", s_gpword
, 0},
1032 {"gpdword", s_gpdword
, 0},
1033 {"cpadd", s_cpadd
, 0},
1034 {"insn", s_insn
, 0},
1036 /* Relatively generic pseudo-ops that happen to be used on MIPS
1038 {"asciiz", stringer
, 1},
1039 {"bss", s_change_sec
, 'b'},
1041 {"half", s_cons
, 1},
1042 {"dword", s_cons
, 3},
1043 {"weakext", s_mips_weakext
, 0},
1045 /* These pseudo-ops are defined in read.c, but must be overridden
1046 here for one reason or another. */
1047 {"align", s_align
, 0},
1048 {"byte", s_cons
, 0},
1049 {"data", s_change_sec
, 'd'},
1050 {"double", s_float_cons
, 'd'},
1051 {"float", s_float_cons
, 'f'},
1052 {"globl", s_mips_globl
, 0},
1053 {"global", s_mips_globl
, 0},
1054 {"hword", s_cons
, 1},
1056 {"long", s_cons
, 2},
1057 {"octa", s_cons
, 4},
1058 {"quad", s_cons
, 3},
1059 {"section", s_change_section
, 0},
1060 {"short", s_cons
, 1},
1061 {"single", s_float_cons
, 'f'},
1062 {"stabn", s_mips_stab
, 'n'},
1063 {"text", s_change_sec
, 't'},
1064 {"word", s_cons
, 2},
1066 { "extern", ecoff_directive_extern
, 0},
1071 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1073 /* These pseudo-ops should be defined by the object file format.
1074 However, a.out doesn't support them, so we have versions here. */
1075 {"aent", s_mips_ent
, 1},
1076 {"bgnb", s_ignore
, 0},
1077 {"end", s_mips_end
, 0},
1078 {"endb", s_ignore
, 0},
1079 {"ent", s_mips_ent
, 0},
1080 {"file", s_mips_file
, 0},
1081 {"fmask", s_mips_mask
, 'F'},
1082 {"frame", s_mips_frame
, 0},
1083 {"loc", s_mips_loc
, 0},
1084 {"mask", s_mips_mask
, 'R'},
1085 {"verstamp", s_ignore
, 0},
1089 extern void pop_insert (const pseudo_typeS
*);
1092 mips_pop_insert (void)
1094 pop_insert (mips_pseudo_table
);
1095 if (! ECOFF_DEBUGGING
)
1096 pop_insert (mips_nonecoff_pseudo_table
);
1099 /* Symbols labelling the current insn. */
1101 struct insn_label_list
1103 struct insn_label_list
*next
;
1107 static struct insn_label_list
*insn_labels
;
1108 static struct insn_label_list
*free_insn_labels
;
1110 static void mips_clear_insn_labels (void);
1113 mips_clear_insn_labels (void)
1115 register struct insn_label_list
**pl
;
1117 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1123 static char *expr_end
;
1125 /* Expressions which appear in instructions. These are set by
1128 static expressionS imm_expr
;
1129 static expressionS imm2_expr
;
1130 static expressionS offset_expr
;
1132 /* Relocs associated with imm_expr and offset_expr. */
1134 static bfd_reloc_code_real_type imm_reloc
[3]
1135 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1136 static bfd_reloc_code_real_type offset_reloc
[3]
1137 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1139 /* These are set by mips16_ip if an explicit extension is used. */
1141 static bfd_boolean mips16_small
, mips16_ext
;
1144 /* The pdr segment for per procedure frame/regmask info. Not used for
1147 static segT pdr_seg
;
1150 /* The default target format to use. */
1153 mips_target_format (void)
1155 switch (OUTPUT_FLAVOR
)
1157 case bfd_target_ecoff_flavour
:
1158 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1159 case bfd_target_coff_flavour
:
1161 case bfd_target_elf_flavour
:
1163 /* This is traditional mips. */
1164 return (target_big_endian
1165 ? (HAVE_64BIT_OBJECTS
1166 ? "elf64-tradbigmips"
1168 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1169 : (HAVE_64BIT_OBJECTS
1170 ? "elf64-tradlittlemips"
1172 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1174 return (target_big_endian
1175 ? (HAVE_64BIT_OBJECTS
1178 ? "elf32-nbigmips" : "elf32-bigmips"))
1179 : (HAVE_64BIT_OBJECTS
1180 ? "elf64-littlemips"
1182 ? "elf32-nlittlemips" : "elf32-littlemips")));
1190 /* Return the length of instruction INSN. */
1192 static inline unsigned int
1193 insn_length (const struct mips_cl_insn
*insn
)
1195 if (!mips_opts
.mips16
)
1197 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1200 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1203 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1208 insn
->use_extend
= FALSE
;
1210 insn
->insn_opcode
= mo
->match
;
1213 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1214 insn
->fixp
[i
] = NULL
;
1215 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1216 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1217 insn
->mips16_absolute_jump_p
= 0;
1220 /* Install INSN at the location specified by its "frag" and "where" fields. */
1223 install_insn (const struct mips_cl_insn
*insn
)
1225 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1226 if (!mips_opts
.mips16
)
1227 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1228 else if (insn
->mips16_absolute_jump_p
)
1230 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1231 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1235 if (insn
->use_extend
)
1237 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1240 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1244 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1245 and install the opcode in the new location. */
1248 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1253 insn
->where
= where
;
1254 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1255 if (insn
->fixp
[i
] != NULL
)
1257 insn
->fixp
[i
]->fx_frag
= frag
;
1258 insn
->fixp
[i
]->fx_where
= where
;
1260 install_insn (insn
);
1263 /* Add INSN to the end of the output. */
1266 add_fixed_insn (struct mips_cl_insn
*insn
)
1268 char *f
= frag_more (insn_length (insn
));
1269 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1272 /* Start a variant frag and move INSN to the start of the variant part,
1273 marking it as fixed. The other arguments are as for frag_var. */
1276 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1277 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1279 frag_grow (max_chars
);
1280 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1282 frag_var (rs_machine_dependent
, max_chars
, var
,
1283 subtype
, symbol
, offset
, NULL
);
1286 /* Insert N copies of INSN into the history buffer, starting at
1287 position FIRST. Neither FIRST nor N need to be clipped. */
1290 insert_into_history (unsigned int first
, unsigned int n
,
1291 const struct mips_cl_insn
*insn
)
1293 if (mips_relax
.sequence
!= 2)
1297 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1299 history
[i
] = history
[i
- n
];
1305 /* Emit a nop instruction, recording it in the history buffer. */
1310 add_fixed_insn (NOP_INSN
);
1311 insert_into_history (0, 1, NOP_INSN
);
1314 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1315 the idea is to make it obvious at a glance that each errata is
1319 init_vr4120_conflicts (void)
1321 #define CONFLICT(FIRST, SECOND) \
1322 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1324 /* Errata 21 - [D]DIV[U] after [D]MACC */
1325 CONFLICT (MACC
, DIV
);
1326 CONFLICT (DMACC
, DIV
);
1328 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1329 CONFLICT (DMULT
, DMULT
);
1330 CONFLICT (DMULT
, DMACC
);
1331 CONFLICT (DMACC
, DMULT
);
1332 CONFLICT (DMACC
, DMACC
);
1334 /* Errata 24 - MT{LO,HI} after [D]MACC */
1335 CONFLICT (MACC
, MTHILO
);
1336 CONFLICT (DMACC
, MTHILO
);
1338 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1339 instruction is executed immediately after a MACC or DMACC
1340 instruction, the result of [either instruction] is incorrect." */
1341 CONFLICT (MACC
, MULT
);
1342 CONFLICT (MACC
, DMULT
);
1343 CONFLICT (DMACC
, MULT
);
1344 CONFLICT (DMACC
, DMULT
);
1346 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1347 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1348 DDIV or DDIVU instruction, the result of the MACC or
1349 DMACC instruction is incorrect.". */
1350 CONFLICT (DMULT
, MACC
);
1351 CONFLICT (DMULT
, DMACC
);
1352 CONFLICT (DIV
, MACC
);
1353 CONFLICT (DIV
, DMACC
);
1358 /* This function is called once, at assembler startup time. It should
1359 set up all the tables, etc. that the MD part of the assembler will need. */
1364 register const char *retval
= NULL
;
1368 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1369 as_warn (_("Could not set architecture and machine"));
1371 op_hash
= hash_new ();
1373 for (i
= 0; i
< NUMOPCODES
;)
1375 const char *name
= mips_opcodes
[i
].name
;
1377 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1380 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1381 mips_opcodes
[i
].name
, retval
);
1382 /* Probably a memory allocation problem? Give up now. */
1383 as_fatal (_("Broken assembler. No assembly attempted."));
1387 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1389 if (!validate_mips_insn (&mips_opcodes
[i
]))
1391 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1393 create_insn (&nop_insn
, mips_opcodes
+ i
);
1394 nop_insn
.fixed_p
= 1;
1399 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1402 mips16_op_hash
= hash_new ();
1405 while (i
< bfd_mips16_num_opcodes
)
1407 const char *name
= mips16_opcodes
[i
].name
;
1409 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1411 as_fatal (_("internal: can't hash `%s': %s"),
1412 mips16_opcodes
[i
].name
, retval
);
1415 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1416 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1417 != mips16_opcodes
[i
].match
))
1419 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1420 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1423 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1425 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1426 mips16_nop_insn
.fixed_p
= 1;
1430 while (i
< bfd_mips16_num_opcodes
1431 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1435 as_fatal (_("Broken assembler. No assembly attempted."));
1437 /* We add all the general register names to the symbol table. This
1438 helps us detect invalid uses of them. */
1439 for (i
= 0; i
< 32; i
++)
1443 sprintf (buf
, "$%d", i
);
1444 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1445 &zero_address_frag
));
1447 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1448 &zero_address_frag
));
1449 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1450 &zero_address_frag
));
1451 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1452 &zero_address_frag
));
1453 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1454 &zero_address_frag
));
1455 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1456 &zero_address_frag
));
1457 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1458 &zero_address_frag
));
1459 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1460 &zero_address_frag
));
1461 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1462 &zero_address_frag
));
1463 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1464 &zero_address_frag
));
1466 /* If we don't add these register names to the symbol table, they
1467 may end up being added as regular symbols by operand(), and then
1468 make it to the object file as undefined in case they're not
1469 regarded as local symbols. They're local in o32, since `$' is a
1470 local symbol prefix, but not in n32 or n64. */
1471 for (i
= 0; i
< 8; i
++)
1475 sprintf (buf
, "$fcc%i", i
);
1476 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1477 &zero_address_frag
));
1480 mips_no_prev_insn ();
1483 mips_cprmask
[0] = 0;
1484 mips_cprmask
[1] = 0;
1485 mips_cprmask
[2] = 0;
1486 mips_cprmask
[3] = 0;
1488 /* set the default alignment for the text section (2**2) */
1489 record_alignment (text_section
, 2);
1491 bfd_set_gp_size (stdoutput
, g_switch_value
);
1493 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1495 /* On a native system, sections must be aligned to 16 byte
1496 boundaries. When configured for an embedded ELF target, we
1498 if (strcmp (TARGET_OS
, "elf") != 0)
1500 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1501 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1502 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1505 /* Create a .reginfo section for register masks and a .mdebug
1506 section for debugging information. */
1514 subseg
= now_subseg
;
1516 /* The ABI says this section should be loaded so that the
1517 running program can access it. However, we don't load it
1518 if we are configured for an embedded target */
1519 flags
= SEC_READONLY
| SEC_DATA
;
1520 if (strcmp (TARGET_OS
, "elf") != 0)
1521 flags
|= SEC_ALLOC
| SEC_LOAD
;
1523 if (mips_abi
!= N64_ABI
)
1525 sec
= subseg_new (".reginfo", (subsegT
) 0);
1527 bfd_set_section_flags (stdoutput
, sec
, flags
);
1528 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1531 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1536 /* The 64-bit ABI uses a .MIPS.options section rather than
1537 .reginfo section. */
1538 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1539 bfd_set_section_flags (stdoutput
, sec
, flags
);
1540 bfd_set_section_alignment (stdoutput
, sec
, 3);
1543 /* Set up the option header. */
1545 Elf_Internal_Options opthdr
;
1548 opthdr
.kind
= ODK_REGINFO
;
1549 opthdr
.size
= (sizeof (Elf_External_Options
)
1550 + sizeof (Elf64_External_RegInfo
));
1553 f
= frag_more (sizeof (Elf_External_Options
));
1554 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1555 (Elf_External_Options
*) f
);
1557 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1562 if (ECOFF_DEBUGGING
)
1564 sec
= subseg_new (".mdebug", (subsegT
) 0);
1565 (void) bfd_set_section_flags (stdoutput
, sec
,
1566 SEC_HAS_CONTENTS
| SEC_READONLY
);
1567 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1570 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1572 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1573 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1574 SEC_READONLY
| SEC_RELOC
1576 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1580 subseg_set (seg
, subseg
);
1584 if (! ECOFF_DEBUGGING
)
1587 if (mips_fix_vr4120
)
1588 init_vr4120_conflicts ();
1594 if (! ECOFF_DEBUGGING
)
1599 md_assemble (char *str
)
1601 struct mips_cl_insn insn
;
1602 bfd_reloc_code_real_type unused_reloc
[3]
1603 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1605 imm_expr
.X_op
= O_absent
;
1606 imm2_expr
.X_op
= O_absent
;
1607 offset_expr
.X_op
= O_absent
;
1608 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1609 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1610 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1611 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1612 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1613 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1615 if (mips_opts
.mips16
)
1616 mips16_ip (str
, &insn
);
1619 mips_ip (str
, &insn
);
1620 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1621 str
, insn
.insn_opcode
));
1626 as_bad ("%s `%s'", insn_error
, str
);
1630 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1633 if (mips_opts
.mips16
)
1634 mips16_macro (&insn
);
1641 if (imm_expr
.X_op
!= O_absent
)
1642 append_insn (&insn
, &imm_expr
, imm_reloc
);
1643 else if (offset_expr
.X_op
!= O_absent
)
1644 append_insn (&insn
, &offset_expr
, offset_reloc
);
1646 append_insn (&insn
, NULL
, unused_reloc
);
1650 /* Return true if the given relocation might need a matching %lo().
1651 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1652 applied to local symbols. */
1654 static inline bfd_boolean
1655 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1657 return (HAVE_IN_PLACE_ADDENDS
1658 && (reloc
== BFD_RELOC_HI16_S
1659 || reloc
== BFD_RELOC_MIPS_GOT16
1660 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1663 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1666 static inline bfd_boolean
1667 fixup_has_matching_lo_p (fixS
*fixp
)
1669 return (fixp
->fx_next
!= NULL
1670 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1671 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1672 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1673 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1676 /* See whether instruction IP reads register REG. CLASS is the type
1680 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1681 enum mips_regclass
class)
1683 if (class == MIPS16_REG
)
1685 assert (mips_opts
.mips16
);
1686 reg
= mips16_to_32_reg_map
[reg
];
1687 class = MIPS_GR_REG
;
1690 /* Don't report on general register ZERO, since it never changes. */
1691 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1694 if (class == MIPS_FP_REG
)
1696 assert (! mips_opts
.mips16
);
1697 /* If we are called with either $f0 or $f1, we must check $f0.
1698 This is not optimal, because it will introduce an unnecessary
1699 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1700 need to distinguish reading both $f0 and $f1 or just one of
1701 them. Note that we don't have to check the other way,
1702 because there is no instruction that sets both $f0 and $f1
1703 and requires a delay. */
1704 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1705 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1706 == (reg
&~ (unsigned) 1)))
1708 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1709 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1710 == (reg
&~ (unsigned) 1)))
1713 else if (! mips_opts
.mips16
)
1715 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1716 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1718 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1719 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1724 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1725 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1727 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1728 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1730 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1731 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1734 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1736 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1738 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1740 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1741 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1748 /* This function returns true if modifying a register requires a
1752 reg_needs_delay (unsigned int reg
)
1754 unsigned long prev_pinfo
;
1756 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1757 if (! mips_opts
.noreorder
1758 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1759 && ! gpr_interlocks
)
1760 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1761 && ! cop_interlocks
)))
1763 /* A load from a coprocessor or from memory. All load delays
1764 delay the use of general register rt for one instruction. */
1765 /* Itbl support may require additional care here. */
1766 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1767 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1774 /* Move all labels in insn_labels to the current insertion point. */
1777 mips_move_labels (void)
1779 struct insn_label_list
*l
;
1782 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1784 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1785 symbol_set_frag (l
->label
, frag_now
);
1786 val
= (valueT
) frag_now_fix ();
1787 /* mips16 text labels are stored as odd. */
1788 if (mips_opts
.mips16
)
1790 S_SET_VALUE (l
->label
, val
);
1794 /* Mark instruction labels in mips16 mode. This permits the linker to
1795 handle them specially, such as generating jalx instructions when
1796 needed. We also make them odd for the duration of the assembly, in
1797 order to generate the right sort of code. We will make them even
1798 in the adjust_symtab routine, while leaving them marked. This is
1799 convenient for the debugger and the disassembler. The linker knows
1800 to make them odd again. */
1803 mips16_mark_labels (void)
1805 if (mips_opts
.mips16
)
1807 struct insn_label_list
*l
;
1810 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1813 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1814 S_SET_OTHER (l
->label
, STO_MIPS16
);
1816 val
= S_GET_VALUE (l
->label
);
1818 S_SET_VALUE (l
->label
, val
+ 1);
1823 /* End the current frag. Make it a variant frag and record the
1827 relax_close_frag (void)
1829 mips_macro_warning
.first_frag
= frag_now
;
1830 frag_var (rs_machine_dependent
, 0, 0,
1831 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1832 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1834 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1835 mips_relax
.first_fixup
= 0;
1838 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1839 See the comment above RELAX_ENCODE for more details. */
1842 relax_start (symbolS
*symbol
)
1844 assert (mips_relax
.sequence
== 0);
1845 mips_relax
.sequence
= 1;
1846 mips_relax
.symbol
= symbol
;
1849 /* Start generating the second version of a relaxable sequence.
1850 See the comment above RELAX_ENCODE for more details. */
1855 assert (mips_relax
.sequence
== 1);
1856 mips_relax
.sequence
= 2;
1859 /* End the current relaxable sequence. */
1864 assert (mips_relax
.sequence
== 2);
1865 relax_close_frag ();
1866 mips_relax
.sequence
= 0;
1869 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1870 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1871 by VR4120 errata. */
1874 classify_vr4120_insn (const char *name
)
1876 if (strncmp (name
, "macc", 4) == 0)
1877 return FIX_VR4120_MACC
;
1878 if (strncmp (name
, "dmacc", 5) == 0)
1879 return FIX_VR4120_DMACC
;
1880 if (strncmp (name
, "mult", 4) == 0)
1881 return FIX_VR4120_MULT
;
1882 if (strncmp (name
, "dmult", 5) == 0)
1883 return FIX_VR4120_DMULT
;
1884 if (strstr (name
, "div"))
1885 return FIX_VR4120_DIV
;
1886 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1887 return FIX_VR4120_MTHILO
;
1888 return NUM_FIX_VR4120_CLASSES
;
1891 /* Return the number of instructions that must separate INSN1 and INSN2,
1892 where INSN1 is the earlier instruction. Return the worst-case value
1893 for any INSN2 if INSN2 is null. */
1896 insns_between (const struct mips_cl_insn
*insn1
,
1897 const struct mips_cl_insn
*insn2
)
1899 unsigned long pinfo1
, pinfo2
;
1901 /* This function needs to know which pinfo flags are set for INSN2
1902 and which registers INSN2 uses. The former is stored in PINFO2 and
1903 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1904 will have every flag set and INSN2_USES_REG will always return true. */
1905 pinfo1
= insn1
->insn_mo
->pinfo
;
1906 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1908 #define INSN2_USES_REG(REG, CLASS) \
1909 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1911 /* For most targets, write-after-read dependencies on the HI and LO
1912 registers must be separated by at least two instructions. */
1913 if (!hilo_interlocks
)
1915 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1917 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1921 /* If we're working around r7000 errata, there must be two instructions
1922 between an mfhi or mflo and any instruction that uses the result. */
1923 if (mips_7000_hilo_fix
1924 && MF_HILO_INSN (pinfo1
)
1925 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1928 /* If working around VR4120 errata, check for combinations that need
1929 a single intervening instruction. */
1930 if (mips_fix_vr4120
)
1932 unsigned int class1
, class2
;
1934 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1935 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1939 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1940 if (vr4120_conflicts
[class1
] & (1 << class2
))
1945 if (!mips_opts
.mips16
)
1947 /* Check for GPR or coprocessor load delays. All such delays
1948 are on the RT register. */
1949 /* Itbl support may require additional care here. */
1950 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1951 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1953 know (pinfo1
& INSN_WRITE_GPR_T
);
1954 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1958 /* Check for generic coprocessor hazards.
1960 This case is not handled very well. There is no special
1961 knowledge of CP0 handling, and the coprocessors other than
1962 the floating point unit are not distinguished at all. */
1963 /* Itbl support may require additional care here. FIXME!
1964 Need to modify this to include knowledge about
1965 user specified delays! */
1966 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1967 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
1969 /* Handle cases where INSN1 writes to a known general coprocessor
1970 register. There must be a one instruction delay before INSN2
1971 if INSN2 reads that register, otherwise no delay is needed. */
1972 if (pinfo1
& INSN_WRITE_FPR_T
)
1974 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
1977 else if (pinfo1
& INSN_WRITE_FPR_S
)
1979 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
1984 /* Read-after-write dependencies on the control registers
1985 require a two-instruction gap. */
1986 if ((pinfo1
& INSN_WRITE_COND_CODE
)
1987 && (pinfo2
& INSN_READ_COND_CODE
))
1990 /* We don't know exactly what INSN1 does. If INSN2 is
1991 also a coprocessor instruction, assume there must be
1992 a one instruction gap. */
1993 if (pinfo2
& INSN_COP
)
1998 /* Check for read-after-write dependencies on the coprocessor
1999 control registers in cases where INSN1 does not need a general
2000 coprocessor delay. This means that INSN1 is a floating point
2001 comparison instruction. */
2002 /* Itbl support may require additional care here. */
2003 else if (!cop_interlocks
2004 && (pinfo1
& INSN_WRITE_COND_CODE
)
2005 && (pinfo2
& INSN_READ_COND_CODE
))
2009 #undef INSN2_USES_REG
2014 /* Return the number of nops that would be needed if instruction INSN
2015 immediately followed the MAX_NOPS instructions given by HISTORY,
2016 where HISTORY[0] is the most recent instruction. If INSN is null,
2017 return the worse-case number of nops for any instruction. */
2020 nops_for_insn (const struct mips_cl_insn
*history
,
2021 const struct mips_cl_insn
*insn
)
2023 int i
, nops
, tmp_nops
;
2026 for (i
= 0; i
< MAX_NOPS
; i
++)
2027 if (!history
[i
].noreorder_p
)
2029 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2030 if (tmp_nops
> nops
)
2036 /* The variable arguments provide NUM_INSNS extra instructions that
2037 might be added to HISTORY. Return the largest number of nops that
2038 would be needed after the extended sequence. */
2041 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2044 struct mips_cl_insn buffer
[MAX_NOPS
];
2045 struct mips_cl_insn
*cursor
;
2048 va_start (args
, history
);
2049 cursor
= buffer
+ num_insns
;
2050 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2051 while (cursor
> buffer
)
2052 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2054 nops
= nops_for_insn (buffer
, NULL
);
2059 /* Like nops_for_insn, but if INSN is a branch, take into account the
2060 worst-case delay for the branch target. */
2063 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2064 const struct mips_cl_insn
*insn
)
2068 nops
= nops_for_insn (history
, insn
);
2069 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2070 | INSN_COND_BRANCH_DELAY
2071 | INSN_COND_BRANCH_LIKELY
))
2073 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2074 if (tmp_nops
> nops
)
2077 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2079 tmp_nops
= nops_for_sequence (1, history
, insn
);
2080 if (tmp_nops
> nops
)
2086 /* Output an instruction. IP is the instruction information.
2087 ADDRESS_EXPR is an operand of the instruction to be used with
2091 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2092 bfd_reloc_code_real_type
*reloc_type
)
2094 register unsigned long prev_pinfo
, pinfo
;
2095 relax_stateT prev_insn_frag_type
= 0;
2096 bfd_boolean relaxed_branch
= FALSE
;
2098 /* Mark instruction labels in mips16 mode. */
2099 mips16_mark_labels ();
2101 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2102 pinfo
= ip
->insn_mo
->pinfo
;
2104 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2106 /* There are a lot of optimizations we could do that we don't.
2107 In particular, we do not, in general, reorder instructions.
2108 If you use gcc with optimization, it will reorder
2109 instructions and generally do much more optimization then we
2110 do here; repeating all that work in the assembler would only
2111 benefit hand written assembly code, and does not seem worth
2113 int nops
= (mips_optimize
== 0
2114 ? nops_for_insn (history
, NULL
)
2115 : nops_for_insn_or_target (history
, ip
));
2119 unsigned long old_frag_offset
;
2122 old_frag
= frag_now
;
2123 old_frag_offset
= frag_now_fix ();
2125 for (i
= 0; i
< nops
; i
++)
2130 listing_prev_line ();
2131 /* We may be at the start of a variant frag. In case we
2132 are, make sure there is enough space for the frag
2133 after the frags created by listing_prev_line. The
2134 argument to frag_grow here must be at least as large
2135 as the argument to all other calls to frag_grow in
2136 this file. We don't have to worry about being in the
2137 middle of a variant frag, because the variants insert
2138 all needed nop instructions themselves. */
2142 mips_move_labels ();
2144 #ifndef NO_ECOFF_DEBUGGING
2145 if (ECOFF_DEBUGGING
)
2146 ecoff_fix_loc (old_frag
, old_frag_offset
);
2150 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2152 /* Work out how many nops in prev_nop_frag are needed by IP. */
2153 int nops
= nops_for_insn_or_target (history
, ip
);
2154 assert (nops
<= prev_nop_frag_holds
);
2156 /* Enforce NOPS as a minimum. */
2157 if (nops
> prev_nop_frag_required
)
2158 prev_nop_frag_required
= nops
;
2160 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2162 /* Settle for the current number of nops. Update the history
2163 accordingly (for the benefit of any future .set reorder code). */
2164 prev_nop_frag
= NULL
;
2165 insert_into_history (prev_nop_frag_since
,
2166 prev_nop_frag_holds
, NOP_INSN
);
2170 /* Allow this instruction to replace one of the nops that was
2171 tentatively added to prev_nop_frag. */
2172 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2173 prev_nop_frag_holds
--;
2174 prev_nop_frag_since
++;
2179 /* The value passed to dwarf2_emit_insn is the distance between
2180 the beginning of the current instruction and the address that
2181 should be recorded in the debug tables. For MIPS16 debug info
2182 we want to use ISA-encoded addresses, so we pass -1 for an
2183 address higher by one than the current. */
2184 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2187 /* Record the frag type before frag_var. */
2188 if (history
[0].frag
)
2189 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2192 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2193 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2194 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2195 && mips_relax_branch
2196 /* Don't try branch relaxation within .set nomacro, or within
2197 .set noat if we use $at for PIC computations. If it turns
2198 out that the branch was out-of-range, we'll get an error. */
2199 && !mips_opts
.warn_about_macros
2200 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2201 && !mips_opts
.mips16
)
2203 relaxed_branch
= TRUE
;
2204 add_relaxed_insn (ip
, (relaxed_branch_length
2206 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2207 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2210 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2211 pinfo
& INSN_COND_BRANCH_LIKELY
,
2212 pinfo
& INSN_WRITE_GPR_31
,
2214 address_expr
->X_add_symbol
,
2215 address_expr
->X_add_number
);
2216 *reloc_type
= BFD_RELOC_UNUSED
;
2218 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2220 /* We need to set up a variant frag. */
2221 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2222 add_relaxed_insn (ip
, 4, 0,
2224 (*reloc_type
- BFD_RELOC_UNUSED
,
2225 mips16_small
, mips16_ext
,
2226 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2227 history
[0].mips16_absolute_jump_p
),
2228 make_expr_symbol (address_expr
), 0);
2230 else if (mips_opts
.mips16
2232 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2234 /* Make sure there is enough room to swap this instruction with
2235 a following jump instruction. */
2237 add_fixed_insn (ip
);
2241 if (mips_opts
.mips16
2242 && mips_opts
.noreorder
2243 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2244 as_warn (_("extended instruction in delay slot"));
2246 if (mips_relax
.sequence
)
2248 /* If we've reached the end of this frag, turn it into a variant
2249 frag and record the information for the instructions we've
2251 if (frag_room () < 4)
2252 relax_close_frag ();
2253 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2256 if (mips_relax
.sequence
!= 2)
2257 mips_macro_warning
.sizes
[0] += 4;
2258 if (mips_relax
.sequence
!= 1)
2259 mips_macro_warning
.sizes
[1] += 4;
2261 if (mips_opts
.mips16
)
2264 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2266 add_fixed_insn (ip
);
2269 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2271 if (address_expr
->X_op
== O_constant
)
2275 switch (*reloc_type
)
2278 ip
->insn_opcode
|= address_expr
->X_add_number
;
2281 case BFD_RELOC_MIPS_HIGHEST
:
2282 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2283 ip
->insn_opcode
|= tmp
& 0xffff;
2286 case BFD_RELOC_MIPS_HIGHER
:
2287 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2288 ip
->insn_opcode
|= tmp
& 0xffff;
2291 case BFD_RELOC_HI16_S
:
2292 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2293 ip
->insn_opcode
|= tmp
& 0xffff;
2296 case BFD_RELOC_HI16
:
2297 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2300 case BFD_RELOC_UNUSED
:
2301 case BFD_RELOC_LO16
:
2302 case BFD_RELOC_MIPS_GOT_DISP
:
2303 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2306 case BFD_RELOC_MIPS_JMP
:
2307 if ((address_expr
->X_add_number
& 3) != 0)
2308 as_bad (_("jump to misaligned address (0x%lx)"),
2309 (unsigned long) address_expr
->X_add_number
);
2310 if (address_expr
->X_add_number
& ~0xfffffff)
2311 as_bad (_("jump address range overflow (0x%lx)"),
2312 (unsigned long) address_expr
->X_add_number
);
2313 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2316 case BFD_RELOC_MIPS16_JMP
:
2317 if ((address_expr
->X_add_number
& 3) != 0)
2318 as_bad (_("jump to misaligned address (0x%lx)"),
2319 (unsigned long) address_expr
->X_add_number
);
2320 if (address_expr
->X_add_number
& ~0xfffffff)
2321 as_bad (_("jump address range overflow (0x%lx)"),
2322 (unsigned long) address_expr
->X_add_number
);
2324 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2325 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2326 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2329 case BFD_RELOC_16_PCREL_S2
:
2336 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2339 reloc_howto_type
*howto
;
2342 /* In a compound relocation, it is the final (outermost)
2343 operator that determines the relocated field. */
2344 for (i
= 1; i
< 3; i
++)
2345 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2348 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2349 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2350 bfd_get_reloc_size (howto
),
2352 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2355 /* These relocations can have an addend that won't fit in
2356 4 octets for 64bit assembly. */
2358 && ! howto
->partial_inplace
2359 && (reloc_type
[0] == BFD_RELOC_16
2360 || reloc_type
[0] == BFD_RELOC_32
2361 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2362 || reloc_type
[0] == BFD_RELOC_HI16_S
2363 || reloc_type
[0] == BFD_RELOC_LO16
2364 || reloc_type
[0] == BFD_RELOC_GPREL16
2365 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2366 || reloc_type
[0] == BFD_RELOC_GPREL32
2367 || reloc_type
[0] == BFD_RELOC_64
2368 || reloc_type
[0] == BFD_RELOC_CTOR
2369 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2370 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2371 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2372 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2373 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2374 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2375 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2376 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2377 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2378 ip
->fixp
[0]->fx_no_overflow
= 1;
2380 if (mips_relax
.sequence
)
2382 if (mips_relax
.first_fixup
== 0)
2383 mips_relax
.first_fixup
= ip
->fixp
[0];
2385 else if (reloc_needs_lo_p (*reloc_type
))
2387 struct mips_hi_fixup
*hi_fixup
;
2389 /* Reuse the last entry if it already has a matching %lo. */
2390 hi_fixup
= mips_hi_fixup_list
;
2392 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2394 hi_fixup
= ((struct mips_hi_fixup
*)
2395 xmalloc (sizeof (struct mips_hi_fixup
)));
2396 hi_fixup
->next
= mips_hi_fixup_list
;
2397 mips_hi_fixup_list
= hi_fixup
;
2399 hi_fixup
->fixp
= ip
->fixp
[0];
2400 hi_fixup
->seg
= now_seg
;
2403 /* Add fixups for the second and third relocations, if given.
2404 Note that the ABI allows the second relocation to be
2405 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2406 moment we only use RSS_UNDEF, but we could add support
2407 for the others if it ever becomes necessary. */
2408 for (i
= 1; i
< 3; i
++)
2409 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2411 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2412 ip
->fixp
[0]->fx_size
, NULL
, 0,
2413 FALSE
, reloc_type
[i
]);
2415 /* Use fx_tcbit to mark compound relocs. */
2416 ip
->fixp
[0]->fx_tcbit
= 1;
2417 ip
->fixp
[i
]->fx_tcbit
= 1;
2423 /* Update the register mask information. */
2424 if (! mips_opts
.mips16
)
2426 if (pinfo
& INSN_WRITE_GPR_D
)
2427 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2428 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2429 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2430 if (pinfo
& INSN_READ_GPR_S
)
2431 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2432 if (pinfo
& INSN_WRITE_GPR_31
)
2433 mips_gprmask
|= 1 << RA
;
2434 if (pinfo
& INSN_WRITE_FPR_D
)
2435 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2436 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2437 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2438 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2439 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2440 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2441 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2442 if (pinfo
& INSN_COP
)
2444 /* We don't keep enough information to sort these cases out.
2445 The itbl support does keep this information however, although
2446 we currently don't support itbl fprmats as part of the cop
2447 instruction. May want to add this support in the future. */
2449 /* Never set the bit for $0, which is always zero. */
2450 mips_gprmask
&= ~1 << 0;
2454 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2455 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2456 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2457 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2458 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2459 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2460 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2461 mips_gprmask
|= 1 << TREG
;
2462 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2463 mips_gprmask
|= 1 << SP
;
2464 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2465 mips_gprmask
|= 1 << RA
;
2466 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2467 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2468 if (pinfo
& MIPS16_INSN_READ_Z
)
2469 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2470 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2471 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2474 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2476 /* Filling the branch delay slot is more complex. We try to
2477 switch the branch with the previous instruction, which we can
2478 do if the previous instruction does not set up a condition
2479 that the branch tests and if the branch is not itself the
2480 target of any branch. */
2481 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2482 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2484 if (mips_optimize
< 2
2485 /* If we have seen .set volatile or .set nomove, don't
2487 || mips_opts
.nomove
!= 0
2488 /* We can't swap if the previous instruction's position
2490 || history
[0].fixed_p
2491 /* If the previous previous insn was in a .set
2492 noreorder, we can't swap. Actually, the MIPS
2493 assembler will swap in this situation. However, gcc
2494 configured -with-gnu-as will generate code like
2500 in which we can not swap the bne and INSN. If gcc is
2501 not configured -with-gnu-as, it does not output the
2503 || history
[1].noreorder_p
2504 /* If the branch is itself the target of a branch, we
2505 can not swap. We cheat on this; all we check for is
2506 whether there is a label on this instruction. If
2507 there are any branches to anything other than a
2508 label, users must use .set noreorder. */
2509 || insn_labels
!= NULL
2510 /* If the previous instruction is in a variant frag
2511 other than this branch's one, we cannot do the swap.
2512 This does not apply to the mips16, which uses variant
2513 frags for different purposes. */
2514 || (! mips_opts
.mips16
2515 && prev_insn_frag_type
== rs_machine_dependent
)
2516 /* If the branch reads the condition codes, we don't
2517 even try to swap, because in the sequence
2522 we can not swap, and I don't feel like handling that
2524 || (! mips_opts
.mips16
2525 && (pinfo
& INSN_READ_COND_CODE
)
2526 && ! cop_interlocks
)
2527 /* Check for conflicts between the branch and the instructions
2528 before the candidate delay slot. */
2529 || nops_for_insn (history
+ 1, ip
) > 0
2530 /* Check for conflicts between the swapped sequence and the
2531 target of the branch. */
2532 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2533 /* We do not swap with a trap instruction, since it
2534 complicates trap handlers to have the trap
2535 instruction be in a delay slot. */
2536 || (prev_pinfo
& INSN_TRAP
)
2537 /* If the branch reads a register that the previous
2538 instruction sets, we can not swap. */
2539 || (! mips_opts
.mips16
2540 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2541 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2543 || (! mips_opts
.mips16
2544 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2545 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2547 || (mips_opts
.mips16
2548 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2550 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2552 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2554 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2556 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2558 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2560 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2561 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2562 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2563 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2564 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2565 && insn_uses_reg (ip
,
2566 MIPS16OP_EXTRACT_REG32R
2567 (history
[0].insn_opcode
),
2569 /* If the branch writes a register that the previous
2570 instruction sets, we can not swap (we know that
2571 branches write only to RD or to $31). */
2572 || (! mips_opts
.mips16
2573 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2574 && (((pinfo
& INSN_WRITE_GPR_D
)
2575 && (EXTRACT_OPERAND (RT
, history
[0])
2576 == EXTRACT_OPERAND (RD
, *ip
)))
2577 || ((pinfo
& INSN_WRITE_GPR_31
)
2578 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2579 || (! mips_opts
.mips16
2580 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2581 && (((pinfo
& INSN_WRITE_GPR_D
)
2582 && (EXTRACT_OPERAND (RD
, history
[0])
2583 == EXTRACT_OPERAND (RD
, *ip
)))
2584 || ((pinfo
& INSN_WRITE_GPR_31
)
2585 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2586 || (mips_opts
.mips16
2587 && (pinfo
& MIPS16_INSN_WRITE_31
)
2588 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2589 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2590 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2592 /* If the branch writes a register that the previous
2593 instruction reads, we can not swap (we know that
2594 branches only write to RD or to $31). */
2595 || (! mips_opts
.mips16
2596 && (pinfo
& INSN_WRITE_GPR_D
)
2597 && insn_uses_reg (&history
[0],
2598 EXTRACT_OPERAND (RD
, *ip
),
2600 || (! mips_opts
.mips16
2601 && (pinfo
& INSN_WRITE_GPR_31
)
2602 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2603 || (mips_opts
.mips16
2604 && (pinfo
& MIPS16_INSN_WRITE_31
)
2605 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2606 /* If one instruction sets a condition code and the
2607 other one uses a condition code, we can not swap. */
2608 || ((pinfo
& INSN_READ_COND_CODE
)
2609 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2610 || ((pinfo
& INSN_WRITE_COND_CODE
)
2611 && (prev_pinfo
& INSN_READ_COND_CODE
))
2612 /* If the previous instruction uses the PC, we can not
2614 || (mips_opts
.mips16
2615 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2616 /* If the previous instruction had a fixup in mips16
2617 mode, we can not swap. This normally means that the
2618 previous instruction was a 4 byte branch anyhow. */
2619 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2620 /* If the previous instruction is a sync, sync.l, or
2621 sync.p, we can not swap. */
2622 || (prev_pinfo
& INSN_SYNC
))
2624 /* We could do even better for unconditional branches to
2625 portions of this object file; we could pick up the
2626 instruction at the destination, put it in the delay
2627 slot, and bump the destination address. */
2628 insert_into_history (0, 1, ip
);
2630 if (mips_relax
.sequence
)
2631 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2635 /* It looks like we can actually do the swap. */
2636 struct mips_cl_insn delay
= history
[0];
2637 if (mips_opts
.mips16
)
2639 know (delay
.frag
== ip
->frag
);
2640 move_insn (ip
, delay
.frag
, delay
.where
);
2641 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2643 else if (relaxed_branch
)
2645 /* Add the delay slot instruction to the end of the
2646 current frag and shrink the fixed part of the
2647 original frag. If the branch occupies the tail of
2648 the latter, move it backwards to cover the gap. */
2649 delay
.frag
->fr_fix
-= 4;
2650 if (delay
.frag
== ip
->frag
)
2651 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2652 add_fixed_insn (&delay
);
2656 move_insn (&delay
, ip
->frag
, ip
->where
);
2657 move_insn (ip
, history
[0].frag
, history
[0].where
);
2661 insert_into_history (0, 1, &delay
);
2664 /* If that was an unconditional branch, forget the previous
2665 insn information. */
2666 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2667 mips_no_prev_insn ();
2669 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2671 /* We don't yet optimize a branch likely. What we should do
2672 is look at the target, copy the instruction found there
2673 into the delay slot, and increment the branch to jump to
2674 the next instruction. */
2675 insert_into_history (0, 1, ip
);
2679 insert_into_history (0, 1, ip
);
2682 insert_into_history (0, 1, ip
);
2684 /* We just output an insn, so the next one doesn't have a label. */
2685 mips_clear_insn_labels ();
2688 /* Forget that there was any previous instruction or label. */
2691 mips_no_prev_insn (void)
2693 prev_nop_frag
= NULL
;
2694 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2695 mips_clear_insn_labels ();
2698 /* This function must be called before we emit something other than
2699 instructions. It is like mips_no_prev_insn except that it inserts
2700 any NOPS that might be needed by previous instructions. */
2703 mips_emit_delays (void)
2705 if (! mips_opts
.noreorder
)
2707 int nops
= nops_for_insn (history
, NULL
);
2711 add_fixed_insn (NOP_INSN
);
2712 mips_move_labels ();
2715 mips_no_prev_insn ();
2718 /* Start a (possibly nested) noreorder block. */
2721 start_noreorder (void)
2723 if (mips_opts
.noreorder
== 0)
2728 /* None of the instructions before the .set noreorder can be moved. */
2729 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2730 history
[i
].fixed_p
= 1;
2732 /* Insert any nops that might be needed between the .set noreorder
2733 block and the previous instructions. We will later remove any
2734 nops that turn out not to be needed. */
2735 nops
= nops_for_insn (history
, NULL
);
2738 if (mips_optimize
!= 0)
2740 /* Record the frag which holds the nop instructions, so
2741 that we can remove them if we don't need them. */
2742 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2743 prev_nop_frag
= frag_now
;
2744 prev_nop_frag_holds
= nops
;
2745 prev_nop_frag_required
= 0;
2746 prev_nop_frag_since
= 0;
2749 for (; nops
> 0; --nops
)
2750 add_fixed_insn (NOP_INSN
);
2752 /* Move on to a new frag, so that it is safe to simply
2753 decrease the size of prev_nop_frag. */
2754 frag_wane (frag_now
);
2756 mips_move_labels ();
2758 mips16_mark_labels ();
2759 mips_clear_insn_labels ();
2761 mips_opts
.noreorder
++;
2762 mips_any_noreorder
= 1;
2765 /* End a nested noreorder block. */
2768 end_noreorder (void)
2770 mips_opts
.noreorder
--;
2771 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2773 /* Commit to inserting prev_nop_frag_required nops and go back to
2774 handling nop insertion the .set reorder way. */
2775 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2776 * (mips_opts
.mips16
? 2 : 4));
2777 insert_into_history (prev_nop_frag_since
,
2778 prev_nop_frag_required
, NOP_INSN
);
2779 prev_nop_frag
= NULL
;
2783 /* Set up global variables for the start of a new macro. */
2788 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2789 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2790 && (history
[0].insn_mo
->pinfo
2791 & (INSN_UNCOND_BRANCH_DELAY
2792 | INSN_COND_BRANCH_DELAY
2793 | INSN_COND_BRANCH_LIKELY
)) != 0);
2796 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2797 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2798 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2801 macro_warning (relax_substateT subtype
)
2803 if (subtype
& RELAX_DELAY_SLOT
)
2804 return _("Macro instruction expanded into multiple instructions"
2805 " in a branch delay slot");
2806 else if (subtype
& RELAX_NOMACRO
)
2807 return _("Macro instruction expanded into multiple instructions");
2812 /* Finish up a macro. Emit warnings as appropriate. */
2817 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2819 relax_substateT subtype
;
2821 /* Set up the relaxation warning flags. */
2823 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2824 subtype
|= RELAX_SECOND_LONGER
;
2825 if (mips_opts
.warn_about_macros
)
2826 subtype
|= RELAX_NOMACRO
;
2827 if (mips_macro_warning
.delay_slot_p
)
2828 subtype
|= RELAX_DELAY_SLOT
;
2830 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2832 /* Either the macro has a single implementation or both
2833 implementations are longer than 4 bytes. Emit the
2835 const char *msg
= macro_warning (subtype
);
2841 /* One implementation might need a warning but the other
2842 definitely doesn't. */
2843 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2848 /* Read a macro's relocation codes from *ARGS and store them in *R.
2849 The first argument in *ARGS will be either the code for a single
2850 relocation or -1 followed by the three codes that make up a
2851 composite relocation. */
2854 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2858 next
= va_arg (*args
, int);
2860 r
[0] = (bfd_reloc_code_real_type
) next
;
2862 for (i
= 0; i
< 3; i
++)
2863 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2866 /* Build an instruction created by a macro expansion. This is passed
2867 a pointer to the count of instructions created so far, an
2868 expression, the name of the instruction to build, an operand format
2869 string, and corresponding arguments. */
2872 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2874 const struct mips_opcode
*mo
;
2875 struct mips_cl_insn insn
;
2876 bfd_reloc_code_real_type r
[3];
2879 va_start (args
, fmt
);
2881 if (mips_opts
.mips16
)
2883 mips16_macro_build (ep
, name
, fmt
, args
);
2888 r
[0] = BFD_RELOC_UNUSED
;
2889 r
[1] = BFD_RELOC_UNUSED
;
2890 r
[2] = BFD_RELOC_UNUSED
;
2891 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2893 assert (strcmp (name
, mo
->name
) == 0);
2895 /* Search until we get a match for NAME. It is assumed here that
2896 macros will never generate MDMX or MIPS-3D instructions. */
2897 while (strcmp (fmt
, mo
->args
) != 0
2898 || mo
->pinfo
== INSN_MACRO
2899 || !OPCODE_IS_MEMBER (mo
,
2901 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2903 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2907 assert (strcmp (name
, mo
->name
) == 0);
2910 create_insn (&insn
, mo
);
2928 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2933 /* Note that in the macro case, these arguments are already
2934 in MSB form. (When handling the instruction in the
2935 non-macro case, these arguments are sizes from which
2936 MSB values must be calculated.) */
2937 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
2943 /* Note that in the macro case, these arguments are already
2944 in MSBD form. (When handling the instruction in the
2945 non-macro case, these arguments are sizes from which
2946 MSBD values must be calculated.) */
2947 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
2958 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
2962 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
2967 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
2973 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
2978 int tmp
= va_arg (args
, int);
2980 INSERT_OPERAND (RT
, insn
, tmp
);
2981 INSERT_OPERAND (RD
, insn
, tmp
);
2987 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
2994 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2998 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3002 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3006 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3010 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3017 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3023 macro_read_relocs (&args
, r
);
3024 assert (*r
== BFD_RELOC_GPREL16
3025 || *r
== BFD_RELOC_MIPS_LITERAL
3026 || *r
== BFD_RELOC_MIPS_HIGHER
3027 || *r
== BFD_RELOC_HI16_S
3028 || *r
== BFD_RELOC_LO16
3029 || *r
== BFD_RELOC_MIPS_GOT16
3030 || *r
== BFD_RELOC_MIPS_CALL16
3031 || *r
== BFD_RELOC_MIPS_GOT_DISP
3032 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3033 || *r
== BFD_RELOC_MIPS_GOT_OFST
3034 || *r
== BFD_RELOC_MIPS_GOT_LO16
3035 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3039 macro_read_relocs (&args
, r
);
3041 && (ep
->X_op
== O_constant
3042 || (ep
->X_op
== O_symbol
3043 && (*r
== BFD_RELOC_MIPS_HIGHEST
3044 || *r
== BFD_RELOC_HI16_S
3045 || *r
== BFD_RELOC_HI16
3046 || *r
== BFD_RELOC_GPREL16
3047 || *r
== BFD_RELOC_MIPS_GOT_HI16
3048 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3052 assert (ep
!= NULL
);
3054 * This allows macro() to pass an immediate expression for
3055 * creating short branches without creating a symbol.
3056 * Note that the expression still might come from the assembly
3057 * input, in which case the value is not checked for range nor
3058 * is a relocation entry generated (yuck).
3060 if (ep
->X_op
== O_constant
)
3062 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3066 *r
= BFD_RELOC_16_PCREL_S2
;
3070 assert (ep
!= NULL
);
3071 *r
= BFD_RELOC_MIPS_JMP
;
3075 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3084 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3086 append_insn (&insn
, ep
, r
);
3090 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3093 struct mips_opcode
*mo
;
3094 struct mips_cl_insn insn
;
3095 bfd_reloc_code_real_type r
[3]
3096 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3098 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3100 assert (strcmp (name
, mo
->name
) == 0);
3102 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3106 assert (strcmp (name
, mo
->name
) == 0);
3109 create_insn (&insn
, mo
);
3127 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3132 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3136 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3140 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3150 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3157 regno
= va_arg (args
, int);
3158 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3159 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3180 assert (ep
!= NULL
);
3182 if (ep
->X_op
!= O_constant
)
3183 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3186 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3187 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3190 *r
= BFD_RELOC_UNUSED
;
3196 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3203 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3205 append_insn (&insn
, ep
, r
);
3209 * Generate a "jalr" instruction with a relocation hint to the called
3210 * function. This occurs in NewABI PIC code.
3213 macro_build_jalr (expressionS
*ep
)
3222 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3224 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3225 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3229 * Generate a "lui" instruction.
3232 macro_build_lui (expressionS
*ep
, int regnum
)
3234 expressionS high_expr
;
3235 const struct mips_opcode
*mo
;
3236 struct mips_cl_insn insn
;
3237 bfd_reloc_code_real_type r
[3]
3238 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3239 const char *name
= "lui";
3240 const char *fmt
= "t,u";
3242 assert (! mips_opts
.mips16
);
3246 if (high_expr
.X_op
== O_constant
)
3248 /* we can compute the instruction now without a relocation entry */
3249 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3251 *r
= BFD_RELOC_UNUSED
;
3255 assert (ep
->X_op
== O_symbol
);
3256 /* _gp_disp is a special case, used from s_cpload.
3257 __gnu_local_gp is used if mips_no_shared. */
3258 assert (mips_pic
== NO_PIC
3260 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3261 || (! mips_in_shared
3262 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3263 "__gnu_local_gp") == 0));
3264 *r
= BFD_RELOC_HI16_S
;
3267 mo
= hash_find (op_hash
, name
);
3268 assert (strcmp (name
, mo
->name
) == 0);
3269 assert (strcmp (fmt
, mo
->args
) == 0);
3270 create_insn (&insn
, mo
);
3272 insn
.insn_opcode
= insn
.insn_mo
->match
;
3273 INSERT_OPERAND (RT
, insn
, regnum
);
3274 if (*r
== BFD_RELOC_UNUSED
)
3276 insn
.insn_opcode
|= high_expr
.X_add_number
;
3277 append_insn (&insn
, NULL
, r
);
3280 append_insn (&insn
, &high_expr
, r
);
3283 /* Generate a sequence of instructions to do a load or store from a constant
3284 offset off of a base register (breg) into/from a target register (treg),
3285 using AT if necessary. */
3287 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3288 int treg
, int breg
, int dbl
)
3290 assert (ep
->X_op
== O_constant
);
3292 /* Sign-extending 32-bit constants makes their handling easier. */
3293 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3294 == ~((bfd_vma
) 0x7fffffff)))
3296 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3297 as_bad (_("constant too large"));
3299 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3303 /* Right now, this routine can only handle signed 32-bit constants. */
3304 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3305 as_warn (_("operand overflow"));
3307 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3309 /* Signed 16-bit offset will fit in the op. Easy! */
3310 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3314 /* 32-bit offset, need multiple instructions and AT, like:
3315 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3316 addu $tempreg,$tempreg,$breg
3317 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3318 to handle the complete offset. */
3319 macro_build_lui (ep
, AT
);
3320 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3321 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3324 as_bad (_("Macro used $at after \".set noat\""));
3329 * Generates code to set the $at register to true (one)
3330 * if reg is less than the immediate expression.
3333 set_at (int reg
, int unsignedp
)
3335 if (imm_expr
.X_op
== O_constant
3336 && imm_expr
.X_add_number
>= -0x8000
3337 && imm_expr
.X_add_number
< 0x8000)
3338 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3339 AT
, reg
, BFD_RELOC_LO16
);
3342 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3343 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3348 normalize_constant_expr (expressionS
*ex
)
3350 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3351 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3355 /* Warn if an expression is not a constant. */
3358 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3360 if (ex
->X_op
== O_big
)
3361 as_bad (_("unsupported large constant"));
3362 else if (ex
->X_op
!= O_constant
)
3363 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3365 normalize_constant_expr (ex
);
3368 /* Count the leading zeroes by performing a binary chop. This is a
3369 bulky bit of source, but performance is a LOT better for the
3370 majority of values than a simple loop to count the bits:
3371 for (lcnt = 0; (lcnt < 32); lcnt++)
3372 if ((v) & (1 << (31 - lcnt)))
3374 However it is not code size friendly, and the gain will drop a bit
3375 on certain cached systems.
3377 #define COUNT_TOP_ZEROES(v) \
3378 (((v) & ~0xffff) == 0 \
3379 ? ((v) & ~0xff) == 0 \
3380 ? ((v) & ~0xf) == 0 \
3381 ? ((v) & ~0x3) == 0 \
3382 ? ((v) & ~0x1) == 0 \
3387 : ((v) & ~0x7) == 0 \
3390 : ((v) & ~0x3f) == 0 \
3391 ? ((v) & ~0x1f) == 0 \
3394 : ((v) & ~0x7f) == 0 \
3397 : ((v) & ~0xfff) == 0 \
3398 ? ((v) & ~0x3ff) == 0 \
3399 ? ((v) & ~0x1ff) == 0 \
3402 : ((v) & ~0x7ff) == 0 \
3405 : ((v) & ~0x3fff) == 0 \
3406 ? ((v) & ~0x1fff) == 0 \
3409 : ((v) & ~0x7fff) == 0 \
3412 : ((v) & ~0xffffff) == 0 \
3413 ? ((v) & ~0xfffff) == 0 \
3414 ? ((v) & ~0x3ffff) == 0 \
3415 ? ((v) & ~0x1ffff) == 0 \
3418 : ((v) & ~0x7ffff) == 0 \
3421 : ((v) & ~0x3fffff) == 0 \
3422 ? ((v) & ~0x1fffff) == 0 \
3425 : ((v) & ~0x7fffff) == 0 \
3428 : ((v) & ~0xfffffff) == 0 \
3429 ? ((v) & ~0x3ffffff) == 0 \
3430 ? ((v) & ~0x1ffffff) == 0 \
3433 : ((v) & ~0x7ffffff) == 0 \
3436 : ((v) & ~0x3fffffff) == 0 \
3437 ? ((v) & ~0x1fffffff) == 0 \
3440 : ((v) & ~0x7fffffff) == 0 \
3445 * This routine generates the least number of instructions necessary to load
3446 * an absolute expression value into a register.
3449 load_register (int reg
, expressionS
*ep
, int dbl
)
3452 expressionS hi32
, lo32
;
3454 if (ep
->X_op
!= O_big
)
3456 assert (ep
->X_op
== O_constant
);
3458 /* Sign-extending 32-bit constants makes their handling easier. */
3459 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3460 == ~((bfd_vma
) 0x7fffffff)))
3462 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3463 as_bad (_("constant too large"));
3465 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3469 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3471 /* We can handle 16 bit signed values with an addiu to
3472 $zero. No need to ever use daddiu here, since $zero and
3473 the result are always correct in 32 bit mode. */
3474 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3477 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3479 /* We can handle 16 bit unsigned values with an ori to
3481 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3484 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3486 /* 32 bit values require an lui. */
3487 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3488 if ((ep
->X_add_number
& 0xffff) != 0)
3489 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3494 /* The value is larger than 32 bits. */
3496 if (HAVE_32BIT_GPRS
)
3498 as_bad (_("Number (0x%lx) larger than 32 bits"),
3499 (unsigned long) ep
->X_add_number
);
3500 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3504 if (ep
->X_op
!= O_big
)
3507 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3508 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3509 hi32
.X_add_number
&= 0xffffffff;
3511 lo32
.X_add_number
&= 0xffffffff;
3515 assert (ep
->X_add_number
> 2);
3516 if (ep
->X_add_number
== 3)
3517 generic_bignum
[3] = 0;
3518 else if (ep
->X_add_number
> 4)
3519 as_bad (_("Number larger than 64 bits"));
3520 lo32
.X_op
= O_constant
;
3521 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3522 hi32
.X_op
= O_constant
;
3523 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3526 if (hi32
.X_add_number
== 0)
3531 unsigned long hi
, lo
;
3533 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3535 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3537 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3540 if (lo32
.X_add_number
& 0x80000000)
3542 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3543 if (lo32
.X_add_number
& 0xffff)
3544 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3549 /* Check for 16bit shifted constant. We know that hi32 is
3550 non-zero, so start the mask on the first bit of the hi32
3555 unsigned long himask
, lomask
;
3559 himask
= 0xffff >> (32 - shift
);
3560 lomask
= (0xffff << shift
) & 0xffffffff;
3564 himask
= 0xffff << (shift
- 32);
3567 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3568 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3572 tmp
.X_op
= O_constant
;
3574 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3575 | (lo32
.X_add_number
>> shift
));
3577 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3578 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3579 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3580 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3585 while (shift
<= (64 - 16));
3587 /* Find the bit number of the lowest one bit, and store the
3588 shifted value in hi/lo. */
3589 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3590 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3594 while ((lo
& 1) == 0)
3599 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3605 while ((hi
& 1) == 0)
3614 /* Optimize if the shifted value is a (power of 2) - 1. */
3615 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3616 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3618 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3623 /* This instruction will set the register to be all
3625 tmp
.X_op
= O_constant
;
3626 tmp
.X_add_number
= (offsetT
) -1;
3627 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3631 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3632 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3634 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3635 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3640 /* Sign extend hi32 before calling load_register, because we can
3641 generally get better code when we load a sign extended value. */
3642 if ((hi32
.X_add_number
& 0x80000000) != 0)
3643 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3644 load_register (reg
, &hi32
, 0);
3647 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3651 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3659 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3661 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3662 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3668 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3672 mid16
.X_add_number
>>= 16;
3673 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3674 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3677 if ((lo32
.X_add_number
& 0xffff) != 0)
3678 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3682 load_delay_nop (void)
3684 if (!gpr_interlocks
)
3685 macro_build (NULL
, "nop", "");
3688 /* Load an address into a register. */
3691 load_address (int reg
, expressionS
*ep
, int *used_at
)
3693 if (ep
->X_op
!= O_constant
3694 && ep
->X_op
!= O_symbol
)
3696 as_bad (_("expression too complex"));
3697 ep
->X_op
= O_constant
;
3700 if (ep
->X_op
== O_constant
)
3702 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3706 if (mips_pic
== NO_PIC
)
3708 /* If this is a reference to a GP relative symbol, we want
3709 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3711 lui $reg,<sym> (BFD_RELOC_HI16_S)
3712 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3713 If we have an addend, we always use the latter form.
3715 With 64bit address space and a usable $at we want
3716 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3717 lui $at,<sym> (BFD_RELOC_HI16_S)
3718 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3719 daddiu $at,<sym> (BFD_RELOC_LO16)
3723 If $at is already in use, we use a path which is suboptimal
3724 on superscalar processors.
3725 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3726 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3728 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3730 daddiu $reg,<sym> (BFD_RELOC_LO16)
3732 For GP relative symbols in 64bit address space we can use
3733 the same sequence as in 32bit address space. */
3734 if (HAVE_64BIT_SYMBOLS
)
3736 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3737 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3739 relax_start (ep
->X_add_symbol
);
3740 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3741 mips_gp_register
, BFD_RELOC_GPREL16
);
3745 if (*used_at
== 0 && !mips_opts
.noat
)
3747 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3748 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3749 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3750 BFD_RELOC_MIPS_HIGHER
);
3751 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3752 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3753 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3758 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3759 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3760 BFD_RELOC_MIPS_HIGHER
);
3761 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3762 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3763 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3764 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3767 if (mips_relax
.sequence
)
3772 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3773 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3775 relax_start (ep
->X_add_symbol
);
3776 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3777 mips_gp_register
, BFD_RELOC_GPREL16
);
3780 macro_build_lui (ep
, reg
);
3781 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3782 reg
, reg
, BFD_RELOC_LO16
);
3783 if (mips_relax
.sequence
)
3787 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3791 /* If this is a reference to an external symbol, we want
3792 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3794 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3796 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3797 If there is a constant, it must be added in after.
3799 If we have NewABI, we want
3800 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3801 unless we're referencing a global symbol with a non-zero
3802 offset, in which case cst must be added separately. */
3805 if (ep
->X_add_number
)
3807 ex
.X_add_number
= ep
->X_add_number
;
3808 ep
->X_add_number
= 0;
3809 relax_start (ep
->X_add_symbol
);
3810 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3811 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3812 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3813 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3814 ex
.X_op
= O_constant
;
3815 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3816 reg
, reg
, BFD_RELOC_LO16
);
3817 ep
->X_add_number
= ex
.X_add_number
;
3820 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3821 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3822 if (mips_relax
.sequence
)
3827 ex
.X_add_number
= ep
->X_add_number
;
3828 ep
->X_add_number
= 0;
3829 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3830 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3832 relax_start (ep
->X_add_symbol
);
3834 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3838 if (ex
.X_add_number
!= 0)
3840 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3841 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3842 ex
.X_op
= O_constant
;
3843 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3844 reg
, reg
, BFD_RELOC_LO16
);
3848 else if (mips_pic
== SVR4_PIC
)
3852 /* This is the large GOT case. If this is a reference to an
3853 external symbol, we want
3854 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3856 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3858 Otherwise, for a reference to a local symbol in old ABI, we want
3859 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3861 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3862 If there is a constant, it must be added in after.
3864 In the NewABI, for local symbols, with or without offsets, we want:
3865 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3866 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3870 ex
.X_add_number
= ep
->X_add_number
;
3871 ep
->X_add_number
= 0;
3872 relax_start (ep
->X_add_symbol
);
3873 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3874 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3875 reg
, reg
, mips_gp_register
);
3876 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3877 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3878 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3879 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3880 else if (ex
.X_add_number
)
3882 ex
.X_op
= O_constant
;
3883 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3887 ep
->X_add_number
= ex
.X_add_number
;
3889 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3890 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3891 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3892 BFD_RELOC_MIPS_GOT_OFST
);
3897 ex
.X_add_number
= ep
->X_add_number
;
3898 ep
->X_add_number
= 0;
3899 relax_start (ep
->X_add_symbol
);
3900 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3901 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3902 reg
, reg
, mips_gp_register
);
3903 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3904 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3906 if (reg_needs_delay (mips_gp_register
))
3908 /* We need a nop before loading from $gp. This special
3909 check is required because the lui which starts the main
3910 instruction stream does not refer to $gp, and so will not
3911 insert the nop which may be required. */
3912 macro_build (NULL
, "nop", "");
3914 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3915 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3917 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3921 if (ex
.X_add_number
!= 0)
3923 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3924 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3925 ex
.X_op
= O_constant
;
3926 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3934 if (mips_opts
.noat
&& *used_at
== 1)
3935 as_bad (_("Macro used $at after \".set noat\""));
3938 /* Move the contents of register SOURCE into register DEST. */
3941 move_register (int dest
, int source
)
3943 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
3947 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
3948 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
3949 The two alternatives are:
3951 Global symbol Local sybmol
3952 ------------- ------------
3953 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
3955 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
3957 load_got_offset emits the first instruction and add_got_offset
3958 emits the second for a 16-bit offset or add_got_offset_hilo emits
3959 a sequence to add a 32-bit offset using a scratch register. */
3962 load_got_offset (int dest
, expressionS
*local
)
3967 global
.X_add_number
= 0;
3969 relax_start (local
->X_add_symbol
);
3970 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
3971 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3973 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
3974 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3979 add_got_offset (int dest
, expressionS
*local
)
3983 global
.X_op
= O_constant
;
3984 global
.X_op_symbol
= NULL
;
3985 global
.X_add_symbol
= NULL
;
3986 global
.X_add_number
= local
->X_add_number
;
3988 relax_start (local
->X_add_symbol
);
3989 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
3990 dest
, dest
, BFD_RELOC_LO16
);
3992 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
3997 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4000 int hold_mips_optimize
;
4002 global
.X_op
= O_constant
;
4003 global
.X_op_symbol
= NULL
;
4004 global
.X_add_symbol
= NULL
;
4005 global
.X_add_number
= local
->X_add_number
;
4007 relax_start (local
->X_add_symbol
);
4008 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4010 /* Set mips_optimize around the lui instruction to avoid
4011 inserting an unnecessary nop after the lw. */
4012 hold_mips_optimize
= mips_optimize
;
4014 macro_build_lui (&global
, tmp
);
4015 mips_optimize
= hold_mips_optimize
;
4016 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4019 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4024 * This routine implements the seemingly endless macro or synthesized
4025 * instructions and addressing modes in the mips assembly language. Many
4026 * of these macros are simple and are similar to each other. These could
4027 * probably be handled by some kind of table or grammar approach instead of
4028 * this verbose method. Others are not simple macros but are more like
4029 * optimizing code generation.
4030 * One interesting optimization is when several store macros appear
4031 * consecutively that would load AT with the upper half of the same address.
4032 * The ensuing load upper instructions are ommited. This implies some kind
4033 * of global optimization. We currently only optimize within a single macro.
4034 * For many of the load and store macros if the address is specified as a
4035 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4036 * first load register 'at' with zero and use it as the base register. The
4037 * mips assembler simply uses register $zero. Just one tiny optimization
4041 macro (struct mips_cl_insn
*ip
)
4043 register int treg
, sreg
, dreg
, breg
;
4059 bfd_reloc_code_real_type r
;
4060 int hold_mips_optimize
;
4062 assert (! mips_opts
.mips16
);
4064 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4065 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4066 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4067 mask
= ip
->insn_mo
->mask
;
4069 expr1
.X_op
= O_constant
;
4070 expr1
.X_op_symbol
= NULL
;
4071 expr1
.X_add_symbol
= NULL
;
4072 expr1
.X_add_number
= 1;
4086 expr1
.X_add_number
= 8;
4087 macro_build (&expr1
, "bgez", "s,p", sreg
);
4089 macro_build (NULL
, "nop", "", 0);
4091 move_register (dreg
, sreg
);
4092 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4115 if (imm_expr
.X_op
== O_constant
4116 && imm_expr
.X_add_number
>= -0x8000
4117 && imm_expr
.X_add_number
< 0x8000)
4119 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4123 load_register (AT
, &imm_expr
, dbl
);
4124 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4143 if (imm_expr
.X_op
== O_constant
4144 && imm_expr
.X_add_number
>= 0
4145 && imm_expr
.X_add_number
< 0x10000)
4147 if (mask
!= M_NOR_I
)
4148 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4151 macro_build (&imm_expr
, "ori", "t,r,i",
4152 treg
, sreg
, BFD_RELOC_LO16
);
4153 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4159 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4160 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4177 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4179 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4183 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4184 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4192 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4197 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4201 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4202 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4208 /* check for > max integer */
4209 maxnum
= 0x7fffffff;
4210 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4217 if (imm_expr
.X_op
== O_constant
4218 && imm_expr
.X_add_number
>= maxnum
4219 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4222 /* result is always false */
4224 macro_build (NULL
, "nop", "", 0);
4226 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4229 if (imm_expr
.X_op
!= O_constant
)
4230 as_bad (_("Unsupported large constant"));
4231 ++imm_expr
.X_add_number
;
4235 if (mask
== M_BGEL_I
)
4237 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4239 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4242 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4244 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4247 maxnum
= 0x7fffffff;
4248 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4255 maxnum
= - maxnum
- 1;
4256 if (imm_expr
.X_op
== O_constant
4257 && imm_expr
.X_add_number
<= maxnum
4258 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4261 /* result is always true */
4262 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4263 macro_build (&offset_expr
, "b", "p");
4268 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4278 macro_build (&offset_expr
, likely
? "beql" : "beq",
4283 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4284 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4292 && imm_expr
.X_op
== O_constant
4293 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4295 if (imm_expr
.X_op
!= O_constant
)
4296 as_bad (_("Unsupported large constant"));
4297 ++imm_expr
.X_add_number
;
4301 if (mask
== M_BGEUL_I
)
4303 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4305 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4307 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4313 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4321 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4326 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4330 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4331 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4339 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4346 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4347 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4355 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4360 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4364 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4365 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4371 maxnum
= 0x7fffffff;
4372 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4379 if (imm_expr
.X_op
== O_constant
4380 && imm_expr
.X_add_number
>= maxnum
4381 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4383 if (imm_expr
.X_op
!= O_constant
)
4384 as_bad (_("Unsupported large constant"));
4385 ++imm_expr
.X_add_number
;
4389 if (mask
== M_BLTL_I
)
4391 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4393 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4396 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4398 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4403 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4411 macro_build (&offset_expr
, likely
? "beql" : "beq",
4418 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4419 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4427 && imm_expr
.X_op
== O_constant
4428 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4430 if (imm_expr
.X_op
!= O_constant
)
4431 as_bad (_("Unsupported large constant"));
4432 ++imm_expr
.X_add_number
;
4436 if (mask
== M_BLTUL_I
)
4438 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4440 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4442 macro_build (&offset_expr
, likely
? "beql" : "beq",
4448 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4456 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4461 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4465 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4466 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4476 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4481 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4482 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4490 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4492 as_bad (_("Unsupported large constant"));
4497 pos
= (unsigned long) imm_expr
.X_add_number
;
4498 size
= (unsigned long) imm2_expr
.X_add_number
;
4503 as_bad (_("Improper position (%lu)"), pos
);
4506 if (size
== 0 || size
> 64
4507 || (pos
+ size
- 1) > 63)
4509 as_bad (_("Improper extract size (%lu, position %lu)"),
4514 if (size
<= 32 && pos
< 32)
4519 else if (size
<= 32)
4529 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4538 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4540 as_bad (_("Unsupported large constant"));
4545 pos
= (unsigned long) imm_expr
.X_add_number
;
4546 size
= (unsigned long) imm2_expr
.X_add_number
;
4551 as_bad (_("Improper position (%lu)"), pos
);
4554 if (size
== 0 || size
> 64
4555 || (pos
+ size
- 1) > 63)
4557 as_bad (_("Improper insert size (%lu, position %lu)"),
4562 if (pos
< 32 && (pos
+ size
- 1) < 32)
4577 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4594 as_warn (_("Divide by zero."));
4596 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4598 macro_build (NULL
, "break", "c", 7);
4605 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4606 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4610 expr1
.X_add_number
= 8;
4611 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4612 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4613 macro_build (NULL
, "break", "c", 7);
4615 expr1
.X_add_number
= -1;
4617 load_register (AT
, &expr1
, dbl
);
4618 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4619 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4622 expr1
.X_add_number
= 1;
4623 load_register (AT
, &expr1
, dbl
);
4624 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4628 expr1
.X_add_number
= 0x80000000;
4629 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4633 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4634 /* We want to close the noreorder block as soon as possible, so
4635 that later insns are available for delay slot filling. */
4640 expr1
.X_add_number
= 8;
4641 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4642 macro_build (NULL
, "nop", "", 0);
4644 /* We want to close the noreorder block as soon as possible, so
4645 that later insns are available for delay slot filling. */
4648 macro_build (NULL
, "break", "c", 6);
4650 macro_build (NULL
, s
, "d", dreg
);
4689 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4691 as_warn (_("Divide by zero."));
4693 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4695 macro_build (NULL
, "break", "c", 7);
4698 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4700 if (strcmp (s2
, "mflo") == 0)
4701 move_register (dreg
, sreg
);
4703 move_register (dreg
, 0);
4706 if (imm_expr
.X_op
== O_constant
4707 && imm_expr
.X_add_number
== -1
4708 && s
[strlen (s
) - 1] != 'u')
4710 if (strcmp (s2
, "mflo") == 0)
4712 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4715 move_register (dreg
, 0);
4720 load_register (AT
, &imm_expr
, dbl
);
4721 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4722 macro_build (NULL
, s2
, "d", dreg
);
4744 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4745 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4746 /* We want to close the noreorder block as soon as possible, so
4747 that later insns are available for delay slot filling. */
4752 expr1
.X_add_number
= 8;
4753 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4754 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4756 /* We want to close the noreorder block as soon as possible, so
4757 that later insns are available for delay slot filling. */
4759 macro_build (NULL
, "break", "c", 7);
4761 macro_build (NULL
, s2
, "d", dreg
);
4773 /* Load the address of a symbol into a register. If breg is not
4774 zero, we then add a base register to it. */
4776 if (dbl
&& HAVE_32BIT_GPRS
)
4777 as_warn (_("dla used to load 32-bit register"));
4779 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4780 as_warn (_("la used to load 64-bit address"));
4782 if (offset_expr
.X_op
== O_constant
4783 && offset_expr
.X_add_number
>= -0x8000
4784 && offset_expr
.X_add_number
< 0x8000)
4786 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4787 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4791 if (!mips_opts
.noat
&& (treg
== breg
))
4801 if (offset_expr
.X_op
!= O_symbol
4802 && offset_expr
.X_op
!= O_constant
)
4804 as_bad (_("expression too complex"));
4805 offset_expr
.X_op
= O_constant
;
4808 if (offset_expr
.X_op
== O_constant
)
4809 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4810 else if (mips_pic
== NO_PIC
)
4812 /* If this is a reference to a GP relative symbol, we want
4813 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4815 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4816 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4817 If we have a constant, we need two instructions anyhow,
4818 so we may as well always use the latter form.
4820 With 64bit address space and a usable $at we want
4821 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4822 lui $at,<sym> (BFD_RELOC_HI16_S)
4823 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4824 daddiu $at,<sym> (BFD_RELOC_LO16)
4826 daddu $tempreg,$tempreg,$at
4828 If $at is already in use, we use a path which is suboptimal
4829 on superscalar processors.
4830 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4831 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4833 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4835 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4837 For GP relative symbols in 64bit address space we can use
4838 the same sequence as in 32bit address space. */
4839 if (HAVE_64BIT_SYMBOLS
)
4841 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4842 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4844 relax_start (offset_expr
.X_add_symbol
);
4845 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4846 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4850 if (used_at
== 0 && !mips_opts
.noat
)
4852 macro_build (&offset_expr
, "lui", "t,u",
4853 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4854 macro_build (&offset_expr
, "lui", "t,u",
4855 AT
, BFD_RELOC_HI16_S
);
4856 macro_build (&offset_expr
, "daddiu", "t,r,j",
4857 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4858 macro_build (&offset_expr
, "daddiu", "t,r,j",
4859 AT
, AT
, BFD_RELOC_LO16
);
4860 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4861 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4866 macro_build (&offset_expr
, "lui", "t,u",
4867 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4868 macro_build (&offset_expr
, "daddiu", "t,r,j",
4869 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4870 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4871 macro_build (&offset_expr
, "daddiu", "t,r,j",
4872 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4873 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4874 macro_build (&offset_expr
, "daddiu", "t,r,j",
4875 tempreg
, tempreg
, BFD_RELOC_LO16
);
4878 if (mips_relax
.sequence
)
4883 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4884 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4886 relax_start (offset_expr
.X_add_symbol
);
4887 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4888 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4891 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4892 as_bad (_("offset too large"));
4893 macro_build_lui (&offset_expr
, tempreg
);
4894 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4895 tempreg
, tempreg
, BFD_RELOC_LO16
);
4896 if (mips_relax
.sequence
)
4900 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4902 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4904 /* If this is a reference to an external symbol, and there
4905 is no constant, we want
4906 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4907 or for lca or if tempreg is PIC_CALL_REG
4908 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4909 For a local symbol, we want
4910 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4912 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4914 If we have a small constant, and this is a reference to
4915 an external symbol, we want
4916 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4918 addiu $tempreg,$tempreg,<constant>
4919 For a local symbol, we want the same instruction
4920 sequence, but we output a BFD_RELOC_LO16 reloc on the
4923 If we have a large constant, and this is a reference to
4924 an external symbol, we want
4925 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4926 lui $at,<hiconstant>
4927 addiu $at,$at,<loconstant>
4928 addu $tempreg,$tempreg,$at
4929 For a local symbol, we want the same instruction
4930 sequence, but we output a BFD_RELOC_LO16 reloc on the
4934 if (offset_expr
.X_add_number
== 0)
4936 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
4937 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4939 relax_start (offset_expr
.X_add_symbol
);
4940 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
4941 lw_reloc_type
, mips_gp_register
);
4944 /* We're going to put in an addu instruction using
4945 tempreg, so we may as well insert the nop right
4950 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
4951 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4953 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4954 tempreg
, tempreg
, BFD_RELOC_LO16
);
4956 /* FIXME: If breg == 0, and the next instruction uses
4957 $tempreg, then if this variant case is used an extra
4958 nop will be generated. */
4960 else if (offset_expr
.X_add_number
>= -0x8000
4961 && offset_expr
.X_add_number
< 0x8000)
4963 load_got_offset (tempreg
, &offset_expr
);
4965 add_got_offset (tempreg
, &offset_expr
);
4969 expr1
.X_add_number
= offset_expr
.X_add_number
;
4970 offset_expr
.X_add_number
=
4971 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
4972 load_got_offset (tempreg
, &offset_expr
);
4973 offset_expr
.X_add_number
= expr1
.X_add_number
;
4974 /* If we are going to add in a base register, and the
4975 target register and the base register are the same,
4976 then we are using AT as a temporary register. Since
4977 we want to load the constant into AT, we add our
4978 current AT (from the global offset table) and the
4979 register into the register now, and pretend we were
4980 not using a base register. */
4984 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4989 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
4993 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
4995 int add_breg_early
= 0;
4997 /* If this is a reference to an external, and there is no
4998 constant, or local symbol (*), with or without a
5000 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5001 or for lca or if tempreg is PIC_CALL_REG
5002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5004 If we have a small constant, and this is a reference to
5005 an external symbol, we want
5006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5007 addiu $tempreg,$tempreg,<constant>
5009 If we have a large constant, and this is a reference to
5010 an external symbol, we want
5011 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5012 lui $at,<hiconstant>
5013 addiu $at,$at,<loconstant>
5014 addu $tempreg,$tempreg,$at
5016 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5017 local symbols, even though it introduces an additional
5020 if (offset_expr
.X_add_number
)
5022 expr1
.X_add_number
= offset_expr
.X_add_number
;
5023 offset_expr
.X_add_number
= 0;
5025 relax_start (offset_expr
.X_add_symbol
);
5026 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5027 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5029 if (expr1
.X_add_number
>= -0x8000
5030 && expr1
.X_add_number
< 0x8000)
5032 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5033 tempreg
, tempreg
, BFD_RELOC_LO16
);
5035 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5039 /* If we are going to add in a base register, and the
5040 target register and the base register are the same,
5041 then we are using AT as a temporary register. Since
5042 we want to load the constant into AT, we add our
5043 current AT (from the global offset table) and the
5044 register into the register now, and pretend we were
5045 not using a base register. */
5050 assert (tempreg
== AT
);
5051 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5057 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5058 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5064 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5067 offset_expr
.X_add_number
= expr1
.X_add_number
;
5069 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5070 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5073 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5074 treg
, tempreg
, breg
);
5080 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5082 relax_start (offset_expr
.X_add_symbol
);
5083 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5084 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5086 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5087 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5092 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5093 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5096 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5099 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5100 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5101 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5103 /* This is the large GOT case. If this is a reference to an
5104 external symbol, and there is no constant, we want
5105 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5106 addu $tempreg,$tempreg,$gp
5107 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5108 or for lca or if tempreg is PIC_CALL_REG
5109 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5110 addu $tempreg,$tempreg,$gp
5111 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5112 For a local symbol, we want
5113 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5115 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5117 If we have a small constant, and this is a reference to
5118 an external symbol, we want
5119 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5120 addu $tempreg,$tempreg,$gp
5121 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5123 addiu $tempreg,$tempreg,<constant>
5124 For a local symbol, we want
5125 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5127 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5129 If we have a large constant, and this is a reference to
5130 an external symbol, we want
5131 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5132 addu $tempreg,$tempreg,$gp
5133 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5134 lui $at,<hiconstant>
5135 addiu $at,$at,<loconstant>
5136 addu $tempreg,$tempreg,$at
5137 For a local symbol, we want
5138 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5139 lui $at,<hiconstant>
5140 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5141 addu $tempreg,$tempreg,$at
5144 expr1
.X_add_number
= offset_expr
.X_add_number
;
5145 offset_expr
.X_add_number
= 0;
5146 relax_start (offset_expr
.X_add_symbol
);
5147 gpdelay
= reg_needs_delay (mips_gp_register
);
5148 if (expr1
.X_add_number
== 0 && breg
== 0
5149 && (call
|| tempreg
== PIC_CALL_REG
))
5151 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5152 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5154 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5155 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5156 tempreg
, tempreg
, mips_gp_register
);
5157 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5158 tempreg
, lw_reloc_type
, tempreg
);
5159 if (expr1
.X_add_number
== 0)
5163 /* We're going to put in an addu instruction using
5164 tempreg, so we may as well insert the nop right
5169 else if (expr1
.X_add_number
>= -0x8000
5170 && expr1
.X_add_number
< 0x8000)
5173 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5174 tempreg
, tempreg
, BFD_RELOC_LO16
);
5180 /* If we are going to add in a base register, and the
5181 target register and the base register are the same,
5182 then we are using AT as a temporary register. Since
5183 we want to load the constant into AT, we add our
5184 current AT (from the global offset table) and the
5185 register into the register now, and pretend we were
5186 not using a base register. */
5191 assert (tempreg
== AT
);
5193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5198 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5199 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5203 offset_expr
.X_add_number
=
5204 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5209 /* This is needed because this instruction uses $gp, but
5210 the first instruction on the main stream does not. */
5211 macro_build (NULL
, "nop", "");
5214 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5215 local_reloc_type
, mips_gp_register
);
5216 if (expr1
.X_add_number
>= -0x8000
5217 && expr1
.X_add_number
< 0x8000)
5220 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5221 tempreg
, tempreg
, BFD_RELOC_LO16
);
5222 /* FIXME: If add_number is 0, and there was no base
5223 register, the external symbol case ended with a load,
5224 so if the symbol turns out to not be external, and
5225 the next instruction uses tempreg, an unnecessary nop
5226 will be inserted. */
5232 /* We must add in the base register now, as in the
5233 external symbol case. */
5234 assert (tempreg
== AT
);
5236 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5239 /* We set breg to 0 because we have arranged to add
5240 it in in both cases. */
5244 macro_build_lui (&expr1
, AT
);
5245 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5246 AT
, AT
, BFD_RELOC_LO16
);
5247 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5248 tempreg
, tempreg
, AT
);
5253 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5255 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5256 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5257 int add_breg_early
= 0;
5259 /* This is the large GOT case. If this is a reference to an
5260 external symbol, and there is no constant, we want
5261 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5262 add $tempreg,$tempreg,$gp
5263 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5264 or for lca or if tempreg is PIC_CALL_REG
5265 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5266 add $tempreg,$tempreg,$gp
5267 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5269 If we have a small constant, and this is a reference to
5270 an external symbol, we want
5271 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5272 add $tempreg,$tempreg,$gp
5273 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5274 addi $tempreg,$tempreg,<constant>
5276 If we have a large constant, and this is a reference to
5277 an external symbol, we want
5278 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5279 addu $tempreg,$tempreg,$gp
5280 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5281 lui $at,<hiconstant>
5282 addi $at,$at,<loconstant>
5283 add $tempreg,$tempreg,$at
5285 If we have NewABI, and we know it's a local symbol, we want
5286 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5287 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5288 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5290 relax_start (offset_expr
.X_add_symbol
);
5292 expr1
.X_add_number
= offset_expr
.X_add_number
;
5293 offset_expr
.X_add_number
= 0;
5295 if (expr1
.X_add_number
== 0 && breg
== 0
5296 && (call
|| tempreg
== PIC_CALL_REG
))
5298 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5299 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5301 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5302 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5303 tempreg
, tempreg
, mips_gp_register
);
5304 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5305 tempreg
, lw_reloc_type
, tempreg
);
5307 if (expr1
.X_add_number
== 0)
5309 else if (expr1
.X_add_number
>= -0x8000
5310 && expr1
.X_add_number
< 0x8000)
5312 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5313 tempreg
, tempreg
, BFD_RELOC_LO16
);
5315 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5319 /* If we are going to add in a base register, and the
5320 target register and the base register are the same,
5321 then we are using AT as a temporary register. Since
5322 we want to load the constant into AT, we add our
5323 current AT (from the global offset table) and the
5324 register into the register now, and pretend we were
5325 not using a base register. */
5330 assert (tempreg
== AT
);
5331 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5337 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5338 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5343 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5346 offset_expr
.X_add_number
= expr1
.X_add_number
;
5347 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5348 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5349 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5350 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5353 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5354 treg
, tempreg
, breg
);
5364 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5368 /* The j instruction may not be used in PIC code, since it
5369 requires an absolute address. We convert it to a b
5371 if (mips_pic
== NO_PIC
)
5372 macro_build (&offset_expr
, "j", "a");
5374 macro_build (&offset_expr
, "b", "p");
5377 /* The jal instructions must be handled as macros because when
5378 generating PIC code they expand to multi-instruction
5379 sequences. Normally they are simple instructions. */
5384 if (mips_pic
== NO_PIC
)
5385 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5386 else if (mips_pic
== SVR4_PIC
)
5388 if (sreg
!= PIC_CALL_REG
)
5389 as_warn (_("MIPS PIC call to register other than $25"));
5391 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5394 if (mips_cprestore_offset
< 0)
5395 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5398 if (! mips_frame_reg_valid
)
5400 as_warn (_("No .frame pseudo-op used in PIC code"));
5401 /* Quiet this warning. */
5402 mips_frame_reg_valid
= 1;
5404 if (! mips_cprestore_valid
)
5406 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5407 /* Quiet this warning. */
5408 mips_cprestore_valid
= 1;
5410 expr1
.X_add_number
= mips_cprestore_offset
;
5411 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5414 HAVE_64BIT_ADDRESSES
);
5424 if (mips_pic
== NO_PIC
)
5425 macro_build (&offset_expr
, "jal", "a");
5426 else if (mips_pic
== SVR4_PIC
)
5428 /* If this is a reference to an external symbol, and we are
5429 using a small GOT, we want
5430 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5434 lw $gp,cprestore($sp)
5435 The cprestore value is set using the .cprestore
5436 pseudo-op. If we are using a big GOT, we want
5437 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5439 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5443 lw $gp,cprestore($sp)
5444 If the symbol is not external, we want
5445 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5447 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5450 lw $gp,cprestore($sp)
5452 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5453 sequences above, minus nops, unless the symbol is local,
5454 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5460 relax_start (offset_expr
.X_add_symbol
);
5461 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5462 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5465 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5466 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5472 relax_start (offset_expr
.X_add_symbol
);
5473 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5474 BFD_RELOC_MIPS_CALL_HI16
);
5475 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5476 PIC_CALL_REG
, mips_gp_register
);
5477 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5478 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5481 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5482 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5484 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5485 PIC_CALL_REG
, PIC_CALL_REG
,
5486 BFD_RELOC_MIPS_GOT_OFST
);
5490 macro_build_jalr (&offset_expr
);
5494 relax_start (offset_expr
.X_add_symbol
);
5497 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5498 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5507 gpdelay
= reg_needs_delay (mips_gp_register
);
5508 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5509 BFD_RELOC_MIPS_CALL_HI16
);
5510 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5511 PIC_CALL_REG
, mips_gp_register
);
5512 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5513 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5518 macro_build (NULL
, "nop", "");
5520 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5521 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5524 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5525 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5527 macro_build_jalr (&offset_expr
);
5529 if (mips_cprestore_offset
< 0)
5530 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5533 if (! mips_frame_reg_valid
)
5535 as_warn (_("No .frame pseudo-op used in PIC code"));
5536 /* Quiet this warning. */
5537 mips_frame_reg_valid
= 1;
5539 if (! mips_cprestore_valid
)
5541 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5542 /* Quiet this warning. */
5543 mips_cprestore_valid
= 1;
5545 if (mips_opts
.noreorder
)
5546 macro_build (NULL
, "nop", "");
5547 expr1
.X_add_number
= mips_cprestore_offset
;
5548 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5551 HAVE_64BIT_ADDRESSES
);
5577 /* Itbl support may require additional care here. */
5582 /* Itbl support may require additional care here. */
5587 /* Itbl support may require additional care here. */
5592 /* Itbl support may require additional care here. */
5604 if (mips_opts
.arch
== CPU_R4650
)
5606 as_bad (_("opcode not supported on this processor"));
5610 /* Itbl support may require additional care here. */
5615 /* Itbl support may require additional care here. */
5620 /* Itbl support may require additional care here. */
5640 if (breg
== treg
|| coproc
|| lr
)
5661 /* Itbl support may require additional care here. */
5666 /* Itbl support may require additional care here. */
5671 /* Itbl support may require additional care here. */
5676 /* Itbl support may require additional care here. */
5692 if (mips_opts
.arch
== CPU_R4650
)
5694 as_bad (_("opcode not supported on this processor"));
5699 /* Itbl support may require additional care here. */
5703 /* Itbl support may require additional care here. */
5708 /* Itbl support may require additional care here. */
5720 /* Itbl support may require additional care here. */
5721 if (mask
== M_LWC1_AB
5722 || mask
== M_SWC1_AB
5723 || mask
== M_LDC1_AB
5724 || mask
== M_SDC1_AB
5733 if (offset_expr
.X_op
!= O_constant
5734 && offset_expr
.X_op
!= O_symbol
)
5736 as_bad (_("expression too complex"));
5737 offset_expr
.X_op
= O_constant
;
5740 /* A constant expression in PIC code can be handled just as it
5741 is in non PIC code. */
5742 if (offset_expr
.X_op
== O_constant
)
5744 if (HAVE_32BIT_ADDRESSES
5745 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5746 as_bad (_("constant too large"));
5748 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5749 & ~(bfd_vma
) 0xffff);
5750 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5752 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5753 tempreg
, tempreg
, breg
);
5754 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5756 else if (mips_pic
== NO_PIC
)
5758 /* If this is a reference to a GP relative symbol, and there
5759 is no base register, we want
5760 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5761 Otherwise, if there is no base register, we want
5762 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5763 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5764 If we have a constant, we need two instructions anyhow,
5765 so we always use the latter form.
5767 If we have a base register, and this is a reference to a
5768 GP relative symbol, we want
5769 addu $tempreg,$breg,$gp
5770 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5772 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5773 addu $tempreg,$tempreg,$breg
5774 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5775 With a constant we always use the latter case.
5777 With 64bit address space and no base register and $at usable,
5779 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5780 lui $at,<sym> (BFD_RELOC_HI16_S)
5781 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5784 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5785 If we have a base register, we want
5786 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5787 lui $at,<sym> (BFD_RELOC_HI16_S)
5788 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5792 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5794 Without $at we can't generate the optimal path for superscalar
5795 processors here since this would require two temporary registers.
5796 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5797 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5799 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5801 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5802 If we have a base register, we want
5803 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5804 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5806 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5808 daddu $tempreg,$tempreg,$breg
5809 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5811 For GP relative symbols in 64bit address space we can use
5812 the same sequence as in 32bit address space. */
5813 if (HAVE_64BIT_SYMBOLS
)
5815 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5816 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5818 relax_start (offset_expr
.X_add_symbol
);
5821 macro_build (&offset_expr
, s
, fmt
, treg
,
5822 BFD_RELOC_GPREL16
, mips_gp_register
);
5826 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5827 tempreg
, breg
, mips_gp_register
);
5828 macro_build (&offset_expr
, s
, fmt
, treg
,
5829 BFD_RELOC_GPREL16
, tempreg
);
5834 if (used_at
== 0 && !mips_opts
.noat
)
5836 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5837 BFD_RELOC_MIPS_HIGHEST
);
5838 macro_build (&offset_expr
, "lui", "t,u", AT
,
5840 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5841 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5843 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5844 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5845 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5846 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5852 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5853 BFD_RELOC_MIPS_HIGHEST
);
5854 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5855 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5856 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5857 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5858 tempreg
, BFD_RELOC_HI16_S
);
5859 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5861 macro_build (NULL
, "daddu", "d,v,t",
5862 tempreg
, tempreg
, breg
);
5863 macro_build (&offset_expr
, s
, fmt
, treg
,
5864 BFD_RELOC_LO16
, tempreg
);
5867 if (mips_relax
.sequence
)
5874 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5875 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5877 relax_start (offset_expr
.X_add_symbol
);
5878 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5882 macro_build_lui (&offset_expr
, tempreg
);
5883 macro_build (&offset_expr
, s
, fmt
, treg
,
5884 BFD_RELOC_LO16
, tempreg
);
5885 if (mips_relax
.sequence
)
5890 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5891 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5893 relax_start (offset_expr
.X_add_symbol
);
5894 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5895 tempreg
, breg
, mips_gp_register
);
5896 macro_build (&offset_expr
, s
, fmt
, treg
,
5897 BFD_RELOC_GPREL16
, tempreg
);
5900 macro_build_lui (&offset_expr
, tempreg
);
5901 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5902 tempreg
, tempreg
, breg
);
5903 macro_build (&offset_expr
, s
, fmt
, treg
,
5904 BFD_RELOC_LO16
, tempreg
);
5905 if (mips_relax
.sequence
)
5909 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5911 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5913 /* If this is a reference to an external symbol, we want
5914 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5916 <op> $treg,0($tempreg)
5918 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5920 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5921 <op> $treg,0($tempreg)
5924 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5925 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
5927 If there is a base register, we add it to $tempreg before
5928 the <op>. If there is a constant, we stick it in the
5929 <op> instruction. We don't handle constants larger than
5930 16 bits, because we have no way to load the upper 16 bits
5931 (actually, we could handle them for the subset of cases
5932 in which we are not using $at). */
5933 assert (offset_expr
.X_op
== O_symbol
);
5936 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5937 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5939 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5940 tempreg
, tempreg
, breg
);
5941 macro_build (&offset_expr
, s
, fmt
, treg
,
5942 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
5945 expr1
.X_add_number
= offset_expr
.X_add_number
;
5946 offset_expr
.X_add_number
= 0;
5947 if (expr1
.X_add_number
< -0x8000
5948 || expr1
.X_add_number
>= 0x8000)
5949 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5950 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5951 lw_reloc_type
, mips_gp_register
);
5953 relax_start (offset_expr
.X_add_symbol
);
5955 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5956 tempreg
, BFD_RELOC_LO16
);
5959 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5960 tempreg
, tempreg
, breg
);
5961 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5963 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5967 /* If this is a reference to an external symbol, we want
5968 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5969 addu $tempreg,$tempreg,$gp
5970 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5971 <op> $treg,0($tempreg)
5973 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5975 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5976 <op> $treg,0($tempreg)
5977 If there is a base register, we add it to $tempreg before
5978 the <op>. If there is a constant, we stick it in the
5979 <op> instruction. We don't handle constants larger than
5980 16 bits, because we have no way to load the upper 16 bits
5981 (actually, we could handle them for the subset of cases
5982 in which we are not using $at). */
5983 assert (offset_expr
.X_op
== O_symbol
);
5984 expr1
.X_add_number
= offset_expr
.X_add_number
;
5985 offset_expr
.X_add_number
= 0;
5986 if (expr1
.X_add_number
< -0x8000
5987 || expr1
.X_add_number
>= 0x8000)
5988 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5989 gpdelay
= reg_needs_delay (mips_gp_register
);
5990 relax_start (offset_expr
.X_add_symbol
);
5991 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5992 BFD_RELOC_MIPS_GOT_HI16
);
5993 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
5995 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5996 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
5999 macro_build (NULL
, "nop", "");
6000 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6001 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6003 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6004 tempreg
, BFD_RELOC_LO16
);
6008 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6009 tempreg
, tempreg
, breg
);
6010 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6012 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6014 /* If this is a reference to an external symbol, we want
6015 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6016 add $tempreg,$tempreg,$gp
6017 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6018 <op> $treg,<ofst>($tempreg)
6019 Otherwise, for local symbols, we want:
6020 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6021 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6022 assert (offset_expr
.X_op
== O_symbol
);
6023 expr1
.X_add_number
= offset_expr
.X_add_number
;
6024 offset_expr
.X_add_number
= 0;
6025 if (expr1
.X_add_number
< -0x8000
6026 || expr1
.X_add_number
>= 0x8000)
6027 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6028 relax_start (offset_expr
.X_add_symbol
);
6029 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6030 BFD_RELOC_MIPS_GOT_HI16
);
6031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6033 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6034 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6036 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6037 tempreg
, tempreg
, breg
);
6038 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6041 offset_expr
.X_add_number
= expr1
.X_add_number
;
6042 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6043 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6045 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6046 tempreg
, tempreg
, breg
);
6047 macro_build (&offset_expr
, s
, fmt
, treg
,
6048 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6058 load_register (treg
, &imm_expr
, 0);
6062 load_register (treg
, &imm_expr
, 1);
6066 if (imm_expr
.X_op
== O_constant
)
6069 load_register (AT
, &imm_expr
, 0);
6070 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6075 assert (offset_expr
.X_op
== O_symbol
6076 && strcmp (segment_name (S_GET_SEGMENT
6077 (offset_expr
.X_add_symbol
)),
6079 && offset_expr
.X_add_number
== 0);
6080 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6081 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6086 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6087 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6088 order 32 bits of the value and the low order 32 bits are either
6089 zero or in OFFSET_EXPR. */
6090 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6092 if (HAVE_64BIT_GPRS
)
6093 load_register (treg
, &imm_expr
, 1);
6098 if (target_big_endian
)
6110 load_register (hreg
, &imm_expr
, 0);
6113 if (offset_expr
.X_op
== O_absent
)
6114 move_register (lreg
, 0);
6117 assert (offset_expr
.X_op
== O_constant
);
6118 load_register (lreg
, &offset_expr
, 0);
6125 /* We know that sym is in the .rdata section. First we get the
6126 upper 16 bits of the address. */
6127 if (mips_pic
== NO_PIC
)
6129 macro_build_lui (&offset_expr
, AT
);
6132 else if (mips_pic
== SVR4_PIC
)
6134 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6135 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6141 /* Now we load the register(s). */
6142 if (HAVE_64BIT_GPRS
)
6145 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6150 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6153 /* FIXME: How in the world do we deal with the possible
6155 offset_expr
.X_add_number
+= 4;
6156 macro_build (&offset_expr
, "lw", "t,o(b)",
6157 treg
+ 1, BFD_RELOC_LO16
, AT
);
6163 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6164 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6165 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6166 the value and the low order 32 bits are either zero or in
6168 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6171 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6172 if (HAVE_64BIT_FPRS
)
6174 assert (HAVE_64BIT_GPRS
);
6175 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6179 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6180 if (offset_expr
.X_op
== O_absent
)
6181 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6184 assert (offset_expr
.X_op
== O_constant
);
6185 load_register (AT
, &offset_expr
, 0);
6186 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6192 assert (offset_expr
.X_op
== O_symbol
6193 && offset_expr
.X_add_number
== 0);
6194 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6195 if (strcmp (s
, ".lit8") == 0)
6197 if (mips_opts
.isa
!= ISA_MIPS1
)
6199 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6200 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6203 breg
= mips_gp_register
;
6204 r
= BFD_RELOC_MIPS_LITERAL
;
6209 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6211 if (mips_pic
== SVR4_PIC
)
6212 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6213 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6216 /* FIXME: This won't work for a 64 bit address. */
6217 macro_build_lui (&offset_expr
, AT
);
6220 if (mips_opts
.isa
!= ISA_MIPS1
)
6222 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6223 treg
, BFD_RELOC_LO16
, AT
);
6232 if (mips_opts
.arch
== CPU_R4650
)
6234 as_bad (_("opcode not supported on this processor"));
6237 /* Even on a big endian machine $fn comes before $fn+1. We have
6238 to adjust when loading from memory. */
6241 assert (mips_opts
.isa
== ISA_MIPS1
);
6242 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6243 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6244 /* FIXME: A possible overflow which I don't know how to deal
6246 offset_expr
.X_add_number
+= 4;
6247 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6248 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6253 * The MIPS assembler seems to check for X_add_number not
6254 * being double aligned and generating:
6257 * addiu at,at,%lo(foo+1)
6260 * But, the resulting address is the same after relocation so why
6261 * generate the extra instruction?
6263 if (mips_opts
.arch
== CPU_R4650
)
6265 as_bad (_("opcode not supported on this processor"));
6268 /* Itbl support may require additional care here. */
6270 if (mips_opts
.isa
!= ISA_MIPS1
)
6281 if (mips_opts
.arch
== CPU_R4650
)
6283 as_bad (_("opcode not supported on this processor"));
6287 if (mips_opts
.isa
!= ISA_MIPS1
)
6295 /* Itbl support may require additional care here. */
6300 if (HAVE_64BIT_GPRS
)
6311 if (HAVE_64BIT_GPRS
)
6321 if (offset_expr
.X_op
!= O_symbol
6322 && offset_expr
.X_op
!= O_constant
)
6324 as_bad (_("expression too complex"));
6325 offset_expr
.X_op
= O_constant
;
6328 /* Even on a big endian machine $fn comes before $fn+1. We have
6329 to adjust when loading from memory. We set coproc if we must
6330 load $fn+1 first. */
6331 /* Itbl support may require additional care here. */
6332 if (! target_big_endian
)
6335 if (mips_pic
== NO_PIC
6336 || offset_expr
.X_op
== O_constant
)
6338 /* If this is a reference to a GP relative symbol, we want
6339 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6340 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6341 If we have a base register, we use this
6343 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6344 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6345 If this is not a GP relative symbol, we want
6346 lui $at,<sym> (BFD_RELOC_HI16_S)
6347 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6348 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6349 If there is a base register, we add it to $at after the
6350 lui instruction. If there is a constant, we always use
6352 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6353 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6355 relax_start (offset_expr
.X_add_symbol
);
6358 tempreg
= mips_gp_register
;
6362 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6363 AT
, breg
, mips_gp_register
);
6368 /* Itbl support may require additional care here. */
6369 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6370 BFD_RELOC_GPREL16
, tempreg
);
6371 offset_expr
.X_add_number
+= 4;
6373 /* Set mips_optimize to 2 to avoid inserting an
6375 hold_mips_optimize
= mips_optimize
;
6377 /* Itbl support may require additional care here. */
6378 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6379 BFD_RELOC_GPREL16
, tempreg
);
6380 mips_optimize
= hold_mips_optimize
;
6384 /* We just generated two relocs. When tc_gen_reloc
6385 handles this case, it will skip the first reloc and
6386 handle the second. The second reloc already has an
6387 extra addend of 4, which we added above. We must
6388 subtract it out, and then subtract another 4 to make
6389 the first reloc come out right. The second reloc
6390 will come out right because we are going to add 4 to
6391 offset_expr when we build its instruction below.
6393 If we have a symbol, then we don't want to include
6394 the offset, because it will wind up being included
6395 when we generate the reloc. */
6397 if (offset_expr
.X_op
== O_constant
)
6398 offset_expr
.X_add_number
-= 8;
6401 offset_expr
.X_add_number
= -4;
6402 offset_expr
.X_op
= O_constant
;
6406 macro_build_lui (&offset_expr
, AT
);
6408 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6409 /* Itbl support may require additional care here. */
6410 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6411 BFD_RELOC_LO16
, AT
);
6412 /* FIXME: How do we handle overflow here? */
6413 offset_expr
.X_add_number
+= 4;
6414 /* Itbl support may require additional care here. */
6415 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6416 BFD_RELOC_LO16
, AT
);
6417 if (mips_relax
.sequence
)
6420 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6422 /* If this is a reference to an external symbol, we want
6423 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6428 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6430 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6431 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6432 If there is a base register we add it to $at before the
6433 lwc1 instructions. If there is a constant we include it
6434 in the lwc1 instructions. */
6436 expr1
.X_add_number
= offset_expr
.X_add_number
;
6437 if (expr1
.X_add_number
< -0x8000
6438 || expr1
.X_add_number
>= 0x8000 - 4)
6439 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6440 load_got_offset (AT
, &offset_expr
);
6443 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6445 /* Set mips_optimize to 2 to avoid inserting an undesired
6447 hold_mips_optimize
= mips_optimize
;
6450 /* Itbl support may require additional care here. */
6451 relax_start (offset_expr
.X_add_symbol
);
6452 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6453 BFD_RELOC_LO16
, AT
);
6454 expr1
.X_add_number
+= 4;
6455 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6456 BFD_RELOC_LO16
, AT
);
6458 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6459 BFD_RELOC_LO16
, AT
);
6460 offset_expr
.X_add_number
+= 4;
6461 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6462 BFD_RELOC_LO16
, AT
);
6465 mips_optimize
= hold_mips_optimize
;
6467 else if (mips_pic
== SVR4_PIC
)
6471 /* If this is a reference to an external symbol, we want
6472 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6474 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6479 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6481 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6482 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6483 If there is a base register we add it to $at before the
6484 lwc1 instructions. If there is a constant we include it
6485 in the lwc1 instructions. */
6487 expr1
.X_add_number
= offset_expr
.X_add_number
;
6488 offset_expr
.X_add_number
= 0;
6489 if (expr1
.X_add_number
< -0x8000
6490 || expr1
.X_add_number
>= 0x8000 - 4)
6491 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6492 gpdelay
= reg_needs_delay (mips_gp_register
);
6493 relax_start (offset_expr
.X_add_symbol
);
6494 macro_build (&offset_expr
, "lui", "t,u",
6495 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6496 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6497 AT
, AT
, mips_gp_register
);
6498 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6499 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6502 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6503 /* Itbl support may require additional care here. */
6504 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6505 BFD_RELOC_LO16
, AT
);
6506 expr1
.X_add_number
+= 4;
6508 /* Set mips_optimize to 2 to avoid inserting an undesired
6510 hold_mips_optimize
= mips_optimize
;
6512 /* Itbl support may require additional care here. */
6513 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6514 BFD_RELOC_LO16
, AT
);
6515 mips_optimize
= hold_mips_optimize
;
6516 expr1
.X_add_number
-= 4;
6519 offset_expr
.X_add_number
= expr1
.X_add_number
;
6521 macro_build (NULL
, "nop", "");
6522 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6523 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6526 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6527 /* Itbl support may require additional care here. */
6528 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6529 BFD_RELOC_LO16
, AT
);
6530 offset_expr
.X_add_number
+= 4;
6532 /* Set mips_optimize to 2 to avoid inserting an undesired
6534 hold_mips_optimize
= mips_optimize
;
6536 /* Itbl support may require additional care here. */
6537 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6538 BFD_RELOC_LO16
, AT
);
6539 mips_optimize
= hold_mips_optimize
;
6553 assert (HAVE_32BIT_ADDRESSES
);
6554 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6555 offset_expr
.X_add_number
+= 4;
6556 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6559 /* New code added to support COPZ instructions.
6560 This code builds table entries out of the macros in mip_opcodes.
6561 R4000 uses interlocks to handle coproc delays.
6562 Other chips (like the R3000) require nops to be inserted for delays.
6564 FIXME: Currently, we require that the user handle delays.
6565 In order to fill delay slots for non-interlocked chips,
6566 we must have a way to specify delays based on the coprocessor.
6567 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6568 What are the side-effects of the cop instruction?
6569 What cache support might we have and what are its effects?
6570 Both coprocessor & memory require delays. how long???
6571 What registers are read/set/modified?
6573 If an itbl is provided to interpret cop instructions,
6574 this knowledge can be encoded in the itbl spec. */
6588 /* For now we just do C (same as Cz). The parameter will be
6589 stored in insn_opcode by mips_ip. */
6590 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6594 move_register (dreg
, sreg
);
6597 #ifdef LOSING_COMPILER
6599 /* Try and see if this is a new itbl instruction.
6600 This code builds table entries out of the macros in mip_opcodes.
6601 FIXME: For now we just assemble the expression and pass it's
6602 value along as a 32-bit immediate.
6603 We may want to have the assembler assemble this value,
6604 so that we gain the assembler's knowledge of delay slots,
6606 Would it be more efficient to use mask (id) here? */
6607 if (itbl_have_entries
6608 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6610 s
= ip
->insn_mo
->name
;
6612 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6613 macro_build (&immed_expr
, s
, "C");
6619 if (mips_opts
.noat
&& used_at
)
6620 as_bad (_("Macro used $at after \".set noat\""));
6624 macro2 (struct mips_cl_insn
*ip
)
6626 register int treg
, sreg
, dreg
, breg
;
6641 bfd_reloc_code_real_type r
;
6643 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6644 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6645 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6646 mask
= ip
->insn_mo
->mask
;
6648 expr1
.X_op
= O_constant
;
6649 expr1
.X_op_symbol
= NULL
;
6650 expr1
.X_add_symbol
= NULL
;
6651 expr1
.X_add_number
= 1;
6655 #endif /* LOSING_COMPILER */
6660 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6661 macro_build (NULL
, "mflo", "d", dreg
);
6667 /* The MIPS assembler some times generates shifts and adds. I'm
6668 not trying to be that fancy. GCC should do this for us
6671 load_register (AT
, &imm_expr
, dbl
);
6672 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6673 macro_build (NULL
, "mflo", "d", dreg
);
6689 load_register (AT
, &imm_expr
, dbl
);
6690 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6691 macro_build (NULL
, "mflo", "d", dreg
);
6692 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6693 macro_build (NULL
, "mfhi", "d", AT
);
6695 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6698 expr1
.X_add_number
= 8;
6699 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6700 macro_build (NULL
, "nop", "", 0);
6701 macro_build (NULL
, "break", "c", 6);
6704 macro_build (NULL
, "mflo", "d", dreg
);
6720 load_register (AT
, &imm_expr
, dbl
);
6721 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6722 sreg
, imm
? AT
: treg
);
6723 macro_build (NULL
, "mfhi", "d", AT
);
6724 macro_build (NULL
, "mflo", "d", dreg
);
6726 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6729 expr1
.X_add_number
= 8;
6730 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6731 macro_build (NULL
, "nop", "", 0);
6732 macro_build (NULL
, "break", "c", 6);
6738 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6749 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6750 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6754 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6755 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6756 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6757 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6761 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6772 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6773 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6777 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6778 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6779 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6780 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6788 if (imm_expr
.X_op
!= O_constant
)
6789 as_bad (_("Improper rotate count"));
6790 rot
= imm_expr
.X_add_number
& 0x3f;
6791 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6793 rot
= (64 - rot
) & 0x3f;
6795 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6797 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6802 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6805 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6806 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6809 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6810 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6811 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6819 if (imm_expr
.X_op
!= O_constant
)
6820 as_bad (_("Improper rotate count"));
6821 rot
= imm_expr
.X_add_number
& 0x1f;
6822 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6824 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6829 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6833 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6834 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6835 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6840 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6842 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6846 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6847 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6848 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6849 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6853 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6855 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6859 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6860 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6861 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6862 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6870 if (imm_expr
.X_op
!= O_constant
)
6871 as_bad (_("Improper rotate count"));
6872 rot
= imm_expr
.X_add_number
& 0x3f;
6873 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6876 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6878 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6883 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6886 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6887 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6890 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6891 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6892 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6900 if (imm_expr
.X_op
!= O_constant
)
6901 as_bad (_("Improper rotate count"));
6902 rot
= imm_expr
.X_add_number
& 0x1f;
6903 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6905 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6910 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6914 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6915 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6916 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6921 if (mips_opts
.arch
== CPU_R4650
)
6923 as_bad (_("opcode not supported on this processor"));
6926 assert (mips_opts
.isa
== ISA_MIPS1
);
6927 /* Even on a big endian machine $fn comes before $fn+1. We have
6928 to adjust when storing to memory. */
6929 macro_build (&offset_expr
, "swc1", "T,o(b)",
6930 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
6931 offset_expr
.X_add_number
+= 4;
6932 macro_build (&offset_expr
, "swc1", "T,o(b)",
6933 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
6938 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
6940 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6943 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
6944 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6949 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6951 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6956 as_warn (_("Instruction %s: result is always false"),
6958 move_register (dreg
, 0);
6961 if (imm_expr
.X_op
== O_constant
6962 && imm_expr
.X_add_number
>= 0
6963 && imm_expr
.X_add_number
< 0x10000)
6965 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
6967 else if (imm_expr
.X_op
== O_constant
6968 && imm_expr
.X_add_number
> -0x8000
6969 && imm_expr
.X_add_number
< 0)
6971 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6972 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6973 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6977 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6978 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
6981 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6984 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6990 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6991 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
6994 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6996 if (imm_expr
.X_op
== O_constant
6997 && imm_expr
.X_add_number
>= -0x8000
6998 && imm_expr
.X_add_number
< 0x8000)
7000 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7001 dreg
, sreg
, BFD_RELOC_LO16
);
7005 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7006 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7010 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7013 case M_SGT
: /* sreg > treg <==> treg < sreg */
7019 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7022 case M_SGT_I
: /* sreg > I <==> I < sreg */
7029 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7030 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7033 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7039 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7040 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7043 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7050 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7051 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7052 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7056 if (imm_expr
.X_op
== O_constant
7057 && imm_expr
.X_add_number
>= -0x8000
7058 && imm_expr
.X_add_number
< 0x8000)
7060 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7064 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7065 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7069 if (imm_expr
.X_op
== O_constant
7070 && imm_expr
.X_add_number
>= -0x8000
7071 && imm_expr
.X_add_number
< 0x8000)
7073 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7078 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7079 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7084 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7086 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7089 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7090 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7095 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7097 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7102 as_warn (_("Instruction %s: result is always true"),
7104 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7105 dreg
, 0, BFD_RELOC_LO16
);
7108 if (imm_expr
.X_op
== O_constant
7109 && imm_expr
.X_add_number
>= 0
7110 && imm_expr
.X_add_number
< 0x10000)
7112 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7114 else if (imm_expr
.X_op
== O_constant
7115 && imm_expr
.X_add_number
> -0x8000
7116 && imm_expr
.X_add_number
< 0)
7118 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7119 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7120 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7124 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7125 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7128 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7134 if (imm_expr
.X_op
== O_constant
7135 && imm_expr
.X_add_number
> -0x8000
7136 && imm_expr
.X_add_number
<= 0x8000)
7138 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7139 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7140 dreg
, sreg
, BFD_RELOC_LO16
);
7144 load_register (AT
, &imm_expr
, dbl
);
7145 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7151 if (imm_expr
.X_op
== O_constant
7152 && imm_expr
.X_add_number
> -0x8000
7153 && imm_expr
.X_add_number
<= 0x8000)
7155 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7156 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7157 dreg
, sreg
, BFD_RELOC_LO16
);
7161 load_register (AT
, &imm_expr
, dbl
);
7162 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7184 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7185 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7190 assert (mips_opts
.isa
== ISA_MIPS1
);
7192 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7193 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7196 * Is the double cfc1 instruction a bug in the mips assembler;
7197 * or is there a reason for it?
7200 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7201 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7202 macro_build (NULL
, "nop", "");
7203 expr1
.X_add_number
= 3;
7204 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7205 expr1
.X_add_number
= 2;
7206 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7207 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7208 macro_build (NULL
, "nop", "");
7209 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7211 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7212 macro_build (NULL
, "nop", "");
7223 if (offset_expr
.X_add_number
>= 0x7fff)
7224 as_bad (_("operand overflow"));
7225 if (! target_big_endian
)
7226 ++offset_expr
.X_add_number
;
7227 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7228 if (! target_big_endian
)
7229 --offset_expr
.X_add_number
;
7231 ++offset_expr
.X_add_number
;
7232 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7233 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7234 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7247 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7248 as_bad (_("operand overflow"));
7256 if (! target_big_endian
)
7257 offset_expr
.X_add_number
+= off
;
7258 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7259 if (! target_big_endian
)
7260 offset_expr
.X_add_number
-= off
;
7262 offset_expr
.X_add_number
+= off
;
7263 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7265 /* If necessary, move the result in tempreg the final destination. */
7266 if (treg
== tempreg
)
7268 /* Protect second load's delay slot. */
7270 move_register (treg
, tempreg
);
7284 load_address (AT
, &offset_expr
, &used_at
);
7286 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7287 if (! target_big_endian
)
7288 expr1
.X_add_number
= off
;
7290 expr1
.X_add_number
= 0;
7291 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7292 if (! target_big_endian
)
7293 expr1
.X_add_number
= 0;
7295 expr1
.X_add_number
= off
;
7296 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7302 load_address (AT
, &offset_expr
, &used_at
);
7304 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7305 if (target_big_endian
)
7306 expr1
.X_add_number
= 0;
7307 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7308 treg
, BFD_RELOC_LO16
, AT
);
7309 if (target_big_endian
)
7310 expr1
.X_add_number
= 1;
7312 expr1
.X_add_number
= 0;
7313 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7314 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7315 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7320 if (offset_expr
.X_add_number
>= 0x7fff)
7321 as_bad (_("operand overflow"));
7322 if (target_big_endian
)
7323 ++offset_expr
.X_add_number
;
7324 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7325 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7326 if (target_big_endian
)
7327 --offset_expr
.X_add_number
;
7329 ++offset_expr
.X_add_number
;
7330 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7343 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7344 as_bad (_("operand overflow"));
7345 if (! target_big_endian
)
7346 offset_expr
.X_add_number
+= off
;
7347 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7348 if (! target_big_endian
)
7349 offset_expr
.X_add_number
-= off
;
7351 offset_expr
.X_add_number
+= off
;
7352 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7366 load_address (AT
, &offset_expr
, &used_at
);
7368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7369 if (! target_big_endian
)
7370 expr1
.X_add_number
= off
;
7372 expr1
.X_add_number
= 0;
7373 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7374 if (! target_big_endian
)
7375 expr1
.X_add_number
= 0;
7377 expr1
.X_add_number
= off
;
7378 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7383 load_address (AT
, &offset_expr
, &used_at
);
7385 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7386 if (! target_big_endian
)
7387 expr1
.X_add_number
= 0;
7388 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7389 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7390 if (! target_big_endian
)
7391 expr1
.X_add_number
= 1;
7393 expr1
.X_add_number
= 0;
7394 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7395 if (! target_big_endian
)
7396 expr1
.X_add_number
= 0;
7398 expr1
.X_add_number
= 1;
7399 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7400 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7401 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7405 /* FIXME: Check if this is one of the itbl macros, since they
7406 are added dynamically. */
7407 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7410 if (mips_opts
.noat
&& used_at
)
7411 as_bad (_("Macro used $at after \".set noat\""));
7414 /* Implement macros in mips16 mode. */
7417 mips16_macro (struct mips_cl_insn
*ip
)
7420 int xreg
, yreg
, zreg
, tmp
;
7423 const char *s
, *s2
, *s3
;
7425 mask
= ip
->insn_mo
->mask
;
7427 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7428 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7429 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7431 expr1
.X_op
= O_constant
;
7432 expr1
.X_op_symbol
= NULL
;
7433 expr1
.X_add_symbol
= NULL
;
7434 expr1
.X_add_number
= 1;
7454 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7455 expr1
.X_add_number
= 2;
7456 macro_build (&expr1
, "bnez", "x,p", yreg
);
7457 macro_build (NULL
, "break", "6", 7);
7459 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7460 since that causes an overflow. We should do that as well,
7461 but I don't see how to do the comparisons without a temporary
7464 macro_build (NULL
, s
, "x", zreg
);
7484 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7485 expr1
.X_add_number
= 2;
7486 macro_build (&expr1
, "bnez", "x,p", yreg
);
7487 macro_build (NULL
, "break", "6", 7);
7489 macro_build (NULL
, s2
, "x", zreg
);
7495 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7496 macro_build (NULL
, "mflo", "x", zreg
);
7504 if (imm_expr
.X_op
!= O_constant
)
7505 as_bad (_("Unsupported large constant"));
7506 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7507 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7511 if (imm_expr
.X_op
!= O_constant
)
7512 as_bad (_("Unsupported large constant"));
7513 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7514 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7518 if (imm_expr
.X_op
!= O_constant
)
7519 as_bad (_("Unsupported large constant"));
7520 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7521 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7543 goto do_reverse_branch
;
7547 goto do_reverse_branch
;
7559 goto do_reverse_branch
;
7570 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7571 macro_build (&offset_expr
, s2
, "p");
7598 goto do_addone_branch_i
;
7603 goto do_addone_branch_i
;
7618 goto do_addone_branch_i
;
7625 if (imm_expr
.X_op
!= O_constant
)
7626 as_bad (_("Unsupported large constant"));
7627 ++imm_expr
.X_add_number
;
7630 macro_build (&imm_expr
, s
, s3
, xreg
);
7631 macro_build (&offset_expr
, s2
, "p");
7635 expr1
.X_add_number
= 0;
7636 macro_build (&expr1
, "slti", "x,8", yreg
);
7638 move_register (xreg
, yreg
);
7639 expr1
.X_add_number
= 2;
7640 macro_build (&expr1
, "bteqz", "p");
7641 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7645 /* For consistency checking, verify that all bits are specified either
7646 by the match/mask part of the instruction definition, or by the
7649 validate_mips_insn (const struct mips_opcode
*opc
)
7651 const char *p
= opc
->args
;
7653 unsigned long used_bits
= opc
->mask
;
7655 if ((used_bits
& opc
->match
) != opc
->match
)
7657 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7658 opc
->name
, opc
->args
);
7661 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7671 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7672 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7673 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7674 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7675 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7676 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7677 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7678 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7679 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7682 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7683 c
, opc
->name
, opc
->args
);
7687 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7688 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7690 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7691 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7692 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7693 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7695 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7696 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7698 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7699 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7701 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7702 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7703 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7704 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7705 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7706 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7707 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7708 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7709 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7710 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7711 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7712 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7713 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7714 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7715 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7716 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7717 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7719 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7720 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7721 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7722 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7724 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7725 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7726 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7727 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7728 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7729 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7730 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7731 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7732 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7735 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7736 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7737 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7738 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7739 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7743 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7744 c
, opc
->name
, opc
->args
);
7748 if (used_bits
!= 0xffffffff)
7750 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7751 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7757 /* This routine assembles an instruction into its binary format. As a
7758 side effect, it sets one of the global variables imm_reloc or
7759 offset_reloc to the type of relocation to do if one of the operands
7760 is an address expression. */
7763 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7768 struct mips_opcode
*insn
;
7771 unsigned int lastregno
= 0;
7772 unsigned int lastpos
= 0;
7773 unsigned int limlo
, limhi
;
7779 /* If the instruction contains a '.', we first try to match an instruction
7780 including the '.'. Then we try again without the '.'. */
7782 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7785 /* If we stopped on whitespace, then replace the whitespace with null for
7786 the call to hash_find. Save the character we replaced just in case we
7787 have to re-parse the instruction. */
7794 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7796 /* If we didn't find the instruction in the opcode table, try again, but
7797 this time with just the instruction up to, but not including the
7801 /* Restore the character we overwrite above (if any). */
7805 /* Scan up to the first '.' or whitespace. */
7807 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7811 /* If we did not find a '.', then we can quit now. */
7814 insn_error
= "unrecognized opcode";
7818 /* Lookup the instruction in the hash table. */
7820 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7822 insn_error
= "unrecognized opcode";
7832 assert (strcmp (insn
->name
, str
) == 0);
7834 if (OPCODE_IS_MEMBER (insn
,
7836 | (file_ase_mips16
? INSN_MIPS16
: 0)
7837 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7838 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7844 if (insn
->pinfo
!= INSN_MACRO
)
7846 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7852 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7853 && strcmp (insn
->name
, insn
[1].name
) == 0)
7862 static char buf
[100];
7864 _("opcode not supported on this processor: %s (%s)"),
7865 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7866 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7875 create_insn (ip
, insn
);
7877 for (args
= insn
->args
;; ++args
)
7881 s
+= strspn (s
, " \t");
7885 case '\0': /* end of args */
7898 INSERT_OPERAND (RS
, *ip
, lastregno
);
7902 INSERT_OPERAND (RT
, *ip
, lastregno
);
7906 INSERT_OPERAND (FT
, *ip
, lastregno
);
7910 INSERT_OPERAND (FS
, *ip
, lastregno
);
7916 /* Handle optional base register.
7917 Either the base register is omitted or
7918 we must have a left paren. */
7919 /* This is dependent on the next operand specifier
7920 is a base register specification. */
7921 assert (args
[1] == 'b' || args
[1] == '5'
7922 || args
[1] == '-' || args
[1] == '4');
7926 case ')': /* these must match exactly */
7933 case '+': /* Opcode extension character. */
7936 case 'A': /* ins/ext position, becomes LSB. */
7945 my_getExpression (&imm_expr
, s
);
7946 check_absolute_expr (ip
, &imm_expr
);
7947 if ((unsigned long) imm_expr
.X_add_number
< limlo
7948 || (unsigned long) imm_expr
.X_add_number
> limhi
)
7950 as_bad (_("Improper position (%lu)"),
7951 (unsigned long) imm_expr
.X_add_number
);
7952 imm_expr
.X_add_number
= limlo
;
7954 lastpos
= imm_expr
.X_add_number
;
7955 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
7956 imm_expr
.X_op
= O_absent
;
7960 case 'B': /* ins size, becomes MSB. */
7969 my_getExpression (&imm_expr
, s
);
7970 check_absolute_expr (ip
, &imm_expr
);
7971 /* Check for negative input so that small negative numbers
7972 will not succeed incorrectly. The checks against
7973 (pos+size) transitively check "size" itself,
7974 assuming that "pos" is reasonable. */
7975 if ((long) imm_expr
.X_add_number
< 0
7976 || ((unsigned long) imm_expr
.X_add_number
7978 || ((unsigned long) imm_expr
.X_add_number
7981 as_bad (_("Improper insert size (%lu, position %lu)"),
7982 (unsigned long) imm_expr
.X_add_number
,
7983 (unsigned long) lastpos
);
7984 imm_expr
.X_add_number
= limlo
- lastpos
;
7986 INSERT_OPERAND (INSMSB
, *ip
,
7987 lastpos
+ imm_expr
.X_add_number
- 1);
7988 imm_expr
.X_op
= O_absent
;
7992 case 'C': /* ext size, becomes MSBD. */
8005 my_getExpression (&imm_expr
, s
);
8006 check_absolute_expr (ip
, &imm_expr
);
8007 /* Check for negative input so that small negative numbers
8008 will not succeed incorrectly. The checks against
8009 (pos+size) transitively check "size" itself,
8010 assuming that "pos" is reasonable. */
8011 if ((long) imm_expr
.X_add_number
< 0
8012 || ((unsigned long) imm_expr
.X_add_number
8014 || ((unsigned long) imm_expr
.X_add_number
8017 as_bad (_("Improper extract size (%lu, position %lu)"),
8018 (unsigned long) imm_expr
.X_add_number
,
8019 (unsigned long) lastpos
);
8020 imm_expr
.X_add_number
= limlo
- lastpos
;
8022 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8023 imm_expr
.X_op
= O_absent
;
8028 /* +D is for disassembly only; never match. */
8032 /* "+I" is like "I", except that imm2_expr is used. */
8033 my_getExpression (&imm2_expr
, s
);
8034 if (imm2_expr
.X_op
!= O_big
8035 && imm2_expr
.X_op
!= O_constant
)
8036 insn_error
= _("absolute expression required");
8037 normalize_constant_expr (&imm2_expr
);
8042 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8043 *args
, insn
->name
, insn
->args
);
8044 /* Further processing is fruitless. */
8049 case '<': /* must be at least one digit */
8051 * According to the manual, if the shift amount is greater
8052 * than 31 or less than 0, then the shift amount should be
8053 * mod 32. In reality the mips assembler issues an error.
8054 * We issue a warning and mask out all but the low 5 bits.
8056 my_getExpression (&imm_expr
, s
);
8057 check_absolute_expr (ip
, &imm_expr
);
8058 if ((unsigned long) imm_expr
.X_add_number
> 31)
8059 as_warn (_("Improper shift amount (%lu)"),
8060 (unsigned long) imm_expr
.X_add_number
);
8061 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8062 imm_expr
.X_op
= O_absent
;
8066 case '>': /* shift amount minus 32 */
8067 my_getExpression (&imm_expr
, s
);
8068 check_absolute_expr (ip
, &imm_expr
);
8069 if ((unsigned long) imm_expr
.X_add_number
< 32
8070 || (unsigned long) imm_expr
.X_add_number
> 63)
8072 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8073 imm_expr
.X_op
= O_absent
;
8077 case 'k': /* cache code */
8078 case 'h': /* prefx code */
8079 my_getExpression (&imm_expr
, s
);
8080 check_absolute_expr (ip
, &imm_expr
);
8081 if ((unsigned long) imm_expr
.X_add_number
> 31)
8082 as_warn (_("Invalid value for `%s' (%lu)"),
8084 (unsigned long) imm_expr
.X_add_number
);
8086 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8088 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8089 imm_expr
.X_op
= O_absent
;
8093 case 'c': /* break code */
8094 my_getExpression (&imm_expr
, s
);
8095 check_absolute_expr (ip
, &imm_expr
);
8096 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8097 as_warn (_("Illegal break code (%lu)"),
8098 (unsigned long) imm_expr
.X_add_number
);
8099 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8100 imm_expr
.X_op
= O_absent
;
8104 case 'q': /* lower break code */
8105 my_getExpression (&imm_expr
, s
);
8106 check_absolute_expr (ip
, &imm_expr
);
8107 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8108 as_warn (_("Illegal lower break code (%lu)"),
8109 (unsigned long) imm_expr
.X_add_number
);
8110 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8111 imm_expr
.X_op
= O_absent
;
8115 case 'B': /* 20-bit syscall/break code. */
8116 my_getExpression (&imm_expr
, s
);
8117 check_absolute_expr (ip
, &imm_expr
);
8118 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8119 as_warn (_("Illegal 20-bit code (%lu)"),
8120 (unsigned long) imm_expr
.X_add_number
);
8121 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8122 imm_expr
.X_op
= O_absent
;
8126 case 'C': /* Coprocessor code */
8127 my_getExpression (&imm_expr
, s
);
8128 check_absolute_expr (ip
, &imm_expr
);
8129 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8131 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8132 (unsigned long) imm_expr
.X_add_number
);
8133 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8135 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8136 imm_expr
.X_op
= O_absent
;
8140 case 'J': /* 19-bit wait code. */
8141 my_getExpression (&imm_expr
, s
);
8142 check_absolute_expr (ip
, &imm_expr
);
8143 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8144 as_warn (_("Illegal 19-bit code (%lu)"),
8145 (unsigned long) imm_expr
.X_add_number
);
8146 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8147 imm_expr
.X_op
= O_absent
;
8151 case 'P': /* Performance register */
8152 my_getExpression (&imm_expr
, s
);
8153 check_absolute_expr (ip
, &imm_expr
);
8154 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8155 as_warn (_("Invalid performance register (%lu)"),
8156 (unsigned long) imm_expr
.X_add_number
);
8157 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8158 imm_expr
.X_op
= O_absent
;
8162 case 'b': /* base register */
8163 case 'd': /* destination register */
8164 case 's': /* source register */
8165 case 't': /* target register */
8166 case 'r': /* both target and source */
8167 case 'v': /* both dest and source */
8168 case 'w': /* both dest and target */
8169 case 'E': /* coprocessor target register */
8170 case 'G': /* coprocessor destination register */
8171 case 'K': /* 'rdhwr' destination register */
8172 case 'x': /* ignore register name */
8173 case 'z': /* must be zero register */
8174 case 'U': /* destination register (clo/clz). */
8189 while (ISDIGIT (*s
));
8191 as_bad (_("Invalid register number (%d)"), regno
);
8193 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8197 if (s
[1] == 'r' && s
[2] == 'a')
8202 else if (s
[1] == 'f' && s
[2] == 'p')
8207 else if (s
[1] == 's' && s
[2] == 'p')
8212 else if (s
[1] == 'g' && s
[2] == 'p')
8217 else if (s
[1] == 'a' && s
[2] == 't')
8222 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8227 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8232 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8237 else if (itbl_have_entries
)
8242 p
= s
+ 1; /* advance past '$' */
8243 n
= itbl_get_field (&p
); /* n is name */
8245 /* See if this is a register defined in an
8247 if (itbl_get_reg_val (n
, &r
))
8249 /* Get_field advances to the start of
8250 the next field, so we need to back
8251 rack to the end of the last field. */
8255 s
= strchr (s
, '\0');
8269 as_warn (_("Used $at without \".set noat\""));
8275 if (c
== 'r' || c
== 'v' || c
== 'w')
8282 /* 'z' only matches $0. */
8283 if (c
== 'z' && regno
!= 0)
8286 /* Now that we have assembled one operand, we use the args string
8287 * to figure out where it goes in the instruction. */
8294 INSERT_OPERAND (RS
, *ip
, regno
);
8299 INSERT_OPERAND (RD
, *ip
, regno
);
8302 INSERT_OPERAND (RD
, *ip
, regno
);
8303 INSERT_OPERAND (RT
, *ip
, regno
);
8308 INSERT_OPERAND (RT
, *ip
, regno
);
8311 /* This case exists because on the r3000 trunc
8312 expands into a macro which requires a gp
8313 register. On the r6000 or r4000 it is
8314 assembled into a single instruction which
8315 ignores the register. Thus the insn version
8316 is MIPS_ISA2 and uses 'x', and the macro
8317 version is MIPS_ISA1 and uses 't'. */
8320 /* This case is for the div instruction, which
8321 acts differently if the destination argument
8322 is $0. This only matches $0, and is checked
8323 outside the switch. */
8326 /* Itbl operand; not yet implemented. FIXME ?? */
8328 /* What about all other operands like 'i', which
8329 can be specified in the opcode table? */
8339 INSERT_OPERAND (RS
, *ip
, lastregno
);
8342 INSERT_OPERAND (RT
, *ip
, lastregno
);
8347 case 'O': /* MDMX alignment immediate constant. */
8348 my_getExpression (&imm_expr
, s
);
8349 check_absolute_expr (ip
, &imm_expr
);
8350 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8351 as_warn ("Improper align amount (%ld), using low bits",
8352 (long) imm_expr
.X_add_number
);
8353 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8354 imm_expr
.X_op
= O_absent
;
8358 case 'Q': /* MDMX vector, element sel, or const. */
8361 /* MDMX Immediate. */
8362 my_getExpression (&imm_expr
, s
);
8363 check_absolute_expr (ip
, &imm_expr
);
8364 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8365 as_warn (_("Invalid MDMX Immediate (%ld)"),
8366 (long) imm_expr
.X_add_number
);
8367 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8368 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8369 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8371 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8372 imm_expr
.X_op
= O_absent
;
8376 /* Not MDMX Immediate. Fall through. */
8377 case 'X': /* MDMX destination register. */
8378 case 'Y': /* MDMX source register. */
8379 case 'Z': /* MDMX target register. */
8381 case 'D': /* floating point destination register */
8382 case 'S': /* floating point source register */
8383 case 'T': /* floating point target register */
8384 case 'R': /* floating point source register */
8388 /* Accept $fN for FP and MDMX register numbers, and in
8389 addition accept $vN for MDMX register numbers. */
8390 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8391 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8402 while (ISDIGIT (*s
));
8405 as_bad (_("Invalid float register number (%d)"), regno
);
8407 if ((regno
& 1) != 0
8409 && ! (strcmp (str
, "mtc1") == 0
8410 || strcmp (str
, "mfc1") == 0
8411 || strcmp (str
, "lwc1") == 0
8412 || strcmp (str
, "swc1") == 0
8413 || strcmp (str
, "l.s") == 0
8414 || strcmp (str
, "s.s") == 0))
8415 as_warn (_("Float register should be even, was %d"),
8423 if (c
== 'V' || c
== 'W')
8434 INSERT_OPERAND (FD
, *ip
, regno
);
8439 INSERT_OPERAND (FS
, *ip
, regno
);
8442 /* This is like 'Z', but also needs to fix the MDMX
8443 vector/scalar select bits. Note that the
8444 scalar immediate case is handled above. */
8447 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8448 int max_el
= (is_qh
? 3 : 7);
8450 my_getExpression(&imm_expr
, s
);
8451 check_absolute_expr (ip
, &imm_expr
);
8453 if (imm_expr
.X_add_number
> max_el
)
8454 as_bad(_("Bad element selector %ld"),
8455 (long) imm_expr
.X_add_number
);
8456 imm_expr
.X_add_number
&= max_el
;
8457 ip
->insn_opcode
|= (imm_expr
.X_add_number
8460 imm_expr
.X_op
= O_absent
;
8462 as_warn(_("Expecting ']' found '%s'"), s
);
8468 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8469 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8472 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8479 INSERT_OPERAND (FT
, *ip
, regno
);
8482 INSERT_OPERAND (FR
, *ip
, regno
);
8492 INSERT_OPERAND (FS
, *ip
, lastregno
);
8495 INSERT_OPERAND (FT
, *ip
, lastregno
);
8501 my_getExpression (&imm_expr
, s
);
8502 if (imm_expr
.X_op
!= O_big
8503 && imm_expr
.X_op
!= O_constant
)
8504 insn_error
= _("absolute expression required");
8505 normalize_constant_expr (&imm_expr
);
8510 my_getExpression (&offset_expr
, s
);
8511 *imm_reloc
= BFD_RELOC_32
;
8524 unsigned char temp
[8];
8526 unsigned int length
;
8531 /* These only appear as the last operand in an
8532 instruction, and every instruction that accepts
8533 them in any variant accepts them in all variants.
8534 This means we don't have to worry about backing out
8535 any changes if the instruction does not match.
8537 The difference between them is the size of the
8538 floating point constant and where it goes. For 'F'
8539 and 'L' the constant is 64 bits; for 'f' and 'l' it
8540 is 32 bits. Where the constant is placed is based
8541 on how the MIPS assembler does things:
8544 f -- immediate value
8547 The .lit4 and .lit8 sections are only used if
8548 permitted by the -G argument.
8550 The code below needs to know whether the target register
8551 is 32 or 64 bits wide. It relies on the fact 'f' and
8552 'F' are used with GPR-based instructions and 'l' and
8553 'L' are used with FPR-based instructions. */
8555 f64
= *args
== 'F' || *args
== 'L';
8556 using_gprs
= *args
== 'F' || *args
== 'f';
8558 save_in
= input_line_pointer
;
8559 input_line_pointer
= s
;
8560 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8562 s
= input_line_pointer
;
8563 input_line_pointer
= save_in
;
8564 if (err
!= NULL
&& *err
!= '\0')
8566 as_bad (_("Bad floating point constant: %s"), err
);
8567 memset (temp
, '\0', sizeof temp
);
8568 length
= f64
? 8 : 4;
8571 assert (length
== (unsigned) (f64
? 8 : 4));
8575 && (g_switch_value
< 4
8576 || (temp
[0] == 0 && temp
[1] == 0)
8577 || (temp
[2] == 0 && temp
[3] == 0))))
8579 imm_expr
.X_op
= O_constant
;
8580 if (! target_big_endian
)
8581 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8583 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8586 && ! mips_disable_float_construction
8587 /* Constants can only be constructed in GPRs and
8588 copied to FPRs if the GPRs are at least as wide
8589 as the FPRs. Force the constant into memory if
8590 we are using 64-bit FPRs but the GPRs are only
8593 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8594 && ((temp
[0] == 0 && temp
[1] == 0)
8595 || (temp
[2] == 0 && temp
[3] == 0))
8596 && ((temp
[4] == 0 && temp
[5] == 0)
8597 || (temp
[6] == 0 && temp
[7] == 0)))
8599 /* The value is simple enough to load with a couple of
8600 instructions. If using 32-bit registers, set
8601 imm_expr to the high order 32 bits and offset_expr to
8602 the low order 32 bits. Otherwise, set imm_expr to
8603 the entire 64 bit constant. */
8604 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8606 imm_expr
.X_op
= O_constant
;
8607 offset_expr
.X_op
= O_constant
;
8608 if (! target_big_endian
)
8610 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8611 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8615 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8616 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8618 if (offset_expr
.X_add_number
== 0)
8619 offset_expr
.X_op
= O_absent
;
8621 else if (sizeof (imm_expr
.X_add_number
) > 4)
8623 imm_expr
.X_op
= O_constant
;
8624 if (! target_big_endian
)
8625 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8627 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8631 imm_expr
.X_op
= O_big
;
8632 imm_expr
.X_add_number
= 4;
8633 if (! target_big_endian
)
8635 generic_bignum
[0] = bfd_getl16 (temp
);
8636 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8637 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8638 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8642 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8643 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8644 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8645 generic_bignum
[3] = bfd_getb16 (temp
);
8651 const char *newname
;
8654 /* Switch to the right section. */
8656 subseg
= now_subseg
;
8659 default: /* unused default case avoids warnings. */
8661 newname
= RDATA_SECTION_NAME
;
8662 if (g_switch_value
>= 8)
8666 newname
= RDATA_SECTION_NAME
;
8669 assert (g_switch_value
>= 4);
8673 new_seg
= subseg_new (newname
, (subsegT
) 0);
8674 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8675 bfd_set_section_flags (stdoutput
, new_seg
,
8680 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8681 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8682 && strcmp (TARGET_OS
, "elf") != 0)
8683 record_alignment (new_seg
, 4);
8685 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8687 as_bad (_("Can't use floating point insn in this section"));
8689 /* Set the argument to the current address in the
8691 offset_expr
.X_op
= O_symbol
;
8692 offset_expr
.X_add_symbol
=
8693 symbol_new ("L0\001", now_seg
,
8694 (valueT
) frag_now_fix (), frag_now
);
8695 offset_expr
.X_add_number
= 0;
8697 /* Put the floating point number into the section. */
8698 p
= frag_more ((int) length
);
8699 memcpy (p
, temp
, length
);
8701 /* Switch back to the original section. */
8702 subseg_set (seg
, subseg
);
8707 case 'i': /* 16 bit unsigned immediate */
8708 case 'j': /* 16 bit signed immediate */
8709 *imm_reloc
= BFD_RELOC_LO16
;
8710 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8713 offsetT minval
, maxval
;
8715 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8716 && strcmp (insn
->name
, insn
[1].name
) == 0);
8718 /* If the expression was written as an unsigned number,
8719 only treat it as signed if there are no more
8723 && sizeof (imm_expr
.X_add_number
) <= 4
8724 && imm_expr
.X_op
== O_constant
8725 && imm_expr
.X_add_number
< 0
8726 && imm_expr
.X_unsigned
8730 /* For compatibility with older assemblers, we accept
8731 0x8000-0xffff as signed 16-bit numbers when only
8732 signed numbers are allowed. */
8734 minval
= 0, maxval
= 0xffff;
8736 minval
= -0x8000, maxval
= 0x7fff;
8738 minval
= -0x8000, maxval
= 0xffff;
8740 if (imm_expr
.X_op
!= O_constant
8741 || imm_expr
.X_add_number
< minval
8742 || imm_expr
.X_add_number
> maxval
)
8746 if (imm_expr
.X_op
== O_constant
8747 || imm_expr
.X_op
== O_big
)
8748 as_bad (_("expression out of range"));
8754 case 'o': /* 16 bit offset */
8755 /* Check whether there is only a single bracketed expression
8756 left. If so, it must be the base register and the
8757 constant must be zero. */
8758 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8760 offset_expr
.X_op
= O_constant
;
8761 offset_expr
.X_add_number
= 0;
8765 /* If this value won't fit into a 16 bit offset, then go
8766 find a macro that will generate the 32 bit offset
8768 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8769 && (offset_expr
.X_op
!= O_constant
8770 || offset_expr
.X_add_number
>= 0x8000
8771 || offset_expr
.X_add_number
< -0x8000))
8777 case 'p': /* pc relative offset */
8778 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8779 my_getExpression (&offset_expr
, s
);
8783 case 'u': /* upper 16 bits */
8784 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8785 && imm_expr
.X_op
== O_constant
8786 && (imm_expr
.X_add_number
< 0
8787 || imm_expr
.X_add_number
>= 0x10000))
8788 as_bad (_("lui expression not in range 0..65535"));
8792 case 'a': /* 26 bit address */
8793 my_getExpression (&offset_expr
, s
);
8795 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8798 case 'N': /* 3 bit branch condition code */
8799 case 'M': /* 3 bit compare condition code */
8800 if (strncmp (s
, "$fcc", 4) != 0)
8810 while (ISDIGIT (*s
));
8812 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8813 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8814 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8815 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8816 && (regno
& 1) != 0)
8817 as_warn(_("Condition code register should be even for %s, was %d"),
8819 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8820 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8821 && (regno
& 3) != 0)
8822 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8825 INSERT_OPERAND (BCC
, *ip
, regno
);
8827 INSERT_OPERAND (CCC
, *ip
, regno
);
8831 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8842 while (ISDIGIT (*s
));
8845 c
= 8; /* Invalid sel value. */
8848 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8849 ip
->insn_opcode
|= c
;
8853 /* Must be at least one digit. */
8854 my_getExpression (&imm_expr
, s
);
8855 check_absolute_expr (ip
, &imm_expr
);
8857 if ((unsigned long) imm_expr
.X_add_number
8858 > (unsigned long) OP_MASK_VECBYTE
)
8860 as_bad (_("bad byte vector index (%ld)"),
8861 (long) imm_expr
.X_add_number
);
8862 imm_expr
.X_add_number
= 0;
8865 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8866 imm_expr
.X_op
= O_absent
;
8871 my_getExpression (&imm_expr
, s
);
8872 check_absolute_expr (ip
, &imm_expr
);
8874 if ((unsigned long) imm_expr
.X_add_number
8875 > (unsigned long) OP_MASK_VECALIGN
)
8877 as_bad (_("bad byte vector index (%ld)"),
8878 (long) imm_expr
.X_add_number
);
8879 imm_expr
.X_add_number
= 0;
8882 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8883 imm_expr
.X_op
= O_absent
;
8888 as_bad (_("bad char = '%c'\n"), *args
);
8893 /* Args don't match. */
8894 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8895 !strcmp (insn
->name
, insn
[1].name
))
8899 insn_error
= _("illegal operands");
8904 insn_error
= _("illegal operands");
8909 /* This routine assembles an instruction into its binary format when
8910 assembling for the mips16. As a side effect, it sets one of the
8911 global variables imm_reloc or offset_reloc to the type of
8912 relocation to do if one of the operands is an address expression.
8913 It also sets mips16_small and mips16_ext if the user explicitly
8914 requested a small or extended instruction. */
8917 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
8921 struct mips_opcode
*insn
;
8924 unsigned int lastregno
= 0;
8930 mips16_small
= FALSE
;
8933 for (s
= str
; ISLOWER (*s
); ++s
)
8945 if (s
[1] == 't' && s
[2] == ' ')
8948 mips16_small
= TRUE
;
8952 else if (s
[1] == 'e' && s
[2] == ' ')
8961 insn_error
= _("unknown opcode");
8965 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8966 mips16_small
= TRUE
;
8968 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8970 insn_error
= _("unrecognized opcode");
8977 assert (strcmp (insn
->name
, str
) == 0);
8979 create_insn (ip
, insn
);
8980 imm_expr
.X_op
= O_absent
;
8981 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8982 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8983 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8984 imm2_expr
.X_op
= O_absent
;
8985 offset_expr
.X_op
= O_absent
;
8986 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8987 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8988 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8989 for (args
= insn
->args
; 1; ++args
)
8996 /* In this switch statement we call break if we did not find
8997 a match, continue if we did find a match, or return if we
9006 /* Stuff the immediate value in now, if we can. */
9007 if (imm_expr
.X_op
== O_constant
9008 && *imm_reloc
> BFD_RELOC_UNUSED
9009 && insn
->pinfo
!= INSN_MACRO
)
9013 switch (*offset_reloc
)
9015 case BFD_RELOC_MIPS16_HI16_S
:
9016 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9019 case BFD_RELOC_MIPS16_HI16
:
9020 tmp
= imm_expr
.X_add_number
>> 16;
9023 case BFD_RELOC_MIPS16_LO16
:
9024 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9028 case BFD_RELOC_UNUSED
:
9029 tmp
= imm_expr
.X_add_number
;
9035 *offset_reloc
= BFD_RELOC_UNUSED
;
9037 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9038 tmp
, TRUE
, mips16_small
,
9039 mips16_ext
, &ip
->insn_opcode
,
9040 &ip
->use_extend
, &ip
->extend
);
9041 imm_expr
.X_op
= O_absent
;
9042 *imm_reloc
= BFD_RELOC_UNUSED
;
9056 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9059 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9075 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9077 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9104 while (ISDIGIT (*s
));
9107 as_bad (_("invalid register number (%d)"), regno
);
9113 if (s
[1] == 'r' && s
[2] == 'a')
9118 else if (s
[1] == 'f' && s
[2] == 'p')
9123 else if (s
[1] == 's' && s
[2] == 'p')
9128 else if (s
[1] == 'g' && s
[2] == 'p')
9133 else if (s
[1] == 'a' && s
[2] == 't')
9138 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9143 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9148 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9161 if (c
== 'v' || c
== 'w')
9163 regno
= mips16_to_32_reg_map
[lastregno
];
9177 regno
= mips32_to_16_reg_map
[regno
];
9182 regno
= ILLEGAL_REG
;
9187 regno
= ILLEGAL_REG
;
9192 regno
= ILLEGAL_REG
;
9197 if (regno
== AT
&& ! mips_opts
.noat
)
9198 as_warn (_("used $at without \".set noat\""));
9205 if (regno
== ILLEGAL_REG
)
9212 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9216 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9219 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9222 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9228 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9231 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9232 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9242 if (strncmp (s
, "$pc", 3) == 0)
9259 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9262 if (imm_expr
.X_op
!= O_constant
)
9265 ip
->use_extend
= TRUE
;
9270 /* We need to relax this instruction. */
9271 *offset_reloc
= *imm_reloc
;
9272 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9277 *imm_reloc
= BFD_RELOC_UNUSED
;
9285 my_getExpression (&imm_expr
, s
);
9286 if (imm_expr
.X_op
== O_register
)
9288 /* What we thought was an expression turned out to
9291 if (s
[0] == '(' && args
[1] == '(')
9293 /* It looks like the expression was omitted
9294 before a register indirection, which means
9295 that the expression is implicitly zero. We
9296 still set up imm_expr, so that we handle
9297 explicit extensions correctly. */
9298 imm_expr
.X_op
= O_constant
;
9299 imm_expr
.X_add_number
= 0;
9300 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9307 /* We need to relax this instruction. */
9308 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9317 /* We use offset_reloc rather than imm_reloc for the PC
9318 relative operands. This lets macros with both
9319 immediate and address operands work correctly. */
9320 my_getExpression (&offset_expr
, s
);
9322 if (offset_expr
.X_op
== O_register
)
9325 /* We need to relax this instruction. */
9326 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9330 case '6': /* break code */
9331 my_getExpression (&imm_expr
, s
);
9332 check_absolute_expr (ip
, &imm_expr
);
9333 if ((unsigned long) imm_expr
.X_add_number
> 63)
9334 as_warn (_("Invalid value for `%s' (%lu)"),
9336 (unsigned long) imm_expr
.X_add_number
);
9337 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9338 imm_expr
.X_op
= O_absent
;
9342 case 'a': /* 26 bit address */
9343 my_getExpression (&offset_expr
, s
);
9345 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9346 ip
->insn_opcode
<<= 16;
9349 case 'l': /* register list for entry macro */
9350 case 'L': /* register list for exit macro */
9360 int freg
, reg1
, reg2
;
9362 while (*s
== ' ' || *s
== ',')
9366 as_bad (_("can't parse register list"));
9378 while (ISDIGIT (*s
))
9400 as_bad (_("invalid register list"));
9405 while (ISDIGIT (*s
))
9412 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9417 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9422 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9423 mask
|= (reg2
- 3) << 3;
9424 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9425 mask
|= (reg2
- 15) << 1;
9426 else if (reg1
== RA
&& reg2
== RA
)
9430 as_bad (_("invalid register list"));
9434 /* The mask is filled in in the opcode table for the
9435 benefit of the disassembler. We remove it before
9436 applying the actual mask. */
9437 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9438 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9442 case 'e': /* extend code */
9443 my_getExpression (&imm_expr
, s
);
9444 check_absolute_expr (ip
, &imm_expr
);
9445 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9447 as_warn (_("Invalid value for `%s' (%lu)"),
9449 (unsigned long) imm_expr
.X_add_number
);
9450 imm_expr
.X_add_number
&= 0x7ff;
9452 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9453 imm_expr
.X_op
= O_absent
;
9463 /* Args don't match. */
9464 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9465 strcmp (insn
->name
, insn
[1].name
) == 0)
9472 insn_error
= _("illegal operands");
9478 /* This structure holds information we know about a mips16 immediate
9481 struct mips16_immed_operand
9483 /* The type code used in the argument string in the opcode table. */
9485 /* The number of bits in the short form of the opcode. */
9487 /* The number of bits in the extended form of the opcode. */
9489 /* The amount by which the short form is shifted when it is used;
9490 for example, the sw instruction has a shift count of 2. */
9492 /* The amount by which the short form is shifted when it is stored
9493 into the instruction code. */
9495 /* Non-zero if the short form is unsigned. */
9497 /* Non-zero if the extended form is unsigned. */
9499 /* Non-zero if the value is PC relative. */
9503 /* The mips16 immediate operand types. */
9505 static const struct mips16_immed_operand mips16_immed_operands
[] =
9507 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9508 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9509 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9510 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9511 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9512 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9513 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9514 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9515 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9516 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9517 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9518 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9519 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9520 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9521 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9522 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9523 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9524 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9525 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9526 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9527 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9530 #define MIPS16_NUM_IMMED \
9531 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9533 /* Handle a mips16 instruction with an immediate value. This or's the
9534 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9535 whether an extended value is needed; if one is needed, it sets
9536 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9537 If SMALL is true, an unextended opcode was explicitly requested.
9538 If EXT is true, an extended opcode was explicitly requested. If
9539 WARN is true, warn if EXT does not match reality. */
9542 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9543 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9544 unsigned long *insn
, bfd_boolean
*use_extend
,
9545 unsigned short *extend
)
9547 register const struct mips16_immed_operand
*op
;
9548 int mintiny
, maxtiny
;
9549 bfd_boolean needext
;
9551 op
= mips16_immed_operands
;
9552 while (op
->type
!= type
)
9555 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9560 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9563 maxtiny
= 1 << op
->nbits
;
9568 maxtiny
= (1 << op
->nbits
) - 1;
9573 mintiny
= - (1 << (op
->nbits
- 1));
9574 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9577 /* Branch offsets have an implicit 0 in the lowest bit. */
9578 if (type
== 'p' || type
== 'q')
9581 if ((val
& ((1 << op
->shift
) - 1)) != 0
9582 || val
< (mintiny
<< op
->shift
)
9583 || val
> (maxtiny
<< op
->shift
))
9588 if (warn
&& ext
&& ! needext
)
9589 as_warn_where (file
, line
,
9590 _("extended operand requested but not required"));
9591 if (small
&& needext
)
9592 as_bad_where (file
, line
, _("invalid unextended operand value"));
9594 if (small
|| (! ext
&& ! needext
))
9598 *use_extend
= FALSE
;
9599 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9600 insnval
<<= op
->op_shift
;
9605 long minext
, maxext
;
9611 maxext
= (1 << op
->extbits
) - 1;
9615 minext
= - (1 << (op
->extbits
- 1));
9616 maxext
= (1 << (op
->extbits
- 1)) - 1;
9618 if (val
< minext
|| val
> maxext
)
9619 as_bad_where (file
, line
,
9620 _("operand value out of range for instruction"));
9623 if (op
->extbits
== 16)
9625 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9628 else if (op
->extbits
== 15)
9630 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9635 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9639 *extend
= (unsigned short) extval
;
9644 struct percent_op_match
9647 bfd_reloc_code_real_type reloc
;
9650 static const struct percent_op_match mips_percent_op
[] =
9652 {"%lo", BFD_RELOC_LO16
},
9654 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9655 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9656 {"%call16", BFD_RELOC_MIPS_CALL16
},
9657 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9658 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9659 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9660 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9661 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9662 {"%got", BFD_RELOC_MIPS_GOT16
},
9663 {"%gp_rel", BFD_RELOC_GPREL16
},
9664 {"%half", BFD_RELOC_16
},
9665 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9666 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9667 {"%neg", BFD_RELOC_MIPS_SUB
},
9668 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9669 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9670 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9671 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9672 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9673 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9674 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9676 {"%hi", BFD_RELOC_HI16_S
}
9679 static const struct percent_op_match mips16_percent_op
[] =
9681 {"%lo", BFD_RELOC_MIPS16_LO16
},
9682 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9683 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9687 /* Return true if *STR points to a relocation operator. When returning true,
9688 move *STR over the operator and store its relocation code in *RELOC.
9689 Leave both *STR and *RELOC alone when returning false. */
9692 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9694 const struct percent_op_match
*percent_op
;
9697 if (mips_opts
.mips16
)
9699 percent_op
= mips16_percent_op
;
9700 limit
= ARRAY_SIZE (mips16_percent_op
);
9704 percent_op
= mips_percent_op
;
9705 limit
= ARRAY_SIZE (mips_percent_op
);
9708 for (i
= 0; i
< limit
; i
++)
9709 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9711 int len
= strlen (percent_op
[i
].str
);
9713 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9716 *str
+= strlen (percent_op
[i
].str
);
9717 *reloc
= percent_op
[i
].reloc
;
9719 /* Check whether the output BFD supports this relocation.
9720 If not, issue an error and fall back on something safe. */
9721 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9723 as_bad ("relocation %s isn't supported by the current ABI",
9725 *reloc
= BFD_RELOC_UNUSED
;
9733 /* Parse string STR as a 16-bit relocatable operand. Store the
9734 expression in *EP and the relocations in the array starting
9735 at RELOC. Return the number of relocation operators used.
9737 On exit, EXPR_END points to the first character after the expression. */
9740 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9743 bfd_reloc_code_real_type reversed_reloc
[3];
9744 size_t reloc_index
, i
;
9745 int crux_depth
, str_depth
;
9748 /* Search for the start of the main expression, recoding relocations
9749 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9750 of the main expression and with CRUX_DEPTH containing the number
9751 of open brackets at that point. */
9758 crux_depth
= str_depth
;
9760 /* Skip over whitespace and brackets, keeping count of the number
9762 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9767 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9768 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9770 my_getExpression (ep
, crux
);
9773 /* Match every open bracket. */
9774 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9779 as_bad ("unclosed '('");
9783 if (reloc_index
!= 0)
9785 prev_reloc_op_frag
= frag_now
;
9786 for (i
= 0; i
< reloc_index
; i
++)
9787 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9794 my_getExpression (expressionS
*ep
, char *str
)
9799 save_in
= input_line_pointer
;
9800 input_line_pointer
= str
;
9802 expr_end
= input_line_pointer
;
9803 input_line_pointer
= save_in
;
9805 /* If we are in mips16 mode, and this is an expression based on `.',
9806 then we bump the value of the symbol by 1 since that is how other
9807 text symbols are handled. We don't bother to handle complex
9808 expressions, just `.' plus or minus a constant. */
9809 if (mips_opts
.mips16
9810 && ep
->X_op
== O_symbol
9811 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9812 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9813 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9814 && symbol_constant_p (ep
->X_add_symbol
)
9815 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9816 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9819 /* Turn a string in input_line_pointer into a floating point constant
9820 of type TYPE, and store the appropriate bytes in *LITP. The number
9821 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9822 returned, or NULL on OK. */
9825 md_atof (int type
, char *litP
, int *sizeP
)
9828 LITTLENUM_TYPE words
[4];
9844 return _("bad call to md_atof");
9847 t
= atof_ieee (input_line_pointer
, type
, words
);
9849 input_line_pointer
= t
;
9853 if (! target_big_endian
)
9855 for (i
= prec
- 1; i
>= 0; i
--)
9857 md_number_to_chars (litP
, words
[i
], 2);
9863 for (i
= 0; i
< prec
; i
++)
9865 md_number_to_chars (litP
, words
[i
], 2);
9874 md_number_to_chars (char *buf
, valueT val
, int n
)
9876 if (target_big_endian
)
9877 number_to_chars_bigendian (buf
, val
, n
);
9879 number_to_chars_littleendian (buf
, val
, n
);
9883 static int support_64bit_objects(void)
9885 const char **list
, **l
;
9888 list
= bfd_target_list ();
9889 for (l
= list
; *l
!= NULL
; l
++)
9891 /* This is traditional mips */
9892 if (strcmp (*l
, "elf64-tradbigmips") == 0
9893 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9895 if (strcmp (*l
, "elf64-bigmips") == 0
9896 || strcmp (*l
, "elf64-littlemips") == 0)
9903 #endif /* OBJ_ELF */
9905 const char *md_shortopts
= "O::g::G:";
9907 struct option md_longopts
[] =
9909 /* Options which specify architecture. */
9910 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9911 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9912 {"march", required_argument
, NULL
, OPTION_MARCH
},
9913 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9914 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9915 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9916 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9917 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9918 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
9919 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9920 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
9921 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9922 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
9923 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9924 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
9925 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9926 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
9927 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9928 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
9929 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9930 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
9931 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
9932 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
9933 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
9935 /* Options which specify Application Specific Extensions (ASEs). */
9936 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
9937 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
9938 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9939 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
9940 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9941 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
9942 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9943 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
9944 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9945 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
9946 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
9947 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
9948 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
9950 /* Old-style architecture options. Don't add more of these. */
9951 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
9952 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
9953 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9954 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
9955 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9956 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
9957 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9958 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
9959 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9960 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
9961 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9962 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
9963 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9964 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
9965 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9966 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
9967 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9969 /* Options which enable bug fixes. */
9970 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
9971 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
9972 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9973 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
9974 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9975 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9976 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
9977 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
9978 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
9979 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
9981 /* Miscellaneous options. */
9982 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
9983 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
9984 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9985 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9986 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
9987 {"break", no_argument
, NULL
, OPTION_BREAK
},
9988 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9989 #define OPTION_EB (OPTION_MISC_BASE + 2)
9990 {"EB", no_argument
, NULL
, OPTION_EB
},
9991 #define OPTION_EL (OPTION_MISC_BASE + 3)
9992 {"EL", no_argument
, NULL
, OPTION_EL
},
9993 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
9994 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9995 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
9996 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9997 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
9998 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9999 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10000 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10001 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10002 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10003 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10004 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10005 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10006 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10007 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10008 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10009 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10010 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10011 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10012 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10013 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10014 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10015 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10016 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10018 /* ELF-specific options. */
10020 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10021 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10022 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10023 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10024 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10025 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10026 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10027 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10028 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10029 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10030 #define OPTION_32 (OPTION_ELF_BASE + 4)
10031 {"32", no_argument
, NULL
, OPTION_32
},
10032 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10033 {"n32", no_argument
, NULL
, OPTION_N32
},
10034 #define OPTION_64 (OPTION_ELF_BASE + 6)
10035 {"64", no_argument
, NULL
, OPTION_64
},
10036 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10037 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10038 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10039 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10040 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10041 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10042 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10043 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10044 #endif /* OBJ_ELF */
10046 {NULL
, no_argument
, NULL
, 0}
10048 size_t md_longopts_size
= sizeof (md_longopts
);
10050 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10051 NEW_VALUE. Warn if another value was already specified. Note:
10052 we have to defer parsing the -march and -mtune arguments in order
10053 to handle 'from-abi' correctly, since the ABI might be specified
10054 in a later argument. */
10057 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10059 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10060 as_warn (_("A different %s was already specified, is now %s"),
10061 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10064 *string_ptr
= new_value
;
10068 md_parse_option (int c
, char *arg
)
10072 case OPTION_CONSTRUCT_FLOATS
:
10073 mips_disable_float_construction
= 0;
10076 case OPTION_NO_CONSTRUCT_FLOATS
:
10077 mips_disable_float_construction
= 1;
10089 target_big_endian
= 1;
10093 target_big_endian
= 0;
10097 if (arg
&& arg
[1] == '0')
10107 mips_debug
= atoi (arg
);
10108 /* When the MIPS assembler sees -g or -g2, it does not do
10109 optimizations which limit full symbolic debugging. We take
10110 that to be equivalent to -O0. */
10111 if (mips_debug
== 2)
10116 file_mips_isa
= ISA_MIPS1
;
10120 file_mips_isa
= ISA_MIPS2
;
10124 file_mips_isa
= ISA_MIPS3
;
10128 file_mips_isa
= ISA_MIPS4
;
10132 file_mips_isa
= ISA_MIPS5
;
10135 case OPTION_MIPS32
:
10136 file_mips_isa
= ISA_MIPS32
;
10139 case OPTION_MIPS32R2
:
10140 file_mips_isa
= ISA_MIPS32R2
;
10143 case OPTION_MIPS64R2
:
10144 file_mips_isa
= ISA_MIPS64R2
;
10147 case OPTION_MIPS64
:
10148 file_mips_isa
= ISA_MIPS64
;
10152 mips_set_option_string (&mips_tune_string
, arg
);
10156 mips_set_option_string (&mips_arch_string
, arg
);
10160 mips_set_option_string (&mips_arch_string
, "4650");
10161 mips_set_option_string (&mips_tune_string
, "4650");
10164 case OPTION_NO_M4650
:
10168 mips_set_option_string (&mips_arch_string
, "4010");
10169 mips_set_option_string (&mips_tune_string
, "4010");
10172 case OPTION_NO_M4010
:
10176 mips_set_option_string (&mips_arch_string
, "4100");
10177 mips_set_option_string (&mips_tune_string
, "4100");
10180 case OPTION_NO_M4100
:
10184 mips_set_option_string (&mips_arch_string
, "3900");
10185 mips_set_option_string (&mips_tune_string
, "3900");
10188 case OPTION_NO_M3900
:
10192 mips_opts
.ase_mdmx
= 1;
10195 case OPTION_NO_MDMX
:
10196 mips_opts
.ase_mdmx
= 0;
10199 case OPTION_MIPS16
:
10200 mips_opts
.mips16
= 1;
10201 mips_no_prev_insn ();
10204 case OPTION_NO_MIPS16
:
10205 mips_opts
.mips16
= 0;
10206 mips_no_prev_insn ();
10209 case OPTION_MIPS3D
:
10210 mips_opts
.ase_mips3d
= 1;
10213 case OPTION_NO_MIPS3D
:
10214 mips_opts
.ase_mips3d
= 0;
10217 case OPTION_FIX_VR4120
:
10218 mips_fix_vr4120
= 1;
10221 case OPTION_NO_FIX_VR4120
:
10222 mips_fix_vr4120
= 0;
10225 case OPTION_RELAX_BRANCH
:
10226 mips_relax_branch
= 1;
10229 case OPTION_NO_RELAX_BRANCH
:
10230 mips_relax_branch
= 0;
10233 case OPTION_MSHARED
:
10234 mips_in_shared
= TRUE
;
10237 case OPTION_MNO_SHARED
:
10238 mips_in_shared
= FALSE
;
10241 case OPTION_MSYM32
:
10242 mips_opts
.sym32
= TRUE
;
10245 case OPTION_MNO_SYM32
:
10246 mips_opts
.sym32
= FALSE
;
10250 /* When generating ELF code, we permit -KPIC and -call_shared to
10251 select SVR4_PIC, and -non_shared to select no PIC. This is
10252 intended to be compatible with Irix 5. */
10253 case OPTION_CALL_SHARED
:
10254 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10256 as_bad (_("-call_shared is supported only for ELF format"));
10259 mips_pic
= SVR4_PIC
;
10260 mips_abicalls
= TRUE
;
10261 if (g_switch_seen
&& g_switch_value
!= 0)
10263 as_bad (_("-G may not be used with SVR4 PIC code"));
10266 g_switch_value
= 0;
10269 case OPTION_NON_SHARED
:
10270 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10272 as_bad (_("-non_shared is supported only for ELF format"));
10276 mips_abicalls
= FALSE
;
10279 /* The -xgot option tells the assembler to use 32 offsets when
10280 accessing the got in SVR4_PIC mode. It is for Irix
10285 #endif /* OBJ_ELF */
10288 g_switch_value
= atoi (arg
);
10290 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10292 as_bad (_("-G may not be used with SVR4 PIC code"));
10298 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10301 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10303 as_bad (_("-32 is supported for ELF format only"));
10306 mips_abi
= O32_ABI
;
10310 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10312 as_bad (_("-n32 is supported for ELF format only"));
10315 mips_abi
= N32_ABI
;
10319 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10321 as_bad (_("-64 is supported for ELF format only"));
10324 mips_abi
= N64_ABI
;
10325 if (! support_64bit_objects())
10326 as_fatal (_("No compiled in support for 64 bit object file format"));
10328 #endif /* OBJ_ELF */
10331 file_mips_gp32
= 1;
10335 file_mips_gp32
= 0;
10339 file_mips_fp32
= 1;
10343 file_mips_fp32
= 0;
10348 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10350 as_bad (_("-mabi is supported for ELF format only"));
10353 if (strcmp (arg
, "32") == 0)
10354 mips_abi
= O32_ABI
;
10355 else if (strcmp (arg
, "o64") == 0)
10356 mips_abi
= O64_ABI
;
10357 else if (strcmp (arg
, "n32") == 0)
10358 mips_abi
= N32_ABI
;
10359 else if (strcmp (arg
, "64") == 0)
10361 mips_abi
= N64_ABI
;
10362 if (! support_64bit_objects())
10363 as_fatal (_("No compiled in support for 64 bit object file "
10366 else if (strcmp (arg
, "eabi") == 0)
10367 mips_abi
= EABI_ABI
;
10370 as_fatal (_("invalid abi -mabi=%s"), arg
);
10374 #endif /* OBJ_ELF */
10376 case OPTION_M7000_HILO_FIX
:
10377 mips_7000_hilo_fix
= TRUE
;
10380 case OPTION_MNO_7000_HILO_FIX
:
10381 mips_7000_hilo_fix
= FALSE
;
10385 case OPTION_MDEBUG
:
10386 mips_flag_mdebug
= TRUE
;
10389 case OPTION_NO_MDEBUG
:
10390 mips_flag_mdebug
= FALSE
;
10394 mips_flag_pdr
= TRUE
;
10397 case OPTION_NO_PDR
:
10398 mips_flag_pdr
= FALSE
;
10400 #endif /* OBJ_ELF */
10409 /* Set up globals to generate code for the ISA or processor
10410 described by INFO. */
10413 mips_set_architecture (const struct mips_cpu_info
*info
)
10417 file_mips_arch
= info
->cpu
;
10418 mips_opts
.arch
= info
->cpu
;
10419 mips_opts
.isa
= info
->isa
;
10424 /* Likewise for tuning. */
10427 mips_set_tune (const struct mips_cpu_info
*info
)
10430 mips_tune
= info
->cpu
;
10435 mips_after_parse_args (void)
10437 const struct mips_cpu_info
*arch_info
= 0;
10438 const struct mips_cpu_info
*tune_info
= 0;
10440 /* GP relative stuff not working for PE */
10441 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10443 if (g_switch_seen
&& g_switch_value
!= 0)
10444 as_bad (_("-G not supported in this configuration."));
10445 g_switch_value
= 0;
10448 if (mips_abi
== NO_ABI
)
10449 mips_abi
= MIPS_DEFAULT_ABI
;
10451 /* The following code determines the architecture and register size.
10452 Similar code was added to GCC 3.3 (see override_options() in
10453 config/mips/mips.c). The GAS and GCC code should be kept in sync
10454 as much as possible. */
10456 if (mips_arch_string
!= 0)
10457 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10459 if (file_mips_isa
!= ISA_UNKNOWN
)
10461 /* Handle -mipsN. At this point, file_mips_isa contains the
10462 ISA level specified by -mipsN, while arch_info->isa contains
10463 the -march selection (if any). */
10464 if (arch_info
!= 0)
10466 /* -march takes precedence over -mipsN, since it is more descriptive.
10467 There's no harm in specifying both as long as the ISA levels
10469 if (file_mips_isa
!= arch_info
->isa
)
10470 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10471 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10472 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10475 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10478 if (arch_info
== 0)
10479 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10481 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10482 as_bad ("-march=%s is not compatible with the selected ABI",
10485 mips_set_architecture (arch_info
);
10487 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10488 if (mips_tune_string
!= 0)
10489 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10491 if (tune_info
== 0)
10492 mips_set_tune (arch_info
);
10494 mips_set_tune (tune_info
);
10496 if (file_mips_gp32
>= 0)
10498 /* The user specified the size of the integer registers. Make sure
10499 it agrees with the ABI and ISA. */
10500 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10501 as_bad (_("-mgp64 used with a 32-bit processor"));
10502 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10503 as_bad (_("-mgp32 used with a 64-bit ABI"));
10504 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10505 as_bad (_("-mgp64 used with a 32-bit ABI"));
10509 /* Infer the integer register size from the ABI and processor.
10510 Restrict ourselves to 32-bit registers if that's all the
10511 processor has, or if the ABI cannot handle 64-bit registers. */
10512 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10513 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10516 /* ??? GAS treats single-float processors as though they had 64-bit
10517 float registers (although it complains when double-precision
10518 instructions are used). As things stand, saying they have 32-bit
10519 registers would lead to spurious "register must be even" messages.
10520 So here we assume float registers are always the same size as
10521 integer ones, unless the user says otherwise. */
10522 if (file_mips_fp32
< 0)
10523 file_mips_fp32
= file_mips_gp32
;
10525 /* End of GCC-shared inference code. */
10527 /* This flag is set when we have a 64-bit capable CPU but use only
10528 32-bit wide registers. Note that EABI does not use it. */
10529 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10530 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10531 || mips_abi
== O32_ABI
))
10532 mips_32bitmode
= 1;
10534 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10535 as_bad (_("trap exception not supported at ISA 1"));
10537 /* If the selected architecture includes support for ASEs, enable
10538 generation of code for them. */
10539 if (mips_opts
.mips16
== -1)
10540 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10541 if (mips_opts
.ase_mips3d
== -1)
10542 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10543 if (mips_opts
.ase_mdmx
== -1)
10544 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10546 file_mips_isa
= mips_opts
.isa
;
10547 file_ase_mips16
= mips_opts
.mips16
;
10548 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10549 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10550 mips_opts
.gp32
= file_mips_gp32
;
10551 mips_opts
.fp32
= file_mips_fp32
;
10553 if (mips_flag_mdebug
< 0)
10555 #ifdef OBJ_MAYBE_ECOFF
10556 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10557 mips_flag_mdebug
= 1;
10559 #endif /* OBJ_MAYBE_ECOFF */
10560 mips_flag_mdebug
= 0;
10565 mips_init_after_args (void)
10567 /* initialize opcodes */
10568 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10569 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10573 md_pcrel_from (fixS
*fixP
)
10575 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10576 switch (fixP
->fx_r_type
)
10578 case BFD_RELOC_16_PCREL_S2
:
10579 case BFD_RELOC_MIPS_JMP
:
10580 /* Return the address of the delay slot. */
10587 /* This is called before the symbol table is processed. In order to
10588 work with gcc when using mips-tfile, we must keep all local labels.
10589 However, in other cases, we want to discard them. If we were
10590 called with -g, but we didn't see any debugging information, it may
10591 mean that gcc is smuggling debugging information through to
10592 mips-tfile, in which case we must generate all local labels. */
10595 mips_frob_file_before_adjust (void)
10597 #ifndef NO_ECOFF_DEBUGGING
10598 if (ECOFF_DEBUGGING
10600 && ! ecoff_debugging_seen
)
10601 flag_keep_locals
= 1;
10605 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10606 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10607 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10608 relocation operators.
10610 For our purposes, a %lo() expression matches a %got() or %hi()
10613 (a) it refers to the same symbol; and
10614 (b) the offset applied in the %lo() expression is no lower than
10615 the offset applied in the %got() or %hi().
10617 (b) allows us to cope with code like:
10620 lh $4,%lo(foo+2)($4)
10622 ...which is legal on RELA targets, and has a well-defined behaviour
10623 if the user knows that adding 2 to "foo" will not induce a carry to
10626 When several %lo()s match a particular %got() or %hi(), we use the
10627 following rules to distinguish them:
10629 (1) %lo()s with smaller offsets are a better match than %lo()s with
10632 (2) %lo()s with no matching %got() or %hi() are better than those
10633 that already have a matching %got() or %hi().
10635 (3) later %lo()s are better than earlier %lo()s.
10637 These rules are applied in order.
10639 (1) means, among other things, that %lo()s with identical offsets are
10640 chosen if they exist.
10642 (2) means that we won't associate several high-part relocations with
10643 the same low-part relocation unless there's no alternative. Having
10644 several high parts for the same low part is a GNU extension; this rule
10645 allows careful users to avoid it.
10647 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10648 with the last high-part relocation being at the front of the list.
10649 It therefore makes sense to choose the last matching low-part
10650 relocation, all other things being equal. It's also easier
10651 to code that way. */
10654 mips_frob_file (void)
10656 struct mips_hi_fixup
*l
;
10658 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10660 segment_info_type
*seginfo
;
10661 bfd_boolean matched_lo_p
;
10662 fixS
**hi_pos
, **lo_pos
, **pos
;
10664 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10666 /* If a GOT16 relocation turns out to be against a global symbol,
10667 there isn't supposed to be a matching LO. */
10668 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10669 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10672 /* Check quickly whether the next fixup happens to be a matching %lo. */
10673 if (fixup_has_matching_lo_p (l
->fixp
))
10676 seginfo
= seg_info (l
->seg
);
10678 /* Set HI_POS to the position of this relocation in the chain.
10679 Set LO_POS to the position of the chosen low-part relocation.
10680 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10681 relocation that matches an immediately-preceding high-part
10685 matched_lo_p
= FALSE
;
10686 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10688 if (*pos
== l
->fixp
)
10691 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10692 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10693 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10695 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10697 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10700 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10701 && fixup_has_matching_lo_p (*pos
));
10704 /* If we found a match, remove the high-part relocation from its
10705 current position and insert it before the low-part relocation.
10706 Make the offsets match so that fixup_has_matching_lo_p()
10709 We don't warn about unmatched high-part relocations since some
10710 versions of gcc have been known to emit dead "lui ...%hi(...)"
10712 if (lo_pos
!= NULL
)
10714 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10715 if (l
->fixp
->fx_next
!= *lo_pos
)
10717 *hi_pos
= l
->fixp
->fx_next
;
10718 l
->fixp
->fx_next
= *lo_pos
;
10725 /* We may have combined relocations without symbols in the N32/N64 ABI.
10726 We have to prevent gas from dropping them. */
10729 mips_force_relocation (fixS
*fixp
)
10731 if (generic_force_reloc (fixp
))
10735 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10736 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10737 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10738 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10744 /* This hook is called before a fix is simplified. We don't really
10745 decide whether to skip a fix here. Rather, we turn global symbols
10746 used as branch targets into local symbols, such that they undergo
10747 simplification. We can only do this if the symbol is defined and
10748 it is in the same section as the branch. If this doesn't hold, we
10749 emit a better error message than just saying the relocation is not
10750 valid for the selected object format.
10752 FIXP is the fix-up we're going to try to simplify, SEG is the
10753 segment in which the fix up occurs. The return value should be
10754 non-zero to indicate the fix-up is valid for further
10755 simplifications. */
10758 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10760 /* There's a lot of discussion on whether it should be possible to
10761 use R_MIPS_PC16 to represent branch relocations. The outcome
10762 seems to be that it can, but gas/bfd are very broken in creating
10763 RELA relocations for this, so for now we only accept branches to
10764 symbols in the same section. Anything else is of dubious value,
10765 since there's no guarantee that at link time the symbol would be
10766 in range. Even for branches to local symbols this is arguably
10767 wrong, since it we assume the symbol is not going to be
10768 overridden, which should be possible per ELF library semantics,
10769 but then, there isn't a dynamic relocation that could be used to
10770 this effect, and the target would likely be out of range as well.
10772 Unfortunately, it seems that there is too much code out there
10773 that relies on branches to symbols that are global to be resolved
10774 as if they were local, like the IRIX tools do, so we do it as
10775 well, but with a warning so that people are reminded to fix their
10776 code. If we ever get back to using R_MIPS_PC16 for branch
10777 targets, this entire block should go away (and probably the
10778 whole function). */
10780 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10781 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10782 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10783 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10786 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10789 _("Cannot branch to undefined symbol."));
10790 /* Avoid any further errors about this fixup. */
10793 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10796 _("Cannot branch to symbol in another section."));
10799 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10801 symbolS
*sym
= fixP
->fx_addsy
;
10803 if (mips_pic
== SVR4_PIC
)
10804 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10805 _("Pretending global symbol used as branch target is local."));
10807 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10808 S_GET_SEGMENT (sym
),
10810 symbol_get_frag (sym
));
10811 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10812 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10813 assert (symbol_resolved_p (sym
));
10814 symbol_mark_resolved (fixP
->fx_addsy
);
10821 /* Apply a fixup to the object file. */
10824 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10828 reloc_howto_type
*howto
;
10830 /* We ignore generic BFD relocations we don't know about. */
10831 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10835 assert (fixP
->fx_size
== 4
10836 || fixP
->fx_r_type
== BFD_RELOC_16
10837 || fixP
->fx_r_type
== BFD_RELOC_64
10838 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10839 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10840 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10841 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10843 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10845 assert (! fixP
->fx_pcrel
);
10847 /* Don't treat parts of a composite relocation as done. There are two
10850 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10851 should nevertheless be emitted if the first part is.
10853 (2) In normal usage, composite relocations are never assembly-time
10854 constants. The easiest way of dealing with the pathological
10855 exceptions is to generate a relocation against STN_UNDEF and
10856 leave everything up to the linker. */
10857 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10860 switch (fixP
->fx_r_type
)
10862 case BFD_RELOC_MIPS_TLS_GD
:
10863 case BFD_RELOC_MIPS_TLS_LDM
:
10864 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10865 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10866 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10867 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10868 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10869 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10872 case BFD_RELOC_MIPS_JMP
:
10873 case BFD_RELOC_MIPS_SHIFT5
:
10874 case BFD_RELOC_MIPS_SHIFT6
:
10875 case BFD_RELOC_MIPS_GOT_DISP
:
10876 case BFD_RELOC_MIPS_GOT_PAGE
:
10877 case BFD_RELOC_MIPS_GOT_OFST
:
10878 case BFD_RELOC_MIPS_SUB
:
10879 case BFD_RELOC_MIPS_INSERT_A
:
10880 case BFD_RELOC_MIPS_INSERT_B
:
10881 case BFD_RELOC_MIPS_DELETE
:
10882 case BFD_RELOC_MIPS_HIGHEST
:
10883 case BFD_RELOC_MIPS_HIGHER
:
10884 case BFD_RELOC_MIPS_SCN_DISP
:
10885 case BFD_RELOC_MIPS_REL16
:
10886 case BFD_RELOC_MIPS_RELGOT
:
10887 case BFD_RELOC_MIPS_JALR
:
10888 case BFD_RELOC_HI16
:
10889 case BFD_RELOC_HI16_S
:
10890 case BFD_RELOC_GPREL16
:
10891 case BFD_RELOC_MIPS_LITERAL
:
10892 case BFD_RELOC_MIPS_CALL16
:
10893 case BFD_RELOC_MIPS_GOT16
:
10894 case BFD_RELOC_GPREL32
:
10895 case BFD_RELOC_MIPS_GOT_HI16
:
10896 case BFD_RELOC_MIPS_GOT_LO16
:
10897 case BFD_RELOC_MIPS_CALL_HI16
:
10898 case BFD_RELOC_MIPS_CALL_LO16
:
10899 case BFD_RELOC_MIPS16_GPREL
:
10900 case BFD_RELOC_MIPS16_HI16
:
10901 case BFD_RELOC_MIPS16_HI16_S
:
10902 assert (! fixP
->fx_pcrel
);
10903 /* Nothing needed to do. The value comes from the reloc entry */
10906 case BFD_RELOC_MIPS16_JMP
:
10907 /* We currently always generate a reloc against a symbol, which
10908 means that we don't want an addend even if the symbol is
10914 /* This is handled like BFD_RELOC_32, but we output a sign
10915 extended value if we are only 32 bits. */
10918 if (8 <= sizeof (valueT
))
10919 md_number_to_chars ((char *) buf
, *valP
, 8);
10924 if ((*valP
& 0x80000000) != 0)
10928 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
10930 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
10936 case BFD_RELOC_RVA
:
10938 /* If we are deleting this reloc entry, we must fill in the
10939 value now. This can happen if we have a .word which is not
10940 resolved when it appears but is later defined. */
10942 md_number_to_chars ((char *) buf
, *valP
, 4);
10946 /* If we are deleting this reloc entry, we must fill in the
10949 md_number_to_chars ((char *) buf
, *valP
, 2);
10952 case BFD_RELOC_LO16
:
10953 case BFD_RELOC_MIPS16_LO16
:
10954 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
10955 may be safe to remove, but if so it's not obvious. */
10956 /* When handling an embedded PIC switch statement, we can wind
10957 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10960 if (*valP
+ 0x8000 > 0xffff)
10961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10962 _("relocation overflow"));
10963 if (target_big_endian
)
10965 md_number_to_chars ((char *) buf
, *valP
, 2);
10969 case BFD_RELOC_16_PCREL_S2
:
10970 if ((*valP
& 0x3) != 0)
10971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10972 _("Branch to odd address (%lx)"), (long) *valP
);
10975 * We need to save the bits in the instruction since fixup_segment()
10976 * might be deleting the relocation entry (i.e., a branch within
10977 * the current segment).
10979 if (! fixP
->fx_done
)
10982 /* update old instruction data */
10983 if (target_big_endian
)
10984 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10986 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10988 if (*valP
+ 0x20000 <= 0x3ffff)
10990 insn
|= (*valP
>> 2) & 0xffff;
10991 md_number_to_chars ((char *) buf
, insn
, 4);
10993 else if (mips_pic
== NO_PIC
10995 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10996 && (fixP
->fx_frag
->fr_address
10997 < text_section
->vma
+ bfd_get_section_size (text_section
))
10998 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10999 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11000 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11002 /* The branch offset is too large. If this is an
11003 unconditional branch, and we are not generating PIC code,
11004 we can convert it to an absolute jump instruction. */
11005 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11006 insn
= 0x0c000000; /* jal */
11008 insn
= 0x08000000; /* j */
11009 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11011 fixP
->fx_addsy
= section_symbol (text_section
);
11012 *valP
+= md_pcrel_from (fixP
);
11013 md_number_to_chars ((char *) buf
, insn
, 4);
11017 /* If we got here, we have branch-relaxation disabled,
11018 and there's nothing we can do to fix this instruction
11019 without turning it into a longer sequence. */
11020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11021 _("Branch out of range"));
11025 case BFD_RELOC_VTABLE_INHERIT
:
11028 && !S_IS_DEFINED (fixP
->fx_addsy
)
11029 && !S_IS_WEAK (fixP
->fx_addsy
))
11030 S_SET_WEAK (fixP
->fx_addsy
);
11033 case BFD_RELOC_VTABLE_ENTRY
:
11041 /* Remember value for tc_gen_reloc. */
11042 fixP
->fx_addnumber
= *valP
;
11052 name
= input_line_pointer
;
11053 c
= get_symbol_end ();
11054 p
= (symbolS
*) symbol_find_or_make (name
);
11055 *input_line_pointer
= c
;
11059 /* Align the current frag to a given power of two. The MIPS assembler
11060 also automatically adjusts any preceding label. */
11063 mips_align (int to
, int fill
, symbolS
*label
)
11065 mips_emit_delays ();
11066 frag_align (to
, fill
, 0);
11067 record_alignment (now_seg
, to
);
11070 assert (S_GET_SEGMENT (label
) == now_seg
);
11071 symbol_set_frag (label
, frag_now
);
11072 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11076 /* Align to a given power of two. .align 0 turns off the automatic
11077 alignment used by the data creating pseudo-ops. */
11080 s_align (int x ATTRIBUTE_UNUSED
)
11083 register long temp_fill
;
11084 long max_alignment
= 15;
11088 o Note that the assembler pulls down any immediately preceding label
11089 to the aligned address.
11090 o It's not documented but auto alignment is reinstated by
11091 a .align pseudo instruction.
11092 o Note also that after auto alignment is turned off the mips assembler
11093 issues an error on attempt to assemble an improperly aligned data item.
11098 temp
= get_absolute_expression ();
11099 if (temp
> max_alignment
)
11100 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11103 as_warn (_("Alignment negative: 0 assumed."));
11106 if (*input_line_pointer
== ',')
11108 ++input_line_pointer
;
11109 temp_fill
= get_absolute_expression ();
11116 mips_align (temp
, (int) temp_fill
,
11117 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11124 demand_empty_rest_of_line ();
11128 s_change_sec (int sec
)
11133 /* The ELF backend needs to know that we are changing sections, so
11134 that .previous works correctly. We could do something like check
11135 for an obj_section_change_hook macro, but that might be confusing
11136 as it would not be appropriate to use it in the section changing
11137 functions in read.c, since obj-elf.c intercepts those. FIXME:
11138 This should be cleaner, somehow. */
11139 obj_elf_section_change_hook ();
11142 mips_emit_delays ();
11152 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11153 demand_empty_rest_of_line ();
11157 seg
= subseg_new (RDATA_SECTION_NAME
,
11158 (subsegT
) get_absolute_expression ());
11159 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11161 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11162 | SEC_READONLY
| SEC_RELOC
11164 if (strcmp (TARGET_OS
, "elf") != 0)
11165 record_alignment (seg
, 4);
11167 demand_empty_rest_of_line ();
11171 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11172 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11174 bfd_set_section_flags (stdoutput
, seg
,
11175 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11176 if (strcmp (TARGET_OS
, "elf") != 0)
11177 record_alignment (seg
, 4);
11179 demand_empty_rest_of_line ();
11187 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11190 char *section_name
;
11195 int section_entry_size
;
11196 int section_alignment
;
11198 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11201 section_name
= input_line_pointer
;
11202 c
= get_symbol_end ();
11204 next_c
= *(input_line_pointer
+ 1);
11206 /* Do we have .section Name<,"flags">? */
11207 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11209 /* just after name is now '\0'. */
11210 *input_line_pointer
= c
;
11211 input_line_pointer
= section_name
;
11212 obj_elf_section (ignore
);
11215 input_line_pointer
++;
11217 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11219 section_type
= get_absolute_expression ();
11222 if (*input_line_pointer
++ == ',')
11223 section_flag
= get_absolute_expression ();
11226 if (*input_line_pointer
++ == ',')
11227 section_entry_size
= get_absolute_expression ();
11229 section_entry_size
= 0;
11230 if (*input_line_pointer
++ == ',')
11231 section_alignment
= get_absolute_expression ();
11233 section_alignment
= 0;
11235 section_name
= xstrdup (section_name
);
11237 /* When using the generic form of .section (as implemented by obj-elf.c),
11238 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11239 traditionally had to fall back on the more common @progbits instead.
11241 There's nothing really harmful in this, since bfd will correct
11242 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11243 means that, for backwards compatibiltiy, the special_section entries
11244 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11246 Even so, we shouldn't force users of the MIPS .section syntax to
11247 incorrectly label the sections as SHT_PROGBITS. The best compromise
11248 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11249 generic type-checking code. */
11250 if (section_type
== SHT_MIPS_DWARF
)
11251 section_type
= SHT_PROGBITS
;
11253 obj_elf_change_section (section_name
, section_type
, section_flag
,
11254 section_entry_size
, 0, 0, 0);
11256 if (now_seg
->name
!= section_name
)
11257 free (section_name
);
11258 #endif /* OBJ_ELF */
11262 mips_enable_auto_align (void)
11268 s_cons (int log_size
)
11272 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11273 mips_emit_delays ();
11274 if (log_size
> 0 && auto_align
)
11275 mips_align (log_size
, 0, label
);
11276 mips_clear_insn_labels ();
11277 cons (1 << log_size
);
11281 s_float_cons (int type
)
11285 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11287 mips_emit_delays ();
11292 mips_align (3, 0, label
);
11294 mips_align (2, 0, label
);
11297 mips_clear_insn_labels ();
11302 /* Handle .globl. We need to override it because on Irix 5 you are
11305 where foo is an undefined symbol, to mean that foo should be
11306 considered to be the address of a function. */
11309 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11316 name
= input_line_pointer
;
11317 c
= get_symbol_end ();
11318 symbolP
= symbol_find_or_make (name
);
11319 *input_line_pointer
= c
;
11320 SKIP_WHITESPACE ();
11322 /* On Irix 5, every global symbol that is not explicitly labelled as
11323 being a function is apparently labelled as being an object. */
11326 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11331 secname
= input_line_pointer
;
11332 c
= get_symbol_end ();
11333 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11335 as_bad (_("%s: no such section"), secname
);
11336 *input_line_pointer
= c
;
11338 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11339 flag
= BSF_FUNCTION
;
11342 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11344 S_SET_EXTERNAL (symbolP
);
11345 demand_empty_rest_of_line ();
11349 s_option (int x ATTRIBUTE_UNUSED
)
11354 opt
= input_line_pointer
;
11355 c
= get_symbol_end ();
11359 /* FIXME: What does this mean? */
11361 else if (strncmp (opt
, "pic", 3) == 0)
11365 i
= atoi (opt
+ 3);
11370 mips_pic
= SVR4_PIC
;
11371 mips_abicalls
= TRUE
;
11374 as_bad (_(".option pic%d not supported"), i
);
11376 if (mips_pic
== SVR4_PIC
)
11378 if (g_switch_seen
&& g_switch_value
!= 0)
11379 as_warn (_("-G may not be used with SVR4 PIC code"));
11380 g_switch_value
= 0;
11381 bfd_set_gp_size (stdoutput
, 0);
11385 as_warn (_("Unrecognized option \"%s\""), opt
);
11387 *input_line_pointer
= c
;
11388 demand_empty_rest_of_line ();
11391 /* This structure is used to hold a stack of .set values. */
11393 struct mips_option_stack
11395 struct mips_option_stack
*next
;
11396 struct mips_set_options options
;
11399 static struct mips_option_stack
*mips_opts_stack
;
11401 /* Handle the .set pseudo-op. */
11404 s_mipsset (int x ATTRIBUTE_UNUSED
)
11406 char *name
= input_line_pointer
, ch
;
11408 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11409 ++input_line_pointer
;
11410 ch
= *input_line_pointer
;
11411 *input_line_pointer
= '\0';
11413 if (strcmp (name
, "reorder") == 0)
11415 if (mips_opts
.noreorder
)
11418 else if (strcmp (name
, "noreorder") == 0)
11420 if (!mips_opts
.noreorder
)
11421 start_noreorder ();
11423 else if (strcmp (name
, "at") == 0)
11425 mips_opts
.noat
= 0;
11427 else if (strcmp (name
, "noat") == 0)
11429 mips_opts
.noat
= 1;
11431 else if (strcmp (name
, "macro") == 0)
11433 mips_opts
.warn_about_macros
= 0;
11435 else if (strcmp (name
, "nomacro") == 0)
11437 if (mips_opts
.noreorder
== 0)
11438 as_bad (_("`noreorder' must be set before `nomacro'"));
11439 mips_opts
.warn_about_macros
= 1;
11441 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11443 mips_opts
.nomove
= 0;
11445 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11447 mips_opts
.nomove
= 1;
11449 else if (strcmp (name
, "bopt") == 0)
11451 mips_opts
.nobopt
= 0;
11453 else if (strcmp (name
, "nobopt") == 0)
11455 mips_opts
.nobopt
= 1;
11457 else if (strcmp (name
, "mips16") == 0
11458 || strcmp (name
, "MIPS-16") == 0)
11459 mips_opts
.mips16
= 1;
11460 else if (strcmp (name
, "nomips16") == 0
11461 || strcmp (name
, "noMIPS-16") == 0)
11462 mips_opts
.mips16
= 0;
11463 else if (strcmp (name
, "mips3d") == 0)
11464 mips_opts
.ase_mips3d
= 1;
11465 else if (strcmp (name
, "nomips3d") == 0)
11466 mips_opts
.ase_mips3d
= 0;
11467 else if (strcmp (name
, "mdmx") == 0)
11468 mips_opts
.ase_mdmx
= 1;
11469 else if (strcmp (name
, "nomdmx") == 0)
11470 mips_opts
.ase_mdmx
= 0;
11471 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11475 /* Permit the user to change the ISA and architecture on the fly.
11476 Needless to say, misuse can cause serious problems. */
11477 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11480 mips_opts
.isa
= file_mips_isa
;
11481 mips_opts
.arch
= file_mips_arch
;
11483 else if (strncmp (name
, "arch=", 5) == 0)
11485 const struct mips_cpu_info
*p
;
11487 p
= mips_parse_cpu("internal use", name
+ 5);
11489 as_bad (_("unknown architecture %s"), name
+ 5);
11492 mips_opts
.arch
= p
->cpu
;
11493 mips_opts
.isa
= p
->isa
;
11496 else if (strncmp (name
, "mips", 4) == 0)
11498 const struct mips_cpu_info
*p
;
11500 p
= mips_parse_cpu("internal use", name
);
11502 as_bad (_("unknown ISA level %s"), name
+ 4);
11505 mips_opts
.arch
= p
->cpu
;
11506 mips_opts
.isa
= p
->isa
;
11510 as_bad (_("unknown ISA or architecture %s"), name
);
11512 switch (mips_opts
.isa
)
11520 mips_opts
.gp32
= 1;
11521 mips_opts
.fp32
= 1;
11528 mips_opts
.gp32
= 0;
11529 mips_opts
.fp32
= 0;
11532 as_bad (_("unknown ISA level %s"), name
+ 4);
11537 mips_opts
.gp32
= file_mips_gp32
;
11538 mips_opts
.fp32
= file_mips_fp32
;
11541 else if (strcmp (name
, "autoextend") == 0)
11542 mips_opts
.noautoextend
= 0;
11543 else if (strcmp (name
, "noautoextend") == 0)
11544 mips_opts
.noautoextend
= 1;
11545 else if (strcmp (name
, "push") == 0)
11547 struct mips_option_stack
*s
;
11549 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11550 s
->next
= mips_opts_stack
;
11551 s
->options
= mips_opts
;
11552 mips_opts_stack
= s
;
11554 else if (strcmp (name
, "pop") == 0)
11556 struct mips_option_stack
*s
;
11558 s
= mips_opts_stack
;
11560 as_bad (_(".set pop with no .set push"));
11563 /* If we're changing the reorder mode we need to handle
11564 delay slots correctly. */
11565 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11566 start_noreorder ();
11567 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11570 mips_opts
= s
->options
;
11571 mips_opts_stack
= s
->next
;
11575 else if (strcmp (name
, "sym32") == 0)
11576 mips_opts
.sym32
= TRUE
;
11577 else if (strcmp (name
, "nosym32") == 0)
11578 mips_opts
.sym32
= FALSE
;
11581 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11583 *input_line_pointer
= ch
;
11584 demand_empty_rest_of_line ();
11587 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11588 .option pic2. It means to generate SVR4 PIC calls. */
11591 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11593 mips_pic
= SVR4_PIC
;
11594 mips_abicalls
= TRUE
;
11596 if (g_switch_seen
&& g_switch_value
!= 0)
11597 as_warn (_("-G may not be used with SVR4 PIC code"));
11598 g_switch_value
= 0;
11600 bfd_set_gp_size (stdoutput
, 0);
11601 demand_empty_rest_of_line ();
11604 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11605 PIC code. It sets the $gp register for the function based on the
11606 function address, which is in the register named in the argument.
11607 This uses a relocation against _gp_disp, which is handled specially
11608 by the linker. The result is:
11609 lui $gp,%hi(_gp_disp)
11610 addiu $gp,$gp,%lo(_gp_disp)
11611 addu $gp,$gp,.cpload argument
11612 The .cpload argument is normally $25 == $t9.
11614 The -mno-shared option changes this to:
11615 lui $gp,%hi(__gnu_local_gp)
11616 addiu $gp,$gp,%lo(__gnu_local_gp)
11617 and the argument is ignored. This saves an instruction, but the
11618 resulting code is not position independent; it uses an absolute
11619 address for __gnu_local_gp. Thus code assembled with -mno-shared
11620 can go into an ordinary executable, but not into a shared library. */
11623 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11629 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11630 .cpload is ignored. */
11631 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11637 /* .cpload should be in a .set noreorder section. */
11638 if (mips_opts
.noreorder
== 0)
11639 as_warn (_(".cpload not in noreorder section"));
11641 reg
= tc_get_register (0);
11643 /* If we need to produce a 64-bit address, we are better off using
11644 the default instruction sequence. */
11645 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11647 ex
.X_op
= O_symbol
;
11648 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11650 ex
.X_op_symbol
= NULL
;
11651 ex
.X_add_number
= 0;
11653 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11654 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11657 macro_build_lui (&ex
, mips_gp_register
);
11658 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11659 mips_gp_register
, BFD_RELOC_LO16
);
11661 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11662 mips_gp_register
, reg
);
11665 demand_empty_rest_of_line ();
11668 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11669 .cpsetup $reg1, offset|$reg2, label
11671 If offset is given, this results in:
11672 sd $gp, offset($sp)
11673 lui $gp, %hi(%neg(%gp_rel(label)))
11674 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11675 daddu $gp, $gp, $reg1
11677 If $reg2 is given, this results in:
11678 daddu $reg2, $gp, $0
11679 lui $gp, %hi(%neg(%gp_rel(label)))
11680 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11681 daddu $gp, $gp, $reg1
11682 $reg1 is normally $25 == $t9.
11684 The -mno-shared option replaces the last three instructions with
11686 addiu $gp,$gp,%lo(_gp)
11690 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11692 expressionS ex_off
;
11693 expressionS ex_sym
;
11696 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11697 We also need NewABI support. */
11698 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11704 reg1
= tc_get_register (0);
11705 SKIP_WHITESPACE ();
11706 if (*input_line_pointer
!= ',')
11708 as_bad (_("missing argument separator ',' for .cpsetup"));
11712 ++input_line_pointer
;
11713 SKIP_WHITESPACE ();
11714 if (*input_line_pointer
== '$')
11716 mips_cpreturn_register
= tc_get_register (0);
11717 mips_cpreturn_offset
= -1;
11721 mips_cpreturn_offset
= get_absolute_expression ();
11722 mips_cpreturn_register
= -1;
11724 SKIP_WHITESPACE ();
11725 if (*input_line_pointer
!= ',')
11727 as_bad (_("missing argument separator ',' for .cpsetup"));
11731 ++input_line_pointer
;
11732 SKIP_WHITESPACE ();
11733 expression (&ex_sym
);
11736 if (mips_cpreturn_register
== -1)
11738 ex_off
.X_op
= O_constant
;
11739 ex_off
.X_add_symbol
= NULL
;
11740 ex_off
.X_op_symbol
= NULL
;
11741 ex_off
.X_add_number
= mips_cpreturn_offset
;
11743 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11744 BFD_RELOC_LO16
, SP
);
11747 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11748 mips_gp_register
, 0);
11750 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11752 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11753 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11756 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11757 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11758 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11760 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11761 mips_gp_register
, reg1
);
11767 ex
.X_op
= O_symbol
;
11768 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11769 ex
.X_op_symbol
= NULL
;
11770 ex
.X_add_number
= 0;
11772 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11773 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11775 macro_build_lui (&ex
, mips_gp_register
);
11776 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11777 mips_gp_register
, BFD_RELOC_LO16
);
11782 demand_empty_rest_of_line ();
11786 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11788 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11789 .cplocal is ignored. */
11790 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11796 mips_gp_register
= tc_get_register (0);
11797 demand_empty_rest_of_line ();
11800 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11801 offset from $sp. The offset is remembered, and after making a PIC
11802 call $gp is restored from that location. */
11805 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11809 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11810 .cprestore is ignored. */
11811 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11817 mips_cprestore_offset
= get_absolute_expression ();
11818 mips_cprestore_valid
= 1;
11820 ex
.X_op
= O_constant
;
11821 ex
.X_add_symbol
= NULL
;
11822 ex
.X_op_symbol
= NULL
;
11823 ex
.X_add_number
= mips_cprestore_offset
;
11826 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11827 SP
, HAVE_64BIT_ADDRESSES
);
11830 demand_empty_rest_of_line ();
11833 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11834 was given in the preceding .cpsetup, it results in:
11835 ld $gp, offset($sp)
11837 If a register $reg2 was given there, it results in:
11838 daddu $gp, $reg2, $0
11841 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11845 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11846 We also need NewABI support. */
11847 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11854 if (mips_cpreturn_register
== -1)
11856 ex
.X_op
= O_constant
;
11857 ex
.X_add_symbol
= NULL
;
11858 ex
.X_op_symbol
= NULL
;
11859 ex
.X_add_number
= mips_cpreturn_offset
;
11861 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11864 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11865 mips_cpreturn_register
, 0);
11868 demand_empty_rest_of_line ();
11871 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11872 code. It sets the offset to use in gp_rel relocations. */
11875 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11877 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11878 We also need NewABI support. */
11879 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11885 mips_gprel_offset
= get_absolute_expression ();
11887 demand_empty_rest_of_line ();
11890 /* Handle the .gpword pseudo-op. This is used when generating PIC
11891 code. It generates a 32 bit GP relative reloc. */
11894 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11900 /* When not generating PIC code, this is treated as .word. */
11901 if (mips_pic
!= SVR4_PIC
)
11907 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11908 mips_emit_delays ();
11910 mips_align (2, 0, label
);
11911 mips_clear_insn_labels ();
11915 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11917 as_bad (_("Unsupported use of .gpword"));
11918 ignore_rest_of_line ();
11922 md_number_to_chars (p
, 0, 4);
11923 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11924 BFD_RELOC_GPREL32
);
11926 demand_empty_rest_of_line ();
11930 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
11936 /* When not generating PIC code, this is treated as .dword. */
11937 if (mips_pic
!= SVR4_PIC
)
11943 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11944 mips_emit_delays ();
11946 mips_align (3, 0, label
);
11947 mips_clear_insn_labels ();
11951 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11953 as_bad (_("Unsupported use of .gpdword"));
11954 ignore_rest_of_line ();
11958 md_number_to_chars (p
, 0, 8);
11959 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11960 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
11962 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
11963 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
11964 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
11966 demand_empty_rest_of_line ();
11969 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11970 tables in SVR4 PIC code. */
11973 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
11977 /* This is ignored when not generating SVR4 PIC code. */
11978 if (mips_pic
!= SVR4_PIC
)
11984 /* Add $gp to the register named as an argument. */
11986 reg
= tc_get_register (0);
11987 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
11990 demand_empty_rest_of_line ();
11993 /* Handle the .insn pseudo-op. This marks instruction labels in
11994 mips16 mode. This permits the linker to handle them specially,
11995 such as generating jalx instructions when needed. We also make
11996 them odd for the duration of the assembly, in order to generate the
11997 right sort of code. We will make them even in the adjust_symtab
11998 routine, while leaving them marked. This is convenient for the
11999 debugger and the disassembler. The linker knows to make them odd
12003 s_insn (int ignore ATTRIBUTE_UNUSED
)
12005 mips16_mark_labels ();
12007 demand_empty_rest_of_line ();
12010 /* Handle a .stabn directive. We need these in order to mark a label
12011 as being a mips16 text label correctly. Sometimes the compiler
12012 will emit a label, followed by a .stabn, and then switch sections.
12013 If the label and .stabn are in mips16 mode, then the label is
12014 really a mips16 text label. */
12017 s_mips_stab (int type
)
12020 mips16_mark_labels ();
12025 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12029 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12036 name
= input_line_pointer
;
12037 c
= get_symbol_end ();
12038 symbolP
= symbol_find_or_make (name
);
12039 S_SET_WEAK (symbolP
);
12040 *input_line_pointer
= c
;
12042 SKIP_WHITESPACE ();
12044 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12046 if (S_IS_DEFINED (symbolP
))
12048 as_bad ("ignoring attempt to redefine symbol %s",
12049 S_GET_NAME (symbolP
));
12050 ignore_rest_of_line ();
12054 if (*input_line_pointer
== ',')
12056 ++input_line_pointer
;
12057 SKIP_WHITESPACE ();
12061 if (exp
.X_op
!= O_symbol
)
12063 as_bad ("bad .weakext directive");
12064 ignore_rest_of_line ();
12067 symbol_set_value_expression (symbolP
, &exp
);
12070 demand_empty_rest_of_line ();
12073 /* Parse a register string into a number. Called from the ECOFF code
12074 to parse .frame. The argument is non-zero if this is the frame
12075 register, so that we can record it in mips_frame_reg. */
12078 tc_get_register (int frame
)
12082 SKIP_WHITESPACE ();
12083 if (*input_line_pointer
++ != '$')
12085 as_warn (_("expected `$'"));
12088 else if (ISDIGIT (*input_line_pointer
))
12090 reg
= get_absolute_expression ();
12091 if (reg
< 0 || reg
>= 32)
12093 as_warn (_("Bad register number"));
12099 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12102 input_line_pointer
+= 2;
12104 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12107 input_line_pointer
+= 2;
12109 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12112 input_line_pointer
+= 2;
12114 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12117 input_line_pointer
+= 2;
12119 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12122 input_line_pointer
+= 2;
12124 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12127 input_line_pointer
+= 3;
12129 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12132 input_line_pointer
+= 3;
12134 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12137 input_line_pointer
+= 4;
12141 as_warn (_("Unrecognized register name"));
12143 while (ISALNUM(*input_line_pointer
))
12144 input_line_pointer
++;
12149 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12150 mips_frame_reg_valid
= 1;
12151 mips_cprestore_valid
= 0;
12157 md_section_align (asection
*seg
, valueT addr
)
12159 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12162 /* We don't need to align ELF sections to the full alignment.
12163 However, Irix 5 may prefer that we align them at least to a 16
12164 byte boundary. We don't bother to align the sections if we are
12165 targeted for an embedded system. */
12166 if (strcmp (TARGET_OS
, "elf") == 0)
12172 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12175 /* Utility routine, called from above as well. If called while the
12176 input file is still being read, it's only an approximation. (For
12177 example, a symbol may later become defined which appeared to be
12178 undefined earlier.) */
12181 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12186 if (g_switch_value
> 0)
12188 const char *symname
;
12191 /* Find out whether this symbol can be referenced off the $gp
12192 register. It can be if it is smaller than the -G size or if
12193 it is in the .sdata or .sbss section. Certain symbols can
12194 not be referenced off the $gp, although it appears as though
12196 symname
= S_GET_NAME (sym
);
12197 if (symname
!= (const char *) NULL
12198 && (strcmp (symname
, "eprol") == 0
12199 || strcmp (symname
, "etext") == 0
12200 || strcmp (symname
, "_gp") == 0
12201 || strcmp (symname
, "edata") == 0
12202 || strcmp (symname
, "_fbss") == 0
12203 || strcmp (symname
, "_fdata") == 0
12204 || strcmp (symname
, "_ftext") == 0
12205 || strcmp (symname
, "end") == 0
12206 || strcmp (symname
, "_gp_disp") == 0))
12208 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12210 #ifndef NO_ECOFF_DEBUGGING
12211 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12212 && (symbol_get_obj (sym
)->ecoff_extern_size
12213 <= g_switch_value
))
12215 /* We must defer this decision until after the whole
12216 file has been read, since there might be a .extern
12217 after the first use of this symbol. */
12218 || (before_relaxing
12219 #ifndef NO_ECOFF_DEBUGGING
12220 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12222 && S_GET_VALUE (sym
) == 0)
12223 || (S_GET_VALUE (sym
) != 0
12224 && S_GET_VALUE (sym
) <= g_switch_value
)))
12228 const char *segname
;
12230 segname
= segment_name (S_GET_SEGMENT (sym
));
12231 assert (strcmp (segname
, ".lit8") != 0
12232 && strcmp (segname
, ".lit4") != 0);
12233 change
= (strcmp (segname
, ".sdata") != 0
12234 && strcmp (segname
, ".sbss") != 0
12235 && strncmp (segname
, ".sdata.", 7) != 0
12236 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12241 /* We are not optimizing for the $gp register. */
12246 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12249 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12252 bfd_boolean linkonce
;
12254 /* Handle the case of a symbol equated to another symbol. */
12255 while (symbol_equated_reloc_p (sym
))
12259 /* It's possible to get a loop here in a badly written
12261 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12267 symsec
= S_GET_SEGMENT (sym
);
12269 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12271 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12273 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12277 /* The GNU toolchain uses an extension for ELF: a section
12278 beginning with the magic string .gnu.linkonce is a linkonce
12280 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12281 sizeof ".gnu.linkonce" - 1) == 0)
12285 /* This must duplicate the test in adjust_reloc_syms. */
12286 return (symsec
!= &bfd_und_section
12287 && symsec
!= &bfd_abs_section
12288 && ! bfd_is_com_section (symsec
)
12291 /* A global or weak symbol is treated as external. */
12292 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12293 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12299 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12300 extended opcode. SEC is the section the frag is in. */
12303 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12306 register const struct mips16_immed_operand
*op
;
12308 int mintiny
, maxtiny
;
12312 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12314 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12317 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12318 op
= mips16_immed_operands
;
12319 while (op
->type
!= type
)
12322 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12327 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12330 maxtiny
= 1 << op
->nbits
;
12335 maxtiny
= (1 << op
->nbits
) - 1;
12340 mintiny
= - (1 << (op
->nbits
- 1));
12341 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12344 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12345 val
= S_GET_VALUE (fragp
->fr_symbol
);
12346 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12352 /* We won't have the section when we are called from
12353 mips_relax_frag. However, we will always have been called
12354 from md_estimate_size_before_relax first. If this is a
12355 branch to a different section, we mark it as such. If SEC is
12356 NULL, and the frag is not marked, then it must be a branch to
12357 the same section. */
12360 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12365 /* Must have been called from md_estimate_size_before_relax. */
12368 fragp
->fr_subtype
=
12369 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12371 /* FIXME: We should support this, and let the linker
12372 catch branches and loads that are out of range. */
12373 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12374 _("unsupported PC relative reference to different section"));
12378 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12379 /* Assume non-extended on the first relaxation pass.
12380 The address we have calculated will be bogus if this is
12381 a forward branch to another frag, as the forward frag
12382 will have fr_address == 0. */
12386 /* In this case, we know for sure that the symbol fragment is in
12387 the same section. If the relax_marker of the symbol fragment
12388 differs from the relax_marker of this fragment, we have not
12389 yet adjusted the symbol fragment fr_address. We want to add
12390 in STRETCH in order to get a better estimate of the address.
12391 This particularly matters because of the shift bits. */
12393 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12397 /* Adjust stretch for any alignment frag. Note that if have
12398 been expanding the earlier code, the symbol may be
12399 defined in what appears to be an earlier frag. FIXME:
12400 This doesn't handle the fr_subtype field, which specifies
12401 a maximum number of bytes to skip when doing an
12403 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12405 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12408 stretch
= - ((- stretch
)
12409 & ~ ((1 << (int) f
->fr_offset
) - 1));
12411 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12420 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12422 /* The base address rules are complicated. The base address of
12423 a branch is the following instruction. The base address of a
12424 PC relative load or add is the instruction itself, but if it
12425 is in a delay slot (in which case it can not be extended) use
12426 the address of the instruction whose delay slot it is in. */
12427 if (type
== 'p' || type
== 'q')
12431 /* If we are currently assuming that this frag should be
12432 extended, then, the current address is two bytes
12434 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12437 /* Ignore the low bit in the target, since it will be set
12438 for a text label. */
12439 if ((val
& 1) != 0)
12442 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12444 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12447 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12449 /* Branch offsets have an implicit 0 in the lowest bit. */
12450 if (type
== 'p' || type
== 'q')
12453 /* If any of the shifted bits are set, we must use an extended
12454 opcode. If the address depends on the size of this
12455 instruction, this can lead to a loop, so we arrange to always
12456 use an extended opcode. We only check this when we are in
12457 the main relaxation loop, when SEC is NULL. */
12458 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12460 fragp
->fr_subtype
=
12461 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12465 /* If we are about to mark a frag as extended because the value
12466 is precisely maxtiny + 1, then there is a chance of an
12467 infinite loop as in the following code:
12472 In this case when the la is extended, foo is 0x3fc bytes
12473 away, so the la can be shrunk, but then foo is 0x400 away, so
12474 the la must be extended. To avoid this loop, we mark the
12475 frag as extended if it was small, and is about to become
12476 extended with a value of maxtiny + 1. */
12477 if (val
== ((maxtiny
+ 1) << op
->shift
)
12478 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12481 fragp
->fr_subtype
=
12482 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12486 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12487 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12489 if ((val
& ((1 << op
->shift
) - 1)) != 0
12490 || val
< (mintiny
<< op
->shift
)
12491 || val
> (maxtiny
<< op
->shift
))
12497 /* Compute the length of a branch sequence, and adjust the
12498 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12499 worst-case length is computed, with UPDATE being used to indicate
12500 whether an unconditional (-1), branch-likely (+1) or regular (0)
12501 branch is to be computed. */
12503 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12505 bfd_boolean toofar
;
12509 && S_IS_DEFINED (fragp
->fr_symbol
)
12510 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12515 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12517 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12521 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12524 /* If the symbol is not defined or it's in a different segment,
12525 assume the user knows what's going on and emit a short
12531 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12533 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12534 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12535 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12541 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12544 if (mips_pic
!= NO_PIC
)
12546 /* Additional space for PIC loading of target address. */
12548 if (mips_opts
.isa
== ISA_MIPS1
)
12549 /* Additional space for $at-stabilizing nop. */
12553 /* If branch is conditional. */
12554 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12561 /* Estimate the size of a frag before relaxing. Unless this is the
12562 mips16, we are not really relaxing here, and the final size is
12563 encoded in the subtype information. For the mips16, we have to
12564 decide whether we are using an extended opcode or not. */
12567 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12571 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12574 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12576 return fragp
->fr_var
;
12579 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12580 /* We don't want to modify the EXTENDED bit here; it might get us
12581 into infinite loops. We change it only in mips_relax_frag(). */
12582 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12584 if (mips_pic
== NO_PIC
)
12585 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12586 else if (mips_pic
== SVR4_PIC
)
12587 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12593 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12594 return -RELAX_FIRST (fragp
->fr_subtype
);
12597 return -RELAX_SECOND (fragp
->fr_subtype
);
12600 /* This is called to see whether a reloc against a defined symbol
12601 should be converted into a reloc against a section. */
12604 mips_fix_adjustable (fixS
*fixp
)
12606 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12607 about the format of the offset in the .o file. */
12608 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12611 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12612 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12615 if (fixp
->fx_addsy
== NULL
)
12618 /* If symbol SYM is in a mergeable section, relocations of the form
12619 SYM + 0 can usually be made section-relative. The mergeable data
12620 is then identified by the section offset rather than by the symbol.
12622 However, if we're generating REL LO16 relocations, the offset is split
12623 between the LO16 and parterning high part relocation. The linker will
12624 need to recalculate the complete offset in order to correctly identify
12627 The linker has traditionally not looked for the parterning high part
12628 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12629 placed anywhere. Rather than break backwards compatibility by changing
12630 this, it seems better not to force the issue, and instead keep the
12631 original symbol. This will work with either linker behavior. */
12632 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12633 && HAVE_IN_PLACE_ADDENDS
12634 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12638 /* Don't adjust relocations against mips16 symbols, so that the linker
12639 can find them if it needs to set up a stub. */
12640 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12641 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12642 && fixp
->fx_subsy
== NULL
)
12649 /* Translate internal representation of relocation info to BFD target
12653 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12655 static arelent
*retval
[4];
12657 bfd_reloc_code_real_type code
;
12659 memset (retval
, 0, sizeof(retval
));
12660 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12661 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12662 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12663 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12665 assert (! fixp
->fx_pcrel
);
12666 reloc
->addend
= fixp
->fx_addnumber
;
12668 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12669 entry to be used in the relocation's section offset. */
12670 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12672 reloc
->address
= reloc
->addend
;
12676 code
= fixp
->fx_r_type
;
12678 /* To support a PC relative reloc, we used a Cygnus extension.
12679 We check for that here to make sure that we don't let such a
12680 reloc escape normally. (FIXME: This was formerly used by
12681 embedded-PIC support, but is now used by branch handling in
12682 general. That probably should be fixed.) */
12683 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12684 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12685 && code
== BFD_RELOC_16_PCREL_S2
)
12686 reloc
->howto
= NULL
;
12688 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12690 if (reloc
->howto
== NULL
)
12692 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12693 _("Can not represent %s relocation in this object file format"),
12694 bfd_get_reloc_code_name (code
));
12701 /* Relax a machine dependent frag. This returns the amount by which
12702 the current size of the frag should change. */
12705 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12707 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12709 offsetT old_var
= fragp
->fr_var
;
12711 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12713 return fragp
->fr_var
- old_var
;
12716 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12719 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12721 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12723 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12728 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12730 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12737 /* Convert a machine dependent frag. */
12740 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12742 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12745 unsigned long insn
;
12749 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12751 if (target_big_endian
)
12752 insn
= bfd_getb32 (buf
);
12754 insn
= bfd_getl32 (buf
);
12756 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12758 /* We generate a fixup instead of applying it right now
12759 because, if there are linker relaxations, we're going to
12760 need the relocations. */
12761 exp
.X_op
= O_symbol
;
12762 exp
.X_add_symbol
= fragp
->fr_symbol
;
12763 exp
.X_add_number
= fragp
->fr_offset
;
12765 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12767 BFD_RELOC_16_PCREL_S2
);
12768 fixp
->fx_file
= fragp
->fr_file
;
12769 fixp
->fx_line
= fragp
->fr_line
;
12771 md_number_to_chars ((char *) buf
, insn
, 4);
12778 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12779 _("relaxed out-of-range branch into a jump"));
12781 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12784 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12786 /* Reverse the branch. */
12787 switch ((insn
>> 28) & 0xf)
12790 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12791 have the condition reversed by tweaking a single
12792 bit, and their opcodes all have 0x4???????. */
12793 assert ((insn
& 0xf1000000) == 0x41000000);
12794 insn
^= 0x00010000;
12798 /* bltz 0x04000000 bgez 0x04010000
12799 bltzal 0x04100000 bgezal 0x04110000 */
12800 assert ((insn
& 0xfc0e0000) == 0x04000000);
12801 insn
^= 0x00010000;
12805 /* beq 0x10000000 bne 0x14000000
12806 blez 0x18000000 bgtz 0x1c000000 */
12807 insn
^= 0x04000000;
12815 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12817 /* Clear the and-link bit. */
12818 assert ((insn
& 0xfc1c0000) == 0x04100000);
12820 /* bltzal 0x04100000 bgezal 0x04110000
12821 bltzall 0x04120000 bgezall 0x04130000 */
12822 insn
&= ~0x00100000;
12825 /* Branch over the branch (if the branch was likely) or the
12826 full jump (not likely case). Compute the offset from the
12827 current instruction to branch to. */
12828 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12832 /* How many bytes in instructions we've already emitted? */
12833 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12834 /* How many bytes in instructions from here to the end? */
12835 i
= fragp
->fr_var
- i
;
12837 /* Convert to instruction count. */
12839 /* Branch counts from the next instruction. */
12842 /* Branch over the jump. */
12843 md_number_to_chars ((char *) buf
, insn
, 4);
12847 md_number_to_chars ((char *) buf
, 0, 4);
12850 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12852 /* beql $0, $0, 2f */
12854 /* Compute the PC offset from the current instruction to
12855 the end of the variable frag. */
12856 /* How many bytes in instructions we've already emitted? */
12857 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12858 /* How many bytes in instructions from here to the end? */
12859 i
= fragp
->fr_var
- i
;
12860 /* Convert to instruction count. */
12862 /* Don't decrement i, because we want to branch over the
12866 md_number_to_chars ((char *) buf
, insn
, 4);
12869 md_number_to_chars ((char *) buf
, 0, 4);
12874 if (mips_pic
== NO_PIC
)
12877 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12878 ? 0x0c000000 : 0x08000000);
12879 exp
.X_op
= O_symbol
;
12880 exp
.X_add_symbol
= fragp
->fr_symbol
;
12881 exp
.X_add_number
= fragp
->fr_offset
;
12883 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12884 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12885 fixp
->fx_file
= fragp
->fr_file
;
12886 fixp
->fx_line
= fragp
->fr_line
;
12888 md_number_to_chars ((char *) buf
, insn
, 4);
12893 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12894 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12895 exp
.X_op
= O_symbol
;
12896 exp
.X_add_symbol
= fragp
->fr_symbol
;
12897 exp
.X_add_number
= fragp
->fr_offset
;
12899 if (fragp
->fr_offset
)
12901 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12902 exp
.X_add_number
= 0;
12905 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12906 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12907 fixp
->fx_file
= fragp
->fr_file
;
12908 fixp
->fx_line
= fragp
->fr_line
;
12910 md_number_to_chars ((char *) buf
, insn
, 4);
12913 if (mips_opts
.isa
== ISA_MIPS1
)
12916 md_number_to_chars ((char *) buf
, 0, 4);
12920 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
12921 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
12923 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12924 4, &exp
, 0, BFD_RELOC_LO16
);
12925 fixp
->fx_file
= fragp
->fr_file
;
12926 fixp
->fx_line
= fragp
->fr_line
;
12928 md_number_to_chars ((char *) buf
, insn
, 4);
12932 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12937 md_number_to_chars ((char *) buf
, insn
, 4);
12942 assert (buf
== (bfd_byte
*)fragp
->fr_literal
12943 + fragp
->fr_fix
+ fragp
->fr_var
);
12945 fragp
->fr_fix
+= fragp
->fr_var
;
12950 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12953 register const struct mips16_immed_operand
*op
;
12954 bfd_boolean small
, ext
;
12957 unsigned long insn
;
12958 bfd_boolean use_extend
;
12959 unsigned short extend
;
12961 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12962 op
= mips16_immed_operands
;
12963 while (op
->type
!= type
)
12966 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12977 resolve_symbol_value (fragp
->fr_symbol
);
12978 val
= S_GET_VALUE (fragp
->fr_symbol
);
12983 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12985 /* The rules for the base address of a PC relative reloc are
12986 complicated; see mips16_extended_frag. */
12987 if (type
== 'p' || type
== 'q')
12992 /* Ignore the low bit in the target, since it will be
12993 set for a text label. */
12994 if ((val
& 1) != 0)
12997 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12999 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13002 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13005 /* Make sure the section winds up with the alignment we have
13008 record_alignment (asec
, op
->shift
);
13012 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13013 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13014 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13015 _("extended instruction in delay slot"));
13017 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13019 if (target_big_endian
)
13020 insn
= bfd_getb16 (buf
);
13022 insn
= bfd_getl16 (buf
);
13024 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13025 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13026 small
, ext
, &insn
, &use_extend
, &extend
);
13030 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13031 fragp
->fr_fix
+= 2;
13035 md_number_to_chars ((char *) buf
, insn
, 2);
13036 fragp
->fr_fix
+= 2;
13044 first
= RELAX_FIRST (fragp
->fr_subtype
);
13045 second
= RELAX_SECOND (fragp
->fr_subtype
);
13046 fixp
= (fixS
*) fragp
->fr_opcode
;
13048 /* Possibly emit a warning if we've chosen the longer option. */
13049 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13050 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13052 const char *msg
= macro_warning (fragp
->fr_subtype
);
13054 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13057 /* Go through all the fixups for the first sequence. Disable them
13058 (by marking them as done) if we're going to use the second
13059 sequence instead. */
13061 && fixp
->fx_frag
== fragp
13062 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13064 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13066 fixp
= fixp
->fx_next
;
13069 /* Go through the fixups for the second sequence. Disable them if
13070 we're going to use the first sequence, otherwise adjust their
13071 addresses to account for the relaxation. */
13072 while (fixp
&& fixp
->fx_frag
== fragp
)
13074 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13075 fixp
->fx_where
-= first
;
13078 fixp
= fixp
->fx_next
;
13081 /* Now modify the frag contents. */
13082 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13086 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13087 memmove (start
, start
+ first
, second
);
13088 fragp
->fr_fix
-= first
;
13091 fragp
->fr_fix
-= second
;
13097 /* This function is called after the relocs have been generated.
13098 We've been storing mips16 text labels as odd. Here we convert them
13099 back to even for the convenience of the debugger. */
13102 mips_frob_file_after_relocs (void)
13105 unsigned int count
, i
;
13107 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13110 syms
= bfd_get_outsymbols (stdoutput
);
13111 count
= bfd_get_symcount (stdoutput
);
13112 for (i
= 0; i
< count
; i
++, syms
++)
13114 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13115 && ((*syms
)->value
& 1) != 0)
13117 (*syms
)->value
&= ~1;
13118 /* If the symbol has an odd size, it was probably computed
13119 incorrectly, so adjust that as well. */
13120 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13121 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13128 /* This function is called whenever a label is defined. It is used
13129 when handling branch delays; if a branch has a label, we assume we
13130 can not move it. */
13133 mips_define_label (symbolS
*sym
)
13135 struct insn_label_list
*l
;
13137 if (free_insn_labels
== NULL
)
13138 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13141 l
= free_insn_labels
;
13142 free_insn_labels
= l
->next
;
13146 l
->next
= insn_labels
;
13150 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13152 /* Some special processing for a MIPS ELF file. */
13155 mips_elf_final_processing (void)
13157 /* Write out the register information. */
13158 if (mips_abi
!= N64_ABI
)
13162 s
.ri_gprmask
= mips_gprmask
;
13163 s
.ri_cprmask
[0] = mips_cprmask
[0];
13164 s
.ri_cprmask
[1] = mips_cprmask
[1];
13165 s
.ri_cprmask
[2] = mips_cprmask
[2];
13166 s
.ri_cprmask
[3] = mips_cprmask
[3];
13167 /* The gp_value field is set by the MIPS ELF backend. */
13169 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13170 ((Elf32_External_RegInfo
*)
13171 mips_regmask_frag
));
13175 Elf64_Internal_RegInfo s
;
13177 s
.ri_gprmask
= mips_gprmask
;
13179 s
.ri_cprmask
[0] = mips_cprmask
[0];
13180 s
.ri_cprmask
[1] = mips_cprmask
[1];
13181 s
.ri_cprmask
[2] = mips_cprmask
[2];
13182 s
.ri_cprmask
[3] = mips_cprmask
[3];
13183 /* The gp_value field is set by the MIPS ELF backend. */
13185 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13186 ((Elf64_External_RegInfo
*)
13187 mips_regmask_frag
));
13190 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13191 sort of BFD interface for this. */
13192 if (mips_any_noreorder
)
13193 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13194 if (mips_pic
!= NO_PIC
)
13196 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13197 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13200 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13202 /* Set MIPS ELF flags for ASEs. */
13203 if (file_ase_mips16
)
13204 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13205 #if 0 /* XXX FIXME */
13206 if (file_ase_mips3d
)
13207 elf_elfheader (stdoutput
)->e_flags
|= ???;
13210 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13212 /* Set the MIPS ELF ABI flags. */
13213 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13214 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13215 else if (mips_abi
== O64_ABI
)
13216 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13217 else if (mips_abi
== EABI_ABI
)
13219 if (!file_mips_gp32
)
13220 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13222 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13224 else if (mips_abi
== N32_ABI
)
13225 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13227 /* Nothing to do for N64_ABI. */
13229 if (mips_32bitmode
)
13230 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13233 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13235 typedef struct proc
{
13237 symbolS
*func_end_sym
;
13238 unsigned long reg_mask
;
13239 unsigned long reg_offset
;
13240 unsigned long fpreg_mask
;
13241 unsigned long fpreg_offset
;
13242 unsigned long frame_offset
;
13243 unsigned long frame_reg
;
13244 unsigned long pc_reg
;
13247 static procS cur_proc
;
13248 static procS
*cur_proc_ptr
;
13249 static int numprocs
;
13251 /* Fill in an rs_align_code fragment. */
13254 mips_handle_align (fragS
*fragp
)
13256 if (fragp
->fr_type
!= rs_align_code
)
13259 if (mips_opts
.mips16
)
13261 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13262 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13267 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13268 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13276 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13280 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13284 md_obj_begin (void)
13291 /* check for premature end, nesting errors, etc */
13293 as_warn (_("missing .end at end of assembly"));
13302 if (*input_line_pointer
== '-')
13304 ++input_line_pointer
;
13307 if (!ISDIGIT (*input_line_pointer
))
13308 as_bad (_("expected simple number"));
13309 if (input_line_pointer
[0] == '0')
13311 if (input_line_pointer
[1] == 'x')
13313 input_line_pointer
+= 2;
13314 while (ISXDIGIT (*input_line_pointer
))
13317 val
|= hex_value (*input_line_pointer
++);
13319 return negative
? -val
: val
;
13323 ++input_line_pointer
;
13324 while (ISDIGIT (*input_line_pointer
))
13327 val
|= *input_line_pointer
++ - '0';
13329 return negative
? -val
: val
;
13332 if (!ISDIGIT (*input_line_pointer
))
13334 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13335 *input_line_pointer
, *input_line_pointer
);
13336 as_warn (_("invalid number"));
13339 while (ISDIGIT (*input_line_pointer
))
13342 val
+= *input_line_pointer
++ - '0';
13344 return negative
? -val
: val
;
13347 /* The .file directive; just like the usual .file directive, but there
13348 is an initial number which is the ECOFF file index. In the non-ECOFF
13349 case .file implies DWARF-2. */
13352 s_mips_file (int x ATTRIBUTE_UNUSED
)
13354 static int first_file_directive
= 0;
13356 if (ECOFF_DEBUGGING
)
13365 filename
= dwarf2_directive_file (0);
13367 /* Versions of GCC up to 3.1 start files with a ".file"
13368 directive even for stabs output. Make sure that this
13369 ".file" is handled. Note that you need a version of GCC
13370 after 3.1 in order to support DWARF-2 on MIPS. */
13371 if (filename
!= NULL
&& ! first_file_directive
)
13373 (void) new_logical_line (filename
, -1);
13374 s_app_file_string (filename
, 0);
13376 first_file_directive
= 1;
13380 /* The .loc directive, implying DWARF-2. */
13383 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13385 if (!ECOFF_DEBUGGING
)
13386 dwarf2_directive_loc (0);
13389 /* The .end directive. */
13392 s_mips_end (int x ATTRIBUTE_UNUSED
)
13396 /* Following functions need their own .frame and .cprestore directives. */
13397 mips_frame_reg_valid
= 0;
13398 mips_cprestore_valid
= 0;
13400 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13403 demand_empty_rest_of_line ();
13408 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13409 as_warn (_(".end not in text section"));
13413 as_warn (_(".end directive without a preceding .ent directive."));
13414 demand_empty_rest_of_line ();
13420 assert (S_GET_NAME (p
));
13421 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13422 as_warn (_(".end symbol does not match .ent symbol."));
13424 if (debug_type
== DEBUG_STABS
)
13425 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13429 as_warn (_(".end directive missing or unknown symbol"));
13432 /* Create an expression to calculate the size of the function. */
13433 if (p
&& cur_proc_ptr
)
13435 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13436 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13439 exp
->X_op
= O_subtract
;
13440 exp
->X_add_symbol
= symbol_temp_new_now ();
13441 exp
->X_op_symbol
= p
;
13442 exp
->X_add_number
= 0;
13444 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13447 /* Generate a .pdr section. */
13448 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13451 segT saved_seg
= now_seg
;
13452 subsegT saved_subseg
= now_subseg
;
13457 dot
= frag_now_fix ();
13459 #ifdef md_flush_pending_output
13460 md_flush_pending_output ();
13464 subseg_set (pdr_seg
, 0);
13466 /* Write the symbol. */
13467 exp
.X_op
= O_symbol
;
13468 exp
.X_add_symbol
= p
;
13469 exp
.X_add_number
= 0;
13470 emit_expr (&exp
, 4);
13472 fragp
= frag_more (7 * 4);
13474 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13475 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13476 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13477 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13478 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13479 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13480 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13482 subseg_set (saved_seg
, saved_subseg
);
13484 #endif /* OBJ_ELF */
13486 cur_proc_ptr
= NULL
;
13489 /* The .aent and .ent directives. */
13492 s_mips_ent (int aent
)
13496 symbolP
= get_symbol ();
13497 if (*input_line_pointer
== ',')
13498 ++input_line_pointer
;
13499 SKIP_WHITESPACE ();
13500 if (ISDIGIT (*input_line_pointer
)
13501 || *input_line_pointer
== '-')
13504 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13505 as_warn (_(".ent or .aent not in text section."));
13507 if (!aent
&& cur_proc_ptr
)
13508 as_warn (_("missing .end"));
13512 /* This function needs its own .frame and .cprestore directives. */
13513 mips_frame_reg_valid
= 0;
13514 mips_cprestore_valid
= 0;
13516 cur_proc_ptr
= &cur_proc
;
13517 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13519 cur_proc_ptr
->func_sym
= symbolP
;
13521 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13525 if (debug_type
== DEBUG_STABS
)
13526 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13527 S_GET_NAME (symbolP
));
13530 demand_empty_rest_of_line ();
13533 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13534 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13535 s_mips_frame is used so that we can set the PDR information correctly.
13536 We can't use the ecoff routines because they make reference to the ecoff
13537 symbol table (in the mdebug section). */
13540 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13543 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13547 if (cur_proc_ptr
== (procS
*) NULL
)
13549 as_warn (_(".frame outside of .ent"));
13550 demand_empty_rest_of_line ();
13554 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13556 SKIP_WHITESPACE ();
13557 if (*input_line_pointer
++ != ','
13558 || get_absolute_expression_and_terminator (&val
) != ',')
13560 as_warn (_("Bad .frame directive"));
13561 --input_line_pointer
;
13562 demand_empty_rest_of_line ();
13566 cur_proc_ptr
->frame_offset
= val
;
13567 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13569 demand_empty_rest_of_line ();
13572 #endif /* OBJ_ELF */
13576 /* The .fmask and .mask directives. If the mdebug section is present
13577 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13578 embedded targets, s_mips_mask is used so that we can set the PDR
13579 information correctly. We can't use the ecoff routines because they
13580 make reference to the ecoff symbol table (in the mdebug section). */
13583 s_mips_mask (int reg_type
)
13586 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13590 if (cur_proc_ptr
== (procS
*) NULL
)
13592 as_warn (_(".mask/.fmask outside of .ent"));
13593 demand_empty_rest_of_line ();
13597 if (get_absolute_expression_and_terminator (&mask
) != ',')
13599 as_warn (_("Bad .mask/.fmask directive"));
13600 --input_line_pointer
;
13601 demand_empty_rest_of_line ();
13605 off
= get_absolute_expression ();
13607 if (reg_type
== 'F')
13609 cur_proc_ptr
->fpreg_mask
= mask
;
13610 cur_proc_ptr
->fpreg_offset
= off
;
13614 cur_proc_ptr
->reg_mask
= mask
;
13615 cur_proc_ptr
->reg_offset
= off
;
13618 demand_empty_rest_of_line ();
13621 #endif /* OBJ_ELF */
13622 s_ignore (reg_type
);
13625 /* A table describing all the processors gas knows about. Names are
13626 matched in the order listed.
13628 To ease comparison, please keep this table in the same order as
13629 gcc's mips_cpu_info_table[]. */
13630 static const struct mips_cpu_info mips_cpu_info_table
[] =
13632 /* Entries for generic ISAs */
13633 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13634 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13635 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13636 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13637 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13638 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13639 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13640 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13641 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13644 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13645 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13646 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13649 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13652 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13653 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13654 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13655 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13656 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13657 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13658 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13659 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13660 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13661 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13662 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13663 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13666 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13667 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13668 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13669 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13670 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13671 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13672 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13673 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13674 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13675 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13676 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13677 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13678 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13681 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13682 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13683 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13686 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13687 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13689 /* Broadcom SB-1 CPU core */
13690 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13697 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13698 with a final "000" replaced by "k". Ignore case.
13700 Note: this function is shared between GCC and GAS. */
13703 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13705 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13706 given
++, canonical
++;
13708 return ((*given
== 0 && *canonical
== 0)
13709 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13713 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13714 CPU name. We've traditionally allowed a lot of variation here.
13716 Note: this function is shared between GCC and GAS. */
13719 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13721 /* First see if the name matches exactly, or with a final "000"
13722 turned into "k". */
13723 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13726 /* If not, try comparing based on numerical designation alone.
13727 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13728 if (TOLOWER (*given
) == 'r')
13730 if (!ISDIGIT (*given
))
13733 /* Skip over some well-known prefixes in the canonical name,
13734 hoping to find a number there too. */
13735 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13737 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13739 else if (TOLOWER (canonical
[0]) == 'r')
13742 return mips_strict_matching_cpu_name_p (canonical
, given
);
13746 /* Parse an option that takes the name of a processor as its argument.
13747 OPTION is the name of the option and CPU_STRING is the argument.
13748 Return the corresponding processor enumeration if the CPU_STRING is
13749 recognized, otherwise report an error and return null.
13751 A similar function exists in GCC. */
13753 static const struct mips_cpu_info
*
13754 mips_parse_cpu (const char *option
, const char *cpu_string
)
13756 const struct mips_cpu_info
*p
;
13758 /* 'from-abi' selects the most compatible architecture for the given
13759 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13760 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13761 version. Look first at the -mgp options, if given, otherwise base
13762 the choice on MIPS_DEFAULT_64BIT.
13764 Treat NO_ABI like the EABIs. One reason to do this is that the
13765 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13766 architecture. This code picks MIPS I for 'mips' and MIPS III for
13767 'mips64', just as we did in the days before 'from-abi'. */
13768 if (strcasecmp (cpu_string
, "from-abi") == 0)
13770 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13771 return mips_cpu_info_from_isa (ISA_MIPS1
);
13773 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13774 return mips_cpu_info_from_isa (ISA_MIPS3
);
13776 if (file_mips_gp32
>= 0)
13777 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13779 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13784 /* 'default' has traditionally been a no-op. Probably not very useful. */
13785 if (strcasecmp (cpu_string
, "default") == 0)
13788 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13789 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13792 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13796 /* Return the canonical processor information for ISA (a member of the
13797 ISA_MIPS* enumeration). */
13799 static const struct mips_cpu_info
*
13800 mips_cpu_info_from_isa (int isa
)
13804 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13805 if (mips_cpu_info_table
[i
].is_isa
13806 && isa
== mips_cpu_info_table
[i
].isa
)
13807 return (&mips_cpu_info_table
[i
]);
13812 static const struct mips_cpu_info
*
13813 mips_cpu_info_from_arch (int arch
)
13817 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13818 if (arch
== mips_cpu_info_table
[i
].cpu
)
13819 return (&mips_cpu_info_table
[i
]);
13825 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13829 fprintf (stream
, "%24s", "");
13834 fprintf (stream
, ", ");
13838 if (*col_p
+ strlen (string
) > 72)
13840 fprintf (stream
, "\n%24s", "");
13844 fprintf (stream
, "%s", string
);
13845 *col_p
+= strlen (string
);
13851 md_show_usage (FILE *stream
)
13856 fprintf (stream
, _("\
13858 -EB generate big endian output\n\
13859 -EL generate little endian output\n\
13860 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13861 -G NUM allow referencing objects up to NUM bytes\n\
13862 implicitly with the gp register [default 8]\n"));
13863 fprintf (stream
, _("\
13864 -mips1 generate MIPS ISA I instructions\n\
13865 -mips2 generate MIPS ISA II instructions\n\
13866 -mips3 generate MIPS ISA III instructions\n\
13867 -mips4 generate MIPS ISA IV instructions\n\
13868 -mips5 generate MIPS ISA V instructions\n\
13869 -mips32 generate MIPS32 ISA instructions\n\
13870 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13871 -mips64 generate MIPS64 ISA instructions\n\
13872 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13873 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13877 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13878 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13879 show (stream
, "from-abi", &column
, &first
);
13880 fputc ('\n', stream
);
13882 fprintf (stream
, _("\
13883 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13884 -no-mCPU don't generate code specific to CPU.\n\
13885 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13889 show (stream
, "3900", &column
, &first
);
13890 show (stream
, "4010", &column
, &first
);
13891 show (stream
, "4100", &column
, &first
);
13892 show (stream
, "4650", &column
, &first
);
13893 fputc ('\n', stream
);
13895 fprintf (stream
, _("\
13896 -mips16 generate mips16 instructions\n\
13897 -no-mips16 do not generate mips16 instructions\n"));
13898 fprintf (stream
, _("\
13899 -mfix-vr4120 work around certain VR4120 errata\n\
13900 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13901 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13902 -mno-shared optimize output for executables\n\
13903 -msym32 assume all symbols have 32-bit values\n\
13904 -O0 remove unneeded NOPs, do not swap branches\n\
13905 -O remove unneeded NOPs and swap branches\n\
13906 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13907 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13908 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13910 fprintf (stream
, _("\
13911 -KPIC, -call_shared generate SVR4 position independent code\n\
13912 -non_shared do not generate position independent code\n\
13913 -xgot assume a 32 bit GOT\n\
13914 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
13915 -mshared, -mno-shared disable/enable .cpload optimization for\n\
13917 -mabi=ABI create ABI conformant object file for:\n"));
13921 show (stream
, "32", &column
, &first
);
13922 show (stream
, "o64", &column
, &first
);
13923 show (stream
, "n32", &column
, &first
);
13924 show (stream
, "64", &column
, &first
);
13925 show (stream
, "eabi", &column
, &first
);
13927 fputc ('\n', stream
);
13929 fprintf (stream
, _("\
13930 -32 create o32 ABI object file (default)\n\
13931 -n32 create n32 ABI object file\n\
13932 -64 create 64 ABI object file\n"));
13937 mips_dwarf2_format (void)
13939 if (mips_abi
== N64_ABI
)
13942 return dwarf2_format_64bit_irix
;
13944 return dwarf2_format_64bit
;
13948 return dwarf2_format_32bit
;
13952 mips_dwarf2_addr_size (void)
13954 if (mips_abi
== N64_ABI
)