1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2019 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float
;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float
;
268 /* 1 if single-precision operations on odd-numbered registers are
272 /* The set of ASEs that should be enabled for the user specified
273 architecture. This cannot be inferred from 'arch' for all cores
274 as processors only have a unique 'arch' if they add architecture
275 specific instructions (UDI). */
279 /* Specifies whether module level options have been checked yet. */
280 static bfd_boolean file_mips_opts_checked
= FALSE
;
282 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
283 value has not been initialized. Changed by `.nan legacy' and
284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
285 options, and the default CPU. */
286 static int mips_nan2008
= -1;
288 /* This is the struct we use to hold the module level set of options.
289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
290 fp fields to -1 to indicate that they have not been initialized. */
292 static struct mips_set_options file_mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
295 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
298 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
302 /* This is similar to file_mips_opts, but for the current set of options. */
304 static struct mips_set_options mips_opts
=
306 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
307 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
310 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
314 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
315 static unsigned int file_ase_explicit
;
317 /* These variables are filled in with the masks of registers used.
318 The object format code reads them and puts them in the appropriate
320 unsigned long mips_gprmask
;
321 unsigned long mips_cprmask
[4];
323 /* True if any MIPS16 code was produced. */
324 static int file_ase_mips16
;
326 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
327 || mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS32R3 \
329 || mips_opts.isa == ISA_MIPS32R5 \
330 || mips_opts.isa == ISA_MIPS64 \
331 || mips_opts.isa == ISA_MIPS64R2 \
332 || mips_opts.isa == ISA_MIPS64R3 \
333 || mips_opts.isa == ISA_MIPS64R5)
335 /* True if any microMIPS code was produced. */
336 static int file_ase_micromips
;
338 /* True if we want to create R_MIPS_JALR for jalr $25. */
340 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
342 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
343 because there's no place for any addend, the only acceptable
344 expression is a bare symbol. */
345 #define MIPS_JALR_HINT_P(EXPR) \
346 (!HAVE_IN_PLACE_ADDENDS \
347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 /* The argument of the -march= flag. The architecture we are assembling. */
351 static const char *mips_arch_string
;
353 /* The argument of the -mtune= flag. The architecture for which we
355 static int mips_tune
= CPU_UNKNOWN
;
356 static const char *mips_tune_string
;
358 /* True when generating 32-bit code for a 64-bit processor. */
359 static int mips_32bitmode
= 0;
361 /* True if the given ABI requires 32-bit registers. */
362 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
364 /* Likewise 64-bit registers. */
365 #define ABI_NEEDS_64BIT_REGS(ABI) \
367 || (ABI) == N64_ABI \
370 #define ISA_IS_R6(ISA) \
371 ((ISA) == ISA_MIPS32R6 \
372 || (ISA) == ISA_MIPS64R6)
374 /* Return true if ISA supports 64 bit wide gp registers. */
375 #define ISA_HAS_64BIT_REGS(ISA) \
376 ((ISA) == ISA_MIPS3 \
377 || (ISA) == ISA_MIPS4 \
378 || (ISA) == ISA_MIPS5 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (ISA) == ISA_MIPS64R6)
385 /* Return true if ISA supports 64 bit wide float registers. */
386 #define ISA_HAS_64BIT_FPRS(ISA) \
387 ((ISA) == ISA_MIPS3 \
388 || (ISA) == ISA_MIPS4 \
389 || (ISA) == ISA_MIPS5 \
390 || (ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS32R6 \
394 || (ISA) == ISA_MIPS64 \
395 || (ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6)
400 /* Return true if ISA supports 64-bit right rotate (dror et al.)
402 #define ISA_HAS_DROR(ISA) \
403 ((ISA) == ISA_MIPS64R2 \
404 || (ISA) == ISA_MIPS64R3 \
405 || (ISA) == ISA_MIPS64R5 \
406 || (ISA) == ISA_MIPS64R6 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS32R6 \
418 || (ISA) == ISA_MIPS64R2 \
419 || (ISA) == ISA_MIPS64R3 \
420 || (ISA) == ISA_MIPS64R5 \
421 || (ISA) == ISA_MIPS64R6 \
422 || (mips_opts.ase & ASE_SMARTMIPS) \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
428 (((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS32R3 \
431 || (ISA) == ISA_MIPS32R5 \
432 || (ISA) == ISA_MIPS32R6 \
433 || (ISA) == ISA_MIPS64 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6 \
438 || (CPU) == CPU_R5900) \
439 && ((CPU) != CPU_GS464 \
440 || (CPU) != CPU_GS464E \
441 || (CPU) != CPU_GS264E))
443 /* Return true if ISA supports move to/from high part of a 64-bit
444 floating-point register. */
445 #define ISA_HAS_MXHC1(ISA) \
446 ((ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS32R3 \
448 || (ISA) == ISA_MIPS32R5 \
449 || (ISA) == ISA_MIPS32R6 \
450 || (ISA) == ISA_MIPS64R2 \
451 || (ISA) == ISA_MIPS64R3 \
452 || (ISA) == ISA_MIPS64R5 \
453 || (ISA) == ISA_MIPS64R6)
455 /* Return true if ISA supports legacy NAN. */
456 #define ISA_HAS_LEGACY_NAN(ISA) \
457 ((ISA) == ISA_MIPS1 \
458 || (ISA) == ISA_MIPS2 \
459 || (ISA) == ISA_MIPS3 \
460 || (ISA) == ISA_MIPS4 \
461 || (ISA) == ISA_MIPS5 \
462 || (ISA) == ISA_MIPS32 \
463 || (ISA) == ISA_MIPS32R2 \
464 || (ISA) == ISA_MIPS32R3 \
465 || (ISA) == ISA_MIPS32R5 \
466 || (ISA) == ISA_MIPS64 \
467 || (ISA) == ISA_MIPS64R2 \
468 || (ISA) == ISA_MIPS64R3 \
469 || (ISA) == ISA_MIPS64R5)
472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
483 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
485 /* True if relocations are stored in-place. */
486 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
488 /* The ABI-derived address size. */
489 #define HAVE_64BIT_ADDRESSES \
490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
491 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
493 /* The size of symbolic constants (i.e., expressions of the form
494 "SYMBOL" or "SYMBOL + OFFSET"). */
495 #define HAVE_32BIT_SYMBOLS \
496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
497 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
499 /* Addresses are loaded in different ways, depending on the address size
500 in use. The n32 ABI Documentation also mandates the use of additions
501 with overflow checking, but existing implementations don't follow it. */
502 #define ADDRESS_ADD_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
505 #define ADDRESS_ADDI_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
508 #define ADDRESS_LOAD_INSN \
509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
511 #define ADDRESS_STORE_INSN \
512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
514 /* Return true if the given CPU supports the MIPS16 ASE. */
515 #define CPU_HAS_MIPS16(cpu) \
516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
519 /* Return true if the given CPU supports the microMIPS ASE. */
520 #define CPU_HAS_MICROMIPS(cpu) 0
522 /* True if CPU has a dror instruction. */
523 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
525 /* True if CPU has a ror instruction. */
526 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
528 /* True if CPU is in the Octeon family. */
529 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
532 /* True if CPU has seq/sne and seqi/snei instructions. */
533 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
535 /* True, if CPU has support for ldc1 and sdc1. */
536 #define CPU_HAS_LDC1_SDC1(CPU) \
537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
539 /* True if mflo and mfhi can be immediately followed by instructions
540 which write to the HI and LO registers.
542 According to MIPS specifications, MIPS ISAs I, II, and III need
543 (at least) two instructions between the reads of HI/LO and
544 instructions which write them, and later ISAs do not. Contradicting
545 the MIPS specifications, some MIPS IV processor user manuals (e.g.
546 the UM for the NEC Vr5000) document needing the instructions between
547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
548 MIPS64 and later ISAs to have the interlocks, plus any specific
549 earlier-ISA CPUs for which CPU documentation declares that the
550 instructions are really interlocked. */
551 #define hilo_interlocks \
552 (mips_opts.isa == ISA_MIPS32 \
553 || mips_opts.isa == ISA_MIPS32R2 \
554 || mips_opts.isa == ISA_MIPS32R3 \
555 || mips_opts.isa == ISA_MIPS32R5 \
556 || mips_opts.isa == ISA_MIPS32R6 \
557 || mips_opts.isa == ISA_MIPS64 \
558 || mips_opts.isa == ISA_MIPS64R2 \
559 || mips_opts.isa == ISA_MIPS64R3 \
560 || mips_opts.isa == ISA_MIPS64R5 \
561 || mips_opts.isa == ISA_MIPS64R6 \
562 || mips_opts.arch == CPU_R4010 \
563 || mips_opts.arch == CPU_R5900 \
564 || mips_opts.arch == CPU_R10000 \
565 || mips_opts.arch == CPU_R12000 \
566 || mips_opts.arch == CPU_R14000 \
567 || mips_opts.arch == CPU_R16000 \
568 || mips_opts.arch == CPU_RM7000 \
569 || mips_opts.arch == CPU_VR5500 \
570 || mips_opts.micromips \
573 /* Whether the processor uses hardware interlocks to protect reads
574 from the GPRs after they are loaded from memory, and thus does not
575 require nops to be inserted. This applies to instructions marked
576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
577 level I and microMIPS mode instructions are always interlocked. */
578 #define gpr_interlocks \
579 (mips_opts.isa != ISA_MIPS1 \
580 || mips_opts.arch == CPU_R3900 \
581 || mips_opts.arch == CPU_R5900 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to avoid delays
586 required by coprocessor instructions, and thus does not require
587 nops to be inserted. This applies to instructions marked
588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
589 instructions marked INSN_WRITE_COND_CODE and ones marked
590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
591 levels I, II, and III and microMIPS mode instructions are always
593 /* Itbl support may require additional care here. */
594 #define cop_interlocks \
595 ((mips_opts.isa != ISA_MIPS1 \
596 && mips_opts.isa != ISA_MIPS2 \
597 && mips_opts.isa != ISA_MIPS3) \
598 || mips_opts.arch == CPU_R4300 \
599 || mips_opts.micromips \
602 /* Whether the processor uses hardware interlocks to protect reads
603 from coprocessor registers after they are loaded from memory, and
604 thus does not require nops to be inserted. This applies to
605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
606 requires at MIPS ISA level I and microMIPS mode instructions are
607 always interlocked. */
608 #define cop_mem_interlocks \
609 (mips_opts.isa != ISA_MIPS1 \
610 || mips_opts.micromips \
613 /* Is this a mfhi or mflo instruction? */
614 #define MF_HILO_INSN(PINFO) \
615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
617 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
618 has been selected. This implies, in particular, that addresses of text
619 labels have their LSB set. */
620 #define HAVE_CODE_COMPRESSION \
621 ((mips_opts.mips16 | mips_opts.micromips) != 0)
623 /* The minimum and maximum signed values that can be stored in a GPR. */
624 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
625 #define GPR_SMIN (-GPR_SMAX - 1)
627 /* MIPS PIC level. */
629 enum mips_pic_level mips_pic
;
631 /* 1 if we should generate 32 bit offsets from the $gp register in
632 SVR4_PIC mode. Currently has no meaning in other modes. */
633 static int mips_big_got
= 0;
635 /* 1 if trap instructions should used for overflow rather than break
637 static int mips_trap
= 0;
639 /* 1 if double width floating point constants should not be constructed
640 by assembling two single width halves into two single width floating
641 point registers which just happen to alias the double width destination
642 register. On some architectures this aliasing can be disabled by a bit
643 in the status register, and the setting of this bit cannot be determined
644 automatically at assemble time. */
645 static int mips_disable_float_construction
;
647 /* Non-zero if any .set noreorder directives were used. */
649 static int mips_any_noreorder
;
651 /* Non-zero if nops should be inserted when the register referenced in
652 an mfhi/mflo instruction is read in the next two instructions. */
653 static int mips_7000_hilo_fix
;
655 /* The size of objects in the small data section. */
656 static unsigned int g_switch_value
= 8;
657 /* Whether the -G option was used. */
658 static int g_switch_seen
= 0;
663 /* If we can determine in advance that GP optimization won't be
664 possible, we can skip the relaxation stuff that tries to produce
665 GP-relative references. This makes delay slot optimization work
668 This function can only provide a guess, but it seems to work for
669 gcc output. It needs to guess right for gcc, otherwise gcc
670 will put what it thinks is a GP-relative instruction in a branch
673 I don't know if a fix is needed for the SVR4_PIC mode. I've only
674 fixed it for the non-PIC mode. KR 95/04/07 */
675 static int nopic_need_relax (symbolS
*, int);
677 /* Handle of the OPCODE hash table. */
678 static struct hash_control
*op_hash
= NULL
;
680 /* The opcode hash table we use for the mips16. */
681 static struct hash_control
*mips16_op_hash
= NULL
;
683 /* The opcode hash table we use for the microMIPS ASE. */
684 static struct hash_control
*micromips_op_hash
= NULL
;
686 /* This array holds the chars that always start a comment. If the
687 pre-processor is disabled, these aren't very useful. */
688 const char comment_chars
[] = "#";
690 /* This array holds the chars that only start a comment at the beginning of
691 a line. If the line seems to have the form '# 123 filename'
692 .line and .file directives will appear in the pre-processed output. */
693 /* Note that input_file.c hand checks for '#' at the beginning of the
694 first line of the input file. This is because the compiler outputs
695 #NO_APP at the beginning of its output. */
696 /* Also note that C style comments are always supported. */
697 const char line_comment_chars
[] = "#";
699 /* This array holds machine specific line separator characters. */
700 const char line_separator_chars
[] = ";";
702 /* Chars that can be used to separate mant from exp in floating point nums. */
703 const char EXP_CHARS
[] = "eE";
705 /* Chars that mean this number is a floating point constant.
708 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
710 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
711 changed in read.c . Ideally it shouldn't have to know about it at all,
712 but nothing is ideal around here. */
714 /* Types of printf format used for instruction-related error messages.
715 "I" means int ("%d") and "S" means string ("%s"). */
716 enum mips_insn_error_format
723 /* Information about an error that was found while assembling the current
725 struct mips_insn_error
727 /* We sometimes need to match an instruction against more than one
728 opcode table entry. Errors found during this matching are reported
729 against a particular syntactic argument rather than against the
730 instruction as a whole. We grade these messages so that errors
731 against argument N have a greater priority than an error against
732 any argument < N, since the former implies that arguments up to N
733 were acceptable and that the opcode entry was therefore a closer match.
734 If several matches report an error against the same argument,
735 we only use that error if it is the same in all cases.
737 min_argnum is the minimum argument number for which an error message
738 should be accepted. It is 0 if MSG is against the instruction as
742 /* The printf()-style message, including its format and arguments. */
743 enum mips_insn_error_format format
;
752 /* The error that should be reported for the current instruction. */
753 static struct mips_insn_error insn_error
;
755 static int auto_align
= 1;
757 /* When outputting SVR4 PIC code, the assembler needs to know the
758 offset in the stack frame from which to restore the $gp register.
759 This is set by the .cprestore pseudo-op, and saved in this
761 static offsetT mips_cprestore_offset
= -1;
763 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
764 more optimizations, it can use a register value instead of a memory-saved
765 offset and even an other register than $gp as global pointer. */
766 static offsetT mips_cpreturn_offset
= -1;
767 static int mips_cpreturn_register
= -1;
768 static int mips_gp_register
= GP
;
769 static int mips_gprel_offset
= 0;
771 /* Whether mips_cprestore_offset has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_cprestore_valid
= 0;
775 /* This is the register which holds the stack frame, as set by the
776 .frame pseudo-op. This is needed to implement .cprestore. */
777 static int mips_frame_reg
= SP
;
779 /* Whether mips_frame_reg has been set in the current function
780 (or whether it has already been warned about, if not). */
781 static int mips_frame_reg_valid
= 0;
783 /* To output NOP instructions correctly, we need to keep information
784 about the previous two instructions. */
786 /* Whether we are optimizing. The default value of 2 means to remove
787 unneeded NOPs and swap branch instructions when possible. A value
788 of 1 means to not swap branches. A value of 0 means to always
790 static int mips_optimize
= 2;
792 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
793 equivalent to seeing no -g option at all. */
794 static int mips_debug
= 0;
796 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
797 #define MAX_VR4130_NOPS 4
799 /* The maximum number of NOPs needed to fill delay slots. */
800 #define MAX_DELAY_NOPS 2
802 /* The maximum number of NOPs needed for any purpose. */
805 /* The maximum range of context length of ll/sc. */
806 #define MAX_LLSC_RANGE 20
808 /* A list of previous instructions, with index 0 being the most recent.
809 We need to look back MAX_NOPS instructions when filling delay slots
810 or working around processor errata. We need to look back one
811 instruction further if we're thinking about using history[0] to
812 fill a branch delay slot. */
813 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
815 /* Arrays of operands for each instruction. */
816 #define MAX_OPERANDS 6
817 struct mips_operand_array
819 const struct mips_operand
*operand
[MAX_OPERANDS
];
821 static struct mips_operand_array
*mips_operands
;
822 static struct mips_operand_array
*mips16_operands
;
823 static struct mips_operand_array
*micromips_operands
;
825 /* Nop instructions used by emit_nop. */
826 static struct mips_cl_insn nop_insn
;
827 static struct mips_cl_insn mips16_nop_insn
;
828 static struct mips_cl_insn micromips_nop16_insn
;
829 static struct mips_cl_insn micromips_nop32_insn
;
831 /* Sync instructions used by insert sync. */
832 static struct mips_cl_insn sync_insn
;
834 /* The appropriate nop for the current mode. */
835 #define NOP_INSN (mips_opts.mips16 \
837 : (mips_opts.micromips \
838 ? (mips_opts.insn32 \
839 ? µmips_nop32_insn \
840 : µmips_nop16_insn) \
843 /* The size of NOP_INSN in bytes. */
844 #define NOP_INSN_SIZE ((mips_opts.mips16 \
845 || (mips_opts.micromips && !mips_opts.insn32)) \
848 /* If this is set, it points to a frag holding nop instructions which
849 were inserted before the start of a noreorder section. If those
850 nops turn out to be unnecessary, the size of the frag can be
852 static fragS
*prev_nop_frag
;
854 /* The number of nop instructions we created in prev_nop_frag. */
855 static int prev_nop_frag_holds
;
857 /* The number of nop instructions that we know we need in
859 static int prev_nop_frag_required
;
861 /* The number of instructions we've seen since prev_nop_frag. */
862 static int prev_nop_frag_since
;
864 /* Relocations against symbols are sometimes done in two parts, with a HI
865 relocation and a LO relocation. Each relocation has only 16 bits of
866 space to store an addend. This means that in order for the linker to
867 handle carries correctly, it must be able to locate both the HI and
868 the LO relocation. This means that the relocations must appear in
869 order in the relocation table.
871 In order to implement this, we keep track of each unmatched HI
872 relocation. We then sort them so that they immediately precede the
873 corresponding LO relocation. */
878 struct mips_hi_fixup
*next
;
881 /* The section this fixup is in. */
885 /* The list of unmatched HI relocs. */
887 static struct mips_hi_fixup
*mips_hi_fixup_list
;
889 /* The frag containing the last explicit relocation operator.
890 Null if explicit relocations have not been used. */
892 static fragS
*prev_reloc_op_frag
;
894 /* Map mips16 register numbers to normal MIPS register numbers. */
896 static const unsigned int mips16_to_32_reg_map
[] =
898 16, 17, 2, 3, 4, 5, 6, 7
901 /* Map microMIPS register numbers to normal MIPS register numbers. */
903 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
905 /* The microMIPS registers with type h. */
906 static const unsigned int micromips_to_32_reg_h_map1
[] =
908 5, 5, 6, 4, 4, 4, 4, 4
910 static const unsigned int micromips_to_32_reg_h_map2
[] =
912 6, 7, 7, 21, 22, 5, 6, 7
915 /* The microMIPS registers with type m. */
916 static const unsigned int micromips_to_32_reg_m_map
[] =
918 0, 17, 2, 3, 16, 18, 19, 20
921 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
923 /* Classifies the kind of instructions we're interested in when
924 implementing -mfix-vr4120. */
925 enum fix_vr4120_class
933 NUM_FIX_VR4120_CLASSES
936 /* ...likewise -mfix-loongson2f-jump. */
937 static bfd_boolean mips_fix_loongson2f_jump
;
939 /* ...likewise -mfix-loongson2f-nop. */
940 static bfd_boolean mips_fix_loongson2f_nop
;
942 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
943 static bfd_boolean mips_fix_loongson2f
;
945 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
946 there must be at least one other instruction between an instruction
947 of type X and an instruction of type Y. */
948 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
950 /* True if -mfix-vr4120 is in force. */
951 static int mips_fix_vr4120
;
953 /* ...likewise -mfix-vr4130. */
954 static int mips_fix_vr4130
;
956 /* ...likewise -mfix-24k. */
957 static int mips_fix_24k
;
959 /* ...likewise -mfix-rm7000 */
960 static int mips_fix_rm7000
;
962 /* ...likewise -mfix-cn63xxp1 */
963 static bfd_boolean mips_fix_cn63xxp1
;
965 /* ...likewise -mfix-r5900 */
966 static bfd_boolean mips_fix_r5900
;
967 static bfd_boolean mips_fix_r5900_explicit
;
969 /* ...likewise -mfix-loongson3-llsc. */
970 static bfd_boolean mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
972 /* We don't relax branches by default, since this causes us to expand
973 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
974 fail to compute the offset before expanding the macro to the most
975 efficient expansion. */
977 static int mips_relax_branch
;
979 /* TRUE if checks are suppressed for invalid branches between ISA modes.
980 Needed for broken assembly produced by some GCC versions and some
981 sloppy code out there, where branches to data labels are present. */
982 static bfd_boolean mips_ignore_branch_isa
;
984 /* The expansion of many macros depends on the type of symbol that
985 they refer to. For example, when generating position-dependent code,
986 a macro that refers to a symbol may have two different expansions,
987 one which uses GP-relative addresses and one which uses absolute
988 addresses. When generating SVR4-style PIC, a macro may have
989 different expansions for local and global symbols.
991 We handle these situations by generating both sequences and putting
992 them in variant frags. In position-dependent code, the first sequence
993 will be the GP-relative one and the second sequence will be the
994 absolute one. In SVR4 PIC, the first sequence will be for global
995 symbols and the second will be for local symbols.
997 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
998 SECOND are the lengths of the two sequences in bytes. These fields
999 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
1000 the subtype has the following flags:
1003 Set if generating PIC code.
1006 Set if it has been decided that we should use the second
1007 sequence instead of the first.
1010 Set in the first variant frag if the macro's second implementation
1011 is longer than its first. This refers to the macro as a whole,
1012 not an individual relaxation.
1015 Set in the first variant frag if the macro appeared in a .set nomacro
1016 block and if one alternative requires a warning but the other does not.
1019 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1022 RELAX_DELAY_SLOT_16BIT
1023 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1026 RELAX_DELAY_SLOT_SIZE_FIRST
1027 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1028 the macro is of the wrong size for the branch delay slot.
1030 RELAX_DELAY_SLOT_SIZE_SECOND
1031 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1032 the macro is of the wrong size for the branch delay slot.
1034 The frag's "opcode" points to the first fixup for relaxable code.
1036 Relaxable macros are generated using a sequence such as:
1038 relax_start (SYMBOL);
1039 ... generate first expansion ...
1041 ... generate second expansion ...
1044 The code and fixups for the unwanted alternative are discarded
1045 by md_convert_frag. */
1046 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1047 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1049 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1050 #define RELAX_SECOND(X) ((X) & 0xff)
1051 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1052 #define RELAX_USE_SECOND 0x20000
1053 #define RELAX_SECOND_LONGER 0x40000
1054 #define RELAX_NOMACRO 0x80000
1055 #define RELAX_DELAY_SLOT 0x100000
1056 #define RELAX_DELAY_SLOT_16BIT 0x200000
1057 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1058 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1060 /* Branch without likely bit. If label is out of range, we turn:
1062 beq reg1, reg2, label
1072 with the following opcode replacements:
1079 bltzal <-> bgezal (with jal label instead of j label)
1081 Even though keeping the delay slot instruction in the delay slot of
1082 the branch would be more efficient, it would be very tricky to do
1083 correctly, because we'd have to introduce a variable frag *after*
1084 the delay slot instruction, and expand that instead. Let's do it
1085 the easy way for now, even if the branch-not-taken case now costs
1086 one additional instruction. Out-of-range branches are not supposed
1087 to be common, anyway.
1089 Branch likely. If label is out of range, we turn:
1091 beql reg1, reg2, label
1092 delay slot (annulled if branch not taken)
1101 delay slot (executed only if branch taken)
1104 It would be possible to generate a shorter sequence by losing the
1105 likely bit, generating something like:
1110 delay slot (executed only if branch taken)
1122 bltzall -> bgezal (with jal label instead of j label)
1123 bgezall -> bltzal (ditto)
1126 but it's not clear that it would actually improve performance. */
1127 #define RELAX_BRANCH_ENCODE(at, pic, \
1128 uncond, likely, link, toofar) \
1129 ((relax_substateT) \
1132 | ((pic) ? 0x20 : 0) \
1133 | ((toofar) ? 0x40 : 0) \
1134 | ((link) ? 0x80 : 0) \
1135 | ((likely) ? 0x100 : 0) \
1136 | ((uncond) ? 0x200 : 0)))
1137 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1138 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1139 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1140 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1141 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1142 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1143 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1145 /* For mips16 code, we use an entirely different form of relaxation.
1146 mips16 supports two versions of most instructions which take
1147 immediate values: a small one which takes some small value, and a
1148 larger one which takes a 16 bit value. Since branches also follow
1149 this pattern, relaxing these values is required.
1151 We can assemble both mips16 and normal MIPS code in a single
1152 object. Therefore, we need to support this type of relaxation at
1153 the same time that we support the relaxation described above. We
1154 use the high bit of the subtype field to distinguish these cases.
1156 The information we store for this type of relaxation is the
1157 argument code found in the opcode file for this relocation, whether
1158 the user explicitly requested a small or extended form, and whether
1159 the relocation is in a jump or jal delay slot. That tells us the
1160 size of the value, and how it should be stored. We also store
1161 whether the fragment is considered to be extended or not. We also
1162 store whether this is known to be a branch to a different section,
1163 whether we have tried to relax this frag yet, and whether we have
1164 ever extended a PC relative fragment because of a shift count. */
1165 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1170 | ((e2) ? 0x100 : 0) \
1171 | ((pic) ? 0x200 : 0) \
1172 | ((sym32) ? 0x400 : 0) \
1173 | ((nomacro) ? 0x800 : 0) \
1174 | ((small) ? 0x1000 : 0) \
1175 | ((ext) ? 0x2000 : 0) \
1176 | ((dslot) ? 0x4000 : 0) \
1177 | ((jal_dslot) ? 0x8000 : 0))
1179 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1180 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1181 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1182 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1183 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1184 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1185 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1186 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1187 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1188 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1190 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1191 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1192 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1193 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1194 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1195 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1196 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1197 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1198 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1200 /* For microMIPS code, we use relaxation similar to one we use for
1201 MIPS16 code. Some instructions that take immediate values support
1202 two encodings: a small one which takes some small value, and a
1203 larger one which takes a 16 bit value. As some branches also follow
1204 this pattern, relaxing these values is required.
1206 We can assemble both microMIPS and normal MIPS code in a single
1207 object. Therefore, we need to support this type of relaxation at
1208 the same time that we support the relaxation described above. We
1209 use one of the high bits of the subtype field to distinguish these
1212 The information we store for this type of relaxation is the argument
1213 code found in the opcode file for this relocation, the register
1214 selected as the assembler temporary, whether in the 32-bit
1215 instruction mode, whether the branch is unconditional, whether it is
1216 compact, whether there is no delay-slot instruction available to fill
1217 in, whether it stores the link address implicitly in $ra, whether
1218 relaxation of out-of-range 32-bit branches to a sequence of
1219 instructions is enabled, and whether the displacement of a branch is
1220 too large to fit as an immediate argument of a 16-bit and a 32-bit
1221 branch, respectively. */
1222 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1223 uncond, compact, link, nods, \
1224 relax32, toofar16, toofar32) \
1227 | (((at) & 0x1f) << 8) \
1228 | ((insn32) ? 0x2000 : 0) \
1229 | ((pic) ? 0x4000 : 0) \
1230 | ((uncond) ? 0x8000 : 0) \
1231 | ((compact) ? 0x10000 : 0) \
1232 | ((link) ? 0x20000 : 0) \
1233 | ((nods) ? 0x40000 : 0) \
1234 | ((relax32) ? 0x80000 : 0) \
1235 | ((toofar16) ? 0x100000 : 0) \
1236 | ((toofar32) ? 0x200000 : 0))
1237 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1238 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1239 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1240 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1241 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1242 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1243 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1244 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1245 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1246 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1248 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1249 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1250 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1251 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1252 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1253 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1255 /* Sign-extend 16-bit value X. */
1256 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1258 /* Is the given value a sign-extended 32-bit value? */
1259 #define IS_SEXT_32BIT_NUM(x) \
1260 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1261 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1263 /* Is the given value a sign-extended 16-bit value? */
1264 #define IS_SEXT_16BIT_NUM(x) \
1265 (((x) &~ (offsetT) 0x7fff) == 0 \
1266 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1268 /* Is the given value a sign-extended 12-bit value? */
1269 #define IS_SEXT_12BIT_NUM(x) \
1270 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1272 /* Is the given value a sign-extended 9-bit value? */
1273 #define IS_SEXT_9BIT_NUM(x) \
1274 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1276 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1277 #define IS_ZEXT_32BIT_NUM(x) \
1278 (((x) &~ (offsetT) 0xffffffff) == 0 \
1279 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1281 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1283 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1284 (((STRUCT) >> (SHIFT)) & (MASK))
1286 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1287 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1289 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1290 : EXTRACT_BITS ((INSN).insn_opcode, \
1291 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1292 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1293 EXTRACT_BITS ((INSN).insn_opcode, \
1294 MIPS16OP_MASK_##FIELD, \
1295 MIPS16OP_SH_##FIELD)
1297 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1298 #define MIPS16_EXTEND (0xf000U << 16)
1300 /* Whether or not we are emitting a branch-likely macro. */
1301 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1303 /* Global variables used when generating relaxable macros. See the
1304 comment above RELAX_ENCODE for more details about how relaxation
1307 /* 0 if we're not emitting a relaxable macro.
1308 1 if we're emitting the first of the two relaxation alternatives.
1309 2 if we're emitting the second alternative. */
1312 /* The first relaxable fixup in the current frag. (In other words,
1313 the first fixup that refers to relaxable code.) */
1316 /* sizes[0] says how many bytes of the first alternative are stored in
1317 the current frag. Likewise sizes[1] for the second alternative. */
1318 unsigned int sizes
[2];
1320 /* The symbol on which the choice of sequence depends. */
1324 /* Global variables used to decide whether a macro needs a warning. */
1326 /* True if the macro is in a branch delay slot. */
1327 bfd_boolean delay_slot_p
;
1329 /* Set to the length in bytes required if the macro is in a delay slot
1330 that requires a specific length of instruction, otherwise zero. */
1331 unsigned int delay_slot_length
;
1333 /* For relaxable macros, sizes[0] is the length of the first alternative
1334 in bytes and sizes[1] is the length of the second alternative.
1335 For non-relaxable macros, both elements give the length of the
1337 unsigned int sizes
[2];
1339 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1340 instruction of the first alternative in bytes and first_insn_sizes[1]
1341 is the length of the first instruction of the second alternative.
1342 For non-relaxable macros, both elements give the length of the first
1343 instruction in bytes.
1345 Set to zero if we haven't yet seen the first instruction. */
1346 unsigned int first_insn_sizes
[2];
1348 /* For relaxable macros, insns[0] is the number of instructions for the
1349 first alternative and insns[1] is the number of instructions for the
1352 For non-relaxable macros, both elements give the number of
1353 instructions for the macro. */
1354 unsigned int insns
[2];
1356 /* The first variant frag for this macro. */
1358 } mips_macro_warning
;
1360 /* Prototypes for static functions. */
1362 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1364 static void append_insn
1365 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1366 bfd_boolean expansionp
);
1367 static void mips_no_prev_insn (void);
1368 static void macro_build (expressionS
*, const char *, const char *, ...);
1369 static void mips16_macro_build
1370 (expressionS
*, const char *, const char *, va_list *);
1371 static void load_register (int, expressionS
*, int);
1372 static void macro_start (void);
1373 static void macro_end (void);
1374 static void macro (struct mips_cl_insn
*ip
, char *str
);
1375 static void mips16_macro (struct mips_cl_insn
* ip
);
1376 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1377 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1378 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1379 static void mips16_immed
1380 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1381 unsigned int, unsigned long *);
1382 static size_t my_getSmallExpression
1383 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1384 static void my_getExpression (expressionS
*, char *);
1385 static void s_align (int);
1386 static void s_change_sec (int);
1387 static void s_change_section (int);
1388 static void s_cons (int);
1389 static void s_float_cons (int);
1390 static void s_mips_globl (int);
1391 static void s_option (int);
1392 static void s_mipsset (int);
1393 static void s_abicalls (int);
1394 static void s_cpload (int);
1395 static void s_cpsetup (int);
1396 static void s_cplocal (int);
1397 static void s_cprestore (int);
1398 static void s_cpreturn (int);
1399 static void s_dtprelword (int);
1400 static void s_dtpreldword (int);
1401 static void s_tprelword (int);
1402 static void s_tpreldword (int);
1403 static void s_gpvalue (int);
1404 static void s_gpword (int);
1405 static void s_gpdword (int);
1406 static void s_ehword (int);
1407 static void s_cpadd (int);
1408 static void s_insn (int);
1409 static void s_nan (int);
1410 static void s_module (int);
1411 static void s_mips_ent (int);
1412 static void s_mips_end (int);
1413 static void s_mips_frame (int);
1414 static void s_mips_mask (int reg_type
);
1415 static void s_mips_stab (int);
1416 static void s_mips_weakext (int);
1417 static void s_mips_file (int);
1418 static void s_mips_loc (int);
1419 static bfd_boolean
pic_need_relax (symbolS
*);
1420 static int relaxed_branch_length (fragS
*, asection
*, int);
1421 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1422 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1423 static void file_mips_check_options (void);
1425 /* Table and functions used to map between CPU/ISA names, and
1426 ISA levels, and CPU numbers. */
1428 struct mips_cpu_info
1430 const char *name
; /* CPU or ISA name. */
1431 int flags
; /* MIPS_CPU_* flags. */
1432 int ase
; /* Set of ASEs implemented by the CPU. */
1433 int isa
; /* ISA level. */
1434 int cpu
; /* CPU number (default CPU if ISA). */
1437 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1439 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1440 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1441 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1443 /* Command-line options. */
1444 const char *md_shortopts
= "O::g::G:";
1448 OPTION_MARCH
= OPTION_MD_BASE
,
1480 OPTION_NO_SMARTMIPS
,
1490 OPTION_NO_MICROMIPS
,
1505 OPTION_M7000_HILO_FIX
,
1506 OPTION_MNO_7000_HILO_FIX
,
1510 OPTION_NO_FIX_RM7000
,
1511 OPTION_FIX_LOONGSON3_LLSC
,
1512 OPTION_NO_FIX_LOONGSON3_LLSC
,
1513 OPTION_FIX_LOONGSON2F_JUMP
,
1514 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1515 OPTION_FIX_LOONGSON2F_NOP
,
1516 OPTION_NO_FIX_LOONGSON2F_NOP
,
1518 OPTION_NO_FIX_VR4120
,
1520 OPTION_NO_FIX_VR4130
,
1521 OPTION_FIX_CN63XXP1
,
1522 OPTION_NO_FIX_CN63XXP1
,
1524 OPTION_NO_FIX_R5900
,
1531 OPTION_CONSTRUCT_FLOATS
,
1532 OPTION_NO_CONSTRUCT_FLOATS
,
1536 OPTION_RELAX_BRANCH
,
1537 OPTION_NO_RELAX_BRANCH
,
1538 OPTION_IGNORE_BRANCH_ISA
,
1539 OPTION_NO_IGNORE_BRANCH_ISA
,
1548 OPTION_SINGLE_FLOAT
,
1549 OPTION_DOUBLE_FLOAT
,
1562 OPTION_MVXWORKS_PIC
,
1565 OPTION_NO_ODD_SPREG
,
1568 OPTION_LOONGSON_MMI
,
1569 OPTION_NO_LOONGSON_MMI
,
1570 OPTION_LOONGSON_CAM
,
1571 OPTION_NO_LOONGSON_CAM
,
1572 OPTION_LOONGSON_EXT
,
1573 OPTION_NO_LOONGSON_EXT
,
1574 OPTION_LOONGSON_EXT2
,
1575 OPTION_NO_LOONGSON_EXT2
,
1579 struct option md_longopts
[] =
1581 /* Options which specify architecture. */
1582 {"march", required_argument
, NULL
, OPTION_MARCH
},
1583 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1584 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1585 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1586 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1587 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1588 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1589 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1590 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1591 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1592 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1593 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1594 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1595 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1596 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1597 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1598 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1599 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1601 /* Options which specify Application Specific Extensions (ASEs). */
1602 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1603 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1604 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1605 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1606 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1607 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1608 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1609 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1610 {"mmt", no_argument
, NULL
, OPTION_MT
},
1611 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1612 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1613 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1614 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1615 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1616 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1617 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1618 {"meva", no_argument
, NULL
, OPTION_EVA
},
1619 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1620 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1621 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1622 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1623 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1624 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1625 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1626 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1627 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1628 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1629 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1630 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1631 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1632 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1633 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1634 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1635 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1636 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1637 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1638 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1639 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1640 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1641 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1642 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1643 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1645 /* Old-style architecture options. Don't add more of these. */
1646 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1647 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1648 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1649 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1650 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1651 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1652 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1653 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1655 /* Options which enable bug fixes. */
1656 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1657 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1658 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1659 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1660 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1661 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1662 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1663 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1664 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1665 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1666 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1667 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1668 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1669 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1670 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1671 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1672 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1673 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1674 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1675 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1676 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1678 /* Miscellaneous options. */
1679 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1680 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1681 {"break", no_argument
, NULL
, OPTION_BREAK
},
1682 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1683 {"EB", no_argument
, NULL
, OPTION_EB
},
1684 {"EL", no_argument
, NULL
, OPTION_EL
},
1685 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1686 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1687 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1688 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1689 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1690 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1691 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1692 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1693 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1694 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1695 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1696 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1697 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1698 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1699 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1700 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1701 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1702 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1703 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1704 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1705 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1706 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1707 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1709 /* Strictly speaking this next option is ELF specific,
1710 but we allow it for other ports as well in order to
1711 make testing easier. */
1712 {"32", no_argument
, NULL
, OPTION_32
},
1714 /* ELF-specific options. */
1715 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1716 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1717 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1718 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1719 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1720 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1721 {"n32", no_argument
, NULL
, OPTION_N32
},
1722 {"64", no_argument
, NULL
, OPTION_64
},
1723 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1724 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1725 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1726 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1727 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1728 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1730 {NULL
, no_argument
, NULL
, 0}
1732 size_t md_longopts_size
= sizeof (md_longopts
);
1734 /* Information about either an Application Specific Extension or an
1735 optional architecture feature that, for simplicity, we treat in the
1736 same way as an ASE. */
1739 /* The name of the ASE, used in both the command-line and .set options. */
1742 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1743 and 64-bit architectures, the flags here refer to the subset that
1744 is available on both. */
1747 /* The ASE_* flag used for instructions that are available on 64-bit
1748 architectures but that are not included in FLAGS. */
1749 unsigned int flags64
;
1751 /* The command-line options that turn the ASE on and off. */
1755 /* The minimum required architecture revisions for MIPS32, MIPS64,
1756 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1759 int micromips32_rev
;
1760 int micromips64_rev
;
1762 /* The architecture where the ASE was removed or -1 if the extension has not
1767 /* A table of all supported ASEs. */
1768 static const struct mips_ase mips_ases
[] = {
1769 { "dsp", ASE_DSP
, ASE_DSP64
,
1770 OPTION_DSP
, OPTION_NO_DSP
,
1774 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1775 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1779 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1780 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1784 { "eva", ASE_EVA
, 0,
1785 OPTION_EVA
, OPTION_NO_EVA
,
1789 { "mcu", ASE_MCU
, 0,
1790 OPTION_MCU
, OPTION_NO_MCU
,
1794 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1795 { "mdmx", ASE_MDMX
, 0,
1796 OPTION_MDMX
, OPTION_NO_MDMX
,
1800 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1801 { "mips3d", ASE_MIPS3D
, 0,
1802 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1807 OPTION_MT
, OPTION_NO_MT
,
1811 { "smartmips", ASE_SMARTMIPS
, 0,
1812 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1816 { "virt", ASE_VIRT
, ASE_VIRT64
,
1817 OPTION_VIRT
, OPTION_NO_VIRT
,
1821 { "msa", ASE_MSA
, ASE_MSA64
,
1822 OPTION_MSA
, OPTION_NO_MSA
,
1826 { "xpa", ASE_XPA
, 0,
1827 OPTION_XPA
, OPTION_NO_XPA
,
1831 { "mips16e2", ASE_MIPS16E2
, 0,
1832 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1836 { "crc", ASE_CRC
, ASE_CRC64
,
1837 OPTION_CRC
, OPTION_NO_CRC
,
1841 { "ginv", ASE_GINV
, 0,
1842 OPTION_GINV
, OPTION_NO_GINV
,
1846 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1847 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1851 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1852 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1856 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1857 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1861 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1862 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1867 /* The set of ASEs that require -mfp64. */
1868 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1870 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1871 static const unsigned int mips_ase_groups
[] = {
1872 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1873 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1878 The following pseudo-ops from the Kane and Heinrich MIPS book
1879 should be defined here, but are currently unsupported: .alias,
1880 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1882 The following pseudo-ops from the Kane and Heinrich MIPS book are
1883 specific to the type of debugging information being generated, and
1884 should be defined by the object format: .aent, .begin, .bend,
1885 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1888 The following pseudo-ops from the Kane and Heinrich MIPS book are
1889 not MIPS CPU specific, but are also not specific to the object file
1890 format. This file is probably the best place to define them, but
1891 they are not currently supported: .asm0, .endr, .lab, .struct. */
1893 static const pseudo_typeS mips_pseudo_table
[] =
1895 /* MIPS specific pseudo-ops. */
1896 {"option", s_option
, 0},
1897 {"set", s_mipsset
, 0},
1898 {"rdata", s_change_sec
, 'r'},
1899 {"sdata", s_change_sec
, 's'},
1900 {"livereg", s_ignore
, 0},
1901 {"abicalls", s_abicalls
, 0},
1902 {"cpload", s_cpload
, 0},
1903 {"cpsetup", s_cpsetup
, 0},
1904 {"cplocal", s_cplocal
, 0},
1905 {"cprestore", s_cprestore
, 0},
1906 {"cpreturn", s_cpreturn
, 0},
1907 {"dtprelword", s_dtprelword
, 0},
1908 {"dtpreldword", s_dtpreldword
, 0},
1909 {"tprelword", s_tprelword
, 0},
1910 {"tpreldword", s_tpreldword
, 0},
1911 {"gpvalue", s_gpvalue
, 0},
1912 {"gpword", s_gpword
, 0},
1913 {"gpdword", s_gpdword
, 0},
1914 {"ehword", s_ehword
, 0},
1915 {"cpadd", s_cpadd
, 0},
1916 {"insn", s_insn
, 0},
1918 {"module", s_module
, 0},
1920 /* Relatively generic pseudo-ops that happen to be used on MIPS
1922 {"asciiz", stringer
, 8 + 1},
1923 {"bss", s_change_sec
, 'b'},
1925 {"half", s_cons
, 1},
1926 {"dword", s_cons
, 3},
1927 {"weakext", s_mips_weakext
, 0},
1928 {"origin", s_org
, 0},
1929 {"repeat", s_rept
, 0},
1931 /* For MIPS this is non-standard, but we define it for consistency. */
1932 {"sbss", s_change_sec
, 'B'},
1934 /* These pseudo-ops are defined in read.c, but must be overridden
1935 here for one reason or another. */
1936 {"align", s_align
, 0},
1937 {"byte", s_cons
, 0},
1938 {"data", s_change_sec
, 'd'},
1939 {"double", s_float_cons
, 'd'},
1940 {"float", s_float_cons
, 'f'},
1941 {"globl", s_mips_globl
, 0},
1942 {"global", s_mips_globl
, 0},
1943 {"hword", s_cons
, 1},
1945 {"long", s_cons
, 2},
1946 {"octa", s_cons
, 4},
1947 {"quad", s_cons
, 3},
1948 {"section", s_change_section
, 0},
1949 {"short", s_cons
, 1},
1950 {"single", s_float_cons
, 'f'},
1951 {"stabd", s_mips_stab
, 'd'},
1952 {"stabn", s_mips_stab
, 'n'},
1953 {"stabs", s_mips_stab
, 's'},
1954 {"text", s_change_sec
, 't'},
1955 {"word", s_cons
, 2},
1957 { "extern", ecoff_directive_extern
, 0},
1962 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1964 /* These pseudo-ops should be defined by the object file format.
1965 However, a.out doesn't support them, so we have versions here. */
1966 {"aent", s_mips_ent
, 1},
1967 {"bgnb", s_ignore
, 0},
1968 {"end", s_mips_end
, 0},
1969 {"endb", s_ignore
, 0},
1970 {"ent", s_mips_ent
, 0},
1971 {"file", s_mips_file
, 0},
1972 {"fmask", s_mips_mask
, 'F'},
1973 {"frame", s_mips_frame
, 0},
1974 {"loc", s_mips_loc
, 0},
1975 {"mask", s_mips_mask
, 'R'},
1976 {"verstamp", s_ignore
, 0},
1980 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1981 purpose of the `.dc.a' internal pseudo-op. */
1984 mips_address_bytes (void)
1986 file_mips_check_options ();
1987 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1990 extern void pop_insert (const pseudo_typeS
*);
1993 mips_pop_insert (void)
1995 pop_insert (mips_pseudo_table
);
1996 if (! ECOFF_DEBUGGING
)
1997 pop_insert (mips_nonecoff_pseudo_table
);
2000 /* Symbols labelling the current insn. */
2002 struct insn_label_list
2004 struct insn_label_list
*next
;
2008 static struct insn_label_list
*free_insn_labels
;
2009 #define label_list tc_segment_info_data.labels
2011 static void mips_clear_insn_labels (void);
2012 static void mips_mark_labels (void);
2013 static void mips_compressed_mark_labels (void);
2016 mips_clear_insn_labels (void)
2018 struct insn_label_list
**pl
;
2019 segment_info_type
*si
;
2023 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2026 si
= seg_info (now_seg
);
2027 *pl
= si
->label_list
;
2028 si
->label_list
= NULL
;
2032 /* Mark instruction labels in MIPS16/microMIPS mode. */
2035 mips_mark_labels (void)
2037 if (HAVE_CODE_COMPRESSION
)
2038 mips_compressed_mark_labels ();
2041 static char *expr_end
;
2043 /* An expression in a macro instruction. This is set by mips_ip and
2044 mips16_ip and when populated is always an O_constant. */
2046 static expressionS imm_expr
;
2048 /* The relocatable field in an instruction and the relocs associated
2049 with it. These variables are used for instructions like LUI and
2050 JAL as well as true offsets. They are also used for address
2051 operands in macros. */
2053 static expressionS offset_expr
;
2054 static bfd_reloc_code_real_type offset_reloc
[3]
2055 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2057 /* This is set to the resulting size of the instruction to be produced
2058 by mips16_ip if an explicit extension is used or by mips_ip if an
2059 explicit size is supplied. */
2061 static unsigned int forced_insn_length
;
2063 /* True if we are assembling an instruction. All dot symbols defined during
2064 this time should be treated as code labels. */
2066 static bfd_boolean mips_assembling_insn
;
2068 /* The pdr segment for per procedure frame/regmask info. Not used for
2071 static segT pdr_seg
;
2073 /* The default target format to use. */
2075 #if defined (TE_FreeBSD)
2076 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2077 #elif defined (TE_TMIPS)
2078 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2080 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2084 mips_target_format (void)
2086 switch (OUTPUT_FLAVOR
)
2088 case bfd_target_elf_flavour
:
2090 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2091 return (target_big_endian
2092 ? "elf32-bigmips-vxworks"
2093 : "elf32-littlemips-vxworks");
2095 return (target_big_endian
2096 ? (HAVE_64BIT_OBJECTS
2097 ? ELF_TARGET ("elf64-", "big")
2099 ? ELF_TARGET ("elf32-n", "big")
2100 : ELF_TARGET ("elf32-", "big")))
2101 : (HAVE_64BIT_OBJECTS
2102 ? ELF_TARGET ("elf64-", "little")
2104 ? ELF_TARGET ("elf32-n", "little")
2105 : ELF_TARGET ("elf32-", "little"))));
2112 /* Return the ISA revision that is currently in use, or 0 if we are
2113 generating code for MIPS V or below. */
2118 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2121 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2124 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2127 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2130 /* microMIPS implies revision 2 or above. */
2131 if (mips_opts
.micromips
)
2134 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2140 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2143 mips_ase_mask (unsigned int flags
)
2147 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2148 if (flags
& mips_ase_groups
[i
])
2149 flags
|= mips_ase_groups
[i
];
2153 /* Check whether the current ISA supports ASE. Issue a warning if
2157 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2161 static unsigned int warned_isa
;
2162 static unsigned int warned_fp32
;
2164 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2165 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2167 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2168 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2169 && (warned_isa
& ase
->flags
) != ase
->flags
)
2171 warned_isa
|= ase
->flags
;
2172 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2173 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2175 as_warn (_("the %d-bit %s architecture does not support the"
2176 " `%s' extension"), size
, base
, ase
->name
);
2178 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2179 ase
->name
, base
, size
, min_rev
);
2181 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2182 && (warned_isa
& ase
->flags
) != ase
->flags
)
2184 warned_isa
|= ase
->flags
;
2185 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2186 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2187 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2188 ase
->name
, base
, size
, ase
->rem_rev
);
2191 if ((ase
->flags
& FP64_ASES
)
2192 && mips_opts
.fp
!= 64
2193 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2195 warned_fp32
|= ase
->flags
;
2196 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2200 /* Check all enabled ASEs to see whether they are supported by the
2201 chosen architecture. */
2204 mips_check_isa_supports_ases (void)
2206 unsigned int i
, mask
;
2208 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2210 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2211 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2212 mips_check_isa_supports_ase (&mips_ases
[i
]);
2216 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2217 that were affected. */
2220 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2221 bfd_boolean enabled_p
)
2225 mask
= mips_ase_mask (ase
->flags
);
2228 /* Clear combination ASE flags, which need to be recalculated based on
2229 updated regular ASE settings. */
2230 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
);
2233 opts
->ase
|= ase
->flags
;
2235 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2236 instructions which are only valid when both ASEs are enabled.
2237 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2238 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2240 opts
->ase
|= ASE_XPA_VIRT
;
2241 mask
|= ASE_XPA_VIRT
;
2243 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2245 opts
->ase
|= ASE_MIPS16E2_MT
;
2246 mask
|= ASE_MIPS16E2_MT
;
2252 /* Return the ASE called NAME, or null if none. */
2254 static const struct mips_ase
*
2255 mips_lookup_ase (const char *name
)
2259 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2260 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2261 return &mips_ases
[i
];
2265 /* Return the length of a microMIPS instruction in bytes. If bits of
2266 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2267 otherwise it is a 32-bit instruction. */
2269 static inline unsigned int
2270 micromips_insn_length (const struct mips_opcode
*mo
)
2272 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2275 /* Return the length of MIPS16 instruction OPCODE. */
2277 static inline unsigned int
2278 mips16_opcode_length (unsigned long opcode
)
2280 return (opcode
>> 16) == 0 ? 2 : 4;
2283 /* Return the length of instruction INSN. */
2285 static inline unsigned int
2286 insn_length (const struct mips_cl_insn
*insn
)
2288 if (mips_opts
.micromips
)
2289 return micromips_insn_length (insn
->insn_mo
);
2290 else if (mips_opts
.mips16
)
2291 return mips16_opcode_length (insn
->insn_opcode
);
2296 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2299 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2304 insn
->insn_opcode
= mo
->match
;
2307 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2308 insn
->fixp
[i
] = NULL
;
2309 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2310 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2311 insn
->mips16_absolute_jump_p
= 0;
2312 insn
->complete_p
= 0;
2313 insn
->cleared_p
= 0;
2316 /* Get a list of all the operands in INSN. */
2318 static const struct mips_operand_array
*
2319 insn_operands (const struct mips_cl_insn
*insn
)
2321 if (insn
->insn_mo
>= &mips_opcodes
[0]
2322 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2323 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2325 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2326 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2327 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2329 if (insn
->insn_mo
>= µmips_opcodes
[0]
2330 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2331 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2336 /* Get a description of operand OPNO of INSN. */
2338 static const struct mips_operand
*
2339 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2341 const struct mips_operand_array
*operands
;
2343 operands
= insn_operands (insn
);
2344 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2346 return operands
->operand
[opno
];
2349 /* Install UVAL as the value of OPERAND in INSN. */
2352 insn_insert_operand (struct mips_cl_insn
*insn
,
2353 const struct mips_operand
*operand
, unsigned int uval
)
2355 if (mips_opts
.mips16
2356 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2357 && mips_opcode_32bit_p (insn
->insn_mo
))
2358 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2360 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2363 /* Extract the value of OPERAND from INSN. */
2365 static inline unsigned
2366 insn_extract_operand (const struct mips_cl_insn
*insn
,
2367 const struct mips_operand
*operand
)
2369 return mips_extract_operand (operand
, insn
->insn_opcode
);
2372 /* Record the current MIPS16/microMIPS mode in now_seg. */
2375 mips_record_compressed_mode (void)
2377 segment_info_type
*si
;
2379 si
= seg_info (now_seg
);
2380 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2381 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2382 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2383 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2386 /* Read a standard MIPS instruction from BUF. */
2388 static unsigned long
2389 read_insn (char *buf
)
2391 if (target_big_endian
)
2392 return bfd_getb32 ((bfd_byte
*) buf
);
2394 return bfd_getl32 ((bfd_byte
*) buf
);
2397 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2401 write_insn (char *buf
, unsigned int insn
)
2403 md_number_to_chars (buf
, insn
, 4);
2407 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2408 has length LENGTH. */
2410 static unsigned long
2411 read_compressed_insn (char *buf
, unsigned int length
)
2417 for (i
= 0; i
< length
; i
+= 2)
2420 if (target_big_endian
)
2421 insn
|= bfd_getb16 ((char *) buf
);
2423 insn
|= bfd_getl16 ((char *) buf
);
2429 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2430 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2433 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2437 for (i
= 0; i
< length
; i
+= 2)
2438 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2439 return buf
+ length
;
2442 /* Install INSN at the location specified by its "frag" and "where" fields. */
2445 install_insn (const struct mips_cl_insn
*insn
)
2447 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2448 if (HAVE_CODE_COMPRESSION
)
2449 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2451 write_insn (f
, insn
->insn_opcode
);
2452 mips_record_compressed_mode ();
2455 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2456 and install the opcode in the new location. */
2459 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2464 insn
->where
= where
;
2465 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2466 if (insn
->fixp
[i
] != NULL
)
2468 insn
->fixp
[i
]->fx_frag
= frag
;
2469 insn
->fixp
[i
]->fx_where
= where
;
2471 install_insn (insn
);
2474 /* Add INSN to the end of the output. */
2477 add_fixed_insn (struct mips_cl_insn
*insn
)
2479 char *f
= frag_more (insn_length (insn
));
2480 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2483 /* Start a variant frag and move INSN to the start of the variant part,
2484 marking it as fixed. The other arguments are as for frag_var. */
2487 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2488 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2490 frag_grow (max_chars
);
2491 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2493 frag_var (rs_machine_dependent
, max_chars
, var
,
2494 subtype
, symbol
, offset
, NULL
);
2497 /* Insert N copies of INSN into the history buffer, starting at
2498 position FIRST. Neither FIRST nor N need to be clipped. */
2501 insert_into_history (unsigned int first
, unsigned int n
,
2502 const struct mips_cl_insn
*insn
)
2504 if (mips_relax
.sequence
!= 2)
2508 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2510 history
[i
] = history
[i
- n
];
2516 /* Clear the error in insn_error. */
2519 clear_insn_error (void)
2521 memset (&insn_error
, 0, sizeof (insn_error
));
2524 /* Possibly record error message MSG for the current instruction.
2525 If the error is about a particular argument, ARGNUM is the 1-based
2526 number of that argument, otherwise it is 0. FORMAT is the format
2527 of MSG. Return true if MSG was used, false if the current message
2531 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2536 /* Give priority to errors against specific arguments, and to
2537 the first whole-instruction message. */
2543 /* Keep insn_error if it is against a later argument. */
2544 if (argnum
< insn_error
.min_argnum
)
2547 /* If both errors are against the same argument but are different,
2548 give up on reporting a specific error for this argument.
2549 See the comment about mips_insn_error for details. */
2550 if (argnum
== insn_error
.min_argnum
2552 && strcmp (insn_error
.msg
, msg
) != 0)
2555 insn_error
.min_argnum
+= 1;
2559 insn_error
.min_argnum
= argnum
;
2560 insn_error
.format
= format
;
2561 insn_error
.msg
= msg
;
2565 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2566 as for set_insn_error_format. */
2569 set_insn_error (int argnum
, const char *msg
)
2571 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2574 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2575 as for set_insn_error_format. */
2578 set_insn_error_i (int argnum
, const char *msg
, int i
)
2580 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2584 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2585 are as for set_insn_error_format. */
2588 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2590 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2592 insn_error
.u
.ss
[0] = s1
;
2593 insn_error
.u
.ss
[1] = s2
;
2597 /* Report the error in insn_error, which is against assembly code STR. */
2600 report_insn_error (const char *str
)
2602 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2604 switch (insn_error
.format
)
2611 as_bad (msg
, insn_error
.u
.i
, str
);
2615 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2619 free ((char *) msg
);
2622 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2623 the idea is to make it obvious at a glance that each errata is
2627 init_vr4120_conflicts (void)
2629 #define CONFLICT(FIRST, SECOND) \
2630 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2632 /* Errata 21 - [D]DIV[U] after [D]MACC */
2633 CONFLICT (MACC
, DIV
);
2634 CONFLICT (DMACC
, DIV
);
2636 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2637 CONFLICT (DMULT
, DMULT
);
2638 CONFLICT (DMULT
, DMACC
);
2639 CONFLICT (DMACC
, DMULT
);
2640 CONFLICT (DMACC
, DMACC
);
2642 /* Errata 24 - MT{LO,HI} after [D]MACC */
2643 CONFLICT (MACC
, MTHILO
);
2644 CONFLICT (DMACC
, MTHILO
);
2646 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2647 instruction is executed immediately after a MACC or DMACC
2648 instruction, the result of [either instruction] is incorrect." */
2649 CONFLICT (MACC
, MULT
);
2650 CONFLICT (MACC
, DMULT
);
2651 CONFLICT (DMACC
, MULT
);
2652 CONFLICT (DMACC
, DMULT
);
2654 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2655 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2656 DDIV or DDIVU instruction, the result of the MACC or
2657 DMACC instruction is incorrect.". */
2658 CONFLICT (DMULT
, MACC
);
2659 CONFLICT (DMULT
, DMACC
);
2660 CONFLICT (DIV
, MACC
);
2661 CONFLICT (DIV
, DMACC
);
2671 #define RNUM_MASK 0x00000ff
2672 #define RTYPE_MASK 0x0ffff00
2673 #define RTYPE_NUM 0x0000100
2674 #define RTYPE_FPU 0x0000200
2675 #define RTYPE_FCC 0x0000400
2676 #define RTYPE_VEC 0x0000800
2677 #define RTYPE_GP 0x0001000
2678 #define RTYPE_CP0 0x0002000
2679 #define RTYPE_PC 0x0004000
2680 #define RTYPE_ACC 0x0008000
2681 #define RTYPE_CCC 0x0010000
2682 #define RTYPE_VI 0x0020000
2683 #define RTYPE_VF 0x0040000
2684 #define RTYPE_R5900_I 0x0080000
2685 #define RTYPE_R5900_Q 0x0100000
2686 #define RTYPE_R5900_R 0x0200000
2687 #define RTYPE_R5900_ACC 0x0400000
2688 #define RTYPE_MSA 0x0800000
2689 #define RWARN 0x8000000
2691 #define GENERIC_REGISTER_NUMBERS \
2692 {"$0", RTYPE_NUM | 0}, \
2693 {"$1", RTYPE_NUM | 1}, \
2694 {"$2", RTYPE_NUM | 2}, \
2695 {"$3", RTYPE_NUM | 3}, \
2696 {"$4", RTYPE_NUM | 4}, \
2697 {"$5", RTYPE_NUM | 5}, \
2698 {"$6", RTYPE_NUM | 6}, \
2699 {"$7", RTYPE_NUM | 7}, \
2700 {"$8", RTYPE_NUM | 8}, \
2701 {"$9", RTYPE_NUM | 9}, \
2702 {"$10", RTYPE_NUM | 10}, \
2703 {"$11", RTYPE_NUM | 11}, \
2704 {"$12", RTYPE_NUM | 12}, \
2705 {"$13", RTYPE_NUM | 13}, \
2706 {"$14", RTYPE_NUM | 14}, \
2707 {"$15", RTYPE_NUM | 15}, \
2708 {"$16", RTYPE_NUM | 16}, \
2709 {"$17", RTYPE_NUM | 17}, \
2710 {"$18", RTYPE_NUM | 18}, \
2711 {"$19", RTYPE_NUM | 19}, \
2712 {"$20", RTYPE_NUM | 20}, \
2713 {"$21", RTYPE_NUM | 21}, \
2714 {"$22", RTYPE_NUM | 22}, \
2715 {"$23", RTYPE_NUM | 23}, \
2716 {"$24", RTYPE_NUM | 24}, \
2717 {"$25", RTYPE_NUM | 25}, \
2718 {"$26", RTYPE_NUM | 26}, \
2719 {"$27", RTYPE_NUM | 27}, \
2720 {"$28", RTYPE_NUM | 28}, \
2721 {"$29", RTYPE_NUM | 29}, \
2722 {"$30", RTYPE_NUM | 30}, \
2723 {"$31", RTYPE_NUM | 31}
2725 #define FPU_REGISTER_NAMES \
2726 {"$f0", RTYPE_FPU | 0}, \
2727 {"$f1", RTYPE_FPU | 1}, \
2728 {"$f2", RTYPE_FPU | 2}, \
2729 {"$f3", RTYPE_FPU | 3}, \
2730 {"$f4", RTYPE_FPU | 4}, \
2731 {"$f5", RTYPE_FPU | 5}, \
2732 {"$f6", RTYPE_FPU | 6}, \
2733 {"$f7", RTYPE_FPU | 7}, \
2734 {"$f8", RTYPE_FPU | 8}, \
2735 {"$f9", RTYPE_FPU | 9}, \
2736 {"$f10", RTYPE_FPU | 10}, \
2737 {"$f11", RTYPE_FPU | 11}, \
2738 {"$f12", RTYPE_FPU | 12}, \
2739 {"$f13", RTYPE_FPU | 13}, \
2740 {"$f14", RTYPE_FPU | 14}, \
2741 {"$f15", RTYPE_FPU | 15}, \
2742 {"$f16", RTYPE_FPU | 16}, \
2743 {"$f17", RTYPE_FPU | 17}, \
2744 {"$f18", RTYPE_FPU | 18}, \
2745 {"$f19", RTYPE_FPU | 19}, \
2746 {"$f20", RTYPE_FPU | 20}, \
2747 {"$f21", RTYPE_FPU | 21}, \
2748 {"$f22", RTYPE_FPU | 22}, \
2749 {"$f23", RTYPE_FPU | 23}, \
2750 {"$f24", RTYPE_FPU | 24}, \
2751 {"$f25", RTYPE_FPU | 25}, \
2752 {"$f26", RTYPE_FPU | 26}, \
2753 {"$f27", RTYPE_FPU | 27}, \
2754 {"$f28", RTYPE_FPU | 28}, \
2755 {"$f29", RTYPE_FPU | 29}, \
2756 {"$f30", RTYPE_FPU | 30}, \
2757 {"$f31", RTYPE_FPU | 31}
2759 #define FPU_CONDITION_CODE_NAMES \
2760 {"$fcc0", RTYPE_FCC | 0}, \
2761 {"$fcc1", RTYPE_FCC | 1}, \
2762 {"$fcc2", RTYPE_FCC | 2}, \
2763 {"$fcc3", RTYPE_FCC | 3}, \
2764 {"$fcc4", RTYPE_FCC | 4}, \
2765 {"$fcc5", RTYPE_FCC | 5}, \
2766 {"$fcc6", RTYPE_FCC | 6}, \
2767 {"$fcc7", RTYPE_FCC | 7}
2769 #define COPROC_CONDITION_CODE_NAMES \
2770 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2771 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2772 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2773 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2774 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2775 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2776 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2777 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2779 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2780 {"$a4", RTYPE_GP | 8}, \
2781 {"$a5", RTYPE_GP | 9}, \
2782 {"$a6", RTYPE_GP | 10}, \
2783 {"$a7", RTYPE_GP | 11}, \
2784 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2785 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2786 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2787 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2788 {"$t0", RTYPE_GP | 12}, \
2789 {"$t1", RTYPE_GP | 13}, \
2790 {"$t2", RTYPE_GP | 14}, \
2791 {"$t3", RTYPE_GP | 15}
2793 #define O32_SYMBOLIC_REGISTER_NAMES \
2794 {"$t0", RTYPE_GP | 8}, \
2795 {"$t1", RTYPE_GP | 9}, \
2796 {"$t2", RTYPE_GP | 10}, \
2797 {"$t3", RTYPE_GP | 11}, \
2798 {"$t4", RTYPE_GP | 12}, \
2799 {"$t5", RTYPE_GP | 13}, \
2800 {"$t6", RTYPE_GP | 14}, \
2801 {"$t7", RTYPE_GP | 15}, \
2802 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2803 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2804 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2805 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2807 /* Remaining symbolic register names. */
2808 #define SYMBOLIC_REGISTER_NAMES \
2809 {"$zero", RTYPE_GP | 0}, \
2810 {"$at", RTYPE_GP | 1}, \
2811 {"$AT", RTYPE_GP | 1}, \
2812 {"$v0", RTYPE_GP | 2}, \
2813 {"$v1", RTYPE_GP | 3}, \
2814 {"$a0", RTYPE_GP | 4}, \
2815 {"$a1", RTYPE_GP | 5}, \
2816 {"$a2", RTYPE_GP | 6}, \
2817 {"$a3", RTYPE_GP | 7}, \
2818 {"$s0", RTYPE_GP | 16}, \
2819 {"$s1", RTYPE_GP | 17}, \
2820 {"$s2", RTYPE_GP | 18}, \
2821 {"$s3", RTYPE_GP | 19}, \
2822 {"$s4", RTYPE_GP | 20}, \
2823 {"$s5", RTYPE_GP | 21}, \
2824 {"$s6", RTYPE_GP | 22}, \
2825 {"$s7", RTYPE_GP | 23}, \
2826 {"$t8", RTYPE_GP | 24}, \
2827 {"$t9", RTYPE_GP | 25}, \
2828 {"$k0", RTYPE_GP | 26}, \
2829 {"$kt0", RTYPE_GP | 26}, \
2830 {"$k1", RTYPE_GP | 27}, \
2831 {"$kt1", RTYPE_GP | 27}, \
2832 {"$gp", RTYPE_GP | 28}, \
2833 {"$sp", RTYPE_GP | 29}, \
2834 {"$s8", RTYPE_GP | 30}, \
2835 {"$fp", RTYPE_GP | 30}, \
2836 {"$ra", RTYPE_GP | 31}
2838 #define MIPS16_SPECIAL_REGISTER_NAMES \
2839 {"$pc", RTYPE_PC | 0}
2841 #define MDMX_VECTOR_REGISTER_NAMES \
2842 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2843 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2844 {"$v2", RTYPE_VEC | 2}, \
2845 {"$v3", RTYPE_VEC | 3}, \
2846 {"$v4", RTYPE_VEC | 4}, \
2847 {"$v5", RTYPE_VEC | 5}, \
2848 {"$v6", RTYPE_VEC | 6}, \
2849 {"$v7", RTYPE_VEC | 7}, \
2850 {"$v8", RTYPE_VEC | 8}, \
2851 {"$v9", RTYPE_VEC | 9}, \
2852 {"$v10", RTYPE_VEC | 10}, \
2853 {"$v11", RTYPE_VEC | 11}, \
2854 {"$v12", RTYPE_VEC | 12}, \
2855 {"$v13", RTYPE_VEC | 13}, \
2856 {"$v14", RTYPE_VEC | 14}, \
2857 {"$v15", RTYPE_VEC | 15}, \
2858 {"$v16", RTYPE_VEC | 16}, \
2859 {"$v17", RTYPE_VEC | 17}, \
2860 {"$v18", RTYPE_VEC | 18}, \
2861 {"$v19", RTYPE_VEC | 19}, \
2862 {"$v20", RTYPE_VEC | 20}, \
2863 {"$v21", RTYPE_VEC | 21}, \
2864 {"$v22", RTYPE_VEC | 22}, \
2865 {"$v23", RTYPE_VEC | 23}, \
2866 {"$v24", RTYPE_VEC | 24}, \
2867 {"$v25", RTYPE_VEC | 25}, \
2868 {"$v26", RTYPE_VEC | 26}, \
2869 {"$v27", RTYPE_VEC | 27}, \
2870 {"$v28", RTYPE_VEC | 28}, \
2871 {"$v29", RTYPE_VEC | 29}, \
2872 {"$v30", RTYPE_VEC | 30}, \
2873 {"$v31", RTYPE_VEC | 31}
2875 #define R5900_I_NAMES \
2876 {"$I", RTYPE_R5900_I | 0}
2878 #define R5900_Q_NAMES \
2879 {"$Q", RTYPE_R5900_Q | 0}
2881 #define R5900_R_NAMES \
2882 {"$R", RTYPE_R5900_R | 0}
2884 #define R5900_ACC_NAMES \
2885 {"$ACC", RTYPE_R5900_ACC | 0 }
2887 #define MIPS_DSP_ACCUMULATOR_NAMES \
2888 {"$ac0", RTYPE_ACC | 0}, \
2889 {"$ac1", RTYPE_ACC | 1}, \
2890 {"$ac2", RTYPE_ACC | 2}, \
2891 {"$ac3", RTYPE_ACC | 3}
2893 static const struct regname reg_names
[] = {
2894 GENERIC_REGISTER_NUMBERS
,
2896 FPU_CONDITION_CODE_NAMES
,
2897 COPROC_CONDITION_CODE_NAMES
,
2899 /* The $txx registers depends on the abi,
2900 these will be added later into the symbol table from
2901 one of the tables below once mips_abi is set after
2902 parsing of arguments from the command line. */
2903 SYMBOLIC_REGISTER_NAMES
,
2905 MIPS16_SPECIAL_REGISTER_NAMES
,
2906 MDMX_VECTOR_REGISTER_NAMES
,
2911 MIPS_DSP_ACCUMULATOR_NAMES
,
2915 static const struct regname reg_names_o32
[] = {
2916 O32_SYMBOLIC_REGISTER_NAMES
,
2920 static const struct regname reg_names_n32n64
[] = {
2921 N32N64_SYMBOLIC_REGISTER_NAMES
,
2925 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2926 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2927 of these register symbols, return the associated vector register,
2928 otherwise return SYMVAL itself. */
2931 mips_prefer_vec_regno (unsigned int symval
)
2933 if ((symval
& -2) == (RTYPE_GP
| 2))
2934 return RTYPE_VEC
| (symval
& 1);
2938 /* Return true if string [S, E) is a valid register name, storing its
2939 symbol value in *SYMVAL_PTR if so. */
2942 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2947 /* Terminate name. */
2951 /* Look up the name. */
2952 symbol
= symbol_find (s
);
2955 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2958 *symval_ptr
= S_GET_VALUE (symbol
);
2962 /* Return true if the string at *SPTR is a valid register name. Allow it
2963 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2966 When returning true, move *SPTR past the register, store the
2967 register's symbol value in *SYMVAL_PTR and the channel mask in
2968 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2969 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2970 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2973 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2974 unsigned int *channels_ptr
)
2978 unsigned int channels
, symval
, bit
;
2980 /* Find end of name. */
2982 if (is_name_beginner (*e
))
2984 while (is_part_of_name (*e
))
2988 if (!mips_parse_register_1 (s
, e
, &symval
))
2993 /* Eat characters from the end of the string that are valid
2994 channel suffixes. The preceding register must be $ACC or
2995 end with a digit, so there is no ambiguity. */
2998 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2999 if (m
> s
&& m
[-1] == *q
)
3006 || !mips_parse_register_1 (s
, m
, &symval
)
3007 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3012 *symval_ptr
= symval
;
3014 *channels_ptr
= channels
;
3018 /* Check if SPTR points at a valid register specifier according to TYPES.
3019 If so, then return 1, advance S to consume the specifier and store
3020 the register's number in REGNOP, otherwise return 0. */
3023 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3027 if (mips_parse_register (s
, ®no
, NULL
))
3029 if (types
& RTYPE_VEC
)
3030 regno
= mips_prefer_vec_regno (regno
);
3039 as_warn (_("unrecognized register name `%s'"), *s
);
3044 return regno
<= RNUM_MASK
;
3047 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3048 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3051 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3056 for (i
= 0; i
< 4; i
++)
3057 if (*s
== "xyzw"[i
])
3059 *channels
|= 1 << (3 - i
);
3065 /* Token types for parsed operand lists. */
3066 enum mips_operand_token_type
{
3067 /* A plain register, e.g. $f2. */
3070 /* A 4-bit XYZW channel mask. */
3073 /* A constant vector index, e.g. [1]. */
3076 /* A register vector index, e.g. [$2]. */
3079 /* A continuous range of registers, e.g. $s0-$s4. */
3082 /* A (possibly relocated) expression. */
3085 /* A floating-point value. */
3088 /* A single character. This can be '(', ')' or ',', but '(' only appears
3092 /* A doubled character, either "--" or "++". */
3095 /* The end of the operand list. */
3099 /* A parsed operand token. */
3100 struct mips_operand_token
3102 /* The type of token. */
3103 enum mips_operand_token_type type
;
3106 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3109 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3110 unsigned int channels
;
3112 /* The integer value of an OT_INTEGER_INDEX. */
3115 /* The two register symbol values involved in an OT_REG_RANGE. */
3117 unsigned int regno1
;
3118 unsigned int regno2
;
3121 /* The value of an OT_INTEGER. The value is represented as an
3122 expression and the relocation operators that were applied to
3123 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3124 relocation operators were used. */
3127 bfd_reloc_code_real_type relocs
[3];
3130 /* The binary data for an OT_FLOAT constant, and the number of bytes
3133 unsigned char data
[8];
3137 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3142 /* An obstack used to construct lists of mips_operand_tokens. */
3143 static struct obstack mips_operand_tokens
;
3145 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3148 mips_add_token (struct mips_operand_token
*token
,
3149 enum mips_operand_token_type type
)
3152 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3155 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3156 and OT_REG tokens for them if so, and return a pointer to the first
3157 unconsumed character. Return null otherwise. */
3160 mips_parse_base_start (char *s
)
3162 struct mips_operand_token token
;
3163 unsigned int regno
, channels
;
3164 bfd_boolean decrement_p
;
3170 SKIP_SPACE_TABS (s
);
3172 /* Only match "--" as part of a base expression. In other contexts "--X"
3173 is a double negative. */
3174 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3178 SKIP_SPACE_TABS (s
);
3181 /* Allow a channel specifier because that leads to better error messages
3182 than treating something like "$vf0x++" as an expression. */
3183 if (!mips_parse_register (&s
, ®no
, &channels
))
3187 mips_add_token (&token
, OT_CHAR
);
3192 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3195 token
.u
.regno
= regno
;
3196 mips_add_token (&token
, OT_REG
);
3200 token
.u
.channels
= channels
;
3201 mips_add_token (&token
, OT_CHANNELS
);
3204 /* For consistency, only match "++" as part of base expressions too. */
3205 SKIP_SPACE_TABS (s
);
3206 if (s
[0] == '+' && s
[1] == '+')
3210 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3216 /* Parse one or more tokens from S. Return a pointer to the first
3217 unconsumed character on success. Return null if an error was found
3218 and store the error text in insn_error. FLOAT_FORMAT is as for
3219 mips_parse_arguments. */
3222 mips_parse_argument_token (char *s
, char float_format
)
3224 char *end
, *save_in
;
3226 unsigned int regno1
, regno2
, channels
;
3227 struct mips_operand_token token
;
3229 /* First look for "($reg", since we want to treat that as an
3230 OT_CHAR and OT_REG rather than an expression. */
3231 end
= mips_parse_base_start (s
);
3235 /* Handle other characters that end up as OT_CHARs. */
3236 if (*s
== ')' || *s
== ',')
3239 mips_add_token (&token
, OT_CHAR
);
3244 /* Handle tokens that start with a register. */
3245 if (mips_parse_register (&s
, ®no1
, &channels
))
3249 /* A register and a VU0 channel suffix. */
3250 token
.u
.regno
= regno1
;
3251 mips_add_token (&token
, OT_REG
);
3253 token
.u
.channels
= channels
;
3254 mips_add_token (&token
, OT_CHANNELS
);
3258 SKIP_SPACE_TABS (s
);
3261 /* A register range. */
3263 SKIP_SPACE_TABS (s
);
3264 if (!mips_parse_register (&s
, ®no2
, NULL
))
3266 set_insn_error (0, _("invalid register range"));
3270 token
.u
.reg_range
.regno1
= regno1
;
3271 token
.u
.reg_range
.regno2
= regno2
;
3272 mips_add_token (&token
, OT_REG_RANGE
);
3276 /* Add the register itself. */
3277 token
.u
.regno
= regno1
;
3278 mips_add_token (&token
, OT_REG
);
3280 /* Check for a vector index. */
3284 SKIP_SPACE_TABS (s
);
3285 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3286 mips_add_token (&token
, OT_REG_INDEX
);
3289 expressionS element
;
3291 my_getExpression (&element
, s
);
3292 if (element
.X_op
!= O_constant
)
3294 set_insn_error (0, _("vector element must be constant"));
3298 token
.u
.index
= element
.X_add_number
;
3299 mips_add_token (&token
, OT_INTEGER_INDEX
);
3301 SKIP_SPACE_TABS (s
);
3304 set_insn_error (0, _("missing `]'"));
3314 /* First try to treat expressions as floats. */
3315 save_in
= input_line_pointer
;
3316 input_line_pointer
= s
;
3317 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3318 &token
.u
.flt
.length
);
3319 end
= input_line_pointer
;
3320 input_line_pointer
= save_in
;
3323 set_insn_error (0, err
);
3328 mips_add_token (&token
, OT_FLOAT
);
3333 /* Treat everything else as an integer expression. */
3334 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3335 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3336 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3337 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3339 mips_add_token (&token
, OT_INTEGER
);
3343 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3344 if expressions should be treated as 32-bit floating-point constants,
3345 'd' if they should be treated as 64-bit floating-point constants,
3346 or 0 if they should be treated as integer expressions (the usual case).
3348 Return a list of tokens on success, otherwise return 0. The caller
3349 must obstack_free the list after use. */
3351 static struct mips_operand_token
*
3352 mips_parse_arguments (char *s
, char float_format
)
3354 struct mips_operand_token token
;
3356 SKIP_SPACE_TABS (s
);
3359 s
= mips_parse_argument_token (s
, float_format
);
3362 obstack_free (&mips_operand_tokens
,
3363 obstack_finish (&mips_operand_tokens
));
3366 SKIP_SPACE_TABS (s
);
3368 mips_add_token (&token
, OT_END
);
3369 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3372 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3373 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3376 is_opcode_valid (const struct mips_opcode
*mo
)
3378 int isa
= mips_opts
.isa
;
3379 int ase
= mips_opts
.ase
;
3383 if (ISA_HAS_64BIT_REGS (isa
))
3384 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3385 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3386 ase
|= mips_ases
[i
].flags64
;
3388 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3391 /* Check whether the instruction or macro requires single-precision or
3392 double-precision floating-point support. Note that this information is
3393 stored differently in the opcode table for insns and macros. */
3394 if (mo
->pinfo
== INSN_MACRO
)
3396 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3397 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3401 fp_s
= mo
->pinfo
& FP_S
;
3402 fp_d
= mo
->pinfo
& FP_D
;
3405 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3408 if (fp_s
&& mips_opts
.soft_float
)
3414 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3415 selected ISA and architecture. */
3418 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3420 int isa
= mips_opts
.isa
;
3421 int ase
= mips_opts
.ase
;
3424 if (ISA_HAS_64BIT_REGS (isa
))
3425 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3426 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3427 ase
|= mips_ases
[i
].flags64
;
3429 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3432 /* Return TRUE if the size of the microMIPS opcode MO matches one
3433 explicitly requested. Always TRUE in the standard MIPS mode.
3434 Use is_size_valid_16 for MIPS16 opcodes. */
3437 is_size_valid (const struct mips_opcode
*mo
)
3439 if (!mips_opts
.micromips
)
3442 if (mips_opts
.insn32
)
3444 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3446 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3449 if (!forced_insn_length
)
3451 if (mo
->pinfo
== INSN_MACRO
)
3453 return forced_insn_length
== micromips_insn_length (mo
);
3456 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3457 explicitly requested. */
3460 is_size_valid_16 (const struct mips_opcode
*mo
)
3462 if (!forced_insn_length
)
3464 if (mo
->pinfo
== INSN_MACRO
)
3466 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3468 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3473 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3474 of the preceding instruction. Always TRUE in the standard MIPS mode.
3476 We don't accept macros in 16-bit delay slots to avoid a case where
3477 a macro expansion fails because it relies on a preceding 32-bit real
3478 instruction to have matched and does not handle the operands correctly.
3479 The only macros that may expand to 16-bit instructions are JAL that
3480 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3481 and BGT (that likewise cannot be placed in a delay slot) that decay to
3482 a NOP. In all these cases the macros precede any corresponding real
3483 instruction definitions in the opcode table, so they will match in the
3484 second pass where the size of the delay slot is ignored and therefore
3485 produce correct code. */
3488 is_delay_slot_valid (const struct mips_opcode
*mo
)
3490 if (!mips_opts
.micromips
)
3493 if (mo
->pinfo
== INSN_MACRO
)
3494 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3495 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3496 && micromips_insn_length (mo
) != 4)
3498 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3499 && micromips_insn_length (mo
) != 2)
3505 /* For consistency checking, verify that all bits of OPCODE are specified
3506 either by the match/mask part of the instruction definition, or by the
3507 operand list. Also build up a list of operands in OPERANDS.
3509 INSN_BITS says which bits of the instruction are significant.
3510 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3511 provides the mips_operand description of each operand. DECODE_OPERAND
3512 is null for MIPS16 instructions. */
3515 validate_mips_insn (const struct mips_opcode
*opcode
,
3516 unsigned long insn_bits
,
3517 const struct mips_operand
*(*decode_operand
) (const char *),
3518 struct mips_operand_array
*operands
)
3521 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3522 const struct mips_operand
*operand
;
3524 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3525 if ((mask
& opcode
->match
) != opcode
->match
)
3527 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3528 opcode
->name
, opcode
->args
);
3533 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3534 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3535 for (s
= opcode
->args
; *s
; ++s
)
3548 if (!decode_operand
)
3549 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3551 operand
= decode_operand (s
);
3552 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3554 as_bad (_("internal: unknown operand type: %s %s"),
3555 opcode
->name
, opcode
->args
);
3558 gas_assert (opno
< MAX_OPERANDS
);
3559 operands
->operand
[opno
] = operand
;
3560 if (!decode_operand
&& operand
3561 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3562 && mips_opcode_32bit_p (opcode
))
3563 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3564 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3566 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3567 if (operand
->type
== OP_MDMX_IMM_REG
)
3568 /* Bit 5 is the format selector (OB vs QH). The opcode table
3569 has separate entries for each format. */
3570 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3571 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3572 used_bits
&= ~(mask
& 0x700);
3573 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3574 operand field that cannot be fully described with LSB/SIZE. */
3575 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3576 used_bits
&= ~0x6000;
3578 /* Skip prefix characters. */
3579 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3584 doubled
= used_bits
& mask
& insn_bits
;
3587 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3588 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3592 undefined
= ~used_bits
& insn_bits
;
3593 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3595 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3596 undefined
, opcode
->name
, opcode
->args
);
3599 used_bits
&= ~insn_bits
;
3602 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3603 used_bits
, opcode
->name
, opcode
->args
);
3609 /* The MIPS16 version of validate_mips_insn. */
3612 validate_mips16_insn (const struct mips_opcode
*opcode
,
3613 struct mips_operand_array
*operands
)
3615 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3617 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3620 /* The microMIPS version of validate_mips_insn. */
3623 validate_micromips_insn (const struct mips_opcode
*opc
,
3624 struct mips_operand_array
*operands
)
3626 unsigned long insn_bits
;
3627 unsigned long major
;
3628 unsigned int length
;
3630 if (opc
->pinfo
== INSN_MACRO
)
3631 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3634 length
= micromips_insn_length (opc
);
3635 if (length
!= 2 && length
!= 4)
3637 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3638 "%s %s"), length
, opc
->name
, opc
->args
);
3641 major
= opc
->match
>> (10 + 8 * (length
- 2));
3642 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3643 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3645 as_bad (_("internal error: bad microMIPS opcode "
3646 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3650 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3651 insn_bits
= 1 << 4 * length
;
3652 insn_bits
<<= 4 * length
;
3654 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3658 /* This function is called once, at assembler startup time. It should set up
3659 all the tables, etc. that the MD part of the assembler will need. */
3664 const char *retval
= NULL
;
3668 if (mips_pic
!= NO_PIC
)
3670 if (g_switch_seen
&& g_switch_value
!= 0)
3671 as_bad (_("-G may not be used in position-independent code"));
3674 else if (mips_abicalls
)
3676 if (g_switch_seen
&& g_switch_value
!= 0)
3677 as_bad (_("-G may not be used with abicalls"));
3681 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3682 as_warn (_("could not set architecture and machine"));
3684 op_hash
= hash_new ();
3686 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3687 for (i
= 0; i
< NUMOPCODES
;)
3689 const char *name
= mips_opcodes
[i
].name
;
3691 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3694 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3695 mips_opcodes
[i
].name
, retval
);
3696 /* Probably a memory allocation problem? Give up now. */
3697 as_fatal (_("broken assembler, no assembly attempted"));
3701 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3702 decode_mips_operand
, &mips_operands
[i
]))
3705 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3707 create_insn (&nop_insn
, mips_opcodes
+ i
);
3708 if (mips_fix_loongson2f_nop
)
3709 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3710 nop_insn
.fixed_p
= 1;
3713 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3714 create_insn (&sync_insn
, mips_opcodes
+ i
);
3718 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3721 mips16_op_hash
= hash_new ();
3722 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3723 bfd_mips16_num_opcodes
);
3726 while (i
< bfd_mips16_num_opcodes
)
3728 const char *name
= mips16_opcodes
[i
].name
;
3730 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3732 as_fatal (_("internal: can't hash `%s': %s"),
3733 mips16_opcodes
[i
].name
, retval
);
3736 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3738 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3740 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3741 mips16_nop_insn
.fixed_p
= 1;
3745 while (i
< bfd_mips16_num_opcodes
3746 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3749 micromips_op_hash
= hash_new ();
3750 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3751 bfd_micromips_num_opcodes
);
3754 while (i
< bfd_micromips_num_opcodes
)
3756 const char *name
= micromips_opcodes
[i
].name
;
3758 retval
= hash_insert (micromips_op_hash
, name
,
3759 (void *) µmips_opcodes
[i
]);
3761 as_fatal (_("internal: can't hash `%s': %s"),
3762 micromips_opcodes
[i
].name
, retval
);
3765 struct mips_cl_insn
*micromips_nop_insn
;
3767 if (!validate_micromips_insn (µmips_opcodes
[i
],
3768 µmips_operands
[i
]))
3771 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3773 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3774 micromips_nop_insn
= µmips_nop16_insn
;
3775 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3776 micromips_nop_insn
= µmips_nop32_insn
;
3780 if (micromips_nop_insn
->insn_mo
== NULL
3781 && strcmp (name
, "nop") == 0)
3783 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3784 micromips_nop_insn
->fixed_p
= 1;
3788 while (++i
< bfd_micromips_num_opcodes
3789 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3793 as_fatal (_("broken assembler, no assembly attempted"));
3795 /* We add all the general register names to the symbol table. This
3796 helps us detect invalid uses of them. */
3797 for (i
= 0; reg_names
[i
].name
; i
++)
3798 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3799 reg_names
[i
].num
, /* & RNUM_MASK, */
3800 &zero_address_frag
));
3802 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3803 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3804 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3805 &zero_address_frag
));
3807 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3808 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3809 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3810 &zero_address_frag
));
3812 for (i
= 0; i
< 32; i
++)
3816 /* R5900 VU0 floating-point register. */
3817 sprintf (regname
, "$vf%d", i
);
3818 symbol_table_insert (symbol_new (regname
, reg_section
,
3819 RTYPE_VF
| i
, &zero_address_frag
));
3821 /* R5900 VU0 integer register. */
3822 sprintf (regname
, "$vi%d", i
);
3823 symbol_table_insert (symbol_new (regname
, reg_section
,
3824 RTYPE_VI
| i
, &zero_address_frag
));
3827 sprintf (regname
, "$w%d", i
);
3828 symbol_table_insert (symbol_new (regname
, reg_section
,
3829 RTYPE_MSA
| i
, &zero_address_frag
));
3832 obstack_init (&mips_operand_tokens
);
3834 mips_no_prev_insn ();
3837 mips_cprmask
[0] = 0;
3838 mips_cprmask
[1] = 0;
3839 mips_cprmask
[2] = 0;
3840 mips_cprmask
[3] = 0;
3842 /* set the default alignment for the text section (2**2) */
3843 record_alignment (text_section
, 2);
3845 bfd_set_gp_size (stdoutput
, g_switch_value
);
3847 /* On a native system other than VxWorks, sections must be aligned
3848 to 16 byte boundaries. When configured for an embedded ELF
3849 target, we don't bother. */
3850 if (strncmp (TARGET_OS
, "elf", 3) != 0
3851 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3853 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3854 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3855 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3858 /* Create a .reginfo section for register masks and a .mdebug
3859 section for debugging information. */
3867 subseg
= now_subseg
;
3869 /* The ABI says this section should be loaded so that the
3870 running program can access it. However, we don't load it
3871 if we are configured for an embedded target. */
3872 flags
= SEC_READONLY
| SEC_DATA
;
3873 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3874 flags
|= SEC_ALLOC
| SEC_LOAD
;
3876 if (mips_abi
!= N64_ABI
)
3878 sec
= subseg_new (".reginfo", (subsegT
) 0);
3880 bfd_set_section_flags (stdoutput
, sec
, flags
);
3881 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3883 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3887 /* The 64-bit ABI uses a .MIPS.options section rather than
3888 .reginfo section. */
3889 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3890 bfd_set_section_flags (stdoutput
, sec
, flags
);
3891 bfd_set_section_alignment (stdoutput
, sec
, 3);
3893 /* Set up the option header. */
3895 Elf_Internal_Options opthdr
;
3898 opthdr
.kind
= ODK_REGINFO
;
3899 opthdr
.size
= (sizeof (Elf_External_Options
)
3900 + sizeof (Elf64_External_RegInfo
));
3903 f
= frag_more (sizeof (Elf_External_Options
));
3904 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3905 (Elf_External_Options
*) f
);
3907 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3911 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3912 bfd_set_section_flags (stdoutput
, sec
,
3913 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3914 bfd_set_section_alignment (stdoutput
, sec
, 3);
3915 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3917 if (ECOFF_DEBUGGING
)
3919 sec
= subseg_new (".mdebug", (subsegT
) 0);
3920 (void) bfd_set_section_flags (stdoutput
, sec
,
3921 SEC_HAS_CONTENTS
| SEC_READONLY
);
3922 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3924 else if (mips_flag_pdr
)
3926 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3927 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3928 SEC_READONLY
| SEC_RELOC
3930 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3933 subseg_set (seg
, subseg
);
3936 if (mips_fix_vr4120
)
3937 init_vr4120_conflicts ();
3941 fpabi_incompatible_with (int fpabi
, const char *what
)
3943 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3944 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3948 fpabi_requires (int fpabi
, const char *what
)
3950 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3951 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3954 /* Check -mabi and register sizes against the specified FP ABI. */
3956 check_fpabi (int fpabi
)
3960 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3961 if (file_mips_opts
.soft_float
)
3962 fpabi_incompatible_with (fpabi
, "softfloat");
3963 else if (file_mips_opts
.single_float
)
3964 fpabi_incompatible_with (fpabi
, "singlefloat");
3965 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3966 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3967 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3968 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3971 case Val_GNU_MIPS_ABI_FP_XX
:
3972 if (mips_abi
!= O32_ABI
)
3973 fpabi_requires (fpabi
, "-mabi=32");
3974 else if (file_mips_opts
.soft_float
)
3975 fpabi_incompatible_with (fpabi
, "softfloat");
3976 else if (file_mips_opts
.single_float
)
3977 fpabi_incompatible_with (fpabi
, "singlefloat");
3978 else if (file_mips_opts
.fp
!= 0)
3979 fpabi_requires (fpabi
, "fp=xx");
3982 case Val_GNU_MIPS_ABI_FP_64A
:
3983 case Val_GNU_MIPS_ABI_FP_64
:
3984 if (mips_abi
!= O32_ABI
)
3985 fpabi_requires (fpabi
, "-mabi=32");
3986 else if (file_mips_opts
.soft_float
)
3987 fpabi_incompatible_with (fpabi
, "softfloat");
3988 else if (file_mips_opts
.single_float
)
3989 fpabi_incompatible_with (fpabi
, "singlefloat");
3990 else if (file_mips_opts
.fp
!= 64)
3991 fpabi_requires (fpabi
, "fp=64");
3992 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3993 fpabi_incompatible_with (fpabi
, "nooddspreg");
3994 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3995 fpabi_requires (fpabi
, "nooddspreg");
3998 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3999 if (file_mips_opts
.soft_float
)
4000 fpabi_incompatible_with (fpabi
, "softfloat");
4001 else if (!file_mips_opts
.single_float
)
4002 fpabi_requires (fpabi
, "singlefloat");
4005 case Val_GNU_MIPS_ABI_FP_SOFT
:
4006 if (!file_mips_opts
.soft_float
)
4007 fpabi_requires (fpabi
, "softfloat");
4010 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4011 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4012 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4015 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4016 /* Silently ignore compatibility value. */
4020 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4021 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4026 /* Perform consistency checks on the current options. */
4029 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
4031 /* Check the size of integer registers agrees with the ABI and ISA. */
4032 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4033 as_bad (_("`gp=64' used with a 32-bit processor"));
4035 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4036 as_bad (_("`gp=32' used with a 64-bit ABI"));
4038 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4039 as_bad (_("`gp=64' used with a 32-bit ABI"));
4041 /* Check the size of the float registers agrees with the ABI and ISA. */
4045 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4046 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4047 else if (opts
->single_float
== 1)
4048 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4051 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4052 as_bad (_("`fp=64' used with a 32-bit fpu"));
4054 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4055 && !ISA_HAS_MXHC1 (opts
->isa
))
4056 as_warn (_("`fp=64' used with a 32-bit ABI"));
4060 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4061 as_warn (_("`fp=32' used with a 64-bit ABI"));
4062 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4063 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4066 as_bad (_("Unknown size of floating point registers"));
4070 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4071 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4073 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4074 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4075 else if (ISA_IS_R6 (opts
->isa
)
4076 && (opts
->micromips
== 1
4077 || opts
->mips16
== 1))
4078 as_fatal (_("`%s' cannot be used with `%s'"),
4079 opts
->micromips
? "micromips" : "mips16",
4080 mips_cpu_info_from_isa (opts
->isa
)->name
);
4082 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4083 as_fatal (_("branch relaxation is not supported in `%s'"),
4084 mips_cpu_info_from_isa (opts
->isa
)->name
);
4087 /* Perform consistency checks on the module level options exactly once.
4088 This is a deferred check that happens:
4089 at the first .set directive
4090 or, at the first pseudo op that generates code (inc .dc.a)
4091 or, at the first instruction
4095 file_mips_check_options (void)
4097 if (file_mips_opts_checked
)
4100 /* The following code determines the register size.
4101 Similar code was added to GCC 3.3 (see override_options() in
4102 config/mips/mips.c). The GAS and GCC code should be kept in sync
4103 as much as possible. */
4105 if (file_mips_opts
.gp
< 0)
4107 /* Infer the integer register size from the ABI and processor.
4108 Restrict ourselves to 32-bit registers if that's all the
4109 processor has, or if the ABI cannot handle 64-bit registers. */
4110 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4111 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4115 if (file_mips_opts
.fp
< 0)
4117 /* No user specified float register size.
4118 ??? GAS treats single-float processors as though they had 64-bit
4119 float registers (although it complains when double-precision
4120 instructions are used). As things stand, saying they have 32-bit
4121 registers would lead to spurious "register must be even" messages.
4122 So here we assume float registers are never smaller than the
4124 if (file_mips_opts
.gp
== 64)
4125 /* 64-bit integer registers implies 64-bit float registers. */
4126 file_mips_opts
.fp
= 64;
4127 else if ((file_mips_opts
.ase
& FP64_ASES
)
4128 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4129 /* Handle ASEs that require 64-bit float registers, if possible. */
4130 file_mips_opts
.fp
= 64;
4131 else if (ISA_IS_R6 (mips_opts
.isa
))
4132 /* R6 implies 64-bit float registers. */
4133 file_mips_opts
.fp
= 64;
4135 /* 32-bit float registers. */
4136 file_mips_opts
.fp
= 32;
4139 /* Disable operations on odd-numbered floating-point registers by default
4140 when using the FPXX ABI. */
4141 if (file_mips_opts
.oddspreg
< 0)
4143 if (file_mips_opts
.fp
== 0)
4144 file_mips_opts
.oddspreg
= 0;
4146 file_mips_opts
.oddspreg
= 1;
4149 /* End of GCC-shared inference code. */
4151 /* This flag is set when we have a 64-bit capable CPU but use only
4152 32-bit wide registers. Note that EABI does not use it. */
4153 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4154 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4155 || mips_abi
== O32_ABI
))
4158 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4159 as_bad (_("trap exception not supported at ISA 1"));
4161 /* If the selected architecture includes support for ASEs, enable
4162 generation of code for them. */
4163 if (file_mips_opts
.mips16
== -1)
4164 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4165 if (file_mips_opts
.micromips
== -1)
4166 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4169 if (mips_nan2008
== -1)
4170 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4171 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4172 as_fatal (_("`%s' does not support legacy NaN"),
4173 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4175 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4176 being selected implicitly. */
4177 if (file_mips_opts
.fp
!= 64)
4178 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4180 /* If the user didn't explicitly select or deselect a particular ASE,
4181 use the default setting for the CPU. */
4182 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4184 /* Set up the current options. These may change throughout assembly. */
4185 mips_opts
= file_mips_opts
;
4187 mips_check_isa_supports_ases ();
4188 mips_check_options (&file_mips_opts
, TRUE
);
4189 file_mips_opts_checked
= TRUE
;
4191 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4192 as_warn (_("could not set architecture and machine"));
4196 md_assemble (char *str
)
4198 struct mips_cl_insn insn
;
4199 bfd_reloc_code_real_type unused_reloc
[3]
4200 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4202 file_mips_check_options ();
4204 imm_expr
.X_op
= O_absent
;
4205 offset_expr
.X_op
= O_absent
;
4206 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4207 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4208 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4210 mips_mark_labels ();
4211 mips_assembling_insn
= TRUE
;
4212 clear_insn_error ();
4214 if (mips_opts
.mips16
)
4215 mips16_ip (str
, &insn
);
4218 mips_ip (str
, &insn
);
4219 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4220 str
, insn
.insn_opcode
));
4224 report_insn_error (str
);
4225 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4228 if (mips_opts
.mips16
)
4229 mips16_macro (&insn
);
4236 if (offset_expr
.X_op
!= O_absent
)
4237 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4239 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4242 mips_assembling_insn
= FALSE
;
4245 /* Convenience functions for abstracting away the differences between
4246 MIPS16 and non-MIPS16 relocations. */
4248 static inline bfd_boolean
4249 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4253 case BFD_RELOC_MIPS16_JMP
:
4254 case BFD_RELOC_MIPS16_GPREL
:
4255 case BFD_RELOC_MIPS16_GOT16
:
4256 case BFD_RELOC_MIPS16_CALL16
:
4257 case BFD_RELOC_MIPS16_HI16_S
:
4258 case BFD_RELOC_MIPS16_HI16
:
4259 case BFD_RELOC_MIPS16_LO16
:
4260 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4268 static inline bfd_boolean
4269 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4273 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4274 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4275 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4276 case BFD_RELOC_MICROMIPS_GPREL16
:
4277 case BFD_RELOC_MICROMIPS_JMP
:
4278 case BFD_RELOC_MICROMIPS_HI16
:
4279 case BFD_RELOC_MICROMIPS_HI16_S
:
4280 case BFD_RELOC_MICROMIPS_LO16
:
4281 case BFD_RELOC_MICROMIPS_LITERAL
:
4282 case BFD_RELOC_MICROMIPS_GOT16
:
4283 case BFD_RELOC_MICROMIPS_CALL16
:
4284 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4285 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4286 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4287 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4288 case BFD_RELOC_MICROMIPS_SUB
:
4289 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4290 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4291 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4292 case BFD_RELOC_MICROMIPS_HIGHEST
:
4293 case BFD_RELOC_MICROMIPS_HIGHER
:
4294 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4295 case BFD_RELOC_MICROMIPS_JALR
:
4303 static inline bfd_boolean
4304 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4306 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4309 static inline bfd_boolean
4310 b_reloc_p (bfd_reloc_code_real_type reloc
)
4312 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4313 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4314 || reloc
== BFD_RELOC_16_PCREL_S2
4315 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4316 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4317 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4318 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4321 static inline bfd_boolean
4322 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4324 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4325 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4328 static inline bfd_boolean
4329 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4331 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4332 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4335 static inline bfd_boolean
4336 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4338 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4339 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4342 static inline bfd_boolean
4343 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4345 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4348 static inline bfd_boolean
4349 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4351 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4352 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4355 /* Return true if RELOC is a PC-relative relocation that does not have
4356 full address range. */
4358 static inline bfd_boolean
4359 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4363 case BFD_RELOC_16_PCREL_S2
:
4364 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4365 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4366 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4367 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4368 case BFD_RELOC_MIPS_21_PCREL_S2
:
4369 case BFD_RELOC_MIPS_26_PCREL_S2
:
4370 case BFD_RELOC_MIPS_18_PCREL_S3
:
4371 case BFD_RELOC_MIPS_19_PCREL_S2
:
4374 case BFD_RELOC_32_PCREL
:
4375 case BFD_RELOC_HI16_S_PCREL
:
4376 case BFD_RELOC_LO16_PCREL
:
4377 return HAVE_64BIT_ADDRESSES
;
4384 /* Return true if the given relocation might need a matching %lo().
4385 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4386 need a matching %lo() when applied to local symbols. */
4388 static inline bfd_boolean
4389 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4391 return (HAVE_IN_PLACE_ADDENDS
4392 && (hi16_reloc_p (reloc
)
4393 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4394 all GOT16 relocations evaluate to "G". */
4395 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4398 /* Return the type of %lo() reloc needed by RELOC, given that
4399 reloc_needs_lo_p. */
4401 static inline bfd_reloc_code_real_type
4402 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4404 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4405 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4409 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4412 static inline bfd_boolean
4413 fixup_has_matching_lo_p (fixS
*fixp
)
4415 return (fixp
->fx_next
!= NULL
4416 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4417 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4418 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4421 /* Move all labels in LABELS to the current insertion point. TEXT_P
4422 says whether the labels refer to text or data. */
4425 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4427 struct insn_label_list
*l
;
4430 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4432 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4433 symbol_set_frag (l
->label
, frag_now
);
4434 val
= (valueT
) frag_now_fix ();
4435 /* MIPS16/microMIPS text labels are stored as odd. */
4436 if (text_p
&& HAVE_CODE_COMPRESSION
)
4438 S_SET_VALUE (l
->label
, val
);
4442 /* Move all labels in insn_labels to the current insertion point
4443 and treat them as text labels. */
4446 mips_move_text_labels (void)
4448 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4451 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4454 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4456 bfd_boolean linkonce
= FALSE
;
4457 segT symseg
= S_GET_SEGMENT (sym
);
4459 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4461 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4463 /* The GNU toolchain uses an extension for ELF: a section
4464 beginning with the magic string .gnu.linkonce is a
4465 linkonce section. */
4466 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4467 sizeof ".gnu.linkonce" - 1) == 0)
4473 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4474 linker to handle them specially, such as generating jalx instructions
4475 when needed. We also make them odd for the duration of the assembly,
4476 in order to generate the right sort of code. We will make them even
4477 in the adjust_symtab routine, while leaving them marked. This is
4478 convenient for the debugger and the disassembler. The linker knows
4479 to make them odd again. */
4482 mips_compressed_mark_label (symbolS
*label
)
4484 gas_assert (HAVE_CODE_COMPRESSION
);
4486 if (mips_opts
.mips16
)
4487 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4489 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4490 if ((S_GET_VALUE (label
) & 1) == 0
4491 /* Don't adjust the address if the label is global or weak, or
4492 in a link-once section, since we'll be emitting symbol reloc
4493 references to it which will be patched up by the linker, and
4494 the final value of the symbol may or may not be MIPS16/microMIPS. */
4495 && !S_IS_WEAK (label
)
4496 && !S_IS_EXTERNAL (label
)
4497 && !s_is_linkonce (label
, now_seg
))
4498 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4501 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4504 mips_compressed_mark_labels (void)
4506 struct insn_label_list
*l
;
4508 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4509 mips_compressed_mark_label (l
->label
);
4512 /* End the current frag. Make it a variant frag and record the
4516 relax_close_frag (void)
4518 mips_macro_warning
.first_frag
= frag_now
;
4519 frag_var (rs_machine_dependent
, 0, 0,
4520 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4521 mips_pic
!= NO_PIC
),
4522 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4524 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4525 mips_relax
.first_fixup
= 0;
4528 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4529 See the comment above RELAX_ENCODE for more details. */
4532 relax_start (symbolS
*symbol
)
4534 gas_assert (mips_relax
.sequence
== 0);
4535 mips_relax
.sequence
= 1;
4536 mips_relax
.symbol
= symbol
;
4539 /* Start generating the second version of a relaxable sequence.
4540 See the comment above RELAX_ENCODE for more details. */
4545 gas_assert (mips_relax
.sequence
== 1);
4546 mips_relax
.sequence
= 2;
4549 /* End the current relaxable sequence. */
4554 gas_assert (mips_relax
.sequence
== 2);
4555 relax_close_frag ();
4556 mips_relax
.sequence
= 0;
4559 /* Return true if IP is a delayed branch or jump. */
4561 static inline bfd_boolean
4562 delayed_branch_p (const struct mips_cl_insn
*ip
)
4564 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4565 | INSN_COND_BRANCH_DELAY
4566 | INSN_COND_BRANCH_LIKELY
)) != 0;
4569 /* Return true if IP is a compact branch or jump. */
4571 static inline bfd_boolean
4572 compact_branch_p (const struct mips_cl_insn
*ip
)
4574 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4575 | INSN2_COND_BRANCH
)) != 0;
4578 /* Return true if IP is an unconditional branch or jump. */
4580 static inline bfd_boolean
4581 uncond_branch_p (const struct mips_cl_insn
*ip
)
4583 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4584 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4587 /* Return true if IP is a branch-likely instruction. */
4589 static inline bfd_boolean
4590 branch_likely_p (const struct mips_cl_insn
*ip
)
4592 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4595 /* Return the type of nop that should be used to fill the delay slot
4596 of delayed branch IP. */
4598 static struct mips_cl_insn
*
4599 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4601 if (mips_opts
.micromips
4602 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4603 return µmips_nop32_insn
;
4607 /* Return a mask that has bit N set if OPCODE reads the register(s)
4611 insn_read_mask (const struct mips_opcode
*opcode
)
4613 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4616 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4620 insn_write_mask (const struct mips_opcode
*opcode
)
4622 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4625 /* Return a mask of the registers specified by operand OPERAND of INSN.
4626 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4630 operand_reg_mask (const struct mips_cl_insn
*insn
,
4631 const struct mips_operand
*operand
,
4632 unsigned int type_mask
)
4634 unsigned int uval
, vsel
;
4636 switch (operand
->type
)
4643 case OP_ADDIUSP_INT
:
4644 case OP_ENTRY_EXIT_LIST
:
4645 case OP_REPEAT_DEST_REG
:
4646 case OP_REPEAT_PREV_REG
:
4649 case OP_VU0_MATCH_SUFFIX
:
4657 case OP_OPTIONAL_REG
:
4659 const struct mips_reg_operand
*reg_op
;
4661 reg_op
= (const struct mips_reg_operand
*) operand
;
4662 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4664 uval
= insn_extract_operand (insn
, operand
);
4665 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4670 const struct mips_reg_pair_operand
*pair_op
;
4672 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4673 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4675 uval
= insn_extract_operand (insn
, operand
);
4676 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4679 case OP_CLO_CLZ_DEST
:
4680 if (!(type_mask
& (1 << OP_REG_GP
)))
4682 uval
= insn_extract_operand (insn
, operand
);
4683 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4686 if (!(type_mask
& (1 << OP_REG_GP
)))
4688 uval
= insn_extract_operand (insn
, operand
);
4689 gas_assert ((uval
& 31) == (uval
>> 5));
4690 return 1 << (uval
& 31);
4693 case OP_NON_ZERO_REG
:
4694 if (!(type_mask
& (1 << OP_REG_GP
)))
4696 uval
= insn_extract_operand (insn
, operand
);
4697 return 1 << (uval
& 31);
4699 case OP_LWM_SWM_LIST
:
4702 case OP_SAVE_RESTORE_LIST
:
4705 case OP_MDMX_IMM_REG
:
4706 if (!(type_mask
& (1 << OP_REG_VEC
)))
4708 uval
= insn_extract_operand (insn
, operand
);
4710 if ((vsel
& 0x18) == 0x18)
4712 return 1 << (uval
& 31);
4715 if (!(type_mask
& (1 << OP_REG_GP
)))
4717 return 1 << insn_extract_operand (insn
, operand
);
4722 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4723 where bit N of OPNO_MASK is set if operand N should be included.
4724 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4728 insn_reg_mask (const struct mips_cl_insn
*insn
,
4729 unsigned int type_mask
, unsigned int opno_mask
)
4731 unsigned int opno
, reg_mask
;
4735 while (opno_mask
!= 0)
4738 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4745 /* Return the mask of core registers that IP reads. */
4748 gpr_read_mask (const struct mips_cl_insn
*ip
)
4750 unsigned long pinfo
, pinfo2
;
4753 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4754 pinfo
= ip
->insn_mo
->pinfo
;
4755 pinfo2
= ip
->insn_mo
->pinfo2
;
4756 if (pinfo
& INSN_UDI
)
4758 /* UDI instructions have traditionally been assumed to read RS
4760 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4761 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4763 if (pinfo
& INSN_READ_GPR_24
)
4765 if (pinfo2
& INSN2_READ_GPR_16
)
4767 if (pinfo2
& INSN2_READ_SP
)
4769 if (pinfo2
& INSN2_READ_GPR_31
)
4771 /* Don't include register 0. */
4775 /* Return the mask of core registers that IP writes. */
4778 gpr_write_mask (const struct mips_cl_insn
*ip
)
4780 unsigned long pinfo
, pinfo2
;
4783 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4784 pinfo
= ip
->insn_mo
->pinfo
;
4785 pinfo2
= ip
->insn_mo
->pinfo2
;
4786 if (pinfo
& INSN_WRITE_GPR_24
)
4788 if (pinfo
& INSN_WRITE_GPR_31
)
4790 if (pinfo
& INSN_UDI
)
4791 /* UDI instructions have traditionally been assumed to write to RD. */
4792 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4793 if (pinfo2
& INSN2_WRITE_SP
)
4795 /* Don't include register 0. */
4799 /* Return the mask of floating-point registers that IP reads. */
4802 fpr_read_mask (const struct mips_cl_insn
*ip
)
4804 unsigned long pinfo
;
4807 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4808 | (1 << OP_REG_MSA
)),
4809 insn_read_mask (ip
->insn_mo
));
4810 pinfo
= ip
->insn_mo
->pinfo
;
4811 /* Conservatively treat all operands to an FP_D instruction are doubles.
4812 (This is overly pessimistic for things like cvt.d.s.) */
4813 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4818 /* Return the mask of floating-point registers that IP writes. */
4821 fpr_write_mask (const struct mips_cl_insn
*ip
)
4823 unsigned long pinfo
;
4826 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4827 | (1 << OP_REG_MSA
)),
4828 insn_write_mask (ip
->insn_mo
));
4829 pinfo
= ip
->insn_mo
->pinfo
;
4830 /* Conservatively treat all operands to an FP_D instruction are doubles.
4831 (This is overly pessimistic for things like cvt.s.d.) */
4832 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4837 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4838 Check whether that is allowed. */
4841 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4843 const char *s
= insn
->name
;
4844 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4846 && mips_opts
.oddspreg
;
4848 if (insn
->pinfo
== INSN_MACRO
)
4849 /* Let a macro pass, we'll catch it later when it is expanded. */
4852 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4853 otherwise it depends on oddspreg. */
4854 if ((insn
->pinfo
& FP_S
)
4855 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4856 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4857 return FPR_SIZE
== 32 || oddspreg
;
4859 /* Allow odd registers for single-precision ops and double-precision if the
4860 floating-point registers are 64-bit wide. */
4861 switch (insn
->pinfo
& (FP_S
| FP_D
))
4867 return FPR_SIZE
== 64;
4872 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4873 s
= strchr (insn
->name
, '.');
4874 if (s
!= NULL
&& opnum
== 2)
4875 s
= strchr (s
+ 1, '.');
4876 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4879 return FPR_SIZE
== 64;
4882 /* Information about an instruction argument that we're trying to match. */
4883 struct mips_arg_info
4885 /* The instruction so far. */
4886 struct mips_cl_insn
*insn
;
4888 /* The first unconsumed operand token. */
4889 struct mips_operand_token
*token
;
4891 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4894 /* The 1-based argument number, for error reporting. This does not
4895 count elided optional registers, etc.. */
4898 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4899 unsigned int last_regno
;
4901 /* If the first operand was an OP_REG, this is the register that it
4902 specified, otherwise it is ILLEGAL_REG. */
4903 unsigned int dest_regno
;
4905 /* The value of the last OP_INT operand. Only used for OP_MSB,
4906 where it gives the lsb position. */
4907 unsigned int last_op_int
;
4909 /* If true, match routines should assume that no later instruction
4910 alternative matches and should therefore be as accommodating as
4911 possible. Match routines should not report errors if something
4912 is only invalid for !LAX_MATCH. */
4913 bfd_boolean lax_match
;
4915 /* True if a reference to the current AT register was seen. */
4916 bfd_boolean seen_at
;
4919 /* Record that the argument is out of range. */
4922 match_out_of_range (struct mips_arg_info
*arg
)
4924 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4927 /* Record that the argument isn't constant but needs to be. */
4930 match_not_constant (struct mips_arg_info
*arg
)
4932 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4936 /* Try to match an OT_CHAR token for character CH. Consume the token
4937 and return true on success, otherwise return false. */
4940 match_char (struct mips_arg_info
*arg
, char ch
)
4942 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4952 /* Try to get an expression from the next tokens in ARG. Consume the
4953 tokens and return true on success, storing the expression value in
4954 VALUE and relocation types in R. */
4957 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4958 bfd_reloc_code_real_type
*r
)
4960 /* If the next token is a '(' that was parsed as being part of a base
4961 expression, assume we have an elided offset. The later match will fail
4962 if this turns out to be wrong. */
4963 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4965 value
->X_op
= O_constant
;
4966 value
->X_add_number
= 0;
4967 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4971 /* Reject register-based expressions such as "0+$2" and "(($2))".
4972 For plain registers the default error seems more appropriate. */
4973 if (arg
->token
->type
== OT_INTEGER
4974 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4976 set_insn_error (arg
->argnum
, _("register value used as expression"));
4980 if (arg
->token
->type
== OT_INTEGER
)
4982 *value
= arg
->token
->u
.integer
.value
;
4983 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4989 (arg
->argnum
, _("operand %d must be an immediate expression"),
4994 /* Try to get a constant expression from the next tokens in ARG. Consume
4995 the tokens and return true on success, storing the constant value
4999 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
5002 bfd_reloc_code_real_type r
[3];
5004 if (!match_expression (arg
, &ex
, r
))
5007 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5008 *value
= ex
.X_add_number
;
5011 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5012 match_out_of_range (arg
);
5014 match_not_constant (arg
);
5020 /* Return the RTYPE_* flags for a register operand of type TYPE that
5021 appears in instruction OPCODE. */
5024 convert_reg_type (const struct mips_opcode
*opcode
,
5025 enum mips_reg_operand_type type
)
5030 return RTYPE_NUM
| RTYPE_GP
;
5033 /* Allow vector register names for MDMX if the instruction is a 64-bit
5034 FPR load, store or move (including moves to and from GPRs). */
5035 if ((mips_opts
.ase
& ASE_MDMX
)
5036 && (opcode
->pinfo
& FP_D
)
5037 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5038 | INSN_COPROC_MEMORY_DELAY
5041 | INSN_STORE_MEMORY
)))
5042 return RTYPE_FPU
| RTYPE_VEC
;
5046 if (opcode
->pinfo
& (FP_D
| FP_S
))
5047 return RTYPE_CCC
| RTYPE_FCC
;
5051 if (opcode
->membership
& INSN_5400
)
5053 return RTYPE_FPU
| RTYPE_VEC
;
5059 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5060 return RTYPE_NUM
| RTYPE_CP0
;
5067 return RTYPE_NUM
| RTYPE_VI
;
5070 return RTYPE_NUM
| RTYPE_VF
;
5072 case OP_REG_R5900_I
:
5073 return RTYPE_R5900_I
;
5075 case OP_REG_R5900_Q
:
5076 return RTYPE_R5900_Q
;
5078 case OP_REG_R5900_R
:
5079 return RTYPE_R5900_R
;
5081 case OP_REG_R5900_ACC
:
5082 return RTYPE_R5900_ACC
;
5087 case OP_REG_MSA_CTRL
:
5093 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5096 check_regno (struct mips_arg_info
*arg
,
5097 enum mips_reg_operand_type type
, unsigned int regno
)
5099 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5100 arg
->seen_at
= TRUE
;
5102 if (type
== OP_REG_FP
5104 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5106 /* This was a warning prior to introducing O32 FPXX and FP64 support
5107 so maintain a warning for FP32 but raise an error for the new
5110 as_warn (_("float register should be even, was %d"), regno
);
5112 as_bad (_("float register should be even, was %d"), regno
);
5115 if (type
== OP_REG_CCC
)
5120 name
= arg
->insn
->insn_mo
->name
;
5121 length
= strlen (name
);
5122 if ((regno
& 1) != 0
5123 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5124 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5125 as_warn (_("condition code register should be even for %s, was %d"),
5128 if ((regno
& 3) != 0
5129 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5130 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5135 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5136 a register of type TYPE. Return true on success, storing the register
5137 number in *REGNO and warning about any dubious uses. */
5140 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5141 unsigned int symval
, unsigned int *regno
)
5143 if (type
== OP_REG_VEC
)
5144 symval
= mips_prefer_vec_regno (symval
);
5145 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5148 *regno
= symval
& RNUM_MASK
;
5149 check_regno (arg
, type
, *regno
);
5153 /* Try to interpret the next token in ARG as a register of type TYPE.
5154 Consume the token and return true on success, storing the register
5155 number in *REGNO. Return false on failure. */
5158 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5159 unsigned int *regno
)
5161 if (arg
->token
->type
== OT_REG
5162 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5170 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5171 Consume the token and return true on success, storing the register numbers
5172 in *REGNO1 and *REGNO2. Return false on failure. */
5175 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5176 unsigned int *regno1
, unsigned int *regno2
)
5178 if (match_reg (arg
, type
, regno1
))
5183 if (arg
->token
->type
== OT_REG_RANGE
5184 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5185 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5186 && *regno1
<= *regno2
)
5194 /* OP_INT matcher. */
5197 match_int_operand (struct mips_arg_info
*arg
,
5198 const struct mips_operand
*operand_base
)
5200 const struct mips_int_operand
*operand
;
5202 int min_val
, max_val
, factor
;
5205 operand
= (const struct mips_int_operand
*) operand_base
;
5206 factor
= 1 << operand
->shift
;
5207 min_val
= mips_int_operand_min (operand
);
5208 max_val
= mips_int_operand_max (operand
);
5210 if (operand_base
->lsb
== 0
5211 && operand_base
->size
== 16
5212 && operand
->shift
== 0
5213 && operand
->bias
== 0
5214 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5216 /* The operand can be relocated. */
5217 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5220 if (offset_expr
.X_op
== O_big
)
5222 match_out_of_range (arg
);
5226 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5227 /* Relocation operators were used. Accept the argument and
5228 leave the relocation value in offset_expr and offset_relocs
5229 for the caller to process. */
5232 if (offset_expr
.X_op
!= O_constant
)
5234 /* Accept non-constant operands if no later alternative matches,
5235 leaving it for the caller to process. */
5236 if (!arg
->lax_match
)
5238 match_not_constant (arg
);
5241 offset_reloc
[0] = BFD_RELOC_LO16
;
5245 /* Clear the global state; we're going to install the operand
5247 sval
= offset_expr
.X_add_number
;
5248 offset_expr
.X_op
= O_absent
;
5250 /* For compatibility with older assemblers, we accept
5251 0x8000-0xffff as signed 16-bit numbers when only
5252 signed numbers are allowed. */
5255 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5256 if (!arg
->lax_match
&& sval
<= max_val
)
5258 match_out_of_range (arg
);
5265 if (!match_const_int (arg
, &sval
))
5269 arg
->last_op_int
= sval
;
5271 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5273 match_out_of_range (arg
);
5277 uval
= (unsigned int) sval
>> operand
->shift
;
5278 uval
-= operand
->bias
;
5280 /* Handle -mfix-cn63xxp1. */
5282 && mips_fix_cn63xxp1
5283 && !mips_opts
.micromips
5284 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5299 /* The rest must be changed to 28. */
5304 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5308 /* OP_MAPPED_INT matcher. */
5311 match_mapped_int_operand (struct mips_arg_info
*arg
,
5312 const struct mips_operand
*operand_base
)
5314 const struct mips_mapped_int_operand
*operand
;
5315 unsigned int uval
, num_vals
;
5318 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5319 if (!match_const_int (arg
, &sval
))
5322 num_vals
= 1 << operand_base
->size
;
5323 for (uval
= 0; uval
< num_vals
; uval
++)
5324 if (operand
->int_map
[uval
] == sval
)
5326 if (uval
== num_vals
)
5328 match_out_of_range (arg
);
5332 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5336 /* OP_MSB matcher. */
5339 match_msb_operand (struct mips_arg_info
*arg
,
5340 const struct mips_operand
*operand_base
)
5342 const struct mips_msb_operand
*operand
;
5343 int min_val
, max_val
, max_high
;
5344 offsetT size
, sval
, high
;
5346 operand
= (const struct mips_msb_operand
*) operand_base
;
5347 min_val
= operand
->bias
;
5348 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5349 max_high
= operand
->opsize
;
5351 if (!match_const_int (arg
, &size
))
5354 high
= size
+ arg
->last_op_int
;
5355 sval
= operand
->add_lsb
? high
: size
;
5357 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5359 match_out_of_range (arg
);
5362 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5366 /* OP_REG matcher. */
5369 match_reg_operand (struct mips_arg_info
*arg
,
5370 const struct mips_operand
*operand_base
)
5372 const struct mips_reg_operand
*operand
;
5373 unsigned int regno
, uval
, num_vals
;
5375 operand
= (const struct mips_reg_operand
*) operand_base
;
5376 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5379 if (operand
->reg_map
)
5381 num_vals
= 1 << operand
->root
.size
;
5382 for (uval
= 0; uval
< num_vals
; uval
++)
5383 if (operand
->reg_map
[uval
] == regno
)
5385 if (num_vals
== uval
)
5391 arg
->last_regno
= regno
;
5392 if (arg
->opnum
== 1)
5393 arg
->dest_regno
= regno
;
5394 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5398 /* OP_REG_PAIR matcher. */
5401 match_reg_pair_operand (struct mips_arg_info
*arg
,
5402 const struct mips_operand
*operand_base
)
5404 const struct mips_reg_pair_operand
*operand
;
5405 unsigned int regno1
, regno2
, uval
, num_vals
;
5407 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5408 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5409 || !match_char (arg
, ',')
5410 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5413 num_vals
= 1 << operand_base
->size
;
5414 for (uval
= 0; uval
< num_vals
; uval
++)
5415 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5417 if (uval
== num_vals
)
5420 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5424 /* OP_PCREL matcher. The caller chooses the relocation type. */
5427 match_pcrel_operand (struct mips_arg_info
*arg
)
5429 bfd_reloc_code_real_type r
[3];
5431 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5434 /* OP_PERF_REG matcher. */
5437 match_perf_reg_operand (struct mips_arg_info
*arg
,
5438 const struct mips_operand
*operand
)
5442 if (!match_const_int (arg
, &sval
))
5447 || (mips_opts
.arch
== CPU_R5900
5448 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5449 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5451 set_insn_error (arg
->argnum
, _("invalid performance register"));
5455 insn_insert_operand (arg
->insn
, operand
, sval
);
5459 /* OP_ADDIUSP matcher. */
5462 match_addiusp_operand (struct mips_arg_info
*arg
,
5463 const struct mips_operand
*operand
)
5468 if (!match_const_int (arg
, &sval
))
5473 match_out_of_range (arg
);
5478 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5480 match_out_of_range (arg
);
5484 uval
= (unsigned int) sval
;
5485 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5486 insn_insert_operand (arg
->insn
, operand
, uval
);
5490 /* OP_CLO_CLZ_DEST matcher. */
5493 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5494 const struct mips_operand
*operand
)
5498 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5501 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5505 /* OP_CHECK_PREV matcher. */
5508 match_check_prev_operand (struct mips_arg_info
*arg
,
5509 const struct mips_operand
*operand_base
)
5511 const struct mips_check_prev_operand
*operand
;
5514 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5516 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5519 if (!operand
->zero_ok
&& regno
== 0)
5522 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5523 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5524 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5526 arg
->last_regno
= regno
;
5527 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5534 /* OP_SAME_RS_RT matcher. */
5537 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5538 const struct mips_operand
*operand
)
5542 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5547 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5551 arg
->last_regno
= regno
;
5553 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5557 /* OP_LWM_SWM_LIST matcher. */
5560 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5561 const struct mips_operand
*operand
)
5563 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5564 struct mips_arg_info reset
;
5567 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5571 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5576 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5579 while (match_char (arg
, ',')
5580 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5583 if (operand
->size
== 2)
5585 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5591 and any permutations of these. */
5592 if ((reglist
& 0xfff1ffff) != 0x80010000)
5595 sregs
= (reglist
>> 17) & 7;
5600 /* The list must include at least one of ra and s0-sN,
5601 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5602 which are $23 and $30 respectively.) E.g.:
5610 and any permutations of these. */
5611 if ((reglist
& 0x3f00ffff) != 0)
5614 ra
= (reglist
>> 27) & 0x10;
5615 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5618 if ((sregs
& -sregs
) != sregs
)
5621 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5625 /* OP_ENTRY_EXIT_LIST matcher. */
5628 match_entry_exit_operand (struct mips_arg_info
*arg
,
5629 const struct mips_operand
*operand
)
5632 bfd_boolean is_exit
;
5634 /* The format is the same for both ENTRY and EXIT, but the constraints
5636 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5637 mask
= (is_exit
? 7 << 3 : 0);
5640 unsigned int regno1
, regno2
;
5641 bfd_boolean is_freg
;
5643 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5645 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5650 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5653 mask
|= (5 + regno2
) << 3;
5655 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5656 mask
|= (regno2
- 3) << 3;
5657 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5658 mask
|= (regno2
- 15) << 1;
5659 else if (regno1
== RA
&& regno2
== RA
)
5664 while (match_char (arg
, ','));
5666 insn_insert_operand (arg
->insn
, operand
, mask
);
5670 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5671 the argument register mask AMASK, the number of static registers
5672 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5673 respectively, and the frame size FRAME_SIZE. */
5676 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5677 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5678 unsigned int frame_size
)
5680 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5681 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5684 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5685 argument register mask AMASK, the number of static registers saved
5686 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5687 respectively, and the frame size FRAME_SIZE. */
5690 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5691 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5692 unsigned int frame_size
)
5696 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5697 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5698 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5699 | ((frame_size
& 0xf0) << 16));
5703 /* OP_SAVE_RESTORE_LIST matcher. */
5706 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5708 unsigned int opcode
, args
, statics
, sregs
;
5709 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5710 unsigned int arg_mask
, ra
, s0
, s1
;
5713 opcode
= arg
->insn
->insn_opcode
;
5715 num_frame_sizes
= 0;
5724 unsigned int regno1
, regno2
;
5726 if (arg
->token
->type
== OT_INTEGER
)
5728 /* Handle the frame size. */
5729 if (!match_const_int (arg
, &frame_size
))
5731 num_frame_sizes
+= 1;
5735 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5738 while (regno1
<= regno2
)
5740 if (regno1
>= 4 && regno1
<= 7)
5742 if (num_frame_sizes
== 0)
5744 args
|= 1 << (regno1
- 4);
5746 /* statics $a0-$a3 */
5747 statics
|= 1 << (regno1
- 4);
5749 else if (regno1
>= 16 && regno1
<= 23)
5751 sregs
|= 1 << (regno1
- 16);
5752 else if (regno1
== 30)
5755 else if (regno1
== 31)
5756 /* Add $ra to insn. */
5766 while (match_char (arg
, ','));
5768 /* Encode args/statics combination. */
5771 else if (args
== 0xf)
5772 /* All $a0-$a3 are args. */
5773 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5774 else if (statics
== 0xf)
5775 /* All $a0-$a3 are statics. */
5776 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5779 /* Count arg registers. */
5789 /* Count static registers. */
5791 while (statics
& 0x8)
5793 statics
= (statics
<< 1) & 0xf;
5799 /* Encode args/statics. */
5800 arg_mask
= (num_args
<< 2) | num_statics
;
5803 /* Encode $s0/$s1. */
5804 if (sregs
& (1 << 0)) /* $s0 */
5806 if (sregs
& (1 << 1)) /* $s1 */
5810 /* Encode $s2-$s8. */
5820 /* Encode frame size. */
5821 if (num_frame_sizes
== 0)
5823 set_insn_error (arg
->argnum
, _("missing frame size"));
5826 if (num_frame_sizes
> 1)
5828 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5831 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5833 set_insn_error (arg
->argnum
, _("invalid frame size"));
5838 /* Finally build the instruction. */
5839 if (mips_opts
.mips16
)
5840 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5842 else if (!mips_opts
.micromips
)
5843 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5848 arg
->insn
->insn_opcode
= opcode
;
5852 /* OP_MDMX_IMM_REG matcher. */
5855 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5856 const struct mips_operand
*operand
)
5858 unsigned int regno
, uval
;
5860 const struct mips_opcode
*opcode
;
5862 /* The mips_opcode records whether this is an octobyte or quadhalf
5863 instruction. Start out with that bit in place. */
5864 opcode
= arg
->insn
->insn_mo
;
5865 uval
= mips_extract_operand (operand
, opcode
->match
);
5866 is_qh
= (uval
!= 0);
5868 if (arg
->token
->type
== OT_REG
)
5870 if ((opcode
->membership
& INSN_5400
)
5871 && strcmp (opcode
->name
, "rzu.ob") == 0)
5873 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5878 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5882 /* Check whether this is a vector register or a broadcast of
5883 a single element. */
5884 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5886 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5888 set_insn_error (arg
->argnum
, _("invalid element selector"));
5891 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5896 /* A full vector. */
5897 if ((opcode
->membership
& INSN_5400
)
5898 && (strcmp (opcode
->name
, "sll.ob") == 0
5899 || strcmp (opcode
->name
, "srl.ob") == 0))
5901 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5907 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5909 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5917 if (!match_const_int (arg
, &sval
))
5919 if (sval
< 0 || sval
> 31)
5921 match_out_of_range (arg
);
5924 uval
|= (sval
& 31);
5926 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5928 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5930 insn_insert_operand (arg
->insn
, operand
, uval
);
5934 /* OP_IMM_INDEX matcher. */
5937 match_imm_index_operand (struct mips_arg_info
*arg
,
5938 const struct mips_operand
*operand
)
5940 unsigned int max_val
;
5942 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5945 max_val
= (1 << operand
->size
) - 1;
5946 if (arg
->token
->u
.index
> max_val
)
5948 match_out_of_range (arg
);
5951 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5956 /* OP_REG_INDEX matcher. */
5959 match_reg_index_operand (struct mips_arg_info
*arg
,
5960 const struct mips_operand
*operand
)
5964 if (arg
->token
->type
!= OT_REG_INDEX
)
5967 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5970 insn_insert_operand (arg
->insn
, operand
, regno
);
5975 /* OP_PC matcher. */
5978 match_pc_operand (struct mips_arg_info
*arg
)
5980 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5988 /* OP_REG28 matcher. */
5991 match_reg28_operand (struct mips_arg_info
*arg
)
5995 if (arg
->token
->type
== OT_REG
5996 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
6005 /* OP_NON_ZERO_REG matcher. */
6008 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6009 const struct mips_operand
*operand
)
6013 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6018 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
6022 arg
->last_regno
= regno
;
6023 insn_insert_operand (arg
->insn
, operand
, regno
);
6027 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6028 register that we need to match. */
6031 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6035 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6038 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6039 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6040 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6042 Return the constant in IMM and OFFSET as follows:
6044 - If the constant should be loaded via memory, set IMM to O_absent and
6045 OFFSET to the memory address.
6047 - Otherwise, if the constant should be loaded into two 32-bit registers,
6048 set IMM to the O_constant to load into the high register and OFFSET
6049 to the corresponding value for the low register.
6051 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6053 These constants only appear as the last operand in an instruction,
6054 and every instruction that accepts them in any variant accepts them
6055 in all variants. This means we don't have to worry about backing out
6056 any changes if the instruction does not match. We just match
6057 unconditionally and report an error if the constant is invalid. */
6060 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6061 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6066 const char *newname
;
6067 unsigned char *data
;
6069 /* Where the constant is placed is based on how the MIPS assembler
6072 length == 4 && using_gprs -- immediate value only
6073 length == 8 && using_gprs -- .rdata or immediate value
6074 length == 4 && !using_gprs -- .lit4 or immediate value
6075 length == 8 && !using_gprs -- .lit8 or immediate value
6077 The .lit4 and .lit8 sections are only used if permitted by the
6079 if (arg
->token
->type
!= OT_FLOAT
)
6081 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6085 gas_assert (arg
->token
->u
.flt
.length
== length
);
6086 data
= arg
->token
->u
.flt
.data
;
6089 /* Handle 32-bit constants for which an immediate value is best. */
6092 || g_switch_value
< 4
6093 || (data
[0] == 0 && data
[1] == 0)
6094 || (data
[2] == 0 && data
[3] == 0)))
6096 imm
->X_op
= O_constant
;
6097 if (!target_big_endian
)
6098 imm
->X_add_number
= bfd_getl32 (data
);
6100 imm
->X_add_number
= bfd_getb32 (data
);
6101 offset
->X_op
= O_absent
;
6105 /* Handle 64-bit constants for which an immediate value is best. */
6107 && !mips_disable_float_construction
6108 /* Constants can only be constructed in GPRs and copied to FPRs if the
6109 GPRs are at least as wide as the FPRs or MTHC1 is available.
6110 Unlike most tests for 32-bit floating-point registers this check
6111 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6112 permit 64-bit moves without MXHC1.
6113 Force the constant into memory otherwise. */
6116 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6118 && ((data
[0] == 0 && data
[1] == 0)
6119 || (data
[2] == 0 && data
[3] == 0))
6120 && ((data
[4] == 0 && data
[5] == 0)
6121 || (data
[6] == 0 && data
[7] == 0)))
6123 /* The value is simple enough to load with a couple of instructions.
6124 If using 32-bit registers, set IMM to the high order 32 bits and
6125 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6127 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6129 imm
->X_op
= O_constant
;
6130 offset
->X_op
= O_constant
;
6131 if (!target_big_endian
)
6133 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6134 offset
->X_add_number
= bfd_getl32 (data
);
6138 imm
->X_add_number
= bfd_getb32 (data
);
6139 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6141 if (offset
->X_add_number
== 0)
6142 offset
->X_op
= O_absent
;
6146 imm
->X_op
= O_constant
;
6147 if (!target_big_endian
)
6148 imm
->X_add_number
= bfd_getl64 (data
);
6150 imm
->X_add_number
= bfd_getb64 (data
);
6151 offset
->X_op
= O_absent
;
6156 /* Switch to the right section. */
6158 subseg
= now_subseg
;
6161 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6166 if (using_gprs
|| g_switch_value
< 8)
6167 newname
= RDATA_SECTION_NAME
;
6172 new_seg
= subseg_new (newname
, (subsegT
) 0);
6173 bfd_set_section_flags (stdoutput
, new_seg
,
6174 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6175 frag_align (length
== 4 ? 2 : 3, 0, 0);
6176 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6177 record_alignment (new_seg
, 4);
6179 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6181 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6183 /* Set the argument to the current address in the section. */
6184 imm
->X_op
= O_absent
;
6185 offset
->X_op
= O_symbol
;
6186 offset
->X_add_symbol
= symbol_temp_new_now ();
6187 offset
->X_add_number
= 0;
6189 /* Put the floating point number into the section. */
6190 p
= frag_more (length
);
6191 memcpy (p
, data
, length
);
6193 /* Switch back to the original section. */
6194 subseg_set (seg
, subseg
);
6198 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6202 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6203 const struct mips_operand
*operand
,
6204 bfd_boolean match_p
)
6208 /* The operand can be an XYZW mask or a single 2-bit channel index
6209 (with X being 0). */
6210 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6212 /* The suffix can be omitted when it is already part of the opcode. */
6213 if (arg
->token
->type
!= OT_CHANNELS
)
6216 uval
= arg
->token
->u
.channels
;
6217 if (operand
->size
== 2)
6219 /* Check that a single bit is set and convert it into a 2-bit index. */
6220 if ((uval
& -uval
) != uval
)
6222 uval
= 4 - ffs (uval
);
6225 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6230 insn_insert_operand (arg
->insn
, operand
, uval
);
6234 /* Try to match a token from ARG against OPERAND. Consume the token
6235 and return true on success, otherwise return false. */
6238 match_operand (struct mips_arg_info
*arg
,
6239 const struct mips_operand
*operand
)
6241 switch (operand
->type
)
6244 return match_int_operand (arg
, operand
);
6247 return match_mapped_int_operand (arg
, operand
);
6250 return match_msb_operand (arg
, operand
);
6253 case OP_OPTIONAL_REG
:
6254 return match_reg_operand (arg
, operand
);
6257 return match_reg_pair_operand (arg
, operand
);
6260 return match_pcrel_operand (arg
);
6263 return match_perf_reg_operand (arg
, operand
);
6265 case OP_ADDIUSP_INT
:
6266 return match_addiusp_operand (arg
, operand
);
6268 case OP_CLO_CLZ_DEST
:
6269 return match_clo_clz_dest_operand (arg
, operand
);
6271 case OP_LWM_SWM_LIST
:
6272 return match_lwm_swm_list_operand (arg
, operand
);
6274 case OP_ENTRY_EXIT_LIST
:
6275 return match_entry_exit_operand (arg
, operand
);
6277 case OP_SAVE_RESTORE_LIST
:
6278 return match_save_restore_list_operand (arg
);
6280 case OP_MDMX_IMM_REG
:
6281 return match_mdmx_imm_reg_operand (arg
, operand
);
6283 case OP_REPEAT_DEST_REG
:
6284 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6286 case OP_REPEAT_PREV_REG
:
6287 return match_tied_reg_operand (arg
, arg
->last_regno
);
6290 return match_pc_operand (arg
);
6293 return match_reg28_operand (arg
);
6296 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6298 case OP_VU0_MATCH_SUFFIX
:
6299 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6302 return match_imm_index_operand (arg
, operand
);
6305 return match_reg_index_operand (arg
, operand
);
6308 return match_same_rs_rt_operand (arg
, operand
);
6311 return match_check_prev_operand (arg
, operand
);
6313 case OP_NON_ZERO_REG
:
6314 return match_non_zero_reg_operand (arg
, operand
);
6319 /* ARG is the state after successfully matching an instruction.
6320 Issue any queued-up warnings. */
6323 check_completed_insn (struct mips_arg_info
*arg
)
6328 as_warn (_("used $at without \".set noat\""));
6330 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6334 /* Return true if modifying general-purpose register REG needs a delay. */
6337 reg_needs_delay (unsigned int reg
)
6339 unsigned long prev_pinfo
;
6341 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6342 if (!mips_opts
.noreorder
6343 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6344 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6345 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6351 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6352 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6353 by VR4120 errata. */
6356 classify_vr4120_insn (const char *name
)
6358 if (strncmp (name
, "macc", 4) == 0)
6359 return FIX_VR4120_MACC
;
6360 if (strncmp (name
, "dmacc", 5) == 0)
6361 return FIX_VR4120_DMACC
;
6362 if (strncmp (name
, "mult", 4) == 0)
6363 return FIX_VR4120_MULT
;
6364 if (strncmp (name
, "dmult", 5) == 0)
6365 return FIX_VR4120_DMULT
;
6366 if (strstr (name
, "div"))
6367 return FIX_VR4120_DIV
;
6368 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6369 return FIX_VR4120_MTHILO
;
6370 return NUM_FIX_VR4120_CLASSES
;
6373 #define INSN_ERET 0x42000018
6374 #define INSN_DERET 0x4200001f
6375 #define INSN_DMULT 0x1c
6376 #define INSN_DMULTU 0x1d
6378 /* Return the number of instructions that must separate INSN1 and INSN2,
6379 where INSN1 is the earlier instruction. Return the worst-case value
6380 for any INSN2 if INSN2 is null. */
6383 insns_between (const struct mips_cl_insn
*insn1
,
6384 const struct mips_cl_insn
*insn2
)
6386 unsigned long pinfo1
, pinfo2
;
6389 /* If INFO2 is null, pessimistically assume that all flags are set for
6390 the second instruction. */
6391 pinfo1
= insn1
->insn_mo
->pinfo
;
6392 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6394 /* For most targets, write-after-read dependencies on the HI and LO
6395 registers must be separated by at least two instructions. */
6396 if (!hilo_interlocks
)
6398 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6400 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6404 /* If we're working around r7000 errata, there must be two instructions
6405 between an mfhi or mflo and any instruction that uses the result. */
6406 if (mips_7000_hilo_fix
6407 && !mips_opts
.micromips
6408 && MF_HILO_INSN (pinfo1
)
6409 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6412 /* If we're working around 24K errata, one instruction is required
6413 if an ERET or DERET is followed by a branch instruction. */
6414 if (mips_fix_24k
&& !mips_opts
.micromips
)
6416 if (insn1
->insn_opcode
== INSN_ERET
6417 || insn1
->insn_opcode
== INSN_DERET
)
6420 || insn2
->insn_opcode
== INSN_ERET
6421 || insn2
->insn_opcode
== INSN_DERET
6422 || delayed_branch_p (insn2
))
6427 /* If we're working around PMC RM7000 errata, there must be three
6428 nops between a dmult and a load instruction. */
6429 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6431 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6432 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6434 if (pinfo2
& INSN_LOAD_MEMORY
)
6439 /* If working around VR4120 errata, check for combinations that need
6440 a single intervening instruction. */
6441 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6443 unsigned int class1
, class2
;
6445 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6446 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6450 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6451 if (vr4120_conflicts
[class1
] & (1 << class2
))
6456 if (!HAVE_CODE_COMPRESSION
)
6458 /* Check for GPR or coprocessor load delays. All such delays
6459 are on the RT register. */
6460 /* Itbl support may require additional care here. */
6461 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6462 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6464 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6468 /* Check for generic coprocessor hazards.
6470 This case is not handled very well. There is no special
6471 knowledge of CP0 handling, and the coprocessors other than
6472 the floating point unit are not distinguished at all. */
6473 /* Itbl support may require additional care here. FIXME!
6474 Need to modify this to include knowledge about
6475 user specified delays! */
6476 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6477 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6479 /* Handle cases where INSN1 writes to a known general coprocessor
6480 register. There must be a one instruction delay before INSN2
6481 if INSN2 reads that register, otherwise no delay is needed. */
6482 mask
= fpr_write_mask (insn1
);
6485 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6490 /* Read-after-write dependencies on the control registers
6491 require a two-instruction gap. */
6492 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6493 && (pinfo2
& INSN_READ_COND_CODE
))
6496 /* We don't know exactly what INSN1 does. If INSN2 is
6497 also a coprocessor instruction, assume there must be
6498 a one instruction gap. */
6499 if (pinfo2
& INSN_COP
)
6504 /* Check for read-after-write dependencies on the coprocessor
6505 control registers in cases where INSN1 does not need a general
6506 coprocessor delay. This means that INSN1 is a floating point
6507 comparison instruction. */
6508 /* Itbl support may require additional care here. */
6509 else if (!cop_interlocks
6510 && (pinfo1
& INSN_WRITE_COND_CODE
)
6511 && (pinfo2
& INSN_READ_COND_CODE
))
6515 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6516 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6518 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6519 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6520 || (insn2
&& delayed_branch_p (insn2
))))
6526 /* Return the number of nops that would be needed to work around the
6527 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6528 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6529 that are contained within the first IGNORE instructions of HIST. */
6532 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6533 const struct mips_cl_insn
*insn
)
6538 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6539 are not affected by the errata. */
6541 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6542 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6543 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6546 /* Search for the first MFLO or MFHI. */
6547 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6548 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6550 /* Extract the destination register. */
6551 mask
= gpr_write_mask (&hist
[i
]);
6553 /* No nops are needed if INSN reads that register. */
6554 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6557 /* ...or if any of the intervening instructions do. */
6558 for (j
= 0; j
< i
; j
++)
6559 if (gpr_read_mask (&hist
[j
]) & mask
)
6563 return MAX_VR4130_NOPS
- i
;
6568 #define BASE_REG_EQ(INSN1, INSN2) \
6569 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6570 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6572 /* Return the minimum alignment for this store instruction. */
6575 fix_24k_align_to (const struct mips_opcode
*mo
)
6577 if (strcmp (mo
->name
, "sh") == 0)
6580 if (strcmp (mo
->name
, "swc1") == 0
6581 || strcmp (mo
->name
, "swc2") == 0
6582 || strcmp (mo
->name
, "sw") == 0
6583 || strcmp (mo
->name
, "sc") == 0
6584 || strcmp (mo
->name
, "s.s") == 0)
6587 if (strcmp (mo
->name
, "sdc1") == 0
6588 || strcmp (mo
->name
, "sdc2") == 0
6589 || strcmp (mo
->name
, "s.d") == 0)
6596 struct fix_24k_store_info
6598 /* Immediate offset, if any, for this store instruction. */
6600 /* Alignment required by this store instruction. */
6602 /* True for register offsets. */
6603 int register_offset
;
6606 /* Comparison function used by qsort. */
6609 fix_24k_sort (const void *a
, const void *b
)
6611 const struct fix_24k_store_info
*pos1
= a
;
6612 const struct fix_24k_store_info
*pos2
= b
;
6614 return (pos1
->off
- pos2
->off
);
6617 /* INSN is a store instruction. Try to record the store information
6618 in STINFO. Return false if the information isn't known. */
6621 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6622 const struct mips_cl_insn
*insn
)
6624 /* The instruction must have a known offset. */
6625 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6628 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6629 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6633 /* Return the number of nops that would be needed to work around the 24k
6634 "lost data on stores during refill" errata if instruction INSN
6635 immediately followed the 2 instructions described by HIST.
6636 Ignore hazards that are contained within the first IGNORE
6637 instructions of HIST.
6639 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6640 for the data cache refills and store data. The following describes
6641 the scenario where the store data could be lost.
6643 * A data cache miss, due to either a load or a store, causing fill
6644 data to be supplied by the memory subsystem
6645 * The first three doublewords of fill data are returned and written
6647 * A sequence of four stores occurs in consecutive cycles around the
6648 final doubleword of the fill:
6652 * Zero, One or more instructions
6655 The four stores A-D must be to different doublewords of the line that
6656 is being filled. The fourth instruction in the sequence above permits
6657 the fill of the final doubleword to be transferred from the FSB into
6658 the cache. In the sequence above, the stores may be either integer
6659 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6660 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6661 different doublewords on the line. If the floating point unit is
6662 running in 1:2 mode, it is not possible to create the sequence above
6663 using only floating point store instructions.
6665 In this case, the cache line being filled is incorrectly marked
6666 invalid, thereby losing the data from any store to the line that
6667 occurs between the original miss and the completion of the five
6668 cycle sequence shown above.
6670 The workarounds are:
6672 * Run the data cache in write-through mode.
6673 * Insert a non-store instruction between
6674 Store A and Store B or Store B and Store C. */
6677 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6678 const struct mips_cl_insn
*insn
)
6680 struct fix_24k_store_info pos
[3];
6681 int align
, i
, base_offset
;
6686 /* If the previous instruction wasn't a store, there's nothing to
6688 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6691 /* If the instructions after the previous one are unknown, we have
6692 to assume the worst. */
6696 /* Check whether we are dealing with three consecutive stores. */
6697 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6698 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6701 /* If we don't know the relationship between the store addresses,
6702 assume the worst. */
6703 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6704 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6707 if (!fix_24k_record_store_info (&pos
[0], insn
)
6708 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6709 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6712 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6714 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6715 X bytes and such that the base register + X is known to be aligned
6718 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6722 align
= pos
[0].align_to
;
6723 base_offset
= pos
[0].off
;
6724 for (i
= 1; i
< 3; i
++)
6725 if (align
< pos
[i
].align_to
)
6727 align
= pos
[i
].align_to
;
6728 base_offset
= pos
[i
].off
;
6730 for (i
= 0; i
< 3; i
++)
6731 pos
[i
].off
-= base_offset
;
6734 pos
[0].off
&= ~align
+ 1;
6735 pos
[1].off
&= ~align
+ 1;
6736 pos
[2].off
&= ~align
+ 1;
6738 /* If any two stores write to the same chunk, they also write to the
6739 same doubleword. The offsets are still sorted at this point. */
6740 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6743 /* A range of at least 9 bytes is needed for the stores to be in
6744 non-overlapping doublewords. */
6745 if (pos
[2].off
- pos
[0].off
<= 8)
6748 if (pos
[2].off
- pos
[1].off
>= 24
6749 || pos
[1].off
- pos
[0].off
>= 24
6750 || pos
[2].off
- pos
[0].off
>= 32)
6756 /* Return the number of nops that would be needed if instruction INSN
6757 immediately followed the MAX_NOPS instructions given by HIST,
6758 where HIST[0] is the most recent instruction. Ignore hazards
6759 between INSN and the first IGNORE instructions in HIST.
6761 If INSN is null, return the worse-case number of nops for any
6765 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6766 const struct mips_cl_insn
*insn
)
6768 int i
, nops
, tmp_nops
;
6771 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6773 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6774 if (tmp_nops
> nops
)
6778 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6780 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6781 if (tmp_nops
> nops
)
6785 if (mips_fix_24k
&& !mips_opts
.micromips
)
6787 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6788 if (tmp_nops
> nops
)
6795 /* The variable arguments provide NUM_INSNS extra instructions that
6796 might be added to HIST. Return the largest number of nops that
6797 would be needed after the extended sequence, ignoring hazards
6798 in the first IGNORE instructions. */
6801 nops_for_sequence (int num_insns
, int ignore
,
6802 const struct mips_cl_insn
*hist
, ...)
6805 struct mips_cl_insn buffer
[MAX_NOPS
];
6806 struct mips_cl_insn
*cursor
;
6809 va_start (args
, hist
);
6810 cursor
= buffer
+ num_insns
;
6811 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6812 while (cursor
> buffer
)
6813 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6815 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6820 /* Like nops_for_insn, but if INSN is a branch, take into account the
6821 worst-case delay for the branch target. */
6824 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6825 const struct mips_cl_insn
*insn
)
6829 nops
= nops_for_insn (ignore
, hist
, insn
);
6830 if (delayed_branch_p (insn
))
6832 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6833 hist
, insn
, get_delay_slot_nop (insn
));
6834 if (tmp_nops
> nops
)
6837 else if (compact_branch_p (insn
))
6839 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6840 if (tmp_nops
> nops
)
6846 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6849 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6851 gas_assert (!HAVE_CODE_COMPRESSION
);
6852 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6853 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6856 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6857 jr target pc &= 'hffff_ffff_cfff_ffff. */
6860 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6862 gas_assert (!HAVE_CODE_COMPRESSION
);
6863 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6864 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6865 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6873 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6874 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6877 ep
.X_op
= O_constant
;
6878 ep
.X_add_number
= 0xcfff0000;
6879 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6880 ep
.X_add_number
= 0xffff;
6881 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6882 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6887 fix_loongson2f (struct mips_cl_insn
* ip
)
6889 if (mips_fix_loongson2f_nop
)
6890 fix_loongson2f_nop (ip
);
6892 if (mips_fix_loongson2f_jump
)
6893 fix_loongson2f_jump (ip
);
6896 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6899 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6901 gas_assert (!HAVE_CODE_COMPRESSION
);
6903 /* If is an local label and the insn is not sync,
6904 look forward that whether an branch between ll/sc jump to here
6905 if so, insert a sync. */
6906 if (seg_info (now_seg
)->label_list
6907 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6908 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6910 const char *label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6911 unsigned long lookback
= ARRAY_SIZE (history
);
6914 for (i
= 0; i
< lookback
; i
++)
6916 if (streq (history
[i
].insn_mo
->name
, "ll")
6917 || streq (history
[i
].insn_mo
->name
, "lld"))
6920 if (streq (history
[i
].insn_mo
->name
, "sc")
6921 || streq (history
[i
].insn_mo
->name
, "scd"))
6925 for (j
= i
+ 1; j
< lookback
; j
++)
6927 if (streq (history
[i
].insn_mo
->name
, "ll")
6928 || streq (history
[i
].insn_mo
->name
, "lld"))
6931 if (delayed_branch_p (&history
[j
]))
6933 if (streq (history
[j
].target
, label_name
))
6935 add_fixed_insn (&sync_insn
);
6936 insert_into_history (0, 1, &sync_insn
);
6945 /* If we find a sc, we look forward to look for an branch insn,
6946 and see whether it jump back and out of ll/sc. */
6947 else if (streq(ip
->insn_mo
->name
, "sc") || streq(ip
->insn_mo
->name
, "scd"))
6949 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6952 for (i
= 0; i
< lookback
; i
++)
6954 if (streq (history
[i
].insn_mo
->name
, "ll")
6955 || streq (history
[i
].insn_mo
->name
, "lld"))
6958 if (delayed_branch_p (&history
[i
]))
6962 for (j
= i
+ 1; j
< lookback
; j
++)
6964 if (streq (history
[j
].insn_mo
->name
, "ll")
6965 || streq (history
[i
].insn_mo
->name
, "lld"))
6969 for (; j
< lookback
; j
++)
6971 if (history
[j
].label
[0] != '\0'
6972 && streq (history
[j
].label
, history
[i
].target
)
6973 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
6975 add_fixed_insn (&sync_insn
);
6976 insert_into_history (++j
, 1, &sync_insn
);
6983 /* Skip if there is a sync before ll/lld. */
6984 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
6985 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
6986 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
6988 add_fixed_insn (&sync_insn
);
6989 insert_into_history (0, 1, &sync_insn
);
6993 /* IP is a branch that has a delay slot, and we need to fill it
6994 automatically. Return true if we can do that by swapping IP
6995 with the previous instruction.
6996 ADDRESS_EXPR is an operand of the instruction to be used with
7000 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7001 bfd_reloc_code_real_type
*reloc_type
)
7003 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7004 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7005 unsigned int fpr_read
, prev_fpr_write
;
7007 /* -O2 and above is required for this optimization. */
7008 if (mips_optimize
< 2)
7011 /* If we have seen .set volatile or .set nomove, don't optimize. */
7012 if (mips_opts
.nomove
)
7015 /* We can't swap if the previous instruction's position is fixed. */
7016 if (history
[0].fixed_p
)
7019 /* If the previous previous insn was in a .set noreorder, we can't
7020 swap. Actually, the MIPS assembler will swap in this situation.
7021 However, gcc configured -with-gnu-as will generate code like
7029 in which we can not swap the bne and INSN. If gcc is not configured
7030 -with-gnu-as, it does not output the .set pseudo-ops. */
7031 if (history
[1].noreorder_p
)
7034 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7035 This means that the previous instruction was a 4-byte one anyhow. */
7036 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7039 /* If the branch is itself the target of a branch, we can not swap.
7040 We cheat on this; all we check for is whether there is a label on
7041 this instruction. If there are any branches to anything other than
7042 a label, users must use .set noreorder. */
7043 if (seg_info (now_seg
)->label_list
)
7046 /* If the previous instruction is in a variant frag other than this
7047 branch's one, we cannot do the swap. This does not apply to
7048 MIPS16 code, which uses variant frags for different purposes. */
7049 if (!mips_opts
.mips16
7051 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7054 /* We do not swap with instructions that cannot architecturally
7055 be placed in a branch delay slot, such as SYNC or ERET. We
7056 also refrain from swapping with a trap instruction, since it
7057 complicates trap handlers to have the trap instruction be in
7059 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7060 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7063 /* Check for conflicts between the branch and the instructions
7064 before the candidate delay slot. */
7065 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7068 /* Check for conflicts between the swapped sequence and the
7069 target of the branch. */
7070 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7073 /* If the branch reads a register that the previous
7074 instruction sets, we can not swap. */
7075 gpr_read
= gpr_read_mask (ip
);
7076 prev_gpr_write
= gpr_write_mask (&history
[0]);
7077 if (gpr_read
& prev_gpr_write
)
7080 fpr_read
= fpr_read_mask (ip
);
7081 prev_fpr_write
= fpr_write_mask (&history
[0]);
7082 if (fpr_read
& prev_fpr_write
)
7085 /* If the branch writes a register that the previous
7086 instruction sets, we can not swap. */
7087 gpr_write
= gpr_write_mask (ip
);
7088 if (gpr_write
& prev_gpr_write
)
7091 /* If the branch writes a register that the previous
7092 instruction reads, we can not swap. */
7093 prev_gpr_read
= gpr_read_mask (&history
[0]);
7094 if (gpr_write
& prev_gpr_read
)
7097 /* If one instruction sets a condition code and the
7098 other one uses a condition code, we can not swap. */
7099 pinfo
= ip
->insn_mo
->pinfo
;
7100 if ((pinfo
& INSN_READ_COND_CODE
)
7101 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7103 if ((pinfo
& INSN_WRITE_COND_CODE
)
7104 && (prev_pinfo
& INSN_READ_COND_CODE
))
7107 /* If the previous instruction uses the PC, we can not swap. */
7108 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7109 if (prev_pinfo2
& INSN2_READ_PC
)
7112 /* If the previous instruction has an incorrect size for a fixed
7113 branch delay slot in microMIPS mode, we cannot swap. */
7114 pinfo2
= ip
->insn_mo
->pinfo2
;
7115 if (mips_opts
.micromips
7116 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7117 && insn_length (history
) != 2)
7119 if (mips_opts
.micromips
7120 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7121 && insn_length (history
) != 4)
7124 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7127 The short loop bug under certain conditions causes loops to execute
7128 only once or twice. We must ensure that the assembler never
7129 generates loops that satisfy all of the following conditions:
7131 - a loop consists of less than or equal to six instructions
7132 (including the branch delay slot);
7133 - a loop contains only one conditional branch instruction at the end
7135 - a loop does not contain any other branch or jump instructions;
7136 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7138 We need to do this because of a hardware bug in the R5900 chip. */
7140 /* Check if instruction has a parameter, ignore "j $31". */
7141 && (address_expr
!= NULL
)
7142 /* Parameter must be 16 bit. */
7143 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7144 /* Branch to same segment. */
7145 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7146 /* Branch to same code fragment. */
7147 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7148 /* Can only calculate branch offset if value is known. */
7149 && symbol_constant_p (address_expr
->X_add_symbol
)
7150 /* Check if branch is really conditional. */
7151 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7152 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7153 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7156 /* Check if loop is shorter than or equal to 6 instructions
7157 including branch and delay slot. */
7158 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7165 /* When the loop includes branches or jumps,
7166 it is not a short loop. */
7167 for (i
= 0; i
< (distance
/ 4); i
++)
7169 if ((history
[i
].cleared_p
)
7170 || delayed_branch_p (&history
[i
]))
7178 /* Insert nop after branch to fix short loop. */
7187 /* Decide how we should add IP to the instruction stream.
7188 ADDRESS_EXPR is an operand of the instruction to be used with
7191 static enum append_method
7192 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7193 bfd_reloc_code_real_type
*reloc_type
)
7195 /* The relaxed version of a macro sequence must be inherently
7197 if (mips_relax
.sequence
== 2)
7200 /* We must not dabble with instructions in a ".set noreorder" block. */
7201 if (mips_opts
.noreorder
)
7204 /* Otherwise, it's our responsibility to fill branch delay slots. */
7205 if (delayed_branch_p (ip
))
7207 if (!branch_likely_p (ip
)
7208 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7211 if (mips_opts
.mips16
7212 && ISA_SUPPORTS_MIPS16E
7213 && gpr_read_mask (ip
) != 0)
7214 return APPEND_ADD_COMPACT
;
7216 if (mips_opts
.micromips
7217 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7218 || (!forced_insn_length
7219 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7220 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7221 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7222 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7223 return APPEND_ADD_COMPACT
;
7225 return APPEND_ADD_WITH_NOP
;
7231 /* IP is an instruction whose opcode we have just changed, END points
7232 to the end of the opcode table processed. Point IP->insn_mo to the
7233 new opcode's definition. */
7236 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7238 const struct mips_opcode
*mo
;
7240 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7241 if (mo
->pinfo
!= INSN_MACRO
7242 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7250 /* IP is a MIPS16 instruction whose opcode we have just changed.
7251 Point IP->insn_mo to the new opcode's definition. */
7254 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7256 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7259 /* IP is a microMIPS instruction whose opcode we have just changed.
7260 Point IP->insn_mo to the new opcode's definition. */
7263 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7265 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7268 /* For microMIPS macros, we need to generate a local number label
7269 as the target of branches. */
7270 #define MICROMIPS_LABEL_CHAR '\037'
7271 static unsigned long micromips_target_label
;
7272 static char micromips_target_name
[32];
7275 micromips_label_name (void)
7277 char *p
= micromips_target_name
;
7278 char symbol_name_temporary
[24];
7286 l
= micromips_target_label
;
7287 #ifdef LOCAL_LABEL_PREFIX
7288 *p
++ = LOCAL_LABEL_PREFIX
;
7291 *p
++ = MICROMIPS_LABEL_CHAR
;
7294 symbol_name_temporary
[i
++] = l
% 10 + '0';
7299 *p
++ = symbol_name_temporary
[--i
];
7302 return micromips_target_name
;
7306 micromips_label_expr (expressionS
*label_expr
)
7308 label_expr
->X_op
= O_symbol
;
7309 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7310 label_expr
->X_add_number
= 0;
7314 micromips_label_inc (void)
7316 micromips_target_label
++;
7317 *micromips_target_name
= '\0';
7321 micromips_add_label (void)
7325 s
= colon (micromips_label_name ());
7326 micromips_label_inc ();
7327 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7330 /* If assembling microMIPS code, then return the microMIPS reloc
7331 corresponding to the requested one if any. Otherwise return
7332 the reloc unchanged. */
7334 static bfd_reloc_code_real_type
7335 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7337 static const bfd_reloc_code_real_type relocs
[][2] =
7339 /* Keep sorted incrementally by the left-hand key. */
7340 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7341 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7342 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7343 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7344 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7345 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7346 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7347 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7348 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7349 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7350 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7351 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7352 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7353 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7354 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7355 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7356 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7357 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7358 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7359 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7360 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7361 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7362 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7363 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7364 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7365 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7366 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7368 bfd_reloc_code_real_type r
;
7371 if (!mips_opts
.micromips
)
7373 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7379 return relocs
[i
][1];
7384 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7385 Return true on success, storing the resolved value in RESULT. */
7388 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7393 case BFD_RELOC_MIPS_HIGHEST
:
7394 case BFD_RELOC_MICROMIPS_HIGHEST
:
7395 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7398 case BFD_RELOC_MIPS_HIGHER
:
7399 case BFD_RELOC_MICROMIPS_HIGHER
:
7400 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7403 case BFD_RELOC_HI16_S
:
7404 case BFD_RELOC_HI16_S_PCREL
:
7405 case BFD_RELOC_MICROMIPS_HI16_S
:
7406 case BFD_RELOC_MIPS16_HI16_S
:
7407 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7410 case BFD_RELOC_HI16
:
7411 case BFD_RELOC_MICROMIPS_HI16
:
7412 case BFD_RELOC_MIPS16_HI16
:
7413 *result
= (operand
>> 16) & 0xffff;
7416 case BFD_RELOC_LO16
:
7417 case BFD_RELOC_LO16_PCREL
:
7418 case BFD_RELOC_MICROMIPS_LO16
:
7419 case BFD_RELOC_MIPS16_LO16
:
7420 *result
= operand
& 0xffff;
7423 case BFD_RELOC_UNUSED
:
7432 /* Output an instruction. IP is the instruction information.
7433 ADDRESS_EXPR is an operand of the instruction to be used with
7434 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7435 a macro expansion. */
7438 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7439 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7441 unsigned long prev_pinfo2
, pinfo
;
7442 bfd_boolean relaxed_branch
= FALSE
;
7443 enum append_method method
;
7444 bfd_boolean relax32
;
7447 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7448 fix_loongson2f (ip
);
7450 ip
->target
[0] = '\0';
7451 if (offset_expr
.X_op
== O_symbol
)
7452 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7453 ip
->label
[0] = '\0';
7454 if (seg_info (now_seg
)->label_list
)
7455 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7456 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7457 fix_loongson3_llsc (ip
);
7459 file_ase_mips16
|= mips_opts
.mips16
;
7460 file_ase_micromips
|= mips_opts
.micromips
;
7462 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7463 pinfo
= ip
->insn_mo
->pinfo
;
7465 /* Don't raise alarm about `nods' frags as they'll fill in the right
7466 kind of nop in relaxation if required. */
7467 if (mips_opts
.micromips
7469 && !(history
[0].frag
7470 && history
[0].frag
->fr_type
== rs_machine_dependent
7471 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7472 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7473 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7474 && micromips_insn_length (ip
->insn_mo
) != 2)
7475 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7476 && micromips_insn_length (ip
->insn_mo
) != 4)))
7477 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7478 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7480 if (address_expr
== NULL
)
7482 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7483 && reloc_type
[1] == BFD_RELOC_UNUSED
7484 && reloc_type
[2] == BFD_RELOC_UNUSED
7485 && address_expr
->X_op
== O_constant
)
7487 switch (*reloc_type
)
7489 case BFD_RELOC_MIPS_JMP
:
7493 /* Shift is 2, unusually, for microMIPS JALX. */
7494 shift
= (mips_opts
.micromips
7495 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7496 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7497 as_bad (_("jump to misaligned address (0x%lx)"),
7498 (unsigned long) address_expr
->X_add_number
);
7499 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7505 case BFD_RELOC_MIPS16_JMP
:
7506 if ((address_expr
->X_add_number
& 3) != 0)
7507 as_bad (_("jump to misaligned address (0x%lx)"),
7508 (unsigned long) address_expr
->X_add_number
);
7510 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7511 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7512 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7516 case BFD_RELOC_16_PCREL_S2
:
7520 shift
= mips_opts
.micromips
? 1 : 2;
7521 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7522 as_bad (_("branch to misaligned address (0x%lx)"),
7523 (unsigned long) address_expr
->X_add_number
);
7524 if (!mips_relax_branch
)
7526 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7527 & ~((1 << (shift
+ 16)) - 1))
7528 as_bad (_("branch address range overflow (0x%lx)"),
7529 (unsigned long) address_expr
->X_add_number
);
7530 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7536 case BFD_RELOC_MIPS_21_PCREL_S2
:
7541 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7542 as_bad (_("branch to misaligned address (0x%lx)"),
7543 (unsigned long) address_expr
->X_add_number
);
7544 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7545 & ~((1 << (shift
+ 21)) - 1))
7546 as_bad (_("branch address range overflow (0x%lx)"),
7547 (unsigned long) address_expr
->X_add_number
);
7548 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7553 case BFD_RELOC_MIPS_26_PCREL_S2
:
7558 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7559 as_bad (_("branch to misaligned address (0x%lx)"),
7560 (unsigned long) address_expr
->X_add_number
);
7561 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7562 & ~((1 << (shift
+ 26)) - 1))
7563 as_bad (_("branch address range overflow (0x%lx)"),
7564 (unsigned long) address_expr
->X_add_number
);
7565 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7574 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7577 ip
->insn_opcode
|= value
& 0xffff;
7585 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7587 /* There are a lot of optimizations we could do that we don't.
7588 In particular, we do not, in general, reorder instructions.
7589 If you use gcc with optimization, it will reorder
7590 instructions and generally do much more optimization then we
7591 do here; repeating all that work in the assembler would only
7592 benefit hand written assembly code, and does not seem worth
7594 int nops
= (mips_optimize
== 0
7595 ? nops_for_insn (0, history
, NULL
)
7596 : nops_for_insn_or_target (0, history
, ip
));
7600 unsigned long old_frag_offset
;
7603 old_frag
= frag_now
;
7604 old_frag_offset
= frag_now_fix ();
7606 for (i
= 0; i
< nops
; i
++)
7607 add_fixed_insn (NOP_INSN
);
7608 insert_into_history (0, nops
, NOP_INSN
);
7612 listing_prev_line ();
7613 /* We may be at the start of a variant frag. In case we
7614 are, make sure there is enough space for the frag
7615 after the frags created by listing_prev_line. The
7616 argument to frag_grow here must be at least as large
7617 as the argument to all other calls to frag_grow in
7618 this file. We don't have to worry about being in the
7619 middle of a variant frag, because the variants insert
7620 all needed nop instructions themselves. */
7624 mips_move_text_labels ();
7626 #ifndef NO_ECOFF_DEBUGGING
7627 if (ECOFF_DEBUGGING
)
7628 ecoff_fix_loc (old_frag
, old_frag_offset
);
7632 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7636 /* Work out how many nops in prev_nop_frag are needed by IP,
7637 ignoring hazards generated by the first prev_nop_frag_since
7639 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7640 gas_assert (nops
<= prev_nop_frag_holds
);
7642 /* Enforce NOPS as a minimum. */
7643 if (nops
> prev_nop_frag_required
)
7644 prev_nop_frag_required
= nops
;
7646 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7648 /* Settle for the current number of nops. Update the history
7649 accordingly (for the benefit of any future .set reorder code). */
7650 prev_nop_frag
= NULL
;
7651 insert_into_history (prev_nop_frag_since
,
7652 prev_nop_frag_holds
, NOP_INSN
);
7656 /* Allow this instruction to replace one of the nops that was
7657 tentatively added to prev_nop_frag. */
7658 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7659 prev_nop_frag_holds
--;
7660 prev_nop_frag_since
++;
7664 method
= get_append_method (ip
, address_expr
, reloc_type
);
7665 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7667 dwarf2_emit_insn (0);
7668 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7669 so "move" the instruction address accordingly.
7671 Also, it doesn't seem appropriate for the assembler to reorder .loc
7672 entries. If this instruction is a branch that we are going to swap
7673 with the previous instruction, the two instructions should be
7674 treated as a unit, and the debug information for both instructions
7675 should refer to the start of the branch sequence. Using the
7676 current position is certainly wrong when swapping a 32-bit branch
7677 and a 16-bit delay slot, since the current position would then be
7678 in the middle of a branch. */
7679 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7681 relax32
= (mips_relax_branch
7682 /* Don't try branch relaxation within .set nomacro, or within
7683 .set noat if we use $at for PIC computations. If it turns
7684 out that the branch was out-of-range, we'll get an error. */
7685 && !mips_opts
.warn_about_macros
7686 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7687 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7688 as they have no complementing branches. */
7689 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7691 if (!HAVE_CODE_COMPRESSION
7694 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7695 && delayed_branch_p (ip
))
7697 relaxed_branch
= TRUE
;
7698 add_relaxed_insn (ip
, (relaxed_branch_length
7700 uncond_branch_p (ip
) ? -1
7701 : branch_likely_p (ip
) ? 1
7704 (AT
, mips_pic
!= NO_PIC
,
7705 uncond_branch_p (ip
),
7706 branch_likely_p (ip
),
7707 pinfo
& INSN_WRITE_GPR_31
,
7709 address_expr
->X_add_symbol
,
7710 address_expr
->X_add_number
);
7711 *reloc_type
= BFD_RELOC_UNUSED
;
7713 else if (mips_opts
.micromips
7715 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7716 || *reloc_type
> BFD_RELOC_UNUSED
)
7717 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7718 /* Don't try branch relaxation when users specify
7719 16-bit/32-bit instructions. */
7720 && !forced_insn_length
)
7722 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7723 && *reloc_type
> BFD_RELOC_UNUSED
);
7724 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7725 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7726 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7727 int nods
= method
== APPEND_ADD_WITH_NOP
;
7728 int al
= pinfo
& INSN_WRITE_GPR_31
;
7729 int length32
= nods
? 8 : 4;
7731 gas_assert (address_expr
!= NULL
);
7732 gas_assert (!mips_relax
.sequence
);
7734 relaxed_branch
= TRUE
;
7736 method
= APPEND_ADD
;
7738 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7739 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7740 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7742 uncond
, compact
, al
, nods
,
7744 address_expr
->X_add_symbol
,
7745 address_expr
->X_add_number
);
7746 *reloc_type
= BFD_RELOC_UNUSED
;
7748 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7750 bfd_boolean require_unextended
;
7751 bfd_boolean require_extended
;
7755 if (forced_insn_length
!= 0)
7757 require_unextended
= forced_insn_length
== 2;
7758 require_extended
= forced_insn_length
== 4;
7762 require_unextended
= (mips_opts
.noautoextend
7763 && !mips_opcode_32bit_p (ip
->insn_mo
));
7764 require_extended
= 0;
7767 /* We need to set up a variant frag. */
7768 gas_assert (address_expr
!= NULL
);
7769 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7770 symbol created by `make_expr_symbol' may not get a necessary
7771 external relocation produced. */
7772 if (address_expr
->X_op
== O_symbol
)
7774 symbol
= address_expr
->X_add_symbol
;
7775 offset
= address_expr
->X_add_number
;
7779 symbol
= make_expr_symbol (address_expr
);
7780 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7783 add_relaxed_insn (ip
, 12, 0,
7785 (*reloc_type
- BFD_RELOC_UNUSED
,
7786 mips_opts
.ase
& ASE_MIPS16E2
,
7789 mips_opts
.warn_about_macros
,
7790 require_unextended
, require_extended
,
7791 delayed_branch_p (&history
[0]),
7792 history
[0].mips16_absolute_jump_p
),
7795 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7797 if (!delayed_branch_p (ip
))
7798 /* Make sure there is enough room to swap this instruction with
7799 a following jump instruction. */
7801 add_fixed_insn (ip
);
7805 if (mips_opts
.mips16
7806 && mips_opts
.noreorder
7807 && delayed_branch_p (&history
[0]))
7808 as_warn (_("extended instruction in delay slot"));
7810 if (mips_relax
.sequence
)
7812 /* If we've reached the end of this frag, turn it into a variant
7813 frag and record the information for the instructions we've
7815 if (frag_room () < 4)
7816 relax_close_frag ();
7817 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7820 if (mips_relax
.sequence
!= 2)
7822 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7823 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7824 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7825 mips_macro_warning
.insns
[0]++;
7827 if (mips_relax
.sequence
!= 1)
7829 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7830 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7831 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7832 mips_macro_warning
.insns
[1]++;
7835 if (mips_opts
.mips16
)
7838 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7840 add_fixed_insn (ip
);
7843 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7845 bfd_reloc_code_real_type final_type
[3];
7846 reloc_howto_type
*howto0
;
7847 reloc_howto_type
*howto
;
7850 /* Perform any necessary conversion to microMIPS relocations
7851 and find out how many relocations there actually are. */
7852 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7853 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7855 /* In a compound relocation, it is the final (outermost)
7856 operator that determines the relocated field. */
7857 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7862 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7863 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7864 bfd_get_reloc_size (howto
),
7866 howto0
&& howto0
->pc_relative
,
7868 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7869 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7871 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7872 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7873 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7875 /* These relocations can have an addend that won't fit in
7876 4 octets for 64bit assembly. */
7878 && ! howto
->partial_inplace
7879 && (reloc_type
[0] == BFD_RELOC_16
7880 || reloc_type
[0] == BFD_RELOC_32
7881 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7882 || reloc_type
[0] == BFD_RELOC_GPREL16
7883 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7884 || reloc_type
[0] == BFD_RELOC_GPREL32
7885 || reloc_type
[0] == BFD_RELOC_64
7886 || reloc_type
[0] == BFD_RELOC_CTOR
7887 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7888 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7889 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7890 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7891 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7892 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7893 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7894 || hi16_reloc_p (reloc_type
[0])
7895 || lo16_reloc_p (reloc_type
[0])))
7896 ip
->fixp
[0]->fx_no_overflow
= 1;
7898 /* These relocations can have an addend that won't fit in 2 octets. */
7899 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7900 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7901 ip
->fixp
[0]->fx_no_overflow
= 1;
7903 if (mips_relax
.sequence
)
7905 if (mips_relax
.first_fixup
== 0)
7906 mips_relax
.first_fixup
= ip
->fixp
[0];
7908 else if (reloc_needs_lo_p (*reloc_type
))
7910 struct mips_hi_fixup
*hi_fixup
;
7912 /* Reuse the last entry if it already has a matching %lo. */
7913 hi_fixup
= mips_hi_fixup_list
;
7915 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7917 hi_fixup
= XNEW (struct mips_hi_fixup
);
7918 hi_fixup
->next
= mips_hi_fixup_list
;
7919 mips_hi_fixup_list
= hi_fixup
;
7921 hi_fixup
->fixp
= ip
->fixp
[0];
7922 hi_fixup
->seg
= now_seg
;
7925 /* Add fixups for the second and third relocations, if given.
7926 Note that the ABI allows the second relocation to be
7927 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7928 moment we only use RSS_UNDEF, but we could add support
7929 for the others if it ever becomes necessary. */
7930 for (i
= 1; i
< 3; i
++)
7931 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7933 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7934 ip
->fixp
[0]->fx_size
, NULL
, 0,
7935 FALSE
, final_type
[i
]);
7937 /* Use fx_tcbit to mark compound relocs. */
7938 ip
->fixp
[0]->fx_tcbit
= 1;
7939 ip
->fixp
[i
]->fx_tcbit
= 1;
7943 /* Update the register mask information. */
7944 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7945 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7950 insert_into_history (0, 1, ip
);
7953 case APPEND_ADD_WITH_NOP
:
7955 struct mips_cl_insn
*nop
;
7957 insert_into_history (0, 1, ip
);
7958 nop
= get_delay_slot_nop (ip
);
7959 add_fixed_insn (nop
);
7960 insert_into_history (0, 1, nop
);
7961 if (mips_relax
.sequence
)
7962 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7966 case APPEND_ADD_COMPACT
:
7967 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7968 if (mips_opts
.mips16
)
7970 ip
->insn_opcode
|= 0x0080;
7971 find_altered_mips16_opcode (ip
);
7973 /* Convert microMIPS instructions. */
7974 else if (mips_opts
.micromips
)
7977 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7978 ip
->insn_opcode
|= 0x0020;
7980 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7981 ip
->insn_opcode
= 0x40e00000;
7982 /* beqz16->beqzc, bnez16->bnezc */
7983 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7985 unsigned long regno
;
7987 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7988 regno
&= MICROMIPSOP_MASK_MD
;
7989 regno
= micromips_to_32_reg_d_map
[regno
];
7990 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7991 | (regno
<< MICROMIPSOP_SH_RS
)
7992 | 0x40a00000) ^ 0x00400000;
7994 /* beqz->beqzc, bnez->bnezc */
7995 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7996 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7997 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7998 | 0x40a00000) ^ 0x00400000;
7999 /* beq $0->beqzc, bne $0->bnezc */
8000 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
8001 ip
->insn_opcode
= (((ip
->insn_opcode
>>
8002 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8003 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8004 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8005 | 0x40a00000) ^ 0x00400000;
8008 find_altered_micromips_opcode (ip
);
8013 insert_into_history (0, 1, ip
);
8018 struct mips_cl_insn delay
= history
[0];
8020 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8022 /* Add the delay slot instruction to the end of the
8023 current frag and shrink the fixed part of the
8024 original frag. If the branch occupies the tail of
8025 the latter, move it backwards to cover the gap. */
8026 delay
.frag
->fr_fix
-= branch_disp
;
8027 if (delay
.frag
== ip
->frag
)
8028 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8029 add_fixed_insn (&delay
);
8033 /* If this is not a relaxed branch and we are in the
8034 same frag, then just swap the instructions. */
8035 move_insn (ip
, delay
.frag
, delay
.where
);
8036 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8040 insert_into_history (0, 1, &delay
);
8045 /* If we have just completed an unconditional branch, clear the history. */
8046 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8047 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8051 mips_no_prev_insn ();
8053 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8054 history
[i
].cleared_p
= 1;
8057 /* We need to emit a label at the end of branch-likely macros. */
8058 if (emit_branch_likely_macro
)
8060 emit_branch_likely_macro
= FALSE
;
8061 micromips_add_label ();
8064 /* We just output an insn, so the next one doesn't have a label. */
8065 mips_clear_insn_labels ();
8068 /* Forget that there was any previous instruction or label.
8069 When BRANCH is true, the branch history is also flushed. */
8072 mips_no_prev_insn (void)
8074 prev_nop_frag
= NULL
;
8075 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8076 mips_clear_insn_labels ();
8079 /* This function must be called before we emit something other than
8080 instructions. It is like mips_no_prev_insn except that it inserts
8081 any NOPS that might be needed by previous instructions. */
8084 mips_emit_delays (void)
8086 if (! mips_opts
.noreorder
)
8088 int nops
= nops_for_insn (0, history
, NULL
);
8092 add_fixed_insn (NOP_INSN
);
8093 mips_move_text_labels ();
8096 mips_no_prev_insn ();
8099 /* Start a (possibly nested) noreorder block. */
8102 start_noreorder (void)
8104 if (mips_opts
.noreorder
== 0)
8109 /* None of the instructions before the .set noreorder can be moved. */
8110 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8111 history
[i
].fixed_p
= 1;
8113 /* Insert any nops that might be needed between the .set noreorder
8114 block and the previous instructions. We will later remove any
8115 nops that turn out not to be needed. */
8116 nops
= nops_for_insn (0, history
, NULL
);
8119 if (mips_optimize
!= 0)
8121 /* Record the frag which holds the nop instructions, so
8122 that we can remove them if we don't need them. */
8123 frag_grow (nops
* NOP_INSN_SIZE
);
8124 prev_nop_frag
= frag_now
;
8125 prev_nop_frag_holds
= nops
;
8126 prev_nop_frag_required
= 0;
8127 prev_nop_frag_since
= 0;
8130 for (; nops
> 0; --nops
)
8131 add_fixed_insn (NOP_INSN
);
8133 /* Move on to a new frag, so that it is safe to simply
8134 decrease the size of prev_nop_frag. */
8135 frag_wane (frag_now
);
8137 mips_move_text_labels ();
8139 mips_mark_labels ();
8140 mips_clear_insn_labels ();
8142 mips_opts
.noreorder
++;
8143 mips_any_noreorder
= 1;
8146 /* End a nested noreorder block. */
8149 end_noreorder (void)
8151 mips_opts
.noreorder
--;
8152 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8154 /* Commit to inserting prev_nop_frag_required nops and go back to
8155 handling nop insertion the .set reorder way. */
8156 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8158 insert_into_history (prev_nop_frag_since
,
8159 prev_nop_frag_required
, NOP_INSN
);
8160 prev_nop_frag
= NULL
;
8164 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8165 higher bits unset. */
8168 normalize_constant_expr (expressionS
*ex
)
8170 if (ex
->X_op
== O_constant
8171 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8172 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8176 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8177 all higher bits unset. */
8180 normalize_address_expr (expressionS
*ex
)
8182 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8183 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8184 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8185 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8189 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8190 Return true if the match was successful.
8192 OPCODE_EXTRA is a value that should be ORed into the opcode
8193 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8194 there are more alternatives after OPCODE and SOFT_MATCH is
8195 as for mips_arg_info. */
8198 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8199 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8200 bfd_boolean lax_match
, bfd_boolean complete_p
)
8203 struct mips_arg_info arg
;
8204 const struct mips_operand
*operand
;
8207 imm_expr
.X_op
= O_absent
;
8208 offset_expr
.X_op
= O_absent
;
8209 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8210 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8211 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8213 create_insn (insn
, opcode
);
8214 /* When no opcode suffix is specified, assume ".xyzw". */
8215 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8216 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8218 insn
->insn_opcode
|= opcode_extra
;
8219 memset (&arg
, 0, sizeof (arg
));
8223 arg
.last_regno
= ILLEGAL_REG
;
8224 arg
.dest_regno
= ILLEGAL_REG
;
8225 arg
.lax_match
= lax_match
;
8226 for (args
= opcode
->args
;; ++args
)
8228 if (arg
.token
->type
== OT_END
)
8230 /* Handle unary instructions in which only one operand is given.
8231 The source is then the same as the destination. */
8232 if (arg
.opnum
== 1 && *args
== ',')
8234 operand
= (mips_opts
.micromips
8235 ? decode_micromips_operand (args
+ 1)
8236 : decode_mips_operand (args
+ 1));
8237 if (operand
&& mips_optional_operand_p (operand
))
8245 /* Treat elided base registers as $0. */
8246 if (strcmp (args
, "(b)") == 0)
8254 /* The register suffix is optional. */
8259 /* Fail the match if there were too few operands. */
8263 /* Successful match. */
8266 clear_insn_error ();
8267 if (arg
.dest_regno
== arg
.last_regno
8268 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8272 (0, _("source and destination must be different"));
8273 else if (arg
.last_regno
== 31)
8275 (0, _("a destination register must be supplied"));
8277 else if (arg
.last_regno
== 31
8278 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8279 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8280 set_insn_error (0, _("the source register must not be $31"));
8281 check_completed_insn (&arg
);
8285 /* Fail the match if the line has too many operands. */
8289 /* Handle characters that need to match exactly. */
8290 if (*args
== '(' || *args
== ')' || *args
== ',')
8292 if (match_char (&arg
, *args
))
8299 if (arg
.token
->type
== OT_DOUBLE_CHAR
8300 && arg
.token
->u
.ch
== *args
)
8308 /* Handle special macro operands. Work out the properties of
8317 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8321 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8330 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8334 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8338 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8344 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8346 imm_expr
.X_op
= O_constant
;
8348 normalize_constant_expr (&imm_expr
);
8352 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8354 /* Assume that the offset has been elided and that what
8355 we saw was a base register. The match will fail later
8356 if that assumption turns out to be wrong. */
8357 offset_expr
.X_op
= O_constant
;
8358 offset_expr
.X_add_number
= 0;
8362 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8364 normalize_address_expr (&offset_expr
);
8369 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8375 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8381 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8387 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8393 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8397 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8401 gas_assert (mips_opts
.micromips
);
8407 if (!forced_insn_length
)
8408 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8410 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8412 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8418 operand
= (mips_opts
.micromips
8419 ? decode_micromips_operand (args
)
8420 : decode_mips_operand (args
));
8424 /* Skip prefixes. */
8425 if (*args
== '+' || *args
== 'm' || *args
== '-')
8428 if (mips_optional_operand_p (operand
)
8430 && (arg
.token
[0].type
!= OT_REG
8431 || arg
.token
[1].type
== OT_END
))
8433 /* Assume that the register has been elided and is the
8434 same as the first operand. */
8439 if (!match_operand (&arg
, operand
))
8444 /* Like match_insn, but for MIPS16. */
8447 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8448 struct mips_operand_token
*tokens
)
8451 const struct mips_operand
*operand
;
8452 const struct mips_operand
*ext_operand
;
8453 bfd_boolean pcrel
= FALSE
;
8454 int required_insn_length
;
8455 struct mips_arg_info arg
;
8458 if (forced_insn_length
)
8459 required_insn_length
= forced_insn_length
;
8460 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8461 required_insn_length
= 2;
8463 required_insn_length
= 0;
8465 create_insn (insn
, opcode
);
8466 imm_expr
.X_op
= O_absent
;
8467 offset_expr
.X_op
= O_absent
;
8468 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8469 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8470 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8473 memset (&arg
, 0, sizeof (arg
));
8477 arg
.last_regno
= ILLEGAL_REG
;
8478 arg
.dest_regno
= ILLEGAL_REG
;
8480 for (args
= opcode
->args
;; ++args
)
8484 if (arg
.token
->type
== OT_END
)
8488 /* Handle unary instructions in which only one operand is given.
8489 The source is then the same as the destination. */
8490 if (arg
.opnum
== 1 && *args
== ',')
8492 operand
= decode_mips16_operand (args
[1], FALSE
);
8493 if (operand
&& mips_optional_operand_p (operand
))
8501 /* Fail the match if there were too few operands. */
8505 /* Successful match. Stuff the immediate value in now, if
8507 clear_insn_error ();
8508 if (opcode
->pinfo
== INSN_MACRO
)
8510 gas_assert (relax_char
== 0 || relax_char
== 'p');
8511 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8514 && offset_expr
.X_op
== O_constant
8516 && calculate_reloc (*offset_reloc
,
8517 offset_expr
.X_add_number
,
8520 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8521 required_insn_length
, &insn
->insn_opcode
);
8522 offset_expr
.X_op
= O_absent
;
8523 *offset_reloc
= BFD_RELOC_UNUSED
;
8525 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8527 if (required_insn_length
== 2)
8528 set_insn_error (0, _("invalid unextended operand value"));
8529 else if (!mips_opcode_32bit_p (opcode
))
8531 forced_insn_length
= 4;
8532 insn
->insn_opcode
|= MIPS16_EXTEND
;
8535 else if (relax_char
)
8536 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8538 check_completed_insn (&arg
);
8542 /* Fail the match if the line has too many operands. */
8546 /* Handle characters that need to match exactly. */
8547 if (*args
== '(' || *args
== ')' || *args
== ',')
8549 if (match_char (&arg
, *args
))
8569 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8571 imm_expr
.X_op
= O_constant
;
8573 normalize_constant_expr (&imm_expr
);
8578 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8582 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8586 if (operand
->type
== OP_PCREL
)
8590 ext_operand
= decode_mips16_operand (c
, TRUE
);
8591 if (operand
!= ext_operand
)
8593 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8595 offset_expr
.X_op
= O_constant
;
8596 offset_expr
.X_add_number
= 0;
8601 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8604 /* '8' is used for SLTI(U) and has traditionally not
8605 been allowed to take relocation operators. */
8606 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8607 && (ext_operand
->size
!= 16 || c
== '8'))
8609 match_not_constant (&arg
);
8613 if (offset_expr
.X_op
== O_big
)
8615 match_out_of_range (&arg
);
8624 if (mips_optional_operand_p (operand
)
8626 && (arg
.token
[0].type
!= OT_REG
8627 || arg
.token
[1].type
== OT_END
))
8629 /* Assume that the register has been elided and is the
8630 same as the first operand. */
8635 if (!match_operand (&arg
, operand
))
8640 /* Record that the current instruction is invalid for the current ISA. */
8643 match_invalid_for_isa (void)
8646 (0, _("opcode not supported on this processor: %s (%s)"),
8647 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8648 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8651 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8652 Return true if a definite match or failure was found, storing any match
8653 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8654 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8655 tried and failed to match under normal conditions and now want to try a
8656 more relaxed match. */
8659 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8660 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8661 int opcode_extra
, bfd_boolean lax_match
)
8663 const struct mips_opcode
*opcode
;
8664 const struct mips_opcode
*invalid_delay_slot
;
8665 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8667 /* Search for a match, ignoring alternatives that don't satisfy the
8668 current ISA or forced_length. */
8669 invalid_delay_slot
= 0;
8670 seen_valid_for_isa
= FALSE
;
8671 seen_valid_for_size
= FALSE
;
8675 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8676 if (is_opcode_valid (opcode
))
8678 seen_valid_for_isa
= TRUE
;
8679 if (is_size_valid (opcode
))
8681 bfd_boolean delay_slot_ok
;
8683 seen_valid_for_size
= TRUE
;
8684 delay_slot_ok
= is_delay_slot_valid (opcode
);
8685 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8686 lax_match
, delay_slot_ok
))
8690 if (!invalid_delay_slot
)
8691 invalid_delay_slot
= opcode
;
8700 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8702 /* If the only matches we found had the wrong length for the delay slot,
8703 pick the first such match. We'll issue an appropriate warning later. */
8704 if (invalid_delay_slot
)
8706 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8712 /* Handle the case where we didn't try to match an instruction because
8713 all the alternatives were incompatible with the current ISA. */
8714 if (!seen_valid_for_isa
)
8716 match_invalid_for_isa ();
8720 /* Handle the case where we didn't try to match an instruction because
8721 all the alternatives were of the wrong size. */
8722 if (!seen_valid_for_size
)
8724 if (mips_opts
.insn32
)
8725 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8728 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8729 8 * forced_insn_length
);
8736 /* Like match_insns, but for MIPS16. */
8739 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8740 struct mips_operand_token
*tokens
)
8742 const struct mips_opcode
*opcode
;
8743 bfd_boolean seen_valid_for_isa
;
8744 bfd_boolean seen_valid_for_size
;
8746 /* Search for a match, ignoring alternatives that don't satisfy the
8747 current ISA. There are no separate entries for extended forms so
8748 we deal with forced_length later. */
8749 seen_valid_for_isa
= FALSE
;
8750 seen_valid_for_size
= FALSE
;
8754 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8755 if (is_opcode_valid_16 (opcode
))
8757 seen_valid_for_isa
= TRUE
;
8758 if (is_size_valid_16 (opcode
))
8760 seen_valid_for_size
= TRUE
;
8761 if (match_mips16_insn (insn
, opcode
, tokens
))
8767 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8768 && strcmp (opcode
->name
, first
->name
) == 0);
8770 /* Handle the case where we didn't try to match an instruction because
8771 all the alternatives were incompatible with the current ISA. */
8772 if (!seen_valid_for_isa
)
8774 match_invalid_for_isa ();
8778 /* Handle the case where we didn't try to match an instruction because
8779 all the alternatives were of the wrong size. */
8780 if (!seen_valid_for_size
)
8782 if (forced_insn_length
== 2)
8784 (0, _("unrecognized unextended version of MIPS16 opcode"));
8787 (0, _("unrecognized extended version of MIPS16 opcode"));
8794 /* Set up global variables for the start of a new macro. */
8799 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8800 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8801 sizeof (mips_macro_warning
.first_insn_sizes
));
8802 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8803 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8804 && delayed_branch_p (&history
[0]));
8806 && history
[0].frag
->fr_type
== rs_machine_dependent
8807 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8808 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8809 mips_macro_warning
.delay_slot_length
= 0;
8811 switch (history
[0].insn_mo
->pinfo2
8812 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8814 case INSN2_BRANCH_DELAY_32BIT
:
8815 mips_macro_warning
.delay_slot_length
= 4;
8817 case INSN2_BRANCH_DELAY_16BIT
:
8818 mips_macro_warning
.delay_slot_length
= 2;
8821 mips_macro_warning
.delay_slot_length
= 0;
8824 mips_macro_warning
.first_frag
= NULL
;
8827 /* Given that a macro is longer than one instruction or of the wrong size,
8828 return the appropriate warning for it. Return null if no warning is
8829 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8830 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8831 and RELAX_NOMACRO. */
8834 macro_warning (relax_substateT subtype
)
8836 if (subtype
& RELAX_DELAY_SLOT
)
8837 return _("macro instruction expanded into multiple instructions"
8838 " in a branch delay slot");
8839 else if (subtype
& RELAX_NOMACRO
)
8840 return _("macro instruction expanded into multiple instructions");
8841 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8842 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8843 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8844 ? _("macro instruction expanded into a wrong size instruction"
8845 " in a 16-bit branch delay slot")
8846 : _("macro instruction expanded into a wrong size instruction"
8847 " in a 32-bit branch delay slot"));
8852 /* Finish up a macro. Emit warnings as appropriate. */
8857 /* Relaxation warning flags. */
8858 relax_substateT subtype
= 0;
8860 /* Check delay slot size requirements. */
8861 if (mips_macro_warning
.delay_slot_length
== 2)
8862 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8863 if (mips_macro_warning
.delay_slot_length
!= 0)
8865 if (mips_macro_warning
.delay_slot_length
8866 != mips_macro_warning
.first_insn_sizes
[0])
8867 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8868 if (mips_macro_warning
.delay_slot_length
8869 != mips_macro_warning
.first_insn_sizes
[1])
8870 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8873 /* Check instruction count requirements. */
8874 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8876 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8877 subtype
|= RELAX_SECOND_LONGER
;
8878 if (mips_opts
.warn_about_macros
)
8879 subtype
|= RELAX_NOMACRO
;
8880 if (mips_macro_warning
.delay_slot_p
)
8881 subtype
|= RELAX_DELAY_SLOT
;
8884 /* If both alternatives fail to fill a delay slot correctly,
8885 emit the warning now. */
8886 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8887 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8892 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8893 | RELAX_DELAY_SLOT_SIZE_FIRST
8894 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8895 msg
= macro_warning (s
);
8897 as_warn ("%s", msg
);
8901 /* If both implementations are longer than 1 instruction, then emit the
8903 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8908 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8909 msg
= macro_warning (s
);
8911 as_warn ("%s", msg
);
8915 /* If any flags still set, then one implementation might need a warning
8916 and the other either will need one of a different kind or none at all.
8917 Pass any remaining flags over to relaxation. */
8918 if (mips_macro_warning
.first_frag
!= NULL
)
8919 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8922 /* Instruction operand formats used in macros that vary between
8923 standard MIPS and microMIPS code. */
8925 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8926 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8927 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8928 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8929 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8930 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8931 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8932 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8934 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8935 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8936 : cop12_fmt[mips_opts.micromips])
8937 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8938 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8939 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8940 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8941 : mem12_fmt[mips_opts.micromips])
8942 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8943 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8944 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8946 /* Read a macro's relocation codes from *ARGS and store them in *R.
8947 The first argument in *ARGS will be either the code for a single
8948 relocation or -1 followed by the three codes that make up a
8949 composite relocation. */
8952 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8956 next
= va_arg (*args
, int);
8958 r
[0] = (bfd_reloc_code_real_type
) next
;
8961 for (i
= 0; i
< 3; i
++)
8962 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8963 /* This function is only used for 16-bit relocation fields.
8964 To make the macro code simpler, treat an unrelocated value
8965 in the same way as BFD_RELOC_LO16. */
8966 if (r
[0] == BFD_RELOC_UNUSED
)
8967 r
[0] = BFD_RELOC_LO16
;
8971 /* Build an instruction created by a macro expansion. This is passed
8972 a pointer to the count of instructions created so far, an
8973 expression, the name of the instruction to build, an operand format
8974 string, and corresponding arguments. */
8977 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8979 const struct mips_opcode
*mo
= NULL
;
8980 bfd_reloc_code_real_type r
[3];
8981 const struct mips_opcode
*amo
;
8982 const struct mips_operand
*operand
;
8983 struct hash_control
*hash
;
8984 struct mips_cl_insn insn
;
8988 va_start (args
, fmt
);
8990 if (mips_opts
.mips16
)
8992 mips16_macro_build (ep
, name
, fmt
, &args
);
8997 r
[0] = BFD_RELOC_UNUSED
;
8998 r
[1] = BFD_RELOC_UNUSED
;
8999 r
[2] = BFD_RELOC_UNUSED
;
9000 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
9001 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
9003 gas_assert (strcmp (name
, amo
->name
) == 0);
9007 /* Search until we get a match for NAME. It is assumed here that
9008 macros will never generate MDMX, MIPS-3D, or MT instructions.
9009 We try to match an instruction that fulfills the branch delay
9010 slot instruction length requirement (if any) of the previous
9011 instruction. While doing this we record the first instruction
9012 seen that matches all the other conditions and use it anyway
9013 if the requirement cannot be met; we will issue an appropriate
9014 warning later on. */
9015 if (strcmp (fmt
, amo
->args
) == 0
9016 && amo
->pinfo
!= INSN_MACRO
9017 && is_opcode_valid (amo
)
9018 && is_size_valid (amo
))
9020 if (is_delay_slot_valid (amo
))
9030 gas_assert (amo
->name
);
9032 while (strcmp (name
, amo
->name
) == 0);
9035 create_insn (&insn
, mo
);
9048 macro_read_relocs (&args
, r
);
9049 gas_assert (*r
== BFD_RELOC_GPREL16
9050 || *r
== BFD_RELOC_MIPS_HIGHER
9051 || *r
== BFD_RELOC_HI16_S
9052 || *r
== BFD_RELOC_LO16
9053 || *r
== BFD_RELOC_MIPS_GOT_OFST
9054 || (mips_opts
.micromips
9055 && (*r
== BFD_RELOC_16
9056 || *r
== BFD_RELOC_MIPS_GOT16
9057 || *r
== BFD_RELOC_MIPS_CALL16
9058 || *r
== BFD_RELOC_MIPS_GOT_HI16
9059 || *r
== BFD_RELOC_MIPS_GOT_LO16
9060 || *r
== BFD_RELOC_MIPS_CALL_HI16
9061 || *r
== BFD_RELOC_MIPS_CALL_LO16
9062 || *r
== BFD_RELOC_MIPS_SUB
9063 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9064 || *r
== BFD_RELOC_MIPS_HIGHEST
9065 || *r
== BFD_RELOC_MIPS_GOT_DISP
9066 || *r
== BFD_RELOC_MIPS_TLS_GD
9067 || *r
== BFD_RELOC_MIPS_TLS_LDM
9068 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9069 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9070 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9071 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9072 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9076 macro_read_relocs (&args
, r
);
9080 macro_read_relocs (&args
, r
);
9081 gas_assert (ep
!= NULL
9082 && (ep
->X_op
== O_constant
9083 || (ep
->X_op
== O_symbol
9084 && (*r
== BFD_RELOC_MIPS_HIGHEST
9085 || *r
== BFD_RELOC_HI16_S
9086 || *r
== BFD_RELOC_HI16
9087 || *r
== BFD_RELOC_GPREL16
9088 || *r
== BFD_RELOC_MIPS_GOT_HI16
9089 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9093 gas_assert (ep
!= NULL
);
9096 * This allows macro() to pass an immediate expression for
9097 * creating short branches without creating a symbol.
9099 * We don't allow branch relaxation for these branches, as
9100 * they should only appear in ".set nomacro" anyway.
9102 if (ep
->X_op
== O_constant
)
9104 /* For microMIPS we always use relocations for branches.
9105 So we should not resolve immediate values. */
9106 gas_assert (!mips_opts
.micromips
);
9108 if ((ep
->X_add_number
& 3) != 0)
9109 as_bad (_("branch to misaligned address (0x%lx)"),
9110 (unsigned long) ep
->X_add_number
);
9111 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9112 as_bad (_("branch address range overflow (0x%lx)"),
9113 (unsigned long) ep
->X_add_number
);
9114 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9118 *r
= BFD_RELOC_16_PCREL_S2
;
9122 gas_assert (ep
!= NULL
);
9123 *r
= BFD_RELOC_MIPS_JMP
;
9127 operand
= (mips_opts
.micromips
9128 ? decode_micromips_operand (fmt
)
9129 : decode_mips_operand (fmt
));
9133 uval
= va_arg (args
, int);
9134 if (operand
->type
== OP_CLO_CLZ_DEST
)
9135 uval
|= (uval
<< 5);
9136 insn_insert_operand (&insn
, operand
, uval
);
9138 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9144 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9146 append_insn (&insn
, ep
, r
, TRUE
);
9150 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9153 struct mips_opcode
*mo
;
9154 struct mips_cl_insn insn
;
9155 const struct mips_operand
*operand
;
9156 bfd_reloc_code_real_type r
[3]
9157 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9159 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
9161 gas_assert (strcmp (name
, mo
->name
) == 0);
9163 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9166 gas_assert (mo
->name
);
9167 gas_assert (strcmp (name
, mo
->name
) == 0);
9170 create_insn (&insn
, mo
);
9207 gas_assert (ep
!= NULL
);
9209 if (ep
->X_op
!= O_constant
)
9210 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9211 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9213 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9215 *r
= BFD_RELOC_UNUSED
;
9221 operand
= decode_mips16_operand (c
, FALSE
);
9225 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9230 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9232 append_insn (&insn
, ep
, r
, TRUE
);
9236 * Generate a "jalr" instruction with a relocation hint to the called
9237 * function. This occurs in NewABI PIC code.
9240 macro_build_jalr (expressionS
*ep
, int cprestore
)
9242 static const bfd_reloc_code_real_type jalr_relocs
[2]
9243 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9244 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9248 if (MIPS_JALR_HINT_P (ep
))
9253 if (mips_opts
.micromips
)
9255 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9256 ? "jalr" : "jalrs");
9257 if (MIPS_JALR_HINT_P (ep
)
9259 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9260 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9262 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9265 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9266 if (MIPS_JALR_HINT_P (ep
))
9267 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9271 * Generate a "lui" instruction.
9274 macro_build_lui (expressionS
*ep
, int regnum
)
9276 gas_assert (! mips_opts
.mips16
);
9278 if (ep
->X_op
!= O_constant
)
9280 gas_assert (ep
->X_op
== O_symbol
);
9281 /* _gp_disp is a special case, used from s_cpload.
9282 __gnu_local_gp is used if mips_no_shared. */
9283 gas_assert (mips_pic
== NO_PIC
9285 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9286 || (! mips_in_shared
9287 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9288 "__gnu_local_gp") == 0));
9291 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9294 /* Generate a sequence of instructions to do a load or store from a constant
9295 offset off of a base register (breg) into/from a target register (treg),
9296 using AT if necessary. */
9298 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9299 int treg
, int breg
, int dbl
)
9301 gas_assert (ep
->X_op
== O_constant
);
9303 /* Sign-extending 32-bit constants makes their handling easier. */
9305 normalize_constant_expr (ep
);
9307 /* Right now, this routine can only handle signed 32-bit constants. */
9308 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9309 as_warn (_("operand overflow"));
9311 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9313 /* Signed 16-bit offset will fit in the op. Easy! */
9314 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9318 /* 32-bit offset, need multiple instructions and AT, like:
9319 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9320 addu $tempreg,$tempreg,$breg
9321 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9322 to handle the complete offset. */
9323 macro_build_lui (ep
, AT
);
9324 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9325 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9328 as_bad (_("macro used $at after \".set noat\""));
9333 * Generates code to set the $at register to true (one)
9334 * if reg is less than the immediate expression.
9337 set_at (int reg
, int unsignedp
)
9339 if (imm_expr
.X_add_number
>= -0x8000
9340 && imm_expr
.X_add_number
< 0x8000)
9341 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9342 AT
, reg
, BFD_RELOC_LO16
);
9345 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9346 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9350 /* Count the leading zeroes by performing a binary chop. This is a
9351 bulky bit of source, but performance is a LOT better for the
9352 majority of values than a simple loop to count the bits:
9353 for (lcnt = 0; (lcnt < 32); lcnt++)
9354 if ((v) & (1 << (31 - lcnt)))
9356 However it is not code size friendly, and the gain will drop a bit
9357 on certain cached systems.
9359 #define COUNT_TOP_ZEROES(v) \
9360 (((v) & ~0xffff) == 0 \
9361 ? ((v) & ~0xff) == 0 \
9362 ? ((v) & ~0xf) == 0 \
9363 ? ((v) & ~0x3) == 0 \
9364 ? ((v) & ~0x1) == 0 \
9369 : ((v) & ~0x7) == 0 \
9372 : ((v) & ~0x3f) == 0 \
9373 ? ((v) & ~0x1f) == 0 \
9376 : ((v) & ~0x7f) == 0 \
9379 : ((v) & ~0xfff) == 0 \
9380 ? ((v) & ~0x3ff) == 0 \
9381 ? ((v) & ~0x1ff) == 0 \
9384 : ((v) & ~0x7ff) == 0 \
9387 : ((v) & ~0x3fff) == 0 \
9388 ? ((v) & ~0x1fff) == 0 \
9391 : ((v) & ~0x7fff) == 0 \
9394 : ((v) & ~0xffffff) == 0 \
9395 ? ((v) & ~0xfffff) == 0 \
9396 ? ((v) & ~0x3ffff) == 0 \
9397 ? ((v) & ~0x1ffff) == 0 \
9400 : ((v) & ~0x7ffff) == 0 \
9403 : ((v) & ~0x3fffff) == 0 \
9404 ? ((v) & ~0x1fffff) == 0 \
9407 : ((v) & ~0x7fffff) == 0 \
9410 : ((v) & ~0xfffffff) == 0 \
9411 ? ((v) & ~0x3ffffff) == 0 \
9412 ? ((v) & ~0x1ffffff) == 0 \
9415 : ((v) & ~0x7ffffff) == 0 \
9418 : ((v) & ~0x3fffffff) == 0 \
9419 ? ((v) & ~0x1fffffff) == 0 \
9422 : ((v) & ~0x7fffffff) == 0 \
9427 * This routine generates the least number of instructions necessary to load
9428 * an absolute expression value into a register.
9431 load_register (int reg
, expressionS
*ep
, int dbl
)
9434 expressionS hi32
, lo32
;
9436 if (ep
->X_op
!= O_big
)
9438 gas_assert (ep
->X_op
== O_constant
);
9440 /* Sign-extending 32-bit constants makes their handling easier. */
9442 normalize_constant_expr (ep
);
9444 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9446 /* We can handle 16 bit signed values with an addiu to
9447 $zero. No need to ever use daddiu here, since $zero and
9448 the result are always correct in 32 bit mode. */
9449 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9452 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9454 /* We can handle 16 bit unsigned values with an ori to
9456 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9459 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9461 /* 32 bit values require an lui. */
9462 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9463 if ((ep
->X_add_number
& 0xffff) != 0)
9464 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9469 /* The value is larger than 32 bits. */
9471 if (!dbl
|| GPR_SIZE
== 32)
9475 sprintf_vma (value
, ep
->X_add_number
);
9476 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9477 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9481 if (ep
->X_op
!= O_big
)
9484 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9485 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9486 hi32
.X_add_number
&= 0xffffffff;
9488 lo32
.X_add_number
&= 0xffffffff;
9492 gas_assert (ep
->X_add_number
> 2);
9493 if (ep
->X_add_number
== 3)
9494 generic_bignum
[3] = 0;
9495 else if (ep
->X_add_number
> 4)
9496 as_bad (_("number larger than 64 bits"));
9497 lo32
.X_op
= O_constant
;
9498 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9499 hi32
.X_op
= O_constant
;
9500 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9503 if (hi32
.X_add_number
== 0)
9508 unsigned long hi
, lo
;
9510 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9512 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9514 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9517 if (lo32
.X_add_number
& 0x80000000)
9519 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9520 if (lo32
.X_add_number
& 0xffff)
9521 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9526 /* Check for 16bit shifted constant. We know that hi32 is
9527 non-zero, so start the mask on the first bit of the hi32
9532 unsigned long himask
, lomask
;
9536 himask
= 0xffff >> (32 - shift
);
9537 lomask
= (0xffff << shift
) & 0xffffffff;
9541 himask
= 0xffff << (shift
- 32);
9544 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9545 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9549 tmp
.X_op
= O_constant
;
9551 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9552 | (lo32
.X_add_number
>> shift
));
9554 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9555 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9556 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9557 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9562 while (shift
<= (64 - 16));
9564 /* Find the bit number of the lowest one bit, and store the
9565 shifted value in hi/lo. */
9566 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9567 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9571 while ((lo
& 1) == 0)
9576 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9582 while ((hi
& 1) == 0)
9591 /* Optimize if the shifted value is a (power of 2) - 1. */
9592 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9593 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9595 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9600 /* This instruction will set the register to be all
9602 tmp
.X_op
= O_constant
;
9603 tmp
.X_add_number
= (offsetT
) -1;
9604 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9608 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9609 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9611 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9612 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9617 /* Sign extend hi32 before calling load_register, because we can
9618 generally get better code when we load a sign extended value. */
9619 if ((hi32
.X_add_number
& 0x80000000) != 0)
9620 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9621 load_register (reg
, &hi32
, 0);
9624 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9628 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9636 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9638 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9639 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9645 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9649 mid16
.X_add_number
>>= 16;
9650 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9651 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9654 if ((lo32
.X_add_number
& 0xffff) != 0)
9655 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9659 load_delay_nop (void)
9661 if (!gpr_interlocks
)
9662 macro_build (NULL
, "nop", "");
9665 /* Load an address into a register. */
9668 load_address (int reg
, expressionS
*ep
, int *used_at
)
9670 if (ep
->X_op
!= O_constant
9671 && ep
->X_op
!= O_symbol
)
9673 as_bad (_("expression too complex"));
9674 ep
->X_op
= O_constant
;
9677 if (ep
->X_op
== O_constant
)
9679 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9683 if (mips_pic
== NO_PIC
)
9685 /* If this is a reference to a GP relative symbol, we want
9686 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9688 lui $reg,<sym> (BFD_RELOC_HI16_S)
9689 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9690 If we have an addend, we always use the latter form.
9692 With 64bit address space and a usable $at we want
9693 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9694 lui $at,<sym> (BFD_RELOC_HI16_S)
9695 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9696 daddiu $at,<sym> (BFD_RELOC_LO16)
9700 If $at is already in use, we use a path which is suboptimal
9701 on superscalar processors.
9702 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9703 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9705 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9707 daddiu $reg,<sym> (BFD_RELOC_LO16)
9709 For GP relative symbols in 64bit address space we can use
9710 the same sequence as in 32bit address space. */
9711 if (HAVE_64BIT_SYMBOLS
)
9713 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9714 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9716 relax_start (ep
->X_add_symbol
);
9717 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9718 mips_gp_register
, BFD_RELOC_GPREL16
);
9722 if (*used_at
== 0 && mips_opts
.at
)
9724 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9725 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9726 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9727 BFD_RELOC_MIPS_HIGHER
);
9728 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9729 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9730 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9735 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9736 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9737 BFD_RELOC_MIPS_HIGHER
);
9738 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9739 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9740 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9741 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9744 if (mips_relax
.sequence
)
9749 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9750 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9752 relax_start (ep
->X_add_symbol
);
9753 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9754 mips_gp_register
, BFD_RELOC_GPREL16
);
9757 macro_build_lui (ep
, reg
);
9758 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9759 reg
, reg
, BFD_RELOC_LO16
);
9760 if (mips_relax
.sequence
)
9764 else if (!mips_big_got
)
9768 /* If this is a reference to an external symbol, we want
9769 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9771 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9773 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9774 If there is a constant, it must be added in after.
9776 If we have NewABI, we want
9777 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9778 unless we're referencing a global symbol with a non-zero
9779 offset, in which case cst must be added separately. */
9782 if (ep
->X_add_number
)
9784 ex
.X_add_number
= ep
->X_add_number
;
9785 ep
->X_add_number
= 0;
9786 relax_start (ep
->X_add_symbol
);
9787 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9788 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9789 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9790 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9791 ex
.X_op
= O_constant
;
9792 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9793 reg
, reg
, BFD_RELOC_LO16
);
9794 ep
->X_add_number
= ex
.X_add_number
;
9797 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9798 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9799 if (mips_relax
.sequence
)
9804 ex
.X_add_number
= ep
->X_add_number
;
9805 ep
->X_add_number
= 0;
9806 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9807 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9809 relax_start (ep
->X_add_symbol
);
9811 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9815 if (ex
.X_add_number
!= 0)
9817 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9818 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9819 ex
.X_op
= O_constant
;
9820 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9821 reg
, reg
, BFD_RELOC_LO16
);
9825 else if (mips_big_got
)
9829 /* This is the large GOT case. If this is a reference to an
9830 external symbol, we want
9831 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9833 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9835 Otherwise, for a reference to a local symbol in old ABI, we want
9836 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9838 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9839 If there is a constant, it must be added in after.
9841 In the NewABI, for local symbols, with or without offsets, we want:
9842 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9843 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9847 ex
.X_add_number
= ep
->X_add_number
;
9848 ep
->X_add_number
= 0;
9849 relax_start (ep
->X_add_symbol
);
9850 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9851 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9852 reg
, reg
, mips_gp_register
);
9853 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9854 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9855 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9856 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9857 else if (ex
.X_add_number
)
9859 ex
.X_op
= O_constant
;
9860 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9864 ep
->X_add_number
= ex
.X_add_number
;
9866 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9867 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9868 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9869 BFD_RELOC_MIPS_GOT_OFST
);
9874 ex
.X_add_number
= ep
->X_add_number
;
9875 ep
->X_add_number
= 0;
9876 relax_start (ep
->X_add_symbol
);
9877 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9878 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9879 reg
, reg
, mips_gp_register
);
9880 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9881 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9883 if (reg_needs_delay (mips_gp_register
))
9885 /* We need a nop before loading from $gp. This special
9886 check is required because the lui which starts the main
9887 instruction stream does not refer to $gp, and so will not
9888 insert the nop which may be required. */
9889 macro_build (NULL
, "nop", "");
9891 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9892 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9894 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9898 if (ex
.X_add_number
!= 0)
9900 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9901 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9902 ex
.X_op
= O_constant
;
9903 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9911 if (!mips_opts
.at
&& *used_at
== 1)
9912 as_bad (_("macro used $at after \".set noat\""));
9915 /* Move the contents of register SOURCE into register DEST. */
9918 move_register (int dest
, int source
)
9920 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9921 instruction specifically requires a 32-bit one. */
9922 if (mips_opts
.micromips
9923 && !mips_opts
.insn32
9924 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9925 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9927 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9930 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9931 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9932 The two alternatives are:
9934 Global symbol Local symbol
9935 ------------- ------------
9936 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9938 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9940 load_got_offset emits the first instruction and add_got_offset
9941 emits the second for a 16-bit offset or add_got_offset_hilo emits
9942 a sequence to add a 32-bit offset using a scratch register. */
9945 load_got_offset (int dest
, expressionS
*local
)
9950 global
.X_add_number
= 0;
9952 relax_start (local
->X_add_symbol
);
9953 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9954 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9956 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9957 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9962 add_got_offset (int dest
, expressionS
*local
)
9966 global
.X_op
= O_constant
;
9967 global
.X_op_symbol
= NULL
;
9968 global
.X_add_symbol
= NULL
;
9969 global
.X_add_number
= local
->X_add_number
;
9971 relax_start (local
->X_add_symbol
);
9972 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9973 dest
, dest
, BFD_RELOC_LO16
);
9975 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9980 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9983 int hold_mips_optimize
;
9985 global
.X_op
= O_constant
;
9986 global
.X_op_symbol
= NULL
;
9987 global
.X_add_symbol
= NULL
;
9988 global
.X_add_number
= local
->X_add_number
;
9990 relax_start (local
->X_add_symbol
);
9991 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9993 /* Set mips_optimize around the lui instruction to avoid
9994 inserting an unnecessary nop after the lw. */
9995 hold_mips_optimize
= mips_optimize
;
9997 macro_build_lui (&global
, tmp
);
9998 mips_optimize
= hold_mips_optimize
;
9999 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
10002 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10005 /* Emit a sequence of instructions to emulate a branch likely operation.
10006 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10007 is its complementing branch with the original condition negated.
10008 CALL is set if the original branch specified the link operation.
10009 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10011 Code like this is produced in the noreorder mode:
10016 delay slot (executed only if branch taken)
10019 or, if CALL is set:
10024 delay slot (executed only if branch taken)
10027 In the reorder mode the delay slot would be filled with a nop anyway,
10028 so code produced is simply:
10033 This function is used when producing code for the microMIPS ASE that
10034 does not implement branch likely instructions in hardware. */
10037 macro_build_branch_likely (const char *br
, const char *brneg
,
10038 int call
, expressionS
*ep
, const char *fmt
,
10039 unsigned int sreg
, unsigned int treg
)
10041 int noreorder
= mips_opts
.noreorder
;
10044 gas_assert (mips_opts
.micromips
);
10045 start_noreorder ();
10048 micromips_label_expr (&expr1
);
10049 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10050 macro_build (NULL
, "nop", "");
10051 macro_build (ep
, call
? "bal" : "b", "p");
10053 /* Set to true so that append_insn adds a label. */
10054 emit_branch_likely_macro
= TRUE
;
10058 macro_build (ep
, br
, fmt
, sreg
, treg
);
10059 macro_build (NULL
, "nop", "");
10064 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10065 the condition code tested. EP specifies the branch target. */
10068 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10070 const int call
= 0;
10095 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10098 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10099 the register tested. EP specifies the branch target. */
10102 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10104 const char *brneg
= NULL
;
10114 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10118 gas_assert (mips_opts
.micromips
);
10119 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10127 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10134 br
= mips_opts
.micromips
? "blez" : "blezl";
10141 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10145 gas_assert (mips_opts
.micromips
);
10146 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10153 if (mips_opts
.micromips
&& brneg
)
10154 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10156 macro_build (ep
, br
, "s,p", sreg
);
10159 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10160 TREG as the registers tested. EP specifies the branch target. */
10163 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10164 unsigned int sreg
, unsigned int treg
)
10166 const char *brneg
= NULL
;
10167 const int call
= 0;
10178 br
= mips_opts
.micromips
? "beq" : "beql";
10187 br
= mips_opts
.micromips
? "bne" : "bnel";
10193 if (mips_opts
.micromips
&& brneg
)
10194 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10196 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10199 /* Return the high part that should be loaded in order to make the low
10200 part of VALUE accessible using an offset of OFFBITS bits. */
10203 offset_high_part (offsetT value
, unsigned int offbits
)
10210 bias
= 1 << (offbits
- 1);
10211 low_mask
= bias
* 2 - 1;
10212 return (value
+ bias
) & ~low_mask
;
10215 /* Return true if the value stored in offset_expr and offset_reloc
10216 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10217 amount that the caller wants to add without inducing overflow
10218 and ALIGN is the known alignment of the value in bytes. */
10221 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10225 /* Accept any relocation operator if overflow isn't a concern. */
10226 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10229 /* These relocations are guaranteed not to overflow in correct links. */
10230 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10231 || gprel16_reloc_p (*offset_reloc
))
10234 if (offset_expr
.X_op
== O_constant
10235 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10236 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10243 * This routine implements the seemingly endless macro or synthesized
10244 * instructions and addressing modes in the mips assembly language. Many
10245 * of these macros are simple and are similar to each other. These could
10246 * probably be handled by some kind of table or grammar approach instead of
10247 * this verbose method. Others are not simple macros but are more like
10248 * optimizing code generation.
10249 * One interesting optimization is when several store macros appear
10250 * consecutively that would load AT with the upper half of the same address.
10251 * The ensuing load upper instructions are omitted. This implies some kind
10252 * of global optimization. We currently only optimize within a single macro.
10253 * For many of the load and store macros if the address is specified as a
10254 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10255 * first load register 'at' with zero and use it as the base register. The
10256 * mips assembler simply uses register $zero. Just one tiny optimization
10260 macro (struct mips_cl_insn
*ip
, char *str
)
10262 const struct mips_operand_array
*operands
;
10263 unsigned int breg
, i
;
10264 unsigned int tempreg
;
10267 expressionS label_expr
;
10282 bfd_boolean large_offset
;
10284 int hold_mips_optimize
;
10285 unsigned int align
;
10286 unsigned int op
[MAX_OPERANDS
];
10288 gas_assert (! mips_opts
.mips16
);
10290 operands
= insn_operands (ip
);
10291 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10292 if (operands
->operand
[i
])
10293 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10297 mask
= ip
->insn_mo
->mask
;
10299 label_expr
.X_op
= O_constant
;
10300 label_expr
.X_op_symbol
= NULL
;
10301 label_expr
.X_add_symbol
= NULL
;
10302 label_expr
.X_add_number
= 0;
10304 expr1
.X_op
= O_constant
;
10305 expr1
.X_op_symbol
= NULL
;
10306 expr1
.X_add_symbol
= NULL
;
10307 expr1
.X_add_number
= 1;
10314 /* Fall through. */
10322 start_noreorder ();
10324 if (mips_opts
.micromips
)
10325 micromips_label_expr (&label_expr
);
10327 label_expr
.X_add_number
= 8;
10328 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10329 if (op
[0] == op
[1])
10330 macro_build (NULL
, "nop", "");
10332 move_register (op
[0], op
[1]);
10333 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10334 if (mips_opts
.micromips
)
10335 micromips_add_label ();
10352 if (!mips_opts
.micromips
)
10354 if (imm_expr
.X_add_number
>= -0x200
10355 && imm_expr
.X_add_number
< 0x200)
10357 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10358 (int) imm_expr
.X_add_number
);
10367 if (imm_expr
.X_add_number
>= -0x8000
10368 && imm_expr
.X_add_number
< 0x8000)
10370 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10375 load_register (AT
, &imm_expr
, dbl
);
10376 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10395 if (imm_expr
.X_add_number
>= 0
10396 && imm_expr
.X_add_number
< 0x10000)
10398 if (mask
!= M_NOR_I
)
10399 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10402 macro_build (&imm_expr
, "ori", "t,r,i",
10403 op
[0], op
[1], BFD_RELOC_LO16
);
10404 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10410 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10411 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10415 switch (imm_expr
.X_add_number
)
10418 macro_build (NULL
, "nop", "");
10421 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10425 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10426 (int) imm_expr
.X_add_number
);
10429 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10430 (unsigned long) imm_expr
.X_add_number
);
10439 gas_assert (mips_opts
.micromips
);
10440 macro_build_branch_ccl (mask
, &offset_expr
,
10441 EXTRACT_OPERAND (1, BCC
, *ip
));
10448 if (imm_expr
.X_add_number
== 0)
10454 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10456 /* Fall through. */
10459 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10464 /* Fall through. */
10467 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10468 else if (op
[0] == 0)
10469 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10473 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10474 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10475 &offset_expr
, AT
, ZERO
);
10485 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10490 /* Fall through. */
10492 /* Check for > max integer. */
10493 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10496 /* Result is always false. */
10498 macro_build (NULL
, "nop", "");
10500 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10503 ++imm_expr
.X_add_number
;
10504 /* Fall through. */
10507 if (mask
== M_BGEL_I
)
10509 if (imm_expr
.X_add_number
== 0)
10511 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10512 &offset_expr
, op
[0]);
10515 if (imm_expr
.X_add_number
== 1)
10517 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10518 &offset_expr
, op
[0]);
10521 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10524 /* Result is always true. */
10525 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10526 macro_build (&offset_expr
, "b", "p");
10531 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10532 &offset_expr
, AT
, ZERO
);
10537 /* Fall through. */
10541 else if (op
[0] == 0)
10542 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10543 &offset_expr
, ZERO
, op
[1]);
10547 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10548 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10549 &offset_expr
, AT
, ZERO
);
10555 /* Fall through. */
10559 && imm_expr
.X_add_number
== -1))
10561 ++imm_expr
.X_add_number
;
10562 /* Fall through. */
10565 if (mask
== M_BGEUL_I
)
10567 if (imm_expr
.X_add_number
== 0)
10569 else if (imm_expr
.X_add_number
== 1)
10570 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10571 &offset_expr
, op
[0], ZERO
);
10576 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10577 &offset_expr
, AT
, ZERO
);
10583 /* Fall through. */
10586 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10587 else if (op
[0] == 0)
10588 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10592 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10593 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10594 &offset_expr
, AT
, ZERO
);
10600 /* Fall through. */
10603 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10604 &offset_expr
, op
[0], ZERO
);
10605 else if (op
[0] == 0)
10610 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10611 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10612 &offset_expr
, AT
, ZERO
);
10618 /* Fall through. */
10621 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10622 else if (op
[0] == 0)
10623 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10627 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10628 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10629 &offset_expr
, AT
, ZERO
);
10635 /* Fall through. */
10637 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10639 ++imm_expr
.X_add_number
;
10640 /* Fall through. */
10643 if (mask
== M_BLTL_I
)
10645 if (imm_expr
.X_add_number
== 0)
10646 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10647 else if (imm_expr
.X_add_number
== 1)
10648 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10653 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10654 &offset_expr
, AT
, ZERO
);
10660 /* Fall through. */
10663 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10664 &offset_expr
, op
[0], ZERO
);
10665 else if (op
[0] == 0)
10670 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10671 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10672 &offset_expr
, AT
, ZERO
);
10678 /* Fall through. */
10682 && imm_expr
.X_add_number
== -1))
10684 ++imm_expr
.X_add_number
;
10685 /* Fall through. */
10688 if (mask
== M_BLTUL_I
)
10690 if (imm_expr
.X_add_number
== 0)
10692 else if (imm_expr
.X_add_number
== 1)
10693 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10694 &offset_expr
, op
[0], ZERO
);
10699 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10700 &offset_expr
, AT
, ZERO
);
10706 /* Fall through. */
10709 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10710 else if (op
[0] == 0)
10711 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10715 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10716 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10717 &offset_expr
, AT
, ZERO
);
10723 /* Fall through. */
10727 else if (op
[0] == 0)
10728 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10729 &offset_expr
, ZERO
, op
[1]);
10733 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10734 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10735 &offset_expr
, AT
, ZERO
);
10741 /* Fall through. */
10747 /* Fall through. */
10753 as_warn (_("divide by zero"));
10755 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10757 macro_build (NULL
, "break", BRK_FMT
, 7);
10761 start_noreorder ();
10764 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10765 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10769 if (mips_opts
.micromips
)
10770 micromips_label_expr (&label_expr
);
10772 label_expr
.X_add_number
= 8;
10773 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10774 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10775 macro_build (NULL
, "break", BRK_FMT
, 7);
10776 if (mips_opts
.micromips
)
10777 micromips_add_label ();
10779 expr1
.X_add_number
= -1;
10781 load_register (AT
, &expr1
, dbl
);
10782 if (mips_opts
.micromips
)
10783 micromips_label_expr (&label_expr
);
10785 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10786 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10789 expr1
.X_add_number
= 1;
10790 load_register (AT
, &expr1
, dbl
);
10791 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10795 expr1
.X_add_number
= 0x80000000;
10796 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10800 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10801 /* We want to close the noreorder block as soon as possible, so
10802 that later insns are available for delay slot filling. */
10807 if (mips_opts
.micromips
)
10808 micromips_label_expr (&label_expr
);
10810 label_expr
.X_add_number
= 8;
10811 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10812 macro_build (NULL
, "nop", "");
10814 /* We want to close the noreorder block as soon as possible, so
10815 that later insns are available for delay slot filling. */
10818 macro_build (NULL
, "break", BRK_FMT
, 6);
10820 if (mips_opts
.micromips
)
10821 micromips_add_label ();
10822 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10861 if (imm_expr
.X_add_number
== 0)
10863 as_warn (_("divide by zero"));
10865 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10867 macro_build (NULL
, "break", BRK_FMT
, 7);
10870 if (imm_expr
.X_add_number
== 1)
10872 if (strcmp (s2
, "mflo") == 0)
10873 move_register (op
[0], op
[1]);
10875 move_register (op
[0], ZERO
);
10878 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10880 if (strcmp (s2
, "mflo") == 0)
10881 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10883 move_register (op
[0], ZERO
);
10888 load_register (AT
, &imm_expr
, dbl
);
10889 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10890 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10909 start_noreorder ();
10912 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10913 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10914 /* We want to close the noreorder block as soon as possible, so
10915 that later insns are available for delay slot filling. */
10920 if (mips_opts
.micromips
)
10921 micromips_label_expr (&label_expr
);
10923 label_expr
.X_add_number
= 8;
10924 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10925 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10927 /* We want to close the noreorder block as soon as possible, so
10928 that later insns are available for delay slot filling. */
10930 macro_build (NULL
, "break", BRK_FMT
, 7);
10931 if (mips_opts
.micromips
)
10932 micromips_add_label ();
10934 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10939 /* Fall through. */
10945 /* Fall through. */
10948 /* Load the address of a symbol into a register. If breg is not
10949 zero, we then add a base register to it. */
10952 if (dbl
&& GPR_SIZE
== 32)
10953 as_warn (_("dla used to load 32-bit register; recommend using la "
10956 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10957 as_warn (_("la used to load 64-bit address; recommend using dla "
10960 if (small_offset_p (0, align
, 16))
10962 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10963 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10967 if (mips_opts
.at
&& (op
[0] == breg
))
10975 if (offset_expr
.X_op
!= O_symbol
10976 && offset_expr
.X_op
!= O_constant
)
10978 as_bad (_("expression too complex"));
10979 offset_expr
.X_op
= O_constant
;
10982 if (offset_expr
.X_op
== O_constant
)
10983 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10984 else if (mips_pic
== NO_PIC
)
10986 /* If this is a reference to a GP relative symbol, we want
10987 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10989 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10990 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10991 If we have a constant, we need two instructions anyhow,
10992 so we may as well always use the latter form.
10994 With 64bit address space and a usable $at we want
10995 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10996 lui $at,<sym> (BFD_RELOC_HI16_S)
10997 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10998 daddiu $at,<sym> (BFD_RELOC_LO16)
11000 daddu $tempreg,$tempreg,$at
11002 If $at is already in use, we use a path which is suboptimal
11003 on superscalar processors.
11004 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11005 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11007 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11009 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11011 For GP relative symbols in 64bit address space we can use
11012 the same sequence as in 32bit address space. */
11013 if (HAVE_64BIT_SYMBOLS
)
11015 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11016 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11018 relax_start (offset_expr
.X_add_symbol
);
11019 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11020 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11024 if (used_at
== 0 && mips_opts
.at
)
11026 macro_build (&offset_expr
, "lui", LUI_FMT
,
11027 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11028 macro_build (&offset_expr
, "lui", LUI_FMT
,
11029 AT
, BFD_RELOC_HI16_S
);
11030 macro_build (&offset_expr
, "daddiu", "t,r,j",
11031 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11032 macro_build (&offset_expr
, "daddiu", "t,r,j",
11033 AT
, AT
, BFD_RELOC_LO16
);
11034 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11035 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11040 macro_build (&offset_expr
, "lui", LUI_FMT
,
11041 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11042 macro_build (&offset_expr
, "daddiu", "t,r,j",
11043 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11044 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11045 macro_build (&offset_expr
, "daddiu", "t,r,j",
11046 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11047 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11048 macro_build (&offset_expr
, "daddiu", "t,r,j",
11049 tempreg
, tempreg
, BFD_RELOC_LO16
);
11052 if (mips_relax
.sequence
)
11057 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11058 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11060 relax_start (offset_expr
.X_add_symbol
);
11061 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11062 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11065 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11066 as_bad (_("offset too large"));
11067 macro_build_lui (&offset_expr
, tempreg
);
11068 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11069 tempreg
, tempreg
, BFD_RELOC_LO16
);
11070 if (mips_relax
.sequence
)
11074 else if (!mips_big_got
&& !HAVE_NEWABI
)
11076 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11078 /* If this is a reference to an external symbol, and there
11079 is no constant, we want
11080 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11081 or for lca or if tempreg is PIC_CALL_REG
11082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11083 For a local symbol, we want
11084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11086 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11088 If we have a small constant, and this is a reference to
11089 an external symbol, we want
11090 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11092 addiu $tempreg,$tempreg,<constant>
11093 For a local symbol, we want the same instruction
11094 sequence, but we output a BFD_RELOC_LO16 reloc on the
11097 If we have a large constant, and this is a reference to
11098 an external symbol, we want
11099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11100 lui $at,<hiconstant>
11101 addiu $at,$at,<loconstant>
11102 addu $tempreg,$tempreg,$at
11103 For a local symbol, we want the same instruction
11104 sequence, but we output a BFD_RELOC_LO16 reloc on the
11108 if (offset_expr
.X_add_number
== 0)
11110 if (mips_pic
== SVR4_PIC
11112 && (call
|| tempreg
== PIC_CALL_REG
))
11113 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11115 relax_start (offset_expr
.X_add_symbol
);
11116 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11117 lw_reloc_type
, mips_gp_register
);
11120 /* We're going to put in an addu instruction using
11121 tempreg, so we may as well insert the nop right
11126 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11127 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11129 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11130 tempreg
, tempreg
, BFD_RELOC_LO16
);
11132 /* FIXME: If breg == 0, and the next instruction uses
11133 $tempreg, then if this variant case is used an extra
11134 nop will be generated. */
11136 else if (offset_expr
.X_add_number
>= -0x8000
11137 && offset_expr
.X_add_number
< 0x8000)
11139 load_got_offset (tempreg
, &offset_expr
);
11141 add_got_offset (tempreg
, &offset_expr
);
11145 expr1
.X_add_number
= offset_expr
.X_add_number
;
11146 offset_expr
.X_add_number
=
11147 SEXT_16BIT (offset_expr
.X_add_number
);
11148 load_got_offset (tempreg
, &offset_expr
);
11149 offset_expr
.X_add_number
= expr1
.X_add_number
;
11150 /* If we are going to add in a base register, and the
11151 target register and the base register are the same,
11152 then we are using AT as a temporary register. Since
11153 we want to load the constant into AT, we add our
11154 current AT (from the global offset table) and the
11155 register into the register now, and pretend we were
11156 not using a base register. */
11160 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11165 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11169 else if (!mips_big_got
&& HAVE_NEWABI
)
11171 int add_breg_early
= 0;
11173 /* If this is a reference to an external, and there is no
11174 constant, or local symbol (*), with or without a
11176 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11177 or for lca or if tempreg is PIC_CALL_REG
11178 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11180 If we have a small constant, and this is a reference to
11181 an external symbol, we want
11182 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11183 addiu $tempreg,$tempreg,<constant>
11185 If we have a large constant, and this is a reference to
11186 an external symbol, we want
11187 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11188 lui $at,<hiconstant>
11189 addiu $at,$at,<loconstant>
11190 addu $tempreg,$tempreg,$at
11192 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11193 local symbols, even though it introduces an additional
11196 if (offset_expr
.X_add_number
)
11198 expr1
.X_add_number
= offset_expr
.X_add_number
;
11199 offset_expr
.X_add_number
= 0;
11201 relax_start (offset_expr
.X_add_symbol
);
11202 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11203 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11205 if (expr1
.X_add_number
>= -0x8000
11206 && expr1
.X_add_number
< 0x8000)
11208 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11209 tempreg
, tempreg
, BFD_RELOC_LO16
);
11211 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11215 /* If we are going to add in a base register, and the
11216 target register and the base register are the same,
11217 then we are using AT as a temporary register. Since
11218 we want to load the constant into AT, we add our
11219 current AT (from the global offset table) and the
11220 register into the register now, and pretend we were
11221 not using a base register. */
11226 gas_assert (tempreg
== AT
);
11227 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11230 add_breg_early
= 1;
11233 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11234 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11240 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11243 offset_expr
.X_add_number
= expr1
.X_add_number
;
11245 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11246 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11247 if (add_breg_early
)
11249 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11250 op
[0], tempreg
, breg
);
11256 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11258 relax_start (offset_expr
.X_add_symbol
);
11259 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11260 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11262 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11263 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11268 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11269 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11272 else if (mips_big_got
&& !HAVE_NEWABI
)
11275 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11276 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11277 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11279 /* This is the large GOT case. If this is a reference to an
11280 external symbol, and there is no constant, we want
11281 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11282 addu $tempreg,$tempreg,$gp
11283 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11284 or for lca or if tempreg is PIC_CALL_REG
11285 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11286 addu $tempreg,$tempreg,$gp
11287 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11288 For a local symbol, we want
11289 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11291 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11293 If we have a small constant, and this is a reference to
11294 an external symbol, we want
11295 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11296 addu $tempreg,$tempreg,$gp
11297 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11299 addiu $tempreg,$tempreg,<constant>
11300 For a local symbol, we want
11301 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11303 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11305 If we have a large constant, and this is a reference to
11306 an external symbol, we want
11307 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11308 addu $tempreg,$tempreg,$gp
11309 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11310 lui $at,<hiconstant>
11311 addiu $at,$at,<loconstant>
11312 addu $tempreg,$tempreg,$at
11313 For a local symbol, we want
11314 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11315 lui $at,<hiconstant>
11316 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11317 addu $tempreg,$tempreg,$at
11320 expr1
.X_add_number
= offset_expr
.X_add_number
;
11321 offset_expr
.X_add_number
= 0;
11322 relax_start (offset_expr
.X_add_symbol
);
11323 gpdelay
= reg_needs_delay (mips_gp_register
);
11324 if (expr1
.X_add_number
== 0 && breg
== 0
11325 && (call
|| tempreg
== PIC_CALL_REG
))
11327 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11328 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11330 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11331 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11332 tempreg
, tempreg
, mips_gp_register
);
11333 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11334 tempreg
, lw_reloc_type
, tempreg
);
11335 if (expr1
.X_add_number
== 0)
11339 /* We're going to put in an addu instruction using
11340 tempreg, so we may as well insert the nop right
11345 else if (expr1
.X_add_number
>= -0x8000
11346 && expr1
.X_add_number
< 0x8000)
11349 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11350 tempreg
, tempreg
, BFD_RELOC_LO16
);
11356 /* If we are going to add in a base register, and the
11357 target register and the base register are the same,
11358 then we are using AT as a temporary register. Since
11359 we want to load the constant into AT, we add our
11360 current AT (from the global offset table) and the
11361 register into the register now, and pretend we were
11362 not using a base register. */
11367 gas_assert (tempreg
== AT
);
11369 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11374 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11375 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11379 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11384 /* This is needed because this instruction uses $gp, but
11385 the first instruction on the main stream does not. */
11386 macro_build (NULL
, "nop", "");
11389 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11390 local_reloc_type
, mips_gp_register
);
11391 if (expr1
.X_add_number
>= -0x8000
11392 && expr1
.X_add_number
< 0x8000)
11395 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11396 tempreg
, tempreg
, BFD_RELOC_LO16
);
11397 /* FIXME: If add_number is 0, and there was no base
11398 register, the external symbol case ended with a load,
11399 so if the symbol turns out to not be external, and
11400 the next instruction uses tempreg, an unnecessary nop
11401 will be inserted. */
11407 /* We must add in the base register now, as in the
11408 external symbol case. */
11409 gas_assert (tempreg
== AT
);
11411 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11414 /* We set breg to 0 because we have arranged to add
11415 it in in both cases. */
11419 macro_build_lui (&expr1
, AT
);
11420 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11421 AT
, AT
, BFD_RELOC_LO16
);
11422 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11423 tempreg
, tempreg
, AT
);
11428 else if (mips_big_got
&& HAVE_NEWABI
)
11430 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11431 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11432 int add_breg_early
= 0;
11434 /* This is the large GOT case. If this is a reference to an
11435 external symbol, and there is no constant, we want
11436 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11437 add $tempreg,$tempreg,$gp
11438 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11439 or for lca or if tempreg is PIC_CALL_REG
11440 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11441 add $tempreg,$tempreg,$gp
11442 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11444 If we have a small constant, and this is a reference to
11445 an external symbol, we want
11446 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11447 add $tempreg,$tempreg,$gp
11448 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11449 addi $tempreg,$tempreg,<constant>
11451 If we have a large constant, and this is a reference to
11452 an external symbol, we want
11453 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11454 addu $tempreg,$tempreg,$gp
11455 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11456 lui $at,<hiconstant>
11457 addi $at,$at,<loconstant>
11458 add $tempreg,$tempreg,$at
11460 If we have NewABI, and we know it's a local symbol, we want
11461 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11462 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11463 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11465 relax_start (offset_expr
.X_add_symbol
);
11467 expr1
.X_add_number
= offset_expr
.X_add_number
;
11468 offset_expr
.X_add_number
= 0;
11470 if (expr1
.X_add_number
== 0 && breg
== 0
11471 && (call
|| tempreg
== PIC_CALL_REG
))
11473 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11474 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11476 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11477 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11478 tempreg
, tempreg
, mips_gp_register
);
11479 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11480 tempreg
, lw_reloc_type
, tempreg
);
11482 if (expr1
.X_add_number
== 0)
11484 else if (expr1
.X_add_number
>= -0x8000
11485 && expr1
.X_add_number
< 0x8000)
11487 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11488 tempreg
, tempreg
, BFD_RELOC_LO16
);
11490 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11494 /* If we are going to add in a base register, and the
11495 target register and the base register are the same,
11496 then we are using AT as a temporary register. Since
11497 we want to load the constant into AT, we add our
11498 current AT (from the global offset table) and the
11499 register into the register now, and pretend we were
11500 not using a base register. */
11505 gas_assert (tempreg
== AT
);
11506 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11509 add_breg_early
= 1;
11512 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11513 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11518 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11521 offset_expr
.X_add_number
= expr1
.X_add_number
;
11522 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11523 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11524 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11525 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11526 if (add_breg_early
)
11528 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11529 op
[0], tempreg
, breg
);
11539 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11543 gas_assert (!mips_opts
.micromips
);
11544 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11548 gas_assert (!mips_opts
.micromips
);
11549 macro_build (NULL
, "c2", "C", 0x02);
11553 gas_assert (!mips_opts
.micromips
);
11554 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11558 gas_assert (!mips_opts
.micromips
);
11559 macro_build (NULL
, "c2", "C", 3);
11563 gas_assert (!mips_opts
.micromips
);
11564 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11568 /* The j instruction may not be used in PIC code, since it
11569 requires an absolute address. We convert it to a b
11571 if (mips_pic
== NO_PIC
)
11572 macro_build (&offset_expr
, "j", "a");
11574 macro_build (&offset_expr
, "b", "p");
11577 /* The jal instructions must be handled as macros because when
11578 generating PIC code they expand to multi-instruction
11579 sequences. Normally they are simple instructions. */
11583 /* Fall through. */
11585 gas_assert (mips_opts
.micromips
);
11586 if (mips_opts
.insn32
)
11588 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11596 /* Fall through. */
11599 if (mips_pic
== NO_PIC
)
11601 s
= jals
? "jalrs" : "jalr";
11602 if (mips_opts
.micromips
11603 && !mips_opts
.insn32
11605 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11606 macro_build (NULL
, s
, "mj", op
[1]);
11608 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11612 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11613 && mips_cprestore_offset
>= 0);
11615 if (op
[1] != PIC_CALL_REG
)
11616 as_warn (_("MIPS PIC call to register other than $25"));
11618 s
= ((mips_opts
.micromips
11619 && !mips_opts
.insn32
11620 && (!mips_opts
.noreorder
|| cprestore
))
11621 ? "jalrs" : "jalr");
11622 if (mips_opts
.micromips
11623 && !mips_opts
.insn32
11625 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11626 macro_build (NULL
, s
, "mj", op
[1]);
11628 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11629 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11631 if (mips_cprestore_offset
< 0)
11632 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11635 if (!mips_frame_reg_valid
)
11637 as_warn (_("no .frame pseudo-op used in PIC code"));
11638 /* Quiet this warning. */
11639 mips_frame_reg_valid
= 1;
11641 if (!mips_cprestore_valid
)
11643 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11644 /* Quiet this warning. */
11645 mips_cprestore_valid
= 1;
11647 if (mips_opts
.noreorder
)
11648 macro_build (NULL
, "nop", "");
11649 expr1
.X_add_number
= mips_cprestore_offset
;
11650 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11653 HAVE_64BIT_ADDRESSES
);
11661 gas_assert (mips_opts
.micromips
);
11662 if (mips_opts
.insn32
)
11664 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11668 /* Fall through. */
11670 if (mips_pic
== NO_PIC
)
11671 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11672 else if (mips_pic
== SVR4_PIC
)
11674 /* If this is a reference to an external symbol, and we are
11675 using a small GOT, we want
11676 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11680 lw $gp,cprestore($sp)
11681 The cprestore value is set using the .cprestore
11682 pseudo-op. If we are using a big GOT, we want
11683 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11685 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11689 lw $gp,cprestore($sp)
11690 If the symbol is not external, we want
11691 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11693 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11696 lw $gp,cprestore($sp)
11698 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11699 sequences above, minus nops, unless the symbol is local,
11700 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11706 relax_start (offset_expr
.X_add_symbol
);
11707 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11708 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11711 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11712 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11718 relax_start (offset_expr
.X_add_symbol
);
11719 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11720 BFD_RELOC_MIPS_CALL_HI16
);
11721 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11722 PIC_CALL_REG
, mips_gp_register
);
11723 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11724 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11727 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11728 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11730 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11731 PIC_CALL_REG
, PIC_CALL_REG
,
11732 BFD_RELOC_MIPS_GOT_OFST
);
11736 macro_build_jalr (&offset_expr
, 0);
11740 relax_start (offset_expr
.X_add_symbol
);
11743 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11744 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11753 gpdelay
= reg_needs_delay (mips_gp_register
);
11754 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11755 BFD_RELOC_MIPS_CALL_HI16
);
11756 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11757 PIC_CALL_REG
, mips_gp_register
);
11758 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11759 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11764 macro_build (NULL
, "nop", "");
11766 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11767 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11770 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11771 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11773 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11775 if (mips_cprestore_offset
< 0)
11776 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11779 if (!mips_frame_reg_valid
)
11781 as_warn (_("no .frame pseudo-op used in PIC code"));
11782 /* Quiet this warning. */
11783 mips_frame_reg_valid
= 1;
11785 if (!mips_cprestore_valid
)
11787 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11788 /* Quiet this warning. */
11789 mips_cprestore_valid
= 1;
11791 if (mips_opts
.noreorder
)
11792 macro_build (NULL
, "nop", "");
11793 expr1
.X_add_number
= mips_cprestore_offset
;
11794 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11797 HAVE_64BIT_ADDRESSES
);
11801 else if (mips_pic
== VXWORKS_PIC
)
11802 as_bad (_("non-PIC jump used in PIC library"));
11909 gas_assert (!mips_opts
.micromips
);
11912 /* Itbl support may require additional care here. */
11918 /* Itbl support may require additional care here. */
11924 offbits
= (mips_opts
.micromips
? 12
11925 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11927 /* Itbl support may require additional care here. */
11931 gas_assert (!mips_opts
.micromips
);
11934 /* Itbl support may require additional care here. */
11940 offbits
= (mips_opts
.micromips
? 12 : 16);
11945 offbits
= (mips_opts
.micromips
? 12 : 16);
11950 /* Itbl support may require additional care here. */
11956 offbits
= (mips_opts
.micromips
? 12
11957 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11959 /* Itbl support may require additional care here. */
11965 /* Itbl support may require additional care here. */
11971 /* Itbl support may require additional care here. */
11977 offbits
= (mips_opts
.micromips
? 12 : 16);
11982 offbits
= (mips_opts
.micromips
? 12 : 16);
11987 offbits
= (mips_opts
.micromips
? 12
11988 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11994 offbits
= (mips_opts
.micromips
? 12
11995 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12001 offbits
= (mips_opts
.micromips
? 12 : 16);
12004 gas_assert (mips_opts
.micromips
);
12011 gas_assert (mips_opts
.micromips
);
12018 gas_assert (mips_opts
.micromips
);
12024 gas_assert (mips_opts
.micromips
);
12031 /* We don't want to use $0 as tempreg. */
12032 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12035 tempreg
= op
[0] + lp
;
12051 gas_assert (!mips_opts
.micromips
);
12054 /* Itbl support may require additional care here. */
12060 /* Itbl support may require additional care here. */
12066 offbits
= (mips_opts
.micromips
? 12
12067 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12069 /* Itbl support may require additional care here. */
12073 gas_assert (!mips_opts
.micromips
);
12076 /* Itbl support may require additional care here. */
12082 offbits
= (mips_opts
.micromips
? 12 : 16);
12087 offbits
= (mips_opts
.micromips
? 12 : 16);
12092 offbits
= (mips_opts
.micromips
? 12
12093 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12099 offbits
= (mips_opts
.micromips
? 12
12100 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12105 fmt
= (mips_opts
.micromips
? "k,~(b)"
12106 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12108 offbits
= (mips_opts
.micromips
? 12
12109 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12119 fmt
= (mips_opts
.micromips
? "k,~(b)"
12120 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12122 offbits
= (mips_opts
.micromips
? 12
12123 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12135 /* Itbl support may require additional care here. */
12140 offbits
= (mips_opts
.micromips
? 12
12141 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12143 /* Itbl support may require additional care here. */
12149 /* Itbl support may require additional care here. */
12153 gas_assert (!mips_opts
.micromips
);
12156 /* Itbl support may require additional care here. */
12162 offbits
= (mips_opts
.micromips
? 12 : 16);
12167 offbits
= (mips_opts
.micromips
? 12 : 16);
12170 gas_assert (mips_opts
.micromips
);
12176 gas_assert (mips_opts
.micromips
);
12182 gas_assert (mips_opts
.micromips
);
12188 gas_assert (mips_opts
.micromips
);
12197 if (small_offset_p (0, align
, 16))
12199 /* The first case exists for M_LD_AB and M_SD_AB, which are
12200 macros for o32 but which should act like normal instructions
12203 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12204 offset_reloc
[1], offset_reloc
[2], breg
);
12205 else if (small_offset_p (0, align
, offbits
))
12208 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12210 macro_build (NULL
, s
, fmt
, op
[0],
12211 (int) offset_expr
.X_add_number
, breg
);
12217 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12218 tempreg
, breg
, -1, offset_reloc
[0],
12219 offset_reloc
[1], offset_reloc
[2]);
12221 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12223 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12231 if (offset_expr
.X_op
!= O_constant
12232 && offset_expr
.X_op
!= O_symbol
)
12234 as_bad (_("expression too complex"));
12235 offset_expr
.X_op
= O_constant
;
12238 if (HAVE_32BIT_ADDRESSES
12239 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12243 sprintf_vma (value
, offset_expr
.X_add_number
);
12244 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12247 /* A constant expression in PIC code can be handled just as it
12248 is in non PIC code. */
12249 if (offset_expr
.X_op
== O_constant
)
12251 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12252 offbits
== 0 ? 16 : offbits
);
12253 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12255 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12257 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12258 tempreg
, tempreg
, breg
);
12261 if (offset_expr
.X_add_number
!= 0)
12262 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12263 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12264 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12266 else if (offbits
== 16)
12267 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12269 macro_build (NULL
, s
, fmt
, op
[0],
12270 (int) offset_expr
.X_add_number
, tempreg
);
12272 else if (offbits
!= 16)
12274 /* The offset field is too narrow to be used for a low-part
12275 relocation, so load the whole address into the auxiliary
12277 load_address (tempreg
, &offset_expr
, &used_at
);
12279 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12280 tempreg
, tempreg
, breg
);
12282 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12284 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12286 else if (mips_pic
== NO_PIC
)
12288 /* If this is a reference to a GP relative symbol, and there
12289 is no base register, we want
12290 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12291 Otherwise, if there is no base register, we want
12292 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12293 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12294 If we have a constant, we need two instructions anyhow,
12295 so we always use the latter form.
12297 If we have a base register, and this is a reference to a
12298 GP relative symbol, we want
12299 addu $tempreg,$breg,$gp
12300 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12302 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12303 addu $tempreg,$tempreg,$breg
12304 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12305 With a constant we always use the latter case.
12307 With 64bit address space and no base register and $at usable,
12309 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12310 lui $at,<sym> (BFD_RELOC_HI16_S)
12311 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12314 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12315 If we have a base register, we want
12316 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12317 lui $at,<sym> (BFD_RELOC_HI16_S)
12318 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12322 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12324 Without $at we can't generate the optimal path for superscalar
12325 processors here since this would require two temporary registers.
12326 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12327 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12329 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12331 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12332 If we have a base register, we want
12333 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12334 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12336 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12338 daddu $tempreg,$tempreg,$breg
12339 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12341 For GP relative symbols in 64bit address space we can use
12342 the same sequence as in 32bit address space. */
12343 if (HAVE_64BIT_SYMBOLS
)
12345 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12346 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12348 relax_start (offset_expr
.X_add_symbol
);
12351 macro_build (&offset_expr
, s
, fmt
, op
[0],
12352 BFD_RELOC_GPREL16
, mips_gp_register
);
12356 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12357 tempreg
, breg
, mips_gp_register
);
12358 macro_build (&offset_expr
, s
, fmt
, op
[0],
12359 BFD_RELOC_GPREL16
, tempreg
);
12364 if (used_at
== 0 && mips_opts
.at
)
12366 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12367 BFD_RELOC_MIPS_HIGHEST
);
12368 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12370 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12371 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12373 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12374 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12375 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12376 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12382 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12383 BFD_RELOC_MIPS_HIGHEST
);
12384 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12385 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12386 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12387 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12388 tempreg
, BFD_RELOC_HI16_S
);
12389 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12391 macro_build (NULL
, "daddu", "d,v,t",
12392 tempreg
, tempreg
, breg
);
12393 macro_build (&offset_expr
, s
, fmt
, op
[0],
12394 BFD_RELOC_LO16
, tempreg
);
12397 if (mips_relax
.sequence
)
12404 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12405 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12407 relax_start (offset_expr
.X_add_symbol
);
12408 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12412 macro_build_lui (&offset_expr
, tempreg
);
12413 macro_build (&offset_expr
, s
, fmt
, op
[0],
12414 BFD_RELOC_LO16
, tempreg
);
12415 if (mips_relax
.sequence
)
12420 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12421 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12423 relax_start (offset_expr
.X_add_symbol
);
12424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12425 tempreg
, breg
, mips_gp_register
);
12426 macro_build (&offset_expr
, s
, fmt
, op
[0],
12427 BFD_RELOC_GPREL16
, tempreg
);
12430 macro_build_lui (&offset_expr
, tempreg
);
12431 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12432 tempreg
, tempreg
, breg
);
12433 macro_build (&offset_expr
, s
, fmt
, op
[0],
12434 BFD_RELOC_LO16
, tempreg
);
12435 if (mips_relax
.sequence
)
12439 else if (!mips_big_got
)
12441 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12443 /* If this is a reference to an external symbol, we want
12444 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12446 <op> op[0],0($tempreg)
12448 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12450 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12451 <op> op[0],0($tempreg)
12453 For NewABI, we want
12454 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12455 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12457 If there is a base register, we add it to $tempreg before
12458 the <op>. If there is a constant, we stick it in the
12459 <op> instruction. We don't handle constants larger than
12460 16 bits, because we have no way to load the upper 16 bits
12461 (actually, we could handle them for the subset of cases
12462 in which we are not using $at). */
12463 gas_assert (offset_expr
.X_op
== O_symbol
);
12466 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12467 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12469 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12470 tempreg
, tempreg
, breg
);
12471 macro_build (&offset_expr
, s
, fmt
, op
[0],
12472 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12475 expr1
.X_add_number
= offset_expr
.X_add_number
;
12476 offset_expr
.X_add_number
= 0;
12477 if (expr1
.X_add_number
< -0x8000
12478 || expr1
.X_add_number
>= 0x8000)
12479 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12480 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12481 lw_reloc_type
, mips_gp_register
);
12483 relax_start (offset_expr
.X_add_symbol
);
12485 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12486 tempreg
, BFD_RELOC_LO16
);
12489 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12490 tempreg
, tempreg
, breg
);
12491 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12493 else if (mips_big_got
&& !HAVE_NEWABI
)
12497 /* If this is a reference to an external symbol, we want
12498 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12499 addu $tempreg,$tempreg,$gp
12500 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12501 <op> op[0],0($tempreg)
12503 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12505 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12506 <op> op[0],0($tempreg)
12507 If there is a base register, we add it to $tempreg before
12508 the <op>. If there is a constant, we stick it in the
12509 <op> instruction. We don't handle constants larger than
12510 16 bits, because we have no way to load the upper 16 bits
12511 (actually, we could handle them for the subset of cases
12512 in which we are not using $at). */
12513 gas_assert (offset_expr
.X_op
== O_symbol
);
12514 expr1
.X_add_number
= offset_expr
.X_add_number
;
12515 offset_expr
.X_add_number
= 0;
12516 if (expr1
.X_add_number
< -0x8000
12517 || expr1
.X_add_number
>= 0x8000)
12518 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12519 gpdelay
= reg_needs_delay (mips_gp_register
);
12520 relax_start (offset_expr
.X_add_symbol
);
12521 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12522 BFD_RELOC_MIPS_GOT_HI16
);
12523 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12525 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12526 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12529 macro_build (NULL
, "nop", "");
12530 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12531 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12533 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12534 tempreg
, BFD_RELOC_LO16
);
12538 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12539 tempreg
, tempreg
, breg
);
12540 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12542 else if (mips_big_got
&& HAVE_NEWABI
)
12544 /* If this is a reference to an external symbol, we want
12545 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12546 add $tempreg,$tempreg,$gp
12547 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12548 <op> op[0],<ofst>($tempreg)
12549 Otherwise, for local symbols, we want:
12550 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12551 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12552 gas_assert (offset_expr
.X_op
== O_symbol
);
12553 expr1
.X_add_number
= offset_expr
.X_add_number
;
12554 offset_expr
.X_add_number
= 0;
12555 if (expr1
.X_add_number
< -0x8000
12556 || expr1
.X_add_number
>= 0x8000)
12557 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12558 relax_start (offset_expr
.X_add_symbol
);
12559 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12560 BFD_RELOC_MIPS_GOT_HI16
);
12561 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12563 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12564 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12566 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12567 tempreg
, tempreg
, breg
);
12568 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12571 offset_expr
.X_add_number
= expr1
.X_add_number
;
12572 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12573 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12575 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12576 tempreg
, tempreg
, breg
);
12577 macro_build (&offset_expr
, s
, fmt
, op
[0],
12578 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12587 gas_assert (mips_opts
.micromips
);
12588 gas_assert (mips_opts
.insn32
);
12589 start_noreorder ();
12590 macro_build (NULL
, "jr", "s", RA
);
12591 expr1
.X_add_number
= op
[0] << 2;
12592 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12597 gas_assert (mips_opts
.micromips
);
12598 gas_assert (mips_opts
.insn32
);
12599 macro_build (NULL
, "jr", "s", op
[0]);
12600 if (mips_opts
.noreorder
)
12601 macro_build (NULL
, "nop", "");
12606 load_register (op
[0], &imm_expr
, 0);
12610 load_register (op
[0], &imm_expr
, 1);
12614 if (imm_expr
.X_op
== O_constant
)
12617 load_register (AT
, &imm_expr
, 0);
12618 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12623 gas_assert (imm_expr
.X_op
== O_absent
12624 && offset_expr
.X_op
== O_symbol
12625 && strcmp (segment_name (S_GET_SEGMENT
12626 (offset_expr
.X_add_symbol
)),
12628 && offset_expr
.X_add_number
== 0);
12629 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12630 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12635 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12636 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12637 order 32 bits of the value and the low order 32 bits are either
12638 zero or in OFFSET_EXPR. */
12639 if (imm_expr
.X_op
== O_constant
)
12641 if (GPR_SIZE
== 64)
12642 load_register (op
[0], &imm_expr
, 1);
12647 if (target_big_endian
)
12659 load_register (hreg
, &imm_expr
, 0);
12662 if (offset_expr
.X_op
== O_absent
)
12663 move_register (lreg
, 0);
12666 gas_assert (offset_expr
.X_op
== O_constant
);
12667 load_register (lreg
, &offset_expr
, 0);
12673 gas_assert (imm_expr
.X_op
== O_absent
);
12675 /* We know that sym is in the .rdata section. First we get the
12676 upper 16 bits of the address. */
12677 if (mips_pic
== NO_PIC
)
12679 macro_build_lui (&offset_expr
, AT
);
12684 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12685 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12689 /* Now we load the register(s). */
12690 if (GPR_SIZE
== 64)
12693 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12694 BFD_RELOC_LO16
, AT
);
12699 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12700 BFD_RELOC_LO16
, AT
);
12703 /* FIXME: How in the world do we deal with the possible
12705 offset_expr
.X_add_number
+= 4;
12706 macro_build (&offset_expr
, "lw", "t,o(b)",
12707 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12713 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12714 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12715 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12716 the value and the low order 32 bits are either zero or in
12718 if (imm_expr
.X_op
== O_constant
)
12721 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12722 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12723 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12726 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12727 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12728 else if (FPR_SIZE
!= 32)
12729 as_bad (_("Unable to generate `%s' compliant code "
12731 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12733 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12734 if (offset_expr
.X_op
== O_absent
)
12735 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12738 gas_assert (offset_expr
.X_op
== O_constant
);
12739 load_register (AT
, &offset_expr
, 0);
12740 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12746 gas_assert (imm_expr
.X_op
== O_absent
12747 && offset_expr
.X_op
== O_symbol
12748 && offset_expr
.X_add_number
== 0);
12749 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12750 if (strcmp (s
, ".lit8") == 0)
12752 op
[2] = mips_gp_register
;
12753 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12754 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12755 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12759 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12761 if (mips_pic
!= NO_PIC
)
12762 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12763 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12766 /* FIXME: This won't work for a 64 bit address. */
12767 macro_build_lui (&offset_expr
, AT
);
12771 offset_reloc
[0] = BFD_RELOC_LO16
;
12772 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12773 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12776 /* Fall through. */
12779 /* The MIPS assembler seems to check for X_add_number not
12780 being double aligned and generating:
12783 addiu at,at,%lo(foo+1)
12786 But, the resulting address is the same after relocation so why
12787 generate the extra instruction? */
12788 /* Itbl support may require additional care here. */
12791 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12800 gas_assert (!mips_opts
.micromips
);
12801 /* Itbl support may require additional care here. */
12804 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12824 if (GPR_SIZE
== 64)
12834 if (GPR_SIZE
== 64)
12842 /* Even on a big endian machine $fn comes before $fn+1. We have
12843 to adjust when loading from memory. We set coproc if we must
12844 load $fn+1 first. */
12845 /* Itbl support may require additional care here. */
12846 if (!target_big_endian
)
12850 if (small_offset_p (0, align
, 16))
12853 if (!small_offset_p (4, align
, 16))
12855 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12856 -1, offset_reloc
[0], offset_reloc
[1],
12858 expr1
.X_add_number
= 0;
12862 offset_reloc
[0] = BFD_RELOC_LO16
;
12863 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12864 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12866 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12868 ep
->X_add_number
+= 4;
12869 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12870 offset_reloc
[1], offset_reloc
[2], breg
);
12871 ep
->X_add_number
-= 4;
12872 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12873 offset_reloc
[1], offset_reloc
[2], breg
);
12877 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12878 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12880 ep
->X_add_number
+= 4;
12881 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12882 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12888 if (offset_expr
.X_op
!= O_symbol
12889 && offset_expr
.X_op
!= O_constant
)
12891 as_bad (_("expression too complex"));
12892 offset_expr
.X_op
= O_constant
;
12895 if (HAVE_32BIT_ADDRESSES
12896 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12900 sprintf_vma (value
, offset_expr
.X_add_number
);
12901 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12904 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12906 /* If this is a reference to a GP relative symbol, we want
12907 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12908 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12909 If we have a base register, we use this
12911 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12912 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12913 If this is not a GP relative symbol, we want
12914 lui $at,<sym> (BFD_RELOC_HI16_S)
12915 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12916 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12917 If there is a base register, we add it to $at after the
12918 lui instruction. If there is a constant, we always use
12920 if (offset_expr
.X_op
== O_symbol
12921 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12922 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12924 relax_start (offset_expr
.X_add_symbol
);
12927 tempreg
= mips_gp_register
;
12931 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12932 AT
, breg
, mips_gp_register
);
12937 /* Itbl support may require additional care here. */
12938 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12939 BFD_RELOC_GPREL16
, tempreg
);
12940 offset_expr
.X_add_number
+= 4;
12942 /* Set mips_optimize to 2 to avoid inserting an
12944 hold_mips_optimize
= mips_optimize
;
12946 /* Itbl support may require additional care here. */
12947 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12948 BFD_RELOC_GPREL16
, tempreg
);
12949 mips_optimize
= hold_mips_optimize
;
12953 offset_expr
.X_add_number
-= 4;
12956 if (offset_high_part (offset_expr
.X_add_number
, 16)
12957 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12959 load_address (AT
, &offset_expr
, &used_at
);
12960 offset_expr
.X_op
= O_constant
;
12961 offset_expr
.X_add_number
= 0;
12964 macro_build_lui (&offset_expr
, AT
);
12966 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12967 /* Itbl support may require additional care here. */
12968 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12969 BFD_RELOC_LO16
, AT
);
12970 /* FIXME: How do we handle overflow here? */
12971 offset_expr
.X_add_number
+= 4;
12972 /* Itbl support may require additional care here. */
12973 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12974 BFD_RELOC_LO16
, AT
);
12975 if (mips_relax
.sequence
)
12978 else if (!mips_big_got
)
12980 /* If this is a reference to an external symbol, we want
12981 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12984 <op> op[0]+1,4($at)
12986 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12988 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12989 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12990 If there is a base register we add it to $at before the
12991 lwc1 instructions. If there is a constant we include it
12992 in the lwc1 instructions. */
12994 expr1
.X_add_number
= offset_expr
.X_add_number
;
12995 if (expr1
.X_add_number
< -0x8000
12996 || expr1
.X_add_number
>= 0x8000 - 4)
12997 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12998 load_got_offset (AT
, &offset_expr
);
13001 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13003 /* Set mips_optimize to 2 to avoid inserting an undesired
13005 hold_mips_optimize
= mips_optimize
;
13008 /* Itbl support may require additional care here. */
13009 relax_start (offset_expr
.X_add_symbol
);
13010 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13011 BFD_RELOC_LO16
, AT
);
13012 expr1
.X_add_number
+= 4;
13013 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13014 BFD_RELOC_LO16
, AT
);
13016 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13017 BFD_RELOC_LO16
, AT
);
13018 offset_expr
.X_add_number
+= 4;
13019 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13020 BFD_RELOC_LO16
, AT
);
13023 mips_optimize
= hold_mips_optimize
;
13025 else if (mips_big_got
)
13029 /* If this is a reference to an external symbol, we want
13030 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13032 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13035 <op> op[0]+1,4($at)
13037 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13039 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13040 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13041 If there is a base register we add it to $at before the
13042 lwc1 instructions. If there is a constant we include it
13043 in the lwc1 instructions. */
13045 expr1
.X_add_number
= offset_expr
.X_add_number
;
13046 offset_expr
.X_add_number
= 0;
13047 if (expr1
.X_add_number
< -0x8000
13048 || expr1
.X_add_number
>= 0x8000 - 4)
13049 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13050 gpdelay
= reg_needs_delay (mips_gp_register
);
13051 relax_start (offset_expr
.X_add_symbol
);
13052 macro_build (&offset_expr
, "lui", LUI_FMT
,
13053 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13054 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13055 AT
, AT
, mips_gp_register
);
13056 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13057 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13060 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13061 /* Itbl support may require additional care here. */
13062 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13063 BFD_RELOC_LO16
, AT
);
13064 expr1
.X_add_number
+= 4;
13066 /* Set mips_optimize to 2 to avoid inserting an undesired
13068 hold_mips_optimize
= mips_optimize
;
13070 /* Itbl support may require additional care here. */
13071 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13072 BFD_RELOC_LO16
, AT
);
13073 mips_optimize
= hold_mips_optimize
;
13074 expr1
.X_add_number
-= 4;
13077 offset_expr
.X_add_number
= expr1
.X_add_number
;
13079 macro_build (NULL
, "nop", "");
13080 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13081 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13084 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13085 /* Itbl support may require additional care here. */
13086 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13087 BFD_RELOC_LO16
, AT
);
13088 offset_expr
.X_add_number
+= 4;
13090 /* Set mips_optimize to 2 to avoid inserting an undesired
13092 hold_mips_optimize
= mips_optimize
;
13094 /* Itbl support may require additional care here. */
13095 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13096 BFD_RELOC_LO16
, AT
);
13097 mips_optimize
= hold_mips_optimize
;
13111 gas_assert (!mips_opts
.micromips
);
13116 /* New code added to support COPZ instructions.
13117 This code builds table entries out of the macros in mip_opcodes.
13118 R4000 uses interlocks to handle coproc delays.
13119 Other chips (like the R3000) require nops to be inserted for delays.
13121 FIXME: Currently, we require that the user handle delays.
13122 In order to fill delay slots for non-interlocked chips,
13123 we must have a way to specify delays based on the coprocessor.
13124 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13125 What are the side-effects of the cop instruction?
13126 What cache support might we have and what are its effects?
13127 Both coprocessor & memory require delays. how long???
13128 What registers are read/set/modified?
13130 If an itbl is provided to interpret cop instructions,
13131 this knowledge can be encoded in the itbl spec. */
13145 gas_assert (!mips_opts
.micromips
);
13146 /* For now we just do C (same as Cz). The parameter will be
13147 stored in insn_opcode by mips_ip. */
13148 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13152 move_register (op
[0], op
[1]);
13156 gas_assert (mips_opts
.micromips
);
13157 gas_assert (mips_opts
.insn32
);
13158 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13159 micromips_to_32_reg_m_map
[op
[1]]);
13160 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13161 micromips_to_32_reg_n_map
[op
[2]]);
13166 /* Fall through. */
13168 if (mips_opts
.arch
== CPU_R5900
)
13169 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13173 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13174 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13180 /* Fall through. */
13182 /* The MIPS assembler some times generates shifts and adds. I'm
13183 not trying to be that fancy. GCC should do this for us
13186 load_register (AT
, &imm_expr
, dbl
);
13187 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13188 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13193 /* Fall through. */
13200 /* Fall through. */
13203 start_noreorder ();
13206 load_register (AT
, &imm_expr
, dbl
);
13207 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13208 op
[1], imm
? AT
: op
[2]);
13209 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13210 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13211 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13213 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13216 if (mips_opts
.micromips
)
13217 micromips_label_expr (&label_expr
);
13219 label_expr
.X_add_number
= 8;
13220 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13221 macro_build (NULL
, "nop", "");
13222 macro_build (NULL
, "break", BRK_FMT
, 6);
13223 if (mips_opts
.micromips
)
13224 micromips_add_label ();
13227 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13232 /* Fall through. */
13239 /* Fall through. */
13242 start_noreorder ();
13245 load_register (AT
, &imm_expr
, dbl
);
13246 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13247 op
[1], imm
? AT
: op
[2]);
13248 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13249 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13251 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13254 if (mips_opts
.micromips
)
13255 micromips_label_expr (&label_expr
);
13257 label_expr
.X_add_number
= 8;
13258 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13259 macro_build (NULL
, "nop", "");
13260 macro_build (NULL
, "break", BRK_FMT
, 6);
13261 if (mips_opts
.micromips
)
13262 micromips_add_label ();
13268 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13270 if (op
[0] == op
[1])
13277 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13278 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13282 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13283 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13284 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13285 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13289 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13291 if (op
[0] == op
[1])
13298 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13299 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13303 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13304 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13305 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13306 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13315 rot
= imm_expr
.X_add_number
& 0x3f;
13316 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13318 rot
= (64 - rot
) & 0x3f;
13320 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13322 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13327 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13330 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13331 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13334 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13335 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13336 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13344 rot
= imm_expr
.X_add_number
& 0x1f;
13345 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13347 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13348 (32 - rot
) & 0x1f);
13353 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13357 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13358 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13359 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13364 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13366 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13370 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13371 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13372 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13373 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13377 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13379 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13383 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13384 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13385 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13386 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13395 rot
= imm_expr
.X_add_number
& 0x3f;
13396 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13399 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13401 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13406 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13409 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13410 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13413 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13414 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13415 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13423 rot
= imm_expr
.X_add_number
& 0x1f;
13424 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13426 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13431 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13435 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13436 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13437 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13443 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13444 else if (op
[2] == 0)
13445 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13448 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13449 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13454 if (imm_expr
.X_add_number
== 0)
13456 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13461 as_warn (_("instruction %s: result is always false"),
13462 ip
->insn_mo
->name
);
13463 move_register (op
[0], 0);
13466 if (CPU_HAS_SEQ (mips_opts
.arch
)
13467 && -512 <= imm_expr
.X_add_number
13468 && imm_expr
.X_add_number
< 512)
13470 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13471 (int) imm_expr
.X_add_number
);
13474 if (imm_expr
.X_add_number
>= 0
13475 && imm_expr
.X_add_number
< 0x10000)
13476 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13477 else if (imm_expr
.X_add_number
> -0x8000
13478 && imm_expr
.X_add_number
< 0)
13480 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13481 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13482 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13484 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13487 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13488 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13493 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13494 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13497 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13500 case M_SGE
: /* X >= Y <==> not (X < Y) */
13506 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13507 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13510 case M_SGE_I
: /* X >= I <==> not (X < I). */
13512 if (imm_expr
.X_add_number
>= -0x8000
13513 && imm_expr
.X_add_number
< 0x8000)
13514 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13515 op
[0], op
[1], BFD_RELOC_LO16
);
13518 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13519 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13523 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13526 case M_SGT
: /* X > Y <==> Y < X. */
13532 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13535 case M_SGT_I
: /* X > I <==> I < X. */
13542 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13543 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13546 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13552 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13553 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13556 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13563 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13564 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13565 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13569 if (imm_expr
.X_add_number
>= -0x8000
13570 && imm_expr
.X_add_number
< 0x8000)
13572 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13577 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13578 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13582 if (imm_expr
.X_add_number
>= -0x8000
13583 && imm_expr
.X_add_number
< 0x8000)
13585 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13590 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13591 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13596 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13597 else if (op
[2] == 0)
13598 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13601 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13602 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13607 if (imm_expr
.X_add_number
== 0)
13609 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13614 as_warn (_("instruction %s: result is always true"),
13615 ip
->insn_mo
->name
);
13616 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13617 op
[0], 0, BFD_RELOC_LO16
);
13620 if (CPU_HAS_SEQ (mips_opts
.arch
)
13621 && -512 <= imm_expr
.X_add_number
13622 && imm_expr
.X_add_number
< 512)
13624 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13625 (int) imm_expr
.X_add_number
);
13628 if (imm_expr
.X_add_number
>= 0
13629 && imm_expr
.X_add_number
< 0x10000)
13631 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13634 else if (imm_expr
.X_add_number
> -0x8000
13635 && imm_expr
.X_add_number
< 0)
13637 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13638 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13639 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13641 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13644 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13645 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13650 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13651 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13654 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13669 if (!mips_opts
.micromips
)
13671 if (imm_expr
.X_add_number
> -0x200
13672 && imm_expr
.X_add_number
<= 0x200)
13674 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13675 (int) -imm_expr
.X_add_number
);
13684 if (imm_expr
.X_add_number
> -0x8000
13685 && imm_expr
.X_add_number
<= 0x8000)
13687 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13688 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13693 load_register (AT
, &imm_expr
, dbl
);
13694 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13716 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13717 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13722 gas_assert (!mips_opts
.micromips
);
13723 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13727 * Is the double cfc1 instruction a bug in the mips assembler;
13728 * or is there a reason for it?
13730 start_noreorder ();
13731 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13732 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13733 macro_build (NULL
, "nop", "");
13734 expr1
.X_add_number
= 3;
13735 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13736 expr1
.X_add_number
= 2;
13737 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13738 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13739 macro_build (NULL
, "nop", "");
13740 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13742 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13743 macro_build (NULL
, "nop", "");
13760 offbits
= (mips_opts
.micromips
? 12 : 16);
13766 offbits
= (mips_opts
.micromips
? 12 : 16);
13778 offbits
= (mips_opts
.micromips
? 12 : 16);
13785 offbits
= (mips_opts
.micromips
? 12 : 16);
13791 large_offset
= !small_offset_p (off
, align
, offbits
);
13793 expr1
.X_add_number
= 0;
13798 if (small_offset_p (0, align
, 16))
13799 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13800 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13803 load_address (tempreg
, ep
, &used_at
);
13805 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13806 tempreg
, tempreg
, breg
);
13808 offset_reloc
[0] = BFD_RELOC_LO16
;
13809 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13810 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13815 else if (!ust
&& op
[0] == breg
)
13826 if (!target_big_endian
)
13827 ep
->X_add_number
+= off
;
13829 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13831 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13832 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13834 if (!target_big_endian
)
13835 ep
->X_add_number
-= off
;
13837 ep
->X_add_number
+= off
;
13839 macro_build (NULL
, s2
, "t,~(b)",
13840 tempreg
, (int) ep
->X_add_number
, breg
);
13842 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13843 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13845 /* If necessary, move the result in tempreg to the final destination. */
13846 if (!ust
&& op
[0] != tempreg
)
13848 /* Protect second load's delay slot. */
13850 move_register (op
[0], tempreg
);
13856 if (target_big_endian
== ust
)
13857 ep
->X_add_number
+= off
;
13858 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13859 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13860 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13862 /* For halfword transfers we need a temporary register to shuffle
13863 bytes. Unfortunately for M_USH_A we have none available before
13864 the next store as AT holds the base address. We deal with this
13865 case by clobbering TREG and then restoring it as with ULH. */
13866 tempreg
= ust
== large_offset
? op
[0] : AT
;
13868 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13870 if (target_big_endian
== ust
)
13871 ep
->X_add_number
-= off
;
13873 ep
->X_add_number
+= off
;
13874 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13875 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13877 /* For M_USH_A re-retrieve the LSB. */
13878 if (ust
&& large_offset
)
13880 if (target_big_endian
)
13881 ep
->X_add_number
+= off
;
13883 ep
->X_add_number
-= off
;
13884 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13885 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13887 /* For ULH and M_USH_A OR the LSB in. */
13888 if (!ust
|| large_offset
)
13890 tempreg
= !large_offset
? AT
: op
[0];
13891 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13892 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13897 /* FIXME: Check if this is one of the itbl macros, since they
13898 are added dynamically. */
13899 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13902 if (!mips_opts
.at
&& used_at
)
13903 as_bad (_("macro used $at after \".set noat\""));
13906 /* Implement macros in mips16 mode. */
13909 mips16_macro (struct mips_cl_insn
*ip
)
13911 const struct mips_operand_array
*operands
;
13916 const char *s
, *s2
, *s3
;
13917 unsigned int op
[MAX_OPERANDS
];
13920 mask
= ip
->insn_mo
->mask
;
13922 operands
= insn_operands (ip
);
13923 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13924 if (operands
->operand
[i
])
13925 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13929 expr1
.X_op
= O_constant
;
13930 expr1
.X_op_symbol
= NULL
;
13931 expr1
.X_add_symbol
= NULL
;
13932 expr1
.X_add_number
= 1;
13943 /* Fall through. */
13949 /* Fall through. */
13953 start_noreorder ();
13954 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13955 expr1
.X_add_number
= 2;
13956 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13957 macro_build (NULL
, "break", "6", 7);
13959 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13960 since that causes an overflow. We should do that as well,
13961 but I don't see how to do the comparisons without a temporary
13964 macro_build (NULL
, s
, "x", op
[0]);
13983 start_noreorder ();
13984 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13985 expr1
.X_add_number
= 2;
13986 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13987 macro_build (NULL
, "break", "6", 7);
13989 macro_build (NULL
, s2
, "x", op
[0]);
13994 /* Fall through. */
13996 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13997 macro_build (NULL
, "mflo", "x", op
[0]);
14005 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14006 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14010 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14011 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14015 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14016 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14038 goto do_reverse_branch
;
14042 goto do_reverse_branch
;
14054 goto do_reverse_branch
;
14065 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14066 macro_build (&offset_expr
, s2
, "p");
14093 goto do_addone_branch_i
;
14098 goto do_addone_branch_i
;
14113 goto do_addone_branch_i
;
14119 do_addone_branch_i
:
14120 ++imm_expr
.X_add_number
;
14123 macro_build (&imm_expr
, s
, s3
, op
[0]);
14124 macro_build (&offset_expr
, s2
, "p");
14128 expr1
.X_add_number
= 0;
14129 macro_build (&expr1
, "slti", "x,8", op
[1]);
14130 if (op
[0] != op
[1])
14131 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14132 expr1
.X_add_number
= 2;
14133 macro_build (&expr1
, "bteqz", "p");
14134 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14139 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14140 opcode bits in *OPCODE_EXTRA. */
14142 static struct mips_opcode
*
14143 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
14144 ssize_t length
, unsigned int *opcode_extra
)
14146 char *name
, *dot
, *p
;
14147 unsigned int mask
, suffix
;
14149 struct mips_opcode
*insn
;
14151 /* Make a copy of the instruction so that we can fiddle with it. */
14152 name
= xstrndup (start
, length
);
14154 /* Look up the instruction as-is. */
14155 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14159 dot
= strchr (name
, '.');
14162 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14163 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14164 if (*p
== 0 && mask
!= 0)
14167 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14169 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14171 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14177 if (mips_opts
.micromips
)
14179 /* See if there's an instruction size override suffix,
14180 either `16' or `32', at the end of the mnemonic proper,
14181 that defines the operation, i.e. before the first `.'
14182 character if any. Strip it and retry. */
14183 opend
= dot
!= NULL
? dot
- name
: length
;
14184 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14186 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14192 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14193 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14196 forced_insn_length
= suffix
;
14208 /* Assemble an instruction into its binary format. If the instruction
14209 is a macro, set imm_expr and offset_expr to the values associated
14210 with "I" and "A" operands respectively. Otherwise store the value
14211 of the relocatable field (if any) in offset_expr. In both cases
14212 set offset_reloc to the relocation operators applied to offset_expr. */
14215 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14217 const struct mips_opcode
*first
, *past
;
14218 struct hash_control
*hash
;
14221 struct mips_operand_token
*tokens
;
14222 unsigned int opcode_extra
;
14224 if (mips_opts
.micromips
)
14226 hash
= micromips_op_hash
;
14227 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14232 past
= &mips_opcodes
[NUMOPCODES
];
14234 forced_insn_length
= 0;
14237 /* We first try to match an instruction up to a space or to the end. */
14238 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14241 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14244 set_insn_error (0, _("unrecognized opcode"));
14248 if (strcmp (first
->name
, "li.s") == 0)
14250 else if (strcmp (first
->name
, "li.d") == 0)
14254 tokens
= mips_parse_arguments (str
+ end
, format
);
14258 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14259 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14260 set_insn_error (0, _("invalid operands"));
14262 obstack_free (&mips_operand_tokens
, tokens
);
14265 /* As for mips_ip, but used when assembling MIPS16 code.
14266 Also set forced_insn_length to the resulting instruction size in
14267 bytes if the user explicitly requested a small or extended instruction. */
14270 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14273 struct mips_opcode
*first
;
14274 struct mips_operand_token
*tokens
;
14277 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14299 else if (*s
== 'e')
14306 else if (*s
++ == ' ')
14308 set_insn_error (0, _("unrecognized opcode"));
14311 forced_insn_length
= l
;
14314 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14319 set_insn_error (0, _("unrecognized opcode"));
14323 tokens
= mips_parse_arguments (s
, 0);
14327 if (!match_mips16_insns (insn
, first
, tokens
))
14328 set_insn_error (0, _("invalid operands"));
14330 obstack_free (&mips_operand_tokens
, tokens
);
14333 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14334 NBITS is the number of significant bits in VAL. */
14336 static unsigned long
14337 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14342 val
&= (1U << nbits
) - 1;
14343 if (nbits
== 16 || nbits
== 9)
14345 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14348 else if (nbits
== 15)
14350 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14353 else if (nbits
== 6)
14355 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14358 return (extval
<< 16) | val
;
14361 /* Like decode_mips16_operand, but require the operand to be defined and
14362 require it to be an integer. */
14364 static const struct mips_int_operand
*
14365 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14367 const struct mips_operand
*operand
;
14369 operand
= decode_mips16_operand (type
, extended_p
);
14370 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14372 return (const struct mips_int_operand
*) operand
;
14375 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14378 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14379 bfd_reloc_code_real_type reloc
, offsetT sval
)
14381 int min_val
, max_val
;
14383 min_val
= mips_int_operand_min (operand
);
14384 max_val
= mips_int_operand_max (operand
);
14385 if (reloc
!= BFD_RELOC_UNUSED
)
14388 sval
= SEXT_16BIT (sval
);
14393 return (sval
>= min_val
14395 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14398 /* Install immediate value VAL into MIPS16 instruction *INSN,
14399 extending it if necessary. The instruction in *INSN may
14400 already be extended.
14402 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14403 if none. In the former case, VAL is a 16-bit number with no
14404 defined signedness.
14406 TYPE is the type of the immediate field. USER_INSN_LENGTH
14407 is the length that the user requested, or 0 if none. */
14410 mips16_immed (const char *file
, unsigned int line
, int type
,
14411 bfd_reloc_code_real_type reloc
, offsetT val
,
14412 unsigned int user_insn_length
, unsigned long *insn
)
14414 const struct mips_int_operand
*operand
;
14415 unsigned int uval
, length
;
14417 operand
= mips16_immed_operand (type
, FALSE
);
14418 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14420 /* We need an extended instruction. */
14421 if (user_insn_length
== 2)
14422 as_bad_where (file
, line
, _("invalid unextended operand value"));
14424 *insn
|= MIPS16_EXTEND
;
14426 else if (user_insn_length
== 4)
14428 /* The operand doesn't force an unextended instruction to be extended.
14429 Warn if the user wanted an extended instruction anyway. */
14430 *insn
|= MIPS16_EXTEND
;
14431 as_warn_where (file
, line
,
14432 _("extended operand requested but not required"));
14435 length
= mips16_opcode_length (*insn
);
14438 operand
= mips16_immed_operand (type
, TRUE
);
14439 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14440 as_bad_where (file
, line
,
14441 _("operand value out of range for instruction"));
14443 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14444 if (length
== 2 || operand
->root
.lsb
!= 0)
14445 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14447 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14450 struct percent_op_match
14453 bfd_reloc_code_real_type reloc
;
14456 static const struct percent_op_match mips_percent_op
[] =
14458 {"%lo", BFD_RELOC_LO16
},
14459 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14460 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14461 {"%call16", BFD_RELOC_MIPS_CALL16
},
14462 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14463 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14464 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14465 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14466 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14467 {"%got", BFD_RELOC_MIPS_GOT16
},
14468 {"%gp_rel", BFD_RELOC_GPREL16
},
14469 {"%gprel", BFD_RELOC_GPREL16
},
14470 {"%half", BFD_RELOC_16
},
14471 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14472 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14473 {"%neg", BFD_RELOC_MIPS_SUB
},
14474 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14475 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14476 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14477 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14478 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14479 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14480 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14481 {"%hi", BFD_RELOC_HI16_S
},
14482 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14483 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14486 static const struct percent_op_match mips16_percent_op
[] =
14488 {"%lo", BFD_RELOC_MIPS16_LO16
},
14489 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14490 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14491 {"%got", BFD_RELOC_MIPS16_GOT16
},
14492 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14493 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14494 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14495 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14496 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14497 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14498 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14499 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14500 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14504 /* Return true if *STR points to a relocation operator. When returning true,
14505 move *STR over the operator and store its relocation code in *RELOC.
14506 Leave both *STR and *RELOC alone when returning false. */
14509 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14511 const struct percent_op_match
*percent_op
;
14514 if (mips_opts
.mips16
)
14516 percent_op
= mips16_percent_op
;
14517 limit
= ARRAY_SIZE (mips16_percent_op
);
14521 percent_op
= mips_percent_op
;
14522 limit
= ARRAY_SIZE (mips_percent_op
);
14525 for (i
= 0; i
< limit
; i
++)
14526 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14528 int len
= strlen (percent_op
[i
].str
);
14530 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14533 *str
+= strlen (percent_op
[i
].str
);
14534 *reloc
= percent_op
[i
].reloc
;
14536 /* Check whether the output BFD supports this relocation.
14537 If not, issue an error and fall back on something safe. */
14538 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14540 as_bad (_("relocation %s isn't supported by the current ABI"),
14541 percent_op
[i
].str
);
14542 *reloc
= BFD_RELOC_UNUSED
;
14550 /* Parse string STR as a 16-bit relocatable operand. Store the
14551 expression in *EP and the relocations in the array starting
14552 at RELOC. Return the number of relocation operators used.
14554 On exit, EXPR_END points to the first character after the expression. */
14557 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14560 bfd_reloc_code_real_type reversed_reloc
[3];
14561 size_t reloc_index
, i
;
14562 int crux_depth
, str_depth
;
14565 /* Search for the start of the main expression, recoding relocations
14566 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14567 of the main expression and with CRUX_DEPTH containing the number
14568 of open brackets at that point. */
14575 crux_depth
= str_depth
;
14577 /* Skip over whitespace and brackets, keeping count of the number
14579 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14584 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14585 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14587 my_getExpression (ep
, crux
);
14590 /* Match every open bracket. */
14591 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14595 if (crux_depth
> 0)
14596 as_bad (_("unclosed '('"));
14600 if (reloc_index
!= 0)
14602 prev_reloc_op_frag
= frag_now
;
14603 for (i
= 0; i
< reloc_index
; i
++)
14604 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14607 return reloc_index
;
14611 my_getExpression (expressionS
*ep
, char *str
)
14615 save_in
= input_line_pointer
;
14616 input_line_pointer
= str
;
14618 expr_end
= input_line_pointer
;
14619 input_line_pointer
= save_in
;
14623 md_atof (int type
, char *litP
, int *sizeP
)
14625 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14629 md_number_to_chars (char *buf
, valueT val
, int n
)
14631 if (target_big_endian
)
14632 number_to_chars_bigendian (buf
, val
, n
);
14634 number_to_chars_littleendian (buf
, val
, n
);
14637 static int support_64bit_objects(void)
14639 const char **list
, **l
;
14642 list
= bfd_target_list ();
14643 for (l
= list
; *l
!= NULL
; l
++)
14644 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14645 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14647 yes
= (*l
!= NULL
);
14652 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14653 NEW_VALUE. Warn if another value was already specified. Note:
14654 we have to defer parsing the -march and -mtune arguments in order
14655 to handle 'from-abi' correctly, since the ABI might be specified
14656 in a later argument. */
14659 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14661 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14662 as_warn (_("a different %s was already specified, is now %s"),
14663 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14666 *string_ptr
= new_value
;
14670 md_parse_option (int c
, const char *arg
)
14674 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14675 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14677 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14678 c
== mips_ases
[i
].option_on
);
14684 case OPTION_CONSTRUCT_FLOATS
:
14685 mips_disable_float_construction
= 0;
14688 case OPTION_NO_CONSTRUCT_FLOATS
:
14689 mips_disable_float_construction
= 1;
14701 target_big_endian
= 1;
14705 target_big_endian
= 0;
14711 else if (arg
[0] == '0')
14713 else if (arg
[0] == '1')
14723 mips_debug
= atoi (arg
);
14727 file_mips_opts
.isa
= ISA_MIPS1
;
14731 file_mips_opts
.isa
= ISA_MIPS2
;
14735 file_mips_opts
.isa
= ISA_MIPS3
;
14739 file_mips_opts
.isa
= ISA_MIPS4
;
14743 file_mips_opts
.isa
= ISA_MIPS5
;
14746 case OPTION_MIPS32
:
14747 file_mips_opts
.isa
= ISA_MIPS32
;
14750 case OPTION_MIPS32R2
:
14751 file_mips_opts
.isa
= ISA_MIPS32R2
;
14754 case OPTION_MIPS32R3
:
14755 file_mips_opts
.isa
= ISA_MIPS32R3
;
14758 case OPTION_MIPS32R5
:
14759 file_mips_opts
.isa
= ISA_MIPS32R5
;
14762 case OPTION_MIPS32R6
:
14763 file_mips_opts
.isa
= ISA_MIPS32R6
;
14766 case OPTION_MIPS64R2
:
14767 file_mips_opts
.isa
= ISA_MIPS64R2
;
14770 case OPTION_MIPS64R3
:
14771 file_mips_opts
.isa
= ISA_MIPS64R3
;
14774 case OPTION_MIPS64R5
:
14775 file_mips_opts
.isa
= ISA_MIPS64R5
;
14778 case OPTION_MIPS64R6
:
14779 file_mips_opts
.isa
= ISA_MIPS64R6
;
14782 case OPTION_MIPS64
:
14783 file_mips_opts
.isa
= ISA_MIPS64
;
14787 mips_set_option_string (&mips_tune_string
, arg
);
14791 mips_set_option_string (&mips_arch_string
, arg
);
14795 mips_set_option_string (&mips_arch_string
, "4650");
14796 mips_set_option_string (&mips_tune_string
, "4650");
14799 case OPTION_NO_M4650
:
14803 mips_set_option_string (&mips_arch_string
, "4010");
14804 mips_set_option_string (&mips_tune_string
, "4010");
14807 case OPTION_NO_M4010
:
14811 mips_set_option_string (&mips_arch_string
, "4100");
14812 mips_set_option_string (&mips_tune_string
, "4100");
14815 case OPTION_NO_M4100
:
14819 mips_set_option_string (&mips_arch_string
, "3900");
14820 mips_set_option_string (&mips_tune_string
, "3900");
14823 case OPTION_NO_M3900
:
14826 case OPTION_MICROMIPS
:
14827 if (file_mips_opts
.mips16
== 1)
14829 as_bad (_("-mmicromips cannot be used with -mips16"));
14832 file_mips_opts
.micromips
= 1;
14833 mips_no_prev_insn ();
14836 case OPTION_NO_MICROMIPS
:
14837 file_mips_opts
.micromips
= 0;
14838 mips_no_prev_insn ();
14841 case OPTION_MIPS16
:
14842 if (file_mips_opts
.micromips
== 1)
14844 as_bad (_("-mips16 cannot be used with -micromips"));
14847 file_mips_opts
.mips16
= 1;
14848 mips_no_prev_insn ();
14851 case OPTION_NO_MIPS16
:
14852 file_mips_opts
.mips16
= 0;
14853 mips_no_prev_insn ();
14856 case OPTION_FIX_24K
:
14860 case OPTION_NO_FIX_24K
:
14864 case OPTION_FIX_RM7000
:
14865 mips_fix_rm7000
= 1;
14868 case OPTION_NO_FIX_RM7000
:
14869 mips_fix_rm7000
= 0;
14872 case OPTION_FIX_LOONGSON3_LLSC
:
14873 mips_fix_loongson3_llsc
= TRUE
;
14876 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14877 mips_fix_loongson3_llsc
= FALSE
;
14880 case OPTION_FIX_LOONGSON2F_JUMP
:
14881 mips_fix_loongson2f_jump
= TRUE
;
14884 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14885 mips_fix_loongson2f_jump
= FALSE
;
14888 case OPTION_FIX_LOONGSON2F_NOP
:
14889 mips_fix_loongson2f_nop
= TRUE
;
14892 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14893 mips_fix_loongson2f_nop
= FALSE
;
14896 case OPTION_FIX_VR4120
:
14897 mips_fix_vr4120
= 1;
14900 case OPTION_NO_FIX_VR4120
:
14901 mips_fix_vr4120
= 0;
14904 case OPTION_FIX_VR4130
:
14905 mips_fix_vr4130
= 1;
14908 case OPTION_NO_FIX_VR4130
:
14909 mips_fix_vr4130
= 0;
14912 case OPTION_FIX_CN63XXP1
:
14913 mips_fix_cn63xxp1
= TRUE
;
14916 case OPTION_NO_FIX_CN63XXP1
:
14917 mips_fix_cn63xxp1
= FALSE
;
14920 case OPTION_FIX_R5900
:
14921 mips_fix_r5900
= TRUE
;
14922 mips_fix_r5900_explicit
= TRUE
;
14925 case OPTION_NO_FIX_R5900
:
14926 mips_fix_r5900
= FALSE
;
14927 mips_fix_r5900_explicit
= TRUE
;
14930 case OPTION_RELAX_BRANCH
:
14931 mips_relax_branch
= 1;
14934 case OPTION_NO_RELAX_BRANCH
:
14935 mips_relax_branch
= 0;
14938 case OPTION_IGNORE_BRANCH_ISA
:
14939 mips_ignore_branch_isa
= TRUE
;
14942 case OPTION_NO_IGNORE_BRANCH_ISA
:
14943 mips_ignore_branch_isa
= FALSE
;
14946 case OPTION_INSN32
:
14947 file_mips_opts
.insn32
= TRUE
;
14950 case OPTION_NO_INSN32
:
14951 file_mips_opts
.insn32
= FALSE
;
14954 case OPTION_MSHARED
:
14955 mips_in_shared
= TRUE
;
14958 case OPTION_MNO_SHARED
:
14959 mips_in_shared
= FALSE
;
14962 case OPTION_MSYM32
:
14963 file_mips_opts
.sym32
= TRUE
;
14966 case OPTION_MNO_SYM32
:
14967 file_mips_opts
.sym32
= FALSE
;
14970 /* When generating ELF code, we permit -KPIC and -call_shared to
14971 select SVR4_PIC, and -non_shared to select no PIC. This is
14972 intended to be compatible with Irix 5. */
14973 case OPTION_CALL_SHARED
:
14974 mips_pic
= SVR4_PIC
;
14975 mips_abicalls
= TRUE
;
14978 case OPTION_CALL_NONPIC
:
14980 mips_abicalls
= TRUE
;
14983 case OPTION_NON_SHARED
:
14985 mips_abicalls
= FALSE
;
14988 /* The -xgot option tells the assembler to use 32 bit offsets
14989 when accessing the got in SVR4_PIC mode. It is for Irix
14996 g_switch_value
= atoi (arg
);
15000 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15003 mips_abi
= O32_ABI
;
15007 mips_abi
= N32_ABI
;
15011 mips_abi
= N64_ABI
;
15012 if (!support_64bit_objects())
15013 as_fatal (_("no compiled in support for 64 bit object file format"));
15017 file_mips_opts
.gp
= 32;
15021 file_mips_opts
.gp
= 64;
15025 file_mips_opts
.fp
= 32;
15029 file_mips_opts
.fp
= 0;
15033 file_mips_opts
.fp
= 64;
15036 case OPTION_ODD_SPREG
:
15037 file_mips_opts
.oddspreg
= 1;
15040 case OPTION_NO_ODD_SPREG
:
15041 file_mips_opts
.oddspreg
= 0;
15044 case OPTION_SINGLE_FLOAT
:
15045 file_mips_opts
.single_float
= 1;
15048 case OPTION_DOUBLE_FLOAT
:
15049 file_mips_opts
.single_float
= 0;
15052 case OPTION_SOFT_FLOAT
:
15053 file_mips_opts
.soft_float
= 1;
15056 case OPTION_HARD_FLOAT
:
15057 file_mips_opts
.soft_float
= 0;
15061 if (strcmp (arg
, "32") == 0)
15062 mips_abi
= O32_ABI
;
15063 else if (strcmp (arg
, "o64") == 0)
15064 mips_abi
= O64_ABI
;
15065 else if (strcmp (arg
, "n32") == 0)
15066 mips_abi
= N32_ABI
;
15067 else if (strcmp (arg
, "64") == 0)
15069 mips_abi
= N64_ABI
;
15070 if (! support_64bit_objects())
15071 as_fatal (_("no compiled in support for 64 bit object file "
15074 else if (strcmp (arg
, "eabi") == 0)
15075 mips_abi
= EABI_ABI
;
15078 as_fatal (_("invalid abi -mabi=%s"), arg
);
15083 case OPTION_M7000_HILO_FIX
:
15084 mips_7000_hilo_fix
= TRUE
;
15087 case OPTION_MNO_7000_HILO_FIX
:
15088 mips_7000_hilo_fix
= FALSE
;
15091 case OPTION_MDEBUG
:
15092 mips_flag_mdebug
= TRUE
;
15095 case OPTION_NO_MDEBUG
:
15096 mips_flag_mdebug
= FALSE
;
15100 mips_flag_pdr
= TRUE
;
15103 case OPTION_NO_PDR
:
15104 mips_flag_pdr
= FALSE
;
15107 case OPTION_MVXWORKS_PIC
:
15108 mips_pic
= VXWORKS_PIC
;
15112 if (strcmp (arg
, "2008") == 0)
15114 else if (strcmp (arg
, "legacy") == 0)
15118 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15127 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15132 /* Set up globals to tune for the ISA or processor described by INFO. */
15135 mips_set_tune (const struct mips_cpu_info
*info
)
15138 mips_tune
= info
->cpu
;
15143 mips_after_parse_args (void)
15145 const struct mips_cpu_info
*arch_info
= 0;
15146 const struct mips_cpu_info
*tune_info
= 0;
15148 /* GP relative stuff not working for PE. */
15149 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15151 if (g_switch_seen
&& g_switch_value
!= 0)
15152 as_bad (_("-G not supported in this configuration"));
15153 g_switch_value
= 0;
15156 if (mips_abi
== NO_ABI
)
15157 mips_abi
= MIPS_DEFAULT_ABI
;
15159 /* The following code determines the architecture.
15160 Similar code was added to GCC 3.3 (see override_options() in
15161 config/mips/mips.c). The GAS and GCC code should be kept in sync
15162 as much as possible. */
15164 if (mips_arch_string
!= 0)
15165 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15167 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15169 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15170 ISA level specified by -mipsN, while arch_info->isa contains
15171 the -march selection (if any). */
15172 if (arch_info
!= 0)
15174 /* -march takes precedence over -mipsN, since it is more descriptive.
15175 There's no harm in specifying both as long as the ISA levels
15177 if (file_mips_opts
.isa
!= arch_info
->isa
)
15178 as_bad (_("-%s conflicts with the other architecture options,"
15179 " which imply -%s"),
15180 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15181 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15184 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15187 if (arch_info
== 0)
15189 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15190 gas_assert (arch_info
);
15193 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15194 as_bad (_("-march=%s is not compatible with the selected ABI"),
15197 file_mips_opts
.arch
= arch_info
->cpu
;
15198 file_mips_opts
.isa
= arch_info
->isa
;
15199 file_mips_opts
.init_ase
= arch_info
->ase
;
15201 /* Set up initial mips_opts state. */
15202 mips_opts
= file_mips_opts
;
15204 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15205 if (!mips_fix_r5900_explicit
)
15206 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15208 /* The register size inference code is now placed in
15209 file_mips_check_options. */
15211 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15213 if (mips_tune_string
!= 0)
15214 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15216 if (tune_info
== 0)
15217 mips_set_tune (arch_info
);
15219 mips_set_tune (tune_info
);
15221 if (mips_flag_mdebug
< 0)
15222 mips_flag_mdebug
= 0;
15226 mips_init_after_args (void)
15228 /* Initialize opcodes. */
15229 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15230 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15234 md_pcrel_from (fixS
*fixP
)
15236 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15238 switch (fixP
->fx_r_type
)
15240 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15241 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15242 /* Return the address of the delay slot. */
15245 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15246 case BFD_RELOC_MICROMIPS_JMP
:
15247 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15248 case BFD_RELOC_16_PCREL_S2
:
15249 case BFD_RELOC_MIPS_21_PCREL_S2
:
15250 case BFD_RELOC_MIPS_26_PCREL_S2
:
15251 case BFD_RELOC_MIPS_JMP
:
15252 /* Return the address of the delay slot. */
15255 case BFD_RELOC_MIPS_18_PCREL_S3
:
15256 /* Return the aligned address of the doubleword containing
15257 the instruction. */
15265 /* This is called before the symbol table is processed. In order to
15266 work with gcc when using mips-tfile, we must keep all local labels.
15267 However, in other cases, we want to discard them. If we were
15268 called with -g, but we didn't see any debugging information, it may
15269 mean that gcc is smuggling debugging information through to
15270 mips-tfile, in which case we must generate all local labels. */
15273 mips_frob_file_before_adjust (void)
15275 #ifndef NO_ECOFF_DEBUGGING
15276 if (ECOFF_DEBUGGING
15278 && ! ecoff_debugging_seen
)
15279 flag_keep_locals
= 1;
15283 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15284 the corresponding LO16 reloc. This is called before md_apply_fix and
15285 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15286 relocation operators.
15288 For our purposes, a %lo() expression matches a %got() or %hi()
15291 (a) it refers to the same symbol; and
15292 (b) the offset applied in the %lo() expression is no lower than
15293 the offset applied in the %got() or %hi().
15295 (b) allows us to cope with code like:
15298 lh $4,%lo(foo+2)($4)
15300 ...which is legal on RELA targets, and has a well-defined behaviour
15301 if the user knows that adding 2 to "foo" will not induce a carry to
15304 When several %lo()s match a particular %got() or %hi(), we use the
15305 following rules to distinguish them:
15307 (1) %lo()s with smaller offsets are a better match than %lo()s with
15310 (2) %lo()s with no matching %got() or %hi() are better than those
15311 that already have a matching %got() or %hi().
15313 (3) later %lo()s are better than earlier %lo()s.
15315 These rules are applied in order.
15317 (1) means, among other things, that %lo()s with identical offsets are
15318 chosen if they exist.
15320 (2) means that we won't associate several high-part relocations with
15321 the same low-part relocation unless there's no alternative. Having
15322 several high parts for the same low part is a GNU extension; this rule
15323 allows careful users to avoid it.
15325 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15326 with the last high-part relocation being at the front of the list.
15327 It therefore makes sense to choose the last matching low-part
15328 relocation, all other things being equal. It's also easier
15329 to code that way. */
15332 mips_frob_file (void)
15334 struct mips_hi_fixup
*l
;
15335 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15337 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15339 segment_info_type
*seginfo
;
15340 bfd_boolean matched_lo_p
;
15341 fixS
**hi_pos
, **lo_pos
, **pos
;
15343 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15345 /* If a GOT16 relocation turns out to be against a global symbol,
15346 there isn't supposed to be a matching LO. Ignore %gots against
15347 constants; we'll report an error for those later. */
15348 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15349 && !(l
->fixp
->fx_addsy
15350 && pic_need_relax (l
->fixp
->fx_addsy
)))
15353 /* Check quickly whether the next fixup happens to be a matching %lo. */
15354 if (fixup_has_matching_lo_p (l
->fixp
))
15357 seginfo
= seg_info (l
->seg
);
15359 /* Set HI_POS to the position of this relocation in the chain.
15360 Set LO_POS to the position of the chosen low-part relocation.
15361 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15362 relocation that matches an immediately-preceding high-part
15366 matched_lo_p
= FALSE
;
15367 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15369 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15371 if (*pos
== l
->fixp
)
15374 if ((*pos
)->fx_r_type
== looking_for_rtype
15375 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15376 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15378 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15380 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15383 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15384 && fixup_has_matching_lo_p (*pos
));
15387 /* If we found a match, remove the high-part relocation from its
15388 current position and insert it before the low-part relocation.
15389 Make the offsets match so that fixup_has_matching_lo_p()
15392 We don't warn about unmatched high-part relocations since some
15393 versions of gcc have been known to emit dead "lui ...%hi(...)"
15395 if (lo_pos
!= NULL
)
15397 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15398 if (l
->fixp
->fx_next
!= *lo_pos
)
15400 *hi_pos
= l
->fixp
->fx_next
;
15401 l
->fixp
->fx_next
= *lo_pos
;
15409 mips_force_relocation (fixS
*fixp
)
15411 if (generic_force_reloc (fixp
))
15414 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15415 so that the linker relaxation can update targets. */
15416 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15417 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15418 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15421 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15422 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15423 microMIPS symbols so that we can do cross-mode branch diagnostics
15424 and BAL to JALX conversion by the linker. */
15425 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15426 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15427 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15429 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15432 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15433 if (ISA_IS_R6 (file_mips_opts
.isa
)
15434 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15435 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15436 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15437 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15438 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15439 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15440 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15446 /* Implement TC_FORCE_RELOCATION_ABS. */
15449 mips_force_relocation_abs (fixS
*fixp
)
15451 if (generic_force_reloc (fixp
))
15454 /* These relocations do not have enough bits in the in-place addend
15455 to hold an arbitrary absolute section's offset. */
15456 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15462 /* Read the instruction associated with RELOC from BUF. */
15464 static unsigned int
15465 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15467 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15468 return read_compressed_insn (buf
, 4);
15470 return read_insn (buf
);
15473 /* Write instruction INSN to BUF, given that it has been relocated
15477 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15478 unsigned long insn
)
15480 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15481 write_compressed_insn (buf
, insn
, 4);
15483 write_insn (buf
, insn
);
15486 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15487 to a symbol in another ISA mode, which cannot be converted to JALX. */
15490 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15492 unsigned long opcode
;
15496 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15499 other
= S_GET_OTHER (fixP
->fx_addsy
);
15500 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15501 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15502 switch (fixP
->fx_r_type
)
15504 case BFD_RELOC_MIPS_JMP
:
15505 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15506 case BFD_RELOC_MICROMIPS_JMP
:
15507 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15513 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15514 jump to a symbol in the same ISA mode. */
15517 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15519 unsigned long opcode
;
15523 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15526 other
= S_GET_OTHER (fixP
->fx_addsy
);
15527 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15528 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15529 switch (fixP
->fx_r_type
)
15531 case BFD_RELOC_MIPS_JMP
:
15532 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15533 case BFD_RELOC_MIPS16_JMP
:
15534 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15535 case BFD_RELOC_MICROMIPS_JMP
:
15536 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15542 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15543 to a symbol whose value plus addend is not aligned according to the
15544 ultimate (after linker relaxation) jump instruction's immediate field
15545 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15546 regular MIPS code, to (1 << 2). */
15549 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15551 bfd_boolean micro_to_mips_p
;
15555 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15558 other
= S_GET_OTHER (fixP
->fx_addsy
);
15559 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15560 val
+= fixP
->fx_offset
;
15561 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15562 && !ELF_ST_IS_MICROMIPS (other
));
15563 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15564 != ELF_ST_IS_COMPRESSED (other
));
15567 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15568 to a symbol whose annotation indicates another ISA mode. For absolute
15569 symbols check the ISA bit instead.
15571 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15572 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15573 MIPS symbols and associated with BAL instructions as these instructions
15574 may be converted to JALX by the linker. */
15577 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15579 bfd_boolean absolute_p
;
15580 unsigned long opcode
;
15586 if (mips_ignore_branch_isa
)
15589 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15592 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15593 absolute_p
= bfd_is_abs_section (symsec
);
15595 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15596 other
= S_GET_OTHER (fixP
->fx_addsy
);
15598 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15599 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15600 switch (fixP
->fx_r_type
)
15602 case BFD_RELOC_16_PCREL_S2
:
15603 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15604 && opcode
!= 0x0411);
15605 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15606 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15607 && opcode
!= 0x4060);
15608 case BFD_RELOC_MIPS_21_PCREL_S2
:
15609 case BFD_RELOC_MIPS_26_PCREL_S2
:
15610 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15611 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15612 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15613 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15614 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15615 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15621 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15622 branch instruction pointed to by FIXP is not aligned according to the
15623 branch instruction's immediate field requirement. We need the addend
15624 to preserve the ISA bit and also the sum must not have bit 2 set. We
15625 must explicitly OR in the ISA bit from symbol annotation as the bit
15626 won't be set in the symbol's value then. */
15629 fix_bad_misaligned_branch_p (fixS
*fixP
)
15631 bfd_boolean absolute_p
;
15638 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15641 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15642 absolute_p
= bfd_is_abs_section (symsec
);
15644 val
= S_GET_VALUE (fixP
->fx_addsy
);
15645 other
= S_GET_OTHER (fixP
->fx_addsy
);
15646 off
= fixP
->fx_offset
;
15648 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15649 val
|= ELF_ST_IS_COMPRESSED (other
);
15651 return (val
& 0x3) != isa_bit
;
15654 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15655 and its calculated value VAL. */
15658 fix_validate_branch (fixS
*fixP
, valueT val
)
15660 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15662 _("branch to misaligned address (0x%lx)"),
15663 (long) (val
+ md_pcrel_from (fixP
)));
15664 else if (fix_bad_cross_mode_branch_p (fixP
))
15665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15666 _("branch to a symbol in another ISA mode"));
15667 else if (fix_bad_misaligned_branch_p (fixP
))
15668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15669 _("branch to misaligned address (0x%lx)"),
15670 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15671 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15673 _("cannot encode misaligned addend "
15674 "in the relocatable field (0x%lx)"),
15675 (long) fixP
->fx_offset
);
15678 /* Apply a fixup to the object file. */
15681 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15684 unsigned long insn
;
15685 reloc_howto_type
*howto
;
15687 if (fixP
->fx_pcrel
)
15688 switch (fixP
->fx_r_type
)
15690 case BFD_RELOC_16_PCREL_S2
:
15691 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15692 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15693 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15694 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15695 case BFD_RELOC_32_PCREL
:
15696 case BFD_RELOC_MIPS_21_PCREL_S2
:
15697 case BFD_RELOC_MIPS_26_PCREL_S2
:
15698 case BFD_RELOC_MIPS_18_PCREL_S3
:
15699 case BFD_RELOC_MIPS_19_PCREL_S2
:
15700 case BFD_RELOC_HI16_S_PCREL
:
15701 case BFD_RELOC_LO16_PCREL
:
15705 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15710 _("PC-relative reference to a different section"));
15714 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15715 that have no MIPS ELF equivalent. */
15716 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15718 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15723 gas_assert (fixP
->fx_size
== 2
15724 || fixP
->fx_size
== 4
15725 || fixP
->fx_r_type
== BFD_RELOC_8
15726 || fixP
->fx_r_type
== BFD_RELOC_16
15727 || fixP
->fx_r_type
== BFD_RELOC_64
15728 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15729 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15730 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15731 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15732 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15733 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15734 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15736 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15738 /* Don't treat parts of a composite relocation as done. There are two
15741 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15742 should nevertheless be emitted if the first part is.
15744 (2) In normal usage, composite relocations are never assembly-time
15745 constants. The easiest way of dealing with the pathological
15746 exceptions is to generate a relocation against STN_UNDEF and
15747 leave everything up to the linker. */
15748 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15751 switch (fixP
->fx_r_type
)
15753 case BFD_RELOC_MIPS_TLS_GD
:
15754 case BFD_RELOC_MIPS_TLS_LDM
:
15755 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15756 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15757 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15758 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15759 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15760 case BFD_RELOC_MIPS_TLS_TPREL32
:
15761 case BFD_RELOC_MIPS_TLS_TPREL64
:
15762 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15763 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15764 case BFD_RELOC_MICROMIPS_TLS_GD
:
15765 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15766 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15767 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15768 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15769 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15770 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15771 case BFD_RELOC_MIPS16_TLS_GD
:
15772 case BFD_RELOC_MIPS16_TLS_LDM
:
15773 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15774 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15775 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15776 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15777 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15778 if (fixP
->fx_addsy
)
15779 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15782 _("TLS relocation against a constant"));
15785 case BFD_RELOC_MIPS_JMP
:
15786 case BFD_RELOC_MIPS16_JMP
:
15787 case BFD_RELOC_MICROMIPS_JMP
:
15791 gas_assert (!fixP
->fx_done
);
15793 /* Shift is 2, unusually, for microMIPS JALX. */
15794 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15795 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15800 if (fix_bad_cross_mode_jump_p (fixP
))
15801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15802 _("jump to a symbol in another ISA mode"));
15803 else if (fix_bad_same_mode_jalx_p (fixP
))
15804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15805 _("JALX to a symbol in the same ISA mode"));
15806 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15808 _("jump to misaligned address (0x%lx)"),
15809 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15810 + fixP
->fx_offset
));
15811 else if (HAVE_IN_PLACE_ADDENDS
15812 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15814 _("cannot encode misaligned addend "
15815 "in the relocatable field (0x%lx)"),
15816 (long) fixP
->fx_offset
);
15818 /* Fall through. */
15820 case BFD_RELOC_MIPS_SHIFT5
:
15821 case BFD_RELOC_MIPS_SHIFT6
:
15822 case BFD_RELOC_MIPS_GOT_DISP
:
15823 case BFD_RELOC_MIPS_GOT_PAGE
:
15824 case BFD_RELOC_MIPS_GOT_OFST
:
15825 case BFD_RELOC_MIPS_SUB
:
15826 case BFD_RELOC_MIPS_INSERT_A
:
15827 case BFD_RELOC_MIPS_INSERT_B
:
15828 case BFD_RELOC_MIPS_DELETE
:
15829 case BFD_RELOC_MIPS_HIGHEST
:
15830 case BFD_RELOC_MIPS_HIGHER
:
15831 case BFD_RELOC_MIPS_SCN_DISP
:
15832 case BFD_RELOC_MIPS_REL16
:
15833 case BFD_RELOC_MIPS_RELGOT
:
15834 case BFD_RELOC_MIPS_JALR
:
15835 case BFD_RELOC_HI16
:
15836 case BFD_RELOC_HI16_S
:
15837 case BFD_RELOC_LO16
:
15838 case BFD_RELOC_GPREL16
:
15839 case BFD_RELOC_MIPS_LITERAL
:
15840 case BFD_RELOC_MIPS_CALL16
:
15841 case BFD_RELOC_MIPS_GOT16
:
15842 case BFD_RELOC_GPREL32
:
15843 case BFD_RELOC_MIPS_GOT_HI16
:
15844 case BFD_RELOC_MIPS_GOT_LO16
:
15845 case BFD_RELOC_MIPS_CALL_HI16
:
15846 case BFD_RELOC_MIPS_CALL_LO16
:
15847 case BFD_RELOC_HI16_S_PCREL
:
15848 case BFD_RELOC_LO16_PCREL
:
15849 case BFD_RELOC_MIPS16_GPREL
:
15850 case BFD_RELOC_MIPS16_GOT16
:
15851 case BFD_RELOC_MIPS16_CALL16
:
15852 case BFD_RELOC_MIPS16_HI16
:
15853 case BFD_RELOC_MIPS16_HI16_S
:
15854 case BFD_RELOC_MIPS16_LO16
:
15855 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15856 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15857 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15858 case BFD_RELOC_MICROMIPS_SUB
:
15859 case BFD_RELOC_MICROMIPS_HIGHEST
:
15860 case BFD_RELOC_MICROMIPS_HIGHER
:
15861 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15862 case BFD_RELOC_MICROMIPS_JALR
:
15863 case BFD_RELOC_MICROMIPS_HI16
:
15864 case BFD_RELOC_MICROMIPS_HI16_S
:
15865 case BFD_RELOC_MICROMIPS_LO16
:
15866 case BFD_RELOC_MICROMIPS_GPREL16
:
15867 case BFD_RELOC_MICROMIPS_LITERAL
:
15868 case BFD_RELOC_MICROMIPS_CALL16
:
15869 case BFD_RELOC_MICROMIPS_GOT16
:
15870 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15871 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15872 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15873 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15874 case BFD_RELOC_MIPS_EH
:
15879 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15881 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15882 if (mips16_reloc_p (fixP
->fx_r_type
))
15883 insn
|= mips16_immed_extend (value
, 16);
15885 insn
|= (value
& 0xffff);
15886 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15890 _("unsupported constant in relocation"));
15895 /* This is handled like BFD_RELOC_32, but we output a sign
15896 extended value if we are only 32 bits. */
15899 if (8 <= sizeof (valueT
))
15900 md_number_to_chars (buf
, *valP
, 8);
15905 if ((*valP
& 0x80000000) != 0)
15909 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15910 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15915 case BFD_RELOC_RVA
:
15917 case BFD_RELOC_32_PCREL
:
15920 /* If we are deleting this reloc entry, we must fill in the
15921 value now. This can happen if we have a .word which is not
15922 resolved when it appears but is later defined. */
15924 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15927 case BFD_RELOC_MIPS_21_PCREL_S2
:
15928 fix_validate_branch (fixP
, *valP
);
15929 if (!fixP
->fx_done
)
15932 if (*valP
+ 0x400000 <= 0x7fffff)
15934 insn
= read_insn (buf
);
15935 insn
|= (*valP
>> 2) & 0x1fffff;
15936 write_insn (buf
, insn
);
15939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15940 _("branch out of range"));
15943 case BFD_RELOC_MIPS_26_PCREL_S2
:
15944 fix_validate_branch (fixP
, *valP
);
15945 if (!fixP
->fx_done
)
15948 if (*valP
+ 0x8000000 <= 0xfffffff)
15950 insn
= read_insn (buf
);
15951 insn
|= (*valP
>> 2) & 0x3ffffff;
15952 write_insn (buf
, insn
);
15955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15956 _("branch out of range"));
15959 case BFD_RELOC_MIPS_18_PCREL_S3
:
15960 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15962 _("PC-relative access using misaligned symbol (%lx)"),
15963 (long) S_GET_VALUE (fixP
->fx_addsy
));
15964 if ((fixP
->fx_offset
& 0x7) != 0)
15965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15966 _("PC-relative access using misaligned offset (%lx)"),
15967 (long) fixP
->fx_offset
);
15968 if (!fixP
->fx_done
)
15971 if (*valP
+ 0x100000 <= 0x1fffff)
15973 insn
= read_insn (buf
);
15974 insn
|= (*valP
>> 3) & 0x3ffff;
15975 write_insn (buf
, insn
);
15978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15979 _("PC-relative access out of range"));
15982 case BFD_RELOC_MIPS_19_PCREL_S2
:
15983 if ((*valP
& 0x3) != 0)
15984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15985 _("PC-relative access to misaligned address (%lx)"),
15987 if (!fixP
->fx_done
)
15990 if (*valP
+ 0x100000 <= 0x1fffff)
15992 insn
= read_insn (buf
);
15993 insn
|= (*valP
>> 2) & 0x7ffff;
15994 write_insn (buf
, insn
);
15997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15998 _("PC-relative access out of range"));
16001 case BFD_RELOC_16_PCREL_S2
:
16002 fix_validate_branch (fixP
, *valP
);
16004 /* We need to save the bits in the instruction since fixup_segment()
16005 might be deleting the relocation entry (i.e., a branch within
16006 the current segment). */
16007 if (! fixP
->fx_done
)
16010 /* Update old instruction data. */
16011 insn
= read_insn (buf
);
16013 if (*valP
+ 0x20000 <= 0x3ffff)
16015 insn
|= (*valP
>> 2) & 0xffff;
16016 write_insn (buf
, insn
);
16018 else if (fixP
->fx_tcbit2
16020 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16021 && (fixP
->fx_frag
->fr_address
16022 < text_section
->vma
+ bfd_get_section_size (text_section
))
16023 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16024 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16025 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16027 /* The branch offset is too large. If this is an
16028 unconditional branch, and we are not generating PIC code,
16029 we can convert it to an absolute jump instruction. */
16030 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16031 insn
= 0x0c000000; /* jal */
16033 insn
= 0x08000000; /* j */
16034 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16036 fixP
->fx_addsy
= section_symbol (text_section
);
16037 *valP
+= md_pcrel_from (fixP
);
16038 write_insn (buf
, insn
);
16042 /* If we got here, we have branch-relaxation disabled,
16043 and there's nothing we can do to fix this instruction
16044 without turning it into a longer sequence. */
16045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16046 _("branch out of range"));
16050 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16051 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16052 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16053 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16054 gas_assert (!fixP
->fx_done
);
16055 if (fix_bad_cross_mode_branch_p (fixP
))
16056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16057 _("branch to a symbol in another ISA mode"));
16058 else if (fixP
->fx_addsy
16059 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
16060 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16061 && (fixP
->fx_offset
& 0x1) != 0)
16062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16063 _("branch to misaligned address (0x%lx)"),
16064 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
16065 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16067 _("cannot encode misaligned addend "
16068 "in the relocatable field (0x%lx)"),
16069 (long) fixP
->fx_offset
);
16072 case BFD_RELOC_VTABLE_INHERIT
:
16075 && !S_IS_DEFINED (fixP
->fx_addsy
)
16076 && !S_IS_WEAK (fixP
->fx_addsy
))
16077 S_SET_WEAK (fixP
->fx_addsy
);
16080 case BFD_RELOC_NONE
:
16081 case BFD_RELOC_VTABLE_ENTRY
:
16089 /* Remember value for tc_gen_reloc. */
16090 fixP
->fx_addnumber
= *valP
;
16100 c
= get_symbol_name (&name
);
16101 p
= (symbolS
*) symbol_find_or_make (name
);
16102 (void) restore_line_pointer (c
);
16106 /* Align the current frag to a given power of two. If a particular
16107 fill byte should be used, FILL points to an integer that contains
16108 that byte, otherwise FILL is null.
16110 This function used to have the comment:
16112 The MIPS assembler also automatically adjusts any preceding label.
16114 The implementation therefore applied the adjustment to a maximum of
16115 one label. However, other label adjustments are applied to batches
16116 of labels, and adjusting just one caused problems when new labels
16117 were added for the sake of debugging or unwind information.
16118 We therefore adjust all preceding labels (given as LABELS) instead. */
16121 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16123 mips_emit_delays ();
16124 mips_record_compressed_mode ();
16125 if (fill
== NULL
&& subseg_text_p (now_seg
))
16126 frag_align_code (to
, 0);
16128 frag_align (to
, fill
? *fill
: 0, 0);
16129 record_alignment (now_seg
, to
);
16130 mips_move_labels (labels
, FALSE
);
16133 /* Align to a given power of two. .align 0 turns off the automatic
16134 alignment used by the data creating pseudo-ops. */
16137 s_align (int x ATTRIBUTE_UNUSED
)
16139 int temp
, fill_value
, *fill_ptr
;
16140 long max_alignment
= 28;
16142 /* o Note that the assembler pulls down any immediately preceding label
16143 to the aligned address.
16144 o It's not documented but auto alignment is reinstated by
16145 a .align pseudo instruction.
16146 o Note also that after auto alignment is turned off the mips assembler
16147 issues an error on attempt to assemble an improperly aligned data item.
16150 temp
= get_absolute_expression ();
16151 if (temp
> max_alignment
)
16152 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16155 as_warn (_("alignment negative, 0 assumed"));
16158 if (*input_line_pointer
== ',')
16160 ++input_line_pointer
;
16161 fill_value
= get_absolute_expression ();
16162 fill_ptr
= &fill_value
;
16168 segment_info_type
*si
= seg_info (now_seg
);
16169 struct insn_label_list
*l
= si
->label_list
;
16170 /* Auto alignment should be switched on by next section change. */
16172 mips_align (temp
, fill_ptr
, l
);
16179 demand_empty_rest_of_line ();
16183 s_change_sec (int sec
)
16187 /* The ELF backend needs to know that we are changing sections, so
16188 that .previous works correctly. We could do something like check
16189 for an obj_section_change_hook macro, but that might be confusing
16190 as it would not be appropriate to use it in the section changing
16191 functions in read.c, since obj-elf.c intercepts those. FIXME:
16192 This should be cleaner, somehow. */
16193 obj_elf_section_change_hook ();
16195 mips_emit_delays ();
16206 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16207 demand_empty_rest_of_line ();
16211 seg
= subseg_new (RDATA_SECTION_NAME
,
16212 (subsegT
) get_absolute_expression ());
16213 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16214 | SEC_READONLY
| SEC_RELOC
16216 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16217 record_alignment (seg
, 4);
16218 demand_empty_rest_of_line ();
16222 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16223 bfd_set_section_flags (stdoutput
, seg
,
16224 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16225 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16226 record_alignment (seg
, 4);
16227 demand_empty_rest_of_line ();
16231 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16232 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16233 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16234 record_alignment (seg
, 4);
16235 demand_empty_rest_of_line ();
16243 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16246 char *section_name
;
16251 int section_entry_size
;
16252 int section_alignment
;
16254 saved_ilp
= input_line_pointer
;
16255 endc
= get_symbol_name (§ion_name
);
16256 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16258 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16260 /* Do we have .section Name<,"flags">? */
16261 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16263 /* Just after name is now '\0'. */
16264 (void) restore_line_pointer (endc
);
16265 input_line_pointer
= saved_ilp
;
16266 obj_elf_section (ignore
);
16270 section_name
= xstrdup (section_name
);
16271 c
= restore_line_pointer (endc
);
16273 input_line_pointer
++;
16275 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16277 section_type
= get_absolute_expression ();
16281 if (*input_line_pointer
++ == ',')
16282 section_flag
= get_absolute_expression ();
16286 if (*input_line_pointer
++ == ',')
16287 section_entry_size
= get_absolute_expression ();
16289 section_entry_size
= 0;
16291 if (*input_line_pointer
++ == ',')
16292 section_alignment
= get_absolute_expression ();
16294 section_alignment
= 0;
16296 /* FIXME: really ignore? */
16297 (void) section_alignment
;
16299 /* When using the generic form of .section (as implemented by obj-elf.c),
16300 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16301 traditionally had to fall back on the more common @progbits instead.
16303 There's nothing really harmful in this, since bfd will correct
16304 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16305 means that, for backwards compatibility, the special_section entries
16306 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16308 Even so, we shouldn't force users of the MIPS .section syntax to
16309 incorrectly label the sections as SHT_PROGBITS. The best compromise
16310 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16311 generic type-checking code. */
16312 if (section_type
== SHT_MIPS_DWARF
)
16313 section_type
= SHT_PROGBITS
;
16315 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16316 section_entry_size
, 0, 0, 0);
16318 if (now_seg
->name
!= section_name
)
16319 free (section_name
);
16323 mips_enable_auto_align (void)
16329 s_cons (int log_size
)
16331 segment_info_type
*si
= seg_info (now_seg
);
16332 struct insn_label_list
*l
= si
->label_list
;
16334 mips_emit_delays ();
16335 if (log_size
> 0 && auto_align
)
16336 mips_align (log_size
, 0, l
);
16337 cons (1 << log_size
);
16338 mips_clear_insn_labels ();
16342 s_float_cons (int type
)
16344 segment_info_type
*si
= seg_info (now_seg
);
16345 struct insn_label_list
*l
= si
->label_list
;
16347 mips_emit_delays ();
16352 mips_align (3, 0, l
);
16354 mips_align (2, 0, l
);
16358 mips_clear_insn_labels ();
16361 /* Handle .globl. We need to override it because on Irix 5 you are
16364 where foo is an undefined symbol, to mean that foo should be
16365 considered to be the address of a function. */
16368 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16377 c
= get_symbol_name (&name
);
16378 symbolP
= symbol_find_or_make (name
);
16379 S_SET_EXTERNAL (symbolP
);
16381 *input_line_pointer
= c
;
16382 SKIP_WHITESPACE_AFTER_NAME ();
16384 /* On Irix 5, every global symbol that is not explicitly labelled as
16385 being a function is apparently labelled as being an object. */
16388 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16389 && (*input_line_pointer
!= ','))
16394 c
= get_symbol_name (&secname
);
16395 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16397 as_bad (_("%s: no such section"), secname
);
16398 (void) restore_line_pointer (c
);
16400 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16401 flag
= BSF_FUNCTION
;
16404 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16406 c
= *input_line_pointer
;
16409 input_line_pointer
++;
16410 SKIP_WHITESPACE ();
16411 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16417 demand_empty_rest_of_line ();
16421 s_option (int x ATTRIBUTE_UNUSED
)
16426 c
= get_symbol_name (&opt
);
16430 /* FIXME: What does this mean? */
16432 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16436 i
= atoi (opt
+ 3);
16437 if (i
!= 0 && i
!= 2)
16438 as_bad (_(".option pic%d not supported"), i
);
16439 else if (mips_pic
== VXWORKS_PIC
)
16440 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16445 mips_pic
= SVR4_PIC
;
16446 mips_abicalls
= TRUE
;
16449 if (mips_pic
== SVR4_PIC
)
16451 if (g_switch_seen
&& g_switch_value
!= 0)
16452 as_warn (_("-G may not be used with SVR4 PIC code"));
16453 g_switch_value
= 0;
16454 bfd_set_gp_size (stdoutput
, 0);
16458 as_warn (_("unrecognized option \"%s\""), opt
);
16460 (void) restore_line_pointer (c
);
16461 demand_empty_rest_of_line ();
16464 /* This structure is used to hold a stack of .set values. */
16466 struct mips_option_stack
16468 struct mips_option_stack
*next
;
16469 struct mips_set_options options
;
16472 static struct mips_option_stack
*mips_opts_stack
;
16474 /* Return status for .set/.module option handling. */
16476 enum code_option_type
16478 /* Unrecognized option. */
16479 OPTION_TYPE_BAD
= -1,
16481 /* Ordinary option. */
16482 OPTION_TYPE_NORMAL
,
16484 /* ISA changing option. */
16488 /* Handle common .set/.module options. Return status indicating option
16491 static enum code_option_type
16492 parse_code_option (char * name
)
16494 bfd_boolean isa_set
= FALSE
;
16495 const struct mips_ase
*ase
;
16497 if (strncmp (name
, "at=", 3) == 0)
16499 char *s
= name
+ 3;
16501 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16502 as_bad (_("unrecognized register name `%s'"), s
);
16504 else if (strcmp (name
, "at") == 0)
16505 mips_opts
.at
= ATREG
;
16506 else if (strcmp (name
, "noat") == 0)
16507 mips_opts
.at
= ZERO
;
16508 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16509 mips_opts
.nomove
= 0;
16510 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16511 mips_opts
.nomove
= 1;
16512 else if (strcmp (name
, "bopt") == 0)
16513 mips_opts
.nobopt
= 0;
16514 else if (strcmp (name
, "nobopt") == 0)
16515 mips_opts
.nobopt
= 1;
16516 else if (strcmp (name
, "gp=32") == 0)
16518 else if (strcmp (name
, "gp=64") == 0)
16520 else if (strcmp (name
, "fp=32") == 0)
16522 else if (strcmp (name
, "fp=xx") == 0)
16524 else if (strcmp (name
, "fp=64") == 0)
16526 else if (strcmp (name
, "softfloat") == 0)
16527 mips_opts
.soft_float
= 1;
16528 else if (strcmp (name
, "hardfloat") == 0)
16529 mips_opts
.soft_float
= 0;
16530 else if (strcmp (name
, "singlefloat") == 0)
16531 mips_opts
.single_float
= 1;
16532 else if (strcmp (name
, "doublefloat") == 0)
16533 mips_opts
.single_float
= 0;
16534 else if (strcmp (name
, "nooddspreg") == 0)
16535 mips_opts
.oddspreg
= 0;
16536 else if (strcmp (name
, "oddspreg") == 0)
16537 mips_opts
.oddspreg
= 1;
16538 else if (strcmp (name
, "mips16") == 0
16539 || strcmp (name
, "MIPS-16") == 0)
16540 mips_opts
.mips16
= 1;
16541 else if (strcmp (name
, "nomips16") == 0
16542 || strcmp (name
, "noMIPS-16") == 0)
16543 mips_opts
.mips16
= 0;
16544 else if (strcmp (name
, "micromips") == 0)
16545 mips_opts
.micromips
= 1;
16546 else if (strcmp (name
, "nomicromips") == 0)
16547 mips_opts
.micromips
= 0;
16548 else if (name
[0] == 'n'
16550 && (ase
= mips_lookup_ase (name
+ 2)))
16551 mips_set_ase (ase
, &mips_opts
, FALSE
);
16552 else if ((ase
= mips_lookup_ase (name
)))
16553 mips_set_ase (ase
, &mips_opts
, TRUE
);
16554 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16556 /* Permit the user to change the ISA and architecture on the fly.
16557 Needless to say, misuse can cause serious problems. */
16558 if (strncmp (name
, "arch=", 5) == 0)
16560 const struct mips_cpu_info
*p
;
16562 p
= mips_parse_cpu ("internal use", name
+ 5);
16564 as_bad (_("unknown architecture %s"), name
+ 5);
16567 mips_opts
.arch
= p
->cpu
;
16568 mips_opts
.isa
= p
->isa
;
16570 mips_opts
.init_ase
= p
->ase
;
16573 else if (strncmp (name
, "mips", 4) == 0)
16575 const struct mips_cpu_info
*p
;
16577 p
= mips_parse_cpu ("internal use", name
);
16579 as_bad (_("unknown ISA level %s"), name
+ 4);
16582 mips_opts
.arch
= p
->cpu
;
16583 mips_opts
.isa
= p
->isa
;
16585 mips_opts
.init_ase
= p
->ase
;
16589 as_bad (_("unknown ISA or architecture %s"), name
);
16591 else if (strcmp (name
, "autoextend") == 0)
16592 mips_opts
.noautoextend
= 0;
16593 else if (strcmp (name
, "noautoextend") == 0)
16594 mips_opts
.noautoextend
= 1;
16595 else if (strcmp (name
, "insn32") == 0)
16596 mips_opts
.insn32
= TRUE
;
16597 else if (strcmp (name
, "noinsn32") == 0)
16598 mips_opts
.insn32
= FALSE
;
16599 else if (strcmp (name
, "sym32") == 0)
16600 mips_opts
.sym32
= TRUE
;
16601 else if (strcmp (name
, "nosym32") == 0)
16602 mips_opts
.sym32
= FALSE
;
16604 return OPTION_TYPE_BAD
;
16606 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16609 /* Handle the .set pseudo-op. */
16612 s_mipsset (int x ATTRIBUTE_UNUSED
)
16614 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16615 char *name
= input_line_pointer
, ch
;
16617 file_mips_check_options ();
16619 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16620 ++input_line_pointer
;
16621 ch
= *input_line_pointer
;
16622 *input_line_pointer
= '\0';
16624 if (strchr (name
, ','))
16626 /* Generic ".set" directive; use the generic handler. */
16627 *input_line_pointer
= ch
;
16628 input_line_pointer
= name
;
16633 if (strcmp (name
, "reorder") == 0)
16635 if (mips_opts
.noreorder
)
16638 else if (strcmp (name
, "noreorder") == 0)
16640 if (!mips_opts
.noreorder
)
16641 start_noreorder ();
16643 else if (strcmp (name
, "macro") == 0)
16644 mips_opts
.warn_about_macros
= 0;
16645 else if (strcmp (name
, "nomacro") == 0)
16647 if (mips_opts
.noreorder
== 0)
16648 as_bad (_("`noreorder' must be set before `nomacro'"));
16649 mips_opts
.warn_about_macros
= 1;
16651 else if (strcmp (name
, "gp=default") == 0)
16652 mips_opts
.gp
= file_mips_opts
.gp
;
16653 else if (strcmp (name
, "fp=default") == 0)
16654 mips_opts
.fp
= file_mips_opts
.fp
;
16655 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16657 mips_opts
.isa
= file_mips_opts
.isa
;
16658 mips_opts
.arch
= file_mips_opts
.arch
;
16659 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16660 mips_opts
.gp
= file_mips_opts
.gp
;
16661 mips_opts
.fp
= file_mips_opts
.fp
;
16663 else if (strcmp (name
, "push") == 0)
16665 struct mips_option_stack
*s
;
16667 s
= XNEW (struct mips_option_stack
);
16668 s
->next
= mips_opts_stack
;
16669 s
->options
= mips_opts
;
16670 mips_opts_stack
= s
;
16672 else if (strcmp (name
, "pop") == 0)
16674 struct mips_option_stack
*s
;
16676 s
= mips_opts_stack
;
16678 as_bad (_(".set pop with no .set push"));
16681 /* If we're changing the reorder mode we need to handle
16682 delay slots correctly. */
16683 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16684 start_noreorder ();
16685 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16688 mips_opts
= s
->options
;
16689 mips_opts_stack
= s
->next
;
16695 type
= parse_code_option (name
);
16696 if (type
== OPTION_TYPE_BAD
)
16697 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16700 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16701 registers based on what is supported by the arch/cpu. */
16702 if (type
== OPTION_TYPE_ISA
)
16704 switch (mips_opts
.isa
)
16709 /* MIPS I cannot support FPXX. */
16711 /* fall-through. */
16718 if (mips_opts
.fp
!= 0)
16734 if (mips_opts
.fp
!= 0)
16736 if (mips_opts
.arch
== CPU_R5900
)
16743 as_bad (_("unknown ISA level %s"), name
+ 4);
16748 mips_check_options (&mips_opts
, FALSE
);
16750 mips_check_isa_supports_ases ();
16751 *input_line_pointer
= ch
;
16752 demand_empty_rest_of_line ();
16755 /* Handle the .module pseudo-op. */
16758 s_module (int ignore ATTRIBUTE_UNUSED
)
16760 char *name
= input_line_pointer
, ch
;
16762 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16763 ++input_line_pointer
;
16764 ch
= *input_line_pointer
;
16765 *input_line_pointer
= '\0';
16767 if (!file_mips_opts_checked
)
16769 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16770 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16772 /* Update module level settings from mips_opts. */
16773 file_mips_opts
= mips_opts
;
16776 as_bad (_(".module is not permitted after generating code"));
16778 *input_line_pointer
= ch
;
16779 demand_empty_rest_of_line ();
16782 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16783 .option pic2. It means to generate SVR4 PIC calls. */
16786 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16788 mips_pic
= SVR4_PIC
;
16789 mips_abicalls
= TRUE
;
16791 if (g_switch_seen
&& g_switch_value
!= 0)
16792 as_warn (_("-G may not be used with SVR4 PIC code"));
16793 g_switch_value
= 0;
16795 bfd_set_gp_size (stdoutput
, 0);
16796 demand_empty_rest_of_line ();
16799 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16800 PIC code. It sets the $gp register for the function based on the
16801 function address, which is in the register named in the argument.
16802 This uses a relocation against _gp_disp, which is handled specially
16803 by the linker. The result is:
16804 lui $gp,%hi(_gp_disp)
16805 addiu $gp,$gp,%lo(_gp_disp)
16806 addu $gp,$gp,.cpload argument
16807 The .cpload argument is normally $25 == $t9.
16809 The -mno-shared option changes this to:
16810 lui $gp,%hi(__gnu_local_gp)
16811 addiu $gp,$gp,%lo(__gnu_local_gp)
16812 and the argument is ignored. This saves an instruction, but the
16813 resulting code is not position independent; it uses an absolute
16814 address for __gnu_local_gp. Thus code assembled with -mno-shared
16815 can go into an ordinary executable, but not into a shared library. */
16818 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16824 file_mips_check_options ();
16826 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16827 .cpload is ignored. */
16828 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16834 if (mips_opts
.mips16
)
16836 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16837 ignore_rest_of_line ();
16841 /* .cpload should be in a .set noreorder section. */
16842 if (mips_opts
.noreorder
== 0)
16843 as_warn (_(".cpload not in noreorder section"));
16845 reg
= tc_get_register (0);
16847 /* If we need to produce a 64-bit address, we are better off using
16848 the default instruction sequence. */
16849 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16851 ex
.X_op
= O_symbol
;
16852 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16854 ex
.X_op_symbol
= NULL
;
16855 ex
.X_add_number
= 0;
16857 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16858 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16860 mips_mark_labels ();
16861 mips_assembling_insn
= TRUE
;
16864 macro_build_lui (&ex
, mips_gp_register
);
16865 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16866 mips_gp_register
, BFD_RELOC_LO16
);
16868 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16869 mips_gp_register
, reg
);
16872 mips_assembling_insn
= FALSE
;
16873 demand_empty_rest_of_line ();
16876 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16877 .cpsetup $reg1, offset|$reg2, label
16879 If offset is given, this results in:
16880 sd $gp, offset($sp)
16881 lui $gp, %hi(%neg(%gp_rel(label)))
16882 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16883 daddu $gp, $gp, $reg1
16885 If $reg2 is given, this results in:
16887 lui $gp, %hi(%neg(%gp_rel(label)))
16888 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16889 daddu $gp, $gp, $reg1
16890 $reg1 is normally $25 == $t9.
16892 The -mno-shared option replaces the last three instructions with
16894 addiu $gp,$gp,%lo(_gp) */
16897 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16899 expressionS ex_off
;
16900 expressionS ex_sym
;
16903 file_mips_check_options ();
16905 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16906 We also need NewABI support. */
16907 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16913 if (mips_opts
.mips16
)
16915 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16916 ignore_rest_of_line ();
16920 reg1
= tc_get_register (0);
16921 SKIP_WHITESPACE ();
16922 if (*input_line_pointer
!= ',')
16924 as_bad (_("missing argument separator ',' for .cpsetup"));
16928 ++input_line_pointer
;
16929 SKIP_WHITESPACE ();
16930 if (*input_line_pointer
== '$')
16932 mips_cpreturn_register
= tc_get_register (0);
16933 mips_cpreturn_offset
= -1;
16937 mips_cpreturn_offset
= get_absolute_expression ();
16938 mips_cpreturn_register
= -1;
16940 SKIP_WHITESPACE ();
16941 if (*input_line_pointer
!= ',')
16943 as_bad (_("missing argument separator ',' for .cpsetup"));
16947 ++input_line_pointer
;
16948 SKIP_WHITESPACE ();
16949 expression (&ex_sym
);
16951 mips_mark_labels ();
16952 mips_assembling_insn
= TRUE
;
16955 if (mips_cpreturn_register
== -1)
16957 ex_off
.X_op
= O_constant
;
16958 ex_off
.X_add_symbol
= NULL
;
16959 ex_off
.X_op_symbol
= NULL
;
16960 ex_off
.X_add_number
= mips_cpreturn_offset
;
16962 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16963 BFD_RELOC_LO16
, SP
);
16966 move_register (mips_cpreturn_register
, mips_gp_register
);
16968 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16970 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16971 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16974 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16975 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16976 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16978 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16979 mips_gp_register
, reg1
);
16985 ex
.X_op
= O_symbol
;
16986 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16987 ex
.X_op_symbol
= NULL
;
16988 ex
.X_add_number
= 0;
16990 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16991 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16993 macro_build_lui (&ex
, mips_gp_register
);
16994 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16995 mips_gp_register
, BFD_RELOC_LO16
);
17000 mips_assembling_insn
= FALSE
;
17001 demand_empty_rest_of_line ();
17005 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17007 file_mips_check_options ();
17009 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17010 .cplocal is ignored. */
17011 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17017 if (mips_opts
.mips16
)
17019 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17020 ignore_rest_of_line ();
17024 mips_gp_register
= tc_get_register (0);
17025 demand_empty_rest_of_line ();
17028 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17029 offset from $sp. The offset is remembered, and after making a PIC
17030 call $gp is restored from that location. */
17033 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17037 file_mips_check_options ();
17039 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17040 .cprestore is ignored. */
17041 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17047 if (mips_opts
.mips16
)
17049 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17050 ignore_rest_of_line ();
17054 mips_cprestore_offset
= get_absolute_expression ();
17055 mips_cprestore_valid
= 1;
17057 ex
.X_op
= O_constant
;
17058 ex
.X_add_symbol
= NULL
;
17059 ex
.X_op_symbol
= NULL
;
17060 ex
.X_add_number
= mips_cprestore_offset
;
17062 mips_mark_labels ();
17063 mips_assembling_insn
= TRUE
;
17066 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17067 SP
, HAVE_64BIT_ADDRESSES
);
17070 mips_assembling_insn
= FALSE
;
17071 demand_empty_rest_of_line ();
17074 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17075 was given in the preceding .cpsetup, it results in:
17076 ld $gp, offset($sp)
17078 If a register $reg2 was given there, it results in:
17079 or $gp, $reg2, $0 */
17082 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17086 file_mips_check_options ();
17088 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17089 We also need NewABI support. */
17090 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17096 if (mips_opts
.mips16
)
17098 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17099 ignore_rest_of_line ();
17103 mips_mark_labels ();
17104 mips_assembling_insn
= TRUE
;
17107 if (mips_cpreturn_register
== -1)
17109 ex
.X_op
= O_constant
;
17110 ex
.X_add_symbol
= NULL
;
17111 ex
.X_op_symbol
= NULL
;
17112 ex
.X_add_number
= mips_cpreturn_offset
;
17114 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17117 move_register (mips_gp_register
, mips_cpreturn_register
);
17121 mips_assembling_insn
= FALSE
;
17122 demand_empty_rest_of_line ();
17125 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17126 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17127 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17128 debug information or MIPS16 TLS. */
17131 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17132 bfd_reloc_code_real_type rtype
)
17139 if (ex
.X_op
!= O_symbol
)
17141 as_bad (_("unsupported use of %s"), dirstr
);
17142 ignore_rest_of_line ();
17145 p
= frag_more (bytes
);
17146 md_number_to_chars (p
, 0, bytes
);
17147 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17148 demand_empty_rest_of_line ();
17149 mips_clear_insn_labels ();
17152 /* Handle .dtprelword. */
17155 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17157 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17160 /* Handle .dtpreldword. */
17163 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17165 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17168 /* Handle .tprelword. */
17171 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17173 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17176 /* Handle .tpreldword. */
17179 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17181 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17184 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17185 code. It sets the offset to use in gp_rel relocations. */
17188 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17190 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17191 We also need NewABI support. */
17192 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17198 mips_gprel_offset
= get_absolute_expression ();
17200 demand_empty_rest_of_line ();
17203 /* Handle the .gpword pseudo-op. This is used when generating PIC
17204 code. It generates a 32 bit GP relative reloc. */
17207 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17209 segment_info_type
*si
;
17210 struct insn_label_list
*l
;
17214 /* When not generating PIC code, this is treated as .word. */
17215 if (mips_pic
!= SVR4_PIC
)
17221 si
= seg_info (now_seg
);
17222 l
= si
->label_list
;
17223 mips_emit_delays ();
17225 mips_align (2, 0, l
);
17228 mips_clear_insn_labels ();
17230 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17232 as_bad (_("unsupported use of .gpword"));
17233 ignore_rest_of_line ();
17237 md_number_to_chars (p
, 0, 4);
17238 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17239 BFD_RELOC_GPREL32
);
17241 demand_empty_rest_of_line ();
17245 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17247 segment_info_type
*si
;
17248 struct insn_label_list
*l
;
17252 /* When not generating PIC code, this is treated as .dword. */
17253 if (mips_pic
!= SVR4_PIC
)
17259 si
= seg_info (now_seg
);
17260 l
= si
->label_list
;
17261 mips_emit_delays ();
17263 mips_align (3, 0, l
);
17266 mips_clear_insn_labels ();
17268 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17270 as_bad (_("unsupported use of .gpdword"));
17271 ignore_rest_of_line ();
17275 md_number_to_chars (p
, 0, 8);
17276 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17277 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17279 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17280 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17281 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17283 demand_empty_rest_of_line ();
17286 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17287 tables. It generates a R_MIPS_EH reloc. */
17290 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17295 mips_emit_delays ();
17298 mips_clear_insn_labels ();
17300 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17302 as_bad (_("unsupported use of .ehword"));
17303 ignore_rest_of_line ();
17307 md_number_to_chars (p
, 0, 4);
17308 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17309 BFD_RELOC_32_PCREL
);
17311 demand_empty_rest_of_line ();
17314 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17315 tables in SVR4 PIC code. */
17318 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17322 file_mips_check_options ();
17324 /* This is ignored when not generating SVR4 PIC code. */
17325 if (mips_pic
!= SVR4_PIC
)
17331 mips_mark_labels ();
17332 mips_assembling_insn
= TRUE
;
17334 /* Add $gp to the register named as an argument. */
17336 reg
= tc_get_register (0);
17337 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17340 mips_assembling_insn
= FALSE
;
17341 demand_empty_rest_of_line ();
17344 /* Handle the .insn pseudo-op. This marks instruction labels in
17345 mips16/micromips mode. This permits the linker to handle them specially,
17346 such as generating jalx instructions when needed. We also make
17347 them odd for the duration of the assembly, in order to generate the
17348 right sort of code. We will make them even in the adjust_symtab
17349 routine, while leaving them marked. This is convenient for the
17350 debugger and the disassembler. The linker knows to make them odd
17354 s_insn (int ignore ATTRIBUTE_UNUSED
)
17356 file_mips_check_options ();
17357 file_ase_mips16
|= mips_opts
.mips16
;
17358 file_ase_micromips
|= mips_opts
.micromips
;
17360 mips_mark_labels ();
17362 demand_empty_rest_of_line ();
17365 /* Handle the .nan pseudo-op. */
17368 s_nan (int ignore ATTRIBUTE_UNUSED
)
17370 static const char str_legacy
[] = "legacy";
17371 static const char str_2008
[] = "2008";
17374 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17376 if (i
== sizeof (str_2008
) - 1
17377 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17379 else if (i
== sizeof (str_legacy
) - 1
17380 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17382 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17385 as_bad (_("`%s' does not support legacy NaN"),
17386 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17389 as_bad (_("bad .nan directive"));
17391 input_line_pointer
+= i
;
17392 demand_empty_rest_of_line ();
17395 /* Handle a .stab[snd] directive. Ideally these directives would be
17396 implemented in a transparent way, so that removing them would not
17397 have any effect on the generated instructions. However, s_stab
17398 internally changes the section, so in practice we need to decide
17399 now whether the preceding label marks compressed code. We do not
17400 support changing the compression mode of a label after a .stab*
17401 directive, such as in:
17407 so the current mode wins. */
17410 s_mips_stab (int type
)
17412 file_mips_check_options ();
17413 mips_mark_labels ();
17417 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17420 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17427 c
= get_symbol_name (&name
);
17428 symbolP
= symbol_find_or_make (name
);
17429 S_SET_WEAK (symbolP
);
17430 *input_line_pointer
= c
;
17432 SKIP_WHITESPACE_AFTER_NAME ();
17434 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17436 if (S_IS_DEFINED (symbolP
))
17438 as_bad (_("ignoring attempt to redefine symbol %s"),
17439 S_GET_NAME (symbolP
));
17440 ignore_rest_of_line ();
17444 if (*input_line_pointer
== ',')
17446 ++input_line_pointer
;
17447 SKIP_WHITESPACE ();
17451 if (exp
.X_op
!= O_symbol
)
17453 as_bad (_("bad .weakext directive"));
17454 ignore_rest_of_line ();
17457 symbol_set_value_expression (symbolP
, &exp
);
17460 demand_empty_rest_of_line ();
17463 /* Parse a register string into a number. Called from the ECOFF code
17464 to parse .frame. The argument is non-zero if this is the frame
17465 register, so that we can record it in mips_frame_reg. */
17468 tc_get_register (int frame
)
17472 SKIP_WHITESPACE ();
17473 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17477 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17478 mips_frame_reg_valid
= 1;
17479 mips_cprestore_valid
= 0;
17485 md_section_align (asection
*seg
, valueT addr
)
17487 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17489 /* We don't need to align ELF sections to the full alignment.
17490 However, Irix 5 may prefer that we align them at least to a 16
17491 byte boundary. We don't bother to align the sections if we
17492 are targeted for an embedded system. */
17493 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17498 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17501 /* Utility routine, called from above as well. If called while the
17502 input file is still being read, it's only an approximation. (For
17503 example, a symbol may later become defined which appeared to be
17504 undefined earlier.) */
17507 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17512 if (g_switch_value
> 0)
17514 const char *symname
;
17517 /* Find out whether this symbol can be referenced off the $gp
17518 register. It can be if it is smaller than the -G size or if
17519 it is in the .sdata or .sbss section. Certain symbols can
17520 not be referenced off the $gp, although it appears as though
17522 symname
= S_GET_NAME (sym
);
17523 if (symname
!= (const char *) NULL
17524 && (strcmp (symname
, "eprol") == 0
17525 || strcmp (symname
, "etext") == 0
17526 || strcmp (symname
, "_gp") == 0
17527 || strcmp (symname
, "edata") == 0
17528 || strcmp (symname
, "_fbss") == 0
17529 || strcmp (symname
, "_fdata") == 0
17530 || strcmp (symname
, "_ftext") == 0
17531 || strcmp (symname
, "end") == 0
17532 || strcmp (symname
, "_gp_disp") == 0))
17534 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17536 #ifndef NO_ECOFF_DEBUGGING
17537 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17538 && (symbol_get_obj (sym
)->ecoff_extern_size
17539 <= g_switch_value
))
17541 /* We must defer this decision until after the whole
17542 file has been read, since there might be a .extern
17543 after the first use of this symbol. */
17544 || (before_relaxing
17545 #ifndef NO_ECOFF_DEBUGGING
17546 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17548 && S_GET_VALUE (sym
) == 0)
17549 || (S_GET_VALUE (sym
) != 0
17550 && S_GET_VALUE (sym
) <= g_switch_value
)))
17554 const char *segname
;
17556 segname
= segment_name (S_GET_SEGMENT (sym
));
17557 gas_assert (strcmp (segname
, ".lit8") != 0
17558 && strcmp (segname
, ".lit4") != 0);
17559 change
= (strcmp (segname
, ".sdata") != 0
17560 && strcmp (segname
, ".sbss") != 0
17561 && strncmp (segname
, ".sdata.", 7) != 0
17562 && strncmp (segname
, ".sbss.", 6) != 0
17563 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17564 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17569 /* We are not optimizing for the $gp register. */
17574 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17577 pic_need_relax (symbolS
*sym
)
17581 /* Handle the case of a symbol equated to another symbol. */
17582 while (symbol_equated_reloc_p (sym
))
17586 /* It's possible to get a loop here in a badly written program. */
17587 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17593 if (symbol_section_p (sym
))
17596 symsec
= S_GET_SEGMENT (sym
);
17598 /* This must duplicate the test in adjust_reloc_syms. */
17599 return (!bfd_is_und_section (symsec
)
17600 && !bfd_is_abs_section (symsec
)
17601 && !bfd_is_com_section (symsec
)
17602 /* A global or weak symbol is treated as external. */
17603 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17606 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17607 convert a section-relative value VAL to the equivalent PC-relative
17611 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17612 offsetT val
, long stretch
)
17617 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17619 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17621 /* If the relax_marker of the symbol fragment differs from the
17622 relax_marker of this fragment, we have not yet adjusted the
17623 symbol fragment fr_address. We want to add in STRETCH in
17624 order to get a better estimate of the address. This
17625 particularly matters because of the shift bits. */
17626 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17630 /* Adjust stretch for any alignment frag. Note that if have
17631 been expanding the earlier code, the symbol may be
17632 defined in what appears to be an earlier frag. FIXME:
17633 This doesn't handle the fr_subtype field, which specifies
17634 a maximum number of bytes to skip when doing an
17636 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17638 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17641 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17643 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17652 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17654 /* The base address rules are complicated. The base address of
17655 a branch is the following instruction. The base address of a
17656 PC relative load or add is the instruction itself, but if it
17657 is in a delay slot (in which case it can not be extended) use
17658 the address of the instruction whose delay slot it is in. */
17659 if (pcrel_op
->include_isa_bit
)
17663 /* If we are currently assuming that this frag should be
17664 extended, then the current address is two bytes higher. */
17665 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17668 /* Ignore the low bit in the target, since it will be set
17669 for a text label. */
17672 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17674 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17677 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17682 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17683 extended opcode. SEC is the section the frag is in. */
17686 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17688 const struct mips_int_operand
*operand
;
17693 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17695 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17698 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17699 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17700 operand
= mips16_immed_operand (type
, FALSE
);
17701 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17702 || (operand
->root
.type
== OP_PCREL
17704 : !bfd_is_abs_section (symsec
)))
17707 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17709 if (operand
->root
.type
== OP_PCREL
)
17711 const struct mips_pcrel_operand
*pcrel_op
;
17714 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17717 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17718 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17720 /* If any of the shifted bits are set, we must use an extended
17721 opcode. If the address depends on the size of this
17722 instruction, this can lead to a loop, so we arrange to always
17723 use an extended opcode. */
17724 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17726 fragp
->fr_subtype
=
17727 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17731 /* If we are about to mark a frag as extended because the value
17732 is precisely the next value above maxtiny, then there is a
17733 chance of an infinite loop as in the following code:
17738 In this case when the la is extended, foo is 0x3fc bytes
17739 away, so the la can be shrunk, but then foo is 0x400 away, so
17740 the la must be extended. To avoid this loop, we mark the
17741 frag as extended if it was small, and is about to become
17742 extended with the next value above maxtiny. */
17743 maxtiny
= mips_int_operand_max (operand
);
17744 if (val
== maxtiny
+ (1 << operand
->shift
)
17745 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17747 fragp
->fr_subtype
=
17748 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17753 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17756 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17757 macro expansion. SEC is the section the frag is in. We only
17758 support PC-relative instructions (LA, DLA, LW, LD) here, in
17759 non-PIC code using 32-bit addressing. */
17762 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17764 const struct mips_pcrel_operand
*pcrel_op
;
17765 const struct mips_int_operand
*operand
;
17770 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17772 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17774 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17777 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17783 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17784 if (bfd_is_abs_section (symsec
))
17786 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17788 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17791 operand
= mips16_immed_operand (type
, TRUE
);
17792 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17793 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17794 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17796 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17803 /* Compute the length of a branch sequence, and adjust the
17804 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17805 worst-case length is computed, with UPDATE being used to indicate
17806 whether an unconditional (-1), branch-likely (+1) or regular (0)
17807 branch is to be computed. */
17809 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17811 bfd_boolean toofar
;
17815 && S_IS_DEFINED (fragp
->fr_symbol
)
17816 && !S_IS_WEAK (fragp
->fr_symbol
)
17817 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17822 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17824 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17828 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17831 /* If the symbol is not defined or it's in a different segment,
17832 we emit the long sequence. */
17835 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17837 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17838 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17839 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17840 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17841 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17847 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17850 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17852 /* Additional space for PIC loading of target address. */
17854 if (mips_opts
.isa
== ISA_MIPS1
)
17855 /* Additional space for $at-stabilizing nop. */
17859 /* If branch is conditional. */
17860 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17867 /* Get a FRAG's branch instruction delay slot size, either from the
17868 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17869 or SHORT_INSN_SIZE otherwise. */
17872 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17874 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17877 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17879 return short_insn_size
;
17882 /* Compute the length of a branch sequence, and adjust the
17883 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17884 worst-case length is computed, with UPDATE being used to indicate
17885 whether an unconditional (-1), or regular (0) branch is to be
17889 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17891 bfd_boolean insn32
= TRUE
;
17892 bfd_boolean nods
= TRUE
;
17893 bfd_boolean pic
= TRUE
;
17894 bfd_boolean al
= TRUE
;
17895 int short_insn_size
;
17896 bfd_boolean toofar
;
17901 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17902 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17903 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17904 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17906 short_insn_size
= insn32
? 4 : 2;
17909 && S_IS_DEFINED (fragp
->fr_symbol
)
17910 && !S_IS_WEAK (fragp
->fr_symbol
)
17911 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17916 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17917 /* Ignore the low bit in the target, since it will be set
17918 for a text label. */
17919 if ((val
& 1) != 0)
17922 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17926 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17929 /* If the symbol is not defined or it's in a different segment,
17930 we emit the long sequence. */
17933 if (fragp
&& update
17934 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17935 fragp
->fr_subtype
= (toofar
17936 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17937 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17942 bfd_boolean compact_known
= fragp
!= NULL
;
17943 bfd_boolean compact
= FALSE
;
17944 bfd_boolean uncond
;
17948 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17949 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17952 uncond
= update
< 0;
17954 /* If label is out of range, we turn branch <br>:
17956 <br> label # 4 bytes
17963 # compact && (!PIC || insn32)
17966 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17967 length
+= short_insn_size
;
17969 /* If assembling PIC code, we further turn:
17975 lw/ld at, %got(label)(gp) # 4 bytes
17976 d/addiu at, %lo(label) # 4 bytes
17977 jr/c at # 2/4 bytes
17980 length
+= 4 + short_insn_size
;
17982 /* Add an extra nop if the jump has no compact form and we need
17983 to fill the delay slot. */
17984 if ((!pic
|| al
) && nods
)
17986 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17987 : short_insn_size
);
17989 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17991 <brneg> 0f # 4 bytes
17992 nop # 2/4 bytes if !compact
17995 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17999 /* Add an extra nop to fill the delay slot. */
18000 gas_assert (fragp
);
18001 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18007 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18008 bit accordingly. */
18011 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18013 bfd_boolean toofar
;
18016 && S_IS_DEFINED (fragp
->fr_symbol
)
18017 && !S_IS_WEAK (fragp
->fr_symbol
)
18018 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18024 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18025 /* Ignore the low bit in the target, since it will be set
18026 for a text label. */
18027 if ((val
& 1) != 0)
18030 /* Assume this is a 2-byte branch. */
18031 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18033 /* We try to avoid the infinite loop by not adding 2 more bytes for
18038 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18040 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18041 else if (type
== 'E')
18042 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18047 /* If the symbol is not defined or it's in a different segment,
18048 we emit a normal 32-bit branch. */
18051 if (fragp
&& update
18052 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18054 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18055 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18063 /* Estimate the size of a frag before relaxing. Unless this is the
18064 mips16, we are not really relaxing here, and the final size is
18065 encoded in the subtype information. For the mips16, we have to
18066 decide whether we are using an extended opcode or not. */
18069 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18073 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18076 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18078 return fragp
->fr_var
;
18081 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18083 /* We don't want to modify the EXTENDED bit here; it might get us
18084 into infinite loops. We change it only in mips_relax_frag(). */
18085 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18086 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18088 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18091 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18095 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18096 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18097 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18098 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18099 fragp
->fr_var
= length
;
18104 if (mips_pic
== VXWORKS_PIC
)
18105 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18107 else if (RELAX_PIC (fragp
->fr_subtype
))
18108 change
= pic_need_relax (fragp
->fr_symbol
);
18110 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18114 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18115 return -RELAX_FIRST (fragp
->fr_subtype
);
18118 return -RELAX_SECOND (fragp
->fr_subtype
);
18121 /* This is called to see whether a reloc against a defined symbol
18122 should be converted into a reloc against a section. */
18125 mips_fix_adjustable (fixS
*fixp
)
18127 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18128 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18131 if (fixp
->fx_addsy
== NULL
)
18134 /* Allow relocs used for EH tables. */
18135 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18138 /* If symbol SYM is in a mergeable section, relocations of the form
18139 SYM + 0 can usually be made section-relative. The mergeable data
18140 is then identified by the section offset rather than by the symbol.
18142 However, if we're generating REL LO16 relocations, the offset is split
18143 between the LO16 and partnering high part relocation. The linker will
18144 need to recalculate the complete offset in order to correctly identify
18147 The linker has traditionally not looked for the partnering high part
18148 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18149 placed anywhere. Rather than break backwards compatibility by changing
18150 this, it seems better not to force the issue, and instead keep the
18151 original symbol. This will work with either linker behavior. */
18152 if ((lo16_reloc_p (fixp
->fx_r_type
)
18153 || reloc_needs_lo_p (fixp
->fx_r_type
))
18154 && HAVE_IN_PLACE_ADDENDS
18155 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18158 /* There is no place to store an in-place offset for JALR relocations. */
18159 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18162 /* Likewise an in-range offset of limited PC-relative relocations may
18163 overflow the in-place relocatable field if recalculated against the
18164 start address of the symbol's containing section.
18166 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18167 section relative to allow linker relaxations to be performed later on. */
18168 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18169 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18172 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18173 to a floating-point stub. The same is true for non-R_MIPS16_26
18174 relocations against MIPS16 functions; in this case, the stub becomes
18175 the function's canonical address.
18177 Floating-point stubs are stored in unique .mips16.call.* or
18178 .mips16.fn.* sections. If a stub T for function F is in section S,
18179 the first relocation in section S must be against F; this is how the
18180 linker determines the target function. All relocations that might
18181 resolve to T must also be against F. We therefore have the following
18182 restrictions, which are given in an intentionally-redundant way:
18184 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18187 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18188 if that stub might be used.
18190 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18193 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18194 that stub might be used.
18196 There is a further restriction:
18198 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18199 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18200 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18201 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18202 against MIPS16 or microMIPS symbols because we need to keep the
18203 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18204 detection and JAL or BAL to JALX instruction conversion in the
18207 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18208 against a MIPS16 symbol. We deal with (5) by additionally leaving
18209 alone any jump and branch relocations against a microMIPS symbol.
18211 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18212 relocation against some symbol R, no relocation against R may be
18213 reduced. (Note that this deals with (2) as well as (1) because
18214 relocations against global symbols will never be reduced on ELF
18215 targets.) This approach is a little simpler than trying to detect
18216 stub sections, and gives the "all or nothing" per-symbol consistency
18217 that we have for MIPS16 symbols. */
18218 if (fixp
->fx_subsy
== NULL
18219 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18220 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18221 && (jmp_reloc_p (fixp
->fx_r_type
)
18222 || b_reloc_p (fixp
->fx_r_type
)))
18223 || *symbol_get_tc (fixp
->fx_addsy
)))
18229 /* Translate internal representation of relocation info to BFD target
18233 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18235 static arelent
*retval
[4];
18237 bfd_reloc_code_real_type code
;
18239 memset (retval
, 0, sizeof(retval
));
18240 reloc
= retval
[0] = XCNEW (arelent
);
18241 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18242 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18243 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18245 if (fixp
->fx_pcrel
)
18247 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18248 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18249 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18250 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18251 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18252 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18253 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18254 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18255 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18256 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18257 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18258 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18260 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18261 Relocations want only the symbol offset. */
18262 switch (fixp
->fx_r_type
)
18264 case BFD_RELOC_MIPS_18_PCREL_S3
:
18265 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18268 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18272 else if (HAVE_IN_PLACE_ADDENDS
18273 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18274 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18275 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18277 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18278 addend accordingly. */
18279 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18282 reloc
->addend
= fixp
->fx_addnumber
;
18284 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18285 entry to be used in the relocation's section offset. */
18286 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18288 reloc
->address
= reloc
->addend
;
18292 code
= fixp
->fx_r_type
;
18294 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18295 if (reloc
->howto
== NULL
)
18297 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18298 _("cannot represent %s relocation in this object file"
18300 bfd_get_reloc_code_name (code
));
18307 /* Relax a machine dependent frag. This returns the amount by which
18308 the current size of the frag should change. */
18311 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18313 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18315 offsetT old_var
= fragp
->fr_var
;
18317 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18319 return fragp
->fr_var
- old_var
;
18322 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18324 offsetT old_var
= fragp
->fr_var
;
18325 offsetT new_var
= 4;
18327 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18328 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18329 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18330 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18331 fragp
->fr_var
= new_var
;
18333 return new_var
- old_var
;
18336 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18339 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18341 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18343 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18344 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18346 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18348 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18354 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18356 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18358 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18359 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18360 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18362 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18364 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18372 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18374 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18376 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18377 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18378 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18382 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18383 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18390 /* Convert a machine dependent frag. */
18393 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18395 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18398 unsigned long insn
;
18401 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18402 insn
= read_insn (buf
);
18404 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18406 /* We generate a fixup instead of applying it right now
18407 because, if there are linker relaxations, we're going to
18408 need the relocations. */
18409 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18410 fragp
->fr_symbol
, fragp
->fr_offset
,
18411 TRUE
, BFD_RELOC_16_PCREL_S2
);
18412 fixp
->fx_file
= fragp
->fr_file
;
18413 fixp
->fx_line
= fragp
->fr_line
;
18415 buf
= write_insn (buf
, insn
);
18421 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18422 _("relaxed out-of-range branch into a jump"));
18424 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18427 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18429 /* Reverse the branch. */
18430 switch ((insn
>> 28) & 0xf)
18433 if ((insn
& 0xff000000) == 0x47000000
18434 || (insn
& 0xff600000) == 0x45600000)
18436 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18437 reversed by tweaking bit 23. */
18438 insn
^= 0x00800000;
18442 /* bc[0-3][tf]l? instructions can have the condition
18443 reversed by tweaking a single TF bit, and their
18444 opcodes all have 0x4???????. */
18445 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18446 insn
^= 0x00010000;
18451 /* bltz 0x04000000 bgez 0x04010000
18452 bltzal 0x04100000 bgezal 0x04110000 */
18453 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18454 insn
^= 0x00010000;
18458 /* beq 0x10000000 bne 0x14000000
18459 blez 0x18000000 bgtz 0x1c000000 */
18460 insn
^= 0x04000000;
18468 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18470 /* Clear the and-link bit. */
18471 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18473 /* bltzal 0x04100000 bgezal 0x04110000
18474 bltzall 0x04120000 bgezall 0x04130000 */
18475 insn
&= ~0x00100000;
18478 /* Branch over the branch (if the branch was likely) or the
18479 full jump (not likely case). Compute the offset from the
18480 current instruction to branch to. */
18481 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18485 /* How many bytes in instructions we've already emitted? */
18486 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18487 /* How many bytes in instructions from here to the end? */
18488 i
= fragp
->fr_var
- i
;
18490 /* Convert to instruction count. */
18492 /* Branch counts from the next instruction. */
18495 /* Branch over the jump. */
18496 buf
= write_insn (buf
, insn
);
18499 buf
= write_insn (buf
, 0);
18501 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18503 /* beql $0, $0, 2f */
18505 /* Compute the PC offset from the current instruction to
18506 the end of the variable frag. */
18507 /* How many bytes in instructions we've already emitted? */
18508 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18509 /* How many bytes in instructions from here to the end? */
18510 i
= fragp
->fr_var
- i
;
18511 /* Convert to instruction count. */
18513 /* Don't decrement i, because we want to branch over the
18517 buf
= write_insn (buf
, insn
);
18518 buf
= write_insn (buf
, 0);
18522 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18525 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18526 ? 0x0c000000 : 0x08000000);
18528 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18529 fragp
->fr_symbol
, fragp
->fr_offset
,
18530 FALSE
, BFD_RELOC_MIPS_JMP
);
18531 fixp
->fx_file
= fragp
->fr_file
;
18532 fixp
->fx_line
= fragp
->fr_line
;
18534 buf
= write_insn (buf
, insn
);
18538 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18540 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18541 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18542 insn
|= at
<< OP_SH_RT
;
18544 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18545 fragp
->fr_symbol
, fragp
->fr_offset
,
18546 FALSE
, BFD_RELOC_MIPS_GOT16
);
18547 fixp
->fx_file
= fragp
->fr_file
;
18548 fixp
->fx_line
= fragp
->fr_line
;
18550 buf
= write_insn (buf
, insn
);
18552 if (mips_opts
.isa
== ISA_MIPS1
)
18554 buf
= write_insn (buf
, 0);
18556 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18557 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18558 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18560 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18561 fragp
->fr_symbol
, fragp
->fr_offset
,
18562 FALSE
, BFD_RELOC_LO16
);
18563 fixp
->fx_file
= fragp
->fr_file
;
18564 fixp
->fx_line
= fragp
->fr_line
;
18566 buf
= write_insn (buf
, insn
);
18569 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18573 insn
|= at
<< OP_SH_RS
;
18575 buf
= write_insn (buf
, insn
);
18579 fragp
->fr_fix
+= fragp
->fr_var
;
18580 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18584 /* Relax microMIPS branches. */
18585 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18587 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18588 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18589 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18590 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18591 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18592 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18593 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18594 bfd_boolean short_ds
;
18595 unsigned long insn
;
18598 fragp
->fr_fix
+= fragp
->fr_var
;
18600 /* Handle 16-bit branches that fit or are forced to fit. */
18601 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18603 /* We generate a fixup instead of applying it right now,
18604 because if there is linker relaxation, we're going to
18605 need the relocations. */
18609 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18610 fragp
->fr_symbol
, fragp
->fr_offset
,
18611 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18614 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18615 fragp
->fr_symbol
, fragp
->fr_offset
,
18616 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18622 fixp
->fx_file
= fragp
->fr_file
;
18623 fixp
->fx_line
= fragp
->fr_line
;
18625 /* These relocations can have an addend that won't fit in
18627 fixp
->fx_no_overflow
= 1;
18632 /* Handle 32-bit branches that fit or are forced to fit. */
18633 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18634 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18636 /* We generate a fixup instead of applying it right now,
18637 because if there is linker relaxation, we're going to
18638 need the relocations. */
18639 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18640 fragp
->fr_symbol
, fragp
->fr_offset
,
18641 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18642 fixp
->fx_file
= fragp
->fr_file
;
18643 fixp
->fx_line
= fragp
->fr_line
;
18647 insn
= read_compressed_insn (buf
, 4);
18652 /* Check the short-delay-slot bit. */
18653 if (!al
|| (insn
& 0x02000000) != 0)
18654 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18656 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18659 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18664 /* Relax 16-bit branches to 32-bit branches. */
18667 insn
= read_compressed_insn (buf
, 2);
18669 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18670 insn
= 0x94000000; /* beq */
18671 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18673 unsigned long regno
;
18675 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18676 regno
= micromips_to_32_reg_d_map
[regno
];
18677 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18678 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18683 /* Nothing else to do, just write it out. */
18684 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18685 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18687 buf
= write_compressed_insn (buf
, insn
, 4);
18689 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18690 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18695 insn
= read_compressed_insn (buf
, 4);
18697 /* Relax 32-bit branches to a sequence of instructions. */
18698 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18699 _("relaxed out-of-range branch into a jump"));
18701 /* Set the short-delay-slot bit. */
18702 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18704 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18708 /* Reverse the branch. */
18709 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18710 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18711 insn
^= 0x20000000;
18712 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18713 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18714 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18715 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18716 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18717 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18718 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18719 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18720 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18721 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18722 insn
^= 0x00400000;
18723 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18724 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18725 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18726 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18727 insn
^= 0x00200000;
18728 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18730 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18732 insn
^= 0x00800000;
18738 /* Clear the and-link and short-delay-slot bits. */
18739 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18741 /* bltzal 0x40200000 bgezal 0x40600000 */
18742 /* bltzals 0x42200000 bgezals 0x42600000 */
18743 insn
&= ~0x02200000;
18746 /* Make a label at the end for use with the branch. */
18747 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18748 micromips_label_inc ();
18749 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18752 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18753 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18754 fixp
->fx_file
= fragp
->fr_file
;
18755 fixp
->fx_line
= fragp
->fr_line
;
18757 /* Branch over the jump. */
18758 buf
= write_compressed_insn (buf
, insn
, 4);
18764 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18766 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18772 unsigned long jal
= (short_ds
|| nods
18773 ? 0x74000000 : 0xf4000000); /* jal/s */
18775 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18776 insn
= al
? jal
: 0xd4000000;
18778 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18779 fragp
->fr_symbol
, fragp
->fr_offset
,
18780 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18781 fixp
->fx_file
= fragp
->fr_file
;
18782 fixp
->fx_line
= fragp
->fr_line
;
18784 buf
= write_compressed_insn (buf
, insn
, 4);
18786 if (compact
|| nods
)
18790 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18792 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18797 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18799 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18800 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18801 insn
|= at
<< MICROMIPSOP_SH_RT
;
18803 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18804 fragp
->fr_symbol
, fragp
->fr_offset
,
18805 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18806 fixp
->fx_file
= fragp
->fr_file
;
18807 fixp
->fx_line
= fragp
->fr_line
;
18809 buf
= write_compressed_insn (buf
, insn
, 4);
18811 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18812 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18813 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18815 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18816 fragp
->fr_symbol
, fragp
->fr_offset
,
18817 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18818 fixp
->fx_file
= fragp
->fr_file
;
18819 fixp
->fx_line
= fragp
->fr_line
;
18821 buf
= write_compressed_insn (buf
, insn
, 4);
18826 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18827 insn
|= at
<< MICROMIPSOP_SH_RS
;
18829 buf
= write_compressed_insn (buf
, insn
, 4);
18831 if (compact
|| nods
)
18833 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18837 /* jr/jrc/jalr/jalrs $at */
18838 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18839 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18841 insn
= al
? jalr
: jr
;
18842 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18844 buf
= write_compressed_insn (buf
, insn
, 2);
18849 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18851 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18856 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18860 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18863 const struct mips_int_operand
*operand
;
18866 unsigned int user_length
;
18867 bfd_boolean need_reloc
;
18868 unsigned long insn
;
18873 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18874 operand
= mips16_immed_operand (type
, FALSE
);
18876 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18877 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18878 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18880 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18881 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18882 || (operand
->root
.type
== OP_PCREL
&& !mac
18884 : !bfd_is_abs_section (symsec
)));
18886 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18888 const struct mips_pcrel_operand
*pcrel_op
;
18890 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18892 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18894 if (!mips_ignore_branch_isa
18895 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18896 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18897 _("branch to a symbol in another ISA mode"));
18898 else if ((fragp
->fr_offset
& 0x1) != 0)
18899 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18900 _("branch to misaligned address (0x%lx)"),
18904 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18906 /* Make sure the section winds up with the alignment we have
18908 if (operand
->shift
> 0)
18909 record_alignment (asec
, operand
->shift
);
18912 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18913 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18916 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18917 _("macro instruction expanded into multiple "
18918 "instructions in a branch delay slot"));
18920 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18921 _("extended instruction in a branch delay slot"));
18923 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18924 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18925 _("macro instruction expanded into multiple "
18928 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18930 insn
= read_compressed_insn (buf
, 2);
18932 insn
|= MIPS16_EXTEND
;
18934 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18936 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18948 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18949 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18951 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18957 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18959 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18960 fragp
->fr_symbol
, fragp
->fr_offset
,
18961 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18962 fixp
->fx_file
= fragp
->fr_file
;
18963 fixp
->fx_line
= fragp
->fr_line
;
18965 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18966 fragp
->fr_symbol
, fragp
->fr_offset
,
18967 FALSE
, BFD_RELOC_MIPS16_LO16
);
18968 fixp
->fx_file
= fragp
->fr_file
;
18969 fixp
->fx_line
= fragp
->fr_line
;
18974 switch (insn
& 0xf800)
18976 case 0x0800: /* ADDIU */
18977 reg
= (insn
>> 8) & 0x7;
18978 op
= 0xf0004800 | (reg
<< 8);
18980 case 0xb000: /* LW */
18981 reg
= (insn
>> 8) & 0x7;
18982 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18984 case 0xf800: /* I64 */
18985 reg
= (insn
>> 5) & 0x7;
18986 switch (insn
& 0x0700)
18988 case 0x0400: /* LD */
18989 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18991 case 0x0600: /* DADDIU */
18992 op
= 0xf000fd00 | (reg
<< 5);
19002 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19003 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19004 buf
= write_compressed_insn (buf
, new, 4);
19007 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19008 buf
= write_compressed_insn (buf
, new, 4);
19010 op
|= mips16_immed_extend (val
, 16);
19011 buf
= write_compressed_insn (buf
, op
, 4);
19013 fragp
->fr_fix
+= e2
? 8 : 12;
19017 unsigned int length
= ext
? 4 : 2;
19021 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19028 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19033 if (mac
|| reloc
== BFD_RELOC_NONE
)
19034 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19035 _("unsupported relocation"));
19038 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19039 fragp
->fr_symbol
, fragp
->fr_offset
,
19041 fixp
->fx_file
= fragp
->fr_file
;
19042 fixp
->fx_line
= fragp
->fr_line
;
19045 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19046 _("invalid unextended operand value"));
19049 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19050 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19052 gas_assert (mips16_opcode_length (insn
) == length
);
19053 write_compressed_insn (buf
, insn
, length
);
19054 fragp
->fr_fix
+= length
;
19059 relax_substateT subtype
= fragp
->fr_subtype
;
19060 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19061 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19062 unsigned int first
, second
;
19065 first
= RELAX_FIRST (subtype
);
19066 second
= RELAX_SECOND (subtype
);
19067 fixp
= (fixS
*) fragp
->fr_opcode
;
19069 /* If the delay slot chosen does not match the size of the instruction,
19070 then emit a warning. */
19071 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19072 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19077 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19078 | RELAX_DELAY_SLOT_SIZE_FIRST
19079 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19080 msg
= macro_warning (s
);
19082 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19086 /* Possibly emit a warning if we've chosen the longer option. */
19087 if (use_second
== second_longer
)
19093 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19094 msg
= macro_warning (s
);
19096 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19100 /* Go through all the fixups for the first sequence. Disable them
19101 (by marking them as done) if we're going to use the second
19102 sequence instead. */
19104 && fixp
->fx_frag
== fragp
19105 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19107 if (subtype
& RELAX_USE_SECOND
)
19109 fixp
= fixp
->fx_next
;
19112 /* Go through the fixups for the second sequence. Disable them if
19113 we're going to use the first sequence, otherwise adjust their
19114 addresses to account for the relaxation. */
19115 while (fixp
&& fixp
->fx_frag
== fragp
)
19117 if (subtype
& RELAX_USE_SECOND
)
19118 fixp
->fx_where
-= first
;
19121 fixp
= fixp
->fx_next
;
19124 /* Now modify the frag contents. */
19125 if (subtype
& RELAX_USE_SECOND
)
19129 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19130 memmove (start
, start
+ first
, second
);
19131 fragp
->fr_fix
-= first
;
19134 fragp
->fr_fix
-= second
;
19138 /* This function is called after the relocs have been generated.
19139 We've been storing mips16 text labels as odd. Here we convert them
19140 back to even for the convenience of the debugger. */
19143 mips_frob_file_after_relocs (void)
19146 unsigned int count
, i
;
19148 syms
= bfd_get_outsymbols (stdoutput
);
19149 count
= bfd_get_symcount (stdoutput
);
19150 for (i
= 0; i
< count
; i
++, syms
++)
19151 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19152 && ((*syms
)->value
& 1) != 0)
19154 (*syms
)->value
&= ~1;
19155 /* If the symbol has an odd size, it was probably computed
19156 incorrectly, so adjust that as well. */
19157 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19158 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19162 /* This function is called whenever a label is defined, including fake
19163 labels instantiated off the dot special symbol. It is used when
19164 handling branch delays; if a branch has a label, we assume we cannot
19165 move it. This also bumps the value of the symbol by 1 in compressed
19169 mips_record_label (symbolS
*sym
)
19171 segment_info_type
*si
= seg_info (now_seg
);
19172 struct insn_label_list
*l
;
19174 if (free_insn_labels
== NULL
)
19175 l
= XNEW (struct insn_label_list
);
19178 l
= free_insn_labels
;
19179 free_insn_labels
= l
->next
;
19183 l
->next
= si
->label_list
;
19184 si
->label_list
= l
;
19187 /* This function is called as tc_frob_label() whenever a label is defined
19188 and adds a DWARF-2 record we only want for true labels. */
19191 mips_define_label (symbolS
*sym
)
19193 mips_record_label (sym
);
19194 dwarf2_emit_label (sym
);
19197 /* This function is called by tc_new_dot_label whenever a new dot symbol
19201 mips_add_dot_label (symbolS
*sym
)
19203 mips_record_label (sym
);
19204 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19205 mips_compressed_mark_label (sym
);
19208 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19209 static unsigned int
19210 mips_convert_ase_flags (int ase
)
19212 unsigned int ext_ases
= 0;
19215 ext_ases
|= AFL_ASE_DSP
;
19216 if (ase
& ASE_DSPR2
)
19217 ext_ases
|= AFL_ASE_DSPR2
;
19218 if (ase
& ASE_DSPR3
)
19219 ext_ases
|= AFL_ASE_DSPR3
;
19221 ext_ases
|= AFL_ASE_EVA
;
19223 ext_ases
|= AFL_ASE_MCU
;
19224 if (ase
& ASE_MDMX
)
19225 ext_ases
|= AFL_ASE_MDMX
;
19226 if (ase
& ASE_MIPS3D
)
19227 ext_ases
|= AFL_ASE_MIPS3D
;
19229 ext_ases
|= AFL_ASE_MT
;
19230 if (ase
& ASE_SMARTMIPS
)
19231 ext_ases
|= AFL_ASE_SMARTMIPS
;
19232 if (ase
& ASE_VIRT
)
19233 ext_ases
|= AFL_ASE_VIRT
;
19235 ext_ases
|= AFL_ASE_MSA
;
19237 ext_ases
|= AFL_ASE_XPA
;
19238 if (ase
& ASE_MIPS16E2
)
19239 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19241 ext_ases
|= AFL_ASE_CRC
;
19242 if (ase
& ASE_GINV
)
19243 ext_ases
|= AFL_ASE_GINV
;
19244 if (ase
& ASE_LOONGSON_MMI
)
19245 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19246 if (ase
& ASE_LOONGSON_CAM
)
19247 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19248 if (ase
& ASE_LOONGSON_EXT
)
19249 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19250 if (ase
& ASE_LOONGSON_EXT2
)
19251 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19255 /* Some special processing for a MIPS ELF file. */
19258 mips_elf_final_processing (void)
19261 Elf_Internal_ABIFlags_v0 flags
;
19265 switch (file_mips_opts
.isa
)
19268 flags
.isa_level
= 1;
19271 flags
.isa_level
= 2;
19274 flags
.isa_level
= 3;
19277 flags
.isa_level
= 4;
19280 flags
.isa_level
= 5;
19283 flags
.isa_level
= 32;
19287 flags
.isa_level
= 32;
19291 flags
.isa_level
= 32;
19295 flags
.isa_level
= 32;
19299 flags
.isa_level
= 32;
19303 flags
.isa_level
= 64;
19307 flags
.isa_level
= 64;
19311 flags
.isa_level
= 64;
19315 flags
.isa_level
= 64;
19319 flags
.isa_level
= 64;
19324 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19325 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19326 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19327 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19329 flags
.cpr2_size
= AFL_REG_NONE
;
19330 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19331 Tag_GNU_MIPS_ABI_FP
);
19332 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19333 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19334 if (file_ase_mips16
)
19335 flags
.ases
|= AFL_ASE_MIPS16
;
19336 if (file_ase_micromips
)
19337 flags
.ases
|= AFL_ASE_MICROMIPS
;
19339 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19340 || file_mips_opts
.fp
== 64)
19341 && file_mips_opts
.oddspreg
)
19342 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19345 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19346 ((Elf_External_ABIFlags_v0
*)
19349 /* Write out the register information. */
19350 if (mips_abi
!= N64_ABI
)
19354 s
.ri_gprmask
= mips_gprmask
;
19355 s
.ri_cprmask
[0] = mips_cprmask
[0];
19356 s
.ri_cprmask
[1] = mips_cprmask
[1];
19357 s
.ri_cprmask
[2] = mips_cprmask
[2];
19358 s
.ri_cprmask
[3] = mips_cprmask
[3];
19359 /* The gp_value field is set by the MIPS ELF backend. */
19361 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19362 ((Elf32_External_RegInfo
*)
19363 mips_regmask_frag
));
19367 Elf64_Internal_RegInfo s
;
19369 s
.ri_gprmask
= mips_gprmask
;
19371 s
.ri_cprmask
[0] = mips_cprmask
[0];
19372 s
.ri_cprmask
[1] = mips_cprmask
[1];
19373 s
.ri_cprmask
[2] = mips_cprmask
[2];
19374 s
.ri_cprmask
[3] = mips_cprmask
[3];
19375 /* The gp_value field is set by the MIPS ELF backend. */
19377 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19378 ((Elf64_External_RegInfo
*)
19379 mips_regmask_frag
));
19382 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19383 sort of BFD interface for this. */
19384 if (mips_any_noreorder
)
19385 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19386 if (mips_pic
!= NO_PIC
)
19388 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19389 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19392 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19394 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19395 defined at present; this might need to change in future. */
19396 if (file_ase_mips16
)
19397 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19398 if (file_ase_micromips
)
19399 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19400 if (file_mips_opts
.ase
& ASE_MDMX
)
19401 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19403 /* Set the MIPS ELF ABI flags. */
19404 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19405 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19406 else if (mips_abi
== O64_ABI
)
19407 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19408 else if (mips_abi
== EABI_ABI
)
19410 if (file_mips_opts
.gp
== 64)
19411 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19413 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19416 /* Nothing to do for N32_ABI or N64_ABI. */
19418 if (mips_32bitmode
)
19419 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19421 if (mips_nan2008
== 1)
19422 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19424 /* 32 bit code with 64 bit FP registers. */
19425 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19426 Tag_GNU_MIPS_ABI_FP
);
19427 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19428 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19431 typedef struct proc
{
19433 symbolS
*func_end_sym
;
19434 unsigned long reg_mask
;
19435 unsigned long reg_offset
;
19436 unsigned long fpreg_mask
;
19437 unsigned long fpreg_offset
;
19438 unsigned long frame_offset
;
19439 unsigned long frame_reg
;
19440 unsigned long pc_reg
;
19443 static procS cur_proc
;
19444 static procS
*cur_proc_ptr
;
19445 static int numprocs
;
19447 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19448 as "2", and a normal nop as "0". */
19450 #define NOP_OPCODE_MIPS 0
19451 #define NOP_OPCODE_MIPS16 1
19452 #define NOP_OPCODE_MICROMIPS 2
19455 mips_nop_opcode (void)
19457 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19458 return NOP_OPCODE_MICROMIPS
;
19459 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19460 return NOP_OPCODE_MIPS16
;
19462 return NOP_OPCODE_MIPS
;
19465 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19466 32-bit microMIPS NOPs here (if applicable). */
19469 mips_handle_align (fragS
*fragp
)
19473 int bytes
, size
, excess
;
19476 if (fragp
->fr_type
!= rs_align_code
)
19479 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19481 switch (nop_opcode
)
19483 case NOP_OPCODE_MICROMIPS
:
19484 opcode
= micromips_nop32_insn
.insn_opcode
;
19487 case NOP_OPCODE_MIPS16
:
19488 opcode
= mips16_nop_insn
.insn_opcode
;
19491 case NOP_OPCODE_MIPS
:
19493 opcode
= nop_insn
.insn_opcode
;
19498 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19499 excess
= bytes
% size
;
19501 /* Handle the leading part if we're not inserting a whole number of
19502 instructions, and make it the end of the fixed part of the frag.
19503 Try to fit in a short microMIPS NOP if applicable and possible,
19504 and use zeroes otherwise. */
19505 gas_assert (excess
< 4);
19506 fragp
->fr_fix
+= excess
;
19511 /* Fall through. */
19513 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19515 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19519 /* Fall through. */
19522 /* Fall through. */
19527 md_number_to_chars (p
, opcode
, size
);
19528 fragp
->fr_var
= size
;
19537 if (*input_line_pointer
== '-')
19539 ++input_line_pointer
;
19542 if (!ISDIGIT (*input_line_pointer
))
19543 as_bad (_("expected simple number"));
19544 if (input_line_pointer
[0] == '0')
19546 if (input_line_pointer
[1] == 'x')
19548 input_line_pointer
+= 2;
19549 while (ISXDIGIT (*input_line_pointer
))
19552 val
|= hex_value (*input_line_pointer
++);
19554 return negative
? -val
: val
;
19558 ++input_line_pointer
;
19559 while (ISDIGIT (*input_line_pointer
))
19562 val
|= *input_line_pointer
++ - '0';
19564 return negative
? -val
: val
;
19567 if (!ISDIGIT (*input_line_pointer
))
19569 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19570 *input_line_pointer
, *input_line_pointer
);
19571 as_warn (_("invalid number"));
19574 while (ISDIGIT (*input_line_pointer
))
19577 val
+= *input_line_pointer
++ - '0';
19579 return negative
? -val
: val
;
19582 /* The .file directive; just like the usual .file directive, but there
19583 is an initial number which is the ECOFF file index. In the non-ECOFF
19584 case .file implies DWARF-2. */
19587 s_mips_file (int x ATTRIBUTE_UNUSED
)
19589 static int first_file_directive
= 0;
19591 if (ECOFF_DEBUGGING
)
19600 filename
= dwarf2_directive_filename ();
19602 /* Versions of GCC up to 3.1 start files with a ".file"
19603 directive even for stabs output. Make sure that this
19604 ".file" is handled. Note that you need a version of GCC
19605 after 3.1 in order to support DWARF-2 on MIPS. */
19606 if (filename
!= NULL
&& ! first_file_directive
)
19608 (void) new_logical_line (filename
, -1);
19609 s_app_file_string (filename
, 0);
19611 first_file_directive
= 1;
19615 /* The .loc directive, implying DWARF-2. */
19618 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19620 if (!ECOFF_DEBUGGING
)
19621 dwarf2_directive_loc (0);
19624 /* The .end directive. */
19627 s_mips_end (int x ATTRIBUTE_UNUSED
)
19631 /* Following functions need their own .frame and .cprestore directives. */
19632 mips_frame_reg_valid
= 0;
19633 mips_cprestore_valid
= 0;
19635 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19638 demand_empty_rest_of_line ();
19643 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19644 as_warn (_(".end not in text section"));
19648 as_warn (_(".end directive without a preceding .ent directive"));
19649 demand_empty_rest_of_line ();
19655 gas_assert (S_GET_NAME (p
));
19656 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19657 as_warn (_(".end symbol does not match .ent symbol"));
19659 if (debug_type
== DEBUG_STABS
)
19660 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19664 as_warn (_(".end directive missing or unknown symbol"));
19666 /* Create an expression to calculate the size of the function. */
19667 if (p
&& cur_proc_ptr
)
19669 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19670 expressionS
*exp
= XNEW (expressionS
);
19673 exp
->X_op
= O_subtract
;
19674 exp
->X_add_symbol
= symbol_temp_new_now ();
19675 exp
->X_op_symbol
= p
;
19676 exp
->X_add_number
= 0;
19678 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19681 #ifdef md_flush_pending_output
19682 md_flush_pending_output ();
19685 /* Generate a .pdr section. */
19686 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19688 segT saved_seg
= now_seg
;
19689 subsegT saved_subseg
= now_subseg
;
19693 gas_assert (pdr_seg
);
19694 subseg_set (pdr_seg
, 0);
19696 /* Write the symbol. */
19697 exp
.X_op
= O_symbol
;
19698 exp
.X_add_symbol
= p
;
19699 exp
.X_add_number
= 0;
19700 emit_expr (&exp
, 4);
19702 fragp
= frag_more (7 * 4);
19704 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19705 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19706 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19707 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19708 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19709 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19710 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19712 subseg_set (saved_seg
, saved_subseg
);
19715 cur_proc_ptr
= NULL
;
19718 /* The .aent and .ent directives. */
19721 s_mips_ent (int aent
)
19725 symbolP
= get_symbol ();
19726 if (*input_line_pointer
== ',')
19727 ++input_line_pointer
;
19728 SKIP_WHITESPACE ();
19729 if (ISDIGIT (*input_line_pointer
)
19730 || *input_line_pointer
== '-')
19733 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19734 as_warn (_(".ent or .aent not in text section"));
19736 if (!aent
&& cur_proc_ptr
)
19737 as_warn (_("missing .end"));
19741 /* This function needs its own .frame and .cprestore directives. */
19742 mips_frame_reg_valid
= 0;
19743 mips_cprestore_valid
= 0;
19745 cur_proc_ptr
= &cur_proc
;
19746 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19748 cur_proc_ptr
->func_sym
= symbolP
;
19752 if (debug_type
== DEBUG_STABS
)
19753 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19754 S_GET_NAME (symbolP
));
19757 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19759 demand_empty_rest_of_line ();
19762 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19763 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19764 s_mips_frame is used so that we can set the PDR information correctly.
19765 We can't use the ecoff routines because they make reference to the ecoff
19766 symbol table (in the mdebug section). */
19769 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19771 if (ECOFF_DEBUGGING
)
19777 if (cur_proc_ptr
== (procS
*) NULL
)
19779 as_warn (_(".frame outside of .ent"));
19780 demand_empty_rest_of_line ();
19784 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19786 SKIP_WHITESPACE ();
19787 if (*input_line_pointer
++ != ','
19788 || get_absolute_expression_and_terminator (&val
) != ',')
19790 as_warn (_("bad .frame directive"));
19791 --input_line_pointer
;
19792 demand_empty_rest_of_line ();
19796 cur_proc_ptr
->frame_offset
= val
;
19797 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19799 demand_empty_rest_of_line ();
19803 /* The .fmask and .mask directives. If the mdebug section is present
19804 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19805 embedded targets, s_mips_mask is used so that we can set the PDR
19806 information correctly. We can't use the ecoff routines because they
19807 make reference to the ecoff symbol table (in the mdebug section). */
19810 s_mips_mask (int reg_type
)
19812 if (ECOFF_DEBUGGING
)
19813 s_ignore (reg_type
);
19818 if (cur_proc_ptr
== (procS
*) NULL
)
19820 as_warn (_(".mask/.fmask outside of .ent"));
19821 demand_empty_rest_of_line ();
19825 if (get_absolute_expression_and_terminator (&mask
) != ',')
19827 as_warn (_("bad .mask/.fmask directive"));
19828 --input_line_pointer
;
19829 demand_empty_rest_of_line ();
19833 off
= get_absolute_expression ();
19835 if (reg_type
== 'F')
19837 cur_proc_ptr
->fpreg_mask
= mask
;
19838 cur_proc_ptr
->fpreg_offset
= off
;
19842 cur_proc_ptr
->reg_mask
= mask
;
19843 cur_proc_ptr
->reg_offset
= off
;
19846 demand_empty_rest_of_line ();
19850 /* A table describing all the processors gas knows about. Names are
19851 matched in the order listed.
19853 To ease comparison, please keep this table in the same order as
19854 gcc's mips_cpu_info_table[]. */
19855 static const struct mips_cpu_info mips_cpu_info_table
[] =
19857 /* Entries for generic ISAs. */
19858 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19859 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19860 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19861 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19862 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19863 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19864 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19865 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19866 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19867 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19868 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19869 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19870 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19871 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19872 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19875 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19876 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19877 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19880 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19883 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19884 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19885 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19886 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19887 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19888 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19889 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19890 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19891 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19892 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19893 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19894 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19895 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19896 /* ST Microelectronics Loongson 2E and 2F cores. */
19897 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19898 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
19901 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19902 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19903 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19904 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19905 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19906 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19907 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19908 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19909 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19910 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19911 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19912 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19913 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19914 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19915 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19918 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19919 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19920 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19921 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19923 /* MIPS 32 Release 2 */
19924 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19925 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19926 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19927 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19928 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19929 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19930 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19931 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19932 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19933 ISA_MIPS32R2
, CPU_MIPS32R2
},
19934 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19935 ISA_MIPS32R2
, CPU_MIPS32R2
},
19936 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19937 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19938 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19939 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19940 /* Deprecated forms of the above. */
19941 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19942 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19943 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19944 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19945 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19946 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19947 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19948 /* Deprecated forms of the above. */
19949 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19950 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19951 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19952 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19953 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19954 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19955 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19956 /* Deprecated forms of the above. */
19957 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19958 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19959 /* 34Kn is a 34kc without DSP. */
19960 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19961 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19962 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19963 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19964 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19965 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19966 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19967 /* Deprecated forms of the above. */
19968 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19969 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19970 /* 1004K cores are multiprocessor versions of the 34K. */
19971 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19972 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19973 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19974 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19975 /* interaptiv is the new name for 1004kf. */
19976 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19977 { "interaptiv-mr2", 0,
19978 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19979 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19980 /* M5100 family. */
19981 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19982 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19983 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19984 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19987 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19988 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19989 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19990 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19992 /* Broadcom SB-1 CPU core. */
19993 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19994 /* Broadcom SB-1A CPU core. */
19995 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19997 /* MIPS 64 Release 2. */
19998 /* Loongson CPU core. */
19999 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20000 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20001 ISA_MIPS64R2
, CPU_GS464
},
20002 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20003 ISA_MIPS64R2
, CPU_GS464
},
20004 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20005 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20006 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20007 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20009 /* Cavium Networks Octeon CPU core. */
20010 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20011 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20012 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20013 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20016 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20019 XLP is mostly like XLR, with the prominent exception that it is
20020 MIPS64R2 rather than MIPS64. */
20021 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20023 /* MIPS 64 Release 6. */
20024 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20025 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20026 ISA_MIPS64R6
, CPU_MIPS64R6
},
20027 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20030 { NULL
, 0, 0, 0, 0 }
20034 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20035 with a final "000" replaced by "k". Ignore case.
20037 Note: this function is shared between GCC and GAS. */
20040 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20042 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20043 given
++, canonical
++;
20045 return ((*given
== 0 && *canonical
== 0)
20046 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20050 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20051 CPU name. We've traditionally allowed a lot of variation here.
20053 Note: this function is shared between GCC and GAS. */
20056 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20058 /* First see if the name matches exactly, or with a final "000"
20059 turned into "k". */
20060 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20063 /* If not, try comparing based on numerical designation alone.
20064 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20065 if (TOLOWER (*given
) == 'r')
20067 if (!ISDIGIT (*given
))
20070 /* Skip over some well-known prefixes in the canonical name,
20071 hoping to find a number there too. */
20072 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20074 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20076 else if (TOLOWER (canonical
[0]) == 'r')
20079 return mips_strict_matching_cpu_name_p (canonical
, given
);
20083 /* Parse an option that takes the name of a processor as its argument.
20084 OPTION is the name of the option and CPU_STRING is the argument.
20085 Return the corresponding processor enumeration if the CPU_STRING is
20086 recognized, otherwise report an error and return null.
20088 A similar function exists in GCC. */
20090 static const struct mips_cpu_info
*
20091 mips_parse_cpu (const char *option
, const char *cpu_string
)
20093 const struct mips_cpu_info
*p
;
20095 /* 'from-abi' selects the most compatible architecture for the given
20096 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20097 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20098 version. Look first at the -mgp options, if given, otherwise base
20099 the choice on MIPS_DEFAULT_64BIT.
20101 Treat NO_ABI like the EABIs. One reason to do this is that the
20102 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20103 architecture. This code picks MIPS I for 'mips' and MIPS III for
20104 'mips64', just as we did in the days before 'from-abi'. */
20105 if (strcasecmp (cpu_string
, "from-abi") == 0)
20107 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20108 return mips_cpu_info_from_isa (ISA_MIPS1
);
20110 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20111 return mips_cpu_info_from_isa (ISA_MIPS3
);
20113 if (file_mips_opts
.gp
>= 0)
20114 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20115 ? ISA_MIPS1
: ISA_MIPS3
);
20117 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20122 /* 'default' has traditionally been a no-op. Probably not very useful. */
20123 if (strcasecmp (cpu_string
, "default") == 0)
20126 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20127 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20130 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20134 /* Return the canonical processor information for ISA (a member of the
20135 ISA_MIPS* enumeration). */
20137 static const struct mips_cpu_info
*
20138 mips_cpu_info_from_isa (int isa
)
20142 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20143 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20144 && isa
== mips_cpu_info_table
[i
].isa
)
20145 return (&mips_cpu_info_table
[i
]);
20150 static const struct mips_cpu_info
*
20151 mips_cpu_info_from_arch (int arch
)
20155 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20156 if (arch
== mips_cpu_info_table
[i
].cpu
)
20157 return (&mips_cpu_info_table
[i
]);
20163 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20167 fprintf (stream
, "%24s", "");
20172 fprintf (stream
, ", ");
20176 if (*col_p
+ strlen (string
) > 72)
20178 fprintf (stream
, "\n%24s", "");
20182 fprintf (stream
, "%s", string
);
20183 *col_p
+= strlen (string
);
20189 md_show_usage (FILE *stream
)
20194 fprintf (stream
, _("\
20196 -EB generate big endian output\n\
20197 -EL generate little endian output\n\
20198 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20199 -G NUM allow referencing objects up to NUM bytes\n\
20200 implicitly with the gp register [default 8]\n"));
20201 fprintf (stream
, _("\
20202 -mips1 generate MIPS ISA I instructions\n\
20203 -mips2 generate MIPS ISA II instructions\n\
20204 -mips3 generate MIPS ISA III instructions\n\
20205 -mips4 generate MIPS ISA IV instructions\n\
20206 -mips5 generate MIPS ISA V instructions\n\
20207 -mips32 generate MIPS32 ISA instructions\n\
20208 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20209 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20210 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20211 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20212 -mips64 generate MIPS64 ISA instructions\n\
20213 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20214 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20215 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20216 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20217 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20221 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20222 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20223 show (stream
, "from-abi", &column
, &first
);
20224 fputc ('\n', stream
);
20226 fprintf (stream
, _("\
20227 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20228 -no-mCPU don't generate code specific to CPU.\n\
20229 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20233 show (stream
, "3900", &column
, &first
);
20234 show (stream
, "4010", &column
, &first
);
20235 show (stream
, "4100", &column
, &first
);
20236 show (stream
, "4650", &column
, &first
);
20237 fputc ('\n', stream
);
20239 fprintf (stream
, _("\
20240 -mips16 generate mips16 instructions\n\
20241 -no-mips16 do not generate mips16 instructions\n"));
20242 fprintf (stream
, _("\
20243 -mmips16e2 generate MIPS16e2 instructions\n\
20244 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20245 fprintf (stream
, _("\
20246 -mmicromips generate microMIPS instructions\n\
20247 -mno-micromips do not generate microMIPS instructions\n"));
20248 fprintf (stream
, _("\
20249 -msmartmips generate smartmips instructions\n\
20250 -mno-smartmips do not generate smartmips instructions\n"));
20251 fprintf (stream
, _("\
20252 -mdsp generate DSP instructions\n\
20253 -mno-dsp do not generate DSP instructions\n"));
20254 fprintf (stream
, _("\
20255 -mdspr2 generate DSP R2 instructions\n\
20256 -mno-dspr2 do not generate DSP R2 instructions\n"));
20257 fprintf (stream
, _("\
20258 -mdspr3 generate DSP R3 instructions\n\
20259 -mno-dspr3 do not generate DSP R3 instructions\n"));
20260 fprintf (stream
, _("\
20261 -mmt generate MT instructions\n\
20262 -mno-mt do not generate MT instructions\n"));
20263 fprintf (stream
, _("\
20264 -mmcu generate MCU instructions\n\
20265 -mno-mcu do not generate MCU instructions\n"));
20266 fprintf (stream
, _("\
20267 -mmsa generate MSA instructions\n\
20268 -mno-msa do not generate MSA instructions\n"));
20269 fprintf (stream
, _("\
20270 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20271 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20272 fprintf (stream
, _("\
20273 -mvirt generate Virtualization instructions\n\
20274 -mno-virt do not generate Virtualization instructions\n"));
20275 fprintf (stream
, _("\
20276 -mcrc generate CRC instructions\n\
20277 -mno-crc do not generate CRC instructions\n"));
20278 fprintf (stream
, _("\
20279 -mginv generate Global INValidate (GINV) instructions\n\
20280 -mno-ginv do not generate Global INValidate instructions\n"));
20281 fprintf (stream
, _("\
20282 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20283 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20284 fprintf (stream
, _("\
20285 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20286 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20287 fprintf (stream
, _("\
20288 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20289 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20290 fprintf (stream
, _("\
20291 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20292 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20293 fprintf (stream
, _("\
20294 -minsn32 only generate 32-bit microMIPS instructions\n\
20295 -mno-insn32 generate all microMIPS instructions\n"));
20296 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20297 fprintf (stream
, _("\
20298 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20299 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20301 fprintf (stream
, _("\
20302 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20303 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20305 fprintf (stream
, _("\
20306 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20307 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20308 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20309 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20310 -mfix-vr4120 work around certain VR4120 errata\n\
20311 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20312 -mfix-24k insert a nop after ERET and DERET instructions\n\
20313 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20314 -mfix-r5900 work around R5900 short loop errata\n\
20315 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20316 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20317 -msym32 assume all symbols have 32-bit values\n\
20318 -O0 do not remove unneeded NOPs, do not swap branches\n\
20319 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20320 -O2 remove unneeded NOPs and swap branches\n\
20321 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20322 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20323 fprintf (stream
, _("\
20324 -mhard-float allow floating-point instructions\n\
20325 -msoft-float do not allow floating-point instructions\n\
20326 -msingle-float only allow 32-bit floating-point operations\n\
20327 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20328 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20329 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20330 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20331 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20332 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20336 show (stream
, "legacy", &column
, &first
);
20337 show (stream
, "2008", &column
, &first
);
20339 fputc ('\n', stream
);
20341 fprintf (stream
, _("\
20342 -KPIC, -call_shared generate SVR4 position independent code\n\
20343 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20344 -mvxworks-pic generate VxWorks position independent code\n\
20345 -non_shared do not generate code that can operate with DSOs\n\
20346 -xgot assume a 32 bit GOT\n\
20347 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20348 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20349 position dependent (non shared) code\n\
20350 -mabi=ABI create ABI conformant object file for:\n"));
20354 show (stream
, "32", &column
, &first
);
20355 show (stream
, "o64", &column
, &first
);
20356 show (stream
, "n32", &column
, &first
);
20357 show (stream
, "64", &column
, &first
);
20358 show (stream
, "eabi", &column
, &first
);
20360 fputc ('\n', stream
);
20362 fprintf (stream
, _("\
20363 -32 create o32 ABI object file%s\n"),
20364 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20365 fprintf (stream
, _("\
20366 -n32 create n32 ABI object file%s\n"),
20367 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20368 fprintf (stream
, _("\
20369 -64 create 64 ABI object file%s\n"),
20370 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20375 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20377 if (HAVE_64BIT_SYMBOLS
)
20378 return dwarf2_format_64bit_irix
;
20380 return dwarf2_format_32bit
;
20385 mips_dwarf2_addr_size (void)
20387 if (HAVE_64BIT_OBJECTS
)
20393 /* Standard calling conventions leave the CFA at SP on entry. */
20395 mips_cfi_frame_initial_instructions (void)
20397 cfi_add_CFA_def_cfa_register (SP
);
20401 tc_mips_regname_to_dw2regnum (char *regname
)
20403 unsigned int regnum
= -1;
20406 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20412 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20413 Given a symbolic attribute NAME, return the proper integer value.
20414 Returns -1 if the attribute is not known. */
20417 mips_convert_symbolic_attribute (const char *name
)
20419 static const struct
20424 attribute_table
[] =
20426 #define T(tag) {#tag, tag}
20427 T (Tag_GNU_MIPS_ABI_FP
),
20428 T (Tag_GNU_MIPS_ABI_MSA
),
20436 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20437 if (streq (name
, attribute_table
[i
].name
))
20438 return attribute_table
[i
].tag
;
20446 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20448 mips_emit_delays ();
20450 as_warn (_("missing .end at end of assembly"));
20452 /* Just in case no code was emitted, do the consistency check. */
20453 file_mips_check_options ();
20455 /* Set a floating-point ABI if the user did not. */
20456 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20458 /* Perform consistency checks on the floating-point ABI. */
20459 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20460 Tag_GNU_MIPS_ABI_FP
);
20461 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20462 check_fpabi (fpabi
);
20466 /* Soft-float gets precedence over single-float, the two options should
20467 not be used together so this should not matter. */
20468 if (file_mips_opts
.soft_float
== 1)
20469 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20470 /* Single-float gets precedence over all double_float cases. */
20471 else if (file_mips_opts
.single_float
== 1)
20472 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20475 switch (file_mips_opts
.fp
)
20478 if (file_mips_opts
.gp
== 32)
20479 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20482 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20485 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20486 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20487 else if (file_mips_opts
.gp
== 32)
20488 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20490 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20495 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20496 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20500 /* Returns the relocation type required for a particular CFI encoding. */
20502 bfd_reloc_code_real_type
20503 mips_cfi_reloc_for_encoding (int encoding
)
20505 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20506 return BFD_RELOC_32_PCREL
;
20507 else return BFD_RELOC_NONE
;