1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* Whether the 4650 instructions (mad/madu) are permitted. */
198 static int mips_4650
= -1;
200 /* Whether the 4010 instructions are permitted. */
201 static int mips_4010
= -1;
203 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
204 static int mips_4100
= -1;
206 /* start-sanitize-vr4320 */
207 /* Whether NEC vr4320 instructions are permitted. */
208 static int mips_4320
= -1;
210 /* end-sanitize-vr4320 */
211 /* start-sanitize-vr5400 */
212 /* Whether NEC vr5400 instructions are permitted. */
213 static int mips_5400
= -1;
215 /* end-sanitize-vr5400 */
216 /* start-sanitize-r5900 */
217 /* Whether Toshiba r5900 instructions are permitted. */
218 static int mips_5900
= -1;
220 /* end-sanitize-r5900 */
221 /* Whether Toshiba r3900 instructions are permitted. */
222 static int mips_3900
= -1;
224 /* start-sanitize-tx49 */
225 /* Whether Toshiba r4900 instructions are permitted. */
226 static int mips_4900
= -1;
228 /* end-sanitize-tx49 */
229 /* start-sanitize-tx19 */
230 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
231 The tx19 related options and configuration bits are handled by
233 /* end-sanitize-tx19 */
235 /* Whether the processor uses hardware interlocks to protect
236 reads from the HI and LO registers, and thus does not
237 require nops to be inserted. */
238 #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \
239 /* start-sanitize-tx49 */ \
240 || mips_cpu == 4900 || mips_4900 \
241 /* end-sanitize-tx49 */ \
242 /* start-sanitize-vr4320 */ \
243 || mips_cpu == 4320 \
244 /* end-sanitize-vr4320 */ \
245 /* start-sanitize-vr5400 */ \
246 || mips_cpu == 5400 \
247 /* end-sanitize-vr5400 */ \
250 /* Whether the processor uses hardware interlocks to protect reads
251 from the GPRs, and thus does not require nops to be inserted. */
252 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
253 /* start-sanitize-vr5400 */
254 #undef gpr_interlocks
255 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400)
256 /* end-sanitize-vr5400 */
259 /* As with other "interlocks" this is used by hardware that has FP
260 (co-processor) interlocks. */
261 /* Itbl support may require additional care here. */
262 #define cop_interlocks (mips_cpu == 4300 \
263 /* start-sanitize-vr4320 */ \
264 || mips_cpu == 4320 \
265 /* end-sanitize-vr4320 */ \
266 /* start-sanitize-vr5400 */ \
267 || mips_cpu == 5400 \
268 /* end-sanitize-vr5400 */ \
271 /* MIPS PIC level. */
275 /* Do not generate PIC code. */
278 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
279 not sure what it is supposed to do. */
282 /* Generate PIC code as in the SVR4 MIPS ABI. */
285 /* Generate PIC code without using a global offset table: the data
286 segment has a maximum size of 64K, all data references are off
287 the $gp register, and all text references are PC relative. This
288 is used on some embedded systems. */
292 static enum mips_pic_level mips_pic
;
294 /* 1 if we should generate 32 bit offsets from the GP register in
295 SVR4_PIC mode. Currently has no meaning in other modes. */
296 static int mips_big_got
;
298 /* 1 if trap instructions should used for overflow rather than break
300 static int mips_trap
;
302 /* Non-zero if any .set noreorder directives were used. */
304 static int mips_any_noreorder
;
306 /* The size of the small data section. */
307 static int g_switch_value
= 8;
308 /* Whether the -G option was used. */
309 static int g_switch_seen
= 0;
314 /* If we can determine in advance that GP optimization won't be
315 possible, we can skip the relaxation stuff that tries to produce
316 GP-relative references. This makes delay slot optimization work
319 This function can only provide a guess, but it seems to work for
320 gcc output. If it guesses wrong, the only loss should be in
321 efficiency; it shouldn't introduce any bugs.
323 I don't know if a fix is needed for the SVR4_PIC mode. I've only
324 fixed it for the non-PIC mode. KR 95/04/07 */
325 static int nopic_need_relax
PARAMS ((symbolS
*, int));
327 /* handle of the OPCODE hash table */
328 static struct hash_control
*op_hash
= NULL
;
330 /* The opcode hash table we use for the mips16. */
331 static struct hash_control
*mips16_op_hash
= NULL
;
333 /* This array holds the chars that always start a comment. If the
334 pre-processor is disabled, these aren't very useful */
335 const char comment_chars
[] = "#";
337 /* This array holds the chars that only start a comment at the beginning of
338 a line. If the line seems to have the form '# 123 filename'
339 .line and .file directives will appear in the pre-processed output */
340 /* Note that input_file.c hand checks for '#' at the beginning of the
341 first line of the input file. This is because the compiler outputs
342 #NO_APP at the beginning of its output. */
343 /* Also note that C style comments are always supported. */
344 const char line_comment_chars
[] = "#";
346 /* This array holds machine specific line separator characters. */
347 const char line_separator_chars
[] = "";
349 /* Chars that can be used to separate mant from exp in floating point nums */
350 const char EXP_CHARS
[] = "eE";
352 /* Chars that mean this number is a floating point constant */
355 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
357 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
358 changed in read.c . Ideally it shouldn't have to know about it at all,
359 but nothing is ideal around here.
362 static char *insn_error
;
364 static int auto_align
= 1;
366 /* When outputting SVR4 PIC code, the assembler needs to know the
367 offset in the stack frame from which to restore the $gp register.
368 This is set by the .cprestore pseudo-op, and saved in this
370 static offsetT mips_cprestore_offset
= -1;
372 /* This is the register which holds the stack frame, as set by the
373 .frame pseudo-op. This is needed to implement .cprestore. */
374 static int mips_frame_reg
= SP
;
376 /* To output NOP instructions correctly, we need to keep information
377 about the previous two instructions. */
379 /* Whether we are optimizing. The default value of 2 means to remove
380 unneeded NOPs and swap branch instructions when possible. A value
381 of 1 means to not swap branches. A value of 0 means to always
383 static int mips_optimize
= 2;
385 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
386 equivalent to seeing no -g option at all. */
387 static int mips_debug
= 0;
389 /* The previous instruction. */
390 static struct mips_cl_insn prev_insn
;
392 /* The instruction before prev_insn. */
393 static struct mips_cl_insn prev_prev_insn
;
395 /* If we don't want information for prev_insn or prev_prev_insn, we
396 point the insn_mo field at this dummy integer. */
397 static const struct mips_opcode dummy_opcode
= { 0 };
399 /* Non-zero if prev_insn is valid. */
400 static int prev_insn_valid
;
402 /* The frag for the previous instruction. */
403 static struct frag
*prev_insn_frag
;
405 /* The offset into prev_insn_frag for the previous instruction. */
406 static long prev_insn_where
;
408 /* The reloc type for the previous instruction, if any. */
409 static bfd_reloc_code_real_type prev_insn_reloc_type
;
411 /* The reloc for the previous instruction, if any. */
412 static fixS
*prev_insn_fixp
;
414 /* Non-zero if the previous instruction was in a delay slot. */
415 static int prev_insn_is_delay_slot
;
417 /* Non-zero if the previous instruction was in a .set noreorder. */
418 static int prev_insn_unreordered
;
420 /* Non-zero if the previous instruction uses an extend opcode (if
422 static int prev_insn_extended
;
424 /* Non-zero if the previous previous instruction was in a .set
426 static int prev_prev_insn_unreordered
;
428 /* If this is set, it points to a frag holding nop instructions which
429 were inserted before the start of a noreorder section. If those
430 nops turn out to be unnecessary, the size of the frag can be
432 static fragS
*prev_nop_frag
;
434 /* The number of nop instructions we created in prev_nop_frag. */
435 static int prev_nop_frag_holds
;
437 /* The number of nop instructions that we know we need in
439 static int prev_nop_frag_required
;
441 /* The number of instructions we've seen since prev_nop_frag. */
442 static int prev_nop_frag_since
;
444 /* For ECOFF and ELF, relocations against symbols are done in two
445 parts, with a HI relocation and a LO relocation. Each relocation
446 has only 16 bits of space to store an addend. This means that in
447 order for the linker to handle carries correctly, it must be able
448 to locate both the HI and the LO relocation. This means that the
449 relocations must appear in order in the relocation table.
451 In order to implement this, we keep track of each unmatched HI
452 relocation. We then sort them so that they immediately precede the
453 corresponding LO relocation. */
458 struct mips_hi_fixup
*next
;
461 /* The section this fixup is in. */
465 /* The list of unmatched HI relocs. */
467 static struct mips_hi_fixup
*mips_hi_fixup_list
;
469 /* Map normal MIPS register numbers to mips16 register numbers. */
471 #define X ILLEGAL_REG
472 static const int mips32_to_16_reg_map
[] =
474 X
, X
, 2, 3, 4, 5, 6, 7,
475 X
, X
, X
, X
, X
, X
, X
, X
,
476 0, 1, X
, X
, X
, X
, X
, X
,
477 X
, X
, X
, X
, X
, X
, X
, X
481 /* Map mips16 register numbers to normal MIPS register numbers. */
483 static const int mips16_to_32_reg_map
[] =
485 16, 17, 2, 3, 4, 5, 6, 7
488 /* Since the MIPS does not have multiple forms of PC relative
489 instructions, we do not have to do relaxing as is done on other
490 platforms. However, we do have to handle GP relative addressing
491 correctly, which turns out to be a similar problem.
493 Every macro that refers to a symbol can occur in (at least) two
494 forms, one with GP relative addressing and one without. For
495 example, loading a global variable into a register generally uses
496 a macro instruction like this:
498 If i can be addressed off the GP register (this is true if it is in
499 the .sbss or .sdata section, or if it is known to be smaller than
500 the -G argument) this will generate the following instruction:
502 This instruction will use a GPREL reloc. If i can not be addressed
503 off the GP register, the following instruction sequence will be used:
506 In this case the first instruction will have a HI16 reloc, and the
507 second reloc will have a LO16 reloc. Both relocs will be against
510 The issue here is that we may not know whether i is GP addressable
511 until after we see the instruction that uses it. Therefore, we
512 want to be able to choose the final instruction sequence only at
513 the end of the assembly. This is similar to the way other
514 platforms choose the size of a PC relative instruction only at the
517 When generating position independent code we do not use GP
518 addressing in quite the same way, but the issue still arises as
519 external symbols and local symbols must be handled differently.
521 We handle these issues by actually generating both possible
522 instruction sequences. The longer one is put in a frag_var with
523 type rs_machine_dependent. We encode what to do with the frag in
524 the subtype field. We encode (1) the number of existing bytes to
525 replace, (2) the number of new bytes to use, (3) the offset from
526 the start of the existing bytes to the first reloc we must generate
527 (that is, the offset is applied from the start of the existing
528 bytes after they are replaced by the new bytes, if any), (4) the
529 offset from the start of the existing bytes to the second reloc,
530 (5) whether a third reloc is needed (the third reloc is always four
531 bytes after the second reloc), and (6) whether to warn if this
532 variant is used (this is sometimes needed if .set nomacro or .set
533 noat is in effect). All these numbers are reasonably small.
535 Generating two instruction sequences must be handled carefully to
536 ensure that delay slots are handled correctly. Fortunately, there
537 are a limited number of cases. When the second instruction
538 sequence is generated, append_insn is directed to maintain the
539 existing delay slot information, so it continues to apply to any
540 code after the second instruction sequence. This means that the
541 second instruction sequence must not impose any requirements not
542 required by the first instruction sequence.
544 These variant frags are then handled in functions called by the
545 machine independent code. md_estimate_size_before_relax returns
546 the final size of the frag. md_convert_frag sets up the final form
547 of the frag. tc_gen_reloc adjust the first reloc and adds a second
549 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
553 | (((reloc1) + 64) << 9) \
554 | (((reloc2) + 64) << 2) \
555 | ((reloc3) ? (1 << 1) : 0) \
557 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
558 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
559 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
560 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
561 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
562 #define RELAX_WARN(i) ((i) & 1)
564 /* For mips16 code, we use an entirely different form of relaxation.
565 mips16 supports two versions of most instructions which take
566 immediate values: a small one which takes some small value, and a
567 larger one which takes a 16 bit value. Since branches also follow
568 this pattern, relaxing these values is required.
570 We can assemble both mips16 and normal MIPS code in a single
571 object. Therefore, we need to support this type of relaxation at
572 the same time that we support the relaxation described above. We
573 use the high bit of the subtype field to distinguish these cases.
575 The information we store for this type of relaxation is the
576 argument code found in the opcode file for this relocation, whether
577 the user explicitly requested a small or extended form, and whether
578 the relocation is in a jump or jal delay slot. That tells us the
579 size of the value, and how it should be stored. We also store
580 whether the fragment is considered to be extended or not. We also
581 store whether this is known to be a branch to a different section,
582 whether we have tried to relax this frag yet, and whether we have
583 ever extended a PC relative fragment because of a shift count. */
584 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
587 | ((small) ? 0x100 : 0) \
588 | ((ext) ? 0x200 : 0) \
589 | ((dslot) ? 0x400 : 0) \
590 | ((jal_dslot) ? 0x800 : 0))
591 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
592 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
593 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
594 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
595 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
596 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
597 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
598 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
599 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
600 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
601 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
602 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
604 /* Prototypes for static functions. */
607 #define internalError() \
608 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
610 #define internalError() as_fatal ("MIPS internal Error");
613 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
615 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
616 unsigned int reg
, enum mips_regclass
class));
617 static int reg_needs_delay
PARAMS ((int));
618 static void mips16_mark_labels
PARAMS ((void));
619 static void append_insn
PARAMS ((char *place
,
620 struct mips_cl_insn
* ip
,
622 bfd_reloc_code_real_type r
,
624 static void mips_no_prev_insn
PARAMS ((int));
625 static void mips_emit_delays
PARAMS ((boolean
));
627 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
628 const char *name
, const char *fmt
,
631 static void macro_build ();
633 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
634 const char *, const char *,
636 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
637 expressionS
* ep
, int regnum
));
638 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
639 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
641 static void load_register
PARAMS ((int *, int, expressionS
*, int));
642 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
643 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
644 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
645 #ifdef LOSING_COMPILER
646 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
648 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
649 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
650 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
651 boolean
, boolean
, unsigned long *,
652 boolean
*, unsigned short *));
653 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
654 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
655 static symbolS
*get_symbol
PARAMS ((void));
656 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
657 static void s_align
PARAMS ((int));
658 static void s_change_sec
PARAMS ((int));
659 static void s_cons
PARAMS ((int));
660 static void s_float_cons
PARAMS ((int));
661 static void s_mips_globl
PARAMS ((int));
662 static void s_option
PARAMS ((int));
663 static void s_mipsset
PARAMS ((int));
664 static void s_abicalls
PARAMS ((int));
665 static void s_cpload
PARAMS ((int));
666 static void s_cprestore
PARAMS ((int));
667 static void s_gpword
PARAMS ((int));
668 static void s_cpadd
PARAMS ((int));
669 static void s_insn
PARAMS ((int));
670 static void md_obj_begin
PARAMS ((void));
671 static void md_obj_end
PARAMS ((void));
672 static long get_number
PARAMS ((void));
673 static void s_ent
PARAMS ((int));
674 static void s_mipsend
PARAMS ((int));
675 static void s_file
PARAMS ((int));
676 static void s_mips_stab
PARAMS ((int));
677 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
679 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
683 The following pseudo-ops from the Kane and Heinrich MIPS book
684 should be defined here, but are currently unsupported: .alias,
685 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
687 The following pseudo-ops from the Kane and Heinrich MIPS book are
688 specific to the type of debugging information being generated, and
689 should be defined by the object format: .aent, .begin, .bend,
690 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
693 The following pseudo-ops from the Kane and Heinrich MIPS book are
694 not MIPS CPU specific, but are also not specific to the object file
695 format. This file is probably the best place to define them, but
696 they are not currently supported: .asm0, .endr, .lab, .repeat,
697 .struct, .weakext. */
699 static const pseudo_typeS mips_pseudo_table
[] =
701 /* MIPS specific pseudo-ops. */
702 {"option", s_option
, 0},
703 {"set", s_mipsset
, 0},
704 {"rdata", s_change_sec
, 'r'},
705 {"sdata", s_change_sec
, 's'},
706 {"livereg", s_ignore
, 0},
707 {"abicalls", s_abicalls
, 0},
708 {"cpload", s_cpload
, 0},
709 {"cprestore", s_cprestore
, 0},
710 {"gpword", s_gpword
, 0},
711 {"cpadd", s_cpadd
, 0},
714 /* Relatively generic pseudo-ops that happen to be used on MIPS
716 {"asciiz", stringer
, 1},
717 {"bss", s_change_sec
, 'b'},
720 {"dword", s_cons
, 3},
722 /* These pseudo-ops are defined in read.c, but must be overridden
723 here for one reason or another. */
724 {"align", s_align
, 0},
726 {"data", s_change_sec
, 'd'},
727 {"double", s_float_cons
, 'd'},
728 {"float", s_float_cons
, 'f'},
729 {"globl", s_mips_globl
, 0},
730 {"global", s_mips_globl
, 0},
731 {"hword", s_cons
, 1},
736 {"short", s_cons
, 1},
737 {"single", s_float_cons
, 'f'},
738 {"stabn", s_mips_stab
, 'n'},
739 {"text", s_change_sec
, 't'},
744 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
745 /* These pseudo-ops should be defined by the object file format.
746 However, a.out doesn't support them, so we have versions here. */
748 {"bgnb", s_ignore
, 0},
749 {"end", s_mipsend
, 0},
750 {"endb", s_ignore
, 0},
753 {"fmask", s_ignore
, 'F'},
754 {"frame", s_ignore
, 0},
755 {"loc", s_ignore
, 0},
756 {"mask", s_ignore
, 'R'},
757 {"verstamp", s_ignore
, 0},
761 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
766 pop_insert (mips_pseudo_table
);
767 if (! ECOFF_DEBUGGING
)
768 pop_insert (mips_nonecoff_pseudo_table
);
771 /* Symbols labelling the current insn. */
773 struct insn_label_list
775 struct insn_label_list
*next
;
779 static struct insn_label_list
*insn_labels
;
780 static struct insn_label_list
*free_insn_labels
;
782 static void mips_clear_insn_labels
PARAMS ((void));
785 mips_clear_insn_labels ()
787 register struct insn_label_list
**pl
;
789 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
795 static char *expr_end
;
797 /* Expressions which appear in instructions. These are set by
800 static expressionS imm_expr
;
801 static expressionS offset_expr
;
803 /* Relocs associated with imm_expr and offset_expr. */
805 static bfd_reloc_code_real_type imm_reloc
;
806 static bfd_reloc_code_real_type offset_reloc
;
808 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
810 static boolean imm_unmatched_hi
;
812 /* These are set by mips16_ip if an explicit extension is used. */
814 static boolean mips16_small
, mips16_ext
;
817 * This function is called once, at assembler startup time. It should
818 * set up all the tables, etc. that the MD part of the assembler will need.
824 register const char *retval
= NULL
;
825 register unsigned int i
= 0;
831 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
833 a
= xmalloc (sizeof TARGET_CPU
);
834 strcpy (a
, TARGET_CPU
);
835 a
[(sizeof TARGET_CPU
) - 3] = '\0';
841 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
842 just the generic 'mips', in which case set mips_cpu based
843 on the given ISA, if any. */
845 if (strcmp (cpu
, "mips") == 0)
847 if (mips_opts
.isa
< 0)
850 else if (mips_opts
.isa
== 2)
853 else if (mips_opts
.isa
== 3)
856 else if (mips_opts
.isa
== 4)
863 else if (strcmp (cpu
, "r3900") == 0
864 || strcmp (cpu
, "mipstx39") == 0
865 /* start-sanitize-tx19 */
866 || strcmp (cpu
, "r1900") == 0
867 || strcmp (cpu
, "mipstx19") == 0
868 /* end-sanitize-tx19 */
872 else if (strcmp (cpu
, "r6000") == 0
873 || strcmp (cpu
, "mips2") == 0)
876 else if (strcmp (cpu
, "mips64") == 0
877 || strcmp (cpu
, "r4000") == 0
878 || strcmp (cpu
, "mips3") == 0)
881 else if (strcmp (cpu
, "r4400") == 0)
884 else if (strcmp (cpu
, "mips64orion") == 0
885 || strcmp (cpu
, "r4600") == 0)
888 else if (strcmp (cpu
, "r4650") == 0)
891 else if (strcmp (cpu
, "mips64vr4300") == 0)
894 /* start-sanitize-vr4320 */
895 else if (strcmp (cpu
, "r4320") == 0
896 || strcmp (cpu
, "mips64vr4320") == 0)
899 /* end-sanitize-vr4320 */
900 else if (strcmp (cpu
, "mips64vr4100") == 0)
903 else if (strcmp (cpu
, "r4010") == 0)
906 /* start-sanitize-tx49 */
907 else if (strcmp (cpu
, "mips64tx49") == 0)
909 /* end-sanitize-tx49 */
911 else if (strcmp (cpu
, "r5000") == 0
912 || strcmp (cpu
, "mips64vr5000") == 0)
915 /* start-sanitize-vr5400 */
916 else if (strcmp (cpu
, "r5400") == 0
917 || strcmp (cpu
, "mips64vr5400") == 0)
919 /* end-sanitize-vr5400 */
921 /* start-sanitize-r5900 */
922 else if (strcmp (cpu
, "r5900") == 0
923 || strcmp (cpu
, "mips64r5900") == 0)
925 /* end-sanitize-r5900 */
927 else if (strcmp (cpu
, "r8000") == 0
928 || strcmp (cpu
, "mips4") == 0)
931 else if (strcmp (cpu
, "r10000") == 0)
934 else if (strcmp (cpu
, "mips16") == 0)
935 mips_cpu
= 0; /* FIXME */
941 if (mips_opts
.isa
== -1)
947 else if (mips_cpu
== 6000
951 else if (mips_cpu
== 4000
955 /* start-sanitize-vr4320 */
957 /* end-sanitize-vr4320 */
959 /* start-sanitize-tx49 */
961 /* end-sanitize-tx49 */
962 /* start-sanitize-r5900 */
964 /* end-sanitize-r5900 */
968 else if (mips_cpu
== 5000
969 /* start-sanitize-vr5400 */
971 /* end-sanitize-vr5400 */
973 || mips_cpu
== 10000)
980 if (mips_opts
.mips16
< 0)
982 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
983 mips_opts
.mips16
= 1;
985 mips_opts
.mips16
= 0;
989 mips_4650
= (mips_cpu
== 4650);
992 mips_4010
= (mips_cpu
== 4010);
995 mips_4100
= (mips_cpu
== 4100);
997 /* start-sanitize-vr4320 */
999 mips_4320
= (mips_cpu
== 4320);
1001 /* end-sanitize-vr4320 */
1002 /* start-sanitize-vr5400 */
1004 mips_5400
= (mips_cpu
== 5400);
1005 /* end-sanitize-vr5400 */
1007 /* start-sanitize-r5900 */
1009 mips_5900
= (mips_cpu
== 5900);
1010 /* end-sanitize-r5900 */
1013 mips_3900
= (mips_cpu
== 3900);
1015 /* start-sanitize-tx49 */
1017 mips_4900
= (mips_cpu
== 4900);
1019 /* end-sanitize-tx49 */
1021 /* End of TARGET_CPU processing, get rid of malloced memory
1030 if (mips_opts
.isa
< 2 && mips_trap
)
1031 as_bad ("trap exception not supported at ISA 1");
1033 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1035 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1039 switch (mips_opts
.isa
)
1042 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1045 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1048 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1051 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1057 as_warn ("Could not set architecture and machine");
1059 file_mips_isa
= mips_opts
.isa
;
1061 op_hash
= hash_new ();
1063 for (i
= 0; i
< NUMOPCODES
;)
1065 const char *name
= mips_opcodes
[i
].name
;
1067 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1070 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
1071 mips_opcodes
[i
].name
, retval
);
1072 /* Probably a memory allocation problem? Give up now. */
1073 as_fatal ("Broken assembler. No assembly attempted.");
1077 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1079 if (!validate_mips_insn (&mips_opcodes
[i
]))
1084 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1087 mips16_op_hash
= hash_new ();
1090 while (i
< bfd_mips16_num_opcodes
)
1092 const char *name
= mips16_opcodes
[i
].name
;
1094 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1096 as_fatal ("internal: can't hash `%s': %s",
1097 mips16_opcodes
[i
].name
, retval
);
1100 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1101 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1102 != mips16_opcodes
[i
].match
))
1104 fprintf (stderr
, "internal error: bad mips16 opcode: %s %s\n",
1105 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1110 while (i
< bfd_mips16_num_opcodes
1111 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1115 as_fatal ("Broken assembler. No assembly attempted.");
1117 /* We add all the general register names to the symbol table. This
1118 helps us detect invalid uses of them. */
1119 for (i
= 0; i
< 32; i
++)
1123 sprintf (buf
, "$%d", i
);
1124 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1125 &zero_address_frag
));
1127 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1128 &zero_address_frag
));
1129 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1130 &zero_address_frag
));
1131 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1132 &zero_address_frag
));
1133 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1134 &zero_address_frag
));
1135 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1136 &zero_address_frag
));
1137 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1138 &zero_address_frag
));
1139 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1140 &zero_address_frag
));
1142 mips_no_prev_insn (false);
1145 mips_cprmask
[0] = 0;
1146 mips_cprmask
[1] = 0;
1147 mips_cprmask
[2] = 0;
1148 mips_cprmask
[3] = 0;
1150 /* set the default alignment for the text section (2**2) */
1151 record_alignment (text_section
, 2);
1153 if (USE_GLOBAL_POINTER_OPT
)
1154 bfd_set_gp_size (stdoutput
, g_switch_value
);
1156 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1158 /* On a native system, sections must be aligned to 16 byte
1159 boundaries. When configured for an embedded ELF target, we
1161 if (strcmp (TARGET_OS
, "elf") != 0)
1163 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1164 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1165 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1168 /* Create a .reginfo section for register masks and a .mdebug
1169 section for debugging information. */
1177 subseg
= now_subseg
;
1179 /* The ABI says this section should be loaded so that the
1180 running program can access it. However, we don't load it
1181 if we are configured for an embedded target */
1182 flags
= SEC_READONLY
| SEC_DATA
;
1183 if (strcmp (TARGET_OS
, "elf") != 0)
1184 flags
|= SEC_ALLOC
| SEC_LOAD
;
1188 sec
= subseg_new (".reginfo", (subsegT
) 0);
1191 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1192 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1195 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1200 /* The 64-bit ABI uses a .MIPS.options section rather than
1201 .reginfo section. */
1202 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1203 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1204 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1207 /* Set up the option header. */
1209 Elf_Internal_Options opthdr
;
1212 opthdr
.kind
= ODK_REGINFO
;
1213 opthdr
.size
= (sizeof (Elf_External_Options
)
1214 + sizeof (Elf64_External_RegInfo
));
1217 f
= frag_more (sizeof (Elf_External_Options
));
1218 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1219 (Elf_External_Options
*) f
);
1221 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1226 if (ECOFF_DEBUGGING
)
1228 sec
= subseg_new (".mdebug", (subsegT
) 0);
1229 (void) bfd_set_section_flags (stdoutput
, sec
,
1230 SEC_HAS_CONTENTS
| SEC_READONLY
);
1231 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1234 subseg_set (seg
, subseg
);
1238 if (! ECOFF_DEBUGGING
)
1245 if (! ECOFF_DEBUGGING
)
1253 struct mips_cl_insn insn
;
1255 imm_expr
.X_op
= O_absent
;
1256 imm_reloc
= BFD_RELOC_UNUSED
;
1257 imm_unmatched_hi
= false;
1258 offset_expr
.X_op
= O_absent
;
1259 offset_reloc
= BFD_RELOC_UNUSED
;
1261 if (mips_opts
.mips16
)
1262 mips16_ip (str
, &insn
);
1265 mips_ip (str
, &insn
);
1266 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1267 str
, insn
.insn_opcode
));
1272 as_bad ("%s `%s'", insn_error
, str
);
1276 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1278 if (mips_opts
.mips16
)
1279 mips16_macro (&insn
);
1285 if (imm_expr
.X_op
!= O_absent
)
1286 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1288 else if (offset_expr
.X_op
!= O_absent
)
1289 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1291 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1295 /* See whether instruction IP reads register REG. CLASS is the type
1299 insn_uses_reg (ip
, reg
, class)
1300 struct mips_cl_insn
*ip
;
1302 enum mips_regclass
class;
1304 if (class == MIPS16_REG
)
1306 assert (mips_opts
.mips16
);
1307 reg
= mips16_to_32_reg_map
[reg
];
1308 class = MIPS_GR_REG
;
1311 /* Don't report on general register 0, since it never changes. */
1312 if (class == MIPS_GR_REG
&& reg
== 0)
1315 if (class == MIPS_FP_REG
)
1317 assert (! mips_opts
.mips16
);
1318 /* If we are called with either $f0 or $f1, we must check $f0.
1319 This is not optimal, because it will introduce an unnecessary
1320 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1321 need to distinguish reading both $f0 and $f1 or just one of
1322 them. Note that we don't have to check the other way,
1323 because there is no instruction that sets both $f0 and $f1
1324 and requires a delay. */
1325 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1326 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1327 == (reg
&~ (unsigned) 1)))
1329 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1330 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1331 == (reg
&~ (unsigned) 1)))
1334 else if (! mips_opts
.mips16
)
1336 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1337 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1339 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1340 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1345 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1346 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1347 & MIPS16OP_MASK_RX
)]
1350 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1351 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1352 & MIPS16OP_MASK_RY
)]
1355 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1356 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1357 & MIPS16OP_MASK_MOVE32Z
)]
1360 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1362 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1364 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1366 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1367 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1368 & MIPS16OP_MASK_REGR32
) == reg
)
1375 /* This function returns true if modifying a register requires a
1379 reg_needs_delay (reg
)
1382 unsigned long prev_pinfo
;
1384 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1385 if (! mips_opts
.noreorder
1386 && mips_opts
.isa
< 4
1387 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1388 || (! gpr_interlocks
1389 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1391 /* A load from a coprocessor or from memory. All load
1392 delays delay the use of general register rt for one
1393 instruction on the r3000. The r6000 and r4000 use
1395 /* Itbl support may require additional care here. */
1396 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1397 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1404 /* Mark instruction labels in mips16 mode. This permits the linker to
1405 handle them specially, such as generating jalx instructions when
1406 needed. We also make them odd for the duration of the assembly, in
1407 order to generate the right sort of code. We will make them even
1408 in the adjust_symtab routine, while leaving them marked. This is
1409 convenient for the debugger and the disassembler. The linker knows
1410 to make them odd again. */
1413 mips16_mark_labels ()
1415 if (mips_opts
.mips16
)
1417 struct insn_label_list
*l
;
1419 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1422 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1423 S_SET_OTHER (l
->label
, STO_MIPS16
);
1425 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1426 ++l
->label
->sy_value
.X_add_number
;
1431 /* Output an instruction. PLACE is where to put the instruction; if
1432 it is NULL, this uses frag_more to get room. IP is the instruction
1433 information. ADDRESS_EXPR is an operand of the instruction to be
1434 used with RELOC_TYPE. */
1437 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1439 struct mips_cl_insn
*ip
;
1440 expressionS
*address_expr
;
1441 bfd_reloc_code_real_type reloc_type
;
1442 boolean unmatched_hi
;
1444 register unsigned long prev_pinfo
, pinfo
;
1449 /* Mark instruction labels in mips16 mode. */
1450 if (mips_opts
.mips16
)
1451 mips16_mark_labels ();
1453 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1454 pinfo
= ip
->insn_mo
->pinfo
;
1456 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1460 /* If the previous insn required any delay slots, see if we need
1461 to insert a NOP or two. There are eight kinds of possible
1462 hazards, of which an instruction can have at most one type.
1463 (1) a load from memory delay
1464 (2) a load from a coprocessor delay
1465 (3) an unconditional branch delay
1466 (4) a conditional branch delay
1467 (5) a move to coprocessor register delay
1468 (6) a load coprocessor register from memory delay
1469 (7) a coprocessor condition code delay
1470 (8) a HI/LO special register delay
1472 There are a lot of optimizations we could do that we don't.
1473 In particular, we do not, in general, reorder instructions.
1474 If you use gcc with optimization, it will reorder
1475 instructions and generally do much more optimization then we
1476 do here; repeating all that work in the assembler would only
1477 benefit hand written assembly code, and does not seem worth
1480 /* This is how a NOP is emitted. */
1481 #define emit_nop() \
1483 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1484 : md_number_to_chars (frag_more (4), 0, 4))
1486 /* The previous insn might require a delay slot, depending upon
1487 the contents of the current insn. */
1488 if (! mips_opts
.mips16
1489 && mips_opts
.isa
< 4
1490 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1491 && ! cop_interlocks
)
1492 || (! gpr_interlocks
1493 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1495 /* A load from a coprocessor or from memory. All load
1496 delays delay the use of general register rt for one
1497 instruction on the r3000. The r6000 and r4000 use
1499 /* Itbl support may require additional care here. */
1500 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1501 if (mips_optimize
== 0
1502 || insn_uses_reg (ip
,
1503 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1508 else if (! mips_opts
.mips16
1509 && mips_opts
.isa
< 4
1510 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1511 && ! cop_interlocks
)
1512 || (mips_opts
.isa
< 2
1513 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1515 /* A generic coprocessor delay. The previous instruction
1516 modified a coprocessor general or control register. If
1517 it modified a control register, we need to avoid any
1518 coprocessor instruction (this is probably not always
1519 required, but it sometimes is). If it modified a general
1520 register, we avoid using that register.
1522 On the r6000 and r4000 loading a coprocessor register
1523 from memory is interlocked, and does not require a delay.
1525 This case is not handled very well. There is no special
1526 knowledge of CP0 handling, and the coprocessors other
1527 than the floating point unit are not distinguished at
1529 /* Itbl support may require additional care here. FIXME!
1530 Need to modify this to include knowledge about
1531 user specified delays! */
1532 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1534 if (mips_optimize
== 0
1535 || insn_uses_reg (ip
,
1536 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1541 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1543 if (mips_optimize
== 0
1544 || insn_uses_reg (ip
,
1545 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1552 /* We don't know exactly what the previous instruction
1553 does. If the current instruction uses a coprocessor
1554 register, we must insert a NOP. If previous
1555 instruction may set the condition codes, and the
1556 current instruction uses them, we must insert two
1558 /* Itbl support may require additional care here. */
1559 if (mips_optimize
== 0
1560 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1561 && (pinfo
& INSN_READ_COND_CODE
)))
1563 else if (pinfo
& INSN_COP
)
1567 else if (! mips_opts
.mips16
1568 && mips_opts
.isa
< 4
1569 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1570 && ! cop_interlocks
)
1572 /* The previous instruction sets the coprocessor condition
1573 codes, but does not require a general coprocessor delay
1574 (this means it is a floating point comparison
1575 instruction). If this instruction uses the condition
1576 codes, we need to insert a single NOP. */
1577 /* Itbl support may require additional care here. */
1578 if (mips_optimize
== 0
1579 || (pinfo
& INSN_READ_COND_CODE
))
1582 else if (prev_pinfo
& INSN_READ_LO
)
1584 /* The previous instruction reads the LO register; if the
1585 current instruction writes to the LO register, we must
1586 insert two NOPS. Some newer processors have interlocks. */
1587 if (! hilo_interlocks
1588 && (mips_optimize
== 0
1589 || (pinfo
& INSN_WRITE_LO
)))
1592 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1594 /* The previous instruction reads the HI register; if the
1595 current instruction writes to the HI register, we must
1596 insert a NOP. Some newer processors have interlocks. */
1597 if (! hilo_interlocks
1598 && (mips_optimize
== 0
1599 || (pinfo
& INSN_WRITE_HI
)))
1603 /* If the previous instruction was in a noreorder section, then
1604 we don't want to insert the nop after all. */
1605 /* Itbl support may require additional care here. */
1606 if (prev_insn_unreordered
)
1609 /* There are two cases which require two intervening
1610 instructions: 1) setting the condition codes using a move to
1611 coprocessor instruction which requires a general coprocessor
1612 delay and then reading the condition codes 2) reading the HI
1613 or LO register and then writing to it (except on processors
1614 which have interlocks). If we are not already emitting a NOP
1615 instruction, we must check for these cases compared to the
1616 instruction previous to the previous instruction. */
1617 if ((! mips_opts
.mips16
1618 && mips_opts
.isa
< 4
1619 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1620 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1621 && (pinfo
& INSN_READ_COND_CODE
)
1622 && ! cop_interlocks
)
1623 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1624 && (pinfo
& INSN_WRITE_LO
)
1625 && ! hilo_interlocks
)
1626 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1627 && (pinfo
& INSN_WRITE_HI
)
1628 && ! hilo_interlocks
))
1633 if (prev_prev_insn_unreordered
)
1636 if (prev_prev_nop
&& nops
== 0)
1639 /* If we are being given a nop instruction, don't bother with
1640 one of the nops we would otherwise output. This will only
1641 happen when a nop instruction is used with mips_optimize set
1644 && ! mips_opts
.noreorder
1645 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1648 /* Now emit the right number of NOP instructions. */
1649 if (nops
> 0 && ! mips_opts
.noreorder
)
1652 unsigned long old_frag_offset
;
1654 struct insn_label_list
*l
;
1656 old_frag
= frag_now
;
1657 old_frag_offset
= frag_now_fix ();
1659 for (i
= 0; i
< nops
; i
++)
1664 listing_prev_line ();
1665 /* We may be at the start of a variant frag. In case we
1666 are, make sure there is enough space for the frag
1667 after the frags created by listing_prev_line. The
1668 argument to frag_grow here must be at least as large
1669 as the argument to all other calls to frag_grow in
1670 this file. We don't have to worry about being in the
1671 middle of a variant frag, because the variants insert
1672 all needed nop instructions themselves. */
1676 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1678 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1679 l
->label
->sy_frag
= frag_now
;
1680 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1681 /* mips16 text labels are stored as odd. */
1682 if (mips_opts
.mips16
)
1683 ++l
->label
->sy_value
.X_add_number
;
1686 #ifndef NO_ECOFF_DEBUGGING
1687 if (ECOFF_DEBUGGING
)
1688 ecoff_fix_loc (old_frag
, old_frag_offset
);
1691 else if (prev_nop_frag
!= NULL
)
1693 /* We have a frag holding nops we may be able to remove. If
1694 we don't need any nops, we can decrease the size of
1695 prev_nop_frag by the size of one instruction. If we do
1696 need some nops, we count them in prev_nops_required. */
1697 if (prev_nop_frag_since
== 0)
1701 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1702 --prev_nop_frag_holds
;
1705 prev_nop_frag_required
+= nops
;
1709 if (prev_prev_nop
== 0)
1711 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1712 --prev_nop_frag_holds
;
1715 ++prev_nop_frag_required
;
1718 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1719 prev_nop_frag
= NULL
;
1721 ++prev_nop_frag_since
;
1723 /* Sanity check: by the time we reach the second instruction
1724 after prev_nop_frag, we should have used up all the nops
1725 one way or another. */
1726 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1730 if (reloc_type
> BFD_RELOC_UNUSED
)
1732 /* We need to set up a variant frag. */
1733 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1734 f
= frag_var (rs_machine_dependent
, 4, 0,
1735 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1736 mips16_small
, mips16_ext
,
1738 & INSN_UNCOND_BRANCH_DELAY
),
1739 (prev_insn_reloc_type
1740 == BFD_RELOC_MIPS16_JMP
)),
1741 make_expr_symbol (address_expr
), (offsetT
) 0,
1744 else if (place
!= NULL
)
1746 else if (mips_opts
.mips16
1748 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1750 /* Make sure there is enough room to swap this instruction with
1751 a following jump instruction. */
1757 if (mips_opts
.mips16
1758 && mips_opts
.noreorder
1759 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1760 as_warn ("extended instruction in delay slot");
1766 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1768 if (address_expr
->X_op
== O_constant
)
1773 ip
->insn_opcode
|= address_expr
->X_add_number
;
1776 case BFD_RELOC_LO16
:
1777 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1780 case BFD_RELOC_MIPS_JMP
:
1781 if ((address_expr
->X_add_number
& 3) != 0)
1782 as_bad ("jump to misaligned address (0x%lx)",
1783 (unsigned long) address_expr
->X_add_number
);
1784 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1787 case BFD_RELOC_MIPS16_JMP
:
1788 if ((address_expr
->X_add_number
& 3) != 0)
1789 as_bad ("jump to misaligned address (0x%lx)",
1790 (unsigned long) address_expr
->X_add_number
);
1792 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1793 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1794 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1797 case BFD_RELOC_16_PCREL_S2
:
1807 /* Don't generate a reloc if we are writing into a variant
1811 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1813 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1817 struct mips_hi_fixup
*hi_fixup
;
1819 assert (reloc_type
== BFD_RELOC_HI16_S
);
1820 hi_fixup
= ((struct mips_hi_fixup
*)
1821 xmalloc (sizeof (struct mips_hi_fixup
)));
1822 hi_fixup
->fixp
= fixp
;
1823 hi_fixup
->seg
= now_seg
;
1824 hi_fixup
->next
= mips_hi_fixup_list
;
1825 mips_hi_fixup_list
= hi_fixup
;
1831 if (! mips_opts
.mips16
)
1832 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1833 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1835 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1836 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1842 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1845 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1848 /* Update the register mask information. */
1849 if (! mips_opts
.mips16
)
1851 if (pinfo
& INSN_WRITE_GPR_D
)
1852 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1853 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1854 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1855 if (pinfo
& INSN_READ_GPR_S
)
1856 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1857 if (pinfo
& INSN_WRITE_GPR_31
)
1858 mips_gprmask
|= 1 << 31;
1859 if (pinfo
& INSN_WRITE_FPR_D
)
1860 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1861 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1862 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1863 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1864 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1865 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1866 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1867 if (pinfo
& INSN_COP
)
1869 /* We don't keep enough information to sort these cases out.
1870 The itbl support does keep this information however, although
1871 we currently don't support itbl fprmats as part of the cop
1872 instruction. May want to add this support in the future. */
1874 /* Never set the bit for $0, which is always zero. */
1875 mips_gprmask
&=~ 1 << 0;
1879 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1880 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1881 & MIPS16OP_MASK_RX
);
1882 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1883 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1884 & MIPS16OP_MASK_RY
);
1885 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1886 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1887 & MIPS16OP_MASK_RZ
);
1888 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1889 mips_gprmask
|= 1 << TREG
;
1890 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1891 mips_gprmask
|= 1 << SP
;
1892 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1893 mips_gprmask
|= 1 << RA
;
1894 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1895 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1896 if (pinfo
& MIPS16_INSN_READ_Z
)
1897 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1898 & MIPS16OP_MASK_MOVE32Z
);
1899 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1900 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1901 & MIPS16OP_MASK_REGR32
);
1904 if (place
== NULL
&& ! mips_opts
.noreorder
)
1906 /* Filling the branch delay slot is more complex. We try to
1907 switch the branch with the previous instruction, which we can
1908 do if the previous instruction does not set up a condition
1909 that the branch tests and if the branch is not itself the
1910 target of any branch. */
1911 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1912 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1914 if (mips_optimize
< 2
1915 /* If we have seen .set volatile or .set nomove, don't
1917 || mips_opts
.nomove
!= 0
1918 /* If we had to emit any NOP instructions, then we
1919 already know we can not swap. */
1921 /* If we don't even know the previous insn, we can not
1923 || ! prev_insn_valid
1924 /* If the previous insn is already in a branch delay
1925 slot, then we can not swap. */
1926 || prev_insn_is_delay_slot
1927 /* If the previous previous insn was in a .set
1928 noreorder, we can't swap. Actually, the MIPS
1929 assembler will swap in this situation. However, gcc
1930 configured -with-gnu-as will generate code like
1936 in which we can not swap the bne and INSN. If gcc is
1937 not configured -with-gnu-as, it does not output the
1938 .set pseudo-ops. We don't have to check
1939 prev_insn_unreordered, because prev_insn_valid will
1940 be 0 in that case. We don't want to use
1941 prev_prev_insn_valid, because we do want to be able
1942 to swap at the start of a function. */
1943 || prev_prev_insn_unreordered
1944 /* If the branch is itself the target of a branch, we
1945 can not swap. We cheat on this; all we check for is
1946 whether there is a label on this instruction. If
1947 there are any branches to anything other than a
1948 label, users must use .set noreorder. */
1949 || insn_labels
!= NULL
1950 /* If the previous instruction is in a variant frag, we
1951 can not do the swap. This does not apply to the
1952 mips16, which uses variant frags for different
1954 || (! mips_opts
.mips16
1955 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1956 /* If the branch reads the condition codes, we don't
1957 even try to swap, because in the sequence
1962 we can not swap, and I don't feel like handling that
1964 || (! mips_opts
.mips16
1965 && mips_opts
.isa
< 4
1966 && (pinfo
& INSN_READ_COND_CODE
))
1967 /* We can not swap with an instruction that requires a
1968 delay slot, becase the target of the branch might
1969 interfere with that instruction. */
1970 || (! mips_opts
.mips16
1971 && mips_opts
.isa
< 4
1973 /* Itbl support may require additional care here. */
1974 & (INSN_LOAD_COPROC_DELAY
1975 | INSN_COPROC_MOVE_DELAY
1976 | INSN_WRITE_COND_CODE
)))
1977 || (! hilo_interlocks
1981 || (! mips_opts
.mips16
1983 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1984 || (! mips_opts
.mips16
1985 && mips_opts
.isa
< 2
1986 /* Itbl support may require additional care here. */
1987 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1988 /* We can not swap with a branch instruction. */
1990 & (INSN_UNCOND_BRANCH_DELAY
1991 | INSN_COND_BRANCH_DELAY
1992 | INSN_COND_BRANCH_LIKELY
))
1993 /* We do not swap with a trap instruction, since it
1994 complicates trap handlers to have the trap
1995 instruction be in a delay slot. */
1996 || (prev_pinfo
& INSN_TRAP
)
1997 /* If the branch reads a register that the previous
1998 instruction sets, we can not swap. */
1999 || (! mips_opts
.mips16
2000 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2001 && insn_uses_reg (ip
,
2002 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2005 || (! mips_opts
.mips16
2006 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2007 && insn_uses_reg (ip
,
2008 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2011 || (mips_opts
.mips16
2012 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2013 && insn_uses_reg (ip
,
2014 ((prev_insn
.insn_opcode
2016 & MIPS16OP_MASK_RX
),
2018 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2019 && insn_uses_reg (ip
,
2020 ((prev_insn
.insn_opcode
2022 & MIPS16OP_MASK_RY
),
2024 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2025 && insn_uses_reg (ip
,
2026 ((prev_insn
.insn_opcode
2028 & MIPS16OP_MASK_RZ
),
2030 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2031 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2032 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2033 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2034 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2035 && insn_uses_reg (ip
,
2036 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2039 /* If the branch writes a register that the previous
2040 instruction sets, we can not swap (we know that
2041 branches write only to RD or to $31). */
2042 || (! mips_opts
.mips16
2043 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2044 && (((pinfo
& INSN_WRITE_GPR_D
)
2045 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2046 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2047 || ((pinfo
& INSN_WRITE_GPR_31
)
2048 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2051 || (! mips_opts
.mips16
2052 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2053 && (((pinfo
& INSN_WRITE_GPR_D
)
2054 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2055 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2056 || ((pinfo
& INSN_WRITE_GPR_31
)
2057 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2060 || (mips_opts
.mips16
2061 && (pinfo
& MIPS16_INSN_WRITE_31
)
2062 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2063 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2064 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2066 /* If the branch writes a register that the previous
2067 instruction reads, we can not swap (we know that
2068 branches only write to RD or to $31). */
2069 || (! mips_opts
.mips16
2070 && (pinfo
& INSN_WRITE_GPR_D
)
2071 && insn_uses_reg (&prev_insn
,
2072 ((ip
->insn_opcode
>> OP_SH_RD
)
2075 || (! mips_opts
.mips16
2076 && (pinfo
& INSN_WRITE_GPR_31
)
2077 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2078 || (mips_opts
.mips16
2079 && (pinfo
& MIPS16_INSN_WRITE_31
)
2080 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2081 /* If we are generating embedded PIC code, the branch
2082 might be expanded into a sequence which uses $at, so
2083 we can't swap with an instruction which reads it. */
2084 || (mips_pic
== EMBEDDED_PIC
2085 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2086 /* If the previous previous instruction has a load
2087 delay, and sets a register that the branch reads, we
2089 || (! mips_opts
.mips16
2090 && mips_opts
.isa
< 4
2091 /* Itbl support may require additional care here. */
2092 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2093 || (! gpr_interlocks
2094 && (prev_prev_insn
.insn_mo
->pinfo
2095 & INSN_LOAD_MEMORY_DELAY
)))
2096 && insn_uses_reg (ip
,
2097 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2100 /* If one instruction sets a condition code and the
2101 other one uses a condition code, we can not swap. */
2102 || ((pinfo
& INSN_READ_COND_CODE
)
2103 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2104 || ((pinfo
& INSN_WRITE_COND_CODE
)
2105 && (prev_pinfo
& INSN_READ_COND_CODE
))
2106 /* If the previous instruction uses the PC, we can not
2108 || (mips_opts
.mips16
2109 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2110 /* If the previous instruction was extended, we can not
2112 || (mips_opts
.mips16
&& prev_insn_extended
)
2113 /* If the previous instruction had a fixup in mips16
2114 mode, we can not swap. This normally means that the
2115 previous instruction was a 4 byte branch anyhow. */
2116 || (mips_opts
.mips16
&& prev_insn_fixp
))
2118 /* We could do even better for unconditional branches to
2119 portions of this object file; we could pick up the
2120 instruction at the destination, put it in the delay
2121 slot, and bump the destination address. */
2123 /* Update the previous insn information. */
2124 prev_prev_insn
= *ip
;
2125 prev_insn
.insn_mo
= &dummy_opcode
;
2129 /* It looks like we can actually do the swap. */
2130 if (! mips_opts
.mips16
)
2135 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2136 memcpy (temp
, prev_f
, 4);
2137 memcpy (prev_f
, f
, 4);
2138 memcpy (f
, temp
, 4);
2141 prev_insn_fixp
->fx_frag
= frag_now
;
2142 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2146 fixp
->fx_frag
= prev_insn_frag
;
2147 fixp
->fx_where
= prev_insn_where
;
2155 assert (prev_insn_fixp
== NULL
);
2156 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2157 memcpy (temp
, prev_f
, 2);
2158 memcpy (prev_f
, f
, 2);
2159 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2161 assert (reloc_type
== BFD_RELOC_UNUSED
);
2162 memcpy (f
, temp
, 2);
2166 memcpy (f
, f
+ 2, 2);
2167 memcpy (f
+ 2, temp
, 2);
2171 fixp
->fx_frag
= prev_insn_frag
;
2172 fixp
->fx_where
= prev_insn_where
;
2176 /* Update the previous insn information; leave prev_insn
2178 prev_prev_insn
= *ip
;
2180 prev_insn_is_delay_slot
= 1;
2182 /* If that was an unconditional branch, forget the previous
2183 insn information. */
2184 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2186 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2187 prev_insn
.insn_mo
= &dummy_opcode
;
2190 prev_insn_fixp
= NULL
;
2191 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2192 prev_insn_extended
= 0;
2194 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2196 /* We don't yet optimize a branch likely. What we should do
2197 is look at the target, copy the instruction found there
2198 into the delay slot, and increment the branch to jump to
2199 the next instruction. */
2201 /* Update the previous insn information. */
2202 prev_prev_insn
= *ip
;
2203 prev_insn
.insn_mo
= &dummy_opcode
;
2204 prev_insn_fixp
= NULL
;
2205 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2206 prev_insn_extended
= 0;
2210 /* Update the previous insn information. */
2212 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2214 prev_prev_insn
= prev_insn
;
2217 /* Any time we see a branch, we always fill the delay slot
2218 immediately; since this insn is not a branch, we know it
2219 is not in a delay slot. */
2220 prev_insn_is_delay_slot
= 0;
2222 prev_insn_fixp
= fixp
;
2223 prev_insn_reloc_type
= reloc_type
;
2224 if (mips_opts
.mips16
)
2225 prev_insn_extended
= (ip
->use_extend
2226 || reloc_type
> BFD_RELOC_UNUSED
);
2229 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2230 prev_insn_unreordered
= 0;
2231 prev_insn_frag
= frag_now
;
2232 prev_insn_where
= f
- frag_now
->fr_literal
;
2233 prev_insn_valid
= 1;
2235 else if (place
== NULL
)
2237 /* We need to record a bit of information even when we are not
2238 reordering, in order to determine the base address for mips16
2239 PC relative relocs. */
2240 prev_prev_insn
= prev_insn
;
2242 prev_insn_reloc_type
= reloc_type
;
2243 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2244 prev_insn_unreordered
= 1;
2247 /* We just output an insn, so the next one doesn't have a label. */
2248 mips_clear_insn_labels ();
2250 /* We must ensure that a fixup associated with an unmatched %hi
2251 reloc does not become a variant frag. Otherwise, the
2252 rearrangement of %hi relocs in frob_file may confuse
2256 frag_wane (frag_now
);
2261 /* This function forgets that there was any previous instruction or
2262 label. If PRESERVE is non-zero, it remembers enough information to
2263 know whether nops are needed before a noreorder section. */
2266 mips_no_prev_insn (preserve
)
2271 prev_insn
.insn_mo
= &dummy_opcode
;
2272 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2273 prev_nop_frag
= NULL
;
2274 prev_nop_frag_holds
= 0;
2275 prev_nop_frag_required
= 0;
2276 prev_nop_frag_since
= 0;
2278 prev_insn_valid
= 0;
2279 prev_insn_is_delay_slot
= 0;
2280 prev_insn_unreordered
= 0;
2281 prev_insn_extended
= 0;
2282 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2283 prev_prev_insn_unreordered
= 0;
2284 mips_clear_insn_labels ();
2287 /* This function must be called whenever we turn on noreorder or emit
2288 something other than instructions. It inserts any NOPS which might
2289 be needed by the previous instruction, and clears the information
2290 kept for the previous instructions. The INSNS parameter is true if
2291 instructions are to follow. */
2294 mips_emit_delays (insns
)
2297 if (! mips_opts
.noreorder
)
2302 if ((! mips_opts
.mips16
2303 && mips_opts
.isa
< 4
2304 && (! cop_interlocks
2305 && (prev_insn
.insn_mo
->pinfo
2306 & (INSN_LOAD_COPROC_DELAY
2307 | INSN_COPROC_MOVE_DELAY
2308 | INSN_WRITE_COND_CODE
))))
2309 || (! hilo_interlocks
2310 && (prev_insn
.insn_mo
->pinfo
2313 || (! mips_opts
.mips16
2315 && (prev_insn
.insn_mo
->pinfo
2316 & INSN_LOAD_MEMORY_DELAY
))
2317 || (! mips_opts
.mips16
2318 && mips_opts
.isa
< 2
2319 && (prev_insn
.insn_mo
->pinfo
2320 & INSN_COPROC_MEMORY_DELAY
)))
2322 /* Itbl support may require additional care here. */
2324 if ((! mips_opts
.mips16
2325 && mips_opts
.isa
< 4
2326 && (! cop_interlocks
2327 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2328 || (! hilo_interlocks
2329 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2330 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2333 if (prev_insn_unreordered
)
2336 else if ((! mips_opts
.mips16
2337 && mips_opts
.isa
< 4
2338 && (! cop_interlocks
2339 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2340 || (! hilo_interlocks
2341 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2342 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2344 /* Itbl support may require additional care here. */
2345 if (! prev_prev_insn_unreordered
)
2351 struct insn_label_list
*l
;
2355 /* Record the frag which holds the nop instructions, so
2356 that we can remove them if we don't need them. */
2357 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2358 prev_nop_frag
= frag_now
;
2359 prev_nop_frag_holds
= nops
;
2360 prev_nop_frag_required
= 0;
2361 prev_nop_frag_since
= 0;
2364 for (; nops
> 0; --nops
)
2369 /* Move on to a new frag, so that it is safe to simply
2370 decrease the size of prev_nop_frag. */
2371 frag_wane (frag_now
);
2375 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2377 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2378 l
->label
->sy_frag
= frag_now
;
2379 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2380 /* mips16 text labels are stored as odd. */
2381 if (mips_opts
.mips16
)
2382 ++l
->label
->sy_value
.X_add_number
;
2387 /* Mark instruction labels in mips16 mode. */
2388 if (mips_opts
.mips16
&& insns
)
2389 mips16_mark_labels ();
2391 mips_no_prev_insn (insns
);
2394 /* Build an instruction created by a macro expansion. This is passed
2395 a pointer to the count of instructions created so far, an
2396 expression, the name of the instruction to build, an operand format
2397 string, and corresponding arguments. */
2401 macro_build (char *place
,
2409 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2418 struct mips_cl_insn insn
;
2419 bfd_reloc_code_real_type r
;
2424 va_start (args
, fmt
);
2430 * If the macro is about to expand into a second instruction,
2431 * print a warning if needed. We need to pass ip as a parameter
2432 * to generate a better warning message here...
2434 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2435 as_warn ("Macro instruction expanded into multiple instructions");
2438 *counter
+= 1; /* bump instruction counter */
2440 if (mips_opts
.mips16
)
2442 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2447 r
= BFD_RELOC_UNUSED
;
2448 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2449 assert (insn
.insn_mo
);
2450 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2452 /* Search until we get a match for NAME. */
2455 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2457 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2459 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2461 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2466 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2467 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2468 && (insn_isa
<= mips_opts
.isa
2470 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2472 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2474 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2475 /* start-sanitize-vr4320 */
2477 && (insn
.insn_mo
->membership
& INSN_4320
) != 0)
2478 /* end-sanitize-vr4320 */
2479 /* start-sanitize-tx49 */
2481 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2482 /* end-sanitize-tx49 */
2483 /* start-sanitize-r5900 */
2485 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2486 /* end-sanitize-r5900 */
2487 /* start-sanitize-vr5400 */
2489 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2490 /* end-sanitize-vr5400 */
2492 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2493 /* start-sanitize-r5900 */
2494 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2495 /* end-sanitize-r5900 */
2496 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2500 assert (insn
.insn_mo
->name
);
2501 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2504 insn
.insn_opcode
= insn
.insn_mo
->match
;
2520 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2526 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2531 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2536 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2543 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2547 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2551 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2558 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2564 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2565 assert (r
== BFD_RELOC_MIPS_GPREL
2566 || r
== BFD_RELOC_MIPS_LITERAL
2567 || r
== BFD_RELOC_LO16
2568 || r
== BFD_RELOC_MIPS_GOT16
2569 || r
== BFD_RELOC_MIPS_CALL16
2570 || r
== BFD_RELOC_MIPS_GOT_LO16
2571 || r
== BFD_RELOC_MIPS_CALL_LO16
2572 || (ep
->X_op
== O_subtract
2573 && now_seg
== text_section
2574 && r
== BFD_RELOC_PCREL_LO16
));
2578 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2580 && (ep
->X_op
== O_constant
2581 || (ep
->X_op
== O_symbol
2582 && (r
== BFD_RELOC_HI16_S
2583 || r
== BFD_RELOC_HI16
2584 || r
== BFD_RELOC_MIPS_GOT_HI16
2585 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2586 || (ep
->X_op
== O_subtract
2587 && now_seg
== text_section
2588 && r
== BFD_RELOC_PCREL_HI16_S
)));
2589 if (ep
->X_op
== O_constant
)
2591 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2593 r
= BFD_RELOC_UNUSED
;
2598 assert (ep
!= NULL
);
2600 * This allows macro() to pass an immediate expression for
2601 * creating short branches without creating a symbol.
2602 * Note that the expression still might come from the assembly
2603 * input, in which case the value is not checked for range nor
2604 * is a relocation entry generated (yuck).
2606 if (ep
->X_op
== O_constant
)
2608 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2612 r
= BFD_RELOC_16_PCREL_S2
;
2616 assert (ep
!= NULL
);
2617 r
= BFD_RELOC_MIPS_JMP
;
2621 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2630 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2632 append_insn (place
, &insn
, ep
, r
, false);
2636 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2644 struct mips_cl_insn insn
;
2645 bfd_reloc_code_real_type r
;
2647 r
= BFD_RELOC_UNUSED
;
2648 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2649 assert (insn
.insn_mo
);
2650 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2652 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2653 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2656 assert (insn
.insn_mo
->name
);
2657 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2660 insn
.insn_opcode
= insn
.insn_mo
->match
;
2661 insn
.use_extend
= false;
2680 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2685 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2689 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2693 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2703 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2710 regno
= va_arg (args
, int);
2711 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2712 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2733 assert (ep
!= NULL
);
2735 if (ep
->X_op
!= O_constant
)
2736 r
= BFD_RELOC_UNUSED
+ c
;
2739 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2740 false, false, &insn
.insn_opcode
,
2741 &insn
.use_extend
, &insn
.extend
);
2743 r
= BFD_RELOC_UNUSED
;
2749 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2756 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2758 append_insn (place
, &insn
, ep
, r
, false);
2762 * Generate a "lui" instruction.
2765 macro_build_lui (place
, counter
, ep
, regnum
)
2771 expressionS high_expr
;
2772 struct mips_cl_insn insn
;
2773 bfd_reloc_code_real_type r
;
2774 CONST
char *name
= "lui";
2775 CONST
char *fmt
= "t,u";
2777 assert (! mips_opts
.mips16
);
2783 high_expr
.X_op
= O_constant
;
2784 high_expr
.X_add_number
= ep
->X_add_number
;
2787 if (high_expr
.X_op
== O_constant
)
2789 /* we can compute the instruction now without a relocation entry */
2790 if (high_expr
.X_add_number
& 0x8000)
2791 high_expr
.X_add_number
+= 0x10000;
2792 high_expr
.X_add_number
=
2793 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2794 r
= BFD_RELOC_UNUSED
;
2798 assert (ep
->X_op
== O_symbol
);
2799 /* _gp_disp is a special case, used from s_cpload. */
2800 assert (mips_pic
== NO_PIC
2801 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2802 r
= BFD_RELOC_HI16_S
;
2806 * If the macro is about to expand into a second instruction,
2807 * print a warning if needed. We need to pass ip as a parameter
2808 * to generate a better warning message here...
2810 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2811 as_warn ("Macro instruction expanded into multiple instructions");
2814 *counter
+= 1; /* bump instruction counter */
2816 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2817 assert (insn
.insn_mo
);
2818 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2819 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2821 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2822 if (r
== BFD_RELOC_UNUSED
)
2824 insn
.insn_opcode
|= high_expr
.X_add_number
;
2825 append_insn (place
, &insn
, NULL
, r
, false);
2828 append_insn (place
, &insn
, &high_expr
, r
, false);
2832 * Generates code to set the $at register to true (one)
2833 * if reg is less than the immediate expression.
2836 set_at (counter
, reg
, unsignedp
)
2841 if (imm_expr
.X_op
== O_constant
2842 && imm_expr
.X_add_number
>= -0x8000
2843 && imm_expr
.X_add_number
< 0x8000)
2844 macro_build ((char *) NULL
, counter
, &imm_expr
,
2845 unsignedp
? "sltiu" : "slti",
2846 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2849 load_register (counter
, AT
, &imm_expr
, 0);
2850 macro_build ((char *) NULL
, counter
, NULL
,
2851 unsignedp
? "sltu" : "slt",
2852 "d,v,t", AT
, reg
, AT
);
2856 /* Warn if an expression is not a constant. */
2859 check_absolute_expr (ip
, ex
)
2860 struct mips_cl_insn
*ip
;
2863 if (ex
->X_op
== O_big
)
2864 as_bad ("unsupported large constant");
2865 else if (ex
->X_op
!= O_constant
)
2866 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2869 /* Count the leading zeroes by performing a binary chop. This is a
2870 bulky bit of source, but performance is a LOT better for the
2871 majority of values than a simple loop to count the bits:
2872 for (lcnt = 0; (lcnt < 32); lcnt++)
2873 if ((v) & (1 << (31 - lcnt)))
2875 However it is not code size friendly, and the gain will drop a bit
2876 on certain cached systems.
2878 #define COUNT_TOP_ZEROES(v) \
2879 (((v) & ~0xffff) == 0 \
2880 ? ((v) & ~0xff) == 0 \
2881 ? ((v) & ~0xf) == 0 \
2882 ? ((v) & ~0x3) == 0 \
2883 ? ((v) & ~0x1) == 0 \
2888 : ((v) & ~0x7) == 0 \
2891 : ((v) & ~0x3f) == 0 \
2892 ? ((v) & ~0x1f) == 0 \
2895 : ((v) & ~0x7f) == 0 \
2898 : ((v) & ~0xfff) == 0 \
2899 ? ((v) & ~0x3ff) == 0 \
2900 ? ((v) & ~0x1ff) == 0 \
2903 : ((v) & ~0x7ff) == 0 \
2906 : ((v) & ~0x3fff) == 0 \
2907 ? ((v) & ~0x1fff) == 0 \
2910 : ((v) & ~0x7fff) == 0 \
2913 : ((v) & ~0xffffff) == 0 \
2914 ? ((v) & ~0xfffff) == 0 \
2915 ? ((v) & ~0x3ffff) == 0 \
2916 ? ((v) & ~0x1ffff) == 0 \
2919 : ((v) & ~0x7ffff) == 0 \
2922 : ((v) & ~0x3fffff) == 0 \
2923 ? ((v) & ~0x1fffff) == 0 \
2926 : ((v) & ~0x7fffff) == 0 \
2929 : ((v) & ~0xfffffff) == 0 \
2930 ? ((v) & ~0x3ffffff) == 0 \
2931 ? ((v) & ~0x1ffffff) == 0 \
2934 : ((v) & ~0x7ffffff) == 0 \
2937 : ((v) & ~0x3fffffff) == 0 \
2938 ? ((v) & ~0x1fffffff) == 0 \
2941 : ((v) & ~0x7fffffff) == 0 \
2946 * This routine generates the least number of instructions neccessary to load
2947 * an absolute expression value into a register.
2950 load_register (counter
, reg
, ep
, dbl
)
2957 expressionS hi32
, lo32
;
2959 if (ep
->X_op
!= O_big
)
2961 assert (ep
->X_op
== O_constant
);
2962 if (ep
->X_add_number
< 0x8000
2963 && (ep
->X_add_number
>= 0
2964 || (ep
->X_add_number
>= -0x8000
2967 || sizeof (ep
->X_add_number
) > 4))))
2969 /* We can handle 16 bit signed values with an addiu to
2970 $zero. No need to ever use daddiu here, since $zero and
2971 the result are always correct in 32 bit mode. */
2972 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2973 (int) BFD_RELOC_LO16
);
2976 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2978 /* We can handle 16 bit unsigned values with an ori to
2980 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2981 (int) BFD_RELOC_LO16
);
2984 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2985 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2986 == ~ (offsetT
) 0x7fffffff))
2989 || sizeof (ep
->X_add_number
) > 4
2990 || (ep
->X_add_number
& 0x80000000) == 0))
2991 || ((mips_opts
.isa
< 3 || ! dbl
)
2992 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2993 || (mips_opts
.isa
< 3
2995 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2996 == ~ (offsetT
) 0xffffffff)))
2998 /* 32 bit values require an lui. */
2999 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3000 (int) BFD_RELOC_HI16
);
3001 if ((ep
->X_add_number
& 0xffff) != 0)
3002 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3003 (int) BFD_RELOC_LO16
);
3008 /* The value is larger than 32 bits. */
3010 if (mips_opts
.isa
< 3)
3012 as_bad ("Number larger than 32 bits");
3013 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3014 (int) BFD_RELOC_LO16
);
3018 if (ep
->X_op
!= O_big
)
3021 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3022 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3023 hi32
.X_add_number
&= 0xffffffff;
3025 lo32
.X_add_number
&= 0xffffffff;
3029 assert (ep
->X_add_number
> 2);
3030 if (ep
->X_add_number
== 3)
3031 generic_bignum
[3] = 0;
3032 else if (ep
->X_add_number
> 4)
3033 as_bad ("Number larger than 64 bits");
3034 lo32
.X_op
= O_constant
;
3035 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3036 hi32
.X_op
= O_constant
;
3037 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3040 if (hi32
.X_add_number
== 0)
3045 unsigned long hi
, lo
;
3047 if (hi32
.X_add_number
== 0xffffffff)
3049 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3051 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3052 reg
, 0, (int) BFD_RELOC_LO16
);
3055 if (lo32
.X_add_number
& 0x80000000)
3057 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3058 (int) BFD_RELOC_HI16
);
3059 if (lo32
.X_add_number
& 0xffff)
3060 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3061 reg
, reg
, (int) BFD_RELOC_LO16
);
3066 /* Check for 16bit shifted constant. We know that hi32 is
3067 non-zero, so start the mask on the first bit of the hi32
3072 unsigned long himask
, lomask
;
3076 himask
= 0xffff >> (32 - shift
);
3077 lomask
= (0xffff << shift
) & 0xffffffff;
3081 himask
= 0xffff << (shift
- 32);
3084 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3085 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3089 tmp
.X_op
= O_constant
;
3091 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3092 | (lo32
.X_add_number
>> shift
));
3094 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3095 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3096 (int) BFD_RELOC_LO16
);
3097 macro_build ((char *) NULL
, counter
, NULL
,
3098 (shift
>= 32) ? "dsll32" : "dsll",
3100 (shift
>= 32) ? shift
- 32 : shift
);
3104 } while (shift
<= (64 - 16));
3106 /* Find the bit number of the lowest one bit, and store the
3107 shifted value in hi/lo. */
3108 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3109 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3113 while ((lo
& 1) == 0)
3118 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3124 while ((hi
& 1) == 0)
3133 /* Optimize if the shifted value is a (power of 2) - 1. */
3134 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3135 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3137 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3142 /* This instruction will set the register to be all
3144 tmp
.X_op
= O_constant
;
3145 tmp
.X_add_number
= (offsetT
) -1;
3146 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3147 reg
, 0, (int) BFD_RELOC_LO16
);
3151 macro_build ((char *) NULL
, counter
, NULL
,
3152 (bit
>= 32) ? "dsll32" : "dsll",
3154 (bit
>= 32) ? bit
- 32 : bit
);
3156 macro_build ((char *) NULL
, counter
, NULL
,
3157 (shift
>= 32) ? "dsrl32" : "dsrl",
3159 (shift
>= 32) ? shift
- 32 : shift
);
3164 /* Sign extend hi32 before calling load_register, because we can
3165 generally get better code when we load a sign extended value. */
3166 if ((hi32
.X_add_number
& 0x80000000) != 0)
3167 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3168 load_register (counter
, reg
, &hi32
, 0);
3171 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3175 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3184 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3186 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3187 (int) BFD_RELOC_HI16
);
3188 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3195 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3200 mid16
.X_add_number
>>= 16;
3201 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3202 freg
, (int) BFD_RELOC_LO16
);
3203 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3207 if ((lo32
.X_add_number
& 0xffff) != 0)
3208 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3209 (int) BFD_RELOC_LO16
);
3212 /* Load an address into a register. */
3215 load_address (counter
, reg
, ep
)
3222 if (ep
->X_op
!= O_constant
3223 && ep
->X_op
!= O_symbol
)
3225 as_bad ("expression too complex");
3226 ep
->X_op
= O_constant
;
3229 if (ep
->X_op
== O_constant
)
3231 load_register (counter
, reg
, ep
, 0);
3235 if (mips_pic
== NO_PIC
)
3237 /* If this is a reference to a GP relative symbol, we want
3238 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3240 lui $reg,<sym> (BFD_RELOC_HI16_S)
3241 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3242 If we have an addend, we always use the latter form. */
3243 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3244 || nopic_need_relax (ep
->X_add_symbol
, 1))
3249 macro_build ((char *) NULL
, counter
, ep
,
3250 ((bfd_arch_bits_per_address (stdoutput
) == 32
3251 || mips_opts
.isa
< 3)
3252 ? "addiu" : "daddiu"),
3253 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3254 p
= frag_var (rs_machine_dependent
, 8, 0,
3255 RELAX_ENCODE (4, 8, 0, 4, 0,
3256 mips_opts
.warn_about_macros
),
3257 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3259 macro_build_lui (p
, counter
, ep
, reg
);
3262 macro_build (p
, counter
, ep
,
3263 ((bfd_arch_bits_per_address (stdoutput
) == 32
3264 || mips_opts
.isa
< 3)
3265 ? "addiu" : "daddiu"),
3266 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3268 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3272 /* If this is a reference to an external symbol, we want
3273 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3275 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3277 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3278 If there is a constant, it must be added in after. */
3279 ex
.X_add_number
= ep
->X_add_number
;
3280 ep
->X_add_number
= 0;
3282 macro_build ((char *) NULL
, counter
, ep
,
3283 ((bfd_arch_bits_per_address (stdoutput
) == 32
3284 || mips_opts
.isa
< 3)
3286 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3287 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3288 p
= frag_var (rs_machine_dependent
, 4, 0,
3289 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3290 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3291 macro_build (p
, counter
, ep
,
3292 ((bfd_arch_bits_per_address (stdoutput
) == 32
3293 || mips_opts
.isa
< 3)
3294 ? "addiu" : "daddiu"),
3295 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3296 if (ex
.X_add_number
!= 0)
3298 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3299 as_bad ("PIC code offset overflow (max 16 signed bits)");
3300 ex
.X_op
= O_constant
;
3301 macro_build ((char *) NULL
, counter
, &ex
,
3302 ((bfd_arch_bits_per_address (stdoutput
) == 32
3303 || mips_opts
.isa
< 3)
3304 ? "addiu" : "daddiu"),
3305 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3308 else if (mips_pic
== SVR4_PIC
)
3313 /* This is the large GOT case. If this is a reference to an
3314 external symbol, we want
3315 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3317 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3318 Otherwise, for a reference to a local symbol, we want
3319 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3321 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3322 If there is a constant, it must be added in after. */
3323 ex
.X_add_number
= ep
->X_add_number
;
3324 ep
->X_add_number
= 0;
3325 if (reg_needs_delay (GP
))
3330 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3331 (int) BFD_RELOC_MIPS_GOT_HI16
);
3332 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3333 ((bfd_arch_bits_per_address (stdoutput
) == 32
3334 || mips_opts
.isa
< 3)
3335 ? "addu" : "daddu"),
3336 "d,v,t", reg
, reg
, GP
);
3337 macro_build ((char *) NULL
, counter
, ep
,
3338 ((bfd_arch_bits_per_address (stdoutput
) == 32
3339 || mips_opts
.isa
< 3)
3341 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3342 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3343 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3344 mips_opts
.warn_about_macros
),
3345 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3348 /* We need a nop before loading from $gp. This special
3349 check is required because the lui which starts the main
3350 instruction stream does not refer to $gp, and so will not
3351 insert the nop which may be required. */
3352 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3355 macro_build (p
, counter
, ep
,
3356 ((bfd_arch_bits_per_address (stdoutput
) == 32
3357 || mips_opts
.isa
< 3)
3359 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3361 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3363 macro_build (p
, counter
, ep
,
3364 ((bfd_arch_bits_per_address (stdoutput
) == 32
3365 || mips_opts
.isa
< 3)
3366 ? "addiu" : "daddiu"),
3367 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3368 if (ex
.X_add_number
!= 0)
3370 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3371 as_bad ("PIC code offset overflow (max 16 signed bits)");
3372 ex
.X_op
= O_constant
;
3373 macro_build ((char *) NULL
, counter
, &ex
,
3374 ((bfd_arch_bits_per_address (stdoutput
) == 32
3375 || mips_opts
.isa
< 3)
3376 ? "addiu" : "daddiu"),
3377 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3380 else if (mips_pic
== EMBEDDED_PIC
)
3383 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3385 macro_build ((char *) NULL
, counter
, ep
,
3386 ((bfd_arch_bits_per_address (stdoutput
) == 32
3387 || mips_opts
.isa
< 3)
3388 ? "addiu" : "daddiu"),
3389 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3397 * This routine implements the seemingly endless macro or synthesized
3398 * instructions and addressing modes in the mips assembly language. Many
3399 * of these macros are simple and are similar to each other. These could
3400 * probably be handled by some kind of table or grammer aproach instead of
3401 * this verbose method. Others are not simple macros but are more like
3402 * optimizing code generation.
3403 * One interesting optimization is when several store macros appear
3404 * consecutivly that would load AT with the upper half of the same address.
3405 * The ensuing load upper instructions are ommited. This implies some kind
3406 * of global optimization. We currently only optimize within a single macro.
3407 * For many of the load and store macros if the address is specified as a
3408 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3409 * first load register 'at' with zero and use it as the base register. The
3410 * mips assembler simply uses register $zero. Just one tiny optimization
3415 struct mips_cl_insn
*ip
;
3417 register int treg
, sreg
, dreg
, breg
;
3432 bfd_reloc_code_real_type r
;
3434 int hold_mips_optimize
;
3436 assert (! mips_opts
.mips16
);
3438 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3439 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3440 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3441 mask
= ip
->insn_mo
->mask
;
3443 expr1
.X_op
= O_constant
;
3444 expr1
.X_op_symbol
= NULL
;
3445 expr1
.X_add_symbol
= NULL
;
3446 expr1
.X_add_number
= 1;
3458 mips_emit_delays (true);
3459 ++mips_opts
.noreorder
;
3460 mips_any_noreorder
= 1;
3462 expr1
.X_add_number
= 8;
3463 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3465 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3467 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3468 macro_build ((char *) NULL
, &icnt
, NULL
,
3469 dbl
? "dsub" : "sub",
3470 "d,v,t", dreg
, 0, sreg
);
3472 --mips_opts
.noreorder
;
3493 if (imm_expr
.X_op
== O_constant
3494 && imm_expr
.X_add_number
>= -0x8000
3495 && imm_expr
.X_add_number
< 0x8000)
3497 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3498 (int) BFD_RELOC_LO16
);
3501 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3502 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3521 if (imm_expr
.X_op
== O_constant
3522 && imm_expr
.X_add_number
>= 0
3523 && imm_expr
.X_add_number
< 0x10000)
3525 if (mask
!= M_NOR_I
)
3526 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3527 sreg
, (int) BFD_RELOC_LO16
);
3530 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3531 treg
, sreg
, (int) BFD_RELOC_LO16
);
3532 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3538 load_register (&icnt
, AT
, &imm_expr
, 0);
3539 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3556 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3558 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3562 load_register (&icnt
, AT
, &imm_expr
, 0);
3563 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3571 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3572 likely
? "bgezl" : "bgez",
3578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3579 likely
? "blezl" : "blez",
3583 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3585 likely
? "beql" : "beq",
3592 /* check for > max integer */
3593 maxnum
= 0x7fffffff;
3594 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3601 if (imm_expr
.X_op
== O_constant
3602 && imm_expr
.X_add_number
>= maxnum
3603 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3606 /* result is always false */
3609 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3610 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3614 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3620 if (imm_expr
.X_op
!= O_constant
)
3621 as_bad ("Unsupported large constant");
3622 imm_expr
.X_add_number
++;
3626 if (mask
== M_BGEL_I
)
3628 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3630 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3631 likely
? "bgezl" : "bgez",
3635 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3637 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3638 likely
? "bgtzl" : "bgtz",
3642 maxnum
= 0x7fffffff;
3643 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3650 maxnum
= - maxnum
- 1;
3651 if (imm_expr
.X_op
== O_constant
3652 && imm_expr
.X_add_number
<= maxnum
3653 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3656 /* result is always true */
3657 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3658 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3661 set_at (&icnt
, sreg
, 0);
3662 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3663 likely
? "beql" : "beq",
3674 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3675 likely
? "beql" : "beq",
3679 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3681 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3682 likely
? "beql" : "beq",
3690 || (mips_opts
.isa
< 3
3691 && imm_expr
.X_op
== O_constant
3692 && imm_expr
.X_add_number
== 0xffffffff))
3694 if (imm_expr
.X_op
!= O_constant
)
3695 as_bad ("Unsupported large constant");
3696 imm_expr
.X_add_number
++;
3700 if (mask
== M_BGEUL_I
)
3702 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3704 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3706 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3707 likely
? "bnel" : "bne",
3711 set_at (&icnt
, sreg
, 1);
3712 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3713 likely
? "beql" : "beq",
3722 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3723 likely
? "bgtzl" : "bgtz",
3729 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3730 likely
? "bltzl" : "bltz",
3734 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3735 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3736 likely
? "bnel" : "bne",
3745 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3746 likely
? "bnel" : "bne",
3752 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3754 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3755 likely
? "bnel" : "bne",
3764 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3765 likely
? "blezl" : "blez",
3771 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3772 likely
? "bgezl" : "bgez",
3776 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3777 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3778 likely
? "beql" : "beq",
3785 maxnum
= 0x7fffffff;
3786 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3793 if (imm_expr
.X_op
== O_constant
3794 && imm_expr
.X_add_number
>= maxnum
3795 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3797 if (imm_expr
.X_op
!= O_constant
)
3798 as_bad ("Unsupported large constant");
3799 imm_expr
.X_add_number
++;
3803 if (mask
== M_BLTL_I
)
3805 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3807 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3808 likely
? "bltzl" : "bltz",
3812 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3814 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3815 likely
? "blezl" : "blez",
3819 set_at (&icnt
, sreg
, 0);
3820 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3821 likely
? "bnel" : "bne",
3830 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3831 likely
? "beql" : "beq",
3837 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3839 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3840 likely
? "beql" : "beq",
3848 || (mips_opts
.isa
< 3
3849 && imm_expr
.X_op
== O_constant
3850 && imm_expr
.X_add_number
== 0xffffffff))
3852 if (imm_expr
.X_op
!= O_constant
)
3853 as_bad ("Unsupported large constant");
3854 imm_expr
.X_add_number
++;
3858 if (mask
== M_BLTUL_I
)
3860 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3862 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3864 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3865 likely
? "beql" : "beq",
3869 set_at (&icnt
, sreg
, 1);
3870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3871 likely
? "bnel" : "bne",
3880 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3881 likely
? "bltzl" : "bltz",
3887 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3888 likely
? "bgtzl" : "bgtz",
3892 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3893 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3894 likely
? "bnel" : "bne",
3905 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3906 likely
? "bnel" : "bne",
3910 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3912 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3913 likely
? "bnel" : "bne",
3929 as_warn ("Divide by zero.");
3931 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3933 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3937 mips_emit_delays (true);
3938 ++mips_opts
.noreorder
;
3939 mips_any_noreorder
= 1;
3942 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3943 macro_build ((char *) NULL
, &icnt
, NULL
,
3944 dbl
? "ddiv" : "div",
3945 "z,s,t", sreg
, treg
);
3949 expr1
.X_add_number
= 8;
3950 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3951 macro_build ((char *) NULL
, &icnt
, NULL
,
3952 dbl
? "ddiv" : "div",
3953 "z,s,t", sreg
, treg
);
3954 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3956 expr1
.X_add_number
= -1;
3957 macro_build ((char *) NULL
, &icnt
, &expr1
,
3958 dbl
? "daddiu" : "addiu",
3959 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3960 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3961 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3964 expr1
.X_add_number
= 1;
3965 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3966 (int) BFD_RELOC_LO16
);
3967 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3972 expr1
.X_add_number
= 0x80000000;
3973 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3974 (int) BFD_RELOC_HI16
);
3977 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3980 expr1
.X_add_number
= 8;
3981 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3982 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3983 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3985 --mips_opts
.noreorder
;
3986 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4025 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4027 as_warn ("Divide by zero.");
4029 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4031 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4034 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4036 if (strcmp (s2
, "mflo") == 0)
4037 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4040 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4043 if (imm_expr
.X_op
== O_constant
4044 && imm_expr
.X_add_number
== -1
4045 && s
[strlen (s
) - 1] != 'u')
4047 if (strcmp (s2
, "mflo") == 0)
4050 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4053 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4057 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4061 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4062 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4063 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4082 mips_emit_delays (true);
4083 ++mips_opts
.noreorder
;
4084 mips_any_noreorder
= 1;
4087 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4088 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4092 expr1
.X_add_number
= 8;
4093 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4094 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4095 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4097 --mips_opts
.noreorder
;
4098 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4104 /* Load the address of a symbol into a register. If breg is not
4105 zero, we then add a base register to it. */
4107 /* When generating embedded PIC code, we permit expressions of
4110 where bar is an address in the .text section. These are used
4111 when getting the addresses of functions. We don't permit
4112 X_add_number to be non-zero, because if the symbol is
4113 external the relaxing code needs to know that any addend is
4114 purely the offset to X_op_symbol. */
4115 if (mips_pic
== EMBEDDED_PIC
4116 && offset_expr
.X_op
== O_subtract
4117 && now_seg
== text_section
4118 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4119 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4120 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4121 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4122 ->sy_value
.X_add_symbol
)
4125 && offset_expr
.X_add_number
== 0)
4127 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4128 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4129 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4130 ((bfd_arch_bits_per_address (stdoutput
) == 32
4131 || mips_opts
.isa
< 3)
4132 ? "addiu" : "daddiu"),
4133 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4137 if (offset_expr
.X_op
!= O_symbol
4138 && offset_expr
.X_op
!= O_constant
)
4140 as_bad ("expression too complex");
4141 offset_expr
.X_op
= O_constant
;
4155 if (offset_expr
.X_op
== O_constant
)
4156 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4157 else if (mips_pic
== NO_PIC
)
4159 /* If this is a reference to an GP relative symbol, we want
4160 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4162 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4163 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4164 If we have a constant, we need two instructions anyhow,
4165 so we may as well always use the latter form. */
4166 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4167 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4172 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4173 ((bfd_arch_bits_per_address (stdoutput
) == 32
4174 || mips_opts
.isa
< 3)
4175 ? "addiu" : "daddiu"),
4176 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4177 p
= frag_var (rs_machine_dependent
, 8, 0,
4178 RELAX_ENCODE (4, 8, 0, 4, 0,
4179 mips_opts
.warn_about_macros
),
4180 offset_expr
.X_add_symbol
, (offsetT
) 0,
4183 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4186 macro_build (p
, &icnt
, &offset_expr
,
4187 ((bfd_arch_bits_per_address (stdoutput
) == 32
4188 || mips_opts
.isa
< 3)
4189 ? "addiu" : "daddiu"),
4190 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4192 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4194 /* If this is a reference to an external symbol, and there
4195 is no constant, we want
4196 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4197 For a local symbol, we want
4198 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4200 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4202 If we have a small constant, and this is a reference to
4203 an external symbol, we want
4204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4206 addiu $tempreg,$tempreg,<constant>
4207 For a local symbol, we want the same instruction
4208 sequence, but we output a BFD_RELOC_LO16 reloc on the
4211 If we have a large constant, and this is a reference to
4212 an external symbol, we want
4213 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4214 lui $at,<hiconstant>
4215 addiu $at,$at,<loconstant>
4216 addu $tempreg,$tempreg,$at
4217 For a local symbol, we want the same instruction
4218 sequence, but we output a BFD_RELOC_LO16 reloc on the
4219 addiu instruction. */
4220 expr1
.X_add_number
= offset_expr
.X_add_number
;
4221 offset_expr
.X_add_number
= 0;
4223 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4225 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4226 if (expr1
.X_add_number
== 0)
4234 /* We're going to put in an addu instruction using
4235 tempreg, so we may as well insert the nop right
4237 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4241 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4242 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4244 ? mips_opts
.warn_about_macros
4246 offset_expr
.X_add_symbol
, (offsetT
) 0,
4250 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4253 macro_build (p
, &icnt
, &expr1
,
4254 ((bfd_arch_bits_per_address (stdoutput
) == 32
4255 || mips_opts
.isa
< 3)
4256 ? "addiu" : "daddiu"),
4257 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4258 /* FIXME: If breg == 0, and the next instruction uses
4259 $tempreg, then if this variant case is used an extra
4260 nop will be generated. */
4262 else if (expr1
.X_add_number
>= -0x8000
4263 && expr1
.X_add_number
< 0x8000)
4265 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4267 macro_build ((char *) NULL
, &icnt
, &expr1
,
4268 ((bfd_arch_bits_per_address (stdoutput
) == 32
4269 || mips_opts
.isa
< 3)
4270 ? "addiu" : "daddiu"),
4271 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4272 (void) frag_var (rs_machine_dependent
, 0, 0,
4273 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4274 offset_expr
.X_add_symbol
, (offsetT
) 0,
4281 /* If we are going to add in a base register, and the
4282 target register and the base register are the same,
4283 then we are using AT as a temporary register. Since
4284 we want to load the constant into AT, we add our
4285 current AT (from the global offset table) and the
4286 register into the register now, and pretend we were
4287 not using a base register. */
4292 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4294 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4295 ((bfd_arch_bits_per_address (stdoutput
) == 32
4296 || mips_opts
.isa
< 3)
4297 ? "addu" : "daddu"),
4298 "d,v,t", treg
, AT
, breg
);
4304 /* Set mips_optimize around the lui instruction to avoid
4305 inserting an unnecessary nop after the lw. */
4306 hold_mips_optimize
= mips_optimize
;
4308 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4309 mips_optimize
= hold_mips_optimize
;
4311 macro_build ((char *) NULL
, &icnt
, &expr1
,
4312 ((bfd_arch_bits_per_address (stdoutput
) == 32
4313 || mips_opts
.isa
< 3)
4314 ? "addiu" : "daddiu"),
4315 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4317 ((bfd_arch_bits_per_address (stdoutput
) == 32
4318 || mips_opts
.isa
< 3)
4319 ? "addu" : "daddu"),
4320 "d,v,t", tempreg
, tempreg
, AT
);
4321 (void) frag_var (rs_machine_dependent
, 0, 0,
4322 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4323 offset_expr
.X_add_symbol
, (offsetT
) 0,
4328 else if (mips_pic
== SVR4_PIC
)
4332 /* This is the large GOT case. If this is a reference to an
4333 external symbol, and there is no constant, we want
4334 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4335 addu $tempreg,$tempreg,$gp
4336 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4337 For a local symbol, we want
4338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4340 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4342 If we have a small constant, and this is a reference to
4343 an external symbol, we want
4344 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4345 addu $tempreg,$tempreg,$gp
4346 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4348 addiu $tempreg,$tempreg,<constant>
4349 For a local symbol, we want
4350 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4352 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4354 If we have a large constant, and this is a reference to
4355 an external symbol, we want
4356 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4357 addu $tempreg,$tempreg,$gp
4358 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4359 lui $at,<hiconstant>
4360 addiu $at,$at,<loconstant>
4361 addu $tempreg,$tempreg,$at
4362 For a local symbol, we want
4363 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4364 lui $at,<hiconstant>
4365 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4366 addu $tempreg,$tempreg,$at
4368 expr1
.X_add_number
= offset_expr
.X_add_number
;
4369 offset_expr
.X_add_number
= 0;
4371 if (reg_needs_delay (GP
))
4375 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4376 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4377 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4378 ((bfd_arch_bits_per_address (stdoutput
) == 32
4379 || mips_opts
.isa
< 3)
4380 ? "addu" : "daddu"),
4381 "d,v,t", tempreg
, tempreg
, GP
);
4382 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4384 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4386 if (expr1
.X_add_number
== 0)
4394 /* We're going to put in an addu instruction using
4395 tempreg, so we may as well insert the nop right
4397 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4402 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4403 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4406 ? mips_opts
.warn_about_macros
4408 offset_expr
.X_add_symbol
, (offsetT
) 0,
4411 else if (expr1
.X_add_number
>= -0x8000
4412 && expr1
.X_add_number
< 0x8000)
4414 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4416 macro_build ((char *) NULL
, &icnt
, &expr1
,
4417 ((bfd_arch_bits_per_address (stdoutput
) == 32
4418 || mips_opts
.isa
< 3)
4419 ? "addiu" : "daddiu"),
4420 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4422 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4423 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4425 ? mips_opts
.warn_about_macros
4427 offset_expr
.X_add_symbol
, (offsetT
) 0,
4434 /* If we are going to add in a base register, and the
4435 target register and the base register are the same,
4436 then we are using AT as a temporary register. Since
4437 we want to load the constant into AT, we add our
4438 current AT (from the global offset table) and the
4439 register into the register now, and pretend we were
4440 not using a base register. */
4448 assert (tempreg
== AT
);
4449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4451 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4452 ((bfd_arch_bits_per_address (stdoutput
) == 32
4453 || mips_opts
.isa
< 3)
4454 ? "addu" : "daddu"),
4455 "d,v,t", treg
, AT
, breg
);
4460 /* Set mips_optimize around the lui instruction to avoid
4461 inserting an unnecessary nop after the lw. */
4462 hold_mips_optimize
= mips_optimize
;
4464 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4465 mips_optimize
= hold_mips_optimize
;
4467 macro_build ((char *) NULL
, &icnt
, &expr1
,
4468 ((bfd_arch_bits_per_address (stdoutput
) == 32
4469 || mips_opts
.isa
< 3)
4470 ? "addiu" : "daddiu"),
4471 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4472 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4473 ((bfd_arch_bits_per_address (stdoutput
) == 32
4474 || mips_opts
.isa
< 3)
4475 ? "addu" : "daddu"),
4476 "d,v,t", dreg
, dreg
, AT
);
4478 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4479 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4482 ? mips_opts
.warn_about_macros
4484 offset_expr
.X_add_symbol
, (offsetT
) 0,
4492 /* This is needed because this instruction uses $gp, but
4493 the first instruction on the main stream does not. */
4494 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4497 macro_build (p
, &icnt
, &offset_expr
,
4499 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4501 if (expr1
.X_add_number
>= -0x8000
4502 && expr1
.X_add_number
< 0x8000)
4504 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4506 macro_build (p
, &icnt
, &expr1
,
4507 ((bfd_arch_bits_per_address (stdoutput
) == 32
4508 || mips_opts
.isa
< 3)
4509 ? "addiu" : "daddiu"),
4510 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4511 /* FIXME: If add_number is 0, and there was no base
4512 register, the external symbol case ended with a load,
4513 so if the symbol turns out to not be external, and
4514 the next instruction uses tempreg, an unnecessary nop
4515 will be inserted. */
4521 /* We must add in the base register now, as in the
4522 external symbol case. */
4523 assert (tempreg
== AT
);
4524 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4526 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4527 ((bfd_arch_bits_per_address (stdoutput
) == 32
4528 || mips_opts
.isa
< 3)
4529 ? "addu" : "daddu"),
4530 "d,v,t", treg
, AT
, breg
);
4533 /* We set breg to 0 because we have arranged to add
4534 it in in both cases. */
4538 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4540 macro_build (p
, &icnt
, &expr1
,
4541 ((bfd_arch_bits_per_address (stdoutput
) == 32
4542 || mips_opts
.isa
< 3)
4543 ? "addiu" : "daddiu"),
4544 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4546 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4547 ((bfd_arch_bits_per_address (stdoutput
) == 32
4548 || mips_opts
.isa
< 3)
4549 ? "addu" : "daddu"),
4550 "d,v,t", tempreg
, tempreg
, AT
);
4554 else if (mips_pic
== EMBEDDED_PIC
)
4557 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4559 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4560 ((bfd_arch_bits_per_address (stdoutput
) == 32
4561 || mips_opts
.isa
< 3)
4562 ? "addiu" : "daddiu"),
4563 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4569 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4570 ((bfd_arch_bits_per_address (stdoutput
) == 32
4571 || mips_opts
.isa
< 3)
4572 ? "addu" : "daddu"),
4573 "d,v,t", treg
, tempreg
, breg
);
4581 /* The j instruction may not be used in PIC code, since it
4582 requires an absolute address. We convert it to a b
4584 if (mips_pic
== NO_PIC
)
4585 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4587 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4590 /* The jal instructions must be handled as macros because when
4591 generating PIC code they expand to multi-instruction
4592 sequences. Normally they are simple instructions. */
4597 if (mips_pic
== NO_PIC
4598 || mips_pic
== EMBEDDED_PIC
)
4599 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4601 else if (mips_pic
== SVR4_PIC
)
4603 if (sreg
!= PIC_CALL_REG
)
4604 as_warn ("MIPS PIC call to register other than $25");
4606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4608 if (mips_cprestore_offset
< 0)
4609 as_warn ("No .cprestore pseudo-op used in PIC code");
4612 expr1
.X_add_number
= mips_cprestore_offset
;
4613 macro_build ((char *) NULL
, &icnt
, &expr1
,
4614 ((bfd_arch_bits_per_address (stdoutput
) == 32
4615 || mips_opts
.isa
< 3)
4617 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4626 if (mips_pic
== NO_PIC
)
4627 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4628 else if (mips_pic
== SVR4_PIC
)
4630 /* If this is a reference to an external symbol, and we are
4631 using a small GOT, we want
4632 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4636 lw $gp,cprestore($sp)
4637 The cprestore value is set using the .cprestore
4638 pseudo-op. If we are using a big GOT, we want
4639 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4641 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4645 lw $gp,cprestore($sp)
4646 If the symbol is not external, we want
4647 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4649 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4652 lw $gp,cprestore($sp) */
4656 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4657 ((bfd_arch_bits_per_address (stdoutput
) == 32
4658 || mips_opts
.isa
< 3)
4660 "t,o(b)", PIC_CALL_REG
,
4661 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4664 p
= frag_var (rs_machine_dependent
, 4, 0,
4665 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4666 offset_expr
.X_add_symbol
, (offsetT
) 0,
4673 if (reg_needs_delay (GP
))
4677 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4678 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4679 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4680 ((bfd_arch_bits_per_address (stdoutput
) == 32
4681 || mips_opts
.isa
< 3)
4682 ? "addu" : "daddu"),
4683 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4684 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4685 ((bfd_arch_bits_per_address (stdoutput
) == 32
4686 || mips_opts
.isa
< 3)
4688 "t,o(b)", PIC_CALL_REG
,
4689 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4690 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4692 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4693 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4695 offset_expr
.X_add_symbol
, (offsetT
) 0,
4699 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4702 macro_build (p
, &icnt
, &offset_expr
,
4703 ((bfd_arch_bits_per_address (stdoutput
) == 32
4704 || mips_opts
.isa
< 3)
4706 "t,o(b)", PIC_CALL_REG
,
4707 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4709 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4712 macro_build (p
, &icnt
, &offset_expr
,
4713 ((bfd_arch_bits_per_address (stdoutput
) == 32
4714 || mips_opts
.isa
< 3)
4715 ? "addiu" : "daddiu"),
4716 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4717 (int) BFD_RELOC_LO16
);
4718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4719 "jalr", "s", PIC_CALL_REG
);
4720 if (mips_cprestore_offset
< 0)
4721 as_warn ("No .cprestore pseudo-op used in PIC code");
4724 if (mips_opts
.noreorder
)
4725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4727 expr1
.X_add_number
= mips_cprestore_offset
;
4728 macro_build ((char *) NULL
, &icnt
, &expr1
,
4729 ((bfd_arch_bits_per_address (stdoutput
) == 32
4730 || mips_opts
.isa
< 3)
4732 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4736 else if (mips_pic
== EMBEDDED_PIC
)
4738 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4739 /* The linker may expand the call to a longer sequence which
4740 uses $at, so we must break rather than return. */
4765 /* Itbl support may require additional care here. */
4770 /* Itbl support may require additional care here. */
4775 /* Itbl support may require additional care here. */
4780 /* Itbl support may require additional care here. */
4794 as_bad ("opcode not supported on this processor");
4798 /* Itbl support may require additional care here. */
4803 /* Itbl support may require additional care here. */
4808 /* Itbl support may require additional care here. */
4828 if (breg
== treg
|| coproc
|| lr
)
4850 /* Itbl support may require additional care here. */
4855 /* Itbl support may require additional care here. */
4860 /* Itbl support may require additional care here. */
4865 /* Itbl support may require additional care here. */
4883 as_bad ("opcode not supported on this processor");
4888 /* Itbl support may require additional care here. */
4892 /* Itbl support may require additional care here. */
4897 /* Itbl support may require additional care here. */
4909 /* Itbl support may require additional care here. */
4910 if (mask
== M_LWC1_AB
4911 || mask
== M_SWC1_AB
4912 || mask
== M_LDC1_AB
4913 || mask
== M_SDC1_AB
4922 if (offset_expr
.X_op
!= O_constant
4923 && offset_expr
.X_op
!= O_symbol
)
4925 as_bad ("expression too complex");
4926 offset_expr
.X_op
= O_constant
;
4929 /* A constant expression in PIC code can be handled just as it
4930 is in non PIC code. */
4931 if (mips_pic
== NO_PIC
4932 || offset_expr
.X_op
== O_constant
)
4934 /* If this is a reference to a GP relative symbol, and there
4935 is no base register, we want
4936 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4937 Otherwise, if there is no base register, we want
4938 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4939 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4940 If we have a constant, we need two instructions anyhow,
4941 so we always use the latter form.
4943 If we have a base register, and this is a reference to a
4944 GP relative symbol, we want
4945 addu $tempreg,$breg,$gp
4946 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4948 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4949 addu $tempreg,$tempreg,$breg
4950 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4951 With a constant we always use the latter case. */
4954 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4955 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4960 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4961 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4962 p
= frag_var (rs_machine_dependent
, 8, 0,
4963 RELAX_ENCODE (4, 8, 0, 4, 0,
4964 (mips_opts
.warn_about_macros
4966 && mips_opts
.noat
))),
4967 offset_expr
.X_add_symbol
, (offsetT
) 0,
4971 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4974 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4975 (int) BFD_RELOC_LO16
, tempreg
);
4979 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4980 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4985 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4986 ((bfd_arch_bits_per_address (stdoutput
) == 32
4987 || mips_opts
.isa
< 3)
4988 ? "addu" : "daddu"),
4989 "d,v,t", tempreg
, breg
, GP
);
4990 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4991 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4992 p
= frag_var (rs_machine_dependent
, 12, 0,
4993 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4994 offset_expr
.X_add_symbol
, (offsetT
) 0,
4997 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5000 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5001 ((bfd_arch_bits_per_address (stdoutput
) == 32
5002 || mips_opts
.isa
< 3)
5003 ? "addu" : "daddu"),
5004 "d,v,t", tempreg
, tempreg
, breg
);
5007 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5008 (int) BFD_RELOC_LO16
, tempreg
);
5011 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5013 /* If this is a reference to an external symbol, we want
5014 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5016 <op> $treg,0($tempreg)
5018 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5020 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5021 <op> $treg,0($tempreg)
5022 If there is a base register, we add it to $tempreg before
5023 the <op>. If there is a constant, we stick it in the
5024 <op> instruction. We don't handle constants larger than
5025 16 bits, because we have no way to load the upper 16 bits
5026 (actually, we could handle them for the subset of cases
5027 in which we are not using $at). */
5028 assert (offset_expr
.X_op
== O_symbol
);
5029 expr1
.X_add_number
= offset_expr
.X_add_number
;
5030 offset_expr
.X_add_number
= 0;
5031 if (expr1
.X_add_number
< -0x8000
5032 || expr1
.X_add_number
>= 0x8000)
5033 as_bad ("PIC code offset overflow (max 16 signed bits)");
5035 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5036 ((bfd_arch_bits_per_address (stdoutput
) == 32
5037 || mips_opts
.isa
< 3)
5039 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5040 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5041 p
= frag_var (rs_machine_dependent
, 4, 0,
5042 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5043 offset_expr
.X_add_symbol
, (offsetT
) 0,
5045 macro_build (p
, &icnt
, &offset_expr
,
5046 ((bfd_arch_bits_per_address (stdoutput
) == 32
5047 || mips_opts
.isa
< 3)
5048 ? "addiu" : "daddiu"),
5049 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5051 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5052 ((bfd_arch_bits_per_address (stdoutput
) == 32
5053 || mips_opts
.isa
< 3)
5054 ? "addu" : "daddu"),
5055 "d,v,t", tempreg
, tempreg
, breg
);
5056 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5057 (int) BFD_RELOC_LO16
, tempreg
);
5059 else if (mips_pic
== SVR4_PIC
)
5063 /* If this is a reference to an external symbol, we want
5064 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5065 addu $tempreg,$tempreg,$gp
5066 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5067 <op> $treg,0($tempreg)
5069 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5071 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5072 <op> $treg,0($tempreg)
5073 If there is a base register, we add it to $tempreg before
5074 the <op>. If there is a constant, we stick it in the
5075 <op> instruction. We don't handle constants larger than
5076 16 bits, because we have no way to load the upper 16 bits
5077 (actually, we could handle them for the subset of cases
5078 in which we are not using $at). */
5079 assert (offset_expr
.X_op
== O_symbol
);
5080 expr1
.X_add_number
= offset_expr
.X_add_number
;
5081 offset_expr
.X_add_number
= 0;
5082 if (expr1
.X_add_number
< -0x8000
5083 || expr1
.X_add_number
>= 0x8000)
5084 as_bad ("PIC code offset overflow (max 16 signed bits)");
5085 if (reg_needs_delay (GP
))
5090 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5091 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5092 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5093 ((bfd_arch_bits_per_address (stdoutput
) == 32
5094 || mips_opts
.isa
< 3)
5095 ? "addu" : "daddu"),
5096 "d,v,t", tempreg
, tempreg
, GP
);
5097 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5098 ((bfd_arch_bits_per_address (stdoutput
) == 32
5099 || mips_opts
.isa
< 3)
5101 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5103 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5104 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5105 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5108 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5111 macro_build (p
, &icnt
, &offset_expr
,
5112 ((bfd_arch_bits_per_address (stdoutput
) == 32
5113 || mips_opts
.isa
< 3)
5115 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5117 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5119 macro_build (p
, &icnt
, &offset_expr
,
5120 ((bfd_arch_bits_per_address (stdoutput
) == 32
5121 || mips_opts
.isa
< 3)
5122 ? "addiu" : "daddiu"),
5123 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5125 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5126 ((bfd_arch_bits_per_address (stdoutput
) == 32
5127 || mips_opts
.isa
< 3)
5128 ? "addu" : "daddu"),
5129 "d,v,t", tempreg
, tempreg
, breg
);
5130 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5131 (int) BFD_RELOC_LO16
, tempreg
);
5133 else if (mips_pic
== EMBEDDED_PIC
)
5135 /* If there is no base register, we want
5136 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5137 If there is a base register, we want
5138 addu $tempreg,$breg,$gp
5139 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5141 assert (offset_expr
.X_op
== O_symbol
);
5144 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5145 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5150 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5151 ((bfd_arch_bits_per_address (stdoutput
) == 32
5152 || mips_opts
.isa
< 3)
5153 ? "addu" : "daddu"),
5154 "d,v,t", tempreg
, breg
, GP
);
5155 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5156 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5169 load_register (&icnt
, treg
, &imm_expr
, 0);
5173 load_register (&icnt
, treg
, &imm_expr
, 1);
5177 if (imm_expr
.X_op
== O_constant
)
5179 load_register (&icnt
, AT
, &imm_expr
, 0);
5180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5181 "mtc1", "t,G", AT
, treg
);
5186 assert (offset_expr
.X_op
== O_symbol
5187 && strcmp (segment_name (S_GET_SEGMENT
5188 (offset_expr
.X_add_symbol
)),
5190 && offset_expr
.X_add_number
== 0);
5191 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5192 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5197 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5198 the entire value, and in mips1 mode it is the high order 32
5199 bits of the value and the low order 32 bits are either zero
5200 or in offset_expr. */
5201 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5203 if (mips_opts
.isa
>= 3)
5204 load_register (&icnt
, treg
, &imm_expr
, 1);
5209 if (target_big_endian
)
5221 load_register (&icnt
, hreg
, &imm_expr
, 0);
5224 if (offset_expr
.X_op
== O_absent
)
5225 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5229 assert (offset_expr
.X_op
== O_constant
);
5230 load_register (&icnt
, lreg
, &offset_expr
, 0);
5237 /* We know that sym is in the .rdata section. First we get the
5238 upper 16 bits of the address. */
5239 if (mips_pic
== NO_PIC
)
5241 /* FIXME: This won't work for a 64 bit address. */
5242 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5244 else if (mips_pic
== SVR4_PIC
)
5246 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5247 ((bfd_arch_bits_per_address (stdoutput
) == 32
5248 || mips_opts
.isa
< 3)
5250 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5252 else if (mips_pic
== EMBEDDED_PIC
)
5254 /* For embedded PIC we pick up the entire address off $gp in
5255 a single instruction. */
5256 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5257 ((bfd_arch_bits_per_address (stdoutput
) == 32
5258 || mips_opts
.isa
< 3)
5259 ? "addiu" : "daddiu"),
5260 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5261 offset_expr
.X_op
= O_constant
;
5262 offset_expr
.X_add_number
= 0;
5267 /* Now we load the register(s). */
5268 if (mips_opts
.isa
>= 3)
5269 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5270 treg
, (int) BFD_RELOC_LO16
, AT
);
5273 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5274 treg
, (int) BFD_RELOC_LO16
, AT
);
5277 /* FIXME: How in the world do we deal with the possible
5279 offset_expr
.X_add_number
+= 4;
5280 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5281 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5285 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5286 does not become a variant frag. */
5287 frag_wane (frag_now
);
5293 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5294 the entire value, and in mips1 mode it is the high order 32
5295 bits of the value and the low order 32 bits are either zero
5296 or in offset_expr. */
5297 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5299 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5300 if (mips_opts
.isa
>= 3)
5301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5302 "dmtc1", "t,S", AT
, treg
);
5305 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5306 "mtc1", "t,G", AT
, treg
+ 1);
5307 if (offset_expr
.X_op
== O_absent
)
5308 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5309 "mtc1", "t,G", 0, treg
);
5312 assert (offset_expr
.X_op
== O_constant
);
5313 load_register (&icnt
, AT
, &offset_expr
, 0);
5314 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5315 "mtc1", "t,G", AT
, treg
);
5321 assert (offset_expr
.X_op
== O_symbol
5322 && offset_expr
.X_add_number
== 0);
5323 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5324 if (strcmp (s
, ".lit8") == 0)
5326 if (mips_opts
.isa
>= 2)
5328 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5329 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5333 r
= BFD_RELOC_MIPS_LITERAL
;
5338 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5339 if (mips_pic
== SVR4_PIC
)
5340 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5341 ((bfd_arch_bits_per_address (stdoutput
) == 32
5342 || mips_opts
.isa
< 3)
5344 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5347 /* FIXME: This won't work for a 64 bit address. */
5348 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5351 if (mips_opts
.isa
>= 2)
5353 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5354 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5356 /* To avoid confusion in tc_gen_reloc, we must ensure
5357 that this does not become a variant frag. */
5358 frag_wane (frag_now
);
5371 as_bad ("opcode not supported on this processor");
5374 /* Even on a big endian machine $fn comes before $fn+1. We have
5375 to adjust when loading from memory. */
5378 assert (mips_opts
.isa
< 2);
5379 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5380 target_big_endian
? treg
+ 1 : treg
,
5382 /* FIXME: A possible overflow which I don't know how to deal
5384 offset_expr
.X_add_number
+= 4;
5385 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5386 target_big_endian
? treg
: treg
+ 1,
5389 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5390 does not become a variant frag. */
5391 frag_wane (frag_now
);
5400 * The MIPS assembler seems to check for X_add_number not
5401 * being double aligned and generating:
5404 * addiu at,at,%lo(foo+1)
5407 * But, the resulting address is the same after relocation so why
5408 * generate the extra instruction?
5412 as_bad ("opcode not supported on this processor");
5415 /* Itbl support may require additional care here. */
5417 if (mips_opts
.isa
>= 2)
5430 as_bad ("opcode not supported on this processor");
5434 if (mips_opts
.isa
>= 2)
5442 /* Itbl support may require additional care here. */
5447 if (mips_opts
.isa
>= 3)
5458 if (mips_opts
.isa
>= 3)
5468 if (offset_expr
.X_op
!= O_symbol
5469 && offset_expr
.X_op
!= O_constant
)
5471 as_bad ("expression too complex");
5472 offset_expr
.X_op
= O_constant
;
5475 /* Even on a big endian machine $fn comes before $fn+1. We have
5476 to adjust when loading from memory. We set coproc if we must
5477 load $fn+1 first. */
5478 /* Itbl support may require additional care here. */
5479 if (! target_big_endian
)
5482 if (mips_pic
== NO_PIC
5483 || offset_expr
.X_op
== O_constant
)
5485 /* If this is a reference to a GP relative symbol, we want
5486 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5487 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5488 If we have a base register, we use this
5490 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5491 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5492 If this is not a GP relative symbol, we want
5493 lui $at,<sym> (BFD_RELOC_HI16_S)
5494 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5495 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5496 If there is a base register, we add it to $at after the
5497 lui instruction. If there is a constant, we always use
5499 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5500 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5520 ((bfd_arch_bits_per_address (stdoutput
) == 32
5521 || mips_opts
.isa
< 3)
5522 ? "addu" : "daddu"),
5523 "d,v,t", AT
, breg
, GP
);
5529 /* Itbl support may require additional care here. */
5530 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5531 coproc
? treg
+ 1 : treg
,
5532 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5533 offset_expr
.X_add_number
+= 4;
5535 /* Set mips_optimize to 2 to avoid inserting an
5537 hold_mips_optimize
= mips_optimize
;
5539 /* Itbl support may require additional care here. */
5540 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5541 coproc
? treg
: treg
+ 1,
5542 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5543 mips_optimize
= hold_mips_optimize
;
5545 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5546 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5547 used_at
&& mips_opts
.noat
),
5548 offset_expr
.X_add_symbol
, (offsetT
) 0,
5551 /* We just generated two relocs. When tc_gen_reloc
5552 handles this case, it will skip the first reloc and
5553 handle the second. The second reloc already has an
5554 extra addend of 4, which we added above. We must
5555 subtract it out, and then subtract another 4 to make
5556 the first reloc come out right. The second reloc
5557 will come out right because we are going to add 4 to
5558 offset_expr when we build its instruction below.
5560 If we have a symbol, then we don't want to include
5561 the offset, because it will wind up being included
5562 when we generate the reloc. */
5564 if (offset_expr
.X_op
== O_constant
)
5565 offset_expr
.X_add_number
-= 8;
5568 offset_expr
.X_add_number
= -4;
5569 offset_expr
.X_op
= O_constant
;
5572 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5577 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5578 ((bfd_arch_bits_per_address (stdoutput
) == 32
5579 || mips_opts
.isa
< 3)
5580 ? "addu" : "daddu"),
5581 "d,v,t", AT
, breg
, AT
);
5585 /* Itbl support may require additional care here. */
5586 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5587 coproc
? treg
+ 1 : treg
,
5588 (int) BFD_RELOC_LO16
, AT
);
5591 /* FIXME: How do we handle overflow here? */
5592 offset_expr
.X_add_number
+= 4;
5593 /* Itbl support may require additional care here. */
5594 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5595 coproc
? treg
: treg
+ 1,
5596 (int) BFD_RELOC_LO16
, AT
);
5598 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5602 /* If this is a reference to an external symbol, we want
5603 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5608 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5610 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5611 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5612 If there is a base register we add it to $at before the
5613 lwc1 instructions. If there is a constant we include it
5614 in the lwc1 instructions. */
5616 expr1
.X_add_number
= offset_expr
.X_add_number
;
5617 offset_expr
.X_add_number
= 0;
5618 if (expr1
.X_add_number
< -0x8000
5619 || expr1
.X_add_number
>= 0x8000 - 4)
5620 as_bad ("PIC code offset overflow (max 16 signed bits)");
5625 frag_grow (24 + off
);
5626 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5627 ((bfd_arch_bits_per_address (stdoutput
) == 32
5628 || mips_opts
.isa
< 3)
5630 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5631 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5634 ((bfd_arch_bits_per_address (stdoutput
) == 32
5635 || mips_opts
.isa
< 3)
5636 ? "addu" : "daddu"),
5637 "d,v,t", AT
, breg
, AT
);
5638 /* Itbl support may require additional care here. */
5639 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5640 coproc
? treg
+ 1 : treg
,
5641 (int) BFD_RELOC_LO16
, AT
);
5642 expr1
.X_add_number
+= 4;
5644 /* Set mips_optimize to 2 to avoid inserting an undesired
5646 hold_mips_optimize
= mips_optimize
;
5648 /* Itbl support may require additional care here. */
5649 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5650 coproc
? treg
: treg
+ 1,
5651 (int) BFD_RELOC_LO16
, AT
);
5652 mips_optimize
= hold_mips_optimize
;
5654 (void) frag_var (rs_machine_dependent
, 0, 0,
5655 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5656 offset_expr
.X_add_symbol
, (offsetT
) 0,
5659 else if (mips_pic
== SVR4_PIC
)
5663 /* If this is a reference to an external symbol, we want
5664 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5666 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5671 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5673 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5674 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5675 If there is a base register we add it to $at before the
5676 lwc1 instructions. If there is a constant we include it
5677 in the lwc1 instructions. */
5679 expr1
.X_add_number
= offset_expr
.X_add_number
;
5680 offset_expr
.X_add_number
= 0;
5681 if (expr1
.X_add_number
< -0x8000
5682 || expr1
.X_add_number
>= 0x8000 - 4)
5683 as_bad ("PIC code offset overflow (max 16 signed bits)");
5684 if (reg_needs_delay (GP
))
5693 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5694 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5695 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5696 ((bfd_arch_bits_per_address (stdoutput
) == 32
5697 || mips_opts
.isa
< 3)
5698 ? "addu" : "daddu"),
5699 "d,v,t", AT
, AT
, GP
);
5700 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5701 ((bfd_arch_bits_per_address (stdoutput
) == 32
5702 || mips_opts
.isa
< 3)
5704 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5705 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5708 ((bfd_arch_bits_per_address (stdoutput
) == 32
5709 || mips_opts
.isa
< 3)
5710 ? "addu" : "daddu"),
5711 "d,v,t", AT
, breg
, AT
);
5712 /* Itbl support may require additional care here. */
5713 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5714 coproc
? treg
+ 1 : treg
,
5715 (int) BFD_RELOC_LO16
, AT
);
5716 expr1
.X_add_number
+= 4;
5718 /* Set mips_optimize to 2 to avoid inserting an undesired
5720 hold_mips_optimize
= mips_optimize
;
5722 /* Itbl support may require additional care here. */
5723 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5724 coproc
? treg
: treg
+ 1,
5725 (int) BFD_RELOC_LO16
, AT
);
5726 mips_optimize
= hold_mips_optimize
;
5727 expr1
.X_add_number
-= 4;
5729 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5730 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5731 8 + gpdel
+ off
, 1, 0),
5732 offset_expr
.X_add_symbol
, (offsetT
) 0,
5736 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5739 macro_build (p
, &icnt
, &offset_expr
,
5740 ((bfd_arch_bits_per_address (stdoutput
) == 32
5741 || mips_opts
.isa
< 3)
5743 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5745 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5749 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5750 ((bfd_arch_bits_per_address (stdoutput
) == 32
5751 || mips_opts
.isa
< 3)
5752 ? "addu" : "daddu"),
5753 "d,v,t", AT
, breg
, AT
);
5756 /* Itbl support may require additional care here. */
5757 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5758 coproc
? treg
+ 1 : treg
,
5759 (int) BFD_RELOC_LO16
, AT
);
5761 expr1
.X_add_number
+= 4;
5763 /* Set mips_optimize to 2 to avoid inserting an undesired
5765 hold_mips_optimize
= mips_optimize
;
5767 /* Itbl support may require additional care here. */
5768 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5769 coproc
? treg
: treg
+ 1,
5770 (int) BFD_RELOC_LO16
, AT
);
5771 mips_optimize
= hold_mips_optimize
;
5773 else if (mips_pic
== EMBEDDED_PIC
)
5775 /* If there is no base register, we use
5776 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5777 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5778 If we have a base register, we use
5780 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5781 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5790 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5791 ((bfd_arch_bits_per_address (stdoutput
) == 32
5792 || mips_opts
.isa
< 3)
5793 ? "addu" : "daddu"),
5794 "d,v,t", AT
, breg
, GP
);
5799 /* Itbl support may require additional care here. */
5800 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5801 coproc
? treg
+ 1 : treg
,
5802 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5803 offset_expr
.X_add_number
+= 4;
5804 /* Itbl support may require additional care here. */
5805 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5806 coproc
? treg
: treg
+ 1,
5807 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5823 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
5824 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5825 (int) BFD_RELOC_LO16
, breg
);
5826 offset_expr
.X_add_number
+= 4;
5827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5828 (int) BFD_RELOC_LO16
, breg
);
5831 /* New code added to support COPZ instructions.
5832 This code builds table entries out of the macros in mip_opcodes.
5833 R4000 uses interlocks to handle coproc delays.
5834 Other chips (like the R3000) require nops to be inserted for delays.
5836 FIXME: Currently, we require that the user handle delays.
5837 In order to fill delay slots for non-interlocked chips,
5838 we must have a way to specify delays based on the coprocessor.
5839 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5840 What are the side-effects of the cop instruction?
5841 What cache support might we have and what are its effects?
5842 Both coprocessor & memory require delays. how long???
5843 What registers are read/set/modified?
5845 If an itbl is provided to interpret cop instructions,
5846 this knowledge can be encoded in the itbl spec. */
5860 /* For now we just do C (same as Cz). The parameter will be
5861 stored in insn_opcode by mips_ip. */
5862 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5866 #ifdef LOSING_COMPILER
5868 /* Try and see if this is a new itbl instruction.
5869 This code builds table entries out of the macros in mip_opcodes.
5870 FIXME: For now we just assemble the expression and pass it's
5871 value along as a 32-bit immediate.
5872 We may want to have the assembler assemble this value,
5873 so that we gain the assembler's knowledge of delay slots,
5875 Would it be more efficient to use mask (id) here? */
5876 if (itbl_have_entries
5877 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5879 s
= ip
->insn_mo
->name
;
5881 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5882 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5889 as_warn ("Macro used $at after \".set noat\"");
5894 struct mips_cl_insn
*ip
;
5896 register int treg
, sreg
, dreg
, breg
;
5911 bfd_reloc_code_real_type r
;
5914 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5915 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5916 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5917 mask
= ip
->insn_mo
->mask
;
5919 expr1
.X_op
= O_constant
;
5920 expr1
.X_op_symbol
= NULL
;
5921 expr1
.X_add_symbol
= NULL
;
5922 expr1
.X_add_number
= 1;
5926 #endif /* LOSING_COMPILER */
5931 macro_build ((char *) NULL
, &icnt
, NULL
,
5932 dbl
? "dmultu" : "multu",
5934 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5940 /* The MIPS assembler some times generates shifts and adds. I'm
5941 not trying to be that fancy. GCC should do this for us
5943 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5944 macro_build ((char *) NULL
, &icnt
, NULL
,
5945 dbl
? "dmult" : "mult",
5947 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5953 mips_emit_delays (true);
5954 ++mips_opts
.noreorder
;
5955 mips_any_noreorder
= 1;
5956 macro_build ((char *) NULL
, &icnt
, NULL
,
5957 dbl
? "dmult" : "mult",
5959 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5960 macro_build ((char *) NULL
, &icnt
, NULL
,
5961 dbl
? "dsra32" : "sra",
5962 "d,w,<", dreg
, dreg
, 31);
5963 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5965 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5968 expr1
.X_add_number
= 8;
5969 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5970 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5971 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5973 --mips_opts
.noreorder
;
5974 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5980 mips_emit_delays (true);
5981 ++mips_opts
.noreorder
;
5982 mips_any_noreorder
= 1;
5983 macro_build ((char *) NULL
, &icnt
, NULL
,
5984 dbl
? "dmultu" : "multu",
5986 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5987 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5989 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5992 expr1
.X_add_number
= 8;
5993 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5994 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5995 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5997 --mips_opts
.noreorder
;
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6002 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6003 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6005 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6009 if (imm_expr
.X_op
!= O_constant
)
6010 as_bad ("rotate count too large");
6011 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6012 (int) (imm_expr
.X_add_number
& 0x1f));
6013 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6014 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6015 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6019 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6021 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6023 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6027 if (imm_expr
.X_op
!= O_constant
)
6028 as_bad ("rotate count too large");
6029 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6030 (int) (imm_expr
.X_add_number
& 0x1f));
6031 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6032 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6033 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6039 as_bad ("opcode not supported on this processor");
6042 assert (mips_opts
.isa
< 2);
6043 /* Even on a big endian machine $fn comes before $fn+1. We have
6044 to adjust when storing to memory. */
6045 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6046 target_big_endian
? treg
+ 1 : treg
,
6047 (int) BFD_RELOC_LO16
, breg
);
6048 offset_expr
.X_add_number
+= 4;
6049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6050 target_big_endian
? treg
: treg
+ 1,
6051 (int) BFD_RELOC_LO16
, breg
);
6056 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6057 treg
, (int) BFD_RELOC_LO16
);
6059 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6060 sreg
, (int) BFD_RELOC_LO16
);
6063 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6065 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6066 dreg
, (int) BFD_RELOC_LO16
);
6071 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6073 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6074 sreg
, (int) BFD_RELOC_LO16
);
6079 as_warn ("Instruction %s: result is always false",
6081 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6084 if (imm_expr
.X_op
== O_constant
6085 && imm_expr
.X_add_number
>= 0
6086 && imm_expr
.X_add_number
< 0x10000)
6088 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6089 sreg
, (int) BFD_RELOC_LO16
);
6092 else if (imm_expr
.X_op
== O_constant
6093 && imm_expr
.X_add_number
> -0x8000
6094 && imm_expr
.X_add_number
< 0)
6096 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6097 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6098 ((bfd_arch_bits_per_address (stdoutput
) == 32
6099 || mips_opts
.isa
< 3)
6100 ? "addiu" : "daddiu"),
6101 "t,r,j", dreg
, sreg
,
6102 (int) BFD_RELOC_LO16
);
6107 load_register (&icnt
, AT
, &imm_expr
, 0);
6108 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6112 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6113 (int) BFD_RELOC_LO16
);
6118 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6124 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6125 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6126 (int) BFD_RELOC_LO16
);
6129 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6131 if (imm_expr
.X_op
== O_constant
6132 && imm_expr
.X_add_number
>= -0x8000
6133 && imm_expr
.X_add_number
< 0x8000)
6135 macro_build ((char *) NULL
, &icnt
, &expr1
,
6136 mask
== M_SGE_I
? "slti" : "sltiu",
6137 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6142 load_register (&icnt
, AT
, &imm_expr
, 0);
6143 macro_build ((char *) NULL
, &icnt
, NULL
,
6144 mask
== M_SGE_I
? "slt" : "sltu",
6145 "d,v,t", dreg
, sreg
, AT
);
6148 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6149 (int) BFD_RELOC_LO16
);
6154 case M_SGT
: /* sreg > treg <==> treg < sreg */
6160 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6163 case M_SGT_I
: /* sreg > I <==> I < sreg */
6169 load_register (&icnt
, AT
, &imm_expr
, 0);
6170 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6173 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6179 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6180 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6181 (int) BFD_RELOC_LO16
);
6184 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6190 load_register (&icnt
, AT
, &imm_expr
, 0);
6191 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6192 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6193 (int) BFD_RELOC_LO16
);
6197 if (imm_expr
.X_op
== O_constant
6198 && imm_expr
.X_add_number
>= -0x8000
6199 && imm_expr
.X_add_number
< 0x8000)
6201 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6202 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6205 load_register (&icnt
, AT
, &imm_expr
, 0);
6206 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6210 if (imm_expr
.X_op
== O_constant
6211 && imm_expr
.X_add_number
>= -0x8000
6212 && imm_expr
.X_add_number
< 0x8000)
6214 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6215 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6218 load_register (&icnt
, AT
, &imm_expr
, 0);
6219 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6225 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6228 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6232 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6234 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6240 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6242 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6248 as_warn ("Instruction %s: result is always true",
6250 macro_build ((char *) NULL
, &icnt
, &expr1
,
6251 ((bfd_arch_bits_per_address (stdoutput
) == 32
6252 || mips_opts
.isa
< 3)
6253 ? "addiu" : "daddiu"),
6254 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6257 if (imm_expr
.X_op
== O_constant
6258 && imm_expr
.X_add_number
>= 0
6259 && imm_expr
.X_add_number
< 0x10000)
6261 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6262 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6265 else if (imm_expr
.X_op
== O_constant
6266 && imm_expr
.X_add_number
> -0x8000
6267 && imm_expr
.X_add_number
< 0)
6269 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6270 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6271 ((bfd_arch_bits_per_address (stdoutput
) == 32
6272 || mips_opts
.isa
< 3)
6273 ? "addiu" : "daddiu"),
6274 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6279 load_register (&icnt
, AT
, &imm_expr
, 0);
6280 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6284 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6292 if (imm_expr
.X_op
== O_constant
6293 && imm_expr
.X_add_number
> -0x8000
6294 && imm_expr
.X_add_number
<= 0x8000)
6296 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6297 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6298 dbl
? "daddi" : "addi",
6299 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6302 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6303 macro_build ((char *) NULL
, &icnt
, NULL
,
6304 dbl
? "dsub" : "sub",
6305 "d,v,t", dreg
, sreg
, AT
);
6311 if (imm_expr
.X_op
== O_constant
6312 && imm_expr
.X_add_number
> -0x8000
6313 && imm_expr
.X_add_number
<= 0x8000)
6315 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6316 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6317 dbl
? "daddiu" : "addiu",
6318 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6321 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6322 macro_build ((char *) NULL
, &icnt
, NULL
,
6323 dbl
? "dsubu" : "subu",
6324 "d,v,t", dreg
, sreg
, AT
);
6345 load_register (&icnt
, AT
, &imm_expr
, 0);
6346 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6351 assert (mips_opts
.isa
< 2);
6352 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6353 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6356 * Is the double cfc1 instruction a bug in the mips assembler;
6357 * or is there a reason for it?
6359 mips_emit_delays (true);
6360 ++mips_opts
.noreorder
;
6361 mips_any_noreorder
= 1;
6362 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6363 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6364 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6365 expr1
.X_add_number
= 3;
6366 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6367 (int) BFD_RELOC_LO16
);
6368 expr1
.X_add_number
= 2;
6369 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6370 (int) BFD_RELOC_LO16
);
6371 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6372 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6373 macro_build ((char *) NULL
, &icnt
, NULL
,
6374 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6375 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6376 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6377 --mips_opts
.noreorder
;
6386 if (offset_expr
.X_add_number
>= 0x7fff)
6387 as_bad ("operand overflow");
6388 /* avoid load delay */
6389 if (! target_big_endian
)
6390 offset_expr
.X_add_number
+= 1;
6391 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6392 (int) BFD_RELOC_LO16
, breg
);
6393 if (! target_big_endian
)
6394 offset_expr
.X_add_number
-= 1;
6396 offset_expr
.X_add_number
+= 1;
6397 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6398 (int) BFD_RELOC_LO16
, breg
);
6399 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6400 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6413 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6414 as_bad ("operand overflow");
6415 if (! target_big_endian
)
6416 offset_expr
.X_add_number
+= off
;
6417 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6418 (int) BFD_RELOC_LO16
, breg
);
6419 if (! target_big_endian
)
6420 offset_expr
.X_add_number
-= off
;
6422 offset_expr
.X_add_number
+= off
;
6423 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6424 (int) BFD_RELOC_LO16
, breg
);
6437 load_address (&icnt
, AT
, &offset_expr
);
6439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6440 ((bfd_arch_bits_per_address (stdoutput
) == 32
6441 || mips_opts
.isa
< 3)
6442 ? "addu" : "daddu"),
6443 "d,v,t", AT
, AT
, breg
);
6444 if (! target_big_endian
)
6445 expr1
.X_add_number
= off
;
6447 expr1
.X_add_number
= 0;
6448 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6449 (int) BFD_RELOC_LO16
, AT
);
6450 if (! target_big_endian
)
6451 expr1
.X_add_number
= 0;
6453 expr1
.X_add_number
= off
;
6454 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6455 (int) BFD_RELOC_LO16
, AT
);
6460 load_address (&icnt
, AT
, &offset_expr
);
6462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6463 ((bfd_arch_bits_per_address (stdoutput
) == 32
6464 || mips_opts
.isa
< 3)
6465 ? "addu" : "daddu"),
6466 "d,v,t", AT
, AT
, breg
);
6467 if (target_big_endian
)
6468 expr1
.X_add_number
= 0;
6469 macro_build ((char *) NULL
, &icnt
, &expr1
,
6470 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6471 (int) BFD_RELOC_LO16
, AT
);
6472 if (target_big_endian
)
6473 expr1
.X_add_number
= 1;
6475 expr1
.X_add_number
= 0;
6476 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6477 (int) BFD_RELOC_LO16
, AT
);
6478 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6480 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6485 if (offset_expr
.X_add_number
>= 0x7fff)
6486 as_bad ("operand overflow");
6487 if (target_big_endian
)
6488 offset_expr
.X_add_number
+= 1;
6489 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6490 (int) BFD_RELOC_LO16
, breg
);
6491 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6492 if (target_big_endian
)
6493 offset_expr
.X_add_number
-= 1;
6495 offset_expr
.X_add_number
+= 1;
6496 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6497 (int) BFD_RELOC_LO16
, breg
);
6510 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6511 as_bad ("operand overflow");
6512 if (! target_big_endian
)
6513 offset_expr
.X_add_number
+= off
;
6514 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6515 (int) BFD_RELOC_LO16
, breg
);
6516 if (! target_big_endian
)
6517 offset_expr
.X_add_number
-= off
;
6519 offset_expr
.X_add_number
+= off
;
6520 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6521 (int) BFD_RELOC_LO16
, breg
);
6534 load_address (&icnt
, AT
, &offset_expr
);
6536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6537 ((bfd_arch_bits_per_address (stdoutput
) == 32
6538 || mips_opts
.isa
< 3)
6539 ? "addu" : "daddu"),
6540 "d,v,t", AT
, AT
, breg
);
6541 if (! target_big_endian
)
6542 expr1
.X_add_number
= off
;
6544 expr1
.X_add_number
= 0;
6545 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6546 (int) BFD_RELOC_LO16
, AT
);
6547 if (! target_big_endian
)
6548 expr1
.X_add_number
= 0;
6550 expr1
.X_add_number
= off
;
6551 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6552 (int) BFD_RELOC_LO16
, AT
);
6556 load_address (&icnt
, AT
, &offset_expr
);
6558 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6559 ((bfd_arch_bits_per_address (stdoutput
) == 32
6560 || mips_opts
.isa
< 3)
6561 ? "addu" : "daddu"),
6562 "d,v,t", AT
, AT
, breg
);
6563 if (! target_big_endian
)
6564 expr1
.X_add_number
= 0;
6565 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6566 (int) BFD_RELOC_LO16
, AT
);
6567 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6569 if (! target_big_endian
)
6570 expr1
.X_add_number
= 1;
6572 expr1
.X_add_number
= 0;
6573 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6574 (int) BFD_RELOC_LO16
, AT
);
6575 if (! target_big_endian
)
6576 expr1
.X_add_number
= 0;
6578 expr1
.X_add_number
= 1;
6579 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6580 (int) BFD_RELOC_LO16
, AT
);
6581 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6583 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6588 /* FIXME: Check if this is one of the itbl macros, since they
6589 are added dynamically. */
6590 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6594 as_warn ("Macro used $at after \".set noat\"");
6597 /* Implement macros in mips16 mode. */
6601 struct mips_cl_insn
*ip
;
6604 int xreg
, yreg
, zreg
, tmp
;
6608 const char *s
, *s2
, *s3
;
6610 mask
= ip
->insn_mo
->mask
;
6612 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6613 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6614 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6618 expr1
.X_op
= O_constant
;
6619 expr1
.X_op_symbol
= NULL
;
6620 expr1
.X_add_symbol
= NULL
;
6621 expr1
.X_add_number
= 1;
6640 mips_emit_delays (true);
6641 ++mips_opts
.noreorder
;
6642 mips_any_noreorder
= 1;
6643 macro_build ((char *) NULL
, &icnt
, NULL
,
6644 dbl
? "ddiv" : "div",
6645 "0,x,y", xreg
, yreg
);
6646 expr1
.X_add_number
= 2;
6647 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6648 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6649 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6650 since that causes an overflow. We should do that as well,
6651 but I don't see how to do the comparisons without a temporary
6653 --mips_opts
.noreorder
;
6654 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6673 mips_emit_delays (true);
6674 ++mips_opts
.noreorder
;
6675 mips_any_noreorder
= 1;
6676 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6677 expr1
.X_add_number
= 2;
6678 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6679 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6680 --mips_opts
.noreorder
;
6681 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6687 macro_build ((char *) NULL
, &icnt
, NULL
,
6688 dbl
? "dmultu" : "multu",
6690 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6698 if (imm_expr
.X_op
!= O_constant
)
6699 as_bad ("Unsupported large constant");
6700 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6701 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6702 dbl
? "daddiu" : "addiu",
6703 "y,x,4", yreg
, xreg
);
6707 if (imm_expr
.X_op
!= O_constant
)
6708 as_bad ("Unsupported large constant");
6709 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6710 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6715 if (imm_expr
.X_op
!= O_constant
)
6716 as_bad ("Unsupported large constant");
6717 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6718 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6741 goto do_reverse_branch
;
6745 goto do_reverse_branch
;
6757 goto do_reverse_branch
;
6768 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6770 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6797 goto do_addone_branch_i
;
6802 goto do_addone_branch_i
;
6817 goto do_addone_branch_i
;
6824 if (imm_expr
.X_op
!= O_constant
)
6825 as_bad ("Unsupported large constant");
6826 ++imm_expr
.X_add_number
;
6829 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6830 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6834 expr1
.X_add_number
= 0;
6835 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6838 "move", "y,X", xreg
, yreg
);
6839 expr1
.X_add_number
= 2;
6840 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6842 "neg", "x,w", xreg
, xreg
);
6846 /* For consistency checking, verify that all bits are specified either
6847 by the match/mask part of the instruction definition, or by the
6850 validate_mips_insn (opc
)
6851 const struct mips_opcode
*opc
;
6853 const char *p
= opc
->args
;
6855 unsigned long used_bits
= opc
->mask
;
6857 if ((used_bits
& opc
->match
) != opc
->match
)
6859 as_bad ("internal: bad mips opcode (mask error): %s %s",
6860 opc
->name
, opc
->args
);
6863 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6870 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6871 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6873 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6874 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6875 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6876 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6878 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6881 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6882 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6883 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6884 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6885 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6886 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6887 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6888 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6889 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6890 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6891 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6893 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6894 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6895 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6896 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6898 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6899 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6900 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6901 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6902 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6903 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6904 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6905 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6908 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6909 /* start-sanitize-vr5400 */
6910 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
6911 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
6914 /* end-sanitize-vr5400 */
6916 as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s",
6917 c
, opc
->name
, opc
->args
);
6921 /* Some of the trapping instructions (break, t*, sdbbp) have "code"
6922 fields that cannot currently be set by assembly code. Ignore them
6924 if (opc
->pinfo
& INSN_TRAP
)
6926 static const char *const trap_insns
[] = {
6928 "teq", "tge", "tgeu", "tlt", "tltu", "tne",
6931 for (i
= sizeof(trap_insns
)/sizeof(trap_insns
[0]) - 1; i
>= 0; i
--)
6932 if (!strcmp (trap_insns
[i
], opc
->name
))
6934 used_bits
|= 0xffc0;
6938 if (used_bits
!= 0xffffffff)
6940 as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s",
6941 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6947 /* This routine assembles an instruction into its binary format. As a
6948 side effect, it sets one of the global variables imm_reloc or
6949 offset_reloc to the type of relocation to do if one of the operands
6950 is an address expression. */
6955 struct mips_cl_insn
*ip
;
6960 struct mips_opcode
*insn
;
6963 unsigned int lastregno
= 0;
6969 /* If the instruction contains a '.', we first try to match an instruction
6970 including the '.'. Then we try again without the '.'. */
6972 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6975 /* If we stopped on whitespace, then replace the whitespace with null for
6976 the call to hash_find. Save the character we replaced just in case we
6977 have to re-parse the instruction. */
6984 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
6986 /* If we didn't find the instruction in the opcode table, try again, but
6987 this time with just the instruction up to, but not including the
6991 /* Restore the character we overwrite above (if any). */
6995 /* Scan up to the first '.' or whitespace. */
6996 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace (*s
); ++s
)
6999 /* If we did not find a '.', then we can quit now. */
7002 insn_error
= "unrecognized opcode";
7006 /* Lookup the instruction in the hash table. */
7008 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7010 insn_error
= "unrecognized opcode";
7021 assert (strcmp (insn
->name
, str
) == 0);
7023 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7025 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7027 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7029 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7034 if (insn_isa
<= mips_opts
.isa
)
7036 else if (insn
->pinfo
== INSN_MACRO
)
7038 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
7039 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
7040 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
7041 /* start-sanitize-vr4320 */
7042 || (mips_4320
&& (insn
->membership
& INSN_4320
) != 0)
7043 /* end-sanitize-vr4320 */
7044 /* start-sanitize-tx49 */
7045 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
7046 /* end-sanitize-tx49 */
7047 /* start-sanitize-r5900 */
7048 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
7049 /* end-sanitize-r5900 */
7050 /* start-sanitize-vr5400 */
7051 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
7052 /* end-sanitize-vr5400 */
7053 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
7058 if (insn
->pinfo
!= INSN_MACRO
)
7060 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
7062 /* start-sanitize-r5900 */
7063 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
7065 /* end-sanitize-r5900 */
7070 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7071 && strcmp (insn
->name
, insn
[1].name
) == 0)
7077 || insn_isa
<= mips_opts
.isa
)
7078 insn_error
= "opcode not supported on this processor";
7081 static char buf
[100];
7083 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
7090 ip
->insn_opcode
= insn
->match
;
7091 for (args
= insn
->args
;; ++args
)
7097 case '\0': /* end of args */
7110 ip
->insn_opcode
|= lastregno
<< 21;
7115 ip
->insn_opcode
|= lastregno
<< 16;
7119 ip
->insn_opcode
|= lastregno
<< 11;
7125 /* Handle optional base register.
7126 Either the base register is omitted or
7127 we must have a left paren. */
7128 /* This is dependent on the next operand specifier
7129 is a base register specification. */
7130 assert (args
[1] == 'b' || args
[1] == '5'
7131 || args
[1] == '-' || args
[1] == '4');
7135 case ')': /* these must match exactly */
7136 /* start-sanitize-vr5400 */
7139 /* end-sanitize-vr5400 */
7140 /* start-sanitize-r5900 */
7143 /* end-sanitize-r5900 */
7148 case '<': /* must be at least one digit */
7150 * According to the manual, if the shift amount is greater
7151 * than 31 or less than 0 the the shift amount should be
7152 * mod 32. In reality the mips assembler issues an error.
7153 * We issue a warning and mask out all but the low 5 bits.
7155 my_getExpression (&imm_expr
, s
);
7156 check_absolute_expr (ip
, &imm_expr
);
7157 if ((unsigned long) imm_expr
.X_add_number
> 31)
7159 as_warn ("Improper shift amount (%ld)",
7160 (long) imm_expr
.X_add_number
);
7161 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7163 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7164 imm_expr
.X_op
= O_absent
;
7168 case '>': /* shift amount minus 32 */
7169 my_getExpression (&imm_expr
, s
);
7170 check_absolute_expr (ip
, &imm_expr
);
7171 if ((unsigned long) imm_expr
.X_add_number
< 32
7172 || (unsigned long) imm_expr
.X_add_number
> 63)
7174 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7175 imm_expr
.X_op
= O_absent
;
7179 /* start-sanitize-r5900 */
7180 case '0': /* 5 bit signed immediate at 6 */
7181 my_getExpression (&imm_expr
, s
);
7182 check_absolute_expr (ip
, &imm_expr
);
7183 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7184 || ((imm_expr
.X_add_number
< -16
7185 || imm_expr
.X_add_number
>= 16)
7186 && imm_expr
.X_op
== O_constant
))
7188 if (imm_expr
.X_op
!= O_constant
7189 && imm_expr
.X_op
!= O_big
)
7190 insn_error
= "absolute expression required";
7192 as_bad ("5 bit expression not in range -16..15");
7194 ip
->insn_opcode
|= (imm_expr
.X_add_number
) << 6;
7195 imm_expr
.X_op
= O_absent
;
7199 case '9': /* vi19 for vcallmsr */
7200 if (strncmp (s
, "vi19", 4) == 0)
7203 as_bad ("expected vi19");
7206 case '#': /* escape character */
7207 /* '#' specifies that we've got an optional suffix to this
7208 operand that must match exactly (if it exists). */
7209 if (*s
!= '\0' && *s
!= ','
7210 && *s
!= ' ' && *s
!= '\t' && *s
!= '\n')
7212 if (*s
== *(args
+ 1))
7223 case 'K': /* DEST operand completer (optional), must
7224 match previous dest if specified. */
7225 case '&': /* DEST instruction completer */
7232 /* Parse the completer. */
7234 while (*s
!= '\0' && *s
!= ' ' && *s
!= ',')
7246 insn_error
= "Invalid dest specification";
7252 /* Each completer can only appear once. */
7253 if (w
> 1 || x
> 1 || y
> 1 || z
> 1)
7255 insn_error
= "Invalid dest specification";
7259 /* If this is the opcode completer, then we must insert
7260 the appropriate value into the insn. */
7263 ip
->insn_opcode
|= ((w
<< 21) | (x
<< 24)
7264 | (y
<< 23) | (z
<< 22));
7265 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7271 /* This is the operand completer, make sure it matches
7272 the previous opcode completer. */
7273 temp
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7274 if (temp
&& temp
!= last_h
)
7276 insn_error
= "DEST field in operand does not match DEST field in instruction";
7285 case 'J': /* vu0 I register */
7289 insn_error
= "operand `I' expected";
7292 case 'Q': /* vu0 Q register */
7296 insn_error
= "operand `Q' expected";
7299 case 'X': /* vu0 R register */
7303 insn_error
= "operand `R' expected";
7306 case 'U': /* vu0 ACC register */
7307 if (s
[0] == 'A' && s
[1] == 'C' && s
[2] == 'C')
7310 insn_error
= "operand `ACC' expected";
7312 /* end-sanitize-r5900 */
7314 case 'k': /* cache code */
7315 case 'h': /* prefx code */
7316 my_getExpression (&imm_expr
, s
);
7317 check_absolute_expr (ip
, &imm_expr
);
7318 if ((unsigned long) imm_expr
.X_add_number
> 31)
7320 as_warn ("Invalid value for `%s' (%lu)",
7322 (unsigned long) imm_expr
.X_add_number
);
7323 imm_expr
.X_add_number
&= 0x1f;
7326 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7328 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7329 imm_expr
.X_op
= O_absent
;
7333 case 'c': /* break code */
7334 my_getExpression (&imm_expr
, s
);
7335 check_absolute_expr (ip
, &imm_expr
);
7336 if ((unsigned) imm_expr
.X_add_number
> 1023)
7337 as_warn ("Illegal break code (%ld)",
7338 (long) imm_expr
.X_add_number
);
7339 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7340 imm_expr
.X_op
= O_absent
;
7344 case 'B': /* syscall code */
7345 my_getExpression (&imm_expr
, s
);
7346 check_absolute_expr (ip
, &imm_expr
);
7347 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7348 as_warn ("Illegal syscall code (%ld)",
7349 (long) imm_expr
.X_add_number
);
7350 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7351 imm_expr
.X_op
= O_absent
;
7355 case 'C': /* Coprocessor code */
7356 my_getExpression (&imm_expr
, s
);
7357 check_absolute_expr (ip
, &imm_expr
);
7358 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7360 as_warn ("Coproccesor code > 25 bits (%ld)",
7361 (long) imm_expr
.X_add_number
);
7362 imm_expr
.X_add_number
&= ((1<<25) - 1);
7364 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7365 imm_expr
.X_op
= O_absent
;
7369 case 'P': /* Performance register */
7370 my_getExpression (&imm_expr
, s
);
7371 check_absolute_expr (ip
, &imm_expr
);
7372 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7374 as_warn ("Invalidate performance regster (%ld)",
7375 (long) imm_expr
.X_add_number
);
7376 imm_expr
.X_add_number
&= 1;
7378 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7379 imm_expr
.X_op
= O_absent
;
7383 case 'b': /* base register */
7384 case 'd': /* destination register */
7385 case 's': /* source register */
7386 case 't': /* target register */
7387 case 'r': /* both target and source */
7388 case 'v': /* both dest and source */
7389 case 'w': /* both dest and target */
7390 case 'E': /* coprocessor target register */
7391 case 'G': /* coprocessor destination register */
7392 case 'x': /* ignore register name */
7393 case 'z': /* must be zero register */
7407 while (isdigit (*s
));
7409 as_bad ("Invalid register number (%d)", regno
);
7411 else if (*args
== 'E' || *args
== 'G')
7415 if (s
[1] == 'f' && s
[2] == 'p')
7420 else if (s
[1] == 's' && s
[2] == 'p')
7425 else if (s
[1] == 'g' && s
[2] == 'p')
7430 else if (s
[1] == 'a' && s
[2] == 't')
7435 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7440 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7445 else if (itbl_have_entries
)
7450 p
= s
+1; /* advance past '$' */
7451 n
= itbl_get_field (&p
); /* n is name */
7453 /* See if this is a register defined in an
7455 r
= itbl_get_reg_val (n
);
7458 /* Get_field advances to the start of
7459 the next field, so we need to back
7460 rack to the end of the last field. */
7464 s
= strchr (s
,'\0');
7477 as_warn ("Used $at without \".set noat\"");
7483 if (c
== 'r' || c
== 'v' || c
== 'w')
7490 /* 'z' only matches $0. */
7491 if (c
== 'z' && regno
!= 0)
7494 /* Now that we have assembled one operand, we use the args string
7495 * to figure out where it goes in the instruction. */
7502 ip
->insn_opcode
|= regno
<< 21;
7506 ip
->insn_opcode
|= regno
<< 11;
7511 ip
->insn_opcode
|= regno
<< 16;
7514 /* This case exists because on the r3000 trunc
7515 expands into a macro which requires a gp
7516 register. On the r6000 or r4000 it is
7517 assembled into a single instruction which
7518 ignores the register. Thus the insn version
7519 is MIPS_ISA2 and uses 'x', and the macro
7520 version is MIPS_ISA1 and uses 't'. */
7523 /* This case is for the div instruction, which
7524 acts differently if the destination argument
7525 is $0. This only matches $0, and is checked
7526 outside the switch. */
7529 /* Itbl operand; not yet implemented. FIXME ?? */
7531 /* What about all other operands like 'i', which
7532 can be specified in the opcode table? */
7542 ip
->insn_opcode
|= lastregno
<< 21;
7545 ip
->insn_opcode
|= lastregno
<< 16;
7550 case 'D': /* floating point destination register */
7551 case 'S': /* floating point source register */
7552 case 'T': /* floating point target register */
7553 case 'R': /* floating point source register */
7556 /* start-sanitize-r5900 */
7557 case '1': /* vu0 fp reg position 1 */
7558 case '2': /* vu0 fp reg position 2 */
7559 case '3': /* vu0 fp reg position 3 */
7560 case '4': /* vu0 int reg position 1 */
7561 case '5': /* vu0 int reg position 2 */
7562 case '6': /* vu0 int reg position 3 */
7563 case '7': /* vu0 fp reg with ftf modifier */
7564 case '8': /* vu0 fp reg with fsf modifier */
7565 /* end-sanitize-r5900 */
7567 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7577 while (isdigit (*s
));
7580 as_bad ("Invalid float register number (%d)", regno
);
7582 if ((regno
& 1) != 0
7583 && mips_opts
.isa
< 3
7584 && ! (strcmp (str
, "mtc1") == 0
7585 || strcmp (str
, "mfc1") == 0
7586 || strcmp (str
, "lwc1") == 0
7587 || strcmp (str
, "swc1") == 0
7588 || strcmp (str
, "l.s") == 0
7589 || strcmp (str
, "s.s") == 0))
7590 as_warn ("Float register should be even, was %d",
7598 if (c
== 'V' || c
== 'W')
7608 ip
->insn_opcode
|= regno
<< 6;
7612 ip
->insn_opcode
|= regno
<< 11;
7616 ip
->insn_opcode
|= regno
<< 16;
7619 ip
->insn_opcode
|= regno
<< 21;
7626 /* start-sanitize-r5900 */
7627 /* Handle vf and vi regsiters for vu0. */
7629 && (s
[1] == 'f' || s
[1] == 'i')
7640 while (isdigit (*s
));
7643 as_bad ("Invalid vu0 register number (%d)", regno
);
7647 if (c
== '7' || c
== '8')
7656 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7661 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7666 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7671 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7674 as_bad ("Invalid FSF/FTF specification");
7682 if (c
== 'V' || c
== 'W')
7694 ip
->insn_opcode
|= regno
<< 16;
7699 ip
->insn_opcode
|= regno
<< 11;
7703 ip
->insn_opcode
|= regno
<< 6;
7709 /* end-sanitize-r5900 */
7714 ip
->insn_opcode
|= lastregno
<< 11;
7717 ip
->insn_opcode
|= lastregno
<< 16;
7723 my_getExpression (&imm_expr
, s
);
7724 if (imm_expr
.X_op
!= O_big
7725 && imm_expr
.X_op
!= O_constant
)
7726 insn_error
= "absolute expression required";
7731 my_getExpression (&offset_expr
, s
);
7732 imm_reloc
= BFD_RELOC_32
;
7744 unsigned char temp
[8];
7746 unsigned int length
;
7751 /* These only appear as the last operand in an
7752 instruction, and every instruction that accepts
7753 them in any variant accepts them in all variants.
7754 This means we don't have to worry about backing out
7755 any changes if the instruction does not match.
7757 The difference between them is the size of the
7758 floating point constant and where it goes. For 'F'
7759 and 'L' the constant is 64 bits; for 'f' and 'l' it
7760 is 32 bits. Where the constant is placed is based
7761 on how the MIPS assembler does things:
7764 f -- immediate value
7767 The .lit4 and .lit8 sections are only used if
7768 permitted by the -G argument.
7770 When generating embedded PIC code, we use the
7771 .lit8 section but not the .lit4 section (we can do
7772 .lit4 inline easily; we need to put .lit8
7773 somewhere in the data segment, and using .lit8
7774 permits the linker to eventually combine identical
7777 f64
= *args
== 'F' || *args
== 'L';
7779 save_in
= input_line_pointer
;
7780 input_line_pointer
= s
;
7781 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7783 s
= input_line_pointer
;
7784 input_line_pointer
= save_in
;
7785 if (err
!= NULL
&& *err
!= '\0')
7787 as_bad ("Bad floating point constant: %s", err
);
7788 memset (temp
, '\0', sizeof temp
);
7789 length
= f64
? 8 : 4;
7792 assert (length
== (f64
? 8 : 4));
7796 && (! USE_GLOBAL_POINTER_OPT
7797 || mips_pic
== EMBEDDED_PIC
7798 || g_switch_value
< 4
7799 || (temp
[0] == 0 && temp
[1] == 0)
7800 || (temp
[2] == 0 && temp
[3] == 0))))
7802 imm_expr
.X_op
= O_constant
;
7803 if (! target_big_endian
)
7804 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7806 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7809 && ((temp
[0] == 0 && temp
[1] == 0)
7810 || (temp
[2] == 0 && temp
[3] == 0))
7811 && ((temp
[4] == 0 && temp
[5] == 0)
7812 || (temp
[6] == 0 && temp
[7] == 0)))
7814 /* The value is simple enough to load with a
7815 couple of instructions. In mips1 mode, set
7816 imm_expr to the high order 32 bits and
7817 offset_expr to the low order 32 bits.
7818 Otherwise, set imm_expr to the entire 64 bit
7820 if (mips_opts
.isa
< 3)
7822 imm_expr
.X_op
= O_constant
;
7823 offset_expr
.X_op
= O_constant
;
7824 if (! target_big_endian
)
7826 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7827 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7831 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7832 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7834 if (offset_expr
.X_add_number
== 0)
7835 offset_expr
.X_op
= O_absent
;
7837 else if (sizeof (imm_expr
.X_add_number
) > 4)
7839 imm_expr
.X_op
= O_constant
;
7840 if (! target_big_endian
)
7841 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7843 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7847 imm_expr
.X_op
= O_big
;
7848 imm_expr
.X_add_number
= 4;
7849 if (! target_big_endian
)
7851 generic_bignum
[0] = bfd_getl16 (temp
);
7852 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7853 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7854 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7858 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7859 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7860 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7861 generic_bignum
[3] = bfd_getb16 (temp
);
7867 const char *newname
;
7870 /* Switch to the right section. */
7872 subseg
= now_subseg
;
7875 default: /* unused default case avoids warnings. */
7877 newname
= RDATA_SECTION_NAME
;
7878 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7882 newname
= RDATA_SECTION_NAME
;
7885 assert (!USE_GLOBAL_POINTER_OPT
7886 || g_switch_value
>= 4);
7890 new_seg
= subseg_new (newname
, (subsegT
) 0);
7891 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7892 bfd_set_section_flags (stdoutput
, new_seg
,
7897 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7898 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7899 && strcmp (TARGET_OS
, "elf") != 0)
7900 record_alignment (new_seg
, 4);
7902 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7904 as_bad ("Can't use floating point insn in this section");
7906 /* Set the argument to the current address in the
7908 offset_expr
.X_op
= O_symbol
;
7909 offset_expr
.X_add_symbol
=
7910 symbol_new ("L0\001", now_seg
,
7911 (valueT
) frag_now_fix (), frag_now
);
7912 offset_expr
.X_add_number
= 0;
7914 /* Put the floating point number into the section. */
7915 p
= frag_more ((int) length
);
7916 memcpy (p
, temp
, length
);
7918 /* Switch back to the original section. */
7919 subseg_set (seg
, subseg
);
7924 case 'i': /* 16 bit unsigned immediate */
7925 case 'j': /* 16 bit signed immediate */
7926 imm_reloc
= BFD_RELOC_LO16
;
7927 c
= my_getSmallExpression (&imm_expr
, s
);
7932 if (imm_expr
.X_op
== O_constant
)
7933 imm_expr
.X_add_number
=
7934 (imm_expr
.X_add_number
>> 16) & 0xffff;
7937 imm_reloc
= BFD_RELOC_HI16_S
;
7938 imm_unmatched_hi
= true;
7941 imm_reloc
= BFD_RELOC_HI16
;
7946 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7947 || ((imm_expr
.X_add_number
< 0
7948 || imm_expr
.X_add_number
>= 0x10000)
7949 && imm_expr
.X_op
== O_constant
))
7951 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7952 !strcmp (insn
->name
, insn
[1].name
))
7954 if (imm_expr
.X_op
!= O_constant
7955 && imm_expr
.X_op
!= O_big
)
7956 insn_error
= "absolute expression required";
7958 as_bad ("16 bit expression not in range 0..65535");
7966 /* The upper bound should be 0x8000, but
7967 unfortunately the MIPS assembler accepts numbers
7968 from 0x8000 to 0xffff and sign extends them, and
7969 we want to be compatible. We only permit this
7970 extended range for an instruction which does not
7971 provide any further alternates, since those
7972 alternates may handle other cases. People should
7973 use the numbers they mean, rather than relying on
7974 a mysterious sign extension. */
7975 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7976 strcmp (insn
->name
, insn
[1].name
) == 0);
7981 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7982 || ((imm_expr
.X_add_number
< -0x8000
7983 || imm_expr
.X_add_number
>= max
)
7984 && imm_expr
.X_op
== O_constant
)
7986 && imm_expr
.X_add_number
< 0
7987 && mips_opts
.isa
>= 3
7988 && imm_expr
.X_unsigned
7989 && sizeof (imm_expr
.X_add_number
) <= 4))
7993 if (imm_expr
.X_op
!= O_constant
7994 && imm_expr
.X_op
!= O_big
)
7995 insn_error
= "absolute expression required";
7997 as_bad ("16 bit expression not in range -32768..32767");
8003 case 'o': /* 16 bit offset */
8004 c
= my_getSmallExpression (&offset_expr
, s
);
8006 /* If this value won't fit into a 16 bit offset, then go
8007 find a macro that will generate the 32 bit offset
8008 code pattern. As a special hack, we accept the
8009 difference of two local symbols as a constant. This
8010 is required to suppose embedded PIC switches, which
8011 use an instruction which looks like
8012 lw $4,$L12-$LS12($4)
8013 The problem with handling this in a more general
8014 fashion is that the macro function doesn't expect to
8015 see anything which can be handled in a single
8016 constant instruction. */
8018 && (offset_expr
.X_op
!= O_constant
8019 || offset_expr
.X_add_number
>= 0x8000
8020 || offset_expr
.X_add_number
< -0x8000)
8021 && (mips_pic
!= EMBEDDED_PIC
8022 || offset_expr
.X_op
!= O_subtract
8023 || now_seg
!= text_section
8024 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
8028 offset_reloc
= BFD_RELOC_LO16
;
8029 if (c
== 'h' || c
== 'H')
8031 assert (offset_expr
.X_op
== O_constant
);
8032 offset_expr
.X_add_number
=
8033 (offset_expr
.X_add_number
>> 16) & 0xffff;
8038 case 'p': /* pc relative offset */
8039 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8040 my_getExpression (&offset_expr
, s
);
8044 case 'u': /* upper 16 bits */
8045 c
= my_getSmallExpression (&imm_expr
, s
);
8046 if (imm_expr
.X_op
== O_constant
8047 && (imm_expr
.X_add_number
< 0
8048 || imm_expr
.X_add_number
>= 0x10000))
8049 as_bad ("lui expression not in range 0..65535");
8050 imm_reloc
= BFD_RELOC_LO16
;
8055 if (imm_expr
.X_op
== O_constant
)
8056 imm_expr
.X_add_number
=
8057 (imm_expr
.X_add_number
>> 16) & 0xffff;
8060 imm_reloc
= BFD_RELOC_HI16_S
;
8061 imm_unmatched_hi
= true;
8064 imm_reloc
= BFD_RELOC_HI16
;
8070 case 'a': /* 26 bit address */
8071 my_getExpression (&offset_expr
, s
);
8073 offset_reloc
= BFD_RELOC_MIPS_JMP
;
8076 case 'N': /* 3 bit branch condition code */
8077 case 'M': /* 3 bit compare condition code */
8078 if (strncmp (s
, "$fcc", 4) != 0)
8088 while (isdigit (*s
));
8090 as_bad ("invalid condition code register $fcc%d", regno
);
8092 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8094 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8097 /* start-sanitize-vr5400 */
8098 case 'e': /* must be at least one digit */
8099 my_getExpression (&imm_expr
, s
);
8100 check_absolute_expr (ip
, &imm_expr
);
8101 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
8103 as_bad ("bad byte vector index (%ld)",
8104 (long) imm_expr
.X_add_number
);
8105 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8107 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8108 imm_expr
.X_op
= O_absent
;
8113 my_getExpression (&imm_expr
, s
);
8114 check_absolute_expr (ip
, &imm_expr
);
8115 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
8117 as_bad ("bad byte vector index (%ld)",
8118 (long) imm_expr
.X_add_number
);
8119 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8121 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
8122 imm_expr
.X_op
= O_absent
;
8126 /* end-sanitize-vr5400 */
8128 as_bad ("bad char = '%c'\n", *args
);
8133 /* Args don't match. */
8134 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8135 !strcmp (insn
->name
, insn
[1].name
))
8141 insn_error
= "illegal operands";
8146 /* This routine assembles an instruction into its binary format when
8147 assembling for the mips16. As a side effect, it sets one of the
8148 global variables imm_reloc or offset_reloc to the type of
8149 relocation to do if one of the operands is an address expression.
8150 It also sets mips16_small and mips16_ext if the user explicitly
8151 requested a small or extended instruction. */
8156 struct mips_cl_insn
*ip
;
8160 struct mips_opcode
*insn
;
8163 unsigned int lastregno
= 0;
8168 mips16_small
= false;
8171 for (s
= str
; islower (*s
); ++s
)
8183 if (s
[1] == 't' && s
[2] == ' ')
8186 mips16_small
= true;
8190 else if (s
[1] == 'e' && s
[2] == ' ')
8199 insn_error
= "unknown opcode";
8203 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8204 mips16_small
= true;
8206 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8208 insn_error
= "unrecognized opcode";
8215 assert (strcmp (insn
->name
, str
) == 0);
8218 ip
->insn_opcode
= insn
->match
;
8219 ip
->use_extend
= false;
8220 imm_expr
.X_op
= O_absent
;
8221 imm_reloc
= BFD_RELOC_UNUSED
;
8222 offset_expr
.X_op
= O_absent
;
8223 offset_reloc
= BFD_RELOC_UNUSED
;
8224 for (args
= insn
->args
; 1; ++args
)
8231 /* In this switch statement we call break if we did not find
8232 a match, continue if we did find a match, or return if we
8241 /* Stuff the immediate value in now, if we can. */
8242 if (imm_expr
.X_op
== O_constant
8243 && imm_reloc
> BFD_RELOC_UNUSED
8244 && insn
->pinfo
!= INSN_MACRO
)
8246 mips16_immed ((char *) NULL
, 0,
8247 imm_reloc
- BFD_RELOC_UNUSED
,
8248 imm_expr
.X_add_number
, true, mips16_small
,
8249 mips16_ext
, &ip
->insn_opcode
,
8250 &ip
->use_extend
, &ip
->extend
);
8251 imm_expr
.X_op
= O_absent
;
8252 imm_reloc
= BFD_RELOC_UNUSED
;
8266 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8269 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8285 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8287 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8314 while (isdigit (*s
));
8317 as_bad ("invalid register number (%d)", regno
);
8323 if (s
[1] == 'f' && s
[2] == 'p')
8328 else if (s
[1] == 's' && s
[2] == 'p')
8333 else if (s
[1] == 'g' && s
[2] == 'p')
8338 else if (s
[1] == 'a' && s
[2] == 't')
8343 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8348 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8361 if (c
== 'v' || c
== 'w')
8363 regno
= mips16_to_32_reg_map
[lastregno
];
8377 regno
= mips32_to_16_reg_map
[regno
];
8382 regno
= ILLEGAL_REG
;
8387 regno
= ILLEGAL_REG
;
8392 regno
= ILLEGAL_REG
;
8397 if (regno
== AT
&& ! mips_opts
.noat
)
8398 as_warn ("used $at without \".set noat\"");
8405 if (regno
== ILLEGAL_REG
)
8412 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8416 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8419 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8422 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8428 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8431 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8432 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8442 if (strncmp (s
, "$pc", 3) == 0)
8466 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8468 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8469 and generate the appropriate reloc. If the text
8470 inside %gprel is not a symbol name with an
8471 optional offset, then we generate a normal reloc
8472 and will probably fail later. */
8473 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8474 if (imm_expr
.X_op
== O_symbol
)
8477 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8479 ip
->use_extend
= true;
8486 /* Just pick up a normal expression. */
8487 my_getExpression (&imm_expr
, s
);
8490 if (imm_expr
.X_op
== O_register
)
8492 /* What we thought was an expression turned out to
8495 if (s
[0] == '(' && args
[1] == '(')
8497 /* It looks like the expression was omitted
8498 before a register indirection, which means
8499 that the expression is implicitly zero. We
8500 still set up imm_expr, so that we handle
8501 explicit extensions correctly. */
8502 imm_expr
.X_op
= O_constant
;
8503 imm_expr
.X_add_number
= 0;
8504 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8511 /* We need to relax this instruction. */
8512 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8521 /* We use offset_reloc rather than imm_reloc for the PC
8522 relative operands. This lets macros with both
8523 immediate and address operands work correctly. */
8524 my_getExpression (&offset_expr
, s
);
8526 if (offset_expr
.X_op
== O_register
)
8529 /* We need to relax this instruction. */
8530 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8534 case '6': /* break code */
8535 my_getExpression (&imm_expr
, s
);
8536 check_absolute_expr (ip
, &imm_expr
);
8537 if ((unsigned long) imm_expr
.X_add_number
> 63)
8539 as_warn ("Invalid value for `%s' (%lu)",
8541 (unsigned long) imm_expr
.X_add_number
);
8542 imm_expr
.X_add_number
&= 0x3f;
8544 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8545 imm_expr
.X_op
= O_absent
;
8549 case 'a': /* 26 bit address */
8550 my_getExpression (&offset_expr
, s
);
8552 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8553 ip
->insn_opcode
<<= 16;
8556 case 'l': /* register list for entry macro */
8557 case 'L': /* register list for exit macro */
8567 int freg
, reg1
, reg2
;
8569 while (*s
== ' ' || *s
== ',')
8573 as_bad ("can't parse register list");
8585 while (isdigit (*s
))
8607 as_bad ("invalid register list");
8612 while (isdigit (*s
))
8619 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8624 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8629 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8630 mask
|= (reg2
- 3) << 3;
8631 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8632 mask
|= (reg2
- 15) << 1;
8633 else if (reg1
== 31 && reg2
== 31)
8637 as_bad ("invalid register list");
8641 /* The mask is filled in in the opcode table for the
8642 benefit of the disassembler. We remove it before
8643 applying the actual mask. */
8644 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8645 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8649 case 'e': /* extend code */
8650 my_getExpression (&imm_expr
, s
);
8651 check_absolute_expr (ip
, &imm_expr
);
8652 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8654 as_warn ("Invalid value for `%s' (%lu)",
8656 (unsigned long) imm_expr
.X_add_number
);
8657 imm_expr
.X_add_number
&= 0x7ff;
8659 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8660 imm_expr
.X_op
= O_absent
;
8670 /* Args don't match. */
8671 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8672 strcmp (insn
->name
, insn
[1].name
) == 0)
8679 insn_error
= "illegal operands";
8685 /* This structure holds information we know about a mips16 immediate
8688 struct mips16_immed_operand
8690 /* The type code used in the argument string in the opcode table. */
8692 /* The number of bits in the short form of the opcode. */
8694 /* The number of bits in the extended form of the opcode. */
8696 /* The amount by which the short form is shifted when it is used;
8697 for example, the sw instruction has a shift count of 2. */
8699 /* The amount by which the short form is shifted when it is stored
8700 into the instruction code. */
8702 /* Non-zero if the short form is unsigned. */
8704 /* Non-zero if the extended form is unsigned. */
8706 /* Non-zero if the value is PC relative. */
8710 /* The mips16 immediate operand types. */
8712 static const struct mips16_immed_operand mips16_immed_operands
[] =
8714 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8715 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8716 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8717 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8718 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8719 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8720 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8721 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8722 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8723 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8724 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8725 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8726 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8727 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8728 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8729 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8730 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8731 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8732 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8733 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8734 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8737 #define MIPS16_NUM_IMMED \
8738 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8740 /* Handle a mips16 instruction with an immediate value. This or's the
8741 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8742 whether an extended value is needed; if one is needed, it sets
8743 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8744 If SMALL is true, an unextended opcode was explicitly requested.
8745 If EXT is true, an extended opcode was explicitly requested. If
8746 WARN is true, warn if EXT does not match reality. */
8749 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8758 unsigned long *insn
;
8759 boolean
*use_extend
;
8760 unsigned short *extend
;
8762 register const struct mips16_immed_operand
*op
;
8763 int mintiny
, maxtiny
;
8766 op
= mips16_immed_operands
;
8767 while (op
->type
!= type
)
8770 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8775 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8778 maxtiny
= 1 << op
->nbits
;
8783 maxtiny
= (1 << op
->nbits
) - 1;
8788 mintiny
= - (1 << (op
->nbits
- 1));
8789 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8792 /* Branch offsets have an implicit 0 in the lowest bit. */
8793 if (type
== 'p' || type
== 'q')
8796 if ((val
& ((1 << op
->shift
) - 1)) != 0
8797 || val
< (mintiny
<< op
->shift
)
8798 || val
> (maxtiny
<< op
->shift
))
8803 if (warn
&& ext
&& ! needext
)
8804 as_warn_where (file
, line
, "extended operand requested but not required");
8805 if (small
&& needext
)
8806 as_bad_where (file
, line
, "invalid unextended operand value");
8808 if (small
|| (! ext
&& ! needext
))
8812 *use_extend
= false;
8813 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8814 insnval
<<= op
->op_shift
;
8819 long minext
, maxext
;
8825 maxext
= (1 << op
->extbits
) - 1;
8829 minext
= - (1 << (op
->extbits
- 1));
8830 maxext
= (1 << (op
->extbits
- 1)) - 1;
8832 if (val
< minext
|| val
> maxext
)
8833 as_bad_where (file
, line
,
8834 "operand value out of range for instruction");
8837 if (op
->extbits
== 16)
8839 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8842 else if (op
->extbits
== 15)
8844 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8849 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8853 *extend
= (unsigned short) extval
;
8862 my_getSmallExpression (ep
, str
)
8873 ((str
[1] == 'h' && str
[2] == 'i')
8874 || (str
[1] == 'H' && str
[2] == 'I')
8875 || (str
[1] == 'l' && str
[2] == 'o'))
8887 * A small expression may be followed by a base register.
8888 * Scan to the end of this operand, and then back over a possible
8889 * base register. Then scan the small expression up to that
8890 * point. (Based on code in sparc.c...)
8892 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8894 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8896 if (isdigit (sp
[-2]))
8898 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8900 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8906 else if (sp
- 5 >= str
8909 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8910 || (sp
[-3] == 's' && sp
[-2] == 'p')
8911 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8912 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8918 /* no expression means zero offset */
8921 /* %xx(reg) is an error */
8922 ep
->X_op
= O_absent
;
8927 ep
->X_op
= O_constant
;
8930 ep
->X_add_symbol
= NULL
;
8931 ep
->X_op_symbol
= NULL
;
8932 ep
->X_add_number
= 0;
8937 my_getExpression (ep
, str
);
8944 my_getExpression (ep
, str
);
8945 return c
; /* => %hi or %lo encountered */
8949 my_getExpression (ep
, str
)
8955 save_in
= input_line_pointer
;
8956 input_line_pointer
= str
;
8958 expr_end
= input_line_pointer
;
8959 input_line_pointer
= save_in
;
8961 /* If we are in mips16 mode, and this is an expression based on `.',
8962 then we bump the value of the symbol by 1 since that is how other
8963 text symbols are handled. We don't bother to handle complex
8964 expressions, just `.' plus or minus a constant. */
8965 if (mips_opts
.mips16
8966 && ep
->X_op
== O_symbol
8967 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8968 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8969 && ep
->X_add_symbol
->sy_frag
== frag_now
8970 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8971 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8972 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8975 /* Turn a string in input_line_pointer into a floating point constant
8976 of type type, and store the appropriate bytes in *litP. The number
8977 of LITTLENUMS emitted is stored in *sizeP . An error message is
8978 returned, or NULL on OK. */
8981 md_atof (type
, litP
, sizeP
)
8987 LITTLENUM_TYPE words
[4];
9003 return "bad call to md_atof";
9006 t
= atof_ieee (input_line_pointer
, type
, words
);
9008 input_line_pointer
= t
;
9012 if (! target_big_endian
)
9014 for (i
= prec
- 1; i
>= 0; i
--)
9016 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9022 for (i
= 0; i
< prec
; i
++)
9024 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9033 md_number_to_chars (buf
, val
, n
)
9038 if (target_big_endian
)
9039 number_to_chars_bigendian (buf
, val
, n
);
9041 number_to_chars_littleendian (buf
, val
, n
);
9044 CONST
char *md_shortopts
= "O::g::G:";
9046 struct option md_longopts
[] = {
9047 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9048 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9049 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9050 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9051 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9052 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9053 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9054 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9055 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9056 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9057 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9058 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9059 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9060 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9061 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9062 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9063 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9064 {"break", no_argument
, NULL
, OPTION_BREAK
},
9065 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9066 #define OPTION_EB (OPTION_MD_BASE + 11)
9067 {"EB", no_argument
, NULL
, OPTION_EB
},
9068 #define OPTION_EL (OPTION_MD_BASE + 12)
9069 {"EL", no_argument
, NULL
, OPTION_EL
},
9070 #define OPTION_M4650 (OPTION_MD_BASE + 13)
9071 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9072 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
9073 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9074 #define OPTION_M4010 (OPTION_MD_BASE + 15)
9075 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9076 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
9077 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9078 #define OPTION_M4100 (OPTION_MD_BASE + 17)
9079 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9080 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
9081 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9082 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
9083 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9084 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
9085 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9086 /* start-sanitize-r5900 */
9087 #define OPTION_M5900 (OPTION_MD_BASE + 24)
9088 {"m5900", no_argument
, NULL
, OPTION_M5900
},
9089 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
9090 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
9091 /* end-sanitize-r5900 */
9092 #define OPTION_M3900 (OPTION_MD_BASE + 26)
9093 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9094 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
9095 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9097 /* start-sanitize-tx19 */
9098 {"m1900", no_argument
, NULL
, OPTION_M3900
},
9099 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
9100 /* end-sanitize-tx19 */
9102 /* start-sanitize-vr5400 */
9103 #define OPTION_M5400 (OPTION_MD_BASE + 28)
9104 {"m5400", no_argument
, NULL
, OPTION_M5400
},
9105 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
9106 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
9108 /* end-sanitize-vr5400 */
9109 /* start-sanitize-tx49 */
9110 #define OPTION_M4900 (OPTION_MD_BASE + 30)
9111 {"m4900", no_argument
, NULL
, OPTION_M4900
},
9112 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
9113 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
9115 /* end-sanitize-tx49 */
9116 /* start-sanitize-vr4320 */
9117 #define OPTION_M4320 (OPTION_MD_BASE + 32)
9118 {"m4320", no_argument
, NULL
, OPTION_M4320
},
9119 #define OPTION_NO_M4320 (OPTION_MD_BASE + 33)
9120 {"no-m4320", no_argument
, NULL
, OPTION_NO_M4320
},
9122 /* end-sanitize-vr4320 */
9123 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
9124 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
9125 #define OPTION_XGOT (OPTION_MD_BASE + 19)
9126 #define OPTION_32 (OPTION_MD_BASE + 20)
9127 #define OPTION_64 (OPTION_MD_BASE + 21)
9129 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9130 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9131 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9132 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9133 {"32", no_argument
, NULL
, OPTION_32
},
9134 {"64", no_argument
, NULL
, OPTION_64
},
9137 {NULL
, no_argument
, NULL
, 0}
9139 size_t md_longopts_size
= sizeof(md_longopts
);
9142 md_parse_option (c
, arg
)
9157 target_big_endian
= 1;
9161 target_big_endian
= 0;
9165 if (arg
&& arg
[1] == '0')
9175 mips_debug
= atoi (arg
);
9176 /* When the MIPS assembler sees -g or -g2, it does not do
9177 optimizations which limit full symbolic debugging. We take
9178 that to be equivalent to -O0. */
9179 if (mips_debug
== 2)
9203 /* Identify the processor type */
9205 if (strcmp (p
, "default") == 0
9206 || strcmp (p
, "DEFAULT") == 0)
9212 /* We need to cope with the various "vr" prefixes for the 4300
9214 if (*p
== 'v' || *p
== 'V')
9220 if (*p
== 'r' || *p
== 'R')
9227 if (strcmp (p
, "10000") == 0
9228 || strcmp (p
, "10k") == 0
9229 || strcmp (p
, "10K") == 0)
9231 /* start-sanitize-tx19 */
9232 else if (strcmp (p
, "1900") == 0)
9234 /* end-sanitize-tx19 */
9238 if (strcmp (p
, "2000") == 0
9239 || strcmp (p
, "2k") == 0
9240 || strcmp (p
, "2K") == 0)
9245 if (strcmp (p
, "3000") == 0
9246 || strcmp (p
, "3k") == 0
9247 || strcmp (p
, "3K") == 0)
9249 else if (strcmp (p
, "3900") == 0)
9254 if (strcmp (p
, "4000") == 0
9255 || strcmp (p
, "4k") == 0
9256 || strcmp (p
, "4K") == 0)
9258 else if (strcmp (p
, "4100") == 0)
9260 else if (strcmp (p
, "4300") == 0)
9262 /* start-sanitize-vr4320 */
9263 else if (strcmp (p
, "4320") == 0)
9265 /* end-sanitize-vr4320 */
9266 else if (strcmp (p
, "4400") == 0)
9268 else if (strcmp (p
, "4600") == 0)
9270 else if (strcmp (p
, "4650") == 0)
9272 /* start-sanitize-tx49 */
9273 else if (strcmp (p
, "4900") == 0)
9275 /* end-sanitize-tx49 */
9276 else if (strcmp (p
, "4010") == 0)
9281 if (strcmp (p
, "5000") == 0
9282 || strcmp (p
, "5k") == 0
9283 || strcmp (p
, "5K") == 0)
9285 /* start-sanitize-vr5400 */
9286 else if (strcmp (p
, "5400") == 0)
9288 /* end-sanitize-vr5400 */
9289 /* start-sanitize-r5900 */
9290 else if (strcmp (p
, "5900") == 0)
9292 /* end-sanitize-r5900 */
9296 if (strcmp (p
, "6000") == 0
9297 || strcmp (p
, "6k") == 0
9298 || strcmp (p
, "6K") == 0)
9303 if (strcmp (p
, "8000") == 0
9304 || strcmp (p
, "8k") == 0
9305 || strcmp (p
, "8K") == 0)
9310 if (strcmp (p
, "orion") == 0)
9316 && (mips_cpu
!= 4300
9318 /* start-sanitize-vr4320 */
9320 /* end-sanitize-vr4320 */
9321 /* start-sanitize-vr5400 */
9323 /* end-sanitize-vr5400 */
9324 && mips_cpu
!= 5000))
9326 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
9332 as_bad ("invalid architecture -mcpu=%s", arg
);
9343 case OPTION_NO_M4650
:
9351 case OPTION_NO_M4010
:
9359 case OPTION_NO_M4100
:
9363 /* start-sanitize-r5900 */
9368 case OPTION_NO_M5900
:
9371 /* end-sanitize-r5900 */
9373 /* start-sanitize-vr4320 */
9378 case OPTION_NO_M4320
:
9382 /* end-sanitize-vr4320 */
9383 /* start-sanitize-vr5400 */
9388 case OPTION_NO_M5400
:
9392 /* end-sanitize-vr5400 */
9397 case OPTION_NO_M3900
:
9401 /* start-sanitize-tx49 */
9406 case OPTION_NO_M4900
:
9410 /* end-sanitize-tx49 */
9412 mips_opts
.mips16
= 1;
9413 mips_no_prev_insn (false);
9416 case OPTION_NO_MIPS16
:
9417 mips_opts
.mips16
= 0;
9418 mips_no_prev_insn (false);
9421 case OPTION_MEMBEDDED_PIC
:
9422 mips_pic
= EMBEDDED_PIC
;
9423 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9425 as_bad ("-G may not be used with embedded PIC code");
9428 g_switch_value
= 0x7fffffff;
9431 /* When generating ELF code, we permit -KPIC and -call_shared to
9432 select SVR4_PIC, and -non_shared to select no PIC. This is
9433 intended to be compatible with Irix 5. */
9434 case OPTION_CALL_SHARED
:
9435 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9437 as_bad ("-call_shared is supported only for ELF format");
9440 mips_pic
= SVR4_PIC
;
9441 if (g_switch_seen
&& g_switch_value
!= 0)
9443 as_bad ("-G may not be used with SVR4 PIC code");
9449 case OPTION_NON_SHARED
:
9450 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9452 as_bad ("-non_shared is supported only for ELF format");
9458 /* The -xgot option tells the assembler to use 32 offsets when
9459 accessing the got in SVR4_PIC mode. It is for Irix
9466 if (! USE_GLOBAL_POINTER_OPT
)
9468 as_bad ("-G is not supported for this configuration");
9471 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9473 as_bad ("-G may not be used with SVR4 or embedded PIC code");
9477 g_switch_value
= atoi (arg
);
9481 /* The -32 and -64 options tell the assembler to output the 32
9482 bit or the 64 bit MIPS ELF format. */
9489 const char **list
, **l
;
9491 list
= bfd_target_list ();
9492 for (l
= list
; *l
!= NULL
; l
++)
9493 if (strcmp (*l
, "elf64-bigmips") == 0
9494 || strcmp (*l
, "elf64-littlemips") == 0)
9497 as_fatal ("No compiled in support for 64 bit object file format");
9511 md_show_usage (stream
)
9516 -membedded-pic generate embedded position independent code\n\
9517 -EB generate big endian output\n\
9518 -EL generate little endian output\n\
9519 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9520 -G NUM allow referencing objects up to NUM bytes\n\
9521 implicitly with the gp register [default 8]\n");
9523 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
9524 -mips2, -mcpu=r6000 generate code for r6000\n\
9525 -mips3, -mcpu=r4000 generate code for r4000\n\
9526 -mips4, -mcpu=r8000 generate code for r8000\n\
9527 -mcpu=vr4300 generate code for vr4300\n\
9528 -mcpu=vr4100 generate code for vr4100\n\
9529 -m4650 permit R4650 instructions\n\
9530 -no-m4650 do not permit R4650 instructions\n\
9531 -m4010 permit R4010 instructions\n\
9532 -no-m4010 do not permit R4010 instructions\n\
9533 -m4100 permit VR4100 instructions\n\
9534 -no-m4100 do not permit VR4100 instructions\n");
9536 -mips16 generate mips16 instructions\n\
9537 -no-mips16 do not generate mips16 instructions\n");
9539 -O0 remove unneeded NOPs, do not swap branches\n\
9540 -O remove unneeded NOPs and swap branches\n\
9541 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9542 --break, --no-trap break exception on div by 0 and mult overflow\n");
9545 -KPIC, -call_shared generate SVR4 position independent code\n\
9546 -non_shared do not generate position independent code\n\
9547 -xgot assume a 32 bit GOT\n\
9548 -32 create 32 bit object file (default)\n\
9549 -64 create 64 bit object file\n");
9554 mips_init_after_args ()
9556 /* initialize opcodes */
9557 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9558 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9562 md_pcrel_from (fixP
)
9565 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9566 && fixP
->fx_addsy
!= (symbolS
*) NULL
9567 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9569 /* This makes a branch to an undefined symbol be a branch to the
9570 current location. */
9574 /* return the address of the delay slot */
9575 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9578 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9579 reloc for a cons. We could use the definition there, except that
9580 we want to handle 64 bit relocs specially. */
9583 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9586 unsigned int nbytes
;
9590 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9592 if (nbytes
== 8 && ! mips_64
)
9594 if (target_big_endian
)
9600 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9601 as_bad ("Unsupported reloc size %d", nbytes
);
9603 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9606 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9609 /* This is called before the symbol table is processed. In order to
9610 work with gcc when using mips-tfile, we must keep all local labels.
9611 However, in other cases, we want to discard them. If we were
9612 called with -g, but we didn't see any debugging information, it may
9613 mean that gcc is smuggling debugging information through to
9614 mips-tfile, in which case we must generate all local labels. */
9617 mips_frob_file_before_adjust ()
9619 #ifndef NO_ECOFF_DEBUGGING
9622 && ! ecoff_debugging_seen
)
9623 flag_keep_locals
= 1;
9627 /* Sort any unmatched HI16_S relocs so that they immediately precede
9628 the corresponding LO reloc. This is called before md_apply_fix and
9629 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9630 explicit use of the %hi modifier. */
9635 struct mips_hi_fixup
*l
;
9637 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9639 segment_info_type
*seginfo
;
9642 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9644 /* Check quickly whether the next fixup happens to be a matching
9646 if (l
->fixp
->fx_next
!= NULL
9647 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9648 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9649 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9652 /* Look through the fixups for this segment for a matching %lo.
9653 When we find one, move the %hi just in front of it. We do
9654 this in two passes. In the first pass, we try to find a
9655 unique %lo. In the second pass, we permit multiple %hi
9656 relocs for a single %lo (this is a GNU extension). */
9657 seginfo
= seg_info (l
->seg
);
9658 for (pass
= 0; pass
< 2; pass
++)
9663 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9665 /* Check whether this is a %lo fixup which matches l->fixp. */
9666 if (f
->fx_r_type
== BFD_RELOC_LO16
9667 && f
->fx_addsy
== l
->fixp
->fx_addsy
9668 && f
->fx_offset
== l
->fixp
->fx_offset
9671 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9672 || prev
->fx_addsy
!= f
->fx_addsy
9673 || prev
->fx_offset
!= f
->fx_offset
))
9677 /* Move l->fixp before f. */
9678 for (pf
= &seginfo
->fix_root
;
9680 pf
= &(*pf
)->fx_next
)
9681 assert (*pf
!= NULL
);
9683 *pf
= l
->fixp
->fx_next
;
9685 l
->fixp
->fx_next
= f
;
9687 seginfo
->fix_root
= l
->fixp
;
9689 prev
->fx_next
= l
->fixp
;
9701 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9702 "Unmatched %%hi reloc");
9707 /* When generating embedded PIC code we need to use a special
9708 relocation to represent the difference of two symbols in the .text
9709 section (switch tables use a difference of this sort). See
9710 include/coff/mips.h for details. This macro checks whether this
9711 fixup requires the special reloc. */
9712 #define SWITCH_TABLE(fixp) \
9713 ((fixp)->fx_r_type == BFD_RELOC_32 \
9714 && (fixp)->fx_addsy != NULL \
9715 && (fixp)->fx_subsy != NULL \
9716 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9717 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9719 /* When generating embedded PIC code we must keep all PC relative
9720 relocations, in case the linker has to relax a call. We also need
9721 to keep relocations for switch table entries. */
9725 mips_force_relocation (fixp
)
9728 return (mips_pic
== EMBEDDED_PIC
9730 || SWITCH_TABLE (fixp
)
9731 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9732 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9735 /* Apply a fixup to the object file. */
9738 md_apply_fix (fixP
, valueP
)
9745 assert (fixP
->fx_size
== 4
9746 || fixP
->fx_r_type
== BFD_RELOC_16
9747 || fixP
->fx_r_type
== BFD_RELOC_64
);
9751 /* If we aren't adjusting this fixup to be against the section
9752 symbol, we need to adjust the value. */
9754 if (fixP
->fx_addsy
!= NULL
9755 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
9756 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
9758 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9759 if (value
!= 0 && ! fixP
->fx_pcrel
)
9761 /* In this case, the bfd_install_relocation routine will
9762 incorrectly add the symbol value back in. We just want
9763 the addend to appear in the object file. */
9764 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9769 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9771 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9774 switch (fixP
->fx_r_type
)
9776 case BFD_RELOC_MIPS_JMP
:
9777 case BFD_RELOC_HI16
:
9778 case BFD_RELOC_HI16_S
:
9779 case BFD_RELOC_MIPS_GPREL
:
9780 case BFD_RELOC_MIPS_LITERAL
:
9781 case BFD_RELOC_MIPS_CALL16
:
9782 case BFD_RELOC_MIPS_GOT16
:
9783 case BFD_RELOC_MIPS_GPREL32
:
9784 case BFD_RELOC_MIPS_GOT_HI16
:
9785 case BFD_RELOC_MIPS_GOT_LO16
:
9786 case BFD_RELOC_MIPS_CALL_HI16
:
9787 case BFD_RELOC_MIPS_CALL_LO16
:
9788 case BFD_RELOC_MIPS16_GPREL
:
9790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9791 "Invalid PC relative reloc");
9792 /* Nothing needed to do. The value comes from the reloc entry */
9795 case BFD_RELOC_MIPS16_JMP
:
9796 /* We currently always generate a reloc against a symbol, which
9797 means that we don't want an addend even if the symbol is
9799 fixP
->fx_addnumber
= 0;
9802 case BFD_RELOC_PCREL_HI16_S
:
9803 /* The addend for this is tricky if it is internal, so we just
9804 do everything here rather than in bfd_install_relocation. */
9805 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9807 /* For an external symbol adjust by the address to make it
9808 pcrel_offset. We use the address of the RELLO reloc
9809 which follows this one. */
9810 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9811 + fixP
->fx_next
->fx_where
);
9816 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9817 if (target_big_endian
)
9819 md_number_to_chars (buf
, value
, 2);
9822 case BFD_RELOC_PCREL_LO16
:
9823 /* The addend for this is tricky if it is internal, so we just
9824 do everything here rather than in bfd_install_relocation. */
9825 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9826 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9827 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9828 if (target_big_endian
)
9830 md_number_to_chars (buf
, value
, 2);
9834 /* This is handled like BFD_RELOC_32, but we output a sign
9835 extended value if we are only 32 bits. */
9837 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9839 if (8 <= sizeof (valueT
))
9840 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9847 w1
= w2
= fixP
->fx_where
;
9848 if (target_big_endian
)
9852 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9853 if ((value
& 0x80000000) != 0)
9857 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9863 /* If we are deleting this reloc entry, we must fill in the
9864 value now. This can happen if we have a .word which is not
9865 resolved when it appears but is later defined. We also need
9866 to fill in the value if this is an embedded PIC switch table
9869 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9870 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9875 /* If we are deleting this reloc entry, we must fill in the
9877 assert (fixP
->fx_size
== 2);
9879 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9883 case BFD_RELOC_LO16
:
9884 /* When handling an embedded PIC switch statement, we can wind
9885 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9888 if (value
< -0x8000 || value
> 0x7fff)
9889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9890 "relocation overflow");
9891 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9892 if (target_big_endian
)
9894 md_number_to_chars (buf
, value
, 2);
9898 case BFD_RELOC_16_PCREL_S2
:
9900 * We need to save the bits in the instruction since fixup_segment()
9901 * might be deleting the relocation entry (i.e., a branch within
9902 * the current segment).
9904 if ((value
& 0x3) != 0)
9905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9906 "Branch to odd address (%lx)", value
);
9909 /* update old instruction data */
9910 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9911 if (target_big_endian
)
9912 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9914 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9916 if (value
>= -0x8000 && value
< 0x8000)
9917 insn
|= value
& 0xffff;
9920 /* The branch offset is too large. If this is an
9921 unconditional branch, and we are not generating PIC code,
9922 we can convert it to an absolute jump instruction. */
9923 if (mips_pic
== NO_PIC
9925 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9926 && (fixP
->fx_frag
->fr_address
9927 < text_section
->vma
+ text_section
->_raw_size
)
9928 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9929 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9930 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9932 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9933 insn
= 0x0c000000; /* jal */
9935 insn
= 0x08000000; /* j */
9936 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9938 fixP
->fx_addsy
= section_symbol (text_section
);
9939 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9943 /* FIXME. It would be possible in principle to handle
9944 conditional branches which overflow. They could be
9945 transformed into a branch around a jump. This would
9946 require setting up variant frags for each different
9947 branch type. The native MIPS assembler attempts to
9948 handle these cases, but it appears to do it
9950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9951 "Branch out of range");
9955 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9970 const struct mips_opcode
*p
;
9971 int treg
, sreg
, dreg
, shamt
;
9976 for (i
= 0; i
< NUMOPCODES
; ++i
)
9978 p
= &mips_opcodes
[i
];
9979 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9981 printf ("%08lx %s\t", oc
, p
->name
);
9982 treg
= (oc
>> 16) & 0x1f;
9983 sreg
= (oc
>> 21) & 0x1f;
9984 dreg
= (oc
>> 11) & 0x1f;
9985 shamt
= (oc
>> 6) & 0x1f;
9987 for (args
= p
->args
;; ++args
)
9998 printf ("%c", *args
);
10002 assert (treg
== sreg
);
10003 printf ("$%d,$%d", treg
, sreg
);
10008 printf ("$%d", dreg
);
10013 printf ("$%d", treg
);
10017 printf ("0x%x", treg
);
10022 printf ("$%d", sreg
);
10026 printf ("0x%08lx", oc
& 0x1ffffff);
10033 printf ("%d", imm
);
10038 printf ("$%d", shamt
);
10049 printf ("%08lx UNDEFINED\n", oc
);
10060 name
= input_line_pointer
;
10061 c
= get_symbol_end ();
10062 p
= (symbolS
*) symbol_find_or_make (name
);
10063 *input_line_pointer
= c
;
10067 /* Align the current frag to a given power of two. The MIPS assembler
10068 also automatically adjusts any preceding label. */
10071 mips_align (to
, fill
, label
)
10076 mips_emit_delays (false);
10077 frag_align (to
, fill
, 0);
10078 record_alignment (now_seg
, to
);
10081 assert (S_GET_SEGMENT (label
) == now_seg
);
10082 label
->sy_frag
= frag_now
;
10083 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10087 /* Align to a given power of two. .align 0 turns off the automatic
10088 alignment used by the data creating pseudo-ops. */
10095 register long temp_fill
;
10096 long max_alignment
= 15;
10100 o Note that the assembler pulls down any immediately preceeding label
10101 to the aligned address.
10102 o It's not documented but auto alignment is reinstated by
10103 a .align pseudo instruction.
10104 o Note also that after auto alignment is turned off the mips assembler
10105 issues an error on attempt to assemble an improperly aligned data item.
10110 temp
= get_absolute_expression ();
10111 if (temp
> max_alignment
)
10112 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
10115 as_warn ("Alignment negative: 0 assumed.");
10118 if (*input_line_pointer
== ',')
10120 input_line_pointer
++;
10121 temp_fill
= get_absolute_expression ();
10128 mips_align (temp
, (int) temp_fill
,
10129 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10136 demand_empty_rest_of_line ();
10140 mips_flush_pending_output ()
10142 mips_emit_delays (false);
10143 mips_clear_insn_labels ();
10152 /* When generating embedded PIC code, we only use the .text, .lit8,
10153 .sdata and .sbss sections. We change the .data and .rdata
10154 pseudo-ops to use .sdata. */
10155 if (mips_pic
== EMBEDDED_PIC
10156 && (sec
== 'd' || sec
== 'r'))
10160 /* The ELF backend needs to know that we are changing sections, so
10161 that .previous works correctly. We could do something like check
10162 for a obj_section_change_hook macro, but that might be confusing
10163 as it would not be appropriate to use it in the section changing
10164 functions in read.c, since obj-elf.c intercepts those. FIXME:
10165 This should be cleaner, somehow. */
10166 obj_elf_section_change_hook ();
10169 mips_emit_delays (false);
10179 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10180 demand_empty_rest_of_line ();
10184 if (USE_GLOBAL_POINTER_OPT
)
10186 seg
= subseg_new (RDATA_SECTION_NAME
,
10187 (subsegT
) get_absolute_expression ());
10188 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10190 bfd_set_section_flags (stdoutput
, seg
,
10196 if (strcmp (TARGET_OS
, "elf") != 0)
10197 bfd_set_section_alignment (stdoutput
, seg
, 4);
10199 demand_empty_rest_of_line ();
10203 as_bad ("No read only data section in this object file format");
10204 demand_empty_rest_of_line ();
10210 if (USE_GLOBAL_POINTER_OPT
)
10212 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10213 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10215 bfd_set_section_flags (stdoutput
, seg
,
10216 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10218 if (strcmp (TARGET_OS
, "elf") != 0)
10219 bfd_set_section_alignment (stdoutput
, seg
, 4);
10221 demand_empty_rest_of_line ();
10226 as_bad ("Global pointers not supported; recompile -G 0");
10227 demand_empty_rest_of_line ();
10236 mips_enable_auto_align ()
10247 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10248 mips_emit_delays (false);
10249 if (log_size
> 0 && auto_align
)
10250 mips_align (log_size
, 0, label
);
10251 mips_clear_insn_labels ();
10252 cons (1 << log_size
);
10256 s_float_cons (type
)
10261 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10263 mips_emit_delays (false);
10267 mips_align (3, 0, label
);
10269 mips_align (2, 0, label
);
10271 mips_clear_insn_labels ();
10276 /* Handle .globl. We need to override it because on Irix 5 you are
10279 where foo is an undefined symbol, to mean that foo should be
10280 considered to be the address of a function. */
10291 name
= input_line_pointer
;
10292 c
= get_symbol_end ();
10293 symbolP
= symbol_find_or_make (name
);
10294 *input_line_pointer
= c
;
10295 SKIP_WHITESPACE ();
10297 /* On Irix 5, every global symbol that is not explicitly labelled as
10298 being a function is apparently labelled as being an object. */
10301 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10306 secname
= input_line_pointer
;
10307 c
= get_symbol_end ();
10308 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10310 as_bad ("%s: no such section", secname
);
10311 *input_line_pointer
= c
;
10313 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10314 flag
= BSF_FUNCTION
;
10317 symbolP
->bsym
->flags
|= flag
;
10319 S_SET_EXTERNAL (symbolP
);
10320 demand_empty_rest_of_line ();
10330 opt
= input_line_pointer
;
10331 c
= get_symbol_end ();
10335 /* FIXME: What does this mean? */
10337 else if (strncmp (opt
, "pic", 3) == 0)
10341 i
= atoi (opt
+ 3);
10345 mips_pic
= SVR4_PIC
;
10347 as_bad (".option pic%d not supported", i
);
10349 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10351 if (g_switch_seen
&& g_switch_value
!= 0)
10352 as_warn ("-G may not be used with SVR4 PIC code");
10353 g_switch_value
= 0;
10354 bfd_set_gp_size (stdoutput
, 0);
10358 as_warn ("Unrecognized option \"%s\"", opt
);
10360 *input_line_pointer
= c
;
10361 demand_empty_rest_of_line ();
10364 /* This structure is used to hold a stack of .set values. */
10366 struct mips_option_stack
10368 struct mips_option_stack
*next
;
10369 struct mips_set_options options
;
10372 static struct mips_option_stack
*mips_opts_stack
;
10374 /* Handle the .set pseudo-op. */
10380 char *name
= input_line_pointer
, ch
;
10382 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10383 input_line_pointer
++;
10384 ch
= *input_line_pointer
;
10385 *input_line_pointer
= '\0';
10387 if (strcmp (name
, "reorder") == 0)
10389 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10391 /* If we still have pending nops, we can discard them. The
10392 usual nop handling will insert any that are still
10394 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10395 * (mips_opts
.mips16
? 2 : 4));
10396 prev_nop_frag
= NULL
;
10398 mips_opts
.noreorder
= 0;
10400 else if (strcmp (name
, "noreorder") == 0)
10402 mips_emit_delays (true);
10403 mips_opts
.noreorder
= 1;
10404 mips_any_noreorder
= 1;
10406 else if (strcmp (name
, "at") == 0)
10408 mips_opts
.noat
= 0;
10410 else if (strcmp (name
, "noat") == 0)
10412 mips_opts
.noat
= 1;
10414 else if (strcmp (name
, "macro") == 0)
10416 mips_opts
.warn_about_macros
= 0;
10418 else if (strcmp (name
, "nomacro") == 0)
10420 if (mips_opts
.noreorder
== 0)
10421 as_bad ("`noreorder' must be set before `nomacro'");
10422 mips_opts
.warn_about_macros
= 1;
10424 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10426 mips_opts
.nomove
= 0;
10428 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10430 mips_opts
.nomove
= 1;
10432 else if (strcmp (name
, "bopt") == 0)
10434 mips_opts
.nobopt
= 0;
10436 else if (strcmp (name
, "nobopt") == 0)
10438 mips_opts
.nobopt
= 1;
10440 else if (strcmp (name
, "mips16") == 0
10441 || strcmp (name
, "MIPS-16") == 0)
10442 mips_opts
.mips16
= 1;
10443 else if (strcmp (name
, "nomips16") == 0
10444 || strcmp (name
, "noMIPS-16") == 0)
10445 mips_opts
.mips16
= 0;
10446 else if (strncmp (name
, "mips", 4) == 0)
10450 /* Permit the user to change the ISA on the fly. Needless to
10451 say, misuse can cause serious problems. */
10452 isa
= atoi (name
+ 4);
10454 mips_opts
.isa
= file_mips_isa
;
10455 else if (isa
< 1 || isa
> 4)
10456 as_bad ("unknown ISA level");
10458 mips_opts
.isa
= isa
;
10460 else if (strcmp (name
, "autoextend") == 0)
10461 mips_opts
.noautoextend
= 0;
10462 else if (strcmp (name
, "noautoextend") == 0)
10463 mips_opts
.noautoextend
= 1;
10464 else if (strcmp (name
, "push") == 0)
10466 struct mips_option_stack
*s
;
10468 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10469 s
->next
= mips_opts_stack
;
10470 s
->options
= mips_opts
;
10471 mips_opts_stack
= s
;
10473 else if (strcmp (name
, "pop") == 0)
10475 struct mips_option_stack
*s
;
10477 s
= mips_opts_stack
;
10479 as_bad (".set pop with no .set push");
10482 /* If we're changing the reorder mode we need to handle
10483 delay slots correctly. */
10484 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10485 mips_emit_delays (true);
10486 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10488 if (prev_nop_frag
!= NULL
)
10490 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10491 * (mips_opts
.mips16
? 2 : 4));
10492 prev_nop_frag
= NULL
;
10496 mips_opts
= s
->options
;
10497 mips_opts_stack
= s
->next
;
10503 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
10505 *input_line_pointer
= ch
;
10506 demand_empty_rest_of_line ();
10509 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10510 .option pic2. It means to generate SVR4 PIC calls. */
10513 s_abicalls (ignore
)
10516 mips_pic
= SVR4_PIC
;
10517 if (USE_GLOBAL_POINTER_OPT
)
10519 if (g_switch_seen
&& g_switch_value
!= 0)
10520 as_warn ("-G may not be used with SVR4 PIC code");
10521 g_switch_value
= 0;
10523 bfd_set_gp_size (stdoutput
, 0);
10524 demand_empty_rest_of_line ();
10527 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10528 PIC code. It sets the $gp register for the function based on the
10529 function address, which is in the register named in the argument.
10530 This uses a relocation against _gp_disp, which is handled specially
10531 by the linker. The result is:
10532 lui $gp,%hi(_gp_disp)
10533 addiu $gp,$gp,%lo(_gp_disp)
10534 addu $gp,$gp,.cpload argument
10535 The .cpload argument is normally $25 == $t9. */
10544 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10545 if (mips_pic
!= SVR4_PIC
)
10551 /* .cpload should be a in .set noreorder section. */
10552 if (mips_opts
.noreorder
== 0)
10553 as_warn (".cpload not in noreorder section");
10555 ex
.X_op
= O_symbol
;
10556 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10557 ex
.X_op_symbol
= NULL
;
10558 ex
.X_add_number
= 0;
10560 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10561 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10563 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10564 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10565 (int) BFD_RELOC_LO16
);
10567 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10568 GP
, GP
, tc_get_register (0));
10570 demand_empty_rest_of_line ();
10573 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10574 offset from $sp. The offset is remembered, and after making a PIC
10575 call $gp is restored from that location. */
10578 s_cprestore (ignore
)
10584 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10585 if (mips_pic
!= SVR4_PIC
)
10591 mips_cprestore_offset
= get_absolute_expression ();
10593 ex
.X_op
= O_constant
;
10594 ex
.X_add_symbol
= NULL
;
10595 ex
.X_op_symbol
= NULL
;
10596 ex
.X_add_number
= mips_cprestore_offset
;
10598 macro_build ((char *) NULL
, &icnt
, &ex
,
10599 ((bfd_arch_bits_per_address (stdoutput
) == 32
10600 || mips_opts
.isa
< 3)
10602 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10604 demand_empty_rest_of_line ();
10607 /* Handle the .gpword pseudo-op. This is used when generating PIC
10608 code. It generates a 32 bit GP relative reloc. */
10618 /* When not generating PIC code, this is treated as .word. */
10619 if (mips_pic
!= SVR4_PIC
)
10625 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10626 mips_emit_delays (true);
10628 mips_align (2, 0, label
);
10629 mips_clear_insn_labels ();
10633 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10635 as_bad ("Unsupported use of .gpword");
10636 ignore_rest_of_line ();
10640 md_number_to_chars (p
, (valueT
) 0, 4);
10641 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10642 BFD_RELOC_MIPS_GPREL32
);
10644 demand_empty_rest_of_line ();
10647 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10648 tables in SVR4 PIC code. */
10657 /* This is ignored when not generating SVR4 PIC code. */
10658 if (mips_pic
!= SVR4_PIC
)
10664 /* Add $gp to the register named as an argument. */
10665 reg
= tc_get_register (0);
10666 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10667 ((bfd_arch_bits_per_address (stdoutput
) == 32
10668 || mips_opts
.isa
< 3)
10669 ? "addu" : "daddu"),
10670 "d,v,t", reg
, reg
, GP
);
10672 demand_empty_rest_of_line ();
10675 /* Handle the .insn pseudo-op. This marks instruction labels in
10676 mips16 mode. This permits the linker to handle them specially,
10677 such as generating jalx instructions when needed. We also make
10678 them odd for the duration of the assembly, in order to generate the
10679 right sort of code. We will make them even in the adjust_symtab
10680 routine, while leaving them marked. This is convenient for the
10681 debugger and the disassembler. The linker knows to make them odd
10688 if (mips_opts
.mips16
)
10689 mips16_mark_labels ();
10691 demand_empty_rest_of_line ();
10694 /* Handle a .stabn directive. We need these in order to mark a label
10695 as being a mips16 text label correctly. Sometimes the compiler
10696 will emit a label, followed by a .stabn, and then switch sections.
10697 If the label and .stabn are in mips16 mode, then the label is
10698 really a mips16 text label. */
10704 if (type
== 'n' && mips_opts
.mips16
)
10705 mips16_mark_labels ();
10710 /* Parse a register string into a number. Called from the ECOFF code
10711 to parse .frame. The argument is non-zero if this is the frame
10712 register, so that we can record it in mips_frame_reg. */
10715 tc_get_register (frame
)
10720 SKIP_WHITESPACE ();
10721 if (*input_line_pointer
++ != '$')
10723 as_warn ("expected `$'");
10726 else if (isdigit ((unsigned char) *input_line_pointer
))
10728 reg
= get_absolute_expression ();
10729 if (reg
< 0 || reg
>= 32)
10731 as_warn ("Bad register number");
10737 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10739 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10741 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10743 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10747 as_warn ("Unrecognized register name");
10750 input_line_pointer
+= 2;
10753 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10758 md_section_align (seg
, addr
)
10762 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10765 /* We don't need to align ELF sections to the full alignment.
10766 However, Irix 5 may prefer that we align them at least to a 16
10767 byte boundary. We don't bother to align the sections if we are
10768 targeted for an embedded system. */
10769 if (strcmp (TARGET_OS
, "elf") == 0)
10775 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10778 /* Utility routine, called from above as well. If called while the
10779 input file is still being read, it's only an approximation. (For
10780 example, a symbol may later become defined which appeared to be
10781 undefined earlier.) */
10784 nopic_need_relax (sym
, before_relaxing
)
10786 int before_relaxing
;
10791 if (USE_GLOBAL_POINTER_OPT
)
10793 const char *symname
;
10796 /* Find out whether this symbol can be referenced off the GP
10797 register. It can be if it is smaller than the -G size or if
10798 it is in the .sdata or .sbss section. Certain symbols can
10799 not be referenced off the GP, although it appears as though
10801 symname
= S_GET_NAME (sym
);
10802 if (symname
!= (const char *) NULL
10803 && (strcmp (symname
, "eprol") == 0
10804 || strcmp (symname
, "etext") == 0
10805 || strcmp (symname
, "_gp") == 0
10806 || strcmp (symname
, "edata") == 0
10807 || strcmp (symname
, "_fbss") == 0
10808 || strcmp (symname
, "_fdata") == 0
10809 || strcmp (symname
, "_ftext") == 0
10810 || strcmp (symname
, "end") == 0
10811 || strcmp (symname
, "_gp_disp") == 0))
10813 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10815 #ifndef NO_ECOFF_DEBUGGING
10816 || (sym
->ecoff_extern_size
!= 0
10817 && sym
->ecoff_extern_size
<= g_switch_value
)
10819 /* We must defer this decision until after the whole
10820 file has been read, since there might be a .extern
10821 after the first use of this symbol. */
10822 || (before_relaxing
10823 #ifndef NO_ECOFF_DEBUGGING
10824 && sym
->ecoff_extern_size
== 0
10826 && S_GET_VALUE (sym
) == 0)
10827 || (S_GET_VALUE (sym
) != 0
10828 && S_GET_VALUE (sym
) <= g_switch_value
)))
10832 const char *segname
;
10834 segname
= segment_name (S_GET_SEGMENT (sym
));
10835 assert (strcmp (segname
, ".lit8") != 0
10836 && strcmp (segname
, ".lit4") != 0);
10837 change
= (strcmp (segname
, ".sdata") != 0
10838 && strcmp (segname
, ".sbss") != 0);
10843 /* We are not optimizing for the GP register. */
10847 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10848 extended opcode. SEC is the section the frag is in. */
10851 mips16_extended_frag (fragp
, sec
, stretch
)
10857 register const struct mips16_immed_operand
*op
;
10859 int mintiny
, maxtiny
;
10862 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10864 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10867 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10868 op
= mips16_immed_operands
;
10869 while (op
->type
!= type
)
10872 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10877 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10880 maxtiny
= 1 << op
->nbits
;
10885 maxtiny
= (1 << op
->nbits
) - 1;
10890 mintiny
= - (1 << (op
->nbits
- 1));
10891 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10894 /* We can't call S_GET_VALUE here, because we don't want to lock in
10895 a particular frag address. */
10896 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10898 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10899 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10900 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10902 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10903 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10906 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10907 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10908 + fragp
->fr_symbol
->sy_value
.X_add_number
10909 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10910 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10919 /* We won't have the section when we are called from
10920 mips_relax_frag. However, we will always have been called
10921 from md_estimate_size_before_relax first. If this is a
10922 branch to a different section, we mark it as such. If SEC is
10923 NULL, and the frag is not marked, then it must be a branch to
10924 the same section. */
10927 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10934 fragp
->fr_subtype
=
10935 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10937 /* FIXME: We should support this, and let the linker
10938 catch branches and loads that are out of range. */
10939 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10940 "unsupported PC relative reference to different section");
10946 /* In this case, we know for sure that the symbol fragment is in
10947 the same section. If the fr_address of the symbol fragment
10948 is greater then the address of this fragment we want to add
10949 in STRETCH in order to get a better estimate of the address.
10950 This particularly matters because of the shift bits. */
10952 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10956 /* Adjust stretch for any alignment frag. Note that if have
10957 been expanding the earlier code, the symbol may be
10958 defined in what appears to be an earlier frag. FIXME:
10959 This doesn't handle the fr_subtype field, which specifies
10960 a maximum number of bytes to skip when doing an
10963 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10966 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10969 stretch
= - ((- stretch
)
10970 & ~ ((1 << (int) f
->fr_offset
) - 1));
10972 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10981 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10983 /* The base address rules are complicated. The base address of
10984 a branch is the following instruction. The base address of a
10985 PC relative load or add is the instruction itself, but if it
10986 is in a delay slot (in which case it can not be extended) use
10987 the address of the instruction whose delay slot it is in. */
10988 if (type
== 'p' || type
== 'q')
10992 /* If we are currently assuming that this frag should be
10993 extended, then, the current address is two bytes
10995 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10998 /* Ignore the low bit in the target, since it will be set
10999 for a text label. */
11000 if ((val
& 1) != 0)
11003 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11005 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11008 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11010 /* Branch offsets have an implicit 0 in the lowest bit. */
11011 if (type
== 'p' || type
== 'q')
11014 /* If any of the shifted bits are set, we must use an extended
11015 opcode. If the address depends on the size of this
11016 instruction, this can lead to a loop, so we arrange to always
11017 use an extended opcode. We only check this when we are in
11018 the main relaxation loop, when SEC is NULL. */
11019 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11021 fragp
->fr_subtype
=
11022 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11026 /* If we are about to mark a frag as extended because the value
11027 is precisely maxtiny + 1, then there is a chance of an
11028 infinite loop as in the following code:
11033 In this case when the la is extended, foo is 0x3fc bytes
11034 away, so the la can be shrunk, but then foo is 0x400 away, so
11035 the la must be extended. To avoid this loop, we mark the
11036 frag as extended if it was small, and is about to become
11037 extended with a value of maxtiny + 1. */
11038 if (val
== ((maxtiny
+ 1) << op
->shift
)
11039 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11042 fragp
->fr_subtype
=
11043 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11047 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11048 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
11050 if ((val
& ((1 << op
->shift
) - 1)) != 0
11051 || val
< (mintiny
<< op
->shift
)
11052 || val
> (maxtiny
<< op
->shift
))
11058 /* Estimate the size of a frag before relaxing. Unless this is the
11059 mips16, we are not really relaxing here, and the final size is
11060 encoded in the subtype information. For the mips16, we have to
11061 decide whether we are using an extended opcode or not. */
11065 md_estimate_size_before_relax (fragp
, segtype
)
11071 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11073 if (mips16_extended_frag (fragp
, segtype
, 0))
11075 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11080 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11085 if (mips_pic
== NO_PIC
)
11087 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11089 else if (mips_pic
== SVR4_PIC
)
11094 sym
= fragp
->fr_symbol
;
11096 /* Handle the case of a symbol equated to another symbol. */
11097 while (sym
->sy_value
.X_op
== O_symbol
11098 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11102 /* It's possible to get a loop here in a badly written
11104 n
= sym
->sy_value
.X_add_symbol
;
11110 symsec
= S_GET_SEGMENT (sym
);
11112 /* This must duplicate the test in adjust_reloc_syms. */
11113 change
= (symsec
!= &bfd_und_section
11114 && symsec
!= &bfd_abs_section
11115 && ! bfd_is_com_section (symsec
));
11122 /* Record the offset to the first reloc in the fr_opcode field.
11123 This lets md_convert_frag and tc_gen_reloc know that the code
11124 must be expanded. */
11125 fragp
->fr_opcode
= (fragp
->fr_literal
11127 - RELAX_OLD (fragp
->fr_subtype
)
11128 + RELAX_RELOC1 (fragp
->fr_subtype
));
11129 /* FIXME: This really needs as_warn_where. */
11130 if (RELAX_WARN (fragp
->fr_subtype
))
11131 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
11137 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11140 /* This is called to see whether a reloc against a defined symbol
11141 should be converted into a reloc against a section. Don't adjust
11142 MIPS16 jump relocations, so we don't have to worry about the format
11143 of the offset in the .o file. Don't adjust relocations against
11144 mips16 symbols, so that the linker can find them if it needs to set
11148 mips_fix_adjustable (fixp
)
11151 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11153 if (fixp
->fx_addsy
== NULL
)
11156 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11157 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11158 && fixp
->fx_subsy
== NULL
)
11164 /* Translate internal representation of relocation info to BFD target
11168 tc_gen_reloc (section
, fixp
)
11172 static arelent
*retval
[4];
11174 bfd_reloc_code_real_type code
;
11176 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11179 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11180 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11182 if (mips_pic
== EMBEDDED_PIC
11183 && SWITCH_TABLE (fixp
))
11185 /* For a switch table entry we use a special reloc. The addend
11186 is actually the difference between the reloc address and the
11188 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11189 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11190 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
11191 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11193 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11195 /* We use a special addend for an internal RELLO reloc. */
11196 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11197 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11199 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11201 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11203 assert (fixp
->fx_next
!= NULL
11204 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11205 /* We use a special addend for an internal RELHI reloc. The
11206 reloc is relative to the RELLO; adjust the addend
11208 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11209 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11210 + fixp
->fx_next
->fx_where
11211 - S_GET_VALUE (fixp
->fx_subsy
));
11213 reloc
->addend
= (fixp
->fx_addnumber
11214 + fixp
->fx_next
->fx_frag
->fr_address
11215 + fixp
->fx_next
->fx_where
);
11217 else if (fixp
->fx_pcrel
== 0)
11218 reloc
->addend
= fixp
->fx_addnumber
;
11221 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11222 /* A gruesome hack which is a result of the gruesome gas reloc
11224 reloc
->addend
= reloc
->address
;
11226 reloc
->addend
= -reloc
->address
;
11229 /* If this is a variant frag, we may need to adjust the existing
11230 reloc and generate a new one. */
11231 if (fixp
->fx_frag
->fr_opcode
!= NULL
11232 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11233 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11234 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11235 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11236 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11237 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11238 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11242 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11244 /* If this is not the last reloc in this frag, then we have two
11245 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11246 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11247 the second one handle all of them. */
11248 if (fixp
->fx_next
!= NULL
11249 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11251 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11252 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11253 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11254 && (fixp
->fx_next
->fx_r_type
11255 == BFD_RELOC_MIPS_GOT_LO16
))
11256 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11257 && (fixp
->fx_next
->fx_r_type
11258 == BFD_RELOC_MIPS_CALL_LO16
)));
11263 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11264 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11265 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11267 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11268 reloc2
->address
= (reloc
->address
11269 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11270 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11271 reloc2
->addend
= fixp
->fx_addnumber
;
11272 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11273 assert (reloc2
->howto
!= NULL
);
11275 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11279 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11282 reloc3
->address
+= 4;
11285 if (mips_pic
== NO_PIC
)
11287 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11288 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11290 else if (mips_pic
== SVR4_PIC
)
11292 switch (fixp
->fx_r_type
)
11296 case BFD_RELOC_MIPS_GOT16
:
11298 case BFD_RELOC_MIPS_CALL16
:
11299 case BFD_RELOC_MIPS_GOT_LO16
:
11300 case BFD_RELOC_MIPS_CALL_LO16
:
11301 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11309 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11310 fixup_segment converted a non-PC relative reloc into a PC
11311 relative reloc. In such a case, we need to convert the reloc
11313 code
= fixp
->fx_r_type
;
11314 if (fixp
->fx_pcrel
)
11319 code
= BFD_RELOC_8_PCREL
;
11322 code
= BFD_RELOC_16_PCREL
;
11325 code
= BFD_RELOC_32_PCREL
;
11328 code
= BFD_RELOC_64_PCREL
;
11330 case BFD_RELOC_8_PCREL
:
11331 case BFD_RELOC_16_PCREL
:
11332 case BFD_RELOC_32_PCREL
:
11333 case BFD_RELOC_64_PCREL
:
11334 case BFD_RELOC_16_PCREL_S2
:
11335 case BFD_RELOC_PCREL_HI16_S
:
11336 case BFD_RELOC_PCREL_LO16
:
11339 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11340 "Cannot make %s relocation PC relative",
11341 bfd_get_reloc_code_name (code
));
11345 /* To support a PC relative reloc when generating embedded PIC code
11346 for ECOFF, we use a Cygnus extension. We check for that here to
11347 make sure that we don't let such a reloc escape normally. */
11348 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11349 && code
== BFD_RELOC_16_PCREL_S2
11350 && mips_pic
!= EMBEDDED_PIC
)
11351 reloc
->howto
= NULL
;
11353 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11355 if (reloc
->howto
== NULL
)
11357 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11358 "Can not represent %s relocation in this object file format",
11359 bfd_get_reloc_code_name (code
));
11366 /* Relax a machine dependent frag. This returns the amount by which
11367 the current size of the frag should change. */
11370 mips_relax_frag (fragp
, stretch
)
11374 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11377 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11379 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11381 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11386 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11388 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11395 /* Convert a machine dependent frag. */
11398 md_convert_frag (abfd
, asec
, fragp
)
11406 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11409 register const struct mips16_immed_operand
*op
;
11410 boolean small
, ext
;
11413 unsigned long insn
;
11414 boolean use_extend
;
11415 unsigned short extend
;
11417 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11418 op
= mips16_immed_operands
;
11419 while (op
->type
!= type
)
11422 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11433 resolve_symbol_value (fragp
->fr_symbol
, 1);
11434 val
= S_GET_VALUE (fragp
->fr_symbol
);
11439 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11441 /* The rules for the base address of a PC relative reloc are
11442 complicated; see mips16_extended_frag. */
11443 if (type
== 'p' || type
== 'q')
11448 /* Ignore the low bit in the target, since it will be
11449 set for a text label. */
11450 if ((val
& 1) != 0)
11453 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11455 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11458 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11461 /* Make sure the section winds up with the alignment we have
11464 record_alignment (asec
, op
->shift
);
11468 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11469 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11470 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11471 "extended instruction in delay slot");
11473 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11475 if (target_big_endian
)
11476 insn
= bfd_getb16 (buf
);
11478 insn
= bfd_getl16 (buf
);
11480 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11481 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11482 small
, ext
, &insn
, &use_extend
, &extend
);
11486 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11487 fragp
->fr_fix
+= 2;
11491 md_number_to_chars (buf
, insn
, 2);
11492 fragp
->fr_fix
+= 2;
11497 if (fragp
->fr_opcode
== NULL
)
11500 old
= RELAX_OLD (fragp
->fr_subtype
);
11501 new = RELAX_NEW (fragp
->fr_subtype
);
11502 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11505 memcpy (fixptr
- old
, fixptr
, new);
11507 fragp
->fr_fix
+= new - old
;
11513 /* This function is called after the relocs have been generated.
11514 We've been storing mips16 text labels as odd. Here we convert them
11515 back to even for the convenience of the debugger. */
11518 mips_frob_file_after_relocs ()
11521 unsigned int count
, i
;
11523 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11526 syms
= bfd_get_outsymbols (stdoutput
);
11527 count
= bfd_get_symcount (stdoutput
);
11528 for (i
= 0; i
< count
; i
++, syms
++)
11530 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11531 && ((*syms
)->value
& 1) != 0)
11533 (*syms
)->value
&= ~1;
11534 /* If the symbol has an odd size, it was probably computed
11535 incorrectly, so adjust that as well. */
11536 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11537 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11544 /* This function is called whenever a label is defined. It is used
11545 when handling branch delays; if a branch has a label, we assume we
11546 can not move it. */
11549 mips_define_label (sym
)
11552 struct insn_label_list
*l
;
11554 if (free_insn_labels
== NULL
)
11555 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11558 l
= free_insn_labels
;
11559 free_insn_labels
= l
->next
;
11563 l
->next
= insn_labels
;
11567 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11569 /* Some special processing for a MIPS ELF file. */
11572 mips_elf_final_processing ()
11574 /* Write out the register information. */
11579 s
.ri_gprmask
= mips_gprmask
;
11580 s
.ri_cprmask
[0] = mips_cprmask
[0];
11581 s
.ri_cprmask
[1] = mips_cprmask
[1];
11582 s
.ri_cprmask
[2] = mips_cprmask
[2];
11583 s
.ri_cprmask
[3] = mips_cprmask
[3];
11584 /* The gp_value field is set by the MIPS ELF backend. */
11586 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11587 ((Elf32_External_RegInfo
*)
11588 mips_regmask_frag
));
11592 Elf64_Internal_RegInfo s
;
11594 s
.ri_gprmask
= mips_gprmask
;
11596 s
.ri_cprmask
[0] = mips_cprmask
[0];
11597 s
.ri_cprmask
[1] = mips_cprmask
[1];
11598 s
.ri_cprmask
[2] = mips_cprmask
[2];
11599 s
.ri_cprmask
[3] = mips_cprmask
[3];
11600 /* The gp_value field is set by the MIPS ELF backend. */
11602 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11603 ((Elf64_External_RegInfo
*)
11604 mips_regmask_frag
));
11607 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11608 sort of BFD interface for this. */
11609 if (mips_any_noreorder
)
11610 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11611 if (mips_pic
!= NO_PIC
)
11612 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11615 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11617 /* These functions should really be defined by the object file format,
11618 since they are related to debugging information. However, this
11619 code has to work for the a.out format, which does not define them,
11620 so we provide simple versions here. These don't actually generate
11621 any debugging information, but they do simple checking and someday
11622 somebody may make them useful. */
11626 struct loc
*loc_next
;
11627 unsigned long loc_fileno
;
11628 unsigned long loc_lineno
;
11629 unsigned long loc_offset
;
11630 unsigned short loc_delta
;
11631 unsigned short loc_count
;
11638 typedef struct proc
11640 struct proc
*proc_next
;
11641 struct symbol
*proc_isym
;
11642 struct symbol
*proc_end
;
11643 unsigned long proc_reg_mask
;
11644 unsigned long proc_reg_offset
;
11645 unsigned long proc_fpreg_mask
;
11646 unsigned long proc_fpreg_offset
;
11647 unsigned long proc_frameoffset
;
11648 unsigned long proc_framereg
;
11649 unsigned long proc_pcreg
;
11651 struct file
*proc_file
;
11656 typedef struct file
11658 struct file
*file_next
;
11659 unsigned long file_fileno
;
11660 struct symbol
*file_symbol
;
11661 struct symbol
*file_end
;
11662 struct proc
*file_proc
;
11667 static struct obstack proc_frags
;
11668 static procS
*proc_lastP
;
11669 static procS
*proc_rootP
;
11670 static int numprocs
;
11675 obstack_begin (&proc_frags
, 0x2000);
11681 /* check for premature end, nesting errors, etc */
11682 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11683 as_warn ("missing `.end' at end of assembly");
11692 if (*input_line_pointer
== '-')
11694 ++input_line_pointer
;
11697 if (!isdigit (*input_line_pointer
))
11698 as_bad ("Expected simple number.");
11699 if (input_line_pointer
[0] == '0')
11701 if (input_line_pointer
[1] == 'x')
11703 input_line_pointer
+= 2;
11704 while (isxdigit (*input_line_pointer
))
11707 val
|= hex_value (*input_line_pointer
++);
11709 return negative
? -val
: val
;
11713 ++input_line_pointer
;
11714 while (isdigit (*input_line_pointer
))
11717 val
|= *input_line_pointer
++ - '0';
11719 return negative
? -val
: val
;
11722 if (!isdigit (*input_line_pointer
))
11724 printf (" *input_line_pointer == '%c' 0x%02x\n",
11725 *input_line_pointer
, *input_line_pointer
);
11726 as_warn ("Invalid number");
11729 while (isdigit (*input_line_pointer
))
11732 val
+= *input_line_pointer
++ - '0';
11734 return negative
? -val
: val
;
11737 /* The .file directive; just like the usual .file directive, but there
11738 is an initial number which is the ECOFF file index. */
11746 line
= get_number ();
11751 /* The .end directive. */
11759 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11762 demand_empty_rest_of_line ();
11766 if (now_seg
!= text_section
)
11767 as_warn (".end not in text section");
11770 as_warn (".end and no .ent seen yet.");
11776 assert (S_GET_NAME (p
));
11777 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
11778 as_warn (".end symbol does not match .ent symbol.");
11781 proc_lastP
->proc_end
= (symbolS
*) 1;
11784 /* The .aent and .ent directives. */
11794 symbolP
= get_symbol ();
11795 if (*input_line_pointer
== ',')
11796 input_line_pointer
++;
11797 SKIP_WHITESPACE ();
11798 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11799 number
= get_number ();
11800 if (now_seg
!= text_section
)
11801 as_warn (".ent or .aent not in text section.");
11803 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11804 as_warn ("missing `.end'");
11808 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11809 procP
->proc_isym
= symbolP
;
11810 procP
->proc_reg_mask
= 0;
11811 procP
->proc_reg_offset
= 0;
11812 procP
->proc_fpreg_mask
= 0;
11813 procP
->proc_fpreg_offset
= 0;
11814 procP
->proc_frameoffset
= 0;
11815 procP
->proc_framereg
= 0;
11816 procP
->proc_pcreg
= 0;
11817 procP
->proc_end
= NULL
;
11818 procP
->proc_next
= NULL
;
11820 proc_lastP
->proc_next
= procP
;
11822 proc_rootP
= procP
;
11823 proc_lastP
= procP
;
11826 demand_empty_rest_of_line ();
11829 /* The .frame directive. */
11842 frame_reg
= tc_get_register (1);
11843 if (*input_line_pointer
== ',')
11844 input_line_pointer
++;
11845 frame_off
= get_absolute_expression ();
11846 if (*input_line_pointer
== ',')
11847 input_line_pointer
++;
11848 pcreg
= tc_get_register (0);
11850 /* bob third eye */
11851 assert (proc_rootP
);
11852 proc_rootP
->proc_framereg
= frame_reg
;
11853 proc_rootP
->proc_frameoffset
= frame_off
;
11854 proc_rootP
->proc_pcreg
= pcreg
;
11855 /* bob macho .frame */
11857 /* We don't have to write out a frame stab for unoptimized code. */
11858 if (!(frame_reg
== FP
&& frame_off
== 0))
11861 as_warn ("No .ent for .frame to use.");
11862 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11863 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11864 S_SET_TYPE (symP
, N_RMASK
);
11865 S_SET_OTHER (symP
, 0);
11866 S_SET_DESC (symP
, 0);
11867 symP
->sy_forward
= proc_lastP
->proc_isym
;
11868 /* bob perhaps I should have used pseudo set */
11870 demand_empty_rest_of_line ();
11874 /* The .fmask and .mask directives. */
11881 char str
[100], *strP
;
11887 mask
= get_number ();
11888 if (*input_line_pointer
== ',')
11889 input_line_pointer
++;
11890 off
= get_absolute_expression ();
11892 /* bob only for coff */
11893 assert (proc_rootP
);
11894 if (reg_type
== 'F')
11896 proc_rootP
->proc_fpreg_mask
= mask
;
11897 proc_rootP
->proc_fpreg_offset
= off
;
11901 proc_rootP
->proc_reg_mask
= mask
;
11902 proc_rootP
->proc_reg_offset
= off
;
11905 /* bob macho .mask + .fmask */
11907 /* We don't have to write out a mask stab if no saved regs. */
11911 as_warn ("No .ent for .mask to use.");
11913 for (i
= 0; i
< 32; i
++)
11917 sprintf (strP
, "%c%d,", reg_type
, i
);
11918 strP
+= strlen (strP
);
11922 sprintf (strP
, ";%d,", off
);
11923 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11924 S_SET_TYPE (symP
, N_RMASK
);
11925 S_SET_OTHER (symP
, 0);
11926 S_SET_DESC (symP
, 0);
11927 symP
->sy_forward
= proc_lastP
->proc_isym
;
11928 /* bob perhaps I should have used pseudo set */
11933 /* The .loc directive. */
11944 assert (now_seg
== text_section
);
11946 lineno
= get_number ();
11947 addroff
= frag_now_fix ();
11949 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11950 S_SET_TYPE (symbolP
, N_SLINE
);
11951 S_SET_OTHER (symbolP
, 0);
11952 S_SET_DESC (symbolP
, lineno
);
11953 symbolP
->sy_segment
= now_seg
;