1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
36 #include "dw2gencfi.h"
39 #define DBG(x) printf x
45 /* Clean up namespace so we can include obj-elf.h too. */
46 static int mips_output_flavor (void);
47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
48 #undef OBJ_PROCESS_STAB
55 #undef obj_frob_file_after_relocs
56 #undef obj_frob_symbol
58 #undef obj_sec_sym_ok_for_reloc
59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
62 /* Fix any of them that we actually care about. */
64 #define OUTPUT_FLAVOR mips_output_flavor()
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
76 int mips_flag_mdebug
= -1;
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
82 int mips_flag_pdr
= FALSE
;
84 int mips_flag_pdr
= TRUE
;
89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
90 static char *mips_regmask_frag
;
96 #define PIC_CALL_REG 25
104 #define ILLEGAL_REG (32)
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
199 /* Whether we are assembling for the mips16 processor. 0 if we are
200 not, 1 if we are, and -1 if the value has not been initialized.
201 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
202 -nomips16 command line options, and the default CPU. */
204 /* Non-zero if we should not reorder instructions. Changed by `.set
205 reorder' and `.set noreorder'. */
207 /* Non-zero if we should not permit the $at ($1) register to be used
208 in instructions. Changed by `.set at' and `.set noat'. */
210 /* Non-zero if we should warn when a macro instruction expands into
211 more than one machine instruction. Changed by `.set nomacro' and
213 int warn_about_macros
;
214 /* Non-zero if we should not move instructions. Changed by `.set
215 move', `.set volatile', `.set nomove', and `.set novolatile'. */
217 /* Non-zero if we should not optimize branches by moving the target
218 of the branch into the delay slot. Actually, we don't perform
219 this optimization anyhow. Changed by `.set bopt' and `.set
222 /* Non-zero if we should not autoextend mips16 instructions.
223 Changed by `.set autoextend' and `.set noautoextend'. */
225 /* Restrict general purpose registers and floating point registers
226 to 32 bit. This is initially determined when -mgp32 or -mfp32
227 is passed but can changed if the assembler code uses .set mipsN. */
230 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
231 command line option, and the default CPU. */
233 /* True if ".set sym32" is in effect. */
237 /* True if -mgp32 was passed. */
238 static int file_mips_gp32
= -1;
240 /* True if -mfp32 was passed. */
241 static int file_mips_fp32
= -1;
243 /* This is the struct we use to hold the current set of options. Note
244 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
245 -1 to indicate that they have not been initialized. */
247 static struct mips_set_options mips_opts
=
249 ISA_UNKNOWN
, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
252 /* These variables are filled in with the masks of registers used.
253 The object format code reads them and puts them in the appropriate
255 unsigned long mips_gprmask
;
256 unsigned long mips_cprmask
[4];
258 /* MIPS ISA we are using for this output file. */
259 static int file_mips_isa
= ISA_UNKNOWN
;
261 /* True if -mips16 was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips16
;
265 /* True if -mips3d was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mips3d
;
269 /* True if -mdmx was passed or implied by arguments passed on the
270 command line (e.g., by -march). */
271 static int file_ase_mdmx
;
273 /* True if -msmartmips was passed or implied by arguments passed on the
274 command line (e.g., by -march). */
275 static int file_ase_smartmips
;
277 #define ISA_SUPPORT_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
278 || mips_opts.isa == ISA_MIPS32R2)
280 /* True if -mdsp was passed or implied by arguments passed on the
281 command line (e.g., by -march). */
282 static int file_ase_dsp
;
284 /* True if -mmt was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mt
;
288 /* The argument of the -march= flag. The architecture we are assembling. */
289 static int file_mips_arch
= CPU_UNKNOWN
;
290 static const char *mips_arch_string
;
292 /* The argument of the -mtune= flag. The architecture for which we
294 static int mips_tune
= CPU_UNKNOWN
;
295 static const char *mips_tune_string
;
297 /* True when generating 32-bit code for a 64-bit processor. */
298 static int mips_32bitmode
= 0;
300 /* True if the given ABI requires 32-bit registers. */
301 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
303 /* Likewise 64-bit registers. */
304 #define ABI_NEEDS_64BIT_REGS(ABI) \
306 || (ABI) == N64_ABI \
309 /* Return true if ISA supports 64 bit gp register instructions. */
310 #define ISA_HAS_64BIT_REGS(ISA) ( \
312 || (ISA) == ISA_MIPS4 \
313 || (ISA) == ISA_MIPS5 \
314 || (ISA) == ISA_MIPS64 \
315 || (ISA) == ISA_MIPS64R2 \
318 /* Return true if ISA supports 64-bit right rotate (dror et al.)
320 #define ISA_HAS_DROR(ISA) ( \
321 (ISA) == ISA_MIPS64R2 \
324 /* Return true if ISA supports 32-bit right rotate (ror et al.)
326 #define ISA_HAS_ROR(ISA) ( \
327 (ISA) == ISA_MIPS32R2 \
328 || (ISA) == ISA_MIPS64R2 \
329 || mips_opts.ase_smartmips \
332 #define HAVE_32BIT_GPRS \
333 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
335 #define HAVE_32BIT_FPRS \
336 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
338 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
339 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
341 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
343 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
345 /* True if relocations are stored in-place. */
346 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
348 /* The ABI-derived address size. */
349 #define HAVE_64BIT_ADDRESSES \
350 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
351 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
353 /* The size of symbolic constants (i.e., expressions of the form
354 "SYMBOL" or "SYMBOL + OFFSET"). */
355 #define HAVE_32BIT_SYMBOLS \
356 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
357 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
359 /* Addresses are loaded in different ways, depending on the address size
360 in use. The n32 ABI Documentation also mandates the use of additions
361 with overflow checking, but existing implementations don't follow it. */
362 #define ADDRESS_ADD_INSN \
363 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
365 #define ADDRESS_ADDI_INSN \
366 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
368 #define ADDRESS_LOAD_INSN \
369 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
371 #define ADDRESS_STORE_INSN \
372 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
374 /* Return true if the given CPU supports the MIPS16 ASE. */
375 #define CPU_HAS_MIPS16(cpu) \
376 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
377 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
379 /* Return true if the given CPU supports the MIPS3D ASE. */
380 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
383 /* Return true if the given CPU supports the MDMX ASE. */
384 #define CPU_HAS_MDMX(cpu) (FALSE \
387 /* Return true if the given CPU supports the DSP ASE. */
388 #define CPU_HAS_DSP(cpu) (FALSE \
391 /* Return true if the given CPU supports the MT ASE. */
392 #define CPU_HAS_MT(cpu) (FALSE \
395 /* True if CPU has a dror instruction. */
396 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
398 /* True if CPU has a ror instruction. */
399 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
401 /* True if mflo and mfhi can be immediately followed by instructions
402 which write to the HI and LO registers.
404 According to MIPS specifications, MIPS ISAs I, II, and III need
405 (at least) two instructions between the reads of HI/LO and
406 instructions which write them, and later ISAs do not. Contradicting
407 the MIPS specifications, some MIPS IV processor user manuals (e.g.
408 the UM for the NEC Vr5000) document needing the instructions between
409 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
410 MIPS64 and later ISAs to have the interlocks, plus any specific
411 earlier-ISA CPUs for which CPU documentation declares that the
412 instructions are really interlocked. */
413 #define hilo_interlocks \
414 (mips_opts.isa == ISA_MIPS32 \
415 || mips_opts.isa == ISA_MIPS32R2 \
416 || mips_opts.isa == ISA_MIPS64 \
417 || mips_opts.isa == ISA_MIPS64R2 \
418 || mips_opts.arch == CPU_R4010 \
419 || mips_opts.arch == CPU_R10000 \
420 || mips_opts.arch == CPU_R12000 \
421 || mips_opts.arch == CPU_RM7000 \
422 || mips_opts.arch == CPU_VR5500 \
425 /* Whether the processor uses hardware interlocks to protect reads
426 from the GPRs after they are loaded from memory, and thus does not
427 require nops to be inserted. This applies to instructions marked
428 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
430 #define gpr_interlocks \
431 (mips_opts.isa != ISA_MIPS1 \
432 || mips_opts.arch == CPU_R3900)
434 /* Whether the processor uses hardware interlocks to avoid delays
435 required by coprocessor instructions, and thus does not require
436 nops to be inserted. This applies to instructions marked
437 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
438 between instructions marked INSN_WRITE_COND_CODE and ones marked
439 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
440 levels I, II, and III. */
441 /* Itbl support may require additional care here. */
442 #define cop_interlocks \
443 ((mips_opts.isa != ISA_MIPS1 \
444 && mips_opts.isa != ISA_MIPS2 \
445 && mips_opts.isa != ISA_MIPS3) \
446 || mips_opts.arch == CPU_R4300 \
449 /* Whether the processor uses hardware interlocks to protect reads
450 from coprocessor registers after they are loaded from memory, and
451 thus does not require nops to be inserted. This applies to
452 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
453 requires at MIPS ISA level I. */
454 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
456 /* Is this a mfhi or mflo instruction? */
457 #define MF_HILO_INSN(PINFO) \
458 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
460 /* MIPS PIC level. */
462 enum mips_pic_level mips_pic
;
464 /* 1 if we should generate 32 bit offsets from the $gp register in
465 SVR4_PIC mode. Currently has no meaning in other modes. */
466 static int mips_big_got
= 0;
468 /* 1 if trap instructions should used for overflow rather than break
470 static int mips_trap
= 0;
472 /* 1 if double width floating point constants should not be constructed
473 by assembling two single width halves into two single width floating
474 point registers which just happen to alias the double width destination
475 register. On some architectures this aliasing can be disabled by a bit
476 in the status register, and the setting of this bit cannot be determined
477 automatically at assemble time. */
478 static int mips_disable_float_construction
;
480 /* Non-zero if any .set noreorder directives were used. */
482 static int mips_any_noreorder
;
484 /* Non-zero if nops should be inserted when the register referenced in
485 an mfhi/mflo instruction is read in the next two instructions. */
486 static int mips_7000_hilo_fix
;
488 /* The size of the small data section. */
489 static unsigned int g_switch_value
= 8;
490 /* Whether the -G option was used. */
491 static int g_switch_seen
= 0;
496 /* If we can determine in advance that GP optimization won't be
497 possible, we can skip the relaxation stuff that tries to produce
498 GP-relative references. This makes delay slot optimization work
501 This function can only provide a guess, but it seems to work for
502 gcc output. It needs to guess right for gcc, otherwise gcc
503 will put what it thinks is a GP-relative instruction in a branch
506 I don't know if a fix is needed for the SVR4_PIC mode. I've only
507 fixed it for the non-PIC mode. KR 95/04/07 */
508 static int nopic_need_relax (symbolS
*, int);
510 /* handle of the OPCODE hash table */
511 static struct hash_control
*op_hash
= NULL
;
513 /* The opcode hash table we use for the mips16. */
514 static struct hash_control
*mips16_op_hash
= NULL
;
516 /* This array holds the chars that always start a comment. If the
517 pre-processor is disabled, these aren't very useful */
518 const char comment_chars
[] = "#";
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output */
523 /* Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output. */
526 /* Also note that C style comments are always supported. */
527 const char line_comment_chars
[] = "#";
529 /* This array holds machine specific line separator characters. */
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point nums */
533 const char EXP_CHARS
[] = "eE";
535 /* Chars that mean this number is a floating point constant */
538 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
540 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
541 changed in read.c . Ideally it shouldn't have to know about it at all,
542 but nothing is ideal around here.
545 static char *insn_error
;
547 static int auto_align
= 1;
549 /* When outputting SVR4 PIC code, the assembler needs to know the
550 offset in the stack frame from which to restore the $gp register.
551 This is set by the .cprestore pseudo-op, and saved in this
553 static offsetT mips_cprestore_offset
= -1;
555 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
556 more optimizations, it can use a register value instead of a memory-saved
557 offset and even an other register than $gp as global pointer. */
558 static offsetT mips_cpreturn_offset
= -1;
559 static int mips_cpreturn_register
= -1;
560 static int mips_gp_register
= GP
;
561 static int mips_gprel_offset
= 0;
563 /* Whether mips_cprestore_offset has been set in the current function
564 (or whether it has already been warned about, if not). */
565 static int mips_cprestore_valid
= 0;
567 /* This is the register which holds the stack frame, as set by the
568 .frame pseudo-op. This is needed to implement .cprestore. */
569 static int mips_frame_reg
= SP
;
571 /* Whether mips_frame_reg has been set in the current function
572 (or whether it has already been warned about, if not). */
573 static int mips_frame_reg_valid
= 0;
575 /* To output NOP instructions correctly, we need to keep information
576 about the previous two instructions. */
578 /* Whether we are optimizing. The default value of 2 means to remove
579 unneeded NOPs and swap branch instructions when possible. A value
580 of 1 means to not swap branches. A value of 0 means to always
582 static int mips_optimize
= 2;
584 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
585 equivalent to seeing no -g option at all. */
586 static int mips_debug
= 0;
588 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
589 #define MAX_VR4130_NOPS 4
591 /* The maximum number of NOPs needed to fill delay slots. */
592 #define MAX_DELAY_NOPS 2
594 /* The maximum number of NOPs needed for any purpose. */
597 /* A list of previous instructions, with index 0 being the most recent.
598 We need to look back MAX_NOPS instructions when filling delay slots
599 or working around processor errata. We need to look back one
600 instruction further if we're thinking about using history[0] to
601 fill a branch delay slot. */
602 static struct mips_cl_insn history
[1 + MAX_NOPS
];
604 /* Nop instructions used by emit_nop. */
605 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
607 /* The appropriate nop for the current mode. */
608 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
610 /* If this is set, it points to a frag holding nop instructions which
611 were inserted before the start of a noreorder section. If those
612 nops turn out to be unnecessary, the size of the frag can be
614 static fragS
*prev_nop_frag
;
616 /* The number of nop instructions we created in prev_nop_frag. */
617 static int prev_nop_frag_holds
;
619 /* The number of nop instructions that we know we need in
621 static int prev_nop_frag_required
;
623 /* The number of instructions we've seen since prev_nop_frag. */
624 static int prev_nop_frag_since
;
626 /* For ECOFF and ELF, relocations against symbols are done in two
627 parts, with a HI relocation and a LO relocation. Each relocation
628 has only 16 bits of space to store an addend. This means that in
629 order for the linker to handle carries correctly, it must be able
630 to locate both the HI and the LO relocation. This means that the
631 relocations must appear in order in the relocation table.
633 In order to implement this, we keep track of each unmatched HI
634 relocation. We then sort them so that they immediately precede the
635 corresponding LO relocation. */
640 struct mips_hi_fixup
*next
;
643 /* The section this fixup is in. */
647 /* The list of unmatched HI relocs. */
649 static struct mips_hi_fixup
*mips_hi_fixup_list
;
651 /* The frag containing the last explicit relocation operator.
652 Null if explicit relocations have not been used. */
654 static fragS
*prev_reloc_op_frag
;
656 /* Map normal MIPS register numbers to mips16 register numbers. */
658 #define X ILLEGAL_REG
659 static const int mips32_to_16_reg_map
[] =
661 X
, X
, 2, 3, 4, 5, 6, 7,
662 X
, X
, X
, X
, X
, X
, X
, X
,
663 0, 1, X
, X
, X
, X
, X
, X
,
664 X
, X
, X
, X
, X
, X
, X
, X
668 /* Map mips16 register numbers to normal MIPS register numbers. */
670 static const unsigned int mips16_to_32_reg_map
[] =
672 16, 17, 2, 3, 4, 5, 6, 7
675 /* Classifies the kind of instructions we're interested in when
676 implementing -mfix-vr4120. */
677 enum fix_vr4120_class
{
684 NUM_FIX_VR4120_CLASSES
687 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
688 there must be at least one other instruction between an instruction
689 of type X and an instruction of type Y. */
690 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
692 /* True if -mfix-vr4120 is in force. */
693 static int mips_fix_vr4120
;
695 /* ...likewise -mfix-vr4130. */
696 static int mips_fix_vr4130
;
698 /* We don't relax branches by default, since this causes us to expand
699 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
700 fail to compute the offset before expanding the macro to the most
701 efficient expansion. */
703 static int mips_relax_branch
;
705 /* The expansion of many macros depends on the type of symbol that
706 they refer to. For example, when generating position-dependent code,
707 a macro that refers to a symbol may have two different expansions,
708 one which uses GP-relative addresses and one which uses absolute
709 addresses. When generating SVR4-style PIC, a macro may have
710 different expansions for local and global symbols.
712 We handle these situations by generating both sequences and putting
713 them in variant frags. In position-dependent code, the first sequence
714 will be the GP-relative one and the second sequence will be the
715 absolute one. In SVR4 PIC, the first sequence will be for global
716 symbols and the second will be for local symbols.
718 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
719 SECOND are the lengths of the two sequences in bytes. These fields
720 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
721 the subtype has the following flags:
724 Set if it has been decided that we should use the second
725 sequence instead of the first.
728 Set in the first variant frag if the macro's second implementation
729 is longer than its first. This refers to the macro as a whole,
730 not an individual relaxation.
733 Set in the first variant frag if the macro appeared in a .set nomacro
734 block and if one alternative requires a warning but the other does not.
737 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
740 The frag's "opcode" points to the first fixup for relaxable code.
742 Relaxable macros are generated using a sequence such as:
744 relax_start (SYMBOL);
745 ... generate first expansion ...
747 ... generate second expansion ...
750 The code and fixups for the unwanted alternative are discarded
751 by md_convert_frag. */
752 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
754 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
755 #define RELAX_SECOND(X) ((X) & 0xff)
756 #define RELAX_USE_SECOND 0x10000
757 #define RELAX_SECOND_LONGER 0x20000
758 #define RELAX_NOMACRO 0x40000
759 #define RELAX_DELAY_SLOT 0x80000
761 /* Branch without likely bit. If label is out of range, we turn:
763 beq reg1, reg2, label
773 with the following opcode replacements:
780 bltzal <-> bgezal (with jal label instead of j label)
782 Even though keeping the delay slot instruction in the delay slot of
783 the branch would be more efficient, it would be very tricky to do
784 correctly, because we'd have to introduce a variable frag *after*
785 the delay slot instruction, and expand that instead. Let's do it
786 the easy way for now, even if the branch-not-taken case now costs
787 one additional instruction. Out-of-range branches are not supposed
788 to be common, anyway.
790 Branch likely. If label is out of range, we turn:
792 beql reg1, reg2, label
793 delay slot (annulled if branch not taken)
802 delay slot (executed only if branch taken)
805 It would be possible to generate a shorter sequence by losing the
806 likely bit, generating something like:
811 delay slot (executed only if branch taken)
823 bltzall -> bgezal (with jal label instead of j label)
824 bgezall -> bltzal (ditto)
827 but it's not clear that it would actually improve performance. */
828 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
831 | ((toofar) ? 1 : 0) \
833 | ((likely) ? 4 : 0) \
834 | ((uncond) ? 8 : 0)))
835 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
836 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
837 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
838 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
839 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
841 /* For mips16 code, we use an entirely different form of relaxation.
842 mips16 supports two versions of most instructions which take
843 immediate values: a small one which takes some small value, and a
844 larger one which takes a 16 bit value. Since branches also follow
845 this pattern, relaxing these values is required.
847 We can assemble both mips16 and normal MIPS code in a single
848 object. Therefore, we need to support this type of relaxation at
849 the same time that we support the relaxation described above. We
850 use the high bit of the subtype field to distinguish these cases.
852 The information we store for this type of relaxation is the
853 argument code found in the opcode file for this relocation, whether
854 the user explicitly requested a small or extended form, and whether
855 the relocation is in a jump or jal delay slot. That tells us the
856 size of the value, and how it should be stored. We also store
857 whether the fragment is considered to be extended or not. We also
858 store whether this is known to be a branch to a different section,
859 whether we have tried to relax this frag yet, and whether we have
860 ever extended a PC relative fragment because of a shift count. */
861 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
864 | ((small) ? 0x100 : 0) \
865 | ((ext) ? 0x200 : 0) \
866 | ((dslot) ? 0x400 : 0) \
867 | ((jal_dslot) ? 0x800 : 0))
868 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
869 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
870 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
871 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
872 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
873 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
874 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
875 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
876 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
877 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
878 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
879 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
881 /* Is the given value a sign-extended 32-bit value? */
882 #define IS_SEXT_32BIT_NUM(x) \
883 (((x) &~ (offsetT) 0x7fffffff) == 0 \
884 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
886 /* Is the given value a sign-extended 16-bit value? */
887 #define IS_SEXT_16BIT_NUM(x) \
888 (((x) &~ (offsetT) 0x7fff) == 0 \
889 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
891 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
892 #define IS_ZEXT_32BIT_NUM(x) \
893 (((x) &~ (offsetT) 0xffffffff) == 0 \
894 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
896 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
897 VALUE << SHIFT. VALUE is evaluated exactly once. */
898 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
899 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
900 | (((VALUE) & (MASK)) << (SHIFT)))
902 /* Extract bits MASK << SHIFT from STRUCT and shift them right
904 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
905 (((STRUCT) >> (SHIFT)) & (MASK))
907 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
908 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
910 include/opcode/mips.h specifies operand fields using the macros
911 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
912 with "MIPS16OP" instead of "OP". */
913 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
914 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
915 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
916 INSERT_BITS ((INSN).insn_opcode, VALUE, \
917 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
919 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
920 #define EXTRACT_OPERAND(FIELD, INSN) \
921 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
922 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
923 EXTRACT_BITS ((INSN).insn_opcode, \
924 MIPS16OP_MASK_##FIELD, \
927 /* Global variables used when generating relaxable macros. See the
928 comment above RELAX_ENCODE for more details about how relaxation
931 /* 0 if we're not emitting a relaxable macro.
932 1 if we're emitting the first of the two relaxation alternatives.
933 2 if we're emitting the second alternative. */
936 /* The first relaxable fixup in the current frag. (In other words,
937 the first fixup that refers to relaxable code.) */
940 /* sizes[0] says how many bytes of the first alternative are stored in
941 the current frag. Likewise sizes[1] for the second alternative. */
942 unsigned int sizes
[2];
944 /* The symbol on which the choice of sequence depends. */
948 /* Global variables used to decide whether a macro needs a warning. */
950 /* True if the macro is in a branch delay slot. */
951 bfd_boolean delay_slot_p
;
953 /* For relaxable macros, sizes[0] is the length of the first alternative
954 in bytes and sizes[1] is the length of the second alternative.
955 For non-relaxable macros, both elements give the length of the
957 unsigned int sizes
[2];
959 /* The first variant frag for this macro. */
961 } mips_macro_warning
;
963 /* Prototypes for static functions. */
965 #define internalError() \
966 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
968 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
970 static void append_insn
971 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
972 static void mips_no_prev_insn (void);
973 static void mips16_macro_build
974 (expressionS
*, const char *, const char *, va_list);
975 static void load_register (int, expressionS
*, int);
976 static void macro_start (void);
977 static void macro_end (void);
978 static void macro (struct mips_cl_insn
* ip
);
979 static void mips16_macro (struct mips_cl_insn
* ip
);
980 #ifdef LOSING_COMPILER
981 static void macro2 (struct mips_cl_insn
* ip
);
983 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
984 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
985 static void mips16_immed
986 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
987 unsigned long *, bfd_boolean
*, unsigned short *);
988 static size_t my_getSmallExpression
989 (expressionS
*, bfd_reloc_code_real_type
*, char *);
990 static void my_getExpression (expressionS
*, char *);
991 static void s_align (int);
992 static void s_change_sec (int);
993 static void s_change_section (int);
994 static void s_cons (int);
995 static void s_float_cons (int);
996 static void s_mips_globl (int);
997 static void s_option (int);
998 static void s_mipsset (int);
999 static void s_abicalls (int);
1000 static void s_cpload (int);
1001 static void s_cpsetup (int);
1002 static void s_cplocal (int);
1003 static void s_cprestore (int);
1004 static void s_cpreturn (int);
1005 static void s_gpvalue (int);
1006 static void s_gpword (int);
1007 static void s_gpdword (int);
1008 static void s_cpadd (int);
1009 static void s_insn (int);
1010 static void md_obj_begin (void);
1011 static void md_obj_end (void);
1012 static void s_mips_ent (int);
1013 static void s_mips_end (int);
1014 static void s_mips_frame (int);
1015 static void s_mips_mask (int reg_type
);
1016 static void s_mips_stab (int);
1017 static void s_mips_weakext (int);
1018 static void s_mips_file (int);
1019 static void s_mips_loc (int);
1020 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1021 static int relaxed_branch_length (fragS
*, asection
*, int);
1022 static int validate_mips_insn (const struct mips_opcode
*);
1024 /* Table and functions used to map between CPU/ISA names, and
1025 ISA levels, and CPU numbers. */
1027 struct mips_cpu_info
1029 const char *name
; /* CPU or ISA name. */
1030 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
1031 int isa
; /* ISA level. */
1032 int cpu
; /* CPU number (default CPU if ISA). */
1035 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1036 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1037 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1041 The following pseudo-ops from the Kane and Heinrich MIPS book
1042 should be defined here, but are currently unsupported: .alias,
1043 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1045 The following pseudo-ops from the Kane and Heinrich MIPS book are
1046 specific to the type of debugging information being generated, and
1047 should be defined by the object format: .aent, .begin, .bend,
1048 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1051 The following pseudo-ops from the Kane and Heinrich MIPS book are
1052 not MIPS CPU specific, but are also not specific to the object file
1053 format. This file is probably the best place to define them, but
1054 they are not currently supported: .asm0, .endr, .lab, .repeat,
1057 static const pseudo_typeS mips_pseudo_table
[] =
1059 /* MIPS specific pseudo-ops. */
1060 {"option", s_option
, 0},
1061 {"set", s_mipsset
, 0},
1062 {"rdata", s_change_sec
, 'r'},
1063 {"sdata", s_change_sec
, 's'},
1064 {"livereg", s_ignore
, 0},
1065 {"abicalls", s_abicalls
, 0},
1066 {"cpload", s_cpload
, 0},
1067 {"cpsetup", s_cpsetup
, 0},
1068 {"cplocal", s_cplocal
, 0},
1069 {"cprestore", s_cprestore
, 0},
1070 {"cpreturn", s_cpreturn
, 0},
1071 {"gpvalue", s_gpvalue
, 0},
1072 {"gpword", s_gpword
, 0},
1073 {"gpdword", s_gpdword
, 0},
1074 {"cpadd", s_cpadd
, 0},
1075 {"insn", s_insn
, 0},
1077 /* Relatively generic pseudo-ops that happen to be used on MIPS
1079 {"asciiz", stringer
, 1},
1080 {"bss", s_change_sec
, 'b'},
1082 {"half", s_cons
, 1},
1083 {"dword", s_cons
, 3},
1084 {"weakext", s_mips_weakext
, 0},
1086 /* These pseudo-ops are defined in read.c, but must be overridden
1087 here for one reason or another. */
1088 {"align", s_align
, 0},
1089 {"byte", s_cons
, 0},
1090 {"data", s_change_sec
, 'd'},
1091 {"double", s_float_cons
, 'd'},
1092 {"float", s_float_cons
, 'f'},
1093 {"globl", s_mips_globl
, 0},
1094 {"global", s_mips_globl
, 0},
1095 {"hword", s_cons
, 1},
1097 {"long", s_cons
, 2},
1098 {"octa", s_cons
, 4},
1099 {"quad", s_cons
, 3},
1100 {"section", s_change_section
, 0},
1101 {"short", s_cons
, 1},
1102 {"single", s_float_cons
, 'f'},
1103 {"stabn", s_mips_stab
, 'n'},
1104 {"text", s_change_sec
, 't'},
1105 {"word", s_cons
, 2},
1107 { "extern", ecoff_directive_extern
, 0},
1112 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1114 /* These pseudo-ops should be defined by the object file format.
1115 However, a.out doesn't support them, so we have versions here. */
1116 {"aent", s_mips_ent
, 1},
1117 {"bgnb", s_ignore
, 0},
1118 {"end", s_mips_end
, 0},
1119 {"endb", s_ignore
, 0},
1120 {"ent", s_mips_ent
, 0},
1121 {"file", s_mips_file
, 0},
1122 {"fmask", s_mips_mask
, 'F'},
1123 {"frame", s_mips_frame
, 0},
1124 {"loc", s_mips_loc
, 0},
1125 {"mask", s_mips_mask
, 'R'},
1126 {"verstamp", s_ignore
, 0},
1130 extern void pop_insert (const pseudo_typeS
*);
1133 mips_pop_insert (void)
1135 pop_insert (mips_pseudo_table
);
1136 if (! ECOFF_DEBUGGING
)
1137 pop_insert (mips_nonecoff_pseudo_table
);
1140 /* Symbols labelling the current insn. */
1142 struct insn_label_list
1144 struct insn_label_list
*next
;
1148 static struct insn_label_list
*insn_labels
;
1149 static struct insn_label_list
*free_insn_labels
;
1151 static void mips_clear_insn_labels (void);
1154 mips_clear_insn_labels (void)
1156 register struct insn_label_list
**pl
;
1158 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1164 static char *expr_end
;
1166 /* Expressions which appear in instructions. These are set by
1169 static expressionS imm_expr
;
1170 static expressionS imm2_expr
;
1171 static expressionS offset_expr
;
1173 /* Relocs associated with imm_expr and offset_expr. */
1175 static bfd_reloc_code_real_type imm_reloc
[3]
1176 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1177 static bfd_reloc_code_real_type offset_reloc
[3]
1178 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1180 /* These are set by mips16_ip if an explicit extension is used. */
1182 static bfd_boolean mips16_small
, mips16_ext
;
1185 /* The pdr segment for per procedure frame/regmask info. Not used for
1188 static segT pdr_seg
;
1191 /* The default target format to use. */
1194 mips_target_format (void)
1196 switch (OUTPUT_FLAVOR
)
1198 case bfd_target_ecoff_flavour
:
1199 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1200 case bfd_target_coff_flavour
:
1202 case bfd_target_elf_flavour
:
1204 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1205 return (target_big_endian
1206 ? "elf32-bigmips-vxworks"
1207 : "elf32-littlemips-vxworks");
1210 /* This is traditional mips. */
1211 return (target_big_endian
1212 ? (HAVE_64BIT_OBJECTS
1213 ? "elf64-tradbigmips"
1215 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1216 : (HAVE_64BIT_OBJECTS
1217 ? "elf64-tradlittlemips"
1219 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1221 return (target_big_endian
1222 ? (HAVE_64BIT_OBJECTS
1225 ? "elf32-nbigmips" : "elf32-bigmips"))
1226 : (HAVE_64BIT_OBJECTS
1227 ? "elf64-littlemips"
1229 ? "elf32-nlittlemips" : "elf32-littlemips")));
1237 /* Return the length of instruction INSN. */
1239 static inline unsigned int
1240 insn_length (const struct mips_cl_insn
*insn
)
1242 if (!mips_opts
.mips16
)
1244 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1247 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1250 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1255 insn
->use_extend
= FALSE
;
1257 insn
->insn_opcode
= mo
->match
;
1260 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1261 insn
->fixp
[i
] = NULL
;
1262 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1263 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1264 insn
->mips16_absolute_jump_p
= 0;
1267 /* Install INSN at the location specified by its "frag" and "where" fields. */
1270 install_insn (const struct mips_cl_insn
*insn
)
1272 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1273 if (!mips_opts
.mips16
)
1274 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1275 else if (insn
->mips16_absolute_jump_p
)
1277 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1278 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1282 if (insn
->use_extend
)
1284 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1287 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1291 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1292 and install the opcode in the new location. */
1295 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1300 insn
->where
= where
;
1301 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1302 if (insn
->fixp
[i
] != NULL
)
1304 insn
->fixp
[i
]->fx_frag
= frag
;
1305 insn
->fixp
[i
]->fx_where
= where
;
1307 install_insn (insn
);
1310 /* Add INSN to the end of the output. */
1313 add_fixed_insn (struct mips_cl_insn
*insn
)
1315 char *f
= frag_more (insn_length (insn
));
1316 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1319 /* Start a variant frag and move INSN to the start of the variant part,
1320 marking it as fixed. The other arguments are as for frag_var. */
1323 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1324 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1326 frag_grow (max_chars
);
1327 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1329 frag_var (rs_machine_dependent
, max_chars
, var
,
1330 subtype
, symbol
, offset
, NULL
);
1333 /* Insert N copies of INSN into the history buffer, starting at
1334 position FIRST. Neither FIRST nor N need to be clipped. */
1337 insert_into_history (unsigned int first
, unsigned int n
,
1338 const struct mips_cl_insn
*insn
)
1340 if (mips_relax
.sequence
!= 2)
1344 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1346 history
[i
] = history
[i
- n
];
1352 /* Emit a nop instruction, recording it in the history buffer. */
1357 add_fixed_insn (NOP_INSN
);
1358 insert_into_history (0, 1, NOP_INSN
);
1361 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1362 the idea is to make it obvious at a glance that each errata is
1366 init_vr4120_conflicts (void)
1368 #define CONFLICT(FIRST, SECOND) \
1369 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1371 /* Errata 21 - [D]DIV[U] after [D]MACC */
1372 CONFLICT (MACC
, DIV
);
1373 CONFLICT (DMACC
, DIV
);
1375 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1376 CONFLICT (DMULT
, DMULT
);
1377 CONFLICT (DMULT
, DMACC
);
1378 CONFLICT (DMACC
, DMULT
);
1379 CONFLICT (DMACC
, DMACC
);
1381 /* Errata 24 - MT{LO,HI} after [D]MACC */
1382 CONFLICT (MACC
, MTHILO
);
1383 CONFLICT (DMACC
, MTHILO
);
1385 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1386 instruction is executed immediately after a MACC or DMACC
1387 instruction, the result of [either instruction] is incorrect." */
1388 CONFLICT (MACC
, MULT
);
1389 CONFLICT (MACC
, DMULT
);
1390 CONFLICT (DMACC
, MULT
);
1391 CONFLICT (DMACC
, DMULT
);
1393 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1394 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1395 DDIV or DDIVU instruction, the result of the MACC or
1396 DMACC instruction is incorrect.". */
1397 CONFLICT (DMULT
, MACC
);
1398 CONFLICT (DMULT
, DMACC
);
1399 CONFLICT (DIV
, MACC
);
1400 CONFLICT (DIV
, DMACC
);
1405 /* This function is called once, at assembler startup time. It should
1406 set up all the tables, etc. that the MD part of the assembler will need. */
1411 register const char *retval
= NULL
;
1415 if (mips_pic
!= NO_PIC
)
1417 if (g_switch_seen
&& g_switch_value
!= 0)
1418 as_bad (_("-G may not be used in position-independent code"));
1422 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1423 as_warn (_("Could not set architecture and machine"));
1425 op_hash
= hash_new ();
1427 for (i
= 0; i
< NUMOPCODES
;)
1429 const char *name
= mips_opcodes
[i
].name
;
1431 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1434 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1435 mips_opcodes
[i
].name
, retval
);
1436 /* Probably a memory allocation problem? Give up now. */
1437 as_fatal (_("Broken assembler. No assembly attempted."));
1441 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1443 if (!validate_mips_insn (&mips_opcodes
[i
]))
1445 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1447 create_insn (&nop_insn
, mips_opcodes
+ i
);
1448 nop_insn
.fixed_p
= 1;
1453 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1456 mips16_op_hash
= hash_new ();
1459 while (i
< bfd_mips16_num_opcodes
)
1461 const char *name
= mips16_opcodes
[i
].name
;
1463 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1465 as_fatal (_("internal: can't hash `%s': %s"),
1466 mips16_opcodes
[i
].name
, retval
);
1469 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1470 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1471 != mips16_opcodes
[i
].match
))
1473 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1474 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1477 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1479 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1480 mips16_nop_insn
.fixed_p
= 1;
1484 while (i
< bfd_mips16_num_opcodes
1485 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1489 as_fatal (_("Broken assembler. No assembly attempted."));
1491 /* We add all the general register names to the symbol table. This
1492 helps us detect invalid uses of them. */
1493 for (i
= 0; i
< 32; i
++)
1497 sprintf (buf
, "$%d", i
);
1498 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1499 &zero_address_frag
));
1501 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1502 &zero_address_frag
));
1503 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1504 &zero_address_frag
));
1505 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1506 &zero_address_frag
));
1507 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1508 &zero_address_frag
));
1509 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1510 &zero_address_frag
));
1511 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1512 &zero_address_frag
));
1513 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1514 &zero_address_frag
));
1515 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1516 &zero_address_frag
));
1517 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1518 &zero_address_frag
));
1520 /* If we don't add these register names to the symbol table, they
1521 may end up being added as regular symbols by operand(), and then
1522 make it to the object file as undefined in case they're not
1523 regarded as local symbols. They're local in o32, since `$' is a
1524 local symbol prefix, but not in n32 or n64. */
1525 for (i
= 0; i
< 8; i
++)
1529 sprintf (buf
, "$fcc%i", i
);
1530 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1531 &zero_address_frag
));
1534 mips_no_prev_insn ();
1537 mips_cprmask
[0] = 0;
1538 mips_cprmask
[1] = 0;
1539 mips_cprmask
[2] = 0;
1540 mips_cprmask
[3] = 0;
1542 /* set the default alignment for the text section (2**2) */
1543 record_alignment (text_section
, 2);
1545 bfd_set_gp_size (stdoutput
, g_switch_value
);
1547 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1549 /* On a native system other than VxWorks, sections must be aligned
1550 to 16 byte boundaries. When configured for an embedded ELF
1551 target, we don't bother. */
1552 if (strcmp (TARGET_OS
, "elf") != 0
1553 && strcmp (TARGET_OS
, "vxworks") != 0)
1555 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1556 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1557 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1560 /* Create a .reginfo section for register masks and a .mdebug
1561 section for debugging information. */
1569 subseg
= now_subseg
;
1571 /* The ABI says this section should be loaded so that the
1572 running program can access it. However, we don't load it
1573 if we are configured for an embedded target */
1574 flags
= SEC_READONLY
| SEC_DATA
;
1575 if (strcmp (TARGET_OS
, "elf") != 0)
1576 flags
|= SEC_ALLOC
| SEC_LOAD
;
1578 if (mips_abi
!= N64_ABI
)
1580 sec
= subseg_new (".reginfo", (subsegT
) 0);
1582 bfd_set_section_flags (stdoutput
, sec
, flags
);
1583 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1586 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1591 /* The 64-bit ABI uses a .MIPS.options section rather than
1592 .reginfo section. */
1593 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1594 bfd_set_section_flags (stdoutput
, sec
, flags
);
1595 bfd_set_section_alignment (stdoutput
, sec
, 3);
1598 /* Set up the option header. */
1600 Elf_Internal_Options opthdr
;
1603 opthdr
.kind
= ODK_REGINFO
;
1604 opthdr
.size
= (sizeof (Elf_External_Options
)
1605 + sizeof (Elf64_External_RegInfo
));
1608 f
= frag_more (sizeof (Elf_External_Options
));
1609 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1610 (Elf_External_Options
*) f
);
1612 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1617 if (ECOFF_DEBUGGING
)
1619 sec
= subseg_new (".mdebug", (subsegT
) 0);
1620 (void) bfd_set_section_flags (stdoutput
, sec
,
1621 SEC_HAS_CONTENTS
| SEC_READONLY
);
1622 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1625 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1627 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1628 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1629 SEC_READONLY
| SEC_RELOC
1631 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1635 subseg_set (seg
, subseg
);
1639 if (! ECOFF_DEBUGGING
)
1642 if (mips_fix_vr4120
)
1643 init_vr4120_conflicts ();
1649 if (! ECOFF_DEBUGGING
)
1654 md_assemble (char *str
)
1656 struct mips_cl_insn insn
;
1657 bfd_reloc_code_real_type unused_reloc
[3]
1658 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1660 imm_expr
.X_op
= O_absent
;
1661 imm2_expr
.X_op
= O_absent
;
1662 offset_expr
.X_op
= O_absent
;
1663 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1664 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1665 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1666 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1667 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1668 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1670 if (mips_opts
.mips16
)
1671 mips16_ip (str
, &insn
);
1674 mips_ip (str
, &insn
);
1675 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1676 str
, insn
.insn_opcode
));
1681 as_bad ("%s `%s'", insn_error
, str
);
1685 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1688 if (mips_opts
.mips16
)
1689 mips16_macro (&insn
);
1696 if (imm_expr
.X_op
!= O_absent
)
1697 append_insn (&insn
, &imm_expr
, imm_reloc
);
1698 else if (offset_expr
.X_op
!= O_absent
)
1699 append_insn (&insn
, &offset_expr
, offset_reloc
);
1701 append_insn (&insn
, NULL
, unused_reloc
);
1705 /* Return true if the given relocation might need a matching %lo().
1706 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1707 need a matching %lo() when applied to local symbols. */
1709 static inline bfd_boolean
1710 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1712 return (HAVE_IN_PLACE_ADDENDS
1713 && (reloc
== BFD_RELOC_HI16_S
1714 || reloc
== BFD_RELOC_MIPS16_HI16_S
1715 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
1716 all GOT16 relocations evaluate to "G". */
1717 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
1720 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1723 static inline bfd_boolean
1724 fixup_has_matching_lo_p (fixS
*fixp
)
1726 return (fixp
->fx_next
!= NULL
1727 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1728 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1729 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1730 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1733 /* See whether instruction IP reads register REG. CLASS is the type
1737 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1738 enum mips_regclass
class)
1740 if (class == MIPS16_REG
)
1742 assert (mips_opts
.mips16
);
1743 reg
= mips16_to_32_reg_map
[reg
];
1744 class = MIPS_GR_REG
;
1747 /* Don't report on general register ZERO, since it never changes. */
1748 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1751 if (class == MIPS_FP_REG
)
1753 assert (! mips_opts
.mips16
);
1754 /* If we are called with either $f0 or $f1, we must check $f0.
1755 This is not optimal, because it will introduce an unnecessary
1756 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1757 need to distinguish reading both $f0 and $f1 or just one of
1758 them. Note that we don't have to check the other way,
1759 because there is no instruction that sets both $f0 and $f1
1760 and requires a delay. */
1761 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1762 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1763 == (reg
&~ (unsigned) 1)))
1765 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1766 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1767 == (reg
&~ (unsigned) 1)))
1770 else if (! mips_opts
.mips16
)
1772 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1773 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1775 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1776 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1781 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1782 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1784 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1785 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1787 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1788 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1791 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1793 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1795 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1797 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1798 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1805 /* This function returns true if modifying a register requires a
1809 reg_needs_delay (unsigned int reg
)
1811 unsigned long prev_pinfo
;
1813 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1814 if (! mips_opts
.noreorder
1815 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1816 && ! gpr_interlocks
)
1817 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1818 && ! cop_interlocks
)))
1820 /* A load from a coprocessor or from memory. All load delays
1821 delay the use of general register rt for one instruction. */
1822 /* Itbl support may require additional care here. */
1823 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1824 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1831 /* Move all labels in insn_labels to the current insertion point. */
1834 mips_move_labels (void)
1836 struct insn_label_list
*l
;
1839 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1841 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1842 symbol_set_frag (l
->label
, frag_now
);
1843 val
= (valueT
) frag_now_fix ();
1844 /* mips16 text labels are stored as odd. */
1845 if (mips_opts
.mips16
)
1847 S_SET_VALUE (l
->label
, val
);
1851 /* Mark instruction labels in mips16 mode. This permits the linker to
1852 handle them specially, such as generating jalx instructions when
1853 needed. We also make them odd for the duration of the assembly, in
1854 order to generate the right sort of code. We will make them even
1855 in the adjust_symtab routine, while leaving them marked. This is
1856 convenient for the debugger and the disassembler. The linker knows
1857 to make them odd again. */
1860 mips16_mark_labels (void)
1862 if (mips_opts
.mips16
)
1864 struct insn_label_list
*l
;
1867 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1870 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1871 S_SET_OTHER (l
->label
, STO_MIPS16
);
1873 val
= S_GET_VALUE (l
->label
);
1875 S_SET_VALUE (l
->label
, val
+ 1);
1880 /* End the current frag. Make it a variant frag and record the
1884 relax_close_frag (void)
1886 mips_macro_warning
.first_frag
= frag_now
;
1887 frag_var (rs_machine_dependent
, 0, 0,
1888 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1889 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1891 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1892 mips_relax
.first_fixup
= 0;
1895 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1896 See the comment above RELAX_ENCODE for more details. */
1899 relax_start (symbolS
*symbol
)
1901 assert (mips_relax
.sequence
== 0);
1902 mips_relax
.sequence
= 1;
1903 mips_relax
.symbol
= symbol
;
1906 /* Start generating the second version of a relaxable sequence.
1907 See the comment above RELAX_ENCODE for more details. */
1912 assert (mips_relax
.sequence
== 1);
1913 mips_relax
.sequence
= 2;
1916 /* End the current relaxable sequence. */
1921 assert (mips_relax
.sequence
== 2);
1922 relax_close_frag ();
1923 mips_relax
.sequence
= 0;
1926 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1927 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1928 by VR4120 errata. */
1931 classify_vr4120_insn (const char *name
)
1933 if (strncmp (name
, "macc", 4) == 0)
1934 return FIX_VR4120_MACC
;
1935 if (strncmp (name
, "dmacc", 5) == 0)
1936 return FIX_VR4120_DMACC
;
1937 if (strncmp (name
, "mult", 4) == 0)
1938 return FIX_VR4120_MULT
;
1939 if (strncmp (name
, "dmult", 5) == 0)
1940 return FIX_VR4120_DMULT
;
1941 if (strstr (name
, "div"))
1942 return FIX_VR4120_DIV
;
1943 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1944 return FIX_VR4120_MTHILO
;
1945 return NUM_FIX_VR4120_CLASSES
;
1948 /* Return the number of instructions that must separate INSN1 and INSN2,
1949 where INSN1 is the earlier instruction. Return the worst-case value
1950 for any INSN2 if INSN2 is null. */
1953 insns_between (const struct mips_cl_insn
*insn1
,
1954 const struct mips_cl_insn
*insn2
)
1956 unsigned long pinfo1
, pinfo2
;
1958 /* This function needs to know which pinfo flags are set for INSN2
1959 and which registers INSN2 uses. The former is stored in PINFO2 and
1960 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1961 will have every flag set and INSN2_USES_REG will always return true. */
1962 pinfo1
= insn1
->insn_mo
->pinfo
;
1963 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1965 #define INSN2_USES_REG(REG, CLASS) \
1966 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1968 /* For most targets, write-after-read dependencies on the HI and LO
1969 registers must be separated by at least two instructions. */
1970 if (!hilo_interlocks
)
1972 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1974 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1978 /* If we're working around r7000 errata, there must be two instructions
1979 between an mfhi or mflo and any instruction that uses the result. */
1980 if (mips_7000_hilo_fix
1981 && MF_HILO_INSN (pinfo1
)
1982 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1985 /* If working around VR4120 errata, check for combinations that need
1986 a single intervening instruction. */
1987 if (mips_fix_vr4120
)
1989 unsigned int class1
, class2
;
1991 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1992 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1996 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1997 if (vr4120_conflicts
[class1
] & (1 << class2
))
2002 if (!mips_opts
.mips16
)
2004 /* Check for GPR or coprocessor load delays. All such delays
2005 are on the RT register. */
2006 /* Itbl support may require additional care here. */
2007 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2008 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2010 know (pinfo1
& INSN_WRITE_GPR_T
);
2011 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2015 /* Check for generic coprocessor hazards.
2017 This case is not handled very well. There is no special
2018 knowledge of CP0 handling, and the coprocessors other than
2019 the floating point unit are not distinguished at all. */
2020 /* Itbl support may require additional care here. FIXME!
2021 Need to modify this to include knowledge about
2022 user specified delays! */
2023 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2024 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2026 /* Handle cases where INSN1 writes to a known general coprocessor
2027 register. There must be a one instruction delay before INSN2
2028 if INSN2 reads that register, otherwise no delay is needed. */
2029 if (pinfo1
& INSN_WRITE_FPR_T
)
2031 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2034 else if (pinfo1
& INSN_WRITE_FPR_S
)
2036 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2041 /* Read-after-write dependencies on the control registers
2042 require a two-instruction gap. */
2043 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2044 && (pinfo2
& INSN_READ_COND_CODE
))
2047 /* We don't know exactly what INSN1 does. If INSN2 is
2048 also a coprocessor instruction, assume there must be
2049 a one instruction gap. */
2050 if (pinfo2
& INSN_COP
)
2055 /* Check for read-after-write dependencies on the coprocessor
2056 control registers in cases where INSN1 does not need a general
2057 coprocessor delay. This means that INSN1 is a floating point
2058 comparison instruction. */
2059 /* Itbl support may require additional care here. */
2060 else if (!cop_interlocks
2061 && (pinfo1
& INSN_WRITE_COND_CODE
)
2062 && (pinfo2
& INSN_READ_COND_CODE
))
2066 #undef INSN2_USES_REG
2071 /* Return the number of nops that would be needed to work around the
2072 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2073 the MAX_VR4130_NOPS instructions described by HISTORY. */
2076 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2077 const struct mips_cl_insn
*insn
)
2081 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2082 are not affected by the errata. */
2084 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2085 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2086 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2089 /* Search for the first MFLO or MFHI. */
2090 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2091 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2093 /* Extract the destination register. */
2094 if (mips_opts
.mips16
)
2095 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2097 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2099 /* No nops are needed if INSN reads that register. */
2100 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2103 /* ...or if any of the intervening instructions do. */
2104 for (j
= 0; j
< i
; j
++)
2105 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2108 return MAX_VR4130_NOPS
- i
;
2113 /* Return the number of nops that would be needed if instruction INSN
2114 immediately followed the MAX_NOPS instructions given by HISTORY,
2115 where HISTORY[0] is the most recent instruction. If INSN is null,
2116 return the worse-case number of nops for any instruction. */
2119 nops_for_insn (const struct mips_cl_insn
*history
,
2120 const struct mips_cl_insn
*insn
)
2122 int i
, nops
, tmp_nops
;
2125 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2126 if (!history
[i
].noreorder_p
)
2128 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2129 if (tmp_nops
> nops
)
2133 if (mips_fix_vr4130
)
2135 tmp_nops
= nops_for_vr4130 (history
, insn
);
2136 if (tmp_nops
> nops
)
2143 /* The variable arguments provide NUM_INSNS extra instructions that
2144 might be added to HISTORY. Return the largest number of nops that
2145 would be needed after the extended sequence. */
2148 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2151 struct mips_cl_insn buffer
[MAX_NOPS
];
2152 struct mips_cl_insn
*cursor
;
2155 va_start (args
, history
);
2156 cursor
= buffer
+ num_insns
;
2157 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2158 while (cursor
> buffer
)
2159 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2161 nops
= nops_for_insn (buffer
, NULL
);
2166 /* Like nops_for_insn, but if INSN is a branch, take into account the
2167 worst-case delay for the branch target. */
2170 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2171 const struct mips_cl_insn
*insn
)
2175 nops
= nops_for_insn (history
, insn
);
2176 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2177 | INSN_COND_BRANCH_DELAY
2178 | INSN_COND_BRANCH_LIKELY
))
2180 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2181 if (tmp_nops
> nops
)
2184 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2186 tmp_nops
= nops_for_sequence (1, history
, insn
);
2187 if (tmp_nops
> nops
)
2193 /* Output an instruction. IP is the instruction information.
2194 ADDRESS_EXPR is an operand of the instruction to be used with
2198 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2199 bfd_reloc_code_real_type
*reloc_type
)
2201 register unsigned long prev_pinfo
, pinfo
;
2202 relax_stateT prev_insn_frag_type
= 0;
2203 bfd_boolean relaxed_branch
= FALSE
;
2205 /* Mark instruction labels in mips16 mode. */
2206 mips16_mark_labels ();
2208 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2209 pinfo
= ip
->insn_mo
->pinfo
;
2211 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2213 /* There are a lot of optimizations we could do that we don't.
2214 In particular, we do not, in general, reorder instructions.
2215 If you use gcc with optimization, it will reorder
2216 instructions and generally do much more optimization then we
2217 do here; repeating all that work in the assembler would only
2218 benefit hand written assembly code, and does not seem worth
2220 int nops
= (mips_optimize
== 0
2221 ? nops_for_insn (history
, NULL
)
2222 : nops_for_insn_or_target (history
, ip
));
2226 unsigned long old_frag_offset
;
2229 old_frag
= frag_now
;
2230 old_frag_offset
= frag_now_fix ();
2232 for (i
= 0; i
< nops
; i
++)
2237 listing_prev_line ();
2238 /* We may be at the start of a variant frag. In case we
2239 are, make sure there is enough space for the frag
2240 after the frags created by listing_prev_line. The
2241 argument to frag_grow here must be at least as large
2242 as the argument to all other calls to frag_grow in
2243 this file. We don't have to worry about being in the
2244 middle of a variant frag, because the variants insert
2245 all needed nop instructions themselves. */
2249 mips_move_labels ();
2251 #ifndef NO_ECOFF_DEBUGGING
2252 if (ECOFF_DEBUGGING
)
2253 ecoff_fix_loc (old_frag
, old_frag_offset
);
2257 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2259 /* Work out how many nops in prev_nop_frag are needed by IP. */
2260 int nops
= nops_for_insn_or_target (history
, ip
);
2261 assert (nops
<= prev_nop_frag_holds
);
2263 /* Enforce NOPS as a minimum. */
2264 if (nops
> prev_nop_frag_required
)
2265 prev_nop_frag_required
= nops
;
2267 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2269 /* Settle for the current number of nops. Update the history
2270 accordingly (for the benefit of any future .set reorder code). */
2271 prev_nop_frag
= NULL
;
2272 insert_into_history (prev_nop_frag_since
,
2273 prev_nop_frag_holds
, NOP_INSN
);
2277 /* Allow this instruction to replace one of the nops that was
2278 tentatively added to prev_nop_frag. */
2279 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2280 prev_nop_frag_holds
--;
2281 prev_nop_frag_since
++;
2286 /* The value passed to dwarf2_emit_insn is the distance between
2287 the beginning of the current instruction and the address that
2288 should be recorded in the debug tables. For MIPS16 debug info
2289 we want to use ISA-encoded addresses, so we pass -1 for an
2290 address higher by one than the current. */
2291 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2294 /* Record the frag type before frag_var. */
2295 if (history
[0].frag
)
2296 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2299 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2300 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2301 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2302 && mips_relax_branch
2303 /* Don't try branch relaxation within .set nomacro, or within
2304 .set noat if we use $at for PIC computations. If it turns
2305 out that the branch was out-of-range, we'll get an error. */
2306 && !mips_opts
.warn_about_macros
2307 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2308 && !mips_opts
.mips16
)
2310 relaxed_branch
= TRUE
;
2311 add_relaxed_insn (ip
, (relaxed_branch_length
2313 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2314 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2317 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2318 pinfo
& INSN_COND_BRANCH_LIKELY
,
2319 pinfo
& INSN_WRITE_GPR_31
,
2321 address_expr
->X_add_symbol
,
2322 address_expr
->X_add_number
);
2323 *reloc_type
= BFD_RELOC_UNUSED
;
2325 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2327 /* We need to set up a variant frag. */
2328 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2329 add_relaxed_insn (ip
, 4, 0,
2331 (*reloc_type
- BFD_RELOC_UNUSED
,
2332 mips16_small
, mips16_ext
,
2333 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2334 history
[0].mips16_absolute_jump_p
),
2335 make_expr_symbol (address_expr
), 0);
2337 else if (mips_opts
.mips16
2339 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2341 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2342 /* Make sure there is enough room to swap this instruction with
2343 a following jump instruction. */
2345 add_fixed_insn (ip
);
2349 if (mips_opts
.mips16
2350 && mips_opts
.noreorder
2351 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2352 as_warn (_("extended instruction in delay slot"));
2354 if (mips_relax
.sequence
)
2356 /* If we've reached the end of this frag, turn it into a variant
2357 frag and record the information for the instructions we've
2359 if (frag_room () < 4)
2360 relax_close_frag ();
2361 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2364 if (mips_relax
.sequence
!= 2)
2365 mips_macro_warning
.sizes
[0] += 4;
2366 if (mips_relax
.sequence
!= 1)
2367 mips_macro_warning
.sizes
[1] += 4;
2369 if (mips_opts
.mips16
)
2372 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2374 add_fixed_insn (ip
);
2377 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2379 if (address_expr
->X_op
== O_constant
)
2383 switch (*reloc_type
)
2386 ip
->insn_opcode
|= address_expr
->X_add_number
;
2389 case BFD_RELOC_MIPS_HIGHEST
:
2390 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2391 ip
->insn_opcode
|= tmp
& 0xffff;
2394 case BFD_RELOC_MIPS_HIGHER
:
2395 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2396 ip
->insn_opcode
|= tmp
& 0xffff;
2399 case BFD_RELOC_HI16_S
:
2400 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2401 ip
->insn_opcode
|= tmp
& 0xffff;
2404 case BFD_RELOC_HI16
:
2405 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2408 case BFD_RELOC_UNUSED
:
2409 case BFD_RELOC_LO16
:
2410 case BFD_RELOC_MIPS_GOT_DISP
:
2411 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2414 case BFD_RELOC_MIPS_JMP
:
2415 if ((address_expr
->X_add_number
& 3) != 0)
2416 as_bad (_("jump to misaligned address (0x%lx)"),
2417 (unsigned long) address_expr
->X_add_number
);
2418 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2421 case BFD_RELOC_MIPS16_JMP
:
2422 if ((address_expr
->X_add_number
& 3) != 0)
2423 as_bad (_("jump to misaligned address (0x%lx)"),
2424 (unsigned long) address_expr
->X_add_number
);
2426 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2427 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2428 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2431 case BFD_RELOC_16_PCREL_S2
:
2432 if ((address_expr
->X_add_number
& 3) != 0)
2433 as_bad (_("branch to misaligned address (0x%lx)"),
2434 (unsigned long) address_expr
->X_add_number
);
2435 if (mips_relax_branch
)
2437 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2438 as_bad (_("branch address range overflow (0x%lx)"),
2439 (unsigned long) address_expr
->X_add_number
);
2440 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2447 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2450 reloc_howto_type
*howto
;
2453 /* In a compound relocation, it is the final (outermost)
2454 operator that determines the relocated field. */
2455 for (i
= 1; i
< 3; i
++)
2456 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2459 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2460 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2461 bfd_get_reloc_size (howto
),
2463 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2466 /* These relocations can have an addend that won't fit in
2467 4 octets for 64bit assembly. */
2469 && ! howto
->partial_inplace
2470 && (reloc_type
[0] == BFD_RELOC_16
2471 || reloc_type
[0] == BFD_RELOC_32
2472 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2473 || reloc_type
[0] == BFD_RELOC_HI16_S
2474 || reloc_type
[0] == BFD_RELOC_LO16
2475 || reloc_type
[0] == BFD_RELOC_GPREL16
2476 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2477 || reloc_type
[0] == BFD_RELOC_GPREL32
2478 || reloc_type
[0] == BFD_RELOC_64
2479 || reloc_type
[0] == BFD_RELOC_CTOR
2480 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2481 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2482 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2483 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2484 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2485 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2486 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2487 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2488 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2489 ip
->fixp
[0]->fx_no_overflow
= 1;
2491 if (mips_relax
.sequence
)
2493 if (mips_relax
.first_fixup
== 0)
2494 mips_relax
.first_fixup
= ip
->fixp
[0];
2496 else if (reloc_needs_lo_p (*reloc_type
))
2498 struct mips_hi_fixup
*hi_fixup
;
2500 /* Reuse the last entry if it already has a matching %lo. */
2501 hi_fixup
= mips_hi_fixup_list
;
2503 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2505 hi_fixup
= ((struct mips_hi_fixup
*)
2506 xmalloc (sizeof (struct mips_hi_fixup
)));
2507 hi_fixup
->next
= mips_hi_fixup_list
;
2508 mips_hi_fixup_list
= hi_fixup
;
2510 hi_fixup
->fixp
= ip
->fixp
[0];
2511 hi_fixup
->seg
= now_seg
;
2514 /* Add fixups for the second and third relocations, if given.
2515 Note that the ABI allows the second relocation to be
2516 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2517 moment we only use RSS_UNDEF, but we could add support
2518 for the others if it ever becomes necessary. */
2519 for (i
= 1; i
< 3; i
++)
2520 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2522 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2523 ip
->fixp
[0]->fx_size
, NULL
, 0,
2524 FALSE
, reloc_type
[i
]);
2526 /* Use fx_tcbit to mark compound relocs. */
2527 ip
->fixp
[0]->fx_tcbit
= 1;
2528 ip
->fixp
[i
]->fx_tcbit
= 1;
2534 /* Update the register mask information. */
2535 if (! mips_opts
.mips16
)
2537 if (pinfo
& INSN_WRITE_GPR_D
)
2538 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2539 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2540 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2541 if (pinfo
& INSN_READ_GPR_S
)
2542 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2543 if (pinfo
& INSN_WRITE_GPR_31
)
2544 mips_gprmask
|= 1 << RA
;
2545 if (pinfo
& INSN_WRITE_FPR_D
)
2546 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2547 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2548 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2549 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2550 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2551 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2552 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2553 if (pinfo
& INSN_COP
)
2555 /* We don't keep enough information to sort these cases out.
2556 The itbl support does keep this information however, although
2557 we currently don't support itbl fprmats as part of the cop
2558 instruction. May want to add this support in the future. */
2560 /* Never set the bit for $0, which is always zero. */
2561 mips_gprmask
&= ~1 << 0;
2565 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2566 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2567 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2568 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2569 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2570 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2571 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2572 mips_gprmask
|= 1 << TREG
;
2573 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2574 mips_gprmask
|= 1 << SP
;
2575 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2576 mips_gprmask
|= 1 << RA
;
2577 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2578 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2579 if (pinfo
& MIPS16_INSN_READ_Z
)
2580 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2581 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2582 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2585 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2587 /* Filling the branch delay slot is more complex. We try to
2588 switch the branch with the previous instruction, which we can
2589 do if the previous instruction does not set up a condition
2590 that the branch tests and if the branch is not itself the
2591 target of any branch. */
2592 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2593 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2595 if (mips_optimize
< 2
2596 /* If we have seen .set volatile or .set nomove, don't
2598 || mips_opts
.nomove
!= 0
2599 /* We can't swap if the previous instruction's position
2601 || history
[0].fixed_p
2602 /* If the previous previous insn was in a .set
2603 noreorder, we can't swap. Actually, the MIPS
2604 assembler will swap in this situation. However, gcc
2605 configured -with-gnu-as will generate code like
2611 in which we can not swap the bne and INSN. If gcc is
2612 not configured -with-gnu-as, it does not output the
2614 || history
[1].noreorder_p
2615 /* If the branch is itself the target of a branch, we
2616 can not swap. We cheat on this; all we check for is
2617 whether there is a label on this instruction. If
2618 there are any branches to anything other than a
2619 label, users must use .set noreorder. */
2620 || insn_labels
!= NULL
2621 /* If the previous instruction is in a variant frag
2622 other than this branch's one, we cannot do the swap.
2623 This does not apply to the mips16, which uses variant
2624 frags for different purposes. */
2625 || (! mips_opts
.mips16
2626 && prev_insn_frag_type
== rs_machine_dependent
)
2627 /* Check for conflicts between the branch and the instructions
2628 before the candidate delay slot. */
2629 || nops_for_insn (history
+ 1, ip
) > 0
2630 /* Check for conflicts between the swapped sequence and the
2631 target of the branch. */
2632 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2633 /* We do not swap with a trap instruction, since it
2634 complicates trap handlers to have the trap
2635 instruction be in a delay slot. */
2636 || (prev_pinfo
& INSN_TRAP
)
2637 /* If the branch reads a register that the previous
2638 instruction sets, we can not swap. */
2639 || (! mips_opts
.mips16
2640 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2641 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2643 || (! mips_opts
.mips16
2644 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2645 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2647 || (mips_opts
.mips16
2648 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2650 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2652 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2654 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2656 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2658 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2660 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2661 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2662 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2663 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2664 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2665 && insn_uses_reg (ip
,
2666 MIPS16OP_EXTRACT_REG32R
2667 (history
[0].insn_opcode
),
2669 /* If the branch writes a register that the previous
2670 instruction sets, we can not swap (we know that
2671 branches write only to RD or to $31). */
2672 || (! mips_opts
.mips16
2673 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2674 && (((pinfo
& INSN_WRITE_GPR_D
)
2675 && (EXTRACT_OPERAND (RT
, history
[0])
2676 == EXTRACT_OPERAND (RD
, *ip
)))
2677 || ((pinfo
& INSN_WRITE_GPR_31
)
2678 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2679 || (! mips_opts
.mips16
2680 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2681 && (((pinfo
& INSN_WRITE_GPR_D
)
2682 && (EXTRACT_OPERAND (RD
, history
[0])
2683 == EXTRACT_OPERAND (RD
, *ip
)))
2684 || ((pinfo
& INSN_WRITE_GPR_31
)
2685 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2686 || (mips_opts
.mips16
2687 && (pinfo
& MIPS16_INSN_WRITE_31
)
2688 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2689 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2690 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2692 /* If the branch writes a register that the previous
2693 instruction reads, we can not swap (we know that
2694 branches only write to RD or to $31). */
2695 || (! mips_opts
.mips16
2696 && (pinfo
& INSN_WRITE_GPR_D
)
2697 && insn_uses_reg (&history
[0],
2698 EXTRACT_OPERAND (RD
, *ip
),
2700 || (! mips_opts
.mips16
2701 && (pinfo
& INSN_WRITE_GPR_31
)
2702 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2703 || (mips_opts
.mips16
2704 && (pinfo
& MIPS16_INSN_WRITE_31
)
2705 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2706 /* If one instruction sets a condition code and the
2707 other one uses a condition code, we can not swap. */
2708 || ((pinfo
& INSN_READ_COND_CODE
)
2709 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2710 || ((pinfo
& INSN_WRITE_COND_CODE
)
2711 && (prev_pinfo
& INSN_READ_COND_CODE
))
2712 /* If the previous instruction uses the PC, we can not
2714 || (mips_opts
.mips16
2715 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2716 /* If the previous instruction had a fixup in mips16
2717 mode, we can not swap. This normally means that the
2718 previous instruction was a 4 byte branch anyhow. */
2719 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2720 /* If the previous instruction is a sync, sync.l, or
2721 sync.p, we can not swap. */
2722 || (prev_pinfo
& INSN_SYNC
))
2724 if (mips_opts
.mips16
2725 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2726 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
2727 && (mips_opts
.isa
== ISA_MIPS32
2728 || mips_opts
.isa
== ISA_MIPS32R2
2729 || mips_opts
.isa
== ISA_MIPS64
2730 || mips_opts
.isa
== ISA_MIPS64R2
))
2732 /* Convert MIPS16 jr/jalr into a "compact" jump. */
2733 ip
->insn_opcode
|= 0x0080;
2735 insert_into_history (0, 1, ip
);
2739 /* We could do even better for unconditional branches to
2740 portions of this object file; we could pick up the
2741 instruction at the destination, put it in the delay
2742 slot, and bump the destination address. */
2743 insert_into_history (0, 1, ip
);
2747 if (mips_relax
.sequence
)
2748 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2752 /* It looks like we can actually do the swap. */
2753 struct mips_cl_insn delay
= history
[0];
2754 if (mips_opts
.mips16
)
2756 know (delay
.frag
== ip
->frag
);
2757 move_insn (ip
, delay
.frag
, delay
.where
);
2758 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2760 else if (relaxed_branch
)
2762 /* Add the delay slot instruction to the end of the
2763 current frag and shrink the fixed part of the
2764 original frag. If the branch occupies the tail of
2765 the latter, move it backwards to cover the gap. */
2766 delay
.frag
->fr_fix
-= 4;
2767 if (delay
.frag
== ip
->frag
)
2768 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2769 add_fixed_insn (&delay
);
2773 move_insn (&delay
, ip
->frag
, ip
->where
);
2774 move_insn (ip
, history
[0].frag
, history
[0].where
);
2778 insert_into_history (0, 1, &delay
);
2781 /* If that was an unconditional branch, forget the previous
2782 insn information. */
2783 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2784 mips_no_prev_insn ();
2786 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2788 /* We don't yet optimize a branch likely. What we should do
2789 is look at the target, copy the instruction found there
2790 into the delay slot, and increment the branch to jump to
2791 the next instruction. */
2792 insert_into_history (0, 1, ip
);
2796 insert_into_history (0, 1, ip
);
2799 insert_into_history (0, 1, ip
);
2801 /* We just output an insn, so the next one doesn't have a label. */
2802 mips_clear_insn_labels ();
2805 /* Forget that there was any previous instruction or label. */
2808 mips_no_prev_insn (void)
2810 prev_nop_frag
= NULL
;
2811 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2812 mips_clear_insn_labels ();
2815 /* This function must be called before we emit something other than
2816 instructions. It is like mips_no_prev_insn except that it inserts
2817 any NOPS that might be needed by previous instructions. */
2820 mips_emit_delays (void)
2822 if (! mips_opts
.noreorder
)
2824 int nops
= nops_for_insn (history
, NULL
);
2828 add_fixed_insn (NOP_INSN
);
2829 mips_move_labels ();
2832 mips_no_prev_insn ();
2835 /* Start a (possibly nested) noreorder block. */
2838 start_noreorder (void)
2840 if (mips_opts
.noreorder
== 0)
2845 /* None of the instructions before the .set noreorder can be moved. */
2846 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2847 history
[i
].fixed_p
= 1;
2849 /* Insert any nops that might be needed between the .set noreorder
2850 block and the previous instructions. We will later remove any
2851 nops that turn out not to be needed. */
2852 nops
= nops_for_insn (history
, NULL
);
2855 if (mips_optimize
!= 0)
2857 /* Record the frag which holds the nop instructions, so
2858 that we can remove them if we don't need them. */
2859 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2860 prev_nop_frag
= frag_now
;
2861 prev_nop_frag_holds
= nops
;
2862 prev_nop_frag_required
= 0;
2863 prev_nop_frag_since
= 0;
2866 for (; nops
> 0; --nops
)
2867 add_fixed_insn (NOP_INSN
);
2869 /* Move on to a new frag, so that it is safe to simply
2870 decrease the size of prev_nop_frag. */
2871 frag_wane (frag_now
);
2873 mips_move_labels ();
2875 mips16_mark_labels ();
2876 mips_clear_insn_labels ();
2878 mips_opts
.noreorder
++;
2879 mips_any_noreorder
= 1;
2882 /* End a nested noreorder block. */
2885 end_noreorder (void)
2887 mips_opts
.noreorder
--;
2888 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2890 /* Commit to inserting prev_nop_frag_required nops and go back to
2891 handling nop insertion the .set reorder way. */
2892 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2893 * (mips_opts
.mips16
? 2 : 4));
2894 insert_into_history (prev_nop_frag_since
,
2895 prev_nop_frag_required
, NOP_INSN
);
2896 prev_nop_frag
= NULL
;
2900 /* Set up global variables for the start of a new macro. */
2905 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2906 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2907 && (history
[0].insn_mo
->pinfo
2908 & (INSN_UNCOND_BRANCH_DELAY
2909 | INSN_COND_BRANCH_DELAY
2910 | INSN_COND_BRANCH_LIKELY
)) != 0);
2913 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2914 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2915 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2918 macro_warning (relax_substateT subtype
)
2920 if (subtype
& RELAX_DELAY_SLOT
)
2921 return _("Macro instruction expanded into multiple instructions"
2922 " in a branch delay slot");
2923 else if (subtype
& RELAX_NOMACRO
)
2924 return _("Macro instruction expanded into multiple instructions");
2929 /* Finish up a macro. Emit warnings as appropriate. */
2934 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2936 relax_substateT subtype
;
2938 /* Set up the relaxation warning flags. */
2940 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2941 subtype
|= RELAX_SECOND_LONGER
;
2942 if (mips_opts
.warn_about_macros
)
2943 subtype
|= RELAX_NOMACRO
;
2944 if (mips_macro_warning
.delay_slot_p
)
2945 subtype
|= RELAX_DELAY_SLOT
;
2947 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2949 /* Either the macro has a single implementation or both
2950 implementations are longer than 4 bytes. Emit the
2952 const char *msg
= macro_warning (subtype
);
2958 /* One implementation might need a warning but the other
2959 definitely doesn't. */
2960 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2965 /* Read a macro's relocation codes from *ARGS and store them in *R.
2966 The first argument in *ARGS will be either the code for a single
2967 relocation or -1 followed by the three codes that make up a
2968 composite relocation. */
2971 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2975 next
= va_arg (*args
, int);
2977 r
[0] = (bfd_reloc_code_real_type
) next
;
2979 for (i
= 0; i
< 3; i
++)
2980 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2983 /* Build an instruction created by a macro expansion. This is passed
2984 a pointer to the count of instructions created so far, an
2985 expression, the name of the instruction to build, an operand format
2986 string, and corresponding arguments. */
2989 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2991 const struct mips_opcode
*mo
;
2992 struct mips_cl_insn insn
;
2993 bfd_reloc_code_real_type r
[3];
2996 va_start (args
, fmt
);
2998 if (mips_opts
.mips16
)
3000 mips16_macro_build (ep
, name
, fmt
, args
);
3005 r
[0] = BFD_RELOC_UNUSED
;
3006 r
[1] = BFD_RELOC_UNUSED
;
3007 r
[2] = BFD_RELOC_UNUSED
;
3008 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3010 assert (strcmp (name
, mo
->name
) == 0);
3012 /* Search until we get a match for NAME. It is assumed here that
3013 macros will never generate MDMX or MIPS-3D instructions. */
3014 while (strcmp (fmt
, mo
->args
) != 0
3015 || mo
->pinfo
== INSN_MACRO
3016 || !OPCODE_IS_MEMBER (mo
,
3018 | (mips_opts
.mips16
? INSN_MIPS16
: 0)
3019 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
3021 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
3025 assert (strcmp (name
, mo
->name
) == 0);
3028 create_insn (&insn
, mo
);
3046 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3051 /* Note that in the macro case, these arguments are already
3052 in MSB form. (When handling the instruction in the
3053 non-macro case, these arguments are sizes from which
3054 MSB values must be calculated.) */
3055 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3061 /* Note that in the macro case, these arguments are already
3062 in MSBD form. (When handling the instruction in the
3063 non-macro case, these arguments are sizes from which
3064 MSBD values must be calculated.) */
3065 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3076 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3080 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3085 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3091 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3096 int tmp
= va_arg (args
, int);
3098 INSERT_OPERAND (RT
, insn
, tmp
);
3099 INSERT_OPERAND (RD
, insn
, tmp
);
3105 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3112 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3116 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3120 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3124 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3128 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3135 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3141 macro_read_relocs (&args
, r
);
3142 assert (*r
== BFD_RELOC_GPREL16
3143 || *r
== BFD_RELOC_MIPS_LITERAL
3144 || *r
== BFD_RELOC_MIPS_HIGHER
3145 || *r
== BFD_RELOC_HI16_S
3146 || *r
== BFD_RELOC_LO16
3147 || *r
== BFD_RELOC_MIPS_GOT16
3148 || *r
== BFD_RELOC_MIPS_CALL16
3149 || *r
== BFD_RELOC_MIPS_GOT_DISP
3150 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3151 || *r
== BFD_RELOC_MIPS_GOT_OFST
3152 || *r
== BFD_RELOC_MIPS_GOT_LO16
3153 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3157 macro_read_relocs (&args
, r
);
3159 && (ep
->X_op
== O_constant
3160 || (ep
->X_op
== O_symbol
3161 && (*r
== BFD_RELOC_MIPS_HIGHEST
3162 || *r
== BFD_RELOC_HI16_S
3163 || *r
== BFD_RELOC_HI16
3164 || *r
== BFD_RELOC_GPREL16
3165 || *r
== BFD_RELOC_MIPS_GOT_HI16
3166 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3170 assert (ep
!= NULL
);
3173 * This allows macro() to pass an immediate expression for
3174 * creating short branches without creating a symbol.
3176 * We don't allow branch relaxation for these branches, as
3177 * they should only appear in ".set nomacro" anyway.
3179 if (ep
->X_op
== O_constant
)
3181 if ((ep
->X_add_number
& 3) != 0)
3182 as_bad (_("branch to misaligned address (0x%lx)"),
3183 (unsigned long) ep
->X_add_number
);
3184 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3185 as_bad (_("branch address range overflow (0x%lx)"),
3186 (unsigned long) ep
->X_add_number
);
3187 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3191 *r
= BFD_RELOC_16_PCREL_S2
;
3195 assert (ep
!= NULL
);
3196 *r
= BFD_RELOC_MIPS_JMP
;
3200 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3204 insn
.insn_opcode
|= va_arg (args
, unsigned long) << OP_SH_CACHE
;
3213 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3215 append_insn (&insn
, ep
, r
);
3219 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3222 struct mips_opcode
*mo
;
3223 struct mips_cl_insn insn
;
3224 bfd_reloc_code_real_type r
[3]
3225 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3227 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3229 assert (strcmp (name
, mo
->name
) == 0);
3231 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3235 assert (strcmp (name
, mo
->name
) == 0);
3238 create_insn (&insn
, mo
);
3256 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3261 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3265 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3269 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3279 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3286 regno
= va_arg (args
, int);
3287 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3288 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3309 assert (ep
!= NULL
);
3311 if (ep
->X_op
!= O_constant
)
3312 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3315 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3316 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3319 *r
= BFD_RELOC_UNUSED
;
3325 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3332 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3334 append_insn (&insn
, ep
, r
);
3338 * Sign-extend 32-bit mode constants that have bit 31 set and all
3339 * higher bits unset.
3342 normalize_constant_expr (expressionS
*ex
)
3344 if (ex
->X_op
== O_constant
3345 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3346 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3351 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3352 * all higher bits unset.
3355 normalize_address_expr (expressionS
*ex
)
3357 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3358 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3359 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3360 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3365 * Generate a "jalr" instruction with a relocation hint to the called
3366 * function. This occurs in NewABI PIC code.
3369 macro_build_jalr (expressionS
*ep
)
3378 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3380 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3381 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3385 * Generate a "lui" instruction.
3388 macro_build_lui (expressionS
*ep
, int regnum
)
3390 expressionS high_expr
;
3391 const struct mips_opcode
*mo
;
3392 struct mips_cl_insn insn
;
3393 bfd_reloc_code_real_type r
[3]
3394 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3395 const char *name
= "lui";
3396 const char *fmt
= "t,u";
3398 assert (! mips_opts
.mips16
);
3402 if (high_expr
.X_op
== O_constant
)
3404 /* we can compute the instruction now without a relocation entry */
3405 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3407 *r
= BFD_RELOC_UNUSED
;
3411 assert (ep
->X_op
== O_symbol
);
3412 /* _gp_disp is a special case, used from s_cpload.
3413 __gnu_local_gp is used if mips_no_shared. */
3414 assert (mips_pic
== NO_PIC
3416 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3417 || (! mips_in_shared
3418 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3419 "__gnu_local_gp") == 0));
3420 *r
= BFD_RELOC_HI16_S
;
3423 mo
= hash_find (op_hash
, name
);
3424 assert (strcmp (name
, mo
->name
) == 0);
3425 assert (strcmp (fmt
, mo
->args
) == 0);
3426 create_insn (&insn
, mo
);
3428 insn
.insn_opcode
= insn
.insn_mo
->match
;
3429 INSERT_OPERAND (RT
, insn
, regnum
);
3430 if (*r
== BFD_RELOC_UNUSED
)
3432 insn
.insn_opcode
|= high_expr
.X_add_number
;
3433 append_insn (&insn
, NULL
, r
);
3436 append_insn (&insn
, &high_expr
, r
);
3439 /* Generate a sequence of instructions to do a load or store from a constant
3440 offset off of a base register (breg) into/from a target register (treg),
3441 using AT if necessary. */
3443 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3444 int treg
, int breg
, int dbl
)
3446 assert (ep
->X_op
== O_constant
);
3448 /* Sign-extending 32-bit constants makes their handling easier. */
3450 normalize_constant_expr (ep
);
3452 /* Right now, this routine can only handle signed 32-bit constants. */
3453 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3454 as_warn (_("operand overflow"));
3456 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3458 /* Signed 16-bit offset will fit in the op. Easy! */
3459 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3463 /* 32-bit offset, need multiple instructions and AT, like:
3464 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3465 addu $tempreg,$tempreg,$breg
3466 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3467 to handle the complete offset. */
3468 macro_build_lui (ep
, AT
);
3469 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3470 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3473 as_bad (_("Macro used $at after \".set noat\""));
3478 * Generates code to set the $at register to true (one)
3479 * if reg is less than the immediate expression.
3482 set_at (int reg
, int unsignedp
)
3484 if (imm_expr
.X_op
== O_constant
3485 && imm_expr
.X_add_number
>= -0x8000
3486 && imm_expr
.X_add_number
< 0x8000)
3487 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3488 AT
, reg
, BFD_RELOC_LO16
);
3491 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3492 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3496 /* Warn if an expression is not a constant. */
3499 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3501 if (ex
->X_op
== O_big
)
3502 as_bad (_("unsupported large constant"));
3503 else if (ex
->X_op
!= O_constant
)
3504 as_bad (_("Instruction %s requires absolute expression"),
3507 if (HAVE_32BIT_GPRS
)
3508 normalize_constant_expr (ex
);
3511 /* Count the leading zeroes by performing a binary chop. This is a
3512 bulky bit of source, but performance is a LOT better for the
3513 majority of values than a simple loop to count the bits:
3514 for (lcnt = 0; (lcnt < 32); lcnt++)
3515 if ((v) & (1 << (31 - lcnt)))
3517 However it is not code size friendly, and the gain will drop a bit
3518 on certain cached systems.
3520 #define COUNT_TOP_ZEROES(v) \
3521 (((v) & ~0xffff) == 0 \
3522 ? ((v) & ~0xff) == 0 \
3523 ? ((v) & ~0xf) == 0 \
3524 ? ((v) & ~0x3) == 0 \
3525 ? ((v) & ~0x1) == 0 \
3530 : ((v) & ~0x7) == 0 \
3533 : ((v) & ~0x3f) == 0 \
3534 ? ((v) & ~0x1f) == 0 \
3537 : ((v) & ~0x7f) == 0 \
3540 : ((v) & ~0xfff) == 0 \
3541 ? ((v) & ~0x3ff) == 0 \
3542 ? ((v) & ~0x1ff) == 0 \
3545 : ((v) & ~0x7ff) == 0 \
3548 : ((v) & ~0x3fff) == 0 \
3549 ? ((v) & ~0x1fff) == 0 \
3552 : ((v) & ~0x7fff) == 0 \
3555 : ((v) & ~0xffffff) == 0 \
3556 ? ((v) & ~0xfffff) == 0 \
3557 ? ((v) & ~0x3ffff) == 0 \
3558 ? ((v) & ~0x1ffff) == 0 \
3561 : ((v) & ~0x7ffff) == 0 \
3564 : ((v) & ~0x3fffff) == 0 \
3565 ? ((v) & ~0x1fffff) == 0 \
3568 : ((v) & ~0x7fffff) == 0 \
3571 : ((v) & ~0xfffffff) == 0 \
3572 ? ((v) & ~0x3ffffff) == 0 \
3573 ? ((v) & ~0x1ffffff) == 0 \
3576 : ((v) & ~0x7ffffff) == 0 \
3579 : ((v) & ~0x3fffffff) == 0 \
3580 ? ((v) & ~0x1fffffff) == 0 \
3583 : ((v) & ~0x7fffffff) == 0 \
3588 * This routine generates the least number of instructions necessary to load
3589 * an absolute expression value into a register.
3592 load_register (int reg
, expressionS
*ep
, int dbl
)
3595 expressionS hi32
, lo32
;
3597 if (ep
->X_op
!= O_big
)
3599 assert (ep
->X_op
== O_constant
);
3601 /* Sign-extending 32-bit constants makes their handling easier. */
3603 normalize_constant_expr (ep
);
3605 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3607 /* We can handle 16 bit signed values with an addiu to
3608 $zero. No need to ever use daddiu here, since $zero and
3609 the result are always correct in 32 bit mode. */
3610 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3613 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3615 /* We can handle 16 bit unsigned values with an ori to
3617 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3620 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3622 /* 32 bit values require an lui. */
3623 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3624 if ((ep
->X_add_number
& 0xffff) != 0)
3625 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3630 /* The value is larger than 32 bits. */
3632 if (!dbl
|| HAVE_32BIT_GPRS
)
3636 sprintf_vma (value
, ep
->X_add_number
);
3637 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3638 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3642 if (ep
->X_op
!= O_big
)
3645 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3646 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3647 hi32
.X_add_number
&= 0xffffffff;
3649 lo32
.X_add_number
&= 0xffffffff;
3653 assert (ep
->X_add_number
> 2);
3654 if (ep
->X_add_number
== 3)
3655 generic_bignum
[3] = 0;
3656 else if (ep
->X_add_number
> 4)
3657 as_bad (_("Number larger than 64 bits"));
3658 lo32
.X_op
= O_constant
;
3659 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3660 hi32
.X_op
= O_constant
;
3661 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3664 if (hi32
.X_add_number
== 0)
3669 unsigned long hi
, lo
;
3671 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3673 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3675 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3678 if (lo32
.X_add_number
& 0x80000000)
3680 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3681 if (lo32
.X_add_number
& 0xffff)
3682 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3687 /* Check for 16bit shifted constant. We know that hi32 is
3688 non-zero, so start the mask on the first bit of the hi32
3693 unsigned long himask
, lomask
;
3697 himask
= 0xffff >> (32 - shift
);
3698 lomask
= (0xffff << shift
) & 0xffffffff;
3702 himask
= 0xffff << (shift
- 32);
3705 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3706 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3710 tmp
.X_op
= O_constant
;
3712 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3713 | (lo32
.X_add_number
>> shift
));
3715 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3716 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3717 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3718 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3723 while (shift
<= (64 - 16));
3725 /* Find the bit number of the lowest one bit, and store the
3726 shifted value in hi/lo. */
3727 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3728 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3732 while ((lo
& 1) == 0)
3737 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3743 while ((hi
& 1) == 0)
3752 /* Optimize if the shifted value is a (power of 2) - 1. */
3753 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3754 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3756 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3761 /* This instruction will set the register to be all
3763 tmp
.X_op
= O_constant
;
3764 tmp
.X_add_number
= (offsetT
) -1;
3765 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3769 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3770 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3772 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3773 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3778 /* Sign extend hi32 before calling load_register, because we can
3779 generally get better code when we load a sign extended value. */
3780 if ((hi32
.X_add_number
& 0x80000000) != 0)
3781 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3782 load_register (reg
, &hi32
, 0);
3785 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3789 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3797 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3799 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3800 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3806 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3810 mid16
.X_add_number
>>= 16;
3811 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3812 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3815 if ((lo32
.X_add_number
& 0xffff) != 0)
3816 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3820 load_delay_nop (void)
3822 if (!gpr_interlocks
)
3823 macro_build (NULL
, "nop", "");
3826 /* Load an address into a register. */
3829 load_address (int reg
, expressionS
*ep
, int *used_at
)
3831 if (ep
->X_op
!= O_constant
3832 && ep
->X_op
!= O_symbol
)
3834 as_bad (_("expression too complex"));
3835 ep
->X_op
= O_constant
;
3838 if (ep
->X_op
== O_constant
)
3840 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3844 if (mips_pic
== NO_PIC
)
3846 /* If this is a reference to a GP relative symbol, we want
3847 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3849 lui $reg,<sym> (BFD_RELOC_HI16_S)
3850 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3851 If we have an addend, we always use the latter form.
3853 With 64bit address space and a usable $at we want
3854 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3855 lui $at,<sym> (BFD_RELOC_HI16_S)
3856 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3857 daddiu $at,<sym> (BFD_RELOC_LO16)
3861 If $at is already in use, we use a path which is suboptimal
3862 on superscalar processors.
3863 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3864 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3866 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3868 daddiu $reg,<sym> (BFD_RELOC_LO16)
3870 For GP relative symbols in 64bit address space we can use
3871 the same sequence as in 32bit address space. */
3872 if (HAVE_64BIT_SYMBOLS
)
3874 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3875 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3877 relax_start (ep
->X_add_symbol
);
3878 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3879 mips_gp_register
, BFD_RELOC_GPREL16
);
3883 if (*used_at
== 0 && !mips_opts
.noat
)
3885 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3886 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3887 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3888 BFD_RELOC_MIPS_HIGHER
);
3889 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3890 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3891 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3896 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3897 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3898 BFD_RELOC_MIPS_HIGHER
);
3899 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3900 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3901 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3902 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3905 if (mips_relax
.sequence
)
3910 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3911 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3913 relax_start (ep
->X_add_symbol
);
3914 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3915 mips_gp_register
, BFD_RELOC_GPREL16
);
3918 macro_build_lui (ep
, reg
);
3919 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3920 reg
, reg
, BFD_RELOC_LO16
);
3921 if (mips_relax
.sequence
)
3925 else if (!mips_big_got
)
3929 /* If this is a reference to an external symbol, we want
3930 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3932 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3934 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3935 If there is a constant, it must be added in after.
3937 If we have NewABI, we want
3938 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3939 unless we're referencing a global symbol with a non-zero
3940 offset, in which case cst must be added separately. */
3943 if (ep
->X_add_number
)
3945 ex
.X_add_number
= ep
->X_add_number
;
3946 ep
->X_add_number
= 0;
3947 relax_start (ep
->X_add_symbol
);
3948 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3949 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3950 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3951 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3952 ex
.X_op
= O_constant
;
3953 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3954 reg
, reg
, BFD_RELOC_LO16
);
3955 ep
->X_add_number
= ex
.X_add_number
;
3958 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3959 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3960 if (mips_relax
.sequence
)
3965 ex
.X_add_number
= ep
->X_add_number
;
3966 ep
->X_add_number
= 0;
3967 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3968 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3970 relax_start (ep
->X_add_symbol
);
3972 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3976 if (ex
.X_add_number
!= 0)
3978 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3979 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3980 ex
.X_op
= O_constant
;
3981 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3982 reg
, reg
, BFD_RELOC_LO16
);
3986 else if (mips_big_got
)
3990 /* This is the large GOT case. If this is a reference to an
3991 external symbol, we want
3992 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3994 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3996 Otherwise, for a reference to a local symbol in old ABI, we want
3997 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3999 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4000 If there is a constant, it must be added in after.
4002 In the NewABI, for local symbols, with or without offsets, we want:
4003 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4004 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4008 ex
.X_add_number
= ep
->X_add_number
;
4009 ep
->X_add_number
= 0;
4010 relax_start (ep
->X_add_symbol
);
4011 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4012 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4013 reg
, reg
, mips_gp_register
);
4014 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4015 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4016 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4017 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4018 else if (ex
.X_add_number
)
4020 ex
.X_op
= O_constant
;
4021 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4025 ep
->X_add_number
= ex
.X_add_number
;
4027 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4028 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4029 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4030 BFD_RELOC_MIPS_GOT_OFST
);
4035 ex
.X_add_number
= ep
->X_add_number
;
4036 ep
->X_add_number
= 0;
4037 relax_start (ep
->X_add_symbol
);
4038 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4039 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4040 reg
, reg
, mips_gp_register
);
4041 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4042 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4044 if (reg_needs_delay (mips_gp_register
))
4046 /* We need a nop before loading from $gp. This special
4047 check is required because the lui which starts the main
4048 instruction stream does not refer to $gp, and so will not
4049 insert the nop which may be required. */
4050 macro_build (NULL
, "nop", "");
4052 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4053 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4055 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4059 if (ex
.X_add_number
!= 0)
4061 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4062 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4063 ex
.X_op
= O_constant
;
4064 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4072 if (mips_opts
.noat
&& *used_at
== 1)
4073 as_bad (_("Macro used $at after \".set noat\""));
4076 /* Move the contents of register SOURCE into register DEST. */
4079 move_register (int dest
, int source
)
4081 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4085 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4086 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4087 The two alternatives are:
4089 Global symbol Local sybmol
4090 ------------- ------------
4091 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4093 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4095 load_got_offset emits the first instruction and add_got_offset
4096 emits the second for a 16-bit offset or add_got_offset_hilo emits
4097 a sequence to add a 32-bit offset using a scratch register. */
4100 load_got_offset (int dest
, expressionS
*local
)
4105 global
.X_add_number
= 0;
4107 relax_start (local
->X_add_symbol
);
4108 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4109 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4111 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4112 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4117 add_got_offset (int dest
, expressionS
*local
)
4121 global
.X_op
= O_constant
;
4122 global
.X_op_symbol
= NULL
;
4123 global
.X_add_symbol
= NULL
;
4124 global
.X_add_number
= local
->X_add_number
;
4126 relax_start (local
->X_add_symbol
);
4127 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4128 dest
, dest
, BFD_RELOC_LO16
);
4130 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4135 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4138 int hold_mips_optimize
;
4140 global
.X_op
= O_constant
;
4141 global
.X_op_symbol
= NULL
;
4142 global
.X_add_symbol
= NULL
;
4143 global
.X_add_number
= local
->X_add_number
;
4145 relax_start (local
->X_add_symbol
);
4146 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4148 /* Set mips_optimize around the lui instruction to avoid
4149 inserting an unnecessary nop after the lw. */
4150 hold_mips_optimize
= mips_optimize
;
4152 macro_build_lui (&global
, tmp
);
4153 mips_optimize
= hold_mips_optimize
;
4154 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4157 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4162 * This routine implements the seemingly endless macro or synthesized
4163 * instructions and addressing modes in the mips assembly language. Many
4164 * of these macros are simple and are similar to each other. These could
4165 * probably be handled by some kind of table or grammar approach instead of
4166 * this verbose method. Others are not simple macros but are more like
4167 * optimizing code generation.
4168 * One interesting optimization is when several store macros appear
4169 * consecutively that would load AT with the upper half of the same address.
4170 * The ensuing load upper instructions are ommited. This implies some kind
4171 * of global optimization. We currently only optimize within a single macro.
4172 * For many of the load and store macros if the address is specified as a
4173 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4174 * first load register 'at' with zero and use it as the base register. The
4175 * mips assembler simply uses register $zero. Just one tiny optimization
4179 macro (struct mips_cl_insn
*ip
)
4181 register int treg
, sreg
, dreg
, breg
;
4197 bfd_reloc_code_real_type r
;
4198 int hold_mips_optimize
;
4200 assert (! mips_opts
.mips16
);
4202 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4203 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4204 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4205 mask
= ip
->insn_mo
->mask
;
4207 expr1
.X_op
= O_constant
;
4208 expr1
.X_op_symbol
= NULL
;
4209 expr1
.X_add_symbol
= NULL
;
4210 expr1
.X_add_number
= 1;
4224 expr1
.X_add_number
= 8;
4225 macro_build (&expr1
, "bgez", "s,p", sreg
);
4227 macro_build (NULL
, "nop", "", 0);
4229 move_register (dreg
, sreg
);
4230 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4253 if (imm_expr
.X_op
== O_constant
4254 && imm_expr
.X_add_number
>= -0x8000
4255 && imm_expr
.X_add_number
< 0x8000)
4257 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4261 load_register (AT
, &imm_expr
, dbl
);
4262 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4281 if (imm_expr
.X_op
== O_constant
4282 && imm_expr
.X_add_number
>= 0
4283 && imm_expr
.X_add_number
< 0x10000)
4285 if (mask
!= M_NOR_I
)
4286 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4289 macro_build (&imm_expr
, "ori", "t,r,i",
4290 treg
, sreg
, BFD_RELOC_LO16
);
4291 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4297 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4298 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4315 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4317 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4321 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4322 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4330 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4335 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4339 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4340 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4346 /* check for > max integer */
4347 maxnum
= 0x7fffffff;
4348 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4355 if (imm_expr
.X_op
== O_constant
4356 && imm_expr
.X_add_number
>= maxnum
4357 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4360 /* result is always false */
4362 macro_build (NULL
, "nop", "", 0);
4364 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4367 if (imm_expr
.X_op
!= O_constant
)
4368 as_bad (_("Unsupported large constant"));
4369 ++imm_expr
.X_add_number
;
4373 if (mask
== M_BGEL_I
)
4375 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4377 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4380 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4382 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4385 maxnum
= 0x7fffffff;
4386 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4393 maxnum
= - maxnum
- 1;
4394 if (imm_expr
.X_op
== O_constant
4395 && imm_expr
.X_add_number
<= maxnum
4396 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4399 /* result is always true */
4400 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4401 macro_build (&offset_expr
, "b", "p");
4406 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4416 macro_build (&offset_expr
, likely
? "beql" : "beq",
4421 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4422 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4430 && imm_expr
.X_op
== O_constant
4431 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4433 if (imm_expr
.X_op
!= O_constant
)
4434 as_bad (_("Unsupported large constant"));
4435 ++imm_expr
.X_add_number
;
4439 if (mask
== M_BGEUL_I
)
4441 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4443 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4445 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4451 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4459 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4464 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4468 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4469 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4477 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4484 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4485 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4493 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4498 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4502 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4503 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4509 maxnum
= 0x7fffffff;
4510 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4517 if (imm_expr
.X_op
== O_constant
4518 && imm_expr
.X_add_number
>= maxnum
4519 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4521 if (imm_expr
.X_op
!= O_constant
)
4522 as_bad (_("Unsupported large constant"));
4523 ++imm_expr
.X_add_number
;
4527 if (mask
== M_BLTL_I
)
4529 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4531 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4534 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4536 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4541 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4549 macro_build (&offset_expr
, likely
? "beql" : "beq",
4556 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4557 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4565 && imm_expr
.X_op
== O_constant
4566 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4568 if (imm_expr
.X_op
!= O_constant
)
4569 as_bad (_("Unsupported large constant"));
4570 ++imm_expr
.X_add_number
;
4574 if (mask
== M_BLTUL_I
)
4576 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4578 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4580 macro_build (&offset_expr
, likely
? "beql" : "beq",
4586 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4594 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4599 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4603 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4604 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4614 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4619 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4620 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4628 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4630 as_bad (_("Unsupported large constant"));
4635 pos
= (unsigned long) imm_expr
.X_add_number
;
4636 size
= (unsigned long) imm2_expr
.X_add_number
;
4641 as_bad (_("Improper position (%lu)"), pos
);
4644 if (size
== 0 || size
> 64
4645 || (pos
+ size
- 1) > 63)
4647 as_bad (_("Improper extract size (%lu, position %lu)"),
4652 if (size
<= 32 && pos
< 32)
4657 else if (size
<= 32)
4667 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4676 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4678 as_bad (_("Unsupported large constant"));
4683 pos
= (unsigned long) imm_expr
.X_add_number
;
4684 size
= (unsigned long) imm2_expr
.X_add_number
;
4689 as_bad (_("Improper position (%lu)"), pos
);
4692 if (size
== 0 || size
> 64
4693 || (pos
+ size
- 1) > 63)
4695 as_bad (_("Improper insert size (%lu, position %lu)"),
4700 if (pos
< 32 && (pos
+ size
- 1) < 32)
4715 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4732 as_warn (_("Divide by zero."));
4734 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4736 macro_build (NULL
, "break", "c", 7);
4743 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4744 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4748 expr1
.X_add_number
= 8;
4749 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4750 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4751 macro_build (NULL
, "break", "c", 7);
4753 expr1
.X_add_number
= -1;
4755 load_register (AT
, &expr1
, dbl
);
4756 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4757 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4760 expr1
.X_add_number
= 1;
4761 load_register (AT
, &expr1
, dbl
);
4762 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4766 expr1
.X_add_number
= 0x80000000;
4767 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4771 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4772 /* We want to close the noreorder block as soon as possible, so
4773 that later insns are available for delay slot filling. */
4778 expr1
.X_add_number
= 8;
4779 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4780 macro_build (NULL
, "nop", "", 0);
4782 /* We want to close the noreorder block as soon as possible, so
4783 that later insns are available for delay slot filling. */
4786 macro_build (NULL
, "break", "c", 6);
4788 macro_build (NULL
, s
, "d", dreg
);
4827 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4829 as_warn (_("Divide by zero."));
4831 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4833 macro_build (NULL
, "break", "c", 7);
4836 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4838 if (strcmp (s2
, "mflo") == 0)
4839 move_register (dreg
, sreg
);
4841 move_register (dreg
, 0);
4844 if (imm_expr
.X_op
== O_constant
4845 && imm_expr
.X_add_number
== -1
4846 && s
[strlen (s
) - 1] != 'u')
4848 if (strcmp (s2
, "mflo") == 0)
4850 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4853 move_register (dreg
, 0);
4858 load_register (AT
, &imm_expr
, dbl
);
4859 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4860 macro_build (NULL
, s2
, "d", dreg
);
4882 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4883 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4884 /* We want to close the noreorder block as soon as possible, so
4885 that later insns are available for delay slot filling. */
4890 expr1
.X_add_number
= 8;
4891 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4892 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4894 /* We want to close the noreorder block as soon as possible, so
4895 that later insns are available for delay slot filling. */
4897 macro_build (NULL
, "break", "c", 7);
4899 macro_build (NULL
, s2
, "d", dreg
);
4911 /* Load the address of a symbol into a register. If breg is not
4912 zero, we then add a base register to it. */
4914 if (dbl
&& HAVE_32BIT_GPRS
)
4915 as_warn (_("dla used to load 32-bit register"));
4917 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4918 as_warn (_("la used to load 64-bit address"));
4920 if (offset_expr
.X_op
== O_constant
4921 && offset_expr
.X_add_number
>= -0x8000
4922 && offset_expr
.X_add_number
< 0x8000)
4924 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4925 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4929 if (!mips_opts
.noat
&& (treg
== breg
))
4939 if (offset_expr
.X_op
!= O_symbol
4940 && offset_expr
.X_op
!= O_constant
)
4942 as_bad (_("expression too complex"));
4943 offset_expr
.X_op
= O_constant
;
4946 if (offset_expr
.X_op
== O_constant
)
4947 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4948 else if (mips_pic
== NO_PIC
)
4950 /* If this is a reference to a GP relative symbol, we want
4951 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4953 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4954 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4955 If we have a constant, we need two instructions anyhow,
4956 so we may as well always use the latter form.
4958 With 64bit address space and a usable $at we want
4959 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4960 lui $at,<sym> (BFD_RELOC_HI16_S)
4961 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4962 daddiu $at,<sym> (BFD_RELOC_LO16)
4964 daddu $tempreg,$tempreg,$at
4966 If $at is already in use, we use a path which is suboptimal
4967 on superscalar processors.
4968 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4969 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4971 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4973 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4975 For GP relative symbols in 64bit address space we can use
4976 the same sequence as in 32bit address space. */
4977 if (HAVE_64BIT_SYMBOLS
)
4979 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4980 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4982 relax_start (offset_expr
.X_add_symbol
);
4983 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4984 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4988 if (used_at
== 0 && !mips_opts
.noat
)
4990 macro_build (&offset_expr
, "lui", "t,u",
4991 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4992 macro_build (&offset_expr
, "lui", "t,u",
4993 AT
, BFD_RELOC_HI16_S
);
4994 macro_build (&offset_expr
, "daddiu", "t,r,j",
4995 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4996 macro_build (&offset_expr
, "daddiu", "t,r,j",
4997 AT
, AT
, BFD_RELOC_LO16
);
4998 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4999 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5004 macro_build (&offset_expr
, "lui", "t,u",
5005 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5006 macro_build (&offset_expr
, "daddiu", "t,r,j",
5007 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5008 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5009 macro_build (&offset_expr
, "daddiu", "t,r,j",
5010 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5011 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5012 macro_build (&offset_expr
, "daddiu", "t,r,j",
5013 tempreg
, tempreg
, BFD_RELOC_LO16
);
5016 if (mips_relax
.sequence
)
5021 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5022 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5024 relax_start (offset_expr
.X_add_symbol
);
5025 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5026 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5029 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5030 as_bad (_("offset too large"));
5031 macro_build_lui (&offset_expr
, tempreg
);
5032 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5033 tempreg
, tempreg
, BFD_RELOC_LO16
);
5034 if (mips_relax
.sequence
)
5038 else if (!mips_big_got
&& !HAVE_NEWABI
)
5040 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5042 /* If this is a reference to an external symbol, and there
5043 is no constant, we want
5044 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5045 or for lca or if tempreg is PIC_CALL_REG
5046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5047 For a local symbol, we want
5048 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5050 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5052 If we have a small constant, and this is a reference to
5053 an external symbol, we want
5054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5056 addiu $tempreg,$tempreg,<constant>
5057 For a local symbol, we want the same instruction
5058 sequence, but we output a BFD_RELOC_LO16 reloc on the
5061 If we have a large constant, and this is a reference to
5062 an external symbol, we want
5063 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5064 lui $at,<hiconstant>
5065 addiu $at,$at,<loconstant>
5066 addu $tempreg,$tempreg,$at
5067 For a local symbol, we want the same instruction
5068 sequence, but we output a BFD_RELOC_LO16 reloc on the
5072 if (offset_expr
.X_add_number
== 0)
5074 if (mips_pic
== SVR4_PIC
5076 && (call
|| tempreg
== PIC_CALL_REG
))
5077 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5079 relax_start (offset_expr
.X_add_symbol
);
5080 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5081 lw_reloc_type
, mips_gp_register
);
5084 /* We're going to put in an addu instruction using
5085 tempreg, so we may as well insert the nop right
5090 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5091 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5093 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5094 tempreg
, tempreg
, BFD_RELOC_LO16
);
5096 /* FIXME: If breg == 0, and the next instruction uses
5097 $tempreg, then if this variant case is used an extra
5098 nop will be generated. */
5100 else if (offset_expr
.X_add_number
>= -0x8000
5101 && offset_expr
.X_add_number
< 0x8000)
5103 load_got_offset (tempreg
, &offset_expr
);
5105 add_got_offset (tempreg
, &offset_expr
);
5109 expr1
.X_add_number
= offset_expr
.X_add_number
;
5110 offset_expr
.X_add_number
=
5111 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5112 load_got_offset (tempreg
, &offset_expr
);
5113 offset_expr
.X_add_number
= expr1
.X_add_number
;
5114 /* If we are going to add in a base register, and the
5115 target register and the base register are the same,
5116 then we are using AT as a temporary register. Since
5117 we want to load the constant into AT, we add our
5118 current AT (from the global offset table) and the
5119 register into the register now, and pretend we were
5120 not using a base register. */
5124 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5129 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5133 else if (!mips_big_got
&& HAVE_NEWABI
)
5135 int add_breg_early
= 0;
5137 /* If this is a reference to an external, and there is no
5138 constant, or local symbol (*), with or without a
5140 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5141 or for lca or if tempreg is PIC_CALL_REG
5142 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5144 If we have a small constant, and this is a reference to
5145 an external symbol, we want
5146 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5147 addiu $tempreg,$tempreg,<constant>
5149 If we have a large constant, and this is a reference to
5150 an external symbol, we want
5151 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5152 lui $at,<hiconstant>
5153 addiu $at,$at,<loconstant>
5154 addu $tempreg,$tempreg,$at
5156 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5157 local symbols, even though it introduces an additional
5160 if (offset_expr
.X_add_number
)
5162 expr1
.X_add_number
= offset_expr
.X_add_number
;
5163 offset_expr
.X_add_number
= 0;
5165 relax_start (offset_expr
.X_add_symbol
);
5166 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5167 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5169 if (expr1
.X_add_number
>= -0x8000
5170 && expr1
.X_add_number
< 0x8000)
5172 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5173 tempreg
, tempreg
, BFD_RELOC_LO16
);
5175 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5179 /* If we are going to add in a base register, and the
5180 target register and the base register are the same,
5181 then we are using AT as a temporary register. Since
5182 we want to load the constant into AT, we add our
5183 current AT (from the global offset table) and the
5184 register into the register now, and pretend we were
5185 not using a base register. */
5190 assert (tempreg
== AT
);
5191 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5197 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5198 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5204 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5207 offset_expr
.X_add_number
= expr1
.X_add_number
;
5209 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5210 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5213 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5214 treg
, tempreg
, breg
);
5220 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5222 relax_start (offset_expr
.X_add_symbol
);
5223 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5224 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5226 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5227 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5232 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5233 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5236 else if (mips_big_got
&& !HAVE_NEWABI
)
5239 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5240 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5241 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5243 /* This is the large GOT case. If this is a reference to an
5244 external symbol, and there is no constant, we want
5245 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5246 addu $tempreg,$tempreg,$gp
5247 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5248 or for lca or if tempreg is PIC_CALL_REG
5249 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5250 addu $tempreg,$tempreg,$gp
5251 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5252 For a local symbol, we want
5253 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5255 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5257 If we have a small constant, and this is a reference to
5258 an external symbol, we want
5259 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5260 addu $tempreg,$tempreg,$gp
5261 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5263 addiu $tempreg,$tempreg,<constant>
5264 For a local symbol, we want
5265 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5267 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5269 If we have a large constant, and this is a reference to
5270 an external symbol, we want
5271 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5272 addu $tempreg,$tempreg,$gp
5273 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5274 lui $at,<hiconstant>
5275 addiu $at,$at,<loconstant>
5276 addu $tempreg,$tempreg,$at
5277 For a local symbol, we want
5278 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5279 lui $at,<hiconstant>
5280 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5281 addu $tempreg,$tempreg,$at
5284 expr1
.X_add_number
= offset_expr
.X_add_number
;
5285 offset_expr
.X_add_number
= 0;
5286 relax_start (offset_expr
.X_add_symbol
);
5287 gpdelay
= reg_needs_delay (mips_gp_register
);
5288 if (expr1
.X_add_number
== 0 && breg
== 0
5289 && (call
|| tempreg
== PIC_CALL_REG
))
5291 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5292 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5294 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5295 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5296 tempreg
, tempreg
, mips_gp_register
);
5297 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5298 tempreg
, lw_reloc_type
, tempreg
);
5299 if (expr1
.X_add_number
== 0)
5303 /* We're going to put in an addu instruction using
5304 tempreg, so we may as well insert the nop right
5309 else if (expr1
.X_add_number
>= -0x8000
5310 && expr1
.X_add_number
< 0x8000)
5313 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5314 tempreg
, tempreg
, BFD_RELOC_LO16
);
5320 /* If we are going to add in a base register, and the
5321 target register and the base register are the same,
5322 then we are using AT as a temporary register. Since
5323 we want to load the constant into AT, we add our
5324 current AT (from the global offset table) and the
5325 register into the register now, and pretend we were
5326 not using a base register. */
5331 assert (tempreg
== AT
);
5333 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5338 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5339 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5343 offset_expr
.X_add_number
=
5344 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5349 /* This is needed because this instruction uses $gp, but
5350 the first instruction on the main stream does not. */
5351 macro_build (NULL
, "nop", "");
5354 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5355 local_reloc_type
, mips_gp_register
);
5356 if (expr1
.X_add_number
>= -0x8000
5357 && expr1
.X_add_number
< 0x8000)
5360 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5361 tempreg
, tempreg
, BFD_RELOC_LO16
);
5362 /* FIXME: If add_number is 0, and there was no base
5363 register, the external symbol case ended with a load,
5364 so if the symbol turns out to not be external, and
5365 the next instruction uses tempreg, an unnecessary nop
5366 will be inserted. */
5372 /* We must add in the base register now, as in the
5373 external symbol case. */
5374 assert (tempreg
== AT
);
5376 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5379 /* We set breg to 0 because we have arranged to add
5380 it in in both cases. */
5384 macro_build_lui (&expr1
, AT
);
5385 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5386 AT
, AT
, BFD_RELOC_LO16
);
5387 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5388 tempreg
, tempreg
, AT
);
5393 else if (mips_big_got
&& HAVE_NEWABI
)
5395 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5396 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5397 int add_breg_early
= 0;
5399 /* This is the large GOT case. If this is a reference to an
5400 external symbol, and there is no constant, we want
5401 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5402 add $tempreg,$tempreg,$gp
5403 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5404 or for lca or if tempreg is PIC_CALL_REG
5405 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5406 add $tempreg,$tempreg,$gp
5407 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5409 If we have a small constant, and this is a reference to
5410 an external symbol, we want
5411 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5412 add $tempreg,$tempreg,$gp
5413 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5414 addi $tempreg,$tempreg,<constant>
5416 If we have a large constant, and this is a reference to
5417 an external symbol, we want
5418 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5419 addu $tempreg,$tempreg,$gp
5420 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5421 lui $at,<hiconstant>
5422 addi $at,$at,<loconstant>
5423 add $tempreg,$tempreg,$at
5425 If we have NewABI, and we know it's a local symbol, we want
5426 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5427 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5428 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5430 relax_start (offset_expr
.X_add_symbol
);
5432 expr1
.X_add_number
= offset_expr
.X_add_number
;
5433 offset_expr
.X_add_number
= 0;
5435 if (expr1
.X_add_number
== 0 && breg
== 0
5436 && (call
|| tempreg
== PIC_CALL_REG
))
5438 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5439 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5441 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5442 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5443 tempreg
, tempreg
, mips_gp_register
);
5444 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5445 tempreg
, lw_reloc_type
, tempreg
);
5447 if (expr1
.X_add_number
== 0)
5449 else if (expr1
.X_add_number
>= -0x8000
5450 && expr1
.X_add_number
< 0x8000)
5452 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5453 tempreg
, tempreg
, BFD_RELOC_LO16
);
5455 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5459 /* If we are going to add in a base register, and the
5460 target register and the base register are the same,
5461 then we are using AT as a temporary register. Since
5462 we want to load the constant into AT, we add our
5463 current AT (from the global offset table) and the
5464 register into the register now, and pretend we were
5465 not using a base register. */
5470 assert (tempreg
== AT
);
5471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5477 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5478 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5483 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5486 offset_expr
.X_add_number
= expr1
.X_add_number
;
5487 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5488 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5489 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5490 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5493 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5494 treg
, tempreg
, breg
);
5504 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5508 /* The j instruction may not be used in PIC code, since it
5509 requires an absolute address. We convert it to a b
5511 if (mips_pic
== NO_PIC
)
5512 macro_build (&offset_expr
, "j", "a");
5514 macro_build (&offset_expr
, "b", "p");
5517 /* The jal instructions must be handled as macros because when
5518 generating PIC code they expand to multi-instruction
5519 sequences. Normally they are simple instructions. */
5524 if (mips_pic
== NO_PIC
)
5525 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5528 if (sreg
!= PIC_CALL_REG
)
5529 as_warn (_("MIPS PIC call to register other than $25"));
5531 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5532 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5534 if (mips_cprestore_offset
< 0)
5535 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5538 if (! mips_frame_reg_valid
)
5540 as_warn (_("No .frame pseudo-op used in PIC code"));
5541 /* Quiet this warning. */
5542 mips_frame_reg_valid
= 1;
5544 if (! mips_cprestore_valid
)
5546 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5547 /* Quiet this warning. */
5548 mips_cprestore_valid
= 1;
5550 expr1
.X_add_number
= mips_cprestore_offset
;
5551 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5554 HAVE_64BIT_ADDRESSES
);
5562 if (mips_pic
== NO_PIC
)
5563 macro_build (&offset_expr
, "jal", "a");
5564 else if (mips_pic
== SVR4_PIC
)
5566 /* If this is a reference to an external symbol, and we are
5567 using a small GOT, we want
5568 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5572 lw $gp,cprestore($sp)
5573 The cprestore value is set using the .cprestore
5574 pseudo-op. If we are using a big GOT, we want
5575 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5577 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5581 lw $gp,cprestore($sp)
5582 If the symbol is not external, we want
5583 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5585 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5588 lw $gp,cprestore($sp)
5590 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5591 sequences above, minus nops, unless the symbol is local,
5592 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5598 relax_start (offset_expr
.X_add_symbol
);
5599 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5600 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5603 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5604 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5610 relax_start (offset_expr
.X_add_symbol
);
5611 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5612 BFD_RELOC_MIPS_CALL_HI16
);
5613 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5614 PIC_CALL_REG
, mips_gp_register
);
5615 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5616 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5619 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5620 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5622 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5623 PIC_CALL_REG
, PIC_CALL_REG
,
5624 BFD_RELOC_MIPS_GOT_OFST
);
5628 macro_build_jalr (&offset_expr
);
5632 relax_start (offset_expr
.X_add_symbol
);
5635 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5636 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5645 gpdelay
= reg_needs_delay (mips_gp_register
);
5646 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5647 BFD_RELOC_MIPS_CALL_HI16
);
5648 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5649 PIC_CALL_REG
, mips_gp_register
);
5650 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5651 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5656 macro_build (NULL
, "nop", "");
5658 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5659 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5662 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5663 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5665 macro_build_jalr (&offset_expr
);
5667 if (mips_cprestore_offset
< 0)
5668 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5671 if (! mips_frame_reg_valid
)
5673 as_warn (_("No .frame pseudo-op used in PIC code"));
5674 /* Quiet this warning. */
5675 mips_frame_reg_valid
= 1;
5677 if (! mips_cprestore_valid
)
5679 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5680 /* Quiet this warning. */
5681 mips_cprestore_valid
= 1;
5683 if (mips_opts
.noreorder
)
5684 macro_build (NULL
, "nop", "");
5685 expr1
.X_add_number
= mips_cprestore_offset
;
5686 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5689 HAVE_64BIT_ADDRESSES
);
5693 else if (mips_pic
== VXWORKS_PIC
)
5694 as_bad (_("Non-PIC jump used in PIC library"));
5717 /* Itbl support may require additional care here. */
5722 /* Itbl support may require additional care here. */
5727 /* Itbl support may require additional care here. */
5732 /* Itbl support may require additional care here. */
5744 if (mips_opts
.arch
== CPU_R4650
)
5746 as_bad (_("opcode not supported on this processor"));
5750 /* Itbl support may require additional care here. */
5755 /* Itbl support may require additional care here. */
5760 /* Itbl support may require additional care here. */
5780 if (breg
== treg
|| coproc
|| lr
)
5801 /* Itbl support may require additional care here. */
5806 /* Itbl support may require additional care here. */
5811 /* Itbl support may require additional care here. */
5816 /* Itbl support may require additional care here. */
5835 if (mips_opts
.arch
== CPU_R4650
)
5837 as_bad (_("opcode not supported on this processor"));
5842 /* Itbl support may require additional care here. */
5846 /* Itbl support may require additional care here. */
5851 /* Itbl support may require additional care here. */
5863 /* Itbl support may require additional care here. */
5864 if (mask
== M_LWC1_AB
5865 || mask
== M_SWC1_AB
5866 || mask
== M_LDC1_AB
5867 || mask
== M_SDC1_AB
5871 else if (mask
== M_CACHE_AB
)
5878 if (offset_expr
.X_op
!= O_constant
5879 && offset_expr
.X_op
!= O_symbol
)
5881 as_bad (_("expression too complex"));
5882 offset_expr
.X_op
= O_constant
;
5885 if (HAVE_32BIT_ADDRESSES
5886 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5890 sprintf_vma (value
, offset_expr
.X_add_number
);
5891 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5894 /* A constant expression in PIC code can be handled just as it
5895 is in non PIC code. */
5896 if (offset_expr
.X_op
== O_constant
)
5898 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5899 & ~(bfd_vma
) 0xffff);
5900 normalize_address_expr (&expr1
);
5901 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5903 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5904 tempreg
, tempreg
, breg
);
5905 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5907 else if (mips_pic
== NO_PIC
)
5909 /* If this is a reference to a GP relative symbol, and there
5910 is no base register, we want
5911 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5912 Otherwise, if there is no base register, we want
5913 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5914 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5915 If we have a constant, we need two instructions anyhow,
5916 so we always use the latter form.
5918 If we have a base register, and this is a reference to a
5919 GP relative symbol, we want
5920 addu $tempreg,$breg,$gp
5921 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5923 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5924 addu $tempreg,$tempreg,$breg
5925 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5926 With a constant we always use the latter case.
5928 With 64bit address space and no base register and $at usable,
5930 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5931 lui $at,<sym> (BFD_RELOC_HI16_S)
5932 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5935 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5936 If we have a base register, we want
5937 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5938 lui $at,<sym> (BFD_RELOC_HI16_S)
5939 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5943 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5945 Without $at we can't generate the optimal path for superscalar
5946 processors here since this would require two temporary registers.
5947 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5948 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5950 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5952 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5953 If we have a base register, we want
5954 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5955 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5957 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5959 daddu $tempreg,$tempreg,$breg
5960 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5962 For GP relative symbols in 64bit address space we can use
5963 the same sequence as in 32bit address space. */
5964 if (HAVE_64BIT_SYMBOLS
)
5966 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5967 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5969 relax_start (offset_expr
.X_add_symbol
);
5972 macro_build (&offset_expr
, s
, fmt
, treg
,
5973 BFD_RELOC_GPREL16
, mips_gp_register
);
5977 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5978 tempreg
, breg
, mips_gp_register
);
5979 macro_build (&offset_expr
, s
, fmt
, treg
,
5980 BFD_RELOC_GPREL16
, tempreg
);
5985 if (used_at
== 0 && !mips_opts
.noat
)
5987 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5988 BFD_RELOC_MIPS_HIGHEST
);
5989 macro_build (&offset_expr
, "lui", "t,u", AT
,
5991 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5992 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5994 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5995 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5996 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5997 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6003 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6004 BFD_RELOC_MIPS_HIGHEST
);
6005 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6006 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6007 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6008 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6009 tempreg
, BFD_RELOC_HI16_S
);
6010 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6012 macro_build (NULL
, "daddu", "d,v,t",
6013 tempreg
, tempreg
, breg
);
6014 macro_build (&offset_expr
, s
, fmt
, treg
,
6015 BFD_RELOC_LO16
, tempreg
);
6018 if (mips_relax
.sequence
)
6025 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6026 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6028 relax_start (offset_expr
.X_add_symbol
);
6029 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6033 macro_build_lui (&offset_expr
, tempreg
);
6034 macro_build (&offset_expr
, s
, fmt
, treg
,
6035 BFD_RELOC_LO16
, tempreg
);
6036 if (mips_relax
.sequence
)
6041 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6042 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6044 relax_start (offset_expr
.X_add_symbol
);
6045 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6046 tempreg
, breg
, mips_gp_register
);
6047 macro_build (&offset_expr
, s
, fmt
, treg
,
6048 BFD_RELOC_GPREL16
, tempreg
);
6051 macro_build_lui (&offset_expr
, tempreg
);
6052 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6053 tempreg
, tempreg
, breg
);
6054 macro_build (&offset_expr
, s
, fmt
, treg
,
6055 BFD_RELOC_LO16
, tempreg
);
6056 if (mips_relax
.sequence
)
6060 else if (!mips_big_got
)
6062 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6064 /* If this is a reference to an external symbol, we want
6065 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6067 <op> $treg,0($tempreg)
6069 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6071 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6072 <op> $treg,0($tempreg)
6075 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6076 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6078 If there is a base register, we add it to $tempreg before
6079 the <op>. If there is a constant, we stick it in the
6080 <op> instruction. We don't handle constants larger than
6081 16 bits, because we have no way to load the upper 16 bits
6082 (actually, we could handle them for the subset of cases
6083 in which we are not using $at). */
6084 assert (offset_expr
.X_op
== O_symbol
);
6087 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6088 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6090 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6091 tempreg
, tempreg
, breg
);
6092 macro_build (&offset_expr
, s
, fmt
, treg
,
6093 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6096 expr1
.X_add_number
= offset_expr
.X_add_number
;
6097 offset_expr
.X_add_number
= 0;
6098 if (expr1
.X_add_number
< -0x8000
6099 || expr1
.X_add_number
>= 0x8000)
6100 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6101 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6102 lw_reloc_type
, mips_gp_register
);
6104 relax_start (offset_expr
.X_add_symbol
);
6106 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6107 tempreg
, BFD_RELOC_LO16
);
6110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6111 tempreg
, tempreg
, breg
);
6112 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6114 else if (mips_big_got
&& !HAVE_NEWABI
)
6118 /* If this is a reference to an external symbol, we want
6119 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6120 addu $tempreg,$tempreg,$gp
6121 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6122 <op> $treg,0($tempreg)
6124 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6126 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6127 <op> $treg,0($tempreg)
6128 If there is a base register, we add it to $tempreg before
6129 the <op>. If there is a constant, we stick it in the
6130 <op> instruction. We don't handle constants larger than
6131 16 bits, because we have no way to load the upper 16 bits
6132 (actually, we could handle them for the subset of cases
6133 in which we are not using $at). */
6134 assert (offset_expr
.X_op
== O_symbol
);
6135 expr1
.X_add_number
= offset_expr
.X_add_number
;
6136 offset_expr
.X_add_number
= 0;
6137 if (expr1
.X_add_number
< -0x8000
6138 || expr1
.X_add_number
>= 0x8000)
6139 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6140 gpdelay
= reg_needs_delay (mips_gp_register
);
6141 relax_start (offset_expr
.X_add_symbol
);
6142 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6143 BFD_RELOC_MIPS_GOT_HI16
);
6144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6146 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6147 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6150 macro_build (NULL
, "nop", "");
6151 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6152 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6154 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6155 tempreg
, BFD_RELOC_LO16
);
6159 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6160 tempreg
, tempreg
, breg
);
6161 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6163 else if (mips_big_got
&& HAVE_NEWABI
)
6165 /* If this is a reference to an external symbol, we want
6166 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6167 add $tempreg,$tempreg,$gp
6168 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6169 <op> $treg,<ofst>($tempreg)
6170 Otherwise, for local symbols, we want:
6171 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6172 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6173 assert (offset_expr
.X_op
== O_symbol
);
6174 expr1
.X_add_number
= offset_expr
.X_add_number
;
6175 offset_expr
.X_add_number
= 0;
6176 if (expr1
.X_add_number
< -0x8000
6177 || expr1
.X_add_number
>= 0x8000)
6178 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6179 relax_start (offset_expr
.X_add_symbol
);
6180 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6181 BFD_RELOC_MIPS_GOT_HI16
);
6182 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6184 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6185 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6187 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6188 tempreg
, tempreg
, breg
);
6189 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6192 offset_expr
.X_add_number
= expr1
.X_add_number
;
6193 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6194 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6196 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6197 tempreg
, tempreg
, breg
);
6198 macro_build (&offset_expr
, s
, fmt
, treg
,
6199 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6209 load_register (treg
, &imm_expr
, 0);
6213 load_register (treg
, &imm_expr
, 1);
6217 if (imm_expr
.X_op
== O_constant
)
6220 load_register (AT
, &imm_expr
, 0);
6221 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6226 assert (offset_expr
.X_op
== O_symbol
6227 && strcmp (segment_name (S_GET_SEGMENT
6228 (offset_expr
.X_add_symbol
)),
6230 && offset_expr
.X_add_number
== 0);
6231 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6232 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6237 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6238 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6239 order 32 bits of the value and the low order 32 bits are either
6240 zero or in OFFSET_EXPR. */
6241 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6243 if (HAVE_64BIT_GPRS
)
6244 load_register (treg
, &imm_expr
, 1);
6249 if (target_big_endian
)
6261 load_register (hreg
, &imm_expr
, 0);
6264 if (offset_expr
.X_op
== O_absent
)
6265 move_register (lreg
, 0);
6268 assert (offset_expr
.X_op
== O_constant
);
6269 load_register (lreg
, &offset_expr
, 0);
6276 /* We know that sym is in the .rdata section. First we get the
6277 upper 16 bits of the address. */
6278 if (mips_pic
== NO_PIC
)
6280 macro_build_lui (&offset_expr
, AT
);
6285 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6286 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6290 /* Now we load the register(s). */
6291 if (HAVE_64BIT_GPRS
)
6294 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6299 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6302 /* FIXME: How in the world do we deal with the possible
6304 offset_expr
.X_add_number
+= 4;
6305 macro_build (&offset_expr
, "lw", "t,o(b)",
6306 treg
+ 1, BFD_RELOC_LO16
, AT
);
6312 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6313 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6314 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6315 the value and the low order 32 bits are either zero or in
6317 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6320 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6321 if (HAVE_64BIT_FPRS
)
6323 assert (HAVE_64BIT_GPRS
);
6324 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6328 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6329 if (offset_expr
.X_op
== O_absent
)
6330 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6333 assert (offset_expr
.X_op
== O_constant
);
6334 load_register (AT
, &offset_expr
, 0);
6335 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6341 assert (offset_expr
.X_op
== O_symbol
6342 && offset_expr
.X_add_number
== 0);
6343 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6344 if (strcmp (s
, ".lit8") == 0)
6346 if (mips_opts
.isa
!= ISA_MIPS1
)
6348 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6349 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6352 breg
= mips_gp_register
;
6353 r
= BFD_RELOC_MIPS_LITERAL
;
6358 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6360 if (mips_pic
!= NO_PIC
)
6361 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6362 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6365 /* FIXME: This won't work for a 64 bit address. */
6366 macro_build_lui (&offset_expr
, AT
);
6369 if (mips_opts
.isa
!= ISA_MIPS1
)
6371 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6372 treg
, BFD_RELOC_LO16
, AT
);
6381 if (mips_opts
.arch
== CPU_R4650
)
6383 as_bad (_("opcode not supported on this processor"));
6386 /* Even on a big endian machine $fn comes before $fn+1. We have
6387 to adjust when loading from memory. */
6390 assert (mips_opts
.isa
== ISA_MIPS1
);
6391 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6392 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6393 /* FIXME: A possible overflow which I don't know how to deal
6395 offset_expr
.X_add_number
+= 4;
6396 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6397 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6402 * The MIPS assembler seems to check for X_add_number not
6403 * being double aligned and generating:
6406 * addiu at,at,%lo(foo+1)
6409 * But, the resulting address is the same after relocation so why
6410 * generate the extra instruction?
6412 if (mips_opts
.arch
== CPU_R4650
)
6414 as_bad (_("opcode not supported on this processor"));
6417 /* Itbl support may require additional care here. */
6419 if (mips_opts
.isa
!= ISA_MIPS1
)
6430 if (mips_opts
.arch
== CPU_R4650
)
6432 as_bad (_("opcode not supported on this processor"));
6436 if (mips_opts
.isa
!= ISA_MIPS1
)
6444 /* Itbl support may require additional care here. */
6449 if (HAVE_64BIT_GPRS
)
6460 if (HAVE_64BIT_GPRS
)
6470 if (offset_expr
.X_op
!= O_symbol
6471 && offset_expr
.X_op
!= O_constant
)
6473 as_bad (_("expression too complex"));
6474 offset_expr
.X_op
= O_constant
;
6477 if (HAVE_32BIT_ADDRESSES
6478 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6482 sprintf_vma (value
, offset_expr
.X_add_number
);
6483 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6486 /* Even on a big endian machine $fn comes before $fn+1. We have
6487 to adjust when loading from memory. We set coproc if we must
6488 load $fn+1 first. */
6489 /* Itbl support may require additional care here. */
6490 if (! target_big_endian
)
6493 if (mips_pic
== NO_PIC
6494 || offset_expr
.X_op
== O_constant
)
6496 /* If this is a reference to a GP relative symbol, we want
6497 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6498 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6499 If we have a base register, we use this
6501 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6502 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6503 If this is not a GP relative symbol, we want
6504 lui $at,<sym> (BFD_RELOC_HI16_S)
6505 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6506 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6507 If there is a base register, we add it to $at after the
6508 lui instruction. If there is a constant, we always use
6510 if (offset_expr
.X_op
== O_symbol
6511 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6512 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6514 relax_start (offset_expr
.X_add_symbol
);
6517 tempreg
= mips_gp_register
;
6521 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6522 AT
, breg
, mips_gp_register
);
6527 /* Itbl support may require additional care here. */
6528 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6529 BFD_RELOC_GPREL16
, tempreg
);
6530 offset_expr
.X_add_number
+= 4;
6532 /* Set mips_optimize to 2 to avoid inserting an
6534 hold_mips_optimize
= mips_optimize
;
6536 /* Itbl support may require additional care here. */
6537 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6538 BFD_RELOC_GPREL16
, tempreg
);
6539 mips_optimize
= hold_mips_optimize
;
6543 /* We just generated two relocs. When tc_gen_reloc
6544 handles this case, it will skip the first reloc and
6545 handle the second. The second reloc already has an
6546 extra addend of 4, which we added above. We must
6547 subtract it out, and then subtract another 4 to make
6548 the first reloc come out right. The second reloc
6549 will come out right because we are going to add 4 to
6550 offset_expr when we build its instruction below.
6552 If we have a symbol, then we don't want to include
6553 the offset, because it will wind up being included
6554 when we generate the reloc. */
6556 if (offset_expr
.X_op
== O_constant
)
6557 offset_expr
.X_add_number
-= 8;
6560 offset_expr
.X_add_number
= -4;
6561 offset_expr
.X_op
= O_constant
;
6565 macro_build_lui (&offset_expr
, AT
);
6567 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6568 /* Itbl support may require additional care here. */
6569 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6570 BFD_RELOC_LO16
, AT
);
6571 /* FIXME: How do we handle overflow here? */
6572 offset_expr
.X_add_number
+= 4;
6573 /* Itbl support may require additional care here. */
6574 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6575 BFD_RELOC_LO16
, AT
);
6576 if (mips_relax
.sequence
)
6579 else if (!mips_big_got
)
6581 /* If this is a reference to an external symbol, we want
6582 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6587 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6589 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6590 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6591 If there is a base register we add it to $at before the
6592 lwc1 instructions. If there is a constant we include it
6593 in the lwc1 instructions. */
6595 expr1
.X_add_number
= offset_expr
.X_add_number
;
6596 if (expr1
.X_add_number
< -0x8000
6597 || expr1
.X_add_number
>= 0x8000 - 4)
6598 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6599 load_got_offset (AT
, &offset_expr
);
6602 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6604 /* Set mips_optimize to 2 to avoid inserting an undesired
6606 hold_mips_optimize
= mips_optimize
;
6609 /* Itbl support may require additional care here. */
6610 relax_start (offset_expr
.X_add_symbol
);
6611 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6612 BFD_RELOC_LO16
, AT
);
6613 expr1
.X_add_number
+= 4;
6614 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6615 BFD_RELOC_LO16
, AT
);
6617 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6618 BFD_RELOC_LO16
, AT
);
6619 offset_expr
.X_add_number
+= 4;
6620 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6621 BFD_RELOC_LO16
, AT
);
6624 mips_optimize
= hold_mips_optimize
;
6626 else if (mips_big_got
)
6630 /* If this is a reference to an external symbol, we want
6631 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6633 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6638 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6640 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6641 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6642 If there is a base register we add it to $at before the
6643 lwc1 instructions. If there is a constant we include it
6644 in the lwc1 instructions. */
6646 expr1
.X_add_number
= offset_expr
.X_add_number
;
6647 offset_expr
.X_add_number
= 0;
6648 if (expr1
.X_add_number
< -0x8000
6649 || expr1
.X_add_number
>= 0x8000 - 4)
6650 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6651 gpdelay
= reg_needs_delay (mips_gp_register
);
6652 relax_start (offset_expr
.X_add_symbol
);
6653 macro_build (&offset_expr
, "lui", "t,u",
6654 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6655 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6656 AT
, AT
, mips_gp_register
);
6657 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6658 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6661 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6662 /* Itbl support may require additional care here. */
6663 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6664 BFD_RELOC_LO16
, AT
);
6665 expr1
.X_add_number
+= 4;
6667 /* Set mips_optimize to 2 to avoid inserting an undesired
6669 hold_mips_optimize
= mips_optimize
;
6671 /* Itbl support may require additional care here. */
6672 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6673 BFD_RELOC_LO16
, AT
);
6674 mips_optimize
= hold_mips_optimize
;
6675 expr1
.X_add_number
-= 4;
6678 offset_expr
.X_add_number
= expr1
.X_add_number
;
6680 macro_build (NULL
, "nop", "");
6681 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6682 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6685 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6686 /* Itbl support may require additional care here. */
6687 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6688 BFD_RELOC_LO16
, AT
);
6689 offset_expr
.X_add_number
+= 4;
6691 /* Set mips_optimize to 2 to avoid inserting an undesired
6693 hold_mips_optimize
= mips_optimize
;
6695 /* Itbl support may require additional care here. */
6696 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6697 BFD_RELOC_LO16
, AT
);
6698 mips_optimize
= hold_mips_optimize
;
6712 assert (HAVE_32BIT_ADDRESSES
);
6713 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6714 offset_expr
.X_add_number
+= 4;
6715 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6718 /* New code added to support COPZ instructions.
6719 This code builds table entries out of the macros in mip_opcodes.
6720 R4000 uses interlocks to handle coproc delays.
6721 Other chips (like the R3000) require nops to be inserted for delays.
6723 FIXME: Currently, we require that the user handle delays.
6724 In order to fill delay slots for non-interlocked chips,
6725 we must have a way to specify delays based on the coprocessor.
6726 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6727 What are the side-effects of the cop instruction?
6728 What cache support might we have and what are its effects?
6729 Both coprocessor & memory require delays. how long???
6730 What registers are read/set/modified?
6732 If an itbl is provided to interpret cop instructions,
6733 this knowledge can be encoded in the itbl spec. */
6747 /* For now we just do C (same as Cz). The parameter will be
6748 stored in insn_opcode by mips_ip. */
6749 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6753 move_register (dreg
, sreg
);
6756 #ifdef LOSING_COMPILER
6758 /* Try and see if this is a new itbl instruction.
6759 This code builds table entries out of the macros in mip_opcodes.
6760 FIXME: For now we just assemble the expression and pass it's
6761 value along as a 32-bit immediate.
6762 We may want to have the assembler assemble this value,
6763 so that we gain the assembler's knowledge of delay slots,
6765 Would it be more efficient to use mask (id) here? */
6766 if (itbl_have_entries
6767 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6769 s
= ip
->insn_mo
->name
;
6771 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6772 macro_build (&immed_expr
, s
, "C");
6778 if (mips_opts
.noat
&& used_at
)
6779 as_bad (_("Macro used $at after \".set noat\""));
6783 macro2 (struct mips_cl_insn
*ip
)
6785 register int treg
, sreg
, dreg
, breg
;
6800 bfd_reloc_code_real_type r
;
6802 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6803 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6804 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6805 mask
= ip
->insn_mo
->mask
;
6807 expr1
.X_op
= O_constant
;
6808 expr1
.X_op_symbol
= NULL
;
6809 expr1
.X_add_symbol
= NULL
;
6810 expr1
.X_add_number
= 1;
6814 #endif /* LOSING_COMPILER */
6819 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6820 macro_build (NULL
, "mflo", "d", dreg
);
6826 /* The MIPS assembler some times generates shifts and adds. I'm
6827 not trying to be that fancy. GCC should do this for us
6830 load_register (AT
, &imm_expr
, dbl
);
6831 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6832 macro_build (NULL
, "mflo", "d", dreg
);
6848 load_register (AT
, &imm_expr
, dbl
);
6849 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6850 macro_build (NULL
, "mflo", "d", dreg
);
6851 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6852 macro_build (NULL
, "mfhi", "d", AT
);
6854 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6857 expr1
.X_add_number
= 8;
6858 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6859 macro_build (NULL
, "nop", "", 0);
6860 macro_build (NULL
, "break", "c", 6);
6863 macro_build (NULL
, "mflo", "d", dreg
);
6879 load_register (AT
, &imm_expr
, dbl
);
6880 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6881 sreg
, imm
? AT
: treg
);
6882 macro_build (NULL
, "mfhi", "d", AT
);
6883 macro_build (NULL
, "mflo", "d", dreg
);
6885 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6888 expr1
.X_add_number
= 8;
6889 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6890 macro_build (NULL
, "nop", "", 0);
6891 macro_build (NULL
, "break", "c", 6);
6897 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6908 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6909 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6913 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6914 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6915 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6916 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6920 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6931 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6932 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6936 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6937 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6938 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6939 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6947 if (imm_expr
.X_op
!= O_constant
)
6948 as_bad (_("Improper rotate count"));
6949 rot
= imm_expr
.X_add_number
& 0x3f;
6950 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6952 rot
= (64 - rot
) & 0x3f;
6954 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6956 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6961 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6964 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6965 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6968 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6969 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6970 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6978 if (imm_expr
.X_op
!= O_constant
)
6979 as_bad (_("Improper rotate count"));
6980 rot
= imm_expr
.X_add_number
& 0x1f;
6981 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6983 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6988 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6992 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6993 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6994 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6999 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7001 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7005 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7006 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7007 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7008 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7012 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7014 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7018 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7019 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7020 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7021 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7029 if (imm_expr
.X_op
!= O_constant
)
7030 as_bad (_("Improper rotate count"));
7031 rot
= imm_expr
.X_add_number
& 0x3f;
7032 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7035 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7037 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7042 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7045 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7046 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7049 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7050 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7051 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7059 if (imm_expr
.X_op
!= O_constant
)
7060 as_bad (_("Improper rotate count"));
7061 rot
= imm_expr
.X_add_number
& 0x1f;
7062 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7064 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7069 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7073 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7074 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7075 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7080 if (mips_opts
.arch
== CPU_R4650
)
7082 as_bad (_("opcode not supported on this processor"));
7085 assert (mips_opts
.isa
== ISA_MIPS1
);
7086 /* Even on a big endian machine $fn comes before $fn+1. We have
7087 to adjust when storing to memory. */
7088 macro_build (&offset_expr
, "swc1", "T,o(b)",
7089 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7090 offset_expr
.X_add_number
+= 4;
7091 macro_build (&offset_expr
, "swc1", "T,o(b)",
7092 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7097 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7099 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7102 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7103 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7108 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7110 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7115 as_warn (_("Instruction %s: result is always false"),
7117 move_register (dreg
, 0);
7120 if (imm_expr
.X_op
== O_constant
7121 && imm_expr
.X_add_number
>= 0
7122 && imm_expr
.X_add_number
< 0x10000)
7124 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7126 else if (imm_expr
.X_op
== O_constant
7127 && imm_expr
.X_add_number
> -0x8000
7128 && imm_expr
.X_add_number
< 0)
7130 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7131 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7132 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7136 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7137 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7140 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7143 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7149 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7150 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7153 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7155 if (imm_expr
.X_op
== O_constant
7156 && imm_expr
.X_add_number
>= -0x8000
7157 && imm_expr
.X_add_number
< 0x8000)
7159 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7160 dreg
, sreg
, BFD_RELOC_LO16
);
7164 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7165 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7169 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7172 case M_SGT
: /* sreg > treg <==> treg < sreg */
7178 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7181 case M_SGT_I
: /* sreg > I <==> I < sreg */
7188 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7189 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7192 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7198 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7199 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7202 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7209 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7210 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7211 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7215 if (imm_expr
.X_op
== O_constant
7216 && imm_expr
.X_add_number
>= -0x8000
7217 && imm_expr
.X_add_number
< 0x8000)
7219 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7223 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7224 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7228 if (imm_expr
.X_op
== O_constant
7229 && imm_expr
.X_add_number
>= -0x8000
7230 && imm_expr
.X_add_number
< 0x8000)
7232 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7237 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7238 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7243 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7245 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7248 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7249 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7254 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7256 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7261 as_warn (_("Instruction %s: result is always true"),
7263 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7264 dreg
, 0, BFD_RELOC_LO16
);
7267 if (imm_expr
.X_op
== O_constant
7268 && imm_expr
.X_add_number
>= 0
7269 && imm_expr
.X_add_number
< 0x10000)
7271 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7273 else if (imm_expr
.X_op
== O_constant
7274 && imm_expr
.X_add_number
> -0x8000
7275 && imm_expr
.X_add_number
< 0)
7277 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7278 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7279 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7283 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7284 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7287 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7293 if (imm_expr
.X_op
== O_constant
7294 && imm_expr
.X_add_number
> -0x8000
7295 && imm_expr
.X_add_number
<= 0x8000)
7297 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7298 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7299 dreg
, sreg
, BFD_RELOC_LO16
);
7303 load_register (AT
, &imm_expr
, dbl
);
7304 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7310 if (imm_expr
.X_op
== O_constant
7311 && imm_expr
.X_add_number
> -0x8000
7312 && imm_expr
.X_add_number
<= 0x8000)
7314 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7315 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7316 dreg
, sreg
, BFD_RELOC_LO16
);
7320 load_register (AT
, &imm_expr
, dbl
);
7321 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7343 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7344 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7349 assert (mips_opts
.isa
== ISA_MIPS1
);
7351 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7352 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7355 * Is the double cfc1 instruction a bug in the mips assembler;
7356 * or is there a reason for it?
7359 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7360 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7361 macro_build (NULL
, "nop", "");
7362 expr1
.X_add_number
= 3;
7363 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7364 expr1
.X_add_number
= 2;
7365 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7366 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7367 macro_build (NULL
, "nop", "");
7368 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7370 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7371 macro_build (NULL
, "nop", "");
7382 if (offset_expr
.X_add_number
>= 0x7fff)
7383 as_bad (_("operand overflow"));
7384 if (! target_big_endian
)
7385 ++offset_expr
.X_add_number
;
7386 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7387 if (! target_big_endian
)
7388 --offset_expr
.X_add_number
;
7390 ++offset_expr
.X_add_number
;
7391 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7392 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7393 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7406 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7407 as_bad (_("operand overflow"));
7415 if (! target_big_endian
)
7416 offset_expr
.X_add_number
+= off
;
7417 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7418 if (! target_big_endian
)
7419 offset_expr
.X_add_number
-= off
;
7421 offset_expr
.X_add_number
+= off
;
7422 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7424 /* If necessary, move the result in tempreg the final destination. */
7425 if (treg
== tempreg
)
7427 /* Protect second load's delay slot. */
7429 move_register (treg
, tempreg
);
7443 load_address (AT
, &offset_expr
, &used_at
);
7445 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7446 if (! target_big_endian
)
7447 expr1
.X_add_number
= off
;
7449 expr1
.X_add_number
= 0;
7450 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7451 if (! target_big_endian
)
7452 expr1
.X_add_number
= 0;
7454 expr1
.X_add_number
= off
;
7455 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7461 load_address (AT
, &offset_expr
, &used_at
);
7463 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7464 if (target_big_endian
)
7465 expr1
.X_add_number
= 0;
7466 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7467 treg
, BFD_RELOC_LO16
, AT
);
7468 if (target_big_endian
)
7469 expr1
.X_add_number
= 1;
7471 expr1
.X_add_number
= 0;
7472 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7473 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7474 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7479 if (offset_expr
.X_add_number
>= 0x7fff)
7480 as_bad (_("operand overflow"));
7481 if (target_big_endian
)
7482 ++offset_expr
.X_add_number
;
7483 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7484 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7485 if (target_big_endian
)
7486 --offset_expr
.X_add_number
;
7488 ++offset_expr
.X_add_number
;
7489 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7502 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7503 as_bad (_("operand overflow"));
7504 if (! target_big_endian
)
7505 offset_expr
.X_add_number
+= off
;
7506 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7507 if (! target_big_endian
)
7508 offset_expr
.X_add_number
-= off
;
7510 offset_expr
.X_add_number
+= off
;
7511 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7525 load_address (AT
, &offset_expr
, &used_at
);
7527 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7528 if (! target_big_endian
)
7529 expr1
.X_add_number
= off
;
7531 expr1
.X_add_number
= 0;
7532 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7533 if (! target_big_endian
)
7534 expr1
.X_add_number
= 0;
7536 expr1
.X_add_number
= off
;
7537 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7542 load_address (AT
, &offset_expr
, &used_at
);
7544 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7545 if (! target_big_endian
)
7546 expr1
.X_add_number
= 0;
7547 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7548 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7549 if (! target_big_endian
)
7550 expr1
.X_add_number
= 1;
7552 expr1
.X_add_number
= 0;
7553 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7554 if (! target_big_endian
)
7555 expr1
.X_add_number
= 0;
7557 expr1
.X_add_number
= 1;
7558 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7559 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7560 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7564 /* FIXME: Check if this is one of the itbl macros, since they
7565 are added dynamically. */
7566 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7569 if (mips_opts
.noat
&& used_at
)
7570 as_bad (_("Macro used $at after \".set noat\""));
7573 /* Implement macros in mips16 mode. */
7576 mips16_macro (struct mips_cl_insn
*ip
)
7579 int xreg
, yreg
, zreg
, tmp
;
7582 const char *s
, *s2
, *s3
;
7584 mask
= ip
->insn_mo
->mask
;
7586 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7587 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7588 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7590 expr1
.X_op
= O_constant
;
7591 expr1
.X_op_symbol
= NULL
;
7592 expr1
.X_add_symbol
= NULL
;
7593 expr1
.X_add_number
= 1;
7613 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7614 expr1
.X_add_number
= 2;
7615 macro_build (&expr1
, "bnez", "x,p", yreg
);
7616 macro_build (NULL
, "break", "6", 7);
7618 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7619 since that causes an overflow. We should do that as well,
7620 but I don't see how to do the comparisons without a temporary
7623 macro_build (NULL
, s
, "x", zreg
);
7643 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7644 expr1
.X_add_number
= 2;
7645 macro_build (&expr1
, "bnez", "x,p", yreg
);
7646 macro_build (NULL
, "break", "6", 7);
7648 macro_build (NULL
, s2
, "x", zreg
);
7654 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7655 macro_build (NULL
, "mflo", "x", zreg
);
7663 if (imm_expr
.X_op
!= O_constant
)
7664 as_bad (_("Unsupported large constant"));
7665 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7666 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7670 if (imm_expr
.X_op
!= O_constant
)
7671 as_bad (_("Unsupported large constant"));
7672 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7673 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7677 if (imm_expr
.X_op
!= O_constant
)
7678 as_bad (_("Unsupported large constant"));
7679 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7680 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7702 goto do_reverse_branch
;
7706 goto do_reverse_branch
;
7718 goto do_reverse_branch
;
7729 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7730 macro_build (&offset_expr
, s2
, "p");
7757 goto do_addone_branch_i
;
7762 goto do_addone_branch_i
;
7777 goto do_addone_branch_i
;
7784 if (imm_expr
.X_op
!= O_constant
)
7785 as_bad (_("Unsupported large constant"));
7786 ++imm_expr
.X_add_number
;
7789 macro_build (&imm_expr
, s
, s3
, xreg
);
7790 macro_build (&offset_expr
, s2
, "p");
7794 expr1
.X_add_number
= 0;
7795 macro_build (&expr1
, "slti", "x,8", yreg
);
7797 move_register (xreg
, yreg
);
7798 expr1
.X_add_number
= 2;
7799 macro_build (&expr1
, "bteqz", "p");
7800 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7804 /* For consistency checking, verify that all bits are specified either
7805 by the match/mask part of the instruction definition, or by the
7808 validate_mips_insn (const struct mips_opcode
*opc
)
7810 const char *p
= opc
->args
;
7812 unsigned long used_bits
= opc
->mask
;
7814 if ((used_bits
& opc
->match
) != opc
->match
)
7816 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7817 opc
->name
, opc
->args
);
7820 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7830 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
7831 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
7832 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
7833 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
7834 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7835 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7836 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7837 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7838 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7839 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7840 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7841 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7842 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7844 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7845 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
7846 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7848 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7849 c
, opc
->name
, opc
->args
);
7853 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7854 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7856 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7857 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7858 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7859 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7861 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7862 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7864 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7865 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7867 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7868 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7869 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7870 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7871 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7872 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7873 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7874 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7875 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7876 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7877 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7878 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7879 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7880 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7881 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7882 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7883 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7885 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7886 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7887 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7888 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7890 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7891 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7892 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7893 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7894 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7895 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7896 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7897 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7898 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7901 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7902 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7903 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7904 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7905 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7908 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
7909 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
7910 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
7911 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7912 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
7913 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
7914 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
7915 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
7916 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
7917 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
7918 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
7919 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
7920 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
7921 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
7922 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
7923 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7925 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7926 c
, opc
->name
, opc
->args
);
7930 if (used_bits
!= 0xffffffff)
7932 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7933 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7939 /* UDI immediates. */
7947 static const struct mips_immed mips_immed
[] = {
7948 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
7949 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
7950 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
7951 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
7955 /* This routine assembles an instruction into its binary format. As a
7956 side effect, it sets one of the global variables imm_reloc or
7957 offset_reloc to the type of relocation to do if one of the operands
7958 is an address expression. */
7961 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7966 struct mips_opcode
*insn
;
7969 unsigned int lastregno
= 0;
7970 unsigned int lastpos
= 0;
7971 unsigned int limlo
, limhi
;
7974 offsetT min_range
, max_range
;
7978 /* If the instruction contains a '.', we first try to match an instruction
7979 including the '.'. Then we try again without the '.'. */
7981 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7984 /* If we stopped on whitespace, then replace the whitespace with null for
7985 the call to hash_find. Save the character we replaced just in case we
7986 have to re-parse the instruction. */
7993 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7995 /* If we didn't find the instruction in the opcode table, try again, but
7996 this time with just the instruction up to, but not including the
8000 /* Restore the character we overwrite above (if any). */
8004 /* Scan up to the first '.' or whitespace. */
8006 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8010 /* If we did not find a '.', then we can quit now. */
8013 insn_error
= "unrecognized opcode";
8017 /* Lookup the instruction in the hash table. */
8019 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8021 insn_error
= "unrecognized opcode";
8031 assert (strcmp (insn
->name
, str
) == 0);
8033 if (OPCODE_IS_MEMBER (insn
,
8035 /* We don't check for mips_opts.mips16 here since
8036 we want to allow jalx if -mips16 was specified
8037 on the command line. */
8038 | (file_ase_mips16
? INSN_MIPS16
: 0)
8039 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8040 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
8041 | (mips_opts
.ase_mt
? INSN_MT
: 0)
8042 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)
8043 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
8049 if (insn
->pinfo
!= INSN_MACRO
)
8051 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8057 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8058 && strcmp (insn
->name
, insn
[1].name
) == 0)
8067 static char buf
[100];
8069 _("opcode not supported on this processor: %s (%s)"),
8070 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8071 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8080 create_insn (ip
, insn
);
8082 for (args
= insn
->args
;; ++args
)
8086 s
+= strspn (s
, " \t");
8090 case '\0': /* end of args */
8095 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8096 my_getExpression (&imm_expr
, s
);
8097 check_absolute_expr (ip
, &imm_expr
);
8098 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8100 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8101 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8102 imm_expr
.X_add_number
&= OP_MASK_SA3
;
8104 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA3
;
8105 imm_expr
.X_op
= O_absent
;
8109 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8110 my_getExpression (&imm_expr
, s
);
8111 check_absolute_expr (ip
, &imm_expr
);
8112 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8114 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8115 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8116 imm_expr
.X_add_number
&= OP_MASK_SA4
;
8118 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA4
;
8119 imm_expr
.X_op
= O_absent
;
8123 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8124 my_getExpression (&imm_expr
, s
);
8125 check_absolute_expr (ip
, &imm_expr
);
8126 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8128 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8129 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8130 imm_expr
.X_add_number
&= OP_MASK_IMM8
;
8132 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_IMM8
;
8133 imm_expr
.X_op
= O_absent
;
8137 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8138 my_getExpression (&imm_expr
, s
);
8139 check_absolute_expr (ip
, &imm_expr
);
8140 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8142 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8143 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8144 imm_expr
.X_add_number
&= OP_MASK_RS
;
8146 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RS
;
8147 imm_expr
.X_op
= O_absent
;
8151 case '7': /* four dsp accumulators in bits 11,12 */
8152 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8153 s
[3] >= '0' && s
[3] <= '3')
8157 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC
;
8161 as_bad (_("Invalid dsp acc register"));
8164 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8165 my_getExpression (&imm_expr
, s
);
8166 check_absolute_expr (ip
, &imm_expr
);
8167 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8169 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8171 (unsigned long) imm_expr
.X_add_number
);
8172 imm_expr
.X_add_number
&= OP_MASK_WRDSP
;
8174 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_WRDSP
;
8175 imm_expr
.X_op
= O_absent
;
8179 case '9': /* four dsp accumulators in bits 21,22 */
8180 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8181 s
[3] >= '0' && s
[3] <= '3')
8185 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC_S
;
8189 as_bad (_("Invalid dsp acc register"));
8192 case '0': /* dsp 6-bit signed immediate in bit 20 */
8193 my_getExpression (&imm_expr
, s
);
8194 check_absolute_expr (ip
, &imm_expr
);
8195 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8196 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8197 if (imm_expr
.X_add_number
< min_range
||
8198 imm_expr
.X_add_number
> max_range
)
8200 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8201 (long) min_range
, (long) max_range
,
8202 (long) imm_expr
.X_add_number
);
8204 imm_expr
.X_add_number
&= OP_MASK_DSPSFT
;
8205 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8207 imm_expr
.X_op
= O_absent
;
8211 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8212 my_getExpression (&imm_expr
, s
);
8213 check_absolute_expr (ip
, &imm_expr
);
8214 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8216 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8218 (unsigned long) imm_expr
.X_add_number
);
8219 imm_expr
.X_add_number
&= OP_MASK_RDDSP
;
8221 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RDDSP
;
8222 imm_expr
.X_op
= O_absent
;
8226 case ':': /* dsp 7-bit signed immediate in bit 19 */
8227 my_getExpression (&imm_expr
, s
);
8228 check_absolute_expr (ip
, &imm_expr
);
8229 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8230 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8231 if (imm_expr
.X_add_number
< min_range
||
8232 imm_expr
.X_add_number
> max_range
)
8234 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8235 (long) min_range
, (long) max_range
,
8236 (long) imm_expr
.X_add_number
);
8238 imm_expr
.X_add_number
&= OP_MASK_DSPSFT_7
;
8239 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8241 imm_expr
.X_op
= O_absent
;
8245 case '@': /* dsp 10-bit signed immediate in bit 16 */
8246 my_getExpression (&imm_expr
, s
);
8247 check_absolute_expr (ip
, &imm_expr
);
8248 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8249 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8250 if (imm_expr
.X_add_number
< min_range
||
8251 imm_expr
.X_add_number
> max_range
)
8253 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8254 (long) min_range
, (long) max_range
,
8255 (long) imm_expr
.X_add_number
);
8257 imm_expr
.X_add_number
&= OP_MASK_IMM10
;
8258 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8260 imm_expr
.X_op
= O_absent
;
8264 case '!': /* mt 1-bit unsigned immediate in bit 5 */
8265 my_getExpression (&imm_expr
, s
);
8266 check_absolute_expr (ip
, &imm_expr
);
8267 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8269 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8270 OP_MASK_MT_U
, (unsigned long) imm_expr
.X_add_number
);
8271 imm_expr
.X_add_number
&= OP_MASK_MT_U
;
8273 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_MT_U
;
8274 imm_expr
.X_op
= O_absent
;
8278 case '$': /* mt 1-bit unsigned immediate in bit 4 */
8279 my_getExpression (&imm_expr
, s
);
8280 check_absolute_expr (ip
, &imm_expr
);
8281 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8283 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8284 OP_MASK_MT_H
, (unsigned long) imm_expr
.X_add_number
);
8285 imm_expr
.X_add_number
&= OP_MASK_MT_H
;
8287 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_MT_H
;
8288 imm_expr
.X_op
= O_absent
;
8292 case '*': /* four dsp accumulators in bits 18,19 */
8293 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8294 s
[3] >= '0' && s
[3] <= '3')
8298 ip
->insn_opcode
|= regno
<< OP_SH_MTACC_T
;
8302 as_bad (_("Invalid dsp/smartmips acc register"));
8305 case '&': /* four dsp accumulators in bits 13,14 */
8306 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8307 s
[3] >= '0' && s
[3] <= '3')
8311 ip
->insn_opcode
|= regno
<< OP_SH_MTACC_D
;
8315 as_bad (_("Invalid dsp/smartmips acc register"));
8326 INSERT_OPERAND (RS
, *ip
, lastregno
);
8330 INSERT_OPERAND (RT
, *ip
, lastregno
);
8334 INSERT_OPERAND (FT
, *ip
, lastregno
);
8338 INSERT_OPERAND (FS
, *ip
, lastregno
);
8344 /* Handle optional base register.
8345 Either the base register is omitted or
8346 we must have a left paren. */
8347 /* This is dependent on the next operand specifier
8348 is a base register specification. */
8349 assert (args
[1] == 'b' || args
[1] == '5'
8350 || args
[1] == '-' || args
[1] == '4');
8354 case ')': /* these must match exactly */
8361 case '+': /* Opcode extension character. */
8364 case '1': /* UDI immediates. */
8369 const struct mips_immed
*imm
= mips_immed
;
8371 while (imm
->type
&& imm
->type
!= *args
)
8375 my_getExpression (&imm_expr
, s
);
8376 check_absolute_expr (ip
, &imm_expr
);
8377 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8379 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8380 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8381 (unsigned long) imm_expr
.X_add_number
,
8382 (unsigned long) imm_expr
.X_add_number
);
8383 imm_expr
.X_add_number
&= imm
->mask
;
8385 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8387 imm_expr
.X_op
= O_absent
;
8392 case 'A': /* ins/ext position, becomes LSB. */
8401 my_getExpression (&imm_expr
, s
);
8402 check_absolute_expr (ip
, &imm_expr
);
8403 if ((unsigned long) imm_expr
.X_add_number
< limlo
8404 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8406 as_bad (_("Improper position (%lu)"),
8407 (unsigned long) imm_expr
.X_add_number
);
8408 imm_expr
.X_add_number
= limlo
;
8410 lastpos
= imm_expr
.X_add_number
;
8411 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8412 imm_expr
.X_op
= O_absent
;
8416 case 'B': /* ins size, becomes MSB. */
8425 my_getExpression (&imm_expr
, s
);
8426 check_absolute_expr (ip
, &imm_expr
);
8427 /* Check for negative input so that small negative numbers
8428 will not succeed incorrectly. The checks against
8429 (pos+size) transitively check "size" itself,
8430 assuming that "pos" is reasonable. */
8431 if ((long) imm_expr
.X_add_number
< 0
8432 || ((unsigned long) imm_expr
.X_add_number
8434 || ((unsigned long) imm_expr
.X_add_number
8437 as_bad (_("Improper insert size (%lu, position %lu)"),
8438 (unsigned long) imm_expr
.X_add_number
,
8439 (unsigned long) lastpos
);
8440 imm_expr
.X_add_number
= limlo
- lastpos
;
8442 INSERT_OPERAND (INSMSB
, *ip
,
8443 lastpos
+ imm_expr
.X_add_number
- 1);
8444 imm_expr
.X_op
= O_absent
;
8448 case 'C': /* ext size, becomes MSBD. */
8461 my_getExpression (&imm_expr
, s
);
8462 check_absolute_expr (ip
, &imm_expr
);
8463 /* Check for negative input so that small negative numbers
8464 will not succeed incorrectly. The checks against
8465 (pos+size) transitively check "size" itself,
8466 assuming that "pos" is reasonable. */
8467 if ((long) imm_expr
.X_add_number
< 0
8468 || ((unsigned long) imm_expr
.X_add_number
8470 || ((unsigned long) imm_expr
.X_add_number
8473 as_bad (_("Improper extract size (%lu, position %lu)"),
8474 (unsigned long) imm_expr
.X_add_number
,
8475 (unsigned long) lastpos
);
8476 imm_expr
.X_add_number
= limlo
- lastpos
;
8478 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8479 imm_expr
.X_op
= O_absent
;
8484 /* +D is for disassembly only; never match. */
8488 /* "+I" is like "I", except that imm2_expr is used. */
8489 my_getExpression (&imm2_expr
, s
);
8490 if (imm2_expr
.X_op
!= O_big
8491 && imm2_expr
.X_op
!= O_constant
)
8492 insn_error
= _("absolute expression required");
8493 if (HAVE_32BIT_GPRS
)
8494 normalize_constant_expr (&imm2_expr
);
8498 case 'T': /* Coprocessor register */
8499 /* +T is for disassembly only; never match. */
8502 case 't': /* Coprocessor register number */
8503 if (s
[0] == '$' && ISDIGIT (s
[1]))
8513 while (ISDIGIT (*s
));
8515 as_bad (_("Invalid register number (%d)"), regno
);
8518 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8523 as_bad (_("Invalid coprocessor 0 register number"));
8527 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8528 *args
, insn
->name
, insn
->args
);
8529 /* Further processing is fruitless. */
8534 case '<': /* must be at least one digit */
8536 * According to the manual, if the shift amount is greater
8537 * than 31 or less than 0, then the shift amount should be
8538 * mod 32. In reality the mips assembler issues an error.
8539 * We issue a warning and mask out all but the low 5 bits.
8541 my_getExpression (&imm_expr
, s
);
8542 check_absolute_expr (ip
, &imm_expr
);
8543 if ((unsigned long) imm_expr
.X_add_number
> 31)
8544 as_warn (_("Improper shift amount (%lu)"),
8545 (unsigned long) imm_expr
.X_add_number
);
8546 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8547 imm_expr
.X_op
= O_absent
;
8551 case '>': /* shift amount minus 32 */
8552 my_getExpression (&imm_expr
, s
);
8553 check_absolute_expr (ip
, &imm_expr
);
8554 if ((unsigned long) imm_expr
.X_add_number
< 32
8555 || (unsigned long) imm_expr
.X_add_number
> 63)
8557 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8558 imm_expr
.X_op
= O_absent
;
8562 case 'k': /* cache code */
8563 case 'h': /* prefx code */
8564 my_getExpression (&imm_expr
, s
);
8565 check_absolute_expr (ip
, &imm_expr
);
8566 if ((unsigned long) imm_expr
.X_add_number
> 31)
8567 as_warn (_("Invalid value for `%s' (%lu)"),
8569 (unsigned long) imm_expr
.X_add_number
);
8571 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8573 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8574 imm_expr
.X_op
= O_absent
;
8578 case 'c': /* break code */
8579 my_getExpression (&imm_expr
, s
);
8580 check_absolute_expr (ip
, &imm_expr
);
8581 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8582 as_warn (_("Illegal break code (%lu)"),
8583 (unsigned long) imm_expr
.X_add_number
);
8584 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8585 imm_expr
.X_op
= O_absent
;
8589 case 'q': /* lower break code */
8590 my_getExpression (&imm_expr
, s
);
8591 check_absolute_expr (ip
, &imm_expr
);
8592 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8593 as_warn (_("Illegal lower break code (%lu)"),
8594 (unsigned long) imm_expr
.X_add_number
);
8595 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8596 imm_expr
.X_op
= O_absent
;
8600 case 'B': /* 20-bit syscall/break code. */
8601 my_getExpression (&imm_expr
, s
);
8602 check_absolute_expr (ip
, &imm_expr
);
8603 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8604 as_warn (_("Illegal 20-bit code (%lu)"),
8605 (unsigned long) imm_expr
.X_add_number
);
8606 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8607 imm_expr
.X_op
= O_absent
;
8611 case 'C': /* Coprocessor code */
8612 my_getExpression (&imm_expr
, s
);
8613 check_absolute_expr (ip
, &imm_expr
);
8614 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8616 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8617 (unsigned long) imm_expr
.X_add_number
);
8618 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8620 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8621 imm_expr
.X_op
= O_absent
;
8625 case 'J': /* 19-bit wait code. */
8626 my_getExpression (&imm_expr
, s
);
8627 check_absolute_expr (ip
, &imm_expr
);
8628 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8629 as_warn (_("Illegal 19-bit code (%lu)"),
8630 (unsigned long) imm_expr
.X_add_number
);
8631 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8632 imm_expr
.X_op
= O_absent
;
8636 case 'P': /* Performance register */
8637 my_getExpression (&imm_expr
, s
);
8638 check_absolute_expr (ip
, &imm_expr
);
8639 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8640 as_warn (_("Invalid performance register (%lu)"),
8641 (unsigned long) imm_expr
.X_add_number
);
8642 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8643 imm_expr
.X_op
= O_absent
;
8647 case 'b': /* base register */
8648 case 'd': /* destination register */
8649 case 's': /* source register */
8650 case 't': /* target register */
8651 case 'r': /* both target and source */
8652 case 'v': /* both dest and source */
8653 case 'w': /* both dest and target */
8654 case 'E': /* coprocessor target register */
8655 case 'G': /* coprocessor destination register */
8656 case 'K': /* 'rdhwr' destination register */
8657 case 'x': /* ignore register name */
8658 case 'z': /* must be zero register */
8659 case 'U': /* destination register (clo/clz). */
8660 case 'g': /* coprocessor destination register */
8674 while (ISDIGIT (*s
));
8676 as_bad (_("Invalid register number (%d)"), regno
);
8678 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8682 if (s
[1] == 'r' && s
[2] == 'a')
8687 else if (s
[1] == 'f' && s
[2] == 'p')
8692 else if (s
[1] == 's' && s
[2] == 'p')
8697 else if (s
[1] == 'g' && s
[2] == 'p')
8702 else if (s
[1] == 'a' && s
[2] == 't')
8707 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8712 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8717 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8722 else if (itbl_have_entries
)
8727 p
= s
+ 1; /* advance past '$' */
8728 n
= itbl_get_field (&p
); /* n is name */
8730 /* See if this is a register defined in an
8732 if (itbl_get_reg_val (n
, &r
))
8734 /* Get_field advances to the start of
8735 the next field, so we need to back
8736 rack to the end of the last field. */
8740 s
= strchr (s
, '\0');
8754 as_warn (_("Used $at without \".set noat\""));
8760 if (c
== 'r' || c
== 'v' || c
== 'w')
8767 /* 'z' only matches $0. */
8768 if (c
== 'z' && regno
!= 0)
8771 /* Now that we have assembled one operand, we use the args string
8772 * to figure out where it goes in the instruction. */
8779 INSERT_OPERAND (RS
, *ip
, regno
);
8785 INSERT_OPERAND (RD
, *ip
, regno
);
8788 INSERT_OPERAND (RD
, *ip
, regno
);
8789 INSERT_OPERAND (RT
, *ip
, regno
);
8794 INSERT_OPERAND (RT
, *ip
, regno
);
8797 /* This case exists because on the r3000 trunc
8798 expands into a macro which requires a gp
8799 register. On the r6000 or r4000 it is
8800 assembled into a single instruction which
8801 ignores the register. Thus the insn version
8802 is MIPS_ISA2 and uses 'x', and the macro
8803 version is MIPS_ISA1 and uses 't'. */
8806 /* This case is for the div instruction, which
8807 acts differently if the destination argument
8808 is $0. This only matches $0, and is checked
8809 outside the switch. */
8812 /* Itbl operand; not yet implemented. FIXME ?? */
8814 /* What about all other operands like 'i', which
8815 can be specified in the opcode table? */
8825 INSERT_OPERAND (RS
, *ip
, lastregno
);
8828 INSERT_OPERAND (RT
, *ip
, lastregno
);
8833 case 'O': /* MDMX alignment immediate constant. */
8834 my_getExpression (&imm_expr
, s
);
8835 check_absolute_expr (ip
, &imm_expr
);
8836 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8837 as_warn ("Improper align amount (%ld), using low bits",
8838 (long) imm_expr
.X_add_number
);
8839 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8840 imm_expr
.X_op
= O_absent
;
8844 case 'Q': /* MDMX vector, element sel, or const. */
8847 /* MDMX Immediate. */
8848 my_getExpression (&imm_expr
, s
);
8849 check_absolute_expr (ip
, &imm_expr
);
8850 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8851 as_warn (_("Invalid MDMX Immediate (%ld)"),
8852 (long) imm_expr
.X_add_number
);
8853 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8854 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8855 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8857 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8858 imm_expr
.X_op
= O_absent
;
8862 /* Not MDMX Immediate. Fall through. */
8863 case 'X': /* MDMX destination register. */
8864 case 'Y': /* MDMX source register. */
8865 case 'Z': /* MDMX target register. */
8867 case 'D': /* floating point destination register */
8868 case 'S': /* floating point source register */
8869 case 'T': /* floating point target register */
8870 case 'R': /* floating point source register */
8874 /* Accept $fN for FP and MDMX register numbers, and in
8875 addition accept $vN for MDMX register numbers. */
8876 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8877 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8888 while (ISDIGIT (*s
));
8891 as_bad (_("Invalid float register number (%d)"), regno
);
8893 if ((regno
& 1) != 0
8895 && ! (strcmp (str
, "mtc1") == 0
8896 || strcmp (str
, "mfc1") == 0
8897 || strcmp (str
, "lwc1") == 0
8898 || strcmp (str
, "swc1") == 0
8899 || strcmp (str
, "l.s") == 0
8900 || strcmp (str
, "s.s") == 0
8901 || strcmp (str
, "mftc1") == 0
8902 || strcmp (str
, "mfthc1") == 0
8903 || strcmp (str
, "cftc1") == 0
8904 || strcmp (str
, "mttc1") == 0
8905 || strcmp (str
, "mtthc1") == 0
8906 || strcmp (str
, "cttc1") == 0))
8907 as_warn (_("Float register should be even, was %d"),
8915 if (c
== 'V' || c
== 'W')
8926 INSERT_OPERAND (FD
, *ip
, regno
);
8931 INSERT_OPERAND (FS
, *ip
, regno
);
8934 /* This is like 'Z', but also needs to fix the MDMX
8935 vector/scalar select bits. Note that the
8936 scalar immediate case is handled above. */
8939 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8940 int max_el
= (is_qh
? 3 : 7);
8942 my_getExpression(&imm_expr
, s
);
8943 check_absolute_expr (ip
, &imm_expr
);
8945 if (imm_expr
.X_add_number
> max_el
)
8946 as_bad(_("Bad element selector %ld"),
8947 (long) imm_expr
.X_add_number
);
8948 imm_expr
.X_add_number
&= max_el
;
8949 ip
->insn_opcode
|= (imm_expr
.X_add_number
8952 imm_expr
.X_op
= O_absent
;
8954 as_warn(_("Expecting ']' found '%s'"), s
);
8960 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8961 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8964 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8971 INSERT_OPERAND (FT
, *ip
, regno
);
8974 INSERT_OPERAND (FR
, *ip
, regno
);
8984 INSERT_OPERAND (FS
, *ip
, lastregno
);
8987 INSERT_OPERAND (FT
, *ip
, lastregno
);
8993 my_getExpression (&imm_expr
, s
);
8994 if (imm_expr
.X_op
!= O_big
8995 && imm_expr
.X_op
!= O_constant
)
8996 insn_error
= _("absolute expression required");
8997 if (HAVE_32BIT_GPRS
)
8998 normalize_constant_expr (&imm_expr
);
9003 my_getExpression (&offset_expr
, s
);
9004 normalize_address_expr (&offset_expr
);
9005 *imm_reloc
= BFD_RELOC_32
;
9018 unsigned char temp
[8];
9020 unsigned int length
;
9025 /* These only appear as the last operand in an
9026 instruction, and every instruction that accepts
9027 them in any variant accepts them in all variants.
9028 This means we don't have to worry about backing out
9029 any changes if the instruction does not match.
9031 The difference between them is the size of the
9032 floating point constant and where it goes. For 'F'
9033 and 'L' the constant is 64 bits; for 'f' and 'l' it
9034 is 32 bits. Where the constant is placed is based
9035 on how the MIPS assembler does things:
9038 f -- immediate value
9041 The .lit4 and .lit8 sections are only used if
9042 permitted by the -G argument.
9044 The code below needs to know whether the target register
9045 is 32 or 64 bits wide. It relies on the fact 'f' and
9046 'F' are used with GPR-based instructions and 'l' and
9047 'L' are used with FPR-based instructions. */
9049 f64
= *args
== 'F' || *args
== 'L';
9050 using_gprs
= *args
== 'F' || *args
== 'f';
9052 save_in
= input_line_pointer
;
9053 input_line_pointer
= s
;
9054 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9056 s
= input_line_pointer
;
9057 input_line_pointer
= save_in
;
9058 if (err
!= NULL
&& *err
!= '\0')
9060 as_bad (_("Bad floating point constant: %s"), err
);
9061 memset (temp
, '\0', sizeof temp
);
9062 length
= f64
? 8 : 4;
9065 assert (length
== (unsigned) (f64
? 8 : 4));
9069 && (g_switch_value
< 4
9070 || (temp
[0] == 0 && temp
[1] == 0)
9071 || (temp
[2] == 0 && temp
[3] == 0))))
9073 imm_expr
.X_op
= O_constant
;
9074 if (! target_big_endian
)
9075 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9077 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9080 && ! mips_disable_float_construction
9081 /* Constants can only be constructed in GPRs and
9082 copied to FPRs if the GPRs are at least as wide
9083 as the FPRs. Force the constant into memory if
9084 we are using 64-bit FPRs but the GPRs are only
9087 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9088 && ((temp
[0] == 0 && temp
[1] == 0)
9089 || (temp
[2] == 0 && temp
[3] == 0))
9090 && ((temp
[4] == 0 && temp
[5] == 0)
9091 || (temp
[6] == 0 && temp
[7] == 0)))
9093 /* The value is simple enough to load with a couple of
9094 instructions. If using 32-bit registers, set
9095 imm_expr to the high order 32 bits and offset_expr to
9096 the low order 32 bits. Otherwise, set imm_expr to
9097 the entire 64 bit constant. */
9098 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9100 imm_expr
.X_op
= O_constant
;
9101 offset_expr
.X_op
= O_constant
;
9102 if (! target_big_endian
)
9104 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9105 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9109 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9110 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9112 if (offset_expr
.X_add_number
== 0)
9113 offset_expr
.X_op
= O_absent
;
9115 else if (sizeof (imm_expr
.X_add_number
) > 4)
9117 imm_expr
.X_op
= O_constant
;
9118 if (! target_big_endian
)
9119 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9121 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9125 imm_expr
.X_op
= O_big
;
9126 imm_expr
.X_add_number
= 4;
9127 if (! target_big_endian
)
9129 generic_bignum
[0] = bfd_getl16 (temp
);
9130 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9131 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9132 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9136 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9137 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9138 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9139 generic_bignum
[3] = bfd_getb16 (temp
);
9145 const char *newname
;
9148 /* Switch to the right section. */
9150 subseg
= now_subseg
;
9153 default: /* unused default case avoids warnings. */
9155 newname
= RDATA_SECTION_NAME
;
9156 if (g_switch_value
>= 8)
9160 newname
= RDATA_SECTION_NAME
;
9163 assert (g_switch_value
>= 4);
9167 new_seg
= subseg_new (newname
, (subsegT
) 0);
9168 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9169 bfd_set_section_flags (stdoutput
, new_seg
,
9174 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9175 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9176 && strcmp (TARGET_OS
, "elf") != 0)
9177 record_alignment (new_seg
, 4);
9179 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9181 as_bad (_("Can't use floating point insn in this section"));
9183 /* Set the argument to the current address in the
9185 offset_expr
.X_op
= O_symbol
;
9186 offset_expr
.X_add_symbol
=
9187 symbol_new ("L0\001", now_seg
,
9188 (valueT
) frag_now_fix (), frag_now
);
9189 offset_expr
.X_add_number
= 0;
9191 /* Put the floating point number into the section. */
9192 p
= frag_more ((int) length
);
9193 memcpy (p
, temp
, length
);
9195 /* Switch back to the original section. */
9196 subseg_set (seg
, subseg
);
9201 case 'i': /* 16 bit unsigned immediate */
9202 case 'j': /* 16 bit signed immediate */
9203 *imm_reloc
= BFD_RELOC_LO16
;
9204 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9207 offsetT minval
, maxval
;
9209 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9210 && strcmp (insn
->name
, insn
[1].name
) == 0);
9212 /* If the expression was written as an unsigned number,
9213 only treat it as signed if there are no more
9217 && sizeof (imm_expr
.X_add_number
) <= 4
9218 && imm_expr
.X_op
== O_constant
9219 && imm_expr
.X_add_number
< 0
9220 && imm_expr
.X_unsigned
9224 /* For compatibility with older assemblers, we accept
9225 0x8000-0xffff as signed 16-bit numbers when only
9226 signed numbers are allowed. */
9228 minval
= 0, maxval
= 0xffff;
9230 minval
= -0x8000, maxval
= 0x7fff;
9232 minval
= -0x8000, maxval
= 0xffff;
9234 if (imm_expr
.X_op
!= O_constant
9235 || imm_expr
.X_add_number
< minval
9236 || imm_expr
.X_add_number
> maxval
)
9240 if (imm_expr
.X_op
== O_constant
9241 || imm_expr
.X_op
== O_big
)
9242 as_bad (_("expression out of range"));
9248 case 'o': /* 16 bit offset */
9249 /* Check whether there is only a single bracketed expression
9250 left. If so, it must be the base register and the
9251 constant must be zero. */
9252 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9254 offset_expr
.X_op
= O_constant
;
9255 offset_expr
.X_add_number
= 0;
9259 /* If this value won't fit into a 16 bit offset, then go
9260 find a macro that will generate the 32 bit offset
9262 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9263 && (offset_expr
.X_op
!= O_constant
9264 || offset_expr
.X_add_number
>= 0x8000
9265 || offset_expr
.X_add_number
< -0x8000))
9271 case 'p': /* pc relative offset */
9272 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9273 my_getExpression (&offset_expr
, s
);
9277 case 'u': /* upper 16 bits */
9278 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9279 && imm_expr
.X_op
== O_constant
9280 && (imm_expr
.X_add_number
< 0
9281 || imm_expr
.X_add_number
>= 0x10000))
9282 as_bad (_("lui expression not in range 0..65535"));
9286 case 'a': /* 26 bit address */
9287 my_getExpression (&offset_expr
, s
);
9289 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9292 case 'N': /* 3 bit branch condition code */
9293 case 'M': /* 3 bit compare condition code */
9294 if (strncmp (s
, "$fcc", 4) != 0)
9304 while (ISDIGIT (*s
));
9306 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9307 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9308 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9309 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9310 && (regno
& 1) != 0)
9311 as_warn(_("Condition code register should be even for %s, was %d"),
9313 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9314 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9315 && (regno
& 3) != 0)
9316 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9319 INSERT_OPERAND (BCC
, *ip
, regno
);
9321 INSERT_OPERAND (CCC
, *ip
, regno
);
9325 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9336 while (ISDIGIT (*s
));
9339 c
= 8; /* Invalid sel value. */
9342 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9343 ip
->insn_opcode
|= c
;
9347 /* Must be at least one digit. */
9348 my_getExpression (&imm_expr
, s
);
9349 check_absolute_expr (ip
, &imm_expr
);
9351 if ((unsigned long) imm_expr
.X_add_number
9352 > (unsigned long) OP_MASK_VECBYTE
)
9354 as_bad (_("bad byte vector index (%ld)"),
9355 (long) imm_expr
.X_add_number
);
9356 imm_expr
.X_add_number
= 0;
9359 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9360 imm_expr
.X_op
= O_absent
;
9365 my_getExpression (&imm_expr
, s
);
9366 check_absolute_expr (ip
, &imm_expr
);
9368 if ((unsigned long) imm_expr
.X_add_number
9369 > (unsigned long) OP_MASK_VECALIGN
)
9371 as_bad (_("bad byte vector index (%ld)"),
9372 (long) imm_expr
.X_add_number
);
9373 imm_expr
.X_add_number
= 0;
9376 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9377 imm_expr
.X_op
= O_absent
;
9382 as_bad (_("bad char = '%c'\n"), *args
);
9387 /* Args don't match. */
9388 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9389 !strcmp (insn
->name
, insn
[1].name
))
9393 insn_error
= _("illegal operands");
9398 insn_error
= _("illegal operands");
9403 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9405 /* This routine assembles an instruction into its binary format when
9406 assembling for the mips16. As a side effect, it sets one of the
9407 global variables imm_reloc or offset_reloc to the type of
9408 relocation to do if one of the operands is an address expression.
9409 It also sets mips16_small and mips16_ext if the user explicitly
9410 requested a small or extended instruction. */
9413 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9417 struct mips_opcode
*insn
;
9420 unsigned int lastregno
= 0;
9426 mips16_small
= FALSE
;
9429 for (s
= str
; ISLOWER (*s
); ++s
)
9441 if (s
[1] == 't' && s
[2] == ' ')
9444 mips16_small
= TRUE
;
9448 else if (s
[1] == 'e' && s
[2] == ' ')
9457 insn_error
= _("unknown opcode");
9461 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9462 mips16_small
= TRUE
;
9464 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9466 insn_error
= _("unrecognized opcode");
9475 assert (strcmp (insn
->name
, str
) == 0);
9477 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_opts
.arch
))
9484 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
9485 && strcmp (insn
->name
, insn
[1].name
) == 0)
9494 static char buf
[100];
9496 _("opcode not supported on this processor: %s (%s)"),
9497 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
9498 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
9505 create_insn (ip
, insn
);
9506 imm_expr
.X_op
= O_absent
;
9507 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9508 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9509 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9510 imm2_expr
.X_op
= O_absent
;
9511 offset_expr
.X_op
= O_absent
;
9512 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9513 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9514 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9515 for (args
= insn
->args
; 1; ++args
)
9522 /* In this switch statement we call break if we did not find
9523 a match, continue if we did find a match, or return if we
9532 /* Stuff the immediate value in now, if we can. */
9533 if (imm_expr
.X_op
== O_constant
9534 && *imm_reloc
> BFD_RELOC_UNUSED
9535 && insn
->pinfo
!= INSN_MACRO
)
9539 switch (*offset_reloc
)
9541 case BFD_RELOC_MIPS16_HI16_S
:
9542 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9545 case BFD_RELOC_MIPS16_HI16
:
9546 tmp
= imm_expr
.X_add_number
>> 16;
9549 case BFD_RELOC_MIPS16_LO16
:
9550 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9554 case BFD_RELOC_UNUSED
:
9555 tmp
= imm_expr
.X_add_number
;
9561 *offset_reloc
= BFD_RELOC_UNUSED
;
9563 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9564 tmp
, TRUE
, mips16_small
,
9565 mips16_ext
, &ip
->insn_opcode
,
9566 &ip
->use_extend
, &ip
->extend
);
9567 imm_expr
.X_op
= O_absent
;
9568 *imm_reloc
= BFD_RELOC_UNUSED
;
9582 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9585 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9601 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9603 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9630 while (ISDIGIT (*s
));
9633 as_bad (_("invalid register number (%d)"), regno
);
9639 if (s
[1] == 'r' && s
[2] == 'a')
9644 else if (s
[1] == 'f' && s
[2] == 'p')
9649 else if (s
[1] == 's' && s
[2] == 'p')
9654 else if (s
[1] == 'g' && s
[2] == 'p')
9659 else if (s
[1] == 'a' && s
[2] == 't')
9664 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9669 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9674 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9687 if (c
== 'v' || c
== 'w')
9689 regno
= mips16_to_32_reg_map
[lastregno
];
9703 regno
= mips32_to_16_reg_map
[regno
];
9708 regno
= ILLEGAL_REG
;
9713 regno
= ILLEGAL_REG
;
9718 regno
= ILLEGAL_REG
;
9723 if (regno
== AT
&& ! mips_opts
.noat
)
9724 as_warn (_("used $at without \".set noat\""));
9731 if (regno
== ILLEGAL_REG
)
9738 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9742 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9745 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9748 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9754 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9757 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9758 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9768 if (strncmp (s
, "$pc", 3) == 0)
9785 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9788 if (imm_expr
.X_op
!= O_constant
)
9791 ip
->use_extend
= TRUE
;
9796 /* We need to relax this instruction. */
9797 *offset_reloc
= *imm_reloc
;
9798 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9803 *imm_reloc
= BFD_RELOC_UNUSED
;
9811 my_getExpression (&imm_expr
, s
);
9812 if (imm_expr
.X_op
== O_register
)
9814 /* What we thought was an expression turned out to
9817 if (s
[0] == '(' && args
[1] == '(')
9819 /* It looks like the expression was omitted
9820 before a register indirection, which means
9821 that the expression is implicitly zero. We
9822 still set up imm_expr, so that we handle
9823 explicit extensions correctly. */
9824 imm_expr
.X_op
= O_constant
;
9825 imm_expr
.X_add_number
= 0;
9826 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9833 /* We need to relax this instruction. */
9834 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9843 /* We use offset_reloc rather than imm_reloc for the PC
9844 relative operands. This lets macros with both
9845 immediate and address operands work correctly. */
9846 my_getExpression (&offset_expr
, s
);
9848 if (offset_expr
.X_op
== O_register
)
9851 /* We need to relax this instruction. */
9852 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9856 case '6': /* break code */
9857 my_getExpression (&imm_expr
, s
);
9858 check_absolute_expr (ip
, &imm_expr
);
9859 if ((unsigned long) imm_expr
.X_add_number
> 63)
9860 as_warn (_("Invalid value for `%s' (%lu)"),
9862 (unsigned long) imm_expr
.X_add_number
);
9863 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9864 imm_expr
.X_op
= O_absent
;
9868 case 'a': /* 26 bit address */
9869 my_getExpression (&offset_expr
, s
);
9871 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9872 ip
->insn_opcode
<<= 16;
9875 case 'l': /* register list for entry macro */
9876 case 'L': /* register list for exit macro */
9886 int freg
, reg1
, reg2
;
9888 while (*s
== ' ' || *s
== ',')
9892 as_bad (_("can't parse register list"));
9904 while (ISDIGIT (*s
))
9926 as_bad (_("invalid register list"));
9931 while (ISDIGIT (*s
))
9938 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9943 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9948 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9949 mask
|= (reg2
- 3) << 3;
9950 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9951 mask
|= (reg2
- 15) << 1;
9952 else if (reg1
== RA
&& reg2
== RA
)
9956 as_bad (_("invalid register list"));
9960 /* The mask is filled in in the opcode table for the
9961 benefit of the disassembler. We remove it before
9962 applying the actual mask. */
9963 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9964 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9968 case 'm': /* Register list for save insn. */
9969 case 'M': /* Register list for restore insn. */
9972 int framesz
= 0, seen_framesz
= 0;
9973 int args
= 0, statics
= 0, sregs
= 0;
9977 unsigned int reg1
, reg2
;
9979 SKIP_SPACE_TABS (s
);
9982 SKIP_SPACE_TABS (s
);
9984 my_getExpression (&imm_expr
, s
);
9985 if (imm_expr
.X_op
== O_constant
)
9987 /* Handle the frame size. */
9990 as_bad (_("more than one frame size in list"));
9994 framesz
= imm_expr
.X_add_number
;
9995 imm_expr
.X_op
= O_absent
;
10002 as_bad (_("can't parse register list"));
10008 while (ISDIGIT (*s
))
10014 SKIP_SPACE_TABS (s
);
10022 as_bad (_("can't parse register list"));
10027 while (ISDIGIT (*s
))
10035 while (reg1
<= reg2
)
10037 if (reg1
>= 4 && reg1
<= 7)
10039 if (c
== 'm' && !seen_framesz
)
10041 args
|= 1 << (reg1
- 4);
10043 /* statics $a0-$a3 */
10044 statics
|= 1 << (reg1
- 4);
10046 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10049 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10051 else if (reg1
== 31)
10053 /* Add $ra to insn. */
10058 as_bad (_("unexpected register in list"));
10066 /* Encode args/statics combination. */
10067 if (args
& statics
)
10068 as_bad (_("arg/static registers overlap"));
10069 else if (args
== 0xf)
10070 /* All $a0-$a3 are args. */
10071 opcode
|= MIPS16_ALL_ARGS
<< 16;
10072 else if (statics
== 0xf)
10073 /* All $a0-$a3 are statics. */
10074 opcode
|= MIPS16_ALL_STATICS
<< 16;
10077 int narg
= 0, nstat
= 0;
10079 /* Count arg registers. */
10086 as_bad (_("invalid arg register list"));
10088 /* Count static registers. */
10089 while (statics
& 0x8)
10091 statics
= (statics
<< 1) & 0xf;
10095 as_bad (_("invalid static register list"));
10097 /* Encode args/statics. */
10098 opcode
|= ((narg
<< 2) | nstat
) << 16;
10101 /* Encode $s0/$s1. */
10102 if (sregs
& (1 << 0)) /* $s0 */
10104 if (sregs
& (1 << 1)) /* $s1 */
10110 /* Count regs $s2-$s8. */
10118 as_bad (_("invalid static register list"));
10119 /* Encode $s2-$s8. */
10120 opcode
|= nsreg
<< 24;
10123 /* Encode frame size. */
10125 as_bad (_("missing frame size"));
10126 else if ((framesz
& 7) != 0 || framesz
< 0
10127 || framesz
> 0xff * 8)
10128 as_bad (_("invalid frame size"));
10129 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10132 opcode
|= (((framesz
& 0xf0) << 16)
10133 | (framesz
& 0x0f));
10136 /* Finally build the instruction. */
10137 if ((opcode
>> 16) != 0 || framesz
== 0)
10139 ip
->use_extend
= TRUE
;
10140 ip
->extend
= opcode
>> 16;
10142 ip
->insn_opcode
|= opcode
& 0x7f;
10146 case 'e': /* extend code */
10147 my_getExpression (&imm_expr
, s
);
10148 check_absolute_expr (ip
, &imm_expr
);
10149 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10151 as_warn (_("Invalid value for `%s' (%lu)"),
10153 (unsigned long) imm_expr
.X_add_number
);
10154 imm_expr
.X_add_number
&= 0x7ff;
10156 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10157 imm_expr
.X_op
= O_absent
;
10167 /* Args don't match. */
10168 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10169 strcmp (insn
->name
, insn
[1].name
) == 0)
10176 insn_error
= _("illegal operands");
10182 /* This structure holds information we know about a mips16 immediate
10185 struct mips16_immed_operand
10187 /* The type code used in the argument string in the opcode table. */
10189 /* The number of bits in the short form of the opcode. */
10191 /* The number of bits in the extended form of the opcode. */
10193 /* The amount by which the short form is shifted when it is used;
10194 for example, the sw instruction has a shift count of 2. */
10196 /* The amount by which the short form is shifted when it is stored
10197 into the instruction code. */
10199 /* Non-zero if the short form is unsigned. */
10201 /* Non-zero if the extended form is unsigned. */
10203 /* Non-zero if the value is PC relative. */
10207 /* The mips16 immediate operand types. */
10209 static const struct mips16_immed_operand mips16_immed_operands
[] =
10211 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10212 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10213 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10214 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10215 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10216 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10217 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10218 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10219 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10220 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10221 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10222 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10223 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10224 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10225 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10226 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10227 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10228 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10229 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10230 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10231 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10234 #define MIPS16_NUM_IMMED \
10235 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10237 /* Handle a mips16 instruction with an immediate value. This or's the
10238 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10239 whether an extended value is needed; if one is needed, it sets
10240 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10241 If SMALL is true, an unextended opcode was explicitly requested.
10242 If EXT is true, an extended opcode was explicitly requested. If
10243 WARN is true, warn if EXT does not match reality. */
10246 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10247 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10248 unsigned long *insn
, bfd_boolean
*use_extend
,
10249 unsigned short *extend
)
10251 register const struct mips16_immed_operand
*op
;
10252 int mintiny
, maxtiny
;
10253 bfd_boolean needext
;
10255 op
= mips16_immed_operands
;
10256 while (op
->type
!= type
)
10259 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10264 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10267 maxtiny
= 1 << op
->nbits
;
10272 maxtiny
= (1 << op
->nbits
) - 1;
10277 mintiny
= - (1 << (op
->nbits
- 1));
10278 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10281 /* Branch offsets have an implicit 0 in the lowest bit. */
10282 if (type
== 'p' || type
== 'q')
10285 if ((val
& ((1 << op
->shift
) - 1)) != 0
10286 || val
< (mintiny
<< op
->shift
)
10287 || val
> (maxtiny
<< op
->shift
))
10292 if (warn
&& ext
&& ! needext
)
10293 as_warn_where (file
, line
,
10294 _("extended operand requested but not required"));
10295 if (small
&& needext
)
10296 as_bad_where (file
, line
, _("invalid unextended operand value"));
10298 if (small
|| (! ext
&& ! needext
))
10302 *use_extend
= FALSE
;
10303 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10304 insnval
<<= op
->op_shift
;
10309 long minext
, maxext
;
10315 maxext
= (1 << op
->extbits
) - 1;
10319 minext
= - (1 << (op
->extbits
- 1));
10320 maxext
= (1 << (op
->extbits
- 1)) - 1;
10322 if (val
< minext
|| val
> maxext
)
10323 as_bad_where (file
, line
,
10324 _("operand value out of range for instruction"));
10326 *use_extend
= TRUE
;
10327 if (op
->extbits
== 16)
10329 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10332 else if (op
->extbits
== 15)
10334 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10339 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10343 *extend
= (unsigned short) extval
;
10348 struct percent_op_match
10351 bfd_reloc_code_real_type reloc
;
10354 static const struct percent_op_match mips_percent_op
[] =
10356 {"%lo", BFD_RELOC_LO16
},
10358 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10359 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10360 {"%call16", BFD_RELOC_MIPS_CALL16
},
10361 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10362 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10363 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10364 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10365 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10366 {"%got", BFD_RELOC_MIPS_GOT16
},
10367 {"%gp_rel", BFD_RELOC_GPREL16
},
10368 {"%half", BFD_RELOC_16
},
10369 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10370 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10371 {"%neg", BFD_RELOC_MIPS_SUB
},
10372 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10373 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10374 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10375 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10376 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10377 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10378 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10380 {"%hi", BFD_RELOC_HI16_S
}
10383 static const struct percent_op_match mips16_percent_op
[] =
10385 {"%lo", BFD_RELOC_MIPS16_LO16
},
10386 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10387 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10391 /* Return true if *STR points to a relocation operator. When returning true,
10392 move *STR over the operator and store its relocation code in *RELOC.
10393 Leave both *STR and *RELOC alone when returning false. */
10396 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10398 const struct percent_op_match
*percent_op
;
10401 if (mips_opts
.mips16
)
10403 percent_op
= mips16_percent_op
;
10404 limit
= ARRAY_SIZE (mips16_percent_op
);
10408 percent_op
= mips_percent_op
;
10409 limit
= ARRAY_SIZE (mips_percent_op
);
10412 for (i
= 0; i
< limit
; i
++)
10413 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10415 int len
= strlen (percent_op
[i
].str
);
10417 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10420 *str
+= strlen (percent_op
[i
].str
);
10421 *reloc
= percent_op
[i
].reloc
;
10423 /* Check whether the output BFD supports this relocation.
10424 If not, issue an error and fall back on something safe. */
10425 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10427 as_bad ("relocation %s isn't supported by the current ABI",
10428 percent_op
[i
].str
);
10429 *reloc
= BFD_RELOC_UNUSED
;
10437 /* Parse string STR as a 16-bit relocatable operand. Store the
10438 expression in *EP and the relocations in the array starting
10439 at RELOC. Return the number of relocation operators used.
10441 On exit, EXPR_END points to the first character after the expression. */
10444 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10447 bfd_reloc_code_real_type reversed_reloc
[3];
10448 size_t reloc_index
, i
;
10449 int crux_depth
, str_depth
;
10452 /* Search for the start of the main expression, recoding relocations
10453 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10454 of the main expression and with CRUX_DEPTH containing the number
10455 of open brackets at that point. */
10462 crux_depth
= str_depth
;
10464 /* Skip over whitespace and brackets, keeping count of the number
10466 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10471 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10472 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10474 my_getExpression (ep
, crux
);
10477 /* Match every open bracket. */
10478 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10482 if (crux_depth
> 0)
10483 as_bad ("unclosed '('");
10487 if (reloc_index
!= 0)
10489 prev_reloc_op_frag
= frag_now
;
10490 for (i
= 0; i
< reloc_index
; i
++)
10491 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10494 return reloc_index
;
10498 my_getExpression (expressionS
*ep
, char *str
)
10503 save_in
= input_line_pointer
;
10504 input_line_pointer
= str
;
10506 expr_end
= input_line_pointer
;
10507 input_line_pointer
= save_in
;
10509 /* If we are in mips16 mode, and this is an expression based on `.',
10510 then we bump the value of the symbol by 1 since that is how other
10511 text symbols are handled. We don't bother to handle complex
10512 expressions, just `.' plus or minus a constant. */
10513 if (mips_opts
.mips16
10514 && ep
->X_op
== O_symbol
10515 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10516 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10517 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10518 && symbol_constant_p (ep
->X_add_symbol
)
10519 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10520 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10523 /* Turn a string in input_line_pointer into a floating point constant
10524 of type TYPE, and store the appropriate bytes in *LITP. The number
10525 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10526 returned, or NULL on OK. */
10529 md_atof (int type
, char *litP
, int *sizeP
)
10532 LITTLENUM_TYPE words
[4];
10548 return _("bad call to md_atof");
10551 t
= atof_ieee (input_line_pointer
, type
, words
);
10553 input_line_pointer
= t
;
10557 if (! target_big_endian
)
10559 for (i
= prec
- 1; i
>= 0; i
--)
10561 md_number_to_chars (litP
, words
[i
], 2);
10567 for (i
= 0; i
< prec
; i
++)
10569 md_number_to_chars (litP
, words
[i
], 2);
10578 md_number_to_chars (char *buf
, valueT val
, int n
)
10580 if (target_big_endian
)
10581 number_to_chars_bigendian (buf
, val
, n
);
10583 number_to_chars_littleendian (buf
, val
, n
);
10587 static int support_64bit_objects(void)
10589 const char **list
, **l
;
10592 list
= bfd_target_list ();
10593 for (l
= list
; *l
!= NULL
; l
++)
10595 /* This is traditional mips */
10596 if (strcmp (*l
, "elf64-tradbigmips") == 0
10597 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10599 if (strcmp (*l
, "elf64-bigmips") == 0
10600 || strcmp (*l
, "elf64-littlemips") == 0)
10603 yes
= (*l
!= NULL
);
10607 #endif /* OBJ_ELF */
10609 const char *md_shortopts
= "O::g::G:";
10611 struct option md_longopts
[] =
10613 /* Options which specify architecture. */
10614 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10615 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10616 {"march", required_argument
, NULL
, OPTION_MARCH
},
10617 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10618 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10619 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10620 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10621 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10622 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10623 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10624 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10625 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10626 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10627 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10628 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10629 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10630 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10631 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10632 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10633 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10634 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10635 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10636 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10637 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10639 /* Options which specify Application Specific Extensions (ASEs). */
10640 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10641 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10642 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10643 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10644 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10645 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10646 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10647 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10648 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10649 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10650 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10651 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10652 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10653 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10654 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10655 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10656 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10657 #define OPTION_MT (OPTION_ASE_BASE + 8)
10658 {"mmt", no_argument
, NULL
, OPTION_MT
},
10659 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10660 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10661 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10662 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
10663 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10664 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
10666 /* Old-style architecture options. Don't add more of these. */
10667 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
10668 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10669 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10670 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10671 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10672 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10673 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10674 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10675 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10676 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10677 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10678 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10679 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10680 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10681 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10682 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10683 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10685 /* Options which enable bug fixes. */
10686 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10687 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10688 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10689 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10690 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10691 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10692 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10693 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10694 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10695 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10696 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10697 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10698 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10699 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10701 /* Miscellaneous options. */
10702 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10703 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10704 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10705 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10706 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10707 {"break", no_argument
, NULL
, OPTION_BREAK
},
10708 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10709 #define OPTION_EB (OPTION_MISC_BASE + 2)
10710 {"EB", no_argument
, NULL
, OPTION_EB
},
10711 #define OPTION_EL (OPTION_MISC_BASE + 3)
10712 {"EL", no_argument
, NULL
, OPTION_EL
},
10713 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10714 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10715 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10716 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10717 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10718 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10719 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10720 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10721 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10722 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10723 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10724 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10725 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10726 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10727 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10728 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10729 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10730 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10731 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10732 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10733 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10734 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10735 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10736 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10738 /* ELF-specific options. */
10740 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10741 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10742 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10743 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10744 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10745 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10746 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10747 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10748 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10749 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10750 #define OPTION_32 (OPTION_ELF_BASE + 4)
10751 {"32", no_argument
, NULL
, OPTION_32
},
10752 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10753 {"n32", no_argument
, NULL
, OPTION_N32
},
10754 #define OPTION_64 (OPTION_ELF_BASE + 6)
10755 {"64", no_argument
, NULL
, OPTION_64
},
10756 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10757 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10758 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10759 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10760 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10761 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10762 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10763 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10764 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10765 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
10766 #endif /* OBJ_ELF */
10768 {NULL
, no_argument
, NULL
, 0}
10770 size_t md_longopts_size
= sizeof (md_longopts
);
10772 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10773 NEW_VALUE. Warn if another value was already specified. Note:
10774 we have to defer parsing the -march and -mtune arguments in order
10775 to handle 'from-abi' correctly, since the ABI might be specified
10776 in a later argument. */
10779 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10781 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10782 as_warn (_("A different %s was already specified, is now %s"),
10783 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10786 *string_ptr
= new_value
;
10790 md_parse_option (int c
, char *arg
)
10794 case OPTION_CONSTRUCT_FLOATS
:
10795 mips_disable_float_construction
= 0;
10798 case OPTION_NO_CONSTRUCT_FLOATS
:
10799 mips_disable_float_construction
= 1;
10811 target_big_endian
= 1;
10815 target_big_endian
= 0;
10819 if (arg
&& arg
[1] == '0')
10829 mips_debug
= atoi (arg
);
10830 /* When the MIPS assembler sees -g or -g2, it does not do
10831 optimizations which limit full symbolic debugging. We take
10832 that to be equivalent to -O0. */
10833 if (mips_debug
== 2)
10838 file_mips_isa
= ISA_MIPS1
;
10842 file_mips_isa
= ISA_MIPS2
;
10846 file_mips_isa
= ISA_MIPS3
;
10850 file_mips_isa
= ISA_MIPS4
;
10854 file_mips_isa
= ISA_MIPS5
;
10857 case OPTION_MIPS32
:
10858 file_mips_isa
= ISA_MIPS32
;
10861 case OPTION_MIPS32R2
:
10862 file_mips_isa
= ISA_MIPS32R2
;
10865 case OPTION_MIPS64R2
:
10866 file_mips_isa
= ISA_MIPS64R2
;
10869 case OPTION_MIPS64
:
10870 file_mips_isa
= ISA_MIPS64
;
10874 mips_set_option_string (&mips_tune_string
, arg
);
10878 mips_set_option_string (&mips_arch_string
, arg
);
10882 mips_set_option_string (&mips_arch_string
, "4650");
10883 mips_set_option_string (&mips_tune_string
, "4650");
10886 case OPTION_NO_M4650
:
10890 mips_set_option_string (&mips_arch_string
, "4010");
10891 mips_set_option_string (&mips_tune_string
, "4010");
10894 case OPTION_NO_M4010
:
10898 mips_set_option_string (&mips_arch_string
, "4100");
10899 mips_set_option_string (&mips_tune_string
, "4100");
10902 case OPTION_NO_M4100
:
10906 mips_set_option_string (&mips_arch_string
, "3900");
10907 mips_set_option_string (&mips_tune_string
, "3900");
10910 case OPTION_NO_M3900
:
10914 mips_opts
.ase_mdmx
= 1;
10917 case OPTION_NO_MDMX
:
10918 mips_opts
.ase_mdmx
= 0;
10922 mips_opts
.ase_dsp
= 1;
10925 case OPTION_NO_DSP
:
10926 mips_opts
.ase_dsp
= 0;
10930 mips_opts
.ase_mt
= 1;
10934 mips_opts
.ase_mt
= 0;
10937 case OPTION_MIPS16
:
10938 mips_opts
.mips16
= 1;
10939 mips_no_prev_insn ();
10942 case OPTION_NO_MIPS16
:
10943 mips_opts
.mips16
= 0;
10944 mips_no_prev_insn ();
10947 case OPTION_MIPS3D
:
10948 mips_opts
.ase_mips3d
= 1;
10951 case OPTION_NO_MIPS3D
:
10952 mips_opts
.ase_mips3d
= 0;
10955 case OPTION_SMARTMIPS
:
10956 mips_opts
.ase_smartmips
= 1;
10959 case OPTION_NO_SMARTMIPS
:
10960 mips_opts
.ase_smartmips
= 0;
10963 case OPTION_FIX_VR4120
:
10964 mips_fix_vr4120
= 1;
10967 case OPTION_NO_FIX_VR4120
:
10968 mips_fix_vr4120
= 0;
10971 case OPTION_FIX_VR4130
:
10972 mips_fix_vr4130
= 1;
10975 case OPTION_NO_FIX_VR4130
:
10976 mips_fix_vr4130
= 0;
10979 case OPTION_RELAX_BRANCH
:
10980 mips_relax_branch
= 1;
10983 case OPTION_NO_RELAX_BRANCH
:
10984 mips_relax_branch
= 0;
10987 case OPTION_MSHARED
:
10988 mips_in_shared
= TRUE
;
10991 case OPTION_MNO_SHARED
:
10992 mips_in_shared
= FALSE
;
10995 case OPTION_MSYM32
:
10996 mips_opts
.sym32
= TRUE
;
10999 case OPTION_MNO_SYM32
:
11000 mips_opts
.sym32
= FALSE
;
11004 /* When generating ELF code, we permit -KPIC and -call_shared to
11005 select SVR4_PIC, and -non_shared to select no PIC. This is
11006 intended to be compatible with Irix 5. */
11007 case OPTION_CALL_SHARED
:
11008 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11010 as_bad (_("-call_shared is supported only for ELF format"));
11013 mips_pic
= SVR4_PIC
;
11014 mips_abicalls
= TRUE
;
11017 case OPTION_NON_SHARED
:
11018 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11020 as_bad (_("-non_shared is supported only for ELF format"));
11024 mips_abicalls
= FALSE
;
11027 /* The -xgot option tells the assembler to use 32 bit offsets
11028 when accessing the got in SVR4_PIC mode. It is for Irix
11033 #endif /* OBJ_ELF */
11036 g_switch_value
= atoi (arg
);
11041 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11044 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11046 as_bad (_("-32 is supported for ELF format only"));
11049 mips_abi
= O32_ABI
;
11053 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11055 as_bad (_("-n32 is supported for ELF format only"));
11058 mips_abi
= N32_ABI
;
11062 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11064 as_bad (_("-64 is supported for ELF format only"));
11067 mips_abi
= N64_ABI
;
11068 if (! support_64bit_objects())
11069 as_fatal (_("No compiled in support for 64 bit object file format"));
11071 #endif /* OBJ_ELF */
11074 file_mips_gp32
= 1;
11078 file_mips_gp32
= 0;
11082 file_mips_fp32
= 1;
11086 file_mips_fp32
= 0;
11091 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11093 as_bad (_("-mabi is supported for ELF format only"));
11096 if (strcmp (arg
, "32") == 0)
11097 mips_abi
= O32_ABI
;
11098 else if (strcmp (arg
, "o64") == 0)
11099 mips_abi
= O64_ABI
;
11100 else if (strcmp (arg
, "n32") == 0)
11101 mips_abi
= N32_ABI
;
11102 else if (strcmp (arg
, "64") == 0)
11104 mips_abi
= N64_ABI
;
11105 if (! support_64bit_objects())
11106 as_fatal (_("No compiled in support for 64 bit object file "
11109 else if (strcmp (arg
, "eabi") == 0)
11110 mips_abi
= EABI_ABI
;
11113 as_fatal (_("invalid abi -mabi=%s"), arg
);
11117 #endif /* OBJ_ELF */
11119 case OPTION_M7000_HILO_FIX
:
11120 mips_7000_hilo_fix
= TRUE
;
11123 case OPTION_MNO_7000_HILO_FIX
:
11124 mips_7000_hilo_fix
= FALSE
;
11128 case OPTION_MDEBUG
:
11129 mips_flag_mdebug
= TRUE
;
11132 case OPTION_NO_MDEBUG
:
11133 mips_flag_mdebug
= FALSE
;
11137 mips_flag_pdr
= TRUE
;
11140 case OPTION_NO_PDR
:
11141 mips_flag_pdr
= FALSE
;
11144 case OPTION_MVXWORKS_PIC
:
11145 mips_pic
= VXWORKS_PIC
;
11147 #endif /* OBJ_ELF */
11156 /* Set up globals to generate code for the ISA or processor
11157 described by INFO. */
11160 mips_set_architecture (const struct mips_cpu_info
*info
)
11164 file_mips_arch
= info
->cpu
;
11165 mips_opts
.arch
= info
->cpu
;
11166 mips_opts
.isa
= info
->isa
;
11171 /* Likewise for tuning. */
11174 mips_set_tune (const struct mips_cpu_info
*info
)
11177 mips_tune
= info
->cpu
;
11182 mips_after_parse_args (void)
11184 const struct mips_cpu_info
*arch_info
= 0;
11185 const struct mips_cpu_info
*tune_info
= 0;
11187 /* GP relative stuff not working for PE */
11188 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11190 if (g_switch_seen
&& g_switch_value
!= 0)
11191 as_bad (_("-G not supported in this configuration."));
11192 g_switch_value
= 0;
11195 if (mips_abi
== NO_ABI
)
11196 mips_abi
= MIPS_DEFAULT_ABI
;
11198 /* The following code determines the architecture and register size.
11199 Similar code was added to GCC 3.3 (see override_options() in
11200 config/mips/mips.c). The GAS and GCC code should be kept in sync
11201 as much as possible. */
11203 if (mips_arch_string
!= 0)
11204 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11206 if (file_mips_isa
!= ISA_UNKNOWN
)
11208 /* Handle -mipsN. At this point, file_mips_isa contains the
11209 ISA level specified by -mipsN, while arch_info->isa contains
11210 the -march selection (if any). */
11211 if (arch_info
!= 0)
11213 /* -march takes precedence over -mipsN, since it is more descriptive.
11214 There's no harm in specifying both as long as the ISA levels
11216 if (file_mips_isa
!= arch_info
->isa
)
11217 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11218 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11219 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11222 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11225 if (arch_info
== 0)
11226 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11228 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11229 as_bad ("-march=%s is not compatible with the selected ABI",
11232 mips_set_architecture (arch_info
);
11234 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11235 if (mips_tune_string
!= 0)
11236 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11238 if (tune_info
== 0)
11239 mips_set_tune (arch_info
);
11241 mips_set_tune (tune_info
);
11243 if (file_mips_gp32
>= 0)
11245 /* The user specified the size of the integer registers. Make sure
11246 it agrees with the ABI and ISA. */
11247 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11248 as_bad (_("-mgp64 used with a 32-bit processor"));
11249 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11250 as_bad (_("-mgp32 used with a 64-bit ABI"));
11251 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11252 as_bad (_("-mgp64 used with a 32-bit ABI"));
11256 /* Infer the integer register size from the ABI and processor.
11257 Restrict ourselves to 32-bit registers if that's all the
11258 processor has, or if the ABI cannot handle 64-bit registers. */
11259 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11260 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11263 /* ??? GAS treats single-float processors as though they had 64-bit
11264 float registers (although it complains when double-precision
11265 instructions are used). As things stand, saying they have 32-bit
11266 registers would lead to spurious "register must be even" messages.
11267 So here we assume float registers are always the same size as
11268 integer ones, unless the user says otherwise. */
11269 if (file_mips_fp32
< 0)
11270 file_mips_fp32
= file_mips_gp32
;
11272 /* End of GCC-shared inference code. */
11274 /* This flag is set when we have a 64-bit capable CPU but use only
11275 32-bit wide registers. Note that EABI does not use it. */
11276 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11277 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11278 || mips_abi
== O32_ABI
))
11279 mips_32bitmode
= 1;
11281 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11282 as_bad (_("trap exception not supported at ISA 1"));
11284 /* If the selected architecture includes support for ASEs, enable
11285 generation of code for them. */
11286 if (mips_opts
.mips16
== -1)
11287 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11288 if (mips_opts
.ase_mips3d
== -1)
11289 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
11290 if (mips_opts
.ase_mdmx
== -1)
11291 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
11292 if (mips_opts
.ase_dsp
== -1)
11293 mips_opts
.ase_dsp
= (CPU_HAS_DSP (file_mips_arch
)) ? 1 : 0;
11294 if (mips_opts
.ase_mt
== -1)
11295 mips_opts
.ase_mt
= (CPU_HAS_MT (file_mips_arch
)) ? 1 : 0;
11297 file_mips_isa
= mips_opts
.isa
;
11298 file_ase_mips16
= mips_opts
.mips16
;
11299 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11300 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11301 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11302 file_ase_dsp
= mips_opts
.ase_dsp
;
11303 file_ase_mt
= mips_opts
.ase_mt
;
11304 mips_opts
.gp32
= file_mips_gp32
;
11305 mips_opts
.fp32
= file_mips_fp32
;
11307 if (mips_flag_mdebug
< 0)
11309 #ifdef OBJ_MAYBE_ECOFF
11310 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11311 mips_flag_mdebug
= 1;
11313 #endif /* OBJ_MAYBE_ECOFF */
11314 mips_flag_mdebug
= 0;
11319 mips_init_after_args (void)
11321 /* initialize opcodes */
11322 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11323 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11327 md_pcrel_from (fixS
*fixP
)
11329 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11330 switch (fixP
->fx_r_type
)
11332 case BFD_RELOC_16_PCREL_S2
:
11333 case BFD_RELOC_MIPS_JMP
:
11334 /* Return the address of the delay slot. */
11341 /* This is called before the symbol table is processed. In order to
11342 work with gcc when using mips-tfile, we must keep all local labels.
11343 However, in other cases, we want to discard them. If we were
11344 called with -g, but we didn't see any debugging information, it may
11345 mean that gcc is smuggling debugging information through to
11346 mips-tfile, in which case we must generate all local labels. */
11349 mips_frob_file_before_adjust (void)
11351 #ifndef NO_ECOFF_DEBUGGING
11352 if (ECOFF_DEBUGGING
11354 && ! ecoff_debugging_seen
)
11355 flag_keep_locals
= 1;
11359 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11360 the corresponding LO16 reloc. This is called before md_apply_fix and
11361 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11362 relocation operators.
11364 For our purposes, a %lo() expression matches a %got() or %hi()
11367 (a) it refers to the same symbol; and
11368 (b) the offset applied in the %lo() expression is no lower than
11369 the offset applied in the %got() or %hi().
11371 (b) allows us to cope with code like:
11374 lh $4,%lo(foo+2)($4)
11376 ...which is legal on RELA targets, and has a well-defined behaviour
11377 if the user knows that adding 2 to "foo" will not induce a carry to
11380 When several %lo()s match a particular %got() or %hi(), we use the
11381 following rules to distinguish them:
11383 (1) %lo()s with smaller offsets are a better match than %lo()s with
11386 (2) %lo()s with no matching %got() or %hi() are better than those
11387 that already have a matching %got() or %hi().
11389 (3) later %lo()s are better than earlier %lo()s.
11391 These rules are applied in order.
11393 (1) means, among other things, that %lo()s with identical offsets are
11394 chosen if they exist.
11396 (2) means that we won't associate several high-part relocations with
11397 the same low-part relocation unless there's no alternative. Having
11398 several high parts for the same low part is a GNU extension; this rule
11399 allows careful users to avoid it.
11401 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11402 with the last high-part relocation being at the front of the list.
11403 It therefore makes sense to choose the last matching low-part
11404 relocation, all other things being equal. It's also easier
11405 to code that way. */
11408 mips_frob_file (void)
11410 struct mips_hi_fixup
*l
;
11412 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11414 segment_info_type
*seginfo
;
11415 bfd_boolean matched_lo_p
;
11416 fixS
**hi_pos
, **lo_pos
, **pos
;
11418 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11420 /* If a GOT16 relocation turns out to be against a global symbol,
11421 there isn't supposed to be a matching LO. */
11422 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11423 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11426 /* Check quickly whether the next fixup happens to be a matching %lo. */
11427 if (fixup_has_matching_lo_p (l
->fixp
))
11430 seginfo
= seg_info (l
->seg
);
11432 /* Set HI_POS to the position of this relocation in the chain.
11433 Set LO_POS to the position of the chosen low-part relocation.
11434 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11435 relocation that matches an immediately-preceding high-part
11439 matched_lo_p
= FALSE
;
11440 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11442 if (*pos
== l
->fixp
)
11445 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11446 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11447 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11448 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11450 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11452 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11455 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11456 && fixup_has_matching_lo_p (*pos
));
11459 /* If we found a match, remove the high-part relocation from its
11460 current position and insert it before the low-part relocation.
11461 Make the offsets match so that fixup_has_matching_lo_p()
11464 We don't warn about unmatched high-part relocations since some
11465 versions of gcc have been known to emit dead "lui ...%hi(...)"
11467 if (lo_pos
!= NULL
)
11469 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11470 if (l
->fixp
->fx_next
!= *lo_pos
)
11472 *hi_pos
= l
->fixp
->fx_next
;
11473 l
->fixp
->fx_next
= *lo_pos
;
11480 /* We may have combined relocations without symbols in the N32/N64 ABI.
11481 We have to prevent gas from dropping them. */
11484 mips_force_relocation (fixS
*fixp
)
11486 if (generic_force_reloc (fixp
))
11490 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11491 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11492 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11493 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11499 /* Apply a fixup to the object file. */
11502 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11506 reloc_howto_type
*howto
;
11508 /* We ignore generic BFD relocations we don't know about. */
11509 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11513 assert (fixP
->fx_size
== 4
11514 || fixP
->fx_r_type
== BFD_RELOC_16
11515 || fixP
->fx_r_type
== BFD_RELOC_64
11516 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11517 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11518 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11519 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11521 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11523 assert (! fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
11525 /* Don't treat parts of a composite relocation as done. There are two
11528 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11529 should nevertheless be emitted if the first part is.
11531 (2) In normal usage, composite relocations are never assembly-time
11532 constants. The easiest way of dealing with the pathological
11533 exceptions is to generate a relocation against STN_UNDEF and
11534 leave everything up to the linker. */
11535 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
11538 switch (fixP
->fx_r_type
)
11540 case BFD_RELOC_MIPS_TLS_GD
:
11541 case BFD_RELOC_MIPS_TLS_LDM
:
11542 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11543 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11544 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11545 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11546 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11547 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11550 case BFD_RELOC_MIPS_JMP
:
11551 case BFD_RELOC_MIPS_SHIFT5
:
11552 case BFD_RELOC_MIPS_SHIFT6
:
11553 case BFD_RELOC_MIPS_GOT_DISP
:
11554 case BFD_RELOC_MIPS_GOT_PAGE
:
11555 case BFD_RELOC_MIPS_GOT_OFST
:
11556 case BFD_RELOC_MIPS_SUB
:
11557 case BFD_RELOC_MIPS_INSERT_A
:
11558 case BFD_RELOC_MIPS_INSERT_B
:
11559 case BFD_RELOC_MIPS_DELETE
:
11560 case BFD_RELOC_MIPS_HIGHEST
:
11561 case BFD_RELOC_MIPS_HIGHER
:
11562 case BFD_RELOC_MIPS_SCN_DISP
:
11563 case BFD_RELOC_MIPS_REL16
:
11564 case BFD_RELOC_MIPS_RELGOT
:
11565 case BFD_RELOC_MIPS_JALR
:
11566 case BFD_RELOC_HI16
:
11567 case BFD_RELOC_HI16_S
:
11568 case BFD_RELOC_GPREL16
:
11569 case BFD_RELOC_MIPS_LITERAL
:
11570 case BFD_RELOC_MIPS_CALL16
:
11571 case BFD_RELOC_MIPS_GOT16
:
11572 case BFD_RELOC_GPREL32
:
11573 case BFD_RELOC_MIPS_GOT_HI16
:
11574 case BFD_RELOC_MIPS_GOT_LO16
:
11575 case BFD_RELOC_MIPS_CALL_HI16
:
11576 case BFD_RELOC_MIPS_CALL_LO16
:
11577 case BFD_RELOC_MIPS16_GPREL
:
11578 case BFD_RELOC_MIPS16_HI16
:
11579 case BFD_RELOC_MIPS16_HI16_S
:
11580 /* Nothing needed to do. The value comes from the reloc entry */
11583 case BFD_RELOC_MIPS16_JMP
:
11584 /* We currently always generate a reloc against a symbol, which
11585 means that we don't want an addend even if the symbol is
11591 /* This is handled like BFD_RELOC_32, but we output a sign
11592 extended value if we are only 32 bits. */
11595 if (8 <= sizeof (valueT
))
11596 md_number_to_chars ((char *) buf
, *valP
, 8);
11601 if ((*valP
& 0x80000000) != 0)
11605 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11607 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11613 case BFD_RELOC_RVA
:
11615 /* If we are deleting this reloc entry, we must fill in the
11616 value now. This can happen if we have a .word which is not
11617 resolved when it appears but is later defined. */
11619 md_number_to_chars ((char *) buf
, *valP
, 4);
11623 /* If we are deleting this reloc entry, we must fill in the
11626 md_number_to_chars ((char *) buf
, *valP
, 2);
11629 case BFD_RELOC_LO16
:
11630 case BFD_RELOC_MIPS16_LO16
:
11631 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11632 may be safe to remove, but if so it's not obvious. */
11633 /* When handling an embedded PIC switch statement, we can wind
11634 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11637 if (*valP
+ 0x8000 > 0xffff)
11638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11639 _("relocation overflow"));
11640 if (target_big_endian
)
11642 md_number_to_chars ((char *) buf
, *valP
, 2);
11646 case BFD_RELOC_16_PCREL_S2
:
11647 if ((*valP
& 0x3) != 0)
11648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11649 _("Branch to misaligned address (%lx)"), (long) *valP
);
11652 * We need to save the bits in the instruction since fixup_segment()
11653 * might be deleting the relocation entry (i.e., a branch within
11654 * the current segment).
11656 if (! fixP
->fx_done
)
11659 /* update old instruction data */
11660 if (target_big_endian
)
11661 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11663 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11665 if (*valP
+ 0x20000 <= 0x3ffff)
11667 insn
|= (*valP
>> 2) & 0xffff;
11668 md_number_to_chars ((char *) buf
, insn
, 4);
11670 else if (mips_pic
== NO_PIC
11672 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11673 && (fixP
->fx_frag
->fr_address
11674 < text_section
->vma
+ bfd_get_section_size (text_section
))
11675 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11676 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11677 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11679 /* The branch offset is too large. If this is an
11680 unconditional branch, and we are not generating PIC code,
11681 we can convert it to an absolute jump instruction. */
11682 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11683 insn
= 0x0c000000; /* jal */
11685 insn
= 0x08000000; /* j */
11686 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11688 fixP
->fx_addsy
= section_symbol (text_section
);
11689 *valP
+= md_pcrel_from (fixP
);
11690 md_number_to_chars ((char *) buf
, insn
, 4);
11694 /* If we got here, we have branch-relaxation disabled,
11695 and there's nothing we can do to fix this instruction
11696 without turning it into a longer sequence. */
11697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11698 _("Branch out of range"));
11702 case BFD_RELOC_VTABLE_INHERIT
:
11705 && !S_IS_DEFINED (fixP
->fx_addsy
)
11706 && !S_IS_WEAK (fixP
->fx_addsy
))
11707 S_SET_WEAK (fixP
->fx_addsy
);
11710 case BFD_RELOC_VTABLE_ENTRY
:
11718 /* Remember value for tc_gen_reloc. */
11719 fixP
->fx_addnumber
= *valP
;
11729 name
= input_line_pointer
;
11730 c
= get_symbol_end ();
11731 p
= (symbolS
*) symbol_find_or_make (name
);
11732 *input_line_pointer
= c
;
11736 /* Align the current frag to a given power of two. The MIPS assembler
11737 also automatically adjusts any preceding label. */
11740 mips_align (int to
, int fill
, symbolS
*label
)
11742 mips_emit_delays ();
11743 frag_align (to
, fill
, 0);
11744 record_alignment (now_seg
, to
);
11747 assert (S_GET_SEGMENT (label
) == now_seg
);
11748 symbol_set_frag (label
, frag_now
);
11749 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11753 /* Align to a given power of two. .align 0 turns off the automatic
11754 alignment used by the data creating pseudo-ops. */
11757 s_align (int x ATTRIBUTE_UNUSED
)
11760 register long temp_fill
;
11761 long max_alignment
= 15;
11765 o Note that the assembler pulls down any immediately preceding label
11766 to the aligned address.
11767 o It's not documented but auto alignment is reinstated by
11768 a .align pseudo instruction.
11769 o Note also that after auto alignment is turned off the mips assembler
11770 issues an error on attempt to assemble an improperly aligned data item.
11775 temp
= get_absolute_expression ();
11776 if (temp
> max_alignment
)
11777 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11780 as_warn (_("Alignment negative: 0 assumed."));
11783 if (*input_line_pointer
== ',')
11785 ++input_line_pointer
;
11786 temp_fill
= get_absolute_expression ();
11793 mips_align (temp
, (int) temp_fill
,
11794 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11801 demand_empty_rest_of_line ();
11805 s_change_sec (int sec
)
11810 /* The ELF backend needs to know that we are changing sections, so
11811 that .previous works correctly. We could do something like check
11812 for an obj_section_change_hook macro, but that might be confusing
11813 as it would not be appropriate to use it in the section changing
11814 functions in read.c, since obj-elf.c intercepts those. FIXME:
11815 This should be cleaner, somehow. */
11816 obj_elf_section_change_hook ();
11819 mips_emit_delays ();
11829 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11830 demand_empty_rest_of_line ();
11834 seg
= subseg_new (RDATA_SECTION_NAME
,
11835 (subsegT
) get_absolute_expression ());
11836 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11838 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11839 | SEC_READONLY
| SEC_RELOC
11841 if (strcmp (TARGET_OS
, "elf") != 0)
11842 record_alignment (seg
, 4);
11844 demand_empty_rest_of_line ();
11848 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11849 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11851 bfd_set_section_flags (stdoutput
, seg
,
11852 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11853 if (strcmp (TARGET_OS
, "elf") != 0)
11854 record_alignment (seg
, 4);
11856 demand_empty_rest_of_line ();
11864 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11867 char *section_name
;
11872 int section_entry_size
;
11873 int section_alignment
;
11875 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11878 section_name
= input_line_pointer
;
11879 c
= get_symbol_end ();
11881 next_c
= *(input_line_pointer
+ 1);
11883 /* Do we have .section Name<,"flags">? */
11884 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11886 /* just after name is now '\0'. */
11887 *input_line_pointer
= c
;
11888 input_line_pointer
= section_name
;
11889 obj_elf_section (ignore
);
11892 input_line_pointer
++;
11894 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11896 section_type
= get_absolute_expression ();
11899 if (*input_line_pointer
++ == ',')
11900 section_flag
= get_absolute_expression ();
11903 if (*input_line_pointer
++ == ',')
11904 section_entry_size
= get_absolute_expression ();
11906 section_entry_size
= 0;
11907 if (*input_line_pointer
++ == ',')
11908 section_alignment
= get_absolute_expression ();
11910 section_alignment
= 0;
11912 section_name
= xstrdup (section_name
);
11914 /* When using the generic form of .section (as implemented by obj-elf.c),
11915 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11916 traditionally had to fall back on the more common @progbits instead.
11918 There's nothing really harmful in this, since bfd will correct
11919 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11920 means that, for backwards compatibility, the special_section entries
11921 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11923 Even so, we shouldn't force users of the MIPS .section syntax to
11924 incorrectly label the sections as SHT_PROGBITS. The best compromise
11925 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11926 generic type-checking code. */
11927 if (section_type
== SHT_MIPS_DWARF
)
11928 section_type
= SHT_PROGBITS
;
11930 obj_elf_change_section (section_name
, section_type
, section_flag
,
11931 section_entry_size
, 0, 0, 0);
11933 if (now_seg
->name
!= section_name
)
11934 free (section_name
);
11935 #endif /* OBJ_ELF */
11939 mips_enable_auto_align (void)
11945 s_cons (int log_size
)
11949 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11950 mips_emit_delays ();
11951 if (log_size
> 0 && auto_align
)
11952 mips_align (log_size
, 0, label
);
11953 mips_clear_insn_labels ();
11954 cons (1 << log_size
);
11958 s_float_cons (int type
)
11962 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11964 mips_emit_delays ();
11969 mips_align (3, 0, label
);
11971 mips_align (2, 0, label
);
11974 mips_clear_insn_labels ();
11979 /* Handle .globl. We need to override it because on Irix 5 you are
11982 where foo is an undefined symbol, to mean that foo should be
11983 considered to be the address of a function. */
11986 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11995 name
= input_line_pointer
;
11996 c
= get_symbol_end ();
11997 symbolP
= symbol_find_or_make (name
);
11998 S_SET_EXTERNAL (symbolP
);
12000 *input_line_pointer
= c
;
12001 SKIP_WHITESPACE ();
12003 /* On Irix 5, every global symbol that is not explicitly labelled as
12004 being a function is apparently labelled as being an object. */
12007 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12008 && (*input_line_pointer
!= ','))
12013 secname
= input_line_pointer
;
12014 c
= get_symbol_end ();
12015 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12017 as_bad (_("%s: no such section"), secname
);
12018 *input_line_pointer
= c
;
12020 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12021 flag
= BSF_FUNCTION
;
12024 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12026 c
= *input_line_pointer
;
12029 input_line_pointer
++;
12030 SKIP_WHITESPACE ();
12031 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12037 demand_empty_rest_of_line ();
12041 s_option (int x ATTRIBUTE_UNUSED
)
12046 opt
= input_line_pointer
;
12047 c
= get_symbol_end ();
12051 /* FIXME: What does this mean? */
12053 else if (strncmp (opt
, "pic", 3) == 0)
12057 i
= atoi (opt
+ 3);
12062 mips_pic
= SVR4_PIC
;
12063 mips_abicalls
= TRUE
;
12066 as_bad (_(".option pic%d not supported"), i
);
12068 if (mips_pic
== SVR4_PIC
)
12070 if (g_switch_seen
&& g_switch_value
!= 0)
12071 as_warn (_("-G may not be used with SVR4 PIC code"));
12072 g_switch_value
= 0;
12073 bfd_set_gp_size (stdoutput
, 0);
12077 as_warn (_("Unrecognized option \"%s\""), opt
);
12079 *input_line_pointer
= c
;
12080 demand_empty_rest_of_line ();
12083 /* This structure is used to hold a stack of .set values. */
12085 struct mips_option_stack
12087 struct mips_option_stack
*next
;
12088 struct mips_set_options options
;
12091 static struct mips_option_stack
*mips_opts_stack
;
12093 /* Handle the .set pseudo-op. */
12096 s_mipsset (int x ATTRIBUTE_UNUSED
)
12098 char *name
= input_line_pointer
, ch
;
12100 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12101 ++input_line_pointer
;
12102 ch
= *input_line_pointer
;
12103 *input_line_pointer
= '\0';
12105 if (strcmp (name
, "reorder") == 0)
12107 if (mips_opts
.noreorder
)
12110 else if (strcmp (name
, "noreorder") == 0)
12112 if (!mips_opts
.noreorder
)
12113 start_noreorder ();
12115 else if (strcmp (name
, "at") == 0)
12117 mips_opts
.noat
= 0;
12119 else if (strcmp (name
, "noat") == 0)
12121 mips_opts
.noat
= 1;
12123 else if (strcmp (name
, "macro") == 0)
12125 mips_opts
.warn_about_macros
= 0;
12127 else if (strcmp (name
, "nomacro") == 0)
12129 if (mips_opts
.noreorder
== 0)
12130 as_bad (_("`noreorder' must be set before `nomacro'"));
12131 mips_opts
.warn_about_macros
= 1;
12133 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12135 mips_opts
.nomove
= 0;
12137 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12139 mips_opts
.nomove
= 1;
12141 else if (strcmp (name
, "bopt") == 0)
12143 mips_opts
.nobopt
= 0;
12145 else if (strcmp (name
, "nobopt") == 0)
12147 mips_opts
.nobopt
= 1;
12149 else if (strcmp (name
, "mips16") == 0
12150 || strcmp (name
, "MIPS-16") == 0)
12151 mips_opts
.mips16
= 1;
12152 else if (strcmp (name
, "nomips16") == 0
12153 || strcmp (name
, "noMIPS-16") == 0)
12154 mips_opts
.mips16
= 0;
12155 else if (strcmp (name
, "smartmips") == 0)
12157 if (!ISA_SUPPORT_SMARTMIPS
)
12158 as_warn ("%s ISA does not support SmartMIPS ASE",
12159 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12160 mips_opts
.ase_smartmips
= 1;
12162 else if (strcmp (name
, "nosmartmips") == 0)
12163 mips_opts
.ase_smartmips
= 0;
12164 else if (strcmp (name
, "mips3d") == 0)
12165 mips_opts
.ase_mips3d
= 1;
12166 else if (strcmp (name
, "nomips3d") == 0)
12167 mips_opts
.ase_mips3d
= 0;
12168 else if (strcmp (name
, "mdmx") == 0)
12169 mips_opts
.ase_mdmx
= 1;
12170 else if (strcmp (name
, "nomdmx") == 0)
12171 mips_opts
.ase_mdmx
= 0;
12172 else if (strcmp (name
, "dsp") == 0)
12173 mips_opts
.ase_dsp
= 1;
12174 else if (strcmp (name
, "nodsp") == 0)
12175 mips_opts
.ase_dsp
= 0;
12176 else if (strcmp (name
, "mt") == 0)
12177 mips_opts
.ase_mt
= 1;
12178 else if (strcmp (name
, "nomt") == 0)
12179 mips_opts
.ase_mt
= 0;
12180 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12184 /* Permit the user to change the ISA and architecture on the fly.
12185 Needless to say, misuse can cause serious problems. */
12186 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12189 mips_opts
.isa
= file_mips_isa
;
12190 mips_opts
.arch
= file_mips_arch
;
12192 else if (strncmp (name
, "arch=", 5) == 0)
12194 const struct mips_cpu_info
*p
;
12196 p
= mips_parse_cpu("internal use", name
+ 5);
12198 as_bad (_("unknown architecture %s"), name
+ 5);
12201 mips_opts
.arch
= p
->cpu
;
12202 mips_opts
.isa
= p
->isa
;
12205 else if (strncmp (name
, "mips", 4) == 0)
12207 const struct mips_cpu_info
*p
;
12209 p
= mips_parse_cpu("internal use", name
);
12211 as_bad (_("unknown ISA level %s"), name
+ 4);
12214 mips_opts
.arch
= p
->cpu
;
12215 mips_opts
.isa
= p
->isa
;
12219 as_bad (_("unknown ISA or architecture %s"), name
);
12221 switch (mips_opts
.isa
)
12229 mips_opts
.gp32
= 1;
12230 mips_opts
.fp32
= 1;
12237 mips_opts
.gp32
= 0;
12238 mips_opts
.fp32
= 0;
12241 as_bad (_("unknown ISA level %s"), name
+ 4);
12246 mips_opts
.gp32
= file_mips_gp32
;
12247 mips_opts
.fp32
= file_mips_fp32
;
12250 else if (strcmp (name
, "autoextend") == 0)
12251 mips_opts
.noautoextend
= 0;
12252 else if (strcmp (name
, "noautoextend") == 0)
12253 mips_opts
.noautoextend
= 1;
12254 else if (strcmp (name
, "push") == 0)
12256 struct mips_option_stack
*s
;
12258 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12259 s
->next
= mips_opts_stack
;
12260 s
->options
= mips_opts
;
12261 mips_opts_stack
= s
;
12263 else if (strcmp (name
, "pop") == 0)
12265 struct mips_option_stack
*s
;
12267 s
= mips_opts_stack
;
12269 as_bad (_(".set pop with no .set push"));
12272 /* If we're changing the reorder mode we need to handle
12273 delay slots correctly. */
12274 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12275 start_noreorder ();
12276 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12279 mips_opts
= s
->options
;
12280 mips_opts_stack
= s
->next
;
12284 else if (strcmp (name
, "sym32") == 0)
12285 mips_opts
.sym32
= TRUE
;
12286 else if (strcmp (name
, "nosym32") == 0)
12287 mips_opts
.sym32
= FALSE
;
12290 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12292 *input_line_pointer
= ch
;
12293 demand_empty_rest_of_line ();
12296 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12297 .option pic2. It means to generate SVR4 PIC calls. */
12300 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12302 mips_pic
= SVR4_PIC
;
12303 mips_abicalls
= TRUE
;
12305 if (g_switch_seen
&& g_switch_value
!= 0)
12306 as_warn (_("-G may not be used with SVR4 PIC code"));
12307 g_switch_value
= 0;
12309 bfd_set_gp_size (stdoutput
, 0);
12310 demand_empty_rest_of_line ();
12313 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12314 PIC code. It sets the $gp register for the function based on the
12315 function address, which is in the register named in the argument.
12316 This uses a relocation against _gp_disp, which is handled specially
12317 by the linker. The result is:
12318 lui $gp,%hi(_gp_disp)
12319 addiu $gp,$gp,%lo(_gp_disp)
12320 addu $gp,$gp,.cpload argument
12321 The .cpload argument is normally $25 == $t9.
12323 The -mno-shared option changes this to:
12324 lui $gp,%hi(__gnu_local_gp)
12325 addiu $gp,$gp,%lo(__gnu_local_gp)
12326 and the argument is ignored. This saves an instruction, but the
12327 resulting code is not position independent; it uses an absolute
12328 address for __gnu_local_gp. Thus code assembled with -mno-shared
12329 can go into an ordinary executable, but not into a shared library. */
12332 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12338 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12339 .cpload is ignored. */
12340 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12346 /* .cpload should be in a .set noreorder section. */
12347 if (mips_opts
.noreorder
== 0)
12348 as_warn (_(".cpload not in noreorder section"));
12350 reg
= tc_get_register (0);
12352 /* If we need to produce a 64-bit address, we are better off using
12353 the default instruction sequence. */
12354 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12356 ex
.X_op
= O_symbol
;
12357 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12359 ex
.X_op_symbol
= NULL
;
12360 ex
.X_add_number
= 0;
12362 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12363 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12366 macro_build_lui (&ex
, mips_gp_register
);
12367 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12368 mips_gp_register
, BFD_RELOC_LO16
);
12370 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12371 mips_gp_register
, reg
);
12374 demand_empty_rest_of_line ();
12377 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12378 .cpsetup $reg1, offset|$reg2, label
12380 If offset is given, this results in:
12381 sd $gp, offset($sp)
12382 lui $gp, %hi(%neg(%gp_rel(label)))
12383 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12384 daddu $gp, $gp, $reg1
12386 If $reg2 is given, this results in:
12387 daddu $reg2, $gp, $0
12388 lui $gp, %hi(%neg(%gp_rel(label)))
12389 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12390 daddu $gp, $gp, $reg1
12391 $reg1 is normally $25 == $t9.
12393 The -mno-shared option replaces the last three instructions with
12395 addiu $gp,$gp,%lo(_gp)
12399 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12401 expressionS ex_off
;
12402 expressionS ex_sym
;
12405 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12406 We also need NewABI support. */
12407 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12413 reg1
= tc_get_register (0);
12414 SKIP_WHITESPACE ();
12415 if (*input_line_pointer
!= ',')
12417 as_bad (_("missing argument separator ',' for .cpsetup"));
12421 ++input_line_pointer
;
12422 SKIP_WHITESPACE ();
12423 if (*input_line_pointer
== '$')
12425 mips_cpreturn_register
= tc_get_register (0);
12426 mips_cpreturn_offset
= -1;
12430 mips_cpreturn_offset
= get_absolute_expression ();
12431 mips_cpreturn_register
= -1;
12433 SKIP_WHITESPACE ();
12434 if (*input_line_pointer
!= ',')
12436 as_bad (_("missing argument separator ',' for .cpsetup"));
12440 ++input_line_pointer
;
12441 SKIP_WHITESPACE ();
12442 expression (&ex_sym
);
12445 if (mips_cpreturn_register
== -1)
12447 ex_off
.X_op
= O_constant
;
12448 ex_off
.X_add_symbol
= NULL
;
12449 ex_off
.X_op_symbol
= NULL
;
12450 ex_off
.X_add_number
= mips_cpreturn_offset
;
12452 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12453 BFD_RELOC_LO16
, SP
);
12456 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12457 mips_gp_register
, 0);
12459 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12461 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12462 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12465 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12466 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12467 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12469 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12470 mips_gp_register
, reg1
);
12476 ex
.X_op
= O_symbol
;
12477 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12478 ex
.X_op_symbol
= NULL
;
12479 ex
.X_add_number
= 0;
12481 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12482 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12484 macro_build_lui (&ex
, mips_gp_register
);
12485 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12486 mips_gp_register
, BFD_RELOC_LO16
);
12491 demand_empty_rest_of_line ();
12495 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12497 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12498 .cplocal is ignored. */
12499 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12505 mips_gp_register
= tc_get_register (0);
12506 demand_empty_rest_of_line ();
12509 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12510 offset from $sp. The offset is remembered, and after making a PIC
12511 call $gp is restored from that location. */
12514 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12518 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12519 .cprestore is ignored. */
12520 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12526 mips_cprestore_offset
= get_absolute_expression ();
12527 mips_cprestore_valid
= 1;
12529 ex
.X_op
= O_constant
;
12530 ex
.X_add_symbol
= NULL
;
12531 ex
.X_op_symbol
= NULL
;
12532 ex
.X_add_number
= mips_cprestore_offset
;
12535 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12536 SP
, HAVE_64BIT_ADDRESSES
);
12539 demand_empty_rest_of_line ();
12542 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12543 was given in the preceding .cpsetup, it results in:
12544 ld $gp, offset($sp)
12546 If a register $reg2 was given there, it results in:
12547 daddu $gp, $reg2, $0
12550 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12554 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12555 We also need NewABI support. */
12556 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12563 if (mips_cpreturn_register
== -1)
12565 ex
.X_op
= O_constant
;
12566 ex
.X_add_symbol
= NULL
;
12567 ex
.X_op_symbol
= NULL
;
12568 ex
.X_add_number
= mips_cpreturn_offset
;
12570 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12573 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12574 mips_cpreturn_register
, 0);
12577 demand_empty_rest_of_line ();
12580 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12581 code. It sets the offset to use in gp_rel relocations. */
12584 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12586 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12587 We also need NewABI support. */
12588 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12594 mips_gprel_offset
= get_absolute_expression ();
12596 demand_empty_rest_of_line ();
12599 /* Handle the .gpword pseudo-op. This is used when generating PIC
12600 code. It generates a 32 bit GP relative reloc. */
12603 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12609 /* When not generating PIC code, this is treated as .word. */
12610 if (mips_pic
!= SVR4_PIC
)
12616 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12617 mips_emit_delays ();
12619 mips_align (2, 0, label
);
12620 mips_clear_insn_labels ();
12624 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12626 as_bad (_("Unsupported use of .gpword"));
12627 ignore_rest_of_line ();
12631 md_number_to_chars (p
, 0, 4);
12632 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12633 BFD_RELOC_GPREL32
);
12635 demand_empty_rest_of_line ();
12639 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12645 /* When not generating PIC code, this is treated as .dword. */
12646 if (mips_pic
!= SVR4_PIC
)
12652 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12653 mips_emit_delays ();
12655 mips_align (3, 0, label
);
12656 mips_clear_insn_labels ();
12660 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12662 as_bad (_("Unsupported use of .gpdword"));
12663 ignore_rest_of_line ();
12667 md_number_to_chars (p
, 0, 8);
12668 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12669 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12671 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12672 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12673 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12675 demand_empty_rest_of_line ();
12678 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12679 tables in SVR4 PIC code. */
12682 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12686 /* This is ignored when not generating SVR4 PIC code. */
12687 if (mips_pic
!= SVR4_PIC
)
12693 /* Add $gp to the register named as an argument. */
12695 reg
= tc_get_register (0);
12696 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12699 demand_empty_rest_of_line ();
12702 /* Handle the .insn pseudo-op. This marks instruction labels in
12703 mips16 mode. This permits the linker to handle them specially,
12704 such as generating jalx instructions when needed. We also make
12705 them odd for the duration of the assembly, in order to generate the
12706 right sort of code. We will make them even in the adjust_symtab
12707 routine, while leaving them marked. This is convenient for the
12708 debugger and the disassembler. The linker knows to make them odd
12712 s_insn (int ignore ATTRIBUTE_UNUSED
)
12714 mips16_mark_labels ();
12716 demand_empty_rest_of_line ();
12719 /* Handle a .stabn directive. We need these in order to mark a label
12720 as being a mips16 text label correctly. Sometimes the compiler
12721 will emit a label, followed by a .stabn, and then switch sections.
12722 If the label and .stabn are in mips16 mode, then the label is
12723 really a mips16 text label. */
12726 s_mips_stab (int type
)
12729 mips16_mark_labels ();
12734 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12738 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12745 name
= input_line_pointer
;
12746 c
= get_symbol_end ();
12747 symbolP
= symbol_find_or_make (name
);
12748 S_SET_WEAK (symbolP
);
12749 *input_line_pointer
= c
;
12751 SKIP_WHITESPACE ();
12753 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12755 if (S_IS_DEFINED (symbolP
))
12757 as_bad ("ignoring attempt to redefine symbol %s",
12758 S_GET_NAME (symbolP
));
12759 ignore_rest_of_line ();
12763 if (*input_line_pointer
== ',')
12765 ++input_line_pointer
;
12766 SKIP_WHITESPACE ();
12770 if (exp
.X_op
!= O_symbol
)
12772 as_bad ("bad .weakext directive");
12773 ignore_rest_of_line ();
12776 symbol_set_value_expression (symbolP
, &exp
);
12779 demand_empty_rest_of_line ();
12782 /* Parse a register string into a number. Called from the ECOFF code
12783 to parse .frame. The argument is non-zero if this is the frame
12784 register, so that we can record it in mips_frame_reg. */
12787 tc_get_register (int frame
)
12791 SKIP_WHITESPACE ();
12792 if (*input_line_pointer
++ != '$')
12794 as_warn (_("expected `$'"));
12797 else if (ISDIGIT (*input_line_pointer
))
12799 reg
= get_absolute_expression ();
12800 if (reg
< 0 || reg
>= 32)
12802 as_warn (_("Bad register number"));
12808 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12811 input_line_pointer
+= 2;
12813 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12816 input_line_pointer
+= 2;
12818 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12821 input_line_pointer
+= 2;
12823 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12826 input_line_pointer
+= 2;
12828 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12831 input_line_pointer
+= 2;
12833 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12836 input_line_pointer
+= 3;
12838 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12841 input_line_pointer
+= 3;
12843 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12846 input_line_pointer
+= 4;
12850 as_warn (_("Unrecognized register name"));
12852 while (ISALNUM(*input_line_pointer
))
12853 input_line_pointer
++;
12858 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12859 mips_frame_reg_valid
= 1;
12860 mips_cprestore_valid
= 0;
12866 md_section_align (asection
*seg
, valueT addr
)
12868 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12871 /* We don't need to align ELF sections to the full alignment.
12872 However, Irix 5 may prefer that we align them at least to a 16
12873 byte boundary. We don't bother to align the sections if we are
12874 targeted for an embedded system. */
12875 if (strcmp (TARGET_OS
, "elf") == 0)
12881 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12884 /* Utility routine, called from above as well. If called while the
12885 input file is still being read, it's only an approximation. (For
12886 example, a symbol may later become defined which appeared to be
12887 undefined earlier.) */
12890 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12895 if (g_switch_value
> 0)
12897 const char *symname
;
12900 /* Find out whether this symbol can be referenced off the $gp
12901 register. It can be if it is smaller than the -G size or if
12902 it is in the .sdata or .sbss section. Certain symbols can
12903 not be referenced off the $gp, although it appears as though
12905 symname
= S_GET_NAME (sym
);
12906 if (symname
!= (const char *) NULL
12907 && (strcmp (symname
, "eprol") == 0
12908 || strcmp (symname
, "etext") == 0
12909 || strcmp (symname
, "_gp") == 0
12910 || strcmp (symname
, "edata") == 0
12911 || strcmp (symname
, "_fbss") == 0
12912 || strcmp (symname
, "_fdata") == 0
12913 || strcmp (symname
, "_ftext") == 0
12914 || strcmp (symname
, "end") == 0
12915 || strcmp (symname
, "_gp_disp") == 0))
12917 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12919 #ifndef NO_ECOFF_DEBUGGING
12920 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12921 && (symbol_get_obj (sym
)->ecoff_extern_size
12922 <= g_switch_value
))
12924 /* We must defer this decision until after the whole
12925 file has been read, since there might be a .extern
12926 after the first use of this symbol. */
12927 || (before_relaxing
12928 #ifndef NO_ECOFF_DEBUGGING
12929 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12931 && S_GET_VALUE (sym
) == 0)
12932 || (S_GET_VALUE (sym
) != 0
12933 && S_GET_VALUE (sym
) <= g_switch_value
)))
12937 const char *segname
;
12939 segname
= segment_name (S_GET_SEGMENT (sym
));
12940 assert (strcmp (segname
, ".lit8") != 0
12941 && strcmp (segname
, ".lit4") != 0);
12942 change
= (strcmp (segname
, ".sdata") != 0
12943 && strcmp (segname
, ".sbss") != 0
12944 && strncmp (segname
, ".sdata.", 7) != 0
12945 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12950 /* We are not optimizing for the $gp register. */
12955 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12958 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12961 bfd_boolean linkonce
;
12963 /* Handle the case of a symbol equated to another symbol. */
12964 while (symbol_equated_reloc_p (sym
))
12968 /* It's possible to get a loop here in a badly written
12970 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12976 symsec
= S_GET_SEGMENT (sym
);
12978 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12980 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12982 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12986 /* The GNU toolchain uses an extension for ELF: a section
12987 beginning with the magic string .gnu.linkonce is a linkonce
12989 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12990 sizeof ".gnu.linkonce" - 1) == 0)
12994 /* This must duplicate the test in adjust_reloc_syms. */
12995 return (symsec
!= &bfd_und_section
12996 && symsec
!= &bfd_abs_section
12997 && ! bfd_is_com_section (symsec
)
13000 /* A global or weak symbol is treated as external. */
13001 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13002 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13008 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13009 extended opcode. SEC is the section the frag is in. */
13012 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13015 register const struct mips16_immed_operand
*op
;
13017 int mintiny
, maxtiny
;
13021 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13023 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13026 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13027 op
= mips16_immed_operands
;
13028 while (op
->type
!= type
)
13031 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13036 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13039 maxtiny
= 1 << op
->nbits
;
13044 maxtiny
= (1 << op
->nbits
) - 1;
13049 mintiny
= - (1 << (op
->nbits
- 1));
13050 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13053 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13054 val
= S_GET_VALUE (fragp
->fr_symbol
);
13055 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13061 /* We won't have the section when we are called from
13062 mips_relax_frag. However, we will always have been called
13063 from md_estimate_size_before_relax first. If this is a
13064 branch to a different section, we mark it as such. If SEC is
13065 NULL, and the frag is not marked, then it must be a branch to
13066 the same section. */
13069 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13074 /* Must have been called from md_estimate_size_before_relax. */
13077 fragp
->fr_subtype
=
13078 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13080 /* FIXME: We should support this, and let the linker
13081 catch branches and loads that are out of range. */
13082 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13083 _("unsupported PC relative reference to different section"));
13087 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13088 /* Assume non-extended on the first relaxation pass.
13089 The address we have calculated will be bogus if this is
13090 a forward branch to another frag, as the forward frag
13091 will have fr_address == 0. */
13095 /* In this case, we know for sure that the symbol fragment is in
13096 the same section. If the relax_marker of the symbol fragment
13097 differs from the relax_marker of this fragment, we have not
13098 yet adjusted the symbol fragment fr_address. We want to add
13099 in STRETCH in order to get a better estimate of the address.
13100 This particularly matters because of the shift bits. */
13102 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13106 /* Adjust stretch for any alignment frag. Note that if have
13107 been expanding the earlier code, the symbol may be
13108 defined in what appears to be an earlier frag. FIXME:
13109 This doesn't handle the fr_subtype field, which specifies
13110 a maximum number of bytes to skip when doing an
13112 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13114 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13117 stretch
= - ((- stretch
)
13118 & ~ ((1 << (int) f
->fr_offset
) - 1));
13120 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13129 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13131 /* The base address rules are complicated. The base address of
13132 a branch is the following instruction. The base address of a
13133 PC relative load or add is the instruction itself, but if it
13134 is in a delay slot (in which case it can not be extended) use
13135 the address of the instruction whose delay slot it is in. */
13136 if (type
== 'p' || type
== 'q')
13140 /* If we are currently assuming that this frag should be
13141 extended, then, the current address is two bytes
13143 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13146 /* Ignore the low bit in the target, since it will be set
13147 for a text label. */
13148 if ((val
& 1) != 0)
13151 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13153 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13156 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13158 /* Branch offsets have an implicit 0 in the lowest bit. */
13159 if (type
== 'p' || type
== 'q')
13162 /* If any of the shifted bits are set, we must use an extended
13163 opcode. If the address depends on the size of this
13164 instruction, this can lead to a loop, so we arrange to always
13165 use an extended opcode. We only check this when we are in
13166 the main relaxation loop, when SEC is NULL. */
13167 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13169 fragp
->fr_subtype
=
13170 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13174 /* If we are about to mark a frag as extended because the value
13175 is precisely maxtiny + 1, then there is a chance of an
13176 infinite loop as in the following code:
13181 In this case when the la is extended, foo is 0x3fc bytes
13182 away, so the la can be shrunk, but then foo is 0x400 away, so
13183 the la must be extended. To avoid this loop, we mark the
13184 frag as extended if it was small, and is about to become
13185 extended with a value of maxtiny + 1. */
13186 if (val
== ((maxtiny
+ 1) << op
->shift
)
13187 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13190 fragp
->fr_subtype
=
13191 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13195 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13196 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13198 if ((val
& ((1 << op
->shift
) - 1)) != 0
13199 || val
< (mintiny
<< op
->shift
)
13200 || val
> (maxtiny
<< op
->shift
))
13206 /* Compute the length of a branch sequence, and adjust the
13207 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13208 worst-case length is computed, with UPDATE being used to indicate
13209 whether an unconditional (-1), branch-likely (+1) or regular (0)
13210 branch is to be computed. */
13212 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13214 bfd_boolean toofar
;
13218 && S_IS_DEFINED (fragp
->fr_symbol
)
13219 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13224 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13226 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13230 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13233 /* If the symbol is not defined or it's in a different segment,
13234 assume the user knows what's going on and emit a short
13240 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13242 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13243 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13244 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13250 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13253 if (mips_pic
!= NO_PIC
)
13255 /* Additional space for PIC loading of target address. */
13257 if (mips_opts
.isa
== ISA_MIPS1
)
13258 /* Additional space for $at-stabilizing nop. */
13262 /* If branch is conditional. */
13263 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13270 /* Estimate the size of a frag before relaxing. Unless this is the
13271 mips16, we are not really relaxing here, and the final size is
13272 encoded in the subtype information. For the mips16, we have to
13273 decide whether we are using an extended opcode or not. */
13276 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13280 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13283 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13285 return fragp
->fr_var
;
13288 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13289 /* We don't want to modify the EXTENDED bit here; it might get us
13290 into infinite loops. We change it only in mips_relax_frag(). */
13291 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13293 if (mips_pic
== NO_PIC
)
13294 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13295 else if (mips_pic
== SVR4_PIC
)
13296 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13297 else if (mips_pic
== VXWORKS_PIC
)
13298 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13305 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13306 return -RELAX_FIRST (fragp
->fr_subtype
);
13309 return -RELAX_SECOND (fragp
->fr_subtype
);
13312 /* This is called to see whether a reloc against a defined symbol
13313 should be converted into a reloc against a section. */
13316 mips_fix_adjustable (fixS
*fixp
)
13318 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13319 about the format of the offset in the .o file. */
13320 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13323 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13324 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13327 if (fixp
->fx_addsy
== NULL
)
13330 /* If symbol SYM is in a mergeable section, relocations of the form
13331 SYM + 0 can usually be made section-relative. The mergeable data
13332 is then identified by the section offset rather than by the symbol.
13334 However, if we're generating REL LO16 relocations, the offset is split
13335 between the LO16 and parterning high part relocation. The linker will
13336 need to recalculate the complete offset in order to correctly identify
13339 The linker has traditionally not looked for the parterning high part
13340 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13341 placed anywhere. Rather than break backwards compatibility by changing
13342 this, it seems better not to force the issue, and instead keep the
13343 original symbol. This will work with either linker behavior. */
13344 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13345 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13346 || reloc_needs_lo_p (fixp
->fx_r_type
))
13347 && HAVE_IN_PLACE_ADDENDS
13348 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13352 /* Don't adjust relocations against mips16 symbols, so that the linker
13353 can find them if it needs to set up a stub. */
13354 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13355 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13356 && fixp
->fx_subsy
== NULL
)
13363 /* Translate internal representation of relocation info to BFD target
13367 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13369 static arelent
*retval
[4];
13371 bfd_reloc_code_real_type code
;
13373 memset (retval
, 0, sizeof(retval
));
13374 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13375 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13376 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13377 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13379 if (fixp
->fx_pcrel
)
13381 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13383 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13384 Relocations want only the symbol offset. */
13385 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13386 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13388 /* A gruesome hack which is a result of the gruesome gas
13389 reloc handling. What's worse, for COFF (as opposed to
13390 ECOFF), we might need yet another copy of reloc->address.
13391 See bfd_install_relocation. */
13392 reloc
->addend
+= reloc
->address
;
13396 reloc
->addend
= fixp
->fx_addnumber
;
13398 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13399 entry to be used in the relocation's section offset. */
13400 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13402 reloc
->address
= reloc
->addend
;
13406 code
= fixp
->fx_r_type
;
13408 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13409 if (reloc
->howto
== NULL
)
13411 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13412 _("Can not represent %s relocation in this object file format"),
13413 bfd_get_reloc_code_name (code
));
13420 /* Relax a machine dependent frag. This returns the amount by which
13421 the current size of the frag should change. */
13424 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13426 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13428 offsetT old_var
= fragp
->fr_var
;
13430 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13432 return fragp
->fr_var
- old_var
;
13435 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13438 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13440 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13442 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13447 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13449 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13456 /* Convert a machine dependent frag. */
13459 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13461 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13464 unsigned long insn
;
13468 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13470 if (target_big_endian
)
13471 insn
= bfd_getb32 (buf
);
13473 insn
= bfd_getl32 (buf
);
13475 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13477 /* We generate a fixup instead of applying it right now
13478 because, if there are linker relaxations, we're going to
13479 need the relocations. */
13480 exp
.X_op
= O_symbol
;
13481 exp
.X_add_symbol
= fragp
->fr_symbol
;
13482 exp
.X_add_number
= fragp
->fr_offset
;
13484 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13485 4, &exp
, 1, BFD_RELOC_16_PCREL_S2
);
13486 fixp
->fx_file
= fragp
->fr_file
;
13487 fixp
->fx_line
= fragp
->fr_line
;
13489 md_number_to_chars ((char *) buf
, insn
, 4);
13496 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13497 _("relaxed out-of-range branch into a jump"));
13499 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13502 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13504 /* Reverse the branch. */
13505 switch ((insn
>> 28) & 0xf)
13508 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13509 have the condition reversed by tweaking a single
13510 bit, and their opcodes all have 0x4???????. */
13511 assert ((insn
& 0xf1000000) == 0x41000000);
13512 insn
^= 0x00010000;
13516 /* bltz 0x04000000 bgez 0x04010000
13517 bltzal 0x04100000 bgezal 0x04110000 */
13518 assert ((insn
& 0xfc0e0000) == 0x04000000);
13519 insn
^= 0x00010000;
13523 /* beq 0x10000000 bne 0x14000000
13524 blez 0x18000000 bgtz 0x1c000000 */
13525 insn
^= 0x04000000;
13533 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13535 /* Clear the and-link bit. */
13536 assert ((insn
& 0xfc1c0000) == 0x04100000);
13538 /* bltzal 0x04100000 bgezal 0x04110000
13539 bltzall 0x04120000 bgezall 0x04130000 */
13540 insn
&= ~0x00100000;
13543 /* Branch over the branch (if the branch was likely) or the
13544 full jump (not likely case). Compute the offset from the
13545 current instruction to branch to. */
13546 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13550 /* How many bytes in instructions we've already emitted? */
13551 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13552 /* How many bytes in instructions from here to the end? */
13553 i
= fragp
->fr_var
- i
;
13555 /* Convert to instruction count. */
13557 /* Branch counts from the next instruction. */
13560 /* Branch over the jump. */
13561 md_number_to_chars ((char *) buf
, insn
, 4);
13565 md_number_to_chars ((char *) buf
, 0, 4);
13568 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13570 /* beql $0, $0, 2f */
13572 /* Compute the PC offset from the current instruction to
13573 the end of the variable frag. */
13574 /* How many bytes in instructions we've already emitted? */
13575 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13576 /* How many bytes in instructions from here to the end? */
13577 i
= fragp
->fr_var
- i
;
13578 /* Convert to instruction count. */
13580 /* Don't decrement i, because we want to branch over the
13584 md_number_to_chars ((char *) buf
, insn
, 4);
13587 md_number_to_chars ((char *) buf
, 0, 4);
13592 if (mips_pic
== NO_PIC
)
13595 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13596 ? 0x0c000000 : 0x08000000);
13597 exp
.X_op
= O_symbol
;
13598 exp
.X_add_symbol
= fragp
->fr_symbol
;
13599 exp
.X_add_number
= fragp
->fr_offset
;
13601 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13602 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13603 fixp
->fx_file
= fragp
->fr_file
;
13604 fixp
->fx_line
= fragp
->fr_line
;
13606 md_number_to_chars ((char *) buf
, insn
, 4);
13611 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13612 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13613 exp
.X_op
= O_symbol
;
13614 exp
.X_add_symbol
= fragp
->fr_symbol
;
13615 exp
.X_add_number
= fragp
->fr_offset
;
13617 if (fragp
->fr_offset
)
13619 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13620 exp
.X_add_number
= 0;
13623 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13624 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13625 fixp
->fx_file
= fragp
->fr_file
;
13626 fixp
->fx_line
= fragp
->fr_line
;
13628 md_number_to_chars ((char *) buf
, insn
, 4);
13631 if (mips_opts
.isa
== ISA_MIPS1
)
13634 md_number_to_chars ((char *) buf
, 0, 4);
13638 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13639 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13641 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13642 4, &exp
, 0, BFD_RELOC_LO16
);
13643 fixp
->fx_file
= fragp
->fr_file
;
13644 fixp
->fx_line
= fragp
->fr_line
;
13646 md_number_to_chars ((char *) buf
, insn
, 4);
13650 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13655 md_number_to_chars ((char *) buf
, insn
, 4);
13660 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13661 + fragp
->fr_fix
+ fragp
->fr_var
);
13663 fragp
->fr_fix
+= fragp
->fr_var
;
13668 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13671 register const struct mips16_immed_operand
*op
;
13672 bfd_boolean small
, ext
;
13675 unsigned long insn
;
13676 bfd_boolean use_extend
;
13677 unsigned short extend
;
13679 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13680 op
= mips16_immed_operands
;
13681 while (op
->type
!= type
)
13684 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13695 resolve_symbol_value (fragp
->fr_symbol
);
13696 val
= S_GET_VALUE (fragp
->fr_symbol
);
13701 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13703 /* The rules for the base address of a PC relative reloc are
13704 complicated; see mips16_extended_frag. */
13705 if (type
== 'p' || type
== 'q')
13710 /* Ignore the low bit in the target, since it will be
13711 set for a text label. */
13712 if ((val
& 1) != 0)
13715 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13717 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13720 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13723 /* Make sure the section winds up with the alignment we have
13726 record_alignment (asec
, op
->shift
);
13730 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13731 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13732 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13733 _("extended instruction in delay slot"));
13735 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13737 if (target_big_endian
)
13738 insn
= bfd_getb16 (buf
);
13740 insn
= bfd_getl16 (buf
);
13742 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13743 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13744 small
, ext
, &insn
, &use_extend
, &extend
);
13748 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13749 fragp
->fr_fix
+= 2;
13753 md_number_to_chars ((char *) buf
, insn
, 2);
13754 fragp
->fr_fix
+= 2;
13762 first
= RELAX_FIRST (fragp
->fr_subtype
);
13763 second
= RELAX_SECOND (fragp
->fr_subtype
);
13764 fixp
= (fixS
*) fragp
->fr_opcode
;
13766 /* Possibly emit a warning if we've chosen the longer option. */
13767 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13768 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13770 const char *msg
= macro_warning (fragp
->fr_subtype
);
13772 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13775 /* Go through all the fixups for the first sequence. Disable them
13776 (by marking them as done) if we're going to use the second
13777 sequence instead. */
13779 && fixp
->fx_frag
== fragp
13780 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13782 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13784 fixp
= fixp
->fx_next
;
13787 /* Go through the fixups for the second sequence. Disable them if
13788 we're going to use the first sequence, otherwise adjust their
13789 addresses to account for the relaxation. */
13790 while (fixp
&& fixp
->fx_frag
== fragp
)
13792 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13793 fixp
->fx_where
-= first
;
13796 fixp
= fixp
->fx_next
;
13799 /* Now modify the frag contents. */
13800 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13804 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13805 memmove (start
, start
+ first
, second
);
13806 fragp
->fr_fix
-= first
;
13809 fragp
->fr_fix
-= second
;
13815 /* This function is called after the relocs have been generated.
13816 We've been storing mips16 text labels as odd. Here we convert them
13817 back to even for the convenience of the debugger. */
13820 mips_frob_file_after_relocs (void)
13823 unsigned int count
, i
;
13825 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13828 syms
= bfd_get_outsymbols (stdoutput
);
13829 count
= bfd_get_symcount (stdoutput
);
13830 for (i
= 0; i
< count
; i
++, syms
++)
13832 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13833 && ((*syms
)->value
& 1) != 0)
13835 (*syms
)->value
&= ~1;
13836 /* If the symbol has an odd size, it was probably computed
13837 incorrectly, so adjust that as well. */
13838 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13839 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13846 /* This function is called whenever a label is defined. It is used
13847 when handling branch delays; if a branch has a label, we assume we
13848 can not move it. */
13851 mips_define_label (symbolS
*sym
)
13853 struct insn_label_list
*l
;
13855 if (free_insn_labels
== NULL
)
13856 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13859 l
= free_insn_labels
;
13860 free_insn_labels
= l
->next
;
13864 l
->next
= insn_labels
;
13868 dwarf2_emit_label (sym
);
13872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13874 /* Some special processing for a MIPS ELF file. */
13877 mips_elf_final_processing (void)
13879 /* Write out the register information. */
13880 if (mips_abi
!= N64_ABI
)
13884 s
.ri_gprmask
= mips_gprmask
;
13885 s
.ri_cprmask
[0] = mips_cprmask
[0];
13886 s
.ri_cprmask
[1] = mips_cprmask
[1];
13887 s
.ri_cprmask
[2] = mips_cprmask
[2];
13888 s
.ri_cprmask
[3] = mips_cprmask
[3];
13889 /* The gp_value field is set by the MIPS ELF backend. */
13891 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13892 ((Elf32_External_RegInfo
*)
13893 mips_regmask_frag
));
13897 Elf64_Internal_RegInfo s
;
13899 s
.ri_gprmask
= mips_gprmask
;
13901 s
.ri_cprmask
[0] = mips_cprmask
[0];
13902 s
.ri_cprmask
[1] = mips_cprmask
[1];
13903 s
.ri_cprmask
[2] = mips_cprmask
[2];
13904 s
.ri_cprmask
[3] = mips_cprmask
[3];
13905 /* The gp_value field is set by the MIPS ELF backend. */
13907 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13908 ((Elf64_External_RegInfo
*)
13909 mips_regmask_frag
));
13912 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13913 sort of BFD interface for this. */
13914 if (mips_any_noreorder
)
13915 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13916 if (mips_pic
!= NO_PIC
)
13918 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13919 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13922 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13924 /* Set MIPS ELF flags for ASEs. */
13925 /* We may need to define a new flag for DSP ASE, and set this flag when
13926 file_ase_dsp is true. */
13927 /* We may need to define a new flag for MT ASE, and set this flag when
13928 file_ase_mt is true. */
13929 if (file_ase_mips16
)
13930 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13931 #if 0 /* XXX FIXME */
13932 if (file_ase_mips3d
)
13933 elf_elfheader (stdoutput
)->e_flags
|= ???;
13936 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13938 /* Set the MIPS ELF ABI flags. */
13939 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13940 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13941 else if (mips_abi
== O64_ABI
)
13942 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13943 else if (mips_abi
== EABI_ABI
)
13945 if (!file_mips_gp32
)
13946 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13948 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13950 else if (mips_abi
== N32_ABI
)
13951 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13953 /* Nothing to do for N64_ABI. */
13955 if (mips_32bitmode
)
13956 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13959 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13961 typedef struct proc
{
13963 symbolS
*func_end_sym
;
13964 unsigned long reg_mask
;
13965 unsigned long reg_offset
;
13966 unsigned long fpreg_mask
;
13967 unsigned long fpreg_offset
;
13968 unsigned long frame_offset
;
13969 unsigned long frame_reg
;
13970 unsigned long pc_reg
;
13973 static procS cur_proc
;
13974 static procS
*cur_proc_ptr
;
13975 static int numprocs
;
13977 /* Fill in an rs_align_code fragment. */
13980 mips_handle_align (fragS
*fragp
)
13982 if (fragp
->fr_type
!= rs_align_code
)
13985 if (mips_opts
.mips16
)
13987 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13988 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13993 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13994 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14002 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14006 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14010 md_obj_begin (void)
14017 /* check for premature end, nesting errors, etc */
14019 as_warn (_("missing .end at end of assembly"));
14028 if (*input_line_pointer
== '-')
14030 ++input_line_pointer
;
14033 if (!ISDIGIT (*input_line_pointer
))
14034 as_bad (_("expected simple number"));
14035 if (input_line_pointer
[0] == '0')
14037 if (input_line_pointer
[1] == 'x')
14039 input_line_pointer
+= 2;
14040 while (ISXDIGIT (*input_line_pointer
))
14043 val
|= hex_value (*input_line_pointer
++);
14045 return negative
? -val
: val
;
14049 ++input_line_pointer
;
14050 while (ISDIGIT (*input_line_pointer
))
14053 val
|= *input_line_pointer
++ - '0';
14055 return negative
? -val
: val
;
14058 if (!ISDIGIT (*input_line_pointer
))
14060 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14061 *input_line_pointer
, *input_line_pointer
);
14062 as_warn (_("invalid number"));
14065 while (ISDIGIT (*input_line_pointer
))
14068 val
+= *input_line_pointer
++ - '0';
14070 return negative
? -val
: val
;
14073 /* The .file directive; just like the usual .file directive, but there
14074 is an initial number which is the ECOFF file index. In the non-ECOFF
14075 case .file implies DWARF-2. */
14078 s_mips_file (int x ATTRIBUTE_UNUSED
)
14080 static int first_file_directive
= 0;
14082 if (ECOFF_DEBUGGING
)
14091 filename
= dwarf2_directive_file (0);
14093 /* Versions of GCC up to 3.1 start files with a ".file"
14094 directive even for stabs output. Make sure that this
14095 ".file" is handled. Note that you need a version of GCC
14096 after 3.1 in order to support DWARF-2 on MIPS. */
14097 if (filename
!= NULL
&& ! first_file_directive
)
14099 (void) new_logical_line (filename
, -1);
14100 s_app_file_string (filename
, 0);
14102 first_file_directive
= 1;
14106 /* The .loc directive, implying DWARF-2. */
14109 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14111 if (!ECOFF_DEBUGGING
)
14112 dwarf2_directive_loc (0);
14115 /* The .end directive. */
14118 s_mips_end (int x ATTRIBUTE_UNUSED
)
14122 /* Following functions need their own .frame and .cprestore directives. */
14123 mips_frame_reg_valid
= 0;
14124 mips_cprestore_valid
= 0;
14126 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14129 demand_empty_rest_of_line ();
14134 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14135 as_warn (_(".end not in text section"));
14139 as_warn (_(".end directive without a preceding .ent directive."));
14140 demand_empty_rest_of_line ();
14146 assert (S_GET_NAME (p
));
14147 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14148 as_warn (_(".end symbol does not match .ent symbol."));
14150 if (debug_type
== DEBUG_STABS
)
14151 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14155 as_warn (_(".end directive missing or unknown symbol"));
14158 /* Create an expression to calculate the size of the function. */
14159 if (p
&& cur_proc_ptr
)
14161 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14162 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14165 exp
->X_op
= O_subtract
;
14166 exp
->X_add_symbol
= symbol_temp_new_now ();
14167 exp
->X_op_symbol
= p
;
14168 exp
->X_add_number
= 0;
14170 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14173 /* Generate a .pdr section. */
14174 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
14177 segT saved_seg
= now_seg
;
14178 subsegT saved_subseg
= now_subseg
;
14183 dot
= frag_now_fix ();
14185 #ifdef md_flush_pending_output
14186 md_flush_pending_output ();
14190 subseg_set (pdr_seg
, 0);
14192 /* Write the symbol. */
14193 exp
.X_op
= O_symbol
;
14194 exp
.X_add_symbol
= p
;
14195 exp
.X_add_number
= 0;
14196 emit_expr (&exp
, 4);
14198 fragp
= frag_more (7 * 4);
14200 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14201 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14202 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14203 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14204 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14205 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14206 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14208 subseg_set (saved_seg
, saved_subseg
);
14210 #endif /* OBJ_ELF */
14212 cur_proc_ptr
= NULL
;
14215 /* The .aent and .ent directives. */
14218 s_mips_ent (int aent
)
14222 symbolP
= get_symbol ();
14223 if (*input_line_pointer
== ',')
14224 ++input_line_pointer
;
14225 SKIP_WHITESPACE ();
14226 if (ISDIGIT (*input_line_pointer
)
14227 || *input_line_pointer
== '-')
14230 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14231 as_warn (_(".ent or .aent not in text section."));
14233 if (!aent
&& cur_proc_ptr
)
14234 as_warn (_("missing .end"));
14238 /* This function needs its own .frame and .cprestore directives. */
14239 mips_frame_reg_valid
= 0;
14240 mips_cprestore_valid
= 0;
14242 cur_proc_ptr
= &cur_proc
;
14243 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14245 cur_proc_ptr
->func_sym
= symbolP
;
14247 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14251 if (debug_type
== DEBUG_STABS
)
14252 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14253 S_GET_NAME (symbolP
));
14256 demand_empty_rest_of_line ();
14259 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14260 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14261 s_mips_frame is used so that we can set the PDR information correctly.
14262 We can't use the ecoff routines because they make reference to the ecoff
14263 symbol table (in the mdebug section). */
14266 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14269 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14273 if (cur_proc_ptr
== (procS
*) NULL
)
14275 as_warn (_(".frame outside of .ent"));
14276 demand_empty_rest_of_line ();
14280 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14282 SKIP_WHITESPACE ();
14283 if (*input_line_pointer
++ != ','
14284 || get_absolute_expression_and_terminator (&val
) != ',')
14286 as_warn (_("Bad .frame directive"));
14287 --input_line_pointer
;
14288 demand_empty_rest_of_line ();
14292 cur_proc_ptr
->frame_offset
= val
;
14293 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14295 demand_empty_rest_of_line ();
14298 #endif /* OBJ_ELF */
14302 /* The .fmask and .mask directives. If the mdebug section is present
14303 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14304 embedded targets, s_mips_mask is used so that we can set the PDR
14305 information correctly. We can't use the ecoff routines because they
14306 make reference to the ecoff symbol table (in the mdebug section). */
14309 s_mips_mask (int reg_type
)
14312 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14316 if (cur_proc_ptr
== (procS
*) NULL
)
14318 as_warn (_(".mask/.fmask outside of .ent"));
14319 demand_empty_rest_of_line ();
14323 if (get_absolute_expression_and_terminator (&mask
) != ',')
14325 as_warn (_("Bad .mask/.fmask directive"));
14326 --input_line_pointer
;
14327 demand_empty_rest_of_line ();
14331 off
= get_absolute_expression ();
14333 if (reg_type
== 'F')
14335 cur_proc_ptr
->fpreg_mask
= mask
;
14336 cur_proc_ptr
->fpreg_offset
= off
;
14340 cur_proc_ptr
->reg_mask
= mask
;
14341 cur_proc_ptr
->reg_offset
= off
;
14344 demand_empty_rest_of_line ();
14347 #endif /* OBJ_ELF */
14348 s_ignore (reg_type
);
14351 /* A table describing all the processors gas knows about. Names are
14352 matched in the order listed.
14354 To ease comparison, please keep this table in the same order as
14355 gcc's mips_cpu_info_table[]. */
14356 static const struct mips_cpu_info mips_cpu_info_table
[] =
14358 /* Entries for generic ISAs */
14359 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14360 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14361 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14362 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14363 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14364 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14365 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14366 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14367 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
14370 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14371 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14372 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14375 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14378 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14379 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14380 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14381 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14382 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14383 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14384 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14385 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14386 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14387 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14388 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14389 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14392 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14393 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14394 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14395 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14396 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14397 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14398 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14399 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14400 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14401 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14402 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14403 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14404 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14407 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14408 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14409 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14411 /* MIPS32 Release 2 */
14412 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14413 { "24k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14414 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14415 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14416 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14419 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14420 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14421 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14423 /* Broadcom SB-1 CPU core */
14424 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14431 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14432 with a final "000" replaced by "k". Ignore case.
14434 Note: this function is shared between GCC and GAS. */
14437 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14439 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14440 given
++, canonical
++;
14442 return ((*given
== 0 && *canonical
== 0)
14443 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14447 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14448 CPU name. We've traditionally allowed a lot of variation here.
14450 Note: this function is shared between GCC and GAS. */
14453 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14455 /* First see if the name matches exactly, or with a final "000"
14456 turned into "k". */
14457 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14460 /* If not, try comparing based on numerical designation alone.
14461 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14462 if (TOLOWER (*given
) == 'r')
14464 if (!ISDIGIT (*given
))
14467 /* Skip over some well-known prefixes in the canonical name,
14468 hoping to find a number there too. */
14469 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14471 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14473 else if (TOLOWER (canonical
[0]) == 'r')
14476 return mips_strict_matching_cpu_name_p (canonical
, given
);
14480 /* Parse an option that takes the name of a processor as its argument.
14481 OPTION is the name of the option and CPU_STRING is the argument.
14482 Return the corresponding processor enumeration if the CPU_STRING is
14483 recognized, otherwise report an error and return null.
14485 A similar function exists in GCC. */
14487 static const struct mips_cpu_info
*
14488 mips_parse_cpu (const char *option
, const char *cpu_string
)
14490 const struct mips_cpu_info
*p
;
14492 /* 'from-abi' selects the most compatible architecture for the given
14493 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14494 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14495 version. Look first at the -mgp options, if given, otherwise base
14496 the choice on MIPS_DEFAULT_64BIT.
14498 Treat NO_ABI like the EABIs. One reason to do this is that the
14499 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14500 architecture. This code picks MIPS I for 'mips' and MIPS III for
14501 'mips64', just as we did in the days before 'from-abi'. */
14502 if (strcasecmp (cpu_string
, "from-abi") == 0)
14504 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14505 return mips_cpu_info_from_isa (ISA_MIPS1
);
14507 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14508 return mips_cpu_info_from_isa (ISA_MIPS3
);
14510 if (file_mips_gp32
>= 0)
14511 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14513 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14518 /* 'default' has traditionally been a no-op. Probably not very useful. */
14519 if (strcasecmp (cpu_string
, "default") == 0)
14522 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14523 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14526 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14530 /* Return the canonical processor information for ISA (a member of the
14531 ISA_MIPS* enumeration). */
14533 static const struct mips_cpu_info
*
14534 mips_cpu_info_from_isa (int isa
)
14538 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14539 if (mips_cpu_info_table
[i
].is_isa
14540 && isa
== mips_cpu_info_table
[i
].isa
)
14541 return (&mips_cpu_info_table
[i
]);
14546 static const struct mips_cpu_info
*
14547 mips_cpu_info_from_arch (int arch
)
14551 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14552 if (arch
== mips_cpu_info_table
[i
].cpu
)
14553 return (&mips_cpu_info_table
[i
]);
14559 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14563 fprintf (stream
, "%24s", "");
14568 fprintf (stream
, ", ");
14572 if (*col_p
+ strlen (string
) > 72)
14574 fprintf (stream
, "\n%24s", "");
14578 fprintf (stream
, "%s", string
);
14579 *col_p
+= strlen (string
);
14585 md_show_usage (FILE *stream
)
14590 fprintf (stream
, _("\
14592 -EB generate big endian output\n\
14593 -EL generate little endian output\n\
14594 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14595 -G NUM allow referencing objects up to NUM bytes\n\
14596 implicitly with the gp register [default 8]\n"));
14597 fprintf (stream
, _("\
14598 -mips1 generate MIPS ISA I instructions\n\
14599 -mips2 generate MIPS ISA II instructions\n\
14600 -mips3 generate MIPS ISA III instructions\n\
14601 -mips4 generate MIPS ISA IV instructions\n\
14602 -mips5 generate MIPS ISA V instructions\n\
14603 -mips32 generate MIPS32 ISA instructions\n\
14604 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14605 -mips64 generate MIPS64 ISA instructions\n\
14606 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14607 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14611 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14612 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14613 show (stream
, "from-abi", &column
, &first
);
14614 fputc ('\n', stream
);
14616 fprintf (stream
, _("\
14617 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14618 -no-mCPU don't generate code specific to CPU.\n\
14619 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14623 show (stream
, "3900", &column
, &first
);
14624 show (stream
, "4010", &column
, &first
);
14625 show (stream
, "4100", &column
, &first
);
14626 show (stream
, "4650", &column
, &first
);
14627 fputc ('\n', stream
);
14629 fprintf (stream
, _("\
14630 -mips16 generate mips16 instructions\n\
14631 -no-mips16 do not generate mips16 instructions\n"));
14632 fprintf (stream
, _("\
14633 -msmartmips generate smartmips instructions\n\
14634 -mno-smartmips do not generate smartmips instructions\n"));
14635 fprintf (stream
, _("\
14636 -mdsp generate DSP instructions\n\
14637 -mno-dsp do not generate DSP instructions\n"));
14638 fprintf (stream
, _("\
14639 -mmt generate MT instructions\n\
14640 -mno-mt do not generate MT instructions\n"));
14641 fprintf (stream
, _("\
14642 -mfix-vr4120 work around certain VR4120 errata\n\
14643 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14644 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14645 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14646 -mno-shared optimize output for executables\n\
14647 -msym32 assume all symbols have 32-bit values\n\
14648 -O0 remove unneeded NOPs, do not swap branches\n\
14649 -O remove unneeded NOPs and swap branches\n\
14650 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14651 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14652 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14654 fprintf (stream
, _("\
14655 -KPIC, -call_shared generate SVR4 position independent code\n\
14656 -non_shared do not generate position independent code\n\
14657 -xgot assume a 32 bit GOT\n\
14658 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14659 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14661 -mabi=ABI create ABI conformant object file for:\n"));
14665 show (stream
, "32", &column
, &first
);
14666 show (stream
, "o64", &column
, &first
);
14667 show (stream
, "n32", &column
, &first
);
14668 show (stream
, "64", &column
, &first
);
14669 show (stream
, "eabi", &column
, &first
);
14671 fputc ('\n', stream
);
14673 fprintf (stream
, _("\
14674 -32 create o32 ABI object file (default)\n\
14675 -n32 create n32 ABI object file\n\
14676 -64 create 64 ABI object file\n"));
14681 mips_dwarf2_format (void)
14683 if (mips_abi
== N64_ABI
)
14686 return dwarf2_format_64bit_irix
;
14688 return dwarf2_format_64bit
;
14692 return dwarf2_format_32bit
;
14696 mips_dwarf2_addr_size (void)
14698 if (mips_abi
== N64_ABI
)
14704 /* Standard calling conventions leave the CFA at SP on entry. */
14706 mips_cfi_frame_initial_instructions (void)
14708 cfi_add_CFA_def_cfa_register (SP
);