1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 /* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635 enum mips_insn_error_format
{
641 /* Information about an error that was found while assembling the current
643 struct mips_insn_error
{
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format
;
668 /* The error that should be reported for the current instruction. */
669 static struct mips_insn_error insn_error
;
671 static int auto_align
= 1;
673 /* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
677 static offsetT mips_cprestore_offset
= -1;
679 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
680 more optimizations, it can use a register value instead of a memory-saved
681 offset and even an other register than $gp as global pointer. */
682 static offsetT mips_cpreturn_offset
= -1;
683 static int mips_cpreturn_register
= -1;
684 static int mips_gp_register
= GP
;
685 static int mips_gprel_offset
= 0;
687 /* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689 static int mips_cprestore_valid
= 0;
691 /* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693 static int mips_frame_reg
= SP
;
695 /* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_frame_reg_valid
= 0;
699 /* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
702 /* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
706 static int mips_optimize
= 2;
708 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710 static int mips_debug
= 0;
712 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713 #define MAX_VR4130_NOPS 4
715 /* The maximum number of NOPs needed to fill delay slots. */
716 #define MAX_DELAY_NOPS 2
718 /* The maximum number of NOPs needed for any purpose. */
721 /* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726 static struct mips_cl_insn history
[1 + MAX_NOPS
];
728 /* Arrays of operands for each instruction. */
729 #define MAX_OPERANDS 6
730 struct mips_operand_array
{
731 const struct mips_operand
*operand
[MAX_OPERANDS
];
733 static struct mips_operand_array
*mips_operands
;
734 static struct mips_operand_array
*mips16_operands
;
735 static struct mips_operand_array
*micromips_operands
;
737 /* Nop instructions used by emit_nop. */
738 static struct mips_cl_insn nop_insn
;
739 static struct mips_cl_insn mips16_nop_insn
;
740 static struct mips_cl_insn micromips_nop16_insn
;
741 static struct mips_cl_insn micromips_nop32_insn
;
743 /* The appropriate nop for the current mode. */
744 #define NOP_INSN (mips_opts.mips16 \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? µmips_nop32_insn \
749 : µmips_nop16_insn) \
752 /* The size of NOP_INSN in bytes. */
753 #define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
757 /* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
761 static fragS
*prev_nop_frag
;
763 /* The number of nop instructions we created in prev_nop_frag. */
764 static int prev_nop_frag_holds
;
766 /* The number of nop instructions that we know we need in
768 static int prev_nop_frag_required
;
770 /* The number of instructions we've seen since prev_nop_frag. */
771 static int prev_nop_frag_since
;
773 /* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
782 corresponding LO relocation. */
787 struct mips_hi_fixup
*next
;
790 /* The section this fixup is in. */
794 /* The list of unmatched HI relocs. */
796 static struct mips_hi_fixup
*mips_hi_fixup_list
;
798 /* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
801 static fragS
*prev_reloc_op_frag
;
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map
[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map microMIPS register numbers to normal MIPS register numbers. */
812 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
814 /* The microMIPS registers with type h. */
815 static const unsigned int micromips_to_32_reg_h_map1
[] =
817 5, 5, 6, 4, 4, 4, 4, 4
819 static const unsigned int micromips_to_32_reg_h_map2
[] =
821 6, 7, 7, 21, 22, 5, 6, 7
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map
[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
834 enum fix_vr4120_class
842 NUM_FIX_VR4120_CLASSES
845 /* ...likewise -mfix-loongson2f-jump. */
846 static bfd_boolean mips_fix_loongson2f_jump
;
848 /* ...likewise -mfix-loongson2f-nop. */
849 static bfd_boolean mips_fix_loongson2f_nop
;
851 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852 static bfd_boolean mips_fix_loongson2f
;
854 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
859 /* True if -mfix-vr4120 is in force. */
860 static int mips_fix_vr4120
;
862 /* ...likewise -mfix-vr4130. */
863 static int mips_fix_vr4130
;
865 /* ...likewise -mfix-24k. */
866 static int mips_fix_24k
;
868 /* ...likewise -mfix-cn63xxp1 */
869 static bfd_boolean mips_fix_cn63xxp1
;
871 /* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
876 static int mips_relax_branch
;
878 /* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
925 The frag's "opcode" points to the first fixup for relaxable code.
927 Relaxable macros are generated using a sequence such as:
929 relax_start (SYMBOL);
930 ... generate first expansion ...
932 ... generate second expansion ...
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
937 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
939 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940 #define RELAX_SECOND(X) ((X) & 0xff)
941 #define RELAX_USE_SECOND 0x10000
942 #define RELAX_SECOND_LONGER 0x20000
943 #define RELAX_NOMACRO 0x40000
944 #define RELAX_DELAY_SLOT 0x80000
945 #define RELAX_DELAY_SLOT_16BIT 0x100000
946 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
949 /* Branch without likely bit. If label is out of range, we turn:
951 beq reg1, reg2, label
961 with the following opcode replacements:
968 bltzal <-> bgezal (with jal label instead of j label)
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
978 Branch likely. If label is out of range, we turn:
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
990 delay slot (executed only if branch taken)
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
999 delay slot (executed only if branch taken)
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1015 but it's not clear that it would actually improve performance. */
1016 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
1024 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1025 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1031 /* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
1058 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1059 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1071 /* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
1102 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1105 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1110 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1117 /* Sign-extend 16-bit value X. */
1118 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1120 /* Is the given value a sign-extended 32-bit value? */
1121 #define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1125 /* Is the given value a sign-extended 16-bit value? */
1126 #define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1130 /* Is the given value a sign-extended 12-bit value? */
1131 #define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1134 /* Is the given value a sign-extended 9-bit value? */
1135 #define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1138 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139 #define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1143 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1145 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1148 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1149 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1154 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
1159 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160 #define MIPS16_EXTEND (0xf000U << 16)
1162 /* Whether or not we are emitting a branch-likely macro. */
1163 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1165 /* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes
[2];
1182 /* The symbol on which the choice of sequence depends. */
1186 /* Global variables used to decide whether a macro needs a warning. */
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p
;
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length
;
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1199 unsigned int sizes
[2];
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes
[2];
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns
[2];
1218 /* The first variant frag for this macro. */
1220 } mips_macro_warning
;
1222 /* Prototypes for static functions. */
1224 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1226 static void append_insn
1227 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1228 bfd_boolean expansionp
);
1229 static void mips_no_prev_insn (void);
1230 static void macro_build (expressionS
*, const char *, const char *, ...);
1231 static void mips16_macro_build
1232 (expressionS
*, const char *, const char *, va_list *);
1233 static void load_register (int, expressionS
*, int);
1234 static void macro_start (void);
1235 static void macro_end (void);
1236 static void macro (struct mips_cl_insn
*ip
, char *str
);
1237 static void mips16_macro (struct mips_cl_insn
* ip
);
1238 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1239 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1240 static void mips16_immed
1241 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1242 unsigned int, unsigned long *);
1243 static size_t my_getSmallExpression
1244 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1245 static void my_getExpression (expressionS
*, char *);
1246 static void s_align (int);
1247 static void s_change_sec (int);
1248 static void s_change_section (int);
1249 static void s_cons (int);
1250 static void s_float_cons (int);
1251 static void s_mips_globl (int);
1252 static void s_option (int);
1253 static void s_mipsset (int);
1254 static void s_abicalls (int);
1255 static void s_cpload (int);
1256 static void s_cpsetup (int);
1257 static void s_cplocal (int);
1258 static void s_cprestore (int);
1259 static void s_cpreturn (int);
1260 static void s_dtprelword (int);
1261 static void s_dtpreldword (int);
1262 static void s_tprelword (int);
1263 static void s_tpreldword (int);
1264 static void s_gpvalue (int);
1265 static void s_gpword (int);
1266 static void s_gpdword (int);
1267 static void s_ehword (int);
1268 static void s_cpadd (int);
1269 static void s_insn (int);
1270 static void s_nan (int);
1271 static void md_obj_begin (void);
1272 static void md_obj_end (void);
1273 static void s_mips_ent (int);
1274 static void s_mips_end (int);
1275 static void s_mips_frame (int);
1276 static void s_mips_mask (int reg_type
);
1277 static void s_mips_stab (int);
1278 static void s_mips_weakext (int);
1279 static void s_mips_file (int);
1280 static void s_mips_loc (int);
1281 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1282 static int relaxed_branch_length (fragS
*, asection
*, int);
1283 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1284 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1286 /* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1289 struct mips_cpu_info
1291 const char *name
; /* CPU or ISA name. */
1292 int flags
; /* MIPS_CPU_* flags. */
1293 int ase
; /* Set of ASEs implemented by the CPU. */
1294 int isa
; /* ISA level. */
1295 int cpu
; /* CPU number (default CPU if ISA). */
1298 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1300 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1301 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1302 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1304 /* Command-line options. */
1305 const char *md_shortopts
= "O::g::G:";
1309 OPTION_MARCH
= OPTION_MD_BASE
,
1335 OPTION_NO_SMARTMIPS
,
1341 OPTION_NO_MICROMIPS
,
1344 OPTION_COMPAT_ARCH_BASE
,
1353 OPTION_M7000_HILO_FIX
,
1354 OPTION_MNO_7000_HILO_FIX
,
1357 OPTION_FIX_LOONGSON2F_JUMP
,
1358 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1359 OPTION_FIX_LOONGSON2F_NOP
,
1360 OPTION_NO_FIX_LOONGSON2F_NOP
,
1362 OPTION_NO_FIX_VR4120
,
1364 OPTION_NO_FIX_VR4130
,
1365 OPTION_FIX_CN63XXP1
,
1366 OPTION_NO_FIX_CN63XXP1
,
1373 OPTION_CONSTRUCT_FLOATS
,
1374 OPTION_NO_CONSTRUCT_FLOATS
,
1377 OPTION_RELAX_BRANCH
,
1378 OPTION_NO_RELAX_BRANCH
,
1387 OPTION_SINGLE_FLOAT
,
1388 OPTION_DOUBLE_FLOAT
,
1401 OPTION_MVXWORKS_PIC
,
1406 struct option md_longopts
[] =
1408 /* Options which specify architecture. */
1409 {"march", required_argument
, NULL
, OPTION_MARCH
},
1410 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1411 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1412 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1413 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1414 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1415 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1416 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1417 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1418 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1419 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1420 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1422 /* Options which specify Application Specific Extensions (ASEs). */
1423 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1424 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1425 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1426 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1427 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1428 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1429 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1430 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1431 {"mmt", no_argument
, NULL
, OPTION_MT
},
1432 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1433 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1434 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1435 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1436 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1437 {"meva", no_argument
, NULL
, OPTION_EVA
},
1438 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1439 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1440 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1441 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1442 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1443 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1444 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1445 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1446 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1448 /* Old-style architecture options. Don't add more of these. */
1449 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1450 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1451 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1452 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1453 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1454 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1455 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1456 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1458 /* Options which enable bug fixes. */
1459 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1460 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1461 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1462 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1463 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1464 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1465 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1466 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1467 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1468 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1469 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1470 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1471 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1472 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1473 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1475 /* Miscellaneous options. */
1476 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1477 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1478 {"break", no_argument
, NULL
, OPTION_BREAK
},
1479 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1480 {"EB", no_argument
, NULL
, OPTION_EB
},
1481 {"EL", no_argument
, NULL
, OPTION_EL
},
1482 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1483 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1484 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1485 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1486 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1487 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1488 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1489 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1490 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1491 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1492 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1493 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1494 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1495 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1496 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1497 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1498 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1499 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1501 /* Strictly speaking this next option is ELF specific,
1502 but we allow it for other ports as well in order to
1503 make testing easier. */
1504 {"32", no_argument
, NULL
, OPTION_32
},
1506 /* ELF-specific options. */
1507 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1508 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1509 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1510 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1511 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1512 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1513 {"n32", no_argument
, NULL
, OPTION_N32
},
1514 {"64", no_argument
, NULL
, OPTION_64
},
1515 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1516 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1517 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1518 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1519 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1520 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1522 {NULL
, no_argument
, NULL
, 0}
1524 size_t md_longopts_size
= sizeof (md_longopts
);
1526 /* Information about either an Application Specific Extension or an
1527 optional architecture feature that, for simplicity, we treat in the
1528 same way as an ASE. */
1531 /* The name of the ASE, used in both the command-line and .set options. */
1534 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1535 and 64-bit architectures, the flags here refer to the subset that
1536 is available on both. */
1539 /* The ASE_* flag used for instructions that are available on 64-bit
1540 architectures but that are not included in FLAGS. */
1541 unsigned int flags64
;
1543 /* The command-line options that turn the ASE on and off. */
1547 /* The minimum required architecture revisions for MIPS32, MIPS64,
1548 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1551 int micromips32_rev
;
1552 int micromips64_rev
;
1555 /* A table of all supported ASEs. */
1556 static const struct mips_ase mips_ases
[] = {
1557 { "dsp", ASE_DSP
, ASE_DSP64
,
1558 OPTION_DSP
, OPTION_NO_DSP
,
1561 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1562 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1565 { "eva", ASE_EVA
, 0,
1566 OPTION_EVA
, OPTION_NO_EVA
,
1569 { "mcu", ASE_MCU
, 0,
1570 OPTION_MCU
, OPTION_NO_MCU
,
1573 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1574 { "mdmx", ASE_MDMX
, 0,
1575 OPTION_MDMX
, OPTION_NO_MDMX
,
1578 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1579 { "mips3d", ASE_MIPS3D
, 0,
1580 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1584 OPTION_MT
, OPTION_NO_MT
,
1587 { "smartmips", ASE_SMARTMIPS
, 0,
1588 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1591 { "virt", ASE_VIRT
, ASE_VIRT64
,
1592 OPTION_VIRT
, OPTION_NO_VIRT
,
1595 { "msa", ASE_MSA
, ASE_MSA64
,
1596 OPTION_MSA
, OPTION_NO_MSA
,
1600 /* The set of ASEs that require -mfp64. */
1601 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1603 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1604 static const unsigned int mips_ase_groups
[] = {
1610 The following pseudo-ops from the Kane and Heinrich MIPS book
1611 should be defined here, but are currently unsupported: .alias,
1612 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1614 The following pseudo-ops from the Kane and Heinrich MIPS book are
1615 specific to the type of debugging information being generated, and
1616 should be defined by the object format: .aent, .begin, .bend,
1617 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1620 The following pseudo-ops from the Kane and Heinrich MIPS book are
1621 not MIPS CPU specific, but are also not specific to the object file
1622 format. This file is probably the best place to define them, but
1623 they are not currently supported: .asm0, .endr, .lab, .struct. */
1625 static const pseudo_typeS mips_pseudo_table
[] =
1627 /* MIPS specific pseudo-ops. */
1628 {"option", s_option
, 0},
1629 {"set", s_mipsset
, 0},
1630 {"rdata", s_change_sec
, 'r'},
1631 {"sdata", s_change_sec
, 's'},
1632 {"livereg", s_ignore
, 0},
1633 {"abicalls", s_abicalls
, 0},
1634 {"cpload", s_cpload
, 0},
1635 {"cpsetup", s_cpsetup
, 0},
1636 {"cplocal", s_cplocal
, 0},
1637 {"cprestore", s_cprestore
, 0},
1638 {"cpreturn", s_cpreturn
, 0},
1639 {"dtprelword", s_dtprelword
, 0},
1640 {"dtpreldword", s_dtpreldword
, 0},
1641 {"tprelword", s_tprelword
, 0},
1642 {"tpreldword", s_tpreldword
, 0},
1643 {"gpvalue", s_gpvalue
, 0},
1644 {"gpword", s_gpword
, 0},
1645 {"gpdword", s_gpdword
, 0},
1646 {"ehword", s_ehword
, 0},
1647 {"cpadd", s_cpadd
, 0},
1648 {"insn", s_insn
, 0},
1651 /* Relatively generic pseudo-ops that happen to be used on MIPS
1653 {"asciiz", stringer
, 8 + 1},
1654 {"bss", s_change_sec
, 'b'},
1656 {"half", s_cons
, 1},
1657 {"dword", s_cons
, 3},
1658 {"weakext", s_mips_weakext
, 0},
1659 {"origin", s_org
, 0},
1660 {"repeat", s_rept
, 0},
1662 /* For MIPS this is non-standard, but we define it for consistency. */
1663 {"sbss", s_change_sec
, 'B'},
1665 /* These pseudo-ops are defined in read.c, but must be overridden
1666 here for one reason or another. */
1667 {"align", s_align
, 0},
1668 {"byte", s_cons
, 0},
1669 {"data", s_change_sec
, 'd'},
1670 {"double", s_float_cons
, 'd'},
1671 {"float", s_float_cons
, 'f'},
1672 {"globl", s_mips_globl
, 0},
1673 {"global", s_mips_globl
, 0},
1674 {"hword", s_cons
, 1},
1676 {"long", s_cons
, 2},
1677 {"octa", s_cons
, 4},
1678 {"quad", s_cons
, 3},
1679 {"section", s_change_section
, 0},
1680 {"short", s_cons
, 1},
1681 {"single", s_float_cons
, 'f'},
1682 {"stabd", s_mips_stab
, 'd'},
1683 {"stabn", s_mips_stab
, 'n'},
1684 {"stabs", s_mips_stab
, 's'},
1685 {"text", s_change_sec
, 't'},
1686 {"word", s_cons
, 2},
1688 { "extern", ecoff_directive_extern
, 0},
1693 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1695 /* These pseudo-ops should be defined by the object file format.
1696 However, a.out doesn't support them, so we have versions here. */
1697 {"aent", s_mips_ent
, 1},
1698 {"bgnb", s_ignore
, 0},
1699 {"end", s_mips_end
, 0},
1700 {"endb", s_ignore
, 0},
1701 {"ent", s_mips_ent
, 0},
1702 {"file", s_mips_file
, 0},
1703 {"fmask", s_mips_mask
, 'F'},
1704 {"frame", s_mips_frame
, 0},
1705 {"loc", s_mips_loc
, 0},
1706 {"mask", s_mips_mask
, 'R'},
1707 {"verstamp", s_ignore
, 0},
1711 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1712 purpose of the `.dc.a' internal pseudo-op. */
1715 mips_address_bytes (void)
1717 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1720 extern void pop_insert (const pseudo_typeS
*);
1723 mips_pop_insert (void)
1725 pop_insert (mips_pseudo_table
);
1726 if (! ECOFF_DEBUGGING
)
1727 pop_insert (mips_nonecoff_pseudo_table
);
1730 /* Symbols labelling the current insn. */
1732 struct insn_label_list
1734 struct insn_label_list
*next
;
1738 static struct insn_label_list
*free_insn_labels
;
1739 #define label_list tc_segment_info_data.labels
1741 static void mips_clear_insn_labels (void);
1742 static void mips_mark_labels (void);
1743 static void mips_compressed_mark_labels (void);
1746 mips_clear_insn_labels (void)
1748 register struct insn_label_list
**pl
;
1749 segment_info_type
*si
;
1753 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1756 si
= seg_info (now_seg
);
1757 *pl
= si
->label_list
;
1758 si
->label_list
= NULL
;
1762 /* Mark instruction labels in MIPS16/microMIPS mode. */
1765 mips_mark_labels (void)
1767 if (HAVE_CODE_COMPRESSION
)
1768 mips_compressed_mark_labels ();
1771 static char *expr_end
;
1773 /* An expression in a macro instruction. This is set by mips_ip and
1774 mips16_ip and when populated is always an O_constant. */
1776 static expressionS imm_expr
;
1778 /* The relocatable field in an instruction and the relocs associated
1779 with it. These variables are used for instructions like LUI and
1780 JAL as well as true offsets. They are also used for address
1781 operands in macros. */
1783 static expressionS offset_expr
;
1784 static bfd_reloc_code_real_type offset_reloc
[3]
1785 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1787 /* This is set to the resulting size of the instruction to be produced
1788 by mips16_ip if an explicit extension is used or by mips_ip if an
1789 explicit size is supplied. */
1791 static unsigned int forced_insn_length
;
1793 /* True if we are assembling an instruction. All dot symbols defined during
1794 this time should be treated as code labels. */
1796 static bfd_boolean mips_assembling_insn
;
1798 /* The pdr segment for per procedure frame/regmask info. Not used for
1801 static segT pdr_seg
;
1803 /* The default target format to use. */
1805 #if defined (TE_FreeBSD)
1806 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1807 #elif defined (TE_TMIPS)
1808 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1810 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1814 mips_target_format (void)
1816 switch (OUTPUT_FLAVOR
)
1818 case bfd_target_elf_flavour
:
1820 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1821 return (target_big_endian
1822 ? "elf32-bigmips-vxworks"
1823 : "elf32-littlemips-vxworks");
1825 return (target_big_endian
1826 ? (HAVE_64BIT_OBJECTS
1827 ? ELF_TARGET ("elf64-", "big")
1829 ? ELF_TARGET ("elf32-n", "big")
1830 : ELF_TARGET ("elf32-", "big")))
1831 : (HAVE_64BIT_OBJECTS
1832 ? ELF_TARGET ("elf64-", "little")
1834 ? ELF_TARGET ("elf32-n", "little")
1835 : ELF_TARGET ("elf32-", "little"))));
1842 /* Return the ISA revision that is currently in use, or 0 if we are
1843 generating code for MIPS V or below. */
1848 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1851 /* microMIPS implies revision 2 or above. */
1852 if (mips_opts
.micromips
)
1855 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1861 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1864 mips_ase_mask (unsigned int flags
)
1868 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1869 if (flags
& mips_ase_groups
[i
])
1870 flags
|= mips_ase_groups
[i
];
1874 /* Check whether the current ISA supports ASE. Issue a warning if
1878 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1882 static unsigned int warned_isa
;
1883 static unsigned int warned_fp32
;
1885 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1886 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1888 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1889 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1890 && (warned_isa
& ase
->flags
) != ase
->flags
)
1892 warned_isa
|= ase
->flags
;
1893 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1894 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1896 as_warn (_("the %d-bit %s architecture does not support the"
1897 " `%s' extension"), size
, base
, ase
->name
);
1899 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
1900 ase
->name
, base
, size
, min_rev
);
1902 if ((ase
->flags
& FP64_ASES
)
1904 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1906 warned_fp32
|= ase
->flags
;
1907 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
1911 /* Check all enabled ASEs to see whether they are supported by the
1912 chosen architecture. */
1915 mips_check_isa_supports_ases (void)
1917 unsigned int i
, mask
;
1919 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1921 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1922 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1923 mips_check_isa_supports_ase (&mips_ases
[i
]);
1927 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1928 that were affected. */
1931 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1935 mask
= mips_ase_mask (ase
->flags
);
1936 mips_opts
.ase
&= ~mask
;
1938 mips_opts
.ase
|= ase
->flags
;
1942 /* Return the ASE called NAME, or null if none. */
1944 static const struct mips_ase
*
1945 mips_lookup_ase (const char *name
)
1949 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1950 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1951 return &mips_ases
[i
];
1955 /* Return the length of a microMIPS instruction in bytes. If bits of
1956 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1957 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1958 major opcode) will require further modifications to the opcode
1961 static inline unsigned int
1962 micromips_insn_length (const struct mips_opcode
*mo
)
1964 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1967 /* Return the length of MIPS16 instruction OPCODE. */
1969 static inline unsigned int
1970 mips16_opcode_length (unsigned long opcode
)
1972 return (opcode
>> 16) == 0 ? 2 : 4;
1975 /* Return the length of instruction INSN. */
1977 static inline unsigned int
1978 insn_length (const struct mips_cl_insn
*insn
)
1980 if (mips_opts
.micromips
)
1981 return micromips_insn_length (insn
->insn_mo
);
1982 else if (mips_opts
.mips16
)
1983 return mips16_opcode_length (insn
->insn_opcode
);
1988 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1991 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1996 insn
->insn_opcode
= mo
->match
;
1999 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2000 insn
->fixp
[i
] = NULL
;
2001 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2002 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2003 insn
->mips16_absolute_jump_p
= 0;
2004 insn
->complete_p
= 0;
2005 insn
->cleared_p
= 0;
2008 /* Get a list of all the operands in INSN. */
2010 static const struct mips_operand_array
*
2011 insn_operands (const struct mips_cl_insn
*insn
)
2013 if (insn
->insn_mo
>= &mips_opcodes
[0]
2014 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2015 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2017 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2018 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2019 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2021 if (insn
->insn_mo
>= µmips_opcodes
[0]
2022 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2023 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2028 /* Get a description of operand OPNO of INSN. */
2030 static const struct mips_operand
*
2031 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2033 const struct mips_operand_array
*operands
;
2035 operands
= insn_operands (insn
);
2036 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2038 return operands
->operand
[opno
];
2041 /* Install UVAL as the value of OPERAND in INSN. */
2044 insn_insert_operand (struct mips_cl_insn
*insn
,
2045 const struct mips_operand
*operand
, unsigned int uval
)
2047 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2050 /* Extract the value of OPERAND from INSN. */
2052 static inline unsigned
2053 insn_extract_operand (const struct mips_cl_insn
*insn
,
2054 const struct mips_operand
*operand
)
2056 return mips_extract_operand (operand
, insn
->insn_opcode
);
2059 /* Record the current MIPS16/microMIPS mode in now_seg. */
2062 mips_record_compressed_mode (void)
2064 segment_info_type
*si
;
2066 si
= seg_info (now_seg
);
2067 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2068 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2069 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2070 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2073 /* Read a standard MIPS instruction from BUF. */
2075 static unsigned long
2076 read_insn (char *buf
)
2078 if (target_big_endian
)
2079 return bfd_getb32 ((bfd_byte
*) buf
);
2081 return bfd_getl32 ((bfd_byte
*) buf
);
2084 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2088 write_insn (char *buf
, unsigned int insn
)
2090 md_number_to_chars (buf
, insn
, 4);
2094 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2095 has length LENGTH. */
2097 static unsigned long
2098 read_compressed_insn (char *buf
, unsigned int length
)
2104 for (i
= 0; i
< length
; i
+= 2)
2107 if (target_big_endian
)
2108 insn
|= bfd_getb16 ((char *) buf
);
2110 insn
|= bfd_getl16 ((char *) buf
);
2116 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2117 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2120 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2124 for (i
= 0; i
< length
; i
+= 2)
2125 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2126 return buf
+ length
;
2129 /* Install INSN at the location specified by its "frag" and "where" fields. */
2132 install_insn (const struct mips_cl_insn
*insn
)
2134 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2135 if (HAVE_CODE_COMPRESSION
)
2136 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2138 write_insn (f
, insn
->insn_opcode
);
2139 mips_record_compressed_mode ();
2142 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2143 and install the opcode in the new location. */
2146 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2151 insn
->where
= where
;
2152 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2153 if (insn
->fixp
[i
] != NULL
)
2155 insn
->fixp
[i
]->fx_frag
= frag
;
2156 insn
->fixp
[i
]->fx_where
= where
;
2158 install_insn (insn
);
2161 /* Add INSN to the end of the output. */
2164 add_fixed_insn (struct mips_cl_insn
*insn
)
2166 char *f
= frag_more (insn_length (insn
));
2167 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2170 /* Start a variant frag and move INSN to the start of the variant part,
2171 marking it as fixed. The other arguments are as for frag_var. */
2174 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2175 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2177 frag_grow (max_chars
);
2178 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2180 frag_var (rs_machine_dependent
, max_chars
, var
,
2181 subtype
, symbol
, offset
, NULL
);
2184 /* Insert N copies of INSN into the history buffer, starting at
2185 position FIRST. Neither FIRST nor N need to be clipped. */
2188 insert_into_history (unsigned int first
, unsigned int n
,
2189 const struct mips_cl_insn
*insn
)
2191 if (mips_relax
.sequence
!= 2)
2195 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2197 history
[i
] = history
[i
- n
];
2203 /* Clear the error in insn_error. */
2206 clear_insn_error (void)
2208 memset (&insn_error
, 0, sizeof (insn_error
));
2211 /* Possibly record error message MSG for the current instruction.
2212 If the error is about a particular argument, ARGNUM is the 1-based
2213 number of that argument, otherwise it is 0. FORMAT is the format
2214 of MSG. Return true if MSG was used, false if the current message
2218 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2223 /* Give priority to errors against specific arguments, and to
2224 the first whole-instruction message. */
2230 /* Keep insn_error if it is against a later argument. */
2231 if (argnum
< insn_error
.min_argnum
)
2234 /* If both errors are against the same argument but are different,
2235 give up on reporting a specific error for this argument.
2236 See the comment about mips_insn_error for details. */
2237 if (argnum
== insn_error
.min_argnum
2239 && strcmp (insn_error
.msg
, msg
) != 0)
2242 insn_error
.min_argnum
+= 1;
2246 insn_error
.min_argnum
= argnum
;
2247 insn_error
.format
= format
;
2248 insn_error
.msg
= msg
;
2252 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2253 as for set_insn_error_format. */
2256 set_insn_error (int argnum
, const char *msg
)
2258 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2261 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2262 as for set_insn_error_format. */
2265 set_insn_error_i (int argnum
, const char *msg
, int i
)
2267 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2271 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2272 are as for set_insn_error_format. */
2275 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2277 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2279 insn_error
.u
.ss
[0] = s1
;
2280 insn_error
.u
.ss
[1] = s2
;
2284 /* Report the error in insn_error, which is against assembly code STR. */
2287 report_insn_error (const char *str
)
2291 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2292 switch (insn_error
.format
)
2299 as_bad (msg
, insn_error
.u
.i
, str
);
2303 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2308 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2309 the idea is to make it obvious at a glance that each errata is
2313 init_vr4120_conflicts (void)
2315 #define CONFLICT(FIRST, SECOND) \
2316 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2318 /* Errata 21 - [D]DIV[U] after [D]MACC */
2319 CONFLICT (MACC
, DIV
);
2320 CONFLICT (DMACC
, DIV
);
2322 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2323 CONFLICT (DMULT
, DMULT
);
2324 CONFLICT (DMULT
, DMACC
);
2325 CONFLICT (DMACC
, DMULT
);
2326 CONFLICT (DMACC
, DMACC
);
2328 /* Errata 24 - MT{LO,HI} after [D]MACC */
2329 CONFLICT (MACC
, MTHILO
);
2330 CONFLICT (DMACC
, MTHILO
);
2332 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2333 instruction is executed immediately after a MACC or DMACC
2334 instruction, the result of [either instruction] is incorrect." */
2335 CONFLICT (MACC
, MULT
);
2336 CONFLICT (MACC
, DMULT
);
2337 CONFLICT (DMACC
, MULT
);
2338 CONFLICT (DMACC
, DMULT
);
2340 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2341 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2342 DDIV or DDIVU instruction, the result of the MACC or
2343 DMACC instruction is incorrect.". */
2344 CONFLICT (DMULT
, MACC
);
2345 CONFLICT (DMULT
, DMACC
);
2346 CONFLICT (DIV
, MACC
);
2347 CONFLICT (DIV
, DMACC
);
2357 #define RNUM_MASK 0x00000ff
2358 #define RTYPE_MASK 0x0ffff00
2359 #define RTYPE_NUM 0x0000100
2360 #define RTYPE_FPU 0x0000200
2361 #define RTYPE_FCC 0x0000400
2362 #define RTYPE_VEC 0x0000800
2363 #define RTYPE_GP 0x0001000
2364 #define RTYPE_CP0 0x0002000
2365 #define RTYPE_PC 0x0004000
2366 #define RTYPE_ACC 0x0008000
2367 #define RTYPE_CCC 0x0010000
2368 #define RTYPE_VI 0x0020000
2369 #define RTYPE_VF 0x0040000
2370 #define RTYPE_R5900_I 0x0080000
2371 #define RTYPE_R5900_Q 0x0100000
2372 #define RTYPE_R5900_R 0x0200000
2373 #define RTYPE_R5900_ACC 0x0400000
2374 #define RTYPE_MSA 0x0800000
2375 #define RWARN 0x8000000
2377 #define GENERIC_REGISTER_NUMBERS \
2378 {"$0", RTYPE_NUM | 0}, \
2379 {"$1", RTYPE_NUM | 1}, \
2380 {"$2", RTYPE_NUM | 2}, \
2381 {"$3", RTYPE_NUM | 3}, \
2382 {"$4", RTYPE_NUM | 4}, \
2383 {"$5", RTYPE_NUM | 5}, \
2384 {"$6", RTYPE_NUM | 6}, \
2385 {"$7", RTYPE_NUM | 7}, \
2386 {"$8", RTYPE_NUM | 8}, \
2387 {"$9", RTYPE_NUM | 9}, \
2388 {"$10", RTYPE_NUM | 10}, \
2389 {"$11", RTYPE_NUM | 11}, \
2390 {"$12", RTYPE_NUM | 12}, \
2391 {"$13", RTYPE_NUM | 13}, \
2392 {"$14", RTYPE_NUM | 14}, \
2393 {"$15", RTYPE_NUM | 15}, \
2394 {"$16", RTYPE_NUM | 16}, \
2395 {"$17", RTYPE_NUM | 17}, \
2396 {"$18", RTYPE_NUM | 18}, \
2397 {"$19", RTYPE_NUM | 19}, \
2398 {"$20", RTYPE_NUM | 20}, \
2399 {"$21", RTYPE_NUM | 21}, \
2400 {"$22", RTYPE_NUM | 22}, \
2401 {"$23", RTYPE_NUM | 23}, \
2402 {"$24", RTYPE_NUM | 24}, \
2403 {"$25", RTYPE_NUM | 25}, \
2404 {"$26", RTYPE_NUM | 26}, \
2405 {"$27", RTYPE_NUM | 27}, \
2406 {"$28", RTYPE_NUM | 28}, \
2407 {"$29", RTYPE_NUM | 29}, \
2408 {"$30", RTYPE_NUM | 30}, \
2409 {"$31", RTYPE_NUM | 31}
2411 #define FPU_REGISTER_NAMES \
2412 {"$f0", RTYPE_FPU | 0}, \
2413 {"$f1", RTYPE_FPU | 1}, \
2414 {"$f2", RTYPE_FPU | 2}, \
2415 {"$f3", RTYPE_FPU | 3}, \
2416 {"$f4", RTYPE_FPU | 4}, \
2417 {"$f5", RTYPE_FPU | 5}, \
2418 {"$f6", RTYPE_FPU | 6}, \
2419 {"$f7", RTYPE_FPU | 7}, \
2420 {"$f8", RTYPE_FPU | 8}, \
2421 {"$f9", RTYPE_FPU | 9}, \
2422 {"$f10", RTYPE_FPU | 10}, \
2423 {"$f11", RTYPE_FPU | 11}, \
2424 {"$f12", RTYPE_FPU | 12}, \
2425 {"$f13", RTYPE_FPU | 13}, \
2426 {"$f14", RTYPE_FPU | 14}, \
2427 {"$f15", RTYPE_FPU | 15}, \
2428 {"$f16", RTYPE_FPU | 16}, \
2429 {"$f17", RTYPE_FPU | 17}, \
2430 {"$f18", RTYPE_FPU | 18}, \
2431 {"$f19", RTYPE_FPU | 19}, \
2432 {"$f20", RTYPE_FPU | 20}, \
2433 {"$f21", RTYPE_FPU | 21}, \
2434 {"$f22", RTYPE_FPU | 22}, \
2435 {"$f23", RTYPE_FPU | 23}, \
2436 {"$f24", RTYPE_FPU | 24}, \
2437 {"$f25", RTYPE_FPU | 25}, \
2438 {"$f26", RTYPE_FPU | 26}, \
2439 {"$f27", RTYPE_FPU | 27}, \
2440 {"$f28", RTYPE_FPU | 28}, \
2441 {"$f29", RTYPE_FPU | 29}, \
2442 {"$f30", RTYPE_FPU | 30}, \
2443 {"$f31", RTYPE_FPU | 31}
2445 #define FPU_CONDITION_CODE_NAMES \
2446 {"$fcc0", RTYPE_FCC | 0}, \
2447 {"$fcc1", RTYPE_FCC | 1}, \
2448 {"$fcc2", RTYPE_FCC | 2}, \
2449 {"$fcc3", RTYPE_FCC | 3}, \
2450 {"$fcc4", RTYPE_FCC | 4}, \
2451 {"$fcc5", RTYPE_FCC | 5}, \
2452 {"$fcc6", RTYPE_FCC | 6}, \
2453 {"$fcc7", RTYPE_FCC | 7}
2455 #define COPROC_CONDITION_CODE_NAMES \
2456 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2457 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2458 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2459 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2460 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2461 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2462 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2463 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2465 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2466 {"$a4", RTYPE_GP | 8}, \
2467 {"$a5", RTYPE_GP | 9}, \
2468 {"$a6", RTYPE_GP | 10}, \
2469 {"$a7", RTYPE_GP | 11}, \
2470 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2471 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2472 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2473 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2474 {"$t0", RTYPE_GP | 12}, \
2475 {"$t1", RTYPE_GP | 13}, \
2476 {"$t2", RTYPE_GP | 14}, \
2477 {"$t3", RTYPE_GP | 15}
2479 #define O32_SYMBOLIC_REGISTER_NAMES \
2480 {"$t0", RTYPE_GP | 8}, \
2481 {"$t1", RTYPE_GP | 9}, \
2482 {"$t2", RTYPE_GP | 10}, \
2483 {"$t3", RTYPE_GP | 11}, \
2484 {"$t4", RTYPE_GP | 12}, \
2485 {"$t5", RTYPE_GP | 13}, \
2486 {"$t6", RTYPE_GP | 14}, \
2487 {"$t7", RTYPE_GP | 15}, \
2488 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2489 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2490 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2491 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2493 /* Remaining symbolic register names */
2494 #define SYMBOLIC_REGISTER_NAMES \
2495 {"$zero", RTYPE_GP | 0}, \
2496 {"$at", RTYPE_GP | 1}, \
2497 {"$AT", RTYPE_GP | 1}, \
2498 {"$v0", RTYPE_GP | 2}, \
2499 {"$v1", RTYPE_GP | 3}, \
2500 {"$a0", RTYPE_GP | 4}, \
2501 {"$a1", RTYPE_GP | 5}, \
2502 {"$a2", RTYPE_GP | 6}, \
2503 {"$a3", RTYPE_GP | 7}, \
2504 {"$s0", RTYPE_GP | 16}, \
2505 {"$s1", RTYPE_GP | 17}, \
2506 {"$s2", RTYPE_GP | 18}, \
2507 {"$s3", RTYPE_GP | 19}, \
2508 {"$s4", RTYPE_GP | 20}, \
2509 {"$s5", RTYPE_GP | 21}, \
2510 {"$s6", RTYPE_GP | 22}, \
2511 {"$s7", RTYPE_GP | 23}, \
2512 {"$t8", RTYPE_GP | 24}, \
2513 {"$t9", RTYPE_GP | 25}, \
2514 {"$k0", RTYPE_GP | 26}, \
2515 {"$kt0", RTYPE_GP | 26}, \
2516 {"$k1", RTYPE_GP | 27}, \
2517 {"$kt1", RTYPE_GP | 27}, \
2518 {"$gp", RTYPE_GP | 28}, \
2519 {"$sp", RTYPE_GP | 29}, \
2520 {"$s8", RTYPE_GP | 30}, \
2521 {"$fp", RTYPE_GP | 30}, \
2522 {"$ra", RTYPE_GP | 31}
2524 #define MIPS16_SPECIAL_REGISTER_NAMES \
2525 {"$pc", RTYPE_PC | 0}
2527 #define MDMX_VECTOR_REGISTER_NAMES \
2528 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2529 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2530 {"$v2", RTYPE_VEC | 2}, \
2531 {"$v3", RTYPE_VEC | 3}, \
2532 {"$v4", RTYPE_VEC | 4}, \
2533 {"$v5", RTYPE_VEC | 5}, \
2534 {"$v6", RTYPE_VEC | 6}, \
2535 {"$v7", RTYPE_VEC | 7}, \
2536 {"$v8", RTYPE_VEC | 8}, \
2537 {"$v9", RTYPE_VEC | 9}, \
2538 {"$v10", RTYPE_VEC | 10}, \
2539 {"$v11", RTYPE_VEC | 11}, \
2540 {"$v12", RTYPE_VEC | 12}, \
2541 {"$v13", RTYPE_VEC | 13}, \
2542 {"$v14", RTYPE_VEC | 14}, \
2543 {"$v15", RTYPE_VEC | 15}, \
2544 {"$v16", RTYPE_VEC | 16}, \
2545 {"$v17", RTYPE_VEC | 17}, \
2546 {"$v18", RTYPE_VEC | 18}, \
2547 {"$v19", RTYPE_VEC | 19}, \
2548 {"$v20", RTYPE_VEC | 20}, \
2549 {"$v21", RTYPE_VEC | 21}, \
2550 {"$v22", RTYPE_VEC | 22}, \
2551 {"$v23", RTYPE_VEC | 23}, \
2552 {"$v24", RTYPE_VEC | 24}, \
2553 {"$v25", RTYPE_VEC | 25}, \
2554 {"$v26", RTYPE_VEC | 26}, \
2555 {"$v27", RTYPE_VEC | 27}, \
2556 {"$v28", RTYPE_VEC | 28}, \
2557 {"$v29", RTYPE_VEC | 29}, \
2558 {"$v30", RTYPE_VEC | 30}, \
2559 {"$v31", RTYPE_VEC | 31}
2561 #define R5900_I_NAMES \
2562 {"$I", RTYPE_R5900_I | 0}
2564 #define R5900_Q_NAMES \
2565 {"$Q", RTYPE_R5900_Q | 0}
2567 #define R5900_R_NAMES \
2568 {"$R", RTYPE_R5900_R | 0}
2570 #define R5900_ACC_NAMES \
2571 {"$ACC", RTYPE_R5900_ACC | 0 }
2573 #define MIPS_DSP_ACCUMULATOR_NAMES \
2574 {"$ac0", RTYPE_ACC | 0}, \
2575 {"$ac1", RTYPE_ACC | 1}, \
2576 {"$ac2", RTYPE_ACC | 2}, \
2577 {"$ac3", RTYPE_ACC | 3}
2579 static const struct regname reg_names
[] = {
2580 GENERIC_REGISTER_NUMBERS
,
2582 FPU_CONDITION_CODE_NAMES
,
2583 COPROC_CONDITION_CODE_NAMES
,
2585 /* The $txx registers depends on the abi,
2586 these will be added later into the symbol table from
2587 one of the tables below once mips_abi is set after
2588 parsing of arguments from the command line. */
2589 SYMBOLIC_REGISTER_NAMES
,
2591 MIPS16_SPECIAL_REGISTER_NAMES
,
2592 MDMX_VECTOR_REGISTER_NAMES
,
2597 MIPS_DSP_ACCUMULATOR_NAMES
,
2601 static const struct regname reg_names_o32
[] = {
2602 O32_SYMBOLIC_REGISTER_NAMES
,
2606 static const struct regname reg_names_n32n64
[] = {
2607 N32N64_SYMBOLIC_REGISTER_NAMES
,
2611 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2612 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2613 of these register symbols, return the associated vector register,
2614 otherwise return SYMVAL itself. */
2617 mips_prefer_vec_regno (unsigned int symval
)
2619 if ((symval
& -2) == (RTYPE_GP
| 2))
2620 return RTYPE_VEC
| (symval
& 1);
2624 /* Return true if string [S, E) is a valid register name, storing its
2625 symbol value in *SYMVAL_PTR if so. */
2628 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2633 /* Terminate name. */
2637 /* Look up the name. */
2638 symbol
= symbol_find (s
);
2641 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2644 *symval_ptr
= S_GET_VALUE (symbol
);
2648 /* Return true if the string at *SPTR is a valid register name. Allow it
2649 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2652 When returning true, move *SPTR past the register, store the
2653 register's symbol value in *SYMVAL_PTR and the channel mask in
2654 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2655 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2656 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2659 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2660 unsigned int *channels_ptr
)
2664 unsigned int channels
, symval
, bit
;
2666 /* Find end of name. */
2668 if (is_name_beginner (*e
))
2670 while (is_part_of_name (*e
))
2674 if (!mips_parse_register_1 (s
, e
, &symval
))
2679 /* Eat characters from the end of the string that are valid
2680 channel suffixes. The preceding register must be $ACC or
2681 end with a digit, so there is no ambiguity. */
2684 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2685 if (m
> s
&& m
[-1] == *q
)
2692 || !mips_parse_register_1 (s
, m
, &symval
)
2693 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2698 *symval_ptr
= symval
;
2700 *channels_ptr
= channels
;
2704 /* Check if SPTR points at a valid register specifier according to TYPES.
2705 If so, then return 1, advance S to consume the specifier and store
2706 the register's number in REGNOP, otherwise return 0. */
2709 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2713 if (mips_parse_register (s
, ®no
, NULL
))
2715 if (types
& RTYPE_VEC
)
2716 regno
= mips_prefer_vec_regno (regno
);
2725 as_warn (_("unrecognized register name `%s'"), *s
);
2730 return regno
<= RNUM_MASK
;
2733 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2734 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2737 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2742 for (i
= 0; i
< 4; i
++)
2743 if (*s
== "xyzw"[i
])
2745 *channels
|= 1 << (3 - i
);
2751 /* Token types for parsed operand lists. */
2752 enum mips_operand_token_type
{
2753 /* A plain register, e.g. $f2. */
2756 /* A 4-bit XYZW channel mask. */
2759 /* A constant vector index, e.g. [1]. */
2762 /* A register vector index, e.g. [$2]. */
2765 /* A continuous range of registers, e.g. $s0-$s4. */
2768 /* A (possibly relocated) expression. */
2771 /* A floating-point value. */
2774 /* A single character. This can be '(', ')' or ',', but '(' only appears
2778 /* A doubled character, either "--" or "++". */
2781 /* The end of the operand list. */
2785 /* A parsed operand token. */
2786 struct mips_operand_token
2788 /* The type of token. */
2789 enum mips_operand_token_type type
;
2792 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2795 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2796 unsigned int channels
;
2798 /* The integer value of an OT_INTEGER_INDEX. */
2801 /* The two register symbol values involved in an OT_REG_RANGE. */
2803 unsigned int regno1
;
2804 unsigned int regno2
;
2807 /* The value of an OT_INTEGER. The value is represented as an
2808 expression and the relocation operators that were applied to
2809 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2810 relocation operators were used. */
2813 bfd_reloc_code_real_type relocs
[3];
2816 /* The binary data for an OT_FLOAT constant, and the number of bytes
2819 unsigned char data
[8];
2823 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2828 /* An obstack used to construct lists of mips_operand_tokens. */
2829 static struct obstack mips_operand_tokens
;
2831 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2834 mips_add_token (struct mips_operand_token
*token
,
2835 enum mips_operand_token_type type
)
2838 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2841 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2842 and OT_REG tokens for them if so, and return a pointer to the first
2843 unconsumed character. Return null otherwise. */
2846 mips_parse_base_start (char *s
)
2848 struct mips_operand_token token
;
2849 unsigned int regno
, channels
;
2850 bfd_boolean decrement_p
;
2856 SKIP_SPACE_TABS (s
);
2858 /* Only match "--" as part of a base expression. In other contexts "--X"
2859 is a double negative. */
2860 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2864 SKIP_SPACE_TABS (s
);
2867 /* Allow a channel specifier because that leads to better error messages
2868 than treating something like "$vf0x++" as an expression. */
2869 if (!mips_parse_register (&s
, ®no
, &channels
))
2873 mips_add_token (&token
, OT_CHAR
);
2878 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2881 token
.u
.regno
= regno
;
2882 mips_add_token (&token
, OT_REG
);
2886 token
.u
.channels
= channels
;
2887 mips_add_token (&token
, OT_CHANNELS
);
2890 /* For consistency, only match "++" as part of base expressions too. */
2891 SKIP_SPACE_TABS (s
);
2892 if (s
[0] == '+' && s
[1] == '+')
2896 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2902 /* Parse one or more tokens from S. Return a pointer to the first
2903 unconsumed character on success. Return null if an error was found
2904 and store the error text in insn_error. FLOAT_FORMAT is as for
2905 mips_parse_arguments. */
2908 mips_parse_argument_token (char *s
, char float_format
)
2910 char *end
, *save_in
, *err
;
2911 unsigned int regno1
, regno2
, channels
;
2912 struct mips_operand_token token
;
2914 /* First look for "($reg", since we want to treat that as an
2915 OT_CHAR and OT_REG rather than an expression. */
2916 end
= mips_parse_base_start (s
);
2920 /* Handle other characters that end up as OT_CHARs. */
2921 if (*s
== ')' || *s
== ',')
2924 mips_add_token (&token
, OT_CHAR
);
2929 /* Handle tokens that start with a register. */
2930 if (mips_parse_register (&s
, ®no1
, &channels
))
2934 /* A register and a VU0 channel suffix. */
2935 token
.u
.regno
= regno1
;
2936 mips_add_token (&token
, OT_REG
);
2938 token
.u
.channels
= channels
;
2939 mips_add_token (&token
, OT_CHANNELS
);
2943 SKIP_SPACE_TABS (s
);
2946 /* A register range. */
2948 SKIP_SPACE_TABS (s
);
2949 if (!mips_parse_register (&s
, ®no2
, NULL
))
2951 set_insn_error (0, _("invalid register range"));
2955 token
.u
.reg_range
.regno1
= regno1
;
2956 token
.u
.reg_range
.regno2
= regno2
;
2957 mips_add_token (&token
, OT_REG_RANGE
);
2961 /* Add the register itself. */
2962 token
.u
.regno
= regno1
;
2963 mips_add_token (&token
, OT_REG
);
2965 /* Check for a vector index. */
2969 SKIP_SPACE_TABS (s
);
2970 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
2971 mips_add_token (&token
, OT_REG_INDEX
);
2974 expressionS element
;
2976 my_getExpression (&element
, s
);
2977 if (element
.X_op
!= O_constant
)
2979 set_insn_error (0, _("vector element must be constant"));
2983 token
.u
.index
= element
.X_add_number
;
2984 mips_add_token (&token
, OT_INTEGER_INDEX
);
2986 SKIP_SPACE_TABS (s
);
2989 set_insn_error (0, _("missing `]'"));
2999 /* First try to treat expressions as floats. */
3000 save_in
= input_line_pointer
;
3001 input_line_pointer
= s
;
3002 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3003 &token
.u
.flt
.length
);
3004 end
= input_line_pointer
;
3005 input_line_pointer
= save_in
;
3008 set_insn_error (0, err
);
3013 mips_add_token (&token
, OT_FLOAT
);
3018 /* Treat everything else as an integer expression. */
3019 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3020 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3021 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3022 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3024 mips_add_token (&token
, OT_INTEGER
);
3028 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3029 if expressions should be treated as 32-bit floating-point constants,
3030 'd' if they should be treated as 64-bit floating-point constants,
3031 or 0 if they should be treated as integer expressions (the usual case).
3033 Return a list of tokens on success, otherwise return 0. The caller
3034 must obstack_free the list after use. */
3036 static struct mips_operand_token
*
3037 mips_parse_arguments (char *s
, char float_format
)
3039 struct mips_operand_token token
;
3041 SKIP_SPACE_TABS (s
);
3044 s
= mips_parse_argument_token (s
, float_format
);
3047 obstack_free (&mips_operand_tokens
,
3048 obstack_finish (&mips_operand_tokens
));
3051 SKIP_SPACE_TABS (s
);
3053 mips_add_token (&token
, OT_END
);
3054 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3057 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3058 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3061 is_opcode_valid (const struct mips_opcode
*mo
)
3063 int isa
= mips_opts
.isa
;
3064 int ase
= mips_opts
.ase
;
3068 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3069 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3070 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3071 ase
|= mips_ases
[i
].flags64
;
3073 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3076 /* Check whether the instruction or macro requires single-precision or
3077 double-precision floating-point support. Note that this information is
3078 stored differently in the opcode table for insns and macros. */
3079 if (mo
->pinfo
== INSN_MACRO
)
3081 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3082 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3086 fp_s
= mo
->pinfo
& FP_S
;
3087 fp_d
= mo
->pinfo
& FP_D
;
3090 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3093 if (fp_s
&& mips_opts
.soft_float
)
3099 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3100 selected ISA and architecture. */
3103 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3105 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3108 /* Return TRUE if the size of the microMIPS opcode MO matches one
3109 explicitly requested. Always TRUE in the standard MIPS mode. */
3112 is_size_valid (const struct mips_opcode
*mo
)
3114 if (!mips_opts
.micromips
)
3117 if (mips_opts
.insn32
)
3119 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3121 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3124 if (!forced_insn_length
)
3126 if (mo
->pinfo
== INSN_MACRO
)
3128 return forced_insn_length
== micromips_insn_length (mo
);
3131 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3132 of the preceding instruction. Always TRUE in the standard MIPS mode.
3134 We don't accept macros in 16-bit delay slots to avoid a case where
3135 a macro expansion fails because it relies on a preceding 32-bit real
3136 instruction to have matched and does not handle the operands correctly.
3137 The only macros that may expand to 16-bit instructions are JAL that
3138 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3139 and BGT (that likewise cannot be placed in a delay slot) that decay to
3140 a NOP. In all these cases the macros precede any corresponding real
3141 instruction definitions in the opcode table, so they will match in the
3142 second pass where the size of the delay slot is ignored and therefore
3143 produce correct code. */
3146 is_delay_slot_valid (const struct mips_opcode
*mo
)
3148 if (!mips_opts
.micromips
)
3151 if (mo
->pinfo
== INSN_MACRO
)
3152 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3153 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3154 && micromips_insn_length (mo
) != 4)
3156 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3157 && micromips_insn_length (mo
) != 2)
3163 /* For consistency checking, verify that all bits of OPCODE are specified
3164 either by the match/mask part of the instruction definition, or by the
3165 operand list. Also build up a list of operands in OPERANDS.
3167 INSN_BITS says which bits of the instruction are significant.
3168 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3169 provides the mips_operand description of each operand. DECODE_OPERAND
3170 is null for MIPS16 instructions. */
3173 validate_mips_insn (const struct mips_opcode
*opcode
,
3174 unsigned long insn_bits
,
3175 const struct mips_operand
*(*decode_operand
) (const char *),
3176 struct mips_operand_array
*operands
)
3179 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3180 const struct mips_operand
*operand
;
3182 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3183 if ((mask
& opcode
->match
) != opcode
->match
)
3185 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3186 opcode
->name
, opcode
->args
);
3191 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3192 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3193 for (s
= opcode
->args
; *s
; ++s
)
3206 if (!decode_operand
)
3207 operand
= decode_mips16_operand (*s
, FALSE
);
3209 operand
= decode_operand (s
);
3210 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3212 as_bad (_("internal: unknown operand type: %s %s"),
3213 opcode
->name
, opcode
->args
);
3216 gas_assert (opno
< MAX_OPERANDS
);
3217 operands
->operand
[opno
] = operand
;
3218 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3220 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3221 if (operand
->type
== OP_MDMX_IMM_REG
)
3222 /* Bit 5 is the format selector (OB vs QH). The opcode table
3223 has separate entries for each format. */
3224 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3225 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3226 used_bits
&= ~(mask
& 0x700);
3228 /* Skip prefix characters. */
3229 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3234 doubled
= used_bits
& mask
& insn_bits
;
3237 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3238 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3242 undefined
= ~used_bits
& insn_bits
;
3243 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3245 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3246 undefined
, opcode
->name
, opcode
->args
);
3249 used_bits
&= ~insn_bits
;
3252 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3253 used_bits
, opcode
->name
, opcode
->args
);
3259 /* The MIPS16 version of validate_mips_insn. */
3262 validate_mips16_insn (const struct mips_opcode
*opcode
,
3263 struct mips_operand_array
*operands
)
3265 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3267 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3268 instruction. Use TMP to describe the full instruction. */
3269 struct mips_opcode tmp
;
3274 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3276 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3279 /* The microMIPS version of validate_mips_insn. */
3282 validate_micromips_insn (const struct mips_opcode
*opc
,
3283 struct mips_operand_array
*operands
)
3285 unsigned long insn_bits
;
3286 unsigned long major
;
3287 unsigned int length
;
3289 if (opc
->pinfo
== INSN_MACRO
)
3290 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3293 length
= micromips_insn_length (opc
);
3294 if (length
!= 2 && length
!= 4)
3296 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3297 "%s %s"), length
, opc
->name
, opc
->args
);
3300 major
= opc
->match
>> (10 + 8 * (length
- 2));
3301 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3302 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3304 as_bad (_("internal error: bad microMIPS opcode "
3305 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3309 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3310 insn_bits
= 1 << 4 * length
;
3311 insn_bits
<<= 4 * length
;
3313 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3317 /* This function is called once, at assembler startup time. It should set up
3318 all the tables, etc. that the MD part of the assembler will need. */
3323 const char *retval
= NULL
;
3327 if (mips_pic
!= NO_PIC
)
3329 if (g_switch_seen
&& g_switch_value
!= 0)
3330 as_bad (_("-G may not be used in position-independent code"));
3334 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3335 as_warn (_("could not set architecture and machine"));
3337 op_hash
= hash_new ();
3339 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3340 for (i
= 0; i
< NUMOPCODES
;)
3342 const char *name
= mips_opcodes
[i
].name
;
3344 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3347 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3348 mips_opcodes
[i
].name
, retval
);
3349 /* Probably a memory allocation problem? Give up now. */
3350 as_fatal (_("broken assembler, no assembly attempted"));
3354 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3355 decode_mips_operand
, &mips_operands
[i
]))
3357 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3359 create_insn (&nop_insn
, mips_opcodes
+ i
);
3360 if (mips_fix_loongson2f_nop
)
3361 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3362 nop_insn
.fixed_p
= 1;
3366 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3369 mips16_op_hash
= hash_new ();
3370 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3371 bfd_mips16_num_opcodes
);
3374 while (i
< bfd_mips16_num_opcodes
)
3376 const char *name
= mips16_opcodes
[i
].name
;
3378 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3380 as_fatal (_("internal: can't hash `%s': %s"),
3381 mips16_opcodes
[i
].name
, retval
);
3384 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3386 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3388 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3389 mips16_nop_insn
.fixed_p
= 1;
3393 while (i
< bfd_mips16_num_opcodes
3394 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3397 micromips_op_hash
= hash_new ();
3398 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3399 bfd_micromips_num_opcodes
);
3402 while (i
< bfd_micromips_num_opcodes
)
3404 const char *name
= micromips_opcodes
[i
].name
;
3406 retval
= hash_insert (micromips_op_hash
, name
,
3407 (void *) µmips_opcodes
[i
]);
3409 as_fatal (_("internal: can't hash `%s': %s"),
3410 micromips_opcodes
[i
].name
, retval
);
3413 struct mips_cl_insn
*micromips_nop_insn
;
3415 if (!validate_micromips_insn (µmips_opcodes
[i
],
3416 µmips_operands
[i
]))
3419 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3421 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3422 micromips_nop_insn
= µmips_nop16_insn
;
3423 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3424 micromips_nop_insn
= µmips_nop32_insn
;
3428 if (micromips_nop_insn
->insn_mo
== NULL
3429 && strcmp (name
, "nop") == 0)
3431 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3432 micromips_nop_insn
->fixed_p
= 1;
3436 while (++i
< bfd_micromips_num_opcodes
3437 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3441 as_fatal (_("broken assembler, no assembly attempted"));
3443 /* We add all the general register names to the symbol table. This
3444 helps us detect invalid uses of them. */
3445 for (i
= 0; reg_names
[i
].name
; i
++)
3446 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3447 reg_names
[i
].num
, /* & RNUM_MASK, */
3448 &zero_address_frag
));
3450 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3451 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3452 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3453 &zero_address_frag
));
3455 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3456 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3457 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3458 &zero_address_frag
));
3460 for (i
= 0; i
< 32; i
++)
3464 /* R5900 VU0 floating-point register. */
3465 regname
[sizeof (rename
) - 1] = 0;
3466 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3467 symbol_table_insert (symbol_new (regname
, reg_section
,
3468 RTYPE_VF
| i
, &zero_address_frag
));
3470 /* R5900 VU0 integer register. */
3471 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3472 symbol_table_insert (symbol_new (regname
, reg_section
,
3473 RTYPE_VI
| i
, &zero_address_frag
));
3476 snprintf (regname
, sizeof (regname
) - 1, "$w%d", i
);
3477 symbol_table_insert (symbol_new (regname
, reg_section
,
3478 RTYPE_MSA
| i
, &zero_address_frag
));
3481 obstack_init (&mips_operand_tokens
);
3483 mips_no_prev_insn ();
3486 mips_cprmask
[0] = 0;
3487 mips_cprmask
[1] = 0;
3488 mips_cprmask
[2] = 0;
3489 mips_cprmask
[3] = 0;
3491 /* set the default alignment for the text section (2**2) */
3492 record_alignment (text_section
, 2);
3494 bfd_set_gp_size (stdoutput
, g_switch_value
);
3496 /* On a native system other than VxWorks, sections must be aligned
3497 to 16 byte boundaries. When configured for an embedded ELF
3498 target, we don't bother. */
3499 if (strncmp (TARGET_OS
, "elf", 3) != 0
3500 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3502 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3503 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3504 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3507 /* Create a .reginfo section for register masks and a .mdebug
3508 section for debugging information. */
3516 subseg
= now_subseg
;
3518 /* The ABI says this section should be loaded so that the
3519 running program can access it. However, we don't load it
3520 if we are configured for an embedded target */
3521 flags
= SEC_READONLY
| SEC_DATA
;
3522 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3523 flags
|= SEC_ALLOC
| SEC_LOAD
;
3525 if (mips_abi
!= N64_ABI
)
3527 sec
= subseg_new (".reginfo", (subsegT
) 0);
3529 bfd_set_section_flags (stdoutput
, sec
, flags
);
3530 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3532 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3536 /* The 64-bit ABI uses a .MIPS.options section rather than
3537 .reginfo section. */
3538 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3539 bfd_set_section_flags (stdoutput
, sec
, flags
);
3540 bfd_set_section_alignment (stdoutput
, sec
, 3);
3542 /* Set up the option header. */
3544 Elf_Internal_Options opthdr
;
3547 opthdr
.kind
= ODK_REGINFO
;
3548 opthdr
.size
= (sizeof (Elf_External_Options
)
3549 + sizeof (Elf64_External_RegInfo
));
3552 f
= frag_more (sizeof (Elf_External_Options
));
3553 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3554 (Elf_External_Options
*) f
);
3556 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3560 if (ECOFF_DEBUGGING
)
3562 sec
= subseg_new (".mdebug", (subsegT
) 0);
3563 (void) bfd_set_section_flags (stdoutput
, sec
,
3564 SEC_HAS_CONTENTS
| SEC_READONLY
);
3565 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3567 else if (mips_flag_pdr
)
3569 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3570 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3571 SEC_READONLY
| SEC_RELOC
3573 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3576 subseg_set (seg
, subseg
);
3579 if (! ECOFF_DEBUGGING
)
3582 if (mips_fix_vr4120
)
3583 init_vr4120_conflicts ();
3589 mips_emit_delays ();
3590 if (! ECOFF_DEBUGGING
)
3595 md_assemble (char *str
)
3597 struct mips_cl_insn insn
;
3598 bfd_reloc_code_real_type unused_reloc
[3]
3599 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3601 imm_expr
.X_op
= O_absent
;
3602 offset_expr
.X_op
= O_absent
;
3603 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3604 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3605 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3607 mips_mark_labels ();
3608 mips_assembling_insn
= TRUE
;
3609 clear_insn_error ();
3611 if (mips_opts
.mips16
)
3612 mips16_ip (str
, &insn
);
3615 mips_ip (str
, &insn
);
3616 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3617 str
, insn
.insn_opcode
));
3621 report_insn_error (str
);
3622 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3625 if (mips_opts
.mips16
)
3626 mips16_macro (&insn
);
3633 if (offset_expr
.X_op
!= O_absent
)
3634 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3636 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3639 mips_assembling_insn
= FALSE
;
3642 /* Convenience functions for abstracting away the differences between
3643 MIPS16 and non-MIPS16 relocations. */
3645 static inline bfd_boolean
3646 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3650 case BFD_RELOC_MIPS16_JMP
:
3651 case BFD_RELOC_MIPS16_GPREL
:
3652 case BFD_RELOC_MIPS16_GOT16
:
3653 case BFD_RELOC_MIPS16_CALL16
:
3654 case BFD_RELOC_MIPS16_HI16_S
:
3655 case BFD_RELOC_MIPS16_HI16
:
3656 case BFD_RELOC_MIPS16_LO16
:
3664 static inline bfd_boolean
3665 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3669 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3670 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3671 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3672 case BFD_RELOC_MICROMIPS_GPREL16
:
3673 case BFD_RELOC_MICROMIPS_JMP
:
3674 case BFD_RELOC_MICROMIPS_HI16
:
3675 case BFD_RELOC_MICROMIPS_HI16_S
:
3676 case BFD_RELOC_MICROMIPS_LO16
:
3677 case BFD_RELOC_MICROMIPS_LITERAL
:
3678 case BFD_RELOC_MICROMIPS_GOT16
:
3679 case BFD_RELOC_MICROMIPS_CALL16
:
3680 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3681 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3682 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3683 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3684 case BFD_RELOC_MICROMIPS_SUB
:
3685 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3686 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3687 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3688 case BFD_RELOC_MICROMIPS_HIGHEST
:
3689 case BFD_RELOC_MICROMIPS_HIGHER
:
3690 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3691 case BFD_RELOC_MICROMIPS_JALR
:
3699 static inline bfd_boolean
3700 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3702 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3705 static inline bfd_boolean
3706 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3708 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3709 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3712 static inline bfd_boolean
3713 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3715 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3716 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3719 static inline bfd_boolean
3720 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3722 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3723 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3726 static inline bfd_boolean
3727 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3729 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3732 static inline bfd_boolean
3733 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3735 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3736 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3739 /* Return true if RELOC is a PC-relative relocation that does not have
3740 full address range. */
3742 static inline bfd_boolean
3743 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3747 case BFD_RELOC_16_PCREL_S2
:
3748 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3749 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3750 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3753 case BFD_RELOC_32_PCREL
:
3754 return HAVE_64BIT_ADDRESSES
;
3761 /* Return true if the given relocation might need a matching %lo().
3762 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3763 need a matching %lo() when applied to local symbols. */
3765 static inline bfd_boolean
3766 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3768 return (HAVE_IN_PLACE_ADDENDS
3769 && (hi16_reloc_p (reloc
)
3770 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3771 all GOT16 relocations evaluate to "G". */
3772 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3775 /* Return the type of %lo() reloc needed by RELOC, given that
3776 reloc_needs_lo_p. */
3778 static inline bfd_reloc_code_real_type
3779 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3781 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3782 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3786 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3789 static inline bfd_boolean
3790 fixup_has_matching_lo_p (fixS
*fixp
)
3792 return (fixp
->fx_next
!= NULL
3793 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3794 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3795 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3798 /* Move all labels in LABELS to the current insertion point. TEXT_P
3799 says whether the labels refer to text or data. */
3802 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3804 struct insn_label_list
*l
;
3807 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3809 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3810 symbol_set_frag (l
->label
, frag_now
);
3811 val
= (valueT
) frag_now_fix ();
3812 /* MIPS16/microMIPS text labels are stored as odd. */
3813 if (text_p
&& HAVE_CODE_COMPRESSION
)
3815 S_SET_VALUE (l
->label
, val
);
3819 /* Move all labels in insn_labels to the current insertion point
3820 and treat them as text labels. */
3823 mips_move_text_labels (void)
3825 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3829 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3831 bfd_boolean linkonce
= FALSE
;
3832 segT symseg
= S_GET_SEGMENT (sym
);
3834 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3836 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3838 /* The GNU toolchain uses an extension for ELF: a section
3839 beginning with the magic string .gnu.linkonce is a
3840 linkonce section. */
3841 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3842 sizeof ".gnu.linkonce" - 1) == 0)
3848 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3849 linker to handle them specially, such as generating jalx instructions
3850 when needed. We also make them odd for the duration of the assembly,
3851 in order to generate the right sort of code. We will make them even
3852 in the adjust_symtab routine, while leaving them marked. This is
3853 convenient for the debugger and the disassembler. The linker knows
3854 to make them odd again. */
3857 mips_compressed_mark_label (symbolS
*label
)
3859 gas_assert (HAVE_CODE_COMPRESSION
);
3861 if (mips_opts
.mips16
)
3862 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3864 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3865 if ((S_GET_VALUE (label
) & 1) == 0
3866 /* Don't adjust the address if the label is global or weak, or
3867 in a link-once section, since we'll be emitting symbol reloc
3868 references to it which will be patched up by the linker, and
3869 the final value of the symbol may or may not be MIPS16/microMIPS. */
3870 && !S_IS_WEAK (label
)
3871 && !S_IS_EXTERNAL (label
)
3872 && !s_is_linkonce (label
, now_seg
))
3873 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3876 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3879 mips_compressed_mark_labels (void)
3881 struct insn_label_list
*l
;
3883 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3884 mips_compressed_mark_label (l
->label
);
3887 /* End the current frag. Make it a variant frag and record the
3891 relax_close_frag (void)
3893 mips_macro_warning
.first_frag
= frag_now
;
3894 frag_var (rs_machine_dependent
, 0, 0,
3895 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3896 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3898 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3899 mips_relax
.first_fixup
= 0;
3902 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3903 See the comment above RELAX_ENCODE for more details. */
3906 relax_start (symbolS
*symbol
)
3908 gas_assert (mips_relax
.sequence
== 0);
3909 mips_relax
.sequence
= 1;
3910 mips_relax
.symbol
= symbol
;
3913 /* Start generating the second version of a relaxable sequence.
3914 See the comment above RELAX_ENCODE for more details. */
3919 gas_assert (mips_relax
.sequence
== 1);
3920 mips_relax
.sequence
= 2;
3923 /* End the current relaxable sequence. */
3928 gas_assert (mips_relax
.sequence
== 2);
3929 relax_close_frag ();
3930 mips_relax
.sequence
= 0;
3933 /* Return true if IP is a delayed branch or jump. */
3935 static inline bfd_boolean
3936 delayed_branch_p (const struct mips_cl_insn
*ip
)
3938 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3939 | INSN_COND_BRANCH_DELAY
3940 | INSN_COND_BRANCH_LIKELY
)) != 0;
3943 /* Return true if IP is a compact branch or jump. */
3945 static inline bfd_boolean
3946 compact_branch_p (const struct mips_cl_insn
*ip
)
3948 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3949 | INSN2_COND_BRANCH
)) != 0;
3952 /* Return true if IP is an unconditional branch or jump. */
3954 static inline bfd_boolean
3955 uncond_branch_p (const struct mips_cl_insn
*ip
)
3957 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3958 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
3961 /* Return true if IP is a branch-likely instruction. */
3963 static inline bfd_boolean
3964 branch_likely_p (const struct mips_cl_insn
*ip
)
3966 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3969 /* Return the type of nop that should be used to fill the delay slot
3970 of delayed branch IP. */
3972 static struct mips_cl_insn
*
3973 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3975 if (mips_opts
.micromips
3976 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3977 return µmips_nop32_insn
;
3981 /* Return a mask that has bit N set if OPCODE reads the register(s)
3985 insn_read_mask (const struct mips_opcode
*opcode
)
3987 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
3990 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3994 insn_write_mask (const struct mips_opcode
*opcode
)
3996 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
3999 /* Return a mask of the registers specified by operand OPERAND of INSN.
4000 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4004 operand_reg_mask (const struct mips_cl_insn
*insn
,
4005 const struct mips_operand
*operand
,
4006 unsigned int type_mask
)
4008 unsigned int uval
, vsel
;
4010 switch (operand
->type
)
4017 case OP_ADDIUSP_INT
:
4018 case OP_ENTRY_EXIT_LIST
:
4019 case OP_REPEAT_DEST_REG
:
4020 case OP_REPEAT_PREV_REG
:
4023 case OP_VU0_MATCH_SUFFIX
:
4028 case OP_OPTIONAL_REG
:
4030 const struct mips_reg_operand
*reg_op
;
4032 reg_op
= (const struct mips_reg_operand
*) operand
;
4033 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4035 uval
= insn_extract_operand (insn
, operand
);
4036 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4041 const struct mips_reg_pair_operand
*pair_op
;
4043 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4044 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4046 uval
= insn_extract_operand (insn
, operand
);
4047 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4050 case OP_CLO_CLZ_DEST
:
4051 if (!(type_mask
& (1 << OP_REG_GP
)))
4053 uval
= insn_extract_operand (insn
, operand
);
4054 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4056 case OP_LWM_SWM_LIST
:
4059 case OP_SAVE_RESTORE_LIST
:
4062 case OP_MDMX_IMM_REG
:
4063 if (!(type_mask
& (1 << OP_REG_VEC
)))
4065 uval
= insn_extract_operand (insn
, operand
);
4067 if ((vsel
& 0x18) == 0x18)
4069 return 1 << (uval
& 31);
4072 if (!(type_mask
& (1 << OP_REG_GP
)))
4074 return 1 << insn_extract_operand (insn
, operand
);
4079 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4080 where bit N of OPNO_MASK is set if operand N should be included.
4081 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4085 insn_reg_mask (const struct mips_cl_insn
*insn
,
4086 unsigned int type_mask
, unsigned int opno_mask
)
4088 unsigned int opno
, reg_mask
;
4092 while (opno_mask
!= 0)
4095 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4102 /* Return the mask of core registers that IP reads. */
4105 gpr_read_mask (const struct mips_cl_insn
*ip
)
4107 unsigned long pinfo
, pinfo2
;
4110 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4111 pinfo
= ip
->insn_mo
->pinfo
;
4112 pinfo2
= ip
->insn_mo
->pinfo2
;
4113 if (pinfo
& INSN_UDI
)
4115 /* UDI instructions have traditionally been assumed to read RS
4117 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4118 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4120 if (pinfo
& INSN_READ_GPR_24
)
4122 if (pinfo2
& INSN2_READ_GPR_16
)
4124 if (pinfo2
& INSN2_READ_SP
)
4126 if (pinfo2
& INSN2_READ_GPR_31
)
4128 /* Don't include register 0. */
4132 /* Return the mask of core registers that IP writes. */
4135 gpr_write_mask (const struct mips_cl_insn
*ip
)
4137 unsigned long pinfo
, pinfo2
;
4140 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4141 pinfo
= ip
->insn_mo
->pinfo
;
4142 pinfo2
= ip
->insn_mo
->pinfo2
;
4143 if (pinfo
& INSN_WRITE_GPR_24
)
4145 if (pinfo
& INSN_WRITE_GPR_31
)
4147 if (pinfo
& INSN_UDI
)
4148 /* UDI instructions have traditionally been assumed to write to RD. */
4149 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4150 if (pinfo2
& INSN2_WRITE_SP
)
4152 /* Don't include register 0. */
4156 /* Return the mask of floating-point registers that IP reads. */
4159 fpr_read_mask (const struct mips_cl_insn
*ip
)
4161 unsigned long pinfo
;
4164 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4165 | (1 << OP_REG_MSA
)),
4166 insn_read_mask (ip
->insn_mo
));
4167 pinfo
= ip
->insn_mo
->pinfo
;
4168 /* Conservatively treat all operands to an FP_D instruction are doubles.
4169 (This is overly pessimistic for things like cvt.d.s.) */
4170 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4175 /* Return the mask of floating-point registers that IP writes. */
4178 fpr_write_mask (const struct mips_cl_insn
*ip
)
4180 unsigned long pinfo
;
4183 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4184 | (1 << OP_REG_MSA
)),
4185 insn_write_mask (ip
->insn_mo
));
4186 pinfo
= ip
->insn_mo
->pinfo
;
4187 /* Conservatively treat all operands to an FP_D instruction are doubles.
4188 (This is overly pessimistic for things like cvt.s.d.) */
4189 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4194 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4195 Check whether that is allowed. */
4198 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4200 const char *s
= insn
->name
;
4202 if (insn
->pinfo
== INSN_MACRO
)
4203 /* Let a macro pass, we'll catch it later when it is expanded. */
4206 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4208 /* Allow odd registers for single-precision ops. */
4209 switch (insn
->pinfo
& (FP_S
| FP_D
))
4220 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4221 s
= strchr (insn
->name
, '.');
4222 if (s
!= NULL
&& opnum
== 2)
4223 s
= strchr (s
+ 1, '.');
4224 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4227 /* Single-precision coprocessor loads and moves are OK too. */
4228 if ((insn
->pinfo
& FP_S
)
4229 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4230 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4236 /* Information about an instruction argument that we're trying to match. */
4237 struct mips_arg_info
4239 /* The instruction so far. */
4240 struct mips_cl_insn
*insn
;
4242 /* The first unconsumed operand token. */
4243 struct mips_operand_token
*token
;
4245 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4248 /* The 1-based argument number, for error reporting. This does not
4249 count elided optional registers, etc.. */
4252 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4253 unsigned int last_regno
;
4255 /* If the first operand was an OP_REG, this is the register that it
4256 specified, otherwise it is ILLEGAL_REG. */
4257 unsigned int dest_regno
;
4259 /* The value of the last OP_INT operand. Only used for OP_MSB,
4260 where it gives the lsb position. */
4261 unsigned int last_op_int
;
4263 /* If true, match routines should assume that no later instruction
4264 alternative matches and should therefore be as accomodating as
4265 possible. Match routines should not report errors if something
4266 is only invalid for !LAX_MATCH. */
4267 bfd_boolean lax_match
;
4269 /* True if a reference to the current AT register was seen. */
4270 bfd_boolean seen_at
;
4273 /* Record that the argument is out of range. */
4276 match_out_of_range (struct mips_arg_info
*arg
)
4278 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4281 /* Record that the argument isn't constant but needs to be. */
4284 match_not_constant (struct mips_arg_info
*arg
)
4286 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4290 /* Try to match an OT_CHAR token for character CH. Consume the token
4291 and return true on success, otherwise return false. */
4294 match_char (struct mips_arg_info
*arg
, char ch
)
4296 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4306 /* Try to get an expression from the next tokens in ARG. Consume the
4307 tokens and return true on success, storing the expression value in
4308 VALUE and relocation types in R. */
4311 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4312 bfd_reloc_code_real_type
*r
)
4314 /* If the next token is a '(' that was parsed as being part of a base
4315 expression, assume we have an elided offset. The later match will fail
4316 if this turns out to be wrong. */
4317 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4319 value
->X_op
= O_constant
;
4320 value
->X_add_number
= 0;
4321 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4325 /* Reject register-based expressions such as "0+$2" and "(($2))".
4326 For plain registers the default error seems more appropriate. */
4327 if (arg
->token
->type
== OT_INTEGER
4328 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4330 set_insn_error (arg
->argnum
, _("register value used as expression"));
4334 if (arg
->token
->type
== OT_INTEGER
)
4336 *value
= arg
->token
->u
.integer
.value
;
4337 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4343 (arg
->argnum
, _("operand %d must be an immediate expression"),
4348 /* Try to get a constant expression from the next tokens in ARG. Consume
4349 the tokens and return return true on success, storing the constant value
4350 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4354 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4357 bfd_reloc_code_real_type r
[3];
4359 if (!match_expression (arg
, &ex
, r
))
4362 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4363 *value
= ex
.X_add_number
;
4366 match_not_constant (arg
);
4372 /* Return the RTYPE_* flags for a register operand of type TYPE that
4373 appears in instruction OPCODE. */
4376 convert_reg_type (const struct mips_opcode
*opcode
,
4377 enum mips_reg_operand_type type
)
4382 return RTYPE_NUM
| RTYPE_GP
;
4385 /* Allow vector register names for MDMX if the instruction is a 64-bit
4386 FPR load, store or move (including moves to and from GPRs). */
4387 if ((mips_opts
.ase
& ASE_MDMX
)
4388 && (opcode
->pinfo
& FP_D
)
4389 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4390 | INSN_COPROC_MEMORY_DELAY
4391 | INSN_LOAD_COPROC_DELAY
4392 | INSN_LOAD_MEMORY_DELAY
4393 | INSN_STORE_MEMORY
)))
4394 return RTYPE_FPU
| RTYPE_VEC
;
4398 if (opcode
->pinfo
& (FP_D
| FP_S
))
4399 return RTYPE_CCC
| RTYPE_FCC
;
4403 if (opcode
->membership
& INSN_5400
)
4405 return RTYPE_FPU
| RTYPE_VEC
;
4411 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4412 return RTYPE_NUM
| RTYPE_CP0
;
4419 return RTYPE_NUM
| RTYPE_VI
;
4422 return RTYPE_NUM
| RTYPE_VF
;
4424 case OP_REG_R5900_I
:
4425 return RTYPE_R5900_I
;
4427 case OP_REG_R5900_Q
:
4428 return RTYPE_R5900_Q
;
4430 case OP_REG_R5900_R
:
4431 return RTYPE_R5900_R
;
4433 case OP_REG_R5900_ACC
:
4434 return RTYPE_R5900_ACC
;
4439 case OP_REG_MSA_CTRL
:
4445 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4448 check_regno (struct mips_arg_info
*arg
,
4449 enum mips_reg_operand_type type
, unsigned int regno
)
4451 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4452 arg
->seen_at
= TRUE
;
4454 if (type
== OP_REG_FP
4457 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4458 as_warn (_("float register should be even, was %d"), regno
);
4460 if (type
== OP_REG_CCC
)
4465 name
= arg
->insn
->insn_mo
->name
;
4466 length
= strlen (name
);
4467 if ((regno
& 1) != 0
4468 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4469 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4470 as_warn (_("condition code register should be even for %s, was %d"),
4473 if ((regno
& 3) != 0
4474 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4475 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4480 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4481 a register of type TYPE. Return true on success, storing the register
4482 number in *REGNO and warning about any dubious uses. */
4485 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4486 unsigned int symval
, unsigned int *regno
)
4488 if (type
== OP_REG_VEC
)
4489 symval
= mips_prefer_vec_regno (symval
);
4490 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4493 *regno
= symval
& RNUM_MASK
;
4494 check_regno (arg
, type
, *regno
);
4498 /* Try to interpret the next token in ARG as a register of type TYPE.
4499 Consume the token and return true on success, storing the register
4500 number in *REGNO. Return false on failure. */
4503 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4504 unsigned int *regno
)
4506 if (arg
->token
->type
== OT_REG
4507 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4515 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4516 Consume the token and return true on success, storing the register numbers
4517 in *REGNO1 and *REGNO2. Return false on failure. */
4520 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4521 unsigned int *regno1
, unsigned int *regno2
)
4523 if (match_reg (arg
, type
, regno1
))
4528 if (arg
->token
->type
== OT_REG_RANGE
4529 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4530 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4531 && *regno1
<= *regno2
)
4539 /* OP_INT matcher. */
4542 match_int_operand (struct mips_arg_info
*arg
,
4543 const struct mips_operand
*operand_base
)
4545 const struct mips_int_operand
*operand
;
4547 int min_val
, max_val
, factor
;
4550 operand
= (const struct mips_int_operand
*) operand_base
;
4551 factor
= 1 << operand
->shift
;
4552 min_val
= mips_int_operand_min (operand
);
4553 max_val
= mips_int_operand_max (operand
);
4555 if (operand_base
->lsb
== 0
4556 && operand_base
->size
== 16
4557 && operand
->shift
== 0
4558 && operand
->bias
== 0
4559 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4561 /* The operand can be relocated. */
4562 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4565 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4566 /* Relocation operators were used. Accept the arguent and
4567 leave the relocation value in offset_expr and offset_relocs
4568 for the caller to process. */
4571 if (offset_expr
.X_op
!= O_constant
)
4573 /* Accept non-constant operands if no later alternative matches,
4574 leaving it for the caller to process. */
4575 if (!arg
->lax_match
)
4577 offset_reloc
[0] = BFD_RELOC_LO16
;
4581 /* Clear the global state; we're going to install the operand
4583 sval
= offset_expr
.X_add_number
;
4584 offset_expr
.X_op
= O_absent
;
4586 /* For compatibility with older assemblers, we accept
4587 0x8000-0xffff as signed 16-bit numbers when only
4588 signed numbers are allowed. */
4591 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4592 if (!arg
->lax_match
&& sval
<= max_val
)
4598 if (!match_const_int (arg
, &sval
))
4602 arg
->last_op_int
= sval
;
4604 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
4606 match_out_of_range (arg
);
4610 uval
= (unsigned int) sval
>> operand
->shift
;
4611 uval
-= operand
->bias
;
4613 /* Handle -mfix-cn63xxp1. */
4615 && mips_fix_cn63xxp1
4616 && !mips_opts
.micromips
4617 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4632 /* The rest must be changed to 28. */
4637 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4641 /* OP_MAPPED_INT matcher. */
4644 match_mapped_int_operand (struct mips_arg_info
*arg
,
4645 const struct mips_operand
*operand_base
)
4647 const struct mips_mapped_int_operand
*operand
;
4648 unsigned int uval
, num_vals
;
4651 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4652 if (!match_const_int (arg
, &sval
))
4655 num_vals
= 1 << operand_base
->size
;
4656 for (uval
= 0; uval
< num_vals
; uval
++)
4657 if (operand
->int_map
[uval
] == sval
)
4659 if (uval
== num_vals
)
4661 match_out_of_range (arg
);
4665 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4669 /* OP_MSB matcher. */
4672 match_msb_operand (struct mips_arg_info
*arg
,
4673 const struct mips_operand
*operand_base
)
4675 const struct mips_msb_operand
*operand
;
4676 int min_val
, max_val
, max_high
;
4677 offsetT size
, sval
, high
;
4679 operand
= (const struct mips_msb_operand
*) operand_base
;
4680 min_val
= operand
->bias
;
4681 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4682 max_high
= operand
->opsize
;
4684 if (!match_const_int (arg
, &size
))
4687 high
= size
+ arg
->last_op_int
;
4688 sval
= operand
->add_lsb
? high
: size
;
4690 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4692 match_out_of_range (arg
);
4695 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4699 /* OP_REG matcher. */
4702 match_reg_operand (struct mips_arg_info
*arg
,
4703 const struct mips_operand
*operand_base
)
4705 const struct mips_reg_operand
*operand
;
4706 unsigned int regno
, uval
, num_vals
;
4708 operand
= (const struct mips_reg_operand
*) operand_base
;
4709 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4712 if (operand
->reg_map
)
4714 num_vals
= 1 << operand
->root
.size
;
4715 for (uval
= 0; uval
< num_vals
; uval
++)
4716 if (operand
->reg_map
[uval
] == regno
)
4718 if (num_vals
== uval
)
4724 arg
->last_regno
= regno
;
4725 if (arg
->opnum
== 1)
4726 arg
->dest_regno
= regno
;
4727 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4731 /* OP_REG_PAIR matcher. */
4734 match_reg_pair_operand (struct mips_arg_info
*arg
,
4735 const struct mips_operand
*operand_base
)
4737 const struct mips_reg_pair_operand
*operand
;
4738 unsigned int regno1
, regno2
, uval
, num_vals
;
4740 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4741 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4742 || !match_char (arg
, ',')
4743 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4746 num_vals
= 1 << operand_base
->size
;
4747 for (uval
= 0; uval
< num_vals
; uval
++)
4748 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4750 if (uval
== num_vals
)
4753 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4757 /* OP_PCREL matcher. The caller chooses the relocation type. */
4760 match_pcrel_operand (struct mips_arg_info
*arg
)
4762 bfd_reloc_code_real_type r
[3];
4764 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4767 /* OP_PERF_REG matcher. */
4770 match_perf_reg_operand (struct mips_arg_info
*arg
,
4771 const struct mips_operand
*operand
)
4775 if (!match_const_int (arg
, &sval
))
4780 || (mips_opts
.arch
== CPU_R5900
4781 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4782 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4784 set_insn_error (arg
->argnum
, _("invalid performance register"));
4788 insn_insert_operand (arg
->insn
, operand
, sval
);
4792 /* OP_ADDIUSP matcher. */
4795 match_addiusp_operand (struct mips_arg_info
*arg
,
4796 const struct mips_operand
*operand
)
4801 if (!match_const_int (arg
, &sval
))
4806 match_out_of_range (arg
);
4811 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4813 match_out_of_range (arg
);
4817 uval
= (unsigned int) sval
;
4818 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4819 insn_insert_operand (arg
->insn
, operand
, uval
);
4823 /* OP_CLO_CLZ_DEST matcher. */
4826 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4827 const struct mips_operand
*operand
)
4831 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4834 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4838 /* OP_LWM_SWM_LIST matcher. */
4841 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4842 const struct mips_operand
*operand
)
4844 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4845 struct mips_arg_info reset
;
4848 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4852 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4857 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4860 while (match_char (arg
, ',')
4861 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4864 if (operand
->size
== 2)
4866 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4872 and any permutations of these. */
4873 if ((reglist
& 0xfff1ffff) != 0x80010000)
4876 sregs
= (reglist
>> 17) & 7;
4881 /* The list must include at least one of ra and s0-sN,
4882 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4883 which are $23 and $30 respectively.) E.g.:
4891 and any permutations of these. */
4892 if ((reglist
& 0x3f00ffff) != 0)
4895 ra
= (reglist
>> 27) & 0x10;
4896 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4899 if ((sregs
& -sregs
) != sregs
)
4902 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4906 /* OP_ENTRY_EXIT_LIST matcher. */
4909 match_entry_exit_operand (struct mips_arg_info
*arg
,
4910 const struct mips_operand
*operand
)
4913 bfd_boolean is_exit
;
4915 /* The format is the same for both ENTRY and EXIT, but the constraints
4917 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4918 mask
= (is_exit
? 7 << 3 : 0);
4921 unsigned int regno1
, regno2
;
4922 bfd_boolean is_freg
;
4924 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4926 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4931 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4934 mask
|= (5 + regno2
) << 3;
4936 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4937 mask
|= (regno2
- 3) << 3;
4938 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4939 mask
|= (regno2
- 15) << 1;
4940 else if (regno1
== RA
&& regno2
== RA
)
4945 while (match_char (arg
, ','));
4947 insn_insert_operand (arg
->insn
, operand
, mask
);
4951 /* OP_SAVE_RESTORE_LIST matcher. */
4954 match_save_restore_list_operand (struct mips_arg_info
*arg
)
4956 unsigned int opcode
, args
, statics
, sregs
;
4957 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4960 opcode
= arg
->insn
->insn_opcode
;
4962 num_frame_sizes
= 0;
4968 unsigned int regno1
, regno2
;
4970 if (arg
->token
->type
== OT_INTEGER
)
4972 /* Handle the frame size. */
4973 if (!match_const_int (arg
, &frame_size
))
4975 num_frame_sizes
+= 1;
4979 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4982 while (regno1
<= regno2
)
4984 if (regno1
>= 4 && regno1
<= 7)
4986 if (num_frame_sizes
== 0)
4988 args
|= 1 << (regno1
- 4);
4990 /* statics $a0-$a3 */
4991 statics
|= 1 << (regno1
- 4);
4993 else if (regno1
>= 16 && regno1
<= 23)
4995 sregs
|= 1 << (regno1
- 16);
4996 else if (regno1
== 30)
4999 else if (regno1
== 31)
5000 /* Add $ra to insn. */
5010 while (match_char (arg
, ','));
5012 /* Encode args/statics combination. */
5015 else if (args
== 0xf)
5016 /* All $a0-$a3 are args. */
5017 opcode
|= MIPS16_ALL_ARGS
<< 16;
5018 else if (statics
== 0xf)
5019 /* All $a0-$a3 are statics. */
5020 opcode
|= MIPS16_ALL_STATICS
<< 16;
5023 /* Count arg registers. */
5033 /* Count static registers. */
5035 while (statics
& 0x8)
5037 statics
= (statics
<< 1) & 0xf;
5043 /* Encode args/statics. */
5044 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5047 /* Encode $s0/$s1. */
5048 if (sregs
& (1 << 0)) /* $s0 */
5050 if (sregs
& (1 << 1)) /* $s1 */
5054 /* Encode $s2-$s8. */
5063 opcode
|= num_sregs
<< 24;
5065 /* Encode frame size. */
5066 if (num_frame_sizes
== 0)
5068 set_insn_error (arg
->argnum
, _("missing frame size"));
5071 if (num_frame_sizes
> 1)
5073 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5076 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5078 set_insn_error (arg
->argnum
, _("invalid frame size"));
5081 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5084 opcode
|= (((frame_size
& 0xf0) << 16)
5085 | (frame_size
& 0x0f));
5088 /* Finally build the instruction. */
5089 if ((opcode
>> 16) != 0 || frame_size
== 0)
5090 opcode
|= MIPS16_EXTEND
;
5091 arg
->insn
->insn_opcode
= opcode
;
5095 /* OP_MDMX_IMM_REG matcher. */
5098 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5099 const struct mips_operand
*operand
)
5101 unsigned int regno
, uval
;
5103 const struct mips_opcode
*opcode
;
5105 /* The mips_opcode records whether this is an octobyte or quadhalf
5106 instruction. Start out with that bit in place. */
5107 opcode
= arg
->insn
->insn_mo
;
5108 uval
= mips_extract_operand (operand
, opcode
->match
);
5109 is_qh
= (uval
!= 0);
5111 if (arg
->token
->type
== OT_REG
)
5113 if ((opcode
->membership
& INSN_5400
)
5114 && strcmp (opcode
->name
, "rzu.ob") == 0)
5116 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5121 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5125 /* Check whether this is a vector register or a broadcast of
5126 a single element. */
5127 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5129 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5131 set_insn_error (arg
->argnum
, _("invalid element selector"));
5134 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5139 /* A full vector. */
5140 if ((opcode
->membership
& INSN_5400
)
5141 && (strcmp (opcode
->name
, "sll.ob") == 0
5142 || strcmp (opcode
->name
, "srl.ob") == 0))
5144 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5150 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5152 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5160 if (!match_const_int (arg
, &sval
))
5162 if (sval
< 0 || sval
> 31)
5164 match_out_of_range (arg
);
5167 uval
|= (sval
& 31);
5169 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5171 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5173 insn_insert_operand (arg
->insn
, operand
, uval
);
5177 /* OP_IMM_INDEX matcher. */
5180 match_imm_index_operand (struct mips_arg_info
*arg
,
5181 const struct mips_operand
*operand
)
5183 unsigned int max_val
;
5185 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5188 max_val
= (1 << operand
->size
) - 1;
5189 if (arg
->token
->u
.index
> max_val
)
5191 match_out_of_range (arg
);
5194 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5199 /* OP_REG_INDEX matcher. */
5202 match_reg_index_operand (struct mips_arg_info
*arg
,
5203 const struct mips_operand
*operand
)
5207 if (arg
->token
->type
!= OT_REG_INDEX
)
5210 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5213 insn_insert_operand (arg
->insn
, operand
, regno
);
5218 /* OP_PC matcher. */
5221 match_pc_operand (struct mips_arg_info
*arg
)
5223 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5231 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5232 register that we need to match. */
5235 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5239 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5242 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5243 the length of the value in bytes (4 for float, 8 for double) and
5244 USING_GPRS says whether the destination is a GPR rather than an FPR.
5246 Return the constant in IMM and OFFSET as follows:
5248 - If the constant should be loaded via memory, set IMM to O_absent and
5249 OFFSET to the memory address.
5251 - Otherwise, if the constant should be loaded into two 32-bit registers,
5252 set IMM to the O_constant to load into the high register and OFFSET
5253 to the corresponding value for the low register.
5255 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5257 These constants only appear as the last operand in an instruction,
5258 and every instruction that accepts them in any variant accepts them
5259 in all variants. This means we don't have to worry about backing out
5260 any changes if the instruction does not match. We just match
5261 unconditionally and report an error if the constant is invalid. */
5264 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5265 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5270 const char *newname
;
5271 unsigned char *data
;
5273 /* Where the constant is placed is based on how the MIPS assembler
5276 length == 4 && using_gprs -- immediate value only
5277 length == 8 && using_gprs -- .rdata or immediate value
5278 length == 4 && !using_gprs -- .lit4 or immediate value
5279 length == 8 && !using_gprs -- .lit8 or immediate value
5281 The .lit4 and .lit8 sections are only used if permitted by the
5283 if (arg
->token
->type
!= OT_FLOAT
)
5285 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5289 gas_assert (arg
->token
->u
.flt
.length
== length
);
5290 data
= arg
->token
->u
.flt
.data
;
5293 /* Handle 32-bit constants for which an immediate value is best. */
5296 || g_switch_value
< 4
5297 || (data
[0] == 0 && data
[1] == 0)
5298 || (data
[2] == 0 && data
[3] == 0)))
5300 imm
->X_op
= O_constant
;
5301 if (!target_big_endian
)
5302 imm
->X_add_number
= bfd_getl32 (data
);
5304 imm
->X_add_number
= bfd_getb32 (data
);
5305 offset
->X_op
= O_absent
;
5309 /* Handle 64-bit constants for which an immediate value is best. */
5311 && !mips_disable_float_construction
5312 /* Constants can only be constructed in GPRs and copied
5313 to FPRs if the GPRs are at least as wide as the FPRs.
5314 Force the constant into memory if we are using 64-bit FPRs
5315 but the GPRs are only 32 bits wide. */
5316 /* ??? No longer true with the addition of MTHC1, but this
5317 is legacy code... */
5318 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5319 && ((data
[0] == 0 && data
[1] == 0)
5320 || (data
[2] == 0 && data
[3] == 0))
5321 && ((data
[4] == 0 && data
[5] == 0)
5322 || (data
[6] == 0 && data
[7] == 0)))
5324 /* The value is simple enough to load with a couple of instructions.
5325 If using 32-bit registers, set IMM to the high order 32 bits and
5326 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5328 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5330 imm
->X_op
= O_constant
;
5331 offset
->X_op
= O_constant
;
5332 if (!target_big_endian
)
5334 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5335 offset
->X_add_number
= bfd_getl32 (data
);
5339 imm
->X_add_number
= bfd_getb32 (data
);
5340 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5342 if (offset
->X_add_number
== 0)
5343 offset
->X_op
= O_absent
;
5347 imm
->X_op
= O_constant
;
5348 if (!target_big_endian
)
5349 imm
->X_add_number
= bfd_getl64 (data
);
5351 imm
->X_add_number
= bfd_getb64 (data
);
5352 offset
->X_op
= O_absent
;
5357 /* Switch to the right section. */
5359 subseg
= now_subseg
;
5362 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5367 if (using_gprs
|| g_switch_value
< 8)
5368 newname
= RDATA_SECTION_NAME
;
5373 new_seg
= subseg_new (newname
, (subsegT
) 0);
5374 bfd_set_section_flags (stdoutput
, new_seg
,
5375 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5376 frag_align (length
== 4 ? 2 : 3, 0, 0);
5377 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5378 record_alignment (new_seg
, 4);
5380 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5382 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5384 /* Set the argument to the current address in the section. */
5385 imm
->X_op
= O_absent
;
5386 offset
->X_op
= O_symbol
;
5387 offset
->X_add_symbol
= symbol_temp_new_now ();
5388 offset
->X_add_number
= 0;
5390 /* Put the floating point number into the section. */
5391 p
= frag_more (length
);
5392 memcpy (p
, data
, length
);
5394 /* Switch back to the original section. */
5395 subseg_set (seg
, subseg
);
5399 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5403 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5404 const struct mips_operand
*operand
,
5405 bfd_boolean match_p
)
5409 /* The operand can be an XYZW mask or a single 2-bit channel index
5410 (with X being 0). */
5411 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5413 /* The suffix can be omitted when it is already part of the opcode. */
5414 if (arg
->token
->type
!= OT_CHANNELS
)
5417 uval
= arg
->token
->u
.channels
;
5418 if (operand
->size
== 2)
5420 /* Check that a single bit is set and convert it into a 2-bit index. */
5421 if ((uval
& -uval
) != uval
)
5423 uval
= 4 - ffs (uval
);
5426 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5431 insn_insert_operand (arg
->insn
, operand
, uval
);
5435 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5436 of the argument text if the match is successful, otherwise return null. */
5439 match_operand (struct mips_arg_info
*arg
,
5440 const struct mips_operand
*operand
)
5442 switch (operand
->type
)
5445 return match_int_operand (arg
, operand
);
5448 return match_mapped_int_operand (arg
, operand
);
5451 return match_msb_operand (arg
, operand
);
5454 case OP_OPTIONAL_REG
:
5455 return match_reg_operand (arg
, operand
);
5458 return match_reg_pair_operand (arg
, operand
);
5461 return match_pcrel_operand (arg
);
5464 return match_perf_reg_operand (arg
, operand
);
5466 case OP_ADDIUSP_INT
:
5467 return match_addiusp_operand (arg
, operand
);
5469 case OP_CLO_CLZ_DEST
:
5470 return match_clo_clz_dest_operand (arg
, operand
);
5472 case OP_LWM_SWM_LIST
:
5473 return match_lwm_swm_list_operand (arg
, operand
);
5475 case OP_ENTRY_EXIT_LIST
:
5476 return match_entry_exit_operand (arg
, operand
);
5478 case OP_SAVE_RESTORE_LIST
:
5479 return match_save_restore_list_operand (arg
);
5481 case OP_MDMX_IMM_REG
:
5482 return match_mdmx_imm_reg_operand (arg
, operand
);
5484 case OP_REPEAT_DEST_REG
:
5485 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5487 case OP_REPEAT_PREV_REG
:
5488 return match_tied_reg_operand (arg
, arg
->last_regno
);
5491 return match_pc_operand (arg
);
5494 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5496 case OP_VU0_MATCH_SUFFIX
:
5497 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5500 return match_imm_index_operand (arg
, operand
);
5503 return match_reg_index_operand (arg
, operand
);
5508 /* ARG is the state after successfully matching an instruction.
5509 Issue any queued-up warnings. */
5512 check_completed_insn (struct mips_arg_info
*arg
)
5517 as_warn (_("used $at without \".set noat\""));
5519 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
5523 /* Return true if modifying general-purpose register REG needs a delay. */
5526 reg_needs_delay (unsigned int reg
)
5528 unsigned long prev_pinfo
;
5530 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5531 if (!mips_opts
.noreorder
5532 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
) && !gpr_interlocks
)
5533 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5534 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5540 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5541 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5542 by VR4120 errata. */
5545 classify_vr4120_insn (const char *name
)
5547 if (strncmp (name
, "macc", 4) == 0)
5548 return FIX_VR4120_MACC
;
5549 if (strncmp (name
, "dmacc", 5) == 0)
5550 return FIX_VR4120_DMACC
;
5551 if (strncmp (name
, "mult", 4) == 0)
5552 return FIX_VR4120_MULT
;
5553 if (strncmp (name
, "dmult", 5) == 0)
5554 return FIX_VR4120_DMULT
;
5555 if (strstr (name
, "div"))
5556 return FIX_VR4120_DIV
;
5557 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5558 return FIX_VR4120_MTHILO
;
5559 return NUM_FIX_VR4120_CLASSES
;
5562 #define INSN_ERET 0x42000018
5563 #define INSN_DERET 0x4200001f
5565 /* Return the number of instructions that must separate INSN1 and INSN2,
5566 where INSN1 is the earlier instruction. Return the worst-case value
5567 for any INSN2 if INSN2 is null. */
5570 insns_between (const struct mips_cl_insn
*insn1
,
5571 const struct mips_cl_insn
*insn2
)
5573 unsigned long pinfo1
, pinfo2
;
5576 /* If INFO2 is null, pessimistically assume that all flags are set for
5577 the second instruction. */
5578 pinfo1
= insn1
->insn_mo
->pinfo
;
5579 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5581 /* For most targets, write-after-read dependencies on the HI and LO
5582 registers must be separated by at least two instructions. */
5583 if (!hilo_interlocks
)
5585 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5587 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5591 /* If we're working around r7000 errata, there must be two instructions
5592 between an mfhi or mflo and any instruction that uses the result. */
5593 if (mips_7000_hilo_fix
5594 && !mips_opts
.micromips
5595 && MF_HILO_INSN (pinfo1
)
5596 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5599 /* If we're working around 24K errata, one instruction is required
5600 if an ERET or DERET is followed by a branch instruction. */
5601 if (mips_fix_24k
&& !mips_opts
.micromips
)
5603 if (insn1
->insn_opcode
== INSN_ERET
5604 || insn1
->insn_opcode
== INSN_DERET
)
5607 || insn2
->insn_opcode
== INSN_ERET
5608 || insn2
->insn_opcode
== INSN_DERET
5609 || delayed_branch_p (insn2
))
5614 /* If working around VR4120 errata, check for combinations that need
5615 a single intervening instruction. */
5616 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5618 unsigned int class1
, class2
;
5620 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5621 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5625 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5626 if (vr4120_conflicts
[class1
] & (1 << class2
))
5631 if (!HAVE_CODE_COMPRESSION
)
5633 /* Check for GPR or coprocessor load delays. All such delays
5634 are on the RT register. */
5635 /* Itbl support may require additional care here. */
5636 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
5637 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5639 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5643 /* Check for generic coprocessor hazards.
5645 This case is not handled very well. There is no special
5646 knowledge of CP0 handling, and the coprocessors other than
5647 the floating point unit are not distinguished at all. */
5648 /* Itbl support may require additional care here. FIXME!
5649 Need to modify this to include knowledge about
5650 user specified delays! */
5651 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5652 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5654 /* Handle cases where INSN1 writes to a known general coprocessor
5655 register. There must be a one instruction delay before INSN2
5656 if INSN2 reads that register, otherwise no delay is needed. */
5657 mask
= fpr_write_mask (insn1
);
5660 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5665 /* Read-after-write dependencies on the control registers
5666 require a two-instruction gap. */
5667 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5668 && (pinfo2
& INSN_READ_COND_CODE
))
5671 /* We don't know exactly what INSN1 does. If INSN2 is
5672 also a coprocessor instruction, assume there must be
5673 a one instruction gap. */
5674 if (pinfo2
& INSN_COP
)
5679 /* Check for read-after-write dependencies on the coprocessor
5680 control registers in cases where INSN1 does not need a general
5681 coprocessor delay. This means that INSN1 is a floating point
5682 comparison instruction. */
5683 /* Itbl support may require additional care here. */
5684 else if (!cop_interlocks
5685 && (pinfo1
& INSN_WRITE_COND_CODE
)
5686 && (pinfo2
& INSN_READ_COND_CODE
))
5693 /* Return the number of nops that would be needed to work around the
5694 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5695 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5696 that are contained within the first IGNORE instructions of HIST. */
5699 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5700 const struct mips_cl_insn
*insn
)
5705 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5706 are not affected by the errata. */
5708 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5709 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5710 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5713 /* Search for the first MFLO or MFHI. */
5714 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5715 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5717 /* Extract the destination register. */
5718 mask
= gpr_write_mask (&hist
[i
]);
5720 /* No nops are needed if INSN reads that register. */
5721 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5724 /* ...or if any of the intervening instructions do. */
5725 for (j
= 0; j
< i
; j
++)
5726 if (gpr_read_mask (&hist
[j
]) & mask
)
5730 return MAX_VR4130_NOPS
- i
;
5735 #define BASE_REG_EQ(INSN1, INSN2) \
5736 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5737 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5739 /* Return the minimum alignment for this store instruction. */
5742 fix_24k_align_to (const struct mips_opcode
*mo
)
5744 if (strcmp (mo
->name
, "sh") == 0)
5747 if (strcmp (mo
->name
, "swc1") == 0
5748 || strcmp (mo
->name
, "swc2") == 0
5749 || strcmp (mo
->name
, "sw") == 0
5750 || strcmp (mo
->name
, "sc") == 0
5751 || strcmp (mo
->name
, "s.s") == 0)
5754 if (strcmp (mo
->name
, "sdc1") == 0
5755 || strcmp (mo
->name
, "sdc2") == 0
5756 || strcmp (mo
->name
, "s.d") == 0)
5763 struct fix_24k_store_info
5765 /* Immediate offset, if any, for this store instruction. */
5767 /* Alignment required by this store instruction. */
5769 /* True for register offsets. */
5770 int register_offset
;
5773 /* Comparison function used by qsort. */
5776 fix_24k_sort (const void *a
, const void *b
)
5778 const struct fix_24k_store_info
*pos1
= a
;
5779 const struct fix_24k_store_info
*pos2
= b
;
5781 return (pos1
->off
- pos2
->off
);
5784 /* INSN is a store instruction. Try to record the store information
5785 in STINFO. Return false if the information isn't known. */
5788 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5789 const struct mips_cl_insn
*insn
)
5791 /* The instruction must have a known offset. */
5792 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5795 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5796 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5800 /* Return the number of nops that would be needed to work around the 24k
5801 "lost data on stores during refill" errata if instruction INSN
5802 immediately followed the 2 instructions described by HIST.
5803 Ignore hazards that are contained within the first IGNORE
5804 instructions of HIST.
5806 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5807 for the data cache refills and store data. The following describes
5808 the scenario where the store data could be lost.
5810 * A data cache miss, due to either a load or a store, causing fill
5811 data to be supplied by the memory subsystem
5812 * The first three doublewords of fill data are returned and written
5814 * A sequence of four stores occurs in consecutive cycles around the
5815 final doubleword of the fill:
5819 * Zero, One or more instructions
5822 The four stores A-D must be to different doublewords of the line that
5823 is being filled. The fourth instruction in the sequence above permits
5824 the fill of the final doubleword to be transferred from the FSB into
5825 the cache. In the sequence above, the stores may be either integer
5826 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5827 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5828 different doublewords on the line. If the floating point unit is
5829 running in 1:2 mode, it is not possible to create the sequence above
5830 using only floating point store instructions.
5832 In this case, the cache line being filled is incorrectly marked
5833 invalid, thereby losing the data from any store to the line that
5834 occurs between the original miss and the completion of the five
5835 cycle sequence shown above.
5837 The workarounds are:
5839 * Run the data cache in write-through mode.
5840 * Insert a non-store instruction between
5841 Store A and Store B or Store B and Store C. */
5844 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5845 const struct mips_cl_insn
*insn
)
5847 struct fix_24k_store_info pos
[3];
5848 int align
, i
, base_offset
;
5853 /* If the previous instruction wasn't a store, there's nothing to
5855 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5858 /* If the instructions after the previous one are unknown, we have
5859 to assume the worst. */
5863 /* Check whether we are dealing with three consecutive stores. */
5864 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5865 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5868 /* If we don't know the relationship between the store addresses,
5869 assume the worst. */
5870 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5871 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5874 if (!fix_24k_record_store_info (&pos
[0], insn
)
5875 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5876 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5879 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5881 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5882 X bytes and such that the base register + X is known to be aligned
5885 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5889 align
= pos
[0].align_to
;
5890 base_offset
= pos
[0].off
;
5891 for (i
= 1; i
< 3; i
++)
5892 if (align
< pos
[i
].align_to
)
5894 align
= pos
[i
].align_to
;
5895 base_offset
= pos
[i
].off
;
5897 for (i
= 0; i
< 3; i
++)
5898 pos
[i
].off
-= base_offset
;
5901 pos
[0].off
&= ~align
+ 1;
5902 pos
[1].off
&= ~align
+ 1;
5903 pos
[2].off
&= ~align
+ 1;
5905 /* If any two stores write to the same chunk, they also write to the
5906 same doubleword. The offsets are still sorted at this point. */
5907 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5910 /* A range of at least 9 bytes is needed for the stores to be in
5911 non-overlapping doublewords. */
5912 if (pos
[2].off
- pos
[0].off
<= 8)
5915 if (pos
[2].off
- pos
[1].off
>= 24
5916 || pos
[1].off
- pos
[0].off
>= 24
5917 || pos
[2].off
- pos
[0].off
>= 32)
5923 /* Return the number of nops that would be needed if instruction INSN
5924 immediately followed the MAX_NOPS instructions given by HIST,
5925 where HIST[0] is the most recent instruction. Ignore hazards
5926 between INSN and the first IGNORE instructions in HIST.
5928 If INSN is null, return the worse-case number of nops for any
5932 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5933 const struct mips_cl_insn
*insn
)
5935 int i
, nops
, tmp_nops
;
5938 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5940 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5941 if (tmp_nops
> nops
)
5945 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5947 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5948 if (tmp_nops
> nops
)
5952 if (mips_fix_24k
&& !mips_opts
.micromips
)
5954 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5955 if (tmp_nops
> nops
)
5962 /* The variable arguments provide NUM_INSNS extra instructions that
5963 might be added to HIST. Return the largest number of nops that
5964 would be needed after the extended sequence, ignoring hazards
5965 in the first IGNORE instructions. */
5968 nops_for_sequence (int num_insns
, int ignore
,
5969 const struct mips_cl_insn
*hist
, ...)
5972 struct mips_cl_insn buffer
[MAX_NOPS
];
5973 struct mips_cl_insn
*cursor
;
5976 va_start (args
, hist
);
5977 cursor
= buffer
+ num_insns
;
5978 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5979 while (cursor
> buffer
)
5980 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5982 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5987 /* Like nops_for_insn, but if INSN is a branch, take into account the
5988 worst-case delay for the branch target. */
5991 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5992 const struct mips_cl_insn
*insn
)
5996 nops
= nops_for_insn (ignore
, hist
, insn
);
5997 if (delayed_branch_p (insn
))
5999 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6000 hist
, insn
, get_delay_slot_nop (insn
));
6001 if (tmp_nops
> nops
)
6004 else if (compact_branch_p (insn
))
6006 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6007 if (tmp_nops
> nops
)
6013 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6016 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6018 gas_assert (!HAVE_CODE_COMPRESSION
);
6019 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6020 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6023 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6024 jr target pc &= 'hffff_ffff_cfff_ffff. */
6027 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6029 gas_assert (!HAVE_CODE_COMPRESSION
);
6030 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6031 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6032 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6040 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6041 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6044 ep
.X_op
= O_constant
;
6045 ep
.X_add_number
= 0xcfff0000;
6046 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6047 ep
.X_add_number
= 0xffff;
6048 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6049 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6054 fix_loongson2f (struct mips_cl_insn
* ip
)
6056 if (mips_fix_loongson2f_nop
)
6057 fix_loongson2f_nop (ip
);
6059 if (mips_fix_loongson2f_jump
)
6060 fix_loongson2f_jump (ip
);
6063 /* IP is a branch that has a delay slot, and we need to fill it
6064 automatically. Return true if we can do that by swapping IP
6065 with the previous instruction.
6066 ADDRESS_EXPR is an operand of the instruction to be used with
6070 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6071 bfd_reloc_code_real_type
*reloc_type
)
6073 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6074 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6075 unsigned int fpr_read
, prev_fpr_write
;
6077 /* -O2 and above is required for this optimization. */
6078 if (mips_optimize
< 2)
6081 /* If we have seen .set volatile or .set nomove, don't optimize. */
6082 if (mips_opts
.nomove
)
6085 /* We can't swap if the previous instruction's position is fixed. */
6086 if (history
[0].fixed_p
)
6089 /* If the previous previous insn was in a .set noreorder, we can't
6090 swap. Actually, the MIPS assembler will swap in this situation.
6091 However, gcc configured -with-gnu-as will generate code like
6099 in which we can not swap the bne and INSN. If gcc is not configured
6100 -with-gnu-as, it does not output the .set pseudo-ops. */
6101 if (history
[1].noreorder_p
)
6104 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6105 This means that the previous instruction was a 4-byte one anyhow. */
6106 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6109 /* If the branch is itself the target of a branch, we can not swap.
6110 We cheat on this; all we check for is whether there is a label on
6111 this instruction. If there are any branches to anything other than
6112 a label, users must use .set noreorder. */
6113 if (seg_info (now_seg
)->label_list
)
6116 /* If the previous instruction is in a variant frag other than this
6117 branch's one, we cannot do the swap. This does not apply to
6118 MIPS16 code, which uses variant frags for different purposes. */
6119 if (!mips_opts
.mips16
6121 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6124 /* We do not swap with instructions that cannot architecturally
6125 be placed in a branch delay slot, such as SYNC or ERET. We
6126 also refrain from swapping with a trap instruction, since it
6127 complicates trap handlers to have the trap instruction be in
6129 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6130 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6133 /* Check for conflicts between the branch and the instructions
6134 before the candidate delay slot. */
6135 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6138 /* Check for conflicts between the swapped sequence and the
6139 target of the branch. */
6140 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6143 /* If the branch reads a register that the previous
6144 instruction sets, we can not swap. */
6145 gpr_read
= gpr_read_mask (ip
);
6146 prev_gpr_write
= gpr_write_mask (&history
[0]);
6147 if (gpr_read
& prev_gpr_write
)
6150 fpr_read
= fpr_read_mask (ip
);
6151 prev_fpr_write
= fpr_write_mask (&history
[0]);
6152 if (fpr_read
& prev_fpr_write
)
6155 /* If the branch writes a register that the previous
6156 instruction sets, we can not swap. */
6157 gpr_write
= gpr_write_mask (ip
);
6158 if (gpr_write
& prev_gpr_write
)
6161 /* If the branch writes a register that the previous
6162 instruction reads, we can not swap. */
6163 prev_gpr_read
= gpr_read_mask (&history
[0]);
6164 if (gpr_write
& prev_gpr_read
)
6167 /* If one instruction sets a condition code and the
6168 other one uses a condition code, we can not swap. */
6169 pinfo
= ip
->insn_mo
->pinfo
;
6170 if ((pinfo
& INSN_READ_COND_CODE
)
6171 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6173 if ((pinfo
& INSN_WRITE_COND_CODE
)
6174 && (prev_pinfo
& INSN_READ_COND_CODE
))
6177 /* If the previous instruction uses the PC, we can not swap. */
6178 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6179 if (prev_pinfo2
& INSN2_READ_PC
)
6182 /* If the previous instruction has an incorrect size for a fixed
6183 branch delay slot in microMIPS mode, we cannot swap. */
6184 pinfo2
= ip
->insn_mo
->pinfo2
;
6185 if (mips_opts
.micromips
6186 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6187 && insn_length (history
) != 2)
6189 if (mips_opts
.micromips
6190 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6191 && insn_length (history
) != 4)
6194 /* On R5900 short loops need to be fixed by inserting a nop in
6195 the branch delay slots.
6196 A short loop can be terminated too early. */
6197 if (mips_opts
.arch
== CPU_R5900
6198 /* Check if instruction has a parameter, ignore "j $31". */
6199 && (address_expr
!= NULL
)
6200 /* Parameter must be 16 bit. */
6201 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6202 /* Branch to same segment. */
6203 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6204 /* Branch to same code fragment. */
6205 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6206 /* Can only calculate branch offset if value is known. */
6207 && symbol_constant_p(address_expr
->X_add_symbol
)
6208 /* Check if branch is really conditional. */
6209 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6210 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6211 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6214 /* Check if loop is shorter than 6 instructions including
6215 branch and delay slot. */
6216 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6223 /* When the loop includes branches or jumps,
6224 it is not a short loop. */
6225 for (i
= 0; i
< (distance
/ 4); i
++)
6227 if ((history
[i
].cleared_p
)
6228 || delayed_branch_p(&history
[i
]))
6236 /* Insert nop after branch to fix short loop. */
6245 /* Decide how we should add IP to the instruction stream.
6246 ADDRESS_EXPR is an operand of the instruction to be used with
6249 static enum append_method
6250 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6251 bfd_reloc_code_real_type
*reloc_type
)
6253 /* The relaxed version of a macro sequence must be inherently
6255 if (mips_relax
.sequence
== 2)
6258 /* We must not dabble with instructions in a ".set norerorder" block. */
6259 if (mips_opts
.noreorder
)
6262 /* Otherwise, it's our responsibility to fill branch delay slots. */
6263 if (delayed_branch_p (ip
))
6265 if (!branch_likely_p (ip
)
6266 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6269 if (mips_opts
.mips16
6270 && ISA_SUPPORTS_MIPS16E
6271 && gpr_read_mask (ip
) != 0)
6272 return APPEND_ADD_COMPACT
;
6274 return APPEND_ADD_WITH_NOP
;
6280 /* IP is a MIPS16 instruction whose opcode we have just changed.
6281 Point IP->insn_mo to the new opcode's definition. */
6284 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6286 const struct mips_opcode
*mo
, *end
;
6288 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6289 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6290 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6298 /* For microMIPS macros, we need to generate a local number label
6299 as the target of branches. */
6300 #define MICROMIPS_LABEL_CHAR '\037'
6301 static unsigned long micromips_target_label
;
6302 static char micromips_target_name
[32];
6305 micromips_label_name (void)
6307 char *p
= micromips_target_name
;
6308 char symbol_name_temporary
[24];
6316 l
= micromips_target_label
;
6317 #ifdef LOCAL_LABEL_PREFIX
6318 *p
++ = LOCAL_LABEL_PREFIX
;
6321 *p
++ = MICROMIPS_LABEL_CHAR
;
6324 symbol_name_temporary
[i
++] = l
% 10 + '0';
6329 *p
++ = symbol_name_temporary
[--i
];
6332 return micromips_target_name
;
6336 micromips_label_expr (expressionS
*label_expr
)
6338 label_expr
->X_op
= O_symbol
;
6339 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6340 label_expr
->X_add_number
= 0;
6344 micromips_label_inc (void)
6346 micromips_target_label
++;
6347 *micromips_target_name
= '\0';
6351 micromips_add_label (void)
6355 s
= colon (micromips_label_name ());
6356 micromips_label_inc ();
6357 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6360 /* If assembling microMIPS code, then return the microMIPS reloc
6361 corresponding to the requested one if any. Otherwise return
6362 the reloc unchanged. */
6364 static bfd_reloc_code_real_type
6365 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6367 static const bfd_reloc_code_real_type relocs
[][2] =
6369 /* Keep sorted incrementally by the left-hand key. */
6370 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6371 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6372 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6373 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6374 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6375 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6376 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6377 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6378 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6379 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6380 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6381 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6382 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6383 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6384 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6385 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6386 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6387 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6388 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6389 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6390 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6391 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6392 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6393 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6394 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6395 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6396 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6398 bfd_reloc_code_real_type r
;
6401 if (!mips_opts
.micromips
)
6403 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6409 return relocs
[i
][1];
6414 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6415 Return true on success, storing the resolved value in RESULT. */
6418 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6423 case BFD_RELOC_MIPS_HIGHEST
:
6424 case BFD_RELOC_MICROMIPS_HIGHEST
:
6425 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6428 case BFD_RELOC_MIPS_HIGHER
:
6429 case BFD_RELOC_MICROMIPS_HIGHER
:
6430 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6433 case BFD_RELOC_HI16_S
:
6434 case BFD_RELOC_MICROMIPS_HI16_S
:
6435 case BFD_RELOC_MIPS16_HI16_S
:
6436 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6439 case BFD_RELOC_HI16
:
6440 case BFD_RELOC_MICROMIPS_HI16
:
6441 case BFD_RELOC_MIPS16_HI16
:
6442 *result
= (operand
>> 16) & 0xffff;
6445 case BFD_RELOC_LO16
:
6446 case BFD_RELOC_MICROMIPS_LO16
:
6447 case BFD_RELOC_MIPS16_LO16
:
6448 *result
= operand
& 0xffff;
6451 case BFD_RELOC_UNUSED
:
6460 /* Output an instruction. IP is the instruction information.
6461 ADDRESS_EXPR is an operand of the instruction to be used with
6462 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6463 a macro expansion. */
6466 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6467 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6469 unsigned long prev_pinfo2
, pinfo
;
6470 bfd_boolean relaxed_branch
= FALSE
;
6471 enum append_method method
;
6472 bfd_boolean relax32
;
6475 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6476 fix_loongson2f (ip
);
6478 file_ase_mips16
|= mips_opts
.mips16
;
6479 file_ase_micromips
|= mips_opts
.micromips
;
6481 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6482 pinfo
= ip
->insn_mo
->pinfo
;
6484 if (mips_opts
.micromips
6486 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6487 && micromips_insn_length (ip
->insn_mo
) != 2)
6488 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6489 && micromips_insn_length (ip
->insn_mo
) != 4)))
6490 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
6491 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6493 if (address_expr
== NULL
)
6495 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6496 && reloc_type
[1] == BFD_RELOC_UNUSED
6497 && reloc_type
[2] == BFD_RELOC_UNUSED
6498 && address_expr
->X_op
== O_constant
)
6500 switch (*reloc_type
)
6502 case BFD_RELOC_MIPS_JMP
:
6506 shift
= mips_opts
.micromips
? 1 : 2;
6507 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6508 as_bad (_("jump to misaligned address (0x%lx)"),
6509 (unsigned long) address_expr
->X_add_number
);
6510 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6516 case BFD_RELOC_MIPS16_JMP
:
6517 if ((address_expr
->X_add_number
& 3) != 0)
6518 as_bad (_("jump to misaligned address (0x%lx)"),
6519 (unsigned long) address_expr
->X_add_number
);
6521 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6522 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6523 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6527 case BFD_RELOC_16_PCREL_S2
:
6531 shift
= mips_opts
.micromips
? 1 : 2;
6532 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6533 as_bad (_("branch to misaligned address (0x%lx)"),
6534 (unsigned long) address_expr
->X_add_number
);
6535 if (!mips_relax_branch
)
6537 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6538 & ~((1 << (shift
+ 16)) - 1))
6539 as_bad (_("branch address range overflow (0x%lx)"),
6540 (unsigned long) address_expr
->X_add_number
);
6541 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6551 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6554 ip
->insn_opcode
|= value
& 0xffff;
6562 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6564 /* There are a lot of optimizations we could do that we don't.
6565 In particular, we do not, in general, reorder instructions.
6566 If you use gcc with optimization, it will reorder
6567 instructions and generally do much more optimization then we
6568 do here; repeating all that work in the assembler would only
6569 benefit hand written assembly code, and does not seem worth
6571 int nops
= (mips_optimize
== 0
6572 ? nops_for_insn (0, history
, NULL
)
6573 : nops_for_insn_or_target (0, history
, ip
));
6577 unsigned long old_frag_offset
;
6580 old_frag
= frag_now
;
6581 old_frag_offset
= frag_now_fix ();
6583 for (i
= 0; i
< nops
; i
++)
6584 add_fixed_insn (NOP_INSN
);
6585 insert_into_history (0, nops
, NOP_INSN
);
6589 listing_prev_line ();
6590 /* We may be at the start of a variant frag. In case we
6591 are, make sure there is enough space for the frag
6592 after the frags created by listing_prev_line. The
6593 argument to frag_grow here must be at least as large
6594 as the argument to all other calls to frag_grow in
6595 this file. We don't have to worry about being in the
6596 middle of a variant frag, because the variants insert
6597 all needed nop instructions themselves. */
6601 mips_move_text_labels ();
6603 #ifndef NO_ECOFF_DEBUGGING
6604 if (ECOFF_DEBUGGING
)
6605 ecoff_fix_loc (old_frag
, old_frag_offset
);
6609 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6613 /* Work out how many nops in prev_nop_frag are needed by IP,
6614 ignoring hazards generated by the first prev_nop_frag_since
6616 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6617 gas_assert (nops
<= prev_nop_frag_holds
);
6619 /* Enforce NOPS as a minimum. */
6620 if (nops
> prev_nop_frag_required
)
6621 prev_nop_frag_required
= nops
;
6623 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6625 /* Settle for the current number of nops. Update the history
6626 accordingly (for the benefit of any future .set reorder code). */
6627 prev_nop_frag
= NULL
;
6628 insert_into_history (prev_nop_frag_since
,
6629 prev_nop_frag_holds
, NOP_INSN
);
6633 /* Allow this instruction to replace one of the nops that was
6634 tentatively added to prev_nop_frag. */
6635 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6636 prev_nop_frag_holds
--;
6637 prev_nop_frag_since
++;
6641 method
= get_append_method (ip
, address_expr
, reloc_type
);
6642 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6644 dwarf2_emit_insn (0);
6645 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6646 so "move" the instruction address accordingly.
6648 Also, it doesn't seem appropriate for the assembler to reorder .loc
6649 entries. If this instruction is a branch that we are going to swap
6650 with the previous instruction, the two instructions should be
6651 treated as a unit, and the debug information for both instructions
6652 should refer to the start of the branch sequence. Using the
6653 current position is certainly wrong when swapping a 32-bit branch
6654 and a 16-bit delay slot, since the current position would then be
6655 in the middle of a branch. */
6656 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6658 relax32
= (mips_relax_branch
6659 /* Don't try branch relaxation within .set nomacro, or within
6660 .set noat if we use $at for PIC computations. If it turns
6661 out that the branch was out-of-range, we'll get an error. */
6662 && !mips_opts
.warn_about_macros
6663 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6664 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6665 as they have no complementing branches. */
6666 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6668 if (!HAVE_CODE_COMPRESSION
6671 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6672 && delayed_branch_p (ip
))
6674 relaxed_branch
= TRUE
;
6675 add_relaxed_insn (ip
, (relaxed_branch_length
6677 uncond_branch_p (ip
) ? -1
6678 : branch_likely_p (ip
) ? 1
6682 uncond_branch_p (ip
),
6683 branch_likely_p (ip
),
6684 pinfo
& INSN_WRITE_GPR_31
,
6686 address_expr
->X_add_symbol
,
6687 address_expr
->X_add_number
);
6688 *reloc_type
= BFD_RELOC_UNUSED
;
6690 else if (mips_opts
.micromips
6692 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6693 || *reloc_type
> BFD_RELOC_UNUSED
)
6694 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6695 /* Don't try branch relaxation when users specify
6696 16-bit/32-bit instructions. */
6697 && !forced_insn_length
)
6699 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6700 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6701 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6702 int compact
= compact_branch_p (ip
);
6703 int al
= pinfo
& INSN_WRITE_GPR_31
;
6706 gas_assert (address_expr
!= NULL
);
6707 gas_assert (!mips_relax
.sequence
);
6709 relaxed_branch
= TRUE
;
6710 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6711 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6712 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6714 address_expr
->X_add_symbol
,
6715 address_expr
->X_add_number
);
6716 *reloc_type
= BFD_RELOC_UNUSED
;
6718 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6720 /* We need to set up a variant frag. */
6721 gas_assert (address_expr
!= NULL
);
6722 add_relaxed_insn (ip
, 4, 0,
6724 (*reloc_type
- BFD_RELOC_UNUSED
,
6725 forced_insn_length
== 2, forced_insn_length
== 4,
6726 delayed_branch_p (&history
[0]),
6727 history
[0].mips16_absolute_jump_p
),
6728 make_expr_symbol (address_expr
), 0);
6730 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6732 if (!delayed_branch_p (ip
))
6733 /* Make sure there is enough room to swap this instruction with
6734 a following jump instruction. */
6736 add_fixed_insn (ip
);
6740 if (mips_opts
.mips16
6741 && mips_opts
.noreorder
6742 && delayed_branch_p (&history
[0]))
6743 as_warn (_("extended instruction in delay slot"));
6745 if (mips_relax
.sequence
)
6747 /* If we've reached the end of this frag, turn it into a variant
6748 frag and record the information for the instructions we've
6750 if (frag_room () < 4)
6751 relax_close_frag ();
6752 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6755 if (mips_relax
.sequence
!= 2)
6757 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6758 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6759 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6760 mips_macro_warning
.insns
[0]++;
6762 if (mips_relax
.sequence
!= 1)
6764 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6765 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6766 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6767 mips_macro_warning
.insns
[1]++;
6770 if (mips_opts
.mips16
)
6773 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6775 add_fixed_insn (ip
);
6778 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6780 bfd_reloc_code_real_type final_type
[3];
6781 reloc_howto_type
*howto0
;
6782 reloc_howto_type
*howto
;
6785 /* Perform any necessary conversion to microMIPS relocations
6786 and find out how many relocations there actually are. */
6787 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6788 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6790 /* In a compound relocation, it is the final (outermost)
6791 operator that determines the relocated field. */
6792 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6797 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6798 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6799 bfd_get_reloc_size (howto
),
6801 howto0
&& howto0
->pc_relative
,
6804 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6805 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6806 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6808 /* These relocations can have an addend that won't fit in
6809 4 octets for 64bit assembly. */
6811 && ! howto
->partial_inplace
6812 && (reloc_type
[0] == BFD_RELOC_16
6813 || reloc_type
[0] == BFD_RELOC_32
6814 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6815 || reloc_type
[0] == BFD_RELOC_GPREL16
6816 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6817 || reloc_type
[0] == BFD_RELOC_GPREL32
6818 || reloc_type
[0] == BFD_RELOC_64
6819 || reloc_type
[0] == BFD_RELOC_CTOR
6820 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6821 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6822 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6823 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6824 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6825 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6826 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6827 || hi16_reloc_p (reloc_type
[0])
6828 || lo16_reloc_p (reloc_type
[0])))
6829 ip
->fixp
[0]->fx_no_overflow
= 1;
6831 /* These relocations can have an addend that won't fit in 2 octets. */
6832 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6833 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6834 ip
->fixp
[0]->fx_no_overflow
= 1;
6836 if (mips_relax
.sequence
)
6838 if (mips_relax
.first_fixup
== 0)
6839 mips_relax
.first_fixup
= ip
->fixp
[0];
6841 else if (reloc_needs_lo_p (*reloc_type
))
6843 struct mips_hi_fixup
*hi_fixup
;
6845 /* Reuse the last entry if it already has a matching %lo. */
6846 hi_fixup
= mips_hi_fixup_list
;
6848 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6850 hi_fixup
= ((struct mips_hi_fixup
*)
6851 xmalloc (sizeof (struct mips_hi_fixup
)));
6852 hi_fixup
->next
= mips_hi_fixup_list
;
6853 mips_hi_fixup_list
= hi_fixup
;
6855 hi_fixup
->fixp
= ip
->fixp
[0];
6856 hi_fixup
->seg
= now_seg
;
6859 /* Add fixups for the second and third relocations, if given.
6860 Note that the ABI allows the second relocation to be
6861 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6862 moment we only use RSS_UNDEF, but we could add support
6863 for the others if it ever becomes necessary. */
6864 for (i
= 1; i
< 3; i
++)
6865 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6867 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6868 ip
->fixp
[0]->fx_size
, NULL
, 0,
6869 FALSE
, final_type
[i
]);
6871 /* Use fx_tcbit to mark compound relocs. */
6872 ip
->fixp
[0]->fx_tcbit
= 1;
6873 ip
->fixp
[i
]->fx_tcbit
= 1;
6878 /* Update the register mask information. */
6879 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6880 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6885 insert_into_history (0, 1, ip
);
6888 case APPEND_ADD_WITH_NOP
:
6890 struct mips_cl_insn
*nop
;
6892 insert_into_history (0, 1, ip
);
6893 nop
= get_delay_slot_nop (ip
);
6894 add_fixed_insn (nop
);
6895 insert_into_history (0, 1, nop
);
6896 if (mips_relax
.sequence
)
6897 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6901 case APPEND_ADD_COMPACT
:
6902 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6903 gas_assert (mips_opts
.mips16
);
6904 ip
->insn_opcode
|= 0x0080;
6905 find_altered_mips16_opcode (ip
);
6907 insert_into_history (0, 1, ip
);
6912 struct mips_cl_insn delay
= history
[0];
6913 if (mips_opts
.mips16
)
6915 know (delay
.frag
== ip
->frag
);
6916 move_insn (ip
, delay
.frag
, delay
.where
);
6917 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6919 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6921 /* Add the delay slot instruction to the end of the
6922 current frag and shrink the fixed part of the
6923 original frag. If the branch occupies the tail of
6924 the latter, move it backwards to cover the gap. */
6925 delay
.frag
->fr_fix
-= branch_disp
;
6926 if (delay
.frag
== ip
->frag
)
6927 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6928 add_fixed_insn (&delay
);
6932 move_insn (&delay
, ip
->frag
,
6933 ip
->where
- branch_disp
+ insn_length (ip
));
6934 move_insn (ip
, history
[0].frag
, history
[0].where
);
6938 insert_into_history (0, 1, &delay
);
6943 /* If we have just completed an unconditional branch, clear the history. */
6944 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6945 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6949 mips_no_prev_insn ();
6951 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6952 history
[i
].cleared_p
= 1;
6955 /* We need to emit a label at the end of branch-likely macros. */
6956 if (emit_branch_likely_macro
)
6958 emit_branch_likely_macro
= FALSE
;
6959 micromips_add_label ();
6962 /* We just output an insn, so the next one doesn't have a label. */
6963 mips_clear_insn_labels ();
6966 /* Forget that there was any previous instruction or label.
6967 When BRANCH is true, the branch history is also flushed. */
6970 mips_no_prev_insn (void)
6972 prev_nop_frag
= NULL
;
6973 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6974 mips_clear_insn_labels ();
6977 /* This function must be called before we emit something other than
6978 instructions. It is like mips_no_prev_insn except that it inserts
6979 any NOPS that might be needed by previous instructions. */
6982 mips_emit_delays (void)
6984 if (! mips_opts
.noreorder
)
6986 int nops
= nops_for_insn (0, history
, NULL
);
6990 add_fixed_insn (NOP_INSN
);
6991 mips_move_text_labels ();
6994 mips_no_prev_insn ();
6997 /* Start a (possibly nested) noreorder block. */
7000 start_noreorder (void)
7002 if (mips_opts
.noreorder
== 0)
7007 /* None of the instructions before the .set noreorder can be moved. */
7008 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7009 history
[i
].fixed_p
= 1;
7011 /* Insert any nops that might be needed between the .set noreorder
7012 block and the previous instructions. We will later remove any
7013 nops that turn out not to be needed. */
7014 nops
= nops_for_insn (0, history
, NULL
);
7017 if (mips_optimize
!= 0)
7019 /* Record the frag which holds the nop instructions, so
7020 that we can remove them if we don't need them. */
7021 frag_grow (nops
* NOP_INSN_SIZE
);
7022 prev_nop_frag
= frag_now
;
7023 prev_nop_frag_holds
= nops
;
7024 prev_nop_frag_required
= 0;
7025 prev_nop_frag_since
= 0;
7028 for (; nops
> 0; --nops
)
7029 add_fixed_insn (NOP_INSN
);
7031 /* Move on to a new frag, so that it is safe to simply
7032 decrease the size of prev_nop_frag. */
7033 frag_wane (frag_now
);
7035 mips_move_text_labels ();
7037 mips_mark_labels ();
7038 mips_clear_insn_labels ();
7040 mips_opts
.noreorder
++;
7041 mips_any_noreorder
= 1;
7044 /* End a nested noreorder block. */
7047 end_noreorder (void)
7049 mips_opts
.noreorder
--;
7050 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7052 /* Commit to inserting prev_nop_frag_required nops and go back to
7053 handling nop insertion the .set reorder way. */
7054 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7056 insert_into_history (prev_nop_frag_since
,
7057 prev_nop_frag_required
, NOP_INSN
);
7058 prev_nop_frag
= NULL
;
7062 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7063 higher bits unset. */
7066 normalize_constant_expr (expressionS
*ex
)
7068 if (ex
->X_op
== O_constant
7069 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7070 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7074 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7075 all higher bits unset. */
7078 normalize_address_expr (expressionS
*ex
)
7080 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7081 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7082 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7083 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7087 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7088 Return true if the match was successful.
7090 OPCODE_EXTRA is a value that should be ORed into the opcode
7091 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7092 there are more alternatives after OPCODE and SOFT_MATCH is
7093 as for mips_arg_info. */
7096 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7097 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7098 bfd_boolean lax_match
, bfd_boolean complete_p
)
7101 struct mips_arg_info arg
;
7102 const struct mips_operand
*operand
;
7105 imm_expr
.X_op
= O_absent
;
7106 offset_expr
.X_op
= O_absent
;
7107 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7108 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7109 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7111 create_insn (insn
, opcode
);
7112 /* When no opcode suffix is specified, assume ".xyzw". */
7113 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7114 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7116 insn
->insn_opcode
|= opcode_extra
;
7117 memset (&arg
, 0, sizeof (arg
));
7121 arg
.last_regno
= ILLEGAL_REG
;
7122 arg
.dest_regno
= ILLEGAL_REG
;
7123 arg
.lax_match
= lax_match
;
7124 for (args
= opcode
->args
;; ++args
)
7126 if (arg
.token
->type
== OT_END
)
7128 /* Handle unary instructions in which only one operand is given.
7129 The source is then the same as the destination. */
7130 if (arg
.opnum
== 1 && *args
== ',')
7132 operand
= (mips_opts
.micromips
7133 ? decode_micromips_operand (args
+ 1)
7134 : decode_mips_operand (args
+ 1));
7135 if (operand
&& mips_optional_operand_p (operand
))
7143 /* Treat elided base registers as $0. */
7144 if (strcmp (args
, "(b)") == 0)
7152 /* The register suffix is optional. */
7157 /* Fail the match if there were too few operands. */
7161 /* Successful match. */
7164 clear_insn_error ();
7165 if (arg
.dest_regno
== arg
.last_regno
7166 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7170 (0, _("source and destination must be different"));
7171 else if (arg
.last_regno
== 31)
7173 (0, _("a destination register must be supplied"));
7175 else if (arg
.last_regno
== 31
7176 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7177 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7178 set_insn_error (0, _("the source register must not be $31"));
7179 check_completed_insn (&arg
);
7183 /* Fail the match if the line has too many operands. */
7187 /* Handle characters that need to match exactly. */
7188 if (*args
== '(' || *args
== ')' || *args
== ',')
7190 if (match_char (&arg
, *args
))
7197 if (arg
.token
->type
== OT_DOUBLE_CHAR
7198 && arg
.token
->u
.ch
== *args
)
7206 /* Handle special macro operands. Work out the properties of
7215 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7221 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7223 imm_expr
.X_op
= O_constant
;
7224 if (HAVE_32BIT_GPRS
)
7225 normalize_constant_expr (&imm_expr
);
7229 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7231 /* Assume that the offset has been elided and that what
7232 we saw was a base register. The match will fail later
7233 if that assumption turns out to be wrong. */
7234 offset_expr
.X_op
= O_constant
;
7235 offset_expr
.X_add_number
= 0;
7239 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7241 normalize_address_expr (&offset_expr
);
7246 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7252 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7258 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7264 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7270 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7274 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7278 gas_assert (mips_opts
.micromips
);
7284 if (!forced_insn_length
)
7285 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7287 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7289 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7295 operand
= (mips_opts
.micromips
7296 ? decode_micromips_operand (args
)
7297 : decode_mips_operand (args
));
7301 /* Skip prefixes. */
7302 if (*args
== '+' || *args
== 'm')
7305 if (mips_optional_operand_p (operand
)
7307 && (arg
.token
[0].type
!= OT_REG
7308 || arg
.token
[1].type
== OT_END
))
7310 /* Assume that the register has been elided and is the
7311 same as the first operand. */
7316 if (!match_operand (&arg
, operand
))
7321 /* Like match_insn, but for MIPS16. */
7324 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7325 struct mips_operand_token
*tokens
)
7328 const struct mips_operand
*operand
;
7329 const struct mips_operand
*ext_operand
;
7330 struct mips_arg_info arg
;
7333 create_insn (insn
, opcode
);
7334 imm_expr
.X_op
= O_absent
;
7335 offset_expr
.X_op
= O_absent
;
7336 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7337 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7338 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7341 memset (&arg
, 0, sizeof (arg
));
7345 arg
.last_regno
= ILLEGAL_REG
;
7346 arg
.dest_regno
= ILLEGAL_REG
;
7348 for (args
= opcode
->args
;; ++args
)
7352 if (arg
.token
->type
== OT_END
)
7356 /* Handle unary instructions in which only one operand is given.
7357 The source is then the same as the destination. */
7358 if (arg
.opnum
== 1 && *args
== ',')
7360 operand
= decode_mips16_operand (args
[1], FALSE
);
7361 if (operand
&& mips_optional_operand_p (operand
))
7369 /* Fail the match if there were too few operands. */
7373 /* Successful match. Stuff the immediate value in now, if
7375 clear_insn_error ();
7376 if (opcode
->pinfo
== INSN_MACRO
)
7378 gas_assert (relax_char
== 0 || relax_char
== 'p');
7379 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7382 && offset_expr
.X_op
== O_constant
7383 && calculate_reloc (*offset_reloc
,
7384 offset_expr
.X_add_number
,
7387 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7388 forced_insn_length
, &insn
->insn_opcode
);
7389 offset_expr
.X_op
= O_absent
;
7390 *offset_reloc
= BFD_RELOC_UNUSED
;
7392 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7394 if (forced_insn_length
== 2)
7395 set_insn_error (0, _("invalid unextended operand value"));
7396 forced_insn_length
= 4;
7397 insn
->insn_opcode
|= MIPS16_EXTEND
;
7399 else if (relax_char
)
7400 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7402 check_completed_insn (&arg
);
7406 /* Fail the match if the line has too many operands. */
7410 /* Handle characters that need to match exactly. */
7411 if (*args
== '(' || *args
== ')' || *args
== ',')
7413 if (match_char (&arg
, *args
))
7431 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7433 imm_expr
.X_op
= O_constant
;
7434 if (HAVE_32BIT_GPRS
)
7435 normalize_constant_expr (&imm_expr
);
7440 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7441 insn
->insn_opcode
<<= 16;
7445 operand
= decode_mips16_operand (c
, FALSE
);
7449 /* '6' is a special case. It is used for BREAK and SDBBP,
7450 whose operands are only meaningful to the software that decodes
7451 them. This means that there is no architectural reason why
7452 they cannot be prefixed by EXTEND, but in practice,
7453 exception handlers will only look at the instruction
7454 itself. We therefore allow '6' to be extended when
7455 disassembling but not when assembling. */
7456 if (operand
->type
!= OP_PCREL
&& c
!= '6')
7458 ext_operand
= decode_mips16_operand (c
, TRUE
);
7459 if (operand
!= ext_operand
)
7461 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7463 offset_expr
.X_op
= O_constant
;
7464 offset_expr
.X_add_number
= 0;
7469 /* We need the OT_INTEGER check because some MIPS16
7470 immediate variants are listed before the register ones. */
7471 if (arg
.token
->type
!= OT_INTEGER
7472 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
7475 /* '8' is used for SLTI(U) and has traditionally not
7476 been allowed to take relocation operators. */
7477 if (offset_reloc
[0] != BFD_RELOC_UNUSED
7478 && (ext_operand
->size
!= 16 || c
== '8'))
7486 if (mips_optional_operand_p (operand
)
7488 && (arg
.token
[0].type
!= OT_REG
7489 || arg
.token
[1].type
== OT_END
))
7491 /* Assume that the register has been elided and is the
7492 same as the first operand. */
7497 if (!match_operand (&arg
, operand
))
7502 /* Record that the current instruction is invalid for the current ISA. */
7505 match_invalid_for_isa (void)
7508 (0, _("opcode not supported on this processor: %s (%s)"),
7509 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7510 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7513 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
7514 Return true if a definite match or failure was found, storing any match
7515 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
7516 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
7517 tried and failed to match under normal conditions and now want to try a
7518 more relaxed match. */
7521 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7522 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
7523 int opcode_extra
, bfd_boolean lax_match
)
7525 const struct mips_opcode
*opcode
;
7526 const struct mips_opcode
*invalid_delay_slot
;
7527 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
7529 /* Search for a match, ignoring alternatives that don't satisfy the
7530 current ISA or forced_length. */
7531 invalid_delay_slot
= 0;
7532 seen_valid_for_isa
= FALSE
;
7533 seen_valid_for_size
= FALSE
;
7537 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7538 if (is_opcode_valid (opcode
))
7540 seen_valid_for_isa
= TRUE
;
7541 if (is_size_valid (opcode
))
7543 bfd_boolean delay_slot_ok
;
7545 seen_valid_for_size
= TRUE
;
7546 delay_slot_ok
= is_delay_slot_valid (opcode
);
7547 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
7548 lax_match
, delay_slot_ok
))
7552 if (!invalid_delay_slot
)
7553 invalid_delay_slot
= opcode
;
7562 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
7564 /* If the only matches we found had the wrong length for the delay slot,
7565 pick the first such match. We'll issue an appropriate warning later. */
7566 if (invalid_delay_slot
)
7568 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
7574 /* Handle the case where we didn't try to match an instruction because
7575 all the alternatives were incompatible with the current ISA. */
7576 if (!seen_valid_for_isa
)
7578 match_invalid_for_isa ();
7582 /* Handle the case where we didn't try to match an instruction because
7583 all the alternatives were of the wrong size. */
7584 if (!seen_valid_for_size
)
7586 if (mips_opts
.insn32
)
7587 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
7590 (0, _("unrecognized %d-bit version of microMIPS opcode"),
7591 8 * forced_insn_length
);
7598 /* Like match_insns, but for MIPS16. */
7601 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7602 struct mips_operand_token
*tokens
)
7604 const struct mips_opcode
*opcode
;
7605 bfd_boolean seen_valid_for_isa
;
7607 /* Search for a match, ignoring alternatives that don't satisfy the
7608 current ISA. There are no separate entries for extended forms so
7609 we deal with forced_length later. */
7610 seen_valid_for_isa
= FALSE
;
7614 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7615 if (is_opcode_valid_16 (opcode
))
7617 seen_valid_for_isa
= TRUE
;
7618 if (match_mips16_insn (insn
, opcode
, tokens
))
7623 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
7624 && strcmp (opcode
->name
, first
->name
) == 0);
7626 /* Handle the case where we didn't try to match an instruction because
7627 all the alternatives were incompatible with the current ISA. */
7628 if (!seen_valid_for_isa
)
7630 match_invalid_for_isa ();
7637 /* Set up global variables for the start of a new macro. */
7642 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
7643 memset (&mips_macro_warning
.first_insn_sizes
, 0,
7644 sizeof (mips_macro_warning
.first_insn_sizes
));
7645 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
7646 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
7647 && delayed_branch_p (&history
[0]));
7648 switch (history
[0].insn_mo
->pinfo2
7649 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
7651 case INSN2_BRANCH_DELAY_32BIT
:
7652 mips_macro_warning
.delay_slot_length
= 4;
7654 case INSN2_BRANCH_DELAY_16BIT
:
7655 mips_macro_warning
.delay_slot_length
= 2;
7658 mips_macro_warning
.delay_slot_length
= 0;
7661 mips_macro_warning
.first_frag
= NULL
;
7664 /* Given that a macro is longer than one instruction or of the wrong size,
7665 return the appropriate warning for it. Return null if no warning is
7666 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7667 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7668 and RELAX_NOMACRO. */
7671 macro_warning (relax_substateT subtype
)
7673 if (subtype
& RELAX_DELAY_SLOT
)
7674 return _("macro instruction expanded into multiple instructions"
7675 " in a branch delay slot");
7676 else if (subtype
& RELAX_NOMACRO
)
7677 return _("macro instruction expanded into multiple instructions");
7678 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
7679 | RELAX_DELAY_SLOT_SIZE_SECOND
))
7680 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
7681 ? _("macro instruction expanded into a wrong size instruction"
7682 " in a 16-bit branch delay slot")
7683 : _("macro instruction expanded into a wrong size instruction"
7684 " in a 32-bit branch delay slot"));
7689 /* Finish up a macro. Emit warnings as appropriate. */
7694 /* Relaxation warning flags. */
7695 relax_substateT subtype
= 0;
7697 /* Check delay slot size requirements. */
7698 if (mips_macro_warning
.delay_slot_length
== 2)
7699 subtype
|= RELAX_DELAY_SLOT_16BIT
;
7700 if (mips_macro_warning
.delay_slot_length
!= 0)
7702 if (mips_macro_warning
.delay_slot_length
7703 != mips_macro_warning
.first_insn_sizes
[0])
7704 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
7705 if (mips_macro_warning
.delay_slot_length
7706 != mips_macro_warning
.first_insn_sizes
[1])
7707 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
7710 /* Check instruction count requirements. */
7711 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
7713 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
7714 subtype
|= RELAX_SECOND_LONGER
;
7715 if (mips_opts
.warn_about_macros
)
7716 subtype
|= RELAX_NOMACRO
;
7717 if (mips_macro_warning
.delay_slot_p
)
7718 subtype
|= RELAX_DELAY_SLOT
;
7721 /* If both alternatives fail to fill a delay slot correctly,
7722 emit the warning now. */
7723 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
7724 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
7729 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
7730 | RELAX_DELAY_SLOT_SIZE_FIRST
7731 | RELAX_DELAY_SLOT_SIZE_SECOND
);
7732 msg
= macro_warning (s
);
7734 as_warn ("%s", msg
);
7738 /* If both implementations are longer than 1 instruction, then emit the
7740 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
7745 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
7746 msg
= macro_warning (s
);
7748 as_warn ("%s", msg
);
7752 /* If any flags still set, then one implementation might need a warning
7753 and the other either will need one of a different kind or none at all.
7754 Pass any remaining flags over to relaxation. */
7755 if (mips_macro_warning
.first_frag
!= NULL
)
7756 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7759 /* Instruction operand formats used in macros that vary between
7760 standard MIPS and microMIPS code. */
7762 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7763 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7764 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7765 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7766 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7767 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7768 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7769 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7771 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7772 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7773 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7774 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7775 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7776 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7777 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7778 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7780 /* Read a macro's relocation codes from *ARGS and store them in *R.
7781 The first argument in *ARGS will be either the code for a single
7782 relocation or -1 followed by the three codes that make up a
7783 composite relocation. */
7786 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7790 next
= va_arg (*args
, int);
7792 r
[0] = (bfd_reloc_code_real_type
) next
;
7795 for (i
= 0; i
< 3; i
++)
7796 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7797 /* This function is only used for 16-bit relocation fields.
7798 To make the macro code simpler, treat an unrelocated value
7799 in the same way as BFD_RELOC_LO16. */
7800 if (r
[0] == BFD_RELOC_UNUSED
)
7801 r
[0] = BFD_RELOC_LO16
;
7805 /* Build an instruction created by a macro expansion. This is passed
7806 a pointer to the count of instructions created so far, an
7807 expression, the name of the instruction to build, an operand format
7808 string, and corresponding arguments. */
7811 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7813 const struct mips_opcode
*mo
= NULL
;
7814 bfd_reloc_code_real_type r
[3];
7815 const struct mips_opcode
*amo
;
7816 const struct mips_operand
*operand
;
7817 struct hash_control
*hash
;
7818 struct mips_cl_insn insn
;
7822 va_start (args
, fmt
);
7824 if (mips_opts
.mips16
)
7826 mips16_macro_build (ep
, name
, fmt
, &args
);
7831 r
[0] = BFD_RELOC_UNUSED
;
7832 r
[1] = BFD_RELOC_UNUSED
;
7833 r
[2] = BFD_RELOC_UNUSED
;
7834 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7835 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7837 gas_assert (strcmp (name
, amo
->name
) == 0);
7841 /* Search until we get a match for NAME. It is assumed here that
7842 macros will never generate MDMX, MIPS-3D, or MT instructions.
7843 We try to match an instruction that fulfils the branch delay
7844 slot instruction length requirement (if any) of the previous
7845 instruction. While doing this we record the first instruction
7846 seen that matches all the other conditions and use it anyway
7847 if the requirement cannot be met; we will issue an appropriate
7848 warning later on. */
7849 if (strcmp (fmt
, amo
->args
) == 0
7850 && amo
->pinfo
!= INSN_MACRO
7851 && is_opcode_valid (amo
)
7852 && is_size_valid (amo
))
7854 if (is_delay_slot_valid (amo
))
7864 gas_assert (amo
->name
);
7866 while (strcmp (name
, amo
->name
) == 0);
7869 create_insn (&insn
, mo
);
7882 macro_read_relocs (&args
, r
);
7883 gas_assert (*r
== BFD_RELOC_GPREL16
7884 || *r
== BFD_RELOC_MIPS_HIGHER
7885 || *r
== BFD_RELOC_HI16_S
7886 || *r
== BFD_RELOC_LO16
7887 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7891 macro_read_relocs (&args
, r
);
7895 macro_read_relocs (&args
, r
);
7896 gas_assert (ep
!= NULL
7897 && (ep
->X_op
== O_constant
7898 || (ep
->X_op
== O_symbol
7899 && (*r
== BFD_RELOC_MIPS_HIGHEST
7900 || *r
== BFD_RELOC_HI16_S
7901 || *r
== BFD_RELOC_HI16
7902 || *r
== BFD_RELOC_GPREL16
7903 || *r
== BFD_RELOC_MIPS_GOT_HI16
7904 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7908 gas_assert (ep
!= NULL
);
7911 * This allows macro() to pass an immediate expression for
7912 * creating short branches without creating a symbol.
7914 * We don't allow branch relaxation for these branches, as
7915 * they should only appear in ".set nomacro" anyway.
7917 if (ep
->X_op
== O_constant
)
7919 /* For microMIPS we always use relocations for branches.
7920 So we should not resolve immediate values. */
7921 gas_assert (!mips_opts
.micromips
);
7923 if ((ep
->X_add_number
& 3) != 0)
7924 as_bad (_("branch to misaligned address (0x%lx)"),
7925 (unsigned long) ep
->X_add_number
);
7926 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7927 as_bad (_("branch address range overflow (0x%lx)"),
7928 (unsigned long) ep
->X_add_number
);
7929 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
7933 *r
= BFD_RELOC_16_PCREL_S2
;
7937 gas_assert (ep
!= NULL
);
7938 *r
= BFD_RELOC_MIPS_JMP
;
7942 operand
= (mips_opts
.micromips
7943 ? decode_micromips_operand (fmt
)
7944 : decode_mips_operand (fmt
));
7948 uval
= va_arg (args
, int);
7949 if (operand
->type
== OP_CLO_CLZ_DEST
)
7950 uval
|= (uval
<< 5);
7951 insn_insert_operand (&insn
, operand
, uval
);
7953 if (*fmt
== '+' || *fmt
== 'm')
7959 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7961 append_insn (&insn
, ep
, r
, TRUE
);
7965 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
7968 struct mips_opcode
*mo
;
7969 struct mips_cl_insn insn
;
7970 const struct mips_operand
*operand
;
7971 bfd_reloc_code_real_type r
[3]
7972 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
7974 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
7976 gas_assert (strcmp (name
, mo
->name
) == 0);
7978 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
7981 gas_assert (mo
->name
);
7982 gas_assert (strcmp (name
, mo
->name
) == 0);
7985 create_insn (&insn
, mo
);
8023 gas_assert (ep
!= NULL
);
8025 if (ep
->X_op
!= O_constant
)
8026 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8027 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8029 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8031 *r
= BFD_RELOC_UNUSED
;
8037 operand
= decode_mips16_operand (c
, FALSE
);
8041 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8046 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8048 append_insn (&insn
, ep
, r
, TRUE
);
8052 * Generate a "jalr" instruction with a relocation hint to the called
8053 * function. This occurs in NewABI PIC code.
8056 macro_build_jalr (expressionS
*ep
, int cprestore
)
8058 static const bfd_reloc_code_real_type jalr_relocs
[2]
8059 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8060 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8064 if (MIPS_JALR_HINT_P (ep
))
8069 if (mips_opts
.micromips
)
8071 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8072 ? "jalr" : "jalrs");
8073 if (MIPS_JALR_HINT_P (ep
)
8075 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8076 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8078 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8081 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8082 if (MIPS_JALR_HINT_P (ep
))
8083 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8087 * Generate a "lui" instruction.
8090 macro_build_lui (expressionS
*ep
, int regnum
)
8092 gas_assert (! mips_opts
.mips16
);
8094 if (ep
->X_op
!= O_constant
)
8096 gas_assert (ep
->X_op
== O_symbol
);
8097 /* _gp_disp is a special case, used from s_cpload.
8098 __gnu_local_gp is used if mips_no_shared. */
8099 gas_assert (mips_pic
== NO_PIC
8101 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8102 || (! mips_in_shared
8103 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8104 "__gnu_local_gp") == 0));
8107 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8110 /* Generate a sequence of instructions to do a load or store from a constant
8111 offset off of a base register (breg) into/from a target register (treg),
8112 using AT if necessary. */
8114 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8115 int treg
, int breg
, int dbl
)
8117 gas_assert (ep
->X_op
== O_constant
);
8119 /* Sign-extending 32-bit constants makes their handling easier. */
8121 normalize_constant_expr (ep
);
8123 /* Right now, this routine can only handle signed 32-bit constants. */
8124 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8125 as_warn (_("operand overflow"));
8127 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8129 /* Signed 16-bit offset will fit in the op. Easy! */
8130 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8134 /* 32-bit offset, need multiple instructions and AT, like:
8135 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8136 addu $tempreg,$tempreg,$breg
8137 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8138 to handle the complete offset. */
8139 macro_build_lui (ep
, AT
);
8140 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8141 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8144 as_bad (_("macro used $at after \".set noat\""));
8149 * Generates code to set the $at register to true (one)
8150 * if reg is less than the immediate expression.
8153 set_at (int reg
, int unsignedp
)
8155 if (imm_expr
.X_add_number
>= -0x8000
8156 && imm_expr
.X_add_number
< 0x8000)
8157 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8158 AT
, reg
, BFD_RELOC_LO16
);
8161 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8162 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8166 /* Count the leading zeroes by performing a binary chop. This is a
8167 bulky bit of source, but performance is a LOT better for the
8168 majority of values than a simple loop to count the bits:
8169 for (lcnt = 0; (lcnt < 32); lcnt++)
8170 if ((v) & (1 << (31 - lcnt)))
8172 However it is not code size friendly, and the gain will drop a bit
8173 on certain cached systems.
8175 #define COUNT_TOP_ZEROES(v) \
8176 (((v) & ~0xffff) == 0 \
8177 ? ((v) & ~0xff) == 0 \
8178 ? ((v) & ~0xf) == 0 \
8179 ? ((v) & ~0x3) == 0 \
8180 ? ((v) & ~0x1) == 0 \
8185 : ((v) & ~0x7) == 0 \
8188 : ((v) & ~0x3f) == 0 \
8189 ? ((v) & ~0x1f) == 0 \
8192 : ((v) & ~0x7f) == 0 \
8195 : ((v) & ~0xfff) == 0 \
8196 ? ((v) & ~0x3ff) == 0 \
8197 ? ((v) & ~0x1ff) == 0 \
8200 : ((v) & ~0x7ff) == 0 \
8203 : ((v) & ~0x3fff) == 0 \
8204 ? ((v) & ~0x1fff) == 0 \
8207 : ((v) & ~0x7fff) == 0 \
8210 : ((v) & ~0xffffff) == 0 \
8211 ? ((v) & ~0xfffff) == 0 \
8212 ? ((v) & ~0x3ffff) == 0 \
8213 ? ((v) & ~0x1ffff) == 0 \
8216 : ((v) & ~0x7ffff) == 0 \
8219 : ((v) & ~0x3fffff) == 0 \
8220 ? ((v) & ~0x1fffff) == 0 \
8223 : ((v) & ~0x7fffff) == 0 \
8226 : ((v) & ~0xfffffff) == 0 \
8227 ? ((v) & ~0x3ffffff) == 0 \
8228 ? ((v) & ~0x1ffffff) == 0 \
8231 : ((v) & ~0x7ffffff) == 0 \
8234 : ((v) & ~0x3fffffff) == 0 \
8235 ? ((v) & ~0x1fffffff) == 0 \
8238 : ((v) & ~0x7fffffff) == 0 \
8243 * This routine generates the least number of instructions necessary to load
8244 * an absolute expression value into a register.
8247 load_register (int reg
, expressionS
*ep
, int dbl
)
8250 expressionS hi32
, lo32
;
8252 if (ep
->X_op
!= O_big
)
8254 gas_assert (ep
->X_op
== O_constant
);
8256 /* Sign-extending 32-bit constants makes their handling easier. */
8258 normalize_constant_expr (ep
);
8260 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8262 /* We can handle 16 bit signed values with an addiu to
8263 $zero. No need to ever use daddiu here, since $zero and
8264 the result are always correct in 32 bit mode. */
8265 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8268 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8270 /* We can handle 16 bit unsigned values with an ori to
8272 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8275 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8277 /* 32 bit values require an lui. */
8278 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8279 if ((ep
->X_add_number
& 0xffff) != 0)
8280 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8285 /* The value is larger than 32 bits. */
8287 if (!dbl
|| HAVE_32BIT_GPRS
)
8291 sprintf_vma (value
, ep
->X_add_number
);
8292 as_bad (_("number (0x%s) larger than 32 bits"), value
);
8293 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8297 if (ep
->X_op
!= O_big
)
8300 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8301 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8302 hi32
.X_add_number
&= 0xffffffff;
8304 lo32
.X_add_number
&= 0xffffffff;
8308 gas_assert (ep
->X_add_number
> 2);
8309 if (ep
->X_add_number
== 3)
8310 generic_bignum
[3] = 0;
8311 else if (ep
->X_add_number
> 4)
8312 as_bad (_("number larger than 64 bits"));
8313 lo32
.X_op
= O_constant
;
8314 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8315 hi32
.X_op
= O_constant
;
8316 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8319 if (hi32
.X_add_number
== 0)
8324 unsigned long hi
, lo
;
8326 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8328 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8330 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8333 if (lo32
.X_add_number
& 0x80000000)
8335 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8336 if (lo32
.X_add_number
& 0xffff)
8337 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8342 /* Check for 16bit shifted constant. We know that hi32 is
8343 non-zero, so start the mask on the first bit of the hi32
8348 unsigned long himask
, lomask
;
8352 himask
= 0xffff >> (32 - shift
);
8353 lomask
= (0xffff << shift
) & 0xffffffff;
8357 himask
= 0xffff << (shift
- 32);
8360 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8361 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8365 tmp
.X_op
= O_constant
;
8367 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8368 | (lo32
.X_add_number
>> shift
));
8370 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8371 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8372 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8373 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8378 while (shift
<= (64 - 16));
8380 /* Find the bit number of the lowest one bit, and store the
8381 shifted value in hi/lo. */
8382 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8383 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8387 while ((lo
& 1) == 0)
8392 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8398 while ((hi
& 1) == 0)
8407 /* Optimize if the shifted value is a (power of 2) - 1. */
8408 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8409 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8411 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8416 /* This instruction will set the register to be all
8418 tmp
.X_op
= O_constant
;
8419 tmp
.X_add_number
= (offsetT
) -1;
8420 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8424 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8425 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
8427 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
8428 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8433 /* Sign extend hi32 before calling load_register, because we can
8434 generally get better code when we load a sign extended value. */
8435 if ((hi32
.X_add_number
& 0x80000000) != 0)
8436 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
8437 load_register (reg
, &hi32
, 0);
8440 if ((lo32
.X_add_number
& 0xffff0000) == 0)
8444 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
8452 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
8454 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8455 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
8461 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
8465 mid16
.X_add_number
>>= 16;
8466 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8467 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8470 if ((lo32
.X_add_number
& 0xffff) != 0)
8471 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8475 load_delay_nop (void)
8477 if (!gpr_interlocks
)
8478 macro_build (NULL
, "nop", "");
8481 /* Load an address into a register. */
8484 load_address (int reg
, expressionS
*ep
, int *used_at
)
8486 if (ep
->X_op
!= O_constant
8487 && ep
->X_op
!= O_symbol
)
8489 as_bad (_("expression too complex"));
8490 ep
->X_op
= O_constant
;
8493 if (ep
->X_op
== O_constant
)
8495 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
8499 if (mips_pic
== NO_PIC
)
8501 /* If this is a reference to a GP relative symbol, we want
8502 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8504 lui $reg,<sym> (BFD_RELOC_HI16_S)
8505 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8506 If we have an addend, we always use the latter form.
8508 With 64bit address space and a usable $at we want
8509 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8510 lui $at,<sym> (BFD_RELOC_HI16_S)
8511 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8512 daddiu $at,<sym> (BFD_RELOC_LO16)
8516 If $at is already in use, we use a path which is suboptimal
8517 on superscalar processors.
8518 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8519 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8521 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8523 daddiu $reg,<sym> (BFD_RELOC_LO16)
8525 For GP relative symbols in 64bit address space we can use
8526 the same sequence as in 32bit address space. */
8527 if (HAVE_64BIT_SYMBOLS
)
8529 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8530 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8532 relax_start (ep
->X_add_symbol
);
8533 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8534 mips_gp_register
, BFD_RELOC_GPREL16
);
8538 if (*used_at
== 0 && mips_opts
.at
)
8540 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8541 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
8542 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8543 BFD_RELOC_MIPS_HIGHER
);
8544 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
8545 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
8546 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
8551 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8552 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8553 BFD_RELOC_MIPS_HIGHER
);
8554 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8555 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
8556 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8557 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
8560 if (mips_relax
.sequence
)
8565 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8566 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8568 relax_start (ep
->X_add_symbol
);
8569 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8570 mips_gp_register
, BFD_RELOC_GPREL16
);
8573 macro_build_lui (ep
, reg
);
8574 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
8575 reg
, reg
, BFD_RELOC_LO16
);
8576 if (mips_relax
.sequence
)
8580 else if (!mips_big_got
)
8584 /* If this is a reference to an external symbol, we want
8585 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8587 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8589 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8590 If there is a constant, it must be added in after.
8592 If we have NewABI, we want
8593 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8594 unless we're referencing a global symbol with a non-zero
8595 offset, in which case cst must be added separately. */
8598 if (ep
->X_add_number
)
8600 ex
.X_add_number
= ep
->X_add_number
;
8601 ep
->X_add_number
= 0;
8602 relax_start (ep
->X_add_symbol
);
8603 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8604 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8605 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8606 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8607 ex
.X_op
= O_constant
;
8608 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8609 reg
, reg
, BFD_RELOC_LO16
);
8610 ep
->X_add_number
= ex
.X_add_number
;
8613 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8614 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8615 if (mips_relax
.sequence
)
8620 ex
.X_add_number
= ep
->X_add_number
;
8621 ep
->X_add_number
= 0;
8622 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8623 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8625 relax_start (ep
->X_add_symbol
);
8627 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8631 if (ex
.X_add_number
!= 0)
8633 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8634 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8635 ex
.X_op
= O_constant
;
8636 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8637 reg
, reg
, BFD_RELOC_LO16
);
8641 else if (mips_big_got
)
8645 /* This is the large GOT case. If this is a reference to an
8646 external symbol, we want
8647 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8649 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8651 Otherwise, for a reference to a local symbol in old ABI, we want
8652 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8654 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8655 If there is a constant, it must be added in after.
8657 In the NewABI, for local symbols, with or without offsets, we want:
8658 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8659 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8663 ex
.X_add_number
= ep
->X_add_number
;
8664 ep
->X_add_number
= 0;
8665 relax_start (ep
->X_add_symbol
);
8666 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8668 reg
, reg
, mips_gp_register
);
8669 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8670 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8671 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8672 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8673 else if (ex
.X_add_number
)
8675 ex
.X_op
= O_constant
;
8676 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8680 ep
->X_add_number
= ex
.X_add_number
;
8682 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8683 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8684 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8685 BFD_RELOC_MIPS_GOT_OFST
);
8690 ex
.X_add_number
= ep
->X_add_number
;
8691 ep
->X_add_number
= 0;
8692 relax_start (ep
->X_add_symbol
);
8693 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8694 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8695 reg
, reg
, mips_gp_register
);
8696 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8697 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8699 if (reg_needs_delay (mips_gp_register
))
8701 /* We need a nop before loading from $gp. This special
8702 check is required because the lui which starts the main
8703 instruction stream does not refer to $gp, and so will not
8704 insert the nop which may be required. */
8705 macro_build (NULL
, "nop", "");
8707 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8708 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8710 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8714 if (ex
.X_add_number
!= 0)
8716 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8717 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8718 ex
.X_op
= O_constant
;
8719 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8727 if (!mips_opts
.at
&& *used_at
== 1)
8728 as_bad (_("macro used $at after \".set noat\""));
8731 /* Move the contents of register SOURCE into register DEST. */
8734 move_register (int dest
, int source
)
8736 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8737 instruction specifically requires a 32-bit one. */
8738 if (mips_opts
.micromips
8739 && !mips_opts
.insn32
8740 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8741 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8743 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8747 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8748 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8749 The two alternatives are:
8751 Global symbol Local sybmol
8752 ------------- ------------
8753 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8755 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8757 load_got_offset emits the first instruction and add_got_offset
8758 emits the second for a 16-bit offset or add_got_offset_hilo emits
8759 a sequence to add a 32-bit offset using a scratch register. */
8762 load_got_offset (int dest
, expressionS
*local
)
8767 global
.X_add_number
= 0;
8769 relax_start (local
->X_add_symbol
);
8770 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8771 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8773 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8774 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8779 add_got_offset (int dest
, expressionS
*local
)
8783 global
.X_op
= O_constant
;
8784 global
.X_op_symbol
= NULL
;
8785 global
.X_add_symbol
= NULL
;
8786 global
.X_add_number
= local
->X_add_number
;
8788 relax_start (local
->X_add_symbol
);
8789 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8790 dest
, dest
, BFD_RELOC_LO16
);
8792 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8797 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8800 int hold_mips_optimize
;
8802 global
.X_op
= O_constant
;
8803 global
.X_op_symbol
= NULL
;
8804 global
.X_add_symbol
= NULL
;
8805 global
.X_add_number
= local
->X_add_number
;
8807 relax_start (local
->X_add_symbol
);
8808 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8810 /* Set mips_optimize around the lui instruction to avoid
8811 inserting an unnecessary nop after the lw. */
8812 hold_mips_optimize
= mips_optimize
;
8814 macro_build_lui (&global
, tmp
);
8815 mips_optimize
= hold_mips_optimize
;
8816 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8819 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8822 /* Emit a sequence of instructions to emulate a branch likely operation.
8823 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8824 is its complementing branch with the original condition negated.
8825 CALL is set if the original branch specified the link operation.
8826 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8828 Code like this is produced in the noreorder mode:
8833 delay slot (executed only if branch taken)
8841 delay slot (executed only if branch taken)
8844 In the reorder mode the delay slot would be filled with a nop anyway,
8845 so code produced is simply:
8850 This function is used when producing code for the microMIPS ASE that
8851 does not implement branch likely instructions in hardware. */
8854 macro_build_branch_likely (const char *br
, const char *brneg
,
8855 int call
, expressionS
*ep
, const char *fmt
,
8856 unsigned int sreg
, unsigned int treg
)
8858 int noreorder
= mips_opts
.noreorder
;
8861 gas_assert (mips_opts
.micromips
);
8865 micromips_label_expr (&expr1
);
8866 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8867 macro_build (NULL
, "nop", "");
8868 macro_build (ep
, call
? "bal" : "b", "p");
8870 /* Set to true so that append_insn adds a label. */
8871 emit_branch_likely_macro
= TRUE
;
8875 macro_build (ep
, br
, fmt
, sreg
, treg
);
8876 macro_build (NULL
, "nop", "");
8881 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8882 the condition code tested. EP specifies the branch target. */
8885 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8912 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8915 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8916 the register tested. EP specifies the branch target. */
8919 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8921 const char *brneg
= NULL
;
8931 br
= mips_opts
.micromips
? "bgez" : "bgezl";
8935 gas_assert (mips_opts
.micromips
);
8936 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
8944 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
8951 br
= mips_opts
.micromips
? "blez" : "blezl";
8958 br
= mips_opts
.micromips
? "bltz" : "bltzl";
8962 gas_assert (mips_opts
.micromips
);
8963 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
8970 if (mips_opts
.micromips
&& brneg
)
8971 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
8973 macro_build (ep
, br
, "s,p", sreg
);
8976 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8977 TREG as the registers tested. EP specifies the branch target. */
8980 macro_build_branch_rsrt (int type
, expressionS
*ep
,
8981 unsigned int sreg
, unsigned int treg
)
8983 const char *brneg
= NULL
;
8995 br
= mips_opts
.micromips
? "beq" : "beql";
9004 br
= mips_opts
.micromips
? "bne" : "bnel";
9010 if (mips_opts
.micromips
&& brneg
)
9011 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9013 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9016 /* Return the high part that should be loaded in order to make the low
9017 part of VALUE accessible using an offset of OFFBITS bits. */
9020 offset_high_part (offsetT value
, unsigned int offbits
)
9027 bias
= 1 << (offbits
- 1);
9028 low_mask
= bias
* 2 - 1;
9029 return (value
+ bias
) & ~low_mask
;
9032 /* Return true if the value stored in offset_expr and offset_reloc
9033 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9034 amount that the caller wants to add without inducing overflow
9035 and ALIGN is the known alignment of the value in bytes. */
9038 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9042 /* Accept any relocation operator if overflow isn't a concern. */
9043 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9046 /* These relocations are guaranteed not to overflow in correct links. */
9047 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9048 || gprel16_reloc_p (*offset_reloc
))
9051 if (offset_expr
.X_op
== O_constant
9052 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9053 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9060 * This routine implements the seemingly endless macro or synthesized
9061 * instructions and addressing modes in the mips assembly language. Many
9062 * of these macros are simple and are similar to each other. These could
9063 * probably be handled by some kind of table or grammar approach instead of
9064 * this verbose method. Others are not simple macros but are more like
9065 * optimizing code generation.
9066 * One interesting optimization is when several store macros appear
9067 * consecutively that would load AT with the upper half of the same address.
9068 * The ensuing load upper instructions are ommited. This implies some kind
9069 * of global optimization. We currently only optimize within a single macro.
9070 * For many of the load and store macros if the address is specified as a
9071 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9072 * first load register 'at' with zero and use it as the base register. The
9073 * mips assembler simply uses register $zero. Just one tiny optimization
9077 macro (struct mips_cl_insn
*ip
, char *str
)
9079 const struct mips_operand_array
*operands
;
9080 unsigned int breg
, i
;
9081 unsigned int tempreg
;
9084 expressionS label_expr
;
9099 bfd_boolean large_offset
;
9101 int hold_mips_optimize
;
9103 unsigned int op
[MAX_OPERANDS
];
9105 gas_assert (! mips_opts
.mips16
);
9107 operands
= insn_operands (ip
);
9108 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9109 if (operands
->operand
[i
])
9110 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9114 mask
= ip
->insn_mo
->mask
;
9116 label_expr
.X_op
= O_constant
;
9117 label_expr
.X_op_symbol
= NULL
;
9118 label_expr
.X_add_symbol
= NULL
;
9119 label_expr
.X_add_number
= 0;
9121 expr1
.X_op
= O_constant
;
9122 expr1
.X_op_symbol
= NULL
;
9123 expr1
.X_add_symbol
= NULL
;
9124 expr1
.X_add_number
= 1;
9140 if (mips_opts
.micromips
)
9141 micromips_label_expr (&label_expr
);
9143 label_expr
.X_add_number
= 8;
9144 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9146 macro_build (NULL
, "nop", "");
9148 move_register (op
[0], op
[1]);
9149 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9150 if (mips_opts
.micromips
)
9151 micromips_add_label ();
9168 if (!mips_opts
.micromips
)
9170 if (imm_expr
.X_add_number
>= -0x200
9171 && imm_expr
.X_add_number
< 0x200)
9173 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9174 (int) imm_expr
.X_add_number
);
9183 if (imm_expr
.X_add_number
>= -0x8000
9184 && imm_expr
.X_add_number
< 0x8000)
9186 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9191 load_register (AT
, &imm_expr
, dbl
);
9192 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9211 if (imm_expr
.X_add_number
>= 0
9212 && imm_expr
.X_add_number
< 0x10000)
9214 if (mask
!= M_NOR_I
)
9215 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9218 macro_build (&imm_expr
, "ori", "t,r,i",
9219 op
[0], op
[1], BFD_RELOC_LO16
);
9220 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9226 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9227 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9231 switch (imm_expr
.X_add_number
)
9234 macro_build (NULL
, "nop", "");
9237 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9241 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9242 (int) imm_expr
.X_add_number
);
9245 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9246 (unsigned long) imm_expr
.X_add_number
);
9255 gas_assert (mips_opts
.micromips
);
9256 macro_build_branch_ccl (mask
, &offset_expr
,
9257 EXTRACT_OPERAND (1, BCC
, *ip
));
9264 if (imm_expr
.X_add_number
== 0)
9270 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
9275 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9282 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9283 else if (op
[0] == 0)
9284 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9288 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9289 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9290 &offset_expr
, AT
, ZERO
);
9300 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9306 /* Check for > max integer. */
9307 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9310 /* Result is always false. */
9312 macro_build (NULL
, "nop", "");
9314 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9317 ++imm_expr
.X_add_number
;
9321 if (mask
== M_BGEL_I
)
9323 if (imm_expr
.X_add_number
== 0)
9325 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9326 &offset_expr
, op
[0]);
9329 if (imm_expr
.X_add_number
== 1)
9331 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9332 &offset_expr
, op
[0]);
9335 if (imm_expr
.X_add_number
<= GPR_SMIN
)
9338 /* result is always true */
9339 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
9340 macro_build (&offset_expr
, "b", "p");
9345 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9346 &offset_expr
, AT
, ZERO
);
9354 else if (op
[0] == 0)
9355 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9356 &offset_expr
, ZERO
, op
[1]);
9360 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9361 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9362 &offset_expr
, AT
, ZERO
);
9371 && imm_expr
.X_add_number
== -1))
9373 ++imm_expr
.X_add_number
;
9377 if (mask
== M_BGEUL_I
)
9379 if (imm_expr
.X_add_number
== 0)
9381 else if (imm_expr
.X_add_number
== 1)
9382 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9383 &offset_expr
, op
[0], ZERO
);
9388 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9389 &offset_expr
, AT
, ZERO
);
9397 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9398 else if (op
[0] == 0)
9399 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9403 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9404 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9405 &offset_expr
, AT
, ZERO
);
9413 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9414 &offset_expr
, op
[0], ZERO
);
9415 else if (op
[0] == 0)
9420 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9421 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9422 &offset_expr
, AT
, ZERO
);
9430 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9431 else if (op
[0] == 0)
9432 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
9436 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9437 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9438 &offset_expr
, AT
, ZERO
);
9445 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9447 ++imm_expr
.X_add_number
;
9451 if (mask
== M_BLTL_I
)
9453 if (imm_expr
.X_add_number
== 0)
9454 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9455 else if (imm_expr
.X_add_number
== 1)
9456 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9461 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9462 &offset_expr
, AT
, ZERO
);
9470 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9471 &offset_expr
, op
[0], ZERO
);
9472 else if (op
[0] == 0)
9477 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9478 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9479 &offset_expr
, AT
, ZERO
);
9488 && imm_expr
.X_add_number
== -1))
9490 ++imm_expr
.X_add_number
;
9494 if (mask
== M_BLTUL_I
)
9496 if (imm_expr
.X_add_number
== 0)
9498 else if (imm_expr
.X_add_number
== 1)
9499 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9500 &offset_expr
, op
[0], ZERO
);
9505 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9506 &offset_expr
, AT
, ZERO
);
9514 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9515 else if (op
[0] == 0)
9516 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
9520 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9521 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9522 &offset_expr
, AT
, ZERO
);
9531 else if (op
[0] == 0)
9532 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9533 &offset_expr
, ZERO
, op
[1]);
9537 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9538 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9539 &offset_expr
, AT
, ZERO
);
9555 as_warn (_("divide by zero"));
9557 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9559 macro_build (NULL
, "break", BRK_FMT
, 7);
9566 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9567 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9571 if (mips_opts
.micromips
)
9572 micromips_label_expr (&label_expr
);
9574 label_expr
.X_add_number
= 8;
9575 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9576 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9577 macro_build (NULL
, "break", BRK_FMT
, 7);
9578 if (mips_opts
.micromips
)
9579 micromips_add_label ();
9581 expr1
.X_add_number
= -1;
9583 load_register (AT
, &expr1
, dbl
);
9584 if (mips_opts
.micromips
)
9585 micromips_label_expr (&label_expr
);
9587 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
9588 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
9591 expr1
.X_add_number
= 1;
9592 load_register (AT
, &expr1
, dbl
);
9593 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
9597 expr1
.X_add_number
= 0x80000000;
9598 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
9602 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
9603 /* We want to close the noreorder block as soon as possible, so
9604 that later insns are available for delay slot filling. */
9609 if (mips_opts
.micromips
)
9610 micromips_label_expr (&label_expr
);
9612 label_expr
.X_add_number
= 8;
9613 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
9614 macro_build (NULL
, "nop", "");
9616 /* We want to close the noreorder block as soon as possible, so
9617 that later insns are available for delay slot filling. */
9620 macro_build (NULL
, "break", BRK_FMT
, 6);
9622 if (mips_opts
.micromips
)
9623 micromips_add_label ();
9624 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9663 if (imm_expr
.X_add_number
== 0)
9665 as_warn (_("divide by zero"));
9667 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9669 macro_build (NULL
, "break", BRK_FMT
, 7);
9672 if (imm_expr
.X_add_number
== 1)
9674 if (strcmp (s2
, "mflo") == 0)
9675 move_register (op
[0], op
[1]);
9677 move_register (op
[0], ZERO
);
9680 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
9682 if (strcmp (s2
, "mflo") == 0)
9683 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9685 move_register (op
[0], ZERO
);
9690 load_register (AT
, &imm_expr
, dbl
);
9691 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9692 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9714 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9715 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9716 /* We want to close the noreorder block as soon as possible, so
9717 that later insns are available for delay slot filling. */
9722 if (mips_opts
.micromips
)
9723 micromips_label_expr (&label_expr
);
9725 label_expr
.X_add_number
= 8;
9726 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9727 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9729 /* We want to close the noreorder block as soon as possible, so
9730 that later insns are available for delay slot filling. */
9732 macro_build (NULL
, "break", BRK_FMT
, 7);
9733 if (mips_opts
.micromips
)
9734 micromips_add_label ();
9736 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9748 /* Load the address of a symbol into a register. If breg is not
9749 zero, we then add a base register to it. */
9752 if (dbl
&& HAVE_32BIT_GPRS
)
9753 as_warn (_("dla used to load 32-bit register"));
9755 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9756 as_warn (_("la used to load 64-bit address"));
9758 if (small_offset_p (0, align
, 16))
9760 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9761 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9765 if (mips_opts
.at
&& (op
[0] == breg
))
9773 if (offset_expr
.X_op
!= O_symbol
9774 && offset_expr
.X_op
!= O_constant
)
9776 as_bad (_("expression too complex"));
9777 offset_expr
.X_op
= O_constant
;
9780 if (offset_expr
.X_op
== O_constant
)
9781 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9782 else if (mips_pic
== NO_PIC
)
9784 /* If this is a reference to a GP relative symbol, we want
9785 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9787 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9788 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9789 If we have a constant, we need two instructions anyhow,
9790 so we may as well always use the latter form.
9792 With 64bit address space and a usable $at we want
9793 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9794 lui $at,<sym> (BFD_RELOC_HI16_S)
9795 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9796 daddiu $at,<sym> (BFD_RELOC_LO16)
9798 daddu $tempreg,$tempreg,$at
9800 If $at is already in use, we use a path which is suboptimal
9801 on superscalar processors.
9802 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9803 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9805 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9807 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9809 For GP relative symbols in 64bit address space we can use
9810 the same sequence as in 32bit address space. */
9811 if (HAVE_64BIT_SYMBOLS
)
9813 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9814 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9816 relax_start (offset_expr
.X_add_symbol
);
9817 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9818 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9822 if (used_at
== 0 && mips_opts
.at
)
9824 macro_build (&offset_expr
, "lui", LUI_FMT
,
9825 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9826 macro_build (&offset_expr
, "lui", LUI_FMT
,
9827 AT
, BFD_RELOC_HI16_S
);
9828 macro_build (&offset_expr
, "daddiu", "t,r,j",
9829 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9830 macro_build (&offset_expr
, "daddiu", "t,r,j",
9831 AT
, AT
, BFD_RELOC_LO16
);
9832 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9833 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9838 macro_build (&offset_expr
, "lui", LUI_FMT
,
9839 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9840 macro_build (&offset_expr
, "daddiu", "t,r,j",
9841 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9842 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9843 macro_build (&offset_expr
, "daddiu", "t,r,j",
9844 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9845 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9846 macro_build (&offset_expr
, "daddiu", "t,r,j",
9847 tempreg
, tempreg
, BFD_RELOC_LO16
);
9850 if (mips_relax
.sequence
)
9855 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9856 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9858 relax_start (offset_expr
.X_add_symbol
);
9859 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9860 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9863 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9864 as_bad (_("offset too large"));
9865 macro_build_lui (&offset_expr
, tempreg
);
9866 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9867 tempreg
, tempreg
, BFD_RELOC_LO16
);
9868 if (mips_relax
.sequence
)
9872 else if (!mips_big_got
&& !HAVE_NEWABI
)
9874 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9876 /* If this is a reference to an external symbol, and there
9877 is no constant, we want
9878 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9879 or for lca or if tempreg is PIC_CALL_REG
9880 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9881 For a local symbol, we want
9882 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9884 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9886 If we have a small constant, and this is a reference to
9887 an external symbol, we want
9888 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9890 addiu $tempreg,$tempreg,<constant>
9891 For a local symbol, we want the same instruction
9892 sequence, but we output a BFD_RELOC_LO16 reloc on the
9895 If we have a large constant, and this is a reference to
9896 an external symbol, we want
9897 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9898 lui $at,<hiconstant>
9899 addiu $at,$at,<loconstant>
9900 addu $tempreg,$tempreg,$at
9901 For a local symbol, we want the same instruction
9902 sequence, but we output a BFD_RELOC_LO16 reloc on the
9906 if (offset_expr
.X_add_number
== 0)
9908 if (mips_pic
== SVR4_PIC
9910 && (call
|| tempreg
== PIC_CALL_REG
))
9911 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9913 relax_start (offset_expr
.X_add_symbol
);
9914 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9915 lw_reloc_type
, mips_gp_register
);
9918 /* We're going to put in an addu instruction using
9919 tempreg, so we may as well insert the nop right
9924 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9925 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9927 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9928 tempreg
, tempreg
, BFD_RELOC_LO16
);
9930 /* FIXME: If breg == 0, and the next instruction uses
9931 $tempreg, then if this variant case is used an extra
9932 nop will be generated. */
9934 else if (offset_expr
.X_add_number
>= -0x8000
9935 && offset_expr
.X_add_number
< 0x8000)
9937 load_got_offset (tempreg
, &offset_expr
);
9939 add_got_offset (tempreg
, &offset_expr
);
9943 expr1
.X_add_number
= offset_expr
.X_add_number
;
9944 offset_expr
.X_add_number
=
9945 SEXT_16BIT (offset_expr
.X_add_number
);
9946 load_got_offset (tempreg
, &offset_expr
);
9947 offset_expr
.X_add_number
= expr1
.X_add_number
;
9948 /* If we are going to add in a base register, and the
9949 target register and the base register are the same,
9950 then we are using AT as a temporary register. Since
9951 we want to load the constant into AT, we add our
9952 current AT (from the global offset table) and the
9953 register into the register now, and pretend we were
9954 not using a base register. */
9958 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9963 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
9967 else if (!mips_big_got
&& HAVE_NEWABI
)
9969 int add_breg_early
= 0;
9971 /* If this is a reference to an external, and there is no
9972 constant, or local symbol (*), with or without a
9974 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9975 or for lca or if tempreg is PIC_CALL_REG
9976 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9978 If we have a small constant, and this is a reference to
9979 an external symbol, we want
9980 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9981 addiu $tempreg,$tempreg,<constant>
9983 If we have a large constant, and this is a reference to
9984 an external symbol, we want
9985 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9986 lui $at,<hiconstant>
9987 addiu $at,$at,<loconstant>
9988 addu $tempreg,$tempreg,$at
9990 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9991 local symbols, even though it introduces an additional
9994 if (offset_expr
.X_add_number
)
9996 expr1
.X_add_number
= offset_expr
.X_add_number
;
9997 offset_expr
.X_add_number
= 0;
9999 relax_start (offset_expr
.X_add_symbol
);
10000 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10001 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10003 if (expr1
.X_add_number
>= -0x8000
10004 && expr1
.X_add_number
< 0x8000)
10006 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10007 tempreg
, tempreg
, BFD_RELOC_LO16
);
10009 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10013 /* If we are going to add in a base register, and the
10014 target register and the base register are the same,
10015 then we are using AT as a temporary register. Since
10016 we want to load the constant into AT, we add our
10017 current AT (from the global offset table) and the
10018 register into the register now, and pretend we were
10019 not using a base register. */
10024 gas_assert (tempreg
== AT
);
10025 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10028 add_breg_early
= 1;
10031 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10032 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10038 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10041 offset_expr
.X_add_number
= expr1
.X_add_number
;
10043 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10044 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10045 if (add_breg_early
)
10047 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10048 op
[0], tempreg
, breg
);
10054 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10056 relax_start (offset_expr
.X_add_symbol
);
10057 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10058 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10060 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10061 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10066 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10067 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10070 else if (mips_big_got
&& !HAVE_NEWABI
)
10073 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10074 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10075 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10077 /* This is the large GOT case. If this is a reference to an
10078 external symbol, and there is no constant, we want
10079 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10080 addu $tempreg,$tempreg,$gp
10081 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10082 or for lca or if tempreg is PIC_CALL_REG
10083 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10084 addu $tempreg,$tempreg,$gp
10085 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10086 For a local symbol, we want
10087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10089 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10091 If we have a small constant, and this is a reference to
10092 an external symbol, we want
10093 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10094 addu $tempreg,$tempreg,$gp
10095 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10097 addiu $tempreg,$tempreg,<constant>
10098 For a local symbol, we want
10099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10101 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10103 If we have a large constant, and this is a reference to
10104 an external symbol, we want
10105 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10106 addu $tempreg,$tempreg,$gp
10107 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10108 lui $at,<hiconstant>
10109 addiu $at,$at,<loconstant>
10110 addu $tempreg,$tempreg,$at
10111 For a local symbol, we want
10112 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10113 lui $at,<hiconstant>
10114 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10115 addu $tempreg,$tempreg,$at
10118 expr1
.X_add_number
= offset_expr
.X_add_number
;
10119 offset_expr
.X_add_number
= 0;
10120 relax_start (offset_expr
.X_add_symbol
);
10121 gpdelay
= reg_needs_delay (mips_gp_register
);
10122 if (expr1
.X_add_number
== 0 && breg
== 0
10123 && (call
|| tempreg
== PIC_CALL_REG
))
10125 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10126 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10128 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10129 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10130 tempreg
, tempreg
, mips_gp_register
);
10131 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10132 tempreg
, lw_reloc_type
, tempreg
);
10133 if (expr1
.X_add_number
== 0)
10137 /* We're going to put in an addu instruction using
10138 tempreg, so we may as well insert the nop right
10143 else if (expr1
.X_add_number
>= -0x8000
10144 && expr1
.X_add_number
< 0x8000)
10147 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10148 tempreg
, tempreg
, BFD_RELOC_LO16
);
10154 /* If we are going to add in a base register, and the
10155 target register and the base register are the same,
10156 then we are using AT as a temporary register. Since
10157 we want to load the constant into AT, we add our
10158 current AT (from the global offset table) and the
10159 register into the register now, and pretend we were
10160 not using a base register. */
10165 gas_assert (tempreg
== AT
);
10167 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10172 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10173 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10177 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10182 /* This is needed because this instruction uses $gp, but
10183 the first instruction on the main stream does not. */
10184 macro_build (NULL
, "nop", "");
10187 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10188 local_reloc_type
, mips_gp_register
);
10189 if (expr1
.X_add_number
>= -0x8000
10190 && expr1
.X_add_number
< 0x8000)
10193 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10194 tempreg
, tempreg
, BFD_RELOC_LO16
);
10195 /* FIXME: If add_number is 0, and there was no base
10196 register, the external symbol case ended with a load,
10197 so if the symbol turns out to not be external, and
10198 the next instruction uses tempreg, an unnecessary nop
10199 will be inserted. */
10205 /* We must add in the base register now, as in the
10206 external symbol case. */
10207 gas_assert (tempreg
== AT
);
10209 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10212 /* We set breg to 0 because we have arranged to add
10213 it in in both cases. */
10217 macro_build_lui (&expr1
, AT
);
10218 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10219 AT
, AT
, BFD_RELOC_LO16
);
10220 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10221 tempreg
, tempreg
, AT
);
10226 else if (mips_big_got
&& HAVE_NEWABI
)
10228 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10229 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10230 int add_breg_early
= 0;
10232 /* This is the large GOT case. If this is a reference to an
10233 external symbol, and there is no constant, we want
10234 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10235 add $tempreg,$tempreg,$gp
10236 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10237 or for lca or if tempreg is PIC_CALL_REG
10238 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10239 add $tempreg,$tempreg,$gp
10240 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10242 If we have a small constant, and this is a reference to
10243 an external symbol, we want
10244 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10245 add $tempreg,$tempreg,$gp
10246 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10247 addi $tempreg,$tempreg,<constant>
10249 If we have a large constant, and this is a reference to
10250 an external symbol, we want
10251 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10252 addu $tempreg,$tempreg,$gp
10253 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10254 lui $at,<hiconstant>
10255 addi $at,$at,<loconstant>
10256 add $tempreg,$tempreg,$at
10258 If we have NewABI, and we know it's a local symbol, we want
10259 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10260 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10261 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10263 relax_start (offset_expr
.X_add_symbol
);
10265 expr1
.X_add_number
= offset_expr
.X_add_number
;
10266 offset_expr
.X_add_number
= 0;
10268 if (expr1
.X_add_number
== 0 && breg
== 0
10269 && (call
|| tempreg
== PIC_CALL_REG
))
10271 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10272 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10274 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10275 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10276 tempreg
, tempreg
, mips_gp_register
);
10277 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10278 tempreg
, lw_reloc_type
, tempreg
);
10280 if (expr1
.X_add_number
== 0)
10282 else if (expr1
.X_add_number
>= -0x8000
10283 && expr1
.X_add_number
< 0x8000)
10285 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10286 tempreg
, tempreg
, BFD_RELOC_LO16
);
10288 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10292 /* If we are going to add in a base register, and the
10293 target register and the base register are the same,
10294 then we are using AT as a temporary register. Since
10295 we want to load the constant into AT, we add our
10296 current AT (from the global offset table) and the
10297 register into the register now, and pretend we were
10298 not using a base register. */
10303 gas_assert (tempreg
== AT
);
10304 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10307 add_breg_early
= 1;
10310 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10311 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10316 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10319 offset_expr
.X_add_number
= expr1
.X_add_number
;
10320 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10321 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10322 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10323 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10324 if (add_breg_early
)
10326 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10327 op
[0], tempreg
, breg
);
10337 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10341 gas_assert (!mips_opts
.micromips
);
10342 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10346 gas_assert (!mips_opts
.micromips
);
10347 macro_build (NULL
, "c2", "C", 0x02);
10351 gas_assert (!mips_opts
.micromips
);
10352 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10356 gas_assert (!mips_opts
.micromips
);
10357 macro_build (NULL
, "c2", "C", 3);
10361 gas_assert (!mips_opts
.micromips
);
10362 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10366 /* The j instruction may not be used in PIC code, since it
10367 requires an absolute address. We convert it to a b
10369 if (mips_pic
== NO_PIC
)
10370 macro_build (&offset_expr
, "j", "a");
10372 macro_build (&offset_expr
, "b", "p");
10375 /* The jal instructions must be handled as macros because when
10376 generating PIC code they expand to multi-instruction
10377 sequences. Normally they are simple instructions. */
10381 /* Fall through. */
10383 gas_assert (mips_opts
.micromips
);
10384 if (mips_opts
.insn32
)
10386 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10394 /* Fall through. */
10397 if (mips_pic
== NO_PIC
)
10399 s
= jals
? "jalrs" : "jalr";
10400 if (mips_opts
.micromips
10401 && !mips_opts
.insn32
10403 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10404 macro_build (NULL
, s
, "mj", op
[1]);
10406 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10410 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10411 && mips_cprestore_offset
>= 0);
10413 if (op
[1] != PIC_CALL_REG
)
10414 as_warn (_("MIPS PIC call to register other than $25"));
10416 s
= ((mips_opts
.micromips
10417 && !mips_opts
.insn32
10418 && (!mips_opts
.noreorder
|| cprestore
))
10419 ? "jalrs" : "jalr");
10420 if (mips_opts
.micromips
10421 && !mips_opts
.insn32
10423 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10424 macro_build (NULL
, s
, "mj", op
[1]);
10426 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10427 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
10429 if (mips_cprestore_offset
< 0)
10430 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10433 if (!mips_frame_reg_valid
)
10435 as_warn (_("no .frame pseudo-op used in PIC code"));
10436 /* Quiet this warning. */
10437 mips_frame_reg_valid
= 1;
10439 if (!mips_cprestore_valid
)
10441 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10442 /* Quiet this warning. */
10443 mips_cprestore_valid
= 1;
10445 if (mips_opts
.noreorder
)
10446 macro_build (NULL
, "nop", "");
10447 expr1
.X_add_number
= mips_cprestore_offset
;
10448 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10451 HAVE_64BIT_ADDRESSES
);
10459 gas_assert (mips_opts
.micromips
);
10460 if (mips_opts
.insn32
)
10462 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10466 /* Fall through. */
10468 if (mips_pic
== NO_PIC
)
10469 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
10470 else if (mips_pic
== SVR4_PIC
)
10472 /* If this is a reference to an external symbol, and we are
10473 using a small GOT, we want
10474 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10478 lw $gp,cprestore($sp)
10479 The cprestore value is set using the .cprestore
10480 pseudo-op. If we are using a big GOT, we want
10481 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10483 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10487 lw $gp,cprestore($sp)
10488 If the symbol is not external, we want
10489 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10491 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10494 lw $gp,cprestore($sp)
10496 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10497 sequences above, minus nops, unless the symbol is local,
10498 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10504 relax_start (offset_expr
.X_add_symbol
);
10505 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10506 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10509 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10510 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
10516 relax_start (offset_expr
.X_add_symbol
);
10517 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10518 BFD_RELOC_MIPS_CALL_HI16
);
10519 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10520 PIC_CALL_REG
, mips_gp_register
);
10521 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10522 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10525 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10526 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
10528 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10529 PIC_CALL_REG
, PIC_CALL_REG
,
10530 BFD_RELOC_MIPS_GOT_OFST
);
10534 macro_build_jalr (&offset_expr
, 0);
10538 relax_start (offset_expr
.X_add_symbol
);
10541 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10542 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10551 gpdelay
= reg_needs_delay (mips_gp_register
);
10552 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10553 BFD_RELOC_MIPS_CALL_HI16
);
10554 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10555 PIC_CALL_REG
, mips_gp_register
);
10556 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10557 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10562 macro_build (NULL
, "nop", "");
10564 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10565 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
10568 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10569 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
10571 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
10573 if (mips_cprestore_offset
< 0)
10574 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10577 if (!mips_frame_reg_valid
)
10579 as_warn (_("no .frame pseudo-op used in PIC code"));
10580 /* Quiet this warning. */
10581 mips_frame_reg_valid
= 1;
10583 if (!mips_cprestore_valid
)
10585 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10586 /* Quiet this warning. */
10587 mips_cprestore_valid
= 1;
10589 if (mips_opts
.noreorder
)
10590 macro_build (NULL
, "nop", "");
10591 expr1
.X_add_number
= mips_cprestore_offset
;
10592 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10595 HAVE_64BIT_ADDRESSES
);
10599 else if (mips_pic
== VXWORKS_PIC
)
10600 as_bad (_("non-PIC jump used in PIC library"));
10707 gas_assert (!mips_opts
.micromips
);
10710 /* Itbl support may require additional care here. */
10716 /* Itbl support may require additional care here. */
10722 offbits
= (mips_opts
.micromips
? 12 : 16);
10723 /* Itbl support may require additional care here. */
10727 gas_assert (!mips_opts
.micromips
);
10730 /* Itbl support may require additional care here. */
10736 offbits
= (mips_opts
.micromips
? 12 : 16);
10741 offbits
= (mips_opts
.micromips
? 12 : 16);
10746 /* Itbl support may require additional care here. */
10752 offbits
= (mips_opts
.micromips
? 12 : 16);
10753 /* Itbl support may require additional care here. */
10759 /* Itbl support may require additional care here. */
10765 /* Itbl support may require additional care here. */
10771 offbits
= (mips_opts
.micromips
? 12 : 16);
10776 offbits
= (mips_opts
.micromips
? 12 : 16);
10781 offbits
= (mips_opts
.micromips
? 12 : 16);
10786 offbits
= (mips_opts
.micromips
? 12 : 16);
10791 offbits
= (mips_opts
.micromips
? 12 : 16);
10794 gas_assert (mips_opts
.micromips
);
10801 gas_assert (mips_opts
.micromips
);
10808 gas_assert (mips_opts
.micromips
);
10814 gas_assert (mips_opts
.micromips
);
10821 /* We don't want to use $0 as tempreg. */
10822 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10825 tempreg
= op
[0] + lp
;
10841 gas_assert (!mips_opts
.micromips
);
10844 /* Itbl support may require additional care here. */
10850 /* Itbl support may require additional care here. */
10856 offbits
= (mips_opts
.micromips
? 12 : 16);
10857 /* Itbl support may require additional care here. */
10861 gas_assert (!mips_opts
.micromips
);
10864 /* Itbl support may require additional care here. */
10870 offbits
= (mips_opts
.micromips
? 12 : 16);
10875 offbits
= (mips_opts
.micromips
? 12 : 16);
10880 offbits
= (mips_opts
.micromips
? 12 : 16);
10885 offbits
= (mips_opts
.micromips
? 12 : 16);
10889 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10890 offbits
= (mips_opts
.micromips
? 12 : 16);
10899 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10900 offbits
= (mips_opts
.micromips
? 12 : 16);
10911 /* Itbl support may require additional care here. */
10916 offbits
= (mips_opts
.micromips
? 12 : 16);
10917 /* Itbl support may require additional care here. */
10923 /* Itbl support may require additional care here. */
10927 gas_assert (!mips_opts
.micromips
);
10930 /* Itbl support may require additional care here. */
10936 offbits
= (mips_opts
.micromips
? 12 : 16);
10941 offbits
= (mips_opts
.micromips
? 12 : 16);
10944 gas_assert (mips_opts
.micromips
);
10950 gas_assert (mips_opts
.micromips
);
10956 gas_assert (mips_opts
.micromips
);
10962 gas_assert (mips_opts
.micromips
);
10971 if (small_offset_p (0, align
, 16))
10973 /* The first case exists for M_LD_AB and M_SD_AB, which are
10974 macros for o32 but which should act like normal instructions
10977 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
10978 offset_reloc
[1], offset_reloc
[2], breg
);
10979 else if (small_offset_p (0, align
, offbits
))
10982 macro_build (NULL
, s
, fmt
, op
[0], breg
);
10984 macro_build (NULL
, s
, fmt
, op
[0],
10985 (int) offset_expr
.X_add_number
, breg
);
10991 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10992 tempreg
, breg
, -1, offset_reloc
[0],
10993 offset_reloc
[1], offset_reloc
[2]);
10995 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10997 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11005 if (offset_expr
.X_op
!= O_constant
11006 && offset_expr
.X_op
!= O_symbol
)
11008 as_bad (_("expression too complex"));
11009 offset_expr
.X_op
= O_constant
;
11012 if (HAVE_32BIT_ADDRESSES
11013 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11017 sprintf_vma (value
, offset_expr
.X_add_number
);
11018 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11021 /* A constant expression in PIC code can be handled just as it
11022 is in non PIC code. */
11023 if (offset_expr
.X_op
== O_constant
)
11025 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11026 offbits
== 0 ? 16 : offbits
);
11027 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11029 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11032 tempreg
, tempreg
, breg
);
11035 if (offset_expr
.X_add_number
!= 0)
11036 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11037 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11038 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11040 else if (offbits
== 16)
11041 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11043 macro_build (NULL
, s
, fmt
, op
[0],
11044 (int) offset_expr
.X_add_number
, tempreg
);
11046 else if (offbits
!= 16)
11048 /* The offset field is too narrow to be used for a low-part
11049 relocation, so load the whole address into the auxillary
11051 load_address (tempreg
, &offset_expr
, &used_at
);
11053 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11054 tempreg
, tempreg
, breg
);
11056 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11058 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11060 else if (mips_pic
== NO_PIC
)
11062 /* If this is a reference to a GP relative symbol, and there
11063 is no base register, we want
11064 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11065 Otherwise, if there is no base register, we want
11066 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11067 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11068 If we have a constant, we need two instructions anyhow,
11069 so we always use the latter form.
11071 If we have a base register, and this is a reference to a
11072 GP relative symbol, we want
11073 addu $tempreg,$breg,$gp
11074 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11076 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11077 addu $tempreg,$tempreg,$breg
11078 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11079 With a constant we always use the latter case.
11081 With 64bit address space and no base register and $at usable,
11083 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11084 lui $at,<sym> (BFD_RELOC_HI16_S)
11085 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11088 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11089 If we have a base register, we want
11090 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11091 lui $at,<sym> (BFD_RELOC_HI16_S)
11092 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11096 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11098 Without $at we can't generate the optimal path for superscalar
11099 processors here since this would require two temporary registers.
11100 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11101 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11103 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11105 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11106 If we have a base register, we want
11107 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11108 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11110 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11112 daddu $tempreg,$tempreg,$breg
11113 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11115 For GP relative symbols in 64bit address space we can use
11116 the same sequence as in 32bit address space. */
11117 if (HAVE_64BIT_SYMBOLS
)
11119 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11120 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11122 relax_start (offset_expr
.X_add_symbol
);
11125 macro_build (&offset_expr
, s
, fmt
, op
[0],
11126 BFD_RELOC_GPREL16
, mips_gp_register
);
11130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11131 tempreg
, breg
, mips_gp_register
);
11132 macro_build (&offset_expr
, s
, fmt
, op
[0],
11133 BFD_RELOC_GPREL16
, tempreg
);
11138 if (used_at
== 0 && mips_opts
.at
)
11140 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11141 BFD_RELOC_MIPS_HIGHEST
);
11142 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11144 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11145 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11147 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11148 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11149 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11150 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11156 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11157 BFD_RELOC_MIPS_HIGHEST
);
11158 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11159 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11160 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11161 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11162 tempreg
, BFD_RELOC_HI16_S
);
11163 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11165 macro_build (NULL
, "daddu", "d,v,t",
11166 tempreg
, tempreg
, breg
);
11167 macro_build (&offset_expr
, s
, fmt
, op
[0],
11168 BFD_RELOC_LO16
, tempreg
);
11171 if (mips_relax
.sequence
)
11178 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11179 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11181 relax_start (offset_expr
.X_add_symbol
);
11182 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11186 macro_build_lui (&offset_expr
, tempreg
);
11187 macro_build (&offset_expr
, s
, fmt
, op
[0],
11188 BFD_RELOC_LO16
, tempreg
);
11189 if (mips_relax
.sequence
)
11194 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11195 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11197 relax_start (offset_expr
.X_add_symbol
);
11198 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11199 tempreg
, breg
, mips_gp_register
);
11200 macro_build (&offset_expr
, s
, fmt
, op
[0],
11201 BFD_RELOC_GPREL16
, tempreg
);
11204 macro_build_lui (&offset_expr
, tempreg
);
11205 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11206 tempreg
, tempreg
, breg
);
11207 macro_build (&offset_expr
, s
, fmt
, op
[0],
11208 BFD_RELOC_LO16
, tempreg
);
11209 if (mips_relax
.sequence
)
11213 else if (!mips_big_got
)
11215 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11217 /* If this is a reference to an external symbol, we want
11218 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11220 <op> op[0],0($tempreg)
11222 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11224 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11225 <op> op[0],0($tempreg)
11227 For NewABI, we want
11228 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11229 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11231 If there is a base register, we add it to $tempreg before
11232 the <op>. If there is a constant, we stick it in the
11233 <op> instruction. We don't handle constants larger than
11234 16 bits, because we have no way to load the upper 16 bits
11235 (actually, we could handle them for the subset of cases
11236 in which we are not using $at). */
11237 gas_assert (offset_expr
.X_op
== O_symbol
);
11240 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11241 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11243 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11244 tempreg
, tempreg
, breg
);
11245 macro_build (&offset_expr
, s
, fmt
, op
[0],
11246 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11249 expr1
.X_add_number
= offset_expr
.X_add_number
;
11250 offset_expr
.X_add_number
= 0;
11251 if (expr1
.X_add_number
< -0x8000
11252 || expr1
.X_add_number
>= 0x8000)
11253 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11254 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11255 lw_reloc_type
, mips_gp_register
);
11257 relax_start (offset_expr
.X_add_symbol
);
11259 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11260 tempreg
, BFD_RELOC_LO16
);
11263 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11264 tempreg
, tempreg
, breg
);
11265 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11267 else if (mips_big_got
&& !HAVE_NEWABI
)
11271 /* If this is a reference to an external symbol, we want
11272 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11273 addu $tempreg,$tempreg,$gp
11274 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11275 <op> op[0],0($tempreg)
11277 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11279 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11280 <op> op[0],0($tempreg)
11281 If there is a base register, we add it to $tempreg before
11282 the <op>. If there is a constant, we stick it in the
11283 <op> instruction. We don't handle constants larger than
11284 16 bits, because we have no way to load the upper 16 bits
11285 (actually, we could handle them for the subset of cases
11286 in which we are not using $at). */
11287 gas_assert (offset_expr
.X_op
== O_symbol
);
11288 expr1
.X_add_number
= offset_expr
.X_add_number
;
11289 offset_expr
.X_add_number
= 0;
11290 if (expr1
.X_add_number
< -0x8000
11291 || expr1
.X_add_number
>= 0x8000)
11292 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11293 gpdelay
= reg_needs_delay (mips_gp_register
);
11294 relax_start (offset_expr
.X_add_symbol
);
11295 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11296 BFD_RELOC_MIPS_GOT_HI16
);
11297 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11299 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11300 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11303 macro_build (NULL
, "nop", "");
11304 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11305 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11307 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11308 tempreg
, BFD_RELOC_LO16
);
11312 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11313 tempreg
, tempreg
, breg
);
11314 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11316 else if (mips_big_got
&& HAVE_NEWABI
)
11318 /* If this is a reference to an external symbol, we want
11319 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11320 add $tempreg,$tempreg,$gp
11321 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11322 <op> op[0],<ofst>($tempreg)
11323 Otherwise, for local symbols, we want:
11324 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11325 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11326 gas_assert (offset_expr
.X_op
== O_symbol
);
11327 expr1
.X_add_number
= offset_expr
.X_add_number
;
11328 offset_expr
.X_add_number
= 0;
11329 if (expr1
.X_add_number
< -0x8000
11330 || expr1
.X_add_number
>= 0x8000)
11331 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11332 relax_start (offset_expr
.X_add_symbol
);
11333 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11334 BFD_RELOC_MIPS_GOT_HI16
);
11335 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11337 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11338 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11340 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11341 tempreg
, tempreg
, breg
);
11342 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11345 offset_expr
.X_add_number
= expr1
.X_add_number
;
11346 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11347 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11349 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11350 tempreg
, tempreg
, breg
);
11351 macro_build (&offset_expr
, s
, fmt
, op
[0],
11352 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11361 gas_assert (mips_opts
.micromips
);
11362 gas_assert (mips_opts
.insn32
);
11363 start_noreorder ();
11364 macro_build (NULL
, "jr", "s", RA
);
11365 expr1
.X_add_number
= op
[0] << 2;
11366 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11371 gas_assert (mips_opts
.micromips
);
11372 gas_assert (mips_opts
.insn32
);
11373 macro_build (NULL
, "jr", "s", op
[0]);
11374 if (mips_opts
.noreorder
)
11375 macro_build (NULL
, "nop", "");
11380 load_register (op
[0], &imm_expr
, 0);
11384 load_register (op
[0], &imm_expr
, 1);
11388 if (imm_expr
.X_op
== O_constant
)
11391 load_register (AT
, &imm_expr
, 0);
11392 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11397 gas_assert (imm_expr
.X_op
== O_absent
11398 && offset_expr
.X_op
== O_symbol
11399 && strcmp (segment_name (S_GET_SEGMENT
11400 (offset_expr
.X_add_symbol
)),
11402 && offset_expr
.X_add_number
== 0);
11403 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
11404 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
11409 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11410 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11411 order 32 bits of the value and the low order 32 bits are either
11412 zero or in OFFSET_EXPR. */
11413 if (imm_expr
.X_op
== O_constant
)
11415 if (HAVE_64BIT_GPRS
)
11416 load_register (op
[0], &imm_expr
, 1);
11421 if (target_big_endian
)
11433 load_register (hreg
, &imm_expr
, 0);
11436 if (offset_expr
.X_op
== O_absent
)
11437 move_register (lreg
, 0);
11440 gas_assert (offset_expr
.X_op
== O_constant
);
11441 load_register (lreg
, &offset_expr
, 0);
11447 gas_assert (imm_expr
.X_op
== O_absent
);
11449 /* We know that sym is in the .rdata section. First we get the
11450 upper 16 bits of the address. */
11451 if (mips_pic
== NO_PIC
)
11453 macro_build_lui (&offset_expr
, AT
);
11458 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11459 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11463 /* Now we load the register(s). */
11464 if (HAVE_64BIT_GPRS
)
11467 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
11468 BFD_RELOC_LO16
, AT
);
11473 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
11474 BFD_RELOC_LO16
, AT
);
11477 /* FIXME: How in the world do we deal with the possible
11479 offset_expr
.X_add_number
+= 4;
11480 macro_build (&offset_expr
, "lw", "t,o(b)",
11481 op
[0] + 1, BFD_RELOC_LO16
, AT
);
11487 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11488 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11489 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11490 the value and the low order 32 bits are either zero or in
11492 if (imm_expr
.X_op
== O_constant
)
11495 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
11496 if (HAVE_64BIT_FPRS
)
11498 gas_assert (HAVE_64BIT_GPRS
);
11499 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
11503 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
11504 if (offset_expr
.X_op
== O_absent
)
11505 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
11508 gas_assert (offset_expr
.X_op
== O_constant
);
11509 load_register (AT
, &offset_expr
, 0);
11510 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11516 gas_assert (imm_expr
.X_op
== O_absent
11517 && offset_expr
.X_op
== O_symbol
11518 && offset_expr
.X_add_number
== 0);
11519 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
11520 if (strcmp (s
, ".lit8") == 0)
11522 op
[2] = mips_gp_register
;
11523 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
11524 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11525 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11529 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
11531 if (mips_pic
!= NO_PIC
)
11532 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11533 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11536 /* FIXME: This won't work for a 64 bit address. */
11537 macro_build_lui (&offset_expr
, AT
);
11541 offset_reloc
[0] = BFD_RELOC_LO16
;
11542 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11543 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11550 * The MIPS assembler seems to check for X_add_number not
11551 * being double aligned and generating:
11552 * lui at,%hi(foo+1)
11554 * addiu at,at,%lo(foo+1)
11557 * But, the resulting address is the same after relocation so why
11558 * generate the extra instruction?
11560 /* Itbl support may require additional care here. */
11563 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11572 gas_assert (!mips_opts
.micromips
);
11573 /* Itbl support may require additional care here. */
11576 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11596 if (HAVE_64BIT_GPRS
)
11606 if (HAVE_64BIT_GPRS
)
11614 /* Even on a big endian machine $fn comes before $fn+1. We have
11615 to adjust when loading from memory. We set coproc if we must
11616 load $fn+1 first. */
11617 /* Itbl support may require additional care here. */
11618 if (!target_big_endian
)
11622 if (small_offset_p (0, align
, 16))
11625 if (!small_offset_p (4, align
, 16))
11627 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11628 -1, offset_reloc
[0], offset_reloc
[1],
11630 expr1
.X_add_number
= 0;
11634 offset_reloc
[0] = BFD_RELOC_LO16
;
11635 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11636 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11638 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11640 ep
->X_add_number
+= 4;
11641 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11642 offset_reloc
[1], offset_reloc
[2], breg
);
11643 ep
->X_add_number
-= 4;
11644 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11645 offset_reloc
[1], offset_reloc
[2], breg
);
11649 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11650 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11652 ep
->X_add_number
+= 4;
11653 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11654 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11660 if (offset_expr
.X_op
!= O_symbol
11661 && offset_expr
.X_op
!= O_constant
)
11663 as_bad (_("expression too complex"));
11664 offset_expr
.X_op
= O_constant
;
11667 if (HAVE_32BIT_ADDRESSES
11668 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11672 sprintf_vma (value
, offset_expr
.X_add_number
);
11673 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11676 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11678 /* If this is a reference to a GP relative symbol, we want
11679 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11680 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11681 If we have a base register, we use this
11683 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11684 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11685 If this is not a GP relative symbol, we want
11686 lui $at,<sym> (BFD_RELOC_HI16_S)
11687 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11688 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11689 If there is a base register, we add it to $at after the
11690 lui instruction. If there is a constant, we always use
11692 if (offset_expr
.X_op
== O_symbol
11693 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11694 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11696 relax_start (offset_expr
.X_add_symbol
);
11699 tempreg
= mips_gp_register
;
11703 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11704 AT
, breg
, mips_gp_register
);
11709 /* Itbl support may require additional care here. */
11710 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11711 BFD_RELOC_GPREL16
, tempreg
);
11712 offset_expr
.X_add_number
+= 4;
11714 /* Set mips_optimize to 2 to avoid inserting an
11716 hold_mips_optimize
= mips_optimize
;
11718 /* Itbl support may require additional care here. */
11719 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11720 BFD_RELOC_GPREL16
, tempreg
);
11721 mips_optimize
= hold_mips_optimize
;
11725 offset_expr
.X_add_number
-= 4;
11728 if (offset_high_part (offset_expr
.X_add_number
, 16)
11729 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11731 load_address (AT
, &offset_expr
, &used_at
);
11732 offset_expr
.X_op
= O_constant
;
11733 offset_expr
.X_add_number
= 0;
11736 macro_build_lui (&offset_expr
, AT
);
11738 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11739 /* Itbl support may require additional care here. */
11740 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11741 BFD_RELOC_LO16
, AT
);
11742 /* FIXME: How do we handle overflow here? */
11743 offset_expr
.X_add_number
+= 4;
11744 /* Itbl support may require additional care here. */
11745 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11746 BFD_RELOC_LO16
, AT
);
11747 if (mips_relax
.sequence
)
11750 else if (!mips_big_got
)
11752 /* If this is a reference to an external symbol, we want
11753 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11756 <op> op[0]+1,4($at)
11758 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11760 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11761 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11762 If there is a base register we add it to $at before the
11763 lwc1 instructions. If there is a constant we include it
11764 in the lwc1 instructions. */
11766 expr1
.X_add_number
= offset_expr
.X_add_number
;
11767 if (expr1
.X_add_number
< -0x8000
11768 || expr1
.X_add_number
>= 0x8000 - 4)
11769 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11770 load_got_offset (AT
, &offset_expr
);
11773 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11775 /* Set mips_optimize to 2 to avoid inserting an undesired
11777 hold_mips_optimize
= mips_optimize
;
11780 /* Itbl support may require additional care here. */
11781 relax_start (offset_expr
.X_add_symbol
);
11782 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11783 BFD_RELOC_LO16
, AT
);
11784 expr1
.X_add_number
+= 4;
11785 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11786 BFD_RELOC_LO16
, AT
);
11788 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11789 BFD_RELOC_LO16
, AT
);
11790 offset_expr
.X_add_number
+= 4;
11791 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11792 BFD_RELOC_LO16
, AT
);
11795 mips_optimize
= hold_mips_optimize
;
11797 else if (mips_big_got
)
11801 /* If this is a reference to an external symbol, we want
11802 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11804 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11807 <op> op[0]+1,4($at)
11809 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11811 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11812 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11813 If there is a base register we add it to $at before the
11814 lwc1 instructions. If there is a constant we include it
11815 in the lwc1 instructions. */
11817 expr1
.X_add_number
= offset_expr
.X_add_number
;
11818 offset_expr
.X_add_number
= 0;
11819 if (expr1
.X_add_number
< -0x8000
11820 || expr1
.X_add_number
>= 0x8000 - 4)
11821 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11822 gpdelay
= reg_needs_delay (mips_gp_register
);
11823 relax_start (offset_expr
.X_add_symbol
);
11824 macro_build (&offset_expr
, "lui", LUI_FMT
,
11825 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11826 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11827 AT
, AT
, mips_gp_register
);
11828 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11829 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11832 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11833 /* Itbl support may require additional care here. */
11834 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11835 BFD_RELOC_LO16
, AT
);
11836 expr1
.X_add_number
+= 4;
11838 /* Set mips_optimize to 2 to avoid inserting an undesired
11840 hold_mips_optimize
= mips_optimize
;
11842 /* Itbl support may require additional care here. */
11843 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11844 BFD_RELOC_LO16
, AT
);
11845 mips_optimize
= hold_mips_optimize
;
11846 expr1
.X_add_number
-= 4;
11849 offset_expr
.X_add_number
= expr1
.X_add_number
;
11851 macro_build (NULL
, "nop", "");
11852 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11853 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11856 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11857 /* Itbl support may require additional care here. */
11858 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11859 BFD_RELOC_LO16
, AT
);
11860 offset_expr
.X_add_number
+= 4;
11862 /* Set mips_optimize to 2 to avoid inserting an undesired
11864 hold_mips_optimize
= mips_optimize
;
11866 /* Itbl support may require additional care here. */
11867 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11868 BFD_RELOC_LO16
, AT
);
11869 mips_optimize
= hold_mips_optimize
;
11888 /* New code added to support COPZ instructions.
11889 This code builds table entries out of the macros in mip_opcodes.
11890 R4000 uses interlocks to handle coproc delays.
11891 Other chips (like the R3000) require nops to be inserted for delays.
11893 FIXME: Currently, we require that the user handle delays.
11894 In order to fill delay slots for non-interlocked chips,
11895 we must have a way to specify delays based on the coprocessor.
11896 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11897 What are the side-effects of the cop instruction?
11898 What cache support might we have and what are its effects?
11899 Both coprocessor & memory require delays. how long???
11900 What registers are read/set/modified?
11902 If an itbl is provided to interpret cop instructions,
11903 this knowledge can be encoded in the itbl spec. */
11917 gas_assert (!mips_opts
.micromips
);
11918 /* For now we just do C (same as Cz). The parameter will be
11919 stored in insn_opcode by mips_ip. */
11920 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11924 move_register (op
[0], op
[1]);
11928 gas_assert (mips_opts
.micromips
);
11929 gas_assert (mips_opts
.insn32
);
11930 move_register (micromips_to_32_reg_h_map1
[op
[0]],
11931 micromips_to_32_reg_m_map
[op
[1]]);
11932 move_register (micromips_to_32_reg_h_map2
[op
[0]],
11933 micromips_to_32_reg_n_map
[op
[2]]);
11939 if (mips_opts
.arch
== CPU_R5900
)
11940 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
11944 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
11945 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11952 /* The MIPS assembler some times generates shifts and adds. I'm
11953 not trying to be that fancy. GCC should do this for us
11956 load_register (AT
, &imm_expr
, dbl
);
11957 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
11958 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11971 start_noreorder ();
11974 load_register (AT
, &imm_expr
, dbl
);
11975 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
11976 op
[1], imm
? AT
: op
[2]);
11977 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11978 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
11979 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11981 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
11984 if (mips_opts
.micromips
)
11985 micromips_label_expr (&label_expr
);
11987 label_expr
.X_add_number
= 8;
11988 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
11989 macro_build (NULL
, "nop", "");
11990 macro_build (NULL
, "break", BRK_FMT
, 6);
11991 if (mips_opts
.micromips
)
11992 micromips_add_label ();
11995 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12008 start_noreorder ();
12011 load_register (AT
, &imm_expr
, dbl
);
12012 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12013 op
[1], imm
? AT
: op
[2]);
12014 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12015 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12017 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12020 if (mips_opts
.micromips
)
12021 micromips_label_expr (&label_expr
);
12023 label_expr
.X_add_number
= 8;
12024 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12025 macro_build (NULL
, "nop", "");
12026 macro_build (NULL
, "break", BRK_FMT
, 6);
12027 if (mips_opts
.micromips
)
12028 micromips_add_label ();
12034 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12036 if (op
[0] == op
[1])
12043 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12044 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12048 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12049 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12050 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12051 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12055 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12057 if (op
[0] == op
[1])
12064 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12065 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12069 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12070 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12071 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12072 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12081 rot
= imm_expr
.X_add_number
& 0x3f;
12082 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12084 rot
= (64 - rot
) & 0x3f;
12086 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12088 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12093 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12096 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12097 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12100 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12101 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12102 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12110 rot
= imm_expr
.X_add_number
& 0x1f;
12111 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12113 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12114 (32 - rot
) & 0x1f);
12119 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12123 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12124 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12125 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12130 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12132 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12136 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12137 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12138 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12139 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12143 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12145 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12149 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12150 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12151 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12152 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12161 rot
= imm_expr
.X_add_number
& 0x3f;
12162 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12165 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12167 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12172 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12175 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12176 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12179 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12180 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12181 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12189 rot
= imm_expr
.X_add_number
& 0x1f;
12190 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12192 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12197 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12201 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12202 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12203 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12209 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12210 else if (op
[2] == 0)
12211 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12214 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12215 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12220 if (imm_expr
.X_add_number
== 0)
12222 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12227 as_warn (_("instruction %s: result is always false"),
12228 ip
->insn_mo
->name
);
12229 move_register (op
[0], 0);
12232 if (CPU_HAS_SEQ (mips_opts
.arch
)
12233 && -512 <= imm_expr
.X_add_number
12234 && imm_expr
.X_add_number
< 512)
12236 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12237 (int) imm_expr
.X_add_number
);
12240 if (imm_expr
.X_add_number
>= 0
12241 && imm_expr
.X_add_number
< 0x10000)
12242 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12243 else if (imm_expr
.X_add_number
> -0x8000
12244 && imm_expr
.X_add_number
< 0)
12246 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12247 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12248 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12250 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12253 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12254 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12259 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12260 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12263 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12266 case M_SGE
: /* X >= Y <==> not (X < Y) */
12272 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12273 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12276 case M_SGE_I
: /* X >= I <==> not (X < I) */
12278 if (imm_expr
.X_add_number
>= -0x8000
12279 && imm_expr
.X_add_number
< 0x8000)
12280 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12281 op
[0], op
[1], BFD_RELOC_LO16
);
12284 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12285 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12289 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12292 case M_SGT
: /* X > Y <==> Y < X */
12298 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12301 case M_SGT_I
: /* X > I <==> I < X */
12308 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12309 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12312 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12318 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12319 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12322 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12329 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12330 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12331 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12335 if (imm_expr
.X_add_number
>= -0x8000
12336 && imm_expr
.X_add_number
< 0x8000)
12338 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12343 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12344 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12348 if (imm_expr
.X_add_number
>= -0x8000
12349 && imm_expr
.X_add_number
< 0x8000)
12351 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12356 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12357 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12362 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12363 else if (op
[2] == 0)
12364 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12367 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12368 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12373 if (imm_expr
.X_add_number
== 0)
12375 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12380 as_warn (_("instruction %s: result is always true"),
12381 ip
->insn_mo
->name
);
12382 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
12383 op
[0], 0, BFD_RELOC_LO16
);
12386 if (CPU_HAS_SEQ (mips_opts
.arch
)
12387 && -512 <= imm_expr
.X_add_number
12388 && imm_expr
.X_add_number
< 512)
12390 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
12391 (int) imm_expr
.X_add_number
);
12394 if (imm_expr
.X_add_number
>= 0
12395 && imm_expr
.X_add_number
< 0x10000)
12397 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
12400 else if (imm_expr
.X_add_number
> -0x8000
12401 && imm_expr
.X_add_number
< 0)
12403 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12404 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12405 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12407 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12410 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12411 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
12416 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12417 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12420 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12435 if (!mips_opts
.micromips
)
12437 if (imm_expr
.X_add_number
> -0x200
12438 && imm_expr
.X_add_number
<= 0x200)
12440 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
12441 (int) -imm_expr
.X_add_number
);
12450 if (imm_expr
.X_add_number
> -0x8000
12451 && imm_expr
.X_add_number
<= 0x8000)
12453 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12454 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12459 load_register (AT
, &imm_expr
, dbl
);
12460 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
12482 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12483 macro_build (NULL
, s
, "s,t", op
[0], AT
);
12488 gas_assert (!mips_opts
.micromips
);
12489 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
12493 * Is the double cfc1 instruction a bug in the mips assembler;
12494 * or is there a reason for it?
12496 start_noreorder ();
12497 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12498 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12499 macro_build (NULL
, "nop", "");
12500 expr1
.X_add_number
= 3;
12501 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
12502 expr1
.X_add_number
= 2;
12503 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
12504 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
12505 macro_build (NULL
, "nop", "");
12506 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
12508 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
12509 macro_build (NULL
, "nop", "");
12526 offbits
= (mips_opts
.micromips
? 12 : 16);
12532 offbits
= (mips_opts
.micromips
? 12 : 16);
12544 offbits
= (mips_opts
.micromips
? 12 : 16);
12551 offbits
= (mips_opts
.micromips
? 12 : 16);
12557 large_offset
= !small_offset_p (off
, align
, offbits
);
12559 expr1
.X_add_number
= 0;
12564 if (small_offset_p (0, align
, 16))
12565 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
12566 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
12569 load_address (tempreg
, ep
, &used_at
);
12571 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12572 tempreg
, tempreg
, breg
);
12574 offset_reloc
[0] = BFD_RELOC_LO16
;
12575 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12576 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12581 else if (!ust
&& op
[0] == breg
)
12592 if (!target_big_endian
)
12593 ep
->X_add_number
+= off
;
12595 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
12597 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12598 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12600 if (!target_big_endian
)
12601 ep
->X_add_number
-= off
;
12603 ep
->X_add_number
+= off
;
12605 macro_build (NULL
, s2
, "t,~(b)",
12606 tempreg
, (int) ep
->X_add_number
, breg
);
12608 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12609 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12611 /* If necessary, move the result in tempreg to the final destination. */
12612 if (!ust
&& op
[0] != tempreg
)
12614 /* Protect second load's delay slot. */
12616 move_register (op
[0], tempreg
);
12622 if (target_big_endian
== ust
)
12623 ep
->X_add_number
+= off
;
12624 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12625 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12626 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12628 /* For halfword transfers we need a temporary register to shuffle
12629 bytes. Unfortunately for M_USH_A we have none available before
12630 the next store as AT holds the base address. We deal with this
12631 case by clobbering TREG and then restoring it as with ULH. */
12632 tempreg
= ust
== large_offset
? op
[0] : AT
;
12634 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12636 if (target_big_endian
== ust
)
12637 ep
->X_add_number
-= off
;
12639 ep
->X_add_number
+= off
;
12640 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12641 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12643 /* For M_USH_A re-retrieve the LSB. */
12644 if (ust
&& large_offset
)
12646 if (target_big_endian
)
12647 ep
->X_add_number
+= off
;
12649 ep
->X_add_number
-= off
;
12650 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12651 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12653 /* For ULH and M_USH_A OR the LSB in. */
12654 if (!ust
|| large_offset
)
12656 tempreg
= !large_offset
? AT
: op
[0];
12657 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12658 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12663 /* FIXME: Check if this is one of the itbl macros, since they
12664 are added dynamically. */
12665 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
12668 if (!mips_opts
.at
&& used_at
)
12669 as_bad (_("macro used $at after \".set noat\""));
12672 /* Implement macros in mips16 mode. */
12675 mips16_macro (struct mips_cl_insn
*ip
)
12677 const struct mips_operand_array
*operands
;
12682 const char *s
, *s2
, *s3
;
12683 unsigned int op
[MAX_OPERANDS
];
12686 mask
= ip
->insn_mo
->mask
;
12688 operands
= insn_operands (ip
);
12689 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12690 if (operands
->operand
[i
])
12691 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12695 expr1
.X_op
= O_constant
;
12696 expr1
.X_op_symbol
= NULL
;
12697 expr1
.X_add_symbol
= NULL
;
12698 expr1
.X_add_number
= 1;
12717 start_noreorder ();
12718 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12719 expr1
.X_add_number
= 2;
12720 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12721 macro_build (NULL
, "break", "6", 7);
12723 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12724 since that causes an overflow. We should do that as well,
12725 but I don't see how to do the comparisons without a temporary
12728 macro_build (NULL
, s
, "x", op
[0]);
12747 start_noreorder ();
12748 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12749 expr1
.X_add_number
= 2;
12750 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12751 macro_build (NULL
, "break", "6", 7);
12753 macro_build (NULL
, s2
, "x", op
[0]);
12759 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12760 macro_build (NULL
, "mflo", "x", op
[0]);
12768 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12769 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12773 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12774 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12778 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12779 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12801 goto do_reverse_branch
;
12805 goto do_reverse_branch
;
12817 goto do_reverse_branch
;
12828 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12829 macro_build (&offset_expr
, s2
, "p");
12856 goto do_addone_branch_i
;
12861 goto do_addone_branch_i
;
12876 goto do_addone_branch_i
;
12882 do_addone_branch_i
:
12883 ++imm_expr
.X_add_number
;
12886 macro_build (&imm_expr
, s
, s3
, op
[0]);
12887 macro_build (&offset_expr
, s2
, "p");
12891 expr1
.X_add_number
= 0;
12892 macro_build (&expr1
, "slti", "x,8", op
[1]);
12893 if (op
[0] != op
[1])
12894 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12895 expr1
.X_add_number
= 2;
12896 macro_build (&expr1
, "bteqz", "p");
12897 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12902 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12903 opcode bits in *OPCODE_EXTRA. */
12905 static struct mips_opcode
*
12906 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
12907 ssize_t length
, unsigned int *opcode_extra
)
12909 char *name
, *dot
, *p
;
12910 unsigned int mask
, suffix
;
12912 struct mips_opcode
*insn
;
12914 /* Make a copy of the instruction so that we can fiddle with it. */
12915 name
= alloca (length
+ 1);
12916 memcpy (name
, start
, length
);
12917 name
[length
] = '\0';
12919 /* Look up the instruction as-is. */
12920 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12924 dot
= strchr (name
, '.');
12927 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12928 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
12929 if (*p
== 0 && mask
!= 0)
12932 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12934 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
12936 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
12942 if (mips_opts
.micromips
)
12944 /* See if there's an instruction size override suffix,
12945 either `16' or `32', at the end of the mnemonic proper,
12946 that defines the operation, i.e. before the first `.'
12947 character if any. Strip it and retry. */
12948 opend
= dot
!= NULL
? dot
- name
: length
;
12949 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
12951 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
12957 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
12958 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12961 forced_insn_length
= suffix
;
12970 /* Assemble an instruction into its binary format. If the instruction
12971 is a macro, set imm_expr and offset_expr to the values associated
12972 with "I" and "A" operands respectively. Otherwise store the value
12973 of the relocatable field (if any) in offset_expr. In both cases
12974 set offset_reloc to the relocation operators applied to offset_expr. */
12977 mips_ip (char *str
, struct mips_cl_insn
*insn
)
12979 const struct mips_opcode
*first
, *past
;
12980 struct hash_control
*hash
;
12983 struct mips_operand_token
*tokens
;
12984 unsigned int opcode_extra
;
12986 if (mips_opts
.micromips
)
12988 hash
= micromips_op_hash
;
12989 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
12994 past
= &mips_opcodes
[NUMOPCODES
];
12996 forced_insn_length
= 0;
12999 /* We first try to match an instruction up to a space or to the end. */
13000 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13003 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13006 set_insn_error (0, _("unrecognized opcode"));
13010 if (strcmp (first
->name
, "li.s") == 0)
13012 else if (strcmp (first
->name
, "li.d") == 0)
13016 tokens
= mips_parse_arguments (str
+ end
, format
);
13020 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13021 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13022 set_insn_error (0, _("invalid operands"));
13024 obstack_free (&mips_operand_tokens
, tokens
);
13027 /* As for mips_ip, but used when assembling MIPS16 code.
13028 Also set forced_insn_length to the resulting instruction size in
13029 bytes if the user explicitly requested a small or extended instruction. */
13032 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13035 struct mips_opcode
*first
;
13036 struct mips_operand_token
*tokens
;
13038 forced_insn_length
= 0;
13040 for (s
= str
; ISLOWER (*s
); ++s
)
13054 if (s
[1] == 't' && s
[2] == ' ')
13056 forced_insn_length
= 2;
13060 else if (s
[1] == 'e' && s
[2] == ' ')
13062 forced_insn_length
= 4;
13066 /* Fall through. */
13068 set_insn_error (0, _("unrecognized opcode"));
13072 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13073 forced_insn_length
= 2;
13076 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13081 set_insn_error (0, _("unrecognized opcode"));
13085 tokens
= mips_parse_arguments (s
, 0);
13089 if (!match_mips16_insns (insn
, first
, tokens
))
13090 set_insn_error (0, _("invalid operands"));
13092 obstack_free (&mips_operand_tokens
, tokens
);
13095 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13096 NBITS is the number of significant bits in VAL. */
13098 static unsigned long
13099 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13104 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13107 else if (nbits
== 15)
13109 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13114 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13117 return (extval
<< 16) | val
;
13120 /* Like decode_mips16_operand, but require the operand to be defined and
13121 require it to be an integer. */
13123 static const struct mips_int_operand
*
13124 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13126 const struct mips_operand
*operand
;
13128 operand
= decode_mips16_operand (type
, extended_p
);
13129 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13131 return (const struct mips_int_operand
*) operand
;
13134 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13137 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13138 bfd_reloc_code_real_type reloc
, offsetT sval
)
13140 int min_val
, max_val
;
13142 min_val
= mips_int_operand_min (operand
);
13143 max_val
= mips_int_operand_max (operand
);
13144 if (reloc
!= BFD_RELOC_UNUSED
)
13147 sval
= SEXT_16BIT (sval
);
13152 return (sval
>= min_val
13154 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13157 /* Install immediate value VAL into MIPS16 instruction *INSN,
13158 extending it if necessary. The instruction in *INSN may
13159 already be extended.
13161 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13162 if none. In the former case, VAL is a 16-bit number with no
13163 defined signedness.
13165 TYPE is the type of the immediate field. USER_INSN_LENGTH
13166 is the length that the user requested, or 0 if none. */
13169 mips16_immed (char *file
, unsigned int line
, int type
,
13170 bfd_reloc_code_real_type reloc
, offsetT val
,
13171 unsigned int user_insn_length
, unsigned long *insn
)
13173 const struct mips_int_operand
*operand
;
13174 unsigned int uval
, length
;
13176 operand
= mips16_immed_operand (type
, FALSE
);
13177 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13179 /* We need an extended instruction. */
13180 if (user_insn_length
== 2)
13181 as_bad_where (file
, line
, _("invalid unextended operand value"));
13183 *insn
|= MIPS16_EXTEND
;
13185 else if (user_insn_length
== 4)
13187 /* The operand doesn't force an unextended instruction to be extended.
13188 Warn if the user wanted an extended instruction anyway. */
13189 *insn
|= MIPS16_EXTEND
;
13190 as_warn_where (file
, line
,
13191 _("extended operand requested but not required"));
13194 length
= mips16_opcode_length (*insn
);
13197 operand
= mips16_immed_operand (type
, TRUE
);
13198 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13199 as_bad_where (file
, line
,
13200 _("operand value out of range for instruction"));
13202 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13204 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13206 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13209 struct percent_op_match
13212 bfd_reloc_code_real_type reloc
;
13215 static const struct percent_op_match mips_percent_op
[] =
13217 {"%lo", BFD_RELOC_LO16
},
13218 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13219 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13220 {"%call16", BFD_RELOC_MIPS_CALL16
},
13221 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13222 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13223 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13224 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13225 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13226 {"%got", BFD_RELOC_MIPS_GOT16
},
13227 {"%gp_rel", BFD_RELOC_GPREL16
},
13228 {"%half", BFD_RELOC_16
},
13229 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13230 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13231 {"%neg", BFD_RELOC_MIPS_SUB
},
13232 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13233 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13234 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13235 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13236 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13237 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13238 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13239 {"%hi", BFD_RELOC_HI16_S
}
13242 static const struct percent_op_match mips16_percent_op
[] =
13244 {"%lo", BFD_RELOC_MIPS16_LO16
},
13245 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13246 {"%got", BFD_RELOC_MIPS16_GOT16
},
13247 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13248 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13249 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13250 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13251 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13252 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13253 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13254 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13255 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13259 /* Return true if *STR points to a relocation operator. When returning true,
13260 move *STR over the operator and store its relocation code in *RELOC.
13261 Leave both *STR and *RELOC alone when returning false. */
13264 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13266 const struct percent_op_match
*percent_op
;
13269 if (mips_opts
.mips16
)
13271 percent_op
= mips16_percent_op
;
13272 limit
= ARRAY_SIZE (mips16_percent_op
);
13276 percent_op
= mips_percent_op
;
13277 limit
= ARRAY_SIZE (mips_percent_op
);
13280 for (i
= 0; i
< limit
; i
++)
13281 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13283 int len
= strlen (percent_op
[i
].str
);
13285 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13288 *str
+= strlen (percent_op
[i
].str
);
13289 *reloc
= percent_op
[i
].reloc
;
13291 /* Check whether the output BFD supports this relocation.
13292 If not, issue an error and fall back on something safe. */
13293 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13295 as_bad (_("relocation %s isn't supported by the current ABI"),
13296 percent_op
[i
].str
);
13297 *reloc
= BFD_RELOC_UNUSED
;
13305 /* Parse string STR as a 16-bit relocatable operand. Store the
13306 expression in *EP and the relocations in the array starting
13307 at RELOC. Return the number of relocation operators used.
13309 On exit, EXPR_END points to the first character after the expression. */
13312 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13315 bfd_reloc_code_real_type reversed_reloc
[3];
13316 size_t reloc_index
, i
;
13317 int crux_depth
, str_depth
;
13320 /* Search for the start of the main expression, recoding relocations
13321 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13322 of the main expression and with CRUX_DEPTH containing the number
13323 of open brackets at that point. */
13330 crux_depth
= str_depth
;
13332 /* Skip over whitespace and brackets, keeping count of the number
13334 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13339 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13340 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13342 my_getExpression (ep
, crux
);
13345 /* Match every open bracket. */
13346 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13350 if (crux_depth
> 0)
13351 as_bad (_("unclosed '('"));
13355 if (reloc_index
!= 0)
13357 prev_reloc_op_frag
= frag_now
;
13358 for (i
= 0; i
< reloc_index
; i
++)
13359 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13362 return reloc_index
;
13366 my_getExpression (expressionS
*ep
, char *str
)
13370 save_in
= input_line_pointer
;
13371 input_line_pointer
= str
;
13373 expr_end
= input_line_pointer
;
13374 input_line_pointer
= save_in
;
13378 md_atof (int type
, char *litP
, int *sizeP
)
13380 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13384 md_number_to_chars (char *buf
, valueT val
, int n
)
13386 if (target_big_endian
)
13387 number_to_chars_bigendian (buf
, val
, n
);
13389 number_to_chars_littleendian (buf
, val
, n
);
13392 static int support_64bit_objects(void)
13394 const char **list
, **l
;
13397 list
= bfd_target_list ();
13398 for (l
= list
; *l
!= NULL
; l
++)
13399 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13400 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13402 yes
= (*l
!= NULL
);
13407 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13408 NEW_VALUE. Warn if another value was already specified. Note:
13409 we have to defer parsing the -march and -mtune arguments in order
13410 to handle 'from-abi' correctly, since the ABI might be specified
13411 in a later argument. */
13414 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13416 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13417 as_warn (_("a different %s was already specified, is now %s"),
13418 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13421 *string_ptr
= new_value
;
13425 md_parse_option (int c
, char *arg
)
13429 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13430 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13432 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13433 c
== mips_ases
[i
].option_on
);
13439 case OPTION_CONSTRUCT_FLOATS
:
13440 mips_disable_float_construction
= 0;
13443 case OPTION_NO_CONSTRUCT_FLOATS
:
13444 mips_disable_float_construction
= 1;
13456 target_big_endian
= 1;
13460 target_big_endian
= 0;
13466 else if (arg
[0] == '0')
13468 else if (arg
[0] == '1')
13478 mips_debug
= atoi (arg
);
13482 file_mips_isa
= ISA_MIPS1
;
13486 file_mips_isa
= ISA_MIPS2
;
13490 file_mips_isa
= ISA_MIPS3
;
13494 file_mips_isa
= ISA_MIPS4
;
13498 file_mips_isa
= ISA_MIPS5
;
13501 case OPTION_MIPS32
:
13502 file_mips_isa
= ISA_MIPS32
;
13505 case OPTION_MIPS32R2
:
13506 file_mips_isa
= ISA_MIPS32R2
;
13509 case OPTION_MIPS64R2
:
13510 file_mips_isa
= ISA_MIPS64R2
;
13513 case OPTION_MIPS64
:
13514 file_mips_isa
= ISA_MIPS64
;
13518 mips_set_option_string (&mips_tune_string
, arg
);
13522 mips_set_option_string (&mips_arch_string
, arg
);
13526 mips_set_option_string (&mips_arch_string
, "4650");
13527 mips_set_option_string (&mips_tune_string
, "4650");
13530 case OPTION_NO_M4650
:
13534 mips_set_option_string (&mips_arch_string
, "4010");
13535 mips_set_option_string (&mips_tune_string
, "4010");
13538 case OPTION_NO_M4010
:
13542 mips_set_option_string (&mips_arch_string
, "4100");
13543 mips_set_option_string (&mips_tune_string
, "4100");
13546 case OPTION_NO_M4100
:
13550 mips_set_option_string (&mips_arch_string
, "3900");
13551 mips_set_option_string (&mips_tune_string
, "3900");
13554 case OPTION_NO_M3900
:
13557 case OPTION_MICROMIPS
:
13558 if (mips_opts
.mips16
== 1)
13560 as_bad (_("-mmicromips cannot be used with -mips16"));
13563 mips_opts
.micromips
= 1;
13564 mips_no_prev_insn ();
13567 case OPTION_NO_MICROMIPS
:
13568 mips_opts
.micromips
= 0;
13569 mips_no_prev_insn ();
13572 case OPTION_MIPS16
:
13573 if (mips_opts
.micromips
== 1)
13575 as_bad (_("-mips16 cannot be used with -micromips"));
13578 mips_opts
.mips16
= 1;
13579 mips_no_prev_insn ();
13582 case OPTION_NO_MIPS16
:
13583 mips_opts
.mips16
= 0;
13584 mips_no_prev_insn ();
13587 case OPTION_FIX_24K
:
13591 case OPTION_NO_FIX_24K
:
13595 case OPTION_FIX_LOONGSON2F_JUMP
:
13596 mips_fix_loongson2f_jump
= TRUE
;
13599 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13600 mips_fix_loongson2f_jump
= FALSE
;
13603 case OPTION_FIX_LOONGSON2F_NOP
:
13604 mips_fix_loongson2f_nop
= TRUE
;
13607 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13608 mips_fix_loongson2f_nop
= FALSE
;
13611 case OPTION_FIX_VR4120
:
13612 mips_fix_vr4120
= 1;
13615 case OPTION_NO_FIX_VR4120
:
13616 mips_fix_vr4120
= 0;
13619 case OPTION_FIX_VR4130
:
13620 mips_fix_vr4130
= 1;
13623 case OPTION_NO_FIX_VR4130
:
13624 mips_fix_vr4130
= 0;
13627 case OPTION_FIX_CN63XXP1
:
13628 mips_fix_cn63xxp1
= TRUE
;
13631 case OPTION_NO_FIX_CN63XXP1
:
13632 mips_fix_cn63xxp1
= FALSE
;
13635 case OPTION_RELAX_BRANCH
:
13636 mips_relax_branch
= 1;
13639 case OPTION_NO_RELAX_BRANCH
:
13640 mips_relax_branch
= 0;
13643 case OPTION_INSN32
:
13644 mips_opts
.insn32
= TRUE
;
13647 case OPTION_NO_INSN32
:
13648 mips_opts
.insn32
= FALSE
;
13651 case OPTION_MSHARED
:
13652 mips_in_shared
= TRUE
;
13655 case OPTION_MNO_SHARED
:
13656 mips_in_shared
= FALSE
;
13659 case OPTION_MSYM32
:
13660 mips_opts
.sym32
= TRUE
;
13663 case OPTION_MNO_SYM32
:
13664 mips_opts
.sym32
= FALSE
;
13667 /* When generating ELF code, we permit -KPIC and -call_shared to
13668 select SVR4_PIC, and -non_shared to select no PIC. This is
13669 intended to be compatible with Irix 5. */
13670 case OPTION_CALL_SHARED
:
13671 mips_pic
= SVR4_PIC
;
13672 mips_abicalls
= TRUE
;
13675 case OPTION_CALL_NONPIC
:
13677 mips_abicalls
= TRUE
;
13680 case OPTION_NON_SHARED
:
13682 mips_abicalls
= FALSE
;
13685 /* The -xgot option tells the assembler to use 32 bit offsets
13686 when accessing the got in SVR4_PIC mode. It is for Irix
13693 g_switch_value
= atoi (arg
);
13697 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13700 mips_abi
= O32_ABI
;
13704 mips_abi
= N32_ABI
;
13708 mips_abi
= N64_ABI
;
13709 if (!support_64bit_objects())
13710 as_fatal (_("no compiled in support for 64 bit object file format"));
13714 file_mips_gp32
= 1;
13718 file_mips_gp32
= 0;
13722 file_mips_fp32
= 1;
13726 file_mips_fp32
= 0;
13729 case OPTION_SINGLE_FLOAT
:
13730 file_mips_single_float
= 1;
13733 case OPTION_DOUBLE_FLOAT
:
13734 file_mips_single_float
= 0;
13737 case OPTION_SOFT_FLOAT
:
13738 file_mips_soft_float
= 1;
13741 case OPTION_HARD_FLOAT
:
13742 file_mips_soft_float
= 0;
13746 if (strcmp (arg
, "32") == 0)
13747 mips_abi
= O32_ABI
;
13748 else if (strcmp (arg
, "o64") == 0)
13749 mips_abi
= O64_ABI
;
13750 else if (strcmp (arg
, "n32") == 0)
13751 mips_abi
= N32_ABI
;
13752 else if (strcmp (arg
, "64") == 0)
13754 mips_abi
= N64_ABI
;
13755 if (! support_64bit_objects())
13756 as_fatal (_("no compiled in support for 64 bit object file "
13759 else if (strcmp (arg
, "eabi") == 0)
13760 mips_abi
= EABI_ABI
;
13763 as_fatal (_("invalid abi -mabi=%s"), arg
);
13768 case OPTION_M7000_HILO_FIX
:
13769 mips_7000_hilo_fix
= TRUE
;
13772 case OPTION_MNO_7000_HILO_FIX
:
13773 mips_7000_hilo_fix
= FALSE
;
13776 case OPTION_MDEBUG
:
13777 mips_flag_mdebug
= TRUE
;
13780 case OPTION_NO_MDEBUG
:
13781 mips_flag_mdebug
= FALSE
;
13785 mips_flag_pdr
= TRUE
;
13788 case OPTION_NO_PDR
:
13789 mips_flag_pdr
= FALSE
;
13792 case OPTION_MVXWORKS_PIC
:
13793 mips_pic
= VXWORKS_PIC
;
13797 if (strcmp (arg
, "2008") == 0)
13798 mips_flag_nan2008
= TRUE
;
13799 else if (strcmp (arg
, "legacy") == 0)
13800 mips_flag_nan2008
= FALSE
;
13803 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
13812 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13817 /* Set up globals to generate code for the ISA or processor
13818 described by INFO. */
13821 mips_set_architecture (const struct mips_cpu_info
*info
)
13825 file_mips_arch
= info
->cpu
;
13826 mips_opts
.arch
= info
->cpu
;
13827 mips_opts
.isa
= info
->isa
;
13832 /* Likewise for tuning. */
13835 mips_set_tune (const struct mips_cpu_info
*info
)
13838 mips_tune
= info
->cpu
;
13843 mips_after_parse_args (void)
13845 const struct mips_cpu_info
*arch_info
= 0;
13846 const struct mips_cpu_info
*tune_info
= 0;
13848 /* GP relative stuff not working for PE */
13849 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13851 if (g_switch_seen
&& g_switch_value
!= 0)
13852 as_bad (_("-G not supported in this configuration"));
13853 g_switch_value
= 0;
13856 if (mips_abi
== NO_ABI
)
13857 mips_abi
= MIPS_DEFAULT_ABI
;
13859 /* The following code determines the architecture and register size.
13860 Similar code was added to GCC 3.3 (see override_options() in
13861 config/mips/mips.c). The GAS and GCC code should be kept in sync
13862 as much as possible. */
13864 if (mips_arch_string
!= 0)
13865 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13867 if (file_mips_isa
!= ISA_UNKNOWN
)
13869 /* Handle -mipsN. At this point, file_mips_isa contains the
13870 ISA level specified by -mipsN, while arch_info->isa contains
13871 the -march selection (if any). */
13872 if (arch_info
!= 0)
13874 /* -march takes precedence over -mipsN, since it is more descriptive.
13875 There's no harm in specifying both as long as the ISA levels
13877 if (file_mips_isa
!= arch_info
->isa
)
13878 as_bad (_("-%s conflicts with the other architecture options,"
13879 " which imply -%s"),
13880 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13881 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13884 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13887 if (arch_info
== 0)
13889 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13890 gas_assert (arch_info
);
13893 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13894 as_bad (_("-march=%s is not compatible with the selected ABI"),
13897 mips_set_architecture (arch_info
);
13899 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13900 if (mips_tune_string
!= 0)
13901 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13903 if (tune_info
== 0)
13904 mips_set_tune (arch_info
);
13906 mips_set_tune (tune_info
);
13908 if (file_mips_gp32
>= 0)
13910 /* The user specified the size of the integer registers. Make sure
13911 it agrees with the ABI and ISA. */
13912 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13913 as_bad (_("-mgp64 used with a 32-bit processor"));
13914 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
13915 as_bad (_("-mgp32 used with a 64-bit ABI"));
13916 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
13917 as_bad (_("-mgp64 used with a 32-bit ABI"));
13921 /* Infer the integer register size from the ABI and processor.
13922 Restrict ourselves to 32-bit registers if that's all the
13923 processor has, or if the ABI cannot handle 64-bit registers. */
13924 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
13925 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
13928 switch (file_mips_fp32
)
13932 /* No user specified float register size.
13933 ??? GAS treats single-float processors as though they had 64-bit
13934 float registers (although it complains when double-precision
13935 instructions are used). As things stand, saying they have 32-bit
13936 registers would lead to spurious "register must be even" messages.
13937 So here we assume float registers are never smaller than the
13939 if (file_mips_gp32
== 0)
13940 /* 64-bit integer registers implies 64-bit float registers. */
13941 file_mips_fp32
= 0;
13942 else if ((mips_opts
.ase
& FP64_ASES
)
13943 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13944 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13945 file_mips_fp32
= 0;
13947 /* 32-bit float registers. */
13948 file_mips_fp32
= 1;
13951 /* The user specified the size of the float registers. Check if it
13952 agrees with the ABI and ISA. */
13954 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13955 as_bad (_("-mfp64 used with a 32-bit fpu"));
13956 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
13957 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
13958 as_warn (_("-mfp64 used with a 32-bit ABI"));
13961 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13962 as_warn (_("-mfp32 used with a 64-bit ABI"));
13966 /* End of GCC-shared inference code. */
13968 /* This flag is set when we have a 64-bit capable CPU but use only
13969 32-bit wide registers. Note that EABI does not use it. */
13970 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
13971 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
13972 || mips_abi
== O32_ABI
))
13973 mips_32bitmode
= 1;
13975 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
13976 as_bad (_("trap exception not supported at ISA 1"));
13978 /* If the selected architecture includes support for ASEs, enable
13979 generation of code for them. */
13980 if (mips_opts
.mips16
== -1)
13981 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
13982 if (mips_opts
.micromips
== -1)
13983 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
13985 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13986 ASEs from being selected implicitly. */
13987 if (file_mips_fp32
== 1)
13988 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
13990 /* If the user didn't explicitly select or deselect a particular ASE,
13991 use the default setting for the CPU. */
13992 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
13994 file_mips_isa
= mips_opts
.isa
;
13995 file_ase
= mips_opts
.ase
;
13996 mips_opts
.gp32
= file_mips_gp32
;
13997 mips_opts
.fp32
= file_mips_fp32
;
13998 mips_opts
.soft_float
= file_mips_soft_float
;
13999 mips_opts
.single_float
= file_mips_single_float
;
14001 mips_check_isa_supports_ases ();
14003 if (mips_flag_mdebug
< 0)
14004 mips_flag_mdebug
= 0;
14008 mips_init_after_args (void)
14010 /* initialize opcodes */
14011 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14012 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14016 md_pcrel_from (fixS
*fixP
)
14018 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14019 switch (fixP
->fx_r_type
)
14021 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14022 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14023 /* Return the address of the delay slot. */
14026 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14027 case BFD_RELOC_MICROMIPS_JMP
:
14028 case BFD_RELOC_16_PCREL_S2
:
14029 case BFD_RELOC_MIPS_JMP
:
14030 /* Return the address of the delay slot. */
14033 case BFD_RELOC_32_PCREL
:
14037 /* We have no relocation type for PC relative MIPS16 instructions. */
14038 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
14039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14040 _("PC relative MIPS16 instruction references"
14041 " a different section"));
14046 /* This is called before the symbol table is processed. In order to
14047 work with gcc when using mips-tfile, we must keep all local labels.
14048 However, in other cases, we want to discard them. If we were
14049 called with -g, but we didn't see any debugging information, it may
14050 mean that gcc is smuggling debugging information through to
14051 mips-tfile, in which case we must generate all local labels. */
14054 mips_frob_file_before_adjust (void)
14056 #ifndef NO_ECOFF_DEBUGGING
14057 if (ECOFF_DEBUGGING
14059 && ! ecoff_debugging_seen
)
14060 flag_keep_locals
= 1;
14064 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14065 the corresponding LO16 reloc. This is called before md_apply_fix and
14066 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14067 relocation operators.
14069 For our purposes, a %lo() expression matches a %got() or %hi()
14072 (a) it refers to the same symbol; and
14073 (b) the offset applied in the %lo() expression is no lower than
14074 the offset applied in the %got() or %hi().
14076 (b) allows us to cope with code like:
14079 lh $4,%lo(foo+2)($4)
14081 ...which is legal on RELA targets, and has a well-defined behaviour
14082 if the user knows that adding 2 to "foo" will not induce a carry to
14085 When several %lo()s match a particular %got() or %hi(), we use the
14086 following rules to distinguish them:
14088 (1) %lo()s with smaller offsets are a better match than %lo()s with
14091 (2) %lo()s with no matching %got() or %hi() are better than those
14092 that already have a matching %got() or %hi().
14094 (3) later %lo()s are better than earlier %lo()s.
14096 These rules are applied in order.
14098 (1) means, among other things, that %lo()s with identical offsets are
14099 chosen if they exist.
14101 (2) means that we won't associate several high-part relocations with
14102 the same low-part relocation unless there's no alternative. Having
14103 several high parts for the same low part is a GNU extension; this rule
14104 allows careful users to avoid it.
14106 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14107 with the last high-part relocation being at the front of the list.
14108 It therefore makes sense to choose the last matching low-part
14109 relocation, all other things being equal. It's also easier
14110 to code that way. */
14113 mips_frob_file (void)
14115 struct mips_hi_fixup
*l
;
14116 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14118 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14120 segment_info_type
*seginfo
;
14121 bfd_boolean matched_lo_p
;
14122 fixS
**hi_pos
, **lo_pos
, **pos
;
14124 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14126 /* If a GOT16 relocation turns out to be against a global symbol,
14127 there isn't supposed to be a matching LO. Ignore %gots against
14128 constants; we'll report an error for those later. */
14129 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14130 && !(l
->fixp
->fx_addsy
14131 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14134 /* Check quickly whether the next fixup happens to be a matching %lo. */
14135 if (fixup_has_matching_lo_p (l
->fixp
))
14138 seginfo
= seg_info (l
->seg
);
14140 /* Set HI_POS to the position of this relocation in the chain.
14141 Set LO_POS to the position of the chosen low-part relocation.
14142 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14143 relocation that matches an immediately-preceding high-part
14147 matched_lo_p
= FALSE
;
14148 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14150 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14152 if (*pos
== l
->fixp
)
14155 if ((*pos
)->fx_r_type
== looking_for_rtype
14156 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14157 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14159 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14161 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14164 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14165 && fixup_has_matching_lo_p (*pos
));
14168 /* If we found a match, remove the high-part relocation from its
14169 current position and insert it before the low-part relocation.
14170 Make the offsets match so that fixup_has_matching_lo_p()
14173 We don't warn about unmatched high-part relocations since some
14174 versions of gcc have been known to emit dead "lui ...%hi(...)"
14176 if (lo_pos
!= NULL
)
14178 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14179 if (l
->fixp
->fx_next
!= *lo_pos
)
14181 *hi_pos
= l
->fixp
->fx_next
;
14182 l
->fixp
->fx_next
= *lo_pos
;
14190 mips_force_relocation (fixS
*fixp
)
14192 if (generic_force_reloc (fixp
))
14195 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14196 so that the linker relaxation can update targets. */
14197 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14198 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14199 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14205 /* Read the instruction associated with RELOC from BUF. */
14207 static unsigned int
14208 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14210 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14211 return read_compressed_insn (buf
, 4);
14213 return read_insn (buf
);
14216 /* Write instruction INSN to BUF, given that it has been relocated
14220 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14221 unsigned long insn
)
14223 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14224 write_compressed_insn (buf
, insn
, 4);
14226 write_insn (buf
, insn
);
14229 /* Apply a fixup to the object file. */
14232 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14235 unsigned long insn
;
14236 reloc_howto_type
*howto
;
14238 /* We ignore generic BFD relocations we don't know about. */
14239 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14243 gas_assert (fixP
->fx_size
== 2
14244 || fixP
->fx_size
== 4
14245 || fixP
->fx_r_type
== BFD_RELOC_16
14246 || fixP
->fx_r_type
== BFD_RELOC_64
14247 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14248 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14249 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14250 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14251 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14252 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14254 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14256 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14257 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14258 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14259 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
14260 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
14262 /* Don't treat parts of a composite relocation as done. There are two
14265 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14266 should nevertheless be emitted if the first part is.
14268 (2) In normal usage, composite relocations are never assembly-time
14269 constants. The easiest way of dealing with the pathological
14270 exceptions is to generate a relocation against STN_UNDEF and
14271 leave everything up to the linker. */
14272 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14275 switch (fixP
->fx_r_type
)
14277 case BFD_RELOC_MIPS_TLS_GD
:
14278 case BFD_RELOC_MIPS_TLS_LDM
:
14279 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14280 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14281 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14282 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14283 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14284 case BFD_RELOC_MIPS_TLS_TPREL32
:
14285 case BFD_RELOC_MIPS_TLS_TPREL64
:
14286 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14287 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14288 case BFD_RELOC_MICROMIPS_TLS_GD
:
14289 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14290 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14291 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14292 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14293 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14294 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14295 case BFD_RELOC_MIPS16_TLS_GD
:
14296 case BFD_RELOC_MIPS16_TLS_LDM
:
14297 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14298 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14299 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14300 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14301 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14302 if (!fixP
->fx_addsy
)
14304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14305 _("TLS relocation against a constant"));
14308 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14311 case BFD_RELOC_MIPS_JMP
:
14312 case BFD_RELOC_MIPS_SHIFT5
:
14313 case BFD_RELOC_MIPS_SHIFT6
:
14314 case BFD_RELOC_MIPS_GOT_DISP
:
14315 case BFD_RELOC_MIPS_GOT_PAGE
:
14316 case BFD_RELOC_MIPS_GOT_OFST
:
14317 case BFD_RELOC_MIPS_SUB
:
14318 case BFD_RELOC_MIPS_INSERT_A
:
14319 case BFD_RELOC_MIPS_INSERT_B
:
14320 case BFD_RELOC_MIPS_DELETE
:
14321 case BFD_RELOC_MIPS_HIGHEST
:
14322 case BFD_RELOC_MIPS_HIGHER
:
14323 case BFD_RELOC_MIPS_SCN_DISP
:
14324 case BFD_RELOC_MIPS_REL16
:
14325 case BFD_RELOC_MIPS_RELGOT
:
14326 case BFD_RELOC_MIPS_JALR
:
14327 case BFD_RELOC_HI16
:
14328 case BFD_RELOC_HI16_S
:
14329 case BFD_RELOC_LO16
:
14330 case BFD_RELOC_GPREL16
:
14331 case BFD_RELOC_MIPS_LITERAL
:
14332 case BFD_RELOC_MIPS_CALL16
:
14333 case BFD_RELOC_MIPS_GOT16
:
14334 case BFD_RELOC_GPREL32
:
14335 case BFD_RELOC_MIPS_GOT_HI16
:
14336 case BFD_RELOC_MIPS_GOT_LO16
:
14337 case BFD_RELOC_MIPS_CALL_HI16
:
14338 case BFD_RELOC_MIPS_CALL_LO16
:
14339 case BFD_RELOC_MIPS16_GPREL
:
14340 case BFD_RELOC_MIPS16_GOT16
:
14341 case BFD_RELOC_MIPS16_CALL16
:
14342 case BFD_RELOC_MIPS16_HI16
:
14343 case BFD_RELOC_MIPS16_HI16_S
:
14344 case BFD_RELOC_MIPS16_LO16
:
14345 case BFD_RELOC_MIPS16_JMP
:
14346 case BFD_RELOC_MICROMIPS_JMP
:
14347 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14348 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14349 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14350 case BFD_RELOC_MICROMIPS_SUB
:
14351 case BFD_RELOC_MICROMIPS_HIGHEST
:
14352 case BFD_RELOC_MICROMIPS_HIGHER
:
14353 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14354 case BFD_RELOC_MICROMIPS_JALR
:
14355 case BFD_RELOC_MICROMIPS_HI16
:
14356 case BFD_RELOC_MICROMIPS_HI16_S
:
14357 case BFD_RELOC_MICROMIPS_LO16
:
14358 case BFD_RELOC_MICROMIPS_GPREL16
:
14359 case BFD_RELOC_MICROMIPS_LITERAL
:
14360 case BFD_RELOC_MICROMIPS_CALL16
:
14361 case BFD_RELOC_MICROMIPS_GOT16
:
14362 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14363 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14364 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14365 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14366 case BFD_RELOC_MIPS_EH
:
14371 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14373 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14374 if (mips16_reloc_p (fixP
->fx_r_type
))
14375 insn
|= mips16_immed_extend (value
, 16);
14377 insn
|= (value
& 0xffff);
14378 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14381 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14382 _("unsupported constant in relocation"));
14387 /* This is handled like BFD_RELOC_32, but we output a sign
14388 extended value if we are only 32 bits. */
14391 if (8 <= sizeof (valueT
))
14392 md_number_to_chars (buf
, *valP
, 8);
14397 if ((*valP
& 0x80000000) != 0)
14401 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14402 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14407 case BFD_RELOC_RVA
:
14409 case BFD_RELOC_32_PCREL
:
14411 /* If we are deleting this reloc entry, we must fill in the
14412 value now. This can happen if we have a .word which is not
14413 resolved when it appears but is later defined. */
14415 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14418 case BFD_RELOC_16_PCREL_S2
:
14419 if ((*valP
& 0x3) != 0)
14420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14421 _("branch to misaligned address (%lx)"), (long) *valP
);
14423 /* We need to save the bits in the instruction since fixup_segment()
14424 might be deleting the relocation entry (i.e., a branch within
14425 the current segment). */
14426 if (! fixP
->fx_done
)
14429 /* Update old instruction data. */
14430 insn
= read_insn (buf
);
14432 if (*valP
+ 0x20000 <= 0x3ffff)
14434 insn
|= (*valP
>> 2) & 0xffff;
14435 write_insn (buf
, insn
);
14437 else if (mips_pic
== NO_PIC
14439 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14440 && (fixP
->fx_frag
->fr_address
14441 < text_section
->vma
+ bfd_get_section_size (text_section
))
14442 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14443 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14444 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14446 /* The branch offset is too large. If this is an
14447 unconditional branch, and we are not generating PIC code,
14448 we can convert it to an absolute jump instruction. */
14449 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14450 insn
= 0x0c000000; /* jal */
14452 insn
= 0x08000000; /* j */
14453 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14455 fixP
->fx_addsy
= section_symbol (text_section
);
14456 *valP
+= md_pcrel_from (fixP
);
14457 write_insn (buf
, insn
);
14461 /* If we got here, we have branch-relaxation disabled,
14462 and there's nothing we can do to fix this instruction
14463 without turning it into a longer sequence. */
14464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14465 _("branch out of range"));
14469 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14470 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14471 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14472 /* We adjust the offset back to even. */
14473 if ((*valP
& 0x1) != 0)
14476 if (! fixP
->fx_done
)
14479 /* Should never visit here, because we keep the relocation. */
14483 case BFD_RELOC_VTABLE_INHERIT
:
14486 && !S_IS_DEFINED (fixP
->fx_addsy
)
14487 && !S_IS_WEAK (fixP
->fx_addsy
))
14488 S_SET_WEAK (fixP
->fx_addsy
);
14491 case BFD_RELOC_VTABLE_ENTRY
:
14499 /* Remember value for tc_gen_reloc. */
14500 fixP
->fx_addnumber
= *valP
;
14510 name
= input_line_pointer
;
14511 c
= get_symbol_end ();
14512 p
= (symbolS
*) symbol_find_or_make (name
);
14513 *input_line_pointer
= c
;
14517 /* Align the current frag to a given power of two. If a particular
14518 fill byte should be used, FILL points to an integer that contains
14519 that byte, otherwise FILL is null.
14521 This function used to have the comment:
14523 The MIPS assembler also automatically adjusts any preceding label.
14525 The implementation therefore applied the adjustment to a maximum of
14526 one label. However, other label adjustments are applied to batches
14527 of labels, and adjusting just one caused problems when new labels
14528 were added for the sake of debugging or unwind information.
14529 We therefore adjust all preceding labels (given as LABELS) instead. */
14532 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14534 mips_emit_delays ();
14535 mips_record_compressed_mode ();
14536 if (fill
== NULL
&& subseg_text_p (now_seg
))
14537 frag_align_code (to
, 0);
14539 frag_align (to
, fill
? *fill
: 0, 0);
14540 record_alignment (now_seg
, to
);
14541 mips_move_labels (labels
, FALSE
);
14544 /* Align to a given power of two. .align 0 turns off the automatic
14545 alignment used by the data creating pseudo-ops. */
14548 s_align (int x ATTRIBUTE_UNUSED
)
14550 int temp
, fill_value
, *fill_ptr
;
14551 long max_alignment
= 28;
14553 /* o Note that the assembler pulls down any immediately preceding label
14554 to the aligned address.
14555 o It's not documented but auto alignment is reinstated by
14556 a .align pseudo instruction.
14557 o Note also that after auto alignment is turned off the mips assembler
14558 issues an error on attempt to assemble an improperly aligned data item.
14561 temp
= get_absolute_expression ();
14562 if (temp
> max_alignment
)
14563 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
14566 as_warn (_("alignment negative, 0 assumed"));
14569 if (*input_line_pointer
== ',')
14571 ++input_line_pointer
;
14572 fill_value
= get_absolute_expression ();
14573 fill_ptr
= &fill_value
;
14579 segment_info_type
*si
= seg_info (now_seg
);
14580 struct insn_label_list
*l
= si
->label_list
;
14581 /* Auto alignment should be switched on by next section change. */
14583 mips_align (temp
, fill_ptr
, l
);
14590 demand_empty_rest_of_line ();
14594 s_change_sec (int sec
)
14598 /* The ELF backend needs to know that we are changing sections, so
14599 that .previous works correctly. We could do something like check
14600 for an obj_section_change_hook macro, but that might be confusing
14601 as it would not be appropriate to use it in the section changing
14602 functions in read.c, since obj-elf.c intercepts those. FIXME:
14603 This should be cleaner, somehow. */
14604 obj_elf_section_change_hook ();
14606 mips_emit_delays ();
14617 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14618 demand_empty_rest_of_line ();
14622 seg
= subseg_new (RDATA_SECTION_NAME
,
14623 (subsegT
) get_absolute_expression ());
14624 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14625 | SEC_READONLY
| SEC_RELOC
14627 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14628 record_alignment (seg
, 4);
14629 demand_empty_rest_of_line ();
14633 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14634 bfd_set_section_flags (stdoutput
, seg
,
14635 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14636 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14637 record_alignment (seg
, 4);
14638 demand_empty_rest_of_line ();
14642 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14643 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14644 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14645 record_alignment (seg
, 4);
14646 demand_empty_rest_of_line ();
14654 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14656 char *section_name
;
14661 int section_entry_size
;
14662 int section_alignment
;
14664 section_name
= input_line_pointer
;
14665 c
= get_symbol_end ();
14667 next_c
= *(input_line_pointer
+ 1);
14669 /* Do we have .section Name<,"flags">? */
14670 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14672 /* just after name is now '\0'. */
14673 *input_line_pointer
= c
;
14674 input_line_pointer
= section_name
;
14675 obj_elf_section (ignore
);
14678 input_line_pointer
++;
14680 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14682 section_type
= get_absolute_expression ();
14685 if (*input_line_pointer
++ == ',')
14686 section_flag
= get_absolute_expression ();
14689 if (*input_line_pointer
++ == ',')
14690 section_entry_size
= get_absolute_expression ();
14692 section_entry_size
= 0;
14693 if (*input_line_pointer
++ == ',')
14694 section_alignment
= get_absolute_expression ();
14696 section_alignment
= 0;
14697 /* FIXME: really ignore? */
14698 (void) section_alignment
;
14700 section_name
= xstrdup (section_name
);
14702 /* When using the generic form of .section (as implemented by obj-elf.c),
14703 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14704 traditionally had to fall back on the more common @progbits instead.
14706 There's nothing really harmful in this, since bfd will correct
14707 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14708 means that, for backwards compatibility, the special_section entries
14709 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14711 Even so, we shouldn't force users of the MIPS .section syntax to
14712 incorrectly label the sections as SHT_PROGBITS. The best compromise
14713 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14714 generic type-checking code. */
14715 if (section_type
== SHT_MIPS_DWARF
)
14716 section_type
= SHT_PROGBITS
;
14718 obj_elf_change_section (section_name
, section_type
, section_flag
,
14719 section_entry_size
, 0, 0, 0);
14721 if (now_seg
->name
!= section_name
)
14722 free (section_name
);
14726 mips_enable_auto_align (void)
14732 s_cons (int log_size
)
14734 segment_info_type
*si
= seg_info (now_seg
);
14735 struct insn_label_list
*l
= si
->label_list
;
14737 mips_emit_delays ();
14738 if (log_size
> 0 && auto_align
)
14739 mips_align (log_size
, 0, l
);
14740 cons (1 << log_size
);
14741 mips_clear_insn_labels ();
14745 s_float_cons (int type
)
14747 segment_info_type
*si
= seg_info (now_seg
);
14748 struct insn_label_list
*l
= si
->label_list
;
14750 mips_emit_delays ();
14755 mips_align (3, 0, l
);
14757 mips_align (2, 0, l
);
14761 mips_clear_insn_labels ();
14764 /* Handle .globl. We need to override it because on Irix 5 you are
14767 where foo is an undefined symbol, to mean that foo should be
14768 considered to be the address of a function. */
14771 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14780 name
= input_line_pointer
;
14781 c
= get_symbol_end ();
14782 symbolP
= symbol_find_or_make (name
);
14783 S_SET_EXTERNAL (symbolP
);
14785 *input_line_pointer
= c
;
14786 SKIP_WHITESPACE ();
14788 /* On Irix 5, every global symbol that is not explicitly labelled as
14789 being a function is apparently labelled as being an object. */
14792 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14793 && (*input_line_pointer
!= ','))
14798 secname
= input_line_pointer
;
14799 c
= get_symbol_end ();
14800 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14802 as_bad (_("%s: no such section"), secname
);
14803 *input_line_pointer
= c
;
14805 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14806 flag
= BSF_FUNCTION
;
14809 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14811 c
= *input_line_pointer
;
14814 input_line_pointer
++;
14815 SKIP_WHITESPACE ();
14816 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14822 demand_empty_rest_of_line ();
14826 s_option (int x ATTRIBUTE_UNUSED
)
14831 opt
= input_line_pointer
;
14832 c
= get_symbol_end ();
14836 /* FIXME: What does this mean? */
14838 else if (strncmp (opt
, "pic", 3) == 0)
14842 i
= atoi (opt
+ 3);
14847 mips_pic
= SVR4_PIC
;
14848 mips_abicalls
= TRUE
;
14851 as_bad (_(".option pic%d not supported"), i
);
14853 if (mips_pic
== SVR4_PIC
)
14855 if (g_switch_seen
&& g_switch_value
!= 0)
14856 as_warn (_("-G may not be used with SVR4 PIC code"));
14857 g_switch_value
= 0;
14858 bfd_set_gp_size (stdoutput
, 0);
14862 as_warn (_("unrecognized option \"%s\""), opt
);
14864 *input_line_pointer
= c
;
14865 demand_empty_rest_of_line ();
14868 /* This structure is used to hold a stack of .set values. */
14870 struct mips_option_stack
14872 struct mips_option_stack
*next
;
14873 struct mips_set_options options
;
14876 static struct mips_option_stack
*mips_opts_stack
;
14878 /* Handle the .set pseudo-op. */
14881 s_mipsset (int x ATTRIBUTE_UNUSED
)
14883 char *name
= input_line_pointer
, ch
;
14884 const struct mips_ase
*ase
;
14886 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14887 ++input_line_pointer
;
14888 ch
= *input_line_pointer
;
14889 *input_line_pointer
= '\0';
14891 if (strcmp (name
, "reorder") == 0)
14893 if (mips_opts
.noreorder
)
14896 else if (strcmp (name
, "noreorder") == 0)
14898 if (!mips_opts
.noreorder
)
14899 start_noreorder ();
14901 else if (strncmp (name
, "at=", 3) == 0)
14903 char *s
= name
+ 3;
14905 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
14906 as_bad (_("unrecognized register name `%s'"), s
);
14908 else if (strcmp (name
, "at") == 0)
14910 mips_opts
.at
= ATREG
;
14912 else if (strcmp (name
, "noat") == 0)
14914 mips_opts
.at
= ZERO
;
14916 else if (strcmp (name
, "macro") == 0)
14918 mips_opts
.warn_about_macros
= 0;
14920 else if (strcmp (name
, "nomacro") == 0)
14922 if (mips_opts
.noreorder
== 0)
14923 as_bad (_("`noreorder' must be set before `nomacro'"));
14924 mips_opts
.warn_about_macros
= 1;
14926 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
14928 mips_opts
.nomove
= 0;
14930 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
14932 mips_opts
.nomove
= 1;
14934 else if (strcmp (name
, "bopt") == 0)
14936 mips_opts
.nobopt
= 0;
14938 else if (strcmp (name
, "nobopt") == 0)
14940 mips_opts
.nobopt
= 1;
14942 else if (strcmp (name
, "gp=default") == 0)
14943 mips_opts
.gp32
= file_mips_gp32
;
14944 else if (strcmp (name
, "gp=32") == 0)
14945 mips_opts
.gp32
= 1;
14946 else if (strcmp (name
, "gp=64") == 0)
14948 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14949 as_warn (_("%s isa does not support 64-bit registers"),
14950 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14951 mips_opts
.gp32
= 0;
14953 else if (strcmp (name
, "fp=default") == 0)
14954 mips_opts
.fp32
= file_mips_fp32
;
14955 else if (strcmp (name
, "fp=32") == 0)
14956 mips_opts
.fp32
= 1;
14957 else if (strcmp (name
, "fp=64") == 0)
14959 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14960 as_warn (_("%s isa does not support 64-bit floating point registers"),
14961 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14962 mips_opts
.fp32
= 0;
14964 else if (strcmp (name
, "softfloat") == 0)
14965 mips_opts
.soft_float
= 1;
14966 else if (strcmp (name
, "hardfloat") == 0)
14967 mips_opts
.soft_float
= 0;
14968 else if (strcmp (name
, "singlefloat") == 0)
14969 mips_opts
.single_float
= 1;
14970 else if (strcmp (name
, "doublefloat") == 0)
14971 mips_opts
.single_float
= 0;
14972 else if (strcmp (name
, "mips16") == 0
14973 || strcmp (name
, "MIPS-16") == 0)
14975 if (mips_opts
.micromips
== 1)
14976 as_fatal (_("`mips16' cannot be used with `micromips'"));
14977 mips_opts
.mips16
= 1;
14979 else if (strcmp (name
, "nomips16") == 0
14980 || strcmp (name
, "noMIPS-16") == 0)
14981 mips_opts
.mips16
= 0;
14982 else if (strcmp (name
, "micromips") == 0)
14984 if (mips_opts
.mips16
== 1)
14985 as_fatal (_("`micromips' cannot be used with `mips16'"));
14986 mips_opts
.micromips
= 1;
14988 else if (strcmp (name
, "nomicromips") == 0)
14989 mips_opts
.micromips
= 0;
14990 else if (name
[0] == 'n'
14992 && (ase
= mips_lookup_ase (name
+ 2)))
14993 mips_set_ase (ase
, FALSE
);
14994 else if ((ase
= mips_lookup_ase (name
)))
14995 mips_set_ase (ase
, TRUE
);
14996 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15000 /* Permit the user to change the ISA and architecture on the fly.
15001 Needless to say, misuse can cause serious problems. */
15002 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15005 mips_opts
.isa
= file_mips_isa
;
15006 mips_opts
.arch
= file_mips_arch
;
15008 else if (strncmp (name
, "arch=", 5) == 0)
15010 const struct mips_cpu_info
*p
;
15012 p
= mips_parse_cpu("internal use", name
+ 5);
15014 as_bad (_("unknown architecture %s"), name
+ 5);
15017 mips_opts
.arch
= p
->cpu
;
15018 mips_opts
.isa
= p
->isa
;
15021 else if (strncmp (name
, "mips", 4) == 0)
15023 const struct mips_cpu_info
*p
;
15025 p
= mips_parse_cpu("internal use", name
);
15027 as_bad (_("unknown ISA level %s"), name
+ 4);
15030 mips_opts
.arch
= p
->cpu
;
15031 mips_opts
.isa
= p
->isa
;
15035 as_bad (_("unknown ISA or architecture %s"), name
);
15037 switch (mips_opts
.isa
)
15045 mips_opts
.gp32
= 1;
15046 mips_opts
.fp32
= 1;
15053 mips_opts
.gp32
= 0;
15054 if (mips_opts
.arch
== CPU_R5900
)
15056 mips_opts
.fp32
= 1;
15060 mips_opts
.fp32
= 0;
15064 as_bad (_("unknown ISA level %s"), name
+ 4);
15069 mips_opts
.gp32
= file_mips_gp32
;
15070 mips_opts
.fp32
= file_mips_fp32
;
15073 else if (strcmp (name
, "autoextend") == 0)
15074 mips_opts
.noautoextend
= 0;
15075 else if (strcmp (name
, "noautoextend") == 0)
15076 mips_opts
.noautoextend
= 1;
15077 else if (strcmp (name
, "insn32") == 0)
15078 mips_opts
.insn32
= TRUE
;
15079 else if (strcmp (name
, "noinsn32") == 0)
15080 mips_opts
.insn32
= FALSE
;
15081 else if (strcmp (name
, "push") == 0)
15083 struct mips_option_stack
*s
;
15085 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15086 s
->next
= mips_opts_stack
;
15087 s
->options
= mips_opts
;
15088 mips_opts_stack
= s
;
15090 else if (strcmp (name
, "pop") == 0)
15092 struct mips_option_stack
*s
;
15094 s
= mips_opts_stack
;
15096 as_bad (_(".set pop with no .set push"));
15099 /* If we're changing the reorder mode we need to handle
15100 delay slots correctly. */
15101 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15102 start_noreorder ();
15103 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15106 mips_opts
= s
->options
;
15107 mips_opts_stack
= s
->next
;
15111 else if (strcmp (name
, "sym32") == 0)
15112 mips_opts
.sym32
= TRUE
;
15113 else if (strcmp (name
, "nosym32") == 0)
15114 mips_opts
.sym32
= FALSE
;
15115 else if (strchr (name
, ','))
15117 /* Generic ".set" directive; use the generic handler. */
15118 *input_line_pointer
= ch
;
15119 input_line_pointer
= name
;
15125 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
15127 mips_check_isa_supports_ases ();
15128 *input_line_pointer
= ch
;
15129 demand_empty_rest_of_line ();
15132 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15133 .option pic2. It means to generate SVR4 PIC calls. */
15136 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15138 mips_pic
= SVR4_PIC
;
15139 mips_abicalls
= TRUE
;
15141 if (g_switch_seen
&& g_switch_value
!= 0)
15142 as_warn (_("-G may not be used with SVR4 PIC code"));
15143 g_switch_value
= 0;
15145 bfd_set_gp_size (stdoutput
, 0);
15146 demand_empty_rest_of_line ();
15149 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15150 PIC code. It sets the $gp register for the function based on the
15151 function address, which is in the register named in the argument.
15152 This uses a relocation against _gp_disp, which is handled specially
15153 by the linker. The result is:
15154 lui $gp,%hi(_gp_disp)
15155 addiu $gp,$gp,%lo(_gp_disp)
15156 addu $gp,$gp,.cpload argument
15157 The .cpload argument is normally $25 == $t9.
15159 The -mno-shared option changes this to:
15160 lui $gp,%hi(__gnu_local_gp)
15161 addiu $gp,$gp,%lo(__gnu_local_gp)
15162 and the argument is ignored. This saves an instruction, but the
15163 resulting code is not position independent; it uses an absolute
15164 address for __gnu_local_gp. Thus code assembled with -mno-shared
15165 can go into an ordinary executable, but not into a shared library. */
15168 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15174 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15175 .cpload is ignored. */
15176 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15182 if (mips_opts
.mips16
)
15184 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15185 ignore_rest_of_line ();
15189 /* .cpload should be in a .set noreorder section. */
15190 if (mips_opts
.noreorder
== 0)
15191 as_warn (_(".cpload not in noreorder section"));
15193 reg
= tc_get_register (0);
15195 /* If we need to produce a 64-bit address, we are better off using
15196 the default instruction sequence. */
15197 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15199 ex
.X_op
= O_symbol
;
15200 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15202 ex
.X_op_symbol
= NULL
;
15203 ex
.X_add_number
= 0;
15205 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15206 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15208 mips_mark_labels ();
15209 mips_assembling_insn
= TRUE
;
15212 macro_build_lui (&ex
, mips_gp_register
);
15213 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15214 mips_gp_register
, BFD_RELOC_LO16
);
15216 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15217 mips_gp_register
, reg
);
15220 mips_assembling_insn
= FALSE
;
15221 demand_empty_rest_of_line ();
15224 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15225 .cpsetup $reg1, offset|$reg2, label
15227 If offset is given, this results in:
15228 sd $gp, offset($sp)
15229 lui $gp, %hi(%neg(%gp_rel(label)))
15230 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15231 daddu $gp, $gp, $reg1
15233 If $reg2 is given, this results in:
15234 daddu $reg2, $gp, $0
15235 lui $gp, %hi(%neg(%gp_rel(label)))
15236 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15237 daddu $gp, $gp, $reg1
15238 $reg1 is normally $25 == $t9.
15240 The -mno-shared option replaces the last three instructions with
15242 addiu $gp,$gp,%lo(_gp) */
15245 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15247 expressionS ex_off
;
15248 expressionS ex_sym
;
15251 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15252 We also need NewABI support. */
15253 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15259 if (mips_opts
.mips16
)
15261 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15262 ignore_rest_of_line ();
15266 reg1
= tc_get_register (0);
15267 SKIP_WHITESPACE ();
15268 if (*input_line_pointer
!= ',')
15270 as_bad (_("missing argument separator ',' for .cpsetup"));
15274 ++input_line_pointer
;
15275 SKIP_WHITESPACE ();
15276 if (*input_line_pointer
== '$')
15278 mips_cpreturn_register
= tc_get_register (0);
15279 mips_cpreturn_offset
= -1;
15283 mips_cpreturn_offset
= get_absolute_expression ();
15284 mips_cpreturn_register
= -1;
15286 SKIP_WHITESPACE ();
15287 if (*input_line_pointer
!= ',')
15289 as_bad (_("missing argument separator ',' for .cpsetup"));
15293 ++input_line_pointer
;
15294 SKIP_WHITESPACE ();
15295 expression (&ex_sym
);
15297 mips_mark_labels ();
15298 mips_assembling_insn
= TRUE
;
15301 if (mips_cpreturn_register
== -1)
15303 ex_off
.X_op
= O_constant
;
15304 ex_off
.X_add_symbol
= NULL
;
15305 ex_off
.X_op_symbol
= NULL
;
15306 ex_off
.X_add_number
= mips_cpreturn_offset
;
15308 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15309 BFD_RELOC_LO16
, SP
);
15312 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15313 mips_gp_register
, 0);
15315 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15317 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15318 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15321 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15322 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15323 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15325 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15326 mips_gp_register
, reg1
);
15332 ex
.X_op
= O_symbol
;
15333 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15334 ex
.X_op_symbol
= NULL
;
15335 ex
.X_add_number
= 0;
15337 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15338 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15340 macro_build_lui (&ex
, mips_gp_register
);
15341 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15342 mips_gp_register
, BFD_RELOC_LO16
);
15347 mips_assembling_insn
= FALSE
;
15348 demand_empty_rest_of_line ();
15352 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15354 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15355 .cplocal is ignored. */
15356 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15362 if (mips_opts
.mips16
)
15364 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15365 ignore_rest_of_line ();
15369 mips_gp_register
= tc_get_register (0);
15370 demand_empty_rest_of_line ();
15373 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15374 offset from $sp. The offset is remembered, and after making a PIC
15375 call $gp is restored from that location. */
15378 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15382 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15383 .cprestore is ignored. */
15384 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15390 if (mips_opts
.mips16
)
15392 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15393 ignore_rest_of_line ();
15397 mips_cprestore_offset
= get_absolute_expression ();
15398 mips_cprestore_valid
= 1;
15400 ex
.X_op
= O_constant
;
15401 ex
.X_add_symbol
= NULL
;
15402 ex
.X_op_symbol
= NULL
;
15403 ex
.X_add_number
= mips_cprestore_offset
;
15405 mips_mark_labels ();
15406 mips_assembling_insn
= TRUE
;
15409 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15410 SP
, HAVE_64BIT_ADDRESSES
);
15413 mips_assembling_insn
= FALSE
;
15414 demand_empty_rest_of_line ();
15417 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15418 was given in the preceding .cpsetup, it results in:
15419 ld $gp, offset($sp)
15421 If a register $reg2 was given there, it results in:
15422 daddu $gp, $reg2, $0 */
15425 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15429 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15430 We also need NewABI support. */
15431 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15437 if (mips_opts
.mips16
)
15439 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15440 ignore_rest_of_line ();
15444 mips_mark_labels ();
15445 mips_assembling_insn
= TRUE
;
15448 if (mips_cpreturn_register
== -1)
15450 ex
.X_op
= O_constant
;
15451 ex
.X_add_symbol
= NULL
;
15452 ex
.X_op_symbol
= NULL
;
15453 ex
.X_add_number
= mips_cpreturn_offset
;
15455 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15458 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15459 mips_cpreturn_register
, 0);
15462 mips_assembling_insn
= FALSE
;
15463 demand_empty_rest_of_line ();
15466 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15467 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15468 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15469 debug information or MIPS16 TLS. */
15472 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15473 bfd_reloc_code_real_type rtype
)
15480 if (ex
.X_op
!= O_symbol
)
15482 as_bad (_("unsupported use of %s"), dirstr
);
15483 ignore_rest_of_line ();
15486 p
= frag_more (bytes
);
15487 md_number_to_chars (p
, 0, bytes
);
15488 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15489 demand_empty_rest_of_line ();
15490 mips_clear_insn_labels ();
15493 /* Handle .dtprelword. */
15496 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15498 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15501 /* Handle .dtpreldword. */
15504 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15506 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15509 /* Handle .tprelword. */
15512 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15514 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15517 /* Handle .tpreldword. */
15520 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15522 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15525 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15526 code. It sets the offset to use in gp_rel relocations. */
15529 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15531 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15532 We also need NewABI support. */
15533 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15539 mips_gprel_offset
= get_absolute_expression ();
15541 demand_empty_rest_of_line ();
15544 /* Handle the .gpword pseudo-op. This is used when generating PIC
15545 code. It generates a 32 bit GP relative reloc. */
15548 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15550 segment_info_type
*si
;
15551 struct insn_label_list
*l
;
15555 /* When not generating PIC code, this is treated as .word. */
15556 if (mips_pic
!= SVR4_PIC
)
15562 si
= seg_info (now_seg
);
15563 l
= si
->label_list
;
15564 mips_emit_delays ();
15566 mips_align (2, 0, l
);
15569 mips_clear_insn_labels ();
15571 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15573 as_bad (_("unsupported use of .gpword"));
15574 ignore_rest_of_line ();
15578 md_number_to_chars (p
, 0, 4);
15579 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15580 BFD_RELOC_GPREL32
);
15582 demand_empty_rest_of_line ();
15586 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15588 segment_info_type
*si
;
15589 struct insn_label_list
*l
;
15593 /* When not generating PIC code, this is treated as .dword. */
15594 if (mips_pic
!= SVR4_PIC
)
15600 si
= seg_info (now_seg
);
15601 l
= si
->label_list
;
15602 mips_emit_delays ();
15604 mips_align (3, 0, l
);
15607 mips_clear_insn_labels ();
15609 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15611 as_bad (_("unsupported use of .gpdword"));
15612 ignore_rest_of_line ();
15616 md_number_to_chars (p
, 0, 8);
15617 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15618 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15620 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15621 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15622 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15624 demand_empty_rest_of_line ();
15627 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15628 tables. It generates a R_MIPS_EH reloc. */
15631 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15636 mips_emit_delays ();
15639 mips_clear_insn_labels ();
15641 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15643 as_bad (_("unsupported use of .ehword"));
15644 ignore_rest_of_line ();
15648 md_number_to_chars (p
, 0, 4);
15649 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15650 BFD_RELOC_MIPS_EH
);
15652 demand_empty_rest_of_line ();
15655 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15656 tables in SVR4 PIC code. */
15659 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15663 /* This is ignored when not generating SVR4 PIC code. */
15664 if (mips_pic
!= SVR4_PIC
)
15670 mips_mark_labels ();
15671 mips_assembling_insn
= TRUE
;
15673 /* Add $gp to the register named as an argument. */
15675 reg
= tc_get_register (0);
15676 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15679 mips_assembling_insn
= FALSE
;
15680 demand_empty_rest_of_line ();
15683 /* Handle the .insn pseudo-op. This marks instruction labels in
15684 mips16/micromips mode. This permits the linker to handle them specially,
15685 such as generating jalx instructions when needed. We also make
15686 them odd for the duration of the assembly, in order to generate the
15687 right sort of code. We will make them even in the adjust_symtab
15688 routine, while leaving them marked. This is convenient for the
15689 debugger and the disassembler. The linker knows to make them odd
15693 s_insn (int ignore ATTRIBUTE_UNUSED
)
15695 mips_mark_labels ();
15697 demand_empty_rest_of_line ();
15700 /* Handle the .nan pseudo-op. */
15703 s_nan (int ignore ATTRIBUTE_UNUSED
)
15705 static const char str_legacy
[] = "legacy";
15706 static const char str_2008
[] = "2008";
15709 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15711 if (i
== sizeof (str_2008
) - 1
15712 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15713 mips_flag_nan2008
= TRUE
;
15714 else if (i
== sizeof (str_legacy
) - 1
15715 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15716 mips_flag_nan2008
= FALSE
;
15718 as_bad (_("bad .nan directive"));
15720 input_line_pointer
+= i
;
15721 demand_empty_rest_of_line ();
15724 /* Handle a .stab[snd] directive. Ideally these directives would be
15725 implemented in a transparent way, so that removing them would not
15726 have any effect on the generated instructions. However, s_stab
15727 internally changes the section, so in practice we need to decide
15728 now whether the preceding label marks compressed code. We do not
15729 support changing the compression mode of a label after a .stab*
15730 directive, such as in:
15736 so the current mode wins. */
15739 s_mips_stab (int type
)
15741 mips_mark_labels ();
15745 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15748 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15755 name
= input_line_pointer
;
15756 c
= get_symbol_end ();
15757 symbolP
= symbol_find_or_make (name
);
15758 S_SET_WEAK (symbolP
);
15759 *input_line_pointer
= c
;
15761 SKIP_WHITESPACE ();
15763 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15765 if (S_IS_DEFINED (symbolP
))
15767 as_bad (_("ignoring attempt to redefine symbol %s"),
15768 S_GET_NAME (symbolP
));
15769 ignore_rest_of_line ();
15773 if (*input_line_pointer
== ',')
15775 ++input_line_pointer
;
15776 SKIP_WHITESPACE ();
15780 if (exp
.X_op
!= O_symbol
)
15782 as_bad (_("bad .weakext directive"));
15783 ignore_rest_of_line ();
15786 symbol_set_value_expression (symbolP
, &exp
);
15789 demand_empty_rest_of_line ();
15792 /* Parse a register string into a number. Called from the ECOFF code
15793 to parse .frame. The argument is non-zero if this is the frame
15794 register, so that we can record it in mips_frame_reg. */
15797 tc_get_register (int frame
)
15801 SKIP_WHITESPACE ();
15802 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15806 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15807 mips_frame_reg_valid
= 1;
15808 mips_cprestore_valid
= 0;
15814 md_section_align (asection
*seg
, valueT addr
)
15816 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15818 /* We don't need to align ELF sections to the full alignment.
15819 However, Irix 5 may prefer that we align them at least to a 16
15820 byte boundary. We don't bother to align the sections if we
15821 are targeted for an embedded system. */
15822 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15827 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15830 /* Utility routine, called from above as well. If called while the
15831 input file is still being read, it's only an approximation. (For
15832 example, a symbol may later become defined which appeared to be
15833 undefined earlier.) */
15836 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15841 if (g_switch_value
> 0)
15843 const char *symname
;
15846 /* Find out whether this symbol can be referenced off the $gp
15847 register. It can be if it is smaller than the -G size or if
15848 it is in the .sdata or .sbss section. Certain symbols can
15849 not be referenced off the $gp, although it appears as though
15851 symname
= S_GET_NAME (sym
);
15852 if (symname
!= (const char *) NULL
15853 && (strcmp (symname
, "eprol") == 0
15854 || strcmp (symname
, "etext") == 0
15855 || strcmp (symname
, "_gp") == 0
15856 || strcmp (symname
, "edata") == 0
15857 || strcmp (symname
, "_fbss") == 0
15858 || strcmp (symname
, "_fdata") == 0
15859 || strcmp (symname
, "_ftext") == 0
15860 || strcmp (symname
, "end") == 0
15861 || strcmp (symname
, "_gp_disp") == 0))
15863 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15865 #ifndef NO_ECOFF_DEBUGGING
15866 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15867 && (symbol_get_obj (sym
)->ecoff_extern_size
15868 <= g_switch_value
))
15870 /* We must defer this decision until after the whole
15871 file has been read, since there might be a .extern
15872 after the first use of this symbol. */
15873 || (before_relaxing
15874 #ifndef NO_ECOFF_DEBUGGING
15875 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15877 && S_GET_VALUE (sym
) == 0)
15878 || (S_GET_VALUE (sym
) != 0
15879 && S_GET_VALUE (sym
) <= g_switch_value
)))
15883 const char *segname
;
15885 segname
= segment_name (S_GET_SEGMENT (sym
));
15886 gas_assert (strcmp (segname
, ".lit8") != 0
15887 && strcmp (segname
, ".lit4") != 0);
15888 change
= (strcmp (segname
, ".sdata") != 0
15889 && strcmp (segname
, ".sbss") != 0
15890 && strncmp (segname
, ".sdata.", 7) != 0
15891 && strncmp (segname
, ".sbss.", 6) != 0
15892 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
15893 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
15898 /* We are not optimizing for the $gp register. */
15903 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15906 pic_need_relax (symbolS
*sym
, asection
*segtype
)
15910 /* Handle the case of a symbol equated to another symbol. */
15911 while (symbol_equated_reloc_p (sym
))
15915 /* It's possible to get a loop here in a badly written program. */
15916 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
15922 if (symbol_section_p (sym
))
15925 symsec
= S_GET_SEGMENT (sym
);
15927 /* This must duplicate the test in adjust_reloc_syms. */
15928 return (!bfd_is_und_section (symsec
)
15929 && !bfd_is_abs_section (symsec
)
15930 && !bfd_is_com_section (symsec
)
15931 && !s_is_linkonce (sym
, segtype
)
15932 /* A global or weak symbol is treated as external. */
15933 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
15937 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15938 extended opcode. SEC is the section the frag is in. */
15941 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
15944 const struct mips_int_operand
*operand
;
15949 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
15951 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
15954 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
15955 operand
= mips16_immed_operand (type
, FALSE
);
15957 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
15958 val
= S_GET_VALUE (fragp
->fr_symbol
);
15959 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
15961 if (operand
->root
.type
== OP_PCREL
)
15963 const struct mips_pcrel_operand
*pcrel_op
;
15967 /* We won't have the section when we are called from
15968 mips_relax_frag. However, we will always have been called
15969 from md_estimate_size_before_relax first. If this is a
15970 branch to a different section, we mark it as such. If SEC is
15971 NULL, and the frag is not marked, then it must be a branch to
15972 the same section. */
15973 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
15976 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
15981 /* Must have been called from md_estimate_size_before_relax. */
15984 fragp
->fr_subtype
=
15985 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
15987 /* FIXME: We should support this, and let the linker
15988 catch branches and loads that are out of range. */
15989 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
15990 _("unsupported PC relative reference to different section"));
15994 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
15995 /* Assume non-extended on the first relaxation pass.
15996 The address we have calculated will be bogus if this is
15997 a forward branch to another frag, as the forward frag
15998 will have fr_address == 0. */
16002 /* In this case, we know for sure that the symbol fragment is in
16003 the same section. If the relax_marker of the symbol fragment
16004 differs from the relax_marker of this fragment, we have not
16005 yet adjusted the symbol fragment fr_address. We want to add
16006 in STRETCH in order to get a better estimate of the address.
16007 This particularly matters because of the shift bits. */
16009 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16013 /* Adjust stretch for any alignment frag. Note that if have
16014 been expanding the earlier code, the symbol may be
16015 defined in what appears to be an earlier frag. FIXME:
16016 This doesn't handle the fr_subtype field, which specifies
16017 a maximum number of bytes to skip when doing an
16019 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16021 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16024 stretch
= - ((- stretch
)
16025 & ~ ((1 << (int) f
->fr_offset
) - 1));
16027 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16036 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16038 /* The base address rules are complicated. The base address of
16039 a branch is the following instruction. The base address of a
16040 PC relative load or add is the instruction itself, but if it
16041 is in a delay slot (in which case it can not be extended) use
16042 the address of the instruction whose delay slot it is in. */
16043 if (pcrel_op
->include_isa_bit
)
16047 /* If we are currently assuming that this frag should be
16048 extended, then, the current address is two bytes
16050 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16053 /* Ignore the low bit in the target, since it will be set
16054 for a text label. */
16057 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16059 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16062 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16064 /* If any of the shifted bits are set, we must use an extended
16065 opcode. If the address depends on the size of this
16066 instruction, this can lead to a loop, so we arrange to always
16067 use an extended opcode. We only check this when we are in
16068 the main relaxation loop, when SEC is NULL. */
16069 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16071 fragp
->fr_subtype
=
16072 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16076 /* If we are about to mark a frag as extended because the value
16077 is precisely the next value above maxtiny, then there is a
16078 chance of an infinite loop as in the following code:
16083 In this case when the la is extended, foo is 0x3fc bytes
16084 away, so the la can be shrunk, but then foo is 0x400 away, so
16085 the la must be extended. To avoid this loop, we mark the
16086 frag as extended if it was small, and is about to become
16087 extended with the next value above maxtiny. */
16088 maxtiny
= mips_int_operand_max (operand
);
16089 if (val
== maxtiny
+ (1 << operand
->shift
)
16090 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16093 fragp
->fr_subtype
=
16094 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16098 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16099 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16101 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16104 /* Compute the length of a branch sequence, and adjust the
16105 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16106 worst-case length is computed, with UPDATE being used to indicate
16107 whether an unconditional (-1), branch-likely (+1) or regular (0)
16108 branch is to be computed. */
16110 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16112 bfd_boolean toofar
;
16116 && S_IS_DEFINED (fragp
->fr_symbol
)
16117 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16122 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16124 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16128 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16131 /* If the symbol is not defined or it's in a different segment,
16132 assume the user knows what's going on and emit a short
16138 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16140 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16141 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16142 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16143 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16149 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16152 if (mips_pic
!= NO_PIC
)
16154 /* Additional space for PIC loading of target address. */
16156 if (mips_opts
.isa
== ISA_MIPS1
)
16157 /* Additional space for $at-stabilizing nop. */
16161 /* If branch is conditional. */
16162 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16169 /* Compute the length of a branch sequence, and adjust the
16170 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16171 worst-case length is computed, with UPDATE being used to indicate
16172 whether an unconditional (-1), or regular (0) branch is to be
16176 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16178 bfd_boolean toofar
;
16182 && S_IS_DEFINED (fragp
->fr_symbol
)
16183 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16188 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16189 /* Ignore the low bit in the target, since it will be set
16190 for a text label. */
16191 if ((val
& 1) != 0)
16194 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16198 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16201 /* If the symbol is not defined or it's in a different segment,
16202 assume the user knows what's going on and emit a short
16208 if (fragp
&& update
16209 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16210 fragp
->fr_subtype
= (toofar
16211 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16212 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16217 bfd_boolean compact_known
= fragp
!= NULL
;
16218 bfd_boolean compact
= FALSE
;
16219 bfd_boolean uncond
;
16222 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16224 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16226 uncond
= update
< 0;
16228 /* If label is out of range, we turn branch <br>:
16230 <br> label # 4 bytes
16236 nop # 2 bytes if compact && !PIC
16239 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16242 /* If assembling PIC code, we further turn:
16248 lw/ld at, %got(label)(gp) # 4 bytes
16249 d/addiu at, %lo(label) # 4 bytes
16252 if (mips_pic
!= NO_PIC
)
16255 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16257 <brneg> 0f # 4 bytes
16258 nop # 2 bytes if !compact
16261 length
+= (compact_known
&& compact
) ? 4 : 6;
16267 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16268 bit accordingly. */
16271 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16273 bfd_boolean toofar
;
16276 && S_IS_DEFINED (fragp
->fr_symbol
)
16277 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16283 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16284 /* Ignore the low bit in the target, since it will be set
16285 for a text label. */
16286 if ((val
& 1) != 0)
16289 /* Assume this is a 2-byte branch. */
16290 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16292 /* We try to avoid the infinite loop by not adding 2 more bytes for
16297 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16299 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16300 else if (type
== 'E')
16301 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16306 /* If the symbol is not defined or it's in a different segment,
16307 we emit a normal 32-bit branch. */
16310 if (fragp
&& update
16311 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16313 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16314 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16322 /* Estimate the size of a frag before relaxing. Unless this is the
16323 mips16, we are not really relaxing here, and the final size is
16324 encoded in the subtype information. For the mips16, we have to
16325 decide whether we are using an extended opcode or not. */
16328 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16332 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16335 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16337 return fragp
->fr_var
;
16340 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16341 /* We don't want to modify the EXTENDED bit here; it might get us
16342 into infinite loops. We change it only in mips_relax_frag(). */
16343 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16345 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16349 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16350 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16351 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16352 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16353 fragp
->fr_var
= length
;
16358 if (mips_pic
== NO_PIC
)
16359 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16360 else if (mips_pic
== SVR4_PIC
)
16361 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16362 else if (mips_pic
== VXWORKS_PIC
)
16363 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16370 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16371 return -RELAX_FIRST (fragp
->fr_subtype
);
16374 return -RELAX_SECOND (fragp
->fr_subtype
);
16377 /* This is called to see whether a reloc against a defined symbol
16378 should be converted into a reloc against a section. */
16381 mips_fix_adjustable (fixS
*fixp
)
16383 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16384 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16387 if (fixp
->fx_addsy
== NULL
)
16390 /* If symbol SYM is in a mergeable section, relocations of the form
16391 SYM + 0 can usually be made section-relative. The mergeable data
16392 is then identified by the section offset rather than by the symbol.
16394 However, if we're generating REL LO16 relocations, the offset is split
16395 between the LO16 and parterning high part relocation. The linker will
16396 need to recalculate the complete offset in order to correctly identify
16399 The linker has traditionally not looked for the parterning high part
16400 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16401 placed anywhere. Rather than break backwards compatibility by changing
16402 this, it seems better not to force the issue, and instead keep the
16403 original symbol. This will work with either linker behavior. */
16404 if ((lo16_reloc_p (fixp
->fx_r_type
)
16405 || reloc_needs_lo_p (fixp
->fx_r_type
))
16406 && HAVE_IN_PLACE_ADDENDS
16407 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16410 /* There is no place to store an in-place offset for JALR relocations.
16411 Likewise an in-range offset of limited PC-relative relocations may
16412 overflow the in-place relocatable field if recalculated against the
16413 start address of the symbol's containing section. */
16414 if (HAVE_IN_PLACE_ADDENDS
16415 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16416 || jalr_reloc_p (fixp
->fx_r_type
)))
16419 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16420 to a floating-point stub. The same is true for non-R_MIPS16_26
16421 relocations against MIPS16 functions; in this case, the stub becomes
16422 the function's canonical address.
16424 Floating-point stubs are stored in unique .mips16.call.* or
16425 .mips16.fn.* sections. If a stub T for function F is in section S,
16426 the first relocation in section S must be against F; this is how the
16427 linker determines the target function. All relocations that might
16428 resolve to T must also be against F. We therefore have the following
16429 restrictions, which are given in an intentionally-redundant way:
16431 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16434 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16435 if that stub might be used.
16437 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16440 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16441 that stub might be used.
16443 There is a further restriction:
16445 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16446 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16447 targets with in-place addends; the relocation field cannot
16448 encode the low bit.
16450 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16451 against a MIPS16 symbol. We deal with (5) by by not reducing any
16452 such relocations on REL targets.
16454 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16455 relocation against some symbol R, no relocation against R may be
16456 reduced. (Note that this deals with (2) as well as (1) because
16457 relocations against global symbols will never be reduced on ELF
16458 targets.) This approach is a little simpler than trying to detect
16459 stub sections, and gives the "all or nothing" per-symbol consistency
16460 that we have for MIPS16 symbols. */
16461 if (fixp
->fx_subsy
== NULL
16462 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16463 || *symbol_get_tc (fixp
->fx_addsy
)
16464 || (HAVE_IN_PLACE_ADDENDS
16465 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16466 && jmp_reloc_p (fixp
->fx_r_type
))))
16472 /* Translate internal representation of relocation info to BFD target
16476 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16478 static arelent
*retval
[4];
16480 bfd_reloc_code_real_type code
;
16482 memset (retval
, 0, sizeof(retval
));
16483 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16484 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16485 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16486 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16488 if (fixp
->fx_pcrel
)
16490 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16491 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16492 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16493 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16494 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16496 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16497 Relocations want only the symbol offset. */
16498 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16501 reloc
->addend
= fixp
->fx_addnumber
;
16503 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16504 entry to be used in the relocation's section offset. */
16505 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16507 reloc
->address
= reloc
->addend
;
16511 code
= fixp
->fx_r_type
;
16513 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16514 if (reloc
->howto
== NULL
)
16516 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16517 _("cannot represent %s relocation in this object file"
16519 bfd_get_reloc_code_name (code
));
16526 /* Relax a machine dependent frag. This returns the amount by which
16527 the current size of the frag should change. */
16530 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16532 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16534 offsetT old_var
= fragp
->fr_var
;
16536 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16538 return fragp
->fr_var
- old_var
;
16541 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16543 offsetT old_var
= fragp
->fr_var
;
16544 offsetT new_var
= 4;
16546 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16547 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16548 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16549 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16550 fragp
->fr_var
= new_var
;
16552 return new_var
- old_var
;
16555 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16558 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16560 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16562 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16567 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16569 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16576 /* Convert a machine dependent frag. */
16579 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16581 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16584 unsigned long insn
;
16588 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16589 insn
= read_insn (buf
);
16591 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16593 /* We generate a fixup instead of applying it right now
16594 because, if there are linker relaxations, we're going to
16595 need the relocations. */
16596 exp
.X_op
= O_symbol
;
16597 exp
.X_add_symbol
= fragp
->fr_symbol
;
16598 exp
.X_add_number
= fragp
->fr_offset
;
16600 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16601 BFD_RELOC_16_PCREL_S2
);
16602 fixp
->fx_file
= fragp
->fr_file
;
16603 fixp
->fx_line
= fragp
->fr_line
;
16605 buf
= write_insn (buf
, insn
);
16611 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16612 _("relaxed out-of-range branch into a jump"));
16614 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16617 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16619 /* Reverse the branch. */
16620 switch ((insn
>> 28) & 0xf)
16623 if ((insn
& 0xff000000) == 0x47000000
16624 || (insn
& 0xff600000) == 0x45600000)
16626 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
16627 reversed by tweaking bit 23. */
16628 insn
^= 0x00800000;
16632 /* bc[0-3][tf]l? instructions can have the condition
16633 reversed by tweaking a single TF bit, and their
16634 opcodes all have 0x4???????. */
16635 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16636 insn
^= 0x00010000;
16641 /* bltz 0x04000000 bgez 0x04010000
16642 bltzal 0x04100000 bgezal 0x04110000 */
16643 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16644 insn
^= 0x00010000;
16648 /* beq 0x10000000 bne 0x14000000
16649 blez 0x18000000 bgtz 0x1c000000 */
16650 insn
^= 0x04000000;
16658 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16660 /* Clear the and-link bit. */
16661 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16663 /* bltzal 0x04100000 bgezal 0x04110000
16664 bltzall 0x04120000 bgezall 0x04130000 */
16665 insn
&= ~0x00100000;
16668 /* Branch over the branch (if the branch was likely) or the
16669 full jump (not likely case). Compute the offset from the
16670 current instruction to branch to. */
16671 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16675 /* How many bytes in instructions we've already emitted? */
16676 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16677 /* How many bytes in instructions from here to the end? */
16678 i
= fragp
->fr_var
- i
;
16680 /* Convert to instruction count. */
16682 /* Branch counts from the next instruction. */
16685 /* Branch over the jump. */
16686 buf
= write_insn (buf
, insn
);
16689 buf
= write_insn (buf
, 0);
16691 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16693 /* beql $0, $0, 2f */
16695 /* Compute the PC offset from the current instruction to
16696 the end of the variable frag. */
16697 /* How many bytes in instructions we've already emitted? */
16698 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16699 /* How many bytes in instructions from here to the end? */
16700 i
= fragp
->fr_var
- i
;
16701 /* Convert to instruction count. */
16703 /* Don't decrement i, because we want to branch over the
16707 buf
= write_insn (buf
, insn
);
16708 buf
= write_insn (buf
, 0);
16712 if (mips_pic
== NO_PIC
)
16715 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16716 ? 0x0c000000 : 0x08000000);
16717 exp
.X_op
= O_symbol
;
16718 exp
.X_add_symbol
= fragp
->fr_symbol
;
16719 exp
.X_add_number
= fragp
->fr_offset
;
16721 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16722 FALSE
, BFD_RELOC_MIPS_JMP
);
16723 fixp
->fx_file
= fragp
->fr_file
;
16724 fixp
->fx_line
= fragp
->fr_line
;
16726 buf
= write_insn (buf
, insn
);
16730 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16732 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16733 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16734 insn
|= at
<< OP_SH_RT
;
16735 exp
.X_op
= O_symbol
;
16736 exp
.X_add_symbol
= fragp
->fr_symbol
;
16737 exp
.X_add_number
= fragp
->fr_offset
;
16739 if (fragp
->fr_offset
)
16741 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16742 exp
.X_add_number
= 0;
16745 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16746 FALSE
, BFD_RELOC_MIPS_GOT16
);
16747 fixp
->fx_file
= fragp
->fr_file
;
16748 fixp
->fx_line
= fragp
->fr_line
;
16750 buf
= write_insn (buf
, insn
);
16752 if (mips_opts
.isa
== ISA_MIPS1
)
16754 buf
= write_insn (buf
, 0);
16756 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16757 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16758 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16760 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16761 FALSE
, BFD_RELOC_LO16
);
16762 fixp
->fx_file
= fragp
->fr_file
;
16763 fixp
->fx_line
= fragp
->fr_line
;
16765 buf
= write_insn (buf
, insn
);
16768 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16772 insn
|= at
<< OP_SH_RS
;
16774 buf
= write_insn (buf
, insn
);
16778 fragp
->fr_fix
+= fragp
->fr_var
;
16779 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16783 /* Relax microMIPS branches. */
16784 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16786 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16787 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16788 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16789 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16790 bfd_boolean short_ds
;
16791 unsigned long insn
;
16795 exp
.X_op
= O_symbol
;
16796 exp
.X_add_symbol
= fragp
->fr_symbol
;
16797 exp
.X_add_number
= fragp
->fr_offset
;
16799 fragp
->fr_fix
+= fragp
->fr_var
;
16801 /* Handle 16-bit branches that fit or are forced to fit. */
16802 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16804 /* We generate a fixup instead of applying it right now,
16805 because if there is linker relaxation, we're going to
16806 need the relocations. */
16808 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16809 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16810 else if (type
== 'E')
16811 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16812 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16816 fixp
->fx_file
= fragp
->fr_file
;
16817 fixp
->fx_line
= fragp
->fr_line
;
16819 /* These relocations can have an addend that won't fit in
16821 fixp
->fx_no_overflow
= 1;
16826 /* Handle 32-bit branches that fit or are forced to fit. */
16827 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16828 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16830 /* We generate a fixup instead of applying it right now,
16831 because if there is linker relaxation, we're going to
16832 need the relocations. */
16833 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16834 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16835 fixp
->fx_file
= fragp
->fr_file
;
16836 fixp
->fx_line
= fragp
->fr_line
;
16842 /* Relax 16-bit branches to 32-bit branches. */
16845 insn
= read_compressed_insn (buf
, 2);
16847 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16848 insn
= 0x94000000; /* beq */
16849 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16851 unsigned long regno
;
16853 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16854 regno
= micromips_to_32_reg_d_map
[regno
];
16855 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16856 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16861 /* Nothing else to do, just write it out. */
16862 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16863 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16865 buf
= write_compressed_insn (buf
, insn
, 4);
16866 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16871 insn
= read_compressed_insn (buf
, 4);
16873 /* Relax 32-bit branches to a sequence of instructions. */
16874 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16875 _("relaxed out-of-range branch into a jump"));
16877 /* Set the short-delay-slot bit. */
16878 short_ds
= al
&& (insn
& 0x02000000) != 0;
16880 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16884 /* Reverse the branch. */
16885 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16886 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16887 insn
^= 0x20000000;
16888 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16889 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16890 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16891 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
16892 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
16893 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
16894 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
16895 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
16896 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
16897 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
16898 insn
^= 0x00400000;
16899 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
16900 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
16901 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
16902 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
16903 insn
^= 0x00200000;
16904 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
16906 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
16908 insn
^= 0x00800000;
16914 /* Clear the and-link and short-delay-slot bits. */
16915 gas_assert ((insn
& 0xfda00000) == 0x40200000);
16917 /* bltzal 0x40200000 bgezal 0x40600000 */
16918 /* bltzals 0x42200000 bgezals 0x42600000 */
16919 insn
&= ~0x02200000;
16922 /* Make a label at the end for use with the branch. */
16923 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
16924 micromips_label_inc ();
16925 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
16928 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
16929 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16930 fixp
->fx_file
= fragp
->fr_file
;
16931 fixp
->fx_line
= fragp
->fr_line
;
16933 /* Branch over the jump. */
16934 buf
= write_compressed_insn (buf
, insn
, 4);
16937 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16940 if (mips_pic
== NO_PIC
)
16942 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
16944 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16945 insn
= al
? jal
: 0xd4000000;
16947 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16948 BFD_RELOC_MICROMIPS_JMP
);
16949 fixp
->fx_file
= fragp
->fr_file
;
16950 fixp
->fx_line
= fragp
->fr_line
;
16952 buf
= write_compressed_insn (buf
, insn
, 4);
16955 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16959 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
16960 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
16961 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
16963 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16964 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
16965 insn
|= at
<< MICROMIPSOP_SH_RT
;
16967 if (exp
.X_add_number
)
16969 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16970 exp
.X_add_number
= 0;
16973 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16974 BFD_RELOC_MICROMIPS_GOT16
);
16975 fixp
->fx_file
= fragp
->fr_file
;
16976 fixp
->fx_line
= fragp
->fr_line
;
16978 buf
= write_compressed_insn (buf
, insn
, 4);
16980 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16981 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
16982 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
16984 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16985 BFD_RELOC_MICROMIPS_LO16
);
16986 fixp
->fx_file
= fragp
->fr_file
;
16987 fixp
->fx_line
= fragp
->fr_line
;
16989 buf
= write_compressed_insn (buf
, insn
, 4);
16991 /* jr/jrc/jalr/jalrs $at */
16992 insn
= al
? jalr
: jr
;
16993 insn
|= at
<< MICROMIPSOP_SH_MJ
;
16995 buf
= write_compressed_insn (buf
, insn
, 2);
16998 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17002 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17005 const struct mips_int_operand
*operand
;
17008 unsigned int user_length
, length
;
17009 unsigned long insn
;
17012 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17013 operand
= mips16_immed_operand (type
, FALSE
);
17015 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17016 val
= resolve_symbol_value (fragp
->fr_symbol
);
17017 if (operand
->root
.type
== OP_PCREL
)
17019 const struct mips_pcrel_operand
*pcrel_op
;
17022 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17023 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17025 /* The rules for the base address of a PC relative reloc are
17026 complicated; see mips16_extended_frag. */
17027 if (pcrel_op
->include_isa_bit
)
17032 /* Ignore the low bit in the target, since it will be
17033 set for a text label. */
17036 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17038 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17041 addr
&= -(1 << pcrel_op
->align_log2
);
17044 /* Make sure the section winds up with the alignment we have
17046 if (operand
->shift
> 0)
17047 record_alignment (asec
, operand
->shift
);
17051 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17052 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17053 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17054 _("extended instruction in delay slot"));
17056 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17058 insn
= read_compressed_insn (buf
, 2);
17060 insn
|= MIPS16_EXTEND
;
17062 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17064 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17069 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17070 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17072 length
= (ext
? 4 : 2);
17073 gas_assert (mips16_opcode_length (insn
) == length
);
17074 write_compressed_insn (buf
, insn
, length
);
17075 fragp
->fr_fix
+= length
;
17079 relax_substateT subtype
= fragp
->fr_subtype
;
17080 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17081 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17085 first
= RELAX_FIRST (subtype
);
17086 second
= RELAX_SECOND (subtype
);
17087 fixp
= (fixS
*) fragp
->fr_opcode
;
17089 /* If the delay slot chosen does not match the size of the instruction,
17090 then emit a warning. */
17091 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17092 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17097 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17098 | RELAX_DELAY_SLOT_SIZE_FIRST
17099 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17100 msg
= macro_warning (s
);
17102 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17106 /* Possibly emit a warning if we've chosen the longer option. */
17107 if (use_second
== second_longer
)
17113 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17114 msg
= macro_warning (s
);
17116 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17120 /* Go through all the fixups for the first sequence. Disable them
17121 (by marking them as done) if we're going to use the second
17122 sequence instead. */
17124 && fixp
->fx_frag
== fragp
17125 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17127 if (subtype
& RELAX_USE_SECOND
)
17129 fixp
= fixp
->fx_next
;
17132 /* Go through the fixups for the second sequence. Disable them if
17133 we're going to use the first sequence, otherwise adjust their
17134 addresses to account for the relaxation. */
17135 while (fixp
&& fixp
->fx_frag
== fragp
)
17137 if (subtype
& RELAX_USE_SECOND
)
17138 fixp
->fx_where
-= first
;
17141 fixp
= fixp
->fx_next
;
17144 /* Now modify the frag contents. */
17145 if (subtype
& RELAX_USE_SECOND
)
17149 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17150 memmove (start
, start
+ first
, second
);
17151 fragp
->fr_fix
-= first
;
17154 fragp
->fr_fix
-= second
;
17158 /* This function is called after the relocs have been generated.
17159 We've been storing mips16 text labels as odd. Here we convert them
17160 back to even for the convenience of the debugger. */
17163 mips_frob_file_after_relocs (void)
17166 unsigned int count
, i
;
17168 syms
= bfd_get_outsymbols (stdoutput
);
17169 count
= bfd_get_symcount (stdoutput
);
17170 for (i
= 0; i
< count
; i
++, syms
++)
17171 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17172 && ((*syms
)->value
& 1) != 0)
17174 (*syms
)->value
&= ~1;
17175 /* If the symbol has an odd size, it was probably computed
17176 incorrectly, so adjust that as well. */
17177 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17178 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17182 /* This function is called whenever a label is defined, including fake
17183 labels instantiated off the dot special symbol. It is used when
17184 handling branch delays; if a branch has a label, we assume we cannot
17185 move it. This also bumps the value of the symbol by 1 in compressed
17189 mips_record_label (symbolS
*sym
)
17191 segment_info_type
*si
= seg_info (now_seg
);
17192 struct insn_label_list
*l
;
17194 if (free_insn_labels
== NULL
)
17195 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17198 l
= free_insn_labels
;
17199 free_insn_labels
= l
->next
;
17203 l
->next
= si
->label_list
;
17204 si
->label_list
= l
;
17207 /* This function is called as tc_frob_label() whenever a label is defined
17208 and adds a DWARF-2 record we only want for true labels. */
17211 mips_define_label (symbolS
*sym
)
17213 mips_record_label (sym
);
17214 dwarf2_emit_label (sym
);
17217 /* This function is called by tc_new_dot_label whenever a new dot symbol
17221 mips_add_dot_label (symbolS
*sym
)
17223 mips_record_label (sym
);
17224 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17225 mips_compressed_mark_label (sym
);
17228 /* Some special processing for a MIPS ELF file. */
17231 mips_elf_final_processing (void)
17233 /* Write out the register information. */
17234 if (mips_abi
!= N64_ABI
)
17238 s
.ri_gprmask
= mips_gprmask
;
17239 s
.ri_cprmask
[0] = mips_cprmask
[0];
17240 s
.ri_cprmask
[1] = mips_cprmask
[1];
17241 s
.ri_cprmask
[2] = mips_cprmask
[2];
17242 s
.ri_cprmask
[3] = mips_cprmask
[3];
17243 /* The gp_value field is set by the MIPS ELF backend. */
17245 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17246 ((Elf32_External_RegInfo
*)
17247 mips_regmask_frag
));
17251 Elf64_Internal_RegInfo s
;
17253 s
.ri_gprmask
= mips_gprmask
;
17255 s
.ri_cprmask
[0] = mips_cprmask
[0];
17256 s
.ri_cprmask
[1] = mips_cprmask
[1];
17257 s
.ri_cprmask
[2] = mips_cprmask
[2];
17258 s
.ri_cprmask
[3] = mips_cprmask
[3];
17259 /* The gp_value field is set by the MIPS ELF backend. */
17261 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17262 ((Elf64_External_RegInfo
*)
17263 mips_regmask_frag
));
17266 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17267 sort of BFD interface for this. */
17268 if (mips_any_noreorder
)
17269 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17270 if (mips_pic
!= NO_PIC
)
17272 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17273 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17276 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17278 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17279 defined at present; this might need to change in future. */
17280 if (file_ase_mips16
)
17281 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17282 if (file_ase_micromips
)
17283 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17284 if (file_ase
& ASE_MDMX
)
17285 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17287 /* Set the MIPS ELF ABI flags. */
17288 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17289 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17290 else if (mips_abi
== O64_ABI
)
17291 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17292 else if (mips_abi
== EABI_ABI
)
17294 if (!file_mips_gp32
)
17295 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17297 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17299 else if (mips_abi
== N32_ABI
)
17300 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17302 /* Nothing to do for N64_ABI. */
17304 if (mips_32bitmode
)
17305 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17307 if (mips_flag_nan2008
)
17308 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17310 /* 32 bit code with 64 bit FP registers. */
17311 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17312 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
17315 typedef struct proc
{
17317 symbolS
*func_end_sym
;
17318 unsigned long reg_mask
;
17319 unsigned long reg_offset
;
17320 unsigned long fpreg_mask
;
17321 unsigned long fpreg_offset
;
17322 unsigned long frame_offset
;
17323 unsigned long frame_reg
;
17324 unsigned long pc_reg
;
17327 static procS cur_proc
;
17328 static procS
*cur_proc_ptr
;
17329 static int numprocs
;
17331 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17332 as "2", and a normal nop as "0". */
17334 #define NOP_OPCODE_MIPS 0
17335 #define NOP_OPCODE_MIPS16 1
17336 #define NOP_OPCODE_MICROMIPS 2
17339 mips_nop_opcode (void)
17341 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17342 return NOP_OPCODE_MICROMIPS
;
17343 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17344 return NOP_OPCODE_MIPS16
;
17346 return NOP_OPCODE_MIPS
;
17349 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17350 32-bit microMIPS NOPs here (if applicable). */
17353 mips_handle_align (fragS
*fragp
)
17357 int bytes
, size
, excess
;
17360 if (fragp
->fr_type
!= rs_align_code
)
17363 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17365 switch (nop_opcode
)
17367 case NOP_OPCODE_MICROMIPS
:
17368 opcode
= micromips_nop32_insn
.insn_opcode
;
17371 case NOP_OPCODE_MIPS16
:
17372 opcode
= mips16_nop_insn
.insn_opcode
;
17375 case NOP_OPCODE_MIPS
:
17377 opcode
= nop_insn
.insn_opcode
;
17382 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17383 excess
= bytes
% size
;
17385 /* Handle the leading part if we're not inserting a whole number of
17386 instructions, and make it the end of the fixed part of the frag.
17387 Try to fit in a short microMIPS NOP if applicable and possible,
17388 and use zeroes otherwise. */
17389 gas_assert (excess
< 4);
17390 fragp
->fr_fix
+= excess
;
17395 /* Fall through. */
17397 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17399 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17403 /* Fall through. */
17406 /* Fall through. */
17411 md_number_to_chars (p
, opcode
, size
);
17412 fragp
->fr_var
= size
;
17416 md_obj_begin (void)
17423 /* Check for premature end, nesting errors, etc. */
17425 as_warn (_("missing .end at end of assembly"));
17434 if (*input_line_pointer
== '-')
17436 ++input_line_pointer
;
17439 if (!ISDIGIT (*input_line_pointer
))
17440 as_bad (_("expected simple number"));
17441 if (input_line_pointer
[0] == '0')
17443 if (input_line_pointer
[1] == 'x')
17445 input_line_pointer
+= 2;
17446 while (ISXDIGIT (*input_line_pointer
))
17449 val
|= hex_value (*input_line_pointer
++);
17451 return negative
? -val
: val
;
17455 ++input_line_pointer
;
17456 while (ISDIGIT (*input_line_pointer
))
17459 val
|= *input_line_pointer
++ - '0';
17461 return negative
? -val
: val
;
17464 if (!ISDIGIT (*input_line_pointer
))
17466 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17467 *input_line_pointer
, *input_line_pointer
);
17468 as_warn (_("invalid number"));
17471 while (ISDIGIT (*input_line_pointer
))
17474 val
+= *input_line_pointer
++ - '0';
17476 return negative
? -val
: val
;
17479 /* The .file directive; just like the usual .file directive, but there
17480 is an initial number which is the ECOFF file index. In the non-ECOFF
17481 case .file implies DWARF-2. */
17484 s_mips_file (int x ATTRIBUTE_UNUSED
)
17486 static int first_file_directive
= 0;
17488 if (ECOFF_DEBUGGING
)
17497 filename
= dwarf2_directive_file (0);
17499 /* Versions of GCC up to 3.1 start files with a ".file"
17500 directive even for stabs output. Make sure that this
17501 ".file" is handled. Note that you need a version of GCC
17502 after 3.1 in order to support DWARF-2 on MIPS. */
17503 if (filename
!= NULL
&& ! first_file_directive
)
17505 (void) new_logical_line (filename
, -1);
17506 s_app_file_string (filename
, 0);
17508 first_file_directive
= 1;
17512 /* The .loc directive, implying DWARF-2. */
17515 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17517 if (!ECOFF_DEBUGGING
)
17518 dwarf2_directive_loc (0);
17521 /* The .end directive. */
17524 s_mips_end (int x ATTRIBUTE_UNUSED
)
17528 /* Following functions need their own .frame and .cprestore directives. */
17529 mips_frame_reg_valid
= 0;
17530 mips_cprestore_valid
= 0;
17532 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17535 demand_empty_rest_of_line ();
17540 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17541 as_warn (_(".end not in text section"));
17545 as_warn (_(".end directive without a preceding .ent directive"));
17546 demand_empty_rest_of_line ();
17552 gas_assert (S_GET_NAME (p
));
17553 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17554 as_warn (_(".end symbol does not match .ent symbol"));
17556 if (debug_type
== DEBUG_STABS
)
17557 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17561 as_warn (_(".end directive missing or unknown symbol"));
17563 /* Create an expression to calculate the size of the function. */
17564 if (p
&& cur_proc_ptr
)
17566 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17567 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17570 exp
->X_op
= O_subtract
;
17571 exp
->X_add_symbol
= symbol_temp_new_now ();
17572 exp
->X_op_symbol
= p
;
17573 exp
->X_add_number
= 0;
17575 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17578 /* Generate a .pdr section. */
17579 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17581 segT saved_seg
= now_seg
;
17582 subsegT saved_subseg
= now_subseg
;
17586 #ifdef md_flush_pending_output
17587 md_flush_pending_output ();
17590 gas_assert (pdr_seg
);
17591 subseg_set (pdr_seg
, 0);
17593 /* Write the symbol. */
17594 exp
.X_op
= O_symbol
;
17595 exp
.X_add_symbol
= p
;
17596 exp
.X_add_number
= 0;
17597 emit_expr (&exp
, 4);
17599 fragp
= frag_more (7 * 4);
17601 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17602 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17603 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17604 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17605 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17606 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17607 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17609 subseg_set (saved_seg
, saved_subseg
);
17612 cur_proc_ptr
= NULL
;
17615 /* The .aent and .ent directives. */
17618 s_mips_ent (int aent
)
17622 symbolP
= get_symbol ();
17623 if (*input_line_pointer
== ',')
17624 ++input_line_pointer
;
17625 SKIP_WHITESPACE ();
17626 if (ISDIGIT (*input_line_pointer
)
17627 || *input_line_pointer
== '-')
17630 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17631 as_warn (_(".ent or .aent not in text section"));
17633 if (!aent
&& cur_proc_ptr
)
17634 as_warn (_("missing .end"));
17638 /* This function needs its own .frame and .cprestore directives. */
17639 mips_frame_reg_valid
= 0;
17640 mips_cprestore_valid
= 0;
17642 cur_proc_ptr
= &cur_proc
;
17643 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17645 cur_proc_ptr
->func_sym
= symbolP
;
17649 if (debug_type
== DEBUG_STABS
)
17650 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17651 S_GET_NAME (symbolP
));
17654 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17656 demand_empty_rest_of_line ();
17659 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17660 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17661 s_mips_frame is used so that we can set the PDR information correctly.
17662 We can't use the ecoff routines because they make reference to the ecoff
17663 symbol table (in the mdebug section). */
17666 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17668 if (ECOFF_DEBUGGING
)
17674 if (cur_proc_ptr
== (procS
*) NULL
)
17676 as_warn (_(".frame outside of .ent"));
17677 demand_empty_rest_of_line ();
17681 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17683 SKIP_WHITESPACE ();
17684 if (*input_line_pointer
++ != ','
17685 || get_absolute_expression_and_terminator (&val
) != ',')
17687 as_warn (_("bad .frame directive"));
17688 --input_line_pointer
;
17689 demand_empty_rest_of_line ();
17693 cur_proc_ptr
->frame_offset
= val
;
17694 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17696 demand_empty_rest_of_line ();
17700 /* The .fmask and .mask directives. If the mdebug section is present
17701 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17702 embedded targets, s_mips_mask is used so that we can set the PDR
17703 information correctly. We can't use the ecoff routines because they
17704 make reference to the ecoff symbol table (in the mdebug section). */
17707 s_mips_mask (int reg_type
)
17709 if (ECOFF_DEBUGGING
)
17710 s_ignore (reg_type
);
17715 if (cur_proc_ptr
== (procS
*) NULL
)
17717 as_warn (_(".mask/.fmask outside of .ent"));
17718 demand_empty_rest_of_line ();
17722 if (get_absolute_expression_and_terminator (&mask
) != ',')
17724 as_warn (_("bad .mask/.fmask directive"));
17725 --input_line_pointer
;
17726 demand_empty_rest_of_line ();
17730 off
= get_absolute_expression ();
17732 if (reg_type
== 'F')
17734 cur_proc_ptr
->fpreg_mask
= mask
;
17735 cur_proc_ptr
->fpreg_offset
= off
;
17739 cur_proc_ptr
->reg_mask
= mask
;
17740 cur_proc_ptr
->reg_offset
= off
;
17743 demand_empty_rest_of_line ();
17747 /* A table describing all the processors gas knows about. Names are
17748 matched in the order listed.
17750 To ease comparison, please keep this table in the same order as
17751 gcc's mips_cpu_info_table[]. */
17752 static const struct mips_cpu_info mips_cpu_info_table
[] =
17754 /* Entries for generic ISAs */
17755 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17756 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17757 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17758 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17759 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17760 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17761 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17762 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17763 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17766 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17767 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17768 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17771 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17774 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17775 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17776 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17777 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17778 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17779 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17780 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17781 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17782 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17783 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17784 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17785 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17786 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17787 /* ST Microelectronics Loongson 2E and 2F cores */
17788 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17789 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17792 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17793 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17794 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17795 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17796 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17797 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17798 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17799 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17800 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17801 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17802 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17803 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17804 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17805 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17806 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17809 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17810 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17811 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17812 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17814 /* MIPS 32 Release 2 */
17815 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17816 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17817 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17818 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17819 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17820 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17821 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17822 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17823 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17824 ISA_MIPS32R2
, CPU_MIPS32R2
},
17825 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17826 ISA_MIPS32R2
, CPU_MIPS32R2
},
17827 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17828 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17829 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17830 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17831 /* Deprecated forms of the above. */
17832 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17833 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17834 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17835 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17836 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17837 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17838 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17839 /* Deprecated forms of the above. */
17840 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17841 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17842 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17843 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17844 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17845 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17846 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17847 /* Deprecated forms of the above. */
17848 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17849 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17850 /* 34Kn is a 34kc without DSP. */
17851 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17852 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17853 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17854 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17855 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17856 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17857 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17858 /* Deprecated forms of the above. */
17859 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17860 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17861 /* 1004K cores are multiprocessor versions of the 34K. */
17862 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17863 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17864 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17865 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17868 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17869 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17870 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17871 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17873 /* Broadcom SB-1 CPU core */
17874 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17875 /* Broadcom SB-1A CPU core */
17876 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17878 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
17880 /* MIPS 64 Release 2 */
17882 /* Cavium Networks Octeon CPU core */
17883 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17884 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17885 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
17888 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
17891 XLP is mostly like XLR, with the prominent exception that it is
17892 MIPS64R2 rather than MIPS64. */
17893 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
17896 { NULL
, 0, 0, 0, 0 }
17900 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17901 with a final "000" replaced by "k". Ignore case.
17903 Note: this function is shared between GCC and GAS. */
17906 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
17908 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
17909 given
++, canonical
++;
17911 return ((*given
== 0 && *canonical
== 0)
17912 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
17916 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17917 CPU name. We've traditionally allowed a lot of variation here.
17919 Note: this function is shared between GCC and GAS. */
17922 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
17924 /* First see if the name matches exactly, or with a final "000"
17925 turned into "k". */
17926 if (mips_strict_matching_cpu_name_p (canonical
, given
))
17929 /* If not, try comparing based on numerical designation alone.
17930 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17931 if (TOLOWER (*given
) == 'r')
17933 if (!ISDIGIT (*given
))
17936 /* Skip over some well-known prefixes in the canonical name,
17937 hoping to find a number there too. */
17938 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
17940 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
17942 else if (TOLOWER (canonical
[0]) == 'r')
17945 return mips_strict_matching_cpu_name_p (canonical
, given
);
17949 /* Parse an option that takes the name of a processor as its argument.
17950 OPTION is the name of the option and CPU_STRING is the argument.
17951 Return the corresponding processor enumeration if the CPU_STRING is
17952 recognized, otherwise report an error and return null.
17954 A similar function exists in GCC. */
17956 static const struct mips_cpu_info
*
17957 mips_parse_cpu (const char *option
, const char *cpu_string
)
17959 const struct mips_cpu_info
*p
;
17961 /* 'from-abi' selects the most compatible architecture for the given
17962 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17963 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17964 version. Look first at the -mgp options, if given, otherwise base
17965 the choice on MIPS_DEFAULT_64BIT.
17967 Treat NO_ABI like the EABIs. One reason to do this is that the
17968 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17969 architecture. This code picks MIPS I for 'mips' and MIPS III for
17970 'mips64', just as we did in the days before 'from-abi'. */
17971 if (strcasecmp (cpu_string
, "from-abi") == 0)
17973 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
17974 return mips_cpu_info_from_isa (ISA_MIPS1
);
17976 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
17977 return mips_cpu_info_from_isa (ISA_MIPS3
);
17979 if (file_mips_gp32
>= 0)
17980 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
17982 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17987 /* 'default' has traditionally been a no-op. Probably not very useful. */
17988 if (strcasecmp (cpu_string
, "default") == 0)
17991 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
17992 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
17995 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
17999 /* Return the canonical processor information for ISA (a member of the
18000 ISA_MIPS* enumeration). */
18002 static const struct mips_cpu_info
*
18003 mips_cpu_info_from_isa (int isa
)
18007 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18008 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18009 && isa
== mips_cpu_info_table
[i
].isa
)
18010 return (&mips_cpu_info_table
[i
]);
18015 static const struct mips_cpu_info
*
18016 mips_cpu_info_from_arch (int arch
)
18020 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18021 if (arch
== mips_cpu_info_table
[i
].cpu
)
18022 return (&mips_cpu_info_table
[i
]);
18028 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18032 fprintf (stream
, "%24s", "");
18037 fprintf (stream
, ", ");
18041 if (*col_p
+ strlen (string
) > 72)
18043 fprintf (stream
, "\n%24s", "");
18047 fprintf (stream
, "%s", string
);
18048 *col_p
+= strlen (string
);
18054 md_show_usage (FILE *stream
)
18059 fprintf (stream
, _("\
18061 -EB generate big endian output\n\
18062 -EL generate little endian output\n\
18063 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18064 -G NUM allow referencing objects up to NUM bytes\n\
18065 implicitly with the gp register [default 8]\n"));
18066 fprintf (stream
, _("\
18067 -mips1 generate MIPS ISA I instructions\n\
18068 -mips2 generate MIPS ISA II instructions\n\
18069 -mips3 generate MIPS ISA III instructions\n\
18070 -mips4 generate MIPS ISA IV instructions\n\
18071 -mips5 generate MIPS ISA V instructions\n\
18072 -mips32 generate MIPS32 ISA instructions\n\
18073 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18074 -mips64 generate MIPS64 ISA instructions\n\
18075 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18076 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18080 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18081 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18082 show (stream
, "from-abi", &column
, &first
);
18083 fputc ('\n', stream
);
18085 fprintf (stream
, _("\
18086 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18087 -no-mCPU don't generate code specific to CPU.\n\
18088 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18092 show (stream
, "3900", &column
, &first
);
18093 show (stream
, "4010", &column
, &first
);
18094 show (stream
, "4100", &column
, &first
);
18095 show (stream
, "4650", &column
, &first
);
18096 fputc ('\n', stream
);
18098 fprintf (stream
, _("\
18099 -mips16 generate mips16 instructions\n\
18100 -no-mips16 do not generate mips16 instructions\n"));
18101 fprintf (stream
, _("\
18102 -mmicromips generate microMIPS instructions\n\
18103 -mno-micromips do not generate microMIPS instructions\n"));
18104 fprintf (stream
, _("\
18105 -msmartmips generate smartmips instructions\n\
18106 -mno-smartmips do not generate smartmips instructions\n"));
18107 fprintf (stream
, _("\
18108 -mdsp generate DSP instructions\n\
18109 -mno-dsp do not generate DSP instructions\n"));
18110 fprintf (stream
, _("\
18111 -mdspr2 generate DSP R2 instructions\n\
18112 -mno-dspr2 do not generate DSP R2 instructions\n"));
18113 fprintf (stream
, _("\
18114 -mmt generate MT instructions\n\
18115 -mno-mt do not generate MT instructions\n"));
18116 fprintf (stream
, _("\
18117 -mmcu generate MCU instructions\n\
18118 -mno-mcu do not generate MCU instructions\n"));
18119 fprintf (stream
, _("\
18120 -mmsa generate MSA instructions\n\
18121 -mno-msa do not generate MSA instructions\n"));
18122 fprintf (stream
, _("\
18123 -mvirt generate Virtualization instructions\n\
18124 -mno-virt do not generate Virtualization instructions\n"));
18125 fprintf (stream
, _("\
18126 -minsn32 only generate 32-bit microMIPS instructions\n\
18127 -mno-insn32 generate all microMIPS instructions\n"));
18128 fprintf (stream
, _("\
18129 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18130 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18131 -mfix-vr4120 work around certain VR4120 errata\n\
18132 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18133 -mfix-24k insert a nop after ERET and DERET instructions\n\
18134 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18135 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18136 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18137 -msym32 assume all symbols have 32-bit values\n\
18138 -O0 remove unneeded NOPs, do not swap branches\n\
18139 -O remove unneeded NOPs and swap branches\n\
18140 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18141 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18142 fprintf (stream
, _("\
18143 -mhard-float allow floating-point instructions\n\
18144 -msoft-float do not allow floating-point instructions\n\
18145 -msingle-float only allow 32-bit floating-point operations\n\
18146 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18147 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18148 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18149 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18153 show (stream
, "legacy", &column
, &first
);
18154 show (stream
, "2008", &column
, &first
);
18156 fputc ('\n', stream
);
18158 fprintf (stream
, _("\
18159 -KPIC, -call_shared generate SVR4 position independent code\n\
18160 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18161 -mvxworks-pic generate VxWorks position independent code\n\
18162 -non_shared do not generate code that can operate with DSOs\n\
18163 -xgot assume a 32 bit GOT\n\
18164 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18165 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18166 position dependent (non shared) code\n\
18167 -mabi=ABI create ABI conformant object file for:\n"));
18171 show (stream
, "32", &column
, &first
);
18172 show (stream
, "o64", &column
, &first
);
18173 show (stream
, "n32", &column
, &first
);
18174 show (stream
, "64", &column
, &first
);
18175 show (stream
, "eabi", &column
, &first
);
18177 fputc ('\n', stream
);
18179 fprintf (stream
, _("\
18180 -32 create o32 ABI object file (default)\n\
18181 -n32 create n32 ABI object file\n\
18182 -64 create 64 ABI object file\n"));
18187 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18189 if (HAVE_64BIT_SYMBOLS
)
18190 return dwarf2_format_64bit_irix
;
18192 return dwarf2_format_32bit
;
18197 mips_dwarf2_addr_size (void)
18199 if (HAVE_64BIT_OBJECTS
)
18205 /* Standard calling conventions leave the CFA at SP on entry. */
18207 mips_cfi_frame_initial_instructions (void)
18209 cfi_add_CFA_def_cfa_register (SP
);
18213 tc_mips_regname_to_dw2regnum (char *regname
)
18215 unsigned int regnum
= -1;
18218 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))