1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
159 /* The ABI to use. */
170 /* MIPS ABI we are using for this output file. */
171 static enum mips_abi_level mips_abi
= NO_ABI
;
173 /* Whether or not we have code that can call pic code. */
174 int mips_abicalls
= FALSE
;
176 /* Whether or not we have code which can be put into a shared
178 static bfd_boolean mips_in_shared
= TRUE
;
180 /* This is the set of options which may be modified by the .set
181 pseudo-op. We use a struct so that .set push and .set pop are more
184 struct mips_set_options
186 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
187 if it has not been initialized. Changed by `.set mipsN', and the
188 -mipsN command line option, and the default CPU. */
190 /* Enabled Application Specific Extensions (ASEs). These are set to -1
191 if they have not been initialized. Changed by `.set <asename>', by
192 command line options, and based on the default architecture. */
195 /* Whether we are assembling for the mips16 processor. 0 if we are
196 not, 1 if we are, and -1 if the value has not been initialized.
197 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
198 -nomips16 command line options, and the default CPU. */
200 /* Non-zero if we should not reorder instructions. Changed by `.set
201 reorder' and `.set noreorder'. */
203 /* Non-zero if we should not permit the $at ($1) register to be used
204 in instructions. Changed by `.set at' and `.set noat'. */
206 /* Non-zero if we should warn when a macro instruction expands into
207 more than one machine instruction. Changed by `.set nomacro' and
209 int warn_about_macros
;
210 /* Non-zero if we should not move instructions. Changed by `.set
211 move', `.set volatile', `.set nomove', and `.set novolatile'. */
213 /* Non-zero if we should not optimize branches by moving the target
214 of the branch into the delay slot. Actually, we don't perform
215 this optimization anyhow. Changed by `.set bopt' and `.set
218 /* Non-zero if we should not autoextend mips16 instructions.
219 Changed by `.set autoextend' and `.set noautoextend'. */
221 /* Restrict general purpose registers and floating point registers
222 to 32 bit. This is initially determined when -mgp32 or -mfp32
223 is passed but can changed if the assembler code uses .set mipsN. */
226 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
227 command line option, and the default CPU. */
229 /* True if ".set sym32" is in effect. */
233 /* True if -mgp32 was passed. */
234 static int file_mips_gp32
= -1;
236 /* True if -mfp32 was passed. */
237 static int file_mips_fp32
= -1;
239 /* This is the struct we use to hold the current set of options. Note
240 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
241 -1 to indicate that they have not been initialized. */
243 static struct mips_set_options mips_opts
=
245 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
248 /* These variables are filled in with the masks of registers used.
249 The object format code reads them and puts them in the appropriate
251 unsigned long mips_gprmask
;
252 unsigned long mips_cprmask
[4];
254 /* MIPS ISA we are using for this output file. */
255 static int file_mips_isa
= ISA_UNKNOWN
;
257 /* True if -mips16 was passed or implied by arguments passed on the
258 command line (e.g., by -march). */
259 static int file_ase_mips16
;
261 /* True if -mips3d was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips3d
;
265 /* True if -mdmx was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mdmx
;
269 /* The argument of the -march= flag. The architecture we are assembling. */
270 static int file_mips_arch
= CPU_UNKNOWN
;
271 static const char *mips_arch_string
;
273 /* The argument of the -mtune= flag. The architecture for which we
275 static int mips_tune
= CPU_UNKNOWN
;
276 static const char *mips_tune_string
;
278 /* True when generating 32-bit code for a 64-bit processor. */
279 static int mips_32bitmode
= 0;
281 /* True if the given ABI requires 32-bit registers. */
282 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
284 /* Likewise 64-bit registers. */
285 #define ABI_NEEDS_64BIT_REGS(ABI) \
287 || (ABI) == N64_ABI \
290 /* Return true if ISA supports 64 bit gp register instructions. */
291 #define ISA_HAS_64BIT_REGS(ISA) ( \
293 || (ISA) == ISA_MIPS4 \
294 || (ISA) == ISA_MIPS5 \
295 || (ISA) == ISA_MIPS64 \
296 || (ISA) == ISA_MIPS64R2 \
299 /* Return true if ISA supports 64-bit right rotate (dror et al.)
301 #define ISA_HAS_DROR(ISA) ( \
302 (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 32-bit right rotate (ror et al.)
307 #define ISA_HAS_ROR(ISA) ( \
308 (ISA) == ISA_MIPS32R2 \
309 || (ISA) == ISA_MIPS64R2 \
312 #define HAVE_32BIT_GPRS \
313 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
315 #define HAVE_32BIT_FPRS \
316 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
318 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
319 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
321 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
323 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
325 /* True if relocations are stored in-place. */
326 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
328 /* The ABI-derived address size. */
329 #define HAVE_64BIT_ADDRESSES \
330 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
331 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
333 /* The size of symbolic constants (i.e., expressions of the form
334 "SYMBOL" or "SYMBOL + OFFSET"). */
335 #define HAVE_32BIT_SYMBOLS \
336 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
337 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
339 /* Addresses are loaded in different ways, depending on the address size
340 in use. The n32 ABI Documentation also mandates the use of additions
341 with overflow checking, but existing implementations don't follow it. */
342 #define ADDRESS_ADD_INSN \
343 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
345 #define ADDRESS_ADDI_INSN \
346 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
348 #define ADDRESS_LOAD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
351 #define ADDRESS_STORE_INSN \
352 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
354 /* Return true if the given CPU supports the MIPS16 ASE. */
355 #define CPU_HAS_MIPS16(cpu) \
356 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
357 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
359 /* Return true if the given CPU supports the MIPS3D ASE. */
360 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
363 /* Return true if the given CPU supports the MDMX ASE. */
364 #define CPU_HAS_MDMX(cpu) (FALSE \
367 /* True if CPU has a dror instruction. */
368 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
370 /* True if CPU has a ror instruction. */
371 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
373 /* True if mflo and mfhi can be immediately followed by instructions
374 which write to the HI and LO registers.
376 According to MIPS specifications, MIPS ISAs I, II, and III need
377 (at least) two instructions between the reads of HI/LO and
378 instructions which write them, and later ISAs do not. Contradicting
379 the MIPS specifications, some MIPS IV processor user manuals (e.g.
380 the UM for the NEC Vr5000) document needing the instructions between
381 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
382 MIPS64 and later ISAs to have the interlocks, plus any specific
383 earlier-ISA CPUs for which CPU documentation declares that the
384 instructions are really interlocked. */
385 #define hilo_interlocks \
386 (mips_opts.isa == ISA_MIPS32 \
387 || mips_opts.isa == ISA_MIPS32R2 \
388 || mips_opts.isa == ISA_MIPS64 \
389 || mips_opts.isa == ISA_MIPS64R2 \
390 || mips_opts.arch == CPU_R4010 \
391 || mips_opts.arch == CPU_R10000 \
392 || mips_opts.arch == CPU_R12000 \
393 || mips_opts.arch == CPU_RM7000 \
394 || mips_opts.arch == CPU_VR5500 \
397 /* Whether the processor uses hardware interlocks to protect reads
398 from the GPRs after they are loaded from memory, and thus does not
399 require nops to be inserted. This applies to instructions marked
400 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
402 #define gpr_interlocks \
403 (mips_opts.isa != ISA_MIPS1 \
404 || mips_opts.arch == CPU_R3900)
406 /* Whether the processor uses hardware interlocks to avoid delays
407 required by coprocessor instructions, and thus does not require
408 nops to be inserted. This applies to instructions marked
409 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
410 between instructions marked INSN_WRITE_COND_CODE and ones marked
411 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
412 levels I, II, and III. */
413 /* Itbl support may require additional care here. */
414 #define cop_interlocks \
415 ((mips_opts.isa != ISA_MIPS1 \
416 && mips_opts.isa != ISA_MIPS2 \
417 && mips_opts.isa != ISA_MIPS3) \
418 || mips_opts.arch == CPU_R4300 \
421 /* Whether the processor uses hardware interlocks to protect reads
422 from coprocessor registers after they are loaded from memory, and
423 thus does not require nops to be inserted. This applies to
424 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
425 requires at MIPS ISA level I. */
426 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
428 /* Is this a mfhi or mflo instruction? */
429 #define MF_HILO_INSN(PINFO) \
430 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
432 /* MIPS PIC level. */
434 enum mips_pic_level mips_pic
;
436 /* 1 if we should generate 32 bit offsets from the $gp register in
437 SVR4_PIC mode. Currently has no meaning in other modes. */
438 static int mips_big_got
= 0;
440 /* 1 if trap instructions should used for overflow rather than break
442 static int mips_trap
= 0;
444 /* 1 if double width floating point constants should not be constructed
445 by assembling two single width halves into two single width floating
446 point registers which just happen to alias the double width destination
447 register. On some architectures this aliasing can be disabled by a bit
448 in the status register, and the setting of this bit cannot be determined
449 automatically at assemble time. */
450 static int mips_disable_float_construction
;
452 /* Non-zero if any .set noreorder directives were used. */
454 static int mips_any_noreorder
;
456 /* Non-zero if nops should be inserted when the register referenced in
457 an mfhi/mflo instruction is read in the next two instructions. */
458 static int mips_7000_hilo_fix
;
460 /* The size of the small data section. */
461 static unsigned int g_switch_value
= 8;
462 /* Whether the -G option was used. */
463 static int g_switch_seen
= 0;
468 /* If we can determine in advance that GP optimization won't be
469 possible, we can skip the relaxation stuff that tries to produce
470 GP-relative references. This makes delay slot optimization work
473 This function can only provide a guess, but it seems to work for
474 gcc output. It needs to guess right for gcc, otherwise gcc
475 will put what it thinks is a GP-relative instruction in a branch
478 I don't know if a fix is needed for the SVR4_PIC mode. I've only
479 fixed it for the non-PIC mode. KR 95/04/07 */
480 static int nopic_need_relax (symbolS
*, int);
482 /* handle of the OPCODE hash table */
483 static struct hash_control
*op_hash
= NULL
;
485 /* The opcode hash table we use for the mips16. */
486 static struct hash_control
*mips16_op_hash
= NULL
;
488 /* This array holds the chars that always start a comment. If the
489 pre-processor is disabled, these aren't very useful */
490 const char comment_chars
[] = "#";
492 /* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
494 .line and .file directives will appear in the pre-processed output */
495 /* Note that input_file.c hand checks for '#' at the beginning of the
496 first line of the input file. This is because the compiler outputs
497 #NO_APP at the beginning of its output. */
498 /* Also note that C style comments are always supported. */
499 const char line_comment_chars
[] = "#";
501 /* This array holds machine specific line separator characters. */
502 const char line_separator_chars
[] = ";";
504 /* Chars that can be used to separate mant from exp in floating point nums */
505 const char EXP_CHARS
[] = "eE";
507 /* Chars that mean this number is a floating point constant */
510 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
512 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
513 changed in read.c . Ideally it shouldn't have to know about it at all,
514 but nothing is ideal around here.
517 static char *insn_error
;
519 static int auto_align
= 1;
521 /* When outputting SVR4 PIC code, the assembler needs to know the
522 offset in the stack frame from which to restore the $gp register.
523 This is set by the .cprestore pseudo-op, and saved in this
525 static offsetT mips_cprestore_offset
= -1;
527 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
528 more optimizations, it can use a register value instead of a memory-saved
529 offset and even an other register than $gp as global pointer. */
530 static offsetT mips_cpreturn_offset
= -1;
531 static int mips_cpreturn_register
= -1;
532 static int mips_gp_register
= GP
;
533 static int mips_gprel_offset
= 0;
535 /* Whether mips_cprestore_offset has been set in the current function
536 (or whether it has already been warned about, if not). */
537 static int mips_cprestore_valid
= 0;
539 /* This is the register which holds the stack frame, as set by the
540 .frame pseudo-op. This is needed to implement .cprestore. */
541 static int mips_frame_reg
= SP
;
543 /* Whether mips_frame_reg has been set in the current function
544 (or whether it has already been warned about, if not). */
545 static int mips_frame_reg_valid
= 0;
547 /* To output NOP instructions correctly, we need to keep information
548 about the previous two instructions. */
550 /* Whether we are optimizing. The default value of 2 means to remove
551 unneeded NOPs and swap branch instructions when possible. A value
552 of 1 means to not swap branches. A value of 0 means to always
554 static int mips_optimize
= 2;
556 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
557 equivalent to seeing no -g option at all. */
558 static int mips_debug
= 0;
560 /* A list of previous instructions, with index 0 being the most recent. */
561 static struct mips_cl_insn history
[2];
563 /* If we don't want information for a history[] entry, we
564 point the insn_mo field at this dummy integer. */
565 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0, 0 };
567 /* If this is set, it points to a frag holding nop instructions which
568 were inserted before the start of a noreorder section. If those
569 nops turn out to be unnecessary, the size of the frag can be
571 static fragS
*prev_nop_frag
;
573 /* The number of nop instructions we created in prev_nop_frag. */
574 static int prev_nop_frag_holds
;
576 /* The number of nop instructions that we know we need in
578 static int prev_nop_frag_required
;
580 /* The number of instructions we've seen since prev_nop_frag. */
581 static int prev_nop_frag_since
;
583 /* For ECOFF and ELF, relocations against symbols are done in two
584 parts, with a HI relocation and a LO relocation. Each relocation
585 has only 16 bits of space to store an addend. This means that in
586 order for the linker to handle carries correctly, it must be able
587 to locate both the HI and the LO relocation. This means that the
588 relocations must appear in order in the relocation table.
590 In order to implement this, we keep track of each unmatched HI
591 relocation. We then sort them so that they immediately precede the
592 corresponding LO relocation. */
597 struct mips_hi_fixup
*next
;
600 /* The section this fixup is in. */
604 /* The list of unmatched HI relocs. */
606 static struct mips_hi_fixup
*mips_hi_fixup_list
;
608 /* The frag containing the last explicit relocation operator.
609 Null if explicit relocations have not been used. */
611 static fragS
*prev_reloc_op_frag
;
613 /* Map normal MIPS register numbers to mips16 register numbers. */
615 #define X ILLEGAL_REG
616 static const int mips32_to_16_reg_map
[] =
618 X
, X
, 2, 3, 4, 5, 6, 7,
619 X
, X
, X
, X
, X
, X
, X
, X
,
620 0, 1, X
, X
, X
, X
, X
, X
,
621 X
, X
, X
, X
, X
, X
, X
, X
625 /* Map mips16 register numbers to normal MIPS register numbers. */
627 static const unsigned int mips16_to_32_reg_map
[] =
629 16, 17, 2, 3, 4, 5, 6, 7
632 static int mips_fix_vr4120
;
634 /* We don't relax branches by default, since this causes us to expand
635 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
636 fail to compute the offset before expanding the macro to the most
637 efficient expansion. */
639 static int mips_relax_branch
;
641 /* The expansion of many macros depends on the type of symbol that
642 they refer to. For example, when generating position-dependent code,
643 a macro that refers to a symbol may have two different expansions,
644 one which uses GP-relative addresses and one which uses absolute
645 addresses. When generating SVR4-style PIC, a macro may have
646 different expansions for local and global symbols.
648 We handle these situations by generating both sequences and putting
649 them in variant frags. In position-dependent code, the first sequence
650 will be the GP-relative one and the second sequence will be the
651 absolute one. In SVR4 PIC, the first sequence will be for global
652 symbols and the second will be for local symbols.
654 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
655 SECOND are the lengths of the two sequences in bytes. These fields
656 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
657 the subtype has the following flags:
660 Set if it has been decided that we should use the second
661 sequence instead of the first.
664 Set in the first variant frag if the macro's second implementation
665 is longer than its first. This refers to the macro as a whole,
666 not an individual relaxation.
669 Set in the first variant frag if the macro appeared in a .set nomacro
670 block and if one alternative requires a warning but the other does not.
673 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
676 The frag's "opcode" points to the first fixup for relaxable code.
678 Relaxable macros are generated using a sequence such as:
680 relax_start (SYMBOL);
681 ... generate first expansion ...
683 ... generate second expansion ...
686 The code and fixups for the unwanted alternative are discarded
687 by md_convert_frag. */
688 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
690 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
691 #define RELAX_SECOND(X) ((X) & 0xff)
692 #define RELAX_USE_SECOND 0x10000
693 #define RELAX_SECOND_LONGER 0x20000
694 #define RELAX_NOMACRO 0x40000
695 #define RELAX_DELAY_SLOT 0x80000
697 /* Branch without likely bit. If label is out of range, we turn:
699 beq reg1, reg2, label
709 with the following opcode replacements:
716 bltzal <-> bgezal (with jal label instead of j label)
718 Even though keeping the delay slot instruction in the delay slot of
719 the branch would be more efficient, it would be very tricky to do
720 correctly, because we'd have to introduce a variable frag *after*
721 the delay slot instruction, and expand that instead. Let's do it
722 the easy way for now, even if the branch-not-taken case now costs
723 one additional instruction. Out-of-range branches are not supposed
724 to be common, anyway.
726 Branch likely. If label is out of range, we turn:
728 beql reg1, reg2, label
729 delay slot (annulled if branch not taken)
738 delay slot (executed only if branch taken)
741 It would be possible to generate a shorter sequence by losing the
742 likely bit, generating something like:
747 delay slot (executed only if branch taken)
759 bltzall -> bgezal (with jal label instead of j label)
760 bgezall -> bltzal (ditto)
763 but it's not clear that it would actually improve performance. */
764 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
767 | ((toofar) ? 1 : 0) \
769 | ((likely) ? 4 : 0) \
770 | ((uncond) ? 8 : 0)))
771 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
772 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
773 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
774 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
775 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
777 /* For mips16 code, we use an entirely different form of relaxation.
778 mips16 supports two versions of most instructions which take
779 immediate values: a small one which takes some small value, and a
780 larger one which takes a 16 bit value. Since branches also follow
781 this pattern, relaxing these values is required.
783 We can assemble both mips16 and normal MIPS code in a single
784 object. Therefore, we need to support this type of relaxation at
785 the same time that we support the relaxation described above. We
786 use the high bit of the subtype field to distinguish these cases.
788 The information we store for this type of relaxation is the
789 argument code found in the opcode file for this relocation, whether
790 the user explicitly requested a small or extended form, and whether
791 the relocation is in a jump or jal delay slot. That tells us the
792 size of the value, and how it should be stored. We also store
793 whether the fragment is considered to be extended or not. We also
794 store whether this is known to be a branch to a different section,
795 whether we have tried to relax this frag yet, and whether we have
796 ever extended a PC relative fragment because of a shift count. */
797 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
800 | ((small) ? 0x100 : 0) \
801 | ((ext) ? 0x200 : 0) \
802 | ((dslot) ? 0x400 : 0) \
803 | ((jal_dslot) ? 0x800 : 0))
804 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
805 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
806 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
807 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
808 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
809 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
810 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
811 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
812 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
813 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
814 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
815 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
817 /* Is the given value a sign-extended 32-bit value? */
818 #define IS_SEXT_32BIT_NUM(x) \
819 (((x) &~ (offsetT) 0x7fffffff) == 0 \
820 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
822 /* Is the given value a sign-extended 16-bit value? */
823 #define IS_SEXT_16BIT_NUM(x) \
824 (((x) &~ (offsetT) 0x7fff) == 0 \
825 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
828 /* Global variables used when generating relaxable macros. See the
829 comment above RELAX_ENCODE for more details about how relaxation
832 /* 0 if we're not emitting a relaxable macro.
833 1 if we're emitting the first of the two relaxation alternatives.
834 2 if we're emitting the second alternative. */
837 /* The first relaxable fixup in the current frag. (In other words,
838 the first fixup that refers to relaxable code.) */
841 /* sizes[0] says how many bytes of the first alternative are stored in
842 the current frag. Likewise sizes[1] for the second alternative. */
843 unsigned int sizes
[2];
845 /* The symbol on which the choice of sequence depends. */
849 /* Global variables used to decide whether a macro needs a warning. */
851 /* True if the macro is in a branch delay slot. */
852 bfd_boolean delay_slot_p
;
854 /* For relaxable macros, sizes[0] is the length of the first alternative
855 in bytes and sizes[1] is the length of the second alternative.
856 For non-relaxable macros, both elements give the length of the
858 unsigned int sizes
[2];
860 /* The first variant frag for this macro. */
862 } mips_macro_warning
;
864 /* Prototypes for static functions. */
866 #define internalError() \
867 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
869 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
871 static void append_insn
872 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
873 static void mips_no_prev_insn (int);
874 static void mips16_macro_build
875 (expressionS
*, const char *, const char *, va_list);
876 static void load_register (int, expressionS
*, int);
877 static void macro_start (void);
878 static void macro_end (void);
879 static void macro (struct mips_cl_insn
* ip
);
880 static void mips16_macro (struct mips_cl_insn
* ip
);
881 #ifdef LOSING_COMPILER
882 static void macro2 (struct mips_cl_insn
* ip
);
884 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
885 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
886 static void mips16_immed
887 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
888 unsigned long *, bfd_boolean
*, unsigned short *);
889 static size_t my_getSmallExpression
890 (expressionS
*, bfd_reloc_code_real_type
*, char *);
891 static void my_getExpression (expressionS
*, char *);
892 static void s_align (int);
893 static void s_change_sec (int);
894 static void s_change_section (int);
895 static void s_cons (int);
896 static void s_float_cons (int);
897 static void s_mips_globl (int);
898 static void s_option (int);
899 static void s_mipsset (int);
900 static void s_abicalls (int);
901 static void s_cpload (int);
902 static void s_cpsetup (int);
903 static void s_cplocal (int);
904 static void s_cprestore (int);
905 static void s_cpreturn (int);
906 static void s_gpvalue (int);
907 static void s_gpword (int);
908 static void s_gpdword (int);
909 static void s_cpadd (int);
910 static void s_insn (int);
911 static void md_obj_begin (void);
912 static void md_obj_end (void);
913 static void s_mips_ent (int);
914 static void s_mips_end (int);
915 static void s_mips_frame (int);
916 static void s_mips_mask (int reg_type
);
917 static void s_mips_stab (int);
918 static void s_mips_weakext (int);
919 static void s_mips_file (int);
920 static void s_mips_loc (int);
921 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
922 static int relaxed_branch_length (fragS
*, asection
*, int);
923 static int validate_mips_insn (const struct mips_opcode
*);
925 /* Table and functions used to map between CPU/ISA names, and
926 ISA levels, and CPU numbers. */
930 const char *name
; /* CPU or ISA name. */
931 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
932 int isa
; /* ISA level. */
933 int cpu
; /* CPU number (default CPU if ISA). */
936 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
937 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
938 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
942 The following pseudo-ops from the Kane and Heinrich MIPS book
943 should be defined here, but are currently unsupported: .alias,
944 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
946 The following pseudo-ops from the Kane and Heinrich MIPS book are
947 specific to the type of debugging information being generated, and
948 should be defined by the object format: .aent, .begin, .bend,
949 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
952 The following pseudo-ops from the Kane and Heinrich MIPS book are
953 not MIPS CPU specific, but are also not specific to the object file
954 format. This file is probably the best place to define them, but
955 they are not currently supported: .asm0, .endr, .lab, .repeat,
958 static const pseudo_typeS mips_pseudo_table
[] =
960 /* MIPS specific pseudo-ops. */
961 {"option", s_option
, 0},
962 {"set", s_mipsset
, 0},
963 {"rdata", s_change_sec
, 'r'},
964 {"sdata", s_change_sec
, 's'},
965 {"livereg", s_ignore
, 0},
966 {"abicalls", s_abicalls
, 0},
967 {"cpload", s_cpload
, 0},
968 {"cpsetup", s_cpsetup
, 0},
969 {"cplocal", s_cplocal
, 0},
970 {"cprestore", s_cprestore
, 0},
971 {"cpreturn", s_cpreturn
, 0},
972 {"gpvalue", s_gpvalue
, 0},
973 {"gpword", s_gpword
, 0},
974 {"gpdword", s_gpdword
, 0},
975 {"cpadd", s_cpadd
, 0},
978 /* Relatively generic pseudo-ops that happen to be used on MIPS
980 {"asciiz", stringer
, 1},
981 {"bss", s_change_sec
, 'b'},
984 {"dword", s_cons
, 3},
985 {"weakext", s_mips_weakext
, 0},
987 /* These pseudo-ops are defined in read.c, but must be overridden
988 here for one reason or another. */
989 {"align", s_align
, 0},
991 {"data", s_change_sec
, 'd'},
992 {"double", s_float_cons
, 'd'},
993 {"float", s_float_cons
, 'f'},
994 {"globl", s_mips_globl
, 0},
995 {"global", s_mips_globl
, 0},
996 {"hword", s_cons
, 1},
1000 {"quad", s_cons
, 3},
1001 {"section", s_change_section
, 0},
1002 {"short", s_cons
, 1},
1003 {"single", s_float_cons
, 'f'},
1004 {"stabn", s_mips_stab
, 'n'},
1005 {"text", s_change_sec
, 't'},
1006 {"word", s_cons
, 2},
1008 { "extern", ecoff_directive_extern
, 0},
1013 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1015 /* These pseudo-ops should be defined by the object file format.
1016 However, a.out doesn't support them, so we have versions here. */
1017 {"aent", s_mips_ent
, 1},
1018 {"bgnb", s_ignore
, 0},
1019 {"end", s_mips_end
, 0},
1020 {"endb", s_ignore
, 0},
1021 {"ent", s_mips_ent
, 0},
1022 {"file", s_mips_file
, 0},
1023 {"fmask", s_mips_mask
, 'F'},
1024 {"frame", s_mips_frame
, 0},
1025 {"loc", s_mips_loc
, 0},
1026 {"mask", s_mips_mask
, 'R'},
1027 {"verstamp", s_ignore
, 0},
1031 extern void pop_insert (const pseudo_typeS
*);
1034 mips_pop_insert (void)
1036 pop_insert (mips_pseudo_table
);
1037 if (! ECOFF_DEBUGGING
)
1038 pop_insert (mips_nonecoff_pseudo_table
);
1041 /* Symbols labelling the current insn. */
1043 struct insn_label_list
1045 struct insn_label_list
*next
;
1049 static struct insn_label_list
*insn_labels
;
1050 static struct insn_label_list
*free_insn_labels
;
1052 static void mips_clear_insn_labels (void);
1055 mips_clear_insn_labels (void)
1057 register struct insn_label_list
**pl
;
1059 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1065 static char *expr_end
;
1067 /* Expressions which appear in instructions. These are set by
1070 static expressionS imm_expr
;
1071 static expressionS imm2_expr
;
1072 static expressionS offset_expr
;
1074 /* Relocs associated with imm_expr and offset_expr. */
1076 static bfd_reloc_code_real_type imm_reloc
[3]
1077 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1078 static bfd_reloc_code_real_type offset_reloc
[3]
1079 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1081 /* These are set by mips16_ip if an explicit extension is used. */
1083 static bfd_boolean mips16_small
, mips16_ext
;
1086 /* The pdr segment for per procedure frame/regmask info. Not used for
1089 static segT pdr_seg
;
1092 /* The default target format to use. */
1095 mips_target_format (void)
1097 switch (OUTPUT_FLAVOR
)
1099 case bfd_target_ecoff_flavour
:
1100 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1101 case bfd_target_coff_flavour
:
1103 case bfd_target_elf_flavour
:
1105 /* This is traditional mips. */
1106 return (target_big_endian
1107 ? (HAVE_64BIT_OBJECTS
1108 ? "elf64-tradbigmips"
1110 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1111 : (HAVE_64BIT_OBJECTS
1112 ? "elf64-tradlittlemips"
1114 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1116 return (target_big_endian
1117 ? (HAVE_64BIT_OBJECTS
1120 ? "elf32-nbigmips" : "elf32-bigmips"))
1121 : (HAVE_64BIT_OBJECTS
1122 ? "elf64-littlemips"
1124 ? "elf32-nlittlemips" : "elf32-littlemips")));
1132 /* This function is called once, at assembler startup time. It should
1133 set up all the tables, etc. that the MD part of the assembler will need. */
1138 register const char *retval
= NULL
;
1142 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1143 as_warn (_("Could not set architecture and machine"));
1145 op_hash
= hash_new ();
1147 for (i
= 0; i
< NUMOPCODES
;)
1149 const char *name
= mips_opcodes
[i
].name
;
1151 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1154 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1155 mips_opcodes
[i
].name
, retval
);
1156 /* Probably a memory allocation problem? Give up now. */
1157 as_fatal (_("Broken assembler. No assembly attempted."));
1161 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1163 if (!validate_mips_insn (&mips_opcodes
[i
]))
1168 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1171 mips16_op_hash
= hash_new ();
1174 while (i
< bfd_mips16_num_opcodes
)
1176 const char *name
= mips16_opcodes
[i
].name
;
1178 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1180 as_fatal (_("internal: can't hash `%s': %s"),
1181 mips16_opcodes
[i
].name
, retval
);
1184 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1185 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1186 != mips16_opcodes
[i
].match
))
1188 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1189 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1194 while (i
< bfd_mips16_num_opcodes
1195 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1199 as_fatal (_("Broken assembler. No assembly attempted."));
1201 /* We add all the general register names to the symbol table. This
1202 helps us detect invalid uses of them. */
1203 for (i
= 0; i
< 32; i
++)
1207 sprintf (buf
, "$%d", i
);
1208 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1209 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1214 &zero_address_frag
));
1215 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1216 &zero_address_frag
));
1217 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1218 &zero_address_frag
));
1219 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1220 &zero_address_frag
));
1221 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1222 &zero_address_frag
));
1223 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1224 &zero_address_frag
));
1225 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1226 &zero_address_frag
));
1227 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1228 &zero_address_frag
));
1230 /* If we don't add these register names to the symbol table, they
1231 may end up being added as regular symbols by operand(), and then
1232 make it to the object file as undefined in case they're not
1233 regarded as local symbols. They're local in o32, since `$' is a
1234 local symbol prefix, but not in n32 or n64. */
1235 for (i
= 0; i
< 8; i
++)
1239 sprintf (buf
, "$fcc%i", i
);
1240 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1241 &zero_address_frag
));
1244 mips_no_prev_insn (FALSE
);
1247 mips_cprmask
[0] = 0;
1248 mips_cprmask
[1] = 0;
1249 mips_cprmask
[2] = 0;
1250 mips_cprmask
[3] = 0;
1252 /* set the default alignment for the text section (2**2) */
1253 record_alignment (text_section
, 2);
1255 bfd_set_gp_size (stdoutput
, g_switch_value
);
1257 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1259 /* On a native system, sections must be aligned to 16 byte
1260 boundaries. When configured for an embedded ELF target, we
1262 if (strcmp (TARGET_OS
, "elf") != 0)
1264 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1265 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1266 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1269 /* Create a .reginfo section for register masks and a .mdebug
1270 section for debugging information. */
1278 subseg
= now_subseg
;
1280 /* The ABI says this section should be loaded so that the
1281 running program can access it. However, we don't load it
1282 if we are configured for an embedded target */
1283 flags
= SEC_READONLY
| SEC_DATA
;
1284 if (strcmp (TARGET_OS
, "elf") != 0)
1285 flags
|= SEC_ALLOC
| SEC_LOAD
;
1287 if (mips_abi
!= N64_ABI
)
1289 sec
= subseg_new (".reginfo", (subsegT
) 0);
1291 bfd_set_section_flags (stdoutput
, sec
, flags
);
1292 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1295 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1300 /* The 64-bit ABI uses a .MIPS.options section rather than
1301 .reginfo section. */
1302 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1303 bfd_set_section_flags (stdoutput
, sec
, flags
);
1304 bfd_set_section_alignment (stdoutput
, sec
, 3);
1307 /* Set up the option header. */
1309 Elf_Internal_Options opthdr
;
1312 opthdr
.kind
= ODK_REGINFO
;
1313 opthdr
.size
= (sizeof (Elf_External_Options
)
1314 + sizeof (Elf64_External_RegInfo
));
1317 f
= frag_more (sizeof (Elf_External_Options
));
1318 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1319 (Elf_External_Options
*) f
);
1321 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1326 if (ECOFF_DEBUGGING
)
1328 sec
= subseg_new (".mdebug", (subsegT
) 0);
1329 (void) bfd_set_section_flags (stdoutput
, sec
,
1330 SEC_HAS_CONTENTS
| SEC_READONLY
);
1331 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1334 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1336 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1337 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1338 SEC_READONLY
| SEC_RELOC
1340 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1344 subseg_set (seg
, subseg
);
1348 if (! ECOFF_DEBUGGING
)
1355 if (! ECOFF_DEBUGGING
)
1360 md_assemble (char *str
)
1362 struct mips_cl_insn insn
;
1363 bfd_reloc_code_real_type unused_reloc
[3]
1364 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1366 imm_expr
.X_op
= O_absent
;
1367 imm2_expr
.X_op
= O_absent
;
1368 offset_expr
.X_op
= O_absent
;
1369 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1370 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1371 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1372 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1373 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1374 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1376 if (mips_opts
.mips16
)
1377 mips16_ip (str
, &insn
);
1380 mips_ip (str
, &insn
);
1381 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1382 str
, insn
.insn_opcode
));
1387 as_bad ("%s `%s'", insn_error
, str
);
1391 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1394 if (mips_opts
.mips16
)
1395 mips16_macro (&insn
);
1402 if (imm_expr
.X_op
!= O_absent
)
1403 append_insn (&insn
, &imm_expr
, imm_reloc
);
1404 else if (offset_expr
.X_op
!= O_absent
)
1405 append_insn (&insn
, &offset_expr
, offset_reloc
);
1407 append_insn (&insn
, NULL
, unused_reloc
);
1411 /* Return true if the given relocation might need a matching %lo().
1412 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1413 applied to local symbols. */
1415 static inline bfd_boolean
1416 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1418 return (HAVE_IN_PLACE_ADDENDS
1419 && (reloc
== BFD_RELOC_HI16_S
1420 || reloc
== BFD_RELOC_MIPS_GOT16
1421 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1424 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1427 static inline bfd_boolean
1428 fixup_has_matching_lo_p (fixS
*fixp
)
1430 return (fixp
->fx_next
!= NULL
1431 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1432 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1433 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1434 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1437 /* See whether instruction IP reads register REG. CLASS is the type
1441 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1442 enum mips_regclass
class)
1444 if (class == MIPS16_REG
)
1446 assert (mips_opts
.mips16
);
1447 reg
= mips16_to_32_reg_map
[reg
];
1448 class = MIPS_GR_REG
;
1451 /* Don't report on general register ZERO, since it never changes. */
1452 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1455 if (class == MIPS_FP_REG
)
1457 assert (! mips_opts
.mips16
);
1458 /* If we are called with either $f0 or $f1, we must check $f0.
1459 This is not optimal, because it will introduce an unnecessary
1460 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1461 need to distinguish reading both $f0 and $f1 or just one of
1462 them. Note that we don't have to check the other way,
1463 because there is no instruction that sets both $f0 and $f1
1464 and requires a delay. */
1465 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1466 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1467 == (reg
&~ (unsigned) 1)))
1469 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1470 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1471 == (reg
&~ (unsigned) 1)))
1474 else if (! mips_opts
.mips16
)
1476 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1477 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1479 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1480 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1485 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1486 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1487 & MIPS16OP_MASK_RX
)]
1490 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1491 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1492 & MIPS16OP_MASK_RY
)]
1495 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1496 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1497 & MIPS16OP_MASK_MOVE32Z
)]
1500 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1502 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1504 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1506 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1507 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1508 & MIPS16OP_MASK_REGR32
) == reg
)
1515 /* This function returns true if modifying a register requires a
1519 reg_needs_delay (unsigned int reg
)
1521 unsigned long prev_pinfo
;
1523 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1524 if (! mips_opts
.noreorder
1525 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1526 && ! gpr_interlocks
)
1527 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1528 && ! cop_interlocks
)))
1530 /* A load from a coprocessor or from memory. All load delays
1531 delay the use of general register rt for one instruction. */
1532 /* Itbl support may require additional care here. */
1533 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1534 if (reg
== ((history
[0].insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1541 /* Mark instruction labels in mips16 mode. This permits the linker to
1542 handle them specially, such as generating jalx instructions when
1543 needed. We also make them odd for the duration of the assembly, in
1544 order to generate the right sort of code. We will make them even
1545 in the adjust_symtab routine, while leaving them marked. This is
1546 convenient for the debugger and the disassembler. The linker knows
1547 to make them odd again. */
1550 mips16_mark_labels (void)
1552 if (mips_opts
.mips16
)
1554 struct insn_label_list
*l
;
1557 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1560 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1561 S_SET_OTHER (l
->label
, STO_MIPS16
);
1563 val
= S_GET_VALUE (l
->label
);
1565 S_SET_VALUE (l
->label
, val
+ 1);
1570 /* End the current frag. Make it a variant frag and record the
1574 relax_close_frag (void)
1576 mips_macro_warning
.first_frag
= frag_now
;
1577 frag_var (rs_machine_dependent
, 0, 0,
1578 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1579 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1581 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1582 mips_relax
.first_fixup
= 0;
1585 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1586 See the comment above RELAX_ENCODE for more details. */
1589 relax_start (symbolS
*symbol
)
1591 assert (mips_relax
.sequence
== 0);
1592 mips_relax
.sequence
= 1;
1593 mips_relax
.symbol
= symbol
;
1596 /* Start generating the second version of a relaxable sequence.
1597 See the comment above RELAX_ENCODE for more details. */
1602 assert (mips_relax
.sequence
== 1);
1603 mips_relax
.sequence
= 2;
1606 /* End the current relaxable sequence. */
1611 assert (mips_relax
.sequence
== 2);
1612 relax_close_frag ();
1613 mips_relax
.sequence
= 0;
1616 /* Output an instruction. IP is the instruction information.
1617 ADDRESS_EXPR is an operand of the instruction to be used with
1621 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1622 bfd_reloc_code_real_type
*reloc_type
)
1624 register unsigned long prev_pinfo
, pinfo
;
1628 relax_stateT prev_insn_frag_type
= 0;
1629 bfd_boolean relaxed_branch
= FALSE
;
1630 bfd_boolean force_new_frag
= FALSE
;
1632 /* Mark instruction labels in mips16 mode. */
1633 mips16_mark_labels ();
1635 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1636 pinfo
= ip
->insn_mo
->pinfo
;
1638 if (mips_relax
.sequence
!= 2
1639 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1643 /* If the previous insn required any delay slots, see if we need
1644 to insert a NOP or two. There are eight kinds of possible
1645 hazards, of which an instruction can have at most one type.
1646 (1) a load from memory delay
1647 (2) a load from a coprocessor delay
1648 (3) an unconditional branch delay
1649 (4) a conditional branch delay
1650 (5) a move to coprocessor register delay
1651 (6) a load coprocessor register from memory delay
1652 (7) a coprocessor condition code delay
1653 (8) a HI/LO special register delay
1655 There are a lot of optimizations we could do that we don't.
1656 In particular, we do not, in general, reorder instructions.
1657 If you use gcc with optimization, it will reorder
1658 instructions and generally do much more optimization then we
1659 do here; repeating all that work in the assembler would only
1660 benefit hand written assembly code, and does not seem worth
1663 /* This is how a NOP is emitted. */
1664 #define emit_nop() \
1666 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1667 : md_number_to_chars (frag_more (4), 0, 4))
1669 /* The previous insn might require a delay slot, depending upon
1670 the contents of the current insn. */
1671 if (! mips_opts
.mips16
1672 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1673 && ! gpr_interlocks
)
1674 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1675 && ! cop_interlocks
)))
1677 /* A load from a coprocessor or from memory. All load
1678 delays delay the use of general register rt for one
1680 /* Itbl support may require additional care here. */
1681 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1682 if (mips_optimize
== 0
1683 || insn_uses_reg (ip
,
1684 ((history
[0].insn_opcode
>> OP_SH_RT
)
1689 else if (! mips_opts
.mips16
1690 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1691 && ! cop_interlocks
)
1692 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1693 && ! cop_mem_interlocks
)))
1695 /* A generic coprocessor delay. The previous instruction
1696 modified a coprocessor general or control register. If
1697 it modified a control register, we need to avoid any
1698 coprocessor instruction (this is probably not always
1699 required, but it sometimes is). If it modified a general
1700 register, we avoid using that register.
1702 This case is not handled very well. There is no special
1703 knowledge of CP0 handling, and the coprocessors other
1704 than the floating point unit are not distinguished at
1706 /* Itbl support may require additional care here. FIXME!
1707 Need to modify this to include knowledge about
1708 user specified delays! */
1709 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1711 if (mips_optimize
== 0
1712 || insn_uses_reg (ip
,
1713 ((history
[0].insn_opcode
>> OP_SH_FT
)
1718 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1720 if (mips_optimize
== 0
1721 || insn_uses_reg (ip
,
1722 ((history
[0].insn_opcode
>> OP_SH_FS
)
1729 /* We don't know exactly what the previous instruction
1730 does. If the current instruction uses a coprocessor
1731 register, we must insert a NOP. If previous
1732 instruction may set the condition codes, and the
1733 current instruction uses them, we must insert two
1735 /* Itbl support may require additional care here. */
1736 if (mips_optimize
== 0
1737 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1738 && (pinfo
& INSN_READ_COND_CODE
)))
1740 else if (pinfo
& INSN_COP
)
1744 else if (! mips_opts
.mips16
1745 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1746 && ! cop_interlocks
)
1748 /* The previous instruction sets the coprocessor condition
1749 codes, but does not require a general coprocessor delay
1750 (this means it is a floating point comparison
1751 instruction). If this instruction uses the condition
1752 codes, we need to insert a single NOP. */
1753 /* Itbl support may require additional care here. */
1754 if (mips_optimize
== 0
1755 || (pinfo
& INSN_READ_COND_CODE
))
1759 /* If we're fixing up mfhi/mflo for the r7000 and the
1760 previous insn was an mfhi/mflo and the current insn
1761 reads the register that the mfhi/mflo wrote to, then
1764 else if (mips_7000_hilo_fix
1765 && MF_HILO_INSN (prev_pinfo
)
1766 && insn_uses_reg (ip
, ((history
[0].insn_opcode
>> OP_SH_RD
)
1773 /* If we're fixing up mfhi/mflo for the r7000 and the
1774 2nd previous insn was an mfhi/mflo and the current insn
1775 reads the register that the mfhi/mflo wrote to, then
1778 else if (mips_7000_hilo_fix
1779 && MF_HILO_INSN (history
[1].insn_opcode
)
1780 && insn_uses_reg (ip
, ((history
[1].insn_opcode
>> OP_SH_RD
)
1788 else if (prev_pinfo
& INSN_READ_LO
)
1790 /* The previous instruction reads the LO register; if the
1791 current instruction writes to the LO register, we must
1792 insert two NOPS. Some newer processors have interlocks.
1793 Also the tx39's multiply instructions can be executed
1794 immediately after a read from HI/LO (without the delay),
1795 though the tx39's divide insns still do require the
1797 if (! (hilo_interlocks
1798 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1799 && (mips_optimize
== 0
1800 || (pinfo
& INSN_WRITE_LO
)))
1802 /* Most mips16 branch insns don't have a delay slot.
1803 If a read from LO is immediately followed by a branch
1804 to a write to LO we have a read followed by a write
1805 less than 2 insns away. We assume the target of
1806 a branch might be a write to LO, and insert a nop
1807 between a read and an immediately following branch. */
1808 else if (mips_opts
.mips16
1809 && (mips_optimize
== 0
1810 || (pinfo
& MIPS16_INSN_BRANCH
)))
1813 else if (history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
1815 /* The previous instruction reads the HI register; if the
1816 current instruction writes to the HI register, we must
1817 insert a NOP. Some newer processors have interlocks.
1818 Also the note tx39's multiply above. */
1819 if (! (hilo_interlocks
1820 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1821 && (mips_optimize
== 0
1822 || (pinfo
& INSN_WRITE_HI
)))
1824 /* Most mips16 branch insns don't have a delay slot.
1825 If a read from HI is immediately followed by a branch
1826 to a write to HI we have a read followed by a write
1827 less than 2 insns away. We assume the target of
1828 a branch might be a write to HI, and insert a nop
1829 between a read and an immediately following branch. */
1830 else if (mips_opts
.mips16
1831 && (mips_optimize
== 0
1832 || (pinfo
& MIPS16_INSN_BRANCH
)))
1836 /* If the previous instruction was in a noreorder section, then
1837 we don't want to insert the nop after all. */
1838 /* Itbl support may require additional care here. */
1839 if (history
[0].noreorder_p
)
1842 /* There are two cases which require two intervening
1843 instructions: 1) setting the condition codes using a move to
1844 coprocessor instruction which requires a general coprocessor
1845 delay and then reading the condition codes 2) reading the HI
1846 or LO register and then writing to it (except on processors
1847 which have interlocks). If we are not already emitting a NOP
1848 instruction, we must check for these cases compared to the
1849 instruction previous to the previous instruction. */
1850 if ((! mips_opts
.mips16
1851 && (history
[1].insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1852 && (history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1853 && (pinfo
& INSN_READ_COND_CODE
)
1854 && ! cop_interlocks
)
1855 || ((history
[1].insn_mo
->pinfo
& INSN_READ_LO
)
1856 && (pinfo
& INSN_WRITE_LO
)
1857 && ! (hilo_interlocks
1858 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1859 || ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
1860 && (pinfo
& INSN_WRITE_HI
)
1861 && ! (hilo_interlocks
1862 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1867 if (history
[1].noreorder_p
)
1870 if (prev_prev_nop
&& nops
== 0)
1873 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
1875 /* We're out of bits in pinfo, so we must resort to string
1876 ops here. Shortcuts are selected based on opcodes being
1877 limited to the VR4120 instruction set. */
1879 const char *pn
= history
[0].insn_mo
->name
;
1880 const char *tn
= ip
->insn_mo
->name
;
1881 if (strncmp (pn
, "macc", 4) == 0
1882 || strncmp (pn
, "dmacc", 5) == 0)
1884 /* Errata 21 - [D]DIV[U] after [D]MACC */
1885 if (strstr (tn
, "div"))
1888 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1889 instruction is executed immediately after a MACC or
1890 DMACC instruction, the result of [either instruction]
1892 if (strncmp (tn
, "mult", 4) == 0
1893 || strncmp (tn
, "dmult", 5) == 0)
1896 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1897 Applies on top of VR4181A MD(1) errata. */
1898 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1901 /* Errata 24 - MT{LO,HI} after [D]MACC */
1902 if (strcmp (tn
, "mtlo") == 0
1903 || strcmp (tn
, "mthi") == 0)
1906 else if (strncmp (pn
, "dmult", 5) == 0
1907 && (strncmp (tn
, "dmult", 5) == 0
1908 || strncmp (tn
, "dmacc", 5) == 0))
1910 /* Here is the rest of errata 23. */
1913 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1914 && (strncmp (tn
, "macc", 4) == 0
1915 || strncmp (tn
, "dmacc", 5) == 0))
1917 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1918 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1919 DDIV or DDIVU instruction, the result of the MACC or
1920 DMACC instruction is incorrect.". This partly overlaps
1921 the workaround for errata 23. */
1924 if (nops
< min_nops
)
1928 /* If we are being given a nop instruction, don't bother with
1929 one of the nops we would otherwise output. This will only
1930 happen when a nop instruction is used with mips_optimize set
1933 && ! mips_opts
.noreorder
1934 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1937 /* Now emit the right number of NOP instructions. */
1938 if (nops
> 0 && ! mips_opts
.noreorder
)
1941 unsigned long old_frag_offset
;
1943 struct insn_label_list
*l
;
1945 old_frag
= frag_now
;
1946 old_frag_offset
= frag_now_fix ();
1948 for (i
= 0; i
< nops
; i
++)
1953 listing_prev_line ();
1954 /* We may be at the start of a variant frag. In case we
1955 are, make sure there is enough space for the frag
1956 after the frags created by listing_prev_line. The
1957 argument to frag_grow here must be at least as large
1958 as the argument to all other calls to frag_grow in
1959 this file. We don't have to worry about being in the
1960 middle of a variant frag, because the variants insert
1961 all needed nop instructions themselves. */
1965 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1969 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1970 symbol_set_frag (l
->label
, frag_now
);
1971 val
= (valueT
) frag_now_fix ();
1972 /* mips16 text labels are stored as odd. */
1973 if (mips_opts
.mips16
)
1975 S_SET_VALUE (l
->label
, val
);
1978 #ifndef NO_ECOFF_DEBUGGING
1979 if (ECOFF_DEBUGGING
)
1980 ecoff_fix_loc (old_frag
, old_frag_offset
);
1983 else if (prev_nop_frag
!= NULL
)
1985 /* We have a frag holding nops we may be able to remove. If
1986 we don't need any nops, we can decrease the size of
1987 prev_nop_frag by the size of one instruction. If we do
1988 need some nops, we count them in prev_nops_required. */
1989 if (prev_nop_frag_since
== 0)
1993 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1994 --prev_nop_frag_holds
;
1997 prev_nop_frag_required
+= nops
;
2001 if (prev_prev_nop
== 0)
2003 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2004 --prev_nop_frag_holds
;
2007 ++prev_nop_frag_required
;
2010 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2011 prev_nop_frag
= NULL
;
2013 ++prev_nop_frag_since
;
2015 /* Sanity check: by the time we reach the second instruction
2016 after prev_nop_frag, we should have used up all the nops
2017 one way or another. */
2018 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2023 /* The value passed to dwarf2_emit_insn is the distance between
2024 the beginning of the current instruction and the address that
2025 should be recorded in the debug tables. For MIPS16 debug info
2026 we want to use ISA-encoded addresses, so we pass -1 for an
2027 address higher by one than the current. */
2028 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2031 /* Record the frag type before frag_var. */
2032 if (history
[0].frag
)
2033 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2036 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2037 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2038 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2039 && mips_relax_branch
2040 /* Don't try branch relaxation within .set nomacro, or within
2041 .set noat if we use $at for PIC computations. If it turns
2042 out that the branch was out-of-range, we'll get an error. */
2043 && !mips_opts
.warn_about_macros
2044 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2045 && !mips_opts
.mips16
)
2047 relaxed_branch
= TRUE
;
2048 f
= frag_var (rs_machine_dependent
,
2049 relaxed_branch_length
2051 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2052 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2054 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2055 pinfo
& INSN_COND_BRANCH_LIKELY
,
2056 pinfo
& INSN_WRITE_GPR_31
,
2058 address_expr
->X_add_symbol
,
2059 address_expr
->X_add_number
,
2061 *reloc_type
= BFD_RELOC_UNUSED
;
2063 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2065 /* We need to set up a variant frag. */
2066 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2067 f
= frag_var (rs_machine_dependent
, 4, 0,
2068 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2069 mips16_small
, mips16_ext
,
2071 & INSN_UNCOND_BRANCH_DELAY
),
2072 history
[0].mips16_absolute_jump_p
),
2073 make_expr_symbol (address_expr
), 0, NULL
);
2075 else if (mips_opts
.mips16
2077 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2079 /* Make sure there is enough room to swap this instruction with
2080 a following jump instruction. */
2086 if (mips_opts
.mips16
2087 && mips_opts
.noreorder
2088 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2089 as_warn (_("extended instruction in delay slot"));
2091 if (mips_relax
.sequence
)
2093 /* If we've reached the end of this frag, turn it into a variant
2094 frag and record the information for the instructions we've
2096 if (frag_room () < 4)
2097 relax_close_frag ();
2098 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2101 if (mips_relax
.sequence
!= 2)
2102 mips_macro_warning
.sizes
[0] += 4;
2103 if (mips_relax
.sequence
!= 1)
2104 mips_macro_warning
.sizes
[1] += 4;
2109 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2110 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2112 if (address_expr
->X_op
== O_constant
)
2116 switch (*reloc_type
)
2119 ip
->insn_opcode
|= address_expr
->X_add_number
;
2122 case BFD_RELOC_MIPS_HIGHEST
:
2123 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2124 ip
->insn_opcode
|= tmp
& 0xffff;
2127 case BFD_RELOC_MIPS_HIGHER
:
2128 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2129 ip
->insn_opcode
|= tmp
& 0xffff;
2132 case BFD_RELOC_HI16_S
:
2133 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2134 ip
->insn_opcode
|= tmp
& 0xffff;
2137 case BFD_RELOC_HI16
:
2138 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2141 case BFD_RELOC_UNUSED
:
2142 case BFD_RELOC_LO16
:
2143 case BFD_RELOC_MIPS_GOT_DISP
:
2144 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2147 case BFD_RELOC_MIPS_JMP
:
2148 if ((address_expr
->X_add_number
& 3) != 0)
2149 as_bad (_("jump to misaligned address (0x%lx)"),
2150 (unsigned long) address_expr
->X_add_number
);
2151 if (address_expr
->X_add_number
& ~0xfffffff)
2152 as_bad (_("jump address range overflow (0x%lx)"),
2153 (unsigned long) address_expr
->X_add_number
);
2154 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2157 case BFD_RELOC_MIPS16_JMP
:
2158 if ((address_expr
->X_add_number
& 3) != 0)
2159 as_bad (_("jump to misaligned address (0x%lx)"),
2160 (unsigned long) address_expr
->X_add_number
);
2161 if (address_expr
->X_add_number
& ~0xfffffff)
2162 as_bad (_("jump address range overflow (0x%lx)"),
2163 (unsigned long) address_expr
->X_add_number
);
2165 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2166 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2167 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2170 case BFD_RELOC_16_PCREL_S2
:
2177 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2180 reloc_howto_type
*howto
;
2183 /* In a compound relocation, it is the final (outermost)
2184 operator that determines the relocated field. */
2185 for (i
= 1; i
< 3; i
++)
2186 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2189 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2190 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2191 bfd_get_reloc_size(howto
),
2193 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2196 /* These relocations can have an addend that won't fit in
2197 4 octets for 64bit assembly. */
2199 && ! howto
->partial_inplace
2200 && (reloc_type
[0] == BFD_RELOC_16
2201 || reloc_type
[0] == BFD_RELOC_32
2202 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2203 || reloc_type
[0] == BFD_RELOC_HI16_S
2204 || reloc_type
[0] == BFD_RELOC_LO16
2205 || reloc_type
[0] == BFD_RELOC_GPREL16
2206 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2207 || reloc_type
[0] == BFD_RELOC_GPREL32
2208 || reloc_type
[0] == BFD_RELOC_64
2209 || reloc_type
[0] == BFD_RELOC_CTOR
2210 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2211 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2212 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2213 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2214 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2215 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2216 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2217 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2218 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2219 fixp
[0]->fx_no_overflow
= 1;
2221 if (mips_relax
.sequence
)
2223 if (mips_relax
.first_fixup
== 0)
2224 mips_relax
.first_fixup
= fixp
[0];
2226 else if (reloc_needs_lo_p (*reloc_type
))
2228 struct mips_hi_fixup
*hi_fixup
;
2230 /* Reuse the last entry if it already has a matching %lo. */
2231 hi_fixup
= mips_hi_fixup_list
;
2233 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2235 hi_fixup
= ((struct mips_hi_fixup
*)
2236 xmalloc (sizeof (struct mips_hi_fixup
)));
2237 hi_fixup
->next
= mips_hi_fixup_list
;
2238 mips_hi_fixup_list
= hi_fixup
;
2240 hi_fixup
->fixp
= fixp
[0];
2241 hi_fixup
->seg
= now_seg
;
2244 /* Add fixups for the second and third relocations, if given.
2245 Note that the ABI allows the second relocation to be
2246 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2247 moment we only use RSS_UNDEF, but we could add support
2248 for the others if it ever becomes necessary. */
2249 for (i
= 1; i
< 3; i
++)
2250 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2252 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2253 fixp
[0]->fx_size
, NULL
, 0,
2254 FALSE
, reloc_type
[i
]);
2256 /* Use fx_tcbit to mark compound relocs. */
2257 fixp
[0]->fx_tcbit
= 1;
2258 fixp
[i
]->fx_tcbit
= 1;
2263 if (! mips_opts
.mips16
)
2264 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2265 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2267 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2268 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2274 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2277 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2280 /* Update the register mask information. */
2281 if (! mips_opts
.mips16
)
2283 if (pinfo
& INSN_WRITE_GPR_D
)
2284 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2285 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2286 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2287 if (pinfo
& INSN_READ_GPR_S
)
2288 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2289 if (pinfo
& INSN_WRITE_GPR_31
)
2290 mips_gprmask
|= 1 << RA
;
2291 if (pinfo
& INSN_WRITE_FPR_D
)
2292 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2293 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2294 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2295 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2296 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2297 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2298 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2299 if (pinfo
& INSN_COP
)
2301 /* We don't keep enough information to sort these cases out.
2302 The itbl support does keep this information however, although
2303 we currently don't support itbl fprmats as part of the cop
2304 instruction. May want to add this support in the future. */
2306 /* Never set the bit for $0, which is always zero. */
2307 mips_gprmask
&= ~1 << 0;
2311 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2312 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2313 & MIPS16OP_MASK_RX
);
2314 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2315 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2316 & MIPS16OP_MASK_RY
);
2317 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2318 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2319 & MIPS16OP_MASK_RZ
);
2320 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2321 mips_gprmask
|= 1 << TREG
;
2322 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2323 mips_gprmask
|= 1 << SP
;
2324 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2325 mips_gprmask
|= 1 << RA
;
2326 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2327 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2328 if (pinfo
& MIPS16_INSN_READ_Z
)
2329 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2330 & MIPS16OP_MASK_MOVE32Z
);
2331 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2332 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2333 & MIPS16OP_MASK_REGR32
);
2336 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2338 /* Filling the branch delay slot is more complex. We try to
2339 switch the branch with the previous instruction, which we can
2340 do if the previous instruction does not set up a condition
2341 that the branch tests and if the branch is not itself the
2342 target of any branch. */
2343 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2344 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2346 if (mips_optimize
< 2
2347 /* If we have seen .set volatile or .set nomove, don't
2349 || mips_opts
.nomove
!= 0
2350 /* If we had to emit any NOP instructions, then we
2351 already know we can not swap. */
2353 /* We can't swap if the previous instruction's position
2355 || history
[0].fixed_p
2356 /* If the previous previous insn was in a .set
2357 noreorder, we can't swap. Actually, the MIPS
2358 assembler will swap in this situation. However, gcc
2359 configured -with-gnu-as will generate code like
2365 in which we can not swap the bne and INSN. If gcc is
2366 not configured -with-gnu-as, it does not output the
2368 || history
[1].noreorder_p
2369 /* If the branch is itself the target of a branch, we
2370 can not swap. We cheat on this; all we check for is
2371 whether there is a label on this instruction. If
2372 there are any branches to anything other than a
2373 label, users must use .set noreorder. */
2374 || insn_labels
!= NULL
2375 /* If the previous instruction is in a variant frag
2376 other than this branch's one, we cannot do the swap.
2377 This does not apply to the mips16, which uses variant
2378 frags for different purposes. */
2379 || (! mips_opts
.mips16
2380 && prev_insn_frag_type
== rs_machine_dependent
)
2381 /* If the branch reads the condition codes, we don't
2382 even try to swap, because in the sequence
2387 we can not swap, and I don't feel like handling that
2389 || (! mips_opts
.mips16
2390 && (pinfo
& INSN_READ_COND_CODE
)
2391 && ! cop_interlocks
)
2392 /* We can not swap with an instruction that requires a
2393 delay slot, because the target of the branch might
2394 interfere with that instruction. */
2395 || (! mips_opts
.mips16
2397 /* Itbl support may require additional care here. */
2398 & (INSN_LOAD_COPROC_DELAY
2399 | INSN_COPROC_MOVE_DELAY
2400 | INSN_WRITE_COND_CODE
))
2401 && ! cop_interlocks
)
2402 || (! (hilo_interlocks
2403 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2407 || (! mips_opts
.mips16
2408 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2409 && ! gpr_interlocks
)
2410 || (! mips_opts
.mips16
2411 /* Itbl support may require additional care here. */
2412 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2413 && ! cop_mem_interlocks
)
2414 /* We can not swap with a branch instruction. */
2416 & (INSN_UNCOND_BRANCH_DELAY
2417 | INSN_COND_BRANCH_DELAY
2418 | INSN_COND_BRANCH_LIKELY
))
2419 /* We do not swap with a trap instruction, since it
2420 complicates trap handlers to have the trap
2421 instruction be in a delay slot. */
2422 || (prev_pinfo
& INSN_TRAP
)
2423 /* If the branch reads a register that the previous
2424 instruction sets, we can not swap. */
2425 || (! mips_opts
.mips16
2426 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2427 && insn_uses_reg (ip
,
2428 ((history
[0].insn_opcode
>> OP_SH_RT
)
2431 || (! mips_opts
.mips16
2432 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2433 && insn_uses_reg (ip
,
2434 ((history
[0].insn_opcode
>> OP_SH_RD
)
2437 || (mips_opts
.mips16
2438 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2439 && insn_uses_reg (ip
,
2440 ((history
[0].insn_opcode
2442 & MIPS16OP_MASK_RX
),
2444 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2445 && insn_uses_reg (ip
,
2446 ((history
[0].insn_opcode
2448 & MIPS16OP_MASK_RY
),
2450 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2451 && insn_uses_reg (ip
,
2452 ((history
[0].insn_opcode
2454 & MIPS16OP_MASK_RZ
),
2456 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2457 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2458 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2459 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2460 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2461 && insn_uses_reg (ip
,
2462 MIPS16OP_EXTRACT_REG32R
2463 (history
[0].insn_opcode
),
2465 /* If the branch writes a register that the previous
2466 instruction sets, we can not swap (we know that
2467 branches write only to RD or to $31). */
2468 || (! mips_opts
.mips16
2469 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2470 && (((pinfo
& INSN_WRITE_GPR_D
)
2471 && (((history
[0].insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2472 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2473 || ((pinfo
& INSN_WRITE_GPR_31
)
2474 && (((history
[0].insn_opcode
>> OP_SH_RT
)
2477 || (! mips_opts
.mips16
2478 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2479 && (((pinfo
& INSN_WRITE_GPR_D
)
2480 && (((history
[0].insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2481 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2482 || ((pinfo
& INSN_WRITE_GPR_31
)
2483 && (((history
[0].insn_opcode
>> OP_SH_RD
)
2486 || (mips_opts
.mips16
2487 && (pinfo
& MIPS16_INSN_WRITE_31
)
2488 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2489 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2490 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2492 /* If the branch writes a register that the previous
2493 instruction reads, we can not swap (we know that
2494 branches only write to RD or to $31). */
2495 || (! mips_opts
.mips16
2496 && (pinfo
& INSN_WRITE_GPR_D
)
2497 && insn_uses_reg (&history
[0],
2498 ((ip
->insn_opcode
>> OP_SH_RD
)
2501 || (! mips_opts
.mips16
2502 && (pinfo
& INSN_WRITE_GPR_31
)
2503 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2504 || (mips_opts
.mips16
2505 && (pinfo
& MIPS16_INSN_WRITE_31
)
2506 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2507 /* If the previous previous instruction has a load
2508 delay, and sets a register that the branch reads, we
2510 || (! mips_opts
.mips16
2511 /* Itbl support may require additional care here. */
2512 && (((history
[1].insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2513 && ! cop_interlocks
)
2514 || ((history
[1].insn_mo
->pinfo
2515 & INSN_LOAD_MEMORY_DELAY
)
2516 && ! gpr_interlocks
))
2517 && insn_uses_reg (ip
,
2518 ((history
[1].insn_opcode
>> OP_SH_RT
)
2521 /* If one instruction sets a condition code and the
2522 other one uses a condition code, we can not swap. */
2523 || ((pinfo
& INSN_READ_COND_CODE
)
2524 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2525 || ((pinfo
& INSN_WRITE_COND_CODE
)
2526 && (prev_pinfo
& INSN_READ_COND_CODE
))
2527 /* If the previous instruction uses the PC, we can not
2529 || (mips_opts
.mips16
2530 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2531 /* If the previous instruction had a fixup in mips16
2532 mode, we can not swap. This normally means that the
2533 previous instruction was a 4 byte branch anyhow. */
2534 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2535 /* If the previous instruction is a sync, sync.l, or
2536 sync.p, we can not swap. */
2537 || (prev_pinfo
& INSN_SYNC
))
2539 /* We could do even better for unconditional branches to
2540 portions of this object file; we could pick up the
2541 instruction at the destination, put it in the delay
2542 slot, and bump the destination address. */
2544 if (mips_relax
.sequence
)
2545 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2546 /* Update the previous insn information. */
2547 history
[1].insn_mo
= ip
->insn_mo
;
2548 history
[1].use_extend
= ip
->use_extend
;
2549 history
[1].extend
= ip
->extend
;
2550 history
[1].insn_opcode
= ip
->insn_opcode
;
2551 history
[0].insn_mo
= &dummy_opcode
;
2555 /* It looks like we can actually do the swap. */
2556 if (! mips_opts
.mips16
)
2561 prev_f
= history
[0].frag
->fr_literal
+ history
[0].where
;
2562 if (!relaxed_branch
)
2564 /* If this is not a relaxed branch, then just
2565 swap the instructions. */
2566 memcpy (temp
, prev_f
, 4);
2567 memcpy (prev_f
, f
, 4);
2568 memcpy (f
, temp
, 4);
2572 /* If this is a relaxed branch, then we move the
2573 instruction to be placed in the delay slot to
2574 the current frag, shrinking the fixed part of
2575 the originating frag. If the branch occupies
2576 the tail of the latter, we move it backwards,
2577 into the space freed by the moved instruction. */
2579 memcpy (f
, prev_f
, 4);
2580 history
[0].frag
->fr_fix
-= 4;
2581 if (history
[0].frag
->fr_type
== rs_machine_dependent
)
2582 memmove (prev_f
, prev_f
+ 4, history
[0].frag
->fr_var
);
2585 if (history
[0].fixp
[0])
2587 history
[0].fixp
[0]->fx_frag
= frag_now
;
2588 history
[0].fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2590 if (history
[0].fixp
[1])
2592 history
[0].fixp
[1]->fx_frag
= frag_now
;
2593 history
[0].fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2595 if (history
[0].fixp
[2])
2597 history
[0].fixp
[2]->fx_frag
= frag_now
;
2598 history
[0].fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2600 if (history
[0].fixp
[0] && HAVE_NEWABI
2601 && history
[0].frag
!= frag_now
2602 && (history
[0].fixp
[0]->fx_r_type
2603 == BFD_RELOC_MIPS_GOT_DISP
2604 || (history
[0].fixp
[0]->fx_r_type
2605 == BFD_RELOC_MIPS_CALL16
)))
2607 /* To avoid confusion in tc_gen_reloc, we must
2608 ensure that this does not become a variant
2610 force_new_frag
= TRUE
;
2613 if (!relaxed_branch
)
2617 fixp
[0]->fx_frag
= history
[0].frag
;
2618 fixp
[0]->fx_where
= history
[0].where
;
2622 fixp
[1]->fx_frag
= history
[0].frag
;
2623 fixp
[1]->fx_where
= history
[0].where
;
2627 fixp
[2]->fx_frag
= history
[0].frag
;
2628 fixp
[2]->fx_where
= history
[0].where
;
2631 else if (history
[0].frag
->fr_type
== rs_machine_dependent
)
2634 fixp
[0]->fx_where
-= 4;
2636 fixp
[1]->fx_where
-= 4;
2638 fixp
[2]->fx_where
-= 4;
2646 assert (history
[0].fixp
[0] == NULL
);
2647 assert (history
[0].fixp
[1] == NULL
);
2648 assert (history
[0].fixp
[2] == NULL
);
2649 prev_f
= history
[0].frag
->fr_literal
+ history
[0].where
;
2650 memcpy (temp
, prev_f
, 2);
2651 memcpy (prev_f
, f
, 2);
2652 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2654 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2655 memcpy (f
, temp
, 2);
2659 memcpy (f
, f
+ 2, 2);
2660 memcpy (f
+ 2, temp
, 2);
2664 fixp
[0]->fx_frag
= history
[0].frag
;
2665 fixp
[0]->fx_where
= history
[0].where
;
2669 fixp
[1]->fx_frag
= history
[0].frag
;
2670 fixp
[1]->fx_where
= history
[0].where
;
2674 fixp
[2]->fx_frag
= history
[0].frag
;
2675 fixp
[2]->fx_where
= history
[0].where
;
2679 /* Update the previous insn information; leave history[0]
2681 history
[1].insn_mo
= ip
->insn_mo
;
2682 history
[1].use_extend
= ip
->use_extend
;
2683 history
[1].extend
= ip
->extend
;
2684 history
[1].insn_opcode
= ip
->insn_opcode
;
2686 history
[0].fixed_p
= 1;
2688 /* If that was an unconditional branch, forget the previous
2689 insn information. */
2690 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2692 history
[1].insn_mo
= &dummy_opcode
;
2693 history
[0].insn_mo
= &dummy_opcode
;
2696 history
[0].fixp
[0] = NULL
;
2697 history
[0].fixp
[1] = NULL
;
2698 history
[0].fixp
[2] = NULL
;
2699 history
[0].mips16_absolute_jump_p
= 0;
2701 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2703 /* We don't yet optimize a branch likely. What we should do
2704 is look at the target, copy the instruction found there
2705 into the delay slot, and increment the branch to jump to
2706 the next instruction. */
2708 /* Update the previous insn information. */
2709 history
[1].insn_mo
= ip
->insn_mo
;
2710 history
[1].use_extend
= ip
->use_extend
;
2711 history
[1].extend
= ip
->extend
;
2712 history
[1].insn_opcode
= ip
->insn_opcode
;
2713 history
[0].insn_mo
= &dummy_opcode
;
2714 history
[0].fixp
[0] = NULL
;
2715 history
[0].fixp
[1] = NULL
;
2716 history
[0].fixp
[2] = NULL
;
2717 history
[0].mips16_absolute_jump_p
= 0;
2718 history
[0].fixed_p
= 1;
2722 /* Update the previous insn information. */
2724 history
[1].insn_mo
= &dummy_opcode
;
2727 history
[1].insn_mo
= history
[0].insn_mo
;
2728 history
[1].use_extend
= history
[0].use_extend
;
2729 history
[1].extend
= history
[0].extend
;
2730 history
[1].insn_opcode
= history
[0].insn_opcode
;
2732 history
[0].insn_mo
= ip
->insn_mo
;
2733 history
[0].use_extend
= ip
->use_extend
;
2734 history
[0].extend
= ip
->extend
;
2735 history
[0].insn_opcode
= ip
->insn_opcode
;
2736 history
[0].fixed_p
= (mips_opts
.mips16
2738 || *reloc_type
> BFD_RELOC_UNUSED
));
2739 history
[0].fixp
[0] = fixp
[0];
2740 history
[0].fixp
[1] = fixp
[1];
2741 history
[0].fixp
[2] = fixp
[2];
2742 history
[0].mips16_absolute_jump_p
= (reloc_type
[0]
2743 == BFD_RELOC_MIPS16_JMP
);
2746 history
[1].noreorder_p
= history
[0].noreorder_p
;
2747 history
[0].noreorder_p
= 0;
2748 history
[0].frag
= frag_now
;
2749 history
[0].where
= f
- frag_now
->fr_literal
;
2751 else if (mips_relax
.sequence
!= 2)
2753 /* We need to record a bit of information even when we are not
2754 reordering, in order to determine the base address for mips16
2755 PC relative relocs. */
2756 history
[1].insn_mo
= history
[0].insn_mo
;
2757 history
[1].use_extend
= history
[0].use_extend
;
2758 history
[1].extend
= history
[0].extend
;
2759 history
[1].insn_opcode
= history
[0].insn_opcode
;
2760 history
[0].insn_mo
= ip
->insn_mo
;
2761 history
[0].use_extend
= ip
->use_extend
;
2762 history
[0].extend
= ip
->extend
;
2763 history
[0].insn_opcode
= ip
->insn_opcode
;
2764 history
[0].mips16_absolute_jump_p
= (reloc_type
[0]
2765 == BFD_RELOC_MIPS16_JMP
);
2766 history
[1].noreorder_p
= history
[0].noreorder_p
;
2767 history
[0].noreorder_p
= 1;
2768 history
[0].fixed_p
= 1;
2771 /* We just output an insn, so the next one doesn't have a label. */
2772 mips_clear_insn_labels ();
2775 /* This function forgets that there was any previous instruction or
2776 label. If PRESERVE is non-zero, it remembers enough information to
2777 know whether nops are needed before a noreorder section. */
2780 mips_no_prev_insn (int preserve
)
2784 history
[0].insn_mo
= &dummy_opcode
;
2785 history
[1].insn_mo
= &dummy_opcode
;
2786 prev_nop_frag
= NULL
;
2787 prev_nop_frag_holds
= 0;
2788 prev_nop_frag_required
= 0;
2789 prev_nop_frag_since
= 0;
2791 history
[0].fixed_p
= 1;
2792 history
[0].noreorder_p
= 0;
2793 history
[0].mips16_absolute_jump_p
= 0;
2794 history
[1].noreorder_p
= 0;
2795 mips_clear_insn_labels ();
2798 /* This function must be called whenever we turn on noreorder or emit
2799 something other than instructions. It inserts any NOPS which might
2800 be needed by the previous instruction, and clears the information
2801 kept for the previous instructions. The INSNS parameter is true if
2802 instructions are to follow. */
2805 mips_emit_delays (bfd_boolean insns
)
2807 if (! mips_opts
.noreorder
)
2812 if ((! mips_opts
.mips16
2813 && ((history
[0].insn_mo
->pinfo
2814 & (INSN_LOAD_COPROC_DELAY
2815 | INSN_COPROC_MOVE_DELAY
2816 | INSN_WRITE_COND_CODE
))
2817 && ! cop_interlocks
))
2818 || (! hilo_interlocks
2819 && (history
[0].insn_mo
->pinfo
2822 || (! mips_opts
.mips16
2823 && (history
[0].insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2824 && ! gpr_interlocks
)
2825 || (! mips_opts
.mips16
2826 && (history
[0].insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2827 && ! cop_mem_interlocks
))
2829 /* Itbl support may require additional care here. */
2831 if ((! mips_opts
.mips16
2832 && ((history
[0].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2833 && ! cop_interlocks
))
2834 || (! hilo_interlocks
2835 && ((history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
2836 || (history
[0].insn_mo
->pinfo
& INSN_READ_LO
))))
2839 if (history
[0].noreorder_p
)
2842 else if ((! mips_opts
.mips16
2843 && ((history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2844 && ! cop_interlocks
))
2845 || (! hilo_interlocks
2846 && ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
2847 || (history
[1].insn_mo
->pinfo
& INSN_READ_LO
))))
2849 /* Itbl support may require additional care here. */
2850 if (! history
[1].noreorder_p
)
2854 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
2857 const char *pn
= history
[0].insn_mo
->name
;
2858 if (strncmp (pn
, "macc", 4) == 0
2859 || strncmp (pn
, "dmacc", 5) == 0
2860 || strncmp (pn
, "dmult", 5) == 0
2861 || strstr (pn
, "div"))
2863 if (nops
< min_nops
)
2869 struct insn_label_list
*l
;
2873 /* Record the frag which holds the nop instructions, so
2874 that we can remove them if we don't need them. */
2875 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2876 prev_nop_frag
= frag_now
;
2877 prev_nop_frag_holds
= nops
;
2878 prev_nop_frag_required
= 0;
2879 prev_nop_frag_since
= 0;
2882 for (; nops
> 0; --nops
)
2887 /* Move on to a new frag, so that it is safe to simply
2888 decrease the size of prev_nop_frag. */
2889 frag_wane (frag_now
);
2893 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2897 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2898 symbol_set_frag (l
->label
, frag_now
);
2899 val
= (valueT
) frag_now_fix ();
2900 /* mips16 text labels are stored as odd. */
2901 if (mips_opts
.mips16
)
2903 S_SET_VALUE (l
->label
, val
);
2908 /* Mark instruction labels in mips16 mode. */
2910 mips16_mark_labels ();
2912 mips_no_prev_insn (insns
);
2915 /* Set up global variables for the start of a new macro. */
2920 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2921 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2922 && (history
[0].insn_mo
->pinfo
2923 & (INSN_UNCOND_BRANCH_DELAY
2924 | INSN_COND_BRANCH_DELAY
2925 | INSN_COND_BRANCH_LIKELY
)) != 0);
2928 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2929 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2930 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2933 macro_warning (relax_substateT subtype
)
2935 if (subtype
& RELAX_DELAY_SLOT
)
2936 return _("Macro instruction expanded into multiple instructions"
2937 " in a branch delay slot");
2938 else if (subtype
& RELAX_NOMACRO
)
2939 return _("Macro instruction expanded into multiple instructions");
2944 /* Finish up a macro. Emit warnings as appropriate. */
2949 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2951 relax_substateT subtype
;
2953 /* Set up the relaxation warning flags. */
2955 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2956 subtype
|= RELAX_SECOND_LONGER
;
2957 if (mips_opts
.warn_about_macros
)
2958 subtype
|= RELAX_NOMACRO
;
2959 if (mips_macro_warning
.delay_slot_p
)
2960 subtype
|= RELAX_DELAY_SLOT
;
2962 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2964 /* Either the macro has a single implementation or both
2965 implementations are longer than 4 bytes. Emit the
2967 const char *msg
= macro_warning (subtype
);
2973 /* One implementation might need a warning but the other
2974 definitely doesn't. */
2975 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2980 /* Read a macro's relocation codes from *ARGS and store them in *R.
2981 The first argument in *ARGS will be either the code for a single
2982 relocation or -1 followed by the three codes that make up a
2983 composite relocation. */
2986 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2990 next
= va_arg (*args
, int);
2992 r
[0] = (bfd_reloc_code_real_type
) next
;
2994 for (i
= 0; i
< 3; i
++)
2995 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2998 /* Build an instruction created by a macro expansion. This is passed
2999 a pointer to the count of instructions created so far, an
3000 expression, the name of the instruction to build, an operand format
3001 string, and corresponding arguments. */
3004 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3006 struct mips_cl_insn insn
;
3007 bfd_reloc_code_real_type r
[3];
3010 va_start (args
, fmt
);
3012 if (mips_opts
.mips16
)
3014 mips16_macro_build (ep
, name
, fmt
, args
);
3019 r
[0] = BFD_RELOC_UNUSED
;
3020 r
[1] = BFD_RELOC_UNUSED
;
3021 r
[2] = BFD_RELOC_UNUSED
;
3022 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3023 assert (insn
.insn_mo
);
3024 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3026 /* Search until we get a match for NAME. */
3029 /* It is assumed here that macros will never generate
3030 MDMX or MIPS-3D instructions. */
3031 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3032 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3033 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3035 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3037 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3041 assert (insn
.insn_mo
->name
);
3042 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3045 insn
.insn_opcode
= insn
.insn_mo
->match
;
3063 insn
.insn_opcode
|= (va_arg (args
, int)
3064 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3069 /* Note that in the macro case, these arguments are already
3070 in MSB form. (When handling the instruction in the
3071 non-macro case, these arguments are sizes from which
3072 MSB values must be calculated.) */
3073 insn
.insn_opcode
|= (va_arg (args
, int)
3074 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3080 /* Note that in the macro case, these arguments are already
3081 in MSBD form. (When handling the instruction in the
3082 non-macro case, these arguments are sizes from which
3083 MSBD values must be calculated.) */
3084 insn
.insn_opcode
|= (va_arg (args
, int)
3085 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3096 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3100 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3105 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3111 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3116 int tmp
= va_arg (args
, int);
3118 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3119 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3125 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3132 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3136 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3140 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3144 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3148 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3155 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3161 macro_read_relocs (&args
, r
);
3162 assert (*r
== BFD_RELOC_GPREL16
3163 || *r
== BFD_RELOC_MIPS_LITERAL
3164 || *r
== BFD_RELOC_MIPS_HIGHER
3165 || *r
== BFD_RELOC_HI16_S
3166 || *r
== BFD_RELOC_LO16
3167 || *r
== BFD_RELOC_MIPS_GOT16
3168 || *r
== BFD_RELOC_MIPS_CALL16
3169 || *r
== BFD_RELOC_MIPS_GOT_DISP
3170 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3171 || *r
== BFD_RELOC_MIPS_GOT_OFST
3172 || *r
== BFD_RELOC_MIPS_GOT_LO16
3173 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3177 macro_read_relocs (&args
, r
);
3179 && (ep
->X_op
== O_constant
3180 || (ep
->X_op
== O_symbol
3181 && (*r
== BFD_RELOC_MIPS_HIGHEST
3182 || *r
== BFD_RELOC_HI16_S
3183 || *r
== BFD_RELOC_HI16
3184 || *r
== BFD_RELOC_GPREL16
3185 || *r
== BFD_RELOC_MIPS_GOT_HI16
3186 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3190 assert (ep
!= NULL
);
3192 * This allows macro() to pass an immediate expression for
3193 * creating short branches without creating a symbol.
3194 * Note that the expression still might come from the assembly
3195 * input, in which case the value is not checked for range nor
3196 * is a relocation entry generated (yuck).
3198 if (ep
->X_op
== O_constant
)
3200 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3204 *r
= BFD_RELOC_16_PCREL_S2
;
3208 assert (ep
!= NULL
);
3209 *r
= BFD_RELOC_MIPS_JMP
;
3213 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3222 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3224 append_insn (&insn
, ep
, r
);
3228 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3231 struct mips_cl_insn insn
;
3232 bfd_reloc_code_real_type r
[3]
3233 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3235 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3236 assert (insn
.insn_mo
);
3237 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3239 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3240 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3243 assert (insn
.insn_mo
->name
);
3244 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3247 insn
.insn_opcode
= insn
.insn_mo
->match
;
3248 insn
.use_extend
= FALSE
;
3267 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3272 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3276 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3280 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3290 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3297 regno
= va_arg (args
, int);
3298 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3299 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3320 assert (ep
!= NULL
);
3322 if (ep
->X_op
!= O_constant
)
3323 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3326 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3327 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3330 *r
= BFD_RELOC_UNUSED
;
3336 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3343 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3345 append_insn (&insn
, ep
, r
);
3349 * Generate a "jalr" instruction with a relocation hint to the called
3350 * function. This occurs in NewABI PIC code.
3353 macro_build_jalr (expressionS
*ep
)
3362 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3364 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3365 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3369 * Generate a "lui" instruction.
3372 macro_build_lui (expressionS
*ep
, int regnum
)
3374 expressionS high_expr
;
3375 struct mips_cl_insn insn
;
3376 bfd_reloc_code_real_type r
[3]
3377 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3378 const char *name
= "lui";
3379 const char *fmt
= "t,u";
3381 assert (! mips_opts
.mips16
);
3385 if (high_expr
.X_op
== O_constant
)
3387 /* we can compute the instruction now without a relocation entry */
3388 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3390 *r
= BFD_RELOC_UNUSED
;
3394 assert (ep
->X_op
== O_symbol
);
3395 /* _gp_disp is a special case, used from s_cpload.
3396 __gnu_local_gp is used if mips_no_shared. */
3397 assert (mips_pic
== NO_PIC
3399 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3400 || (! mips_in_shared
3401 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3402 "__gnu_local_gp") == 0));
3403 *r
= BFD_RELOC_HI16_S
;
3406 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3407 assert (insn
.insn_mo
);
3408 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3409 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3411 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3412 if (*r
== BFD_RELOC_UNUSED
)
3414 insn
.insn_opcode
|= high_expr
.X_add_number
;
3415 append_insn (&insn
, NULL
, r
);
3418 append_insn (&insn
, &high_expr
, r
);
3421 /* Generate a sequence of instructions to do a load or store from a constant
3422 offset off of a base register (breg) into/from a target register (treg),
3423 using AT if necessary. */
3425 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3426 int treg
, int breg
, int dbl
)
3428 assert (ep
->X_op
== O_constant
);
3430 /* Sign-extending 32-bit constants makes their handling easier. */
3431 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3432 == ~((bfd_vma
) 0x7fffffff)))
3434 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3435 as_bad (_("constant too large"));
3437 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3441 /* Right now, this routine can only handle signed 32-bit constants. */
3442 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3443 as_warn (_("operand overflow"));
3445 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3447 /* Signed 16-bit offset will fit in the op. Easy! */
3448 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3452 /* 32-bit offset, need multiple instructions and AT, like:
3453 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3454 addu $tempreg,$tempreg,$breg
3455 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3456 to handle the complete offset. */
3457 macro_build_lui (ep
, AT
);
3458 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3459 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3462 as_bad (_("Macro used $at after \".set noat\""));
3467 * Generates code to set the $at register to true (one)
3468 * if reg is less than the immediate expression.
3471 set_at (int reg
, int unsignedp
)
3473 if (imm_expr
.X_op
== O_constant
3474 && imm_expr
.X_add_number
>= -0x8000
3475 && imm_expr
.X_add_number
< 0x8000)
3476 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3477 AT
, reg
, BFD_RELOC_LO16
);
3480 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3481 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3486 normalize_constant_expr (expressionS
*ex
)
3488 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3489 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3493 /* Warn if an expression is not a constant. */
3496 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3498 if (ex
->X_op
== O_big
)
3499 as_bad (_("unsupported large constant"));
3500 else if (ex
->X_op
!= O_constant
)
3501 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3503 normalize_constant_expr (ex
);
3506 /* Count the leading zeroes by performing a binary chop. This is a
3507 bulky bit of source, but performance is a LOT better for the
3508 majority of values than a simple loop to count the bits:
3509 for (lcnt = 0; (lcnt < 32); lcnt++)
3510 if ((v) & (1 << (31 - lcnt)))
3512 However it is not code size friendly, and the gain will drop a bit
3513 on certain cached systems.
3515 #define COUNT_TOP_ZEROES(v) \
3516 (((v) & ~0xffff) == 0 \
3517 ? ((v) & ~0xff) == 0 \
3518 ? ((v) & ~0xf) == 0 \
3519 ? ((v) & ~0x3) == 0 \
3520 ? ((v) & ~0x1) == 0 \
3525 : ((v) & ~0x7) == 0 \
3528 : ((v) & ~0x3f) == 0 \
3529 ? ((v) & ~0x1f) == 0 \
3532 : ((v) & ~0x7f) == 0 \
3535 : ((v) & ~0xfff) == 0 \
3536 ? ((v) & ~0x3ff) == 0 \
3537 ? ((v) & ~0x1ff) == 0 \
3540 : ((v) & ~0x7ff) == 0 \
3543 : ((v) & ~0x3fff) == 0 \
3544 ? ((v) & ~0x1fff) == 0 \
3547 : ((v) & ~0x7fff) == 0 \
3550 : ((v) & ~0xffffff) == 0 \
3551 ? ((v) & ~0xfffff) == 0 \
3552 ? ((v) & ~0x3ffff) == 0 \
3553 ? ((v) & ~0x1ffff) == 0 \
3556 : ((v) & ~0x7ffff) == 0 \
3559 : ((v) & ~0x3fffff) == 0 \
3560 ? ((v) & ~0x1fffff) == 0 \
3563 : ((v) & ~0x7fffff) == 0 \
3566 : ((v) & ~0xfffffff) == 0 \
3567 ? ((v) & ~0x3ffffff) == 0 \
3568 ? ((v) & ~0x1ffffff) == 0 \
3571 : ((v) & ~0x7ffffff) == 0 \
3574 : ((v) & ~0x3fffffff) == 0 \
3575 ? ((v) & ~0x1fffffff) == 0 \
3578 : ((v) & ~0x7fffffff) == 0 \
3583 * This routine generates the least number of instructions necessary to load
3584 * an absolute expression value into a register.
3587 load_register (int reg
, expressionS
*ep
, int dbl
)
3590 expressionS hi32
, lo32
;
3592 if (ep
->X_op
!= O_big
)
3594 assert (ep
->X_op
== O_constant
);
3596 /* Sign-extending 32-bit constants makes their handling easier. */
3597 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3598 == ~((bfd_vma
) 0x7fffffff)))
3600 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3601 as_bad (_("constant too large"));
3603 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3607 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3609 /* We can handle 16 bit signed values with an addiu to
3610 $zero. No need to ever use daddiu here, since $zero and
3611 the result are always correct in 32 bit mode. */
3612 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3615 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3617 /* We can handle 16 bit unsigned values with an ori to
3619 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3622 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3624 /* 32 bit values require an lui. */
3625 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3626 if ((ep
->X_add_number
& 0xffff) != 0)
3627 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3632 /* The value is larger than 32 bits. */
3634 if (HAVE_32BIT_GPRS
)
3636 as_bad (_("Number (0x%lx) larger than 32 bits"),
3637 (unsigned long) ep
->X_add_number
);
3638 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3642 if (ep
->X_op
!= O_big
)
3645 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3646 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3647 hi32
.X_add_number
&= 0xffffffff;
3649 lo32
.X_add_number
&= 0xffffffff;
3653 assert (ep
->X_add_number
> 2);
3654 if (ep
->X_add_number
== 3)
3655 generic_bignum
[3] = 0;
3656 else if (ep
->X_add_number
> 4)
3657 as_bad (_("Number larger than 64 bits"));
3658 lo32
.X_op
= O_constant
;
3659 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3660 hi32
.X_op
= O_constant
;
3661 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3664 if (hi32
.X_add_number
== 0)
3669 unsigned long hi
, lo
;
3671 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3673 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3675 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3678 if (lo32
.X_add_number
& 0x80000000)
3680 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3681 if (lo32
.X_add_number
& 0xffff)
3682 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3687 /* Check for 16bit shifted constant. We know that hi32 is
3688 non-zero, so start the mask on the first bit of the hi32
3693 unsigned long himask
, lomask
;
3697 himask
= 0xffff >> (32 - shift
);
3698 lomask
= (0xffff << shift
) & 0xffffffff;
3702 himask
= 0xffff << (shift
- 32);
3705 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3706 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3710 tmp
.X_op
= O_constant
;
3712 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3713 | (lo32
.X_add_number
>> shift
));
3715 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3716 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3717 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3718 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3723 while (shift
<= (64 - 16));
3725 /* Find the bit number of the lowest one bit, and store the
3726 shifted value in hi/lo. */
3727 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3728 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3732 while ((lo
& 1) == 0)
3737 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3743 while ((hi
& 1) == 0)
3752 /* Optimize if the shifted value is a (power of 2) - 1. */
3753 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3754 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3756 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3761 /* This instruction will set the register to be all
3763 tmp
.X_op
= O_constant
;
3764 tmp
.X_add_number
= (offsetT
) -1;
3765 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3769 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3770 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3772 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3773 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3778 /* Sign extend hi32 before calling load_register, because we can
3779 generally get better code when we load a sign extended value. */
3780 if ((hi32
.X_add_number
& 0x80000000) != 0)
3781 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3782 load_register (reg
, &hi32
, 0);
3785 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3789 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3797 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3799 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3800 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3806 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3810 mid16
.X_add_number
>>= 16;
3811 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3812 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3815 if ((lo32
.X_add_number
& 0xffff) != 0)
3816 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3820 load_delay_nop (void)
3822 if (!gpr_interlocks
)
3823 macro_build (NULL
, "nop", "");
3826 /* Load an address into a register. */
3829 load_address (int reg
, expressionS
*ep
, int *used_at
)
3831 if (ep
->X_op
!= O_constant
3832 && ep
->X_op
!= O_symbol
)
3834 as_bad (_("expression too complex"));
3835 ep
->X_op
= O_constant
;
3838 if (ep
->X_op
== O_constant
)
3840 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3844 if (mips_pic
== NO_PIC
)
3846 /* If this is a reference to a GP relative symbol, we want
3847 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3849 lui $reg,<sym> (BFD_RELOC_HI16_S)
3850 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3851 If we have an addend, we always use the latter form.
3853 With 64bit address space and a usable $at we want
3854 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3855 lui $at,<sym> (BFD_RELOC_HI16_S)
3856 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3857 daddiu $at,<sym> (BFD_RELOC_LO16)
3861 If $at is already in use, we use a path which is suboptimal
3862 on superscalar processors.
3863 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3864 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3866 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3868 daddiu $reg,<sym> (BFD_RELOC_LO16)
3870 For GP relative symbols in 64bit address space we can use
3871 the same sequence as in 32bit address space. */
3872 if (HAVE_64BIT_SYMBOLS
)
3874 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3875 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3877 relax_start (ep
->X_add_symbol
);
3878 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3879 mips_gp_register
, BFD_RELOC_GPREL16
);
3883 if (*used_at
== 0 && !mips_opts
.noat
)
3885 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3886 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3887 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3888 BFD_RELOC_MIPS_HIGHER
);
3889 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3890 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3891 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3896 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3897 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3898 BFD_RELOC_MIPS_HIGHER
);
3899 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3900 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3901 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3902 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3905 if (mips_relax
.sequence
)
3910 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3911 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3913 relax_start (ep
->X_add_symbol
);
3914 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3915 mips_gp_register
, BFD_RELOC_GPREL16
);
3918 macro_build_lui (ep
, reg
);
3919 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3920 reg
, reg
, BFD_RELOC_LO16
);
3921 if (mips_relax
.sequence
)
3925 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3929 /* If this is a reference to an external symbol, we want
3930 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3932 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3934 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3935 If there is a constant, it must be added in after.
3937 If we have NewABI, we want
3938 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3939 unless we're referencing a global symbol with a non-zero
3940 offset, in which case cst must be added separately. */
3943 if (ep
->X_add_number
)
3945 ex
.X_add_number
= ep
->X_add_number
;
3946 ep
->X_add_number
= 0;
3947 relax_start (ep
->X_add_symbol
);
3948 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3949 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3950 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3951 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3952 ex
.X_op
= O_constant
;
3953 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3954 reg
, reg
, BFD_RELOC_LO16
);
3955 ep
->X_add_number
= ex
.X_add_number
;
3958 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3959 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3960 if (mips_relax
.sequence
)
3965 ex
.X_add_number
= ep
->X_add_number
;
3966 ep
->X_add_number
= 0;
3967 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3968 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3970 relax_start (ep
->X_add_symbol
);
3972 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3976 if (ex
.X_add_number
!= 0)
3978 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3979 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3980 ex
.X_op
= O_constant
;
3981 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3982 reg
, reg
, BFD_RELOC_LO16
);
3986 else if (mips_pic
== SVR4_PIC
)
3990 /* This is the large GOT case. If this is a reference to an
3991 external symbol, we want
3992 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3994 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3996 Otherwise, for a reference to a local symbol in old ABI, we want
3997 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3999 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4000 If there is a constant, it must be added in after.
4002 In the NewABI, for local symbols, with or without offsets, we want:
4003 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4004 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4008 ex
.X_add_number
= ep
->X_add_number
;
4009 ep
->X_add_number
= 0;
4010 relax_start (ep
->X_add_symbol
);
4011 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4012 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4013 reg
, reg
, mips_gp_register
);
4014 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4015 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4016 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4017 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4018 else if (ex
.X_add_number
)
4020 ex
.X_op
= O_constant
;
4021 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4025 ep
->X_add_number
= ex
.X_add_number
;
4027 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4028 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4029 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4030 BFD_RELOC_MIPS_GOT_OFST
);
4035 ex
.X_add_number
= ep
->X_add_number
;
4036 ep
->X_add_number
= 0;
4037 relax_start (ep
->X_add_symbol
);
4038 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4039 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4040 reg
, reg
, mips_gp_register
);
4041 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4042 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4044 if (reg_needs_delay (mips_gp_register
))
4046 /* We need a nop before loading from $gp. This special
4047 check is required because the lui which starts the main
4048 instruction stream does not refer to $gp, and so will not
4049 insert the nop which may be required. */
4050 macro_build (NULL
, "nop", "");
4052 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4053 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4055 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4059 if (ex
.X_add_number
!= 0)
4061 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4062 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4063 ex
.X_op
= O_constant
;
4064 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4072 if (mips_opts
.noat
&& *used_at
== 1)
4073 as_bad (_("Macro used $at after \".set noat\""));
4076 /* Move the contents of register SOURCE into register DEST. */
4079 move_register (int dest
, int source
)
4081 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4085 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4086 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4087 The two alternatives are:
4089 Global symbol Local sybmol
4090 ------------- ------------
4091 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4093 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4095 load_got_offset emits the first instruction and add_got_offset
4096 emits the second for a 16-bit offset or add_got_offset_hilo emits
4097 a sequence to add a 32-bit offset using a scratch register. */
4100 load_got_offset (int dest
, expressionS
*local
)
4105 global
.X_add_number
= 0;
4107 relax_start (local
->X_add_symbol
);
4108 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4109 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4111 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4112 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4117 add_got_offset (int dest
, expressionS
*local
)
4121 global
.X_op
= O_constant
;
4122 global
.X_op_symbol
= NULL
;
4123 global
.X_add_symbol
= NULL
;
4124 global
.X_add_number
= local
->X_add_number
;
4126 relax_start (local
->X_add_symbol
);
4127 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4128 dest
, dest
, BFD_RELOC_LO16
);
4130 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4135 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4138 int hold_mips_optimize
;
4140 global
.X_op
= O_constant
;
4141 global
.X_op_symbol
= NULL
;
4142 global
.X_add_symbol
= NULL
;
4143 global
.X_add_number
= local
->X_add_number
;
4145 relax_start (local
->X_add_symbol
);
4146 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4148 /* Set mips_optimize around the lui instruction to avoid
4149 inserting an unnecessary nop after the lw. */
4150 hold_mips_optimize
= mips_optimize
;
4152 macro_build_lui (&global
, tmp
);
4153 mips_optimize
= hold_mips_optimize
;
4154 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4157 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4162 * This routine implements the seemingly endless macro or synthesized
4163 * instructions and addressing modes in the mips assembly language. Many
4164 * of these macros are simple and are similar to each other. These could
4165 * probably be handled by some kind of table or grammar approach instead of
4166 * this verbose method. Others are not simple macros but are more like
4167 * optimizing code generation.
4168 * One interesting optimization is when several store macros appear
4169 * consecutively that would load AT with the upper half of the same address.
4170 * The ensuing load upper instructions are ommited. This implies some kind
4171 * of global optimization. We currently only optimize within a single macro.
4172 * For many of the load and store macros if the address is specified as a
4173 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4174 * first load register 'at' with zero and use it as the base register. The
4175 * mips assembler simply uses register $zero. Just one tiny optimization
4179 macro (struct mips_cl_insn
*ip
)
4181 register int treg
, sreg
, dreg
, breg
;
4197 bfd_reloc_code_real_type r
;
4198 int hold_mips_optimize
;
4200 assert (! mips_opts
.mips16
);
4202 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4203 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4204 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4205 mask
= ip
->insn_mo
->mask
;
4207 expr1
.X_op
= O_constant
;
4208 expr1
.X_op_symbol
= NULL
;
4209 expr1
.X_add_symbol
= NULL
;
4210 expr1
.X_add_number
= 1;
4222 mips_emit_delays (TRUE
);
4223 ++mips_opts
.noreorder
;
4224 mips_any_noreorder
= 1;
4226 expr1
.X_add_number
= 8;
4227 macro_build (&expr1
, "bgez", "s,p", sreg
);
4229 macro_build (NULL
, "nop", "", 0);
4231 move_register (dreg
, sreg
);
4232 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4234 --mips_opts
.noreorder
;
4255 if (imm_expr
.X_op
== O_constant
4256 && imm_expr
.X_add_number
>= -0x8000
4257 && imm_expr
.X_add_number
< 0x8000)
4259 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4263 load_register (AT
, &imm_expr
, dbl
);
4264 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4283 if (imm_expr
.X_op
== O_constant
4284 && imm_expr
.X_add_number
>= 0
4285 && imm_expr
.X_add_number
< 0x10000)
4287 if (mask
!= M_NOR_I
)
4288 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4291 macro_build (&imm_expr
, "ori", "t,r,i",
4292 treg
, sreg
, BFD_RELOC_LO16
);
4293 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4299 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4300 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4317 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4319 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4323 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4324 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4332 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4337 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4341 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4342 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4348 /* check for > max integer */
4349 maxnum
= 0x7fffffff;
4350 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4357 if (imm_expr
.X_op
== O_constant
4358 && imm_expr
.X_add_number
>= maxnum
4359 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4362 /* result is always false */
4364 macro_build (NULL
, "nop", "", 0);
4366 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4369 if (imm_expr
.X_op
!= O_constant
)
4370 as_bad (_("Unsupported large constant"));
4371 ++imm_expr
.X_add_number
;
4375 if (mask
== M_BGEL_I
)
4377 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4379 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4382 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4384 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4387 maxnum
= 0x7fffffff;
4388 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4395 maxnum
= - maxnum
- 1;
4396 if (imm_expr
.X_op
== O_constant
4397 && imm_expr
.X_add_number
<= maxnum
4398 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4401 /* result is always true */
4402 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4403 macro_build (&offset_expr
, "b", "p");
4408 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4418 macro_build (&offset_expr
, likely
? "beql" : "beq",
4423 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4424 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4432 && imm_expr
.X_op
== O_constant
4433 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4435 if (imm_expr
.X_op
!= O_constant
)
4436 as_bad (_("Unsupported large constant"));
4437 ++imm_expr
.X_add_number
;
4441 if (mask
== M_BGEUL_I
)
4443 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4445 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4447 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4453 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4461 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4466 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4470 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4471 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4479 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4486 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4487 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4495 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4500 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4504 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4505 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4511 maxnum
= 0x7fffffff;
4512 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4519 if (imm_expr
.X_op
== O_constant
4520 && imm_expr
.X_add_number
>= maxnum
4521 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4523 if (imm_expr
.X_op
!= O_constant
)
4524 as_bad (_("Unsupported large constant"));
4525 ++imm_expr
.X_add_number
;
4529 if (mask
== M_BLTL_I
)
4531 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4533 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4536 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4538 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4543 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4551 macro_build (&offset_expr
, likely
? "beql" : "beq",
4558 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4559 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4567 && imm_expr
.X_op
== O_constant
4568 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4570 if (imm_expr
.X_op
!= O_constant
)
4571 as_bad (_("Unsupported large constant"));
4572 ++imm_expr
.X_add_number
;
4576 if (mask
== M_BLTUL_I
)
4578 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4580 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4582 macro_build (&offset_expr
, likely
? "beql" : "beq",
4588 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4596 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4601 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4605 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4606 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4616 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4621 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4622 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4630 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4632 as_bad (_("Unsupported large constant"));
4637 pos
= (unsigned long) imm_expr
.X_add_number
;
4638 size
= (unsigned long) imm2_expr
.X_add_number
;
4643 as_bad (_("Improper position (%lu)"), pos
);
4646 if (size
== 0 || size
> 64
4647 || (pos
+ size
- 1) > 63)
4649 as_bad (_("Improper extract size (%lu, position %lu)"),
4654 if (size
<= 32 && pos
< 32)
4659 else if (size
<= 32)
4669 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4678 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4680 as_bad (_("Unsupported large constant"));
4685 pos
= (unsigned long) imm_expr
.X_add_number
;
4686 size
= (unsigned long) imm2_expr
.X_add_number
;
4691 as_bad (_("Improper position (%lu)"), pos
);
4694 if (size
== 0 || size
> 64
4695 || (pos
+ size
- 1) > 63)
4697 as_bad (_("Improper insert size (%lu, position %lu)"),
4702 if (pos
< 32 && (pos
+ size
- 1) < 32)
4717 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4734 as_warn (_("Divide by zero."));
4736 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4738 macro_build (NULL
, "break", "c", 7);
4742 mips_emit_delays (TRUE
);
4743 ++mips_opts
.noreorder
;
4744 mips_any_noreorder
= 1;
4747 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4748 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4752 expr1
.X_add_number
= 8;
4753 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4754 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4755 macro_build (NULL
, "break", "c", 7);
4757 expr1
.X_add_number
= -1;
4759 load_register (AT
, &expr1
, dbl
);
4760 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4761 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4764 expr1
.X_add_number
= 1;
4765 load_register (AT
, &expr1
, dbl
);
4766 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4770 expr1
.X_add_number
= 0x80000000;
4771 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4775 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4776 /* We want to close the noreorder block as soon as possible, so
4777 that later insns are available for delay slot filling. */
4778 --mips_opts
.noreorder
;
4782 expr1
.X_add_number
= 8;
4783 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4784 macro_build (NULL
, "nop", "", 0);
4786 /* We want to close the noreorder block as soon as possible, so
4787 that later insns are available for delay slot filling. */
4788 --mips_opts
.noreorder
;
4790 macro_build (NULL
, "break", "c", 6);
4792 macro_build (NULL
, s
, "d", dreg
);
4831 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4833 as_warn (_("Divide by zero."));
4835 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4837 macro_build (NULL
, "break", "c", 7);
4840 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4842 if (strcmp (s2
, "mflo") == 0)
4843 move_register (dreg
, sreg
);
4845 move_register (dreg
, 0);
4848 if (imm_expr
.X_op
== O_constant
4849 && imm_expr
.X_add_number
== -1
4850 && s
[strlen (s
) - 1] != 'u')
4852 if (strcmp (s2
, "mflo") == 0)
4854 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4857 move_register (dreg
, 0);
4862 load_register (AT
, &imm_expr
, dbl
);
4863 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4864 macro_build (NULL
, s2
, "d", dreg
);
4883 mips_emit_delays (TRUE
);
4884 ++mips_opts
.noreorder
;
4885 mips_any_noreorder
= 1;
4888 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4889 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4890 /* We want to close the noreorder block as soon as possible, so
4891 that later insns are available for delay slot filling. */
4892 --mips_opts
.noreorder
;
4896 expr1
.X_add_number
= 8;
4897 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4898 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4900 /* We want to close the noreorder block as soon as possible, so
4901 that later insns are available for delay slot filling. */
4902 --mips_opts
.noreorder
;
4903 macro_build (NULL
, "break", "c", 7);
4905 macro_build (NULL
, s2
, "d", dreg
);
4917 /* Load the address of a symbol into a register. If breg is not
4918 zero, we then add a base register to it. */
4920 if (dbl
&& HAVE_32BIT_GPRS
)
4921 as_warn (_("dla used to load 32-bit register"));
4923 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4924 as_warn (_("la used to load 64-bit address"));
4926 if (offset_expr
.X_op
== O_constant
4927 && offset_expr
.X_add_number
>= -0x8000
4928 && offset_expr
.X_add_number
< 0x8000)
4930 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4931 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4935 if (!mips_opts
.noat
&& (treg
== breg
))
4945 if (offset_expr
.X_op
!= O_symbol
4946 && offset_expr
.X_op
!= O_constant
)
4948 as_bad (_("expression too complex"));
4949 offset_expr
.X_op
= O_constant
;
4952 if (offset_expr
.X_op
== O_constant
)
4953 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4954 else if (mips_pic
== NO_PIC
)
4956 /* If this is a reference to a GP relative symbol, we want
4957 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4959 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4960 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4961 If we have a constant, we need two instructions anyhow,
4962 so we may as well always use the latter form.
4964 With 64bit address space and a usable $at we want
4965 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4966 lui $at,<sym> (BFD_RELOC_HI16_S)
4967 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4968 daddiu $at,<sym> (BFD_RELOC_LO16)
4970 daddu $tempreg,$tempreg,$at
4972 If $at is already in use, we use a path which is suboptimal
4973 on superscalar processors.
4974 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4975 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4977 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4979 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4981 For GP relative symbols in 64bit address space we can use
4982 the same sequence as in 32bit address space. */
4983 if (HAVE_64BIT_SYMBOLS
)
4985 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4986 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4988 relax_start (offset_expr
.X_add_symbol
);
4989 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4990 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4994 if (used_at
== 0 && !mips_opts
.noat
)
4996 macro_build (&offset_expr
, "lui", "t,u",
4997 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4998 macro_build (&offset_expr
, "lui", "t,u",
4999 AT
, BFD_RELOC_HI16_S
);
5000 macro_build (&offset_expr
, "daddiu", "t,r,j",
5001 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5002 macro_build (&offset_expr
, "daddiu", "t,r,j",
5003 AT
, AT
, BFD_RELOC_LO16
);
5004 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5005 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5010 macro_build (&offset_expr
, "lui", "t,u",
5011 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5012 macro_build (&offset_expr
, "daddiu", "t,r,j",
5013 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5014 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5015 macro_build (&offset_expr
, "daddiu", "t,r,j",
5016 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5017 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5018 macro_build (&offset_expr
, "daddiu", "t,r,j",
5019 tempreg
, tempreg
, BFD_RELOC_LO16
);
5022 if (mips_relax
.sequence
)
5027 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5028 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5030 relax_start (offset_expr
.X_add_symbol
);
5031 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5032 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5035 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5036 as_bad (_("offset too large"));
5037 macro_build_lui (&offset_expr
, tempreg
);
5038 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5039 tempreg
, tempreg
, BFD_RELOC_LO16
);
5040 if (mips_relax
.sequence
)
5044 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5046 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5048 /* If this is a reference to an external symbol, and there
5049 is no constant, we want
5050 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5051 or for lca or if tempreg is PIC_CALL_REG
5052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5053 For a local symbol, we want
5054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5056 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5058 If we have a small constant, and this is a reference to
5059 an external symbol, we want
5060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5062 addiu $tempreg,$tempreg,<constant>
5063 For a local symbol, we want the same instruction
5064 sequence, but we output a BFD_RELOC_LO16 reloc on the
5067 If we have a large constant, and this is a reference to
5068 an external symbol, we want
5069 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5070 lui $at,<hiconstant>
5071 addiu $at,$at,<loconstant>
5072 addu $tempreg,$tempreg,$at
5073 For a local symbol, we want the same instruction
5074 sequence, but we output a BFD_RELOC_LO16 reloc on the
5078 if (offset_expr
.X_add_number
== 0)
5080 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5081 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5083 relax_start (offset_expr
.X_add_symbol
);
5084 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5085 lw_reloc_type
, mips_gp_register
);
5088 /* We're going to put in an addu instruction using
5089 tempreg, so we may as well insert the nop right
5094 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5095 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5097 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5098 tempreg
, tempreg
, BFD_RELOC_LO16
);
5100 /* FIXME: If breg == 0, and the next instruction uses
5101 $tempreg, then if this variant case is used an extra
5102 nop will be generated. */
5104 else if (offset_expr
.X_add_number
>= -0x8000
5105 && offset_expr
.X_add_number
< 0x8000)
5107 load_got_offset (tempreg
, &offset_expr
);
5109 add_got_offset (tempreg
, &offset_expr
);
5113 expr1
.X_add_number
= offset_expr
.X_add_number
;
5114 offset_expr
.X_add_number
=
5115 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5116 load_got_offset (tempreg
, &offset_expr
);
5117 offset_expr
.X_add_number
= expr1
.X_add_number
;
5118 /* If we are going to add in a base register, and the
5119 target register and the base register are the same,
5120 then we are using AT as a temporary register. Since
5121 we want to load the constant into AT, we add our
5122 current AT (from the global offset table) and the
5123 register into the register now, and pretend we were
5124 not using a base register. */
5128 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5133 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5137 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5139 int add_breg_early
= 0;
5141 /* If this is a reference to an external, and there is no
5142 constant, or local symbol (*), with or without a
5144 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5145 or for lca or if tempreg is PIC_CALL_REG
5146 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5148 If we have a small constant, and this is a reference to
5149 an external symbol, we want
5150 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5151 addiu $tempreg,$tempreg,<constant>
5153 If we have a large constant, and this is a reference to
5154 an external symbol, we want
5155 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5156 lui $at,<hiconstant>
5157 addiu $at,$at,<loconstant>
5158 addu $tempreg,$tempreg,$at
5160 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5161 local symbols, even though it introduces an additional
5164 if (offset_expr
.X_add_number
)
5166 expr1
.X_add_number
= offset_expr
.X_add_number
;
5167 offset_expr
.X_add_number
= 0;
5169 relax_start (offset_expr
.X_add_symbol
);
5170 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5171 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5173 if (expr1
.X_add_number
>= -0x8000
5174 && expr1
.X_add_number
< 0x8000)
5176 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5177 tempreg
, tempreg
, BFD_RELOC_LO16
);
5179 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5183 /* If we are going to add in a base register, and the
5184 target register and the base register are the same,
5185 then we are using AT as a temporary register. Since
5186 we want to load the constant into AT, we add our
5187 current AT (from the global offset table) and the
5188 register into the register now, and pretend we were
5189 not using a base register. */
5194 assert (tempreg
== AT
);
5195 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5201 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5208 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5211 offset_expr
.X_add_number
= expr1
.X_add_number
;
5213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5214 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5217 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5218 treg
, tempreg
, breg
);
5224 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5226 relax_start (offset_expr
.X_add_symbol
);
5227 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5228 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5230 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5231 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5236 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5237 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5240 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5243 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5244 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5245 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5247 /* This is the large GOT case. If this is a reference to an
5248 external symbol, and there is no constant, we want
5249 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5250 addu $tempreg,$tempreg,$gp
5251 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5252 or for lca or if tempreg is PIC_CALL_REG
5253 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5254 addu $tempreg,$tempreg,$gp
5255 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5256 For a local symbol, we want
5257 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5259 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5261 If we have a small constant, and this is a reference to
5262 an external symbol, we want
5263 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5264 addu $tempreg,$tempreg,$gp
5265 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5267 addiu $tempreg,$tempreg,<constant>
5268 For a local symbol, we want
5269 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5271 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5273 If we have a large constant, and this is a reference to
5274 an external symbol, we want
5275 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5276 addu $tempreg,$tempreg,$gp
5277 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5278 lui $at,<hiconstant>
5279 addiu $at,$at,<loconstant>
5280 addu $tempreg,$tempreg,$at
5281 For a local symbol, we want
5282 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5283 lui $at,<hiconstant>
5284 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5285 addu $tempreg,$tempreg,$at
5288 expr1
.X_add_number
= offset_expr
.X_add_number
;
5289 offset_expr
.X_add_number
= 0;
5290 relax_start (offset_expr
.X_add_symbol
);
5291 gpdelay
= reg_needs_delay (mips_gp_register
);
5292 if (expr1
.X_add_number
== 0 && breg
== 0
5293 && (call
|| tempreg
== PIC_CALL_REG
))
5295 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5296 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5298 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5299 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5300 tempreg
, tempreg
, mips_gp_register
);
5301 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5302 tempreg
, lw_reloc_type
, tempreg
);
5303 if (expr1
.X_add_number
== 0)
5307 /* We're going to put in an addu instruction using
5308 tempreg, so we may as well insert the nop right
5313 else if (expr1
.X_add_number
>= -0x8000
5314 && expr1
.X_add_number
< 0x8000)
5317 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5318 tempreg
, tempreg
, BFD_RELOC_LO16
);
5324 /* If we are going to add in a base register, and the
5325 target register and the base register are the same,
5326 then we are using AT as a temporary register. Since
5327 we want to load the constant into AT, we add our
5328 current AT (from the global offset table) and the
5329 register into the register now, and pretend we were
5330 not using a base register. */
5335 assert (tempreg
== AT
);
5337 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5342 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5343 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5347 offset_expr
.X_add_number
=
5348 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5353 /* This is needed because this instruction uses $gp, but
5354 the first instruction on the main stream does not. */
5355 macro_build (NULL
, "nop", "");
5358 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5359 local_reloc_type
, mips_gp_register
);
5360 if (expr1
.X_add_number
>= -0x8000
5361 && expr1
.X_add_number
< 0x8000)
5364 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5365 tempreg
, tempreg
, BFD_RELOC_LO16
);
5366 /* FIXME: If add_number is 0, and there was no base
5367 register, the external symbol case ended with a load,
5368 so if the symbol turns out to not be external, and
5369 the next instruction uses tempreg, an unnecessary nop
5370 will be inserted. */
5376 /* We must add in the base register now, as in the
5377 external symbol case. */
5378 assert (tempreg
== AT
);
5380 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5383 /* We set breg to 0 because we have arranged to add
5384 it in in both cases. */
5388 macro_build_lui (&expr1
, AT
);
5389 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5390 AT
, AT
, BFD_RELOC_LO16
);
5391 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5392 tempreg
, tempreg
, AT
);
5397 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5399 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5400 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5401 int add_breg_early
= 0;
5403 /* This is the large GOT case. If this is a reference to an
5404 external symbol, and there is no constant, we want
5405 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5406 add $tempreg,$tempreg,$gp
5407 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5408 or for lca or if tempreg is PIC_CALL_REG
5409 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5410 add $tempreg,$tempreg,$gp
5411 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5413 If we have a small constant, and this is a reference to
5414 an external symbol, we want
5415 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5416 add $tempreg,$tempreg,$gp
5417 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5418 addi $tempreg,$tempreg,<constant>
5420 If we have a large constant, and this is a reference to
5421 an external symbol, we want
5422 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5423 addu $tempreg,$tempreg,$gp
5424 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5425 lui $at,<hiconstant>
5426 addi $at,$at,<loconstant>
5427 add $tempreg,$tempreg,$at
5429 If we have NewABI, and we know it's a local symbol, we want
5430 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5431 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5432 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5434 relax_start (offset_expr
.X_add_symbol
);
5436 expr1
.X_add_number
= offset_expr
.X_add_number
;
5437 offset_expr
.X_add_number
= 0;
5439 if (expr1
.X_add_number
== 0 && breg
== 0
5440 && (call
|| tempreg
== PIC_CALL_REG
))
5442 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5443 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5445 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5446 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5447 tempreg
, tempreg
, mips_gp_register
);
5448 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5449 tempreg
, lw_reloc_type
, tempreg
);
5451 if (expr1
.X_add_number
== 0)
5453 else if (expr1
.X_add_number
>= -0x8000
5454 && expr1
.X_add_number
< 0x8000)
5456 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5457 tempreg
, tempreg
, BFD_RELOC_LO16
);
5459 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5463 /* If we are going to add in a base register, and the
5464 target register and the base register are the same,
5465 then we are using AT as a temporary register. Since
5466 we want to load the constant into AT, we add our
5467 current AT (from the global offset table) and the
5468 register into the register now, and pretend we were
5469 not using a base register. */
5474 assert (tempreg
== AT
);
5475 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5481 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5482 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5487 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5490 offset_expr
.X_add_number
= expr1
.X_add_number
;
5491 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5492 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5493 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5494 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5497 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5498 treg
, tempreg
, breg
);
5508 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5512 /* The j instruction may not be used in PIC code, since it
5513 requires an absolute address. We convert it to a b
5515 if (mips_pic
== NO_PIC
)
5516 macro_build (&offset_expr
, "j", "a");
5518 macro_build (&offset_expr
, "b", "p");
5521 /* The jal instructions must be handled as macros because when
5522 generating PIC code they expand to multi-instruction
5523 sequences. Normally they are simple instructions. */
5528 if (mips_pic
== NO_PIC
)
5529 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5530 else if (mips_pic
== SVR4_PIC
)
5532 if (sreg
!= PIC_CALL_REG
)
5533 as_warn (_("MIPS PIC call to register other than $25"));
5535 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5538 if (mips_cprestore_offset
< 0)
5539 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5542 if (! mips_frame_reg_valid
)
5544 as_warn (_("No .frame pseudo-op used in PIC code"));
5545 /* Quiet this warning. */
5546 mips_frame_reg_valid
= 1;
5548 if (! mips_cprestore_valid
)
5550 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5551 /* Quiet this warning. */
5552 mips_cprestore_valid
= 1;
5554 expr1
.X_add_number
= mips_cprestore_offset
;
5555 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5558 HAVE_64BIT_ADDRESSES
);
5568 if (mips_pic
== NO_PIC
)
5569 macro_build (&offset_expr
, "jal", "a");
5570 else if (mips_pic
== SVR4_PIC
)
5572 /* If this is a reference to an external symbol, and we are
5573 using a small GOT, we want
5574 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5578 lw $gp,cprestore($sp)
5579 The cprestore value is set using the .cprestore
5580 pseudo-op. If we are using a big GOT, we want
5581 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5583 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5587 lw $gp,cprestore($sp)
5588 If the symbol is not external, we want
5589 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5591 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5594 lw $gp,cprestore($sp)
5596 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5597 sequences above, minus nops, unless the symbol is local,
5598 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5604 relax_start (offset_expr
.X_add_symbol
);
5605 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5606 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5609 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5610 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5616 relax_start (offset_expr
.X_add_symbol
);
5617 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5618 BFD_RELOC_MIPS_CALL_HI16
);
5619 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5620 PIC_CALL_REG
, mips_gp_register
);
5621 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5622 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5625 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5626 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5628 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5629 PIC_CALL_REG
, PIC_CALL_REG
,
5630 BFD_RELOC_MIPS_GOT_OFST
);
5634 macro_build_jalr (&offset_expr
);
5638 relax_start (offset_expr
.X_add_symbol
);
5641 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5642 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5651 gpdelay
= reg_needs_delay (mips_gp_register
);
5652 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5653 BFD_RELOC_MIPS_CALL_HI16
);
5654 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5655 PIC_CALL_REG
, mips_gp_register
);
5656 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5657 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5662 macro_build (NULL
, "nop", "");
5664 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5665 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5668 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5669 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5671 macro_build_jalr (&offset_expr
);
5673 if (mips_cprestore_offset
< 0)
5674 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5677 if (! mips_frame_reg_valid
)
5679 as_warn (_("No .frame pseudo-op used in PIC code"));
5680 /* Quiet this warning. */
5681 mips_frame_reg_valid
= 1;
5683 if (! mips_cprestore_valid
)
5685 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5686 /* Quiet this warning. */
5687 mips_cprestore_valid
= 1;
5689 if (mips_opts
.noreorder
)
5690 macro_build (NULL
, "nop", "");
5691 expr1
.X_add_number
= mips_cprestore_offset
;
5692 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5695 HAVE_64BIT_ADDRESSES
);
5721 /* Itbl support may require additional care here. */
5726 /* Itbl support may require additional care here. */
5731 /* Itbl support may require additional care here. */
5736 /* Itbl support may require additional care here. */
5748 if (mips_opts
.arch
== CPU_R4650
)
5750 as_bad (_("opcode not supported on this processor"));
5754 /* Itbl support may require additional care here. */
5759 /* Itbl support may require additional care here. */
5764 /* Itbl support may require additional care here. */
5784 if (breg
== treg
|| coproc
|| lr
)
5805 /* Itbl support may require additional care here. */
5810 /* Itbl support may require additional care here. */
5815 /* Itbl support may require additional care here. */
5820 /* Itbl support may require additional care here. */
5836 if (mips_opts
.arch
== CPU_R4650
)
5838 as_bad (_("opcode not supported on this processor"));
5843 /* Itbl support may require additional care here. */
5847 /* Itbl support may require additional care here. */
5852 /* Itbl support may require additional care here. */
5864 /* Itbl support may require additional care here. */
5865 if (mask
== M_LWC1_AB
5866 || mask
== M_SWC1_AB
5867 || mask
== M_LDC1_AB
5868 || mask
== M_SDC1_AB
5877 if (offset_expr
.X_op
!= O_constant
5878 && offset_expr
.X_op
!= O_symbol
)
5880 as_bad (_("expression too complex"));
5881 offset_expr
.X_op
= O_constant
;
5884 /* A constant expression in PIC code can be handled just as it
5885 is in non PIC code. */
5886 if (offset_expr
.X_op
== O_constant
)
5888 if (HAVE_32BIT_ADDRESSES
5889 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5890 as_bad (_("constant too large"));
5892 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5893 & ~(bfd_vma
) 0xffff);
5894 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5896 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5897 tempreg
, tempreg
, breg
);
5898 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5900 else if (mips_pic
== NO_PIC
)
5902 /* If this is a reference to a GP relative symbol, and there
5903 is no base register, we want
5904 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5905 Otherwise, if there is no base register, we want
5906 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5907 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5908 If we have a constant, we need two instructions anyhow,
5909 so we always use the latter form.
5911 If we have a base register, and this is a reference to a
5912 GP relative symbol, we want
5913 addu $tempreg,$breg,$gp
5914 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5916 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5917 addu $tempreg,$tempreg,$breg
5918 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5919 With a constant we always use the latter case.
5921 With 64bit address space and no base register and $at usable,
5923 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5924 lui $at,<sym> (BFD_RELOC_HI16_S)
5925 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5928 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5929 If we have a base register, we want
5930 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5931 lui $at,<sym> (BFD_RELOC_HI16_S)
5932 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5936 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5938 Without $at we can't generate the optimal path for superscalar
5939 processors here since this would require two temporary registers.
5940 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5941 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5943 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5945 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5946 If we have a base register, we want
5947 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5948 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5950 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5952 daddu $tempreg,$tempreg,$breg
5953 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5955 For GP relative symbols in 64bit address space we can use
5956 the same sequence as in 32bit address space. */
5957 if (HAVE_64BIT_SYMBOLS
)
5959 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5960 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5962 relax_start (offset_expr
.X_add_symbol
);
5965 macro_build (&offset_expr
, s
, fmt
, treg
,
5966 BFD_RELOC_GPREL16
, mips_gp_register
);
5970 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5971 tempreg
, breg
, mips_gp_register
);
5972 macro_build (&offset_expr
, s
, fmt
, treg
,
5973 BFD_RELOC_GPREL16
, tempreg
);
5978 if (used_at
== 0 && !mips_opts
.noat
)
5980 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5981 BFD_RELOC_MIPS_HIGHEST
);
5982 macro_build (&offset_expr
, "lui", "t,u", AT
,
5984 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5985 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5987 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5988 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5989 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5990 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5996 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5997 BFD_RELOC_MIPS_HIGHEST
);
5998 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5999 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6000 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6001 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6002 tempreg
, BFD_RELOC_HI16_S
);
6003 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6005 macro_build (NULL
, "daddu", "d,v,t",
6006 tempreg
, tempreg
, breg
);
6007 macro_build (&offset_expr
, s
, fmt
, treg
,
6008 BFD_RELOC_LO16
, tempreg
);
6011 if (mips_relax
.sequence
)
6018 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6019 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6021 relax_start (offset_expr
.X_add_symbol
);
6022 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6026 macro_build_lui (&offset_expr
, tempreg
);
6027 macro_build (&offset_expr
, s
, fmt
, treg
,
6028 BFD_RELOC_LO16
, tempreg
);
6029 if (mips_relax
.sequence
)
6034 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6035 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6037 relax_start (offset_expr
.X_add_symbol
);
6038 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6039 tempreg
, breg
, mips_gp_register
);
6040 macro_build (&offset_expr
, s
, fmt
, treg
,
6041 BFD_RELOC_GPREL16
, tempreg
);
6044 macro_build_lui (&offset_expr
, tempreg
);
6045 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6046 tempreg
, tempreg
, breg
);
6047 macro_build (&offset_expr
, s
, fmt
, treg
,
6048 BFD_RELOC_LO16
, tempreg
);
6049 if (mips_relax
.sequence
)
6053 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6055 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6057 /* If this is a reference to an external symbol, we want
6058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6060 <op> $treg,0($tempreg)
6062 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6064 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6065 <op> $treg,0($tempreg)
6068 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6069 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6071 If there is a base register, we add it to $tempreg before
6072 the <op>. If there is a constant, we stick it in the
6073 <op> instruction. We don't handle constants larger than
6074 16 bits, because we have no way to load the upper 16 bits
6075 (actually, we could handle them for the subset of cases
6076 in which we are not using $at). */
6077 assert (offset_expr
.X_op
== O_symbol
);
6080 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6081 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6083 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6084 tempreg
, tempreg
, breg
);
6085 macro_build (&offset_expr
, s
, fmt
, treg
,
6086 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6089 expr1
.X_add_number
= offset_expr
.X_add_number
;
6090 offset_expr
.X_add_number
= 0;
6091 if (expr1
.X_add_number
< -0x8000
6092 || expr1
.X_add_number
>= 0x8000)
6093 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6094 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6095 lw_reloc_type
, mips_gp_register
);
6097 relax_start (offset_expr
.X_add_symbol
);
6099 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6100 tempreg
, BFD_RELOC_LO16
);
6103 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6104 tempreg
, tempreg
, breg
);
6105 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6107 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6111 /* If this is a reference to an external symbol, we want
6112 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6113 addu $tempreg,$tempreg,$gp
6114 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6115 <op> $treg,0($tempreg)
6117 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6119 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6120 <op> $treg,0($tempreg)
6121 If there is a base register, we add it to $tempreg before
6122 the <op>. If there is a constant, we stick it in the
6123 <op> instruction. We don't handle constants larger than
6124 16 bits, because we have no way to load the upper 16 bits
6125 (actually, we could handle them for the subset of cases
6126 in which we are not using $at). */
6127 assert (offset_expr
.X_op
== O_symbol
);
6128 expr1
.X_add_number
= offset_expr
.X_add_number
;
6129 offset_expr
.X_add_number
= 0;
6130 if (expr1
.X_add_number
< -0x8000
6131 || expr1
.X_add_number
>= 0x8000)
6132 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6133 gpdelay
= reg_needs_delay (mips_gp_register
);
6134 relax_start (offset_expr
.X_add_symbol
);
6135 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6136 BFD_RELOC_MIPS_GOT_HI16
);
6137 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6139 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6140 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6143 macro_build (NULL
, "nop", "");
6144 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6145 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6147 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6148 tempreg
, BFD_RELOC_LO16
);
6152 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6153 tempreg
, tempreg
, breg
);
6154 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6156 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6158 /* If this is a reference to an external symbol, we want
6159 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6160 add $tempreg,$tempreg,$gp
6161 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6162 <op> $treg,<ofst>($tempreg)
6163 Otherwise, for local symbols, we want:
6164 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6165 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6166 assert (offset_expr
.X_op
== O_symbol
);
6167 expr1
.X_add_number
= offset_expr
.X_add_number
;
6168 offset_expr
.X_add_number
= 0;
6169 if (expr1
.X_add_number
< -0x8000
6170 || expr1
.X_add_number
>= 0x8000)
6171 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6172 relax_start (offset_expr
.X_add_symbol
);
6173 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6174 BFD_RELOC_MIPS_GOT_HI16
);
6175 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6177 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6178 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6180 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6181 tempreg
, tempreg
, breg
);
6182 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6185 offset_expr
.X_add_number
= expr1
.X_add_number
;
6186 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6187 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6189 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6190 tempreg
, tempreg
, breg
);
6191 macro_build (&offset_expr
, s
, fmt
, treg
,
6192 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6202 load_register (treg
, &imm_expr
, 0);
6206 load_register (treg
, &imm_expr
, 1);
6210 if (imm_expr
.X_op
== O_constant
)
6213 load_register (AT
, &imm_expr
, 0);
6214 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6219 assert (offset_expr
.X_op
== O_symbol
6220 && strcmp (segment_name (S_GET_SEGMENT
6221 (offset_expr
.X_add_symbol
)),
6223 && offset_expr
.X_add_number
== 0);
6224 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6225 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6230 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6231 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6232 order 32 bits of the value and the low order 32 bits are either
6233 zero or in OFFSET_EXPR. */
6234 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6236 if (HAVE_64BIT_GPRS
)
6237 load_register (treg
, &imm_expr
, 1);
6242 if (target_big_endian
)
6254 load_register (hreg
, &imm_expr
, 0);
6257 if (offset_expr
.X_op
== O_absent
)
6258 move_register (lreg
, 0);
6261 assert (offset_expr
.X_op
== O_constant
);
6262 load_register (lreg
, &offset_expr
, 0);
6269 /* We know that sym is in the .rdata section. First we get the
6270 upper 16 bits of the address. */
6271 if (mips_pic
== NO_PIC
)
6273 macro_build_lui (&offset_expr
, AT
);
6276 else if (mips_pic
== SVR4_PIC
)
6278 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6279 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6285 /* Now we load the register(s). */
6286 if (HAVE_64BIT_GPRS
)
6289 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6294 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6297 /* FIXME: How in the world do we deal with the possible
6299 offset_expr
.X_add_number
+= 4;
6300 macro_build (&offset_expr
, "lw", "t,o(b)",
6301 treg
+ 1, BFD_RELOC_LO16
, AT
);
6307 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6308 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6309 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6310 the value and the low order 32 bits are either zero or in
6312 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6315 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6316 if (HAVE_64BIT_FPRS
)
6318 assert (HAVE_64BIT_GPRS
);
6319 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6323 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6324 if (offset_expr
.X_op
== O_absent
)
6325 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6328 assert (offset_expr
.X_op
== O_constant
);
6329 load_register (AT
, &offset_expr
, 0);
6330 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6336 assert (offset_expr
.X_op
== O_symbol
6337 && offset_expr
.X_add_number
== 0);
6338 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6339 if (strcmp (s
, ".lit8") == 0)
6341 if (mips_opts
.isa
!= ISA_MIPS1
)
6343 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6344 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6347 breg
= mips_gp_register
;
6348 r
= BFD_RELOC_MIPS_LITERAL
;
6353 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6355 if (mips_pic
== SVR4_PIC
)
6356 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6357 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6360 /* FIXME: This won't work for a 64 bit address. */
6361 macro_build_lui (&offset_expr
, AT
);
6364 if (mips_opts
.isa
!= ISA_MIPS1
)
6366 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6367 treg
, BFD_RELOC_LO16
, AT
);
6376 if (mips_opts
.arch
== CPU_R4650
)
6378 as_bad (_("opcode not supported on this processor"));
6381 /* Even on a big endian machine $fn comes before $fn+1. We have
6382 to adjust when loading from memory. */
6385 assert (mips_opts
.isa
== ISA_MIPS1
);
6386 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6387 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6388 /* FIXME: A possible overflow which I don't know how to deal
6390 offset_expr
.X_add_number
+= 4;
6391 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6392 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6397 * The MIPS assembler seems to check for X_add_number not
6398 * being double aligned and generating:
6401 * addiu at,at,%lo(foo+1)
6404 * But, the resulting address is the same after relocation so why
6405 * generate the extra instruction?
6407 if (mips_opts
.arch
== CPU_R4650
)
6409 as_bad (_("opcode not supported on this processor"));
6412 /* Itbl support may require additional care here. */
6414 if (mips_opts
.isa
!= ISA_MIPS1
)
6425 if (mips_opts
.arch
== CPU_R4650
)
6427 as_bad (_("opcode not supported on this processor"));
6431 if (mips_opts
.isa
!= ISA_MIPS1
)
6439 /* Itbl support may require additional care here. */
6444 if (HAVE_64BIT_GPRS
)
6455 if (HAVE_64BIT_GPRS
)
6465 if (offset_expr
.X_op
!= O_symbol
6466 && offset_expr
.X_op
!= O_constant
)
6468 as_bad (_("expression too complex"));
6469 offset_expr
.X_op
= O_constant
;
6472 /* Even on a big endian machine $fn comes before $fn+1. We have
6473 to adjust when loading from memory. We set coproc if we must
6474 load $fn+1 first. */
6475 /* Itbl support may require additional care here. */
6476 if (! target_big_endian
)
6479 if (mips_pic
== NO_PIC
6480 || offset_expr
.X_op
== O_constant
)
6482 /* If this is a reference to a GP relative symbol, we want
6483 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6484 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6485 If we have a base register, we use this
6487 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6488 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6489 If this is not a GP relative symbol, we want
6490 lui $at,<sym> (BFD_RELOC_HI16_S)
6491 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6492 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6493 If there is a base register, we add it to $at after the
6494 lui instruction. If there is a constant, we always use
6496 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6497 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6499 relax_start (offset_expr
.X_add_symbol
);
6502 tempreg
= mips_gp_register
;
6506 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6507 AT
, breg
, mips_gp_register
);
6512 /* Itbl support may require additional care here. */
6513 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6514 BFD_RELOC_GPREL16
, tempreg
);
6515 offset_expr
.X_add_number
+= 4;
6517 /* Set mips_optimize to 2 to avoid inserting an
6519 hold_mips_optimize
= mips_optimize
;
6521 /* Itbl support may require additional care here. */
6522 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6523 BFD_RELOC_GPREL16
, tempreg
);
6524 mips_optimize
= hold_mips_optimize
;
6528 /* We just generated two relocs. When tc_gen_reloc
6529 handles this case, it will skip the first reloc and
6530 handle the second. The second reloc already has an
6531 extra addend of 4, which we added above. We must
6532 subtract it out, and then subtract another 4 to make
6533 the first reloc come out right. The second reloc
6534 will come out right because we are going to add 4 to
6535 offset_expr when we build its instruction below.
6537 If we have a symbol, then we don't want to include
6538 the offset, because it will wind up being included
6539 when we generate the reloc. */
6541 if (offset_expr
.X_op
== O_constant
)
6542 offset_expr
.X_add_number
-= 8;
6545 offset_expr
.X_add_number
= -4;
6546 offset_expr
.X_op
= O_constant
;
6550 macro_build_lui (&offset_expr
, AT
);
6552 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6553 /* Itbl support may require additional care here. */
6554 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6555 BFD_RELOC_LO16
, AT
);
6556 /* FIXME: How do we handle overflow here? */
6557 offset_expr
.X_add_number
+= 4;
6558 /* Itbl support may require additional care here. */
6559 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6560 BFD_RELOC_LO16
, AT
);
6561 if (mips_relax
.sequence
)
6564 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6566 /* If this is a reference to an external symbol, we want
6567 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6572 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6574 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6575 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6576 If there is a base register we add it to $at before the
6577 lwc1 instructions. If there is a constant we include it
6578 in the lwc1 instructions. */
6580 expr1
.X_add_number
= offset_expr
.X_add_number
;
6581 if (expr1
.X_add_number
< -0x8000
6582 || expr1
.X_add_number
>= 0x8000 - 4)
6583 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6584 load_got_offset (AT
, &offset_expr
);
6587 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6589 /* Set mips_optimize to 2 to avoid inserting an undesired
6591 hold_mips_optimize
= mips_optimize
;
6594 /* Itbl support may require additional care here. */
6595 relax_start (offset_expr
.X_add_symbol
);
6596 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6597 BFD_RELOC_LO16
, AT
);
6598 expr1
.X_add_number
+= 4;
6599 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6600 BFD_RELOC_LO16
, AT
);
6602 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6603 BFD_RELOC_LO16
, AT
);
6604 offset_expr
.X_add_number
+= 4;
6605 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6606 BFD_RELOC_LO16
, AT
);
6609 mips_optimize
= hold_mips_optimize
;
6611 else if (mips_pic
== SVR4_PIC
)
6615 /* If this is a reference to an external symbol, we want
6616 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6618 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6623 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6625 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6626 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6627 If there is a base register we add it to $at before the
6628 lwc1 instructions. If there is a constant we include it
6629 in the lwc1 instructions. */
6631 expr1
.X_add_number
= offset_expr
.X_add_number
;
6632 offset_expr
.X_add_number
= 0;
6633 if (expr1
.X_add_number
< -0x8000
6634 || expr1
.X_add_number
>= 0x8000 - 4)
6635 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6636 gpdelay
= reg_needs_delay (mips_gp_register
);
6637 relax_start (offset_expr
.X_add_symbol
);
6638 macro_build (&offset_expr
, "lui", "t,u",
6639 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6640 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6641 AT
, AT
, mips_gp_register
);
6642 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6643 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6646 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6647 /* Itbl support may require additional care here. */
6648 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6649 BFD_RELOC_LO16
, AT
);
6650 expr1
.X_add_number
+= 4;
6652 /* Set mips_optimize to 2 to avoid inserting an undesired
6654 hold_mips_optimize
= mips_optimize
;
6656 /* Itbl support may require additional care here. */
6657 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6658 BFD_RELOC_LO16
, AT
);
6659 mips_optimize
= hold_mips_optimize
;
6660 expr1
.X_add_number
-= 4;
6663 offset_expr
.X_add_number
= expr1
.X_add_number
;
6665 macro_build (NULL
, "nop", "");
6666 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6667 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6670 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6671 /* Itbl support may require additional care here. */
6672 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6673 BFD_RELOC_LO16
, AT
);
6674 offset_expr
.X_add_number
+= 4;
6676 /* Set mips_optimize to 2 to avoid inserting an undesired
6678 hold_mips_optimize
= mips_optimize
;
6680 /* Itbl support may require additional care here. */
6681 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6682 BFD_RELOC_LO16
, AT
);
6683 mips_optimize
= hold_mips_optimize
;
6697 assert (HAVE_32BIT_ADDRESSES
);
6698 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6699 offset_expr
.X_add_number
+= 4;
6700 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6703 /* New code added to support COPZ instructions.
6704 This code builds table entries out of the macros in mip_opcodes.
6705 R4000 uses interlocks to handle coproc delays.
6706 Other chips (like the R3000) require nops to be inserted for delays.
6708 FIXME: Currently, we require that the user handle delays.
6709 In order to fill delay slots for non-interlocked chips,
6710 we must have a way to specify delays based on the coprocessor.
6711 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6712 What are the side-effects of the cop instruction?
6713 What cache support might we have and what are its effects?
6714 Both coprocessor & memory require delays. how long???
6715 What registers are read/set/modified?
6717 If an itbl is provided to interpret cop instructions,
6718 this knowledge can be encoded in the itbl spec. */
6732 /* For now we just do C (same as Cz). The parameter will be
6733 stored in insn_opcode by mips_ip. */
6734 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6738 move_register (dreg
, sreg
);
6741 #ifdef LOSING_COMPILER
6743 /* Try and see if this is a new itbl instruction.
6744 This code builds table entries out of the macros in mip_opcodes.
6745 FIXME: For now we just assemble the expression and pass it's
6746 value along as a 32-bit immediate.
6747 We may want to have the assembler assemble this value,
6748 so that we gain the assembler's knowledge of delay slots,
6750 Would it be more efficient to use mask (id) here? */
6751 if (itbl_have_entries
6752 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6754 s
= ip
->insn_mo
->name
;
6756 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6757 macro_build (&immed_expr
, s
, "C");
6763 if (mips_opts
.noat
&& used_at
)
6764 as_bad (_("Macro used $at after \".set noat\""));
6768 macro2 (struct mips_cl_insn
*ip
)
6770 register int treg
, sreg
, dreg
, breg
;
6785 bfd_reloc_code_real_type r
;
6787 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6788 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6789 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6790 mask
= ip
->insn_mo
->mask
;
6792 expr1
.X_op
= O_constant
;
6793 expr1
.X_op_symbol
= NULL
;
6794 expr1
.X_add_symbol
= NULL
;
6795 expr1
.X_add_number
= 1;
6799 #endif /* LOSING_COMPILER */
6804 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6805 macro_build (NULL
, "mflo", "d", dreg
);
6811 /* The MIPS assembler some times generates shifts and adds. I'm
6812 not trying to be that fancy. GCC should do this for us
6815 load_register (AT
, &imm_expr
, dbl
);
6816 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6817 macro_build (NULL
, "mflo", "d", dreg
);
6830 mips_emit_delays (TRUE
);
6831 ++mips_opts
.noreorder
;
6832 mips_any_noreorder
= 1;
6835 load_register (AT
, &imm_expr
, dbl
);
6836 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6837 macro_build (NULL
, "mflo", "d", dreg
);
6838 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6839 macro_build (NULL
, "mfhi", "d", AT
);
6841 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6844 expr1
.X_add_number
= 8;
6845 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6846 macro_build (NULL
, "nop", "", 0);
6847 macro_build (NULL
, "break", "c", 6);
6849 --mips_opts
.noreorder
;
6850 macro_build (NULL
, "mflo", "d", dreg
);
6863 mips_emit_delays (TRUE
);
6864 ++mips_opts
.noreorder
;
6865 mips_any_noreorder
= 1;
6868 load_register (AT
, &imm_expr
, dbl
);
6869 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6870 sreg
, imm
? AT
: treg
);
6871 macro_build (NULL
, "mfhi", "d", AT
);
6872 macro_build (NULL
, "mflo", "d", dreg
);
6874 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6877 expr1
.X_add_number
= 8;
6878 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6879 macro_build (NULL
, "nop", "", 0);
6880 macro_build (NULL
, "break", "c", 6);
6882 --mips_opts
.noreorder
;
6886 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6897 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6898 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6902 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6903 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6904 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6905 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6909 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6920 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6921 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6925 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6926 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6927 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6928 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6936 if (imm_expr
.X_op
!= O_constant
)
6937 as_bad (_("Improper rotate count"));
6938 rot
= imm_expr
.X_add_number
& 0x3f;
6939 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6941 rot
= (64 - rot
) & 0x3f;
6943 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6945 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6950 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6953 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6954 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6957 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6958 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6959 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6967 if (imm_expr
.X_op
!= O_constant
)
6968 as_bad (_("Improper rotate count"));
6969 rot
= imm_expr
.X_add_number
& 0x1f;
6970 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6972 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6977 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6981 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6982 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6983 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6988 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6990 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6994 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6995 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6996 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6997 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7001 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7003 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7007 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7008 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7009 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7010 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7018 if (imm_expr
.X_op
!= O_constant
)
7019 as_bad (_("Improper rotate count"));
7020 rot
= imm_expr
.X_add_number
& 0x3f;
7021 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7024 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7026 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7031 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7034 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7035 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7038 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7039 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7040 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7048 if (imm_expr
.X_op
!= O_constant
)
7049 as_bad (_("Improper rotate count"));
7050 rot
= imm_expr
.X_add_number
& 0x1f;
7051 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7053 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7058 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7062 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7063 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7064 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7069 if (mips_opts
.arch
== CPU_R4650
)
7071 as_bad (_("opcode not supported on this processor"));
7074 assert (mips_opts
.isa
== ISA_MIPS1
);
7075 /* Even on a big endian machine $fn comes before $fn+1. We have
7076 to adjust when storing to memory. */
7077 macro_build (&offset_expr
, "swc1", "T,o(b)",
7078 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7079 offset_expr
.X_add_number
+= 4;
7080 macro_build (&offset_expr
, "swc1", "T,o(b)",
7081 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7086 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7088 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7091 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7092 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7097 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7099 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7104 as_warn (_("Instruction %s: result is always false"),
7106 move_register (dreg
, 0);
7109 if (imm_expr
.X_op
== O_constant
7110 && imm_expr
.X_add_number
>= 0
7111 && imm_expr
.X_add_number
< 0x10000)
7113 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7115 else if (imm_expr
.X_op
== O_constant
7116 && imm_expr
.X_add_number
> -0x8000
7117 && imm_expr
.X_add_number
< 0)
7119 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7120 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7121 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7125 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7126 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7129 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7132 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7138 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7139 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7142 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7144 if (imm_expr
.X_op
== O_constant
7145 && imm_expr
.X_add_number
>= -0x8000
7146 && imm_expr
.X_add_number
< 0x8000)
7148 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7149 dreg
, sreg
, BFD_RELOC_LO16
);
7153 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7154 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7158 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7161 case M_SGT
: /* sreg > treg <==> treg < sreg */
7167 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7170 case M_SGT_I
: /* sreg > I <==> I < sreg */
7177 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7178 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7181 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7187 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7188 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7191 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7198 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7199 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7200 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7204 if (imm_expr
.X_op
== O_constant
7205 && imm_expr
.X_add_number
>= -0x8000
7206 && imm_expr
.X_add_number
< 0x8000)
7208 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7212 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7213 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7217 if (imm_expr
.X_op
== O_constant
7218 && imm_expr
.X_add_number
>= -0x8000
7219 && imm_expr
.X_add_number
< 0x8000)
7221 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7226 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7227 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7232 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7234 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7237 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7238 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7243 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7245 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7250 as_warn (_("Instruction %s: result is always true"),
7252 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7253 dreg
, 0, BFD_RELOC_LO16
);
7256 if (imm_expr
.X_op
== O_constant
7257 && imm_expr
.X_add_number
>= 0
7258 && imm_expr
.X_add_number
< 0x10000)
7260 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7262 else if (imm_expr
.X_op
== O_constant
7263 && imm_expr
.X_add_number
> -0x8000
7264 && imm_expr
.X_add_number
< 0)
7266 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7267 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7268 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7272 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7273 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7276 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7282 if (imm_expr
.X_op
== O_constant
7283 && imm_expr
.X_add_number
> -0x8000
7284 && imm_expr
.X_add_number
<= 0x8000)
7286 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7287 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7288 dreg
, sreg
, BFD_RELOC_LO16
);
7292 load_register (AT
, &imm_expr
, dbl
);
7293 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7299 if (imm_expr
.X_op
== O_constant
7300 && imm_expr
.X_add_number
> -0x8000
7301 && imm_expr
.X_add_number
<= 0x8000)
7303 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7304 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7305 dreg
, sreg
, BFD_RELOC_LO16
);
7309 load_register (AT
, &imm_expr
, dbl
);
7310 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7332 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7333 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7338 assert (mips_opts
.isa
== ISA_MIPS1
);
7340 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7341 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7344 * Is the double cfc1 instruction a bug in the mips assembler;
7345 * or is there a reason for it?
7347 mips_emit_delays (TRUE
);
7348 ++mips_opts
.noreorder
;
7349 mips_any_noreorder
= 1;
7350 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7351 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7352 macro_build (NULL
, "nop", "");
7353 expr1
.X_add_number
= 3;
7354 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7355 expr1
.X_add_number
= 2;
7356 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7357 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7358 macro_build (NULL
, "nop", "");
7359 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7361 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7362 macro_build (NULL
, "nop", "");
7363 --mips_opts
.noreorder
;
7373 if (offset_expr
.X_add_number
>= 0x7fff)
7374 as_bad (_("operand overflow"));
7375 if (! target_big_endian
)
7376 ++offset_expr
.X_add_number
;
7377 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7378 if (! target_big_endian
)
7379 --offset_expr
.X_add_number
;
7381 ++offset_expr
.X_add_number
;
7382 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7383 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7384 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7397 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7398 as_bad (_("operand overflow"));
7406 if (! target_big_endian
)
7407 offset_expr
.X_add_number
+= off
;
7408 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7409 if (! target_big_endian
)
7410 offset_expr
.X_add_number
-= off
;
7412 offset_expr
.X_add_number
+= off
;
7413 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7415 /* If necessary, move the result in tempreg the final destination. */
7416 if (treg
== tempreg
)
7418 /* Protect second load's delay slot. */
7420 move_register (treg
, tempreg
);
7434 load_address (AT
, &offset_expr
, &used_at
);
7436 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7437 if (! target_big_endian
)
7438 expr1
.X_add_number
= off
;
7440 expr1
.X_add_number
= 0;
7441 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7442 if (! target_big_endian
)
7443 expr1
.X_add_number
= 0;
7445 expr1
.X_add_number
= off
;
7446 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7452 load_address (AT
, &offset_expr
, &used_at
);
7454 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7455 if (target_big_endian
)
7456 expr1
.X_add_number
= 0;
7457 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7458 treg
, BFD_RELOC_LO16
, AT
);
7459 if (target_big_endian
)
7460 expr1
.X_add_number
= 1;
7462 expr1
.X_add_number
= 0;
7463 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7464 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7465 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7470 if (offset_expr
.X_add_number
>= 0x7fff)
7471 as_bad (_("operand overflow"));
7472 if (target_big_endian
)
7473 ++offset_expr
.X_add_number
;
7474 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7475 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7476 if (target_big_endian
)
7477 --offset_expr
.X_add_number
;
7479 ++offset_expr
.X_add_number
;
7480 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7493 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7494 as_bad (_("operand overflow"));
7495 if (! target_big_endian
)
7496 offset_expr
.X_add_number
+= off
;
7497 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7498 if (! target_big_endian
)
7499 offset_expr
.X_add_number
-= off
;
7501 offset_expr
.X_add_number
+= off
;
7502 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7516 load_address (AT
, &offset_expr
, &used_at
);
7518 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7519 if (! target_big_endian
)
7520 expr1
.X_add_number
= off
;
7522 expr1
.X_add_number
= 0;
7523 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7524 if (! target_big_endian
)
7525 expr1
.X_add_number
= 0;
7527 expr1
.X_add_number
= off
;
7528 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7533 load_address (AT
, &offset_expr
, &used_at
);
7535 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7536 if (! target_big_endian
)
7537 expr1
.X_add_number
= 0;
7538 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7539 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7540 if (! target_big_endian
)
7541 expr1
.X_add_number
= 1;
7543 expr1
.X_add_number
= 0;
7544 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7545 if (! target_big_endian
)
7546 expr1
.X_add_number
= 0;
7548 expr1
.X_add_number
= 1;
7549 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7550 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7551 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7555 /* FIXME: Check if this is one of the itbl macros, since they
7556 are added dynamically. */
7557 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7560 if (mips_opts
.noat
&& used_at
)
7561 as_bad (_("Macro used $at after \".set noat\""));
7564 /* Implement macros in mips16 mode. */
7567 mips16_macro (struct mips_cl_insn
*ip
)
7570 int xreg
, yreg
, zreg
, tmp
;
7573 const char *s
, *s2
, *s3
;
7575 mask
= ip
->insn_mo
->mask
;
7577 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7578 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7579 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7581 expr1
.X_op
= O_constant
;
7582 expr1
.X_op_symbol
= NULL
;
7583 expr1
.X_add_symbol
= NULL
;
7584 expr1
.X_add_number
= 1;
7603 mips_emit_delays (TRUE
);
7604 ++mips_opts
.noreorder
;
7605 mips_any_noreorder
= 1;
7606 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7607 expr1
.X_add_number
= 2;
7608 macro_build (&expr1
, "bnez", "x,p", yreg
);
7609 macro_build (NULL
, "break", "6", 7);
7611 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7612 since that causes an overflow. We should do that as well,
7613 but I don't see how to do the comparisons without a temporary
7615 --mips_opts
.noreorder
;
7616 macro_build (NULL
, s
, "x", zreg
);
7635 mips_emit_delays (TRUE
);
7636 ++mips_opts
.noreorder
;
7637 mips_any_noreorder
= 1;
7638 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7639 expr1
.X_add_number
= 2;
7640 macro_build (&expr1
, "bnez", "x,p", yreg
);
7641 macro_build (NULL
, "break", "6", 7);
7642 --mips_opts
.noreorder
;
7643 macro_build (NULL
, s2
, "x", zreg
);
7649 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7650 macro_build (NULL
, "mflo", "x", zreg
);
7658 if (imm_expr
.X_op
!= O_constant
)
7659 as_bad (_("Unsupported large constant"));
7660 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7661 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7665 if (imm_expr
.X_op
!= O_constant
)
7666 as_bad (_("Unsupported large constant"));
7667 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7668 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7672 if (imm_expr
.X_op
!= O_constant
)
7673 as_bad (_("Unsupported large constant"));
7674 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7675 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7697 goto do_reverse_branch
;
7701 goto do_reverse_branch
;
7713 goto do_reverse_branch
;
7724 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7725 macro_build (&offset_expr
, s2
, "p");
7752 goto do_addone_branch_i
;
7757 goto do_addone_branch_i
;
7772 goto do_addone_branch_i
;
7779 if (imm_expr
.X_op
!= O_constant
)
7780 as_bad (_("Unsupported large constant"));
7781 ++imm_expr
.X_add_number
;
7784 macro_build (&imm_expr
, s
, s3
, xreg
);
7785 macro_build (&offset_expr
, s2
, "p");
7789 expr1
.X_add_number
= 0;
7790 macro_build (&expr1
, "slti", "x,8", yreg
);
7792 move_register (xreg
, yreg
);
7793 expr1
.X_add_number
= 2;
7794 macro_build (&expr1
, "bteqz", "p");
7795 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7799 /* For consistency checking, verify that all bits are specified either
7800 by the match/mask part of the instruction definition, or by the
7803 validate_mips_insn (const struct mips_opcode
*opc
)
7805 const char *p
= opc
->args
;
7807 unsigned long used_bits
= opc
->mask
;
7809 if ((used_bits
& opc
->match
) != opc
->match
)
7811 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7812 opc
->name
, opc
->args
);
7815 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7825 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7826 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7827 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7828 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7829 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7830 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7831 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7832 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7833 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7836 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7837 c
, opc
->name
, opc
->args
);
7841 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7842 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7844 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7845 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7846 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7847 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7849 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7850 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7852 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7853 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7855 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7856 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7857 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7858 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7859 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7860 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7861 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7862 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7863 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7864 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7865 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7866 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7867 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7868 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7869 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7870 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7871 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7873 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7874 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7875 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7876 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7878 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7879 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7880 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7881 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7882 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7883 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7884 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7885 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7886 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7889 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7890 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7891 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7892 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7893 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7897 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7898 c
, opc
->name
, opc
->args
);
7902 if (used_bits
!= 0xffffffff)
7904 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7905 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7911 /* This routine assembles an instruction into its binary format. As a
7912 side effect, it sets one of the global variables imm_reloc or
7913 offset_reloc to the type of relocation to do if one of the operands
7914 is an address expression. */
7917 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7922 struct mips_opcode
*insn
;
7925 unsigned int lastregno
= 0;
7926 unsigned int lastpos
= 0;
7927 unsigned int limlo
, limhi
;
7933 /* If the instruction contains a '.', we first try to match an instruction
7934 including the '.'. Then we try again without the '.'. */
7936 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7939 /* If we stopped on whitespace, then replace the whitespace with null for
7940 the call to hash_find. Save the character we replaced just in case we
7941 have to re-parse the instruction. */
7948 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7950 /* If we didn't find the instruction in the opcode table, try again, but
7951 this time with just the instruction up to, but not including the
7955 /* Restore the character we overwrite above (if any). */
7959 /* Scan up to the first '.' or whitespace. */
7961 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7965 /* If we did not find a '.', then we can quit now. */
7968 insn_error
= "unrecognized opcode";
7972 /* Lookup the instruction in the hash table. */
7974 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7976 insn_error
= "unrecognized opcode";
7986 assert (strcmp (insn
->name
, str
) == 0);
7988 if (OPCODE_IS_MEMBER (insn
,
7990 | (file_ase_mips16
? INSN_MIPS16
: 0)
7991 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7992 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7998 if (insn
->pinfo
!= INSN_MACRO
)
8000 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8006 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8007 && strcmp (insn
->name
, insn
[1].name
) == 0)
8016 static char buf
[100];
8018 _("opcode not supported on this processor: %s (%s)"),
8019 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8020 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8030 ip
->insn_opcode
= insn
->match
;
8032 for (args
= insn
->args
;; ++args
)
8036 s
+= strspn (s
, " \t");
8040 case '\0': /* end of args */
8053 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8057 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8061 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8065 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8071 /* Handle optional base register.
8072 Either the base register is omitted or
8073 we must have a left paren. */
8074 /* This is dependent on the next operand specifier
8075 is a base register specification. */
8076 assert (args
[1] == 'b' || args
[1] == '5'
8077 || args
[1] == '-' || args
[1] == '4');
8081 case ')': /* these must match exactly */
8088 case '+': /* Opcode extension character. */
8091 case 'A': /* ins/ext position, becomes LSB. */
8100 my_getExpression (&imm_expr
, s
);
8101 check_absolute_expr (ip
, &imm_expr
);
8102 if ((unsigned long) imm_expr
.X_add_number
< limlo
8103 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8105 as_bad (_("Improper position (%lu)"),
8106 (unsigned long) imm_expr
.X_add_number
);
8107 imm_expr
.X_add_number
= limlo
;
8109 lastpos
= imm_expr
.X_add_number
;
8110 ip
->insn_opcode
|= (imm_expr
.X_add_number
8111 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8112 imm_expr
.X_op
= O_absent
;
8116 case 'B': /* ins size, becomes MSB. */
8125 my_getExpression (&imm_expr
, s
);
8126 check_absolute_expr (ip
, &imm_expr
);
8127 /* Check for negative input so that small negative numbers
8128 will not succeed incorrectly. The checks against
8129 (pos+size) transitively check "size" itself,
8130 assuming that "pos" is reasonable. */
8131 if ((long) imm_expr
.X_add_number
< 0
8132 || ((unsigned long) imm_expr
.X_add_number
8134 || ((unsigned long) imm_expr
.X_add_number
8137 as_bad (_("Improper insert size (%lu, position %lu)"),
8138 (unsigned long) imm_expr
.X_add_number
,
8139 (unsigned long) lastpos
);
8140 imm_expr
.X_add_number
= limlo
- lastpos
;
8142 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8143 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8144 imm_expr
.X_op
= O_absent
;
8148 case 'C': /* ext size, becomes MSBD. */
8161 my_getExpression (&imm_expr
, s
);
8162 check_absolute_expr (ip
, &imm_expr
);
8163 /* Check for negative input so that small negative numbers
8164 will not succeed incorrectly. The checks against
8165 (pos+size) transitively check "size" itself,
8166 assuming that "pos" is reasonable. */
8167 if ((long) imm_expr
.X_add_number
< 0
8168 || ((unsigned long) imm_expr
.X_add_number
8170 || ((unsigned long) imm_expr
.X_add_number
8173 as_bad (_("Improper extract size (%lu, position %lu)"),
8174 (unsigned long) imm_expr
.X_add_number
,
8175 (unsigned long) lastpos
);
8176 imm_expr
.X_add_number
= limlo
- lastpos
;
8178 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8179 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8180 imm_expr
.X_op
= O_absent
;
8185 /* +D is for disassembly only; never match. */
8189 /* "+I" is like "I", except that imm2_expr is used. */
8190 my_getExpression (&imm2_expr
, s
);
8191 if (imm2_expr
.X_op
!= O_big
8192 && imm2_expr
.X_op
!= O_constant
)
8193 insn_error
= _("absolute expression required");
8194 normalize_constant_expr (&imm2_expr
);
8199 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8200 *args
, insn
->name
, insn
->args
);
8201 /* Further processing is fruitless. */
8206 case '<': /* must be at least one digit */
8208 * According to the manual, if the shift amount is greater
8209 * than 31 or less than 0, then the shift amount should be
8210 * mod 32. In reality the mips assembler issues an error.
8211 * We issue a warning and mask out all but the low 5 bits.
8213 my_getExpression (&imm_expr
, s
);
8214 check_absolute_expr (ip
, &imm_expr
);
8215 if ((unsigned long) imm_expr
.X_add_number
> 31)
8217 as_warn (_("Improper shift amount (%lu)"),
8218 (unsigned long) imm_expr
.X_add_number
);
8219 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8221 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8222 imm_expr
.X_op
= O_absent
;
8226 case '>': /* shift amount minus 32 */
8227 my_getExpression (&imm_expr
, s
);
8228 check_absolute_expr (ip
, &imm_expr
);
8229 if ((unsigned long) imm_expr
.X_add_number
< 32
8230 || (unsigned long) imm_expr
.X_add_number
> 63)
8232 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8233 imm_expr
.X_op
= O_absent
;
8237 case 'k': /* cache code */
8238 case 'h': /* prefx code */
8239 my_getExpression (&imm_expr
, s
);
8240 check_absolute_expr (ip
, &imm_expr
);
8241 if ((unsigned long) imm_expr
.X_add_number
> 31)
8243 as_warn (_("Invalid value for `%s' (%lu)"),
8245 (unsigned long) imm_expr
.X_add_number
);
8246 imm_expr
.X_add_number
&= 0x1f;
8249 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8251 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8252 imm_expr
.X_op
= O_absent
;
8256 case 'c': /* break code */
8257 my_getExpression (&imm_expr
, s
);
8258 check_absolute_expr (ip
, &imm_expr
);
8259 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8261 as_warn (_("Illegal break code (%lu)"),
8262 (unsigned long) imm_expr
.X_add_number
);
8263 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8265 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8266 imm_expr
.X_op
= O_absent
;
8270 case 'q': /* lower break code */
8271 my_getExpression (&imm_expr
, s
);
8272 check_absolute_expr (ip
, &imm_expr
);
8273 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8275 as_warn (_("Illegal lower break code (%lu)"),
8276 (unsigned long) imm_expr
.X_add_number
);
8277 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8279 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8280 imm_expr
.X_op
= O_absent
;
8284 case 'B': /* 20-bit syscall/break code. */
8285 my_getExpression (&imm_expr
, s
);
8286 check_absolute_expr (ip
, &imm_expr
);
8287 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8288 as_warn (_("Illegal 20-bit code (%lu)"),
8289 (unsigned long) imm_expr
.X_add_number
);
8290 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8291 imm_expr
.X_op
= O_absent
;
8295 case 'C': /* Coprocessor code */
8296 my_getExpression (&imm_expr
, s
);
8297 check_absolute_expr (ip
, &imm_expr
);
8298 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8300 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8301 (unsigned long) imm_expr
.X_add_number
);
8302 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8304 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8305 imm_expr
.X_op
= O_absent
;
8309 case 'J': /* 19-bit wait code. */
8310 my_getExpression (&imm_expr
, s
);
8311 check_absolute_expr (ip
, &imm_expr
);
8312 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8313 as_warn (_("Illegal 19-bit code (%lu)"),
8314 (unsigned long) imm_expr
.X_add_number
);
8315 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8316 imm_expr
.X_op
= O_absent
;
8320 case 'P': /* Performance register */
8321 my_getExpression (&imm_expr
, s
);
8322 check_absolute_expr (ip
, &imm_expr
);
8323 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8325 as_warn (_("Invalid performance register (%lu)"),
8326 (unsigned long) imm_expr
.X_add_number
);
8327 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8329 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8330 imm_expr
.X_op
= O_absent
;
8334 case 'b': /* base register */
8335 case 'd': /* destination register */
8336 case 's': /* source register */
8337 case 't': /* target register */
8338 case 'r': /* both target and source */
8339 case 'v': /* both dest and source */
8340 case 'w': /* both dest and target */
8341 case 'E': /* coprocessor target register */
8342 case 'G': /* coprocessor destination register */
8343 case 'K': /* 'rdhwr' destination register */
8344 case 'x': /* ignore register name */
8345 case 'z': /* must be zero register */
8346 case 'U': /* destination register (clo/clz). */
8361 while (ISDIGIT (*s
));
8363 as_bad (_("Invalid register number (%d)"), regno
);
8365 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8369 if (s
[1] == 'r' && s
[2] == 'a')
8374 else if (s
[1] == 'f' && s
[2] == 'p')
8379 else if (s
[1] == 's' && s
[2] == 'p')
8384 else if (s
[1] == 'g' && s
[2] == 'p')
8389 else if (s
[1] == 'a' && s
[2] == 't')
8394 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8399 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8404 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8409 else if (itbl_have_entries
)
8414 p
= s
+ 1; /* advance past '$' */
8415 n
= itbl_get_field (&p
); /* n is name */
8417 /* See if this is a register defined in an
8419 if (itbl_get_reg_val (n
, &r
))
8421 /* Get_field advances to the start of
8422 the next field, so we need to back
8423 rack to the end of the last field. */
8427 s
= strchr (s
, '\0');
8441 as_warn (_("Used $at without \".set noat\""));
8447 if (c
== 'r' || c
== 'v' || c
== 'w')
8454 /* 'z' only matches $0. */
8455 if (c
== 'z' && regno
!= 0)
8458 /* Now that we have assembled one operand, we use the args string
8459 * to figure out where it goes in the instruction. */
8466 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8471 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8474 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8475 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8480 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8483 /* This case exists because on the r3000 trunc
8484 expands into a macro which requires a gp
8485 register. On the r6000 or r4000 it is
8486 assembled into a single instruction which
8487 ignores the register. Thus the insn version
8488 is MIPS_ISA2 and uses 'x', and the macro
8489 version is MIPS_ISA1 and uses 't'. */
8492 /* This case is for the div instruction, which
8493 acts differently if the destination argument
8494 is $0. This only matches $0, and is checked
8495 outside the switch. */
8498 /* Itbl operand; not yet implemented. FIXME ?? */
8500 /* What about all other operands like 'i', which
8501 can be specified in the opcode table? */
8511 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8514 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8519 case 'O': /* MDMX alignment immediate constant. */
8520 my_getExpression (&imm_expr
, s
);
8521 check_absolute_expr (ip
, &imm_expr
);
8522 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8524 as_warn ("Improper align amount (%ld), using low bits",
8525 (long) imm_expr
.X_add_number
);
8526 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8528 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8529 imm_expr
.X_op
= O_absent
;
8533 case 'Q': /* MDMX vector, element sel, or const. */
8536 /* MDMX Immediate. */
8537 my_getExpression (&imm_expr
, s
);
8538 check_absolute_expr (ip
, &imm_expr
);
8539 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8541 as_warn (_("Invalid MDMX Immediate (%ld)"),
8542 (long) imm_expr
.X_add_number
);
8543 imm_expr
.X_add_number
&= OP_MASK_FT
;
8545 imm_expr
.X_add_number
&= OP_MASK_FT
;
8546 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8547 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8549 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8550 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8551 imm_expr
.X_op
= O_absent
;
8555 /* Not MDMX Immediate. Fall through. */
8556 case 'X': /* MDMX destination register. */
8557 case 'Y': /* MDMX source register. */
8558 case 'Z': /* MDMX target register. */
8560 case 'D': /* floating point destination register */
8561 case 'S': /* floating point source register */
8562 case 'T': /* floating point target register */
8563 case 'R': /* floating point source register */
8567 /* Accept $fN for FP and MDMX register numbers, and in
8568 addition accept $vN for MDMX register numbers. */
8569 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8570 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8581 while (ISDIGIT (*s
));
8584 as_bad (_("Invalid float register number (%d)"), regno
);
8586 if ((regno
& 1) != 0
8588 && ! (strcmp (str
, "mtc1") == 0
8589 || strcmp (str
, "mfc1") == 0
8590 || strcmp (str
, "lwc1") == 0
8591 || strcmp (str
, "swc1") == 0
8592 || strcmp (str
, "l.s") == 0
8593 || strcmp (str
, "s.s") == 0))
8594 as_warn (_("Float register should be even, was %d"),
8602 if (c
== 'V' || c
== 'W')
8613 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8618 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8621 /* This is like 'Z', but also needs to fix the MDMX
8622 vector/scalar select bits. Note that the
8623 scalar immediate case is handled above. */
8626 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8627 int max_el
= (is_qh
? 3 : 7);
8629 my_getExpression(&imm_expr
, s
);
8630 check_absolute_expr (ip
, &imm_expr
);
8632 if (imm_expr
.X_add_number
> max_el
)
8633 as_bad(_("Bad element selector %ld"),
8634 (long) imm_expr
.X_add_number
);
8635 imm_expr
.X_add_number
&= max_el
;
8636 ip
->insn_opcode
|= (imm_expr
.X_add_number
8639 imm_expr
.X_op
= O_absent
;
8641 as_warn(_("Expecting ']' found '%s'"), s
);
8647 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8648 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8651 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8658 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8661 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8671 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8674 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8680 my_getExpression (&imm_expr
, s
);
8681 if (imm_expr
.X_op
!= O_big
8682 && imm_expr
.X_op
!= O_constant
)
8683 insn_error
= _("absolute expression required");
8684 normalize_constant_expr (&imm_expr
);
8689 my_getExpression (&offset_expr
, s
);
8690 *imm_reloc
= BFD_RELOC_32
;
8703 unsigned char temp
[8];
8705 unsigned int length
;
8710 /* These only appear as the last operand in an
8711 instruction, and every instruction that accepts
8712 them in any variant accepts them in all variants.
8713 This means we don't have to worry about backing out
8714 any changes if the instruction does not match.
8716 The difference between them is the size of the
8717 floating point constant and where it goes. For 'F'
8718 and 'L' the constant is 64 bits; for 'f' and 'l' it
8719 is 32 bits. Where the constant is placed is based
8720 on how the MIPS assembler does things:
8723 f -- immediate value
8726 The .lit4 and .lit8 sections are only used if
8727 permitted by the -G argument.
8729 The code below needs to know whether the target register
8730 is 32 or 64 bits wide. It relies on the fact 'f' and
8731 'F' are used with GPR-based instructions and 'l' and
8732 'L' are used with FPR-based instructions. */
8734 f64
= *args
== 'F' || *args
== 'L';
8735 using_gprs
= *args
== 'F' || *args
== 'f';
8737 save_in
= input_line_pointer
;
8738 input_line_pointer
= s
;
8739 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8741 s
= input_line_pointer
;
8742 input_line_pointer
= save_in
;
8743 if (err
!= NULL
&& *err
!= '\0')
8745 as_bad (_("Bad floating point constant: %s"), err
);
8746 memset (temp
, '\0', sizeof temp
);
8747 length
= f64
? 8 : 4;
8750 assert (length
== (unsigned) (f64
? 8 : 4));
8754 && (g_switch_value
< 4
8755 || (temp
[0] == 0 && temp
[1] == 0)
8756 || (temp
[2] == 0 && temp
[3] == 0))))
8758 imm_expr
.X_op
= O_constant
;
8759 if (! target_big_endian
)
8760 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8762 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8765 && ! mips_disable_float_construction
8766 /* Constants can only be constructed in GPRs and
8767 copied to FPRs if the GPRs are at least as wide
8768 as the FPRs. Force the constant into memory if
8769 we are using 64-bit FPRs but the GPRs are only
8772 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8773 && ((temp
[0] == 0 && temp
[1] == 0)
8774 || (temp
[2] == 0 && temp
[3] == 0))
8775 && ((temp
[4] == 0 && temp
[5] == 0)
8776 || (temp
[6] == 0 && temp
[7] == 0)))
8778 /* The value is simple enough to load with a couple of
8779 instructions. If using 32-bit registers, set
8780 imm_expr to the high order 32 bits and offset_expr to
8781 the low order 32 bits. Otherwise, set imm_expr to
8782 the entire 64 bit constant. */
8783 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8785 imm_expr
.X_op
= O_constant
;
8786 offset_expr
.X_op
= O_constant
;
8787 if (! target_big_endian
)
8789 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8790 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8794 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8795 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8797 if (offset_expr
.X_add_number
== 0)
8798 offset_expr
.X_op
= O_absent
;
8800 else if (sizeof (imm_expr
.X_add_number
) > 4)
8802 imm_expr
.X_op
= O_constant
;
8803 if (! target_big_endian
)
8804 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8806 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8810 imm_expr
.X_op
= O_big
;
8811 imm_expr
.X_add_number
= 4;
8812 if (! target_big_endian
)
8814 generic_bignum
[0] = bfd_getl16 (temp
);
8815 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8816 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8817 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8821 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8822 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8823 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8824 generic_bignum
[3] = bfd_getb16 (temp
);
8830 const char *newname
;
8833 /* Switch to the right section. */
8835 subseg
= now_subseg
;
8838 default: /* unused default case avoids warnings. */
8840 newname
= RDATA_SECTION_NAME
;
8841 if (g_switch_value
>= 8)
8845 newname
= RDATA_SECTION_NAME
;
8848 assert (g_switch_value
>= 4);
8852 new_seg
= subseg_new (newname
, (subsegT
) 0);
8853 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8854 bfd_set_section_flags (stdoutput
, new_seg
,
8859 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8860 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8861 && strcmp (TARGET_OS
, "elf") != 0)
8862 record_alignment (new_seg
, 4);
8864 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8866 as_bad (_("Can't use floating point insn in this section"));
8868 /* Set the argument to the current address in the
8870 offset_expr
.X_op
= O_symbol
;
8871 offset_expr
.X_add_symbol
=
8872 symbol_new ("L0\001", now_seg
,
8873 (valueT
) frag_now_fix (), frag_now
);
8874 offset_expr
.X_add_number
= 0;
8876 /* Put the floating point number into the section. */
8877 p
= frag_more ((int) length
);
8878 memcpy (p
, temp
, length
);
8880 /* Switch back to the original section. */
8881 subseg_set (seg
, subseg
);
8886 case 'i': /* 16 bit unsigned immediate */
8887 case 'j': /* 16 bit signed immediate */
8888 *imm_reloc
= BFD_RELOC_LO16
;
8889 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8892 offsetT minval
, maxval
;
8894 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8895 && strcmp (insn
->name
, insn
[1].name
) == 0);
8897 /* If the expression was written as an unsigned number,
8898 only treat it as signed if there are no more
8902 && sizeof (imm_expr
.X_add_number
) <= 4
8903 && imm_expr
.X_op
== O_constant
8904 && imm_expr
.X_add_number
< 0
8905 && imm_expr
.X_unsigned
8909 /* For compatibility with older assemblers, we accept
8910 0x8000-0xffff as signed 16-bit numbers when only
8911 signed numbers are allowed. */
8913 minval
= 0, maxval
= 0xffff;
8915 minval
= -0x8000, maxval
= 0x7fff;
8917 minval
= -0x8000, maxval
= 0xffff;
8919 if (imm_expr
.X_op
!= O_constant
8920 || imm_expr
.X_add_number
< minval
8921 || imm_expr
.X_add_number
> maxval
)
8925 if (imm_expr
.X_op
== O_constant
8926 || imm_expr
.X_op
== O_big
)
8927 as_bad (_("expression out of range"));
8933 case 'o': /* 16 bit offset */
8934 /* Check whether there is only a single bracketed expression
8935 left. If so, it must be the base register and the
8936 constant must be zero. */
8937 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8939 offset_expr
.X_op
= O_constant
;
8940 offset_expr
.X_add_number
= 0;
8944 /* If this value won't fit into a 16 bit offset, then go
8945 find a macro that will generate the 32 bit offset
8947 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8948 && (offset_expr
.X_op
!= O_constant
8949 || offset_expr
.X_add_number
>= 0x8000
8950 || offset_expr
.X_add_number
< -0x8000))
8956 case 'p': /* pc relative offset */
8957 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8958 my_getExpression (&offset_expr
, s
);
8962 case 'u': /* upper 16 bits */
8963 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8964 && imm_expr
.X_op
== O_constant
8965 && (imm_expr
.X_add_number
< 0
8966 || imm_expr
.X_add_number
>= 0x10000))
8967 as_bad (_("lui expression not in range 0..65535"));
8971 case 'a': /* 26 bit address */
8972 my_getExpression (&offset_expr
, s
);
8974 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8977 case 'N': /* 3 bit branch condition code */
8978 case 'M': /* 3 bit compare condition code */
8979 if (strncmp (s
, "$fcc", 4) != 0)
8989 while (ISDIGIT (*s
));
8991 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8992 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8993 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8994 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8995 && (regno
& 1) != 0)
8996 as_warn(_("Condition code register should be even for %s, was %d"),
8998 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8999 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9000 && (regno
& 3) != 0)
9001 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9004 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9006 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9010 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9021 while (ISDIGIT (*s
));
9024 c
= 8; /* Invalid sel value. */
9027 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9028 ip
->insn_opcode
|= c
;
9032 /* Must be at least one digit. */
9033 my_getExpression (&imm_expr
, s
);
9034 check_absolute_expr (ip
, &imm_expr
);
9036 if ((unsigned long) imm_expr
.X_add_number
9037 > (unsigned long) OP_MASK_VECBYTE
)
9039 as_bad (_("bad byte vector index (%ld)"),
9040 (long) imm_expr
.X_add_number
);
9041 imm_expr
.X_add_number
= 0;
9044 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9045 imm_expr
.X_op
= O_absent
;
9050 my_getExpression (&imm_expr
, s
);
9051 check_absolute_expr (ip
, &imm_expr
);
9053 if ((unsigned long) imm_expr
.X_add_number
9054 > (unsigned long) OP_MASK_VECALIGN
)
9056 as_bad (_("bad byte vector index (%ld)"),
9057 (long) imm_expr
.X_add_number
);
9058 imm_expr
.X_add_number
= 0;
9061 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9062 imm_expr
.X_op
= O_absent
;
9067 as_bad (_("bad char = '%c'\n"), *args
);
9072 /* Args don't match. */
9073 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9074 !strcmp (insn
->name
, insn
[1].name
))
9078 insn_error
= _("illegal operands");
9083 insn_error
= _("illegal operands");
9088 /* This routine assembles an instruction into its binary format when
9089 assembling for the mips16. As a side effect, it sets one of the
9090 global variables imm_reloc or offset_reloc to the type of
9091 relocation to do if one of the operands is an address expression.
9092 It also sets mips16_small and mips16_ext if the user explicitly
9093 requested a small or extended instruction. */
9096 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9100 struct mips_opcode
*insn
;
9103 unsigned int lastregno
= 0;
9109 mips16_small
= FALSE
;
9112 for (s
= str
; ISLOWER (*s
); ++s
)
9124 if (s
[1] == 't' && s
[2] == ' ')
9127 mips16_small
= TRUE
;
9131 else if (s
[1] == 'e' && s
[2] == ' ')
9140 insn_error
= _("unknown opcode");
9144 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9145 mips16_small
= TRUE
;
9147 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9149 insn_error
= _("unrecognized opcode");
9156 assert (strcmp (insn
->name
, str
) == 0);
9159 ip
->insn_opcode
= insn
->match
;
9160 ip
->use_extend
= FALSE
;
9161 imm_expr
.X_op
= O_absent
;
9162 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9163 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9164 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9165 imm2_expr
.X_op
= O_absent
;
9166 offset_expr
.X_op
= O_absent
;
9167 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9168 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9169 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9170 for (args
= insn
->args
; 1; ++args
)
9177 /* In this switch statement we call break if we did not find
9178 a match, continue if we did find a match, or return if we
9187 /* Stuff the immediate value in now, if we can. */
9188 if (imm_expr
.X_op
== O_constant
9189 && *imm_reloc
> BFD_RELOC_UNUSED
9190 && insn
->pinfo
!= INSN_MACRO
)
9194 switch (*offset_reloc
)
9196 case BFD_RELOC_MIPS16_HI16_S
:
9197 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9200 case BFD_RELOC_MIPS16_HI16
:
9201 tmp
= imm_expr
.X_add_number
>> 16;
9204 case BFD_RELOC_MIPS16_LO16
:
9205 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9209 case BFD_RELOC_UNUSED
:
9210 tmp
= imm_expr
.X_add_number
;
9216 *offset_reloc
= BFD_RELOC_UNUSED
;
9218 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9219 tmp
, TRUE
, mips16_small
,
9220 mips16_ext
, &ip
->insn_opcode
,
9221 &ip
->use_extend
, &ip
->extend
);
9222 imm_expr
.X_op
= O_absent
;
9223 *imm_reloc
= BFD_RELOC_UNUSED
;
9237 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9240 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9256 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9258 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9285 while (ISDIGIT (*s
));
9288 as_bad (_("invalid register number (%d)"), regno
);
9294 if (s
[1] == 'r' && s
[2] == 'a')
9299 else if (s
[1] == 'f' && s
[2] == 'p')
9304 else if (s
[1] == 's' && s
[2] == 'p')
9309 else if (s
[1] == 'g' && s
[2] == 'p')
9314 else if (s
[1] == 'a' && s
[2] == 't')
9319 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9324 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9329 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9342 if (c
== 'v' || c
== 'w')
9344 regno
= mips16_to_32_reg_map
[lastregno
];
9358 regno
= mips32_to_16_reg_map
[regno
];
9363 regno
= ILLEGAL_REG
;
9368 regno
= ILLEGAL_REG
;
9373 regno
= ILLEGAL_REG
;
9378 if (regno
== AT
&& ! mips_opts
.noat
)
9379 as_warn (_("used $at without \".set noat\""));
9386 if (regno
== ILLEGAL_REG
)
9393 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9397 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9400 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9403 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9409 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9412 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9413 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9423 if (strncmp (s
, "$pc", 3) == 0)
9440 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9443 if (imm_expr
.X_op
!= O_constant
)
9446 ip
->use_extend
= TRUE
;
9451 /* We need to relax this instruction. */
9452 *offset_reloc
= *imm_reloc
;
9453 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9458 *imm_reloc
= BFD_RELOC_UNUSED
;
9466 my_getExpression (&imm_expr
, s
);
9467 if (imm_expr
.X_op
== O_register
)
9469 /* What we thought was an expression turned out to
9472 if (s
[0] == '(' && args
[1] == '(')
9474 /* It looks like the expression was omitted
9475 before a register indirection, which means
9476 that the expression is implicitly zero. We
9477 still set up imm_expr, so that we handle
9478 explicit extensions correctly. */
9479 imm_expr
.X_op
= O_constant
;
9480 imm_expr
.X_add_number
= 0;
9481 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9488 /* We need to relax this instruction. */
9489 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9498 /* We use offset_reloc rather than imm_reloc for the PC
9499 relative operands. This lets macros with both
9500 immediate and address operands work correctly. */
9501 my_getExpression (&offset_expr
, s
);
9503 if (offset_expr
.X_op
== O_register
)
9506 /* We need to relax this instruction. */
9507 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9511 case '6': /* break code */
9512 my_getExpression (&imm_expr
, s
);
9513 check_absolute_expr (ip
, &imm_expr
);
9514 if ((unsigned long) imm_expr
.X_add_number
> 63)
9516 as_warn (_("Invalid value for `%s' (%lu)"),
9518 (unsigned long) imm_expr
.X_add_number
);
9519 imm_expr
.X_add_number
&= 0x3f;
9521 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9522 imm_expr
.X_op
= O_absent
;
9526 case 'a': /* 26 bit address */
9527 my_getExpression (&offset_expr
, s
);
9529 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9530 ip
->insn_opcode
<<= 16;
9533 case 'l': /* register list for entry macro */
9534 case 'L': /* register list for exit macro */
9544 int freg
, reg1
, reg2
;
9546 while (*s
== ' ' || *s
== ',')
9550 as_bad (_("can't parse register list"));
9562 while (ISDIGIT (*s
))
9584 as_bad (_("invalid register list"));
9589 while (ISDIGIT (*s
))
9596 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9601 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9606 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9607 mask
|= (reg2
- 3) << 3;
9608 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9609 mask
|= (reg2
- 15) << 1;
9610 else if (reg1
== RA
&& reg2
== RA
)
9614 as_bad (_("invalid register list"));
9618 /* The mask is filled in in the opcode table for the
9619 benefit of the disassembler. We remove it before
9620 applying the actual mask. */
9621 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9622 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9626 case 'e': /* extend code */
9627 my_getExpression (&imm_expr
, s
);
9628 check_absolute_expr (ip
, &imm_expr
);
9629 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9631 as_warn (_("Invalid value for `%s' (%lu)"),
9633 (unsigned long) imm_expr
.X_add_number
);
9634 imm_expr
.X_add_number
&= 0x7ff;
9636 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9637 imm_expr
.X_op
= O_absent
;
9647 /* Args don't match. */
9648 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9649 strcmp (insn
->name
, insn
[1].name
) == 0)
9656 insn_error
= _("illegal operands");
9662 /* This structure holds information we know about a mips16 immediate
9665 struct mips16_immed_operand
9667 /* The type code used in the argument string in the opcode table. */
9669 /* The number of bits in the short form of the opcode. */
9671 /* The number of bits in the extended form of the opcode. */
9673 /* The amount by which the short form is shifted when it is used;
9674 for example, the sw instruction has a shift count of 2. */
9676 /* The amount by which the short form is shifted when it is stored
9677 into the instruction code. */
9679 /* Non-zero if the short form is unsigned. */
9681 /* Non-zero if the extended form is unsigned. */
9683 /* Non-zero if the value is PC relative. */
9687 /* The mips16 immediate operand types. */
9689 static const struct mips16_immed_operand mips16_immed_operands
[] =
9691 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9692 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9693 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9694 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9695 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9696 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9697 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9698 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9699 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9700 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9701 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9702 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9703 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9704 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9705 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9706 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9707 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9708 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9709 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9710 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9711 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9714 #define MIPS16_NUM_IMMED \
9715 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9717 /* Handle a mips16 instruction with an immediate value. This or's the
9718 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9719 whether an extended value is needed; if one is needed, it sets
9720 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9721 If SMALL is true, an unextended opcode was explicitly requested.
9722 If EXT is true, an extended opcode was explicitly requested. If
9723 WARN is true, warn if EXT does not match reality. */
9726 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9727 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9728 unsigned long *insn
, bfd_boolean
*use_extend
,
9729 unsigned short *extend
)
9731 register const struct mips16_immed_operand
*op
;
9732 int mintiny
, maxtiny
;
9733 bfd_boolean needext
;
9735 op
= mips16_immed_operands
;
9736 while (op
->type
!= type
)
9739 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9744 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9747 maxtiny
= 1 << op
->nbits
;
9752 maxtiny
= (1 << op
->nbits
) - 1;
9757 mintiny
= - (1 << (op
->nbits
- 1));
9758 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9761 /* Branch offsets have an implicit 0 in the lowest bit. */
9762 if (type
== 'p' || type
== 'q')
9765 if ((val
& ((1 << op
->shift
) - 1)) != 0
9766 || val
< (mintiny
<< op
->shift
)
9767 || val
> (maxtiny
<< op
->shift
))
9772 if (warn
&& ext
&& ! needext
)
9773 as_warn_where (file
, line
,
9774 _("extended operand requested but not required"));
9775 if (small
&& needext
)
9776 as_bad_where (file
, line
, _("invalid unextended operand value"));
9778 if (small
|| (! ext
&& ! needext
))
9782 *use_extend
= FALSE
;
9783 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9784 insnval
<<= op
->op_shift
;
9789 long minext
, maxext
;
9795 maxext
= (1 << op
->extbits
) - 1;
9799 minext
= - (1 << (op
->extbits
- 1));
9800 maxext
= (1 << (op
->extbits
- 1)) - 1;
9802 if (val
< minext
|| val
> maxext
)
9803 as_bad_where (file
, line
,
9804 _("operand value out of range for instruction"));
9807 if (op
->extbits
== 16)
9809 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9812 else if (op
->extbits
== 15)
9814 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9819 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9823 *extend
= (unsigned short) extval
;
9828 struct percent_op_match
9831 bfd_reloc_code_real_type reloc
;
9834 static const struct percent_op_match mips_percent_op
[] =
9836 {"%lo", BFD_RELOC_LO16
},
9838 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9839 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9840 {"%call16", BFD_RELOC_MIPS_CALL16
},
9841 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9842 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9843 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9844 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9845 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9846 {"%got", BFD_RELOC_MIPS_GOT16
},
9847 {"%gp_rel", BFD_RELOC_GPREL16
},
9848 {"%half", BFD_RELOC_16
},
9849 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9850 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9851 {"%neg", BFD_RELOC_MIPS_SUB
},
9852 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9853 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9854 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9855 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9856 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9857 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9858 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9860 {"%hi", BFD_RELOC_HI16_S
}
9863 static const struct percent_op_match mips16_percent_op
[] =
9865 {"%lo", BFD_RELOC_MIPS16_LO16
},
9866 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9867 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9871 /* Return true if *STR points to a relocation operator. When returning true,
9872 move *STR over the operator and store its relocation code in *RELOC.
9873 Leave both *STR and *RELOC alone when returning false. */
9876 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9878 const struct percent_op_match
*percent_op
;
9881 if (mips_opts
.mips16
)
9883 percent_op
= mips16_percent_op
;
9884 limit
= ARRAY_SIZE (mips16_percent_op
);
9888 percent_op
= mips_percent_op
;
9889 limit
= ARRAY_SIZE (mips_percent_op
);
9892 for (i
= 0; i
< limit
; i
++)
9893 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9895 int len
= strlen (percent_op
[i
].str
);
9897 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9900 *str
+= strlen (percent_op
[i
].str
);
9901 *reloc
= percent_op
[i
].reloc
;
9903 /* Check whether the output BFD supports this relocation.
9904 If not, issue an error and fall back on something safe. */
9905 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9907 as_bad ("relocation %s isn't supported by the current ABI",
9909 *reloc
= BFD_RELOC_UNUSED
;
9917 /* Parse string STR as a 16-bit relocatable operand. Store the
9918 expression in *EP and the relocations in the array starting
9919 at RELOC. Return the number of relocation operators used.
9921 On exit, EXPR_END points to the first character after the expression. */
9924 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9927 bfd_reloc_code_real_type reversed_reloc
[3];
9928 size_t reloc_index
, i
;
9929 int crux_depth
, str_depth
;
9932 /* Search for the start of the main expression, recoding relocations
9933 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9934 of the main expression and with CRUX_DEPTH containing the number
9935 of open brackets at that point. */
9942 crux_depth
= str_depth
;
9944 /* Skip over whitespace and brackets, keeping count of the number
9946 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9951 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9952 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9954 my_getExpression (ep
, crux
);
9957 /* Match every open bracket. */
9958 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9963 as_bad ("unclosed '('");
9967 if (reloc_index
!= 0)
9969 prev_reloc_op_frag
= frag_now
;
9970 for (i
= 0; i
< reloc_index
; i
++)
9971 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9978 my_getExpression (expressionS
*ep
, char *str
)
9983 save_in
= input_line_pointer
;
9984 input_line_pointer
= str
;
9986 expr_end
= input_line_pointer
;
9987 input_line_pointer
= save_in
;
9989 /* If we are in mips16 mode, and this is an expression based on `.',
9990 then we bump the value of the symbol by 1 since that is how other
9991 text symbols are handled. We don't bother to handle complex
9992 expressions, just `.' plus or minus a constant. */
9993 if (mips_opts
.mips16
9994 && ep
->X_op
== O_symbol
9995 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9996 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9997 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9998 && symbol_constant_p (ep
->X_add_symbol
)
9999 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10000 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10003 /* Turn a string in input_line_pointer into a floating point constant
10004 of type TYPE, and store the appropriate bytes in *LITP. The number
10005 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10006 returned, or NULL on OK. */
10009 md_atof (int type
, char *litP
, int *sizeP
)
10012 LITTLENUM_TYPE words
[4];
10028 return _("bad call to md_atof");
10031 t
= atof_ieee (input_line_pointer
, type
, words
);
10033 input_line_pointer
= t
;
10037 if (! target_big_endian
)
10039 for (i
= prec
- 1; i
>= 0; i
--)
10041 md_number_to_chars (litP
, words
[i
], 2);
10047 for (i
= 0; i
< prec
; i
++)
10049 md_number_to_chars (litP
, words
[i
], 2);
10058 md_number_to_chars (char *buf
, valueT val
, int n
)
10060 if (target_big_endian
)
10061 number_to_chars_bigendian (buf
, val
, n
);
10063 number_to_chars_littleendian (buf
, val
, n
);
10067 static int support_64bit_objects(void)
10069 const char **list
, **l
;
10072 list
= bfd_target_list ();
10073 for (l
= list
; *l
!= NULL
; l
++)
10075 /* This is traditional mips */
10076 if (strcmp (*l
, "elf64-tradbigmips") == 0
10077 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10079 if (strcmp (*l
, "elf64-bigmips") == 0
10080 || strcmp (*l
, "elf64-littlemips") == 0)
10083 yes
= (*l
!= NULL
);
10087 #endif /* OBJ_ELF */
10089 const char *md_shortopts
= "O::g::G:";
10091 struct option md_longopts
[] =
10093 /* Options which specify architecture. */
10094 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10095 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10096 {"march", required_argument
, NULL
, OPTION_MARCH
},
10097 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10098 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10099 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10100 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10101 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10102 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10103 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10104 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10105 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10106 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10107 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10108 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10109 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10110 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10111 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10112 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10113 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10114 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10115 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10116 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10117 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10119 /* Options which specify Application Specific Extensions (ASEs). */
10120 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10121 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10122 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10123 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10124 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10125 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10126 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10127 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10128 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10129 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10130 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10131 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10132 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10134 /* Old-style architecture options. Don't add more of these. */
10135 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10136 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10137 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10138 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10139 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10140 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10141 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10142 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10143 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10144 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10145 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10146 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10147 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10148 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10149 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10150 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10151 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10153 /* Options which enable bug fixes. */
10154 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10155 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10156 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10157 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10158 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10159 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10160 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10161 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10162 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10163 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10165 /* Miscellaneous options. */
10166 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10167 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10168 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10169 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10170 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10171 {"break", no_argument
, NULL
, OPTION_BREAK
},
10172 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10173 #define OPTION_EB (OPTION_MISC_BASE + 2)
10174 {"EB", no_argument
, NULL
, OPTION_EB
},
10175 #define OPTION_EL (OPTION_MISC_BASE + 3)
10176 {"EL", no_argument
, NULL
, OPTION_EL
},
10177 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10178 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10179 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10180 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10181 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10182 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10183 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10184 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10185 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10186 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10187 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10188 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10189 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10190 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10191 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10192 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10193 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10194 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10195 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10196 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10197 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10198 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10199 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10200 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10202 /* ELF-specific options. */
10204 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10205 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10206 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10207 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10208 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10209 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10210 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10211 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10212 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10213 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10214 #define OPTION_32 (OPTION_ELF_BASE + 4)
10215 {"32", no_argument
, NULL
, OPTION_32
},
10216 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10217 {"n32", no_argument
, NULL
, OPTION_N32
},
10218 #define OPTION_64 (OPTION_ELF_BASE + 6)
10219 {"64", no_argument
, NULL
, OPTION_64
},
10220 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10221 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10222 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10223 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10224 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10225 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10226 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10227 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10228 #endif /* OBJ_ELF */
10230 {NULL
, no_argument
, NULL
, 0}
10232 size_t md_longopts_size
= sizeof (md_longopts
);
10234 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10235 NEW_VALUE. Warn if another value was already specified. Note:
10236 we have to defer parsing the -march and -mtune arguments in order
10237 to handle 'from-abi' correctly, since the ABI might be specified
10238 in a later argument. */
10241 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10243 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10244 as_warn (_("A different %s was already specified, is now %s"),
10245 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10248 *string_ptr
= new_value
;
10252 md_parse_option (int c
, char *arg
)
10256 case OPTION_CONSTRUCT_FLOATS
:
10257 mips_disable_float_construction
= 0;
10260 case OPTION_NO_CONSTRUCT_FLOATS
:
10261 mips_disable_float_construction
= 1;
10273 target_big_endian
= 1;
10277 target_big_endian
= 0;
10281 if (arg
&& arg
[1] == '0')
10291 mips_debug
= atoi (arg
);
10292 /* When the MIPS assembler sees -g or -g2, it does not do
10293 optimizations which limit full symbolic debugging. We take
10294 that to be equivalent to -O0. */
10295 if (mips_debug
== 2)
10300 file_mips_isa
= ISA_MIPS1
;
10304 file_mips_isa
= ISA_MIPS2
;
10308 file_mips_isa
= ISA_MIPS3
;
10312 file_mips_isa
= ISA_MIPS4
;
10316 file_mips_isa
= ISA_MIPS5
;
10319 case OPTION_MIPS32
:
10320 file_mips_isa
= ISA_MIPS32
;
10323 case OPTION_MIPS32R2
:
10324 file_mips_isa
= ISA_MIPS32R2
;
10327 case OPTION_MIPS64R2
:
10328 file_mips_isa
= ISA_MIPS64R2
;
10331 case OPTION_MIPS64
:
10332 file_mips_isa
= ISA_MIPS64
;
10336 mips_set_option_string (&mips_tune_string
, arg
);
10340 mips_set_option_string (&mips_arch_string
, arg
);
10344 mips_set_option_string (&mips_arch_string
, "4650");
10345 mips_set_option_string (&mips_tune_string
, "4650");
10348 case OPTION_NO_M4650
:
10352 mips_set_option_string (&mips_arch_string
, "4010");
10353 mips_set_option_string (&mips_tune_string
, "4010");
10356 case OPTION_NO_M4010
:
10360 mips_set_option_string (&mips_arch_string
, "4100");
10361 mips_set_option_string (&mips_tune_string
, "4100");
10364 case OPTION_NO_M4100
:
10368 mips_set_option_string (&mips_arch_string
, "3900");
10369 mips_set_option_string (&mips_tune_string
, "3900");
10372 case OPTION_NO_M3900
:
10376 mips_opts
.ase_mdmx
= 1;
10379 case OPTION_NO_MDMX
:
10380 mips_opts
.ase_mdmx
= 0;
10383 case OPTION_MIPS16
:
10384 mips_opts
.mips16
= 1;
10385 mips_no_prev_insn (FALSE
);
10388 case OPTION_NO_MIPS16
:
10389 mips_opts
.mips16
= 0;
10390 mips_no_prev_insn (FALSE
);
10393 case OPTION_MIPS3D
:
10394 mips_opts
.ase_mips3d
= 1;
10397 case OPTION_NO_MIPS3D
:
10398 mips_opts
.ase_mips3d
= 0;
10401 case OPTION_FIX_VR4120
:
10402 mips_fix_vr4120
= 1;
10405 case OPTION_NO_FIX_VR4120
:
10406 mips_fix_vr4120
= 0;
10409 case OPTION_RELAX_BRANCH
:
10410 mips_relax_branch
= 1;
10413 case OPTION_NO_RELAX_BRANCH
:
10414 mips_relax_branch
= 0;
10417 case OPTION_MSHARED
:
10418 mips_in_shared
= TRUE
;
10421 case OPTION_MNO_SHARED
:
10422 mips_in_shared
= FALSE
;
10425 case OPTION_MSYM32
:
10426 mips_opts
.sym32
= TRUE
;
10429 case OPTION_MNO_SYM32
:
10430 mips_opts
.sym32
= FALSE
;
10434 /* When generating ELF code, we permit -KPIC and -call_shared to
10435 select SVR4_PIC, and -non_shared to select no PIC. This is
10436 intended to be compatible with Irix 5. */
10437 case OPTION_CALL_SHARED
:
10438 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10440 as_bad (_("-call_shared is supported only for ELF format"));
10443 mips_pic
= SVR4_PIC
;
10444 mips_abicalls
= TRUE
;
10445 if (g_switch_seen
&& g_switch_value
!= 0)
10447 as_bad (_("-G may not be used with SVR4 PIC code"));
10450 g_switch_value
= 0;
10453 case OPTION_NON_SHARED
:
10454 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10456 as_bad (_("-non_shared is supported only for ELF format"));
10460 mips_abicalls
= FALSE
;
10463 /* The -xgot option tells the assembler to use 32 offsets when
10464 accessing the got in SVR4_PIC mode. It is for Irix
10469 #endif /* OBJ_ELF */
10472 g_switch_value
= atoi (arg
);
10474 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10476 as_bad (_("-G may not be used with SVR4 PIC code"));
10482 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10485 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10487 as_bad (_("-32 is supported for ELF format only"));
10490 mips_abi
= O32_ABI
;
10494 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10496 as_bad (_("-n32 is supported for ELF format only"));
10499 mips_abi
= N32_ABI
;
10503 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10505 as_bad (_("-64 is supported for ELF format only"));
10508 mips_abi
= N64_ABI
;
10509 if (! support_64bit_objects())
10510 as_fatal (_("No compiled in support for 64 bit object file format"));
10512 #endif /* OBJ_ELF */
10515 file_mips_gp32
= 1;
10519 file_mips_gp32
= 0;
10523 file_mips_fp32
= 1;
10527 file_mips_fp32
= 0;
10532 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10534 as_bad (_("-mabi is supported for ELF format only"));
10537 if (strcmp (arg
, "32") == 0)
10538 mips_abi
= O32_ABI
;
10539 else if (strcmp (arg
, "o64") == 0)
10540 mips_abi
= O64_ABI
;
10541 else if (strcmp (arg
, "n32") == 0)
10542 mips_abi
= N32_ABI
;
10543 else if (strcmp (arg
, "64") == 0)
10545 mips_abi
= N64_ABI
;
10546 if (! support_64bit_objects())
10547 as_fatal (_("No compiled in support for 64 bit object file "
10550 else if (strcmp (arg
, "eabi") == 0)
10551 mips_abi
= EABI_ABI
;
10554 as_fatal (_("invalid abi -mabi=%s"), arg
);
10558 #endif /* OBJ_ELF */
10560 case OPTION_M7000_HILO_FIX
:
10561 mips_7000_hilo_fix
= TRUE
;
10564 case OPTION_MNO_7000_HILO_FIX
:
10565 mips_7000_hilo_fix
= FALSE
;
10569 case OPTION_MDEBUG
:
10570 mips_flag_mdebug
= TRUE
;
10573 case OPTION_NO_MDEBUG
:
10574 mips_flag_mdebug
= FALSE
;
10578 mips_flag_pdr
= TRUE
;
10581 case OPTION_NO_PDR
:
10582 mips_flag_pdr
= FALSE
;
10584 #endif /* OBJ_ELF */
10593 /* Set up globals to generate code for the ISA or processor
10594 described by INFO. */
10597 mips_set_architecture (const struct mips_cpu_info
*info
)
10601 file_mips_arch
= info
->cpu
;
10602 mips_opts
.arch
= info
->cpu
;
10603 mips_opts
.isa
= info
->isa
;
10608 /* Likewise for tuning. */
10611 mips_set_tune (const struct mips_cpu_info
*info
)
10614 mips_tune
= info
->cpu
;
10619 mips_after_parse_args (void)
10621 const struct mips_cpu_info
*arch_info
= 0;
10622 const struct mips_cpu_info
*tune_info
= 0;
10624 /* GP relative stuff not working for PE */
10625 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10627 if (g_switch_seen
&& g_switch_value
!= 0)
10628 as_bad (_("-G not supported in this configuration."));
10629 g_switch_value
= 0;
10632 if (mips_abi
== NO_ABI
)
10633 mips_abi
= MIPS_DEFAULT_ABI
;
10635 /* The following code determines the architecture and register size.
10636 Similar code was added to GCC 3.3 (see override_options() in
10637 config/mips/mips.c). The GAS and GCC code should be kept in sync
10638 as much as possible. */
10640 if (mips_arch_string
!= 0)
10641 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10643 if (file_mips_isa
!= ISA_UNKNOWN
)
10645 /* Handle -mipsN. At this point, file_mips_isa contains the
10646 ISA level specified by -mipsN, while arch_info->isa contains
10647 the -march selection (if any). */
10648 if (arch_info
!= 0)
10650 /* -march takes precedence over -mipsN, since it is more descriptive.
10651 There's no harm in specifying both as long as the ISA levels
10653 if (file_mips_isa
!= arch_info
->isa
)
10654 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10655 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10656 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10659 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10662 if (arch_info
== 0)
10663 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10665 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10666 as_bad ("-march=%s is not compatible with the selected ABI",
10669 mips_set_architecture (arch_info
);
10671 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10672 if (mips_tune_string
!= 0)
10673 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10675 if (tune_info
== 0)
10676 mips_set_tune (arch_info
);
10678 mips_set_tune (tune_info
);
10680 if (file_mips_gp32
>= 0)
10682 /* The user specified the size of the integer registers. Make sure
10683 it agrees with the ABI and ISA. */
10684 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10685 as_bad (_("-mgp64 used with a 32-bit processor"));
10686 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10687 as_bad (_("-mgp32 used with a 64-bit ABI"));
10688 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10689 as_bad (_("-mgp64 used with a 32-bit ABI"));
10693 /* Infer the integer register size from the ABI and processor.
10694 Restrict ourselves to 32-bit registers if that's all the
10695 processor has, or if the ABI cannot handle 64-bit registers. */
10696 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10697 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10700 /* ??? GAS treats single-float processors as though they had 64-bit
10701 float registers (although it complains when double-precision
10702 instructions are used). As things stand, saying they have 32-bit
10703 registers would lead to spurious "register must be even" messages.
10704 So here we assume float registers are always the same size as
10705 integer ones, unless the user says otherwise. */
10706 if (file_mips_fp32
< 0)
10707 file_mips_fp32
= file_mips_gp32
;
10709 /* End of GCC-shared inference code. */
10711 /* This flag is set when we have a 64-bit capable CPU but use only
10712 32-bit wide registers. Note that EABI does not use it. */
10713 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10714 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10715 || mips_abi
== O32_ABI
))
10716 mips_32bitmode
= 1;
10718 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10719 as_bad (_("trap exception not supported at ISA 1"));
10721 /* If the selected architecture includes support for ASEs, enable
10722 generation of code for them. */
10723 if (mips_opts
.mips16
== -1)
10724 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10725 if (mips_opts
.ase_mips3d
== -1)
10726 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10727 if (mips_opts
.ase_mdmx
== -1)
10728 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10730 file_mips_isa
= mips_opts
.isa
;
10731 file_ase_mips16
= mips_opts
.mips16
;
10732 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10733 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10734 mips_opts
.gp32
= file_mips_gp32
;
10735 mips_opts
.fp32
= file_mips_fp32
;
10737 if (mips_flag_mdebug
< 0)
10739 #ifdef OBJ_MAYBE_ECOFF
10740 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10741 mips_flag_mdebug
= 1;
10743 #endif /* OBJ_MAYBE_ECOFF */
10744 mips_flag_mdebug
= 0;
10749 mips_init_after_args (void)
10751 /* initialize opcodes */
10752 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10753 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10757 md_pcrel_from (fixS
*fixP
)
10759 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10760 switch (fixP
->fx_r_type
)
10762 case BFD_RELOC_16_PCREL_S2
:
10763 case BFD_RELOC_MIPS_JMP
:
10764 /* Return the address of the delay slot. */
10771 /* This is called before the symbol table is processed. In order to
10772 work with gcc when using mips-tfile, we must keep all local labels.
10773 However, in other cases, we want to discard them. If we were
10774 called with -g, but we didn't see any debugging information, it may
10775 mean that gcc is smuggling debugging information through to
10776 mips-tfile, in which case we must generate all local labels. */
10779 mips_frob_file_before_adjust (void)
10781 #ifndef NO_ECOFF_DEBUGGING
10782 if (ECOFF_DEBUGGING
10784 && ! ecoff_debugging_seen
)
10785 flag_keep_locals
= 1;
10789 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10790 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10791 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10792 relocation operators.
10794 For our purposes, a %lo() expression matches a %got() or %hi()
10797 (a) it refers to the same symbol; and
10798 (b) the offset applied in the %lo() expression is no lower than
10799 the offset applied in the %got() or %hi().
10801 (b) allows us to cope with code like:
10804 lh $4,%lo(foo+2)($4)
10806 ...which is legal on RELA targets, and has a well-defined behaviour
10807 if the user knows that adding 2 to "foo" will not induce a carry to
10810 When several %lo()s match a particular %got() or %hi(), we use the
10811 following rules to distinguish them:
10813 (1) %lo()s with smaller offsets are a better match than %lo()s with
10816 (2) %lo()s with no matching %got() or %hi() are better than those
10817 that already have a matching %got() or %hi().
10819 (3) later %lo()s are better than earlier %lo()s.
10821 These rules are applied in order.
10823 (1) means, among other things, that %lo()s with identical offsets are
10824 chosen if they exist.
10826 (2) means that we won't associate several high-part relocations with
10827 the same low-part relocation unless there's no alternative. Having
10828 several high parts for the same low part is a GNU extension; this rule
10829 allows careful users to avoid it.
10831 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10832 with the last high-part relocation being at the front of the list.
10833 It therefore makes sense to choose the last matching low-part
10834 relocation, all other things being equal. It's also easier
10835 to code that way. */
10838 mips_frob_file (void)
10840 struct mips_hi_fixup
*l
;
10842 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10844 segment_info_type
*seginfo
;
10845 bfd_boolean matched_lo_p
;
10846 fixS
**hi_pos
, **lo_pos
, **pos
;
10848 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10850 /* If a GOT16 relocation turns out to be against a global symbol,
10851 there isn't supposed to be a matching LO. */
10852 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10853 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10856 /* Check quickly whether the next fixup happens to be a matching %lo. */
10857 if (fixup_has_matching_lo_p (l
->fixp
))
10860 seginfo
= seg_info (l
->seg
);
10862 /* Set HI_POS to the position of this relocation in the chain.
10863 Set LO_POS to the position of the chosen low-part relocation.
10864 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10865 relocation that matches an immediately-preceding high-part
10869 matched_lo_p
= FALSE
;
10870 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10872 if (*pos
== l
->fixp
)
10875 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10876 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10877 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10879 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10881 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10884 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10885 && fixup_has_matching_lo_p (*pos
));
10888 /* If we found a match, remove the high-part relocation from its
10889 current position and insert it before the low-part relocation.
10890 Make the offsets match so that fixup_has_matching_lo_p()
10893 We don't warn about unmatched high-part relocations since some
10894 versions of gcc have been known to emit dead "lui ...%hi(...)"
10896 if (lo_pos
!= NULL
)
10898 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10899 if (l
->fixp
->fx_next
!= *lo_pos
)
10901 *hi_pos
= l
->fixp
->fx_next
;
10902 l
->fixp
->fx_next
= *lo_pos
;
10909 /* We may have combined relocations without symbols in the N32/N64 ABI.
10910 We have to prevent gas from dropping them. */
10913 mips_force_relocation (fixS
*fixp
)
10915 if (generic_force_reloc (fixp
))
10919 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10920 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10921 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10922 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10928 /* This hook is called before a fix is simplified. We don't really
10929 decide whether to skip a fix here. Rather, we turn global symbols
10930 used as branch targets into local symbols, such that they undergo
10931 simplification. We can only do this if the symbol is defined and
10932 it is in the same section as the branch. If this doesn't hold, we
10933 emit a better error message than just saying the relocation is not
10934 valid for the selected object format.
10936 FIXP is the fix-up we're going to try to simplify, SEG is the
10937 segment in which the fix up occurs. The return value should be
10938 non-zero to indicate the fix-up is valid for further
10939 simplifications. */
10942 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10944 /* There's a lot of discussion on whether it should be possible to
10945 use R_MIPS_PC16 to represent branch relocations. The outcome
10946 seems to be that it can, but gas/bfd are very broken in creating
10947 RELA relocations for this, so for now we only accept branches to
10948 symbols in the same section. Anything else is of dubious value,
10949 since there's no guarantee that at link time the symbol would be
10950 in range. Even for branches to local symbols this is arguably
10951 wrong, since it we assume the symbol is not going to be
10952 overridden, which should be possible per ELF library semantics,
10953 but then, there isn't a dynamic relocation that could be used to
10954 this effect, and the target would likely be out of range as well.
10956 Unfortunately, it seems that there is too much code out there
10957 that relies on branches to symbols that are global to be resolved
10958 as if they were local, like the IRIX tools do, so we do it as
10959 well, but with a warning so that people are reminded to fix their
10960 code. If we ever get back to using R_MIPS_PC16 for branch
10961 targets, this entire block should go away (and probably the
10962 whole function). */
10964 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10965 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10966 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10967 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10970 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10973 _("Cannot branch to undefined symbol."));
10974 /* Avoid any further errors about this fixup. */
10977 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10980 _("Cannot branch to symbol in another section."));
10983 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10985 symbolS
*sym
= fixP
->fx_addsy
;
10987 if (mips_pic
== SVR4_PIC
)
10988 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10989 _("Pretending global symbol used as branch target is local."));
10991 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10992 S_GET_SEGMENT (sym
),
10994 symbol_get_frag (sym
));
10995 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10996 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10997 assert (symbol_resolved_p (sym
));
10998 symbol_mark_resolved (fixP
->fx_addsy
);
11005 /* Apply a fixup to the object file. */
11008 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11012 reloc_howto_type
*howto
;
11014 /* We ignore generic BFD relocations we don't know about. */
11015 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11019 assert (fixP
->fx_size
== 4
11020 || fixP
->fx_r_type
== BFD_RELOC_16
11021 || fixP
->fx_r_type
== BFD_RELOC_64
11022 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11023 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11024 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11025 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11027 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11029 assert (! fixP
->fx_pcrel
);
11031 /* Don't treat parts of a composite relocation as done. There are two
11034 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11035 should nevertheless be emitted if the first part is.
11037 (2) In normal usage, composite relocations are never assembly-time
11038 constants. The easiest way of dealing with the pathological
11039 exceptions is to generate a relocation against STN_UNDEF and
11040 leave everything up to the linker. */
11041 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11044 switch (fixP
->fx_r_type
)
11046 case BFD_RELOC_MIPS_TLS_GD
:
11047 case BFD_RELOC_MIPS_TLS_LDM
:
11048 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11049 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11050 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11051 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11052 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11053 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11056 case BFD_RELOC_MIPS_JMP
:
11057 case BFD_RELOC_MIPS_SHIFT5
:
11058 case BFD_RELOC_MIPS_SHIFT6
:
11059 case BFD_RELOC_MIPS_GOT_DISP
:
11060 case BFD_RELOC_MIPS_GOT_PAGE
:
11061 case BFD_RELOC_MIPS_GOT_OFST
:
11062 case BFD_RELOC_MIPS_SUB
:
11063 case BFD_RELOC_MIPS_INSERT_A
:
11064 case BFD_RELOC_MIPS_INSERT_B
:
11065 case BFD_RELOC_MIPS_DELETE
:
11066 case BFD_RELOC_MIPS_HIGHEST
:
11067 case BFD_RELOC_MIPS_HIGHER
:
11068 case BFD_RELOC_MIPS_SCN_DISP
:
11069 case BFD_RELOC_MIPS_REL16
:
11070 case BFD_RELOC_MIPS_RELGOT
:
11071 case BFD_RELOC_MIPS_JALR
:
11072 case BFD_RELOC_HI16
:
11073 case BFD_RELOC_HI16_S
:
11074 case BFD_RELOC_GPREL16
:
11075 case BFD_RELOC_MIPS_LITERAL
:
11076 case BFD_RELOC_MIPS_CALL16
:
11077 case BFD_RELOC_MIPS_GOT16
:
11078 case BFD_RELOC_GPREL32
:
11079 case BFD_RELOC_MIPS_GOT_HI16
:
11080 case BFD_RELOC_MIPS_GOT_LO16
:
11081 case BFD_RELOC_MIPS_CALL_HI16
:
11082 case BFD_RELOC_MIPS_CALL_LO16
:
11083 case BFD_RELOC_MIPS16_GPREL
:
11084 case BFD_RELOC_MIPS16_HI16
:
11085 case BFD_RELOC_MIPS16_HI16_S
:
11086 assert (! fixP
->fx_pcrel
);
11087 /* Nothing needed to do. The value comes from the reloc entry */
11090 case BFD_RELOC_MIPS16_JMP
:
11091 /* We currently always generate a reloc against a symbol, which
11092 means that we don't want an addend even if the symbol is
11098 /* This is handled like BFD_RELOC_32, but we output a sign
11099 extended value if we are only 32 bits. */
11102 if (8 <= sizeof (valueT
))
11103 md_number_to_chars ((char *) buf
, *valP
, 8);
11108 if ((*valP
& 0x80000000) != 0)
11112 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11114 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11120 case BFD_RELOC_RVA
:
11122 /* If we are deleting this reloc entry, we must fill in the
11123 value now. This can happen if we have a .word which is not
11124 resolved when it appears but is later defined. */
11126 md_number_to_chars ((char *) buf
, *valP
, 4);
11130 /* If we are deleting this reloc entry, we must fill in the
11133 md_number_to_chars ((char *) buf
, *valP
, 2);
11136 case BFD_RELOC_LO16
:
11137 case BFD_RELOC_MIPS16_LO16
:
11138 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11139 may be safe to remove, but if so it's not obvious. */
11140 /* When handling an embedded PIC switch statement, we can wind
11141 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11144 if (*valP
+ 0x8000 > 0xffff)
11145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11146 _("relocation overflow"));
11147 if (target_big_endian
)
11149 md_number_to_chars ((char *) buf
, *valP
, 2);
11153 case BFD_RELOC_16_PCREL_S2
:
11154 if ((*valP
& 0x3) != 0)
11155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11156 _("Branch to odd address (%lx)"), (long) *valP
);
11159 * We need to save the bits in the instruction since fixup_segment()
11160 * might be deleting the relocation entry (i.e., a branch within
11161 * the current segment).
11163 if (! fixP
->fx_done
)
11166 /* update old instruction data */
11167 if (target_big_endian
)
11168 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11170 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11172 if (*valP
+ 0x20000 <= 0x3ffff)
11174 insn
|= (*valP
>> 2) & 0xffff;
11175 md_number_to_chars ((char *) buf
, insn
, 4);
11177 else if (mips_pic
== NO_PIC
11179 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11180 && (fixP
->fx_frag
->fr_address
11181 < text_section
->vma
+ bfd_get_section_size (text_section
))
11182 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11183 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11184 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11186 /* The branch offset is too large. If this is an
11187 unconditional branch, and we are not generating PIC code,
11188 we can convert it to an absolute jump instruction. */
11189 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11190 insn
= 0x0c000000; /* jal */
11192 insn
= 0x08000000; /* j */
11193 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11195 fixP
->fx_addsy
= section_symbol (text_section
);
11196 *valP
+= md_pcrel_from (fixP
);
11197 md_number_to_chars ((char *) buf
, insn
, 4);
11201 /* If we got here, we have branch-relaxation disabled,
11202 and there's nothing we can do to fix this instruction
11203 without turning it into a longer sequence. */
11204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11205 _("Branch out of range"));
11209 case BFD_RELOC_VTABLE_INHERIT
:
11212 && !S_IS_DEFINED (fixP
->fx_addsy
)
11213 && !S_IS_WEAK (fixP
->fx_addsy
))
11214 S_SET_WEAK (fixP
->fx_addsy
);
11217 case BFD_RELOC_VTABLE_ENTRY
:
11225 /* Remember value for tc_gen_reloc. */
11226 fixP
->fx_addnumber
= *valP
;
11236 name
= input_line_pointer
;
11237 c
= get_symbol_end ();
11238 p
= (symbolS
*) symbol_find_or_make (name
);
11239 *input_line_pointer
= c
;
11243 /* Align the current frag to a given power of two. The MIPS assembler
11244 also automatically adjusts any preceding label. */
11247 mips_align (int to
, int fill
, symbolS
*label
)
11249 mips_emit_delays (FALSE
);
11250 frag_align (to
, fill
, 0);
11251 record_alignment (now_seg
, to
);
11254 assert (S_GET_SEGMENT (label
) == now_seg
);
11255 symbol_set_frag (label
, frag_now
);
11256 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11260 /* Align to a given power of two. .align 0 turns off the automatic
11261 alignment used by the data creating pseudo-ops. */
11264 s_align (int x ATTRIBUTE_UNUSED
)
11267 register long temp_fill
;
11268 long max_alignment
= 15;
11272 o Note that the assembler pulls down any immediately preceding label
11273 to the aligned address.
11274 o It's not documented but auto alignment is reinstated by
11275 a .align pseudo instruction.
11276 o Note also that after auto alignment is turned off the mips assembler
11277 issues an error on attempt to assemble an improperly aligned data item.
11282 temp
= get_absolute_expression ();
11283 if (temp
> max_alignment
)
11284 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11287 as_warn (_("Alignment negative: 0 assumed."));
11290 if (*input_line_pointer
== ',')
11292 ++input_line_pointer
;
11293 temp_fill
= get_absolute_expression ();
11300 mips_align (temp
, (int) temp_fill
,
11301 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11308 demand_empty_rest_of_line ();
11312 mips_flush_pending_output (void)
11314 mips_emit_delays (FALSE
);
11315 mips_clear_insn_labels ();
11319 s_change_sec (int sec
)
11324 /* The ELF backend needs to know that we are changing sections, so
11325 that .previous works correctly. We could do something like check
11326 for an obj_section_change_hook macro, but that might be confusing
11327 as it would not be appropriate to use it in the section changing
11328 functions in read.c, since obj-elf.c intercepts those. FIXME:
11329 This should be cleaner, somehow. */
11330 obj_elf_section_change_hook ();
11333 mips_emit_delays (FALSE
);
11343 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11344 demand_empty_rest_of_line ();
11348 seg
= subseg_new (RDATA_SECTION_NAME
,
11349 (subsegT
) get_absolute_expression ());
11350 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11352 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11353 | SEC_READONLY
| SEC_RELOC
11355 if (strcmp (TARGET_OS
, "elf") != 0)
11356 record_alignment (seg
, 4);
11358 demand_empty_rest_of_line ();
11362 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11363 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11365 bfd_set_section_flags (stdoutput
, seg
,
11366 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11367 if (strcmp (TARGET_OS
, "elf") != 0)
11368 record_alignment (seg
, 4);
11370 demand_empty_rest_of_line ();
11378 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11381 char *section_name
;
11386 int section_entry_size
;
11387 int section_alignment
;
11389 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11392 section_name
= input_line_pointer
;
11393 c
= get_symbol_end ();
11395 next_c
= *(input_line_pointer
+ 1);
11397 /* Do we have .section Name<,"flags">? */
11398 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11400 /* just after name is now '\0'. */
11401 *input_line_pointer
= c
;
11402 input_line_pointer
= section_name
;
11403 obj_elf_section (ignore
);
11406 input_line_pointer
++;
11408 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11410 section_type
= get_absolute_expression ();
11413 if (*input_line_pointer
++ == ',')
11414 section_flag
= get_absolute_expression ();
11417 if (*input_line_pointer
++ == ',')
11418 section_entry_size
= get_absolute_expression ();
11420 section_entry_size
= 0;
11421 if (*input_line_pointer
++ == ',')
11422 section_alignment
= get_absolute_expression ();
11424 section_alignment
= 0;
11426 section_name
= xstrdup (section_name
);
11428 /* When using the generic form of .section (as implemented by obj-elf.c),
11429 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11430 traditionally had to fall back on the more common @progbits instead.
11432 There's nothing really harmful in this, since bfd will correct
11433 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11434 means that, for backwards compatibiltiy, the special_section entries
11435 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11437 Even so, we shouldn't force users of the MIPS .section syntax to
11438 incorrectly label the sections as SHT_PROGBITS. The best compromise
11439 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11440 generic type-checking code. */
11441 if (section_type
== SHT_MIPS_DWARF
)
11442 section_type
= SHT_PROGBITS
;
11444 obj_elf_change_section (section_name
, section_type
, section_flag
,
11445 section_entry_size
, 0, 0, 0);
11447 if (now_seg
->name
!= section_name
)
11448 free (section_name
);
11449 #endif /* OBJ_ELF */
11453 mips_enable_auto_align (void)
11459 s_cons (int log_size
)
11463 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11464 mips_emit_delays (FALSE
);
11465 if (log_size
> 0 && auto_align
)
11466 mips_align (log_size
, 0, label
);
11467 mips_clear_insn_labels ();
11468 cons (1 << log_size
);
11472 s_float_cons (int type
)
11476 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11478 mips_emit_delays (FALSE
);
11483 mips_align (3, 0, label
);
11485 mips_align (2, 0, label
);
11488 mips_clear_insn_labels ();
11493 /* Handle .globl. We need to override it because on Irix 5 you are
11496 where foo is an undefined symbol, to mean that foo should be
11497 considered to be the address of a function. */
11500 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11507 name
= input_line_pointer
;
11508 c
= get_symbol_end ();
11509 symbolP
= symbol_find_or_make (name
);
11510 *input_line_pointer
= c
;
11511 SKIP_WHITESPACE ();
11513 /* On Irix 5, every global symbol that is not explicitly labelled as
11514 being a function is apparently labelled as being an object. */
11517 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11522 secname
= input_line_pointer
;
11523 c
= get_symbol_end ();
11524 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11526 as_bad (_("%s: no such section"), secname
);
11527 *input_line_pointer
= c
;
11529 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11530 flag
= BSF_FUNCTION
;
11533 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11535 S_SET_EXTERNAL (symbolP
);
11536 demand_empty_rest_of_line ();
11540 s_option (int x ATTRIBUTE_UNUSED
)
11545 opt
= input_line_pointer
;
11546 c
= get_symbol_end ();
11550 /* FIXME: What does this mean? */
11552 else if (strncmp (opt
, "pic", 3) == 0)
11556 i
= atoi (opt
+ 3);
11561 mips_pic
= SVR4_PIC
;
11562 mips_abicalls
= TRUE
;
11565 as_bad (_(".option pic%d not supported"), i
);
11567 if (mips_pic
== SVR4_PIC
)
11569 if (g_switch_seen
&& g_switch_value
!= 0)
11570 as_warn (_("-G may not be used with SVR4 PIC code"));
11571 g_switch_value
= 0;
11572 bfd_set_gp_size (stdoutput
, 0);
11576 as_warn (_("Unrecognized option \"%s\""), opt
);
11578 *input_line_pointer
= c
;
11579 demand_empty_rest_of_line ();
11582 /* This structure is used to hold a stack of .set values. */
11584 struct mips_option_stack
11586 struct mips_option_stack
*next
;
11587 struct mips_set_options options
;
11590 static struct mips_option_stack
*mips_opts_stack
;
11592 /* Handle the .set pseudo-op. */
11595 s_mipsset (int x ATTRIBUTE_UNUSED
)
11597 char *name
= input_line_pointer
, ch
;
11599 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11600 ++input_line_pointer
;
11601 ch
= *input_line_pointer
;
11602 *input_line_pointer
= '\0';
11604 if (strcmp (name
, "reorder") == 0)
11606 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11608 /* If we still have pending nops, we can discard them. The
11609 usual nop handling will insert any that are still
11611 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11612 * (mips_opts
.mips16
? 2 : 4));
11613 prev_nop_frag
= NULL
;
11615 mips_opts
.noreorder
= 0;
11617 else if (strcmp (name
, "noreorder") == 0)
11619 mips_emit_delays (TRUE
);
11620 mips_opts
.noreorder
= 1;
11621 mips_any_noreorder
= 1;
11623 else if (strcmp (name
, "at") == 0)
11625 mips_opts
.noat
= 0;
11627 else if (strcmp (name
, "noat") == 0)
11629 mips_opts
.noat
= 1;
11631 else if (strcmp (name
, "macro") == 0)
11633 mips_opts
.warn_about_macros
= 0;
11635 else if (strcmp (name
, "nomacro") == 0)
11637 if (mips_opts
.noreorder
== 0)
11638 as_bad (_("`noreorder' must be set before `nomacro'"));
11639 mips_opts
.warn_about_macros
= 1;
11641 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11643 mips_opts
.nomove
= 0;
11645 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11647 mips_opts
.nomove
= 1;
11649 else if (strcmp (name
, "bopt") == 0)
11651 mips_opts
.nobopt
= 0;
11653 else if (strcmp (name
, "nobopt") == 0)
11655 mips_opts
.nobopt
= 1;
11657 else if (strcmp (name
, "mips16") == 0
11658 || strcmp (name
, "MIPS-16") == 0)
11659 mips_opts
.mips16
= 1;
11660 else if (strcmp (name
, "nomips16") == 0
11661 || strcmp (name
, "noMIPS-16") == 0)
11662 mips_opts
.mips16
= 0;
11663 else if (strcmp (name
, "mips3d") == 0)
11664 mips_opts
.ase_mips3d
= 1;
11665 else if (strcmp (name
, "nomips3d") == 0)
11666 mips_opts
.ase_mips3d
= 0;
11667 else if (strcmp (name
, "mdmx") == 0)
11668 mips_opts
.ase_mdmx
= 1;
11669 else if (strcmp (name
, "nomdmx") == 0)
11670 mips_opts
.ase_mdmx
= 0;
11671 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11675 /* Permit the user to change the ISA and architecture on the fly.
11676 Needless to say, misuse can cause serious problems. */
11677 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11680 mips_opts
.isa
= file_mips_isa
;
11681 mips_opts
.arch
= file_mips_arch
;
11683 else if (strncmp (name
, "arch=", 5) == 0)
11685 const struct mips_cpu_info
*p
;
11687 p
= mips_parse_cpu("internal use", name
+ 5);
11689 as_bad (_("unknown architecture %s"), name
+ 5);
11692 mips_opts
.arch
= p
->cpu
;
11693 mips_opts
.isa
= p
->isa
;
11696 else if (strncmp (name
, "mips", 4) == 0)
11698 const struct mips_cpu_info
*p
;
11700 p
= mips_parse_cpu("internal use", name
);
11702 as_bad (_("unknown ISA level %s"), name
+ 4);
11705 mips_opts
.arch
= p
->cpu
;
11706 mips_opts
.isa
= p
->isa
;
11710 as_bad (_("unknown ISA or architecture %s"), name
);
11712 switch (mips_opts
.isa
)
11720 mips_opts
.gp32
= 1;
11721 mips_opts
.fp32
= 1;
11728 mips_opts
.gp32
= 0;
11729 mips_opts
.fp32
= 0;
11732 as_bad (_("unknown ISA level %s"), name
+ 4);
11737 mips_opts
.gp32
= file_mips_gp32
;
11738 mips_opts
.fp32
= file_mips_fp32
;
11741 else if (strcmp (name
, "autoextend") == 0)
11742 mips_opts
.noautoextend
= 0;
11743 else if (strcmp (name
, "noautoextend") == 0)
11744 mips_opts
.noautoextend
= 1;
11745 else if (strcmp (name
, "push") == 0)
11747 struct mips_option_stack
*s
;
11749 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11750 s
->next
= mips_opts_stack
;
11751 s
->options
= mips_opts
;
11752 mips_opts_stack
= s
;
11754 else if (strcmp (name
, "pop") == 0)
11756 struct mips_option_stack
*s
;
11758 s
= mips_opts_stack
;
11760 as_bad (_(".set pop with no .set push"));
11763 /* If we're changing the reorder mode we need to handle
11764 delay slots correctly. */
11765 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11766 mips_emit_delays (TRUE
);
11767 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11769 if (prev_nop_frag
!= NULL
)
11771 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11772 * (mips_opts
.mips16
? 2 : 4));
11773 prev_nop_frag
= NULL
;
11777 mips_opts
= s
->options
;
11778 mips_opts_stack
= s
->next
;
11782 else if (strcmp (name
, "sym32") == 0)
11783 mips_opts
.sym32
= TRUE
;
11784 else if (strcmp (name
, "nosym32") == 0)
11785 mips_opts
.sym32
= FALSE
;
11788 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11790 *input_line_pointer
= ch
;
11791 demand_empty_rest_of_line ();
11794 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11795 .option pic2. It means to generate SVR4 PIC calls. */
11798 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11800 mips_pic
= SVR4_PIC
;
11801 mips_abicalls
= TRUE
;
11803 if (g_switch_seen
&& g_switch_value
!= 0)
11804 as_warn (_("-G may not be used with SVR4 PIC code"));
11805 g_switch_value
= 0;
11807 bfd_set_gp_size (stdoutput
, 0);
11808 demand_empty_rest_of_line ();
11811 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11812 PIC code. It sets the $gp register for the function based on the
11813 function address, which is in the register named in the argument.
11814 This uses a relocation against _gp_disp, which is handled specially
11815 by the linker. The result is:
11816 lui $gp,%hi(_gp_disp)
11817 addiu $gp,$gp,%lo(_gp_disp)
11818 addu $gp,$gp,.cpload argument
11819 The .cpload argument is normally $25 == $t9.
11821 The -mno-shared option changes this to:
11822 lui $gp,%hi(__gnu_local_gp)
11823 addiu $gp,$gp,%lo(__gnu_local_gp)
11824 and the argument is ignored. This saves an instruction, but the
11825 resulting code is not position independent; it uses an absolute
11826 address for __gnu_local_gp. Thus code assembled with -mno-shared
11827 can go into an ordinary executable, but not into a shared library. */
11830 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11836 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11837 .cpload is ignored. */
11838 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11844 /* .cpload should be in a .set noreorder section. */
11845 if (mips_opts
.noreorder
== 0)
11846 as_warn (_(".cpload not in noreorder section"));
11848 reg
= tc_get_register (0);
11850 /* If we need to produce a 64-bit address, we are better off using
11851 the default instruction sequence. */
11852 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11854 ex
.X_op
= O_symbol
;
11855 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11857 ex
.X_op_symbol
= NULL
;
11858 ex
.X_add_number
= 0;
11860 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11861 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11864 macro_build_lui (&ex
, mips_gp_register
);
11865 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11866 mips_gp_register
, BFD_RELOC_LO16
);
11868 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11869 mips_gp_register
, reg
);
11872 demand_empty_rest_of_line ();
11875 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11876 .cpsetup $reg1, offset|$reg2, label
11878 If offset is given, this results in:
11879 sd $gp, offset($sp)
11880 lui $gp, %hi(%neg(%gp_rel(label)))
11881 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11882 daddu $gp, $gp, $reg1
11884 If $reg2 is given, this results in:
11885 daddu $reg2, $gp, $0
11886 lui $gp, %hi(%neg(%gp_rel(label)))
11887 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11888 daddu $gp, $gp, $reg1
11889 $reg1 is normally $25 == $t9.
11891 The -mno-shared option replaces the last three instructions with
11893 addiu $gp,$gp,%lo(_gp)
11897 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11899 expressionS ex_off
;
11900 expressionS ex_sym
;
11903 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11904 We also need NewABI support. */
11905 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11911 reg1
= tc_get_register (0);
11912 SKIP_WHITESPACE ();
11913 if (*input_line_pointer
!= ',')
11915 as_bad (_("missing argument separator ',' for .cpsetup"));
11919 ++input_line_pointer
;
11920 SKIP_WHITESPACE ();
11921 if (*input_line_pointer
== '$')
11923 mips_cpreturn_register
= tc_get_register (0);
11924 mips_cpreturn_offset
= -1;
11928 mips_cpreturn_offset
= get_absolute_expression ();
11929 mips_cpreturn_register
= -1;
11931 SKIP_WHITESPACE ();
11932 if (*input_line_pointer
!= ',')
11934 as_bad (_("missing argument separator ',' for .cpsetup"));
11938 ++input_line_pointer
;
11939 SKIP_WHITESPACE ();
11940 expression (&ex_sym
);
11943 if (mips_cpreturn_register
== -1)
11945 ex_off
.X_op
= O_constant
;
11946 ex_off
.X_add_symbol
= NULL
;
11947 ex_off
.X_op_symbol
= NULL
;
11948 ex_off
.X_add_number
= mips_cpreturn_offset
;
11950 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11951 BFD_RELOC_LO16
, SP
);
11954 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11955 mips_gp_register
, 0);
11957 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11959 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11960 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11963 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11964 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11965 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11967 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11968 mips_gp_register
, reg1
);
11974 ex
.X_op
= O_symbol
;
11975 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11976 ex
.X_op_symbol
= NULL
;
11977 ex
.X_add_number
= 0;
11979 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11980 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11982 macro_build_lui (&ex
, mips_gp_register
);
11983 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11984 mips_gp_register
, BFD_RELOC_LO16
);
11989 demand_empty_rest_of_line ();
11993 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11995 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11996 .cplocal is ignored. */
11997 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12003 mips_gp_register
= tc_get_register (0);
12004 demand_empty_rest_of_line ();
12007 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12008 offset from $sp. The offset is remembered, and after making a PIC
12009 call $gp is restored from that location. */
12012 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12016 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12017 .cprestore is ignored. */
12018 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12024 mips_cprestore_offset
= get_absolute_expression ();
12025 mips_cprestore_valid
= 1;
12027 ex
.X_op
= O_constant
;
12028 ex
.X_add_symbol
= NULL
;
12029 ex
.X_op_symbol
= NULL
;
12030 ex
.X_add_number
= mips_cprestore_offset
;
12033 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12034 SP
, HAVE_64BIT_ADDRESSES
);
12037 demand_empty_rest_of_line ();
12040 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12041 was given in the preceding .cpsetup, it results in:
12042 ld $gp, offset($sp)
12044 If a register $reg2 was given there, it results in:
12045 daddu $gp, $reg2, $0
12048 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12052 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12053 We also need NewABI support. */
12054 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12061 if (mips_cpreturn_register
== -1)
12063 ex
.X_op
= O_constant
;
12064 ex
.X_add_symbol
= NULL
;
12065 ex
.X_op_symbol
= NULL
;
12066 ex
.X_add_number
= mips_cpreturn_offset
;
12068 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12071 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12072 mips_cpreturn_register
, 0);
12075 demand_empty_rest_of_line ();
12078 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12079 code. It sets the offset to use in gp_rel relocations. */
12082 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12084 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12085 We also need NewABI support. */
12086 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12092 mips_gprel_offset
= get_absolute_expression ();
12094 demand_empty_rest_of_line ();
12097 /* Handle the .gpword pseudo-op. This is used when generating PIC
12098 code. It generates a 32 bit GP relative reloc. */
12101 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12107 /* When not generating PIC code, this is treated as .word. */
12108 if (mips_pic
!= SVR4_PIC
)
12114 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12115 mips_emit_delays (TRUE
);
12117 mips_align (2, 0, label
);
12118 mips_clear_insn_labels ();
12122 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12124 as_bad (_("Unsupported use of .gpword"));
12125 ignore_rest_of_line ();
12129 md_number_to_chars (p
, 0, 4);
12130 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12131 BFD_RELOC_GPREL32
);
12133 demand_empty_rest_of_line ();
12137 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12143 /* When not generating PIC code, this is treated as .dword. */
12144 if (mips_pic
!= SVR4_PIC
)
12150 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12151 mips_emit_delays (TRUE
);
12153 mips_align (3, 0, label
);
12154 mips_clear_insn_labels ();
12158 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12160 as_bad (_("Unsupported use of .gpdword"));
12161 ignore_rest_of_line ();
12165 md_number_to_chars (p
, 0, 8);
12166 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12167 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12169 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12170 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12171 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12173 demand_empty_rest_of_line ();
12176 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12177 tables in SVR4 PIC code. */
12180 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12184 /* This is ignored when not generating SVR4 PIC code. */
12185 if (mips_pic
!= SVR4_PIC
)
12191 /* Add $gp to the register named as an argument. */
12193 reg
= tc_get_register (0);
12194 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12197 demand_empty_rest_of_line ();
12200 /* Handle the .insn pseudo-op. This marks instruction labels in
12201 mips16 mode. This permits the linker to handle them specially,
12202 such as generating jalx instructions when needed. We also make
12203 them odd for the duration of the assembly, in order to generate the
12204 right sort of code. We will make them even in the adjust_symtab
12205 routine, while leaving them marked. This is convenient for the
12206 debugger and the disassembler. The linker knows to make them odd
12210 s_insn (int ignore ATTRIBUTE_UNUSED
)
12212 mips16_mark_labels ();
12214 demand_empty_rest_of_line ();
12217 /* Handle a .stabn directive. We need these in order to mark a label
12218 as being a mips16 text label correctly. Sometimes the compiler
12219 will emit a label, followed by a .stabn, and then switch sections.
12220 If the label and .stabn are in mips16 mode, then the label is
12221 really a mips16 text label. */
12224 s_mips_stab (int type
)
12227 mips16_mark_labels ();
12232 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12236 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12243 name
= input_line_pointer
;
12244 c
= get_symbol_end ();
12245 symbolP
= symbol_find_or_make (name
);
12246 S_SET_WEAK (symbolP
);
12247 *input_line_pointer
= c
;
12249 SKIP_WHITESPACE ();
12251 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12253 if (S_IS_DEFINED (symbolP
))
12255 as_bad ("ignoring attempt to redefine symbol %s",
12256 S_GET_NAME (symbolP
));
12257 ignore_rest_of_line ();
12261 if (*input_line_pointer
== ',')
12263 ++input_line_pointer
;
12264 SKIP_WHITESPACE ();
12268 if (exp
.X_op
!= O_symbol
)
12270 as_bad ("bad .weakext directive");
12271 ignore_rest_of_line ();
12274 symbol_set_value_expression (symbolP
, &exp
);
12277 demand_empty_rest_of_line ();
12280 /* Parse a register string into a number. Called from the ECOFF code
12281 to parse .frame. The argument is non-zero if this is the frame
12282 register, so that we can record it in mips_frame_reg. */
12285 tc_get_register (int frame
)
12289 SKIP_WHITESPACE ();
12290 if (*input_line_pointer
++ != '$')
12292 as_warn (_("expected `$'"));
12295 else if (ISDIGIT (*input_line_pointer
))
12297 reg
= get_absolute_expression ();
12298 if (reg
< 0 || reg
>= 32)
12300 as_warn (_("Bad register number"));
12306 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12309 input_line_pointer
+= 2;
12311 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12314 input_line_pointer
+= 2;
12316 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12319 input_line_pointer
+= 2;
12321 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12324 input_line_pointer
+= 2;
12326 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12329 input_line_pointer
+= 2;
12331 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12334 input_line_pointer
+= 3;
12336 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12339 input_line_pointer
+= 3;
12341 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12344 input_line_pointer
+= 4;
12348 as_warn (_("Unrecognized register name"));
12350 while (ISALNUM(*input_line_pointer
))
12351 input_line_pointer
++;
12356 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12357 mips_frame_reg_valid
= 1;
12358 mips_cprestore_valid
= 0;
12364 md_section_align (asection
*seg
, valueT addr
)
12366 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12369 /* We don't need to align ELF sections to the full alignment.
12370 However, Irix 5 may prefer that we align them at least to a 16
12371 byte boundary. We don't bother to align the sections if we are
12372 targeted for an embedded system. */
12373 if (strcmp (TARGET_OS
, "elf") == 0)
12379 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12382 /* Utility routine, called from above as well. If called while the
12383 input file is still being read, it's only an approximation. (For
12384 example, a symbol may later become defined which appeared to be
12385 undefined earlier.) */
12388 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12393 if (g_switch_value
> 0)
12395 const char *symname
;
12398 /* Find out whether this symbol can be referenced off the $gp
12399 register. It can be if it is smaller than the -G size or if
12400 it is in the .sdata or .sbss section. Certain symbols can
12401 not be referenced off the $gp, although it appears as though
12403 symname
= S_GET_NAME (sym
);
12404 if (symname
!= (const char *) NULL
12405 && (strcmp (symname
, "eprol") == 0
12406 || strcmp (symname
, "etext") == 0
12407 || strcmp (symname
, "_gp") == 0
12408 || strcmp (symname
, "edata") == 0
12409 || strcmp (symname
, "_fbss") == 0
12410 || strcmp (symname
, "_fdata") == 0
12411 || strcmp (symname
, "_ftext") == 0
12412 || strcmp (symname
, "end") == 0
12413 || strcmp (symname
, "_gp_disp") == 0))
12415 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12417 #ifndef NO_ECOFF_DEBUGGING
12418 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12419 && (symbol_get_obj (sym
)->ecoff_extern_size
12420 <= g_switch_value
))
12422 /* We must defer this decision until after the whole
12423 file has been read, since there might be a .extern
12424 after the first use of this symbol. */
12425 || (before_relaxing
12426 #ifndef NO_ECOFF_DEBUGGING
12427 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12429 && S_GET_VALUE (sym
) == 0)
12430 || (S_GET_VALUE (sym
) != 0
12431 && S_GET_VALUE (sym
) <= g_switch_value
)))
12435 const char *segname
;
12437 segname
= segment_name (S_GET_SEGMENT (sym
));
12438 assert (strcmp (segname
, ".lit8") != 0
12439 && strcmp (segname
, ".lit4") != 0);
12440 change
= (strcmp (segname
, ".sdata") != 0
12441 && strcmp (segname
, ".sbss") != 0
12442 && strncmp (segname
, ".sdata.", 7) != 0
12443 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12448 /* We are not optimizing for the $gp register. */
12453 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12456 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12459 bfd_boolean linkonce
;
12461 /* Handle the case of a symbol equated to another symbol. */
12462 while (symbol_equated_reloc_p (sym
))
12466 /* It's possible to get a loop here in a badly written
12468 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12474 symsec
= S_GET_SEGMENT (sym
);
12476 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12478 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12480 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12484 /* The GNU toolchain uses an extension for ELF: a section
12485 beginning with the magic string .gnu.linkonce is a linkonce
12487 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12488 sizeof ".gnu.linkonce" - 1) == 0)
12492 /* This must duplicate the test in adjust_reloc_syms. */
12493 return (symsec
!= &bfd_und_section
12494 && symsec
!= &bfd_abs_section
12495 && ! bfd_is_com_section (symsec
)
12498 /* A global or weak symbol is treated as external. */
12499 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12500 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12506 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12507 extended opcode. SEC is the section the frag is in. */
12510 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12513 register const struct mips16_immed_operand
*op
;
12515 int mintiny
, maxtiny
;
12519 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12521 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12524 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12525 op
= mips16_immed_operands
;
12526 while (op
->type
!= type
)
12529 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12534 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12537 maxtiny
= 1 << op
->nbits
;
12542 maxtiny
= (1 << op
->nbits
) - 1;
12547 mintiny
= - (1 << (op
->nbits
- 1));
12548 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12551 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12552 val
= S_GET_VALUE (fragp
->fr_symbol
);
12553 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12559 /* We won't have the section when we are called from
12560 mips_relax_frag. However, we will always have been called
12561 from md_estimate_size_before_relax first. If this is a
12562 branch to a different section, we mark it as such. If SEC is
12563 NULL, and the frag is not marked, then it must be a branch to
12564 the same section. */
12567 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12572 /* Must have been called from md_estimate_size_before_relax. */
12575 fragp
->fr_subtype
=
12576 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12578 /* FIXME: We should support this, and let the linker
12579 catch branches and loads that are out of range. */
12580 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12581 _("unsupported PC relative reference to different section"));
12585 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12586 /* Assume non-extended on the first relaxation pass.
12587 The address we have calculated will be bogus if this is
12588 a forward branch to another frag, as the forward frag
12589 will have fr_address == 0. */
12593 /* In this case, we know for sure that the symbol fragment is in
12594 the same section. If the relax_marker of the symbol fragment
12595 differs from the relax_marker of this fragment, we have not
12596 yet adjusted the symbol fragment fr_address. We want to add
12597 in STRETCH in order to get a better estimate of the address.
12598 This particularly matters because of the shift bits. */
12600 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12604 /* Adjust stretch for any alignment frag. Note that if have
12605 been expanding the earlier code, the symbol may be
12606 defined in what appears to be an earlier frag. FIXME:
12607 This doesn't handle the fr_subtype field, which specifies
12608 a maximum number of bytes to skip when doing an
12610 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12612 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12615 stretch
= - ((- stretch
)
12616 & ~ ((1 << (int) f
->fr_offset
) - 1));
12618 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12627 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12629 /* The base address rules are complicated. The base address of
12630 a branch is the following instruction. The base address of a
12631 PC relative load or add is the instruction itself, but if it
12632 is in a delay slot (in which case it can not be extended) use
12633 the address of the instruction whose delay slot it is in. */
12634 if (type
== 'p' || type
== 'q')
12638 /* If we are currently assuming that this frag should be
12639 extended, then, the current address is two bytes
12641 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12644 /* Ignore the low bit in the target, since it will be set
12645 for a text label. */
12646 if ((val
& 1) != 0)
12649 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12651 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12654 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12656 /* Branch offsets have an implicit 0 in the lowest bit. */
12657 if (type
== 'p' || type
== 'q')
12660 /* If any of the shifted bits are set, we must use an extended
12661 opcode. If the address depends on the size of this
12662 instruction, this can lead to a loop, so we arrange to always
12663 use an extended opcode. We only check this when we are in
12664 the main relaxation loop, when SEC is NULL. */
12665 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12667 fragp
->fr_subtype
=
12668 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12672 /* If we are about to mark a frag as extended because the value
12673 is precisely maxtiny + 1, then there is a chance of an
12674 infinite loop as in the following code:
12679 In this case when the la is extended, foo is 0x3fc bytes
12680 away, so the la can be shrunk, but then foo is 0x400 away, so
12681 the la must be extended. To avoid this loop, we mark the
12682 frag as extended if it was small, and is about to become
12683 extended with a value of maxtiny + 1. */
12684 if (val
== ((maxtiny
+ 1) << op
->shift
)
12685 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12688 fragp
->fr_subtype
=
12689 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12693 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12694 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12696 if ((val
& ((1 << op
->shift
) - 1)) != 0
12697 || val
< (mintiny
<< op
->shift
)
12698 || val
> (maxtiny
<< op
->shift
))
12704 /* Compute the length of a branch sequence, and adjust the
12705 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12706 worst-case length is computed, with UPDATE being used to indicate
12707 whether an unconditional (-1), branch-likely (+1) or regular (0)
12708 branch is to be computed. */
12710 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12712 bfd_boolean toofar
;
12716 && S_IS_DEFINED (fragp
->fr_symbol
)
12717 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12722 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12724 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12728 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12731 /* If the symbol is not defined or it's in a different segment,
12732 assume the user knows what's going on and emit a short
12738 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12740 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12741 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12742 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12748 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12751 if (mips_pic
!= NO_PIC
)
12753 /* Additional space for PIC loading of target address. */
12755 if (mips_opts
.isa
== ISA_MIPS1
)
12756 /* Additional space for $at-stabilizing nop. */
12760 /* If branch is conditional. */
12761 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12768 /* Estimate the size of a frag before relaxing. Unless this is the
12769 mips16, we are not really relaxing here, and the final size is
12770 encoded in the subtype information. For the mips16, we have to
12771 decide whether we are using an extended opcode or not. */
12774 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12778 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12781 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12783 return fragp
->fr_var
;
12786 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12787 /* We don't want to modify the EXTENDED bit here; it might get us
12788 into infinite loops. We change it only in mips_relax_frag(). */
12789 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12791 if (mips_pic
== NO_PIC
)
12792 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12793 else if (mips_pic
== SVR4_PIC
)
12794 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12800 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12801 return -RELAX_FIRST (fragp
->fr_subtype
);
12804 return -RELAX_SECOND (fragp
->fr_subtype
);
12807 /* This is called to see whether a reloc against a defined symbol
12808 should be converted into a reloc against a section. */
12811 mips_fix_adjustable (fixS
*fixp
)
12813 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12814 about the format of the offset in the .o file. */
12815 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12818 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12819 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12822 if (fixp
->fx_addsy
== NULL
)
12825 /* If symbol SYM is in a mergeable section, relocations of the form
12826 SYM + 0 can usually be made section-relative. The mergeable data
12827 is then identified by the section offset rather than by the symbol.
12829 However, if we're generating REL LO16 relocations, the offset is split
12830 between the LO16 and parterning high part relocation. The linker will
12831 need to recalculate the complete offset in order to correctly identify
12834 The linker has traditionally not looked for the parterning high part
12835 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12836 placed anywhere. Rather than break backwards compatibility by changing
12837 this, it seems better not to force the issue, and instead keep the
12838 original symbol. This will work with either linker behavior. */
12839 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12840 && HAVE_IN_PLACE_ADDENDS
12841 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12845 /* Don't adjust relocations against mips16 symbols, so that the linker
12846 can find them if it needs to set up a stub. */
12847 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12848 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12849 && fixp
->fx_subsy
== NULL
)
12856 /* Translate internal representation of relocation info to BFD target
12860 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12862 static arelent
*retval
[4];
12864 bfd_reloc_code_real_type code
;
12866 memset (retval
, 0, sizeof(retval
));
12867 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12868 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12869 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12870 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12872 assert (! fixp
->fx_pcrel
);
12873 reloc
->addend
= fixp
->fx_addnumber
;
12875 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12876 entry to be used in the relocation's section offset. */
12877 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12879 reloc
->address
= reloc
->addend
;
12883 code
= fixp
->fx_r_type
;
12885 /* To support a PC relative reloc, we used a Cygnus extension.
12886 We check for that here to make sure that we don't let such a
12887 reloc escape normally. (FIXME: This was formerly used by
12888 embedded-PIC support, but is now used by branch handling in
12889 general. That probably should be fixed.) */
12890 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12891 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12892 && code
== BFD_RELOC_16_PCREL_S2
)
12893 reloc
->howto
= NULL
;
12895 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12897 if (reloc
->howto
== NULL
)
12899 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12900 _("Can not represent %s relocation in this object file format"),
12901 bfd_get_reloc_code_name (code
));
12908 /* Relax a machine dependent frag. This returns the amount by which
12909 the current size of the frag should change. */
12912 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12914 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12916 offsetT old_var
= fragp
->fr_var
;
12918 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12920 return fragp
->fr_var
- old_var
;
12923 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12926 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12928 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12930 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12935 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12937 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12944 /* Convert a machine dependent frag. */
12947 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12949 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12952 unsigned long insn
;
12956 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12958 if (target_big_endian
)
12959 insn
= bfd_getb32 (buf
);
12961 insn
= bfd_getl32 (buf
);
12963 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12965 /* We generate a fixup instead of applying it right now
12966 because, if there are linker relaxations, we're going to
12967 need the relocations. */
12968 exp
.X_op
= O_symbol
;
12969 exp
.X_add_symbol
= fragp
->fr_symbol
;
12970 exp
.X_add_number
= fragp
->fr_offset
;
12972 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12974 BFD_RELOC_16_PCREL_S2
);
12975 fixp
->fx_file
= fragp
->fr_file
;
12976 fixp
->fx_line
= fragp
->fr_line
;
12978 md_number_to_chars ((char *) buf
, insn
, 4);
12985 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12986 _("relaxed out-of-range branch into a jump"));
12988 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12991 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12993 /* Reverse the branch. */
12994 switch ((insn
>> 28) & 0xf)
12997 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12998 have the condition reversed by tweaking a single
12999 bit, and their opcodes all have 0x4???????. */
13000 assert ((insn
& 0xf1000000) == 0x41000000);
13001 insn
^= 0x00010000;
13005 /* bltz 0x04000000 bgez 0x04010000
13006 bltzal 0x04100000 bgezal 0x04110000 */
13007 assert ((insn
& 0xfc0e0000) == 0x04000000);
13008 insn
^= 0x00010000;
13012 /* beq 0x10000000 bne 0x14000000
13013 blez 0x18000000 bgtz 0x1c000000 */
13014 insn
^= 0x04000000;
13022 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13024 /* Clear the and-link bit. */
13025 assert ((insn
& 0xfc1c0000) == 0x04100000);
13027 /* bltzal 0x04100000 bgezal 0x04110000
13028 bltzall 0x04120000 bgezall 0x04130000 */
13029 insn
&= ~0x00100000;
13032 /* Branch over the branch (if the branch was likely) or the
13033 full jump (not likely case). Compute the offset from the
13034 current instruction to branch to. */
13035 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13039 /* How many bytes in instructions we've already emitted? */
13040 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13041 /* How many bytes in instructions from here to the end? */
13042 i
= fragp
->fr_var
- i
;
13044 /* Convert to instruction count. */
13046 /* Branch counts from the next instruction. */
13049 /* Branch over the jump. */
13050 md_number_to_chars ((char *) buf
, insn
, 4);
13054 md_number_to_chars ((char *) buf
, 0, 4);
13057 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13059 /* beql $0, $0, 2f */
13061 /* Compute the PC offset from the current instruction to
13062 the end of the variable frag. */
13063 /* How many bytes in instructions we've already emitted? */
13064 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13065 /* How many bytes in instructions from here to the end? */
13066 i
= fragp
->fr_var
- i
;
13067 /* Convert to instruction count. */
13069 /* Don't decrement i, because we want to branch over the
13073 md_number_to_chars ((char *) buf
, insn
, 4);
13076 md_number_to_chars ((char *) buf
, 0, 4);
13081 if (mips_pic
== NO_PIC
)
13084 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13085 ? 0x0c000000 : 0x08000000);
13086 exp
.X_op
= O_symbol
;
13087 exp
.X_add_symbol
= fragp
->fr_symbol
;
13088 exp
.X_add_number
= fragp
->fr_offset
;
13090 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13091 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13092 fixp
->fx_file
= fragp
->fr_file
;
13093 fixp
->fx_line
= fragp
->fr_line
;
13095 md_number_to_chars ((char *) buf
, insn
, 4);
13100 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13101 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13102 exp
.X_op
= O_symbol
;
13103 exp
.X_add_symbol
= fragp
->fr_symbol
;
13104 exp
.X_add_number
= fragp
->fr_offset
;
13106 if (fragp
->fr_offset
)
13108 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13109 exp
.X_add_number
= 0;
13112 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13113 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13114 fixp
->fx_file
= fragp
->fr_file
;
13115 fixp
->fx_line
= fragp
->fr_line
;
13117 md_number_to_chars ((char *) buf
, insn
, 4);
13120 if (mips_opts
.isa
== ISA_MIPS1
)
13123 md_number_to_chars ((char *) buf
, 0, 4);
13127 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13128 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13130 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13131 4, &exp
, 0, BFD_RELOC_LO16
);
13132 fixp
->fx_file
= fragp
->fr_file
;
13133 fixp
->fx_line
= fragp
->fr_line
;
13135 md_number_to_chars ((char *) buf
, insn
, 4);
13139 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13144 md_number_to_chars ((char *) buf
, insn
, 4);
13149 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13150 + fragp
->fr_fix
+ fragp
->fr_var
);
13152 fragp
->fr_fix
+= fragp
->fr_var
;
13157 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13160 register const struct mips16_immed_operand
*op
;
13161 bfd_boolean small
, ext
;
13164 unsigned long insn
;
13165 bfd_boolean use_extend
;
13166 unsigned short extend
;
13168 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13169 op
= mips16_immed_operands
;
13170 while (op
->type
!= type
)
13173 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13184 resolve_symbol_value (fragp
->fr_symbol
);
13185 val
= S_GET_VALUE (fragp
->fr_symbol
);
13190 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13192 /* The rules for the base address of a PC relative reloc are
13193 complicated; see mips16_extended_frag. */
13194 if (type
== 'p' || type
== 'q')
13199 /* Ignore the low bit in the target, since it will be
13200 set for a text label. */
13201 if ((val
& 1) != 0)
13204 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13206 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13209 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13212 /* Make sure the section winds up with the alignment we have
13215 record_alignment (asec
, op
->shift
);
13219 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13220 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13221 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13222 _("extended instruction in delay slot"));
13224 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13226 if (target_big_endian
)
13227 insn
= bfd_getb16 (buf
);
13229 insn
= bfd_getl16 (buf
);
13231 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13232 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13233 small
, ext
, &insn
, &use_extend
, &extend
);
13237 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13238 fragp
->fr_fix
+= 2;
13242 md_number_to_chars ((char *) buf
, insn
, 2);
13243 fragp
->fr_fix
+= 2;
13251 first
= RELAX_FIRST (fragp
->fr_subtype
);
13252 second
= RELAX_SECOND (fragp
->fr_subtype
);
13253 fixp
= (fixS
*) fragp
->fr_opcode
;
13255 /* Possibly emit a warning if we've chosen the longer option. */
13256 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13257 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13259 const char *msg
= macro_warning (fragp
->fr_subtype
);
13261 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13264 /* Go through all the fixups for the first sequence. Disable them
13265 (by marking them as done) if we're going to use the second
13266 sequence instead. */
13268 && fixp
->fx_frag
== fragp
13269 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13271 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13273 fixp
= fixp
->fx_next
;
13276 /* Go through the fixups for the second sequence. Disable them if
13277 we're going to use the first sequence, otherwise adjust their
13278 addresses to account for the relaxation. */
13279 while (fixp
&& fixp
->fx_frag
== fragp
)
13281 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13282 fixp
->fx_where
-= first
;
13285 fixp
= fixp
->fx_next
;
13288 /* Now modify the frag contents. */
13289 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13293 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13294 memmove (start
, start
+ first
, second
);
13295 fragp
->fr_fix
-= first
;
13298 fragp
->fr_fix
-= second
;
13304 /* This function is called after the relocs have been generated.
13305 We've been storing mips16 text labels as odd. Here we convert them
13306 back to even for the convenience of the debugger. */
13309 mips_frob_file_after_relocs (void)
13312 unsigned int count
, i
;
13314 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13317 syms
= bfd_get_outsymbols (stdoutput
);
13318 count
= bfd_get_symcount (stdoutput
);
13319 for (i
= 0; i
< count
; i
++, syms
++)
13321 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13322 && ((*syms
)->value
& 1) != 0)
13324 (*syms
)->value
&= ~1;
13325 /* If the symbol has an odd size, it was probably computed
13326 incorrectly, so adjust that as well. */
13327 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13328 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13335 /* This function is called whenever a label is defined. It is used
13336 when handling branch delays; if a branch has a label, we assume we
13337 can not move it. */
13340 mips_define_label (symbolS
*sym
)
13342 struct insn_label_list
*l
;
13344 if (free_insn_labels
== NULL
)
13345 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13348 l
= free_insn_labels
;
13349 free_insn_labels
= l
->next
;
13353 l
->next
= insn_labels
;
13357 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13359 /* Some special processing for a MIPS ELF file. */
13362 mips_elf_final_processing (void)
13364 /* Write out the register information. */
13365 if (mips_abi
!= N64_ABI
)
13369 s
.ri_gprmask
= mips_gprmask
;
13370 s
.ri_cprmask
[0] = mips_cprmask
[0];
13371 s
.ri_cprmask
[1] = mips_cprmask
[1];
13372 s
.ri_cprmask
[2] = mips_cprmask
[2];
13373 s
.ri_cprmask
[3] = mips_cprmask
[3];
13374 /* The gp_value field is set by the MIPS ELF backend. */
13376 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13377 ((Elf32_External_RegInfo
*)
13378 mips_regmask_frag
));
13382 Elf64_Internal_RegInfo s
;
13384 s
.ri_gprmask
= mips_gprmask
;
13386 s
.ri_cprmask
[0] = mips_cprmask
[0];
13387 s
.ri_cprmask
[1] = mips_cprmask
[1];
13388 s
.ri_cprmask
[2] = mips_cprmask
[2];
13389 s
.ri_cprmask
[3] = mips_cprmask
[3];
13390 /* The gp_value field is set by the MIPS ELF backend. */
13392 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13393 ((Elf64_External_RegInfo
*)
13394 mips_regmask_frag
));
13397 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13398 sort of BFD interface for this. */
13399 if (mips_any_noreorder
)
13400 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13401 if (mips_pic
!= NO_PIC
)
13403 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13404 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13407 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13409 /* Set MIPS ELF flags for ASEs. */
13410 if (file_ase_mips16
)
13411 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13412 #if 0 /* XXX FIXME */
13413 if (file_ase_mips3d
)
13414 elf_elfheader (stdoutput
)->e_flags
|= ???;
13417 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13419 /* Set the MIPS ELF ABI flags. */
13420 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13421 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13422 else if (mips_abi
== O64_ABI
)
13423 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13424 else if (mips_abi
== EABI_ABI
)
13426 if (!file_mips_gp32
)
13427 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13429 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13431 else if (mips_abi
== N32_ABI
)
13432 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13434 /* Nothing to do for N64_ABI. */
13436 if (mips_32bitmode
)
13437 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13440 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13442 typedef struct proc
{
13444 symbolS
*func_end_sym
;
13445 unsigned long reg_mask
;
13446 unsigned long reg_offset
;
13447 unsigned long fpreg_mask
;
13448 unsigned long fpreg_offset
;
13449 unsigned long frame_offset
;
13450 unsigned long frame_reg
;
13451 unsigned long pc_reg
;
13454 static procS cur_proc
;
13455 static procS
*cur_proc_ptr
;
13456 static int numprocs
;
13458 /* Fill in an rs_align_code fragment. */
13461 mips_handle_align (fragS
*fragp
)
13463 if (fragp
->fr_type
!= rs_align_code
)
13466 if (mips_opts
.mips16
)
13468 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13469 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13474 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13475 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13483 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13487 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13491 md_obj_begin (void)
13498 /* check for premature end, nesting errors, etc */
13500 as_warn (_("missing .end at end of assembly"));
13509 if (*input_line_pointer
== '-')
13511 ++input_line_pointer
;
13514 if (!ISDIGIT (*input_line_pointer
))
13515 as_bad (_("expected simple number"));
13516 if (input_line_pointer
[0] == '0')
13518 if (input_line_pointer
[1] == 'x')
13520 input_line_pointer
+= 2;
13521 while (ISXDIGIT (*input_line_pointer
))
13524 val
|= hex_value (*input_line_pointer
++);
13526 return negative
? -val
: val
;
13530 ++input_line_pointer
;
13531 while (ISDIGIT (*input_line_pointer
))
13534 val
|= *input_line_pointer
++ - '0';
13536 return negative
? -val
: val
;
13539 if (!ISDIGIT (*input_line_pointer
))
13541 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13542 *input_line_pointer
, *input_line_pointer
);
13543 as_warn (_("invalid number"));
13546 while (ISDIGIT (*input_line_pointer
))
13549 val
+= *input_line_pointer
++ - '0';
13551 return negative
? -val
: val
;
13554 /* The .file directive; just like the usual .file directive, but there
13555 is an initial number which is the ECOFF file index. In the non-ECOFF
13556 case .file implies DWARF-2. */
13559 s_mips_file (int x ATTRIBUTE_UNUSED
)
13561 static int first_file_directive
= 0;
13563 if (ECOFF_DEBUGGING
)
13572 filename
= dwarf2_directive_file (0);
13574 /* Versions of GCC up to 3.1 start files with a ".file"
13575 directive even for stabs output. Make sure that this
13576 ".file" is handled. Note that you need a version of GCC
13577 after 3.1 in order to support DWARF-2 on MIPS. */
13578 if (filename
!= NULL
&& ! first_file_directive
)
13580 (void) new_logical_line (filename
, -1);
13581 s_app_file_string (filename
, 0);
13583 first_file_directive
= 1;
13587 /* The .loc directive, implying DWARF-2. */
13590 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13592 if (!ECOFF_DEBUGGING
)
13593 dwarf2_directive_loc (0);
13596 /* The .end directive. */
13599 s_mips_end (int x ATTRIBUTE_UNUSED
)
13603 /* Following functions need their own .frame and .cprestore directives. */
13604 mips_frame_reg_valid
= 0;
13605 mips_cprestore_valid
= 0;
13607 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13610 demand_empty_rest_of_line ();
13615 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13616 as_warn (_(".end not in text section"));
13620 as_warn (_(".end directive without a preceding .ent directive."));
13621 demand_empty_rest_of_line ();
13627 assert (S_GET_NAME (p
));
13628 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13629 as_warn (_(".end symbol does not match .ent symbol."));
13631 if (debug_type
== DEBUG_STABS
)
13632 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13636 as_warn (_(".end directive missing or unknown symbol"));
13639 /* Create an expression to calculate the size of the function. */
13640 if (p
&& cur_proc_ptr
)
13642 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13643 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13646 exp
->X_op
= O_subtract
;
13647 exp
->X_add_symbol
= symbol_temp_new_now ();
13648 exp
->X_op_symbol
= p
;
13649 exp
->X_add_number
= 0;
13651 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13654 /* Generate a .pdr section. */
13655 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13658 segT saved_seg
= now_seg
;
13659 subsegT saved_subseg
= now_subseg
;
13664 dot
= frag_now_fix ();
13666 #ifdef md_flush_pending_output
13667 md_flush_pending_output ();
13671 subseg_set (pdr_seg
, 0);
13673 /* Write the symbol. */
13674 exp
.X_op
= O_symbol
;
13675 exp
.X_add_symbol
= p
;
13676 exp
.X_add_number
= 0;
13677 emit_expr (&exp
, 4);
13679 fragp
= frag_more (7 * 4);
13681 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13682 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13683 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13684 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13685 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13686 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13687 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13689 subseg_set (saved_seg
, saved_subseg
);
13691 #endif /* OBJ_ELF */
13693 cur_proc_ptr
= NULL
;
13696 /* The .aent and .ent directives. */
13699 s_mips_ent (int aent
)
13703 symbolP
= get_symbol ();
13704 if (*input_line_pointer
== ',')
13705 ++input_line_pointer
;
13706 SKIP_WHITESPACE ();
13707 if (ISDIGIT (*input_line_pointer
)
13708 || *input_line_pointer
== '-')
13711 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13712 as_warn (_(".ent or .aent not in text section."));
13714 if (!aent
&& cur_proc_ptr
)
13715 as_warn (_("missing .end"));
13719 /* This function needs its own .frame and .cprestore directives. */
13720 mips_frame_reg_valid
= 0;
13721 mips_cprestore_valid
= 0;
13723 cur_proc_ptr
= &cur_proc
;
13724 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13726 cur_proc_ptr
->func_sym
= symbolP
;
13728 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13732 if (debug_type
== DEBUG_STABS
)
13733 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13734 S_GET_NAME (symbolP
));
13737 demand_empty_rest_of_line ();
13740 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13741 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13742 s_mips_frame is used so that we can set the PDR information correctly.
13743 We can't use the ecoff routines because they make reference to the ecoff
13744 symbol table (in the mdebug section). */
13747 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13750 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13754 if (cur_proc_ptr
== (procS
*) NULL
)
13756 as_warn (_(".frame outside of .ent"));
13757 demand_empty_rest_of_line ();
13761 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13763 SKIP_WHITESPACE ();
13764 if (*input_line_pointer
++ != ','
13765 || get_absolute_expression_and_terminator (&val
) != ',')
13767 as_warn (_("Bad .frame directive"));
13768 --input_line_pointer
;
13769 demand_empty_rest_of_line ();
13773 cur_proc_ptr
->frame_offset
= val
;
13774 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13776 demand_empty_rest_of_line ();
13779 #endif /* OBJ_ELF */
13783 /* The .fmask and .mask directives. If the mdebug section is present
13784 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13785 embedded targets, s_mips_mask is used so that we can set the PDR
13786 information correctly. We can't use the ecoff routines because they
13787 make reference to the ecoff symbol table (in the mdebug section). */
13790 s_mips_mask (int reg_type
)
13793 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13797 if (cur_proc_ptr
== (procS
*) NULL
)
13799 as_warn (_(".mask/.fmask outside of .ent"));
13800 demand_empty_rest_of_line ();
13804 if (get_absolute_expression_and_terminator (&mask
) != ',')
13806 as_warn (_("Bad .mask/.fmask directive"));
13807 --input_line_pointer
;
13808 demand_empty_rest_of_line ();
13812 off
= get_absolute_expression ();
13814 if (reg_type
== 'F')
13816 cur_proc_ptr
->fpreg_mask
= mask
;
13817 cur_proc_ptr
->fpreg_offset
= off
;
13821 cur_proc_ptr
->reg_mask
= mask
;
13822 cur_proc_ptr
->reg_offset
= off
;
13825 demand_empty_rest_of_line ();
13828 #endif /* OBJ_ELF */
13829 s_ignore (reg_type
);
13832 /* A table describing all the processors gas knows about. Names are
13833 matched in the order listed.
13835 To ease comparison, please keep this table in the same order as
13836 gcc's mips_cpu_info_table[]. */
13837 static const struct mips_cpu_info mips_cpu_info_table
[] =
13839 /* Entries for generic ISAs */
13840 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13841 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13842 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13843 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13844 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13845 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13846 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13847 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13848 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13851 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13852 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13853 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13856 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13859 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13860 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13861 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13862 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13863 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13864 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13865 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13866 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13867 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13868 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13869 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13870 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13873 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13874 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13875 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13876 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13877 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13878 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13879 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13880 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13881 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13882 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13883 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13884 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13885 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13888 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13889 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13890 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13893 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13894 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13896 /* Broadcom SB-1 CPU core */
13897 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13904 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13905 with a final "000" replaced by "k". Ignore case.
13907 Note: this function is shared between GCC and GAS. */
13910 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13912 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13913 given
++, canonical
++;
13915 return ((*given
== 0 && *canonical
== 0)
13916 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13920 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13921 CPU name. We've traditionally allowed a lot of variation here.
13923 Note: this function is shared between GCC and GAS. */
13926 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13928 /* First see if the name matches exactly, or with a final "000"
13929 turned into "k". */
13930 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13933 /* If not, try comparing based on numerical designation alone.
13934 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13935 if (TOLOWER (*given
) == 'r')
13937 if (!ISDIGIT (*given
))
13940 /* Skip over some well-known prefixes in the canonical name,
13941 hoping to find a number there too. */
13942 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13944 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13946 else if (TOLOWER (canonical
[0]) == 'r')
13949 return mips_strict_matching_cpu_name_p (canonical
, given
);
13953 /* Parse an option that takes the name of a processor as its argument.
13954 OPTION is the name of the option and CPU_STRING is the argument.
13955 Return the corresponding processor enumeration if the CPU_STRING is
13956 recognized, otherwise report an error and return null.
13958 A similar function exists in GCC. */
13960 static const struct mips_cpu_info
*
13961 mips_parse_cpu (const char *option
, const char *cpu_string
)
13963 const struct mips_cpu_info
*p
;
13965 /* 'from-abi' selects the most compatible architecture for the given
13966 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13967 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13968 version. Look first at the -mgp options, if given, otherwise base
13969 the choice on MIPS_DEFAULT_64BIT.
13971 Treat NO_ABI like the EABIs. One reason to do this is that the
13972 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13973 architecture. This code picks MIPS I for 'mips' and MIPS III for
13974 'mips64', just as we did in the days before 'from-abi'. */
13975 if (strcasecmp (cpu_string
, "from-abi") == 0)
13977 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13978 return mips_cpu_info_from_isa (ISA_MIPS1
);
13980 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13981 return mips_cpu_info_from_isa (ISA_MIPS3
);
13983 if (file_mips_gp32
>= 0)
13984 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13986 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13991 /* 'default' has traditionally been a no-op. Probably not very useful. */
13992 if (strcasecmp (cpu_string
, "default") == 0)
13995 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13996 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13999 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14003 /* Return the canonical processor information for ISA (a member of the
14004 ISA_MIPS* enumeration). */
14006 static const struct mips_cpu_info
*
14007 mips_cpu_info_from_isa (int isa
)
14011 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14012 if (mips_cpu_info_table
[i
].is_isa
14013 && isa
== mips_cpu_info_table
[i
].isa
)
14014 return (&mips_cpu_info_table
[i
]);
14019 static const struct mips_cpu_info
*
14020 mips_cpu_info_from_arch (int arch
)
14024 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14025 if (arch
== mips_cpu_info_table
[i
].cpu
)
14026 return (&mips_cpu_info_table
[i
]);
14032 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14036 fprintf (stream
, "%24s", "");
14041 fprintf (stream
, ", ");
14045 if (*col_p
+ strlen (string
) > 72)
14047 fprintf (stream
, "\n%24s", "");
14051 fprintf (stream
, "%s", string
);
14052 *col_p
+= strlen (string
);
14058 md_show_usage (FILE *stream
)
14063 fprintf (stream
, _("\
14065 -EB generate big endian output\n\
14066 -EL generate little endian output\n\
14067 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14068 -G NUM allow referencing objects up to NUM bytes\n\
14069 implicitly with the gp register [default 8]\n"));
14070 fprintf (stream
, _("\
14071 -mips1 generate MIPS ISA I instructions\n\
14072 -mips2 generate MIPS ISA II instructions\n\
14073 -mips3 generate MIPS ISA III instructions\n\
14074 -mips4 generate MIPS ISA IV instructions\n\
14075 -mips5 generate MIPS ISA V instructions\n\
14076 -mips32 generate MIPS32 ISA instructions\n\
14077 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14078 -mips64 generate MIPS64 ISA instructions\n\
14079 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14080 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14084 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14085 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14086 show (stream
, "from-abi", &column
, &first
);
14087 fputc ('\n', stream
);
14089 fprintf (stream
, _("\
14090 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14091 -no-mCPU don't generate code specific to CPU.\n\
14092 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14096 show (stream
, "3900", &column
, &first
);
14097 show (stream
, "4010", &column
, &first
);
14098 show (stream
, "4100", &column
, &first
);
14099 show (stream
, "4650", &column
, &first
);
14100 fputc ('\n', stream
);
14102 fprintf (stream
, _("\
14103 -mips16 generate mips16 instructions\n\
14104 -no-mips16 do not generate mips16 instructions\n"));
14105 fprintf (stream
, _("\
14106 -mfix-vr4120 work around certain VR4120 errata\n\
14107 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14108 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14109 -mno-shared optimize output for executables\n\
14110 -msym32 assume all symbols have 32-bit values\n\
14111 -O0 remove unneeded NOPs, do not swap branches\n\
14112 -O remove unneeded NOPs and swap branches\n\
14113 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14114 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14115 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14117 fprintf (stream
, _("\
14118 -KPIC, -call_shared generate SVR4 position independent code\n\
14119 -non_shared do not generate position independent code\n\
14120 -xgot assume a 32 bit GOT\n\
14121 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14122 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14124 -mabi=ABI create ABI conformant object file for:\n"));
14128 show (stream
, "32", &column
, &first
);
14129 show (stream
, "o64", &column
, &first
);
14130 show (stream
, "n32", &column
, &first
);
14131 show (stream
, "64", &column
, &first
);
14132 show (stream
, "eabi", &column
, &first
);
14134 fputc ('\n', stream
);
14136 fprintf (stream
, _("\
14137 -32 create o32 ABI object file (default)\n\
14138 -n32 create n32 ABI object file\n\
14139 -64 create 64 ABI object file\n"));
14144 mips_dwarf2_format (void)
14146 if (mips_abi
== N64_ABI
)
14149 return dwarf2_format_64bit_irix
;
14151 return dwarf2_format_64bit
;
14155 return dwarf2_format_32bit
;
14159 mips_dwarf2_addr_size (void)
14161 if (mips_abi
== N64_ABI
)