1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF. */
109 /* The default target format to use. */
111 mips_target_format ()
113 switch (OUTPUT_FLAVOR
)
115 case bfd_target_aout_flavour
:
116 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
117 case bfd_target_ecoff_flavour
:
118 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
119 case bfd_target_elf_flavour
:
120 return (target_big_endian
121 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
122 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
128 /* The name of the readonly data section. */
129 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
131 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
133 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
137 /* This is the set of options which may be modified by the .set
138 pseudo-op. We use a struct so that .set push and .set pop are more
141 struct mips_set_options
143 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
144 if it has not been initialized. Changed by `.set mipsN', and the
145 -mipsN command line option, and the default CPU. */
147 /* Whether we are assembling for the mips16 processor. 0 if we are
148 not, 1 if we are, and -1 if the value has not been initialized.
149 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
150 -nomips16 command line options, and the default CPU. */
152 /* Non-zero if we should not reorder instructions. Changed by `.set
153 reorder' and `.set noreorder'. */
155 /* Non-zero if we should not permit the $at ($1) register to be used
156 in instructions. Changed by `.set at' and `.set noat'. */
158 /* Non-zero if we should warn when a macro instruction expands into
159 more than one machine instruction. Changed by `.set nomacro' and
161 int warn_about_macros
;
162 /* Non-zero if we should not move instructions. Changed by `.set
163 move', `.set volatile', `.set nomove', and `.set novolatile'. */
165 /* Non-zero if we should not optimize branches by moving the target
166 of the branch into the delay slot. Actually, we don't perform
167 this optimization anyhow. Changed by `.set bopt' and `.set
170 /* Non-zero if we should not autoextend mips16 instructions.
171 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* This is the struct we use to hold the current set of options. Note
176 that we must set the isa and mips16 fields to -1 to indicate that
177 they have not been initialized. */
179 static struct mips_set_options mips_opts
= { -1, -1 };
181 /* These variables are filled in with the masks of registers used.
182 The object format code reads them and puts them in the appropriate
184 unsigned long mips_gprmask
;
185 unsigned long mips_cprmask
[4];
187 /* MIPS ISA we are using for this output file. */
188 static int file_mips_isa
;
190 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
191 static int mips_cpu
= -1;
193 /* Whether the 4650 instructions (mad/madu) are permitted. */
194 static int mips_4650
= -1;
196 /* Whether the 4010 instructions are permitted. */
197 static int mips_4010
= -1;
199 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
200 static int mips_4100
= -1;
202 /* start-sanitize-r5900 */
203 /* Whether Toshiba r5900 instructions are permitted. */
204 static int mips_5900
= -1;
205 /* end-sanitize-r5900 */
207 /* Whether Toshiba r3900 instructions are permitted. */
208 static int mips_3900
= -1;
210 /* Whether the processor uses hardware interlocks to protect
211 reads from the HI and LO registers, and thus does not
212 require nops to be inserted. */
213 static int hilo_interlocks
= -1;
215 /* Whether the processor uses hardware interlocks to protect
216 reads from the GPRs, and thus does not
217 require nops to be inserted. */
218 static int gpr_interlocks
= -1;
220 /* As with other "interlocks" this is used by hardware that has FP
221 (co-processor) interlocks. */
222 /* Itbl support may require additional care here. */
223 static int cop_interlocks
= -1;
225 /* MIPS PIC level. */
229 /* Do not generate PIC code. */
232 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
233 not sure what it is supposed to do. */
236 /* Generate PIC code as in the SVR4 MIPS ABI. */
239 /* Generate PIC code without using a global offset table: the data
240 segment has a maximum size of 64K, all data references are off
241 the $gp register, and all text references are PC relative. This
242 is used on some embedded systems. */
246 static enum mips_pic_level mips_pic
;
248 /* 1 if we should generate 32 bit offsets from the GP register in
249 SVR4_PIC mode. Currently has no meaning in other modes. */
250 static int mips_big_got
;
252 /* 1 if trap instructions should used for overflow rather than break
254 static int mips_trap
;
256 /* Non-zero if any .set noreorder directives were used. */
258 static int mips_any_noreorder
;
260 /* The size of the small data section. */
261 static int g_switch_value
= 8;
262 /* Whether the -G option was used. */
263 static int g_switch_seen
= 0;
268 /* If we can determine in advance that GP optimization won't be
269 possible, we can skip the relaxation stuff that tries to produce
270 GP-relative references. This makes delay slot optimization work
273 This function can only provide a guess, but it seems to work for
274 gcc output. If it guesses wrong, the only loss should be in
275 efficiency; it shouldn't introduce any bugs.
277 I don't know if a fix is needed for the SVR4_PIC mode. I've only
278 fixed it for the non-PIC mode. KR 95/04/07 */
279 static int nopic_need_relax
PARAMS ((symbolS
*, int));
281 /* handle of the OPCODE hash table */
282 static struct hash_control
*op_hash
= NULL
;
284 /* The opcode hash table we use for the mips16. */
285 static struct hash_control
*mips16_op_hash
= NULL
;
287 /* This array holds the chars that always start a comment. If the
288 pre-processor is disabled, these aren't very useful */
289 const char comment_chars
[] = "#";
291 /* This array holds the chars that only start a comment at the beginning of
292 a line. If the line seems to have the form '# 123 filename'
293 .line and .file directives will appear in the pre-processed output */
294 /* Note that input_file.c hand checks for '#' at the beginning of the
295 first line of the input file. This is because the compiler outputs
296 #NO_APP at the beginning of its output. */
297 /* Also note that C style comments are always supported. */
298 const char line_comment_chars
[] = "#";
300 /* This array holds machine specific line separator characters. */
301 const char line_separator_chars
[] = "";
303 /* Chars that can be used to separate mant from exp in floating point nums */
304 const char EXP_CHARS
[] = "eE";
306 /* Chars that mean this number is a floating point constant */
309 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
311 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
312 changed in read.c . Ideally it shouldn't have to know about it at all,
313 but nothing is ideal around here.
316 static char *insn_error
;
318 static int auto_align
= 1;
320 /* When outputting SVR4 PIC code, the assembler needs to know the
321 offset in the stack frame from which to restore the $gp register.
322 This is set by the .cprestore pseudo-op, and saved in this
324 static offsetT mips_cprestore_offset
= -1;
326 /* This is the register which holds the stack frame, as set by the
327 .frame pseudo-op. This is needed to implement .cprestore. */
328 static int mips_frame_reg
= SP
;
330 /* To output NOP instructions correctly, we need to keep information
331 about the previous two instructions. */
333 /* Whether we are optimizing. The default value of 2 means to remove
334 unneeded NOPs and swap branch instructions when possible. A value
335 of 1 means to not swap branches. A value of 0 means to always
337 static int mips_optimize
= 2;
339 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
340 equivalent to seeing no -g option at all. */
341 static int mips_debug
= 0;
343 /* The previous instruction. */
344 static struct mips_cl_insn prev_insn
;
346 /* The instruction before prev_insn. */
347 static struct mips_cl_insn prev_prev_insn
;
349 /* If we don't want information for prev_insn or prev_prev_insn, we
350 point the insn_mo field at this dummy integer. */
351 static const struct mips_opcode dummy_opcode
= { 0 };
353 /* Non-zero if prev_insn is valid. */
354 static int prev_insn_valid
;
356 /* The frag for the previous instruction. */
357 static struct frag
*prev_insn_frag
;
359 /* The offset into prev_insn_frag for the previous instruction. */
360 static long prev_insn_where
;
362 /* The reloc type for the previous instruction, if any. */
363 static bfd_reloc_code_real_type prev_insn_reloc_type
;
365 /* The reloc for the previous instruction, if any. */
366 static fixS
*prev_insn_fixp
;
368 /* Non-zero if the previous instruction was in a delay slot. */
369 static int prev_insn_is_delay_slot
;
371 /* Non-zero if the previous instruction was in a .set noreorder. */
372 static int prev_insn_unreordered
;
374 /* Non-zero if the previous instruction uses an extend opcode (if
376 static int prev_insn_extended
;
378 /* Non-zero if the previous previous instruction was in a .set
380 static int prev_prev_insn_unreordered
;
382 /* If this is set, it points to a frag holding nop instructions which
383 were inserted before the start of a noreorder section. If those
384 nops turn out to be unnecessary, the size of the frag can be
386 static fragS
*prev_nop_frag
;
388 /* The number of nop instructions we created in prev_nop_frag. */
389 static int prev_nop_frag_holds
;
391 /* The number of nop instructions that we know we need in
393 static int prev_nop_frag_required
;
395 /* The number of instructions we've seen since prev_nop_frag. */
396 static int prev_nop_frag_since
;
398 /* For ECOFF and ELF, relocations against symbols are done in two
399 parts, with a HI relocation and a LO relocation. Each relocation
400 has only 16 bits of space to store an addend. This means that in
401 order for the linker to handle carries correctly, it must be able
402 to locate both the HI and the LO relocation. This means that the
403 relocations must appear in order in the relocation table.
405 In order to implement this, we keep track of each unmatched HI
406 relocation. We then sort them so that they immediately precede the
407 corresponding LO relocation. */
412 struct mips_hi_fixup
*next
;
415 /* The section this fixup is in. */
419 /* The list of unmatched HI relocs. */
421 static struct mips_hi_fixup
*mips_hi_fixup_list
;
423 /* Map normal MIPS register numbers to mips16 register numbers. */
425 #define X ILLEGAL_REG
426 static const int mips32_to_16_reg_map
[] =
428 X
, X
, 2, 3, 4, 5, 6, 7,
429 X
, X
, X
, X
, X
, X
, X
, X
,
430 0, 1, X
, X
, X
, X
, X
, X
,
431 X
, X
, X
, X
, X
, X
, X
, X
435 /* Map mips16 register numbers to normal MIPS register numbers. */
437 static const int mips16_to_32_reg_map
[] =
439 16, 17, 2, 3, 4, 5, 6, 7
442 /* Since the MIPS does not have multiple forms of PC relative
443 instructions, we do not have to do relaxing as is done on other
444 platforms. However, we do have to handle GP relative addressing
445 correctly, which turns out to be a similar problem.
447 Every macro that refers to a symbol can occur in (at least) two
448 forms, one with GP relative addressing and one without. For
449 example, loading a global variable into a register generally uses
450 a macro instruction like this:
452 If i can be addressed off the GP register (this is true if it is in
453 the .sbss or .sdata section, or if it is known to be smaller than
454 the -G argument) this will generate the following instruction:
456 This instruction will use a GPREL reloc. If i can not be addressed
457 off the GP register, the following instruction sequence will be used:
460 In this case the first instruction will have a HI16 reloc, and the
461 second reloc will have a LO16 reloc. Both relocs will be against
464 The issue here is that we may not know whether i is GP addressable
465 until after we see the instruction that uses it. Therefore, we
466 want to be able to choose the final instruction sequence only at
467 the end of the assembly. This is similar to the way other
468 platforms choose the size of a PC relative instruction only at the
471 When generating position independent code we do not use GP
472 addressing in quite the same way, but the issue still arises as
473 external symbols and local symbols must be handled differently.
475 We handle these issues by actually generating both possible
476 instruction sequences. The longer one is put in a frag_var with
477 type rs_machine_dependent. We encode what to do with the frag in
478 the subtype field. We encode (1) the number of existing bytes to
479 replace, (2) the number of new bytes to use, (3) the offset from
480 the start of the existing bytes to the first reloc we must generate
481 (that is, the offset is applied from the start of the existing
482 bytes after they are replaced by the new bytes, if any), (4) the
483 offset from the start of the existing bytes to the second reloc,
484 (5) whether a third reloc is needed (the third reloc is always four
485 bytes after the second reloc), and (6) whether to warn if this
486 variant is used (this is sometimes needed if .set nomacro or .set
487 noat is in effect). All these numbers are reasonably small.
489 Generating two instruction sequences must be handled carefully to
490 ensure that delay slots are handled correctly. Fortunately, there
491 are a limited number of cases. When the second instruction
492 sequence is generated, append_insn is directed to maintain the
493 existing delay slot information, so it continues to apply to any
494 code after the second instruction sequence. This means that the
495 second instruction sequence must not impose any requirements not
496 required by the first instruction sequence.
498 These variant frags are then handled in functions called by the
499 machine independent code. md_estimate_size_before_relax returns
500 the final size of the frag. md_convert_frag sets up the final form
501 of the frag. tc_gen_reloc adjust the first reloc and adds a second
503 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
507 | (((reloc1) + 64) << 9) \
508 | (((reloc2) + 64) << 2) \
509 | ((reloc3) ? (1 << 1) : 0) \
511 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
512 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
513 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
514 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
515 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
516 #define RELAX_WARN(i) ((i) & 1)
518 /* For mips16 code, we use an entirely different form of relaxation.
519 mips16 supports two versions of most instructions which take
520 immediate values: a small one which takes some small value, and a
521 larger one which takes a 16 bit value. Since branches also follow
522 this pattern, relaxing these values is required.
524 We can assemble both mips16 and normal MIPS code in a single
525 object. Therefore, we need to support this type of relaxation at
526 the same time that we support the relaxation described above. We
527 use the high bit of the subtype field to distinguish these cases.
529 The information we store for this type of relaxation is the
530 argument code found in the opcode file for this relocation, whether
531 the user explicitly requested a small or extended form, and whether
532 the relocation is in a jump or jal delay slot. That tells us the
533 size of the value, and how it should be stored. We also store
534 whether the fragment is considered to be extended or not. We also
535 store whether this is known to be a branch to a different section,
536 whether we have tried to relax this frag yet, and whether we have
537 ever extended a PC relative fragment because of a shift count. */
538 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
541 | ((small) ? 0x100 : 0) \
542 | ((ext) ? 0x200 : 0) \
543 | ((dslot) ? 0x400 : 0) \
544 | ((jal_dslot) ? 0x800 : 0))
545 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
546 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
547 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
548 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
549 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
550 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
551 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
552 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
553 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
554 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
555 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
556 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
558 /* Prototypes for static functions. */
561 #define internalError() \
562 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
564 #define internalError() as_fatal ("MIPS internal Error");
567 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
569 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
570 unsigned int reg
, enum mips_regclass
class));
571 static int reg_needs_delay
PARAMS ((int));
572 static void mips16_mark_labels
PARAMS ((void));
573 static void append_insn
PARAMS ((char *place
,
574 struct mips_cl_insn
* ip
,
576 bfd_reloc_code_real_type r
,
578 static void mips_no_prev_insn
PARAMS ((int));
579 static void mips_emit_delays
PARAMS ((boolean
));
581 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
582 const char *name
, const char *fmt
,
585 static void macro_build ();
587 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
588 const char *, const char *,
590 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
591 expressionS
* ep
, int regnum
));
592 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
593 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
595 static void load_register
PARAMS ((int *, int, expressionS
*, int));
596 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
597 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
598 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
599 #ifdef LOSING_COMPILER
600 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
602 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
603 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
604 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
605 boolean
, boolean
, unsigned long *,
606 boolean
*, unsigned short *));
607 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
608 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
609 static symbolS
*get_symbol
PARAMS ((void));
610 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
611 static void s_align
PARAMS ((int));
612 static void s_change_sec
PARAMS ((int));
613 static void s_cons
PARAMS ((int));
614 static void s_float_cons
PARAMS ((int));
615 static void s_mips_globl
PARAMS ((int));
616 static void s_option
PARAMS ((int));
617 static void s_mipsset
PARAMS ((int));
618 static void s_abicalls
PARAMS ((int));
619 static void s_cpload
PARAMS ((int));
620 static void s_cprestore
PARAMS ((int));
621 static void s_gpword
PARAMS ((int));
622 static void s_cpadd
PARAMS ((int));
623 static void s_insn
PARAMS ((int));
624 static void md_obj_begin
PARAMS ((void));
625 static void md_obj_end
PARAMS ((void));
626 static long get_number
PARAMS ((void));
627 static void s_ent
PARAMS ((int));
628 static void s_mipsend
PARAMS ((int));
629 static void s_file
PARAMS ((int));
630 static void s_mips_stab
PARAMS ((int));
631 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
635 The following pseudo-ops from the Kane and Heinrich MIPS book
636 should be defined here, but are currently unsupported: .alias,
637 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
639 The following pseudo-ops from the Kane and Heinrich MIPS book are
640 specific to the type of debugging information being generated, and
641 should be defined by the object format: .aent, .begin, .bend,
642 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
645 The following pseudo-ops from the Kane and Heinrich MIPS book are
646 not MIPS CPU specific, but are also not specific to the object file
647 format. This file is probably the best place to define them, but
648 they are not currently supported: .asm0, .endr, .lab, .repeat,
649 .struct, .weakext. */
651 static const pseudo_typeS mips_pseudo_table
[] =
653 /* MIPS specific pseudo-ops. */
654 {"option", s_option
, 0},
655 {"set", s_mipsset
, 0},
656 {"rdata", s_change_sec
, 'r'},
657 {"sdata", s_change_sec
, 's'},
658 {"livereg", s_ignore
, 0},
659 {"abicalls", s_abicalls
, 0},
660 {"cpload", s_cpload
, 0},
661 {"cprestore", s_cprestore
, 0},
662 {"gpword", s_gpword
, 0},
663 {"cpadd", s_cpadd
, 0},
666 /* Relatively generic pseudo-ops that happen to be used on MIPS
668 {"asciiz", stringer
, 1},
669 {"bss", s_change_sec
, 'b'},
672 {"dword", s_cons
, 3},
674 /* These pseudo-ops are defined in read.c, but must be overridden
675 here for one reason or another. */
676 {"align", s_align
, 0},
678 {"data", s_change_sec
, 'd'},
679 {"double", s_float_cons
, 'd'},
680 {"float", s_float_cons
, 'f'},
681 {"globl", s_mips_globl
, 0},
682 {"global", s_mips_globl
, 0},
683 {"hword", s_cons
, 1},
688 {"short", s_cons
, 1},
689 {"single", s_float_cons
, 'f'},
690 {"stabn", s_mips_stab
, 'n'},
691 {"text", s_change_sec
, 't'},
696 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
697 /* These pseudo-ops should be defined by the object file format.
698 However, a.out doesn't support them, so we have versions here. */
700 {"bgnb", s_ignore
, 0},
701 {"end", s_mipsend
, 0},
702 {"endb", s_ignore
, 0},
705 {"fmask", s_ignore
, 'F'},
706 {"frame", s_ignore
, 0},
707 {"loc", s_ignore
, 0},
708 {"mask", s_ignore
, 'R'},
709 {"verstamp", s_ignore
, 0},
713 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
718 pop_insert (mips_pseudo_table
);
719 if (! ECOFF_DEBUGGING
)
720 pop_insert (mips_nonecoff_pseudo_table
);
723 /* Symbols labelling the current insn. */
725 struct insn_label_list
727 struct insn_label_list
*next
;
731 static struct insn_label_list
*insn_labels
;
732 static struct insn_label_list
*free_insn_labels
;
734 static void mips_clear_insn_labels
PARAMS ((void));
737 mips_clear_insn_labels ()
739 register struct insn_label_list
**pl
;
741 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
747 static char *expr_end
;
749 /* Expressions which appear in instructions. These are set by
752 static expressionS imm_expr
;
753 static expressionS offset_expr
;
755 /* Relocs associated with imm_expr and offset_expr. */
757 static bfd_reloc_code_real_type imm_reloc
;
758 static bfd_reloc_code_real_type offset_reloc
;
760 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
762 static boolean imm_unmatched_hi
;
764 /* These are set by mips16_ip if an explicit extension is used. */
766 static boolean mips16_small
, mips16_ext
;
769 * This function is called once, at assembler startup time. It should
770 * set up all the tables, etc. that the MD part of the assembler will need.
776 register const char *retval
= NULL
;
777 register unsigned int i
= 0;
779 if (mips_opts
.isa
== -1)
785 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
787 a
= xmalloc (sizeof TARGET_CPU
);
788 strcpy (a
, TARGET_CPU
);
789 a
[(sizeof TARGET_CPU
) - 3] = '\0';
793 if (strcmp (cpu
, "mips") == 0)
799 else if (strcmp (cpu
, "r3900") == 0
800 || strcmp (cpu
, "mipsr3900") == 0)
808 else if (strcmp (cpu
, "r6000") == 0
809 || strcmp (cpu
, "mips2") == 0)
815 else if (strcmp (cpu
, "mips64") == 0
816 || strcmp (cpu
, "r4000") == 0
817 || strcmp (cpu
, "mips3") == 0)
823 else if (strcmp (cpu
, "r4400") == 0)
829 else if (strcmp (cpu
, "mips64orion") == 0
830 || strcmp (cpu
, "r4600") == 0)
836 else if (strcmp (cpu
, "r4650") == 0)
844 else if (strcmp (cpu
, "mips64vr4300") == 0)
850 else if (strcmp (cpu
, "mips64vr4100") == 0)
858 else if (strcmp (cpu
, "r4010") == 0)
866 else if (strcmp (cpu
, "r5000") == 0
867 || strcmp (cpu
, "mips64vr5000") == 0)
873 /* start-sanitize-r5900 */
874 else if (strcmp (cpu
, "r5900") == 0
875 || strcmp (cpu
, "mips64vr5900") == 0
876 || strcmp (cpu
, "mips64vr5900el") == 0)
884 /* end-sanitize-r5900 */
885 else if (strcmp (cpu
, "r8000") == 0
886 || strcmp (cpu
, "mips4") == 0)
892 else if (strcmp (cpu
, "r10000") == 0)
898 else if (strcmp (cpu
, "mips16") == 0)
902 mips_cpu
= 0; /* FIXME */
915 if (mips_opts
.mips16
< 0)
917 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
918 mips_opts
.mips16
= 1;
920 mips_opts
.mips16
= 0;
932 /* start-sanitize-r5900 */
935 /* end-sanitize-r5900 */
948 if (mips_opts
.isa
>= 2
955 /* Itbl support may require additional care here. */
956 if (mips_cpu
== 4300)
961 if (mips_opts
.isa
< 2 && mips_trap
)
962 as_bad ("trap exception not supported at ISA 1");
964 switch (mips_opts
.isa
)
967 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
970 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
973 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
976 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
980 as_warn ("Could not set architecture and machine");
982 file_mips_isa
= mips_opts
.isa
;
984 op_hash
= hash_new ();
986 for (i
= 0; i
< NUMOPCODES
;)
988 const char *name
= mips_opcodes
[i
].name
;
990 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
993 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
994 mips_opcodes
[i
].name
, retval
);
995 as_fatal ("Broken assembler. No assembly attempted.");
999 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1000 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
1001 != mips_opcodes
[i
].match
))
1003 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
1004 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
1005 as_fatal ("Broken assembler. No assembly attempted.");
1009 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1012 mips16_op_hash
= hash_new ();
1015 while (i
< bfd_mips16_num_opcodes
)
1017 const char *name
= mips16_opcodes
[i
].name
;
1019 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1021 as_fatal ("internal error: can't hash `%s': %s\n",
1022 mips16_opcodes
[i
].name
, retval
);
1025 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1026 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1027 != mips16_opcodes
[i
].match
))
1028 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
1029 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1032 while (i
< bfd_mips16_num_opcodes
1033 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1036 /* We add all the general register names to the symbol table. This
1037 helps us detect invalid uses of them. */
1038 for (i
= 0; i
< 32; i
++)
1042 sprintf (buf
, "$%d", i
);
1043 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1044 &zero_address_frag
));
1046 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1047 &zero_address_frag
));
1048 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1049 &zero_address_frag
));
1050 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1051 &zero_address_frag
));
1052 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1053 &zero_address_frag
));
1054 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1055 &zero_address_frag
));
1056 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1057 &zero_address_frag
));
1058 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1059 &zero_address_frag
));
1061 mips_no_prev_insn (false);
1064 mips_cprmask
[0] = 0;
1065 mips_cprmask
[1] = 0;
1066 mips_cprmask
[2] = 0;
1067 mips_cprmask
[3] = 0;
1069 /* set the default alignment for the text section (2**2) */
1070 record_alignment (text_section
, 2);
1072 if (USE_GLOBAL_POINTER_OPT
)
1073 bfd_set_gp_size (stdoutput
, g_switch_value
);
1075 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1077 /* On a native system, sections must be aligned to 16 byte
1078 boundaries. When configured for an embedded ELF target, we
1080 if (strcmp (TARGET_OS
, "elf") != 0)
1082 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1083 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1084 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1087 /* Create a .reginfo section for register masks and a .mdebug
1088 section for debugging information. */
1096 subseg
= now_subseg
;
1098 /* The ABI says this section should be loaded so that the
1099 running program can access it. However, we don't load it
1100 if we are configured for an embedded target */
1101 flags
= SEC_READONLY
| SEC_DATA
;
1102 if (strcmp (TARGET_OS
, "elf") != 0)
1103 flags
|= SEC_ALLOC
| SEC_LOAD
;
1107 sec
= subseg_new (".reginfo", (subsegT
) 0);
1110 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1111 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1114 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1119 /* The 64-bit ABI uses a .MIPS.options section rather than
1120 .reginfo section. */
1121 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1122 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1123 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1126 /* Set up the option header. */
1128 Elf_Internal_Options opthdr
;
1131 opthdr
.kind
= ODK_REGINFO
;
1132 opthdr
.size
= (sizeof (Elf_External_Options
)
1133 + sizeof (Elf64_External_RegInfo
));
1136 f
= frag_more (sizeof (Elf_External_Options
));
1137 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1138 (Elf_External_Options
*) f
);
1140 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1145 if (ECOFF_DEBUGGING
)
1147 sec
= subseg_new (".mdebug", (subsegT
) 0);
1148 (void) bfd_set_section_flags (stdoutput
, sec
,
1149 SEC_HAS_CONTENTS
| SEC_READONLY
);
1150 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1153 subseg_set (seg
, subseg
);
1157 if (! ECOFF_DEBUGGING
)
1164 if (! ECOFF_DEBUGGING
)
1172 struct mips_cl_insn insn
;
1174 imm_expr
.X_op
= O_absent
;
1175 imm_reloc
= BFD_RELOC_UNUSED
;
1176 imm_unmatched_hi
= false;
1177 offset_expr
.X_op
= O_absent
;
1178 offset_reloc
= BFD_RELOC_UNUSED
;
1180 if (mips_opts
.mips16
)
1181 mips16_ip (str
, &insn
);
1184 mips_ip (str
, &insn
);
1185 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1186 str
, insn
.insn_opcode
));
1191 as_bad ("%s `%s'", insn_error
, str
);
1195 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1197 if (mips_opts
.mips16
)
1198 mips16_macro (&insn
);
1204 if (imm_expr
.X_op
!= O_absent
)
1205 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1207 else if (offset_expr
.X_op
!= O_absent
)
1208 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1210 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1214 /* See whether instruction IP reads register REG. CLASS is the type
1218 insn_uses_reg (ip
, reg
, class)
1219 struct mips_cl_insn
*ip
;
1221 enum mips_regclass
class;
1223 if (class == MIPS16_REG
)
1225 assert (mips_opts
.mips16
);
1226 reg
= mips16_to_32_reg_map
[reg
];
1227 class = MIPS_GR_REG
;
1230 /* Don't report on general register 0, since it never changes. */
1231 if (class == MIPS_GR_REG
&& reg
== 0)
1234 if (class == MIPS_FP_REG
)
1236 assert (! mips_opts
.mips16
);
1237 /* If we are called with either $f0 or $f1, we must check $f0.
1238 This is not optimal, because it will introduce an unnecessary
1239 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1240 need to distinguish reading both $f0 and $f1 or just one of
1241 them. Note that we don't have to check the other way,
1242 because there is no instruction that sets both $f0 and $f1
1243 and requires a delay. */
1244 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1245 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1246 == (reg
&~ (unsigned) 1)))
1248 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1249 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1250 == (reg
&~ (unsigned) 1)))
1253 else if (! mips_opts
.mips16
)
1255 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1256 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1258 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1259 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1264 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1265 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1266 & MIPS16OP_MASK_RX
)]
1269 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1270 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1271 & MIPS16OP_MASK_RY
)]
1274 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1275 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1276 & MIPS16OP_MASK_MOVE32Z
)]
1279 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1281 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1283 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1285 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1286 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1287 & MIPS16OP_MASK_REGR32
) == reg
)
1294 /* This function returns true if modifying a register requires a
1298 reg_needs_delay (reg
)
1301 unsigned long prev_pinfo
;
1303 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1304 if (! mips_opts
.noreorder
1305 && mips_opts
.isa
< 4
1306 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1307 || (! gpr_interlocks
1308 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1310 /* A load from a coprocessor or from memory. All load
1311 delays delay the use of general register rt for one
1312 instruction on the r3000. The r6000 and r4000 use
1314 /* Itbl support may require additional care here. */
1315 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1316 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1323 /* Mark instruction labels in mips16 mode. This permits the linker to
1324 handle them specially, such as generating jalx instructions when
1325 needed. We also make them odd for the duration of the assembly, in
1326 order to generate the right sort of code. We will make them even
1327 in the adjust_symtab routine, while leaving them marked. This is
1328 convenient for the debugger and the disassembler. The linker knows
1329 to make them odd again. */
1332 mips16_mark_labels ()
1334 if (mips_opts
.mips16
)
1336 struct insn_label_list
*l
;
1338 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1341 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1342 S_SET_OTHER (l
->label
, STO_MIPS16
);
1344 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1345 ++l
->label
->sy_value
.X_add_number
;
1350 /* Output an instruction. PLACE is where to put the instruction; if
1351 it is NULL, this uses frag_more to get room. IP is the instruction
1352 information. ADDRESS_EXPR is an operand of the instruction to be
1353 used with RELOC_TYPE. */
1356 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1358 struct mips_cl_insn
*ip
;
1359 expressionS
*address_expr
;
1360 bfd_reloc_code_real_type reloc_type
;
1361 boolean unmatched_hi
;
1363 register unsigned long prev_pinfo
, pinfo
;
1368 /* Mark instruction labels in mips16 mode. */
1369 if (mips_opts
.mips16
)
1370 mips16_mark_labels ();
1372 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1373 pinfo
= ip
->insn_mo
->pinfo
;
1375 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1379 /* If the previous insn required any delay slots, see if we need
1380 to insert a NOP or two. There are eight kinds of possible
1381 hazards, of which an instruction can have at most one type.
1382 (1) a load from memory delay
1383 (2) a load from a coprocessor delay
1384 (3) an unconditional branch delay
1385 (4) a conditional branch delay
1386 (5) a move to coprocessor register delay
1387 (6) a load coprocessor register from memory delay
1388 (7) a coprocessor condition code delay
1389 (8) a HI/LO special register delay
1391 There are a lot of optimizations we could do that we don't.
1392 In particular, we do not, in general, reorder instructions.
1393 If you use gcc with optimization, it will reorder
1394 instructions and generally do much more optimization then we
1395 do here; repeating all that work in the assembler would only
1396 benefit hand written assembly code, and does not seem worth
1399 /* This is how a NOP is emitted. */
1400 #define emit_nop() \
1402 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1403 : md_number_to_chars (frag_more (4), 0, 4))
1405 /* The previous insn might require a delay slot, depending upon
1406 the contents of the current insn. */
1407 if (! mips_opts
.mips16
1408 && mips_opts
.isa
< 4
1409 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1410 && ! cop_interlocks
)
1411 || (! gpr_interlocks
1412 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1414 /* A load from a coprocessor or from memory. All load
1415 delays delay the use of general register rt for one
1416 instruction on the r3000. The r6000 and r4000 use
1418 /* Itbl support may require additional care here. */
1419 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1420 if (mips_optimize
== 0
1421 || insn_uses_reg (ip
,
1422 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1427 else if (! mips_opts
.mips16
1428 && mips_opts
.isa
< 4
1429 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1430 && ! cop_interlocks
)
1431 || (mips_opts
.isa
< 2
1432 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1434 /* A generic coprocessor delay. The previous instruction
1435 modified a coprocessor general or control register. If
1436 it modified a control register, we need to avoid any
1437 coprocessor instruction (this is probably not always
1438 required, but it sometimes is). If it modified a general
1439 register, we avoid using that register.
1441 On the r6000 and r4000 loading a coprocessor register
1442 from memory is interlocked, and does not require a delay.
1444 This case is not handled very well. There is no special
1445 knowledge of CP0 handling, and the coprocessors other
1446 than the floating point unit are not distinguished at
1448 /* Itbl support may require additional care here. FIXME!
1449 Need to modify this to include knowledge about
1450 user specified delays! */
1451 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1453 if (mips_optimize
== 0
1454 || insn_uses_reg (ip
,
1455 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1460 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1462 if (mips_optimize
== 0
1463 || insn_uses_reg (ip
,
1464 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1471 /* We don't know exactly what the previous instruction
1472 does. If the current instruction uses a coprocessor
1473 register, we must insert a NOP. If previous
1474 instruction may set the condition codes, and the
1475 current instruction uses them, we must insert two
1477 /* Itbl support may require additional care here. */
1478 if (mips_optimize
== 0
1479 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1480 && (pinfo
& INSN_READ_COND_CODE
)))
1482 else if (pinfo
& INSN_COP
)
1486 else if (! mips_opts
.mips16
1487 && mips_opts
.isa
< 4
1488 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1489 && ! cop_interlocks
)
1491 /* The previous instruction sets the coprocessor condition
1492 codes, but does not require a general coprocessor delay
1493 (this means it is a floating point comparison
1494 instruction). If this instruction uses the condition
1495 codes, we need to insert a single NOP. */
1496 /* Itbl support may require additional care here. */
1497 if (mips_optimize
== 0
1498 || (pinfo
& INSN_READ_COND_CODE
))
1501 else if (prev_pinfo
& INSN_READ_LO
)
1503 /* The previous instruction reads the LO register; if the
1504 current instruction writes to the LO register, we must
1505 insert two NOPS. Some newer processors have interlocks. */
1506 if (! hilo_interlocks
1507 && (mips_optimize
== 0
1508 || (pinfo
& INSN_WRITE_LO
)))
1511 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1513 /* The previous instruction reads the HI register; if the
1514 current instruction writes to the HI register, we must
1515 insert a NOP. Some newer processors have interlocks. */
1516 if (! hilo_interlocks
1517 && (mips_optimize
== 0
1518 || (pinfo
& INSN_WRITE_HI
)))
1522 /* If the previous instruction was in a noreorder section, then
1523 we don't want to insert the nop after all. */
1524 /* Itbl support may require additional care here. */
1525 if (prev_insn_unreordered
)
1528 /* There are two cases which require two intervening
1529 instructions: 1) setting the condition codes using a move to
1530 coprocessor instruction which requires a general coprocessor
1531 delay and then reading the condition codes 2) reading the HI
1532 or LO register and then writing to it (except on processors
1533 which have interlocks). If we are not already emitting a NOP
1534 instruction, we must check for these cases compared to the
1535 instruction previous to the previous instruction. */
1536 if ((! mips_opts
.mips16
1537 && mips_opts
.isa
< 4
1538 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1539 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1540 && (pinfo
& INSN_READ_COND_CODE
)
1541 && ! cop_interlocks
)
1542 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1543 && (pinfo
& INSN_WRITE_LO
)
1544 && ! hilo_interlocks
)
1545 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1546 && (pinfo
& INSN_WRITE_HI
)
1547 && ! hilo_interlocks
))
1552 if (prev_prev_insn_unreordered
)
1555 if (prev_prev_nop
&& nops
== 0)
1558 /* If we are being given a nop instruction, don't bother with
1559 one of the nops we would otherwise output. This will only
1560 happen when a nop instruction is used with mips_optimize set
1563 && ! mips_opts
.noreorder
1564 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1567 /* Now emit the right number of NOP instructions. */
1568 if (nops
> 0 && ! mips_opts
.noreorder
)
1571 unsigned long old_frag_offset
;
1573 struct insn_label_list
*l
;
1575 old_frag
= frag_now
;
1576 old_frag_offset
= frag_now_fix ();
1578 for (i
= 0; i
< nops
; i
++)
1583 listing_prev_line ();
1584 /* We may be at the start of a variant frag. In case we
1585 are, make sure there is enough space for the frag
1586 after the frags created by listing_prev_line. The
1587 argument to frag_grow here must be at least as large
1588 as the argument to all other calls to frag_grow in
1589 this file. We don't have to worry about being in the
1590 middle of a variant frag, because the variants insert
1591 all needed nop instructions themselves. */
1595 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1597 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1598 l
->label
->sy_frag
= frag_now
;
1599 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1600 /* mips16 text labels are stored as odd. */
1601 if (mips_opts
.mips16
)
1602 ++l
->label
->sy_value
.X_add_number
;
1605 #ifndef NO_ECOFF_DEBUGGING
1606 if (ECOFF_DEBUGGING
)
1607 ecoff_fix_loc (old_frag
, old_frag_offset
);
1610 else if (prev_nop_frag
!= NULL
)
1612 /* We have a frag holding nops we may be able to remove. If
1613 we don't need any nops, we can decrease the size of
1614 prev_nop_frag by the size of one instruction. If we do
1615 need some nops, we count them in prev_nops_required. */
1616 if (prev_nop_frag_since
== 0)
1620 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1621 --prev_nop_frag_holds
;
1624 prev_nop_frag_required
+= nops
;
1628 if (prev_prev_nop
== 0)
1630 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1631 --prev_nop_frag_holds
;
1634 ++prev_nop_frag_required
;
1637 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1638 prev_nop_frag
= NULL
;
1640 ++prev_nop_frag_since
;
1642 /* Sanity check: by the time we reach the second instruction
1643 after prev_nop_frag, we should have used up all the nops
1644 one way or another. */
1645 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1649 if (reloc_type
> BFD_RELOC_UNUSED
)
1651 /* We need to set up a variant frag. */
1652 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1653 f
= frag_var (rs_machine_dependent
, 4, 0,
1654 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1655 mips16_small
, mips16_ext
,
1657 & INSN_UNCOND_BRANCH_DELAY
),
1658 (prev_insn_reloc_type
1659 == BFD_RELOC_MIPS16_JMP
)),
1660 make_expr_symbol (address_expr
), (offsetT
) 0,
1663 else if (place
!= NULL
)
1665 else if (mips_opts
.mips16
1667 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1669 /* Make sure there is enough room to swap this instruction with
1670 a following jump instruction. */
1676 if (mips_opts
.mips16
1677 && mips_opts
.noreorder
1678 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1679 as_warn ("extended instruction in delay slot");
1685 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1687 if (address_expr
->X_op
== O_constant
)
1692 ip
->insn_opcode
|= address_expr
->X_add_number
;
1695 case BFD_RELOC_LO16
:
1696 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1699 case BFD_RELOC_MIPS_JMP
:
1700 if ((address_expr
->X_add_number
& 3) != 0)
1701 as_bad ("jump to misaligned address (0x%lx)",
1702 (unsigned long) address_expr
->X_add_number
);
1703 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1706 case BFD_RELOC_MIPS16_JMP
:
1707 if ((address_expr
->X_add_number
& 3) != 0)
1708 as_bad ("jump to misaligned address (0x%lx)",
1709 (unsigned long) address_expr
->X_add_number
);
1711 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1712 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1713 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1716 case BFD_RELOC_16_PCREL_S2
:
1726 /* Don't generate a reloc if we are writing into a variant
1730 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1732 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1736 struct mips_hi_fixup
*hi_fixup
;
1738 assert (reloc_type
== BFD_RELOC_HI16_S
);
1739 hi_fixup
= ((struct mips_hi_fixup
*)
1740 xmalloc (sizeof (struct mips_hi_fixup
)));
1741 hi_fixup
->fixp
= fixp
;
1742 hi_fixup
->seg
= now_seg
;
1743 hi_fixup
->next
= mips_hi_fixup_list
;
1744 mips_hi_fixup_list
= hi_fixup
;
1750 if (! mips_opts
.mips16
)
1751 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1752 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1754 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1755 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1761 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1764 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1767 /* Update the register mask information. */
1768 if (! mips_opts
.mips16
)
1770 if (pinfo
& INSN_WRITE_GPR_D
)
1771 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1772 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1773 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1774 if (pinfo
& INSN_READ_GPR_S
)
1775 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1776 if (pinfo
& INSN_WRITE_GPR_31
)
1777 mips_gprmask
|= 1 << 31;
1778 if (pinfo
& INSN_WRITE_FPR_D
)
1779 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1780 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1781 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1782 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1783 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1784 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1785 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1786 if (pinfo
& INSN_COP
)
1788 /* We don't keep enough information to sort these cases out.
1789 The itbl support does keep this information however, although
1790 we currently don't support itbl fprmats as part of the cop
1791 instruction. May want to add this support in the future. */
1793 /* Never set the bit for $0, which is always zero. */
1794 mips_gprmask
&=~ 1 << 0;
1798 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1799 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1800 & MIPS16OP_MASK_RX
);
1801 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1802 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1803 & MIPS16OP_MASK_RY
);
1804 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1805 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1806 & MIPS16OP_MASK_RZ
);
1807 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1808 mips_gprmask
|= 1 << TREG
;
1809 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1810 mips_gprmask
|= 1 << SP
;
1811 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1812 mips_gprmask
|= 1 << RA
;
1813 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1814 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1815 if (pinfo
& MIPS16_INSN_READ_Z
)
1816 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1817 & MIPS16OP_MASK_MOVE32Z
);
1818 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1819 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1820 & MIPS16OP_MASK_REGR32
);
1823 if (place
== NULL
&& ! mips_opts
.noreorder
)
1825 /* Filling the branch delay slot is more complex. We try to
1826 switch the branch with the previous instruction, which we can
1827 do if the previous instruction does not set up a condition
1828 that the branch tests and if the branch is not itself the
1829 target of any branch. */
1830 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1831 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1833 if (mips_optimize
< 2
1834 /* If we have seen .set volatile or .set nomove, don't
1836 || mips_opts
.nomove
!= 0
1837 /* If we had to emit any NOP instructions, then we
1838 already know we can not swap. */
1840 /* If we don't even know the previous insn, we can not
1842 || ! prev_insn_valid
1843 /* If the previous insn is already in a branch delay
1844 slot, then we can not swap. */
1845 || prev_insn_is_delay_slot
1846 /* If the previous previous insn was in a .set
1847 noreorder, we can't swap. Actually, the MIPS
1848 assembler will swap in this situation. However, gcc
1849 configured -with-gnu-as will generate code like
1855 in which we can not swap the bne and INSN. If gcc is
1856 not configured -with-gnu-as, it does not output the
1857 .set pseudo-ops. We don't have to check
1858 prev_insn_unreordered, because prev_insn_valid will
1859 be 0 in that case. We don't want to use
1860 prev_prev_insn_valid, because we do want to be able
1861 to swap at the start of a function. */
1862 || prev_prev_insn_unreordered
1863 /* If the branch is itself the target of a branch, we
1864 can not swap. We cheat on this; all we check for is
1865 whether there is a label on this instruction. If
1866 there are any branches to anything other than a
1867 label, users must use .set noreorder. */
1868 || insn_labels
!= NULL
1869 /* If the previous instruction is in a variant frag, we
1870 can not do the swap. This does not apply to the
1871 mips16, which uses variant frags for different
1873 || (! mips_opts
.mips16
1874 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1875 /* If the branch reads the condition codes, we don't
1876 even try to swap, because in the sequence
1881 we can not swap, and I don't feel like handling that
1883 || (! mips_opts
.mips16
1884 && mips_opts
.isa
< 4
1885 && (pinfo
& INSN_READ_COND_CODE
))
1886 /* We can not swap with an instruction that requires a
1887 delay slot, becase the target of the branch might
1888 interfere with that instruction. */
1889 || (! mips_opts
.mips16
1890 && mips_opts
.isa
< 4
1892 /* Itbl support may require additional care here. */
1893 & (INSN_LOAD_COPROC_DELAY
1894 | INSN_COPROC_MOVE_DELAY
1895 | INSN_WRITE_COND_CODE
)))
1896 || (! hilo_interlocks
1900 || (! mips_opts
.mips16
1902 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1903 || (! mips_opts
.mips16
1904 && mips_opts
.isa
< 2
1905 /* Itbl support may require additional care here. */
1906 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1907 /* We can not swap with a branch instruction. */
1909 & (INSN_UNCOND_BRANCH_DELAY
1910 | INSN_COND_BRANCH_DELAY
1911 | INSN_COND_BRANCH_LIKELY
))
1912 /* We do not swap with a trap instruction, since it
1913 complicates trap handlers to have the trap
1914 instruction be in a delay slot. */
1915 || (prev_pinfo
& INSN_TRAP
)
1916 /* If the branch reads a register that the previous
1917 instruction sets, we can not swap. */
1918 || (! mips_opts
.mips16
1919 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1920 && insn_uses_reg (ip
,
1921 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1924 || (! mips_opts
.mips16
1925 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1926 && insn_uses_reg (ip
,
1927 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1930 || (mips_opts
.mips16
1931 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1932 && insn_uses_reg (ip
,
1933 ((prev_insn
.insn_opcode
1935 & MIPS16OP_MASK_RX
),
1937 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1938 && insn_uses_reg (ip
,
1939 ((prev_insn
.insn_opcode
1941 & MIPS16OP_MASK_RY
),
1943 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1944 && insn_uses_reg (ip
,
1945 ((prev_insn
.insn_opcode
1947 & MIPS16OP_MASK_RZ
),
1949 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1950 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1951 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1952 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1953 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1954 && insn_uses_reg (ip
,
1955 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1958 /* If the branch writes a register that the previous
1959 instruction sets, we can not swap (we know that
1960 branches write only to RD or to $31). */
1961 || (! mips_opts
.mips16
1962 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1963 && (((pinfo
& INSN_WRITE_GPR_D
)
1964 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1965 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1966 || ((pinfo
& INSN_WRITE_GPR_31
)
1967 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1970 || (! mips_opts
.mips16
1971 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1972 && (((pinfo
& INSN_WRITE_GPR_D
)
1973 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1974 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1975 || ((pinfo
& INSN_WRITE_GPR_31
)
1976 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1979 || (mips_opts
.mips16
1980 && (pinfo
& MIPS16_INSN_WRITE_31
)
1981 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1982 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1983 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1985 /* If the branch writes a register that the previous
1986 instruction reads, we can not swap (we know that
1987 branches only write to RD or to $31). */
1988 || (! mips_opts
.mips16
1989 && (pinfo
& INSN_WRITE_GPR_D
)
1990 && insn_uses_reg (&prev_insn
,
1991 ((ip
->insn_opcode
>> OP_SH_RD
)
1994 || (! mips_opts
.mips16
1995 && (pinfo
& INSN_WRITE_GPR_31
)
1996 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1997 || (mips_opts
.mips16
1998 && (pinfo
& MIPS16_INSN_WRITE_31
)
1999 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2000 /* If we are generating embedded PIC code, the branch
2001 might be expanded into a sequence which uses $at, so
2002 we can't swap with an instruction which reads it. */
2003 || (mips_pic
== EMBEDDED_PIC
2004 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2005 /* If the previous previous instruction has a load
2006 delay, and sets a register that the branch reads, we
2008 || (! mips_opts
.mips16
2009 && mips_opts
.isa
< 4
2010 /* Itbl support may require additional care here. */
2011 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2012 || (! gpr_interlocks
2013 && (prev_prev_insn
.insn_mo
->pinfo
2014 & INSN_LOAD_MEMORY_DELAY
)))
2015 && insn_uses_reg (ip
,
2016 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2019 /* If one instruction sets a condition code and the
2020 other one uses a condition code, we can not swap. */
2021 || ((pinfo
& INSN_READ_COND_CODE
)
2022 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2023 || ((pinfo
& INSN_WRITE_COND_CODE
)
2024 && (prev_pinfo
& INSN_READ_COND_CODE
))
2025 /* If the previous instruction uses the PC, we can not
2027 || (mips_opts
.mips16
2028 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2029 /* If the previous instruction was extended, we can not
2031 || (mips_opts
.mips16
&& prev_insn_extended
)
2032 /* If the previous instruction had a fixup in mips16
2033 mode, we can not swap. This normally means that the
2034 previous instruction was a 4 byte branch anyhow. */
2035 || (mips_opts
.mips16
&& prev_insn_fixp
))
2037 /* We could do even better for unconditional branches to
2038 portions of this object file; we could pick up the
2039 instruction at the destination, put it in the delay
2040 slot, and bump the destination address. */
2042 /* Update the previous insn information. */
2043 prev_prev_insn
= *ip
;
2044 prev_insn
.insn_mo
= &dummy_opcode
;
2048 /* It looks like we can actually do the swap. */
2049 if (! mips_opts
.mips16
)
2054 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2055 memcpy (temp
, prev_f
, 4);
2056 memcpy (prev_f
, f
, 4);
2057 memcpy (f
, temp
, 4);
2060 prev_insn_fixp
->fx_frag
= frag_now
;
2061 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2065 fixp
->fx_frag
= prev_insn_frag
;
2066 fixp
->fx_where
= prev_insn_where
;
2074 assert (prev_insn_fixp
== NULL
);
2075 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2076 memcpy (temp
, prev_f
, 2);
2077 memcpy (prev_f
, f
, 2);
2078 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2080 assert (reloc_type
== BFD_RELOC_UNUSED
);
2081 memcpy (f
, temp
, 2);
2085 memcpy (f
, f
+ 2, 2);
2086 memcpy (f
+ 2, temp
, 2);
2090 fixp
->fx_frag
= prev_insn_frag
;
2091 fixp
->fx_where
= prev_insn_where
;
2095 /* Update the previous insn information; leave prev_insn
2097 prev_prev_insn
= *ip
;
2099 prev_insn_is_delay_slot
= 1;
2101 /* If that was an unconditional branch, forget the previous
2102 insn information. */
2103 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2105 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2106 prev_insn
.insn_mo
= &dummy_opcode
;
2109 prev_insn_fixp
= NULL
;
2110 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2111 prev_insn_extended
= 0;
2113 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2115 /* We don't yet optimize a branch likely. What we should do
2116 is look at the target, copy the instruction found there
2117 into the delay slot, and increment the branch to jump to
2118 the next instruction. */
2120 /* Update the previous insn information. */
2121 prev_prev_insn
= *ip
;
2122 prev_insn
.insn_mo
= &dummy_opcode
;
2123 prev_insn_fixp
= NULL
;
2124 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2125 prev_insn_extended
= 0;
2129 /* Update the previous insn information. */
2131 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2133 prev_prev_insn
= prev_insn
;
2136 /* Any time we see a branch, we always fill the delay slot
2137 immediately; since this insn is not a branch, we know it
2138 is not in a delay slot. */
2139 prev_insn_is_delay_slot
= 0;
2141 prev_insn_fixp
= fixp
;
2142 prev_insn_reloc_type
= reloc_type
;
2143 if (mips_opts
.mips16
)
2144 prev_insn_extended
= (ip
->use_extend
2145 || reloc_type
> BFD_RELOC_UNUSED
);
2148 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2149 prev_insn_unreordered
= 0;
2150 prev_insn_frag
= frag_now
;
2151 prev_insn_where
= f
- frag_now
->fr_literal
;
2152 prev_insn_valid
= 1;
2154 else if (place
== NULL
)
2156 /* We need to record a bit of information even when we are not
2157 reordering, in order to determine the base address for mips16
2158 PC relative relocs. */
2159 prev_prev_insn
= prev_insn
;
2161 prev_insn_reloc_type
= reloc_type
;
2162 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2163 prev_insn_unreordered
= 1;
2166 /* We just output an insn, so the next one doesn't have a label. */
2167 mips_clear_insn_labels ();
2170 /* This function forgets that there was any previous instruction or
2171 label. If PRESERVE is non-zero, it remembers enough information to
2172 know whether nops are needed before a noreorder section. */
2175 mips_no_prev_insn (preserve
)
2180 prev_insn
.insn_mo
= &dummy_opcode
;
2181 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2182 prev_nop_frag
= NULL
;
2183 prev_nop_frag_holds
= 0;
2184 prev_nop_frag_required
= 0;
2185 prev_nop_frag_since
= 0;
2187 prev_insn_valid
= 0;
2188 prev_insn_is_delay_slot
= 0;
2189 prev_insn_unreordered
= 0;
2190 prev_insn_extended
= 0;
2191 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2192 prev_prev_insn_unreordered
= 0;
2193 mips_clear_insn_labels ();
2196 /* This function must be called whenever we turn on noreorder or emit
2197 something other than instructions. It inserts any NOPS which might
2198 be needed by the previous instruction, and clears the information
2199 kept for the previous instructions. The INSNS parameter is true if
2200 instructions are to follow. */
2203 mips_emit_delays (insns
)
2206 if (! mips_opts
.noreorder
)
2211 if ((! mips_opts
.mips16
2212 && mips_opts
.isa
< 4
2213 && (! cop_interlocks
2214 && (prev_insn
.insn_mo
->pinfo
2215 & (INSN_LOAD_COPROC_DELAY
2216 | INSN_COPROC_MOVE_DELAY
2217 | INSN_WRITE_COND_CODE
))))
2218 || (! hilo_interlocks
2219 && (prev_insn
.insn_mo
->pinfo
2222 || (! mips_opts
.mips16
2224 && (prev_insn
.insn_mo
->pinfo
2225 & INSN_LOAD_MEMORY_DELAY
))
2226 || (! mips_opts
.mips16
2227 && mips_opts
.isa
< 2
2228 && (prev_insn
.insn_mo
->pinfo
2229 & INSN_COPROC_MEMORY_DELAY
)))
2231 /* Itbl support may require additional care here. */
2233 if ((! mips_opts
.mips16
2234 && mips_opts
.isa
< 4
2235 && (! cop_interlocks
2236 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2237 || (! hilo_interlocks
2238 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2239 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2242 if (prev_insn_unreordered
)
2245 else if ((! mips_opts
.mips16
2246 && mips_opts
.isa
< 4
2247 && (! cop_interlocks
2248 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2249 || (! hilo_interlocks
2250 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2251 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2253 /* Itbl support may require additional care here. */
2254 if (! prev_prev_insn_unreordered
)
2260 struct insn_label_list
*l
;
2264 /* Record the frag which holds the nop instructions, so
2265 that we can remove them if we don't need them. */
2266 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2267 prev_nop_frag
= frag_now
;
2268 prev_nop_frag_holds
= nops
;
2269 prev_nop_frag_required
= 0;
2270 prev_nop_frag_since
= 0;
2273 for (; nops
> 0; --nops
)
2278 /* Move on to a new frag, so that it is safe to simply
2279 decrease the size of prev_nop_frag. */
2280 frag_wane (frag_now
);
2284 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2286 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2287 l
->label
->sy_frag
= frag_now
;
2288 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2289 /* mips16 text labels are stored as odd. */
2290 if (mips_opts
.mips16
)
2291 ++l
->label
->sy_value
.X_add_number
;
2296 /* Mark instruction labels in mips16 mode. */
2297 if (mips_opts
.mips16
&& insns
)
2298 mips16_mark_labels ();
2300 mips_no_prev_insn (insns
);
2303 /* Build an instruction created by a macro expansion. This is passed
2304 a pointer to the count of instructions created so far, an
2305 expression, the name of the instruction to build, an operand format
2306 string, and corresponding arguments. */
2310 macro_build (char *place
,
2318 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2327 struct mips_cl_insn insn
;
2328 bfd_reloc_code_real_type r
;
2333 va_start (args
, fmt
);
2339 * If the macro is about to expand into a second instruction,
2340 * print a warning if needed. We need to pass ip as a parameter
2341 * to generate a better warning message here...
2343 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2344 as_warn ("Macro instruction expanded into multiple instructions");
2347 *counter
+= 1; /* bump instruction counter */
2349 if (mips_opts
.mips16
)
2351 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2356 r
= BFD_RELOC_UNUSED
;
2357 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2358 assert (insn
.insn_mo
);
2359 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2361 /* Search until we get a match for NAME. */
2364 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2365 insn_isa
= insn
.insn_mo
->match
;
2366 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2368 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2370 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2372 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2377 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2378 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2379 && (insn_isa
<= mips_opts
.isa
2381 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2383 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2385 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2386 /* start-sanitize-r5900 */
2388 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2389 /* end-sanitize-r5900 */
2391 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2392 /* start-sanitize-r5900 */
2393 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2394 /* end-sanitize-r5900 */
2395 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2399 assert (insn
.insn_mo
->name
);
2400 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2403 insn
.insn_opcode
= insn
.insn_mo
->match
;
2419 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2425 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2430 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2435 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2442 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2446 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2450 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2457 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2463 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2464 assert (r
== BFD_RELOC_MIPS_GPREL
2465 || r
== BFD_RELOC_MIPS_LITERAL
2466 || r
== BFD_RELOC_LO16
2467 || r
== BFD_RELOC_MIPS_GOT16
2468 || r
== BFD_RELOC_MIPS_CALL16
2469 || r
== BFD_RELOC_MIPS_GOT_LO16
2470 || r
== BFD_RELOC_MIPS_CALL_LO16
2471 || (ep
->X_op
== O_subtract
2472 && now_seg
== text_section
2473 && r
== BFD_RELOC_PCREL_LO16
));
2477 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2479 && (ep
->X_op
== O_constant
2480 || (ep
->X_op
== O_symbol
2481 && (r
== BFD_RELOC_HI16_S
2482 || r
== BFD_RELOC_HI16
2483 || r
== BFD_RELOC_MIPS_GOT_HI16
2484 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2485 || (ep
->X_op
== O_subtract
2486 && now_seg
== text_section
2487 && r
== BFD_RELOC_PCREL_HI16_S
)));
2488 if (ep
->X_op
== O_constant
)
2490 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2492 r
= BFD_RELOC_UNUSED
;
2497 assert (ep
!= NULL
);
2499 * This allows macro() to pass an immediate expression for
2500 * creating short branches without creating a symbol.
2501 * Note that the expression still might come from the assembly
2502 * input, in which case the value is not checked for range nor
2503 * is a relocation entry generated (yuck).
2505 if (ep
->X_op
== O_constant
)
2507 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2511 r
= BFD_RELOC_16_PCREL_S2
;
2515 assert (ep
!= NULL
);
2516 r
= BFD_RELOC_MIPS_JMP
;
2525 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2527 append_insn (place
, &insn
, ep
, r
, false);
2531 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2539 struct mips_cl_insn insn
;
2540 bfd_reloc_code_real_type r
;
2542 r
= BFD_RELOC_UNUSED
;
2543 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2544 assert (insn
.insn_mo
);
2545 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2547 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2548 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2551 assert (insn
.insn_mo
->name
);
2552 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2555 insn
.insn_opcode
= insn
.insn_mo
->match
;
2556 insn
.use_extend
= false;
2575 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2580 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2584 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2588 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2598 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2605 regno
= va_arg (args
, int);
2606 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2607 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2628 assert (ep
!= NULL
);
2630 if (ep
->X_op
!= O_constant
)
2631 r
= BFD_RELOC_UNUSED
+ c
;
2634 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2635 false, false, &insn
.insn_opcode
,
2636 &insn
.use_extend
, &insn
.extend
);
2638 r
= BFD_RELOC_UNUSED
;
2644 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2651 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2653 append_insn (place
, &insn
, ep
, r
, false);
2657 * Generate a "lui" instruction.
2660 macro_build_lui (place
, counter
, ep
, regnum
)
2666 expressionS high_expr
;
2667 struct mips_cl_insn insn
;
2668 bfd_reloc_code_real_type r
;
2669 CONST
char *name
= "lui";
2670 CONST
char *fmt
= "t,u";
2672 assert (! mips_opts
.mips16
);
2678 high_expr
.X_op
= O_constant
;
2679 high_expr
.X_add_number
= ep
->X_add_number
;
2682 if (high_expr
.X_op
== O_constant
)
2684 /* we can compute the instruction now without a relocation entry */
2685 if (high_expr
.X_add_number
& 0x8000)
2686 high_expr
.X_add_number
+= 0x10000;
2687 high_expr
.X_add_number
=
2688 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2689 r
= BFD_RELOC_UNUSED
;
2693 assert (ep
->X_op
== O_symbol
);
2694 /* _gp_disp is a special case, used from s_cpload. */
2695 assert (mips_pic
== NO_PIC
2696 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2697 r
= BFD_RELOC_HI16_S
;
2701 * If the macro is about to expand into a second instruction,
2702 * print a warning if needed. We need to pass ip as a parameter
2703 * to generate a better warning message here...
2705 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2706 as_warn ("Macro instruction expanded into multiple instructions");
2709 *counter
+= 1; /* bump instruction counter */
2711 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2712 assert (insn
.insn_mo
);
2713 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2714 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2716 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2717 if (r
== BFD_RELOC_UNUSED
)
2719 insn
.insn_opcode
|= high_expr
.X_add_number
;
2720 append_insn (place
, &insn
, NULL
, r
, false);
2723 append_insn (place
, &insn
, &high_expr
, r
, false);
2727 * Generates code to set the $at register to true (one)
2728 * if reg is less than the immediate expression.
2731 set_at (counter
, reg
, unsignedp
)
2736 if (imm_expr
.X_op
== O_constant
2737 && imm_expr
.X_add_number
>= -0x8000
2738 && imm_expr
.X_add_number
< 0x8000)
2739 macro_build ((char *) NULL
, counter
, &imm_expr
,
2740 unsignedp
? "sltiu" : "slti",
2741 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2744 load_register (counter
, AT
, &imm_expr
, 0);
2745 macro_build ((char *) NULL
, counter
, NULL
,
2746 unsignedp
? "sltu" : "slt",
2747 "d,v,t", AT
, reg
, AT
);
2751 /* Warn if an expression is not a constant. */
2754 check_absolute_expr (ip
, ex
)
2755 struct mips_cl_insn
*ip
;
2758 if (ex
->X_op
== O_big
)
2759 as_bad ("unsupported large constant");
2760 else if (ex
->X_op
!= O_constant
)
2761 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2764 /* Count the leading zeroes by performing a binary chop. This is a
2765 bulky bit of source, but performance is a LOT better for the
2766 majority of values than a simple loop to count the bits:
2767 for (lcnt = 0; (lcnt < 32); lcnt++)
2768 if ((v) & (1 << (31 - lcnt)))
2770 However it is not code size friendly, and the gain will drop a bit
2771 on certain cached systems.
2773 #define COUNT_TOP_ZEROES(v) \
2774 (((v) & ~0xffff) == 0 \
2775 ? ((v) & ~0xff) == 0 \
2776 ? ((v) & ~0xf) == 0 \
2777 ? ((v) & ~0x3) == 0 \
2778 ? ((v) & ~0x1) == 0 \
2783 : ((v) & ~0x7) == 0 \
2786 : ((v) & ~0x3f) == 0 \
2787 ? ((v) & ~0x1f) == 0 \
2790 : ((v) & ~0x7f) == 0 \
2793 : ((v) & ~0xfff) == 0 \
2794 ? ((v) & ~0x3ff) == 0 \
2795 ? ((v) & ~0x1ff) == 0 \
2798 : ((v) & ~0x7ff) == 0 \
2801 : ((v) & ~0x3fff) == 0 \
2802 ? ((v) & ~0x1fff) == 0 \
2805 : ((v) & ~0x7fff) == 0 \
2808 : ((v) & ~0xffffff) == 0 \
2809 ? ((v) & ~0xfffff) == 0 \
2810 ? ((v) & ~0x3ffff) == 0 \
2811 ? ((v) & ~0x1ffff) == 0 \
2814 : ((v) & ~0x7ffff) == 0 \
2817 : ((v) & ~0x3fffff) == 0 \
2818 ? ((v) & ~0x1fffff) == 0 \
2821 : ((v) & ~0x7fffff) == 0 \
2824 : ((v) & ~0xfffffff) == 0 \
2825 ? ((v) & ~0x3ffffff) == 0 \
2826 ? ((v) & ~0x1ffffff) == 0 \
2829 : ((v) & ~0x7ffffff) == 0 \
2832 : ((v) & ~0x3fffffff) == 0 \
2833 ? ((v) & ~0x1fffffff) == 0 \
2836 : ((v) & ~0x7fffffff) == 0 \
2841 * This routine generates the least number of instructions neccessary to load
2842 * an absolute expression value into a register.
2845 load_register (counter
, reg
, ep
, dbl
)
2852 expressionS hi32
, lo32
;
2854 if (ep
->X_op
!= O_big
)
2856 assert (ep
->X_op
== O_constant
);
2857 if (ep
->X_add_number
< 0x8000
2858 && (ep
->X_add_number
>= 0
2859 || (ep
->X_add_number
>= -0x8000
2862 || sizeof (ep
->X_add_number
) > 4))))
2864 /* We can handle 16 bit signed values with an addiu to
2865 $zero. No need to ever use daddiu here, since $zero and
2866 the result are always correct in 32 bit mode. */
2867 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2868 (int) BFD_RELOC_LO16
);
2871 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2873 /* We can handle 16 bit unsigned values with an ori to
2875 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2876 (int) BFD_RELOC_LO16
);
2879 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2880 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2881 == ~ (offsetT
) 0x7fffffff))
2884 || sizeof (ep
->X_add_number
) > 4
2885 || (ep
->X_add_number
& 0x80000000) == 0))
2886 || ((mips_opts
.isa
< 3 || ! dbl
)
2887 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2888 || (mips_opts
.isa
< 3
2890 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2891 == ~ (offsetT
) 0xffffffff)))
2893 /* 32 bit values require an lui. */
2894 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2895 (int) BFD_RELOC_HI16
);
2896 if ((ep
->X_add_number
& 0xffff) != 0)
2897 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2898 (int) BFD_RELOC_LO16
);
2903 /* The value is larger than 32 bits. */
2905 if (mips_opts
.isa
< 3)
2907 as_bad ("Number larger than 32 bits");
2908 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2909 (int) BFD_RELOC_LO16
);
2913 if (ep
->X_op
!= O_big
)
2916 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2917 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2918 hi32
.X_add_number
&= 0xffffffff;
2920 lo32
.X_add_number
&= 0xffffffff;
2924 assert (ep
->X_add_number
> 2);
2925 if (ep
->X_add_number
== 3)
2926 generic_bignum
[3] = 0;
2927 else if (ep
->X_add_number
> 4)
2928 as_bad ("Number larger than 64 bits");
2929 lo32
.X_op
= O_constant
;
2930 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2931 hi32
.X_op
= O_constant
;
2932 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2935 if (hi32
.X_add_number
== 0)
2940 unsigned long hi
, lo
;
2942 if (hi32
.X_add_number
== 0xffffffff)
2944 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2946 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2947 reg
, 0, (int) BFD_RELOC_LO16
);
2950 if (lo32
.X_add_number
& 0x80000000)
2952 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2953 (int) BFD_RELOC_HI16
);
2954 if (lo32
.X_add_number
& 0xffff)
2955 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2956 reg
, reg
, (int) BFD_RELOC_LO16
);
2961 /* Check for 16bit shifted constant. We know that hi32 is
2962 non-zero, so start the mask on the first bit of the hi32
2967 unsigned long himask
, lomask
;
2971 himask
= 0xffff >> (32 - shift
);
2972 lomask
= (0xffff << shift
) & 0xffffffff;
2976 himask
= 0xffff << (shift
- 32);
2979 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2980 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2984 tmp
.X_op
= O_constant
;
2986 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2987 | (lo32
.X_add_number
>> shift
));
2989 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2990 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2991 (int) BFD_RELOC_LO16
);
2992 macro_build ((char *) NULL
, counter
, NULL
,
2993 (shift
>= 32) ? "dsll32" : "dsll",
2995 (shift
>= 32) ? shift
- 32 : shift
);
2999 } while (shift
<= (64 - 16));
3001 /* Find the bit number of the lowest one bit, and store the
3002 shifted value in hi/lo. */
3003 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3004 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3008 while ((lo
& 1) == 0)
3013 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3019 while ((hi
& 1) == 0)
3028 /* Optimize if the shifted value is a (power of 2) - 1. */
3029 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3030 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3032 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3037 /* This instruction will set the register to be all
3039 tmp
.X_op
= O_constant
;
3040 tmp
.X_add_number
= (offsetT
) -1;
3041 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3042 reg
, 0, (int) BFD_RELOC_LO16
);
3046 macro_build ((char *) NULL
, counter
, NULL
,
3047 (bit
>= 32) ? "dsll32" : "dsll",
3049 (bit
>= 32) ? bit
- 32 : bit
);
3051 macro_build ((char *) NULL
, counter
, NULL
,
3052 (shift
>= 32) ? "dsrl32" : "dsrl",
3054 (shift
>= 32) ? shift
- 32 : shift
);
3059 /* Sign extend hi32 before calling load_register, because we can
3060 generally get better code when we load a sign extended value. */
3061 if ((hi32
.X_add_number
& 0x80000000) != 0)
3062 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3063 load_register (counter
, reg
, &hi32
, 0);
3066 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3070 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3079 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3081 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3082 (int) BFD_RELOC_HI16
);
3083 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3090 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3095 mid16
.X_add_number
>>= 16;
3096 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3097 freg
, (int) BFD_RELOC_LO16
);
3098 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3102 if ((lo32
.X_add_number
& 0xffff) != 0)
3103 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3104 (int) BFD_RELOC_LO16
);
3107 /* Load an address into a register. */
3110 load_address (counter
, reg
, ep
)
3117 if (ep
->X_op
!= O_constant
3118 && ep
->X_op
!= O_symbol
)
3120 as_bad ("expression too complex");
3121 ep
->X_op
= O_constant
;
3124 if (ep
->X_op
== O_constant
)
3126 load_register (counter
, reg
, ep
, 0);
3130 if (mips_pic
== NO_PIC
)
3132 /* If this is a reference to a GP relative symbol, we want
3133 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3135 lui $reg,<sym> (BFD_RELOC_HI16_S)
3136 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3137 If we have an addend, we always use the latter form. */
3138 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3139 || nopic_need_relax (ep
->X_add_symbol
, 1))
3144 macro_build ((char *) NULL
, counter
, ep
,
3145 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3146 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3147 p
= frag_var (rs_machine_dependent
, 8, 0,
3148 RELAX_ENCODE (4, 8, 0, 4, 0,
3149 mips_opts
.warn_about_macros
),
3150 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3152 macro_build_lui (p
, counter
, ep
, reg
);
3155 macro_build (p
, counter
, ep
,
3156 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3157 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3159 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3163 /* If this is a reference to an external symbol, we want
3164 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3166 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3168 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3169 If there is a constant, it must be added in after. */
3170 ex
.X_add_number
= ep
->X_add_number
;
3171 ep
->X_add_number
= 0;
3173 macro_build ((char *) NULL
, counter
, ep
,
3174 mips_opts
.isa
< 3 ? "lw" : "ld",
3175 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3176 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3177 p
= frag_var (rs_machine_dependent
, 4, 0,
3178 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3179 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3180 macro_build (p
, counter
, ep
,
3181 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3182 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3183 if (ex
.X_add_number
!= 0)
3185 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3186 as_bad ("PIC code offset overflow (max 16 signed bits)");
3187 ex
.X_op
= O_constant
;
3188 macro_build ((char *) NULL
, counter
, &ex
,
3189 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3190 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3193 else if (mips_pic
== SVR4_PIC
)
3198 /* This is the large GOT case. If this is a reference to an
3199 external symbol, we want
3200 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3202 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3203 Otherwise, for a reference to a local symbol, we want
3204 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3206 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3207 If there is a constant, it must be added in after. */
3208 ex
.X_add_number
= ep
->X_add_number
;
3209 ep
->X_add_number
= 0;
3210 if (reg_needs_delay (GP
))
3215 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3216 (int) BFD_RELOC_MIPS_GOT_HI16
);
3217 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3218 mips_opts
.isa
< 3 ? "addu" : "daddu",
3219 "d,v,t", reg
, reg
, GP
);
3220 macro_build ((char *) NULL
, counter
, ep
,
3221 mips_opts
.isa
< 3 ? "lw" : "ld",
3222 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3223 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3224 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3225 mips_opts
.warn_about_macros
),
3226 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3229 /* We need a nop before loading from $gp. This special
3230 check is required because the lui which starts the main
3231 instruction stream does not refer to $gp, and so will not
3232 insert the nop which may be required. */
3233 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3236 macro_build (p
, counter
, ep
,
3237 mips_opts
.isa
< 3 ? "lw" : "ld",
3238 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3240 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3242 macro_build (p
, counter
, ep
,
3243 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3244 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3245 if (ex
.X_add_number
!= 0)
3247 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3248 as_bad ("PIC code offset overflow (max 16 signed bits)");
3249 ex
.X_op
= O_constant
;
3250 macro_build ((char *) NULL
, counter
, &ex
,
3251 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3252 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3255 else if (mips_pic
== EMBEDDED_PIC
)
3258 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3260 macro_build ((char *) NULL
, counter
, ep
,
3261 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3262 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3270 * This routine implements the seemingly endless macro or synthesized
3271 * instructions and addressing modes in the mips assembly language. Many
3272 * of these macros are simple and are similar to each other. These could
3273 * probably be handled by some kind of table or grammer aproach instead of
3274 * this verbose method. Others are not simple macros but are more like
3275 * optimizing code generation.
3276 * One interesting optimization is when several store macros appear
3277 * consecutivly that would load AT with the upper half of the same address.
3278 * The ensuing load upper instructions are ommited. This implies some kind
3279 * of global optimization. We currently only optimize within a single macro.
3280 * For many of the load and store macros if the address is specified as a
3281 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3282 * first load register 'at' with zero and use it as the base register. The
3283 * mips assembler simply uses register $zero. Just one tiny optimization
3288 struct mips_cl_insn
*ip
;
3290 register int treg
, sreg
, dreg
, breg
;
3305 bfd_reloc_code_real_type r
;
3307 int hold_mips_optimize
;
3309 assert (! mips_opts
.mips16
);
3311 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3312 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3313 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3314 mask
= ip
->insn_mo
->mask
;
3316 expr1
.X_op
= O_constant
;
3317 expr1
.X_op_symbol
= NULL
;
3318 expr1
.X_add_symbol
= NULL
;
3319 expr1
.X_add_number
= 1;
3331 mips_emit_delays (true);
3332 ++mips_opts
.noreorder
;
3333 mips_any_noreorder
= 1;
3335 expr1
.X_add_number
= 8;
3336 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3338 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3340 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3341 macro_build ((char *) NULL
, &icnt
, NULL
,
3342 dbl
? "dsub" : "sub",
3343 "d,v,t", dreg
, 0, sreg
);
3345 --mips_opts
.noreorder
;
3366 if (imm_expr
.X_op
== O_constant
3367 && imm_expr
.X_add_number
>= -0x8000
3368 && imm_expr
.X_add_number
< 0x8000)
3370 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3371 (int) BFD_RELOC_LO16
);
3374 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3375 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3394 if (imm_expr
.X_op
== O_constant
3395 && imm_expr
.X_add_number
>= 0
3396 && imm_expr
.X_add_number
< 0x10000)
3398 if (mask
!= M_NOR_I
)
3399 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3400 sreg
, (int) BFD_RELOC_LO16
);
3403 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3404 treg
, sreg
, (int) BFD_RELOC_LO16
);
3405 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3411 load_register (&icnt
, AT
, &imm_expr
, 0);
3412 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3429 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3431 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3435 load_register (&icnt
, AT
, &imm_expr
, 0);
3436 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3445 likely
? "bgezl" : "bgez",
3451 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3452 likely
? "blezl" : "blez",
3456 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3457 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3458 likely
? "beql" : "beq",
3465 /* check for > max integer */
3466 maxnum
= 0x7fffffff;
3467 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3474 if (imm_expr
.X_op
== O_constant
3475 && imm_expr
.X_add_number
>= maxnum
3476 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3479 /* result is always false */
3482 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3483 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3487 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3488 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3493 if (imm_expr
.X_op
!= O_constant
)
3494 as_bad ("Unsupported large constant");
3495 imm_expr
.X_add_number
++;
3499 if (mask
== M_BGEL_I
)
3501 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3503 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3504 likely
? "bgezl" : "bgez",
3508 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3510 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3511 likely
? "bgtzl" : "bgtz",
3515 maxnum
= 0x7fffffff;
3516 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3523 maxnum
= - maxnum
- 1;
3524 if (imm_expr
.X_op
== O_constant
3525 && imm_expr
.X_add_number
<= maxnum
3526 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3529 /* result is always true */
3530 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3531 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3534 set_at (&icnt
, sreg
, 0);
3535 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3536 likely
? "beql" : "beq",
3547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3548 likely
? "beql" : "beq",
3552 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3554 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3555 likely
? "beql" : "beq",
3563 || (mips_opts
.isa
< 3
3564 && imm_expr
.X_op
== O_constant
3565 && imm_expr
.X_add_number
== 0xffffffff))
3567 if (imm_expr
.X_op
!= O_constant
)
3568 as_bad ("Unsupported large constant");
3569 imm_expr
.X_add_number
++;
3573 if (mask
== M_BGEUL_I
)
3575 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3577 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3579 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3580 likely
? "bnel" : "bne",
3584 set_at (&icnt
, sreg
, 1);
3585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3586 likely
? "beql" : "beq",
3595 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3596 likely
? "bgtzl" : "bgtz",
3602 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3603 likely
? "bltzl" : "bltz",
3607 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3608 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3609 likely
? "bnel" : "bne",
3618 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3619 likely
? "bnel" : "bne",
3625 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3627 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3628 likely
? "bnel" : "bne",
3637 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3638 likely
? "blezl" : "blez",
3644 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3645 likely
? "bgezl" : "bgez",
3649 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3650 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3651 likely
? "beql" : "beq",
3658 maxnum
= 0x7fffffff;
3659 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3666 if (imm_expr
.X_op
== O_constant
3667 && imm_expr
.X_add_number
>= maxnum
3668 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3670 if (imm_expr
.X_op
!= O_constant
)
3671 as_bad ("Unsupported large constant");
3672 imm_expr
.X_add_number
++;
3676 if (mask
== M_BLTL_I
)
3678 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3680 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3681 likely
? "bltzl" : "bltz",
3685 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3687 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3688 likely
? "blezl" : "blez",
3692 set_at (&icnt
, sreg
, 0);
3693 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3694 likely
? "bnel" : "bne",
3703 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3704 likely
? "beql" : "beq",
3710 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3712 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3713 likely
? "beql" : "beq",
3721 || (mips_opts
.isa
< 3
3722 && imm_expr
.X_op
== O_constant
3723 && imm_expr
.X_add_number
== 0xffffffff))
3725 if (imm_expr
.X_op
!= O_constant
)
3726 as_bad ("Unsupported large constant");
3727 imm_expr
.X_add_number
++;
3731 if (mask
== M_BLTUL_I
)
3733 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3735 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3737 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3738 likely
? "beql" : "beq",
3742 set_at (&icnt
, sreg
, 1);
3743 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3744 likely
? "bnel" : "bne",
3753 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3754 likely
? "bltzl" : "bltz",
3760 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3761 likely
? "bgtzl" : "bgtz",
3765 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3766 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3767 likely
? "bnel" : "bne",
3778 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3779 likely
? "bnel" : "bne",
3783 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3785 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3786 likely
? "bnel" : "bne",
3802 as_warn ("Divide by zero.");
3804 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3806 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3810 mips_emit_delays (true);
3811 ++mips_opts
.noreorder
;
3812 mips_any_noreorder
= 1;
3813 macro_build ((char *) NULL
, &icnt
, NULL
,
3814 dbl
? "ddiv" : "div",
3815 "z,s,t", sreg
, treg
);
3817 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3820 expr1
.X_add_number
= 8;
3821 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3822 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3823 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3825 expr1
.X_add_number
= -1;
3826 macro_build ((char *) NULL
, &icnt
, &expr1
,
3827 dbl
? "daddiu" : "addiu",
3828 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3829 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3830 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3833 expr1
.X_add_number
= 1;
3834 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3835 (int) BFD_RELOC_LO16
);
3836 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3841 expr1
.X_add_number
= 0x80000000;
3842 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3843 (int) BFD_RELOC_HI16
);
3846 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3849 expr1
.X_add_number
= 8;
3850 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3851 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3852 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3854 --mips_opts
.noreorder
;
3855 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3894 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3896 as_warn ("Divide by zero.");
3898 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3900 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3903 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3905 if (strcmp (s2
, "mflo") == 0)
3906 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3909 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3912 if (imm_expr
.X_op
== O_constant
3913 && imm_expr
.X_add_number
== -1
3914 && s
[strlen (s
) - 1] != 'u')
3916 if (strcmp (s2
, "mflo") == 0)
3919 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3922 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3926 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3930 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3931 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3932 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3951 mips_emit_delays (true);
3952 ++mips_opts
.noreorder
;
3953 mips_any_noreorder
= 1;
3954 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3956 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3959 expr1
.X_add_number
= 8;
3960 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3961 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3962 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3964 --mips_opts
.noreorder
;
3965 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3971 /* Load the address of a symbol into a register. If breg is not
3972 zero, we then add a base register to it. */
3974 /* When generating embedded PIC code, we permit expressions of
3977 where bar is an address in the .text section. These are used
3978 when getting the addresses of functions. We don't permit
3979 X_add_number to be non-zero, because if the symbol is
3980 external the relaxing code needs to know that any addend is
3981 purely the offset to X_op_symbol. */
3982 if (mips_pic
== EMBEDDED_PIC
3983 && offset_expr
.X_op
== O_subtract
3984 && now_seg
== text_section
3985 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3986 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3987 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3988 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3989 ->sy_value
.X_add_symbol
)
3992 && offset_expr
.X_add_number
== 0)
3994 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3995 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3996 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3997 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3998 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4002 if (offset_expr
.X_op
!= O_symbol
4003 && offset_expr
.X_op
!= O_constant
)
4005 as_bad ("expression too complex");
4006 offset_expr
.X_op
= O_constant
;
4020 if (offset_expr
.X_op
== O_constant
)
4021 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4022 else if (mips_pic
== NO_PIC
)
4024 /* If this is a reference to an GP relative symbol, we want
4025 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4027 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4028 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4029 If we have a constant, we need two instructions anyhow,
4030 so we may as well always use the latter form. */
4031 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4032 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4037 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4038 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4039 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4040 p
= frag_var (rs_machine_dependent
, 8, 0,
4041 RELAX_ENCODE (4, 8, 0, 4, 0,
4042 mips_opts
.warn_about_macros
),
4043 offset_expr
.X_add_symbol
, (offsetT
) 0,
4046 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4049 macro_build (p
, &icnt
, &offset_expr
,
4050 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4051 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4053 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4055 /* If this is a reference to an external symbol, and there
4056 is no constant, we want
4057 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4058 For a local symbol, we want
4059 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4061 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4063 If we have a small constant, and this is a reference to
4064 an external symbol, we want
4065 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4067 addiu $tempreg,$tempreg,<constant>
4068 For a local symbol, we want the same instruction
4069 sequence, but we output a BFD_RELOC_LO16 reloc on the
4072 If we have a large constant, and this is a reference to
4073 an external symbol, we want
4074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4075 lui $at,<hiconstant>
4076 addiu $at,$at,<loconstant>
4077 addu $tempreg,$tempreg,$at
4078 For a local symbol, we want the same instruction
4079 sequence, but we output a BFD_RELOC_LO16 reloc on the
4080 addiu instruction. */
4081 expr1
.X_add_number
= offset_expr
.X_add_number
;
4082 offset_expr
.X_add_number
= 0;
4084 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4086 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4087 if (expr1
.X_add_number
== 0)
4095 /* We're going to put in an addu instruction using
4096 tempreg, so we may as well insert the nop right
4098 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4102 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4103 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4105 ? mips_opts
.warn_about_macros
4107 offset_expr
.X_add_symbol
, (offsetT
) 0,
4111 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4114 macro_build (p
, &icnt
, &expr1
,
4115 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4116 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4117 /* FIXME: If breg == 0, and the next instruction uses
4118 $tempreg, then if this variant case is used an extra
4119 nop will be generated. */
4121 else if (expr1
.X_add_number
>= -0x8000
4122 && expr1
.X_add_number
< 0x8000)
4124 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4126 macro_build ((char *) NULL
, &icnt
, &expr1
,
4127 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4128 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4129 (void) frag_var (rs_machine_dependent
, 0, 0,
4130 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4131 offset_expr
.X_add_symbol
, (offsetT
) 0,
4138 /* If we are going to add in a base register, and the
4139 target register and the base register are the same,
4140 then we are using AT as a temporary register. Since
4141 we want to load the constant into AT, we add our
4142 current AT (from the global offset table) and the
4143 register into the register now, and pretend we were
4144 not using a base register. */
4149 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4151 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4152 mips_opts
.isa
< 3 ? "addu" : "daddu",
4153 "d,v,t", treg
, AT
, breg
);
4159 /* Set mips_optimize around the lui instruction to avoid
4160 inserting an unnecessary nop after the lw. */
4161 hold_mips_optimize
= mips_optimize
;
4163 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4164 mips_optimize
= hold_mips_optimize
;
4166 macro_build ((char *) NULL
, &icnt
, &expr1
,
4167 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4168 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4169 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4170 mips_opts
.isa
< 3 ? "addu" : "daddu",
4171 "d,v,t", tempreg
, tempreg
, AT
);
4172 (void) frag_var (rs_machine_dependent
, 0, 0,
4173 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4174 offset_expr
.X_add_symbol
, (offsetT
) 0,
4179 else if (mips_pic
== SVR4_PIC
)
4183 /* This is the large GOT case. If this is a reference to an
4184 external symbol, and there is no constant, we want
4185 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4186 addu $tempreg,$tempreg,$gp
4187 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4188 For a local symbol, we want
4189 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4191 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4193 If we have a small constant, and this is a reference to
4194 an external symbol, we want
4195 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4196 addu $tempreg,$tempreg,$gp
4197 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4199 addiu $tempreg,$tempreg,<constant>
4200 For a local symbol, we want
4201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4203 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4205 If we have a large constant, and this is a reference to
4206 an external symbol, we want
4207 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4208 addu $tempreg,$tempreg,$gp
4209 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4210 lui $at,<hiconstant>
4211 addiu $at,$at,<loconstant>
4212 addu $tempreg,$tempreg,$at
4213 For a local symbol, we want
4214 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4215 lui $at,<hiconstant>
4216 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4217 addu $tempreg,$tempreg,$at
4219 expr1
.X_add_number
= offset_expr
.X_add_number
;
4220 offset_expr
.X_add_number
= 0;
4222 if (reg_needs_delay (GP
))
4226 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4227 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4228 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4229 mips_opts
.isa
< 3 ? "addu" : "daddu",
4230 "d,v,t", tempreg
, tempreg
, GP
);
4231 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4233 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4235 if (expr1
.X_add_number
== 0)
4243 /* We're going to put in an addu instruction using
4244 tempreg, so we may as well insert the nop right
4246 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4251 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4252 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4255 ? mips_opts
.warn_about_macros
4257 offset_expr
.X_add_symbol
, (offsetT
) 0,
4260 else if (expr1
.X_add_number
>= -0x8000
4261 && expr1
.X_add_number
< 0x8000)
4263 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4265 macro_build ((char *) NULL
, &icnt
, &expr1
,
4266 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4267 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4269 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4270 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4272 ? mips_opts
.warn_about_macros
4274 offset_expr
.X_add_symbol
, (offsetT
) 0,
4281 /* If we are going to add in a base register, and the
4282 target register and the base register are the same,
4283 then we are using AT as a temporary register. Since
4284 we want to load the constant into AT, we add our
4285 current AT (from the global offset table) and the
4286 register into the register now, and pretend we were
4287 not using a base register. */
4295 assert (tempreg
== AT
);
4296 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4299 mips_opts
.isa
< 3 ? "addu" : "daddu",
4300 "d,v,t", treg
, AT
, breg
);
4305 /* Set mips_optimize around the lui instruction to avoid
4306 inserting an unnecessary nop after the lw. */
4307 hold_mips_optimize
= mips_optimize
;
4309 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4310 mips_optimize
= hold_mips_optimize
;
4312 macro_build ((char *) NULL
, &icnt
, &expr1
,
4313 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4314 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4315 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4316 mips_opts
.isa
< 3 ? "addu" : "daddu",
4317 "d,v,t", dreg
, dreg
, AT
);
4319 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4320 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4323 ? mips_opts
.warn_about_macros
4325 offset_expr
.X_add_symbol
, (offsetT
) 0,
4333 /* This is needed because this instruction uses $gp, but
4334 the first instruction on the main stream does not. */
4335 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4338 macro_build (p
, &icnt
, &offset_expr
,
4340 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4342 if (expr1
.X_add_number
>= -0x8000
4343 && expr1
.X_add_number
< 0x8000)
4345 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4347 macro_build (p
, &icnt
, &expr1
,
4348 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4349 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4350 /* FIXME: If add_number is 0, and there was no base
4351 register, the external symbol case ended with a load,
4352 so if the symbol turns out to not be external, and
4353 the next instruction uses tempreg, an unnecessary nop
4354 will be inserted. */
4360 /* We must add in the base register now, as in the
4361 external symbol case. */
4362 assert (tempreg
== AT
);
4363 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4365 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4366 mips_opts
.isa
< 3 ? "addu" : "daddu",
4367 "d,v,t", treg
, AT
, breg
);
4370 /* We set breg to 0 because we have arranged to add
4371 it in in both cases. */
4375 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4377 macro_build (p
, &icnt
, &expr1
,
4378 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4379 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4381 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4382 mips_opts
.isa
< 3 ? "addu" : "daddu",
4383 "d,v,t", tempreg
, tempreg
, AT
);
4387 else if (mips_pic
== EMBEDDED_PIC
)
4390 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4392 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4393 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4394 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4401 mips_opts
.isa
< 3 ? "addu" : "daddu",
4402 "d,v,t", treg
, tempreg
, breg
);
4410 /* The j instruction may not be used in PIC code, since it
4411 requires an absolute address. We convert it to a b
4413 if (mips_pic
== NO_PIC
)
4414 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4416 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4419 /* The jal instructions must be handled as macros because when
4420 generating PIC code they expand to multi-instruction
4421 sequences. Normally they are simple instructions. */
4426 if (mips_pic
== NO_PIC
4427 || mips_pic
== EMBEDDED_PIC
)
4428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4430 else if (mips_pic
== SVR4_PIC
)
4432 if (sreg
!= PIC_CALL_REG
)
4433 as_warn ("MIPS PIC call to register other than $25");
4435 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4437 if (mips_cprestore_offset
< 0)
4438 as_warn ("No .cprestore pseudo-op used in PIC code");
4441 expr1
.X_add_number
= mips_cprestore_offset
;
4442 macro_build ((char *) NULL
, &icnt
, &expr1
,
4443 mips_opts
.isa
< 3 ? "lw" : "ld",
4444 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4453 if (mips_pic
== NO_PIC
)
4454 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4455 else if (mips_pic
== SVR4_PIC
)
4457 /* If this is a reference to an external symbol, and we are
4458 using a small GOT, we want
4459 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4463 lw $gp,cprestore($sp)
4464 The cprestore value is set using the .cprestore
4465 pseudo-op. If we are using a big GOT, we want
4466 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4468 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4472 lw $gp,cprestore($sp)
4473 If the symbol is not external, we want
4474 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4476 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4479 lw $gp,cprestore($sp) */
4483 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4484 mips_opts
.isa
< 3 ? "lw" : "ld",
4485 "t,o(b)", PIC_CALL_REG
,
4486 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4487 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4489 p
= frag_var (rs_machine_dependent
, 4, 0,
4490 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4491 offset_expr
.X_add_symbol
, (offsetT
) 0,
4498 if (reg_needs_delay (GP
))
4502 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4503 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4504 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4505 mips_opts
.isa
< 3 ? "addu" : "daddu",
4506 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4507 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4508 mips_opts
.isa
< 3 ? "lw" : "ld",
4509 "t,o(b)", PIC_CALL_REG
,
4510 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4511 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4513 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4514 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4516 offset_expr
.X_add_symbol
, (offsetT
) 0,
4520 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4523 macro_build (p
, &icnt
, &offset_expr
,
4524 mips_opts
.isa
< 3 ? "lw" : "ld",
4525 "t,o(b)", PIC_CALL_REG
,
4526 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4528 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4531 macro_build (p
, &icnt
, &offset_expr
,
4532 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4533 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4534 (int) BFD_RELOC_LO16
);
4535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4536 "jalr", "s", PIC_CALL_REG
);
4537 if (mips_cprestore_offset
< 0)
4538 as_warn ("No .cprestore pseudo-op used in PIC code");
4541 if (mips_opts
.noreorder
)
4542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4544 expr1
.X_add_number
= mips_cprestore_offset
;
4545 macro_build ((char *) NULL
, &icnt
, &expr1
,
4546 mips_opts
.isa
< 3 ? "lw" : "ld",
4547 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4551 else if (mips_pic
== EMBEDDED_PIC
)
4553 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4554 /* The linker may expand the call to a longer sequence which
4555 uses $at, so we must break rather than return. */
4580 /* Itbl support may require additional care here. */
4585 /* Itbl support may require additional care here. */
4590 /* Itbl support may require additional care here. */
4595 /* Itbl support may require additional care here. */
4608 /* Itbl support may require additional care here. */
4613 /* Itbl support may require additional care here. */
4618 /* Itbl support may require additional care here. */
4638 if (breg
== treg
|| coproc
|| lr
)
4660 /* Itbl support may require additional care here. */
4665 /* Itbl support may require additional care here. */
4670 /* Itbl support may require additional care here. */
4675 /* Itbl support may require additional care here. */
4693 /* Itbl support may require additional care here. */
4697 /* Itbl support may require additional care here. */
4702 /* Itbl support may require additional care here. */
4714 /* Itbl support may require additional care here. */
4715 if (mask
== M_LWC1_AB
4716 || mask
== M_SWC1_AB
4717 || mask
== M_LDC1_AB
4718 || mask
== M_SDC1_AB
4727 if (offset_expr
.X_op
!= O_constant
4728 && offset_expr
.X_op
!= O_symbol
)
4730 as_bad ("expression too complex");
4731 offset_expr
.X_op
= O_constant
;
4734 /* A constant expression in PIC code can be handled just as it
4735 is in non PIC code. */
4736 if (mips_pic
== NO_PIC
4737 || offset_expr
.X_op
== O_constant
)
4739 /* If this is a reference to a GP relative symbol, and there
4740 is no base register, we want
4741 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4742 Otherwise, if there is no base register, we want
4743 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4744 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4745 If we have a constant, we need two instructions anyhow,
4746 so we always use the latter form.
4748 If we have a base register, and this is a reference to a
4749 GP relative symbol, we want
4750 addu $tempreg,$breg,$gp
4751 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4753 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4754 addu $tempreg,$tempreg,$breg
4755 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4756 With a constant we always use the latter case. */
4759 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4760 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4765 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4766 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4767 p
= frag_var (rs_machine_dependent
, 8, 0,
4768 RELAX_ENCODE (4, 8, 0, 4, 0,
4769 (mips_opts
.warn_about_macros
4771 && mips_opts
.noat
))),
4772 offset_expr
.X_add_symbol
, (offsetT
) 0,
4776 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4779 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4780 (int) BFD_RELOC_LO16
, tempreg
);
4784 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4785 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4790 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4791 mips_opts
.isa
< 3 ? "addu" : "daddu",
4792 "d,v,t", tempreg
, breg
, GP
);
4793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4794 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4795 p
= frag_var (rs_machine_dependent
, 12, 0,
4796 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4797 offset_expr
.X_add_symbol
, (offsetT
) 0,
4800 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4803 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4804 mips_opts
.isa
< 3 ? "addu" : "daddu",
4805 "d,v,t", tempreg
, tempreg
, breg
);
4808 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4809 (int) BFD_RELOC_LO16
, tempreg
);
4812 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4814 /* If this is a reference to an external symbol, we want
4815 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4817 <op> $treg,0($tempreg)
4819 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4821 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4822 <op> $treg,0($tempreg)
4823 If there is a base register, we add it to $tempreg before
4824 the <op>. If there is a constant, we stick it in the
4825 <op> instruction. We don't handle constants larger than
4826 16 bits, because we have no way to load the upper 16 bits
4827 (actually, we could handle them for the subset of cases
4828 in which we are not using $at). */
4829 assert (offset_expr
.X_op
== O_symbol
);
4830 expr1
.X_add_number
= offset_expr
.X_add_number
;
4831 offset_expr
.X_add_number
= 0;
4832 if (expr1
.X_add_number
< -0x8000
4833 || expr1
.X_add_number
>= 0x8000)
4834 as_bad ("PIC code offset overflow (max 16 signed bits)");
4836 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4837 mips_opts
.isa
< 3 ? "lw" : "ld",
4838 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4839 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4840 p
= frag_var (rs_machine_dependent
, 4, 0,
4841 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4842 offset_expr
.X_add_symbol
, (offsetT
) 0,
4844 macro_build (p
, &icnt
, &offset_expr
,
4845 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4846 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4848 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4849 mips_opts
.isa
< 3 ? "addu" : "daddu",
4850 "d,v,t", tempreg
, tempreg
, breg
);
4851 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4852 (int) BFD_RELOC_LO16
, tempreg
);
4854 else if (mips_pic
== SVR4_PIC
)
4858 /* If this is a reference to an external symbol, we want
4859 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4860 addu $tempreg,$tempreg,$gp
4861 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4862 <op> $treg,0($tempreg)
4864 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4866 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4867 <op> $treg,0($tempreg)
4868 If there is a base register, we add it to $tempreg before
4869 the <op>. If there is a constant, we stick it in the
4870 <op> instruction. We don't handle constants larger than
4871 16 bits, because we have no way to load the upper 16 bits
4872 (actually, we could handle them for the subset of cases
4873 in which we are not using $at). */
4874 assert (offset_expr
.X_op
== O_symbol
);
4875 expr1
.X_add_number
= offset_expr
.X_add_number
;
4876 offset_expr
.X_add_number
= 0;
4877 if (expr1
.X_add_number
< -0x8000
4878 || expr1
.X_add_number
>= 0x8000)
4879 as_bad ("PIC code offset overflow (max 16 signed bits)");
4880 if (reg_needs_delay (GP
))
4885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4886 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4887 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4888 mips_opts
.isa
< 3 ? "addu" : "daddu",
4889 "d,v,t", tempreg
, tempreg
, GP
);
4890 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4891 mips_opts
.isa
< 3 ? "lw" : "ld",
4892 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4894 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4895 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4896 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
4899 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4902 macro_build (p
, &icnt
, &offset_expr
,
4903 mips_opts
.isa
< 3 ? "lw" : "ld",
4904 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4906 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4908 macro_build (p
, &icnt
, &offset_expr
,
4909 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4910 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4913 mips_opts
.isa
< 3 ? "addu" : "daddu",
4914 "d,v,t", tempreg
, tempreg
, breg
);
4915 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4916 (int) BFD_RELOC_LO16
, tempreg
);
4918 else if (mips_pic
== EMBEDDED_PIC
)
4920 /* If there is no base register, we want
4921 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4922 If there is a base register, we want
4923 addu $tempreg,$breg,$gp
4924 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4926 assert (offset_expr
.X_op
== O_symbol
);
4929 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4930 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4935 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4936 mips_opts
.isa
< 3 ? "addu" : "daddu",
4937 "d,v,t", tempreg
, breg
, GP
);
4938 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4939 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4952 load_register (&icnt
, treg
, &imm_expr
, 0);
4956 load_register (&icnt
, treg
, &imm_expr
, 1);
4960 if (imm_expr
.X_op
== O_constant
)
4962 load_register (&icnt
, AT
, &imm_expr
, 0);
4963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4964 "mtc1", "t,G", AT
, treg
);
4969 assert (offset_expr
.X_op
== O_symbol
4970 && strcmp (segment_name (S_GET_SEGMENT
4971 (offset_expr
.X_add_symbol
)),
4973 && offset_expr
.X_add_number
== 0);
4974 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4975 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4980 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
4981 the entire value, and in mips1 mode it is the high order 32
4982 bits of the value and the low order 32 bits are either zero
4983 or in offset_expr. */
4984 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
4986 load_register (&icnt
, treg
, &imm_expr
, mips_opts
.isa
>= 3);
4987 if (mips_opts
.isa
< 3 && treg
!= 31)
4989 if (offset_expr
.X_op
== O_absent
)
4990 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
4994 assert (offset_expr
.X_op
== O_constant
);
4995 load_register (&icnt
, treg
+ 1, &offset_expr
, 0);
5001 /* We know that sym is in the .rdata section. First we get the
5002 upper 16 bits of the address. */
5003 if (mips_pic
== NO_PIC
)
5005 /* FIXME: This won't work for a 64 bit address. */
5006 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5008 else if (mips_pic
== SVR4_PIC
)
5010 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5011 mips_opts
.isa
< 3 ? "lw" : "ld",
5012 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5014 else if (mips_pic
== EMBEDDED_PIC
)
5016 /* For embedded PIC we pick up the entire address off $gp in
5017 a single instruction. */
5018 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5019 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5020 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5021 offset_expr
.X_op
= O_constant
;
5022 offset_expr
.X_add_number
= 0;
5027 /* Now we load the register(s). */
5028 if (mips_opts
.isa
>= 3)
5029 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5030 treg
, (int) BFD_RELOC_LO16
, AT
);
5033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5034 treg
, (int) BFD_RELOC_LO16
, AT
);
5037 /* FIXME: How in the world do we deal with the possible
5039 offset_expr
.X_add_number
+= 4;
5040 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5041 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5045 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5046 does not become a variant frag. */
5047 frag_wane (frag_now
);
5053 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5054 the entire value, and in mips1 mode it is the high order 32
5055 bits of the value and the low order 32 bits are either zero
5056 or in offset_expr. */
5057 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5059 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5060 if (mips_opts
.isa
>= 3)
5061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5062 "dmtc1", "t,S", AT
, treg
);
5065 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5066 "mtc1", "t,G", AT
, treg
+ 1);
5067 if (offset_expr
.X_op
== O_absent
)
5068 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5069 "mtc1", "t,G", 0, treg
);
5072 assert (offset_expr
.X_op
== O_constant
);
5073 load_register (&icnt
, AT
, &offset_expr
, 0);
5074 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5075 "mtc1", "t,G", AT
, treg
);
5081 assert (offset_expr
.X_op
== O_symbol
5082 && offset_expr
.X_add_number
== 0);
5083 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5084 if (strcmp (s
, ".lit8") == 0)
5086 if (mips_opts
.isa
>= 2)
5088 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5089 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5093 r
= BFD_RELOC_MIPS_LITERAL
;
5098 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5099 if (mips_pic
== SVR4_PIC
)
5100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5101 mips_opts
.isa
< 3 ? "lw" : "ld",
5102 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5105 /* FIXME: This won't work for a 64 bit address. */
5106 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5109 if (mips_opts
.isa
>= 2)
5111 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5112 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5114 /* To avoid confusion in tc_gen_reloc, we must ensure
5115 that this does not become a variant frag. */
5116 frag_wane (frag_now
);
5127 /* Even on a big endian machine $fn comes before $fn+1. We have
5128 to adjust when loading from memory. */
5131 assert (mips_opts
.isa
< 2);
5132 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5133 target_big_endian
? treg
+ 1 : treg
,
5135 /* FIXME: A possible overflow which I don't know how to deal
5137 offset_expr
.X_add_number
+= 4;
5138 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5139 target_big_endian
? treg
: treg
+ 1,
5142 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5143 does not become a variant frag. */
5144 frag_wane (frag_now
);
5153 * The MIPS assembler seems to check for X_add_number not
5154 * being double aligned and generating:
5157 * addiu at,at,%lo(foo+1)
5160 * But, the resulting address is the same after relocation so why
5161 * generate the extra instruction?
5163 /* Itbl support may require additional care here. */
5165 if (mips_opts
.isa
>= 2)
5176 if (mips_opts
.isa
>= 2)
5184 /* Itbl support may require additional care here. */
5189 if (mips_opts
.isa
>= 3)
5200 if (mips_opts
.isa
>= 3)
5210 if (offset_expr
.X_op
!= O_symbol
5211 && offset_expr
.X_op
!= O_constant
)
5213 as_bad ("expression too complex");
5214 offset_expr
.X_op
= O_constant
;
5217 /* Even on a big endian machine $fn comes before $fn+1. We have
5218 to adjust when loading from memory. We set coproc if we must
5219 load $fn+1 first. */
5220 /* Itbl support may require additional care here. */
5221 if (! target_big_endian
)
5224 if (mips_pic
== NO_PIC
5225 || offset_expr
.X_op
== O_constant
)
5227 /* If this is a reference to a GP relative symbol, we want
5228 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5229 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5230 If we have a base register, we use this
5232 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5233 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5234 If this is not a GP relative symbol, we want
5235 lui $at,<sym> (BFD_RELOC_HI16_S)
5236 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5237 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5238 If there is a base register, we add it to $at after the
5239 lui instruction. If there is a constant, we always use
5241 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5242 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5261 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5262 mips_opts
.isa
< 3 ? "addu" : "daddu",
5263 "d,v,t", AT
, breg
, GP
);
5269 /* Itbl support may require additional care here. */
5270 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5271 coproc
? treg
+ 1 : treg
,
5272 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5273 offset_expr
.X_add_number
+= 4;
5275 /* Set mips_optimize to 2 to avoid inserting an
5277 hold_mips_optimize
= mips_optimize
;
5279 /* Itbl support may require additional care here. */
5280 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5281 coproc
? treg
: treg
+ 1,
5282 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5283 mips_optimize
= hold_mips_optimize
;
5285 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5286 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5287 used_at
&& mips_opts
.noat
),
5288 offset_expr
.X_add_symbol
, (offsetT
) 0,
5291 /* We just generated two relocs. When tc_gen_reloc
5292 handles this case, it will skip the first reloc and
5293 handle the second. The second reloc already has an
5294 extra addend of 4, which we added above. We must
5295 subtract it out, and then subtract another 4 to make
5296 the first reloc come out right. The second reloc
5297 will come out right because we are going to add 4 to
5298 offset_expr when we build its instruction below. */
5299 offset_expr
.X_add_number
-= 8;
5300 offset_expr
.X_op
= O_constant
;
5302 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5307 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5308 mips_opts
.isa
< 3 ? "addu" : "daddu",
5309 "d,v,t", AT
, breg
, AT
);
5313 /* Itbl support may require additional care here. */
5314 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5315 coproc
? treg
+ 1 : treg
,
5316 (int) BFD_RELOC_LO16
, AT
);
5319 /* FIXME: How do we handle overflow here? */
5320 offset_expr
.X_add_number
+= 4;
5321 /* Itbl support may require additional care here. */
5322 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5323 coproc
? treg
: treg
+ 1,
5324 (int) BFD_RELOC_LO16
, AT
);
5326 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5330 /* If this is a reference to an external symbol, we want
5331 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5336 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5338 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5339 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5340 If there is a base register we add it to $at before the
5341 lwc1 instructions. If there is a constant we include it
5342 in the lwc1 instructions. */
5344 expr1
.X_add_number
= offset_expr
.X_add_number
;
5345 offset_expr
.X_add_number
= 0;
5346 if (expr1
.X_add_number
< -0x8000
5347 || expr1
.X_add_number
>= 0x8000 - 4)
5348 as_bad ("PIC code offset overflow (max 16 signed bits)");
5353 frag_grow (24 + off
);
5354 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5355 mips_opts
.isa
< 3 ? "lw" : "ld",
5356 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5357 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5359 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5360 mips_opts
.isa
< 3 ? "addu" : "daddu",
5361 "d,v,t", AT
, breg
, AT
);
5362 /* Itbl support may require additional care here. */
5363 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5364 coproc
? treg
+ 1 : treg
,
5365 (int) BFD_RELOC_LO16
, AT
);
5366 expr1
.X_add_number
+= 4;
5368 /* Set mips_optimize to 2 to avoid inserting an undesired
5370 hold_mips_optimize
= mips_optimize
;
5372 /* Itbl support may require additional care here. */
5373 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5374 coproc
? treg
: treg
+ 1,
5375 (int) BFD_RELOC_LO16
, AT
);
5376 mips_optimize
= hold_mips_optimize
;
5378 (void) frag_var (rs_machine_dependent
, 0, 0,
5379 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5380 offset_expr
.X_add_symbol
, (offsetT
) 0,
5383 else if (mips_pic
== SVR4_PIC
)
5387 /* If this is a reference to an external symbol, we want
5388 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5390 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5395 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5397 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5398 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5399 If there is a base register we add it to $at before the
5400 lwc1 instructions. If there is a constant we include it
5401 in the lwc1 instructions. */
5403 expr1
.X_add_number
= offset_expr
.X_add_number
;
5404 offset_expr
.X_add_number
= 0;
5405 if (expr1
.X_add_number
< -0x8000
5406 || expr1
.X_add_number
>= 0x8000 - 4)
5407 as_bad ("PIC code offset overflow (max 16 signed bits)");
5408 if (reg_needs_delay (GP
))
5417 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5418 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5419 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5420 mips_opts
.isa
< 3 ? "addu" : "daddu",
5421 "d,v,t", AT
, AT
, GP
);
5422 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5423 mips_opts
.isa
< 3 ? "lw" : "ld",
5424 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5427 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5428 mips_opts
.isa
< 3 ? "addu" : "daddu",
5429 "d,v,t", AT
, breg
, AT
);
5430 /* Itbl support may require additional care here. */
5431 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5432 coproc
? treg
+ 1 : treg
,
5433 (int) BFD_RELOC_LO16
, AT
);
5434 expr1
.X_add_number
+= 4;
5436 /* Set mips_optimize to 2 to avoid inserting an undesired
5438 hold_mips_optimize
= mips_optimize
;
5440 /* Itbl support may require additional care here. */
5441 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5442 coproc
? treg
: treg
+ 1,
5443 (int) BFD_RELOC_LO16
, AT
);
5444 mips_optimize
= hold_mips_optimize
;
5445 expr1
.X_add_number
-= 4;
5447 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5448 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5449 8 + gpdel
+ off
, 1, 0),
5450 offset_expr
.X_add_symbol
, (offsetT
) 0,
5454 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5457 macro_build (p
, &icnt
, &offset_expr
,
5458 mips_opts
.isa
< 3 ? "lw" : "ld",
5459 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5461 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5465 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5466 mips_opts
.isa
< 3 ? "addu" : "daddu",
5467 "d,v,t", AT
, breg
, AT
);
5470 /* Itbl support may require additional care here. */
5471 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5472 coproc
? treg
+ 1 : treg
,
5473 (int) BFD_RELOC_LO16
, AT
);
5475 expr1
.X_add_number
+= 4;
5477 /* Set mips_optimize to 2 to avoid inserting an undesired
5479 hold_mips_optimize
= mips_optimize
;
5481 /* Itbl support may require additional care here. */
5482 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5483 coproc
? treg
: treg
+ 1,
5484 (int) BFD_RELOC_LO16
, AT
);
5485 mips_optimize
= hold_mips_optimize
;
5487 else if (mips_pic
== EMBEDDED_PIC
)
5489 /* If there is no base register, we use
5490 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5491 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5492 If we have a base register, we use
5494 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5495 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5504 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5505 mips_opts
.isa
< 3 ? "addu" : "daddu",
5506 "d,v,t", AT
, breg
, GP
);
5511 /* Itbl support may require additional care here. */
5512 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5513 coproc
? treg
+ 1 : treg
,
5514 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5515 offset_expr
.X_add_number
+= 4;
5516 /* Itbl support may require additional care here. */
5517 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5518 coproc
? treg
: treg
+ 1,
5519 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5535 assert (mips_opts
.isa
< 3);
5536 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5537 (int) BFD_RELOC_LO16
, breg
);
5538 offset_expr
.X_add_number
+= 4;
5539 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5540 (int) BFD_RELOC_LO16
, breg
);
5543 /* New code added to support COPZ instructions.
5544 This code builds table entries out of the macros in mip_opcodes.
5545 R4000 uses interlocks to handle coproc delays.
5546 Other chips (like the R3000) require nops to be inserted for delays.
5548 FIXME: Currently, we require that the user handle delays.
5549 In order to fill delay slots for non-interlocked chips,
5550 we must have a way to specify delays based on the coprocessor.
5551 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5552 What are the side-effects of the cop instruction?
5553 What cache support might we have and what are its effects?
5554 Both coprocessor & memory require delays. how long???
5555 What registers are read/set/modified?
5557 If an itbl is provided to interpret cop instructions,
5558 this knowledge can be encoded in the itbl spec. */
5572 /* For now we just do C (same as Cz). */
5573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5576 #ifdef LOSING_COMPILER
5578 /* Try and see if this is a new itbl instruction.
5579 This code builds table entries out of the macros in mip_opcodes.
5580 FIXME: For now we just assemble the expression and pass it's
5581 value along as a 32-bit immediate.
5582 We may want to have the assembler assemble this value,
5583 so that we gain the assembler's knowledge of delay slots,
5585 Would it be more efficient to use mask (id) here? */
5586 if (itbl_have_entries
5587 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5589 s
= ip
->insn_mo
->name
;
5591 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5592 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5599 as_warn ("Macro used $at after \".set noat\"");
5604 struct mips_cl_insn
*ip
;
5606 register int treg
, sreg
, dreg
, breg
;
5621 bfd_reloc_code_real_type r
;
5624 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5625 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5626 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5627 mask
= ip
->insn_mo
->mask
;
5629 expr1
.X_op
= O_constant
;
5630 expr1
.X_op_symbol
= NULL
;
5631 expr1
.X_add_symbol
= NULL
;
5632 expr1
.X_add_number
= 1;
5636 #endif /* LOSING_COMPILER */
5641 macro_build ((char *) NULL
, &icnt
, NULL
,
5642 dbl
? "dmultu" : "multu",
5644 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5650 /* The MIPS assembler some times generates shifts and adds. I'm
5651 not trying to be that fancy. GCC should do this for us
5653 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5654 macro_build ((char *) NULL
, &icnt
, NULL
,
5655 dbl
? "dmult" : "mult",
5657 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5663 mips_emit_delays (true);
5664 ++mips_opts
.noreorder
;
5665 mips_any_noreorder
= 1;
5666 macro_build ((char *) NULL
, &icnt
, NULL
,
5667 dbl
? "dmult" : "mult",
5669 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5670 macro_build ((char *) NULL
, &icnt
, NULL
,
5671 dbl
? "dsra32" : "sra",
5672 "d,w,<", dreg
, dreg
, 31);
5673 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5675 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5678 expr1
.X_add_number
= 8;
5679 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5680 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5681 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5683 --mips_opts
.noreorder
;
5684 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5690 mips_emit_delays (true);
5691 ++mips_opts
.noreorder
;
5692 mips_any_noreorder
= 1;
5693 macro_build ((char *) NULL
, &icnt
, NULL
,
5694 dbl
? "dmultu" : "multu",
5696 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5697 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5699 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5702 expr1
.X_add_number
= 8;
5703 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5704 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5705 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5707 --mips_opts
.noreorder
;
5711 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5712 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5713 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5715 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5719 if (imm_expr
.X_op
!= O_constant
)
5720 as_bad ("rotate count too large");
5721 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5722 (int) (imm_expr
.X_add_number
& 0x1f));
5723 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5724 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5725 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5729 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5730 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5731 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5733 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5737 if (imm_expr
.X_op
!= O_constant
)
5738 as_bad ("rotate count too large");
5739 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5740 (int) (imm_expr
.X_add_number
& 0x1f));
5741 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5742 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5743 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5747 assert (mips_opts
.isa
< 2);
5748 /* Even on a big endian machine $fn comes before $fn+1. We have
5749 to adjust when storing to memory. */
5750 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5751 target_big_endian
? treg
+ 1 : treg
,
5752 (int) BFD_RELOC_LO16
, breg
);
5753 offset_expr
.X_add_number
+= 4;
5754 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5755 target_big_endian
? treg
: treg
+ 1,
5756 (int) BFD_RELOC_LO16
, breg
);
5761 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5762 treg
, (int) BFD_RELOC_LO16
);
5764 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5765 sreg
, (int) BFD_RELOC_LO16
);
5768 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5770 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5771 dreg
, (int) BFD_RELOC_LO16
);
5776 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5778 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5779 sreg
, (int) BFD_RELOC_LO16
);
5784 as_warn ("Instruction %s: result is always false",
5786 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5789 if (imm_expr
.X_op
== O_constant
5790 && imm_expr
.X_add_number
>= 0
5791 && imm_expr
.X_add_number
< 0x10000)
5793 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5794 sreg
, (int) BFD_RELOC_LO16
);
5797 else if (imm_expr
.X_op
== O_constant
5798 && imm_expr
.X_add_number
> -0x8000
5799 && imm_expr
.X_add_number
< 0)
5801 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5802 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5803 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5804 "t,r,j", dreg
, sreg
,
5805 (int) BFD_RELOC_LO16
);
5810 load_register (&icnt
, AT
, &imm_expr
, 0);
5811 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5815 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5816 (int) BFD_RELOC_LO16
);
5821 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5827 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5828 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5829 (int) BFD_RELOC_LO16
);
5832 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5834 if (imm_expr
.X_op
== O_constant
5835 && imm_expr
.X_add_number
>= -0x8000
5836 && imm_expr
.X_add_number
< 0x8000)
5838 macro_build ((char *) NULL
, &icnt
, &expr1
,
5839 mask
== M_SGE_I
? "slti" : "sltiu",
5840 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5845 load_register (&icnt
, AT
, &imm_expr
, 0);
5846 macro_build ((char *) NULL
, &icnt
, NULL
,
5847 mask
== M_SGE_I
? "slt" : "sltu",
5848 "d,v,t", dreg
, sreg
, AT
);
5851 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5852 (int) BFD_RELOC_LO16
);
5857 case M_SGT
: /* sreg > treg <==> treg < sreg */
5863 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5866 case M_SGT_I
: /* sreg > I <==> I < sreg */
5872 load_register (&icnt
, AT
, &imm_expr
, 0);
5873 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5876 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5882 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5883 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5884 (int) BFD_RELOC_LO16
);
5887 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5893 load_register (&icnt
, AT
, &imm_expr
, 0);
5894 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5895 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5896 (int) BFD_RELOC_LO16
);
5900 if (imm_expr
.X_op
== O_constant
5901 && imm_expr
.X_add_number
>= -0x8000
5902 && imm_expr
.X_add_number
< 0x8000)
5904 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5905 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5908 load_register (&icnt
, AT
, &imm_expr
, 0);
5909 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5913 if (imm_expr
.X_op
== O_constant
5914 && imm_expr
.X_add_number
>= -0x8000
5915 && imm_expr
.X_add_number
< 0x8000)
5917 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5918 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5921 load_register (&icnt
, AT
, &imm_expr
, 0);
5922 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5928 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5931 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5935 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5937 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5943 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5945 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5951 as_warn ("Instruction %s: result is always true",
5953 macro_build ((char *) NULL
, &icnt
, &expr1
,
5954 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5955 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5958 if (imm_expr
.X_op
== O_constant
5959 && imm_expr
.X_add_number
>= 0
5960 && imm_expr
.X_add_number
< 0x10000)
5962 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5963 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5966 else if (imm_expr
.X_op
== O_constant
5967 && imm_expr
.X_add_number
> -0x8000
5968 && imm_expr
.X_add_number
< 0)
5970 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5971 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5972 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5973 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5978 load_register (&icnt
, AT
, &imm_expr
, 0);
5979 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5983 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5991 if (imm_expr
.X_op
== O_constant
5992 && imm_expr
.X_add_number
> -0x8000
5993 && imm_expr
.X_add_number
<= 0x8000)
5995 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5996 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5997 dbl
? "daddi" : "addi",
5998 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6001 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6002 macro_build ((char *) NULL
, &icnt
, NULL
,
6003 dbl
? "dsub" : "sub",
6004 "d,v,t", dreg
, sreg
, AT
);
6010 if (imm_expr
.X_op
== O_constant
6011 && imm_expr
.X_add_number
> -0x8000
6012 && imm_expr
.X_add_number
<= 0x8000)
6014 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6015 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6016 dbl
? "daddiu" : "addiu",
6017 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6020 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6021 macro_build ((char *) NULL
, &icnt
, NULL
,
6022 dbl
? "dsubu" : "subu",
6023 "d,v,t", dreg
, sreg
, AT
);
6044 load_register (&icnt
, AT
, &imm_expr
, 0);
6045 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6050 assert (mips_opts
.isa
< 2);
6051 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6052 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6055 * Is the double cfc1 instruction a bug in the mips assembler;
6056 * or is there a reason for it?
6058 mips_emit_delays (true);
6059 ++mips_opts
.noreorder
;
6060 mips_any_noreorder
= 1;
6061 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6062 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6063 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6064 expr1
.X_add_number
= 3;
6065 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6066 (int) BFD_RELOC_LO16
);
6067 expr1
.X_add_number
= 2;
6068 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6069 (int) BFD_RELOC_LO16
);
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6071 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6072 macro_build ((char *) NULL
, &icnt
, NULL
,
6073 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6074 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6075 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6076 --mips_opts
.noreorder
;
6085 if (offset_expr
.X_add_number
>= 0x7fff)
6086 as_bad ("operand overflow");
6087 /* avoid load delay */
6088 if (! target_big_endian
)
6089 offset_expr
.X_add_number
+= 1;
6090 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6091 (int) BFD_RELOC_LO16
, breg
);
6092 if (! target_big_endian
)
6093 offset_expr
.X_add_number
-= 1;
6095 offset_expr
.X_add_number
+= 1;
6096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6097 (int) BFD_RELOC_LO16
, breg
);
6098 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6099 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6112 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6113 as_bad ("operand overflow");
6114 if (! target_big_endian
)
6115 offset_expr
.X_add_number
+= off
;
6116 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6117 (int) BFD_RELOC_LO16
, breg
);
6118 if (! target_big_endian
)
6119 offset_expr
.X_add_number
-= off
;
6121 offset_expr
.X_add_number
+= off
;
6122 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6123 (int) BFD_RELOC_LO16
, breg
);
6136 load_address (&icnt
, AT
, &offset_expr
);
6138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6139 mips_opts
.isa
< 3 ? "addu" : "daddu",
6140 "d,v,t", AT
, AT
, breg
);
6141 if (! target_big_endian
)
6142 expr1
.X_add_number
= off
;
6144 expr1
.X_add_number
= 0;
6145 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6146 (int) BFD_RELOC_LO16
, AT
);
6147 if (! target_big_endian
)
6148 expr1
.X_add_number
= 0;
6150 expr1
.X_add_number
= off
;
6151 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6152 (int) BFD_RELOC_LO16
, AT
);
6157 load_address (&icnt
, AT
, &offset_expr
);
6159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6160 mips_opts
.isa
< 3 ? "addu" : "daddu",
6161 "d,v,t", AT
, AT
, breg
);
6162 if (target_big_endian
)
6163 expr1
.X_add_number
= 0;
6164 macro_build ((char *) NULL
, &icnt
, &expr1
,
6165 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6166 (int) BFD_RELOC_LO16
, AT
);
6167 if (target_big_endian
)
6168 expr1
.X_add_number
= 1;
6170 expr1
.X_add_number
= 0;
6171 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6172 (int) BFD_RELOC_LO16
, AT
);
6173 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6175 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6180 if (offset_expr
.X_add_number
>= 0x7fff)
6181 as_bad ("operand overflow");
6182 if (target_big_endian
)
6183 offset_expr
.X_add_number
+= 1;
6184 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6185 (int) BFD_RELOC_LO16
, breg
);
6186 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6187 if (target_big_endian
)
6188 offset_expr
.X_add_number
-= 1;
6190 offset_expr
.X_add_number
+= 1;
6191 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6192 (int) BFD_RELOC_LO16
, breg
);
6205 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6206 as_bad ("operand overflow");
6207 if (! target_big_endian
)
6208 offset_expr
.X_add_number
+= off
;
6209 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6210 (int) BFD_RELOC_LO16
, breg
);
6211 if (! target_big_endian
)
6212 offset_expr
.X_add_number
-= off
;
6214 offset_expr
.X_add_number
+= off
;
6215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6216 (int) BFD_RELOC_LO16
, breg
);
6229 load_address (&icnt
, AT
, &offset_expr
);
6231 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6232 mips_opts
.isa
< 3 ? "addu" : "daddu",
6233 "d,v,t", AT
, AT
, breg
);
6234 if (! target_big_endian
)
6235 expr1
.X_add_number
= off
;
6237 expr1
.X_add_number
= 0;
6238 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6239 (int) BFD_RELOC_LO16
, AT
);
6240 if (! target_big_endian
)
6241 expr1
.X_add_number
= 0;
6243 expr1
.X_add_number
= off
;
6244 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6245 (int) BFD_RELOC_LO16
, AT
);
6249 load_address (&icnt
, AT
, &offset_expr
);
6251 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6252 mips_opts
.isa
< 3 ? "addu" : "daddu",
6253 "d,v,t", AT
, AT
, breg
);
6254 if (! target_big_endian
)
6255 expr1
.X_add_number
= 0;
6256 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6257 (int) BFD_RELOC_LO16
, AT
);
6258 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6260 if (! target_big_endian
)
6261 expr1
.X_add_number
= 1;
6263 expr1
.X_add_number
= 0;
6264 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6265 (int) BFD_RELOC_LO16
, AT
);
6266 if (! target_big_endian
)
6267 expr1
.X_add_number
= 0;
6269 expr1
.X_add_number
= 1;
6270 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6271 (int) BFD_RELOC_LO16
, AT
);
6272 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6274 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6279 /* FIXME: Check if this is one of the itbl macros, since they
6280 are added dynamically. */
6281 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6285 as_warn ("Macro used $at after \".set noat\"");
6288 /* Implement macros in mips16 mode. */
6292 struct mips_cl_insn
*ip
;
6295 int xreg
, yreg
, zreg
, tmp
;
6299 const char *s
, *s2
, *s3
;
6301 mask
= ip
->insn_mo
->mask
;
6303 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6304 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6305 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6309 expr1
.X_op
= O_constant
;
6310 expr1
.X_op_symbol
= NULL
;
6311 expr1
.X_add_symbol
= NULL
;
6312 expr1
.X_add_number
= 1;
6331 mips_emit_delays (true);
6332 ++mips_opts
.noreorder
;
6333 mips_any_noreorder
= 1;
6334 macro_build ((char *) NULL
, &icnt
, NULL
,
6335 dbl
? "ddiv" : "div",
6336 "0,x,y", xreg
, yreg
);
6337 expr1
.X_add_number
= 2;
6338 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6339 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6340 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6341 since that causes an overflow. We should do that as well,
6342 but I don't see how to do the comparisons without a temporary
6344 --mips_opts
.noreorder
;
6345 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6364 mips_emit_delays (true);
6365 ++mips_opts
.noreorder
;
6366 mips_any_noreorder
= 1;
6367 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6368 expr1
.X_add_number
= 2;
6369 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6370 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6371 --mips_opts
.noreorder
;
6372 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6378 macro_build ((char *) NULL
, &icnt
, NULL
,
6379 dbl
? "dmultu" : "multu",
6381 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6389 if (imm_expr
.X_op
!= O_constant
)
6390 as_bad ("Unsupported large constant");
6391 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6392 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6393 dbl
? "daddiu" : "addiu",
6394 "y,x,4", yreg
, xreg
);
6398 if (imm_expr
.X_op
!= O_constant
)
6399 as_bad ("Unsupported large constant");
6400 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6401 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6406 if (imm_expr
.X_op
!= O_constant
)
6407 as_bad ("Unsupported large constant");
6408 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6409 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6432 goto do_reverse_branch
;
6436 goto do_reverse_branch
;
6448 goto do_reverse_branch
;
6459 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6461 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6488 goto do_addone_branch_i
;
6493 goto do_addone_branch_i
;
6508 goto do_addone_branch_i
;
6515 if (imm_expr
.X_op
!= O_constant
)
6516 as_bad ("Unsupported large constant");
6517 ++imm_expr
.X_add_number
;
6520 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6525 expr1
.X_add_number
= 0;
6526 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6529 "move", "y,X", xreg
, yreg
);
6530 expr1
.X_add_number
= 2;
6531 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6532 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6533 "neg", "x,w", xreg
, xreg
);
6537 /* This routine assembles an instruction into its binary format. As a
6538 side effect, it sets one of the global variables imm_reloc or
6539 offset_reloc to the type of relocation to do if one of the operands
6540 is an address expression. */
6545 struct mips_cl_insn
*ip
;
6550 struct mips_opcode
*insn
;
6553 unsigned int lastregno
= 0;
6558 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6563 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6565 insn_error
= "unrecognized opcode";
6574 assert (strcmp (insn
->name
, str
) == 0);
6576 if (insn
->pinfo
== INSN_MACRO
)
6577 insn_isa
= insn
->match
;
6578 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
6580 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
6582 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
6584 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
6589 if (insn_isa
<= mips_opts
.isa
)
6591 else if (insn
->pinfo
== INSN_MACRO
)
6593 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
6594 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
6595 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
6596 /* start-sanitize-r5900 */
6597 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
6598 /* end-sanitize-r5900 */
6599 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
6602 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
6604 /* start-sanitize-r5900 */
6605 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
6607 /* end-sanitize-r5900 */
6614 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6615 && strcmp (insn
->name
, insn
[1].name
) == 0)
6620 if (insn_isa
<= mips_opts
.isa
)
6621 insn_error
= "opcode not supported on this processor";
6624 static char buf
[100];
6626 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6633 ip
->insn_opcode
= insn
->match
;
6634 for (args
= insn
->args
;; ++args
)
6640 case '\0': /* end of args */
6653 ip
->insn_opcode
|= lastregno
<< 21;
6658 ip
->insn_opcode
|= lastregno
<< 16;
6662 ip
->insn_opcode
|= lastregno
<< 11;
6668 /* handle optional base register.
6669 Either the base register is omitted or
6670 we must have a left paren. */
6671 /* this is dependent on the next operand specifier
6672 is a 'b' for base register */
6673 assert (args
[1] == 'b');
6677 case ')': /* these must match exactly */
6682 case '<': /* must be at least one digit */
6684 * According to the manual, if the shift amount is greater
6685 * than 31 or less than 0 the the shift amount should be
6686 * mod 32. In reality the mips assembler issues an error.
6687 * We issue a warning and mask out all but the low 5 bits.
6689 my_getExpression (&imm_expr
, s
);
6690 check_absolute_expr (ip
, &imm_expr
);
6691 if ((unsigned long) imm_expr
.X_add_number
> 31)
6693 as_warn ("Improper shift amount (%ld)",
6694 (long) imm_expr
.X_add_number
);
6695 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6697 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6698 imm_expr
.X_op
= O_absent
;
6702 case '>': /* shift amount minus 32 */
6703 my_getExpression (&imm_expr
, s
);
6704 check_absolute_expr (ip
, &imm_expr
);
6705 if ((unsigned long) imm_expr
.X_add_number
< 32
6706 || (unsigned long) imm_expr
.X_add_number
> 63)
6708 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6709 imm_expr
.X_op
= O_absent
;
6713 case 'k': /* cache code */
6714 case 'h': /* prefx code */
6715 my_getExpression (&imm_expr
, s
);
6716 check_absolute_expr (ip
, &imm_expr
);
6717 if ((unsigned long) imm_expr
.X_add_number
> 31)
6719 as_warn ("Invalid value for `%s' (%lu)",
6721 (unsigned long) imm_expr
.X_add_number
);
6722 imm_expr
.X_add_number
&= 0x1f;
6725 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6727 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6728 imm_expr
.X_op
= O_absent
;
6732 case 'c': /* break code */
6733 my_getExpression (&imm_expr
, s
);
6734 check_absolute_expr (ip
, &imm_expr
);
6735 if ((unsigned) imm_expr
.X_add_number
> 1023)
6736 as_warn ("Illegal break code (%ld)",
6737 (long) imm_expr
.X_add_number
);
6738 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6739 imm_expr
.X_op
= O_absent
;
6743 case 'B': /* syscall code */
6744 my_getExpression (&imm_expr
, s
);
6745 check_absolute_expr (ip
, &imm_expr
);
6746 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6747 as_warn ("Illegal syscall code (%ld)",
6748 (long) imm_expr
.X_add_number
);
6749 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6750 imm_expr
.X_op
= O_absent
;
6754 case 'C': /* Coprocessor code */
6755 my_getExpression (&imm_expr
, s
);
6756 check_absolute_expr (ip
, &imm_expr
);
6757 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6759 as_warn ("Coproccesor code > 25 bits (%ld)",
6760 (long) imm_expr
.X_add_number
);
6761 imm_expr
.X_add_number
&= ((1<<25) - 1);
6763 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6764 imm_expr
.X_op
= O_absent
;
6768 case 'b': /* base register */
6769 case 'd': /* destination register */
6770 case 's': /* source register */
6771 case 't': /* target register */
6772 case 'r': /* both target and source */
6773 case 'v': /* both dest and source */
6774 case 'w': /* both dest and target */
6775 case 'E': /* coprocessor target register */
6776 case 'G': /* coprocessor destination register */
6777 case 'x': /* ignore register name */
6778 case 'z': /* must be zero register */
6792 while (isdigit (*s
));
6794 as_bad ("Invalid register number (%d)", regno
);
6796 else if (*args
== 'E' || *args
== 'G')
6800 if (s
[1] == 'f' && s
[2] == 'p')
6805 else if (s
[1] == 's' && s
[2] == 'p')
6810 else if (s
[1] == 'g' && s
[2] == 'p')
6815 else if (s
[1] == 'a' && s
[2] == 't')
6820 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6825 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6830 else if (itbl_have_entries
)
6835 p
= s
+1; /* advance past '$' */
6836 n
= itbl_get_field (&p
); /* n is name */
6838 /* See if this is a register defined in an
6840 r
= itbl_get_reg_val (n
);
6843 /* Get_field advances to the start of
6844 the next field, so we need to back
6845 rack to the end of the last field. */
6849 s
= strchr (s
,'\0');
6862 as_warn ("Used $at without \".set noat\"");
6868 if (c
== 'r' || c
== 'v' || c
== 'w')
6875 /* 'z' only matches $0. */
6876 if (c
== 'z' && regno
!= 0)
6879 /* Now that we have assembled one operand, we use the args string
6880 * to figure out where it goes in the instruction. */
6887 ip
->insn_opcode
|= regno
<< 21;
6891 ip
->insn_opcode
|= regno
<< 11;
6896 ip
->insn_opcode
|= regno
<< 16;
6899 /* This case exists because on the r3000 trunc
6900 expands into a macro which requires a gp
6901 register. On the r6000 or r4000 it is
6902 assembled into a single instruction which
6903 ignores the register. Thus the insn version
6904 is MIPS_ISA2 and uses 'x', and the macro
6905 version is MIPS_ISA1 and uses 't'. */
6908 /* This case is for the div instruction, which
6909 acts differently if the destination argument
6910 is $0. This only matches $0, and is checked
6911 outside the switch. */
6914 /* Itbl operand; not yet implemented. FIXME ?? */
6916 /* What about all other operands like 'i', which
6917 can be specified in the opcode table? */
6927 ip
->insn_opcode
|= lastregno
<< 21;
6930 ip
->insn_opcode
|= lastregno
<< 16;
6935 case 'D': /* floating point destination register */
6936 case 'S': /* floating point source register */
6937 case 'T': /* floating point target register */
6938 case 'R': /* floating point source register */
6942 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6952 while (isdigit (*s
));
6955 as_bad ("Invalid float register number (%d)", regno
);
6957 if ((regno
& 1) != 0
6958 && mips_opts
.isa
< 3
6959 && ! (strcmp (str
, "mtc1") == 0
6960 || strcmp (str
, "mfc1") == 0
6961 || strcmp (str
, "lwc1") == 0
6962 || strcmp (str
, "swc1") == 0
6963 || strcmp (str
, "l.s") == 0
6964 || strcmp (str
, "s.s") == 0))
6965 as_warn ("Float register should be even, was %d",
6973 if (c
== 'V' || c
== 'W')
6983 ip
->insn_opcode
|= regno
<< 6;
6987 ip
->insn_opcode
|= regno
<< 11;
6991 ip
->insn_opcode
|= regno
<< 16;
6994 ip
->insn_opcode
|= regno
<< 21;
7003 ip
->insn_opcode
|= lastregno
<< 11;
7006 ip
->insn_opcode
|= lastregno
<< 16;
7012 my_getExpression (&imm_expr
, s
);
7013 if (imm_expr
.X_op
!= O_big
7014 && imm_expr
.X_op
!= O_constant
)
7015 insn_error
= "absolute expression required";
7020 my_getExpression (&offset_expr
, s
);
7021 imm_reloc
= BFD_RELOC_32
;
7033 unsigned char temp
[8];
7035 unsigned int length
;
7040 /* These only appear as the last operand in an
7041 instruction, and every instruction that accepts
7042 them in any variant accepts them in all variants.
7043 This means we don't have to worry about backing out
7044 any changes if the instruction does not match.
7046 The difference between them is the size of the
7047 floating point constant and where it goes. For 'F'
7048 and 'L' the constant is 64 bits; for 'f' and 'l' it
7049 is 32 bits. Where the constant is placed is based
7050 on how the MIPS assembler does things:
7053 f -- immediate value
7056 The .lit4 and .lit8 sections are only used if
7057 permitted by the -G argument.
7059 When generating embedded PIC code, we use the
7060 .lit8 section but not the .lit4 section (we can do
7061 .lit4 inline easily; we need to put .lit8
7062 somewhere in the data segment, and using .lit8
7063 permits the linker to eventually combine identical
7066 f64
= *args
== 'F' || *args
== 'L';
7068 save_in
= input_line_pointer
;
7069 input_line_pointer
= s
;
7070 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7072 s
= input_line_pointer
;
7073 input_line_pointer
= save_in
;
7074 if (err
!= NULL
&& *err
!= '\0')
7076 as_bad ("Bad floating point constant: %s", err
);
7077 memset (temp
, '\0', sizeof temp
);
7078 length
= f64
? 8 : 4;
7081 assert (length
== (f64
? 8 : 4));
7085 && (! USE_GLOBAL_POINTER_OPT
7086 || mips_pic
== EMBEDDED_PIC
7087 || g_switch_value
< 4
7088 || (temp
[0] == 0 && temp
[1] == 0)
7089 || (temp
[2] == 0 && temp
[3] == 0))))
7091 imm_expr
.X_op
= O_constant
;
7092 if (! target_big_endian
)
7093 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7095 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7098 && ((temp
[0] == 0 && temp
[1] == 0)
7099 || (temp
[2] == 0 && temp
[3] == 0))
7100 && ((temp
[4] == 0 && temp
[5] == 0)
7101 || (temp
[6] == 0 && temp
[7] == 0)))
7103 /* The value is simple enough to load with a
7104 couple of instructions. In mips1 mode, set
7105 imm_expr to the high order 32 bits and
7106 offset_expr to the low order 32 bits.
7107 Otherwise, set imm_expr to the entire 64 bit
7109 if (mips_opts
.isa
< 3)
7111 imm_expr
.X_op
= O_constant
;
7112 offset_expr
.X_op
= O_constant
;
7113 if (! target_big_endian
)
7115 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7116 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7120 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7121 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7123 if (offset_expr
.X_add_number
== 0)
7124 offset_expr
.X_op
= O_absent
;
7126 else if (sizeof (imm_expr
.X_add_number
) > 4)
7128 imm_expr
.X_op
= O_constant
;
7129 if (! target_big_endian
)
7130 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7132 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7136 imm_expr
.X_op
= O_big
;
7137 imm_expr
.X_add_number
= 4;
7138 if (! target_big_endian
)
7140 generic_bignum
[0] = bfd_getl16 (temp
);
7141 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7142 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7143 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7147 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7148 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7149 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7150 generic_bignum
[3] = bfd_getb16 (temp
);
7156 const char *newname
;
7159 /* Switch to the right section. */
7161 subseg
= now_subseg
;
7164 default: /* unused default case avoids warnings. */
7166 newname
= RDATA_SECTION_NAME
;
7167 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7171 newname
= RDATA_SECTION_NAME
;
7174 assert (!USE_GLOBAL_POINTER_OPT
7175 || g_switch_value
>= 4);
7179 new_seg
= subseg_new (newname
, (subsegT
) 0);
7180 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7181 bfd_set_section_flags (stdoutput
, new_seg
,
7186 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7187 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7188 && strcmp (TARGET_OS
, "elf") != 0)
7189 record_alignment (new_seg
, 4);
7191 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7193 as_bad ("Can't use floating point insn in this section");
7195 /* Set the argument to the current address in the
7197 offset_expr
.X_op
= O_symbol
;
7198 offset_expr
.X_add_symbol
=
7199 symbol_new ("L0\001", now_seg
,
7200 (valueT
) frag_now_fix (), frag_now
);
7201 offset_expr
.X_add_number
= 0;
7203 /* Put the floating point number into the section. */
7204 p
= frag_more ((int) length
);
7205 memcpy (p
, temp
, length
);
7207 /* Switch back to the original section. */
7208 subseg_set (seg
, subseg
);
7213 case 'i': /* 16 bit unsigned immediate */
7214 case 'j': /* 16 bit signed immediate */
7215 imm_reloc
= BFD_RELOC_LO16
;
7216 c
= my_getSmallExpression (&imm_expr
, s
);
7221 if (imm_expr
.X_op
== O_constant
)
7222 imm_expr
.X_add_number
=
7223 (imm_expr
.X_add_number
>> 16) & 0xffff;
7226 imm_reloc
= BFD_RELOC_HI16_S
;
7227 imm_unmatched_hi
= true;
7230 imm_reloc
= BFD_RELOC_HI16
;
7235 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7236 || ((imm_expr
.X_add_number
< 0
7237 || imm_expr
.X_add_number
>= 0x10000)
7238 && imm_expr
.X_op
== O_constant
))
7240 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7241 !strcmp (insn
->name
, insn
[1].name
))
7243 if (imm_expr
.X_op
!= O_constant
7244 && imm_expr
.X_op
!= O_big
)
7245 insn_error
= "absolute expression required";
7247 as_bad ("16 bit expression not in range 0..65535");
7255 /* The upper bound should be 0x8000, but
7256 unfortunately the MIPS assembler accepts numbers
7257 from 0x8000 to 0xffff and sign extends them, and
7258 we want to be compatible. We only permit this
7259 extended range for an instruction which does not
7260 provide any further alternates, since those
7261 alternates may handle other cases. People should
7262 use the numbers they mean, rather than relying on
7263 a mysterious sign extension. */
7264 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7265 strcmp (insn
->name
, insn
[1].name
) == 0);
7270 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7271 || ((imm_expr
.X_add_number
< -0x8000
7272 || imm_expr
.X_add_number
>= max
)
7273 && imm_expr
.X_op
== O_constant
)
7275 && imm_expr
.X_add_number
< 0
7276 && mips_opts
.isa
>= 3
7277 && imm_expr
.X_unsigned
7278 && sizeof (imm_expr
.X_add_number
) <= 4))
7282 if (imm_expr
.X_op
!= O_constant
7283 && imm_expr
.X_op
!= O_big
)
7284 insn_error
= "absolute expression required";
7286 as_bad ("16 bit expression not in range -32768..32767");
7292 case 'o': /* 16 bit offset */
7293 c
= my_getSmallExpression (&offset_expr
, s
);
7295 /* If this value won't fit into a 16 bit offset, then go
7296 find a macro that will generate the 32 bit offset
7297 code pattern. As a special hack, we accept the
7298 difference of two local symbols as a constant. This
7299 is required to suppose embedded PIC switches, which
7300 use an instruction which looks like
7301 lw $4,$L12-$LS12($4)
7302 The problem with handling this in a more general
7303 fashion is that the macro function doesn't expect to
7304 see anything which can be handled in a single
7305 constant instruction. */
7307 && (offset_expr
.X_op
!= O_constant
7308 || offset_expr
.X_add_number
>= 0x8000
7309 || offset_expr
.X_add_number
< -0x8000)
7310 && (mips_pic
!= EMBEDDED_PIC
7311 || offset_expr
.X_op
!= O_subtract
7312 || now_seg
!= text_section
7313 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7317 offset_reloc
= BFD_RELOC_LO16
;
7318 if (c
== 'h' || c
== 'H')
7320 assert (offset_expr
.X_op
== O_constant
);
7321 offset_expr
.X_add_number
=
7322 (offset_expr
.X_add_number
>> 16) & 0xffff;
7327 case 'p': /* pc relative offset */
7328 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7329 my_getExpression (&offset_expr
, s
);
7333 case 'u': /* upper 16 bits */
7334 c
= my_getSmallExpression (&imm_expr
, s
);
7335 if (imm_expr
.X_op
== O_constant
7336 && (imm_expr
.X_add_number
< 0
7337 || imm_expr
.X_add_number
>= 0x10000))
7338 as_bad ("lui expression not in range 0..65535");
7339 imm_reloc
= BFD_RELOC_LO16
;
7344 if (imm_expr
.X_op
== O_constant
)
7345 imm_expr
.X_add_number
=
7346 (imm_expr
.X_add_number
>> 16) & 0xffff;
7349 imm_reloc
= BFD_RELOC_HI16_S
;
7350 imm_unmatched_hi
= true;
7353 imm_reloc
= BFD_RELOC_HI16
;
7359 case 'a': /* 26 bit address */
7360 my_getExpression (&offset_expr
, s
);
7362 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7365 case 'N': /* 3 bit branch condition code */
7366 case 'M': /* 3 bit compare condition code */
7367 if (strncmp (s
, "$fcc", 4) != 0)
7377 while (isdigit (*s
));
7379 as_bad ("invalid condition code register $fcc%d", regno
);
7381 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7383 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7387 fprintf (stderr
, "bad char = '%c'\n", *args
);
7392 /* Args don't match. */
7393 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7394 !strcmp (insn
->name
, insn
[1].name
))
7400 insn_error
= "illegal operands";
7405 /* This routine assembles an instruction into its binary format when
7406 assembling for the mips16. As a side effect, it sets one of the
7407 global variables imm_reloc or offset_reloc to the type of
7408 relocation to do if one of the operands is an address expression.
7409 It also sets mips16_small and mips16_ext if the user explicitly
7410 requested a small or extended instruction. */
7415 struct mips_cl_insn
*ip
;
7419 struct mips_opcode
*insn
;
7422 unsigned int lastregno
= 0;
7427 mips16_small
= false;
7430 for (s
= str
; islower (*s
); ++s
)
7442 if (s
[1] == 't' && s
[2] == ' ')
7445 mips16_small
= true;
7449 else if (s
[1] == 'e' && s
[2] == ' ')
7458 insn_error
= "unknown opcode";
7462 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7463 mips16_small
= true;
7465 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7467 insn_error
= "unrecognized opcode";
7474 assert (strcmp (insn
->name
, str
) == 0);
7477 ip
->insn_opcode
= insn
->match
;
7478 ip
->use_extend
= false;
7479 imm_expr
.X_op
= O_absent
;
7480 imm_reloc
= BFD_RELOC_UNUSED
;
7481 offset_expr
.X_op
= O_absent
;
7482 offset_reloc
= BFD_RELOC_UNUSED
;
7483 for (args
= insn
->args
; 1; ++args
)
7490 /* In this switch statement we call break if we did not find
7491 a match, continue if we did find a match, or return if we
7500 /* Stuff the immediate value in now, if we can. */
7501 if (imm_expr
.X_op
== O_constant
7502 && imm_reloc
> BFD_RELOC_UNUSED
7503 && insn
->pinfo
!= INSN_MACRO
)
7505 mips16_immed ((char *) NULL
, 0,
7506 imm_reloc
- BFD_RELOC_UNUSED
,
7507 imm_expr
.X_add_number
, true, mips16_small
,
7508 mips16_ext
, &ip
->insn_opcode
,
7509 &ip
->use_extend
, &ip
->extend
);
7510 imm_expr
.X_op
= O_absent
;
7511 imm_reloc
= BFD_RELOC_UNUSED
;
7525 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7528 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7544 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7546 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7573 while (isdigit (*s
));
7576 as_bad ("invalid register number (%d)", regno
);
7582 if (s
[1] == 'f' && s
[2] == 'p')
7587 else if (s
[1] == 's' && s
[2] == 'p')
7592 else if (s
[1] == 'g' && s
[2] == 'p')
7597 else if (s
[1] == 'a' && s
[2] == 't')
7602 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7607 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7620 if (c
== 'v' || c
== 'w')
7622 regno
= mips16_to_32_reg_map
[lastregno
];
7636 regno
= mips32_to_16_reg_map
[regno
];
7641 regno
= ILLEGAL_REG
;
7646 regno
= ILLEGAL_REG
;
7651 regno
= ILLEGAL_REG
;
7656 if (regno
== AT
&& ! mips_opts
.noat
)
7657 as_warn ("used $at without \".set noat\"");
7664 if (regno
== ILLEGAL_REG
)
7671 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7675 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7678 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7681 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7687 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7690 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7691 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7701 if (strncmp (s
, "$pc", 3) == 0)
7725 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7727 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7728 and generate the appropriate reloc. If the text
7729 inside %gprel is not a symbol name with an
7730 optional offset, then we generate a normal reloc
7731 and will probably fail later. */
7732 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7733 if (imm_expr
.X_op
== O_symbol
)
7736 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7738 ip
->use_extend
= true;
7745 /* Just pick up a normal expression. */
7746 my_getExpression (&imm_expr
, s
);
7749 if (imm_expr
.X_op
== O_register
)
7751 /* What we thought was an expression turned out to
7754 if (s
[0] == '(' && args
[1] == '(')
7756 /* It looks like the expression was omitted
7757 before a register indirection, which means
7758 that the expression is implicitly zero. We
7759 still set up imm_expr, so that we handle
7760 explicit extensions correctly. */
7761 imm_expr
.X_op
= O_constant
;
7762 imm_expr
.X_add_number
= 0;
7763 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7770 /* We need to relax this instruction. */
7771 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7780 /* We use offset_reloc rather than imm_reloc for the PC
7781 relative operands. This lets macros with both
7782 immediate and address operands work correctly. */
7783 my_getExpression (&offset_expr
, s
);
7785 if (offset_expr
.X_op
== O_register
)
7788 /* We need to relax this instruction. */
7789 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7793 case '6': /* break code */
7794 my_getExpression (&imm_expr
, s
);
7795 check_absolute_expr (ip
, &imm_expr
);
7796 if ((unsigned long) imm_expr
.X_add_number
> 63)
7798 as_warn ("Invalid value for `%s' (%lu)",
7800 (unsigned long) imm_expr
.X_add_number
);
7801 imm_expr
.X_add_number
&= 0x3f;
7803 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7804 imm_expr
.X_op
= O_absent
;
7808 case 'a': /* 26 bit address */
7809 my_getExpression (&offset_expr
, s
);
7811 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7812 ip
->insn_opcode
<<= 16;
7815 case 'l': /* register list for entry macro */
7816 case 'L': /* register list for exit macro */
7826 int freg
, reg1
, reg2
;
7828 while (*s
== ' ' || *s
== ',')
7832 as_bad ("can't parse register list");
7844 while (isdigit (*s
))
7866 as_bad ("invalid register list");
7871 while (isdigit (*s
))
7878 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7883 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7888 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7889 mask
|= (reg2
- 3) << 3;
7890 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7891 mask
|= (reg2
- 15) << 1;
7892 else if (reg1
== 31 && reg2
== 31)
7896 as_bad ("invalid register list");
7900 /* The mask is filled in in the opcode table for the
7901 benefit of the disassembler. We remove it before
7902 applying the actual mask. */
7903 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7904 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7908 case 'e': /* extend code */
7909 my_getExpression (&imm_expr
, s
);
7910 check_absolute_expr (ip
, &imm_expr
);
7911 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7913 as_warn ("Invalid value for `%s' (%lu)",
7915 (unsigned long) imm_expr
.X_add_number
);
7916 imm_expr
.X_add_number
&= 0x7ff;
7918 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7919 imm_expr
.X_op
= O_absent
;
7929 /* Args don't match. */
7930 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7931 strcmp (insn
->name
, insn
[1].name
) == 0)
7938 insn_error
= "illegal operands";
7944 /* This structure holds information we know about a mips16 immediate
7947 struct mips16_immed_operand
7949 /* The type code used in the argument string in the opcode table. */
7951 /* The number of bits in the short form of the opcode. */
7953 /* The number of bits in the extended form of the opcode. */
7955 /* The amount by which the short form is shifted when it is used;
7956 for example, the sw instruction has a shift count of 2. */
7958 /* The amount by which the short form is shifted when it is stored
7959 into the instruction code. */
7961 /* Non-zero if the short form is unsigned. */
7963 /* Non-zero if the extended form is unsigned. */
7965 /* Non-zero if the value is PC relative. */
7969 /* The mips16 immediate operand types. */
7971 static const struct mips16_immed_operand mips16_immed_operands
[] =
7973 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7974 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7975 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7976 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7977 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7978 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7979 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7980 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7981 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7982 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7983 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7984 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7985 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7986 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7987 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7988 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7989 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7990 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7991 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7992 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7993 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7996 #define MIPS16_NUM_IMMED \
7997 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7999 /* Handle a mips16 instruction with an immediate value. This or's the
8000 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8001 whether an extended value is needed; if one is needed, it sets
8002 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8003 If SMALL is true, an unextended opcode was explicitly requested.
8004 If EXT is true, an extended opcode was explicitly requested. If
8005 WARN is true, warn if EXT does not match reality. */
8008 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8017 unsigned long *insn
;
8018 boolean
*use_extend
;
8019 unsigned short *extend
;
8021 register const struct mips16_immed_operand
*op
;
8022 int mintiny
, maxtiny
;
8025 op
= mips16_immed_operands
;
8026 while (op
->type
!= type
)
8029 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8034 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8037 maxtiny
= 1 << op
->nbits
;
8042 maxtiny
= (1 << op
->nbits
) - 1;
8047 mintiny
= - (1 << (op
->nbits
- 1));
8048 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8051 /* Branch offsets have an implicit 0 in the lowest bit. */
8052 if (type
== 'p' || type
== 'q')
8055 if ((val
& ((1 << op
->shift
) - 1)) != 0
8056 || val
< (mintiny
<< op
->shift
)
8057 || val
> (maxtiny
<< op
->shift
))
8062 if (warn
&& ext
&& ! needext
)
8063 as_warn_where (file
, line
, "extended operand requested but not required");
8064 if (small
&& needext
)
8065 as_bad_where (file
, line
, "invalid unextended operand value");
8067 if (small
|| (! ext
&& ! needext
))
8071 *use_extend
= false;
8072 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8073 insnval
<<= op
->op_shift
;
8078 long minext
, maxext
;
8084 maxext
= (1 << op
->extbits
) - 1;
8088 minext
= - (1 << (op
->extbits
- 1));
8089 maxext
= (1 << (op
->extbits
- 1)) - 1;
8091 if (val
< minext
|| val
> maxext
)
8092 as_bad_where (file
, line
,
8093 "operand value out of range for instruction");
8096 if (op
->extbits
== 16)
8098 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8101 else if (op
->extbits
== 15)
8103 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8108 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8112 *extend
= (unsigned short) extval
;
8121 my_getSmallExpression (ep
, str
)
8132 ((str
[1] == 'h' && str
[2] == 'i')
8133 || (str
[1] == 'H' && str
[2] == 'I')
8134 || (str
[1] == 'l' && str
[2] == 'o'))
8146 * A small expression may be followed by a base register.
8147 * Scan to the end of this operand, and then back over a possible
8148 * base register. Then scan the small expression up to that
8149 * point. (Based on code in sparc.c...)
8151 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8153 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8155 if (isdigit (sp
[-2]))
8157 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8159 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8165 else if (sp
- 5 >= str
8168 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8169 || (sp
[-3] == 's' && sp
[-2] == 'p')
8170 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8171 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8177 /* no expression means zero offset */
8180 /* %xx(reg) is an error */
8181 ep
->X_op
= O_absent
;
8186 ep
->X_op
= O_constant
;
8189 ep
->X_add_symbol
= NULL
;
8190 ep
->X_op_symbol
= NULL
;
8191 ep
->X_add_number
= 0;
8196 my_getExpression (ep
, str
);
8203 my_getExpression (ep
, str
);
8204 return c
; /* => %hi or %lo encountered */
8208 my_getExpression (ep
, str
)
8214 save_in
= input_line_pointer
;
8215 input_line_pointer
= str
;
8217 expr_end
= input_line_pointer
;
8218 input_line_pointer
= save_in
;
8220 /* If we are in mips16 mode, and this is an expression based on `.',
8221 then we bump the value of the symbol by 1 since that is how other
8222 text symbols are handled. We don't bother to handle complex
8223 expressions, just `.' plus or minus a constant. */
8224 if (mips_opts
.mips16
8225 && ep
->X_op
== O_symbol
8226 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8227 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8228 && ep
->X_add_symbol
->sy_frag
== frag_now
8229 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8230 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8231 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8234 /* Turn a string in input_line_pointer into a floating point constant
8235 of type type, and store the appropriate bytes in *litP. The number
8236 of LITTLENUMS emitted is stored in *sizeP . An error message is
8237 returned, or NULL on OK. */
8240 md_atof (type
, litP
, sizeP
)
8246 LITTLENUM_TYPE words
[4];
8262 return "bad call to md_atof";
8265 t
= atof_ieee (input_line_pointer
, type
, words
);
8267 input_line_pointer
= t
;
8271 if (! target_big_endian
)
8273 for (i
= prec
- 1; i
>= 0; i
--)
8275 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8281 for (i
= 0; i
< prec
; i
++)
8283 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8292 md_number_to_chars (buf
, val
, n
)
8297 if (target_big_endian
)
8298 number_to_chars_bigendian (buf
, val
, n
);
8300 number_to_chars_littleendian (buf
, val
, n
);
8303 CONST
char *md_shortopts
= "O::g::G:";
8305 struct option md_longopts
[] = {
8306 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8307 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8308 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8309 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8310 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8311 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8312 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8313 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8314 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8315 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8316 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8317 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8318 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8319 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8320 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8321 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8322 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8323 {"break", no_argument
, NULL
, OPTION_BREAK
},
8324 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8325 #define OPTION_EB (OPTION_MD_BASE + 11)
8326 {"EB", no_argument
, NULL
, OPTION_EB
},
8327 #define OPTION_EL (OPTION_MD_BASE + 12)
8328 {"EL", no_argument
, NULL
, OPTION_EL
},
8329 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8330 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8331 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8332 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8333 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8334 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8335 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8336 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8337 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8338 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8339 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8340 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8341 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8342 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8343 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8344 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8345 /* start-sanitize-r5900 */
8346 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8347 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8348 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8349 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8350 /* end-sanitize-r5900 */
8351 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8352 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8353 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8354 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8357 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8358 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8359 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8360 #define OPTION_32 (OPTION_MD_BASE + 20)
8361 #define OPTION_64 (OPTION_MD_BASE + 21)
8363 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8364 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8365 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8366 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8367 {"32", no_argument
, NULL
, OPTION_32
},
8368 {"64", no_argument
, NULL
, OPTION_64
},
8371 {NULL
, no_argument
, NULL
, 0}
8373 size_t md_longopts_size
= sizeof(md_longopts
);
8376 md_parse_option (c
, arg
)
8391 target_big_endian
= 1;
8395 target_big_endian
= 0;
8399 if (arg
&& arg
[1] == '0')
8409 mips_debug
= atoi (arg
);
8410 /* When the MIPS assembler sees -g or -g2, it does not do
8411 optimizations which limit full symbolic debugging. We take
8412 that to be equivalent to -O0. */
8413 if (mips_debug
== 2)
8445 /* Identify the processor type */
8447 if (strcmp (p
, "default") == 0
8448 || strcmp (p
, "DEFAULT") == 0)
8454 /* We need to cope with the various "vr" prefixes for the 4300
8456 if (*p
== 'v' || *p
== 'V')
8462 if (*p
== 'r' || *p
== 'R')
8469 if (strcmp (p
, "10000") == 0
8470 || strcmp (p
, "10k") == 0
8471 || strcmp (p
, "10K") == 0)
8476 if (strcmp (p
, "2000") == 0
8477 || strcmp (p
, "2k") == 0
8478 || strcmp (p
, "2K") == 0)
8483 if (strcmp (p
, "3000") == 0
8484 || strcmp (p
, "3k") == 0
8485 || strcmp (p
, "3K") == 0)
8487 else if (strcmp (p
, "3900") == 0)
8492 if (strcmp (p
, "4000") == 0
8493 || strcmp (p
, "4k") == 0
8494 || strcmp (p
, "4K") == 0)
8496 else if (strcmp (p
, "4100") == 0)
8502 else if (strcmp (p
, "4300") == 0)
8504 else if (strcmp (p
, "4400") == 0)
8506 else if (strcmp (p
, "4600") == 0)
8508 else if (strcmp (p
, "4650") == 0)
8514 else if (strcmp (p
, "4010") == 0)
8523 if (strcmp (p
, "5000") == 0
8524 || strcmp (p
, "5k") == 0
8525 || strcmp (p
, "5K") == 0)
8527 /* start-sanitize-r5900 */
8528 else if (strcmp (p
, "5900") == 0)
8530 /* end-sanitize-r5900 */
8534 if (strcmp (p
, "6000") == 0
8535 || strcmp (p
, "6k") == 0
8536 || strcmp (p
, "6K") == 0)
8541 if (strcmp (p
, "8000") == 0
8542 || strcmp (p
, "8k") == 0
8543 || strcmp (p
, "8K") == 0)
8548 if (strcmp (p
, "orion") == 0)
8553 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8555 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8561 as_bad ("invalid architecture -mcpu=%s", arg
);
8572 case OPTION_NO_M4650
:
8580 case OPTION_NO_M4010
:
8588 case OPTION_NO_M4100
:
8592 /* start-sanitize-r5900 */
8597 case OPTION_NO_M5900
:
8600 /* end-sanitize-r5900 */
8606 case OPTION_NO_M3900
:
8611 mips_opts
.mips16
= 1;
8612 mips_no_prev_insn (false);
8615 case OPTION_NO_MIPS16
:
8616 mips_opts
.mips16
= 0;
8617 mips_no_prev_insn (false);
8620 case OPTION_MEMBEDDED_PIC
:
8621 mips_pic
= EMBEDDED_PIC
;
8622 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8624 as_bad ("-G may not be used with embedded PIC code");
8627 g_switch_value
= 0x7fffffff;
8630 /* When generating ELF code, we permit -KPIC and -call_shared to
8631 select SVR4_PIC, and -non_shared to select no PIC. This is
8632 intended to be compatible with Irix 5. */
8633 case OPTION_CALL_SHARED
:
8634 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8636 as_bad ("-call_shared is supported only for ELF format");
8639 mips_pic
= SVR4_PIC
;
8640 if (g_switch_seen
&& g_switch_value
!= 0)
8642 as_bad ("-G may not be used with SVR4 PIC code");
8648 case OPTION_NON_SHARED
:
8649 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8651 as_bad ("-non_shared is supported only for ELF format");
8657 /* The -xgot option tells the assembler to use 32 offsets when
8658 accessing the got in SVR4_PIC mode. It is for Irix
8665 if (! USE_GLOBAL_POINTER_OPT
)
8667 as_bad ("-G is not supported for this configuration");
8670 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8672 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8676 g_switch_value
= atoi (arg
);
8680 /* The -32 and -64 options tell the assembler to output the 32
8681 bit or the 64 bit MIPS ELF format. */
8688 const char **list
, **l
;
8690 list
= bfd_target_list ();
8691 for (l
= list
; *l
!= NULL
; l
++)
8692 if (strcmp (*l
, "elf64-bigmips") == 0
8693 || strcmp (*l
, "elf64-littlemips") == 0)
8696 as_fatal ("No compiled in support for 64 bit object file format");
8710 md_show_usage (stream
)
8715 -membedded-pic generate embedded position independent code\n\
8716 -EB generate big endian output\n\
8717 -EL generate little endian output\n\
8718 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8719 -G NUM allow referencing objects up to NUM bytes\n\
8720 implicitly with the gp register [default 8]\n");
8722 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8723 -mips2, -mcpu=r6000 generate code for r6000\n\
8724 -mips3, -mcpu=r4000 generate code for r4000\n\
8725 -mips4, -mcpu=r8000 generate code for r8000\n\
8726 -mcpu=vr4300 generate code for vr4300\n\
8727 -mcpu=vr4100 generate code for vr4100\n\
8728 -m4650 permit R4650 instructions\n\
8729 -no-m4650 do not permit R4650 instructions\n\
8730 -m4010 permit R4010 instructions\n\
8731 -no-m4010 do not permit R4010 instructions\n\
8732 -m4100 permit VR4100 instructions\n\
8733 -no-m4100 do not permit VR4100 instructions\n");
8735 -mips16 generate mips16 instructions\n\
8736 -no-mips16 do not generate mips16 instructions\n");
8738 -O0 remove unneeded NOPs, do not swap branches\n\
8739 -O remove unneeded NOPs and swap branches\n\
8740 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8741 --break, --no-trap break exception on div by 0 and mult overflow\n");
8744 -KPIC, -call_shared generate SVR4 position independent code\n\
8745 -non_shared do not generate position independent code\n\
8746 -xgot assume a 32 bit GOT\n\
8747 -32 create 32 bit object file (default)\n\
8748 -64 create 64 bit object file\n");
8753 mips_init_after_args ()
8755 /* initialize opcodes */
8756 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8757 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8761 md_pcrel_from (fixP
)
8764 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8765 && fixP
->fx_addsy
!= (symbolS
*) NULL
8766 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8768 /* This makes a branch to an undefined symbol be a branch to the
8769 current location. */
8773 /* return the address of the delay slot */
8774 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8777 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8778 reloc for a cons. We could use the definition there, except that
8779 we want to handle 64 bit relocs specially. */
8782 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8785 unsigned int nbytes
;
8789 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8791 if (nbytes
== 8 && ! mips_64
)
8793 if (target_big_endian
)
8799 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8800 as_bad ("Unsupported reloc size %d", nbytes
);
8802 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8805 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8808 /* This is called before the symbol table is processed. In order to
8809 work with gcc when using mips-tfile, we must keep all local labels.
8810 However, in other cases, we want to discard them. If we were
8811 called with -g, but we didn't see any debugging information, it may
8812 mean that gcc is smuggling debugging information through to
8813 mips-tfile, in which case we must generate all local labels. */
8816 mips_frob_file_before_adjust ()
8818 #ifndef NO_ECOFF_DEBUGGING
8821 && ! ecoff_debugging_seen
)
8822 flag_keep_locals
= 1;
8826 /* Sort any unmatched HI16_S relocs so that they immediately precede
8827 the corresponding LO reloc. This is called before md_apply_fix and
8828 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8829 explicit use of the %hi modifier. */
8834 struct mips_hi_fixup
*l
;
8836 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8838 segment_info_type
*seginfo
;
8841 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8843 /* Check quickly whether the next fixup happens to be a matching
8845 if (l
->fixp
->fx_next
!= NULL
8846 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8847 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8848 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8851 /* Look through the fixups for this segment for a matching %lo.
8852 When we find one, move the %hi just in front of it. We do
8853 this in two passes. In the first pass, we try to find a
8854 unique %lo. In the second pass, we permit multiple %hi
8855 relocs for a single %lo (this is a GNU extension). */
8856 seginfo
= seg_info (l
->seg
);
8857 for (pass
= 0; pass
< 2; pass
++)
8862 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8864 /* Check whether this is a %lo fixup which matches l->fixp. */
8865 if (f
->fx_r_type
== BFD_RELOC_LO16
8866 && f
->fx_addsy
== l
->fixp
->fx_addsy
8867 && f
->fx_offset
== l
->fixp
->fx_offset
8870 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8871 || prev
->fx_addsy
!= f
->fx_addsy
8872 || prev
->fx_offset
!= f
->fx_offset
))
8876 /* Move l->fixp before f. */
8877 for (pf
= &seginfo
->fix_root
;
8879 pf
= &(*pf
)->fx_next
)
8880 assert (*pf
!= NULL
);
8882 *pf
= l
->fixp
->fx_next
;
8884 l
->fixp
->fx_next
= f
;
8886 seginfo
->fix_root
= l
->fixp
;
8888 prev
->fx_next
= l
->fixp
;
8900 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8901 "Unmatched %%hi reloc");
8906 /* When generating embedded PIC code we need to use a special
8907 relocation to represent the difference of two symbols in the .text
8908 section (switch tables use a difference of this sort). See
8909 include/coff/mips.h for details. This macro checks whether this
8910 fixup requires the special reloc. */
8911 #define SWITCH_TABLE(fixp) \
8912 ((fixp)->fx_r_type == BFD_RELOC_32 \
8913 && (fixp)->fx_addsy != NULL \
8914 && (fixp)->fx_subsy != NULL \
8915 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8916 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8918 /* When generating embedded PIC code we must keep all PC relative
8919 relocations, in case the linker has to relax a call. We also need
8920 to keep relocations for switch table entries. */
8924 mips_force_relocation (fixp
)
8927 return (mips_pic
== EMBEDDED_PIC
8929 || SWITCH_TABLE (fixp
)
8930 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8931 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8934 /* Apply a fixup to the object file. */
8937 md_apply_fix (fixP
, valueP
)
8944 assert (fixP
->fx_size
== 4
8945 || fixP
->fx_r_type
== BFD_RELOC_16
8946 || fixP
->fx_r_type
== BFD_RELOC_64
);
8950 /* If we aren't adjusting this fixup to be against the section
8951 symbol, we need to adjust the value. */
8953 if (fixP
->fx_addsy
!= NULL
8954 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8955 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8957 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8958 if (value
!= 0 && ! fixP
->fx_pcrel
)
8960 /* In this case, the bfd_install_relocation routine will
8961 incorrectly add the symbol value back in. We just want
8962 the addend to appear in the object file. */
8963 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8968 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8970 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8973 switch (fixP
->fx_r_type
)
8975 case BFD_RELOC_MIPS_JMP
:
8976 case BFD_RELOC_HI16
:
8977 case BFD_RELOC_HI16_S
:
8978 case BFD_RELOC_MIPS_GPREL
:
8979 case BFD_RELOC_MIPS_LITERAL
:
8980 case BFD_RELOC_MIPS_CALL16
:
8981 case BFD_RELOC_MIPS_GOT16
:
8982 case BFD_RELOC_MIPS_GPREL32
:
8983 case BFD_RELOC_MIPS_GOT_HI16
:
8984 case BFD_RELOC_MIPS_GOT_LO16
:
8985 case BFD_RELOC_MIPS_CALL_HI16
:
8986 case BFD_RELOC_MIPS_CALL_LO16
:
8987 case BFD_RELOC_MIPS16_GPREL
:
8989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8990 "Invalid PC relative reloc");
8991 /* Nothing needed to do. The value comes from the reloc entry */
8994 case BFD_RELOC_MIPS16_JMP
:
8995 /* We currently always generate a reloc against a symbol, which
8996 means that we don't want an addend even if the symbol is
8998 fixP
->fx_addnumber
= 0;
9001 case BFD_RELOC_PCREL_HI16_S
:
9002 /* The addend for this is tricky if it is internal, so we just
9003 do everything here rather than in bfd_install_relocation. */
9004 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9006 /* For an external symbol adjust by the address to make it
9007 pcrel_offset. We use the address of the RELLO reloc
9008 which follows this one. */
9009 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9010 + fixP
->fx_next
->fx_where
);
9015 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9016 if (target_big_endian
)
9018 md_number_to_chars (buf
, value
, 2);
9021 case BFD_RELOC_PCREL_LO16
:
9022 /* The addend for this is tricky if it is internal, so we just
9023 do everything here rather than in bfd_install_relocation. */
9024 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9025 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9026 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9027 if (target_big_endian
)
9029 md_number_to_chars (buf
, value
, 2);
9033 /* This is handled like BFD_RELOC_32, but we output a sign
9034 extended value if we are only 32 bits. */
9036 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9038 if (8 <= sizeof (valueT
))
9039 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9046 w1
= w2
= fixP
->fx_where
;
9047 if (target_big_endian
)
9051 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9052 if ((value
& 0x80000000) != 0)
9056 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9062 /* If we are deleting this reloc entry, we must fill in the
9063 value now. This can happen if we have a .word which is not
9064 resolved when it appears but is later defined. We also need
9065 to fill in the value if this is an embedded PIC switch table
9068 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9069 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9074 /* If we are deleting this reloc entry, we must fill in the
9076 assert (fixP
->fx_size
== 2);
9078 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9082 case BFD_RELOC_LO16
:
9083 /* When handling an embedded PIC switch statement, we can wind
9084 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9087 if (value
< -0x8000 || value
> 0x7fff)
9088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9089 "relocation overflow");
9090 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9091 if (target_big_endian
)
9093 md_number_to_chars (buf
, value
, 2);
9097 case BFD_RELOC_16_PCREL_S2
:
9099 * We need to save the bits in the instruction since fixup_segment()
9100 * might be deleting the relocation entry (i.e., a branch within
9101 * the current segment).
9103 if ((value
& 0x3) != 0)
9104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9105 "Branch to odd address (%lx)", value
);
9108 /* update old instruction data */
9109 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9110 if (target_big_endian
)
9111 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9113 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9115 if (value
>= -0x8000 && value
< 0x8000)
9116 insn
|= value
& 0xffff;
9119 /* The branch offset is too large. If this is an
9120 unconditional branch, and we are not generating PIC code,
9121 we can convert it to an absolute jump instruction. */
9122 if (mips_pic
== NO_PIC
9124 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9125 && (fixP
->fx_frag
->fr_address
9126 < text_section
->vma
+ text_section
->_raw_size
)
9127 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9128 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9129 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9131 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9132 insn
= 0x0c000000; /* jal */
9134 insn
= 0x08000000; /* j */
9135 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9137 fixP
->fx_addsy
= section_symbol (text_section
);
9138 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9142 /* FIXME. It would be possible in principle to handle
9143 conditional branches which overflow. They could be
9144 transformed into a branch around a jump. This would
9145 require setting up variant frags for each different
9146 branch type. The native MIPS assembler attempts to
9147 handle these cases, but it appears to do it
9149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9150 "Branch out of range");
9154 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9169 const struct mips_opcode
*p
;
9170 int treg
, sreg
, dreg
, shamt
;
9175 for (i
= 0; i
< NUMOPCODES
; ++i
)
9177 p
= &mips_opcodes
[i
];
9178 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9180 printf ("%08lx %s\t", oc
, p
->name
);
9181 treg
= (oc
>> 16) & 0x1f;
9182 sreg
= (oc
>> 21) & 0x1f;
9183 dreg
= (oc
>> 11) & 0x1f;
9184 shamt
= (oc
>> 6) & 0x1f;
9186 for (args
= p
->args
;; ++args
)
9197 printf ("%c", *args
);
9201 assert (treg
== sreg
);
9202 printf ("$%d,$%d", treg
, sreg
);
9207 printf ("$%d", dreg
);
9212 printf ("$%d", treg
);
9216 printf ("0x%x", treg
);
9221 printf ("$%d", sreg
);
9225 printf ("0x%08lx", oc
& 0x1ffffff);
9237 printf ("$%d", shamt
);
9248 printf ("%08lx UNDEFINED\n", oc
);
9259 name
= input_line_pointer
;
9260 c
= get_symbol_end ();
9261 p
= (symbolS
*) symbol_find_or_make (name
);
9262 *input_line_pointer
= c
;
9266 /* Align the current frag to a given power of two. The MIPS assembler
9267 also automatically adjusts any preceding label. */
9270 mips_align (to
, fill
, label
)
9275 mips_emit_delays (false);
9276 frag_align (to
, fill
, 0);
9277 record_alignment (now_seg
, to
);
9280 assert (S_GET_SEGMENT (label
) == now_seg
);
9281 label
->sy_frag
= frag_now
;
9282 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9286 /* Align to a given power of two. .align 0 turns off the automatic
9287 alignment used by the data creating pseudo-ops. */
9294 register long temp_fill
;
9295 long max_alignment
= 15;
9299 o Note that the assembler pulls down any immediately preceeding label
9300 to the aligned address.
9301 o It's not documented but auto alignment is reinstated by
9302 a .align pseudo instruction.
9303 o Note also that after auto alignment is turned off the mips assembler
9304 issues an error on attempt to assemble an improperly aligned data item.
9309 temp
= get_absolute_expression ();
9310 if (temp
> max_alignment
)
9311 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9314 as_warn ("Alignment negative: 0 assumed.");
9317 if (*input_line_pointer
== ',')
9319 input_line_pointer
++;
9320 temp_fill
= get_absolute_expression ();
9327 mips_align (temp
, (int) temp_fill
,
9328 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9335 demand_empty_rest_of_line ();
9339 mips_flush_pending_output ()
9341 mips_emit_delays (false);
9342 mips_clear_insn_labels ();
9351 /* When generating embedded PIC code, we only use the .text, .lit8,
9352 .sdata and .sbss sections. We change the .data and .rdata
9353 pseudo-ops to use .sdata. */
9354 if (mips_pic
== EMBEDDED_PIC
9355 && (sec
== 'd' || sec
== 'r'))
9359 /* The ELF backend needs to know that we are changing sections, so
9360 that .previous works correctly. We could do something like check
9361 for a obj_section_change_hook macro, but that might be confusing
9362 as it would not be appropriate to use it in the section changing
9363 functions in read.c, since obj-elf.c intercepts those. FIXME:
9364 This should be cleaner, somehow. */
9365 obj_elf_section_change_hook ();
9368 mips_emit_delays (false);
9378 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9379 demand_empty_rest_of_line ();
9383 if (USE_GLOBAL_POINTER_OPT
)
9385 seg
= subseg_new (RDATA_SECTION_NAME
,
9386 (subsegT
) get_absolute_expression ());
9387 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9389 bfd_set_section_flags (stdoutput
, seg
,
9395 if (strcmp (TARGET_OS
, "elf") != 0)
9396 bfd_set_section_alignment (stdoutput
, seg
, 4);
9398 demand_empty_rest_of_line ();
9402 as_bad ("No read only data section in this object file format");
9403 demand_empty_rest_of_line ();
9409 if (USE_GLOBAL_POINTER_OPT
)
9411 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9412 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9414 bfd_set_section_flags (stdoutput
, seg
,
9415 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9417 if (strcmp (TARGET_OS
, "elf") != 0)
9418 bfd_set_section_alignment (stdoutput
, seg
, 4);
9420 demand_empty_rest_of_line ();
9425 as_bad ("Global pointers not supported; recompile -G 0");
9426 demand_empty_rest_of_line ();
9435 mips_enable_auto_align ()
9446 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9447 mips_emit_delays (false);
9448 if (log_size
> 0 && auto_align
)
9449 mips_align (log_size
, 0, label
);
9450 mips_clear_insn_labels ();
9451 cons (1 << log_size
);
9460 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9462 mips_emit_delays (false);
9466 mips_align (3, 0, label
);
9468 mips_align (2, 0, label
);
9470 mips_clear_insn_labels ();
9475 /* Handle .globl. We need to override it because on Irix 5 you are
9478 where foo is an undefined symbol, to mean that foo should be
9479 considered to be the address of a function. */
9490 name
= input_line_pointer
;
9491 c
= get_symbol_end ();
9492 symbolP
= symbol_find_or_make (name
);
9493 *input_line_pointer
= c
;
9496 /* On Irix 5, every global symbol that is not explicitly labelled as
9497 being a function is apparently labelled as being an object. */
9500 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9505 secname
= input_line_pointer
;
9506 c
= get_symbol_end ();
9507 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9509 as_bad ("%s: no such section", secname
);
9510 *input_line_pointer
= c
;
9512 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9513 flag
= BSF_FUNCTION
;
9516 symbolP
->bsym
->flags
|= flag
;
9518 S_SET_EXTERNAL (symbolP
);
9519 demand_empty_rest_of_line ();
9529 opt
= input_line_pointer
;
9530 c
= get_symbol_end ();
9534 /* FIXME: What does this mean? */
9536 else if (strncmp (opt
, "pic", 3) == 0)
9544 mips_pic
= SVR4_PIC
;
9546 as_bad (".option pic%d not supported", i
);
9548 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9550 if (g_switch_seen
&& g_switch_value
!= 0)
9551 as_warn ("-G may not be used with SVR4 PIC code");
9553 bfd_set_gp_size (stdoutput
, 0);
9557 as_warn ("Unrecognized option \"%s\"", opt
);
9559 *input_line_pointer
= c
;
9560 demand_empty_rest_of_line ();
9563 /* This structure is used to hold a stack of .set values. */
9565 struct mips_option_stack
9567 struct mips_option_stack
*next
;
9568 struct mips_set_options options
;
9571 static struct mips_option_stack
*mips_opts_stack
;
9573 /* Handle the .set pseudo-op. */
9579 char *name
= input_line_pointer
, ch
;
9581 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9582 input_line_pointer
++;
9583 ch
= *input_line_pointer
;
9584 *input_line_pointer
= '\0';
9586 if (strcmp (name
, "reorder") == 0)
9588 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
9590 /* If we still have pending nops, we can discard them. The
9591 usual nop handling will insert any that are still
9593 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9594 * (mips_opts
.mips16
? 2 : 4));
9595 prev_nop_frag
= NULL
;
9597 mips_opts
.noreorder
= 0;
9599 else if (strcmp (name
, "noreorder") == 0)
9601 mips_emit_delays (true);
9602 mips_opts
.noreorder
= 1;
9603 mips_any_noreorder
= 1;
9605 else if (strcmp (name
, "at") == 0)
9609 else if (strcmp (name
, "noat") == 0)
9613 else if (strcmp (name
, "macro") == 0)
9615 mips_opts
.warn_about_macros
= 0;
9617 else if (strcmp (name
, "nomacro") == 0)
9619 if (mips_opts
.noreorder
== 0)
9620 as_bad ("`noreorder' must be set before `nomacro'");
9621 mips_opts
.warn_about_macros
= 1;
9623 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9625 mips_opts
.nomove
= 0;
9627 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9629 mips_opts
.nomove
= 1;
9631 else if (strcmp (name
, "bopt") == 0)
9633 mips_opts
.nobopt
= 0;
9635 else if (strcmp (name
, "nobopt") == 0)
9637 mips_opts
.nobopt
= 1;
9639 else if (strcmp (name
, "mips16") == 0
9640 || strcmp (name
, "MIPS-16") == 0)
9641 mips_opts
.mips16
= 1;
9642 else if (strcmp (name
, "nomips16") == 0
9643 || strcmp (name
, "noMIPS-16") == 0)
9644 mips_opts
.mips16
= 0;
9645 else if (strncmp (name
, "mips", 4) == 0)
9649 /* Permit the user to change the ISA on the fly. Needless to
9650 say, misuse can cause serious problems. */
9651 isa
= atoi (name
+ 4);
9653 mips_opts
.isa
= file_mips_isa
;
9654 else if (isa
< 1 || isa
> 4)
9655 as_bad ("unknown ISA level");
9657 mips_opts
.isa
= isa
;
9659 else if (strcmp (name
, "autoextend") == 0)
9660 mips_opts
.noautoextend
= 0;
9661 else if (strcmp (name
, "noautoextend") == 0)
9662 mips_opts
.noautoextend
= 1;
9663 else if (strcmp (name
, "push") == 0)
9665 struct mips_option_stack
*s
;
9667 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
9668 s
->next
= mips_opts_stack
;
9669 s
->options
= mips_opts
;
9670 mips_opts_stack
= s
;
9672 else if (strcmp (name
, "pop") == 0)
9674 struct mips_option_stack
*s
;
9676 s
= mips_opts_stack
;
9678 as_bad (".set pop with no .set push");
9681 /* If we're changing the reorder mode we need to handle
9682 delay slots correctly. */
9683 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
9684 mips_emit_delays (true);
9685 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
9687 if (prev_nop_frag
!= NULL
)
9689 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9690 * (mips_opts
.mips16
? 2 : 4));
9691 prev_nop_frag
= NULL
;
9695 mips_opts
= s
->options
;
9696 mips_opts_stack
= s
->next
;
9702 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9704 *input_line_pointer
= ch
;
9705 demand_empty_rest_of_line ();
9708 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9709 .option pic2. It means to generate SVR4 PIC calls. */
9715 mips_pic
= SVR4_PIC
;
9716 if (USE_GLOBAL_POINTER_OPT
)
9718 if (g_switch_seen
&& g_switch_value
!= 0)
9719 as_warn ("-G may not be used with SVR4 PIC code");
9722 bfd_set_gp_size (stdoutput
, 0);
9723 demand_empty_rest_of_line ();
9726 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9727 PIC code. It sets the $gp register for the function based on the
9728 function address, which is in the register named in the argument.
9729 This uses a relocation against _gp_disp, which is handled specially
9730 by the linker. The result is:
9731 lui $gp,%hi(_gp_disp)
9732 addiu $gp,$gp,%lo(_gp_disp)
9733 addu $gp,$gp,.cpload argument
9734 The .cpload argument is normally $25 == $t9. */
9743 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9744 if (mips_pic
!= SVR4_PIC
)
9750 /* .cpload should be a in .set noreorder section. */
9751 if (mips_opts
.noreorder
== 0)
9752 as_warn (".cpload not in noreorder section");
9755 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9756 ex
.X_op_symbol
= NULL
;
9757 ex
.X_add_number
= 0;
9759 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9760 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9762 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9763 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9764 (int) BFD_RELOC_LO16
);
9766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9767 GP
, GP
, tc_get_register (0));
9769 demand_empty_rest_of_line ();
9772 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9773 offset from $sp. The offset is remembered, and after making a PIC
9774 call $gp is restored from that location. */
9777 s_cprestore (ignore
)
9783 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9784 if (mips_pic
!= SVR4_PIC
)
9790 mips_cprestore_offset
= get_absolute_expression ();
9792 ex
.X_op
= O_constant
;
9793 ex
.X_add_symbol
= NULL
;
9794 ex
.X_op_symbol
= NULL
;
9795 ex
.X_add_number
= mips_cprestore_offset
;
9797 macro_build ((char *) NULL
, &icnt
, &ex
,
9798 mips_opts
.isa
< 3 ? "sw" : "sd",
9799 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9801 demand_empty_rest_of_line ();
9804 /* Handle the .gpword pseudo-op. This is used when generating PIC
9805 code. It generates a 32 bit GP relative reloc. */
9815 /* When not generating PIC code, this is treated as .word. */
9816 if (mips_pic
!= SVR4_PIC
)
9822 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9823 mips_emit_delays (true);
9825 mips_align (2, 0, label
);
9826 mips_clear_insn_labels ();
9830 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9832 as_bad ("Unsupported use of .gpword");
9833 ignore_rest_of_line ();
9837 md_number_to_chars (p
, (valueT
) 0, 4);
9838 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9839 BFD_RELOC_MIPS_GPREL32
);
9841 demand_empty_rest_of_line ();
9844 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9845 tables in SVR4 PIC code. */
9854 /* This is ignored when not generating SVR4 PIC code. */
9855 if (mips_pic
!= SVR4_PIC
)
9861 /* Add $gp to the register named as an argument. */
9862 reg
= tc_get_register (0);
9863 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9864 mips_opts
.isa
< 3 ? "addu" : "daddu",
9865 "d,v,t", reg
, reg
, GP
);
9867 demand_empty_rest_of_line ();
9870 /* Handle the .insn pseudo-op. This marks instruction labels in
9871 mips16 mode. This permits the linker to handle them specially,
9872 such as generating jalx instructions when needed. We also make
9873 them odd for the duration of the assembly, in order to generate the
9874 right sort of code. We will make them even in the adjust_symtab
9875 routine, while leaving them marked. This is convenient for the
9876 debugger and the disassembler. The linker knows to make them odd
9883 if (mips_opts
.mips16
)
9884 mips16_mark_labels ();
9886 demand_empty_rest_of_line ();
9889 /* Handle a .stabn directive. We need these in order to mark a label
9890 as being a mips16 text label correctly. Sometimes the compiler
9891 will emit a label, followed by a .stabn, and then switch sections.
9892 If the label and .stabn are in mips16 mode, then the label is
9893 really a mips16 text label. */
9899 if (type
== 'n' && mips_opts
.mips16
)
9900 mips16_mark_labels ();
9905 /* Parse a register string into a number. Called from the ECOFF code
9906 to parse .frame. The argument is non-zero if this is the frame
9907 register, so that we can record it in mips_frame_reg. */
9910 tc_get_register (frame
)
9916 if (*input_line_pointer
++ != '$')
9918 as_warn ("expected `$'");
9921 else if (isdigit ((unsigned char) *input_line_pointer
))
9923 reg
= get_absolute_expression ();
9924 if (reg
< 0 || reg
>= 32)
9926 as_warn ("Bad register number");
9932 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9934 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9936 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9938 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9942 as_warn ("Unrecognized register name");
9945 input_line_pointer
+= 2;
9948 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9953 md_section_align (seg
, addr
)
9957 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9960 /* We don't need to align ELF sections to the full alignment.
9961 However, Irix 5 may prefer that we align them at least to a 16
9962 byte boundary. We don't bother to align the sections if we are
9963 targeted for an embedded system. */
9964 if (strcmp (TARGET_OS
, "elf") == 0)
9970 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9973 /* Utility routine, called from above as well. If called while the
9974 input file is still being read, it's only an approximation. (For
9975 example, a symbol may later become defined which appeared to be
9976 undefined earlier.) */
9979 nopic_need_relax (sym
, before_relaxing
)
9981 int before_relaxing
;
9986 if (USE_GLOBAL_POINTER_OPT
)
9988 const char *symname
;
9991 /* Find out whether this symbol can be referenced off the GP
9992 register. It can be if it is smaller than the -G size or if
9993 it is in the .sdata or .sbss section. Certain symbols can
9994 not be referenced off the GP, although it appears as though
9996 symname
= S_GET_NAME (sym
);
9997 if (symname
!= (const char *) NULL
9998 && (strcmp (symname
, "eprol") == 0
9999 || strcmp (symname
, "etext") == 0
10000 || strcmp (symname
, "_gp") == 0
10001 || strcmp (symname
, "edata") == 0
10002 || strcmp (symname
, "_fbss") == 0
10003 || strcmp (symname
, "_fdata") == 0
10004 || strcmp (symname
, "_ftext") == 0
10005 || strcmp (symname
, "end") == 0
10006 || strcmp (symname
, "_gp_disp") == 0))
10008 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10010 #ifndef NO_ECOFF_DEBUGGING
10011 || (sym
->ecoff_extern_size
!= 0
10012 && sym
->ecoff_extern_size
<= g_switch_value
)
10014 /* We must defer this decision until after the whole
10015 file has been read, since there might be a .extern
10016 after the first use of this symbol. */
10017 || (before_relaxing
10018 #ifndef NO_ECOFF_DEBUGGING
10019 && sym
->ecoff_extern_size
== 0
10021 && S_GET_VALUE (sym
) == 0)
10022 || (S_GET_VALUE (sym
) != 0
10023 && S_GET_VALUE (sym
) <= g_switch_value
)))
10027 const char *segname
;
10029 segname
= segment_name (S_GET_SEGMENT (sym
));
10030 assert (strcmp (segname
, ".lit8") != 0
10031 && strcmp (segname
, ".lit4") != 0);
10032 change
= (strcmp (segname
, ".sdata") != 0
10033 && strcmp (segname
, ".sbss") != 0);
10038 /* We are not optimizing for the GP register. */
10042 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10043 extended opcode. SEC is the section the frag is in. */
10046 mips16_extended_frag (fragp
, sec
, stretch
)
10052 register const struct mips16_immed_operand
*op
;
10054 int mintiny
, maxtiny
;
10057 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10059 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10062 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10063 op
= mips16_immed_operands
;
10064 while (op
->type
!= type
)
10067 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10072 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10075 maxtiny
= 1 << op
->nbits
;
10080 maxtiny
= (1 << op
->nbits
) - 1;
10085 mintiny
= - (1 << (op
->nbits
- 1));
10086 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10089 /* We can't call S_GET_VALUE here, because we don't want to lock in
10090 a particular frag address. */
10091 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10093 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10094 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10095 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10097 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10098 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10101 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10102 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10103 + fragp
->fr_symbol
->sy_value
.X_add_number
10104 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10105 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10114 /* We won't have the section when we are called from
10115 mips_relax_frag. However, we will always have been called
10116 from md_estimate_size_before_relax first. If this is a
10117 branch to a different section, we mark it as such. If SEC is
10118 NULL, and the frag is not marked, then it must be a branch to
10119 the same section. */
10122 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10129 fragp
->fr_subtype
=
10130 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10132 /* FIXME: We should support this, and let the linker
10133 catch branches and loads that are out of range. */
10134 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10135 "unsupported PC relative reference to different section");
10141 /* In this case, we know for sure that the symbol fragment is in
10142 the same section. If the fr_address of the symbol fragment
10143 is greater then the address of this fragment we want to add
10144 in STRETCH in order to get a better estimate of the address.
10145 This particularly matters because of the shift bits. */
10147 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10151 /* Adjust stretch for any alignment frag. Note that if have
10152 been expanding the earlier code, the symbol may be
10153 defined in what appears to be an earlier frag. FIXME:
10154 This doesn't handle the fr_subtype field, which specifies
10155 a maximum number of bytes to skip when doing an
10158 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10161 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10164 stretch
= - ((- stretch
)
10165 & ~ ((1 << (int) f
->fr_offset
) - 1));
10167 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10176 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10178 /* The base address rules are complicated. The base address of
10179 a branch is the following instruction. The base address of a
10180 PC relative load or add is the instruction itself, but if it
10181 is in a delay slot (in which case it can not be extended) use
10182 the address of the instruction whose delay slot it is in. */
10183 if (type
== 'p' || type
== 'q')
10187 /* If we are currently assuming that this frag should be
10188 extended, then, the current address is two bytes
10190 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10193 /* Ignore the low bit in the target, since it will be set
10194 for a text label. */
10195 if ((val
& 1) != 0)
10198 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10200 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10203 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10205 /* Branch offsets have an implicit 0 in the lowest bit. */
10206 if (type
== 'p' || type
== 'q')
10209 /* If any of the shifted bits are set, we must use an extended
10210 opcode. If the address depends on the size of this
10211 instruction, this can lead to a loop, so we arrange to always
10212 use an extended opcode. We only check this when we are in
10213 the main relaxation loop, when SEC is NULL. */
10214 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10216 fragp
->fr_subtype
=
10217 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10221 /* If we are about to mark a frag as extended because the value
10222 is precisely maxtiny + 1, then there is a chance of an
10223 infinite loop as in the following code:
10228 In this case when the la is extended, foo is 0x3fc bytes
10229 away, so the la can be shrunk, but then foo is 0x400 away, so
10230 the la must be extended. To avoid this loop, we mark the
10231 frag as extended if it was small, and is about to become
10232 extended with a value of maxtiny + 1. */
10233 if (val
== ((maxtiny
+ 1) << op
->shift
)
10234 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10237 fragp
->fr_subtype
=
10238 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10242 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10243 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
10245 if ((val
& ((1 << op
->shift
) - 1)) != 0
10246 || val
< (mintiny
<< op
->shift
)
10247 || val
> (maxtiny
<< op
->shift
))
10253 /* Estimate the size of a frag before relaxing. Unless this is the
10254 mips16, we are not really relaxing here, and the final size is
10255 encoded in the subtype information. For the mips16, we have to
10256 decide whether we are using an extended opcode or not. */
10260 md_estimate_size_before_relax (fragp
, segtype
)
10266 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10268 if (mips16_extended_frag (fragp
, segtype
, 0))
10270 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10275 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10280 if (mips_pic
== NO_PIC
)
10282 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10284 else if (mips_pic
== SVR4_PIC
)
10289 sym
= fragp
->fr_symbol
;
10291 /* Handle the case of a symbol equated to another symbol. */
10292 while (sym
->sy_value
.X_op
== O_symbol
10293 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10297 /* It's possible to get a loop here in a badly written
10299 n
= sym
->sy_value
.X_add_symbol
;
10305 symsec
= S_GET_SEGMENT (sym
);
10307 /* This must duplicate the test in adjust_reloc_syms. */
10308 change
= (symsec
!= &bfd_und_section
10309 && symsec
!= &bfd_abs_section
10310 && ! bfd_is_com_section (symsec
));
10317 /* Record the offset to the first reloc in the fr_opcode field.
10318 This lets md_convert_frag and tc_gen_reloc know that the code
10319 must be expanded. */
10320 fragp
->fr_opcode
= (fragp
->fr_literal
10322 - RELAX_OLD (fragp
->fr_subtype
)
10323 + RELAX_RELOC1 (fragp
->fr_subtype
));
10324 /* FIXME: This really needs as_warn_where. */
10325 if (RELAX_WARN (fragp
->fr_subtype
))
10326 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
10332 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10335 /* This is called to see whether a reloc against a defined symbol
10336 should be converted into a reloc against a section. Don't adjust
10337 MIPS16 jump relocations, so we don't have to worry about the format
10338 of the offset in the .o file. Don't adjust relocations against
10339 mips16 symbols, so that the linker can find them if it needs to set
10343 mips_fix_adjustable (fixp
)
10346 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10348 if (fixp
->fx_addsy
== NULL
)
10351 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10352 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10353 && fixp
->fx_subsy
== NULL
)
10359 /* Translate internal representation of relocation info to BFD target
10363 tc_gen_reloc (section
, fixp
)
10367 static arelent
*retval
[4];
10369 bfd_reloc_code_real_type code
;
10371 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10374 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10375 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10377 if (mips_pic
== EMBEDDED_PIC
10378 && SWITCH_TABLE (fixp
))
10380 /* For a switch table entry we use a special reloc. The addend
10381 is actually the difference between the reloc address and the
10383 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10384 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10385 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10386 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10388 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10390 /* We use a special addend for an internal RELLO reloc. */
10391 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10392 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10394 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10396 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10398 assert (fixp
->fx_next
!= NULL
10399 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10400 /* We use a special addend for an internal RELHI reloc. The
10401 reloc is relative to the RELLO; adjust the addend
10403 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10404 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10405 + fixp
->fx_next
->fx_where
10406 - S_GET_VALUE (fixp
->fx_subsy
));
10408 reloc
->addend
= (fixp
->fx_addnumber
10409 + fixp
->fx_next
->fx_frag
->fr_address
10410 + fixp
->fx_next
->fx_where
);
10412 else if (fixp
->fx_pcrel
== 0)
10413 reloc
->addend
= fixp
->fx_addnumber
;
10416 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10417 /* A gruesome hack which is a result of the gruesome gas reloc
10419 reloc
->addend
= reloc
->address
;
10421 reloc
->addend
= -reloc
->address
;
10424 /* If this is a variant frag, we may need to adjust the existing
10425 reloc and generate a new one. */
10426 if (fixp
->fx_frag
->fr_opcode
!= NULL
10427 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10428 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10429 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10430 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10431 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10432 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10433 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10437 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10439 /* If this is not the last reloc in this frag, then we have two
10440 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10441 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10442 the second one handle all of them. */
10443 if (fixp
->fx_next
!= NULL
10444 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10446 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10447 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10448 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10449 && (fixp
->fx_next
->fx_r_type
10450 == BFD_RELOC_MIPS_GOT_LO16
))
10451 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10452 && (fixp
->fx_next
->fx_r_type
10453 == BFD_RELOC_MIPS_CALL_LO16
)));
10458 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10459 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10460 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10462 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10463 reloc2
->address
= (reloc
->address
10464 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10465 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10466 reloc2
->addend
= fixp
->fx_addnumber
;
10467 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10468 assert (reloc2
->howto
!= NULL
);
10470 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10474 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10477 reloc3
->address
+= 4;
10480 if (mips_pic
== NO_PIC
)
10482 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10483 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10485 else if (mips_pic
== SVR4_PIC
)
10487 switch (fixp
->fx_r_type
)
10491 case BFD_RELOC_MIPS_GOT16
:
10493 case BFD_RELOC_MIPS_CALL16
:
10494 case BFD_RELOC_MIPS_GOT_LO16
:
10495 case BFD_RELOC_MIPS_CALL_LO16
:
10496 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10504 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10505 fixup_segment converted a non-PC relative reloc into a PC
10506 relative reloc. In such a case, we need to convert the reloc
10508 code
= fixp
->fx_r_type
;
10509 if (fixp
->fx_pcrel
)
10514 code
= BFD_RELOC_8_PCREL
;
10517 code
= BFD_RELOC_16_PCREL
;
10520 code
= BFD_RELOC_32_PCREL
;
10523 code
= BFD_RELOC_64_PCREL
;
10525 case BFD_RELOC_8_PCREL
:
10526 case BFD_RELOC_16_PCREL
:
10527 case BFD_RELOC_32_PCREL
:
10528 case BFD_RELOC_64_PCREL
:
10529 case BFD_RELOC_16_PCREL_S2
:
10530 case BFD_RELOC_PCREL_HI16_S
:
10531 case BFD_RELOC_PCREL_LO16
:
10534 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10535 "Cannot make %s relocation PC relative",
10536 bfd_get_reloc_code_name (code
));
10540 /* To support a PC relative reloc when generating embedded PIC code
10541 for ECOFF, we use a Cygnus extension. We check for that here to
10542 make sure that we don't let such a reloc escape normally. */
10543 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10544 && code
== BFD_RELOC_16_PCREL_S2
10545 && mips_pic
!= EMBEDDED_PIC
)
10546 reloc
->howto
= NULL
;
10548 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10550 if (reloc
->howto
== NULL
)
10552 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10553 "Can not represent %s relocation in this object file format",
10554 bfd_get_reloc_code_name (code
));
10561 /* Relax a machine dependent frag. This returns the amount by which
10562 the current size of the frag should change. */
10565 mips_relax_frag (fragp
, stretch
)
10569 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10572 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10574 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10576 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10581 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10583 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10590 /* Convert a machine dependent frag. */
10593 md_convert_frag (abfd
, asec
, fragp
)
10601 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10604 register const struct mips16_immed_operand
*op
;
10605 boolean small
, ext
;
10608 unsigned long insn
;
10609 boolean use_extend
;
10610 unsigned short extend
;
10612 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10613 op
= mips16_immed_operands
;
10614 while (op
->type
!= type
)
10617 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10628 resolve_symbol_value (fragp
->fr_symbol
);
10629 val
= S_GET_VALUE (fragp
->fr_symbol
);
10634 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10636 /* The rules for the base address of a PC relative reloc are
10637 complicated; see mips16_extended_frag. */
10638 if (type
== 'p' || type
== 'q')
10643 /* Ignore the low bit in the target, since it will be
10644 set for a text label. */
10645 if ((val
& 1) != 0)
10648 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10650 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10653 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10656 /* Make sure the section winds up with the alignment we have
10659 record_alignment (asec
, op
->shift
);
10663 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10664 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10665 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10666 "extended instruction in delay slot");
10668 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10670 if (target_big_endian
)
10671 insn
= bfd_getb16 (buf
);
10673 insn
= bfd_getl16 (buf
);
10675 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10676 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10677 small
, ext
, &insn
, &use_extend
, &extend
);
10681 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10682 fragp
->fr_fix
+= 2;
10686 md_number_to_chars (buf
, insn
, 2);
10687 fragp
->fr_fix
+= 2;
10692 if (fragp
->fr_opcode
== NULL
)
10695 old
= RELAX_OLD (fragp
->fr_subtype
);
10696 new = RELAX_NEW (fragp
->fr_subtype
);
10697 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10700 memcpy (fixptr
- old
, fixptr
, new);
10702 fragp
->fr_fix
+= new - old
;
10708 /* This function is called after the relocs have been generated.
10709 We've been storing mips16 text labels as odd. Here we convert them
10710 back to even for the convenience of the debugger. */
10713 mips_frob_file_after_relocs ()
10716 unsigned int count
, i
;
10718 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10721 syms
= bfd_get_outsymbols (stdoutput
);
10722 count
= bfd_get_symcount (stdoutput
);
10723 for (i
= 0; i
< count
; i
++, syms
++)
10725 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10726 && ((*syms
)->value
& 1) != 0)
10728 (*syms
)->value
&= ~1;
10729 /* If the symbol has an odd size, it was probably computed
10730 incorrectly, so adjust that as well. */
10731 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10732 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10739 /* This function is called whenever a label is defined. It is used
10740 when handling branch delays; if a branch has a label, we assume we
10741 can not move it. */
10744 mips_define_label (sym
)
10747 struct insn_label_list
*l
;
10749 if (free_insn_labels
== NULL
)
10750 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10753 l
= free_insn_labels
;
10754 free_insn_labels
= l
->next
;
10758 l
->next
= insn_labels
;
10762 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10764 /* Some special processing for a MIPS ELF file. */
10767 mips_elf_final_processing ()
10769 /* Write out the register information. */
10774 s
.ri_gprmask
= mips_gprmask
;
10775 s
.ri_cprmask
[0] = mips_cprmask
[0];
10776 s
.ri_cprmask
[1] = mips_cprmask
[1];
10777 s
.ri_cprmask
[2] = mips_cprmask
[2];
10778 s
.ri_cprmask
[3] = mips_cprmask
[3];
10779 /* The gp_value field is set by the MIPS ELF backend. */
10781 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10782 ((Elf32_External_RegInfo
*)
10783 mips_regmask_frag
));
10787 Elf64_Internal_RegInfo s
;
10789 s
.ri_gprmask
= mips_gprmask
;
10791 s
.ri_cprmask
[0] = mips_cprmask
[0];
10792 s
.ri_cprmask
[1] = mips_cprmask
[1];
10793 s
.ri_cprmask
[2] = mips_cprmask
[2];
10794 s
.ri_cprmask
[3] = mips_cprmask
[3];
10795 /* The gp_value field is set by the MIPS ELF backend. */
10797 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10798 ((Elf64_External_RegInfo
*)
10799 mips_regmask_frag
));
10802 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10803 sort of BFD interface for this. */
10804 if (mips_any_noreorder
)
10805 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10806 if (mips_pic
!= NO_PIC
)
10807 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10810 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10812 /* These functions should really be defined by the object file format,
10813 since they are related to debugging information. However, this
10814 code has to work for the a.out format, which does not define them,
10815 so we provide simple versions here. These don't actually generate
10816 any debugging information, but they do simple checking and someday
10817 somebody may make them useful. */
10821 struct loc
*loc_next
;
10822 unsigned long loc_fileno
;
10823 unsigned long loc_lineno
;
10824 unsigned long loc_offset
;
10825 unsigned short loc_delta
;
10826 unsigned short loc_count
;
10833 typedef struct proc
10835 struct proc
*proc_next
;
10836 struct symbol
*proc_isym
;
10837 struct symbol
*proc_end
;
10838 unsigned long proc_reg_mask
;
10839 unsigned long proc_reg_offset
;
10840 unsigned long proc_fpreg_mask
;
10841 unsigned long proc_fpreg_offset
;
10842 unsigned long proc_frameoffset
;
10843 unsigned long proc_framereg
;
10844 unsigned long proc_pcreg
;
10846 struct file
*proc_file
;
10851 typedef struct file
10853 struct file
*file_next
;
10854 unsigned long file_fileno
;
10855 struct symbol
*file_symbol
;
10856 struct symbol
*file_end
;
10857 struct proc
*file_proc
;
10862 static struct obstack proc_frags
;
10863 static procS
*proc_lastP
;
10864 static procS
*proc_rootP
;
10865 static int numprocs
;
10870 obstack_begin (&proc_frags
, 0x2000);
10876 /* check for premature end, nesting errors, etc */
10877 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10878 as_warn ("missing `.end' at end of assembly");
10887 if (*input_line_pointer
== '-')
10889 ++input_line_pointer
;
10892 if (!isdigit (*input_line_pointer
))
10893 as_bad ("Expected simple number.");
10894 if (input_line_pointer
[0] == '0')
10896 if (input_line_pointer
[1] == 'x')
10898 input_line_pointer
+= 2;
10899 while (isxdigit (*input_line_pointer
))
10902 val
|= hex_value (*input_line_pointer
++);
10904 return negative
? -val
: val
;
10908 ++input_line_pointer
;
10909 while (isdigit (*input_line_pointer
))
10912 val
|= *input_line_pointer
++ - '0';
10914 return negative
? -val
: val
;
10917 if (!isdigit (*input_line_pointer
))
10919 printf (" *input_line_pointer == '%c' 0x%02x\n",
10920 *input_line_pointer
, *input_line_pointer
);
10921 as_warn ("Invalid number");
10924 while (isdigit (*input_line_pointer
))
10927 val
+= *input_line_pointer
++ - '0';
10929 return negative
? -val
: val
;
10932 /* The .file directive; just like the usual .file directive, but there
10933 is an initial number which is the ECOFF file index. */
10941 line
= get_number ();
10946 /* The .end directive. */
10954 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10957 demand_empty_rest_of_line ();
10961 if (now_seg
!= text_section
)
10962 as_warn (".end not in text section");
10965 as_warn (".end and no .ent seen yet.");
10971 assert (S_GET_NAME (p
));
10972 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10973 as_warn (".end symbol does not match .ent symbol.");
10976 proc_lastP
->proc_end
= (symbolS
*) 1;
10979 /* The .aent and .ent directives. */
10989 symbolP
= get_symbol ();
10990 if (*input_line_pointer
== ',')
10991 input_line_pointer
++;
10992 SKIP_WHITESPACE ();
10993 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10994 number
= get_number ();
10995 if (now_seg
!= text_section
)
10996 as_warn (".ent or .aent not in text section.");
10998 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10999 as_warn ("missing `.end'");
11003 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11004 procP
->proc_isym
= symbolP
;
11005 procP
->proc_reg_mask
= 0;
11006 procP
->proc_reg_offset
= 0;
11007 procP
->proc_fpreg_mask
= 0;
11008 procP
->proc_fpreg_offset
= 0;
11009 procP
->proc_frameoffset
= 0;
11010 procP
->proc_framereg
= 0;
11011 procP
->proc_pcreg
= 0;
11012 procP
->proc_end
= NULL
;
11013 procP
->proc_next
= NULL
;
11015 proc_lastP
->proc_next
= procP
;
11017 proc_rootP
= procP
;
11018 proc_lastP
= procP
;
11021 demand_empty_rest_of_line ();
11024 /* The .frame directive. */
11037 frame_reg
= tc_get_register (1);
11038 if (*input_line_pointer
== ',')
11039 input_line_pointer
++;
11040 frame_off
= get_absolute_expression ();
11041 if (*input_line_pointer
== ',')
11042 input_line_pointer
++;
11043 pcreg
= tc_get_register (0);
11045 /* bob third eye */
11046 assert (proc_rootP
);
11047 proc_rootP
->proc_framereg
= frame_reg
;
11048 proc_rootP
->proc_frameoffset
= frame_off
;
11049 proc_rootP
->proc_pcreg
= pcreg
;
11050 /* bob macho .frame */
11052 /* We don't have to write out a frame stab for unoptimized code. */
11053 if (!(frame_reg
== FP
&& frame_off
== 0))
11056 as_warn ("No .ent for .frame to use.");
11057 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11058 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11059 S_SET_TYPE (symP
, N_RMASK
);
11060 S_SET_OTHER (symP
, 0);
11061 S_SET_DESC (symP
, 0);
11062 symP
->sy_forward
= proc_lastP
->proc_isym
;
11063 /* bob perhaps I should have used pseudo set */
11065 demand_empty_rest_of_line ();
11069 /* The .fmask and .mask directives. */
11076 char str
[100], *strP
;
11082 mask
= get_number ();
11083 if (*input_line_pointer
== ',')
11084 input_line_pointer
++;
11085 off
= get_absolute_expression ();
11087 /* bob only for coff */
11088 assert (proc_rootP
);
11089 if (reg_type
== 'F')
11091 proc_rootP
->proc_fpreg_mask
= mask
;
11092 proc_rootP
->proc_fpreg_offset
= off
;
11096 proc_rootP
->proc_reg_mask
= mask
;
11097 proc_rootP
->proc_reg_offset
= off
;
11100 /* bob macho .mask + .fmask */
11102 /* We don't have to write out a mask stab if no saved regs. */
11106 as_warn ("No .ent for .mask to use.");
11108 for (i
= 0; i
< 32; i
++)
11112 sprintf (strP
, "%c%d,", reg_type
, i
);
11113 strP
+= strlen (strP
);
11117 sprintf (strP
, ";%d,", off
);
11118 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11119 S_SET_TYPE (symP
, N_RMASK
);
11120 S_SET_OTHER (symP
, 0);
11121 S_SET_DESC (symP
, 0);
11122 symP
->sy_forward
= proc_lastP
->proc_isym
;
11123 /* bob perhaps I should have used pseudo set */
11128 /* The .loc directive. */
11139 assert (now_seg
== text_section
);
11141 lineno
= get_number ();
11142 addroff
= frag_now_fix ();
11144 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11145 S_SET_TYPE (symbolP
, N_SLINE
);
11146 S_SET_OTHER (symbolP
, 0);
11147 S_SET_DESC (symbolP
, lineno
);
11148 symbolP
->sy_segment
= now_seg
;